diff options
| author | Sekhar Nori <nsekhar@ti.com> | 2009-10-21 11:48:24 -0400 |
|---|---|---|
| committer | Kevin Hilman <khilman@deeprootsystems.com> | 2009-11-25 13:21:36 -0500 |
| commit | 17fadd9a5edfeef15ea0e06822a25cc073d9ee02 (patch) | |
| tree | 3248df919cadac7654900a4083765d447b1d0e86 | |
| parent | 797d799ed09bbbfd13f684756bccafbbd44ffcd0 (diff) | |
davinci: DA850/OMAP-L138 EVM: simplify configuration of emac in MII/RMII mode
There are multiple steps in configuring the EMAC to MII or RMII mode.
Current code implements them using multiple checks.
Consolidate the multiple checks into a single if construct.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| -rw-r--r-- | arch/arm/mach-davinci/board-da850-evm.c | 35 |
1 files changed, 15 insertions, 20 deletions
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index fd6f7800611a..d0e3178f8fe9 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c | |||
| @@ -535,23 +535,27 @@ static int __init da850_evm_config_emac(void) | |||
| 535 | 535 | ||
| 536 | cfg_chip3_base = DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG); | 536 | cfg_chip3_base = DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG); |
| 537 | 537 | ||
| 538 | /* configure the CFGCHIP3 register for RMII or MII */ | ||
| 539 | val = __raw_readl(cfg_chip3_base); | 538 | val = __raw_readl(cfg_chip3_base); |
| 540 | if (rmii_en) | 539 | |
| 540 | if (rmii_en) { | ||
| 541 | val |= BIT(8); | 541 | val |= BIT(8); |
| 542 | else | 542 | ret = da8xx_pinmux_setup(da850_rmii_pins); |
| 543 | pr_info("EMAC: RMII PHY configured, MII PHY will not be" | ||
| 544 | " functional\n"); | ||
| 545 | } else { | ||
| 543 | val &= ~BIT(8); | 546 | val &= ~BIT(8); |
| 544 | |||
| 545 | __raw_writel(val, cfg_chip3_base); | ||
| 546 | |||
| 547 | if (!rmii_en) | ||
| 548 | ret = da8xx_pinmux_setup(da850_cpgmac_pins); | 547 | ret = da8xx_pinmux_setup(da850_cpgmac_pins); |
| 549 | else | 548 | pr_info("EMAC: MII PHY configured, RMII PHY will not be" |
| 550 | ret = da8xx_pinmux_setup(da850_rmii_pins); | 549 | " functional\n"); |
| 550 | } | ||
| 551 | |||
| 551 | if (ret) | 552 | if (ret) |
| 552 | pr_warning("da850_evm_init: cpgmac/rmii mux setup failed: %d\n", | 553 | pr_warning("da850_evm_init: cpgmac/rmii mux setup failed: %d\n", |
| 553 | ret); | 554 | ret); |
| 554 | 555 | ||
| 556 | /* configure the CFGCHIP3 register for RMII or MII */ | ||
| 557 | __raw_writel(val, cfg_chip3_base); | ||
| 558 | |||
| 555 | ret = davinci_cfg_reg(DA850_GPIO2_6); | 559 | ret = davinci_cfg_reg(DA850_GPIO2_6); |
| 556 | if (ret) | 560 | if (ret) |
| 557 | pr_warning("da850_evm_init:GPIO(2,6) mux setup " | 561 | pr_warning("da850_evm_init:GPIO(2,6) mux setup " |
| @@ -564,17 +568,8 @@ static int __init da850_evm_config_emac(void) | |||
| 564 | return ret; | 568 | return ret; |
| 565 | } | 569 | } |
| 566 | 570 | ||
| 567 | if (rmii_en) { | 571 | /* Enable/Disable MII MDIO clock */ |
| 568 | /* Disable MII MDIO clock */ | 572 | gpio_direction_output(DA850_MII_MDIO_CLKEN_PIN, rmii_en); |
| 569 | gpio_direction_output(DA850_MII_MDIO_CLKEN_PIN, 1); | ||
| 570 | pr_info("EMAC: RMII PHY configured, MII PHY will not be" | ||
| 571 | " functional\n"); | ||
| 572 | } else { | ||
| 573 | /* Enable MII MDIO clock */ | ||
| 574 | gpio_direction_output(DA850_MII_MDIO_CLKEN_PIN, 0); | ||
| 575 | pr_info("EMAC: MII PHY configured, RMII PHY will not be" | ||
| 576 | " functional\n"); | ||
| 577 | } | ||
| 578 | 573 | ||
| 579 | soc_info->emac_pdata->phy_mask = DA850_EVM_PHY_MASK; | 574 | soc_info->emac_pdata->phy_mask = DA850_EVM_PHY_MASK; |
| 580 | soc_info->emac_pdata->mdio_max_freq = DA850_EVM_MDIO_FREQUENCY; | 575 | soc_info->emac_pdata->mdio_max_freq = DA850_EVM_MDIO_FREQUENCY; |
