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authorLinus Torvalds <torvalds@linux-foundation.org>2010-08-06 12:20:19 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-08-06 12:20:19 -0400
commit132a4edb2b69924742f62dc06ace42ad2a9f57f3 (patch)
tree53b73abd91273d2cad021fb9b5218f3d18d90c86
parente6da54d84f9286edbe4c92ff5023ff481ce2a5c9 (diff)
parent752e386c247664152f2cce37915d1f50631d7f42 (diff)
Merge branch 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev
* 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev: sata_fsl,mv,nv: prepare for NCQ command completion update ata: Convert pci_table entries to PCI_VDEVICE (if PCI_ANY_ID is used) libata: more PCI IDs for jmicron controllers ata_piix: fix locking around SIDPR access [libata] update blacklist for new hyphenated pattern ranges (v2) libata: allow hyphenated pattern ranges ata_generic: drop hard coded DMA force logic for CENATEK [libata] ahci: Fix warning: comparison between 'enum <anonymous>' and 'enum <anonymous>' [libata] add ATA_CMD_DSM to ata_get_cmd_descript [libata] Add Samsung PATA controller driver, pata_samsung_cf [libata] Add 460EX on-chip SATA driver, sata_dwc_460ex libata: reduce blacklist size even more (v2) libata: reduce blacklist size (v2) libata: glob_match for ata_device_blacklist (v2) ahci_platform: Remove unneeded ahci_driver.probe assignment ahci_platform: Provide for vendor specific init
Diffstat
-rw-r--r--drivers/ata/Kconfig18
-rw-r--r--drivers/ata/Makefile2
-rw-r--r--drivers/ata/ahci.c2
-rw-r--r--drivers/ata/ahci_platform.c26
-rw-r--r--drivers/ata/ata_generic.c4
-rw-r--r--drivers/ata/ata_piix.c8
-rw-r--r--drivers/ata/libata-core.c161
-rw-r--r--drivers/ata/libata-eh.c1
-rw-r--r--drivers/ata/pata_samsung_cf.c683
-rw-r--r--drivers/ata/pata_scc.c3
-rw-r--r--drivers/ata/sata_dwc_460ex.c1756
-rw-r--r--drivers/ata/sata_fsl.c20
-rw-r--r--drivers/ata/sata_mv.c47
-rw-r--r--drivers/ata/sata_nv.c32
-rw-r--r--drivers/pci/quirks.c6
-rw-r--r--include/linux/ahci_platform.h4
-rw-r--r--include/linux/pci_ids.h2
17 files changed, 2616 insertions, 159 deletions
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index aa85a98d3a4f..8fae6afd6a3d 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -187,6 +187,15 @@ config ATA_PIIX
187 187
188 If unsure, say N. 188 If unsure, say N.
189 189
190config SATA_DWC
191 tristate "DesignWare Cores SATA support"
192 depends on 460EX
193 help
194 This option enables support for the on-chip SATA controller of the
195 AppliedMicro processor 460EX.
196
197 If unsure, say N.
198
190config SATA_MV 199config SATA_MV
191 tristate "Marvell SATA support" 200 tristate "Marvell SATA support"
192 help 201 help
@@ -796,6 +805,15 @@ config PATA_RZ1000
796 805
797 If unsure, say N. 806 If unsure, say N.
798 807
808config PATA_SAMSUNG_CF
809 tristate "Samsung SoC PATA support"
810 depends on SAMSUNG_DEV_IDE
811 help
812 This option enables basic support for Samsung's S3C/S5P board
813 PATA controllers via the new ATA layer
814
815 If unsure, say N.
816
799config PATA_WINBOND_VLB 817config PATA_WINBOND_VLB
800 tristate "Winbond W83759A VLB PATA support (Experimental)" 818 tristate "Winbond W83759A VLB PATA support (Experimental)"
801 depends on ISA && EXPERIMENTAL 819 depends on ISA && EXPERIMENTAL
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 7ef89d73df63..6540632bda08 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_SATA_AHCI_PLATFORM) += ahci_platform.o libahci.o
7obj-$(CONFIG_SATA_FSL) += sata_fsl.o 7obj-$(CONFIG_SATA_FSL) += sata_fsl.o
8obj-$(CONFIG_SATA_INIC162X) += sata_inic162x.o 8obj-$(CONFIG_SATA_INIC162X) += sata_inic162x.o
9obj-$(CONFIG_SATA_SIL24) += sata_sil24.o 9obj-$(CONFIG_SATA_SIL24) += sata_sil24.o
10obj-$(CONFIG_SATA_DWC) += sata_dwc_460ex.o
10 11
11# SFF w/ custom DMA 12# SFF w/ custom DMA
12obj-$(CONFIG_PDC_ADMA) += pdc_adma.o 13obj-$(CONFIG_PDC_ADMA) += pdc_adma.o
@@ -87,6 +88,7 @@ obj-$(CONFIG_PATA_OF_PLATFORM) += pata_of_platform.o
87obj-$(CONFIG_PATA_QDI) += pata_qdi.o 88obj-$(CONFIG_PATA_QDI) += pata_qdi.o
88obj-$(CONFIG_PATA_RB532) += pata_rb532_cf.o 89obj-$(CONFIG_PATA_RB532) += pata_rb532_cf.o
89obj-$(CONFIG_PATA_RZ1000) += pata_rz1000.o 90obj-$(CONFIG_PATA_RZ1000) += pata_rz1000.o
91obj-$(CONFIG_PATA_SAMSUNG_CF) += pata_samsung_cf.o
90obj-$(CONFIG_PATA_WINBOND_VLB) += pata_winbond.o 92obj-$(CONFIG_PATA_WINBOND_VLB) += pata_winbond.o
91 93
92# Should be last but two libata driver 94# Should be last but two libata driver
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index f2522534ae63..fe75d8befc3a 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -1042,7 +1042,7 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1042 1042
1043 VPRINTK("ENTER\n"); 1043 VPRINTK("ENTER\n");
1044 1044
1045 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS); 1045 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1046 1046
1047 if (!printed_version++) 1047 if (!printed_version++)
1048 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 1048 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
index 5e11b160f247..4e97f33cca44 100644
--- a/drivers/ata/ahci_platform.c
+++ b/drivers/ata/ahci_platform.c
@@ -54,19 +54,13 @@ static int __init ahci_probe(struct platform_device *pdev)
54 return -EINVAL; 54 return -EINVAL;
55 } 55 }
56 56
57 if (pdata && pdata->init) {
58 rc = pdata->init(dev);
59 if (rc)
60 return rc;
61 }
62
63 if (pdata && pdata->ata_port_info) 57 if (pdata && pdata->ata_port_info)
64 pi = *pdata->ata_port_info; 58 pi = *pdata->ata_port_info;
65 59
66 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 60 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
67 if (!hpriv) { 61 if (!hpriv) {
68 rc = -ENOMEM; 62 dev_err(dev, "can't alloc ahci_host_priv\n");
69 goto err0; 63 return -ENOMEM;
70 } 64 }
71 65
72 hpriv->flags |= (unsigned long)pi.private_data; 66 hpriv->flags |= (unsigned long)pi.private_data;
@@ -74,8 +68,19 @@ static int __init ahci_probe(struct platform_device *pdev)
74 hpriv->mmio = devm_ioremap(dev, mem->start, resource_size(mem)); 68 hpriv->mmio = devm_ioremap(dev, mem->start, resource_size(mem));
75 if (!hpriv->mmio) { 69 if (!hpriv->mmio) {
76 dev_err(dev, "can't map %pR\n", mem); 70 dev_err(dev, "can't map %pR\n", mem);
77 rc = -ENOMEM; 71 return -ENOMEM;
78 goto err0; 72 }
73
74 /*
75 * Some platforms might need to prepare for mmio region access,
76 * which could be done in the following init call. So, the mmio
77 * region shouldn't be accessed before init (if provided) has
78 * returned successfully.
79 */
80 if (pdata && pdata->init) {
81 rc = pdata->init(dev, hpriv->mmio);
82 if (rc)
83 return rc;
79 } 84 }
80 85
81 ahci_save_initial_config(dev, hpriv, 86 ahci_save_initial_config(dev, hpriv,
@@ -166,7 +171,6 @@ static int __devexit ahci_remove(struct platform_device *pdev)
166} 171}
167 172
168static struct platform_driver ahci_driver = { 173static struct platform_driver ahci_driver = {
169 .probe = ahci_probe,
170 .remove = __devexit_p(ahci_remove), 174 .remove = __devexit_p(ahci_remove),
171 .driver = { 175 .driver = {
172 .name = "ahci", 176 .name = "ahci",
diff --git a/drivers/ata/ata_generic.c b/drivers/ata/ata_generic.c
index 7107a6929deb..cc5f7726bde7 100644
--- a/drivers/ata/ata_generic.c
+++ b/drivers/ata/ata_generic.c
@@ -54,7 +54,6 @@ static int generic_set_mode(struct ata_link *link, struct ata_device **unused)
54 const struct pci_device_id *id = ap->host->private_data; 54 const struct pci_device_id *id = ap->host->private_data;
55 int dma_enabled = 0; 55 int dma_enabled = 0;
56 struct ata_device *dev; 56 struct ata_device *dev;
57 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
58 57
59 if (id->driver_data & ATA_GEN_FORCE_DMA) { 58 if (id->driver_data & ATA_GEN_FORCE_DMA) {
60 dma_enabled = 0xff; 59 dma_enabled = 0xff;
@@ -63,9 +62,6 @@ static int generic_set_mode(struct ata_link *link, struct ata_device **unused)
63 dma_enabled = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); 62 dma_enabled = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
64 } 63 }
65 64
66 if (pdev->vendor == PCI_VENDOR_ID_CENATEK)
67 dma_enabled = 0xFF;
68
69 ata_for_each_dev(dev, link, ENABLED) { 65 ata_for_each_dev(dev, link, ENABLED) {
70 /* We don't really care */ 66 /* We don't really care */
71 dev->pio_mode = XFER_PIO_0; 67 dev->pio_mode = XFER_PIO_0;
diff --git a/drivers/ata/ata_piix.c b/drivers/ata/ata_piix.c
index 7409f98d2ae6..3971bc0a4838 100644
--- a/drivers/ata/ata_piix.c
+++ b/drivers/ata/ata_piix.c
@@ -158,6 +158,7 @@ struct piix_map_db {
158struct piix_host_priv { 158struct piix_host_priv {
159 const int *map; 159 const int *map;
160 u32 saved_iocfg; 160 u32 saved_iocfg;
161 spinlock_t sidpr_lock; /* FIXME: remove once locking in EH is fixed */
161 void __iomem *sidpr; 162 void __iomem *sidpr;
162}; 163};
163 164
@@ -951,12 +952,15 @@ static int piix_sidpr_scr_read(struct ata_link *link,
951 unsigned int reg, u32 *val) 952 unsigned int reg, u32 *val)
952{ 953{
953 struct piix_host_priv *hpriv = link->ap->host->private_data; 954 struct piix_host_priv *hpriv = link->ap->host->private_data;
955 unsigned long flags;
954 956
955 if (reg >= ARRAY_SIZE(piix_sidx_map)) 957 if (reg >= ARRAY_SIZE(piix_sidx_map))
956 return -EINVAL; 958 return -EINVAL;
957 959
960 spin_lock_irqsave(&hpriv->sidpr_lock, flags);
958 piix_sidpr_sel(link, reg); 961 piix_sidpr_sel(link, reg);
959 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA); 962 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
963 spin_unlock_irqrestore(&hpriv->sidpr_lock, flags);
960 return 0; 964 return 0;
961} 965}
962 966
@@ -964,12 +968,15 @@ static int piix_sidpr_scr_write(struct ata_link *link,
964 unsigned int reg, u32 val) 968 unsigned int reg, u32 val)
965{ 969{
966 struct piix_host_priv *hpriv = link->ap->host->private_data; 970 struct piix_host_priv *hpriv = link->ap->host->private_data;
971 unsigned long flags;
967 972
968 if (reg >= ARRAY_SIZE(piix_sidx_map)) 973 if (reg >= ARRAY_SIZE(piix_sidx_map))
969 return -EINVAL; 974 return -EINVAL;
970 975
976 spin_lock_irqsave(&hpriv->sidpr_lock, flags);
971 piix_sidpr_sel(link, reg); 977 piix_sidpr_sel(link, reg);
972 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA); 978 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
979 spin_unlock_irqrestore(&hpriv->sidpr_lock, flags);
973 return 0; 980 return 0;
974} 981}
975 982
@@ -1566,6 +1573,7 @@ static int __devinit piix_init_one(struct pci_dev *pdev,
1566 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1573 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1567 if (!hpriv) 1574 if (!hpriv)
1568 return -ENOMEM; 1575 return -ENOMEM;
1576 spin_lock_init(&hpriv->sidpr_lock);
1569 1577
1570 /* Save IOCFG, this will be used for cable detection, quirk 1578 /* Save IOCFG, this will be used for cable detection, quirk
1571 * detection and restoration on detach. This is necessary 1579 * detection and restoration on detach. This is necessary
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index ddf8e4862787..a0a4d6968400 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -4167,15 +4167,13 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = {
4167 { "WDC AC23200L", "21.10N21", ATA_HORKAGE_NODMA }, 4167 { "WDC AC23200L", "21.10N21", ATA_HORKAGE_NODMA },
4168 { "Compaq CRD-8241B", NULL, ATA_HORKAGE_NODMA }, 4168 { "Compaq CRD-8241B", NULL, ATA_HORKAGE_NODMA },
4169 { "CRD-8400B", NULL, ATA_HORKAGE_NODMA }, 4169 { "CRD-8400B", NULL, ATA_HORKAGE_NODMA },
4170 { "CRD-8480B", NULL, ATA_HORKAGE_NODMA }, 4170 { "CRD-848[02]B", NULL, ATA_HORKAGE_NODMA },
4171 { "CRD-8482B", NULL, ATA_HORKAGE_NODMA },
4172 { "CRD-84", NULL, ATA_HORKAGE_NODMA }, 4171 { "CRD-84", NULL, ATA_HORKAGE_NODMA },
4173 { "SanDisk SDP3B", NULL, ATA_HORKAGE_NODMA }, 4172 { "SanDisk SDP3B", NULL, ATA_HORKAGE_NODMA },
4174 { "SanDisk SDP3B-64", NULL, ATA_HORKAGE_NODMA }, 4173 { "SanDisk SDP3B-64", NULL, ATA_HORKAGE_NODMA },
4175 { "SANYO CD-ROM CRD", NULL, ATA_HORKAGE_NODMA }, 4174 { "SANYO CD-ROM CRD", NULL, ATA_HORKAGE_NODMA },
4176 { "HITACHI CDR-8", NULL, ATA_HORKAGE_NODMA }, 4175 { "HITACHI CDR-8", NULL, ATA_HORKAGE_NODMA },
4177 { "HITACHI CDR-8335", NULL, ATA_HORKAGE_NODMA }, 4176 { "HITACHI CDR-8[34]35",NULL, ATA_HORKAGE_NODMA },
4178 { "HITACHI CDR-8435", NULL, ATA_HORKAGE_NODMA },
4179 { "Toshiba CD-ROM XM-6202B", NULL, ATA_HORKAGE_NODMA }, 4177 { "Toshiba CD-ROM XM-6202B", NULL, ATA_HORKAGE_NODMA },
4180 { "TOSHIBA CD-ROM XM-1702BC", NULL, ATA_HORKAGE_NODMA }, 4178 { "TOSHIBA CD-ROM XM-1702BC", NULL, ATA_HORKAGE_NODMA },
4181 { "CD-532E-A", NULL, ATA_HORKAGE_NODMA }, 4179 { "CD-532E-A", NULL, ATA_HORKAGE_NODMA },
@@ -4211,70 +4209,16 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = {
4211 { "OCZ CORE_SSD", "02.10104", ATA_HORKAGE_NONCQ }, 4209 { "OCZ CORE_SSD", "02.10104", ATA_HORKAGE_NONCQ },
4212 4210
4213 /* Seagate NCQ + FLUSH CACHE firmware bug */ 4211 /* Seagate NCQ + FLUSH CACHE firmware bug */
4214 { "ST31500341AS", "SD15", ATA_HORKAGE_NONCQ | 4212 { "ST31500341AS", "SD1[5-9]", ATA_HORKAGE_NONCQ |
4215 ATA_HORKAGE_FIRMWARE_WARN },
4216 { "ST31500341AS", "SD16", ATA_HORKAGE_NONCQ |
4217 ATA_HORKAGE_FIRMWARE_WARN },
4218 { "ST31500341AS", "SD17", ATA_HORKAGE_NONCQ |
4219 ATA_HORKAGE_FIRMWARE_WARN },
4220 { "ST31500341AS", "SD18", ATA_HORKAGE_NONCQ |
4221 ATA_HORKAGE_FIRMWARE_WARN },
4222 { "ST31500341AS", "SD19", ATA_HORKAGE_NONCQ |
4223 ATA_HORKAGE_FIRMWARE_WARN }, 4213 ATA_HORKAGE_FIRMWARE_WARN },
4224 4214
4225 { "ST31000333AS", "SD15", ATA_HORKAGE_NONCQ | 4215 { "ST31000333AS", "SD1[5-9]", ATA_HORKAGE_NONCQ |
4226 ATA_HORKAGE_FIRMWARE_WARN },
4227 { "ST31000333AS", "SD16", ATA_HORKAGE_NONCQ |
4228 ATA_HORKAGE_FIRMWARE_WARN },
4229 { "ST31000333AS", "SD17", ATA_HORKAGE_NONCQ |
4230 ATA_HORKAGE_FIRMWARE_WARN },
4231 { "ST31000333AS", "SD18", ATA_HORKAGE_NONCQ |
4232 ATA_HORKAGE_FIRMWARE_WARN },
4233 { "ST31000333AS", "SD19", ATA_HORKAGE_NONCQ |
4234 ATA_HORKAGE_FIRMWARE_WARN }, 4216 ATA_HORKAGE_FIRMWARE_WARN },
4235 4217
4236 { "ST3640623AS", "SD15", ATA_HORKAGE_NONCQ | 4218 { "ST3640[36]23AS", "SD1[5-9]", ATA_HORKAGE_NONCQ |
4237 ATA_HORKAGE_FIRMWARE_WARN },
4238 { "ST3640623AS", "SD16", ATA_HORKAGE_NONCQ |
4239 ATA_HORKAGE_FIRMWARE_WARN },
4240 { "ST3640623AS", "SD17", ATA_HORKAGE_NONCQ |
4241 ATA_HORKAGE_FIRMWARE_WARN },
4242 { "ST3640623AS", "SD18", ATA_HORKAGE_NONCQ |
4243 ATA_HORKAGE_FIRMWARE_WARN },
4244 { "ST3640623AS", "SD19", ATA_HORKAGE_NONCQ |
4245 ATA_HORKAGE_FIRMWARE_WARN }, 4219 ATA_HORKAGE_FIRMWARE_WARN },
4246 4220
4247 { "ST3640323AS", "SD15", ATA_HORKAGE_NONCQ | 4221 { "ST3320[68]13AS", "SD1[5-9]", ATA_HORKAGE_NONCQ |
4248 ATA_HORKAGE_FIRMWARE_WARN },
4249 { "ST3640323AS", "SD16", ATA_HORKAGE_NONCQ |
4250 ATA_HORKAGE_FIRMWARE_WARN },
4251 { "ST3640323AS", "SD17", ATA_HORKAGE_NONCQ |
4252 ATA_HORKAGE_FIRMWARE_WARN },
4253 { "ST3640323AS", "SD18", ATA_HORKAGE_NONCQ |
4254 ATA_HORKAGE_FIRMWARE_WARN },
4255 { "ST3640323AS", "SD19", ATA_HORKAGE_NONCQ |
4256 ATA_HORKAGE_FIRMWARE_WARN },
4257
4258 { "ST3320813AS", "SD15", ATA_HORKAGE_NONCQ |
4259 ATA_HORKAGE_FIRMWARE_WARN },
4260 { "ST3320813AS", "SD16", ATA_HORKAGE_NONCQ |
4261 ATA_HORKAGE_FIRMWARE_WARN },
4262 { "ST3320813AS", "SD17", ATA_HORKAGE_NONCQ |
4263 ATA_HORKAGE_FIRMWARE_WARN },
4264 { "ST3320813AS", "SD18", ATA_HORKAGE_NONCQ |
4265 ATA_HORKAGE_FIRMWARE_WARN },
4266 { "ST3320813AS", "SD19", ATA_HORKAGE_NONCQ |
4267 ATA_HORKAGE_FIRMWARE_WARN },
4268
4269 { "ST3320613AS", "SD15", ATA_HORKAGE_NONCQ |
4270 ATA_HORKAGE_FIRMWARE_WARN },
4271 { "ST3320613AS", "SD16", ATA_HORKAGE_NONCQ |
4272 ATA_HORKAGE_FIRMWARE_WARN },
4273 { "ST3320613AS", "SD17", ATA_HORKAGE_NONCQ |
4274 ATA_HORKAGE_FIRMWARE_WARN },
4275 { "ST3320613AS", "SD18", ATA_HORKAGE_NONCQ |
4276 ATA_HORKAGE_FIRMWARE_WARN },
4277 { "ST3320613AS", "SD19", ATA_HORKAGE_NONCQ |
4278 ATA_HORKAGE_FIRMWARE_WARN }, 4222 ATA_HORKAGE_FIRMWARE_WARN },
4279 4223
4280 /* Blacklist entries taken from Silicon Image 3124/3132 4224 /* Blacklist entries taken from Silicon Image 3124/3132
@@ -4303,12 +4247,7 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = {
4303 /* Devices which get the IVB wrong */ 4247 /* Devices which get the IVB wrong */
4304 { "QUANTUM FIREBALLlct10 05", "A03.0900", ATA_HORKAGE_IVB, }, 4248 { "QUANTUM FIREBALLlct10 05", "A03.0900", ATA_HORKAGE_IVB, },
4305 /* Maybe we should just blacklist TSSTcorp... */ 4249 /* Maybe we should just blacklist TSSTcorp... */
4306 { "TSSTcorp CDDVDW SH-S202H", "SB00", ATA_HORKAGE_IVB, }, 4250 { "TSSTcorp CDDVDW SH-S202[HJN]", "SB0[01]", ATA_HORKAGE_IVB, },
4307 { "TSSTcorp CDDVDW SH-S202H", "SB01", ATA_HORKAGE_IVB, },
4308 { "TSSTcorp CDDVDW SH-S202J", "SB00", ATA_HORKAGE_IVB, },
4309 { "TSSTcorp CDDVDW SH-S202J", "SB01", ATA_HORKAGE_IVB, },
4310 { "TSSTcorp CDDVDW SH-S202N", "SB00", ATA_HORKAGE_IVB, },
4311 { "TSSTcorp CDDVDW SH-S202N", "SB01", ATA_HORKAGE_IVB, },
4312 4251
4313 /* Devices that do not need bridging limits applied */ 4252 /* Devices that do not need bridging limits applied */
4314 { "MTRON MSP-SATA*", NULL, ATA_HORKAGE_BRIDGE_OK, }, 4253 { "MTRON MSP-SATA*", NULL, ATA_HORKAGE_BRIDGE_OK, },
@@ -4326,29 +4265,73 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = {
4326 { } 4265 { }
4327}; 4266};
4328 4267
4329static int strn_pattern_cmp(const char *patt, const char *name, int wildchar) 4268/**
4269 * glob_match - match a text string against a glob-style pattern
4270 * @text: the string to be examined
4271 * @pattern: the glob-style pattern to be matched against
4272 *
4273 * Either/both of text and pattern can be empty strings.
4274 *
4275 * Match text against a glob-style pattern, with wildcards and simple sets:
4276 *
4277 * ? matches any single character.
4278 * * matches any run of characters.
4279 * [xyz] matches a single character from the set: x, y, or z.
4280 * [a-d] matches a single character from the range: a, b, c, or d.
4281 * [a-d0-9] matches a single character from either range.
4282 *
4283 * The special characters ?, [, -, or *, can be matched using a set, eg. [*]
4284 * Behaviour with malformed patterns is undefined, though generally reasonable.
4285 *
4286 * Example patterns: "SD1?", "SD1[0-5]", "*R0", SD*1?[012]*xx"
4287 *
4288 * This function uses one level of recursion per '*' in pattern.
4289 * Since it calls _nothing_ else, and has _no_ explicit local variables,
4290 * this will not cause stack problems for any reasonable use here.
4291 *
4292 * RETURNS:
4293 * 0 on match, 1 otherwise.
4294 */
4295static int glob_match (const char *text, const char *pattern)
4330{ 4296{
4331 const char *p; 4297 do {
4332 int len; 4298 /* Match single character or a '?' wildcard */
4333 4299 if (*text == *pattern || *pattern == '?') {
4334 /* 4300 if (!*pattern++)
4335 * check for trailing wildcard: *\0 4301 return 0; /* End of both strings: match */
4336 */ 4302 } else {
4337 p = strchr(patt, wildchar); 4303 /* Match single char against a '[' bracketed ']' pattern set */
4338 if (p && ((*(p + 1)) == 0)) 4304 if (!*text || *pattern != '[')
4339 len = p - patt; 4305 break; /* Not a pattern set */
4340 else { 4306 while (*++pattern && *pattern != ']' && *text != *pattern) {
4341 len = strlen(name); 4307 if (*pattern == '-' && *(pattern - 1) != '[')
4342 if (!len) { 4308 if (*text > *(pattern - 1) && *text < *(pattern + 1)) {
4343 if (!*patt) 4309 ++pattern;
4344 return 0; 4310 break;
4345 return -1; 4311 }
4312 }
4313 if (!*pattern || *pattern == ']')
4314 return 1; /* No match */
4315 while (*pattern && *pattern++ != ']');
4316 }
4317 } while (*++text && *pattern);
4318
4319 /* Match any run of chars against a '*' wildcard */
4320 if (*pattern == '*') {
4321 if (!*++pattern)
4322 return 0; /* Match: avoid recursion at end of pattern */
4323 /* Loop to handle additional pattern chars after the wildcard */
4324 while (*text) {
4325 if (glob_match(text, pattern) == 0)
4326 return 0; /* Remainder matched */
4327 ++text; /* Absorb (match) this char and try again */
4346 } 4328 }
4347 } 4329 }
4348 4330 if (!*text && !*pattern)
4349 return strncmp(patt, name, len); 4331 return 0; /* End of both strings: match */
4332 return 1; /* No match */
4350} 4333}
4351 4334
4352static unsigned long ata_dev_blacklisted(const struct ata_device *dev) 4335static unsigned long ata_dev_blacklisted(const struct ata_device *dev)
4353{ 4336{
4354 unsigned char model_num[ATA_ID_PROD_LEN + 1]; 4337 unsigned char model_num[ATA_ID_PROD_LEN + 1];
@@ -4359,10 +4342,10 @@ static unsigned long ata_dev_blacklisted(const struct ata_device *dev)
4359 ata_id_c_string(dev->id, model_rev, ATA_ID_FW_REV, sizeof(model_rev)); 4342 ata_id_c_string(dev->id, model_rev, ATA_ID_FW_REV, sizeof(model_rev));
4360 4343
4361 while (ad->model_num) { 4344 while (ad->model_num) {
4362 if (!strn_pattern_cmp(ad->model_num, model_num, '*')) { 4345 if (!glob_match(model_num, ad->model_num)) {
4363 if (ad->model_rev == NULL) 4346 if (ad->model_rev == NULL)
4364 return ad->horkage; 4347 return ad->horkage;
4365 if (!strn_pattern_cmp(ad->model_rev, model_rev, '*')) 4348 if (!glob_match(model_rev, ad->model_rev))
4366 return ad->horkage; 4349 return ad->horkage;
4367 } 4350 }
4368 ad++; 4351 ad++;
diff --git a/drivers/ata/libata-eh.c b/drivers/ata/libata-eh.c
index f77a67303f8b..697474b625b7 100644
--- a/drivers/ata/libata-eh.c
+++ b/drivers/ata/libata-eh.c
@@ -2214,6 +2214,7 @@ const char *ata_get_cmd_descript(u8 command)
2214 { ATA_CMD_SMART, "SMART" }, 2214 { ATA_CMD_SMART, "SMART" },
2215 { ATA_CMD_MEDIA_LOCK, "DOOR LOCK" }, 2215 { ATA_CMD_MEDIA_LOCK, "DOOR LOCK" },
2216 { ATA_CMD_MEDIA_UNLOCK, "DOOR UNLOCK" }, 2216 { ATA_CMD_MEDIA_UNLOCK, "DOOR UNLOCK" },
2217 { ATA_CMD_DSM, "DATA SET MANAGEMENT" },
2217 { ATA_CMD_CHK_MED_CRD_TYP, "CHECK MEDIA CARD TYPE" }, 2218 { ATA_CMD_CHK_MED_CRD_TYP, "CHECK MEDIA CARD TYPE" },
2218 { ATA_CMD_CFA_REQ_EXT_ERR, "CFA REQUEST EXTENDED ERROR" }, 2219 { ATA_CMD_CFA_REQ_EXT_ERR, "CFA REQUEST EXTENDED ERROR" },
2219 { ATA_CMD_CFA_WRITE_NE, "CFA WRITE SECTORS WITHOUT ERASE" }, 2220 { ATA_CMD_CFA_WRITE_NE, "CFA WRITE SECTORS WITHOUT ERASE" },
diff --git a/drivers/ata/pata_samsung_cf.c b/drivers/ata/pata_samsung_cf.c
new file mode 100644
index 000000000000..6f9cfb24b751
--- /dev/null
+++ b/drivers/ata/pata_samsung_cf.c
@@ -0,0 +1,683 @@
1/*
2 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * PATA driver for Samsung SoCs.
6 * Supports CF Interface in True IDE mode. Currently only PIO mode has been
7 * implemented; UDMA support has to be added.
8 *
9 * Based on:
10 * PATA driver for AT91SAM9260 Static Memory Controller
11 * PATA driver for Toshiba SCC controller
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License version 2
15 * as published by the Free Software Foundation.
16*/
17
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/init.h>
21#include <linux/clk.h>
22#include <linux/libata.h>
23#include <linux/platform_device.h>
24#include <linux/slab.h>
25
26#include <plat/ata.h>
27#include <plat/regs-ata.h>
28
29#define DRV_NAME "pata_samsung_cf"
30#define DRV_VERSION "0.1"
31
32enum s3c_cpu_type {
33 TYPE_S3C64XX,
34 TYPE_S5PC100,
35 TYPE_S5PV210,
36};
37
38/*
39 * struct s3c_ide_info - S3C PATA instance.
40 * @clk: The clock resource for this controller.
41 * @ide_addr: The area mapped for the hardware registers.
42 * @sfr_addr: The area mapped for the special function registers.
43 * @irq: The IRQ number we are using.
44 * @cpu_type: The exact type of this controller.
45 * @fifo_status_reg: The ATA_FIFO_STATUS register offset.
46 */
47struct s3c_ide_info {
48 struct clk *clk;
49 void __iomem *ide_addr;
50 void __iomem *sfr_addr;
51 unsigned int irq;
52 enum s3c_cpu_type cpu_type;
53 unsigned int fifo_status_reg;
54};
55
56static void pata_s3c_set_endian(void __iomem *s3c_ide_regbase, u8 mode)
57{
58 u32 reg = readl(s3c_ide_regbase + S3C_ATA_CFG);
59 reg = mode ? (reg & ~S3C_ATA_CFG_SWAP) : (reg | S3C_ATA_CFG_SWAP);
60 writel(reg, s3c_ide_regbase + S3C_ATA_CFG);
61}
62
63static void pata_s3c_cfg_mode(void __iomem *s3c_ide_sfrbase)
64{
65 /* Select true-ide as the internal operating mode */
66 writel(readl(s3c_ide_sfrbase + S3C_CFATA_MUX) | S3C_CFATA_MUX_TRUEIDE,
67 s3c_ide_sfrbase + S3C_CFATA_MUX);
68}
69
70static unsigned long
71pata_s3c_setup_timing(struct s3c_ide_info *info, const struct ata_timing *ata)
72{
73 int t1 = ata->setup;
74 int t2 = ata->act8b;
75 int t2i = ata->rec8b;
76 ulong piotime;
77
78 piotime = ((t2i & 0xff) << 12) | ((t2 & 0xff) << 4) | (t1 & 0xf);
79
80 return piotime;
81}
82
83static void pata_s3c_set_piomode(struct ata_port *ap, struct ata_device *adev)
84{
85 struct s3c_ide_info *info = ap->host->private_data;
86 struct ata_timing timing;
87 int cycle_time;
88 ulong ata_cfg = readl(info->ide_addr + S3C_ATA_CFG);
89 ulong piotime;
90
91 /* Enables IORDY if mode requires it */
92 if (ata_pio_need_iordy(adev))
93 ata_cfg |= S3C_ATA_CFG_IORDYEN;
94 else
95 ata_cfg &= ~S3C_ATA_CFG_IORDYEN;
96
97 cycle_time = (int)(1000000000UL / clk_get_rate(info->clk));
98
99 ata_timing_compute(adev, adev->pio_mode, &timing,
100 cycle_time * 1000, 0);
101
102 piotime = pata_s3c_setup_timing(info, &timing);
103
104 writel(ata_cfg, info->ide_addr + S3C_ATA_CFG);
105 writel(piotime, info->ide_addr + S3C_ATA_PIO_TIME);
106}
107
108/*
109 * Waits until the IDE controller is able to perform next read/write
110 * operation to the disk. Needed for 64XX series boards only.
111 */
112static int wait_for_host_ready(struct s3c_ide_info *info)
113{
114 ulong timeout;
115 void __iomem *fifo_reg = info->ide_addr + info->fifo_status_reg;
116
117 /* wait for maximum of 20 msec */
118 timeout = jiffies + msecs_to_jiffies(20);
119 while (time_before(jiffies, timeout)) {
120 if ((readl(fifo_reg) >> 28) == 0)
121 return 0;
122 }
123 return -EBUSY;
124}
125
126/*
127 * Writes to one of the task file registers.
128 */
129static void ata_outb(struct ata_host *host, u8 addr, void __iomem *reg)
130{
131 struct s3c_ide_info *info = host->private_data;
132
133 wait_for_host_ready(info);
134 writeb(addr, reg);
135}
136
137/*
138 * Reads from one of the task file registers.
139 */
140static u8 ata_inb(struct ata_host *host, void __iomem *reg)
141{
142 struct s3c_ide_info *info = host->private_data;
143 u8 temp;
144
145 wait_for_host_ready(info);
146 (void) readb(reg);
147 wait_for_host_ready(info);
148 temp = readb(info->ide_addr + S3C_ATA_PIO_RDATA);
149 return temp;
150}
151
152/*
153 * pata_s3c_tf_load - send taskfile registers to host controller
154 */
155static void pata_s3c_tf_load(struct ata_port *ap,
156 const struct ata_taskfile *tf)
157{
158 struct ata_ioports *ioaddr = &ap->ioaddr;
159 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
160
161 if (tf->ctl != ap->last_ctl) {
162 ata_outb(ap->host, tf->ctl, ioaddr->ctl_addr);
163 ap->last_ctl = tf->ctl;
164 ata_wait_idle(ap);
165 }
166
167 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
168 ata_outb(ap->host, tf->hob_feature, ioaddr->feature_addr);
169 ata_outb(ap->host, tf->hob_nsect, ioaddr->nsect_addr);
170 ata_outb(ap->host, tf->hob_lbal, ioaddr->lbal_addr);
171 ata_outb(ap->host, tf->hob_lbam, ioaddr->lbam_addr);
172 ata_outb(ap->host, tf->hob_lbah, ioaddr->lbah_addr);
173 }
174
175 if (is_addr) {
176 ata_outb(ap->host, tf->feature, ioaddr->feature_addr);
177 ata_outb(ap->host, tf->nsect, ioaddr->nsect_addr);
178 ata_outb(ap->host, tf->lbal, ioaddr->lbal_addr);
179 ata_outb(ap->host, tf->lbam, ioaddr->lbam_addr);
180 ata_outb(ap->host, tf->lbah, ioaddr->lbah_addr);
181 }
182
183 if (tf->flags & ATA_TFLAG_DEVICE)
184 ata_outb(ap->host, tf->device, ioaddr->device_addr);
185
186 ata_wait_idle(ap);
187}
188
189/*
190 * pata_s3c_tf_read - input device's ATA taskfile shadow registers
191 */
192static void pata_s3c_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
193{
194 struct ata_ioports *ioaddr = &ap->ioaddr;
195
196 tf->feature = ata_inb(ap->host, ioaddr->error_addr);
197 tf->nsect = ata_inb(ap->host, ioaddr->nsect_addr);
198 tf->lbal = ata_inb(ap->host, ioaddr->lbal_addr);
199 tf->lbam = ata_inb(ap->host, ioaddr->lbam_addr);
200 tf->lbah = ata_inb(ap->host, ioaddr->lbah_addr);
201 tf->device = ata_inb(ap->host, ioaddr->device_addr);
202
203 if (tf->flags & ATA_TFLAG_LBA48) {
204 ata_outb(ap->host, tf->ctl | ATA_HOB, ioaddr->ctl_addr);
205 tf->hob_feature = ata_inb(ap->host, ioaddr->error_addr);
206 tf->hob_nsect = ata_inb(ap->host, ioaddr->nsect_addr);
207 tf->hob_lbal = ata_inb(ap->host, ioaddr->lbal_addr);
208 tf->hob_lbam = ata_inb(ap->host, ioaddr->lbam_addr);
209 tf->hob_lbah = ata_inb(ap->host, ioaddr->lbah_addr);
210 ata_outb(ap->host, tf->ctl, ioaddr->ctl_addr);
211 ap->last_ctl = tf->ctl;
212 }
213}
214
215/*
216 * pata_s3c_exec_command - issue ATA command to host controller
217 */
218static void pata_s3c_exec_command(struct ata_port *ap,
219 const struct ata_taskfile *tf)
220{
221 ata_outb(ap->host, tf->command, ap->ioaddr.command_addr);
222 ata_sff_pause(ap);
223}
224
225/*
226 * pata_s3c_check_status - Read device status register
227 */
228static u8 pata_s3c_check_status(struct ata_port *ap)
229{
230 return ata_inb(ap->host, ap->ioaddr.status_addr);
231}
232
233/*
234 * pata_s3c_check_altstatus - Read alternate device status register
235 */
236static u8 pata_s3c_check_altstatus(struct ata_port *ap)
237{
238 return ata_inb(ap->host, ap->ioaddr.altstatus_addr);
239}
240
241/*
242 * pata_s3c_data_xfer - Transfer data by PIO
243 */
244unsigned int pata_s3c_data_xfer(struct ata_device *dev, unsigned char *buf,
245 unsigned int buflen, int rw)
246{
247 struct ata_port *ap = dev->link->ap;
248 struct s3c_ide_info *info = ap->host->private_data;
249 void __iomem *data_addr = ap->ioaddr.data_addr;
250 unsigned int words = buflen >> 1, i;
251 u16 *data_ptr = (u16 *)buf;
252
253 /* Requires wait same as in ata_inb/ata_outb */
254 if (rw == READ)
255 for (i = 0; i < words; i++, data_ptr++) {
256 wait_for_host_ready(info);
257 (void) readw(data_addr);
258 wait_for_host_ready(info);
259 *data_ptr = readw(info->ide_addr
260 + S3C_ATA_PIO_RDATA);
261 }
262 else
263 for (i = 0; i < words; i++, data_ptr++) {
264 wait_for_host_ready(info);
265 writew(*data_ptr, data_addr);
266 }
267
268 if (buflen & 0x01)
269 dev_err(ap->dev, "unexpected trailing data\n");
270
271 return words << 1;
272}
273
274/*
275 * pata_s3c_dev_select - Select device on ATA bus
276 */
277static void pata_s3c_dev_select(struct ata_port *ap, unsigned int device)
278{
279 u8 tmp = ATA_DEVICE_OBS;
280
281 if (device != 0)
282 tmp |= ATA_DEV1;
283
284 ata_outb(ap->host, tmp, ap->ioaddr.device_addr);
285 ata_sff_pause(ap);
286}
287
288/*
289 * pata_s3c_devchk - PATA device presence detection
290 */
291static unsigned int pata_s3c_devchk(struct ata_port *ap,
292 unsigned int device)
293{
294 struct ata_ioports *ioaddr = &ap->ioaddr;
295 u8 nsect, lbal;
296
297 pata_s3c_dev_select(ap, device);
298
299 ata_outb(ap->host, 0x55, ioaddr->nsect_addr);
300 ata_outb(ap->host, 0xaa, ioaddr->lbal_addr);
301
302 ata_outb(ap->host, 0xaa, ioaddr->nsect_addr);
303 ata_outb(ap->host, 0x55, ioaddr->lbal_addr);
304
305 ata_outb(ap->host, 0x55, ioaddr->nsect_addr);
306 ata_outb(ap->host, 0xaa, ioaddr->lbal_addr);
307
308 nsect = ata_inb(ap->host, ioaddr->nsect_addr);
309 lbal = ata_inb(ap->host, ioaddr->lbal_addr);
310
311 if ((nsect == 0x55) && (lbal == 0xaa))
312 return 1; /* we found a device */
313
314 return 0; /* nothing found */
315}
316
317/*
318 * pata_s3c_wait_after_reset - wait for devices to become ready after reset
319 */
320static int pata_s3c_wait_after_reset(struct ata_link *link,
321 unsigned long deadline)
322{
323 int rc;
324
325 msleep(ATA_WAIT_AFTER_RESET);
326
327 /* always check readiness of the master device */
328 rc = ata_sff_wait_ready(link, deadline);
329 /* -ENODEV means the odd clown forgot the D7 pulldown resistor
330 * and TF status is 0xff, bail out on it too.
331 */
332 if (rc)
333 return rc;
334
335 return 0;
336}
337
338/*
339 * pata_s3c_bus_softreset - PATA device software reset
340 */
341static unsigned int pata_s3c_bus_softreset(struct ata_port *ap,
342 unsigned long deadline)
343{
344 struct ata_ioports *ioaddr = &ap->ioaddr;
345
346 /* software reset. causes dev0 to be selected */
347 ata_outb(ap->host, ap->ctl, ioaddr->ctl_addr);
348 udelay(20);
349 ata_outb(ap->host, ap->ctl | ATA_SRST, ioaddr->ctl_addr);
350 udelay(20);
351 ata_outb(ap->host, ap->ctl, ioaddr->ctl_addr);
352 ap->last_ctl = ap->ctl;
353
354 return pata_s3c_wait_after_reset(&ap->link, deadline);
355}
356
357/*
358 * pata_s3c_softreset - reset host port via ATA SRST
359 */
360static int pata_s3c_softreset(struct ata_link *link, unsigned int *classes,
361 unsigned long deadline)
362{
363 struct ata_port *ap = link->ap;
364 unsigned int devmask = 0;
365 int rc;
366 u8 err;
367
368 /* determine if device 0 is present */
369 if (pata_s3c_devchk(ap, 0))
370 devmask |= (1 << 0);
371
372 /* select device 0 again */
373 pata_s3c_dev_select(ap, 0);
374
375 /* issue bus reset */
376 rc = pata_s3c_bus_softreset(ap, deadline);
377 /* if link is occupied, -ENODEV too is an error */
378 if (rc && rc != -ENODEV) {
379 ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc);
380 return rc;
381 }
382
383 /* determine by signature whether we have ATA or ATAPI devices */
384 classes[0] = ata_sff_dev_classify(&ap->link.device[0],
385 devmask & (1 << 0), &err);
386
387 return 0;
388}
389
390/*
391 * pata_s3c_set_devctl - Write device control register
392 */
393static void pata_s3c_set_devctl(struct ata_port *ap, u8 ctl)
394{
395 ata_outb(ap->host, ctl, ap->ioaddr.ctl_addr);
396}
397
398static struct scsi_host_template pata_s3c_sht = {
399 ATA_PIO_SHT(DRV_NAME),
400};
401
402static struct ata_port_operations pata_s3c_port_ops = {
403 .inherits = &ata_sff_port_ops,
404 .sff_check_status = pata_s3c_check_status,
405 .sff_check_altstatus = pata_s3c_check_altstatus,
406 .sff_tf_load = pata_s3c_tf_load,
407 .sff_tf_read = pata_s3c_tf_read,
408 .sff_data_xfer = pata_s3c_data_xfer,
409 .sff_exec_command = pata_s3c_exec_command,
410 .sff_dev_select = pata_s3c_dev_select,
411 .sff_set_devctl = pata_s3c_set_devctl,
412 .softreset = pata_s3c_softreset,
413 .set_piomode = pata_s3c_set_piomode,
414};
415
416static struct ata_port_operations pata_s5p_port_ops = {
417 .inherits = &ata_sff_port_ops,
418 .set_piomode = pata_s3c_set_piomode,
419};
420
421static void pata_s3c_enable(void *s3c_ide_regbase, bool state)
422{
423 u32 temp = readl(s3c_ide_regbase + S3C_ATA_CTRL);
424 temp = state ? (temp | 1) : (temp & ~1);
425 writel(temp, s3c_ide_regbase + S3C_ATA_CTRL);
426}
427
428static irqreturn_t pata_s3c_irq(int irq, void *dev_instance)
429{
430 struct ata_host *host = dev_instance;
431 struct s3c_ide_info *info = host->private_data;
432 u32 reg;
433
434 reg = readl(info->ide_addr + S3C_ATA_IRQ);
435 writel(reg, info->ide_addr + S3C_ATA_IRQ);
436
437 return ata_sff_interrupt(irq, dev_instance);
438}
439
440static void pata_s3c_hwinit(struct s3c_ide_info *info,
441 struct s3c_ide_platdata *pdata)
442{
443 switch (info->cpu_type) {
444 case TYPE_S3C64XX:
445 /* Configure as big endian */
446 pata_s3c_cfg_mode(info->sfr_addr);
447 pata_s3c_set_endian(info->ide_addr, 1);
448 pata_s3c_enable(info->ide_addr, true);
449 msleep(100);
450
451 /* Remove IRQ Status */
452 writel(0x1f, info->ide_addr + S3C_ATA_IRQ);
453 writel(0x1b, info->ide_addr + S3C_ATA_IRQ_MSK);
454 break;
455
456 case TYPE_S5PC100:
457 pata_s3c_cfg_mode(info->sfr_addr);
458 /* FALLTHROUGH */
459
460 case TYPE_S5PV210:
461 /* Configure as little endian */
462 pata_s3c_set_endian(info->ide_addr, 0);
463 pata_s3c_enable(info->ide_addr, true);
464 msleep(100);
465
466 /* Remove IRQ Status */
467 writel(0x3f, info->ide_addr + S3C_ATA_IRQ);
468 writel(0x3f, info->ide_addr + S3C_ATA_IRQ_MSK);
469 break;
470
471 default:
472 BUG();
473 }
474}
475
476static int __init pata_s3c_probe(struct platform_device *pdev)
477{
478 struct s3c_ide_platdata *pdata = pdev->dev.platform_data;
479 struct device *dev = &pdev->dev;
480 struct s3c_ide_info *info;
481 struct resource *res;
482 struct ata_port *ap;
483 struct ata_host *host;
484 enum s3c_cpu_type cpu_type;
485 int ret;
486
487 cpu_type = platform_get_device_id(pdev)->driver_data;
488
489 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
490 if (!info) {
491 dev_err(dev, "failed to allocate memory for device data\n");
492 return -ENOMEM;
493 }
494
495 info->irq = platform_get_irq(pdev, 0);
496
497 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
498 if (res == NULL) {
499 dev_err(dev, "failed to get mem resource\n");
500 return -EINVAL;
501 }
502
503 if (!devm_request_mem_region(dev, res->start,
504 resource_size(res), DRV_NAME)) {
505 dev_err(dev, "error requesting register region\n");
506 return -EBUSY;
507 }
508
509 info->ide_addr = devm_ioremap(dev, res->start, resource_size(res));
510 if (!info->ide_addr) {
511 dev_err(dev, "failed to map IO base address\n");
512 return -ENOMEM;
513 }
514
515 info->clk = clk_get(&pdev->dev, "cfcon");
516 if (IS_ERR(info->clk)) {
517 dev_err(dev, "failed to get access to cf controller clock\n");
518 ret = PTR_ERR(info->clk);
519 info->clk = NULL;
520 return ret;
521 }
522
523 clk_enable(info->clk);
524
525 /* init ata host */
526 host = ata_host_alloc(dev, 1);
527 if (!host) {
528 dev_err(dev, "failed to allocate ide host\n");
529 ret = -ENOMEM;
530 goto stop_clk;
531 }
532
533 ap = host->ports[0];
534 ap->flags |= ATA_FLAG_MMIO;
535 ap->pio_mask = ATA_PIO4;
536
537 if (cpu_type == TYPE_S3C64XX) {
538 ap->ops = &pata_s3c_port_ops;
539 info->sfr_addr = info->ide_addr + 0x1800;
540 info->ide_addr += 0x1900;
541 info->fifo_status_reg = 0x94;
542 } else if (cpu_type == TYPE_S5PC100) {
543 ap->ops = &pata_s5p_port_ops;
544 info->sfr_addr = info->ide_addr + 0x1800;
545 info->ide_addr += 0x1900;
546 info->fifo_status_reg = 0x84;
547 } else {
548 ap->ops = &pata_s5p_port_ops;
549 info->fifo_status_reg = 0x84;
550 }
551
552 info->cpu_type = cpu_type;
553
554 if (info->irq <= 0) {
555 ap->flags |= ATA_FLAG_PIO_POLLING;
556 info->irq = 0;
557 ata_port_desc(ap, "no IRQ, using PIO polling\n");
558 }
559
560 ap->ioaddr.cmd_addr = info->ide_addr + S3C_ATA_CMD;
561 ap->ioaddr.data_addr = info->ide_addr + S3C_ATA_PIO_DTR;
562 ap->ioaddr.error_addr = info->ide_addr + S3C_ATA_PIO_FED;
563 ap->ioaddr.feature_addr = info->ide_addr + S3C_ATA_PIO_FED;
564 ap->ioaddr.nsect_addr = info->ide_addr + S3C_ATA_PIO_SCR;
565 ap->ioaddr.lbal_addr = info->ide_addr + S3C_ATA_PIO_LLR;
566 ap->ioaddr.lbam_addr = info->ide_addr + S3C_ATA_PIO_LMR;
567 ap->ioaddr.lbah_addr = info->ide_addr + S3C_ATA_PIO_LHR;
568 ap->ioaddr.device_addr = info->ide_addr + S3C_ATA_PIO_DVR;
569 ap->ioaddr.status_addr = info->ide_addr + S3C_ATA_PIO_CSD;
570 ap->ioaddr.command_addr = info->ide_addr + S3C_ATA_PIO_CSD;
571 ap->ioaddr.altstatus_addr = info->ide_addr + S3C_ATA_PIO_DAD;
572 ap->ioaddr.ctl_addr = info->ide_addr + S3C_ATA_PIO_DAD;
573
574 ata_port_desc(ap, "mmio cmd 0x%llx ",
575 (unsigned long long)res->start);
576
577 host->private_data = info;
578
579 if (pdata && pdata->setup_gpio)
580 pdata->setup_gpio();
581
582 /* Set endianness and enable the interface */
583 pata_s3c_hwinit(info, pdata);
584
585 platform_set_drvdata(pdev, host);
586
587 return ata_host_activate(host, info->irq,
588 info->irq ? pata_s3c_irq : NULL,
589 0, &pata_s3c_sht);
590
591stop_clk:
592 clk_disable(info->clk);
593 clk_put(info->clk);
594 return ret;
595}
596
597static int __exit pata_s3c_remove(struct platform_device *pdev)
598{
599 struct ata_host *host = platform_get_drvdata(pdev);
600 struct s3c_ide_info *info = host->private_data;
601
602 ata_host_detach(host);
603
604 clk_disable(info->clk);
605 clk_put(info->clk);
606
607 return 0;
608}
609
610#ifdef CONFIG_PM
611static int pata_s3c_suspend(struct device *dev)
612{
613 struct platform_device *pdev = to_platform_device(dev);
614 struct ata_host *host = platform_get_drvdata(pdev);
615
616 return ata_host_suspend(host, PMSG_SUSPEND);
617}
618
619static int pata_s3c_resume(struct device *dev)
620{
621 struct platform_device *pdev = to_platform_device(dev);
622 struct ata_host *host = platform_get_drvdata(pdev);
623 struct s3c_ide_platdata *pdata = pdev->dev.platform_data;
624 struct s3c_ide_info *info = host->private_data;
625
626 pata_s3c_hwinit(info, pdata);
627 ata_host_resume(host);
628
629 return 0;
630}
631
632static const struct dev_pm_ops pata_s3c_pm_ops = {
633 .suspend = pata_s3c_suspend,
634 .resume = pata_s3c_resume,
635};
636#endif
637
638/* driver device registration */
639static struct platform_device_id pata_s3c_driver_ids[] = {
640 {
641 .name = "s3c64xx-pata",
642 .driver_data = TYPE_S3C64XX,
643 }, {
644 .name = "s5pc100-pata",
645 .driver_data = TYPE_S5PC100,
646 }, {
647 .name = "s5pv210-pata",
648 .driver_data = TYPE_S5PV210,
649 },
650 { }
651};
652
653MODULE_DEVICE_TABLE(platform, pata_s3c_driver_ids);
654
655static struct platform_driver pata_s3c_driver = {
656 .remove = __exit_p(pata_s3c_remove),
657 .id_table = pata_s3c_driver_ids,
658 .driver = {
659 .name = DRV_NAME,
660 .owner = THIS_MODULE,
661#ifdef CONFIG_PM
662 .pm = &pata_s3c_pm_ops,
663#endif
664 },
665};
666
667static int __init pata_s3c_init(void)
668{
669 return platform_driver_probe(&pata_s3c_driver, pata_s3c_probe);
670}
671
672static void __exit pata_s3c_exit(void)
673{
674 platform_driver_unregister(&pata_s3c_driver);
675}
676
677module_init(pata_s3c_init);
678module_exit(pata_s3c_exit);
679
680MODULE_AUTHOR("Abhilash Kesavan, <a.kesavan@samsung.com>");
681MODULE_DESCRIPTION("low-level driver for Samsung PATA controller");
682MODULE_LICENSE("GPL");
683MODULE_VERSION(DRV_VERSION);
diff --git a/drivers/ata/pata_scc.c b/drivers/ata/pata_scc.c
index d9db3f8d60ef..fe36966f7e34 100644
--- a/drivers/ata/pata_scc.c
+++ b/drivers/ata/pata_scc.c
@@ -168,8 +168,7 @@ static const unsigned long JCACTSELtbl[2][7] = {
168}; 168};
169 169
170static const struct pci_device_id scc_pci_tbl[] = { 170static const struct pci_device_id scc_pci_tbl[] = {
171 {PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA, 171 { PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA), 0},
172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
173 { } /* terminate list */ 172 { } /* terminate list */
174}; 173};
175 174
diff --git a/drivers/ata/sata_dwc_460ex.c b/drivers/ata/sata_dwc_460ex.c
new file mode 100644
index 000000000000..ea24c1e51be2
--- /dev/null
+++ b/drivers/ata/sata_dwc_460ex.c
@@ -0,0 +1,1756 @@
1/*
2 * drivers/ata/sata_dwc_460ex.c
3 *
4 * Synopsys DesignWare Cores (DWC) SATA host driver
5 *
6 * Author: Mark Miesfeld <mmiesfeld@amcc.com>
7 *
8 * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
9 * Copyright 2008 DENX Software Engineering
10 *
11 * Based on versions provided by AMCC and Synopsys which are:
12 * Copyright 2006 Applied Micro Circuits Corporation
13 * COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
20
21#ifdef CONFIG_SATA_DWC_DEBUG
22#define DEBUG
23#endif
24
25#ifdef CONFIG_SATA_DWC_VDEBUG
26#define VERBOSE_DEBUG
27#define DEBUG_NCQ
28#endif
29
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/init.h>
33#include <linux/device.h>
34#include <linux/of_platform.h>
35#include <linux/platform_device.h>
36#include <linux/libata.h>
37#include <linux/slab.h>
38#include "libata.h"
39
40#include <scsi/scsi_host.h>
41#include <scsi/scsi_cmnd.h>
42
43#define DRV_NAME "sata-dwc"
44#define DRV_VERSION "1.0"
45
46/* SATA DMA driver Globals */
47#define DMA_NUM_CHANS 1
48#define DMA_NUM_CHAN_REGS 8
49
50/* SATA DMA Register definitions */
51#define AHB_DMA_BRST_DFLT 64 /* 16 data items burst length*/
52
53struct dmareg {
54 u32 low; /* Low bits 0-31 */
55 u32 high; /* High bits 32-63 */
56};
57
58/* DMA Per Channel registers */
59struct dma_chan_regs {
60 struct dmareg sar; /* Source Address */
61 struct dmareg dar; /* Destination address */
62 struct dmareg llp; /* Linked List Pointer */
63 struct dmareg ctl; /* Control */
64 struct dmareg sstat; /* Source Status not implemented in core */
65 struct dmareg dstat; /* Destination Status not implemented in core*/
66 struct dmareg sstatar; /* Source Status Address not impl in core */
67 struct dmareg dstatar; /* Destination Status Address not implemente */
68 struct dmareg cfg; /* Config */
69 struct dmareg sgr; /* Source Gather */
70 struct dmareg dsr; /* Destination Scatter */
71};
72
73/* Generic Interrupt Registers */
74struct dma_interrupt_regs {
75 struct dmareg tfr; /* Transfer Interrupt */
76 struct dmareg block; /* Block Interrupt */
77 struct dmareg srctran; /* Source Transfer Interrupt */
78 struct dmareg dsttran; /* Dest Transfer Interrupt */
79 struct dmareg error; /* Error */
80};
81
82struct ahb_dma_regs {
83 struct dma_chan_regs chan_regs[DMA_NUM_CHAN_REGS];
84 struct dma_interrupt_regs interrupt_raw; /* Raw Interrupt */
85 struct dma_interrupt_regs interrupt_status; /* Interrupt Status */
86 struct dma_interrupt_regs interrupt_mask; /* Interrupt Mask */
87 struct dma_interrupt_regs interrupt_clear; /* Interrupt Clear */
88 struct dmareg statusInt; /* Interrupt combined*/
89 struct dmareg rq_srcreg; /* Src Trans Req */
90 struct dmareg rq_dstreg; /* Dst Trans Req */
91 struct dmareg rq_sgl_srcreg; /* Sngl Src Trans Req*/
92 struct dmareg rq_sgl_dstreg; /* Sngl Dst Trans Req*/
93 struct dmareg rq_lst_srcreg; /* Last Src Trans Req*/
94 struct dmareg rq_lst_dstreg; /* Last Dst Trans Req*/
95 struct dmareg dma_cfg; /* DMA Config */
96 struct dmareg dma_chan_en; /* DMA Channel Enable*/
97 struct dmareg dma_id; /* DMA ID */
98 struct dmareg dma_test; /* DMA Test */
99 struct dmareg res1; /* reserved */
100 struct dmareg res2; /* reserved */
101 /*
102 * DMA Comp Params
103 * Param 6 = dma_param[0], Param 5 = dma_param[1],
104 * Param 4 = dma_param[2] ...
105 */
106 struct dmareg dma_params[6];
107};
108
109/* Data structure for linked list item */
110struct lli {
111 u32 sar; /* Source Address */
112 u32 dar; /* Destination address */
113 u32 llp; /* Linked List Pointer */
114 struct dmareg ctl; /* Control */
115 struct dmareg dstat; /* Destination Status */
116};
117
118enum {
119 SATA_DWC_DMAC_LLI_SZ = (sizeof(struct lli)),
120 SATA_DWC_DMAC_LLI_NUM = 256,
121 SATA_DWC_DMAC_LLI_TBL_SZ = (SATA_DWC_DMAC_LLI_SZ * \
122 SATA_DWC_DMAC_LLI_NUM),
123 SATA_DWC_DMAC_TWIDTH_BYTES = 4,
124 SATA_DWC_DMAC_CTRL_TSIZE_MAX = (0x00000800 * \
125 SATA_DWC_DMAC_TWIDTH_BYTES),
126};
127
128/* DMA Register Operation Bits */
129enum {
130 DMA_EN = 0x00000001, /* Enable AHB DMA */
131 DMA_CTL_LLP_SRCEN = 0x10000000, /* Blk chain enable Src */
132 DMA_CTL_LLP_DSTEN = 0x08000000, /* Blk chain enable Dst */
133};
134
135#define DMA_CTL_BLK_TS(size) ((size) & 0x000000FFF) /* Blk Transfer size */
136#define DMA_CHANNEL(ch) (0x00000001 << (ch)) /* Select channel */
137 /* Enable channel */
138#define DMA_ENABLE_CHAN(ch) ((0x00000001 << (ch)) | \
139 ((0x000000001 << (ch)) << 8))
140 /* Disable channel */
141#define DMA_DISABLE_CHAN(ch) (0x00000000 | ((0x000000001 << (ch)) << 8))
142 /* Transfer Type & Flow Controller */
143#define DMA_CTL_TTFC(type) (((type) & 0x7) << 20)
144#define DMA_CTL_SMS(num) (((num) & 0x3) << 25) /* Src Master Select */
145#define DMA_CTL_DMS(num) (((num) & 0x3) << 23)/* Dst Master Select */
146 /* Src Burst Transaction Length */
147#define DMA_CTL_SRC_MSIZE(size) (((size) & 0x7) << 14)
148 /* Dst Burst Transaction Length */
149#define DMA_CTL_DST_MSIZE(size) (((size) & 0x7) << 11)
150 /* Source Transfer Width */
151#define DMA_CTL_SRC_TRWID(size) (((size) & 0x7) << 4)
152 /* Destination Transfer Width */
153#define DMA_CTL_DST_TRWID(size) (((size) & 0x7) << 1)
154
155/* Assign HW handshaking interface (x) to destination / source peripheral */
156#define DMA_CFG_HW_HS_DEST(int_num) (((int_num) & 0xF) << 11)
157#define DMA_CFG_HW_HS_SRC(int_num) (((int_num) & 0xF) << 7)
158#define DMA_LLP_LMS(addr, master) (((addr) & 0xfffffffc) | (master))
159
160/*
161 * This define is used to set block chaining disabled in the control low
162 * register. It is already in little endian format so it can be &'d dirctly.
163 * It is essentially: cpu_to_le32(~(DMA_CTL_LLP_SRCEN | DMA_CTL_LLP_DSTEN))
164 */
165enum {
166 DMA_CTL_LLP_DISABLE_LE32 = 0xffffffe7,
167 DMA_CTL_TTFC_P2M_DMAC = 0x00000002, /* Per to mem, DMAC cntr */
168 DMA_CTL_TTFC_M2P_PER = 0x00000003, /* Mem to per, peripheral cntr */
169 DMA_CTL_SINC_INC = 0x00000000, /* Source Address Increment */
170 DMA_CTL_SINC_DEC = 0x00000200,
171 DMA_CTL_SINC_NOCHANGE = 0x00000400,
172 DMA_CTL_DINC_INC = 0x00000000, /* Destination Address Increment */
173 DMA_CTL_DINC_DEC = 0x00000080,
174 DMA_CTL_DINC_NOCHANGE = 0x00000100,
175 DMA_CTL_INT_EN = 0x00000001, /* Interrupt Enable */
176
177/* Channel Configuration Register high bits */
178 DMA_CFG_FCMOD_REQ = 0x00000001, /* Flow Control - request based */
179 DMA_CFG_PROTCTL = (0x00000003 << 2),/* Protection Control */
180
181/* Channel Configuration Register low bits */
182 DMA_CFG_RELD_DST = 0x80000000, /* Reload Dest / Src Addr */
183 DMA_CFG_RELD_SRC = 0x40000000,
184 DMA_CFG_HS_SELSRC = 0x00000800, /* Software handshake Src/ Dest */
185 DMA_CFG_HS_SELDST = 0x00000400,
186 DMA_CFG_FIFOEMPTY = (0x00000001 << 9), /* FIFO Empty bit */
187
188/* Channel Linked List Pointer Register */
189 DMA_LLP_AHBMASTER1 = 0, /* List Master Select */
190 DMA_LLP_AHBMASTER2 = 1,
191
192 SATA_DWC_MAX_PORTS = 1,
193
194 SATA_DWC_SCR_OFFSET = 0x24,
195 SATA_DWC_REG_OFFSET = 0x64,
196};
197
198/* DWC SATA Registers */
199struct sata_dwc_regs {
200 u32 fptagr; /* 1st party DMA tag */
201 u32 fpbor; /* 1st party DMA buffer offset */
202 u32 fptcr; /* 1st party DMA Xfr count */
203 u32 dmacr; /* DMA Control */
204 u32 dbtsr; /* DMA Burst Transac size */
205 u32 intpr; /* Interrupt Pending */
206 u32 intmr; /* Interrupt Mask */
207 u32 errmr; /* Error Mask */
208 u32 llcr; /* Link Layer Control */
209 u32 phycr; /* PHY Control */
210 u32 physr; /* PHY Status */
211 u32 rxbistpd; /* Recvd BIST pattern def register */
212 u32 rxbistpd1; /* Recvd BIST data dword1 */
213 u32 rxbistpd2; /* Recvd BIST pattern data dword2 */
214 u32 txbistpd; /* Trans BIST pattern def register */
215 u32 txbistpd1; /* Trans BIST data dword1 */
216 u32 txbistpd2; /* Trans BIST data dword2 */
217 u32 bistcr; /* BIST Control Register */
218 u32 bistfctr; /* BIST FIS Count Register */
219 u32 bistsr; /* BIST Status Register */
220 u32 bistdecr; /* BIST Dword Error count register */
221 u32 res[15]; /* Reserved locations */
222 u32 testr; /* Test Register */
223 u32 versionr; /* Version Register */
224 u32 idr; /* ID Register */
225 u32 unimpl[192]; /* Unimplemented */
226 u32 dmadr[256]; /* FIFO Locations in DMA Mode */
227};
228
229enum {
230 SCR_SCONTROL_DET_ENABLE = 0x00000001,
231 SCR_SSTATUS_DET_PRESENT = 0x00000001,
232 SCR_SERROR_DIAG_X = 0x04000000,
233/* DWC SATA Register Operations */
234 SATA_DWC_TXFIFO_DEPTH = 0x01FF,
235 SATA_DWC_RXFIFO_DEPTH = 0x01FF,
236 SATA_DWC_DMACR_TMOD_TXCHEN = 0x00000004,
237 SATA_DWC_DMACR_TXCHEN = (0x00000001 | SATA_DWC_DMACR_TMOD_TXCHEN),
238 SATA_DWC_DMACR_RXCHEN = (0x00000002 | SATA_DWC_DMACR_TMOD_TXCHEN),
239 SATA_DWC_DMACR_TXRXCH_CLEAR = SATA_DWC_DMACR_TMOD_TXCHEN,
240 SATA_DWC_INTPR_DMAT = 0x00000001,
241 SATA_DWC_INTPR_NEWFP = 0x00000002,
242 SATA_DWC_INTPR_PMABRT = 0x00000004,
243 SATA_DWC_INTPR_ERR = 0x00000008,
244 SATA_DWC_INTPR_NEWBIST = 0x00000010,
245 SATA_DWC_INTPR_IPF = 0x10000000,
246 SATA_DWC_INTMR_DMATM = 0x00000001,
247 SATA_DWC_INTMR_NEWFPM = 0x00000002,
248 SATA_DWC_INTMR_PMABRTM = 0x00000004,
249 SATA_DWC_INTMR_ERRM = 0x00000008,
250 SATA_DWC_INTMR_NEWBISTM = 0x00000010,
251 SATA_DWC_LLCR_SCRAMEN = 0x00000001,
252 SATA_DWC_LLCR_DESCRAMEN = 0x00000002,
253 SATA_DWC_LLCR_RPDEN = 0x00000004,
254/* This is all error bits, zero's are reserved fields. */
255 SATA_DWC_SERROR_ERR_BITS = 0x0FFF0F03
256};
257
258#define SATA_DWC_SCR0_SPD_GET(v) (((v) >> 4) & 0x0000000F)
259#define SATA_DWC_DMACR_TX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_TXCHEN) |\
260 SATA_DWC_DMACR_TMOD_TXCHEN)
261#define SATA_DWC_DMACR_RX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_RXCHEN) |\
262 SATA_DWC_DMACR_TMOD_TXCHEN)
263#define SATA_DWC_DBTSR_MWR(size) (((size)/4) & SATA_DWC_TXFIFO_DEPTH)
264#define SATA_DWC_DBTSR_MRD(size) ((((size)/4) & SATA_DWC_RXFIFO_DEPTH)\
265 << 16)
266struct sata_dwc_device {
267 struct device *dev; /* generic device struct */
268 struct ata_probe_ent *pe; /* ptr to probe-ent */
269 struct ata_host *host;
270 u8 *reg_base;
271 struct sata_dwc_regs *sata_dwc_regs; /* DW Synopsys SATA specific */
272 int irq_dma;
273};
274
275#define SATA_DWC_QCMD_MAX 32
276
277struct sata_dwc_device_port {
278 struct sata_dwc_device *hsdev;
279 int cmd_issued[SATA_DWC_QCMD_MAX];
280 struct lli *llit[SATA_DWC_QCMD_MAX]; /* DMA LLI table */
281 dma_addr_t llit_dma[SATA_DWC_QCMD_MAX];
282 u32 dma_chan[SATA_DWC_QCMD_MAX];
283 int dma_pending[SATA_DWC_QCMD_MAX];
284};
285
286/*
287 * Commonly used DWC SATA driver Macros
288 */
289#define HSDEV_FROM_HOST(host) ((struct sata_dwc_device *)\
290 (host)->private_data)
291#define HSDEV_FROM_AP(ap) ((struct sata_dwc_device *)\
292 (ap)->host->private_data)
293#define HSDEVP_FROM_AP(ap) ((struct sata_dwc_device_port *)\
294 (ap)->private_data)
295#define HSDEV_FROM_QC(qc) ((struct sata_dwc_device *)\
296 (qc)->ap->host->private_data)
297#define HSDEV_FROM_HSDEVP(p) ((struct sata_dwc_device *)\
298 (hsdevp)->hsdev)
299
300enum {
301 SATA_DWC_CMD_ISSUED_NOT = 0,
302 SATA_DWC_CMD_ISSUED_PEND = 1,
303 SATA_DWC_CMD_ISSUED_EXEC = 2,
304 SATA_DWC_CMD_ISSUED_NODATA = 3,
305
306 SATA_DWC_DMA_PENDING_NONE = 0,
307 SATA_DWC_DMA_PENDING_TX = 1,
308 SATA_DWC_DMA_PENDING_RX = 2,
309};
310
311struct sata_dwc_host_priv {
312 void __iomem *scr_addr_sstatus;
313 u32 sata_dwc_sactive_issued ;
314 u32 sata_dwc_sactive_queued ;
315 u32 dma_interrupt_count;
316 struct ahb_dma_regs *sata_dma_regs;
317 struct device *dwc_dev;
318};
319struct sata_dwc_host_priv host_pvt;
320/*
321 * Prototypes
322 */
323static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag);
324static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
325 u32 check_status);
326static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status);
327static void sata_dwc_port_stop(struct ata_port *ap);
328static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag);
329static int dma_dwc_init(struct sata_dwc_device *hsdev, int irq);
330static void dma_dwc_exit(struct sata_dwc_device *hsdev);
331static int dma_dwc_xfer_setup(struct scatterlist *sg, int num_elems,
332 struct lli *lli, dma_addr_t dma_lli,
333 void __iomem *addr, int dir);
334static void dma_dwc_xfer_start(int dma_ch);
335
336static void sata_dwc_tf_dump(struct ata_taskfile *tf)
337{
338 dev_vdbg(host_pvt.dwc_dev, "taskfile cmd: 0x%02x protocol: %s flags:"
339 "0x%lx device: %x\n", tf->command, ata_get_cmd_descript\
340 (tf->protocol), tf->flags, tf->device);
341 dev_vdbg(host_pvt.dwc_dev, "feature: 0x%02x nsect: 0x%x lbal: 0x%x "
342 "lbam: 0x%x lbah: 0x%x\n", tf->feature, tf->nsect, tf->lbal,
343 tf->lbam, tf->lbah);
344 dev_vdbg(host_pvt.dwc_dev, "hob_feature: 0x%02x hob_nsect: 0x%x "
345 "hob_lbal: 0x%x hob_lbam: 0x%x hob_lbah: 0x%x\n",
346 tf->hob_feature, tf->hob_nsect, tf->hob_lbal, tf->hob_lbam,
347 tf->hob_lbah);
348}
349
350/*
351 * Function: get_burst_length_encode
352 * arguments: datalength: length in bytes of data
353 * returns value to be programmed in register corrresponding to data length
354 * This value is effectively the log(base 2) of the length
355 */
356static int get_burst_length_encode(int datalength)
357{
358 int items = datalength >> 2; /* div by 4 to get lword count */
359
360 if (items >= 64)
361 return 5;
362
363 if (items >= 32)
364 return 4;
365
366 if (items >= 16)
367 return 3;
368
369 if (items >= 8)
370 return 2;
371
372 if (items >= 4)
373 return 1;
374
375 return 0;
376}
377
378static void clear_chan_interrupts(int c)
379{
380 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.tfr.low),
381 DMA_CHANNEL(c));
382 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.block.low),
383 DMA_CHANNEL(c));
384 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.srctran.low),
385 DMA_CHANNEL(c));
386 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.dsttran.low),
387 DMA_CHANNEL(c));
388 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.error.low),
389 DMA_CHANNEL(c));
390}
391
392/*
393 * Function: dma_request_channel
394 * arguments: None
395 * returns channel number if available else -1
396 * This function assigns the next available DMA channel from the list to the
397 * requester
398 */
399static int dma_request_channel(void)
400{
401 int i;
402
403 for (i = 0; i < DMA_NUM_CHANS; i++) {
404 if (!(in_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low)) &\
405 DMA_CHANNEL(i)))
406 return i;
407 }
408 dev_err(host_pvt.dwc_dev, "%s NO channel chan_en: 0x%08x\n", __func__,
409 in_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low)));
410 return -1;
411}
412
413/*
414 * Function: dma_dwc_interrupt
415 * arguments: irq, dev_id, pt_regs
416 * returns channel number if available else -1
417 * Interrupt Handler for DW AHB SATA DMA
418 */
419static irqreturn_t dma_dwc_interrupt(int irq, void *hsdev_instance)
420{
421 int chan;
422 u32 tfr_reg, err_reg;
423 unsigned long flags;
424 struct sata_dwc_device *hsdev =
425 (struct sata_dwc_device *)hsdev_instance;
426 struct ata_host *host = (struct ata_host *)hsdev->host;
427 struct ata_port *ap;
428 struct sata_dwc_device_port *hsdevp;
429 u8 tag = 0;
430 unsigned int port = 0;
431
432 spin_lock_irqsave(&host->lock, flags);
433 ap = host->ports[port];
434 hsdevp = HSDEVP_FROM_AP(ap);
435 tag = ap->link.active_tag;
436
437 tfr_reg = in_le32(&(host_pvt.sata_dma_regs->interrupt_status.tfr\
438 .low));
439 err_reg = in_le32(&(host_pvt.sata_dma_regs->interrupt_status.error\
440 .low));
441
442 dev_dbg(ap->dev, "eot=0x%08x err=0x%08x pending=%d active port=%d\n",
443 tfr_reg, err_reg, hsdevp->dma_pending[tag], port);
444
445 for (chan = 0; chan < DMA_NUM_CHANS; chan++) {
446 /* Check for end-of-transfer interrupt. */
447 if (tfr_reg & DMA_CHANNEL(chan)) {
448 /*
449 * Each DMA command produces 2 interrupts. Only
450 * complete the command after both interrupts have been
451 * seen. (See sata_dwc_isr())
452 */
453 host_pvt.dma_interrupt_count++;
454 sata_dwc_clear_dmacr(hsdevp, tag);
455
456 if (hsdevp->dma_pending[tag] ==
457 SATA_DWC_DMA_PENDING_NONE) {
458 dev_err(ap->dev, "DMA not pending eot=0x%08x "
459 "err=0x%08x tag=0x%02x pending=%d\n",
460 tfr_reg, err_reg, tag,
461 hsdevp->dma_pending[tag]);
462 }
463
464 if ((host_pvt.dma_interrupt_count % 2) == 0)
465 sata_dwc_dma_xfer_complete(ap, 1);
466
467 /* Clear the interrupt */
468 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear\
469 .tfr.low),
470 DMA_CHANNEL(chan));
471 }
472
473 /* Check for error interrupt. */
474 if (err_reg & DMA_CHANNEL(chan)) {
475 /* TODO Need error handler ! */
476 dev_err(ap->dev, "error interrupt err_reg=0x%08x\n",
477 err_reg);
478
479 /* Clear the interrupt. */
480 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear\
481 .error.low),
482 DMA_CHANNEL(chan));
483 }
484 }
485 spin_unlock_irqrestore(&host->lock, flags);
486 return IRQ_HANDLED;
487}
488
489/*
490 * Function: dma_request_interrupts
491 * arguments: hsdev
492 * returns status
493 * This function registers ISR for a particular DMA channel interrupt
494 */
495static int dma_request_interrupts(struct sata_dwc_device *hsdev, int irq)
496{
497 int retval = 0;
498 int chan;
499
500 for (chan = 0; chan < DMA_NUM_CHANS; chan++) {
501 /* Unmask error interrupt */
502 out_le32(&(host_pvt.sata_dma_regs)->interrupt_mask.error.low,
503 DMA_ENABLE_CHAN(chan));
504
505 /* Unmask end-of-transfer interrupt */
506 out_le32(&(host_pvt.sata_dma_regs)->interrupt_mask.tfr.low,
507 DMA_ENABLE_CHAN(chan));
508 }
509
510 retval = request_irq(irq, dma_dwc_interrupt, 0, "SATA DMA", hsdev);
511 if (retval) {
512 dev_err(host_pvt.dwc_dev, "%s: could not get IRQ %d\n",
513 __func__, irq);
514 return -ENODEV;
515 }
516
517 /* Mark this interrupt as requested */
518 hsdev->irq_dma = irq;
519 return 0;
520}
521
522/*
523 * Function: map_sg_to_lli
524 * The Synopsis driver has a comment proposing that better performance
525 * is possible by only enabling interrupts on the last item in the linked list.
526 * However, it seems that could be a problem if an error happened on one of the
527 * first items. The transfer would halt, but no error interrupt would occur.
528 * Currently this function sets interrupts enabled for each linked list item:
529 * DMA_CTL_INT_EN.
530 */
531static int map_sg_to_lli(struct scatterlist *sg, int num_elems,
532 struct lli *lli, dma_addr_t dma_lli,
533 void __iomem *dmadr_addr, int dir)
534{
535 int i, idx = 0;
536 int fis_len = 0;
537 dma_addr_t next_llp;
538 int bl;
539
540 dev_dbg(host_pvt.dwc_dev, "%s: sg=%p nelem=%d lli=%p dma_lli=0x%08x"
541 " dmadr=0x%08x\n", __func__, sg, num_elems, lli, (u32)dma_lli,
542 (u32)dmadr_addr);
543
544 bl = get_burst_length_encode(AHB_DMA_BRST_DFLT);
545
546 for (i = 0; i < num_elems; i++, sg++) {
547 u32 addr, offset;
548 u32 sg_len, len;
549
550 addr = (u32) sg_dma_address(sg);
551 sg_len = sg_dma_len(sg);
552
553 dev_dbg(host_pvt.dwc_dev, "%s: elem=%d sg_addr=0x%x sg_len"
554 "=%d\n", __func__, i, addr, sg_len);
555
556 while (sg_len) {
557 if (idx >= SATA_DWC_DMAC_LLI_NUM) {
558 /* The LLI table is not large enough. */
559 dev_err(host_pvt.dwc_dev, "LLI table overrun "
560 "(idx=%d)\n", idx);
561 break;
562 }
563 len = (sg_len > SATA_DWC_DMAC_CTRL_TSIZE_MAX) ?
564 SATA_DWC_DMAC_CTRL_TSIZE_MAX : sg_len;
565
566 offset = addr & 0xffff;
567 if ((offset + sg_len) > 0x10000)
568 len = 0x10000 - offset;
569
570 /*
571 * Make sure a LLI block is not created that will span
572 * 8K max FIS boundary. If the block spans such a FIS
573 * boundary, there is a chance that a DMA burst will
574 * cross that boundary -- this results in an error in
575 * the host controller.
576 */
577 if (fis_len + len > 8192) {
578 dev_dbg(host_pvt.dwc_dev, "SPLITTING: fis_len="
579 "%d(0x%x) len=%d(0x%x)\n", fis_len,
580 fis_len, len, len);
581 len = 8192 - fis_len;
582 fis_len = 0;
583 } else {
584 fis_len += len;
585 }
586 if (fis_len == 8192)
587 fis_len = 0;
588
589 /*
590 * Set DMA addresses and lower half of control register
591 * based on direction.
592 */
593 if (dir == DMA_FROM_DEVICE) {
594 lli[idx].dar = cpu_to_le32(addr);
595 lli[idx].sar = cpu_to_le32((u32)dmadr_addr);
596
597 lli[idx].ctl.low = cpu_to_le32(
598 DMA_CTL_TTFC(DMA_CTL_TTFC_P2M_DMAC) |
599 DMA_CTL_SMS(0) |
600 DMA_CTL_DMS(1) |
601 DMA_CTL_SRC_MSIZE(bl) |
602 DMA_CTL_DST_MSIZE(bl) |
603 DMA_CTL_SINC_NOCHANGE |
604 DMA_CTL_SRC_TRWID(2) |
605 DMA_CTL_DST_TRWID(2) |
606 DMA_CTL_INT_EN |
607 DMA_CTL_LLP_SRCEN |
608 DMA_CTL_LLP_DSTEN);
609 } else { /* DMA_TO_DEVICE */
610 lli[idx].sar = cpu_to_le32(addr);
611 lli[idx].dar = cpu_to_le32((u32)dmadr_addr);
612
613 lli[idx].ctl.low = cpu_to_le32(
614 DMA_CTL_TTFC(DMA_CTL_TTFC_M2P_PER) |
615 DMA_CTL_SMS(1) |
616 DMA_CTL_DMS(0) |
617 DMA_CTL_SRC_MSIZE(bl) |
618 DMA_CTL_DST_MSIZE(bl) |
619 DMA_CTL_DINC_NOCHANGE |
620 DMA_CTL_SRC_TRWID(2) |
621 DMA_CTL_DST_TRWID(2) |
622 DMA_CTL_INT_EN |
623 DMA_CTL_LLP_SRCEN |
624 DMA_CTL_LLP_DSTEN);
625 }
626
627 dev_dbg(host_pvt.dwc_dev, "%s setting ctl.high len: "
628 "0x%08x val: 0x%08x\n", __func__,
629 len, DMA_CTL_BLK_TS(len / 4));
630
631 /* Program the LLI CTL high register */
632 lli[idx].ctl.high = cpu_to_le32(DMA_CTL_BLK_TS\
633 (len / 4));
634
635 /* Program the next pointer. The next pointer must be
636 * the physical address, not the virtual address.
637 */
638 next_llp = (dma_lli + ((idx + 1) * sizeof(struct \
639 lli)));
640
641 /* The last 2 bits encode the list master select. */
642 next_llp = DMA_LLP_LMS(next_llp, DMA_LLP_AHBMASTER2);
643
644 lli[idx].llp = cpu_to_le32(next_llp);
645 idx++;
646 sg_len -= len;
647 addr += len;
648 }
649 }
650
651 /*
652 * The last next ptr has to be zero and the last control low register
653 * has to have LLP_SRC_EN and LLP_DST_EN (linked list pointer source
654 * and destination enable) set back to 0 (disabled.) This is what tells
655 * the core that this is the last item in the linked list.
656 */
657 if (idx) {
658 lli[idx-1].llp = 0x00000000;
659 lli[idx-1].ctl.low &= DMA_CTL_LLP_DISABLE_LE32;
660
661 /* Flush cache to memory */
662 dma_cache_sync(NULL, lli, (sizeof(struct lli) * idx),
663 DMA_BIDIRECTIONAL);
664 }
665
666 return idx;
667}
668
669/*
670 * Function: dma_dwc_xfer_start
671 * arguments: Channel number
672 * Return : None
673 * Enables the DMA channel
674 */
675static void dma_dwc_xfer_start(int dma_ch)
676{
677 /* Enable the DMA channel */
678 out_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low),
679 in_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low)) |
680 DMA_ENABLE_CHAN(dma_ch));
681}
682
683static int dma_dwc_xfer_setup(struct scatterlist *sg, int num_elems,
684 struct lli *lli, dma_addr_t dma_lli,
685 void __iomem *addr, int dir)
686{
687 int dma_ch;
688 int num_lli;
689 /* Acquire DMA channel */
690 dma_ch = dma_request_channel();
691 if (dma_ch == -1) {
692 dev_err(host_pvt.dwc_dev, "%s: dma channel unavailable\n",
693 __func__);
694 return -EAGAIN;
695 }
696
697 /* Convert SG list to linked list of items (LLIs) for AHB DMA */
698 num_lli = map_sg_to_lli(sg, num_elems, lli, dma_lli, addr, dir);
699
700 dev_dbg(host_pvt.dwc_dev, "%s sg: 0x%p, count: %d lli: %p dma_lli:"
701 " 0x%0xlx addr: %p lli count: %d\n", __func__, sg, num_elems,
702 lli, (u32)dma_lli, addr, num_lli);
703
704 clear_chan_interrupts(dma_ch);
705
706 /* Program the CFG register. */
707 out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].cfg.high),
708 DMA_CFG_PROTCTL | DMA_CFG_FCMOD_REQ);
709 out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].cfg.low), 0);
710
711 /* Program the address of the linked list */
712 out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].llp.low),
713 DMA_LLP_LMS(dma_lli, DMA_LLP_AHBMASTER2));
714
715 /* Program the CTL register with src enable / dst enable */
716 out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].ctl.low),
717 DMA_CTL_LLP_SRCEN | DMA_CTL_LLP_DSTEN);
718 return 0;
719}
720
721/*
722 * Function: dma_dwc_exit
723 * arguments: None
724 * returns status
725 * This function exits the SATA DMA driver
726 */
727static void dma_dwc_exit(struct sata_dwc_device *hsdev)
728{
729 dev_dbg(host_pvt.dwc_dev, "%s:\n", __func__);
730 if (host_pvt.sata_dma_regs)
731 iounmap(host_pvt.sata_dma_regs);
732
733 if (hsdev->irq_dma)
734 free_irq(hsdev->irq_dma, hsdev);
735}
736
737/*
738 * Function: dma_dwc_init
739 * arguments: hsdev
740 * returns status
741 * This function initializes the SATA DMA driver
742 */
743static int dma_dwc_init(struct sata_dwc_device *hsdev, int irq)
744{
745 int err;
746
747 err = dma_request_interrupts(hsdev, irq);
748 if (err) {
749 dev_err(host_pvt.dwc_dev, "%s: dma_request_interrupts returns"
750 " %d\n", __func__, err);
751 goto error_out;
752 }
753
754 /* Enabe DMA */
755 out_le32(&(host_pvt.sata_dma_regs->dma_cfg.low), DMA_EN);
756
757 dev_notice(host_pvt.dwc_dev, "DMA initialized\n");
758 dev_dbg(host_pvt.dwc_dev, "SATA DMA registers=0x%p\n", host_pvt.\
759 sata_dma_regs);
760
761 return 0;
762
763error_out:
764 dma_dwc_exit(hsdev);
765
766 return err;
767}
768
769static int sata_dwc_scr_read(struct ata_link *link, unsigned int scr, u32 *val)
770{
771 if (scr > SCR_NOTIFICATION) {
772 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
773 __func__, scr);
774 return -EINVAL;
775 }
776
777 *val = in_le32((void *)link->ap->ioaddr.scr_addr + (scr * 4));
778 dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n",
779 __func__, link->ap->print_id, scr, *val);
780
781 return 0;
782}
783
784static int sata_dwc_scr_write(struct ata_link *link, unsigned int scr, u32 val)
785{
786 dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n",
787 __func__, link->ap->print_id, scr, val);
788 if (scr > SCR_NOTIFICATION) {
789 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
790 __func__, scr);
791 return -EINVAL;
792 }
793 out_le32((void *)link->ap->ioaddr.scr_addr + (scr * 4), val);
794
795 return 0;
796}
797
798static u32 core_scr_read(unsigned int scr)
799{
800 return in_le32((void __iomem *)(host_pvt.scr_addr_sstatus) +\
801 (scr * 4));
802}
803
804static void core_scr_write(unsigned int scr, u32 val)
805{
806 out_le32((void __iomem *)(host_pvt.scr_addr_sstatus) + (scr * 4),
807 val);
808}
809
810static void clear_serror(void)
811{
812 u32 val;
813 val = core_scr_read(SCR_ERROR);
814 core_scr_write(SCR_ERROR, val);
815
816}
817
818static void clear_interrupt_bit(struct sata_dwc_device *hsdev, u32 bit)
819{
820 out_le32(&hsdev->sata_dwc_regs->intpr,
821 in_le32(&hsdev->sata_dwc_regs->intpr));
822}
823
824static u32 qcmd_tag_to_mask(u8 tag)
825{
826 return 0x00000001 << (tag & 0x1f);
827}
828
829/* See ahci.c */
830static void sata_dwc_error_intr(struct ata_port *ap,
831 struct sata_dwc_device *hsdev, uint intpr)
832{
833 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
834 struct ata_eh_info *ehi = &ap->link.eh_info;
835 unsigned int err_mask = 0, action = 0;
836 struct ata_queued_cmd *qc;
837 u32 serror;
838 u8 status, tag;
839 u32 err_reg;
840
841 ata_ehi_clear_desc(ehi);
842
843 serror = core_scr_read(SCR_ERROR);
844 status = ap->ops->sff_check_status(ap);
845
846 err_reg = in_le32(&(host_pvt.sata_dma_regs->interrupt_status.error.\
847 low));
848 tag = ap->link.active_tag;
849
850 dev_err(ap->dev, "%s SCR_ERROR=0x%08x intpr=0x%08x status=0x%08x "
851 "dma_intp=%d pending=%d issued=%d dma_err_status=0x%08x\n",
852 __func__, serror, intpr, status, host_pvt.dma_interrupt_count,
853 hsdevp->dma_pending[tag], hsdevp->cmd_issued[tag], err_reg);
854
855 /* Clear error register and interrupt bit */
856 clear_serror();
857 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_ERR);
858
859 /* This is the only error happening now. TODO check for exact error */
860
861 err_mask |= AC_ERR_HOST_BUS;
862 action |= ATA_EH_RESET;
863
864 /* Pass this on to EH */
865 ehi->serror |= serror;
866 ehi->action |= action;
867
868 qc = ata_qc_from_tag(ap, tag);
869 if (qc)
870 qc->err_mask |= err_mask;
871 else
872 ehi->err_mask |= err_mask;
873
874 ata_port_abort(ap);
875}
876
877/*
878 * Function : sata_dwc_isr
879 * arguments : irq, void *dev_instance, struct pt_regs *regs
880 * Return value : irqreturn_t - status of IRQ
881 * This Interrupt handler called via port ops registered function.
882 * .irq_handler = sata_dwc_isr
883 */
884static irqreturn_t sata_dwc_isr(int irq, void *dev_instance)
885{
886 struct ata_host *host = (struct ata_host *)dev_instance;
887 struct sata_dwc_device *hsdev = HSDEV_FROM_HOST(host);
888 struct ata_port *ap;
889 struct ata_queued_cmd *qc;
890 unsigned long flags;
891 u8 status, tag;
892 int handled, num_processed, port = 0;
893 uint intpr, sactive, sactive2, tag_mask;
894 struct sata_dwc_device_port *hsdevp;
895 host_pvt.sata_dwc_sactive_issued = 0;
896
897 spin_lock_irqsave(&host->lock, flags);
898
899 /* Read the interrupt register */
900 intpr = in_le32(&hsdev->sata_dwc_regs->intpr);
901
902 ap = host->ports[port];
903 hsdevp = HSDEVP_FROM_AP(ap);
904
905 dev_dbg(ap->dev, "%s intpr=0x%08x active_tag=%d\n", __func__, intpr,
906 ap->link.active_tag);
907
908 /* Check for error interrupt */
909 if (intpr & SATA_DWC_INTPR_ERR) {
910 sata_dwc_error_intr(ap, hsdev, intpr);
911 handled = 1;
912 goto DONE;
913 }
914
915 /* Check for DMA SETUP FIS (FP DMA) interrupt */
916 if (intpr & SATA_DWC_INTPR_NEWFP) {
917 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_NEWFP);
918
919 tag = (u8)(in_le32(&hsdev->sata_dwc_regs->fptagr));
920 dev_dbg(ap->dev, "%s: NEWFP tag=%d\n", __func__, tag);
921 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_PEND)
922 dev_warn(ap->dev, "CMD tag=%d not pending?\n", tag);
923
924 host_pvt.sata_dwc_sactive_issued |= qcmd_tag_to_mask(tag);
925
926 qc = ata_qc_from_tag(ap, tag);
927 /*
928 * Start FP DMA for NCQ command. At this point the tag is the
929 * active tag. It is the tag that matches the command about to
930 * be completed.
931 */
932 qc->ap->link.active_tag = tag;
933 sata_dwc_bmdma_start_by_tag(qc, tag);
934
935 handled = 1;
936 goto DONE;
937 }
938 sactive = core_scr_read(SCR_ACTIVE);
939 tag_mask = (host_pvt.sata_dwc_sactive_issued | sactive) ^ sactive;
940
941 /* If no sactive issued and tag_mask is zero then this is not NCQ */
942 if (host_pvt.sata_dwc_sactive_issued == 0 && tag_mask == 0) {
943 if (ap->link.active_tag == ATA_TAG_POISON)
944 tag = 0;
945 else
946 tag = ap->link.active_tag;
947 qc = ata_qc_from_tag(ap, tag);
948
949 /* DEV interrupt w/ no active qc? */
950 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
951 dev_err(ap->dev, "%s interrupt with no active qc "
952 "qc=%p\n", __func__, qc);
953 ap->ops->sff_check_status(ap);
954 handled = 1;
955 goto DONE;
956 }
957 status = ap->ops->sff_check_status(ap);
958
959 qc->ap->link.active_tag = tag;
960 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
961
962 if (status & ATA_ERR) {
963 dev_dbg(ap->dev, "interrupt ATA_ERR (0x%x)\n", status);
964 sata_dwc_qc_complete(ap, qc, 1);
965 handled = 1;
966 goto DONE;
967 }
968
969 dev_dbg(ap->dev, "%s non-NCQ cmd interrupt, protocol: %s\n",
970 __func__, ata_get_cmd_descript(qc->tf.protocol));
971DRVSTILLBUSY:
972 if (ata_is_dma(qc->tf.protocol)) {
973 /*
974 * Each DMA transaction produces 2 interrupts. The DMAC
975 * transfer complete interrupt and the SATA controller
976 * operation done interrupt. The command should be
977 * completed only after both interrupts are seen.
978 */
979 host_pvt.dma_interrupt_count++;
980 if (hsdevp->dma_pending[tag] == \
981 SATA_DWC_DMA_PENDING_NONE) {
982 dev_err(ap->dev, "%s: DMA not pending "
983 "intpr=0x%08x status=0x%08x pending"
984 "=%d\n", __func__, intpr, status,
985 hsdevp->dma_pending[tag]);
986 }
987
988 if ((host_pvt.dma_interrupt_count % 2) == 0)
989 sata_dwc_dma_xfer_complete(ap, 1);
990 } else if (ata_is_pio(qc->tf.protocol)) {
991 ata_sff_hsm_move(ap, qc, status, 0);
992 handled = 1;
993 goto DONE;
994 } else {
995 if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
996 goto DRVSTILLBUSY;
997 }
998
999 handled = 1;
1000 goto DONE;
1001 }
1002
1003 /*
1004 * This is a NCQ command. At this point we need to figure out for which
1005 * tags we have gotten a completion interrupt. One interrupt may serve
1006 * as completion for more than one operation when commands are queued
1007 * (NCQ). We need to process each completed command.
1008 */
1009
1010 /* process completed commands */
1011 sactive = core_scr_read(SCR_ACTIVE);
1012 tag_mask = (host_pvt.sata_dwc_sactive_issued | sactive) ^ sactive;
1013
1014 if (sactive != 0 || (host_pvt.sata_dwc_sactive_issued) > 1 || \
1015 tag_mask > 1) {
1016 dev_dbg(ap->dev, "%s NCQ:sactive=0x%08x sactive_issued=0x%08x"
1017 "tag_mask=0x%08x\n", __func__, sactive,
1018 host_pvt.sata_dwc_sactive_issued, tag_mask);
1019 }
1020
1021 if ((tag_mask | (host_pvt.sata_dwc_sactive_issued)) != \
1022 (host_pvt.sata_dwc_sactive_issued)) {
1023 dev_warn(ap->dev, "Bad tag mask? sactive=0x%08x "
1024 "(host_pvt.sata_dwc_sactive_issued)=0x%08x tag_mask"
1025 "=0x%08x\n", sactive, host_pvt.sata_dwc_sactive_issued,
1026 tag_mask);
1027 }
1028
1029 /* read just to clear ... not bad if currently still busy */
1030 status = ap->ops->sff_check_status(ap);
1031 dev_dbg(ap->dev, "%s ATA status register=0x%x\n", __func__, status);
1032
1033 tag = 0;
1034 num_processed = 0;
1035 while (tag_mask) {
1036 num_processed++;
1037 while (!(tag_mask & 0x00000001)) {
1038 tag++;
1039 tag_mask <<= 1;
1040 }
1041
1042 tag_mask &= (~0x00000001);
1043 qc = ata_qc_from_tag(ap, tag);
1044
1045 /* To be picked up by completion functions */
1046 qc->ap->link.active_tag = tag;
1047 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
1048
1049 /* Let libata/scsi layers handle error */
1050 if (status & ATA_ERR) {
1051 dev_dbg(ap->dev, "%s ATA_ERR (0x%x)\n", __func__,
1052 status);
1053 sata_dwc_qc_complete(ap, qc, 1);
1054 handled = 1;
1055 goto DONE;
1056 }
1057
1058 /* Process completed command */
1059 dev_dbg(ap->dev, "%s NCQ command, protocol: %s\n", __func__,
1060 ata_get_cmd_descript(qc->tf.protocol));
1061 if (ata_is_dma(qc->tf.protocol)) {
1062 host_pvt.dma_interrupt_count++;
1063 if (hsdevp->dma_pending[tag] == \
1064 SATA_DWC_DMA_PENDING_NONE)
1065 dev_warn(ap->dev, "%s: DMA not pending?\n",
1066 __func__);
1067 if ((host_pvt.dma_interrupt_count % 2) == 0)
1068 sata_dwc_dma_xfer_complete(ap, 1);
1069 } else {
1070 if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
1071 goto STILLBUSY;
1072 }
1073 continue;
1074
1075STILLBUSY:
1076 ap->stats.idle_irq++;
1077 dev_warn(ap->dev, "STILL BUSY IRQ ata%d: irq trap\n",
1078 ap->print_id);
1079 } /* while tag_mask */
1080
1081 /*
1082 * Check to see if any commands completed while we were processing our
1083 * initial set of completed commands (read status clears interrupts,
1084 * so we might miss a completed command interrupt if one came in while
1085 * we were processing --we read status as part of processing a completed
1086 * command).
1087 */
1088 sactive2 = core_scr_read(SCR_ACTIVE);
1089 if (sactive2 != sactive) {
1090 dev_dbg(ap->dev, "More completed - sactive=0x%x sactive2"
1091 "=0x%x\n", sactive, sactive2);
1092 }
1093 handled = 1;
1094
1095DONE:
1096 spin_unlock_irqrestore(&host->lock, flags);
1097 return IRQ_RETVAL(handled);
1098}
1099
1100static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag)
1101{
1102 struct sata_dwc_device *hsdev = HSDEV_FROM_HSDEVP(hsdevp);
1103
1104 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX) {
1105 out_le32(&(hsdev->sata_dwc_regs->dmacr),
1106 SATA_DWC_DMACR_RX_CLEAR(
1107 in_le32(&(hsdev->sata_dwc_regs->dmacr))));
1108 } else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX) {
1109 out_le32(&(hsdev->sata_dwc_regs->dmacr),
1110 SATA_DWC_DMACR_TX_CLEAR(
1111 in_le32(&(hsdev->sata_dwc_regs->dmacr))));
1112 } else {
1113 /*
1114 * This should not happen, it indicates the driver is out of
1115 * sync. If it does happen, clear dmacr anyway.
1116 */
1117 dev_err(host_pvt.dwc_dev, "%s DMA protocol RX and"
1118 "TX DMA not pending tag=0x%02x pending=%d"
1119 " dmacr: 0x%08x\n", __func__, tag,
1120 hsdevp->dma_pending[tag],
1121 in_le32(&(hsdev->sata_dwc_regs->dmacr)));
1122 out_le32(&(hsdev->sata_dwc_regs->dmacr),
1123 SATA_DWC_DMACR_TXRXCH_CLEAR);
1124 }
1125}
1126
1127static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status)
1128{
1129 struct ata_queued_cmd *qc;
1130 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1131 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
1132 u8 tag = 0;
1133
1134 tag = ap->link.active_tag;
1135 qc = ata_qc_from_tag(ap, tag);
1136 if (!qc) {
1137 dev_err(ap->dev, "failed to get qc");
1138 return;
1139 }
1140
1141#ifdef DEBUG_NCQ
1142 if (tag > 0) {
1143 dev_info(ap->dev, "%s tag=%u cmd=0x%02x dma dir=%s proto=%s "
1144 "dmacr=0x%08x\n", __func__, qc->tag, qc->tf.command,
1145 ata_get_cmd_descript(qc->dma_dir),
1146 ata_get_cmd_descript(qc->tf.protocol),
1147 in_le32(&(hsdev->sata_dwc_regs->dmacr)));
1148 }
1149#endif
1150
1151 if (ata_is_dma(qc->tf.protocol)) {
1152 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) {
1153 dev_err(ap->dev, "%s DMA protocol RX and TX DMA not "
1154 "pending dmacr: 0x%08x\n", __func__,
1155 in_le32(&(hsdev->sata_dwc_regs->dmacr)));
1156 }
1157
1158 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_NONE;
1159 sata_dwc_qc_complete(ap, qc, check_status);
1160 ap->link.active_tag = ATA_TAG_POISON;
1161 } else {
1162 sata_dwc_qc_complete(ap, qc, check_status);
1163 }
1164}
1165
1166static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
1167 u32 check_status)
1168{
1169 u8 status = 0;
1170 u32 mask = 0x0;
1171 u8 tag = qc->tag;
1172 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1173 host_pvt.sata_dwc_sactive_queued = 0;
1174 dev_dbg(ap->dev, "%s checkstatus? %x\n", __func__, check_status);
1175
1176 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX)
1177 dev_err(ap->dev, "TX DMA PENDING\n");
1178 else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX)
1179 dev_err(ap->dev, "RX DMA PENDING\n");
1180 dev_dbg(ap->dev, "QC complete cmd=0x%02x status=0x%02x ata%u:"
1181 " protocol=%d\n", qc->tf.command, status, ap->print_id,
1182 qc->tf.protocol);
1183
1184 /* clear active bit */
1185 mask = (~(qcmd_tag_to_mask(tag)));
1186 host_pvt.sata_dwc_sactive_queued = (host_pvt.sata_dwc_sactive_queued) \
1187 & mask;
1188 host_pvt.sata_dwc_sactive_issued = (host_pvt.sata_dwc_sactive_issued) \
1189 & mask;
1190 ata_qc_complete(qc);
1191 return 0;
1192}
1193
1194static void sata_dwc_enable_interrupts(struct sata_dwc_device *hsdev)
1195{
1196 /* Enable selective interrupts by setting the interrupt maskregister*/
1197 out_le32(&hsdev->sata_dwc_regs->intmr,
1198 SATA_DWC_INTMR_ERRM |
1199 SATA_DWC_INTMR_NEWFPM |
1200 SATA_DWC_INTMR_PMABRTM |
1201 SATA_DWC_INTMR_DMATM);
1202 /*
1203 * Unmask the error bits that should trigger an error interrupt by
1204 * setting the error mask register.
1205 */
1206 out_le32(&hsdev->sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS);
1207
1208 dev_dbg(host_pvt.dwc_dev, "%s: INTMR = 0x%08x, ERRMR = 0x%08x\n",
1209 __func__, in_le32(&hsdev->sata_dwc_regs->intmr),
1210 in_le32(&hsdev->sata_dwc_regs->errmr));
1211}
1212
1213static void sata_dwc_setup_port(struct ata_ioports *port, unsigned long base)
1214{
1215 port->cmd_addr = (void *)base + 0x00;
1216 port->data_addr = (void *)base + 0x00;
1217
1218 port->error_addr = (void *)base + 0x04;
1219 port->feature_addr = (void *)base + 0x04;
1220
1221 port->nsect_addr = (void *)base + 0x08;
1222
1223 port->lbal_addr = (void *)base + 0x0c;
1224 port->lbam_addr = (void *)base + 0x10;
1225 port->lbah_addr = (void *)base + 0x14;
1226
1227 port->device_addr = (void *)base + 0x18;
1228 port->command_addr = (void *)base + 0x1c;
1229 port->status_addr = (void *)base + 0x1c;
1230
1231 port->altstatus_addr = (void *)base + 0x20;
1232 port->ctl_addr = (void *)base + 0x20;
1233}
1234
1235/*
1236 * Function : sata_dwc_port_start
1237 * arguments : struct ata_ioports *port
1238 * Return value : returns 0 if success, error code otherwise
1239 * This function allocates the scatter gather LLI table for AHB DMA
1240 */
1241static int sata_dwc_port_start(struct ata_port *ap)
1242{
1243 int err = 0;
1244 struct sata_dwc_device *hsdev;
1245 struct sata_dwc_device_port *hsdevp = NULL;
1246 struct device *pdev;
1247 int i;
1248
1249 hsdev = HSDEV_FROM_AP(ap);
1250
1251 dev_dbg(ap->dev, "%s: port_no=%d\n", __func__, ap->port_no);
1252
1253 hsdev->host = ap->host;
1254 pdev = ap->host->dev;
1255 if (!pdev) {
1256 dev_err(ap->dev, "%s: no ap->host->dev\n", __func__);
1257 err = -ENODEV;
1258 goto CLEANUP;
1259 }
1260
1261 /* Allocate Port Struct */
1262 hsdevp = kzalloc(sizeof(*hsdevp), GFP_KERNEL);
1263 if (!hsdevp) {
1264 dev_err(ap->dev, "%s: kmalloc failed for hsdevp\n", __func__);
1265 err = -ENOMEM;
1266 goto CLEANUP;
1267 }
1268 hsdevp->hsdev = hsdev;
1269
1270 for (i = 0; i < SATA_DWC_QCMD_MAX; i++)
1271 hsdevp->cmd_issued[i] = SATA_DWC_CMD_ISSUED_NOT;
1272
1273 ap->bmdma_prd = 0; /* set these so libata doesn't use them */
1274 ap->bmdma_prd_dma = 0;
1275
1276 /*
1277 * DMA - Assign scatter gather LLI table. We can't use the libata
1278 * version since it's PRD is IDE PCI specific.
1279 */
1280 for (i = 0; i < SATA_DWC_QCMD_MAX; i++) {
1281 hsdevp->llit[i] = dma_alloc_coherent(pdev,
1282 SATA_DWC_DMAC_LLI_TBL_SZ,
1283 &(hsdevp->llit_dma[i]),
1284 GFP_ATOMIC);
1285 if (!hsdevp->llit[i]) {
1286 dev_err(ap->dev, "%s: dma_alloc_coherent failed\n",
1287 __func__);
1288 err = -ENOMEM;
1289 goto CLEANUP;
1290 }
1291 }
1292
1293 if (ap->port_no == 0) {
1294 dev_dbg(ap->dev, "%s: clearing TXCHEN, RXCHEN in DMAC\n",
1295 __func__);
1296 out_le32(&hsdev->sata_dwc_regs->dmacr,
1297 SATA_DWC_DMACR_TXRXCH_CLEAR);
1298
1299 dev_dbg(ap->dev, "%s: setting burst size in DBTSR\n",
1300 __func__);
1301 out_le32(&hsdev->sata_dwc_regs->dbtsr,
1302 (SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
1303 SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT)));
1304 }
1305
1306 /* Clear any error bits before libata starts issuing commands */
1307 clear_serror();
1308 ap->private_data = hsdevp;
1309
1310CLEANUP:
1311 if (err) {
1312 sata_dwc_port_stop(ap);
1313 dev_dbg(ap->dev, "%s: fail\n", __func__);
1314 } else {
1315 dev_dbg(ap->dev, "%s: done\n", __func__);
1316 }
1317
1318 return err;
1319}
1320
1321static void sata_dwc_port_stop(struct ata_port *ap)
1322{
1323 int i;
1324 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
1325 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1326
1327 dev_dbg(ap->dev, "%s: ap->id = %d\n", __func__, ap->print_id);
1328
1329 if (hsdevp && hsdev) {
1330 /* deallocate LLI table */
1331 for (i = 0; i < SATA_DWC_QCMD_MAX; i++) {
1332 dma_free_coherent(ap->host->dev,
1333 SATA_DWC_DMAC_LLI_TBL_SZ,
1334 hsdevp->llit[i], hsdevp->llit_dma[i]);
1335 }
1336
1337 kfree(hsdevp);
1338 }
1339 ap->private_data = NULL;
1340}
1341
1342/*
1343 * Function : sata_dwc_exec_command_by_tag
1344 * arguments : ata_port *ap, ata_taskfile *tf, u8 tag, u32 cmd_issued
1345 * Return value : None
1346 * This function keeps track of individual command tag ids and calls
1347 * ata_exec_command in libata
1348 */
1349static void sata_dwc_exec_command_by_tag(struct ata_port *ap,
1350 struct ata_taskfile *tf,
1351 u8 tag, u32 cmd_issued)
1352{
1353 unsigned long flags;
1354 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1355
1356 dev_dbg(ap->dev, "%s cmd(0x%02x): %s tag=%d\n", __func__, tf->command,
1357 ata_get_cmd_descript(tf), tag);
1358
1359 spin_lock_irqsave(&ap->host->lock, flags);
1360 hsdevp->cmd_issued[tag] = cmd_issued;
1361 spin_unlock_irqrestore(&ap->host->lock, flags);
1362 /*
1363 * Clear SError before executing a new command.
1364 * sata_dwc_scr_write and read can not be used here. Clearing the PM
1365 * managed SError register for the disk needs to be done before the
1366 * task file is loaded.
1367 */
1368 clear_serror();
1369 ata_sff_exec_command(ap, tf);
1370}
1371
1372static void sata_dwc_bmdma_setup_by_tag(struct ata_queued_cmd *qc, u8 tag)
1373{
1374 sata_dwc_exec_command_by_tag(qc->ap, &qc->tf, tag,
1375 SATA_DWC_CMD_ISSUED_PEND);
1376}
1377
1378static void sata_dwc_bmdma_setup(struct ata_queued_cmd *qc)
1379{
1380 u8 tag = qc->tag;
1381
1382 if (ata_is_ncq(qc->tf.protocol)) {
1383 dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
1384 __func__, qc->ap->link.sactive, tag);
1385 } else {
1386 tag = 0;
1387 }
1388 sata_dwc_bmdma_setup_by_tag(qc, tag);
1389}
1390
1391static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag)
1392{
1393 int start_dma;
1394 u32 reg, dma_chan;
1395 struct sata_dwc_device *hsdev = HSDEV_FROM_QC(qc);
1396 struct ata_port *ap = qc->ap;
1397 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1398 int dir = qc->dma_dir;
1399 dma_chan = hsdevp->dma_chan[tag];
1400
1401 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_NOT) {
1402 start_dma = 1;
1403 if (dir == DMA_TO_DEVICE)
1404 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_TX;
1405 else
1406 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_RX;
1407 } else {
1408 dev_err(ap->dev, "%s: Command not pending cmd_issued=%d "
1409 "(tag=%d) DMA NOT started\n", __func__,
1410 hsdevp->cmd_issued[tag], tag);
1411 start_dma = 0;
1412 }
1413
1414 dev_dbg(ap->dev, "%s qc=%p tag: %x cmd: 0x%02x dma_dir: %s "
1415 "start_dma? %x\n", __func__, qc, tag, qc->tf.command,
1416 ata_get_cmd_descript(qc->dma_dir), start_dma);
1417 sata_dwc_tf_dump(&(qc->tf));
1418
1419 if (start_dma) {
1420 reg = core_scr_read(SCR_ERROR);
1421 if (reg & SATA_DWC_SERROR_ERR_BITS) {
1422 dev_err(ap->dev, "%s: ****** SError=0x%08x ******\n",
1423 __func__, reg);
1424 }
1425
1426 if (dir == DMA_TO_DEVICE)
1427 out_le32(&hsdev->sata_dwc_regs->dmacr,
1428 SATA_DWC_DMACR_TXCHEN);
1429 else
1430 out_le32(&hsdev->sata_dwc_regs->dmacr,
1431 SATA_DWC_DMACR_RXCHEN);
1432
1433 /* Enable AHB DMA transfer on the specified channel */
1434 dma_dwc_xfer_start(dma_chan);
1435 }
1436}
1437
1438static void sata_dwc_bmdma_start(struct ata_queued_cmd *qc)
1439{
1440 u8 tag = qc->tag;
1441
1442 if (ata_is_ncq(qc->tf.protocol)) {
1443 dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
1444 __func__, qc->ap->link.sactive, tag);
1445 } else {
1446 tag = 0;
1447 }
1448 dev_dbg(qc->ap->dev, "%s\n", __func__);
1449 sata_dwc_bmdma_start_by_tag(qc, tag);
1450}
1451
1452/*
1453 * Function : sata_dwc_qc_prep_by_tag
1454 * arguments : ata_queued_cmd *qc, u8 tag
1455 * Return value : None
1456 * qc_prep for a particular queued command based on tag
1457 */
1458static void sata_dwc_qc_prep_by_tag(struct ata_queued_cmd *qc, u8 tag)
1459{
1460 struct scatterlist *sg = qc->sg;
1461 struct ata_port *ap = qc->ap;
1462 u32 dma_chan;
1463 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
1464 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1465 int err;
1466
1467 dev_dbg(ap->dev, "%s: port=%d dma dir=%s n_elem=%d\n",
1468 __func__, ap->port_no, ata_get_cmd_descript(qc->dma_dir),
1469 qc->n_elem);
1470
1471 dma_chan = dma_dwc_xfer_setup(sg, qc->n_elem, hsdevp->llit[tag],
1472 hsdevp->llit_dma[tag],
1473 (void *__iomem)(&hsdev->sata_dwc_regs->\
1474 dmadr), qc->dma_dir);
1475 if (dma_chan < 0) {
1476 dev_err(ap->dev, "%s: dma_dwc_xfer_setup returns err %d\n",
1477 __func__, err);
1478 return;
1479 }
1480 hsdevp->dma_chan[tag] = dma_chan;
1481}
1482
1483static unsigned int sata_dwc_qc_issue(struct ata_queued_cmd *qc)
1484{
1485 u32 sactive;
1486 u8 tag = qc->tag;
1487 struct ata_port *ap = qc->ap;
1488
1489#ifdef DEBUG_NCQ
1490 if (qc->tag > 0 || ap->link.sactive > 1)
1491 dev_info(ap->dev, "%s ap id=%d cmd(0x%02x)=%s qc tag=%d "
1492 "prot=%s ap active_tag=0x%08x ap sactive=0x%08x\n",
1493 __func__, ap->print_id, qc->tf.command,
1494 ata_get_cmd_descript(&qc->tf),
1495 qc->tag, ata_get_cmd_descript(qc->tf.protocol),
1496 ap->link.active_tag, ap->link.sactive);
1497#endif
1498
1499 if (!ata_is_ncq(qc->tf.protocol))
1500 tag = 0;
1501 sata_dwc_qc_prep_by_tag(qc, tag);
1502
1503 if (ata_is_ncq(qc->tf.protocol)) {
1504 sactive = core_scr_read(SCR_ACTIVE);
1505 sactive |= (0x00000001 << tag);
1506 core_scr_write(SCR_ACTIVE, sactive);
1507
1508 dev_dbg(qc->ap->dev, "%s: tag=%d ap->link.sactive = 0x%08x "
1509 "sactive=0x%08x\n", __func__, tag, qc->ap->link.sactive,
1510 sactive);
1511
1512 ap->ops->sff_tf_load(ap, &qc->tf);
1513 sata_dwc_exec_command_by_tag(ap, &qc->tf, qc->tag,
1514 SATA_DWC_CMD_ISSUED_PEND);
1515 } else {
1516 ata_sff_qc_issue(qc);
1517 }
1518 return 0;
1519}
1520
1521/*
1522 * Function : sata_dwc_qc_prep
1523 * arguments : ata_queued_cmd *qc
1524 * Return value : None
1525 * qc_prep for a particular queued command
1526 */
1527
1528static void sata_dwc_qc_prep(struct ata_queued_cmd *qc)
1529{
1530 if ((qc->dma_dir == DMA_NONE) || (qc->tf.protocol == ATA_PROT_PIO))
1531 return;
1532
1533#ifdef DEBUG_NCQ
1534 if (qc->tag > 0)
1535 dev_info(qc->ap->dev, "%s: qc->tag=%d ap->active_tag=0x%08x\n",
1536 __func__, tag, qc->ap->link.active_tag);
1537
1538 return ;
1539#endif
1540}
1541
1542static void sata_dwc_error_handler(struct ata_port *ap)
1543{
1544 ap->link.flags |= ATA_LFLAG_NO_HRST;
1545 ata_sff_error_handler(ap);
1546}
1547
1548/*
1549 * scsi mid-layer and libata interface structures
1550 */
1551static struct scsi_host_template sata_dwc_sht = {
1552 ATA_NCQ_SHT(DRV_NAME),
1553 /*
1554 * test-only: Currently this driver doesn't handle NCQ
1555 * correctly. We enable NCQ but set the queue depth to a
1556 * max of 1. This will get fixed in in a future release.
1557 */
1558 .sg_tablesize = LIBATA_MAX_PRD,
1559 .can_queue = ATA_DEF_QUEUE, /* ATA_MAX_QUEUE */
1560 .dma_boundary = ATA_DMA_BOUNDARY,
1561};
1562
1563static struct ata_port_operations sata_dwc_ops = {
1564 .inherits = &ata_sff_port_ops,
1565
1566 .error_handler = sata_dwc_error_handler,
1567
1568 .qc_prep = sata_dwc_qc_prep,
1569 .qc_issue = sata_dwc_qc_issue,
1570
1571 .scr_read = sata_dwc_scr_read,
1572 .scr_write = sata_dwc_scr_write,
1573
1574 .port_start = sata_dwc_port_start,
1575 .port_stop = sata_dwc_port_stop,
1576
1577 .bmdma_setup = sata_dwc_bmdma_setup,
1578 .bmdma_start = sata_dwc_bmdma_start,
1579};
1580
1581static const struct ata_port_info sata_dwc_port_info[] = {
1582 {
1583 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
1584 ATA_FLAG_MMIO | ATA_FLAG_NCQ,
1585 .pio_mask = 0x1f, /* pio 0-4 */
1586 .udma_mask = ATA_UDMA6,
1587 .port_ops = &sata_dwc_ops,
1588 },
1589};
1590
1591static int sata_dwc_probe(struct of_device *ofdev,
1592 const struct of_device_id *match)
1593{
1594 struct sata_dwc_device *hsdev;
1595 u32 idr, versionr;
1596 char *ver = (char *)&versionr;
1597 u8 *base = NULL;
1598 int err = 0;
1599 int irq, rc;
1600 struct ata_host *host;
1601 struct ata_port_info pi = sata_dwc_port_info[0];
1602 const struct ata_port_info *ppi[] = { &pi, NULL };
1603
1604 /* Allocate DWC SATA device */
1605 hsdev = kmalloc(sizeof(*hsdev), GFP_KERNEL);
1606 if (hsdev == NULL) {
1607 dev_err(&ofdev->dev, "kmalloc failed for hsdev\n");
1608 err = -ENOMEM;
1609 goto error_out;
1610 }
1611 memset(hsdev, 0, sizeof(*hsdev));
1612
1613 /* Ioremap SATA registers */
1614 base = of_iomap(ofdev->dev.of_node, 0);
1615 if (!base) {
1616 dev_err(&ofdev->dev, "ioremap failed for SATA register"
1617 " address\n");
1618 err = -ENODEV;
1619 goto error_out;
1620 }
1621 hsdev->reg_base = base;
1622 dev_dbg(&ofdev->dev, "ioremap done for SATA register address\n");
1623
1624 /* Synopsys DWC SATA specific Registers */
1625 hsdev->sata_dwc_regs = (void *__iomem)(base + SATA_DWC_REG_OFFSET);
1626
1627 /* Allocate and fill host */
1628 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_DWC_MAX_PORTS);
1629 if (!host) {
1630 dev_err(&ofdev->dev, "ata_host_alloc_pinfo failed\n");
1631 err = -ENOMEM;
1632 goto error_out;
1633 }
1634
1635 host->private_data = hsdev;
1636
1637 /* Setup port */
1638 host->ports[0]->ioaddr.cmd_addr = base;
1639 host->ports[0]->ioaddr.scr_addr = base + SATA_DWC_SCR_OFFSET;
1640 host_pvt.scr_addr_sstatus = base + SATA_DWC_SCR_OFFSET;
1641 sata_dwc_setup_port(&host->ports[0]->ioaddr, (unsigned long)base);
1642
1643 /* Read the ID and Version Registers */
1644 idr = in_le32(&hsdev->sata_dwc_regs->idr);
1645 versionr = in_le32(&hsdev->sata_dwc_regs->versionr);
1646 dev_notice(&ofdev->dev, "id %d, controller version %c.%c%c\n",
1647 idr, ver[0], ver[1], ver[2]);
1648
1649 /* Get SATA DMA interrupt number */
1650 irq = irq_of_parse_and_map(ofdev->dev.of_node, 1);
1651 if (irq == NO_IRQ) {
1652 dev_err(&ofdev->dev, "no SATA DMA irq\n");
1653 err = -ENODEV;
1654 goto error_out;
1655 }
1656
1657 /* Get physical SATA DMA register base address */
1658 host_pvt.sata_dma_regs = of_iomap(ofdev->dev.of_node, 1);
1659 if (!(host_pvt.sata_dma_regs)) {
1660 dev_err(&ofdev->dev, "ioremap failed for AHBDMA register"
1661 " address\n");
1662 err = -ENODEV;
1663 goto error_out;
1664 }
1665
1666 /* Save dev for later use in dev_xxx() routines */
1667 host_pvt.dwc_dev = &ofdev->dev;
1668
1669 /* Initialize AHB DMAC */
1670 dma_dwc_init(hsdev, irq);
1671
1672 /* Enable SATA Interrupts */
1673 sata_dwc_enable_interrupts(hsdev);
1674
1675 /* Get SATA interrupt number */
1676 irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
1677 if (irq == NO_IRQ) {
1678 dev_err(&ofdev->dev, "no SATA DMA irq\n");
1679 err = -ENODEV;
1680 goto error_out;
1681 }
1682
1683 /*
1684 * Now, register with libATA core, this will also initiate the
1685 * device discovery process, invoking our port_start() handler &
1686 * error_handler() to execute a dummy Softreset EH session
1687 */
1688 rc = ata_host_activate(host, irq, sata_dwc_isr, 0, &sata_dwc_sht);
1689
1690 if (rc != 0)
1691 dev_err(&ofdev->dev, "failed to activate host");
1692
1693 dev_set_drvdata(&ofdev->dev, host);
1694 return 0;
1695
1696error_out:
1697 /* Free SATA DMA resources */
1698 dma_dwc_exit(hsdev);
1699
1700 if (base)
1701 iounmap(base);
1702 return err;
1703}
1704
1705static int sata_dwc_remove(struct of_device *ofdev)
1706{
1707 struct device *dev = &ofdev->dev;
1708 struct ata_host *host = dev_get_drvdata(dev);
1709 struct sata_dwc_device *hsdev = host->private_data;
1710
1711 ata_host_detach(host);
1712 dev_set_drvdata(dev, NULL);
1713
1714 /* Free SATA DMA resources */
1715 dma_dwc_exit(hsdev);
1716
1717 iounmap(hsdev->reg_base);
1718 kfree(hsdev);
1719 kfree(host);
1720 dev_dbg(&ofdev->dev, "done\n");
1721 return 0;
1722}
1723
1724static const struct of_device_id sata_dwc_match[] = {
1725 { .compatible = "amcc,sata-460ex", },
1726 {}
1727};
1728MODULE_DEVICE_TABLE(of, sata_dwc_match);
1729
1730static struct of_platform_driver sata_dwc_driver = {
1731 .driver = {
1732 .name = DRV_NAME,
1733 .owner = THIS_MODULE,
1734 .of_match_table = sata_dwc_match,
1735 },
1736 .probe = sata_dwc_probe,
1737 .remove = sata_dwc_remove,
1738};
1739
1740static int __init sata_dwc_init(void)
1741{
1742 return of_register_platform_driver(&sata_dwc_driver);
1743}
1744
1745static void __exit sata_dwc_exit(void)
1746{
1747 of_unregister_platform_driver(&sata_dwc_driver);
1748}
1749
1750module_init(sata_dwc_init);
1751module_exit(sata_dwc_exit);
1752
1753MODULE_LICENSE("GPL");
1754MODULE_AUTHOR("Mark Miesfeld <mmiesfeld@amcc.com>");
1755MODULE_DESCRIPTION("DesignWare Cores SATA controller low lever driver");
1756MODULE_VERSION(DRV_VERSION);
diff --git a/drivers/ata/sata_fsl.c b/drivers/ata/sata_fsl.c
index 61c89b54ea23..18c986dbb7f1 100644
--- a/drivers/ata/sata_fsl.c
+++ b/drivers/ata/sata_fsl.c
@@ -1096,7 +1096,7 @@ static void sata_fsl_host_intr(struct ata_port *ap)
1096{ 1096{
1097 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 1097 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1098 void __iomem *hcr_base = host_priv->hcr_base; 1098 void __iomem *hcr_base = host_priv->hcr_base;
1099 u32 hstatus, qc_active = 0; 1099 u32 hstatus, done_mask = 0;
1100 struct ata_queued_cmd *qc; 1100 struct ata_queued_cmd *qc;
1101 u32 SError; 1101 u32 SError;
1102 1102
@@ -1116,28 +1116,28 @@ static void sata_fsl_host_intr(struct ata_port *ap)
1116 } 1116 }
1117 1117
1118 /* Read command completed register */ 1118 /* Read command completed register */
1119 qc_active = ioread32(hcr_base + CC); 1119 done_mask = ioread32(hcr_base + CC);
1120 1120
1121 VPRINTK("Status of all queues :\n"); 1121 VPRINTK("Status of all queues :\n");
1122 VPRINTK("qc_active/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%x\n", 1122 VPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%x\n",
1123 qc_active, 1123 done_mask,
1124 ioread32(hcr_base + CA), 1124 ioread32(hcr_base + CA),
1125 ioread32(hcr_base + CE), 1125 ioread32(hcr_base + CE),
1126 ioread32(hcr_base + CQ), 1126 ioread32(hcr_base + CQ),
1127 ap->qc_active); 1127 ap->qc_active);
1128 1128
1129 if (qc_active & ap->qc_active) { 1129 if (done_mask & ap->qc_active) {
1130 int i; 1130 int i;
1131 /* clear CC bit, this will also complete the interrupt */ 1131 /* clear CC bit, this will also complete the interrupt */
1132 iowrite32(qc_active, hcr_base + CC); 1132 iowrite32(done_mask, hcr_base + CC);
1133 1133
1134 DPRINTK("Status of all queues :\n"); 1134 DPRINTK("Status of all queues :\n");
1135 DPRINTK("qc_active/CC = 0x%x, CA = 0x%x, CE=0x%x\n", 1135 DPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
1136 qc_active, ioread32(hcr_base + CA), 1136 done_mask, ioread32(hcr_base + CA),
1137 ioread32(hcr_base + CE)); 1137 ioread32(hcr_base + CE));
1138 1138
1139 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) { 1139 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) {
1140 if (qc_active & (1 << i)) { 1140 if (done_mask & (1 << i)) {
1141 qc = ata_qc_from_tag(ap, i); 1141 qc = ata_qc_from_tag(ap, i);
1142 if (qc) { 1142 if (qc) {
1143 ata_qc_complete(qc); 1143 ata_qc_complete(qc);
@@ -1164,7 +1164,7 @@ static void sata_fsl_host_intr(struct ata_port *ap)
1164 /* Spurious Interrupt!! */ 1164 /* Spurious Interrupt!! */
1165 DPRINTK("spurious interrupt!!, CC = 0x%x\n", 1165 DPRINTK("spurious interrupt!!, CC = 0x%x\n",
1166 ioread32(hcr_base + CC)); 1166 ioread32(hcr_base + CC));
1167 iowrite32(qc_active, hcr_base + CC); 1167 iowrite32(done_mask, hcr_base + CC);
1168 return; 1168 return;
1169 } 1169 }
1170} 1170}
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
index a476cd99b95d..9463c71dd38e 100644
--- a/drivers/ata/sata_mv.c
+++ b/drivers/ata/sata_mv.c
@@ -2716,34 +2716,35 @@ static void mv_err_intr(struct ata_port *ap)
2716static void mv_process_crpb_response(struct ata_port *ap, 2716static void mv_process_crpb_response(struct ata_port *ap,
2717 struct mv_crpb *response, unsigned int tag, int ncq_enabled) 2717 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
2718{ 2718{
2719 u8 ata_status;
2720 u16 edma_status = le16_to_cpu(response->flags);
2719 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag); 2721 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
2720 2722
2721 if (qc) { 2723 if (unlikely(!qc)) {
2722 u8 ata_status;
2723 u16 edma_status = le16_to_cpu(response->flags);
2724 /*
2725 * edma_status from a response queue entry:
2726 * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only).
2727 * MSB is saved ATA status from command completion.
2728 */
2729 if (!ncq_enabled) {
2730 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
2731 if (err_cause) {
2732 /*
2733 * Error will be seen/handled by mv_err_intr().
2734 * So do nothing at all here.
2735 */
2736 return;
2737 }
2738 }
2739 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
2740 if (!ac_err_mask(ata_status))
2741 ata_qc_complete(qc);
2742 /* else: leave it for mv_err_intr() */
2743 } else {
2744 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n", 2724 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
2745 __func__, tag); 2725 __func__, tag);
2726 return;
2727 }
2728
2729 /*
2730 * edma_status from a response queue entry:
2731 * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only).
2732 * MSB is saved ATA status from command completion.
2733 */
2734 if (!ncq_enabled) {
2735 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
2736 if (err_cause) {
2737 /*
2738 * Error will be seen/handled by
2739 * mv_err_intr(). So do nothing at all here.
2740 */
2741 return;
2742 }
2746 } 2743 }
2744 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
2745 if (!ac_err_mask(ata_status))
2746 ata_qc_complete(qc);
2747 /* else: leave it for mv_err_intr() */
2747} 2748}
2748 2749
2749static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp) 2750static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
diff --git a/drivers/ata/sata_nv.c b/drivers/ata/sata_nv.c
index 21161136cad0..cb89ef8d99d9 100644
--- a/drivers/ata/sata_nv.c
+++ b/drivers/ata/sata_nv.c
@@ -1018,7 +1018,7 @@ static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance)
1018 NV_ADMA_STAT_CPBERR | 1018 NV_ADMA_STAT_CPBERR |
1019 NV_ADMA_STAT_CMD_COMPLETE)) { 1019 NV_ADMA_STAT_CMD_COMPLETE)) {
1020 u32 check_commands = notifier_clears[i]; 1020 u32 check_commands = notifier_clears[i];
1021 int pos, error = 0; 1021 int pos, rc;
1022 1022
1023 if (status & NV_ADMA_STAT_CPBERR) { 1023 if (status & NV_ADMA_STAT_CPBERR) {
1024 /* check all active commands */ 1024 /* check all active commands */
@@ -1030,10 +1030,12 @@ static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance)
1030 } 1030 }
1031 1031
1032 /* check CPBs for completed commands */ 1032 /* check CPBs for completed commands */
1033 while ((pos = ffs(check_commands)) && !error) { 1033 while ((pos = ffs(check_commands))) {
1034 pos--; 1034 pos--;
1035 error = nv_adma_check_cpb(ap, pos, 1035 rc = nv_adma_check_cpb(ap, pos,
1036 notifier_error & (1 << pos)); 1036 notifier_error & (1 << pos));
1037 if (unlikely(rc))
1038 check_commands = 0;
1037 check_commands &= ~(1 << pos); 1039 check_commands &= ~(1 << pos);
1038 } 1040 }
1039 } 1041 }
@@ -2129,7 +2131,6 @@ static int nv_swncq_sdbfis(struct ata_port *ap)
2129 struct nv_swncq_port_priv *pp = ap->private_data; 2131 struct nv_swncq_port_priv *pp = ap->private_data;
2130 struct ata_eh_info *ehi = &ap->link.eh_info; 2132 struct ata_eh_info *ehi = &ap->link.eh_info;
2131 u32 sactive; 2133 u32 sactive;
2132 int nr_done = 0;
2133 u32 done_mask; 2134 u32 done_mask;
2134 int i; 2135 int i;
2135 u8 host_stat; 2136 u8 host_stat;
@@ -2170,22 +2171,21 @@ static int nv_swncq_sdbfis(struct ata_port *ap)
2170 pp->dhfis_bits &= ~(1 << i); 2171 pp->dhfis_bits &= ~(1 << i);
2171 pp->dmafis_bits &= ~(1 << i); 2172 pp->dmafis_bits &= ~(1 << i);
2172 pp->sdbfis_bits |= (1 << i); 2173 pp->sdbfis_bits |= (1 << i);
2173 nr_done++;
2174 } 2174 }
2175 } 2175 }
2176 2176
2177 if (!ap->qc_active) { 2177 if (!ap->qc_active) {
2178 DPRINTK("over\n"); 2178 DPRINTK("over\n");
2179 nv_swncq_pp_reinit(ap); 2179 nv_swncq_pp_reinit(ap);
2180 return nr_done; 2180 return 0;
2181 } 2181 }
2182 2182
2183 if (pp->qc_active & pp->dhfis_bits) 2183 if (pp->qc_active & pp->dhfis_bits)
2184 return nr_done; 2184 return 0;
2185 2185
2186 if ((pp->ncq_flags & ncq_saw_backout) || 2186 if ((pp->ncq_flags & ncq_saw_backout) ||
2187 (pp->qc_active ^ pp->dhfis_bits)) 2187 (pp->qc_active ^ pp->dhfis_bits))
2188 /* if the controller cann't get a device to host register FIS, 2188 /* if the controller can't get a device to host register FIS,
2189 * The driver needs to reissue the new command. 2189 * The driver needs to reissue the new command.
2190 */ 2190 */
2191 lack_dhfis = 1; 2191 lack_dhfis = 1;
@@ -2202,7 +2202,7 @@ static int nv_swncq_sdbfis(struct ata_port *ap)
2202 if (lack_dhfis) { 2202 if (lack_dhfis) {
2203 qc = ata_qc_from_tag(ap, pp->last_issue_tag); 2203 qc = ata_qc_from_tag(ap, pp->last_issue_tag);
2204 nv_swncq_issue_atacmd(ap, qc); 2204 nv_swncq_issue_atacmd(ap, qc);
2205 return nr_done; 2205 return 0;
2206 } 2206 }
2207 2207
2208 if (pp->defer_queue.defer_bits) { 2208 if (pp->defer_queue.defer_bits) {
@@ -2212,7 +2212,7 @@ static int nv_swncq_sdbfis(struct ata_port *ap)
2212 nv_swncq_issue_atacmd(ap, qc); 2212 nv_swncq_issue_atacmd(ap, qc);
2213 } 2213 }
2214 2214
2215 return nr_done; 2215 return 0;
2216} 2216}
2217 2217
2218static inline u32 nv_swncq_tag(struct ata_port *ap) 2218static inline u32 nv_swncq_tag(struct ata_port *ap)
@@ -2224,7 +2224,7 @@ static inline u32 nv_swncq_tag(struct ata_port *ap)
2224 return (tag & 0x1f); 2224 return (tag & 0x1f);
2225} 2225}
2226 2226
2227static int nv_swncq_dmafis(struct ata_port *ap) 2227static void nv_swncq_dmafis(struct ata_port *ap)
2228{ 2228{
2229 struct ata_queued_cmd *qc; 2229 struct ata_queued_cmd *qc;
2230 unsigned int rw; 2230 unsigned int rw;
@@ -2239,7 +2239,7 @@ static int nv_swncq_dmafis(struct ata_port *ap)
2239 qc = ata_qc_from_tag(ap, tag); 2239 qc = ata_qc_from_tag(ap, tag);
2240 2240
2241 if (unlikely(!qc)) 2241 if (unlikely(!qc))
2242 return 0; 2242 return;
2243 2243
2244 rw = qc->tf.flags & ATA_TFLAG_WRITE; 2244 rw = qc->tf.flags & ATA_TFLAG_WRITE;
2245 2245
@@ -2254,8 +2254,6 @@ static int nv_swncq_dmafis(struct ata_port *ap)
2254 dmactl |= ATA_DMA_WR; 2254 dmactl |= ATA_DMA_WR;
2255 2255
2256 iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); 2256 iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2257
2258 return 1;
2259} 2257}
2260 2258
2261static void nv_swncq_host_interrupt(struct ata_port *ap, u16 fis) 2259static void nv_swncq_host_interrupt(struct ata_port *ap, u16 fis)
@@ -2265,7 +2263,6 @@ static void nv_swncq_host_interrupt(struct ata_port *ap, u16 fis)
2265 struct ata_eh_info *ehi = &ap->link.eh_info; 2263 struct ata_eh_info *ehi = &ap->link.eh_info;
2266 u32 serror; 2264 u32 serror;
2267 u8 ata_stat; 2265 u8 ata_stat;
2268 int rc = 0;
2269 2266
2270 ata_stat = ap->ops->sff_check_status(ap); 2267 ata_stat = ap->ops->sff_check_status(ap);
2271 nv_swncq_irq_clear(ap, fis); 2268 nv_swncq_irq_clear(ap, fis);
@@ -2310,8 +2307,7 @@ static void nv_swncq_host_interrupt(struct ata_port *ap, u16 fis)
2310 "dhfis 0x%X dmafis 0x%X sactive 0x%X\n", 2307 "dhfis 0x%X dmafis 0x%X sactive 0x%X\n",
2311 ap->print_id, pp->qc_active, pp->dhfis_bits, 2308 ap->print_id, pp->qc_active, pp->dhfis_bits,
2312 pp->dmafis_bits, readl(pp->sactive_block)); 2309 pp->dmafis_bits, readl(pp->sactive_block));
2313 rc = nv_swncq_sdbfis(ap); 2310 if (nv_swncq_sdbfis(ap) < 0)
2314 if (rc < 0)
2315 goto irq_error; 2311 goto irq_error;
2316 } 2312 }
2317 2313
@@ -2348,7 +2344,7 @@ static void nv_swncq_host_interrupt(struct ata_port *ap, u16 fis)
2348 */ 2344 */
2349 pp->dmafis_bits |= (0x1 << nv_swncq_tag(ap)); 2345 pp->dmafis_bits |= (0x1 << nv_swncq_tag(ap));
2350 pp->ncq_flags |= ncq_saw_dmas; 2346 pp->ncq_flags |= ncq_saw_dmas;
2351 rc = nv_swncq_dmafis(ap); 2347 nv_swncq_dmafis(ap);
2352 } 2348 }
2353 2349
2354irq_exit: 2350irq_exit:
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 477345d41641..a0c20d9e8396 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -1459,6 +1459,7 @@ static void quirk_jmicron_ata(struct pci_dev *pdev)
1459 switch (pdev->device) { 1459 switch (pdev->device) {
1460 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ 1460 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1461 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ 1461 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1462 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1462 /* The controller should be in single function ahci mode */ 1463 /* The controller should be in single function ahci mode */
1463 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ 1464 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1464 break; 1465 break;
@@ -1470,6 +1471,7 @@ static void quirk_jmicron_ata(struct pci_dev *pdev)
1470 /* Fall through */ 1471 /* Fall through */
1471 case PCI_DEVICE_ID_JMICRON_JMB361: 1472 case PCI_DEVICE_ID_JMICRON_JMB361:
1472 case PCI_DEVICE_ID_JMICRON_JMB363: 1473 case PCI_DEVICE_ID_JMICRON_JMB363:
1474 case PCI_DEVICE_ID_JMICRON_JMB369:
1473 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1475 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1474 /* Set the class codes correctly and then direct IDE 0 */ 1476 /* Set the class codes correctly and then direct IDE 0 */
1475 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ 1477 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
@@ -1496,16 +1498,20 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, qui
1496DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1498DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1497DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1499DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1498DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1500DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1501DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1499DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1502DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1500DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1503DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1501DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1504DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1505DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1502DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1506DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1503DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1507DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1504DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1508DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1505DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1509DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1510DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1506DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1511DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1507DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1512DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1508DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1513DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1514DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1509 1515
1510#endif 1516#endif
1511 1517
diff --git a/include/linux/ahci_platform.h b/include/linux/ahci_platform.h
index f7dd576dd5a4..be3d9a77d6ed 100644
--- a/include/linux/ahci_platform.h
+++ b/include/linux/ahci_platform.h
@@ -15,11 +15,13 @@
15#ifndef _AHCI_PLATFORM_H 15#ifndef _AHCI_PLATFORM_H
16#define _AHCI_PLATFORM_H 16#define _AHCI_PLATFORM_H
17 17
18#include <linux/compiler.h>
19
18struct device; 20struct device;
19struct ata_port_info; 21struct ata_port_info;
20 22
21struct ahci_platform_data { 23struct ahci_platform_data {
22 int (*init)(struct device *dev); 24 int (*init)(struct device *dev, void __iomem *addr);
23 void (*exit)(struct device *dev); 25 void (*exit)(struct device *dev);
24 const struct ata_port_info *ata_port_info; 26 const struct ata_port_info *ata_port_info;
25 unsigned int force_port_map; 27 unsigned int force_port_map;
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 40c804d484ca..c81eec4d3c35 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2325,9 +2325,11 @@
2325#define PCI_DEVICE_ID_JMICRON_JMB361 0x2361 2325#define PCI_DEVICE_ID_JMICRON_JMB361 0x2361
2326#define PCI_DEVICE_ID_JMICRON_JMB362 0x2362 2326#define PCI_DEVICE_ID_JMICRON_JMB362 0x2362
2327#define PCI_DEVICE_ID_JMICRON_JMB363 0x2363 2327#define PCI_DEVICE_ID_JMICRON_JMB363 0x2363
2328#define PCI_DEVICE_ID_JMICRON_JMB364 0x2364
2328#define PCI_DEVICE_ID_JMICRON_JMB365 0x2365 2329#define PCI_DEVICE_ID_JMICRON_JMB365 0x2365
2329#define PCI_DEVICE_ID_JMICRON_JMB366 0x2366 2330#define PCI_DEVICE_ID_JMICRON_JMB366 0x2366
2330#define PCI_DEVICE_ID_JMICRON_JMB368 0x2368 2331#define PCI_DEVICE_ID_JMICRON_JMB368 0x2368
2332#define PCI_DEVICE_ID_JMICRON_JMB369 0x2369
2331#define PCI_DEVICE_ID_JMICRON_JMB38X_SD 0x2381 2333#define PCI_DEVICE_ID_JMICRON_JMB38X_SD 0x2381
2332#define PCI_DEVICE_ID_JMICRON_JMB38X_MMC 0x2382 2334#define PCI_DEVICE_ID_JMICRON_JMB38X_MMC 0x2382
2333#define PCI_DEVICE_ID_JMICRON_JMB38X_MS 0x2383 2335#define PCI_DEVICE_ID_JMICRON_JMB38X_MS 0x2383
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 08:02:15 -0500