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authorAndrew Victor <linux@maxim.org.za>2008-01-24 09:10:39 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-01-26 10:01:13 -0500
commit2b3b3516b6eeea1464e205b2dde9ebc9b7dd2ec8 (patch)
tree29ec4fd51c8231fd710783effcbaf21b4f80005d
parentda7a42d60ba214937ddb35152f336a4e4baa49a6 (diff)
[ARM] 4764/1: [AT91] AT91CAP9 core support
Add support for Atmel's AT91CAP9 Customizable Microcontroller family. <http://www.atmel.com/products/AT91CAP/Default.asp> Signed-off-by: Stelian Pop <stelian@popies.net> Signed-off-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat
-rw-r--r--arch/arm/Kconfig4
-rw-r--r--arch/arm/mach-at91/Kconfig3
-rw-r--r--arch/arm/mach-at91/Makefile1
-rw-r--r--arch/arm/mach-at91/Makefile.boot7
-rw-r--r--arch/arm/mach-at91/at91cap9.c365
-rw-r--r--arch/arm/mach-at91/at91cap9_devices.c1066
-rw-r--r--arch/arm/mach-at91/clock.c2
-rw-r--r--arch/arm/mach-at91/generic.h2
-rw-r--r--arch/arm/mach-at91/pm.c5
-rw-r--r--arch/arm/mm/Kconfig4
-rw-r--r--drivers/net/Kconfig2
-rw-r--r--drivers/usb/gadget/Kconfig2
-rw-r--r--drivers/video/Kconfig2
-rw-r--r--drivers/video/atmel_lcdfb.c2
-rw-r--r--include/asm-arm/arch-at91/at91_pmc.h7
-rw-r--r--include/asm-arm/arch-at91/at91cap9.h121
-rw-r--r--include/asm-arm/arch-at91/at91cap9_matrix.h132
-rw-r--r--include/asm-arm/arch-at91/at91sam9263_matrix.h2
-rw-r--r--include/asm-arm/arch-at91/at91sam9rl_matrix.h2
-rw-r--r--include/asm-arm/arch-at91/board.h2
-rw-r--r--include/asm-arm/arch-at91/cpu.h9
-rw-r--r--include/asm-arm/arch-at91/hardware.h2
-rw-r--r--include/asm-arm/arch-at91/timex.h5
-rw-r--r--include/asm-avr32/arch-at32ap/cpu.h1
24 files changed, 1735 insertions, 15 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 93e40b65fd0b..0bd479c47651 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -180,8 +180,8 @@ config ARCH_AT91
180 bool "Atmel AT91" 180 bool "Atmel AT91"
181 select GENERIC_GPIO 181 select GENERIC_GPIO
182 help 182 help
183 This enables support for systems based on the Atmel AT91RM9200 183 This enables support for systems based on the Atmel AT91RM9200,
184 and AT91SAM9xxx processors. 184 AT91SAM9 and AT91CAP9 processors.
185 185
186config ARCH_CLPS7500 186config ARCH_CLPS7500
187 bool "Cirrus CL-PS7500FE" 187 bool "Cirrus CL-PS7500FE"
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 214733e897e5..d12c616407d6 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -22,6 +22,9 @@ config ARCH_AT91SAM9263
22config ARCH_AT91SAM9RL 22config ARCH_AT91SAM9RL
23 bool "AT91SAM9RL" 23 bool "AT91SAM9RL"
24 24
25config ARCH_AT91CAP9
26 bool "AT91CAP9"
27
25config ARCH_AT91X40 28config ARCH_AT91X40
26 bool "AT91x40" 29 bool "AT91x40"
27 30
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 529ffb5f3f13..10413c5d3f8a 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_d
15obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o 15obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o
16obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o 16obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o
17obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o 17obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o
18obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o
18obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o 19obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o
19 20
20# AT91RM9200 board-specific support 21# AT91RM9200 board-specific support
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot
index e667dcc7cd34..071a2506a69f 100644
--- a/arch/arm/mach-at91/Makefile.boot
+++ b/arch/arm/mach-at91/Makefile.boot
@@ -3,7 +3,12 @@
3# PARAMS_PHYS must be within 4MB of ZRELADDR 3# PARAMS_PHYS must be within 4MB of ZRELADDR
4# INITRD_PHYS must be in RAM 4# INITRD_PHYS must be in RAM
5 5
6ifeq ($(CONFIG_ARCH_AT91CAP9),y)
7 zreladdr-y := 0x70008000
8params_phys-y := 0x70000100
9initrd_phys-y := 0x70410000
10else
6 zreladdr-y := 0x20008000 11 zreladdr-y := 0x20008000
7params_phys-y := 0x20000100 12params_phys-y := 0x20000100
8initrd_phys-y := 0x20410000 13initrd_phys-y := 0x20410000
9 14endif
diff --git a/arch/arm/mach-at91/at91cap9.c b/arch/arm/mach-at91/at91cap9.c
new file mode 100644
index 000000000000..48d27d8000b0
--- /dev/null
+++ b/arch/arm/mach-at91/at91cap9.c
@@ -0,0 +1,365 @@
1/*
2 * arch/arm/mach-at91/at91cap9.c
3 *
4 * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5 * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2007 Atmel Corporation.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 */
14
15#include <linux/module.h>
16
17#include <asm/mach/arch.h>
18#include <asm/mach/map.h>
19#include <asm/arch/at91cap9.h>
20#include <asm/arch/at91_pmc.h>
21#include <asm/arch/at91_rstc.h>
22
23#include "generic.h"
24#include "clock.h"
25
26static struct map_desc at91cap9_io_desc[] __initdata = {
27 {
28 .virtual = AT91_VA_BASE_SYS,
29 .pfn = __phys_to_pfn(AT91_BASE_SYS),
30 .length = SZ_16K,
31 .type = MT_DEVICE,
32 }, {
33 .virtual = AT91_IO_VIRT_BASE - AT91CAP9_SRAM_SIZE,
34 .pfn = __phys_to_pfn(AT91CAP9_SRAM_BASE),
35 .length = AT91CAP9_SRAM_SIZE,
36 .type = MT_DEVICE,
37 },
38};
39
40/* --------------------------------------------------------------------
41 * Clocks
42 * -------------------------------------------------------------------- */
43
44/*
45 * The peripheral clocks.
46 */
47static struct clk pioABCD_clk = {
48 .name = "pioABCD_clk",
49 .pmc_mask = 1 << AT91CAP9_ID_PIOABCD,
50 .type = CLK_TYPE_PERIPHERAL,
51};
52static struct clk mpb0_clk = {
53 .name = "mpb0_clk",
54 .pmc_mask = 1 << AT91CAP9_ID_MPB0,
55 .type = CLK_TYPE_PERIPHERAL,
56};
57static struct clk mpb1_clk = {
58 .name = "mpb1_clk",
59 .pmc_mask = 1 << AT91CAP9_ID_MPB1,
60 .type = CLK_TYPE_PERIPHERAL,
61};
62static struct clk mpb2_clk = {
63 .name = "mpb2_clk",
64 .pmc_mask = 1 << AT91CAP9_ID_MPB2,
65 .type = CLK_TYPE_PERIPHERAL,
66};
67static struct clk mpb3_clk = {
68 .name = "mpb3_clk",
69 .pmc_mask = 1 << AT91CAP9_ID_MPB3,
70 .type = CLK_TYPE_PERIPHERAL,
71};
72static struct clk mpb4_clk = {
73 .name = "mpb4_clk",
74 .pmc_mask = 1 << AT91CAP9_ID_MPB4,
75 .type = CLK_TYPE_PERIPHERAL,
76};
77static struct clk usart0_clk = {
78 .name = "usart0_clk",
79 .pmc_mask = 1 << AT91CAP9_ID_US0,
80 .type = CLK_TYPE_PERIPHERAL,
81};
82static struct clk usart1_clk = {
83 .name = "usart1_clk",
84 .pmc_mask = 1 << AT91CAP9_ID_US1,
85 .type = CLK_TYPE_PERIPHERAL,
86};
87static struct clk usart2_clk = {
88 .name = "usart2_clk",
89 .pmc_mask = 1 << AT91CAP9_ID_US2,
90 .type = CLK_TYPE_PERIPHERAL,
91};
92static struct clk mmc0_clk = {
93 .name = "mci0_clk",
94 .pmc_mask = 1 << AT91CAP9_ID_MCI0,
95 .type = CLK_TYPE_PERIPHERAL,
96};
97static struct clk mmc1_clk = {
98 .name = "mci1_clk",
99 .pmc_mask = 1 << AT91CAP9_ID_MCI1,
100 .type = CLK_TYPE_PERIPHERAL,
101};
102static struct clk can_clk = {
103 .name = "can_clk",
104 .pmc_mask = 1 << AT91CAP9_ID_CAN,
105 .type = CLK_TYPE_PERIPHERAL,
106};
107static struct clk twi_clk = {
108 .name = "twi_clk",
109 .pmc_mask = 1 << AT91CAP9_ID_TWI,
110 .type = CLK_TYPE_PERIPHERAL,
111};
112static struct clk spi0_clk = {
113 .name = "spi0_clk",
114 .pmc_mask = 1 << AT91CAP9_ID_SPI0,
115 .type = CLK_TYPE_PERIPHERAL,
116};
117static struct clk spi1_clk = {
118 .name = "spi1_clk",
119 .pmc_mask = 1 << AT91CAP9_ID_SPI1,
120 .type = CLK_TYPE_PERIPHERAL,
121};
122static struct clk ssc0_clk = {
123 .name = "ssc0_clk",
124 .pmc_mask = 1 << AT91CAP9_ID_SSC0,
125 .type = CLK_TYPE_PERIPHERAL,
126};
127static struct clk ssc1_clk = {
128 .name = "ssc1_clk",
129 .pmc_mask = 1 << AT91CAP9_ID_SSC1,
130 .type = CLK_TYPE_PERIPHERAL,
131};
132static struct clk ac97_clk = {
133 .name = "ac97_clk",
134 .pmc_mask = 1 << AT91CAP9_ID_AC97C,
135 .type = CLK_TYPE_PERIPHERAL,
136};
137static struct clk tcb_clk = {
138 .name = "tcb_clk",
139 .pmc_mask = 1 << AT91CAP9_ID_TCB,
140 .type = CLK_TYPE_PERIPHERAL,
141};
142static struct clk pwmc_clk = {
143 .name = "pwmc_clk",
144 .pmc_mask = 1 << AT91CAP9_ID_PWMC,
145 .type = CLK_TYPE_PERIPHERAL,
146};
147static struct clk macb_clk = {
148 .name = "macb_clk",
149 .pmc_mask = 1 << AT91CAP9_ID_EMAC,
150 .type = CLK_TYPE_PERIPHERAL,
151};
152static struct clk aestdes_clk = {
153 .name = "aestdes_clk",
154 .pmc_mask = 1 << AT91CAP9_ID_AESTDES,
155 .type = CLK_TYPE_PERIPHERAL,
156};
157static struct clk adc_clk = {
158 .name = "adc_clk",
159 .pmc_mask = 1 << AT91CAP9_ID_ADC,
160 .type = CLK_TYPE_PERIPHERAL,
161};
162static struct clk isi_clk = {
163 .name = "isi_clk",
164 .pmc_mask = 1 << AT91CAP9_ID_ISI,
165 .type = CLK_TYPE_PERIPHERAL,
166};
167static struct clk lcdc_clk = {
168 .name = "lcdc_clk",
169 .pmc_mask = 1 << AT91CAP9_ID_LCDC,
170 .type = CLK_TYPE_PERIPHERAL,
171};
172static struct clk dma_clk = {
173 .name = "dma_clk",
174 .pmc_mask = 1 << AT91CAP9_ID_DMA,
175 .type = CLK_TYPE_PERIPHERAL,
176};
177static struct clk udphs_clk = {
178 .name = "udphs_clk",
179 .pmc_mask = 1 << AT91CAP9_ID_UDPHS,
180 .type = CLK_TYPE_PERIPHERAL,
181};
182static struct clk ohci_clk = {
183 .name = "ohci_clk",
184 .pmc_mask = 1 << AT91CAP9_ID_UHP,
185 .type = CLK_TYPE_PERIPHERAL,
186};
187
188static struct clk *periph_clocks[] __initdata = {
189 &pioABCD_clk,
190 &mpb0_clk,
191 &mpb1_clk,
192 &mpb2_clk,
193 &mpb3_clk,
194 &mpb4_clk,
195 &usart0_clk,
196 &usart1_clk,
197 &usart2_clk,
198 &mmc0_clk,
199 &mmc1_clk,
200 &can_clk,
201 &twi_clk,
202 &spi0_clk,
203 &spi1_clk,
204 &ssc0_clk,
205 &ssc1_clk,
206 &ac97_clk,
207 &tcb_clk,
208 &pwmc_clk,
209 &macb_clk,
210 &aestdes_clk,
211 &adc_clk,
212 &isi_clk,
213 &lcdc_clk,
214 &dma_clk,
215 &udphs_clk,
216 &ohci_clk,
217 // irq0 .. irq1
218};
219
220/*
221 * The four programmable clocks.
222 * You must configure pin multiplexing to bring these signals out.
223 */
224static struct clk pck0 = {
225 .name = "pck0",
226 .pmc_mask = AT91_PMC_PCK0,
227 .type = CLK_TYPE_PROGRAMMABLE,
228 .id = 0,
229};
230static struct clk pck1 = {
231 .name = "pck1",
232 .pmc_mask = AT91_PMC_PCK1,
233 .type = CLK_TYPE_PROGRAMMABLE,
234 .id = 1,
235};
236static struct clk pck2 = {
237 .name = "pck2",
238 .pmc_mask = AT91_PMC_PCK2,
239 .type = CLK_TYPE_PROGRAMMABLE,
240 .id = 2,
241};
242static struct clk pck3 = {
243 .name = "pck3",
244 .pmc_mask = AT91_PMC_PCK3,
245 .type = CLK_TYPE_PROGRAMMABLE,
246 .id = 3,
247};
248
249static void __init at91cap9_register_clocks(void)
250{
251 int i;
252
253 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
254 clk_register(periph_clocks[i]);
255
256 clk_register(&pck0);
257 clk_register(&pck1);
258 clk_register(&pck2);
259 clk_register(&pck3);
260}
261
262/* --------------------------------------------------------------------
263 * GPIO
264 * -------------------------------------------------------------------- */
265
266static struct at91_gpio_bank at91cap9_gpio[] = {
267 {
268 .id = AT91CAP9_ID_PIOABCD,
269 .offset = AT91_PIOA,
270 .clock = &pioABCD_clk,
271 }, {
272 .id = AT91CAP9_ID_PIOABCD,
273 .offset = AT91_PIOB,
274 .clock = &pioABCD_clk,
275 }, {
276 .id = AT91CAP9_ID_PIOABCD,
277 .offset = AT91_PIOC,
278 .clock = &pioABCD_clk,
279 }, {
280 .id = AT91CAP9_ID_PIOABCD,
281 .offset = AT91_PIOD,
282 .clock = &pioABCD_clk,
283 }
284};
285
286static void at91cap9_reset(void)
287{
288 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
289}
290
291/* --------------------------------------------------------------------
292 * AT91CAP9 processor initialization
293 * -------------------------------------------------------------------- */
294
295void __init at91cap9_initialize(unsigned long main_clock)
296{
297 /* Map peripherals */
298 iotable_init(at91cap9_io_desc, ARRAY_SIZE(at91cap9_io_desc));
299
300 at91_arch_reset = at91cap9_reset;
301 at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
302
303 /* Init clock subsystem */
304 at91_clock_init(main_clock);
305
306 /* Register the processor-specific clocks */
307 at91cap9_register_clocks();
308
309 /* Register GPIO subsystem */
310 at91_gpio_init(at91cap9_gpio, 4);
311}
312
313/* --------------------------------------------------------------------
314 * Interrupt initialization
315 * -------------------------------------------------------------------- */
316
317/*
318 * The default interrupt priority levels (0 = lowest, 7 = highest).
319 */
320static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = {
321 7, /* Advanced Interrupt Controller (FIQ) */
322 7, /* System Peripherals */
323 1, /* Parallel IO Controller A, B, C and D */
324 0, /* MP Block Peripheral 0 */
325 0, /* MP Block Peripheral 1 */
326 0, /* MP Block Peripheral 2 */
327 0, /* MP Block Peripheral 3 */
328 0, /* MP Block Peripheral 4 */
329 5, /* USART 0 */
330 5, /* USART 1 */
331 5, /* USART 2 */
332 0, /* Multimedia Card Interface 0 */
333 0, /* Multimedia Card Interface 1 */
334 3, /* CAN */
335 6, /* Two-Wire Interface */
336 5, /* Serial Peripheral Interface 0 */
337 5, /* Serial Peripheral Interface 1 */
338 4, /* Serial Synchronous Controller 0 */
339 4, /* Serial Synchronous Controller 1 */
340 5, /* AC97 Controller */
341 0, /* Timer Counter 0, 1 and 2 */
342 0, /* Pulse Width Modulation Controller */
343 3, /* Ethernet */
344 0, /* Advanced Encryption Standard, Triple DES*/
345 0, /* Analog-to-Digital Converter */
346 0, /* Image Sensor Interface */
347 3, /* LCD Controller */
348 0, /* DMA Controller */
349 2, /* USB Device Port */
350 2, /* USB Host port */
351 0, /* Advanced Interrupt Controller (IRQ0) */
352 0, /* Advanced Interrupt Controller (IRQ1) */
353};
354
355void __init at91cap9_init_interrupts(unsigned int priority[NR_AIC_IRQS])
356{
357 if (!priority)
358 priority = at91cap9_default_irq_priority;
359
360 /* Initialize the AIC interrupt controller */
361 at91_aic_init(priority);
362
363 /* Enable GPIO interrupts */
364 at91_gpio_irq_setup();
365}
diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c
new file mode 100644
index 000000000000..c50fad9cd143
--- /dev/null
+++ b/arch/arm/mach-at91/at91cap9_devices.c
@@ -0,0 +1,1066 @@
1/*
2 * arch/arm/mach-at91/at91cap9_devices.c
3 *
4 * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5 * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2007 Atmel Corporation.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 */
14#include <asm/mach/arch.h>
15#include <asm/mach/map.h>
16
17#include <linux/dma-mapping.h>
18#include <linux/platform_device.h>
19#include <linux/mtd/physmap.h>
20
21#include <video/atmel_lcdc.h>
22
23#include <asm/arch/board.h>
24#include <asm/arch/gpio.h>
25#include <asm/arch/at91cap9.h>
26#include <asm/arch/at91sam926x_mc.h>
27#include <asm/arch/at91cap9_matrix.h>
28
29#include "generic.h"
30
31
32/* --------------------------------------------------------------------
33 * USB Host
34 * -------------------------------------------------------------------- */
35
36#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
37static u64 ohci_dmamask = DMA_BIT_MASK(32);
38static struct at91_usbh_data usbh_data;
39
40static struct resource usbh_resources[] = {
41 [0] = {
42 .start = AT91CAP9_UHP_BASE,
43 .end = AT91CAP9_UHP_BASE + SZ_1M - 1,
44 .flags = IORESOURCE_MEM,
45 },
46 [1] = {
47 .start = AT91CAP9_ID_UHP,
48 .end = AT91CAP9_ID_UHP,
49 .flags = IORESOURCE_IRQ,
50 },
51};
52
53static struct platform_device at91_usbh_device = {
54 .name = "at91_ohci",
55 .id = -1,
56 .dev = {
57 .dma_mask = &ohci_dmamask,
58 .coherent_dma_mask = DMA_BIT_MASK(32),
59 .platform_data = &usbh_data,
60 },
61 .resource = usbh_resources,
62 .num_resources = ARRAY_SIZE(usbh_resources),
63};
64
65void __init at91_add_device_usbh(struct at91_usbh_data *data)
66{
67 int i;
68
69 if (!data)
70 return;
71
72 /* Enable VBus control for UHP ports */
73 for (i = 0; i < data->ports; i++) {
74 if (data->vbus_pin[i])
75 at91_set_gpio_output(data->vbus_pin[i], 0);
76 }
77
78 usbh_data = *data;
79 platform_device_register(&at91_usbh_device);
80}
81#else
82void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
83#endif
84
85
86/* --------------------------------------------------------------------
87 * Ethernet
88 * -------------------------------------------------------------------- */
89
90#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
91static u64 eth_dmamask = DMA_BIT_MASK(32);
92static struct at91_eth_data eth_data;
93
94static struct resource eth_resources[] = {
95 [0] = {
96 .start = AT91CAP9_BASE_EMAC,
97 .end = AT91CAP9_BASE_EMAC + SZ_16K - 1,
98 .flags = IORESOURCE_MEM,
99 },
100 [1] = {
101 .start = AT91CAP9_ID_EMAC,
102 .end = AT91CAP9_ID_EMAC,
103 .flags = IORESOURCE_IRQ,
104 },
105};
106
107static struct platform_device at91cap9_eth_device = {
108 .name = "macb",
109 .id = -1,
110 .dev = {
111 .dma_mask = &eth_dmamask,
112 .coherent_dma_mask = DMA_BIT_MASK(32),
113 .platform_data = &eth_data,
114 },
115 .resource = eth_resources,
116 .num_resources = ARRAY_SIZE(eth_resources),
117};
118
119void __init at91_add_device_eth(struct at91_eth_data *data)
120{
121 if (!data)
122 return;
123
124 if (data->phy_irq_pin) {
125 at91_set_gpio_input(data->phy_irq_pin, 0);
126 at91_set_deglitch(data->phy_irq_pin, 1);
127 }
128
129 /* Pins used for MII and RMII */
130 at91_set_A_periph(AT91_PIN_PB21, 0); /* ETXCK_EREFCK */
131 at91_set_A_periph(AT91_PIN_PB22, 0); /* ERXDV */
132 at91_set_A_periph(AT91_PIN_PB25, 0); /* ERX0 */
133 at91_set_A_periph(AT91_PIN_PB26, 0); /* ERX1 */
134 at91_set_A_periph(AT91_PIN_PB27, 0); /* ERXER */
135 at91_set_A_periph(AT91_PIN_PB28, 0); /* ETXEN */
136 at91_set_A_periph(AT91_PIN_PB23, 0); /* ETX0 */
137 at91_set_A_periph(AT91_PIN_PB24, 0); /* ETX1 */
138 at91_set_A_periph(AT91_PIN_PB30, 0); /* EMDIO */
139 at91_set_A_periph(AT91_PIN_PB29, 0); /* EMDC */
140
141 if (!data->is_rmii) {
142 at91_set_B_periph(AT91_PIN_PC25, 0); /* ECRS */
143 at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
144 at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
145 at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
146 at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
147 at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
148 at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
149 at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
150 }
151
152 eth_data = *data;
153 platform_device_register(&at91cap9_eth_device);
154}
155#else
156void __init at91_add_device_eth(struct at91_eth_data *data) {}
157#endif
158
159
160/* --------------------------------------------------------------------
161 * MMC / SD
162 * -------------------------------------------------------------------- */
163
164#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
165static u64 mmc_dmamask = DMA_BIT_MASK(32);
166static struct at91_mmc_data mmc0_data, mmc1_data;
167
168static struct resource mmc0_resources[] = {
169 [0] = {
170 .start = AT91CAP9_BASE_MCI0,
171 .end = AT91CAP9_BASE_MCI0 + SZ_16K - 1,
172 .flags = IORESOURCE_MEM,
173 },
174 [1] = {
175 .start = AT91CAP9_ID_MCI0,
176 .end = AT91CAP9_ID_MCI0,
177 .flags = IORESOURCE_IRQ,
178 },
179};
180
181static struct platform_device at91cap9_mmc0_device = {
182 .name = "at91_mci",
183 .id = 0,
184 .dev = {
185 .dma_mask = &mmc_dmamask,
186 .coherent_dma_mask = DMA_BIT_MASK(32),
187 .platform_data = &mmc0_data,
188 },
189 .resource = mmc0_resources,
190 .num_resources = ARRAY_SIZE(mmc0_resources),
191};
192
193static struct resource mmc1_resources[] = {
194 [0] = {
195 .start = AT91CAP9_BASE_MCI1,
196 .end = AT91CAP9_BASE_MCI1 + SZ_16K - 1,
197 .flags = IORESOURCE_MEM,
198 },
199 [1] = {
200 .start = AT91CAP9_ID_MCI1,
201 .end = AT91CAP9_ID_MCI1,
202 .flags = IORESOURCE_IRQ,
203 },
204};
205
206static struct platform_device at91cap9_mmc1_device = {
207 .name = "at91_mci",
208 .id = 1,
209 .dev = {
210 .dma_mask = &mmc_dmamask,
211 .coherent_dma_mask = DMA_BIT_MASK(32),
212 .platform_data = &mmc1_data,
213 },
214 .resource = mmc1_resources,
215 .num_resources = ARRAY_SIZE(mmc1_resources),
216};
217
218void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
219{
220 if (!data)
221 return;
222
223 /* input/irq */
224 if (data->det_pin) {
225 at91_set_gpio_input(data->det_pin, 1);
226 at91_set_deglitch(data->det_pin, 1);
227 }
228 if (data->wp_pin)
229 at91_set_gpio_input(data->wp_pin, 1);
230 if (data->vcc_pin)
231 at91_set_gpio_output(data->vcc_pin, 0);
232
233 if (mmc_id == 0) { /* MCI0 */
234 /* CLK */
235 at91_set_A_periph(AT91_PIN_PA2, 0);
236
237 /* CMD */
238 at91_set_A_periph(AT91_PIN_PA1, 1);
239
240 /* DAT0, maybe DAT1..DAT3 */
241 at91_set_A_periph(AT91_PIN_PA0, 1);
242 if (data->wire4) {
243 at91_set_A_periph(AT91_PIN_PA3, 1);
244 at91_set_A_periph(AT91_PIN_PA4, 1);
245 at91_set_A_periph(AT91_PIN_PA5, 1);
246 }
247
248 mmc0_data = *data;
249 at91_clock_associate("mci0_clk", &at91cap9_mmc1_device.dev, "mci_clk");
250 platform_device_register(&at91cap9_mmc0_device);
251 } else { /* MCI1 */
252 /* CLK */
253 at91_set_A_periph(AT91_PIN_PA16, 0);
254
255 /* CMD */
256 at91_set_A_periph(AT91_PIN_PA17, 1);
257
258 /* DAT0, maybe DAT1..DAT3 */
259 at91_set_A_periph(AT91_PIN_PA18, 1);
260 if (data->wire4) {
261 at91_set_A_periph(AT91_PIN_PA19, 1);
262 at91_set_A_periph(AT91_PIN_PA20, 1);
263 at91_set_A_periph(AT91_PIN_PA21, 1);
264 }
265
266 mmc1_data = *data;
267 at91_clock_associate("mci1_clk", &at91cap9_mmc1_device.dev, "mci_clk");
268 platform_device_register(&at91cap9_mmc1_device);
269 }
270}
271#else
272void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
273#endif
274
275
276/* --------------------------------------------------------------------
277 * NAND / SmartMedia
278 * -------------------------------------------------------------------- */
279
280#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
281static struct at91_nand_data nand_data;
282
283#define NAND_BASE AT91_CHIPSELECT_3
284
285static struct resource nand_resources[] = {
286 {
287 .start = NAND_BASE,
288 .end = NAND_BASE + SZ_256M - 1,
289 .flags = IORESOURCE_MEM,
290 }
291};
292
293static struct platform_device at91cap9_nand_device = {
294 .name = "at91_nand",
295 .id = -1,
296 .dev = {
297 .platform_data = &nand_data,
298 },
299 .resource = nand_resources,
300 .num_resources = ARRAY_SIZE(nand_resources),
301};
302
303void __init at91_add_device_nand(struct at91_nand_data *data)
304{
305 unsigned long csa, mode;
306
307 if (!data)
308 return;
309
310 csa = at91_sys_read(AT91_MATRIX_EBICSA);
311 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
312
313 /* set the bus interface characteristics */
314 at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(1)
315 | AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(1));
316
317 at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(6)
318 | AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(6));
319
320 at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
321
322 if (data->bus_width_16)
323 mode = AT91_SMC_DBW_16;
324 else
325 mode = AT91_SMC_DBW_8;
326 at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
327
328 /* enable pin */
329 if (data->enable_pin)
330 at91_set_gpio_output(data->enable_pin, 1);
331
332 /* ready/busy pin */
333 if (data->rdy_pin)
334 at91_set_gpio_input(data->rdy_pin, 1);
335
336 /* card detect pin */
337 if (data->det_pin)
338 at91_set_gpio_input(data->det_pin, 1);
339
340 nand_data = *data;
341 platform_device_register(&at91cap9_nand_device);
342}
343#else
344void __init at91_add_device_nand(struct at91_nand_data *data) {}
345#endif
346
347/* --------------------------------------------------------------------
348 * TWI (i2c)
349 * -------------------------------------------------------------------- */
350
351/*
352 * Prefer the GPIO code since the TWI controller isn't robust
353 * (gets overruns and underruns under load) and can only issue
354 * repeated STARTs in one scenario (the driver doesn't yet handle them).
355 */
356#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
357
358static struct i2c_gpio_platform_data pdata = {
359 .sda_pin = AT91_PIN_PB4,
360 .sda_is_open_drain = 1,
361 .scl_pin = AT91_PIN_PB5,
362 .scl_is_open_drain = 1,
363 .udelay = 2, /* ~100 kHz */
364};
365
366static struct platform_device at91cap9_twi_device = {
367 .name = "i2c-gpio",
368 .id = -1,
369 .dev.platform_data = &pdata,
370};
371
372void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
373{
374 at91_set_GPIO_periph(AT91_PIN_PB4, 1); /* TWD (SDA) */
375 at91_set_multi_drive(AT91_PIN_PB4, 1);
376
377 at91_set_GPIO_periph(AT91_PIN_PB5, 1); /* TWCK (SCL) */
378 at91_set_multi_drive(AT91_PIN_PB5, 1);
379
380 i2c_register_board_info(0, devices, nr_devices);
381 platform_device_register(&at91cap9_twi_device);
382}
383
384#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
385
386static struct resource twi_resources[] = {
387 [0] = {
388 .start = AT91CAP9_BASE_TWI,
389 .end = AT91CAP9_BASE_TWI + SZ_16K - 1,
390 .flags = IORESOURCE_MEM,
391 },
392 [1] = {
393 .start = AT91CAP9_ID_TWI,
394 .end = AT91CAP9_ID_TWI,
395 .flags = IORESOURCE_IRQ,
396 },
397};
398
399static struct platform_device at91cap9_twi_device = {
400 .name = "at91_i2c",
401 .id = -1,
402 .resource = twi_resources,
403 .num_resources = ARRAY_SIZE(twi_resources),
404};
405
406void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
407{
408 /* pins used for TWI interface */
409 at91_set_B_periph(AT91_PIN_PB4, 0); /* TWD */
410 at91_set_multi_drive(AT91_PIN_PB4, 1);
411
412 at91_set_B_periph(AT91_PIN_PB5, 0); /* TWCK */
413 at91_set_multi_drive(AT91_PIN_PB5, 1);
414
415 i2c_register_board_info(0, devices, nr_devices);
416 platform_device_register(&at91cap9_twi_device);
417}
418#else
419void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
420#endif
421
422/* --------------------------------------------------------------------
423 * SPI
424 * -------------------------------------------------------------------- */
425
426#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
427static u64 spi_dmamask = DMA_BIT_MASK(32);
428
429static struct resource spi0_resources[] = {
430 [0] = {
431 .start = AT91CAP9_BASE_SPI0,
432 .end = AT91CAP9_BASE_SPI0 + SZ_16K - 1,
433 .flags = IORESOURCE_MEM,
434 },
435 [1] = {
436 .start = AT91CAP9_ID_SPI0,
437 .end = AT91CAP9_ID_SPI0,
438 .flags = IORESOURCE_IRQ,
439 },
440};
441
442static struct platform_device at91cap9_spi0_device = {
443 .name = "atmel_spi",
444 .id = 0,
445 .dev = {
446 .dma_mask = &spi_dmamask,
447 .coherent_dma_mask = DMA_BIT_MASK(32),
448 },
449 .resource = spi0_resources,
450 .num_resources = ARRAY_SIZE(spi0_resources),
451};
452
453static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA5, AT91_PIN_PA3, AT91_PIN_PD0, AT91_PIN_PD1 };
454
455static struct resource spi1_resources[] = {
456 [0] = {
457 .start = AT91CAP9_BASE_SPI1,
458 .end = AT91CAP9_BASE_SPI1 + SZ_16K - 1,
459 .flags = IORESOURCE_MEM,
460 },
461 [1] = {
462 .start = AT91CAP9_ID_SPI1,
463 .end = AT91CAP9_ID_SPI1,
464 .flags = IORESOURCE_IRQ,
465 },
466};
467
468static struct platform_device at91cap9_spi1_device = {
469 .name = "atmel_spi",
470 .id = 1,
471 .dev = {
472 .dma_mask = &spi_dmamask,
473 .coherent_dma_mask = DMA_BIT_MASK(32),
474 },
475 .resource = spi1_resources,
476 .num_resources = ARRAY_SIZE(spi1_resources),
477};
478
479static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB15, AT91_PIN_PB16, AT91_PIN_PB17, AT91_PIN_PB18 };
480
481void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
482{
483 int i;
484 unsigned long cs_pin;
485 short enable_spi0 = 0;
486 short enable_spi1 = 0;
487
488 /* Choose SPI chip-selects */
489 for (i = 0; i < nr_devices; i++) {
490 if (devices[i].controller_data)
491 cs_pin = (unsigned long) devices[i].controller_data;
492 else if (devices[i].bus_num == 0)
493 cs_pin = spi0_standard_cs[devices[i].chip_select];
494 else
495 cs_pin = spi1_standard_cs[devices[i].chip_select];
496
497 if (devices[i].bus_num == 0)
498 enable_spi0 = 1;
499 else
500 enable_spi1 = 1;
501
502 /* enable chip-select pin */
503 at91_set_gpio_output(cs_pin, 1);
504
505 /* pass chip-select pin to driver */
506 devices[i].controller_data = (void *) cs_pin;
507 }
508
509 spi_register_board_info(devices, nr_devices);
510
511 /* Configure SPI bus(es) */
512 if (enable_spi0) {
513 at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
514 at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
515 at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
516
517 at91_clock_associate("spi0_clk", &at91cap9_spi0_device.dev, "spi_clk");
518 platform_device_register(&at91cap9_spi0_device);
519 }
520 if (enable_spi1) {
521 at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */
522 at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */
523 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */
524
525 at91_clock_associate("spi1_clk", &at91cap9_spi1_device.dev, "spi_clk");
526 platform_device_register(&at91cap9_spi1_device);
527 }
528}
529#else
530void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
531#endif
532
533
534/* --------------------------------------------------------------------
535 * RTT
536 * -------------------------------------------------------------------- */
537
538static struct platform_device at91cap9_rtt_device = {
539 .name = "at91_rtt",
540 .id = -1,
541 .num_resources = 0,
542};
543
544static void __init at91_add_device_rtt(void)
545{
546 platform_device_register(&at91cap9_rtt_device);
547}
548
549
550/* --------------------------------------------------------------------
551 * Watchdog
552 * -------------------------------------------------------------------- */
553
554#if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE)
555static struct platform_device at91cap9_wdt_device = {
556 .name = "at91_wdt",
557 .id = -1,
558 .num_resources = 0,
559};
560
561static void __init at91_add_device_watchdog(void)
562{
563 platform_device_register(&at91cap9_wdt_device);
564}
565#else
566static void __init at91_add_device_watchdog(void) {}
567#endif
568
569
570/* --------------------------------------------------------------------
571 * AC97
572 * -------------------------------------------------------------------- */
573
574#if defined(CONFIG_SND_AT91_AC97) || defined(CONFIG_SND_AT91_AC97_MODULE)
575static u64 ac97_dmamask = DMA_BIT_MASK(32);
576static struct atmel_ac97_data ac97_data;
577
578static struct resource ac97_resources[] = {
579 [0] = {
580 .start = AT91CAP9_BASE_AC97C,
581 .end = AT91CAP9_BASE_AC97C + SZ_16K - 1,
582 .flags = IORESOURCE_MEM,
583 },
584 [1] = {
585 .start = AT91CAP9_ID_AC97C,
586 .end = AT91CAP9_ID_AC97C,
587 .flags = IORESOURCE_IRQ,
588 },
589};
590
591static struct platform_device at91cap9_ac97_device = {
592 .name = "ac97c",
593 .id = 1,
594 .dev = {
595 .dma_mask = &ac97_dmamask,
596 .coherent_dma_mask = DMA_BIT_MASK(32),
597 .platform_data = &ac97_data,
598 },
599 .resource = ac97_resources,
600 .num_resources = ARRAY_SIZE(ac97_resources),
601};
602
603void __init at91_add_device_ac97(struct atmel_ac97_data *data)
604{
605 if (!data)
606 return;
607
608 at91_set_A_periph(AT91_PIN_PA6, 0); /* AC97FS */
609 at91_set_A_periph(AT91_PIN_PA7, 0); /* AC97CK */
610 at91_set_A_periph(AT91_PIN_PA8, 0); /* AC97TX */
611 at91_set_A_periph(AT91_PIN_PA9, 0); /* AC97RX */
612
613 /* reset */
614 if (data->reset_pin)
615 at91_set_gpio_output(data->reset_pin, 0);
616
617 ac97_data = *data;
618 platform_device_register(&at91cap9_ac97_device);
619}
620#else
621void __init at91_add_device_ac97(struct atmel_ac97_data *data) {}
622#endif
623
624
625/* --------------------------------------------------------------------
626 * LCD Controller
627 * -------------------------------------------------------------------- */
628
629#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
630static u64 lcdc_dmamask = DMA_BIT_MASK(32);
631static struct atmel_lcdfb_info lcdc_data;
632
633static struct resource lcdc_resources[] = {
634 [0] = {
635 .start = AT91CAP9_LCDC_BASE,
636 .end = AT91CAP9_LCDC_BASE + SZ_4K - 1,
637 .flags = IORESOURCE_MEM,
638 },
639 [1] = {
640 .start = AT91CAP9_ID_LCDC,
641 .end = AT91CAP9_ID_LCDC,
642 .flags = IORESOURCE_IRQ,
643 },
644};
645
646static struct platform_device at91_lcdc_device = {
647 .name = "atmel_lcdfb",
648 .id = 0,
649 .dev = {
650 .dma_mask = &lcdc_dmamask,
651 .coherent_dma_mask = DMA_BIT_MASK(32),
652 .platform_data = &lcdc_data,
653 },
654 .resource = lcdc_resources,
655 .num_resources = ARRAY_SIZE(lcdc_resources),
656};
657
658void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
659{
660 if (!data)
661 return;
662
663 at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
664 at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
665 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
666 at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
667 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
668 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
669 at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
670 at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
671 at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
672 at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
673 at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
674 at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
675 at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
676 at91_set_A_periph(AT91_PIN_PC17, 0); /* LCDD13 */
677 at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
678 at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
679 at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
680 at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
681 at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
682 at91_set_A_periph(AT91_PIN_PC25, 0); /* LCDD21 */
683 at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
684 at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
685
686 lcdc_data = *data;
687 platform_device_register(&at91_lcdc_device);
688}
689#else
690void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
691#endif
692
693
694/* --------------------------------------------------------------------
695 * SSC -- Synchronous Serial Controller
696 * -------------------------------------------------------------------- */
697
698#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
699static u64 ssc0_dmamask = DMA_BIT_MASK(32);
700
701static struct resource ssc0_resources[] = {
702 [0] = {
703 .start = AT91CAP9_BASE_SSC0,
704 .end = AT91CAP9_BASE_SSC0 + SZ_16K - 1,
705 .flags = IORESOURCE_MEM,
706 },
707 [1] = {
708 .start = AT91CAP9_ID_SSC0,
709 .end = AT91CAP9_ID_SSC0,
710 .flags = IORESOURCE_IRQ,
711 },
712};
713
714static struct platform_device at91cap9_ssc0_device = {
715 .name = "ssc",
716 .id = 0,
717 .dev = {
718 .dma_mask = &ssc0_dmamask,
719 .coherent_dma_mask = DMA_BIT_MASK(32),
720 },
721 .resource = ssc0_resources,
722 .num_resources = ARRAY_SIZE(ssc0_resources),
723};
724
725static inline void configure_ssc0_pins(unsigned pins)
726{
727 if (pins & ATMEL_SSC_TF)
728 at91_set_A_periph(AT91_PIN_PB0, 1);
729 if (pins & ATMEL_SSC_TK)
730 at91_set_A_periph(AT91_PIN_PB1, 1);
731 if (pins & ATMEL_SSC_TD)
732 at91_set_A_periph(AT91_PIN_PB2, 1);
733 if (pins & ATMEL_SSC_RD)
734 at91_set_A_periph(AT91_PIN_PB3, 1);
735 if (pins & ATMEL_SSC_RK)
736 at91_set_A_periph(AT91_PIN_PB4, 1);
737 if (pins & ATMEL_SSC_RF)
738 at91_set_A_periph(AT91_PIN_PB5, 1);
739}
740
741static u64 ssc1_dmamask = DMA_BIT_MASK(32);
742
743static struct resource ssc1_resources[] = {
744 [0] = {
745 .start = AT91CAP9_BASE_SSC1,
746 .end = AT91CAP9_BASE_SSC1 + SZ_16K - 1,
747 .flags = IORESOURCE_MEM,
748 },
749 [1] = {
750 .start = AT91CAP9_ID_SSC1,
751 .end = AT91CAP9_ID_SSC1,
752 .flags = IORESOURCE_IRQ,
753 },
754};
755
756static struct platform_device at91cap9_ssc1_device = {
757 .name = "ssc",
758 .id = 1,
759 .dev = {
760 .dma_mask = &ssc1_dmamask,
761 .coherent_dma_mask = DMA_BIT_MASK(32),
762 },
763 .resource = ssc1_resources,
764 .num_resources = ARRAY_SIZE(ssc1_resources),
765};
766
767static inline void configure_ssc1_pins(unsigned pins)
768{
769 if (pins & ATMEL_SSC_TF)
770 at91_set_A_periph(AT91_PIN_PB6, 1);
771 if (pins & ATMEL_SSC_TK)
772 at91_set_A_periph(AT91_PIN_PB7, 1);
773 if (pins & ATMEL_SSC_TD)
774 at91_set_A_periph(AT91_PIN_PB8, 1);
775 if (pins & ATMEL_SSC_RD)
776 at91_set_A_periph(AT91_PIN_PB9, 1);
777 if (pins & ATMEL_SSC_RK)
778 at91_set_A_periph(AT91_PIN_PB10, 1);
779 if (pins & ATMEL_SSC_RF)
780 at91_set_A_periph(AT91_PIN_PB11, 1);
781}
782
783/*
784 * SSC controllers are accessed through library code, instead of any
785 * kind of all-singing/all-dancing driver. For example one could be
786 * used by a particular I2S audio codec's driver, while another one
787 * on the same system might be used by a custom data capture driver.
788 */
789void __init at91_add_device_ssc(unsigned id, unsigned pins)
790{
791 struct platform_device *pdev;
792
793 /*
794 * NOTE: caller is responsible for passing information matching
795 * "pins" to whatever will be using each particular controller.
796 */
797 switch (id) {
798 case AT91CAP9_ID_SSC0:
799 pdev = &at91cap9_ssc0_device;
800 configure_ssc0_pins(pins);
801 at91_clock_associate("ssc0_clk", &pdev->dev, "ssc");
802 break;
803 case AT91CAP9_ID_SSC1:
804 pdev = &at91cap9_ssc1_device;
805 configure_ssc1_pins(pins);
806 at91_clock_associate("ssc1_clk", &pdev->dev, "ssc");
807 break;
808 default:
809 return;
810 }
811
812 platform_device_register(pdev);
813}
814
815#else
816void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
817#endif
818
819
820/* --------------------------------------------------------------------
821 * UART
822 * -------------------------------------------------------------------- */
823
824#if defined(CONFIG_SERIAL_ATMEL)
825static struct resource dbgu_resources[] = {
826 [0] = {
827 .start = AT91_VA_BASE_SYS + AT91_DBGU,
828 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
829 .flags = IORESOURCE_MEM,
830 },
831 [1] = {
832 .start = AT91_ID_SYS,
833 .end = AT91_ID_SYS,
834 .flags = IORESOURCE_IRQ,
835 },
836};
837
838static struct atmel_uart_data dbgu_data = {
839 .use_dma_tx = 0,
840 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
841 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
842};
843
844static u64 dbgu_dmamask = DMA_BIT_MASK(32);
845
846static struct platform_device at91cap9_dbgu_device = {
847 .name = "atmel_usart",
848 .id = 0,
849 .dev = {
850 .dma_mask = &dbgu_dmamask,
851 .coherent_dma_mask = DMA_BIT_MASK(32),
852 .platform_data = &dbgu_data,
853 },
854 .resource = dbgu_resources,
855 .num_resources = ARRAY_SIZE(dbgu_resources),
856};
857
858static inline void configure_dbgu_pins(void)
859{
860 at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
861 at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
862}
863
864static struct resource uart0_resources[] = {
865 [0] = {
866 .start = AT91CAP9_BASE_US0,
867 .end = AT91CAP9_BASE_US0 + SZ_16K - 1,
868 .flags = IORESOURCE_MEM,
869 },
870 [1] = {
871 .start = AT91CAP9_ID_US0,
872 .end = AT91CAP9_ID_US0,
873 .flags = IORESOURCE_IRQ,
874 },
875};
876
877static struct atmel_uart_data uart0_data = {
878 .use_dma_tx = 1,
879 .use_dma_rx = 1,
880};
881
882static u64 uart0_dmamask = DMA_BIT_MASK(32);
883
884static struct platform_device at91cap9_uart0_device = {
885 .name = "atmel_usart",
886 .id = 1,
887 .dev = {
888 .dma_mask = &uart0_dmamask,
889 .coherent_dma_mask = DMA_BIT_MASK(32),
890 .platform_data = &uart0_data,
891 },
892 .resource = uart0_resources,
893 .num_resources = ARRAY_SIZE(uart0_resources),
894};
895
896static inline void configure_usart0_pins(unsigned pins)
897{
898 at91_set_A_periph(AT91_PIN_PA22, 1); /* TXD0 */
899 at91_set_A_periph(AT91_PIN_PA23, 0); /* RXD0 */
900
901 if (pins & ATMEL_UART_RTS)
902 at91_set_A_periph(AT91_PIN_PA24, 0); /* RTS0 */
903 if (pins & ATMEL_UART_CTS)
904 at91_set_A_periph(AT91_PIN_PA25, 0); /* CTS0 */
905}
906
907static struct resource uart1_resources[] = {
908 [0] = {
909 .start = AT91CAP9_BASE_US1,
910 .end = AT91CAP9_BASE_US1 + SZ_16K - 1,
911 .flags = IORESOURCE_MEM,
912 },
913 [1] = {
914 .start = AT91CAP9_ID_US1,
915 .end = AT91CAP9_ID_US1,
916 .flags = IORESOURCE_IRQ,
917 },
918};
919
920static struct atmel_uart_data uart1_data = {
921 .use_dma_tx = 1,
922 .use_dma_rx = 1,
923};
924
925static u64 uart1_dmamask = DMA_BIT_MASK(32);
926
927static struct platform_device at91cap9_uart1_device = {
928 .name = "atmel_usart",
929 .id = 2,
930 .dev = {
931 .dma_mask = &uart1_dmamask,
932 .coherent_dma_mask = DMA_BIT_MASK(32),
933 .platform_data = &uart1_data,
934 },
935 .resource = uart1_resources,
936 .num_resources = ARRAY_SIZE(uart1_resources),
937};
938
939static inline void configure_usart1_pins(unsigned pins)
940{
941 at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
942 at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
943
944 if (pins & ATMEL_UART_RTS)
945 at91_set_B_periph(AT91_PIN_PD7, 0); /* RTS1 */
946 if (pins & ATMEL_UART_CTS)
947 at91_set_B_periph(AT91_PIN_PD8, 0); /* CTS1 */
948}
949
950static struct resource uart2_resources[] = {
951 [0] = {
952 .start = AT91CAP9_BASE_US2,
953 .end = AT91CAP9_BASE_US2 + SZ_16K - 1,
954 .flags = IORESOURCE_MEM,
955 },
956 [1] = {
957 .start = AT91CAP9_ID_US2,
958 .end = AT91CAP9_ID_US2,
959 .flags = IORESOURCE_IRQ,
960 },
961};
962
963static struct atmel_uart_data uart2_data = {
964 .use_dma_tx = 1,
965 .use_dma_rx = 1,
966};
967
968static u64 uart2_dmamask = DMA_BIT_MASK(32);
969
970static struct platform_device at91cap9_uart2_device = {
971 .name = "atmel_usart",
972 .id = 3,
973 .dev = {
974 .dma_mask = &uart2_dmamask,
975 .coherent_dma_mask = DMA_BIT_MASK(32),
976 .platform_data = &uart2_data,
977 },
978 .resource = uart2_resources,
979 .num_resources = ARRAY_SIZE(uart2_resources),
980};
981
982static inline void configure_usart2_pins(unsigned pins)
983{
984 at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
985 at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
986
987 if (pins & ATMEL_UART_RTS)
988 at91_set_B_periph(AT91_PIN_PD5, 0); /* RTS2 */
989 if (pins & ATMEL_UART_CTS)
990 at91_set_B_periph(AT91_PIN_PD6, 0); /* CTS2 */
991}
992
993static struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
994struct platform_device *atmel_default_console_device; /* the serial console device */
995
996void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
997{
998 struct platform_device *pdev;
999
1000 switch (id) {
1001 case 0: /* DBGU */
1002 pdev = &at91cap9_dbgu_device;
1003 configure_dbgu_pins();
1004 at91_clock_associate("mck", &pdev->dev, "usart");
1005 break;
1006 case AT91CAP9_ID_US0:
1007 pdev = &at91cap9_uart0_device;
1008 configure_usart0_pins(pins);
1009 at91_clock_associate("usart0_clk", &pdev->dev, "usart");
1010 break;
1011 case AT91CAP9_ID_US1:
1012 pdev = &at91cap9_uart1_device;
1013 configure_usart1_pins(pins);
1014 at91_clock_associate("usart1_clk", &pdev->dev, "usart");
1015 break;
1016 case AT91CAP9_ID_US2:
1017 pdev = &at91cap9_uart2_device;
1018 configure_usart2_pins(pins);
1019 at91_clock_associate("usart2_clk", &pdev->dev, "usart");
1020 break;
1021 default:
1022 return;
1023 }
1024 pdev->id = portnr; /* update to mapped ID */
1025
1026 if (portnr < ATMEL_MAX_UART)
1027 at91_uarts[portnr] = pdev;
1028}
1029
1030void __init at91_set_serial_console(unsigned portnr)
1031{
1032 if (portnr < ATMEL_MAX_UART)
1033 atmel_default_console_device = at91_uarts[portnr];
1034 if (!atmel_default_console_device)
1035 printk(KERN_INFO "AT91: No default serial console defined.\n");
1036}
1037
1038void __init at91_add_device_serial(void)
1039{
1040 int i;
1041
1042 for (i = 0; i < ATMEL_MAX_UART; i++) {
1043 if (at91_uarts[i])
1044 platform_device_register(at91_uarts[i]);
1045 }
1046}
1047#else
1048void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1049void __init at91_set_serial_console(unsigned portnr) {}
1050void __init at91_add_device_serial(void) {}
1051#endif
1052
1053
1054/* -------------------------------------------------------------------- */
1055/*
1056 * These devices are always present and don't need any board-specific
1057 * setup.
1058 */
1059static int __init at91_add_standard_devices(void)
1060{
1061 at91_add_device_rtt();
1062 at91_add_device_watchdog();
1063 return 0;
1064}
1065
1066arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 57c3b647ce83..ec76eeaafd45 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -574,6 +574,8 @@ int __init at91_clock_init(unsigned long main_clock)
574 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263()) { 574 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263()) {
575 uhpck.pmc_mask = AT91SAM926x_PMC_UHP; 575 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
576 udpck.pmc_mask = AT91SAM926x_PMC_UDP; 576 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
577 } else if (cpu_is_at91cap9()) {
578 uhpck.pmc_mask = AT91CAP9_PMC_UHP;
577 } 579 }
578 at91_sys_write(AT91_CKGR_PLLBR, 0); 580 at91_sys_write(AT91_CKGR_PLLBR, 0);
579 581
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 77d4c0a37842..b5daf7f5e011 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -15,6 +15,7 @@ extern void __init at91sam9261_initialize(unsigned long main_clock);
15extern void __init at91sam9263_initialize(unsigned long main_clock); 15extern void __init at91sam9263_initialize(unsigned long main_clock);
16extern void __init at91sam9rl_initialize(unsigned long main_clock); 16extern void __init at91sam9rl_initialize(unsigned long main_clock);
17extern void __init at91x40_initialize(unsigned long main_clock); 17extern void __init at91x40_initialize(unsigned long main_clock);
18extern void __init at91cap9_initialize(unsigned long main_clock);
18 19
19 /* Interrupts */ 20 /* Interrupts */
20extern void __init at91rm9200_init_interrupts(unsigned int priority[]); 21extern void __init at91rm9200_init_interrupts(unsigned int priority[]);
@@ -23,6 +24,7 @@ extern void __init at91sam9261_init_interrupts(unsigned int priority[]);
23extern void __init at91sam9263_init_interrupts(unsigned int priority[]); 24extern void __init at91sam9263_init_interrupts(unsigned int priority[]);
24extern void __init at91sam9rl_init_interrupts(unsigned int priority[]); 25extern void __init at91sam9rl_init_interrupts(unsigned int priority[]);
25extern void __init at91x40_init_interrupts(unsigned int priority[]); 26extern void __init at91x40_init_interrupts(unsigned int priority[]);
27extern void __init at91cap9_init_interrupts(unsigned int priority[]);
26extern void __init at91_aic_init(unsigned int priority[]); 28extern void __init at91_aic_init(unsigned int priority[]);
27 29
28 /* Timer */ 30 /* Timer */
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 98cb61482917..4b120cc36135 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -80,6 +80,11 @@ static int at91_pm_verify_clocks(void)
80 pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n"); 80 pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n");
81 return 0; 81 return 0;
82 } 82 }
83 } else if (cpu_is_at91cap9()) {
84 if ((scsr & AT91CAP9_PMC_UHP) != 0) {
85 pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n");
86 return 0;
87 }
83 } 88 }
84 89
85#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS 90#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 7868f4dc1d00..1bf2a7bfe09d 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -171,8 +171,8 @@ config CPU_ARM925T
171# ARM926T 171# ARM926T
172config CPU_ARM926T 172config CPU_ARM926T
173 bool "Support ARM926T processor" 173 bool "Support ARM926T processor"
174 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_NS9XXX || ARCH_DAVINCI 174 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI
175 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_NS9XXX || ARCH_DAVINCI 175 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI
176 select CPU_32v5 176 select CPU_32v5
177 select CPU_ABRT_EV5TJ 177 select CPU_ABRT_EV5TJ
178 select CPU_CACHE_VIVT 178 select CPU_CACHE_VIVT
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 9af05a2f4af3..a6728661c416 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -212,7 +212,7 @@ config MII
212 212
213config MACB 213config MACB
214 tristate "Atmel MACB support" 214 tristate "Atmel MACB support"
215 depends on AVR32 || ARCH_AT91SAM9260 || ARCH_AT91SAM9263 215 depends on AVR32 || ARCH_AT91SAM9260 || ARCH_AT91SAM9263 || ARCH_AT91CAP9
216 select PHYLIB 216 select PHYLIB
217 help 217 help
218 The Atmel MACB ethernet interface is found on many AT32 and AT91 218 The Atmel MACB ethernet interface is found on many AT32 and AT91
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index f81d08d6538b..77a3759d6fc7 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -308,7 +308,7 @@ config USB_S3C2410_DEBUG
308 308
309config USB_GADGET_AT91 309config USB_GADGET_AT91
310 boolean "AT91 USB Device Port" 310 boolean "AT91 USB Device Port"
311 depends on ARCH_AT91 && !ARCH_AT91SAM9RL 311 depends on ARCH_AT91 && !ARCH_AT91SAM9RL && !ARCH_AT91CAP9
312 select USB_GADGET_SELECTED 312 select USB_GADGET_SELECTED
313 help 313 help
314 Many Atmel AT91 processors (such as the AT91RM2000) have a 314 Many Atmel AT91 processors (such as the AT91RM2000) have a
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 5b3dbcfcda48..758435f8a6f8 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -889,7 +889,7 @@ config FB_S1D13XXX
889 889
890config FB_ATMEL 890config FB_ATMEL
891 tristate "AT91/AT32 LCD Controller support" 891 tristate "AT91/AT32 LCD Controller support"
892 depends on FB && (ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || AVR32) 892 depends on FB && (ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || AVR32)
893 select FB_CFB_FILLRECT 893 select FB_CFB_FILLRECT
894 select FB_CFB_COPYAREA 894 select FB_CFB_COPYAREA
895 select FB_CFB_IMAGEBLIT 895 select FB_CFB_IMAGEBLIT
diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
index 7c30cc8df71e..f8e711147501 100644
--- a/drivers/video/atmel_lcdfb.c
+++ b/drivers/video/atmel_lcdfb.c
@@ -30,7 +30,7 @@
30#define ATMEL_LCDC_CVAL_DEFAULT 0xc8 30#define ATMEL_LCDC_CVAL_DEFAULT 0xc8
31#define ATMEL_LCDC_DMA_BURST_LEN 8 31#define ATMEL_LCDC_DMA_BURST_LEN 8
32 32
33#if defined(CONFIG_ARCH_AT91SAM9263) 33#if defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91CAP9)
34#define ATMEL_LCDC_FIFO_SIZE 2048 34#define ATMEL_LCDC_FIFO_SIZE 2048
35#else 35#else
36#define ATMEL_LCDC_FIFO_SIZE 512 36#define ATMEL_LCDC_FIFO_SIZE 512
diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h
index 34804eaab4f2..52cd8e5dabc9 100644
--- a/include/asm-arm/arch-at91/at91_pmc.h
+++ b/include/asm-arm/arch-at91/at91_pmc.h
@@ -25,6 +25,7 @@
25#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ 25#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
26#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ 26#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
27#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ 27#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
28#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */
28#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ 29#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
29#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ 30#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
30#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ 31#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
@@ -37,7 +38,7 @@
37#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ 38#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
38#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ 39#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
39 40
40#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL only] */ 41#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */
41 42
42#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ 43#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
43#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ 44#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
@@ -54,6 +55,10 @@
54#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ 55#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
55#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ 56#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
56#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ 57#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
58#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */
59#define AT91_PMC_USBDIV_1 (0 << 28)
60#define AT91_PMC_USBDIV_2 (1 << 28)
61#define AT91_PMC_USBDIV_4 (2 << 28)
57#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ 62#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
58 63
59#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ 64#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
diff --git a/include/asm-arm/arch-at91/at91cap9.h b/include/asm-arm/arch-at91/at91cap9.h
new file mode 100644
index 000000000000..73e1fcf4a0aa
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91cap9.h
@@ -0,0 +1,121 @@
1/*
2 * include/asm-arm/arch-at91/at91cap9.h
3 *
4 * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5 * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2007 Atmel Corporation.
7 *
8 * Common definitions.
9 * Based on AT91CAP9 datasheet revision B (Preliminary).
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17#ifndef AT91CAP9_H
18#define AT91CAP9_H
19
20/*
21 * Peripheral identifiers/interrupts.
22 */
23#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
24#define AT91_ID_SYS 1 /* System Peripherals */
25#define AT91CAP9_ID_PIOABCD 2 /* Parallel IO Controller A, B, C and D */
26#define AT91CAP9_ID_MPB0 3 /* MP Block Peripheral 0 */
27#define AT91CAP9_ID_MPB1 4 /* MP Block Peripheral 1 */
28#define AT91CAP9_ID_MPB2 5 /* MP Block Peripheral 2 */
29#define AT91CAP9_ID_MPB3 6 /* MP Block Peripheral 3 */
30#define AT91CAP9_ID_MPB4 7 /* MP Block Peripheral 4 */
31#define AT91CAP9_ID_US0 8 /* USART 0 */
32#define AT91CAP9_ID_US1 9 /* USART 1 */
33#define AT91CAP9_ID_US2 10 /* USART 2 */
34#define AT91CAP9_ID_MCI0 11 /* Multimedia Card Interface 0 */
35#define AT91CAP9_ID_MCI1 12 /* Multimedia Card Interface 1 */
36#define AT91CAP9_ID_CAN 13 /* CAN */
37#define AT91CAP9_ID_TWI 14 /* Two-Wire Interface */
38#define AT91CAP9_ID_SPI0 15 /* Serial Peripheral Interface 0 */
39#define AT91CAP9_ID_SPI1 16 /* Serial Peripheral Interface 0 */
40#define AT91CAP9_ID_SSC0 17 /* Serial Synchronous Controller 0 */
41#define AT91CAP9_ID_SSC1 18 /* Serial Synchronous Controller 1 */
42#define AT91CAP9_ID_AC97C 19 /* AC97 Controller */
43#define AT91CAP9_ID_TCB 20 /* Timer Counter 0, 1 and 2 */
44#define AT91CAP9_ID_PWMC 21 /* Pulse Width Modulation Controller */
45#define AT91CAP9_ID_EMAC 22 /* Ethernet */
46#define AT91CAP9_ID_AESTDES 23 /* Advanced Encryption Standard, Triple DES */
47#define AT91CAP9_ID_ADC 24 /* Analog-to-Digital Converter */
48#define AT91CAP9_ID_ISI 25 /* Image Sensor Interface */
49#define AT91CAP9_ID_LCDC 26 /* LCD Controller */
50#define AT91CAP9_ID_DMA 27 /* DMA Controller */
51#define AT91CAP9_ID_UDPHS 28 /* USB High Speed Device Port */
52#define AT91CAP9_ID_UHP 29 /* USB Host Port */
53#define AT91CAP9_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
54#define AT91CAP9_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
55
56/*
57 * User Peripheral physical base addresses.
58 */
59#define AT91CAP9_BASE_UDPHS 0xfff78000
60#define AT91CAP9_BASE_TCB0 0xfff7c000
61#define AT91CAP9_BASE_TC0 0xfff7c000
62#define AT91CAP9_BASE_TC1 0xfff7c040
63#define AT91CAP9_BASE_TC2 0xfff7c080
64#define AT91CAP9_BASE_MCI0 0xfff80000
65#define AT91CAP9_BASE_MCI1 0xfff84000
66#define AT91CAP9_BASE_TWI 0xfff88000
67#define AT91CAP9_BASE_US0 0xfff8c000
68#define AT91CAP9_BASE_US1 0xfff90000
69#define AT91CAP9_BASE_US2 0xfff94000
70#define AT91CAP9_BASE_SSC0 0xfff98000
71#define AT91CAP9_BASE_SSC1 0xfff9c000
72#define AT91CAP9_BASE_AC97C 0xfffa0000
73#define AT91CAP9_BASE_SPI0 0xfffa4000
74#define AT91CAP9_BASE_SPI1 0xfffa8000
75#define AT91CAP9_BASE_CAN 0xfffac000
76#define AT91CAP9_BASE_PWMC 0xfffb8000
77#define AT91CAP9_BASE_EMAC 0xfffbc000
78#define AT91CAP9_BASE_ADC 0xfffc0000
79#define AT91CAP9_BASE_ISI 0xfffc4000
80#define AT91_BASE_SYS 0xffffe200
81
82/*
83 * System Peripherals (offset from AT91_BASE_SYS)
84 */
85#define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
86#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS)
87#define AT91_DDRSDRC (0xffffe600 - AT91_BASE_SYS)
88#define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
89#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
90#define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS)
91#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
92#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
93#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
94#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
95#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
96#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
97#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
98#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
99#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
100#define AT91_SHDC (0xfffffd10 - AT91_BASE_SYS)
101#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
102#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
103#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
104#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
105
106/*
107 * Internal Memory.
108 */
109#define AT91CAP9_SRAM_BASE 0x00100000 /* Internal SRAM base address */
110#define AT91CAP9_SRAM_SIZE (32 * SZ_1K) /* Internal SRAM size (32Kb) */
111
112#define AT91CAP9_ROM_BASE 0x00400000 /* Internal ROM base address */
113#define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */
114
115#define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */
116#define AT91CAP9_UDPHS_BASE 0x00600000 /* USB High Speed Device Port */
117#define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */
118
119#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6
120
121#endif
diff --git a/include/asm-arm/arch-at91/at91cap9_matrix.h b/include/asm-arm/arch-at91/at91cap9_matrix.h
new file mode 100644
index 000000000000..a641686b6c3d
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91cap9_matrix.h
@@ -0,0 +1,132 @@
1/*
2 * include/asm-arm/arch-at91/at91cap9_matrix.h
3 *
4 * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5 * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2006 Atmel Corporation.
7 *
8 * Memory Controllers (MATRIX, EBI) - System peripherals registers.
9 * Based on AT91CAP9 datasheet revision B (Preliminary).
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17#ifndef AT91CAP9_MATRIX_H
18#define AT91CAP9_MATRIX_H
19
20#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
21#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
22#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
23#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
24#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
25#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
26#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
27#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
28#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
29#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */
30#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */
31#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */
32#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
33#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
34#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
35#define AT91_MATRIX_ULBT_FOUR (2 << 0)
36#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
37#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
38
39#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
40#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
41#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
42#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
43#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
44#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
45#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
46#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
47#define AT91_MATRIX_SCFG8 (AT91_MATRIX + 0x60) /* Slave Configuration Register 8 */
48#define AT91_MATRIX_SCFG9 (AT91_MATRIX + 0x64) /* Slave Configuration Register 9 */
49#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
50#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
51#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
52#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
53#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
54#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
55#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
56#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
57#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
58
59#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
60#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
61#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
62#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
63#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
64#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
65#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
66#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
67#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
68#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
69#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
70#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
71#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
72#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
73#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
74#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
75#define AT91_MATRIX_PRAS8 (AT91_MATRIX + 0xC0) /* Priority Register A for Slave 8 */
76#define AT91_MATRIX_PRBS8 (AT91_MATRIX + 0xC4) /* Priority Register B for Slave 8 */
77#define AT91_MATRIX_PRAS9 (AT91_MATRIX + 0xC8) /* Priority Register A for Slave 9 */
78#define AT91_MATRIX_PRBS9 (AT91_MATRIX + 0xCC) /* Priority Register B for Slave 9 */
79#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
80#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
81#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
82#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
83#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
84#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
85#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
86#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
87#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
88#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
89#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
90#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
91
92#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
93#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
94#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
95#define AT91_MATRIX_RCB2 (1 << 2)
96#define AT91_MATRIX_RCB3 (1 << 3)
97#define AT91_MATRIX_RCB4 (1 << 4)
98#define AT91_MATRIX_RCB5 (1 << 5)
99#define AT91_MATRIX_RCB6 (1 << 6)
100#define AT91_MATRIX_RCB7 (1 << 7)
101#define AT91_MATRIX_RCB8 (1 << 8)
102#define AT91_MATRIX_RCB9 (1 << 9)
103#define AT91_MATRIX_RCB10 (1 << 10)
104#define AT91_MATRIX_RCB11 (1 << 11)
105
106#define AT91_MPBS0_SFR (AT91_MATRIX + 0x114) /* MPBlock Slave 0 Special Function Register */
107#define AT91_MPBS1_SFR (AT91_MATRIX + 0x11C) /* MPBlock Slave 1 Special Function Register */
108
109#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */
110#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
111#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
112#define AT91_MATRIX_EBI_CS1A_BCRAMC (1 << 1)
113#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
114#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
115#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
116#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */
117#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
118#define AT91_MATRIX_EBI_CS4A_SMC_CF1 (1 << 4)
119#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */
120#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
121#define AT91_MATRIX_EBI_CS5A_SMC_CF2 (1 << 5)
122#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
123#define AT91_MATRIX_EBI_DQSPDC (1 << 9) /* Data Qualifier Strobe Pull-Down Configuration */
124#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
125#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
126#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
127
128#define AT91_MPBS2_SFR (AT91_MATRIX + 0x12C) /* MPBlock Slave 2 Special Function Register */
129#define AT91_MPBS3_SFR (AT91_MATRIX + 0x130) /* MPBlock Slave 3 Special Function Register */
130#define AT91_APB_SFR (AT91_MATRIX + 0x134) /* APB Bridge Special Function Register */
131
132#endif
diff --git a/include/asm-arm/arch-at91/at91sam9263_matrix.h b/include/asm-arm/arch-at91/at91sam9263_matrix.h
index 6fc6e4be624e..72f6e668e414 100644
--- a/include/asm-arm/arch-at91/at91sam9263_matrix.h
+++ b/include/asm-arm/arch-at91/at91sam9263_matrix.h
@@ -44,7 +44,7 @@
44#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) 44#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
45#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) 45#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
46#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) 46#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
47#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ 47#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
48#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ 48#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
49#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) 49#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
50#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) 50#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
diff --git a/include/asm-arm/arch-at91/at91sam9rl_matrix.h b/include/asm-arm/arch-at91/at91sam9rl_matrix.h
index b15f11b7c08d..84224174e6a1 100644
--- a/include/asm-arm/arch-at91/at91sam9rl_matrix.h
+++ b/include/asm-arm/arch-at91/at91sam9rl_matrix.h
@@ -38,7 +38,7 @@
38#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) 38#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
39#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) 39#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
40#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) 40#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
41#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ 41#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
42#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ 42#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
43#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) 43#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
44#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) 44#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
diff --git a/include/asm-arm/arch-at91/board.h b/include/asm-arm/arch-at91/board.h
index e88ad8621c17..55b07bd5316c 100644
--- a/include/asm-arm/arch-at91/board.h
+++ b/include/asm-arm/arch-at91/board.h
@@ -72,7 +72,7 @@ struct at91_eth_data {
72}; 72};
73extern void __init at91_add_device_eth(struct at91_eth_data *data); 73extern void __init at91_add_device_eth(struct at91_eth_data *data);
74 74
75#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) 75#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91CAP9)
76#define eth_platform_data at91_eth_data 76#define eth_platform_data at91_eth_data
77#endif 77#endif
78 78
diff --git a/include/asm-arm/arch-at91/cpu.h b/include/asm-arm/arch-at91/cpu.h
index 080cbb401a87..7145166826a2 100644
--- a/include/asm-arm/arch-at91/cpu.h
+++ b/include/asm-arm/arch-at91/cpu.h
@@ -21,13 +21,13 @@
21#define ARCH_ID_AT91SAM9260 0x019803a0 21#define ARCH_ID_AT91SAM9260 0x019803a0
22#define ARCH_ID_AT91SAM9261 0x019703a0 22#define ARCH_ID_AT91SAM9261 0x019703a0
23#define ARCH_ID_AT91SAM9263 0x019607a0 23#define ARCH_ID_AT91SAM9263 0x019607a0
24#define ARCH_ID_AT91SAM9RL64 0x019b03a0
25#define ARCH_ID_AT91CAP9 0x039A03A0
24 26
25#define ARCH_ID_AT91SAM9XE128 0x329973a0 27#define ARCH_ID_AT91SAM9XE128 0x329973a0
26#define ARCH_ID_AT91SAM9XE256 0x329a93a0 28#define ARCH_ID_AT91SAM9XE256 0x329a93a0
27#define ARCH_ID_AT91SAM9XE512 0x329aa3a0 29#define ARCH_ID_AT91SAM9XE512 0x329aa3a0
28 30
29#define ARCH_ID_AT91SAM9RL64 0x019b03a0
30
31#define ARCH_ID_AT91M40800 0x14080044 31#define ARCH_ID_AT91M40800 0x14080044
32#define ARCH_ID_AT91R40807 0x44080746 32#define ARCH_ID_AT91R40807 0x44080746
33#define ARCH_ID_AT91M40807 0x14080745 33#define ARCH_ID_AT91M40807 0x14080745
@@ -81,6 +81,11 @@ static inline unsigned long at91_arch_identify(void)
81#define cpu_is_at91sam9rl() (0) 81#define cpu_is_at91sam9rl() (0)
82#endif 82#endif
83 83
84#ifdef CONFIG_ARCH_AT91CAP9
85#define cpu_is_at91cap9() (at91_cpu_identify() == ARCH_ID_AT91CAP9)
86#else
87#define cpu_is_at91cap9() (0)
88#endif
84 89
85/* 90/*
86 * Since this is ARM, we will never run on any AVR32 CPU. But these 91 * Since this is ARM, we will never run on any AVR32 CPU. But these
diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h
index 8f1cdd38a969..2c826d8247a3 100644
--- a/include/asm-arm/arch-at91/hardware.h
+++ b/include/asm-arm/arch-at91/hardware.h
@@ -26,6 +26,8 @@
26#include <asm/arch/at91sam9263.h> 26#include <asm/arch/at91sam9263.h>
27#elif defined(CONFIG_ARCH_AT91SAM9RL) 27#elif defined(CONFIG_ARCH_AT91SAM9RL)
28#include <asm/arch/at91sam9rl.h> 28#include <asm/arch/at91sam9rl.h>
29#elif defined(CONFIG_ARCH_AT91CAP9)
30#include <asm/arch/at91cap9.h>
29#elif defined(CONFIG_ARCH_AT91X40) 31#elif defined(CONFIG_ARCH_AT91X40)
30#include <asm/arch/at91x40.h> 32#include <asm/arch/at91x40.h>
31#else 33#else
diff --git a/include/asm-arm/arch-at91/timex.h b/include/asm-arm/arch-at91/timex.h
index a310698fb4da..f1933b0fa43f 100644
--- a/include/asm-arm/arch-at91/timex.h
+++ b/include/asm-arm/arch-at91/timex.h
@@ -42,6 +42,11 @@
42#define AT91SAM9_MASTER_CLOCK 100000000 42#define AT91SAM9_MASTER_CLOCK 100000000
43#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) 43#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
44 44
45#elif defined(CONFIG_ARCH_AT91CAP9)
46
47#define AT91CAP9_MASTER_CLOCK 100000000
48#define CLOCK_TICK_RATE (AT91CAP9_MASTER_CLOCK/16)
49
45#elif defined(CONFIG_ARCH_AT91X40) 50#elif defined(CONFIG_ARCH_AT91X40)
46 51
47#define AT91X40_MASTER_CLOCK 40000000 52#define AT91X40_MASTER_CLOCK 40000000
diff --git a/include/asm-avr32/arch-at32ap/cpu.h b/include/asm-avr32/arch-at32ap/cpu.h
index 0dc20261c1ea..44d0bfa1f409 100644
--- a/include/asm-avr32/arch-at32ap/cpu.h
+++ b/include/asm-avr32/arch-at32ap/cpu.h
@@ -30,5 +30,6 @@
30#define cpu_is_at91sam9261() (0) 30#define cpu_is_at91sam9261() (0)
31#define cpu_is_at91sam9263() (0) 31#define cpu_is_at91sam9263() (0)
32#define cpu_is_at91sam9rl() (0) 32#define cpu_is_at91sam9rl() (0)
33#define cpu_is_at91cap9() (0)
33 34
34#endif /* __ASM_ARCH_CPU_H */ 35#endif /* __ASM_ARCH_CPU_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-13 22:37:43 -0500