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authorKumar Gala <galak@freescale.com>2005-09-23 15:08:58 -0400
committerPaul Mackerras <paulus@samba.org>2005-09-28 01:42:53 -0400
commit10b35d9978ac35556aec0d2642055742d8941488 (patch)
tree7c59c62e2840d7d9971076e1acccaa0cadd678b8
parenta559c91d77c3220be521453bd23815e1e1980a82 (diff)
[PATCH] powerpc: merged asm/cputable.h
Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat
-rw-r--r--arch/ppc/kernel/cputable.c399
-rw-r--r--arch/ppc64/kernel/cputable.c82
-rw-r--r--include/asm-powerpc/cputable.h442
-rw-r--r--include/asm-ppc/cputable.h128
-rw-r--r--include/asm-ppc/mmu_context.h6
-rw-r--r--include/asm-ppc64/cputable.h167
6 files changed, 547 insertions, 677 deletions
diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c
index 546e1ea4cafa..97663d5d96ca 100644
--- a/arch/ppc/kernel/cputable.c
+++ b/arch/ppc/kernel/cputable.c
@@ -42,17 +42,6 @@ extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spe
42#define COMMON_PPC (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \ 42#define COMMON_PPC (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
43 PPC_FEATURE_HAS_MMU) 43 PPC_FEATURE_HAS_MMU)
44 44
45/* We only set the altivec features if the kernel was compiled with altivec
46 * support
47 */
48#ifdef CONFIG_ALTIVEC
49#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
50#define PPC_FEATURE_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
51#else
52#define CPU_FTR_ALTIVEC_COMP 0
53#define PPC_FEATURE_ALTIVEC_COMP 0
54#endif
55
56/* We only set the spe features if the kernel was compiled with 45/* We only set the spe features if the kernel was compiled with
57 * spe support 46 * spe support
58 */ 47 */
@@ -62,34 +51,13 @@ extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spe
62#define PPC_FEATURE_SPE_COMP 0 51#define PPC_FEATURE_SPE_COMP 0
63#endif 52#endif
64 53
65/* We need to mark all pages as being coherent if we're SMP or we
66 * have a 74[45]x and an MPC107 host bridge.
67 */
68#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
69#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
70#else
71#define CPU_FTR_COMMON 0
72#endif
73
74/* The powersave features NAP & DOZE seems to confuse BDI when
75 debugging. So if a BDI is used, disable theses
76 */
77#ifndef CONFIG_BDI_SWITCH
78#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
79#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
80#else
81#define CPU_FTR_MAYBE_CAN_DOZE 0
82#define CPU_FTR_MAYBE_CAN_NAP 0
83#endif
84
85struct cpu_spec cpu_specs[] = { 54struct cpu_spec cpu_specs[] = {
86#if CLASSIC_PPC 55#if CLASSIC_PPC
87 { /* 601 */ 56 { /* 601 */
88 .pvr_mask = 0xffff0000, 57 .pvr_mask = 0xffff0000,
89 .pvr_value = 0x00010000, 58 .pvr_value = 0x00010000,
90 .cpu_name = "601", 59 .cpu_name = "601",
91 .cpu_features = CPU_FTR_COMMON | CPU_FTR_601 | 60 .cpu_features = CPU_FTRS_PPC601,
92 CPU_FTR_HPTE_TABLE,
93 .cpu_user_features = COMMON_PPC | PPC_FEATURE_601_INSTR | 61 .cpu_user_features = COMMON_PPC | PPC_FEATURE_601_INSTR |
94 PPC_FEATURE_UNIFIED_CACHE, 62 PPC_FEATURE_UNIFIED_CACHE,
95 .icache_bsize = 32, 63 .icache_bsize = 32,
@@ -100,9 +68,7 @@ struct cpu_spec cpu_specs[] = {
100 .pvr_mask = 0xffff0000, 68 .pvr_mask = 0xffff0000,
101 .pvr_value = 0x00030000, 69 .pvr_value = 0x00030000,
102 .cpu_name = "603", 70 .cpu_name = "603",
103 .cpu_features = CPU_FTR_COMMON | 71 .cpu_features = CPU_FTRS_603,
104 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
105 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
106 .cpu_user_features = COMMON_PPC, 72 .cpu_user_features = COMMON_PPC,
107 .icache_bsize = 32, 73 .icache_bsize = 32,
108 .dcache_bsize = 32, 74 .dcache_bsize = 32,
@@ -112,9 +78,7 @@ struct cpu_spec cpu_specs[] = {
112 .pvr_mask = 0xffff0000, 78 .pvr_mask = 0xffff0000,
113 .pvr_value = 0x00060000, 79 .pvr_value = 0x00060000,
114 .cpu_name = "603e", 80 .cpu_name = "603e",
115 .cpu_features = CPU_FTR_COMMON | 81 .cpu_features = CPU_FTRS_603,
116 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
117 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
118 .cpu_user_features = COMMON_PPC, 82 .cpu_user_features = COMMON_PPC,
119 .icache_bsize = 32, 83 .icache_bsize = 32,
120 .dcache_bsize = 32, 84 .dcache_bsize = 32,
@@ -124,9 +88,7 @@ struct cpu_spec cpu_specs[] = {
124 .pvr_mask = 0xffff0000, 88 .pvr_mask = 0xffff0000,
125 .pvr_value = 0x00070000, 89 .pvr_value = 0x00070000,
126 .cpu_name = "603ev", 90 .cpu_name = "603ev",
127 .cpu_features = CPU_FTR_COMMON | 91 .cpu_features = CPU_FTRS_603,
128 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
129 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
130 .cpu_user_features = COMMON_PPC, 92 .cpu_user_features = COMMON_PPC,
131 .icache_bsize = 32, 93 .icache_bsize = 32,
132 .dcache_bsize = 32, 94 .dcache_bsize = 32,
@@ -136,9 +98,7 @@ struct cpu_spec cpu_specs[] = {
136 .pvr_mask = 0xffff0000, 98 .pvr_mask = 0xffff0000,
137 .pvr_value = 0x00040000, 99 .pvr_value = 0x00040000,
138 .cpu_name = "604", 100 .cpu_name = "604",
139 .cpu_features = CPU_FTR_COMMON | 101 .cpu_features = CPU_FTRS_604,
140 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
141 CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
142 .cpu_user_features = COMMON_PPC, 102 .cpu_user_features = COMMON_PPC,
143 .icache_bsize = 32, 103 .icache_bsize = 32,
144 .dcache_bsize = 32, 104 .dcache_bsize = 32,
@@ -149,9 +109,7 @@ struct cpu_spec cpu_specs[] = {
149 .pvr_mask = 0xfffff000, 109 .pvr_mask = 0xfffff000,
150 .pvr_value = 0x00090000, 110 .pvr_value = 0x00090000,
151 .cpu_name = "604e", 111 .cpu_name = "604e",
152 .cpu_features = CPU_FTR_COMMON | 112 .cpu_features = CPU_FTRS_604,
153 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
154 CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
155 .cpu_user_features = COMMON_PPC, 113 .cpu_user_features = COMMON_PPC,
156 .icache_bsize = 32, 114 .icache_bsize = 32,
157 .dcache_bsize = 32, 115 .dcache_bsize = 32,
@@ -162,9 +120,7 @@ struct cpu_spec cpu_specs[] = {
162 .pvr_mask = 0xffff0000, 120 .pvr_mask = 0xffff0000,
163 .pvr_value = 0x00090000, 121 .pvr_value = 0x00090000,
164 .cpu_name = "604r", 122 .cpu_name = "604r",
165 .cpu_features = CPU_FTR_COMMON | 123 .cpu_features = CPU_FTRS_604,
166 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
167 CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
168 .cpu_user_features = COMMON_PPC, 124 .cpu_user_features = COMMON_PPC,
169 .icache_bsize = 32, 125 .icache_bsize = 32,
170 .dcache_bsize = 32, 126 .dcache_bsize = 32,
@@ -175,9 +131,7 @@ struct cpu_spec cpu_specs[] = {
175 .pvr_mask = 0xffff0000, 131 .pvr_mask = 0xffff0000,
176 .pvr_value = 0x000a0000, 132 .pvr_value = 0x000a0000,
177 .cpu_name = "604ev", 133 .cpu_name = "604ev",
178 .cpu_features = CPU_FTR_COMMON | 134 .cpu_features = CPU_FTRS_604,
179 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
180 CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
181 .cpu_user_features = COMMON_PPC, 135 .cpu_user_features = COMMON_PPC,
182 .icache_bsize = 32, 136 .icache_bsize = 32,
183 .dcache_bsize = 32, 137 .dcache_bsize = 32,
@@ -188,10 +142,7 @@ struct cpu_spec cpu_specs[] = {
188 .pvr_mask = 0xffffffff, 142 .pvr_mask = 0xffffffff,
189 .pvr_value = 0x00084202, 143 .pvr_value = 0x00084202,
190 .cpu_name = "740/750", 144 .cpu_name = "740/750",
191 .cpu_features = CPU_FTR_COMMON | 145 .cpu_features = CPU_FTRS_740_NOTAU,
192 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
193 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_HPTE_TABLE |
194 CPU_FTR_MAYBE_CAN_NAP,
195 .cpu_user_features = COMMON_PPC, 146 .cpu_user_features = COMMON_PPC,
196 .icache_bsize = 32, 147 .icache_bsize = 32,
197 .dcache_bsize = 32, 148 .dcache_bsize = 32,
@@ -202,10 +153,7 @@ struct cpu_spec cpu_specs[] = {
202 .pvr_mask = 0xfffffff0, 153 .pvr_mask = 0xfffffff0,
203 .pvr_value = 0x00080100, 154 .pvr_value = 0x00080100,
204 .cpu_name = "750CX", 155 .cpu_name = "750CX",
205 .cpu_features = CPU_FTR_COMMON | 156 .cpu_features = CPU_FTRS_750,
206 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
207 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
208 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
209 .cpu_user_features = COMMON_PPC, 157 .cpu_user_features = COMMON_PPC,
210 .icache_bsize = 32, 158 .icache_bsize = 32,
211 .dcache_bsize = 32, 159 .dcache_bsize = 32,
@@ -216,10 +164,7 @@ struct cpu_spec cpu_specs[] = {
216 .pvr_mask = 0xfffffff0, 164 .pvr_mask = 0xfffffff0,
217 .pvr_value = 0x00082200, 165 .pvr_value = 0x00082200,
218 .cpu_name = "750CX", 166 .cpu_name = "750CX",
219 .cpu_features = CPU_FTR_COMMON | 167 .cpu_features = CPU_FTRS_750,
220 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
221 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
222 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
223 .cpu_user_features = COMMON_PPC, 168 .cpu_user_features = COMMON_PPC,
224 .icache_bsize = 32, 169 .icache_bsize = 32,
225 .dcache_bsize = 32, 170 .dcache_bsize = 32,
@@ -230,10 +175,7 @@ struct cpu_spec cpu_specs[] = {
230 .pvr_mask = 0xfffffff0, 175 .pvr_mask = 0xfffffff0,
231 .pvr_value = 0x00082210, 176 .pvr_value = 0x00082210,
232 .cpu_name = "750CXe", 177 .cpu_name = "750CXe",
233 .cpu_features = CPU_FTR_COMMON | 178 .cpu_features = CPU_FTRS_750,
234 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
235 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
236 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
237 .cpu_user_features = COMMON_PPC, 179 .cpu_user_features = COMMON_PPC,
238 .icache_bsize = 32, 180 .icache_bsize = 32,
239 .dcache_bsize = 32, 181 .dcache_bsize = 32,
@@ -244,10 +186,7 @@ struct cpu_spec cpu_specs[] = {
244 .pvr_mask = 0xffffffff, 186 .pvr_mask = 0xffffffff,
245 .pvr_value = 0x00083214, 187 .pvr_value = 0x00083214,
246 .cpu_name = "750CXe", 188 .cpu_name = "750CXe",
247 .cpu_features = CPU_FTR_COMMON | 189 .cpu_features = CPU_FTRS_750,
248 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
249 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
250 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
251 .cpu_user_features = COMMON_PPC, 190 .cpu_user_features = COMMON_PPC,
252 .icache_bsize = 32, 191 .icache_bsize = 32,
253 .dcache_bsize = 32, 192 .dcache_bsize = 32,
@@ -258,10 +197,7 @@ struct cpu_spec cpu_specs[] = {
258 .pvr_mask = 0xfffff000, 197 .pvr_mask = 0xfffff000,
259 .pvr_value = 0x00083000, 198 .pvr_value = 0x00083000,
260 .cpu_name = "745/755", 199 .cpu_name = "745/755",
261 .cpu_features = CPU_FTR_COMMON | 200 .cpu_features = CPU_FTRS_750,
262 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
263 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
264 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
265 .cpu_user_features = COMMON_PPC, 201 .cpu_user_features = COMMON_PPC,
266 .icache_bsize = 32, 202 .icache_bsize = 32,
267 .dcache_bsize = 32, 203 .dcache_bsize = 32,
@@ -272,11 +208,7 @@ struct cpu_spec cpu_specs[] = {
272 .pvr_mask = 0xffffff00, 208 .pvr_mask = 0xffffff00,
273 .pvr_value = 0x70000100, 209 .pvr_value = 0x70000100,
274 .cpu_name = "750FX", 210 .cpu_name = "750FX",
275 .cpu_features = CPU_FTR_COMMON | 211 .cpu_features = CPU_FTRS_750FX1,
276 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
277 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
278 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
279 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
280 .cpu_user_features = COMMON_PPC, 212 .cpu_user_features = COMMON_PPC,
281 .icache_bsize = 32, 213 .icache_bsize = 32,
282 .dcache_bsize = 32, 214 .dcache_bsize = 32,
@@ -287,11 +219,7 @@ struct cpu_spec cpu_specs[] = {
287 .pvr_mask = 0xffffffff, 219 .pvr_mask = 0xffffffff,
288 .pvr_value = 0x70000200, 220 .pvr_value = 0x70000200,
289 .cpu_name = "750FX", 221 .cpu_name = "750FX",
290 .cpu_features = CPU_FTR_COMMON | 222 .cpu_features = CPU_FTRS_750FX2,
291 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
292 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
293 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
294 CPU_FTR_NO_DPM,
295 .cpu_user_features = COMMON_PPC, 223 .cpu_user_features = COMMON_PPC,
296 .icache_bsize = 32, 224 .icache_bsize = 32,
297 .dcache_bsize = 32, 225 .dcache_bsize = 32,
@@ -302,11 +230,7 @@ struct cpu_spec cpu_specs[] = {
302 .pvr_mask = 0xffff0000, 230 .pvr_mask = 0xffff0000,
303 .pvr_value = 0x70000000, 231 .pvr_value = 0x70000000,
304 .cpu_name = "750FX", 232 .cpu_name = "750FX",
305 .cpu_features = CPU_FTR_COMMON | 233 .cpu_features = CPU_FTRS_750FX,
306 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
307 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
308 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
309 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
310 .cpu_user_features = COMMON_PPC, 234 .cpu_user_features = COMMON_PPC,
311 .icache_bsize = 32, 235 .icache_bsize = 32,
312 .dcache_bsize = 32, 236 .dcache_bsize = 32,
@@ -317,11 +241,7 @@ struct cpu_spec cpu_specs[] = {
317 .pvr_mask = 0xffff0000, 241 .pvr_mask = 0xffff0000,
318 .pvr_value = 0x70020000, 242 .pvr_value = 0x70020000,
319 .cpu_name = "750GX", 243 .cpu_name = "750GX",
320 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 244 .cpu_features = CPU_FTRS_750GX,
321 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
322 CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE |
323 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_DUAL_PLL_750FX |
324 CPU_FTR_HAS_HIGH_BATS,
325 .cpu_user_features = COMMON_PPC, 245 .cpu_user_features = COMMON_PPC,
326 .icache_bsize = 32, 246 .icache_bsize = 32,
327 .dcache_bsize = 32, 247 .dcache_bsize = 32,
@@ -332,10 +252,7 @@ struct cpu_spec cpu_specs[] = {
332 .pvr_mask = 0xffff0000, 252 .pvr_mask = 0xffff0000,
333 .pvr_value = 0x00080000, 253 .pvr_value = 0x00080000,
334 .cpu_name = "740/750", 254 .cpu_name = "740/750",
335 .cpu_features = CPU_FTR_COMMON | 255 .cpu_features = CPU_FTRS_740,
336 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
337 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
338 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
339 .cpu_user_features = COMMON_PPC, 256 .cpu_user_features = COMMON_PPC,
340 .icache_bsize = 32, 257 .icache_bsize = 32,
341 .dcache_bsize = 32, 258 .dcache_bsize = 32,
@@ -346,11 +263,8 @@ struct cpu_spec cpu_specs[] = {
346 .pvr_mask = 0xffffffff, 263 .pvr_mask = 0xffffffff,
347 .pvr_value = 0x000c1101, 264 .pvr_value = 0x000c1101,
348 .cpu_name = "7400 (1.1)", 265 .cpu_name = "7400 (1.1)",
349 .cpu_features = CPU_FTR_COMMON | 266 .cpu_features = CPU_FTRS_7400_NOTAU,
350 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | 267 .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
351 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
352 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
353 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
354 .icache_bsize = 32, 268 .icache_bsize = 32,
355 .dcache_bsize = 32, 269 .dcache_bsize = 32,
356 .num_pmcs = 4, 270 .num_pmcs = 4,
@@ -360,12 +274,8 @@ struct cpu_spec cpu_specs[] = {
360 .pvr_mask = 0xffff0000, 274 .pvr_mask = 0xffff0000,
361 .pvr_value = 0x000c0000, 275 .pvr_value = 0x000c0000,
362 .cpu_name = "7400", 276 .cpu_name = "7400",
363 .cpu_features = CPU_FTR_COMMON | 277 .cpu_features = CPU_FTRS_7400,
364 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | 278 .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
365 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
366 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
367 CPU_FTR_MAYBE_CAN_NAP,
368 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
369 .icache_bsize = 32, 279 .icache_bsize = 32,
370 .dcache_bsize = 32, 280 .dcache_bsize = 32,
371 .num_pmcs = 4, 281 .num_pmcs = 4,
@@ -375,12 +285,8 @@ struct cpu_spec cpu_specs[] = {
375 .pvr_mask = 0xffff0000, 285 .pvr_mask = 0xffff0000,
376 .pvr_value = 0x800c0000, 286 .pvr_value = 0x800c0000,
377 .cpu_name = "7410", 287 .cpu_name = "7410",
378 .cpu_features = CPU_FTR_COMMON | 288 .cpu_features = CPU_FTRS_7400,
379 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | 289 .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
380 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
381 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
382 CPU_FTR_MAYBE_CAN_NAP,
383 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
384 .icache_bsize = 32, 290 .icache_bsize = 32,
385 .dcache_bsize = 32, 291 .dcache_bsize = 32,
386 .num_pmcs = 4, 292 .num_pmcs = 4,
@@ -390,12 +296,8 @@ struct cpu_spec cpu_specs[] = {
390 .pvr_mask = 0xffffffff, 296 .pvr_mask = 0xffffffff,
391 .pvr_value = 0x80000200, 297 .pvr_value = 0x80000200,
392 .cpu_name = "7450", 298 .cpu_name = "7450",
393 .cpu_features = CPU_FTR_COMMON | 299 .cpu_features = CPU_FTRS_7450_20,
394 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | 300 .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
395 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
396 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
397 CPU_FTR_NEED_COHERENT,
398 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
399 .icache_bsize = 32, 301 .icache_bsize = 32,
400 .dcache_bsize = 32, 302 .dcache_bsize = 32,
401 .num_pmcs = 6, 303 .num_pmcs = 6,
@@ -405,14 +307,8 @@ struct cpu_spec cpu_specs[] = {
405 .pvr_mask = 0xffffffff, 307 .pvr_mask = 0xffffffff,
406 .pvr_value = 0x80000201, 308 .pvr_value = 0x80000201,
407 .cpu_name = "7450", 309 .cpu_name = "7450",
408 .cpu_features = CPU_FTR_COMMON | 310 .cpu_features = CPU_FTRS_7450_21,
409 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | 311 .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
410 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
411 CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
412 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
413 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
414 CPU_FTR_NEED_COHERENT,
415 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
416 .icache_bsize = 32, 312 .icache_bsize = 32,
417 .dcache_bsize = 32, 313 .dcache_bsize = 32,
418 .num_pmcs = 6, 314 .num_pmcs = 6,
@@ -422,13 +318,8 @@ struct cpu_spec cpu_specs[] = {
422 .pvr_mask = 0xffff0000, 318 .pvr_mask = 0xffff0000,
423 .pvr_value = 0x80000000, 319 .pvr_value = 0x80000000,
424 .cpu_name = "7450", 320 .cpu_name = "7450",
425 .cpu_features = CPU_FTR_COMMON | 321 .cpu_features = CPU_FTRS_7450_23,
426 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | 322 .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
427 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
428 CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
429 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
430 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT,
431 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
432 .icache_bsize = 32, 323 .icache_bsize = 32,
433 .dcache_bsize = 32, 324 .dcache_bsize = 32,
434 .num_pmcs = 6, 325 .num_pmcs = 6,
@@ -438,12 +329,8 @@ struct cpu_spec cpu_specs[] = {
438 .pvr_mask = 0xffffff00, 329 .pvr_mask = 0xffffff00,
439 .pvr_value = 0x80010100, 330 .pvr_value = 0x80010100,
440 .cpu_name = "7455", 331 .cpu_name = "7455",
441 .cpu_features = CPU_FTR_COMMON | 332 .cpu_features = CPU_FTRS_7455_1,
442 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | 333 .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
443 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
444 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
445 CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
446 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
447 .icache_bsize = 32, 334 .icache_bsize = 32,
448 .dcache_bsize = 32, 335 .dcache_bsize = 32,
449 .num_pmcs = 6, 336 .num_pmcs = 6,
@@ -453,14 +340,8 @@ struct cpu_spec cpu_specs[] = {
453 .pvr_mask = 0xffffffff, 340 .pvr_mask = 0xffffffff,
454 .pvr_value = 0x80010200, 341 .pvr_value = 0x80010200,
455 .cpu_name = "7455", 342 .cpu_name = "7455",
456 .cpu_features = CPU_FTR_COMMON | 343 .cpu_features = CPU_FTRS_7455_20,
457 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | 344 .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
458 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
459 CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
460 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
461 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
462 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
463 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
464 .icache_bsize = 32, 345 .icache_bsize = 32,
465 .dcache_bsize = 32, 346 .dcache_bsize = 32,
466 .num_pmcs = 6, 347 .num_pmcs = 6,
@@ -470,14 +351,8 @@ struct cpu_spec cpu_specs[] = {
470 .pvr_mask = 0xffff0000, 351 .pvr_mask = 0xffff0000,
471 .pvr_value = 0x80010000, 352 .pvr_value = 0x80010000,
472 .cpu_name = "7455", 353 .cpu_name = "7455",
473 .cpu_features = CPU_FTR_COMMON | 354 .cpu_features = CPU_FTRS_7455,
474 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | 355 .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
475 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
476 CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
477 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
478 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
479 CPU_FTR_NEED_COHERENT,
480 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
481 .icache_bsize = 32, 356 .icache_bsize = 32,
482 .dcache_bsize = 32, 357 .dcache_bsize = 32,
483 .num_pmcs = 6, 358 .num_pmcs = 6,
@@ -487,14 +362,8 @@ struct cpu_spec cpu_specs[] = {
487 .pvr_mask = 0xffffffff, 362 .pvr_mask = 0xffffffff,
488 .pvr_value = 0x80020100, 363 .pvr_value = 0x80020100,
489 .cpu_name = "7447/7457", 364 .cpu_name = "7447/7457",
490 .cpu_features = CPU_FTR_COMMON | 365 .cpu_features = CPU_FTRS_7447_10,
491 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | 366 .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
492 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
493 CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
494 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
495 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
496 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
497 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
498 .icache_bsize = 32, 367 .icache_bsize = 32,
499 .dcache_bsize = 32, 368 .dcache_bsize = 32,
500 .num_pmcs = 6, 369 .num_pmcs = 6,
@@ -504,14 +373,8 @@ struct cpu_spec cpu_specs[] = {
504 .pvr_mask = 0xffffffff, 373 .pvr_mask = 0xffffffff,
505 .pvr_value = 0x80020101, 374 .pvr_value = 0x80020101,
506 .cpu_name = "7447/7457", 375 .cpu_name = "7447/7457",
507 .cpu_features = CPU_FTR_COMMON | 376 .cpu_features = CPU_FTRS_7447_10,
508 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | 377 .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
509 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
510 CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
511 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
512 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
513 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
514 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
515 .icache_bsize = 32, 378 .icache_bsize = 32,
516 .dcache_bsize = 32, 379 .dcache_bsize = 32,
517 .num_pmcs = 6, 380 .num_pmcs = 6,
@@ -521,14 +384,8 @@ struct cpu_spec cpu_specs[] = {
521 .pvr_mask = 0xffff0000, 384 .pvr_mask = 0xffff0000,
522 .pvr_value = 0x80020000, 385 .pvr_value = 0x80020000,
523 .cpu_name = "7447/7457", 386 .cpu_name = "7447/7457",
524 .cpu_features = CPU_FTR_COMMON | 387 .cpu_features = CPU_FTRS_7447,
525 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | 388 .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
526 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
527 CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
528 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
529 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
530 CPU_FTR_NEED_COHERENT,
531 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
532 .icache_bsize = 32, 389 .icache_bsize = 32,
533 .dcache_bsize = 32, 390 .dcache_bsize = 32,
534 .num_pmcs = 6, 391 .num_pmcs = 6,
@@ -538,13 +395,8 @@ struct cpu_spec cpu_specs[] = {
538 .pvr_mask = 0xffff0000, 395 .pvr_mask = 0xffff0000,
539 .pvr_value = 0x80030000, 396 .pvr_value = 0x80030000,
540 .cpu_name = "7447A", 397 .cpu_name = "7447A",
541 .cpu_features = CPU_FTR_COMMON | 398 .cpu_features = CPU_FTRS_7447A,
542 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | 399 .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
543 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
544 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
545 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
546 CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
547 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
548 .icache_bsize = 32, 400 .icache_bsize = 32,
549 .dcache_bsize = 32, 401 .dcache_bsize = 32,
550 .num_pmcs = 6, 402 .num_pmcs = 6,
@@ -554,13 +406,8 @@ struct cpu_spec cpu_specs[] = {
554 .pvr_mask = 0xffff0000, 406 .pvr_mask = 0xffff0000,
555 .pvr_value = 0x80040000, 407 .pvr_value = 0x80040000,
556 .cpu_name = "7448", 408 .cpu_name = "7448",
557 .cpu_features = CPU_FTR_COMMON | 409 .cpu_features = CPU_FTRS_7447A,
558 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | 410 .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
559 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
560 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
561 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
562 CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
563 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
564 .icache_bsize = 32, 411 .icache_bsize = 32,
565 .dcache_bsize = 32, 412 .dcache_bsize = 32,
566 .num_pmcs = 6, 413 .num_pmcs = 6,
@@ -570,9 +417,7 @@ struct cpu_spec cpu_specs[] = {
570 .pvr_mask = 0x7fff0000, 417 .pvr_mask = 0x7fff0000,
571 .pvr_value = 0x00810000, 418 .pvr_value = 0x00810000,
572 .cpu_name = "82xx", 419 .cpu_name = "82xx",
573 .cpu_features = CPU_FTR_COMMON | 420 .cpu_features = CPU_FTRS_82XX,
574 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
575 CPU_FTR_USE_TB,
576 .cpu_user_features = COMMON_PPC, 421 .cpu_user_features = COMMON_PPC,
577 .icache_bsize = 32, 422 .icache_bsize = 32,
578 .dcache_bsize = 32, 423 .dcache_bsize = 32,
@@ -582,9 +427,7 @@ struct cpu_spec cpu_specs[] = {
582 .pvr_mask = 0x7fff0000, 427 .pvr_mask = 0x7fff0000,
583 .pvr_value = 0x00820000, 428 .pvr_value = 0x00820000,
584 .cpu_name = "G2_LE", 429 .cpu_name = "G2_LE",
585 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 430 .cpu_features = CPU_FTRS_G2_LE,
586 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
587 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
588 .cpu_user_features = COMMON_PPC, 431 .cpu_user_features = COMMON_PPC,
589 .icache_bsize = 32, 432 .icache_bsize = 32,
590 .dcache_bsize = 32, 433 .dcache_bsize = 32,
@@ -594,9 +437,7 @@ struct cpu_spec cpu_specs[] = {
594 .pvr_mask = 0x7fff0000, 437 .pvr_mask = 0x7fff0000,
595 .pvr_value = 0x00830000, 438 .pvr_value = 0x00830000,
596 .cpu_name = "e300", 439 .cpu_name = "e300",
597 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 440 .cpu_features = CPU_FTRS_E300,
598 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
599 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
600 .cpu_user_features = COMMON_PPC, 441 .cpu_user_features = COMMON_PPC,
601 .icache_bsize = 32, 442 .icache_bsize = 32,
602 .dcache_bsize = 32, 443 .dcache_bsize = 32,
@@ -606,9 +447,7 @@ struct cpu_spec cpu_specs[] = {
606 .pvr_mask = 0x00000000, 447 .pvr_mask = 0x00000000,
607 .pvr_value = 0x00000000, 448 .pvr_value = 0x00000000,
608 .cpu_name = "(generic PPC)", 449 .cpu_name = "(generic PPC)",
609 .cpu_features = CPU_FTR_COMMON | 450 .cpu_features = CPU_FTRS_CLASSIC32,
610 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
611 CPU_FTR_HPTE_TABLE,
612 .cpu_user_features = COMMON_PPC, 451 .cpu_user_features = COMMON_PPC,
613 .icache_bsize = 32, 452 .icache_bsize = 32,
614 .dcache_bsize = 32, 453 .dcache_bsize = 32,
@@ -620,9 +459,7 @@ struct cpu_spec cpu_specs[] = {
620 .pvr_mask = 0xffff0000, 459 .pvr_mask = 0xffff0000,
621 .pvr_value = 0x00400000, 460 .pvr_value = 0x00400000,
622 .cpu_name = "Power3 (630)", 461 .cpu_name = "Power3 (630)",
623 .cpu_features = CPU_FTR_COMMON | 462 .cpu_features = CPU_FTRS_POWER3_32,
624 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
625 CPU_FTR_HPTE_TABLE,
626 .cpu_user_features = COMMON_PPC | PPC_FEATURE_64, 463 .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
627 .icache_bsize = 128, 464 .icache_bsize = 128,
628 .dcache_bsize = 128, 465 .dcache_bsize = 128,
@@ -633,9 +470,7 @@ struct cpu_spec cpu_specs[] = {
633 .pvr_mask = 0xffff0000, 470 .pvr_mask = 0xffff0000,
634 .pvr_value = 0x00410000, 471 .pvr_value = 0x00410000,
635 .cpu_name = "Power3 (630+)", 472 .cpu_name = "Power3 (630+)",
636 .cpu_features = CPU_FTR_COMMON | 473 .cpu_features = CPU_FTRS_POWER3_32,
637 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
638 CPU_FTR_HPTE_TABLE,
639 .cpu_user_features = COMMON_PPC | PPC_FEATURE_64, 474 .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
640 .icache_bsize = 128, 475 .icache_bsize = 128,
641 .dcache_bsize = 128, 476 .dcache_bsize = 128,
@@ -646,9 +481,7 @@ struct cpu_spec cpu_specs[] = {
646 .pvr_mask = 0xffff0000, 481 .pvr_mask = 0xffff0000,
647 .pvr_value = 0x00360000, 482 .pvr_value = 0x00360000,
648 .cpu_name = "I-star", 483 .cpu_name = "I-star",
649 .cpu_features = CPU_FTR_COMMON | 484 .cpu_features = CPU_FTRS_POWER3_32,
650 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
651 CPU_FTR_HPTE_TABLE,
652 .cpu_user_features = COMMON_PPC | PPC_FEATURE_64, 485 .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
653 .icache_bsize = 128, 486 .icache_bsize = 128,
654 .dcache_bsize = 128, 487 .dcache_bsize = 128,
@@ -659,9 +492,7 @@ struct cpu_spec cpu_specs[] = {
659 .pvr_mask = 0xffff0000, 492 .pvr_mask = 0xffff0000,
660 .pvr_value = 0x00370000, 493 .pvr_value = 0x00370000,
661 .cpu_name = "S-star", 494 .cpu_name = "S-star",
662 .cpu_features = CPU_FTR_COMMON | 495 .cpu_features = CPU_FTRS_POWER3_32,
663 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
664 CPU_FTR_HPTE_TABLE,
665 .cpu_user_features = COMMON_PPC | PPC_FEATURE_64, 496 .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
666 .icache_bsize = 128, 497 .icache_bsize = 128,
667 .dcache_bsize = 128, 498 .dcache_bsize = 128,
@@ -670,44 +501,12 @@ struct cpu_spec cpu_specs[] = {
670 }, 501 },
671#endif /* CONFIG_PPC64BRIDGE */ 502#endif /* CONFIG_PPC64BRIDGE */
672#ifdef CONFIG_POWER4 503#ifdef CONFIG_POWER4
673 { /* Power4 */
674 .pvr_mask = 0xffff0000,
675 .pvr_value = 0x00350000,
676 .cpu_name = "Power4",
677 .cpu_features = CPU_FTR_COMMON |
678 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
679 CPU_FTR_HPTE_TABLE,
680 .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
681 .icache_bsize = 128,
682 .dcache_bsize = 128,
683 .num_pmcs = 8,
684 .cpu_setup = __setup_cpu_power4
685 },
686 { /* PPC970 */
687 .pvr_mask = 0xffff0000,
688 .pvr_value = 0x00390000,
689 .cpu_name = "PPC970",
690 .cpu_features = CPU_FTR_COMMON |
691 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
692 CPU_FTR_HPTE_TABLE |
693 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
694 .cpu_user_features = COMMON_PPC | PPC_FEATURE_64 |
695 PPC_FEATURE_ALTIVEC_COMP,
696 .icache_bsize = 128,
697 .dcache_bsize = 128,
698 .num_pmcs = 8,
699 .cpu_setup = __setup_cpu_ppc970
700 },
701 { /* PPC970FX */ 504 { /* PPC970FX */
702 .pvr_mask = 0xffff0000, 505 .pvr_mask = 0xffff0000,
703 .pvr_value = 0x003c0000, 506 .pvr_value = 0x003c0000,
704 .cpu_name = "PPC970FX", 507 .cpu_name = "PPC970FX",
705 .cpu_features = CPU_FTR_COMMON | 508 .cpu_features = CPU_FTRS_970_32,
706 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | 509 .cpu_user_features = COMMON_PPC | PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC_COMP,
707 CPU_FTR_HPTE_TABLE |
708 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
709 .cpu_user_features = COMMON_PPC | PPC_FEATURE_64 |
710 PPC_FEATURE_ALTIVEC_COMP,
711 .icache_bsize = 128, 510 .icache_bsize = 128,
712 .dcache_bsize = 128, 511 .dcache_bsize = 128,
713 .num_pmcs = 8, 512 .num_pmcs = 8,
@@ -721,8 +520,7 @@ struct cpu_spec cpu_specs[] = {
721 .cpu_name = "8xx", 520 .cpu_name = "8xx",
722 /* CPU_FTR_MAYBE_CAN_DOZE is possible, 521 /* CPU_FTR_MAYBE_CAN_DOZE is possible,
723 * if the 8xx code is there.... */ 522 * if the 8xx code is there.... */
724 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 523 .cpu_features = CPU_FTRS_8XX,
725 CPU_FTR_USE_TB,
726 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 524 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
727 .icache_bsize = 16, 525 .icache_bsize = 16,
728 .dcache_bsize = 16, 526 .dcache_bsize = 16,
@@ -733,8 +531,7 @@ struct cpu_spec cpu_specs[] = {
733 .pvr_mask = 0xffffff00, 531 .pvr_mask = 0xffffff00,
734 .pvr_value = 0x00200200, 532 .pvr_value = 0x00200200,
735 .cpu_name = "403GC", 533 .cpu_name = "403GC",
736 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 534 .cpu_features = CPU_FTRS_40X,
737 CPU_FTR_USE_TB,
738 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 535 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
739 .icache_bsize = 16, 536 .icache_bsize = 16,
740 .dcache_bsize = 16, 537 .dcache_bsize = 16,
@@ -743,8 +540,7 @@ struct cpu_spec cpu_specs[] = {
743 .pvr_mask = 0xffffff00, 540 .pvr_mask = 0xffffff00,
744 .pvr_value = 0x00201400, 541 .pvr_value = 0x00201400,
745 .cpu_name = "403GCX", 542 .cpu_name = "403GCX",
746 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 543 .cpu_features = CPU_FTRS_40X,
747 CPU_FTR_USE_TB,
748 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 544 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
749 .icache_bsize = 16, 545 .icache_bsize = 16,
750 .dcache_bsize = 16, 546 .dcache_bsize = 16,
@@ -753,8 +549,7 @@ struct cpu_spec cpu_specs[] = {
753 .pvr_mask = 0xffff0000, 549 .pvr_mask = 0xffff0000,
754 .pvr_value = 0x00200000, 550 .pvr_value = 0x00200000,
755 .cpu_name = "403G ??", 551 .cpu_name = "403G ??",
756 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 552 .cpu_features = CPU_FTRS_40X,
757 CPU_FTR_USE_TB,
758 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 553 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
759 .icache_bsize = 16, 554 .icache_bsize = 16,
760 .dcache_bsize = 16, 555 .dcache_bsize = 16,
@@ -763,8 +558,7 @@ struct cpu_spec cpu_specs[] = {
763 .pvr_mask = 0xffff0000, 558 .pvr_mask = 0xffff0000,
764 .pvr_value = 0x40110000, 559 .pvr_value = 0x40110000,
765 .cpu_name = "405GP", 560 .cpu_name = "405GP",
766 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 561 .cpu_features = CPU_FTRS_40X,
767 CPU_FTR_USE_TB,
768 .cpu_user_features = PPC_FEATURE_32 | 562 .cpu_user_features = PPC_FEATURE_32 |
769 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 563 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
770 .icache_bsize = 32, 564 .icache_bsize = 32,
@@ -774,8 +568,7 @@ struct cpu_spec cpu_specs[] = {
774 .pvr_mask = 0xffff0000, 568 .pvr_mask = 0xffff0000,
775 .pvr_value = 0x40130000, 569 .pvr_value = 0x40130000,
776 .cpu_name = "STB03xxx", 570 .cpu_name = "STB03xxx",
777 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 571 .cpu_features = CPU_FTRS_40X,
778 CPU_FTR_USE_TB,
779 .cpu_user_features = PPC_FEATURE_32 | 572 .cpu_user_features = PPC_FEATURE_32 |
780 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 573 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
781 .icache_bsize = 32, 574 .icache_bsize = 32,
@@ -785,8 +578,7 @@ struct cpu_spec cpu_specs[] = {
785 .pvr_mask = 0xffff0000, 578 .pvr_mask = 0xffff0000,
786 .pvr_value = 0x41810000, 579 .pvr_value = 0x41810000,
787 .cpu_name = "STB04xxx", 580 .cpu_name = "STB04xxx",
788 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 581 .cpu_features = CPU_FTRS_40X,
789 CPU_FTR_USE_TB,
790 .cpu_user_features = PPC_FEATURE_32 | 582 .cpu_user_features = PPC_FEATURE_32 |
791 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 583 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
792 .icache_bsize = 32, 584 .icache_bsize = 32,
@@ -796,8 +588,7 @@ struct cpu_spec cpu_specs[] = {
796 .pvr_mask = 0xffff0000, 588 .pvr_mask = 0xffff0000,
797 .pvr_value = 0x41610000, 589 .pvr_value = 0x41610000,
798 .cpu_name = "NP405L", 590 .cpu_name = "NP405L",
799 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 591 .cpu_features = CPU_FTRS_40X,
800 CPU_FTR_USE_TB,
801 .cpu_user_features = PPC_FEATURE_32 | 592 .cpu_user_features = PPC_FEATURE_32 |
802 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 593 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
803 .icache_bsize = 32, 594 .icache_bsize = 32,
@@ -807,8 +598,7 @@ struct cpu_spec cpu_specs[] = {
807 .pvr_mask = 0xffff0000, 598 .pvr_mask = 0xffff0000,
808 .pvr_value = 0x40B10000, 599 .pvr_value = 0x40B10000,
809 .cpu_name = "NP4GS3", 600 .cpu_name = "NP4GS3",
810 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 601 .cpu_features = CPU_FTRS_40X,
811 CPU_FTR_USE_TB,
812 .cpu_user_features = PPC_FEATURE_32 | 602 .cpu_user_features = PPC_FEATURE_32 |
813 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 603 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
814 .icache_bsize = 32, 604 .icache_bsize = 32,
@@ -818,8 +608,7 @@ struct cpu_spec cpu_specs[] = {
818 .pvr_mask = 0xffff0000, 608 .pvr_mask = 0xffff0000,
819 .pvr_value = 0x41410000, 609 .pvr_value = 0x41410000,
820 .cpu_name = "NP405H", 610 .cpu_name = "NP405H",
821 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 611 .cpu_features = CPU_FTRS_40X,
822 CPU_FTR_USE_TB,
823 .cpu_user_features = PPC_FEATURE_32 | 612 .cpu_user_features = PPC_FEATURE_32 |
824 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 613 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
825 .icache_bsize = 32, 614 .icache_bsize = 32,
@@ -829,8 +618,7 @@ struct cpu_spec cpu_specs[] = {
829 .pvr_mask = 0xffff0000, 618 .pvr_mask = 0xffff0000,
830 .pvr_value = 0x50910000, 619 .pvr_value = 0x50910000,
831 .cpu_name = "405GPr", 620 .cpu_name = "405GPr",
832 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 621 .cpu_features = CPU_FTRS_40X,
833 CPU_FTR_USE_TB,
834 .cpu_user_features = PPC_FEATURE_32 | 622 .cpu_user_features = PPC_FEATURE_32 |
835 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 623 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
836 .icache_bsize = 32, 624 .icache_bsize = 32,
@@ -840,8 +628,7 @@ struct cpu_spec cpu_specs[] = {
840 .pvr_mask = 0xffff0000, 628 .pvr_mask = 0xffff0000,
841 .pvr_value = 0x51510000, 629 .pvr_value = 0x51510000,
842 .cpu_name = "STBx25xx", 630 .cpu_name = "STBx25xx",
843 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 631 .cpu_features = CPU_FTRS_40X,
844 CPU_FTR_USE_TB,
845 .cpu_user_features = PPC_FEATURE_32 | 632 .cpu_user_features = PPC_FEATURE_32 |
846 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 633 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
847 .icache_bsize = 32, 634 .icache_bsize = 32,
@@ -851,8 +638,7 @@ struct cpu_spec cpu_specs[] = {
851 .pvr_mask = 0xffff0000, 638 .pvr_mask = 0xffff0000,
852 .pvr_value = 0x41F10000, 639 .pvr_value = 0x41F10000,
853 .cpu_name = "405LP", 640 .cpu_name = "405LP",
854 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 641 .cpu_features = CPU_FTRS_40X,
855 CPU_FTR_USE_TB,
856 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 642 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
857 .icache_bsize = 32, 643 .icache_bsize = 32,
858 .dcache_bsize = 32, 644 .dcache_bsize = 32,
@@ -861,8 +647,7 @@ struct cpu_spec cpu_specs[] = {
861 .pvr_mask = 0xffff0000, 647 .pvr_mask = 0xffff0000,
862 .pvr_value = 0x20010000, 648 .pvr_value = 0x20010000,
863 .cpu_name = "Virtex-II Pro", 649 .cpu_name = "Virtex-II Pro",
864 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 650 .cpu_features = CPU_FTRS_40X,
865 CPU_FTR_USE_TB,
866 .cpu_user_features = PPC_FEATURE_32 | 651 .cpu_user_features = PPC_FEATURE_32 |
867 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 652 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
868 .icache_bsize = 32, 653 .icache_bsize = 32,
@@ -872,8 +657,7 @@ struct cpu_spec cpu_specs[] = {
872 .pvr_mask = 0xffff0000, 657 .pvr_mask = 0xffff0000,
873 .pvr_value = 0x51210000, 658 .pvr_value = 0x51210000,
874 .cpu_name = "405EP", 659 .cpu_name = "405EP",
875 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 660 .cpu_features = CPU_FTRS_40X,
876 CPU_FTR_USE_TB,
877 .cpu_user_features = PPC_FEATURE_32 | 661 .cpu_user_features = PPC_FEATURE_32 |
878 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 662 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
879 .icache_bsize = 32, 663 .icache_bsize = 32,
@@ -886,8 +670,7 @@ struct cpu_spec cpu_specs[] = {
886 .pvr_mask = 0xf0000fff, 670 .pvr_mask = 0xf0000fff,
887 .pvr_value = 0x40000850, 671 .pvr_value = 0x40000850,
888 .cpu_name = "440EP Rev. A", 672 .cpu_name = "440EP Rev. A",
889 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 673 .cpu_features = CPU_FTRS_44X,
890 CPU_FTR_USE_TB,
891 .cpu_user_features = COMMON_PPC, /* 440EP has an FPU */ 674 .cpu_user_features = COMMON_PPC, /* 440EP has an FPU */
892 .icache_bsize = 32, 675 .icache_bsize = 32,
893 .dcache_bsize = 32, 676 .dcache_bsize = 32,
@@ -896,8 +679,7 @@ struct cpu_spec cpu_specs[] = {
896 .pvr_mask = 0xf0000fff, 679 .pvr_mask = 0xf0000fff,
897 .pvr_value = 0x400008d3, 680 .pvr_value = 0x400008d3,
898 .cpu_name = "440EP Rev. B", 681 .cpu_name = "440EP Rev. B",
899 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 682 .cpu_features = CPU_FTRS_44X,
900 CPU_FTR_USE_TB,
901 .cpu_user_features = COMMON_PPC, /* 440EP has an FPU */ 683 .cpu_user_features = COMMON_PPC, /* 440EP has an FPU */
902 .icache_bsize = 32, 684 .icache_bsize = 32,
903 .dcache_bsize = 32, 685 .dcache_bsize = 32,
@@ -906,8 +688,7 @@ struct cpu_spec cpu_specs[] = {
906 .pvr_mask = 0xf0000fff, 688 .pvr_mask = 0xf0000fff,
907 .pvr_value = 0x40000440, 689 .pvr_value = 0x40000440,
908 .cpu_name = "440GP Rev. B", 690 .cpu_name = "440GP Rev. B",
909 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 691 .cpu_features = CPU_FTRS_44X,
910 CPU_FTR_USE_TB,
911 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 692 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
912 .icache_bsize = 32, 693 .icache_bsize = 32,
913 .dcache_bsize = 32, 694 .dcache_bsize = 32,
@@ -916,8 +697,7 @@ struct cpu_spec cpu_specs[] = {
916 .pvr_mask = 0xf0000fff, 697 .pvr_mask = 0xf0000fff,
917 .pvr_value = 0x40000481, 698 .pvr_value = 0x40000481,
918 .cpu_name = "440GP Rev. C", 699 .cpu_name = "440GP Rev. C",
919 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 700 .cpu_features = CPU_FTRS_44X,
920 CPU_FTR_USE_TB,
921 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 701 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
922 .icache_bsize = 32, 702 .icache_bsize = 32,
923 .dcache_bsize = 32, 703 .dcache_bsize = 32,
@@ -926,8 +706,7 @@ struct cpu_spec cpu_specs[] = {
926 .pvr_mask = 0xf0000fff, 706 .pvr_mask = 0xf0000fff,
927 .pvr_value = 0x50000850, 707 .pvr_value = 0x50000850,
928 .cpu_name = "440GX Rev. A", 708 .cpu_name = "440GX Rev. A",
929 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 709 .cpu_features = CPU_FTRS_44X,
930 CPU_FTR_USE_TB,
931 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 710 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
932 .icache_bsize = 32, 711 .icache_bsize = 32,
933 .dcache_bsize = 32, 712 .dcache_bsize = 32,
@@ -936,8 +715,7 @@ struct cpu_spec cpu_specs[] = {
936 .pvr_mask = 0xf0000fff, 715 .pvr_mask = 0xf0000fff,
937 .pvr_value = 0x50000851, 716 .pvr_value = 0x50000851,
938 .cpu_name = "440GX Rev. B", 717 .cpu_name = "440GX Rev. B",
939 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 718 .cpu_features = CPU_FTRS_44X,
940 CPU_FTR_USE_TB,
941 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 719 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
942 .icache_bsize = 32, 720 .icache_bsize = 32,
943 .dcache_bsize = 32, 721 .dcache_bsize = 32,
@@ -946,8 +724,7 @@ struct cpu_spec cpu_specs[] = {
946 .pvr_mask = 0xf0000fff, 724 .pvr_mask = 0xf0000fff,
947 .pvr_value = 0x50000892, 725 .pvr_value = 0x50000892,
948 .cpu_name = "440GX Rev. C", 726 .cpu_name = "440GX Rev. C",
949 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 727 .cpu_features = CPU_FTRS_44X,
950 CPU_FTR_USE_TB,
951 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 728 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
952 .icache_bsize = 32, 729 .icache_bsize = 32,
953 .dcache_bsize = 32, 730 .dcache_bsize = 32,
@@ -956,8 +733,7 @@ struct cpu_spec cpu_specs[] = {
956 .pvr_mask = 0xf0000fff, 733 .pvr_mask = 0xf0000fff,
957 .pvr_value = 0x50000894, 734 .pvr_value = 0x50000894,
958 .cpu_name = "440GX Rev. F", 735 .cpu_name = "440GX Rev. F",
959 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 736 .cpu_features = CPU_FTRS_44X,
960 CPU_FTR_USE_TB,
961 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 737 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
962 .icache_bsize = 32, 738 .icache_bsize = 32,
963 .dcache_bsize = 32, 739 .dcache_bsize = 32,
@@ -966,8 +742,7 @@ struct cpu_spec cpu_specs[] = {
966 .pvr_mask = 0xff000fff, 742 .pvr_mask = 0xff000fff,
967 .pvr_value = 0x53000891, 743 .pvr_value = 0x53000891,
968 .cpu_name = "440SP Rev. A", 744 .cpu_name = "440SP Rev. A",
969 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 745 .cpu_features = CPU_FTRS_44X,
970 CPU_FTR_USE_TB,
971 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 746 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
972 .icache_bsize = 32, 747 .icache_bsize = 32,
973 .dcache_bsize = 32, 748 .dcache_bsize = 32,
@@ -979,7 +754,7 @@ struct cpu_spec cpu_specs[] = {
979 .pvr_value = 0x81000000, 754 .pvr_value = 0x81000000,
980 .cpu_name = "e200z5", 755 .cpu_name = "e200z5",
981 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */ 756 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
982 .cpu_features = CPU_FTR_USE_TB, 757 .cpu_features = CPU_FTRS_E200,
983 .cpu_user_features = PPC_FEATURE_32 | 758 .cpu_user_features = PPC_FEATURE_32 |
984 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_EFP_SINGLE | 759 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_EFP_SINGLE |
985 PPC_FEATURE_UNIFIED_CACHE, 760 PPC_FEATURE_UNIFIED_CACHE,
@@ -990,7 +765,7 @@ struct cpu_spec cpu_specs[] = {
990 .pvr_value = 0x81100000, 765 .pvr_value = 0x81100000,
991 .cpu_name = "e200z6", 766 .cpu_name = "e200z6",
992 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */ 767 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
993 .cpu_features = CPU_FTR_USE_TB, 768 .cpu_features = CPU_FTRS_E200,
994 .cpu_user_features = PPC_FEATURE_32 | 769 .cpu_user_features = PPC_FEATURE_32 |
995 PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP | 770 PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
996 PPC_FEATURE_HAS_EFP_SINGLE | 771 PPC_FEATURE_HAS_EFP_SINGLE |
@@ -1002,8 +777,7 @@ struct cpu_spec cpu_specs[] = {
1002 .pvr_value = 0x80200000, 777 .pvr_value = 0x80200000,
1003 .cpu_name = "e500", 778 .cpu_name = "e500",
1004 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */ 779 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
1005 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 780 .cpu_features = CPU_FTRS_E500,
1006 CPU_FTR_USE_TB,
1007 .cpu_user_features = PPC_FEATURE_32 | 781 .cpu_user_features = PPC_FEATURE_32 |
1008 PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP | 782 PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
1009 PPC_FEATURE_HAS_EFP_SINGLE, 783 PPC_FEATURE_HAS_EFP_SINGLE,
@@ -1016,8 +790,7 @@ struct cpu_spec cpu_specs[] = {
1016 .pvr_value = 0x80210000, 790 .pvr_value = 0x80210000,
1017 .cpu_name = "e500v2", 791 .cpu_name = "e500v2",
1018 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */ 792 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
1019 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 793 .cpu_features = CPU_FTRS_E500_2,
1020 CPU_FTR_USE_TB | CPU_FTR_BIG_PHYS,
1021 .cpu_user_features = PPC_FEATURE_32 | 794 .cpu_user_features = PPC_FEATURE_32 |
1022 PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP | 795 PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
1023 PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_HAS_EFP_DOUBLE, 796 PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_HAS_EFP_DOUBLE,
@@ -1031,7 +804,7 @@ struct cpu_spec cpu_specs[] = {
1031 .pvr_mask = 0x00000000, 804 .pvr_mask = 0x00000000,
1032 .pvr_value = 0x00000000, 805 .pvr_value = 0x00000000,
1033 .cpu_name = "(generic PPC)", 806 .cpu_name = "(generic PPC)",
1034 .cpu_features = CPU_FTR_COMMON, 807 .cpu_features = CPU_FTRS_GENERIC_32,
1035 .cpu_user_features = PPC_FEATURE_32, 808 .cpu_user_features = PPC_FEATURE_32,
1036 .icache_bsize = 32, 809 .icache_bsize = 32,
1037 .dcache_bsize = 32, 810 .dcache_bsize = 32,
diff --git a/arch/ppc64/kernel/cputable.c b/arch/ppc64/kernel/cputable.c
index 8831a28c3c4e..5134c53d536d 100644
--- a/arch/ppc64/kernel/cputable.c
+++ b/arch/ppc64/kernel/cputable.c
@@ -37,26 +37,13 @@ extern void __setup_cpu_power4(unsigned long offset, struct cpu_spec* spec);
37extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec); 37extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
38extern void __setup_cpu_be(unsigned long offset, struct cpu_spec* spec); 38extern void __setup_cpu_be(unsigned long offset, struct cpu_spec* spec);
39 39
40
41/* We only set the altivec features if the kernel was compiled with altivec
42 * support
43 */
44#ifdef CONFIG_ALTIVEC
45#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
46#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
47#else
48#define CPU_FTR_ALTIVEC_COMP 0
49#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
50#endif
51
52struct cpu_spec cpu_specs[] = { 40struct cpu_spec cpu_specs[] = {
53 { /* Power3 */ 41 { /* Power3 */
54 .pvr_mask = 0xffff0000, 42 .pvr_mask = 0xffff0000,
55 .pvr_value = 0x00400000, 43 .pvr_value = 0x00400000,
56 .cpu_name = "POWER3 (630)", 44 .cpu_name = "POWER3 (630)",
57 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 45 .cpu_features = CPU_FTRS_POWER3,
58 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR, 46 .cpu_user_features = COMMON_USER_PPC64,
59 .cpu_user_features = COMMON_USER_PPC64,
60 .icache_bsize = 128, 47 .icache_bsize = 128,
61 .dcache_bsize = 128, 48 .dcache_bsize = 128,
62 .num_pmcs = 8, 49 .num_pmcs = 8,
@@ -70,8 +57,7 @@ struct cpu_spec cpu_specs[] = {
70 .pvr_mask = 0xffff0000, 57 .pvr_mask = 0xffff0000,
71 .pvr_value = 0x00410000, 58 .pvr_value = 0x00410000,
72 .cpu_name = "POWER3 (630+)", 59 .cpu_name = "POWER3 (630+)",
73 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 60 .cpu_features = CPU_FTRS_POWER3,
74 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
75 .cpu_user_features = COMMON_USER_PPC64, 61 .cpu_user_features = COMMON_USER_PPC64,
76 .icache_bsize = 128, 62 .icache_bsize = 128,
77 .dcache_bsize = 128, 63 .dcache_bsize = 128,
@@ -86,9 +72,7 @@ struct cpu_spec cpu_specs[] = {
86 .pvr_mask = 0xffff0000, 72 .pvr_mask = 0xffff0000,
87 .pvr_value = 0x00330000, 73 .pvr_value = 0x00330000,
88 .cpu_name = "RS64-II (northstar)", 74 .cpu_name = "RS64-II (northstar)",
89 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 75 .cpu_features = CPU_FTRS_RS64,
90 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
91 CPU_FTR_MMCRA | CPU_FTR_CTRL,
92 .cpu_user_features = COMMON_USER_PPC64, 76 .cpu_user_features = COMMON_USER_PPC64,
93 .icache_bsize = 128, 77 .icache_bsize = 128,
94 .dcache_bsize = 128, 78 .dcache_bsize = 128,
@@ -103,9 +87,7 @@ struct cpu_spec cpu_specs[] = {
103 .pvr_mask = 0xffff0000, 87 .pvr_mask = 0xffff0000,
104 .pvr_value = 0x00340000, 88 .pvr_value = 0x00340000,
105 .cpu_name = "RS64-III (pulsar)", 89 .cpu_name = "RS64-III (pulsar)",
106 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 90 .cpu_features = CPU_FTRS_RS64,
107 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
108 CPU_FTR_MMCRA | CPU_FTR_CTRL,
109 .cpu_user_features = COMMON_USER_PPC64, 91 .cpu_user_features = COMMON_USER_PPC64,
110 .icache_bsize = 128, 92 .icache_bsize = 128,
111 .dcache_bsize = 128, 93 .dcache_bsize = 128,
@@ -120,9 +102,7 @@ struct cpu_spec cpu_specs[] = {
120 .pvr_mask = 0xffff0000, 102 .pvr_mask = 0xffff0000,
121 .pvr_value = 0x00360000, 103 .pvr_value = 0x00360000,
122 .cpu_name = "RS64-III (icestar)", 104 .cpu_name = "RS64-III (icestar)",
123 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 105 .cpu_features = CPU_FTRS_RS64,
124 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
125 CPU_FTR_MMCRA | CPU_FTR_CTRL,
126 .cpu_user_features = COMMON_USER_PPC64, 106 .cpu_user_features = COMMON_USER_PPC64,
127 .icache_bsize = 128, 107 .icache_bsize = 128,
128 .dcache_bsize = 128, 108 .dcache_bsize = 128,
@@ -137,9 +117,7 @@ struct cpu_spec cpu_specs[] = {
137 .pvr_mask = 0xffff0000, 117 .pvr_mask = 0xffff0000,
138 .pvr_value = 0x00370000, 118 .pvr_value = 0x00370000,
139 .cpu_name = "RS64-IV (sstar)", 119 .cpu_name = "RS64-IV (sstar)",
140 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 120 .cpu_features = CPU_FTRS_RS64,
141 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
142 CPU_FTR_MMCRA | CPU_FTR_CTRL,
143 .cpu_user_features = COMMON_USER_PPC64, 121 .cpu_user_features = COMMON_USER_PPC64,
144 .icache_bsize = 128, 122 .icache_bsize = 128,
145 .dcache_bsize = 128, 123 .dcache_bsize = 128,
@@ -154,9 +132,7 @@ struct cpu_spec cpu_specs[] = {
154 .pvr_mask = 0xffff0000, 132 .pvr_mask = 0xffff0000,
155 .pvr_value = 0x00350000, 133 .pvr_value = 0x00350000,
156 .cpu_name = "POWER4 (gp)", 134 .cpu_name = "POWER4 (gp)",
157 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 135 .cpu_features = CPU_FTRS_POWER4,
158 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
159 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
160 .cpu_user_features = COMMON_USER_PPC64, 136 .cpu_user_features = COMMON_USER_PPC64,
161 .icache_bsize = 128, 137 .icache_bsize = 128,
162 .dcache_bsize = 128, 138 .dcache_bsize = 128,
@@ -171,9 +147,7 @@ struct cpu_spec cpu_specs[] = {
171 .pvr_mask = 0xffff0000, 147 .pvr_mask = 0xffff0000,
172 .pvr_value = 0x00380000, 148 .pvr_value = 0x00380000,
173 .cpu_name = "POWER4+ (gq)", 149 .cpu_name = "POWER4+ (gq)",
174 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 150 .cpu_features = CPU_FTRS_POWER4,
175 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
176 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
177 .cpu_user_features = COMMON_USER_PPC64, 151 .cpu_user_features = COMMON_USER_PPC64,
178 .icache_bsize = 128, 152 .icache_bsize = 128,
179 .dcache_bsize = 128, 153 .dcache_bsize = 128,
@@ -188,10 +162,7 @@ struct cpu_spec cpu_specs[] = {
188 .pvr_mask = 0xffff0000, 162 .pvr_mask = 0xffff0000,
189 .pvr_value = 0x00390000, 163 .pvr_value = 0x00390000,
190 .cpu_name = "PPC970", 164 .cpu_name = "PPC970",
191 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 165 .cpu_features = CPU_FTRS_PPC970,
192 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
193 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
194 CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
195 .cpu_user_features = COMMON_USER_PPC64 | 166 .cpu_user_features = COMMON_USER_PPC64 |
196 PPC_FEATURE_HAS_ALTIVEC_COMP, 167 PPC_FEATURE_HAS_ALTIVEC_COMP,
197 .icache_bsize = 128, 168 .icache_bsize = 128,
@@ -207,10 +178,7 @@ struct cpu_spec cpu_specs[] = {
207 .pvr_mask = 0xffff0000, 178 .pvr_mask = 0xffff0000,
208 .pvr_value = 0x003c0000, 179 .pvr_value = 0x003c0000,
209 .cpu_name = "PPC970FX", 180 .cpu_name = "PPC970FX",
210 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 181 .cpu_features = CPU_FTRS_PPC970,
211 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
212 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
213 CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
214 .cpu_user_features = COMMON_USER_PPC64 | 182 .cpu_user_features = COMMON_USER_PPC64 |
215 PPC_FEATURE_HAS_ALTIVEC_COMP, 183 PPC_FEATURE_HAS_ALTIVEC_COMP,
216 .icache_bsize = 128, 184 .icache_bsize = 128,
@@ -226,10 +194,7 @@ struct cpu_spec cpu_specs[] = {
226 .pvr_mask = 0xffff0000, 194 .pvr_mask = 0xffff0000,
227 .pvr_value = 0x00440000, 195 .pvr_value = 0x00440000,
228 .cpu_name = "PPC970MP", 196 .cpu_name = "PPC970MP",
229 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 197 .cpu_features = CPU_FTRS_PPC970,
230 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
231 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
232 CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
233 .cpu_user_features = COMMON_USER_PPC64 | 198 .cpu_user_features = COMMON_USER_PPC64 |
234 PPC_FEATURE_HAS_ALTIVEC_COMP, 199 PPC_FEATURE_HAS_ALTIVEC_COMP,
235 .icache_bsize = 128, 200 .icache_bsize = 128,
@@ -244,11 +209,7 @@ struct cpu_spec cpu_specs[] = {
244 .pvr_mask = 0xffff0000, 209 .pvr_mask = 0xffff0000,
245 .pvr_value = 0x003a0000, 210 .pvr_value = 0x003a0000,
246 .cpu_name = "POWER5 (gr)", 211 .cpu_name = "POWER5 (gr)",
247 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 212 .cpu_features = CPU_FTRS_POWER5,
248 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
249 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
250 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
251 CPU_FTR_MMCRA_SIHV,
252 .cpu_user_features = COMMON_USER_PPC64, 213 .cpu_user_features = COMMON_USER_PPC64,
253 .icache_bsize = 128, 214 .icache_bsize = 128,
254 .dcache_bsize = 128, 215 .dcache_bsize = 128,
@@ -263,11 +224,7 @@ struct cpu_spec cpu_specs[] = {
263 .pvr_mask = 0xffff0000, 224 .pvr_mask = 0xffff0000,
264 .pvr_value = 0x003b0000, 225 .pvr_value = 0x003b0000,
265 .cpu_name = "POWER5 (gs)", 226 .cpu_name = "POWER5 (gs)",
266 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 227 .cpu_features = CPU_FTRS_POWER5,
267 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
268 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
269 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
270 CPU_FTR_MMCRA_SIHV,
271 .cpu_user_features = COMMON_USER_PPC64, 228 .cpu_user_features = COMMON_USER_PPC64,
272 .icache_bsize = 128, 229 .icache_bsize = 128,
273 .dcache_bsize = 128, 230 .dcache_bsize = 128,
@@ -281,11 +238,8 @@ struct cpu_spec cpu_specs[] = {
281 { /* BE DD1.x */ 238 { /* BE DD1.x */
282 .pvr_mask = 0xffff0000, 239 .pvr_mask = 0xffff0000,
283 .pvr_value = 0x00700000, 240 .pvr_value = 0x00700000,
284 .cpu_name = "Broadband Engine", 241 .cpu_name = "Cell Broadband Engine",
285 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 242 .cpu_features = CPU_FTRS_CELL,
286 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
287 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
288 CPU_FTR_SMT,
289 .cpu_user_features = COMMON_USER_PPC64 | 243 .cpu_user_features = COMMON_USER_PPC64 |
290 PPC_FEATURE_HAS_ALTIVEC_COMP, 244 PPC_FEATURE_HAS_ALTIVEC_COMP,
291 .icache_bsize = 128, 245 .icache_bsize = 128,
@@ -296,9 +250,7 @@ struct cpu_spec cpu_specs[] = {
296 .pvr_mask = 0x00000000, 250 .pvr_mask = 0x00000000,
297 .pvr_value = 0x00000000, 251 .pvr_value = 0x00000000,
298 .cpu_name = "POWER4 (compatible)", 252 .cpu_name = "POWER4 (compatible)",
299 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 253 .cpu_features = CPU_FTRS_COMPATIBLE,
300 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
301 CPU_FTR_PPCAS_ARCH_V2,
302 .cpu_user_features = COMMON_USER_PPC64, 254 .cpu_user_features = COMMON_USER_PPC64,
303 .icache_bsize = 128, 255 .icache_bsize = 128,
304 .dcache_bsize = 128, 256 .dcache_bsize = 128,
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h
new file mode 100644
index 000000000000..5f81d44963f1
--- /dev/null
+++ b/include/asm-powerpc/cputable.h
@@ -0,0 +1,442 @@
1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
4#include <linux/config.h>
5#include <asm/ppc_asm.h> /* for ASM_CONST */
6
7#define PPC_FEATURE_32 0x80000000
8#define PPC_FEATURE_64 0x40000000
9#define PPC_FEATURE_601_INSTR 0x20000000
10#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
11#define PPC_FEATURE_HAS_FPU 0x08000000
12#define PPC_FEATURE_HAS_MMU 0x04000000
13#define PPC_FEATURE_HAS_4xxMAC 0x02000000
14#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
15#define PPC_FEATURE_HAS_SPE 0x00800000
16#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
17#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
18
19#ifdef __KERNEL__
20#ifndef __ASSEMBLY__
21
22/* This structure can grow, it's real size is used by head.S code
23 * via the mkdefs mechanism.
24 */
25struct cpu_spec;
26struct op_powerpc_model;
27
28#ifdef __powerpc64__
29typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
30#else /* __powerpc64__ */
31typedef void (*cpu_setup_t)(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
32#endif /* __powerpc64__ */
33
34struct cpu_spec {
35 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
36 unsigned int pvr_mask;
37 unsigned int pvr_value;
38
39 char *cpu_name;
40 unsigned long cpu_features; /* Kernel features */
41 unsigned int cpu_user_features; /* Userland features */
42
43 /* cache line sizes */
44 unsigned int icache_bsize;
45 unsigned int dcache_bsize;
46
47 /* number of performance monitor counters */
48 unsigned int num_pmcs;
49
50 /* this is called to initialize various CPU bits like L1 cache,
51 * BHT, SPD, etc... from head.S before branching to identify_machine
52 */
53 cpu_setup_t cpu_setup;
54#ifdef __powerpc64__
55
56 /* Used by oprofile userspace to select the right counters */
57 char *oprofile_cpu_type;
58
59 /* Processor specific oprofile operations */
60 struct op_powerpc_model *oprofile_model;
61#endif /* __powerpc64__ */
62};
63
64extern struct cpu_spec cpu_specs[];
65
66#ifdef __powerpc64__
67extern struct cpu_spec *cur_cpu_spec;
68#else /* __powerpc64__ */
69extern struct cpu_spec *cur_cpu_spec[];
70#endif /* __powerpc64__ */
71
72#endif /* __ASSEMBLY__ */
73
74/* CPU kernel features */
75
76/* Retain the 32b definitions all use bottom half of word */
77#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
78#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
79#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
80#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
81#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
82#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
83#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
84#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
85#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
86#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
87#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
88#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
89#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
90#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
91#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
92#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
93#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
94#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
95#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
96#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
97
98#ifdef __powerpc64__
99/* Add the 64b processor unique features in the top half of the word */
100#define CPU_FTR_SLB ASM_CONST(0x0000000100000000)
101#define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000)
102#define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000)
103#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000)
104#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000001000000000)
105#define CPU_FTR_IABR ASM_CONST(0x0000002000000000)
106#define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000)
107#define CPU_FTR_CTRL ASM_CONST(0x0000008000000000)
108#define CPU_FTR_SMT ASM_CONST(0x0000010000000000)
109#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
110#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
111#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000)
112#else
113/* ensure on 32b processors the flags are available for compiling but
114 * don't do anything */
115#define CPU_FTR_SLB ASM_CONST(0x0)
116#define CPU_FTR_16M_PAGE ASM_CONST(0x0)
117#define CPU_FTR_TLBIEL ASM_CONST(0x0)
118#define CPU_FTR_NOEXECUTE ASM_CONST(0x0)
119#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0)
120#define CPU_FTR_IABR ASM_CONST(0x0)
121#define CPU_FTR_MMCRA ASM_CONST(0x0)
122#define CPU_FTR_CTRL ASM_CONST(0x0)
123#define CPU_FTR_SMT ASM_CONST(0x0)
124#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0)
125#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0)
126#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0)
127#endif
128
129#ifndef __ASSEMBLY__
130
131#define COMMON_USER_PPC64 (PPC_FEATURE_32 | PPC_FEATURE_64 | \
132 PPC_FEATURE_HAS_FPU | PPC_FEATURE_HAS_MMU)
133
134#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
135 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
136 CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
137
138/* iSeries doesn't support large pages */
139#ifdef CONFIG_PPC_ISERIES
140#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
141#else
142#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
143#endif /* CONFIG_PPC_ISERIES */
144
145/* We only set the altivec features if the kernel was compiled with altivec
146 * support
147 */
148#ifdef CONFIG_ALTIVEC
149#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
150#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
151#else
152#define CPU_FTR_ALTIVEC_COMP 0
153#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
154#endif
155
156/* We need to mark all pages as being coherent if we're SMP or we
157 * have a 74[45]x and an MPC107 host bridge.
158 */
159#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
160#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
161#else
162#define CPU_FTR_COMMON 0
163#endif
164
165/* The powersave features NAP & DOZE seems to confuse BDI when
166 debugging. So if a BDI is used, disable theses
167 */
168#ifndef CONFIG_BDI_SWITCH
169#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
170#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
171#else
172#define CPU_FTR_MAYBE_CAN_DOZE 0
173#define CPU_FTR_MAYBE_CAN_NAP 0
174#endif
175
176#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
177 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
178 !defined(CONFIG_BOOKE))
179
180enum {
181 CPU_FTRS_PPC601 = CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE,
182 CPU_FTRS_603 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
183 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
184 CPU_FTR_MAYBE_CAN_NAP,
185 CPU_FTRS_604 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
186 CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
187 CPU_FTRS_740_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
188 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
189 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
190 CPU_FTRS_740 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
191 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
192 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
193 CPU_FTRS_750 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
194 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
195 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
196 CPU_FTRS_750FX1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
197 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
198 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
199 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
200 CPU_FTRS_750FX2 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
201 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
202 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
203 CPU_FTR_NO_DPM,
204 CPU_FTRS_750FX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
205 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
206 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
207 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
208 CPU_FTRS_750GX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
209 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
210 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
211 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
212 CPU_FTRS_7400_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
213 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
214 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
215 CPU_FTR_MAYBE_CAN_NAP,
216 CPU_FTRS_7400 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
217 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
218 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
219 CPU_FTR_MAYBE_CAN_NAP,
220 CPU_FTRS_7450_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
221 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
222 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
223 CPU_FTR_NEED_COHERENT,
224 CPU_FTRS_7450_21 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
225 CPU_FTR_USE_TB |
226 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
227 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
228 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
229 CPU_FTR_NEED_COHERENT,
230 CPU_FTRS_7450_23 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
231 CPU_FTR_USE_TB |
232 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
233 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
234 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT,
235 CPU_FTRS_7455_1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
236 CPU_FTR_USE_TB |
237 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
238 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS |
239 CPU_FTR_NEED_COHERENT,
240 CPU_FTRS_7455_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
241 CPU_FTR_USE_TB |
242 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
243 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
244 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
245 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
246 CPU_FTRS_7455 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
247 CPU_FTR_USE_TB |
248 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
249 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
250 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
251 CPU_FTR_NEED_COHERENT,
252 CPU_FTRS_7447_10 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
253 CPU_FTR_USE_TB |
254 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
255 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
256 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
257 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
258 CPU_FTRS_7447 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
259 CPU_FTR_USE_TB |
260 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
261 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
262 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
263 CPU_FTR_NEED_COHERENT,
264 CPU_FTRS_7447A = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
265 CPU_FTR_USE_TB |
266 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
267 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
268 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
269 CPU_FTR_NEED_COHERENT,
270 CPU_FTRS_82XX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
271 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB,
272 CPU_FTRS_G2_LE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
273 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
274 CPU_FTRS_E300 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
275 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
276 CPU_FTRS_CLASSIC32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
277 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
278 CPU_FTRS_POWER3_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
279 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
280 CPU_FTRS_POWER4_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
281 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
282 CPU_FTRS_970_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
283 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_ALTIVEC_COMP |
284 CPU_FTR_MAYBE_CAN_NAP,
285 CPU_FTRS_8XX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
286 CPU_FTRS_40X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
287 CPU_FTRS_44X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
288 CPU_FTRS_E200 = CPU_FTR_USE_TB,
289 CPU_FTRS_E500 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
290 CPU_FTRS_E500_2 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
291 CPU_FTR_BIG_PHYS,
292 CPU_FTRS_GENERIC_32 = CPU_FTR_COMMON,
293#ifdef __powerpc64__
294 CPU_FTRS_POWER3 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
295 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
296 CPU_FTRS_RS64 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
297 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
298 CPU_FTR_MMCRA | CPU_FTR_CTRL,
299 CPU_FTRS_POWER4 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
300 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
301 CPU_FTRS_PPC970 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
302 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
303 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
304 CPU_FTRS_POWER5 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
305 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
306 CPU_FTR_MMCRA | CPU_FTR_SMT |
307 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
308 CPU_FTR_MMCRA_SIHV,
309 CPU_FTRS_CELL = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
310 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
311 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT,
312 CPU_FTRS_COMPATIBLE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
313 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2,
314#endif
315
316 CPU_FTRS_POSSIBLE =
317#if CLASSIC_PPC
318 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
319 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
320 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
321 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
322 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
323 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
324 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
325 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 |
326#else
327 CPU_FTRS_GENERIC_32 |
328#endif
329#ifdef CONFIG_PPC64BRIDGE
330 CPU_FTRS_POWER3_32 |
331#endif
332#ifdef CONFIG_POWER4
333 CPU_FTRS_POWER4_32 | CPU_FTRS_970_32 |
334#endif
335#ifdef CONFIG_8xx
336 CPU_FTRS_8XX |
337#endif
338#ifdef CONFIG_40x
339 CPU_FTRS_40X |
340#endif
341#ifdef CONFIG_44x
342 CPU_FTRS_44X |
343#endif
344#ifdef CONFIG_E200
345 CPU_FTRS_E200 |
346#endif
347#ifdef CONFIG_E500
348 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
349#endif
350#ifdef __powerpc64__
351 CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |
352 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_CELL |
353#endif
354 0,
355
356 CPU_FTRS_ALWAYS =
357#if CLASSIC_PPC
358 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
359 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
360 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
361 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
362 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
363 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
364 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
365 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 &
366#else
367 CPU_FTRS_GENERIC_32 &
368#endif
369#ifdef CONFIG_PPC64BRIDGE
370 CPU_FTRS_POWER3_32 &
371#endif
372#ifdef CONFIG_POWER4
373 CPU_FTRS_POWER4_32 & CPU_FTRS_970_32 &
374#endif
375#ifdef CONFIG_8xx
376 CPU_FTRS_8XX &
377#endif
378#ifdef CONFIG_40x
379 CPU_FTRS_40X &
380#endif
381#ifdef CONFIG_44x
382 CPU_FTRS_44X &
383#endif
384#ifdef CONFIG_E200
385 CPU_FTRS_E200 &
386#endif
387#ifdef CONFIG_E500
388 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
389#endif
390#ifdef __powerpc64__
391 CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &
392 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_CELL &
393#endif
394 CPU_FTRS_POSSIBLE,
395};
396
397static inline int cpu_has_feature(unsigned long feature)
398{
399 return (CPU_FTRS_ALWAYS & feature) ||
400 (CPU_FTRS_POSSIBLE
401#ifndef __powerpc64__
402 & cur_cpu_spec[0]->cpu_features
403#else
404 & cur_cpu_spec->cpu_features
405#endif
406 & feature);
407}
408
409#endif /* !__ASSEMBLY__ */
410
411#ifdef __ASSEMBLY__
412
413#define BEGIN_FTR_SECTION 98:
414
415#ifndef __powerpc64__
416#define END_FTR_SECTION(msk, val) \
41799: \
418 .section __ftr_fixup,"a"; \
419 .align 2; \
420 .long msk; \
421 .long val; \
422 .long 98b; \
423 .long 99b; \
424 .previous
425#else /* __powerpc64__ */
426#define END_FTR_SECTION(msk, val) \
42799: \
428 .section __ftr_fixup,"a"; \
429 .align 3; \
430 .llong msk; \
431 .llong val; \
432 .llong 98b; \
433 .llong 99b; \
434 .previous
435#endif /* __powerpc64__ */
436
437#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
438#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
439#endif /* __ASSEMBLY__ */
440
441#endif /* __KERNEL__ */
442#endif /* __ASM_POWERPC_CPUTABLE_H */
diff --git a/include/asm-ppc/cputable.h b/include/asm-ppc/cputable.h
deleted file mode 100644
index 41d8f8425c04..000000000000
--- a/include/asm-ppc/cputable.h
+++ /dev/null
@@ -1,128 +0,0 @@
1/*
2 * include/asm-ppc/cputable.h
3 *
4 * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#ifndef __ASM_PPC_CPUTABLE_H
13#define __ASM_PPC_CPUTABLE_H
14
15/* Exposed to userland CPU features */
16#define PPC_FEATURE_32 0x80000000
17#define PPC_FEATURE_64 0x40000000
18#define PPC_FEATURE_601_INSTR 0x20000000
19#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
20#define PPC_FEATURE_HAS_FPU 0x08000000
21#define PPC_FEATURE_HAS_MMU 0x04000000
22#define PPC_FEATURE_HAS_4xxMAC 0x02000000
23#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
24#define PPC_FEATURE_HAS_SPE 0x00800000
25#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
26#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
27
28#ifdef __KERNEL__
29
30#ifndef __ASSEMBLY__
31
32/* This structure can grow, it's real size is used by head.S code
33 * via the mkdefs mecanism.
34 */
35struct cpu_spec;
36
37typedef void (*cpu_setup_t)(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
38
39struct cpu_spec {
40 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
41 unsigned int pvr_mask;
42 unsigned int pvr_value;
43
44 char *cpu_name;
45 unsigned int cpu_features; /* Kernel features */
46 unsigned int cpu_user_features; /* Userland features */
47
48 /* cache line sizes */
49 unsigned int icache_bsize;
50 unsigned int dcache_bsize;
51
52 /* number of performance monitor counters */
53 unsigned int num_pmcs;
54
55 /* this is called to initialize various CPU bits like L1 cache,
56 * BHT, SPD, etc... from head.S before branching to identify_machine
57 */
58 cpu_setup_t cpu_setup;
59};
60
61extern struct cpu_spec cpu_specs[];
62extern struct cpu_spec *cur_cpu_spec[];
63
64static inline unsigned int cpu_has_feature(unsigned int feature)
65{
66 return cur_cpu_spec[0]->cpu_features & feature;
67}
68
69#endif /* __ASSEMBLY__ */
70
71/* CPU kernel features */
72#define CPU_FTR_SPLIT_ID_CACHE 0x00000001
73#define CPU_FTR_L2CR 0x00000002
74#define CPU_FTR_SPEC7450 0x00000004
75#define CPU_FTR_ALTIVEC 0x00000008
76#define CPU_FTR_TAU 0x00000010
77#define CPU_FTR_CAN_DOZE 0x00000020
78#define CPU_FTR_USE_TB 0x00000040
79#define CPU_FTR_604_PERF_MON 0x00000080
80#define CPU_FTR_601 0x00000100
81#define CPU_FTR_HPTE_TABLE 0x00000200
82#define CPU_FTR_CAN_NAP 0x00000400
83#define CPU_FTR_L3CR 0x00000800
84#define CPU_FTR_L3_DISABLE_NAP 0x00001000
85#define CPU_FTR_NAP_DISABLE_L2_PR 0x00002000
86#define CPU_FTR_DUAL_PLL_750FX 0x00004000
87#define CPU_FTR_NO_DPM 0x00008000
88#define CPU_FTR_HAS_HIGH_BATS 0x00010000
89#define CPU_FTR_NEED_COHERENT 0x00020000
90#define CPU_FTR_NO_BTIC 0x00040000
91#define CPU_FTR_BIG_PHYS 0x00080000
92
93#ifdef __ASSEMBLY__
94
95#define BEGIN_FTR_SECTION 98:
96
97#define END_FTR_SECTION(msk, val) \
9899: \
99 .section __ftr_fixup,"a"; \
100 .align 2; \
101 .long msk; \
102 .long val; \
103 .long 98b; \
104 .long 99b; \
105 .previous
106
107#else
108
109#define BEGIN_FTR_SECTION "98:\n"
110#define END_FTR_SECTION(msk, val) \
111"99:\n" \
112" .section __ftr_fixup,\"a\";\n" \
113" .align 2;\n" \
114" .long "#msk";\n" \
115" .long "#val";\n" \
116" .long 98b;\n" \
117" .long 99b;\n" \
118" .previous\n"
119
120
121#endif /* __ASSEMBLY__ */
122
123#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
124#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
125
126#endif /* __ASM_PPC_CPUTABLE_H */
127#endif /* __KERNEL__ */
128
diff --git a/include/asm-ppc/mmu_context.h b/include/asm-ppc/mmu_context.h
index afe26ffc2e2d..4f152cca13c1 100644
--- a/include/asm-ppc/mmu_context.h
+++ b/include/asm-ppc/mmu_context.h
@@ -164,13 +164,11 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
164 struct task_struct *tsk) 164 struct task_struct *tsk)
165{ 165{
166#ifdef CONFIG_ALTIVEC 166#ifdef CONFIG_ALTIVEC
167 asm volatile ( 167 if (cpu_has_feature(CPU_FTR_ALTIVEC))
168 BEGIN_FTR_SECTION 168 asm volatile ("dssall;\n"
169 "dssall;\n"
170#ifndef CONFIG_POWER4 169#ifndef CONFIG_POWER4
171 "sync;\n" /* G4 needs a sync here, G5 apparently not */ 170 "sync;\n" /* G4 needs a sync here, G5 apparently not */
172#endif 171#endif
173 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
174 : : ); 172 : : );
175#endif /* CONFIG_ALTIVEC */ 173#endif /* CONFIG_ALTIVEC */
176 174
diff --git a/include/asm-ppc64/cputable.h b/include/asm-ppc64/cputable.h
deleted file mode 100644
index 3eef40efd082..000000000000
--- a/include/asm-ppc64/cputable.h
+++ /dev/null
@@ -1,167 +0,0 @@
1/*
2 * include/asm-ppc64/cputable.h
3 *
4 * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
5 *
6 * Modifications for ppc64:
7 * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
15#ifndef __ASM_PPC_CPUTABLE_H
16#define __ASM_PPC_CPUTABLE_H
17
18#include <linux/config.h>
19#include <asm/ppc_asm.h> /* for ASM_CONST */
20
21/* Exposed to userland CPU features - Must match ppc32 definitions */
22#define PPC_FEATURE_32 0x80000000
23#define PPC_FEATURE_64 0x40000000
24#define PPC_FEATURE_601_INSTR 0x20000000
25#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
26#define PPC_FEATURE_HAS_FPU 0x08000000
27#define PPC_FEATURE_HAS_MMU 0x04000000
28#define PPC_FEATURE_HAS_4xxMAC 0x02000000
29#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
30
31#ifdef __KERNEL__
32
33#ifndef __ASSEMBLY__
34
35/* This structure can grow, it's real size is used by head.S code
36 * via the mkdefs mechanism.
37 */
38struct cpu_spec;
39struct op_powerpc_model;
40
41typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
42
43struct cpu_spec {
44 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
45 unsigned int pvr_mask;
46 unsigned int pvr_value;
47
48 char *cpu_name;
49 unsigned long cpu_features; /* Kernel features */
50 unsigned int cpu_user_features; /* Userland features */
51
52 /* cache line sizes */
53 unsigned int icache_bsize;
54 unsigned int dcache_bsize;
55
56 /* number of performance monitor counters */
57 unsigned int num_pmcs;
58
59 /* this is called to initialize various CPU bits like L1 cache,
60 * BHT, SPD, etc... from head.S before branching to identify_machine
61 */
62 cpu_setup_t cpu_setup;
63
64 /* Used by oprofile userspace to select the right counters */
65 char *oprofile_cpu_type;
66
67 /* Processor specific oprofile operations */
68 struct op_powerpc_model *oprofile_model;
69};
70
71extern struct cpu_spec cpu_specs[];
72extern struct cpu_spec *cur_cpu_spec;
73
74static inline unsigned long cpu_has_feature(unsigned long feature)
75{
76 return cur_cpu_spec->cpu_features & feature;
77}
78
79#endif /* __ASSEMBLY__ */
80
81/* CPU kernel features */
82
83/* Retain the 32b definitions for the time being - use bottom half of word */
84#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
85#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
86#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
87#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
88#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
89#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
90#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
91#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
92#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
93#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
94#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
95#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
96#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
97#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
98#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
99
100/* Add the 64b processor unique features in the top half of the word */
101#define CPU_FTR_SLB ASM_CONST(0x0000000100000000)
102#define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000)
103#define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000)
104#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000)
105#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000001000000000)
106#define CPU_FTR_IABR ASM_CONST(0x0000002000000000)
107#define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000)
108/* unused ASM_CONST(0x0000008000000000) */
109#define CPU_FTR_SMT ASM_CONST(0x0000010000000000)
110#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
111#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
112#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000)
113#define CPU_FTR_CTRL ASM_CONST(0x0000100000000000)
114
115#ifndef __ASSEMBLY__
116
117#define COMMON_USER_PPC64 (PPC_FEATURE_32 | PPC_FEATURE_64 | \
118 PPC_FEATURE_HAS_FPU | PPC_FEATURE_HAS_MMU)
119
120#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
121 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
122 CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
123
124/* iSeries doesn't support large pages */
125#ifdef CONFIG_PPC_ISERIES
126#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
127#else
128#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
129#endif /* CONFIG_PPC_ISERIES */
130
131#endif /* __ASSEMBLY */
132
133#ifdef __ASSEMBLY__
134
135#define BEGIN_FTR_SECTION 98:
136
137#define END_FTR_SECTION(msk, val) \
13899: \
139 .section __ftr_fixup,"a"; \
140 .align 3; \
141 .llong msk; \
142 .llong val; \
143 .llong 98b; \
144 .llong 99b; \
145 .previous
146
147#else
148
149#define BEGIN_FTR_SECTION "98:\n"
150#define END_FTR_SECTION(msk, val) \
151"99:\n" \
152" .section __ftr_fixup,\"a\";\n" \
153" .align 3;\n" \
154" .llong "#msk";\n" \
155" .llong "#val";\n" \
156" .llong 98b;\n" \
157" .llong 99b;\n" \
158" .previous\n"
159
160#endif /* __ASSEMBLY__ */
161
162#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
163#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
164
165#endif /* __ASM_PPC_CPUTABLE_H */
166#endif /* __KERNEL__ */
167
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-08 17:23:21 -0500