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authorHyok S. Choi <hyok.choi@samsung.com>2006-09-26 04:36:37 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-09-27 12:28:47 -0400
commitfefdaa06ccdde394be865ed76509be82813e425b (patch)
tree66be18fac28b847e33ff24f8d2a878fa35b3450c
parent6a570b28b5948e7bf54ea42ec3161bded0a1c460 (diff)
[ARM] nommu: defines CPU_CP15, CPU_CP15_MMU and CPU_CP15_MPU
By merging of uClinux/ARM, we need to treat various CPU cores which have MMU, MPU or even none for memory management. The memory management coprocessors are controlled by CP15 register set and the ARM core family can be categorized by 5 groups by the register ; G-a. CP15 is MMU : 610, 710, 720, 920, 922, 925, 926, 1020, 1020e, 1022, v6 and the derivations sa1100, sa110, xscale, xsc3. G-b. CP15 is MPU : 740, 940, 946, 996, 1156. G-c. CP15 is MPU or MMU : 1026 (selectable by schematic design) G-d. CP15 is exist, but nothing for memory managemnt : 966, 968. G-e. no-CP15 : 7tdmi, 9tdmi, 9e, 9ej This patch defines CPU_CP15, CPU_CP15_MMU and CPU_CP15_MPU. Thus the family can be defined as : - CPU_CP15 only : G-d - CPU_CP15_MMU(implies CPU_CP15) : G-a, G-c(selectable) - CPU_CP15_MPU(implies CPU_CP15) : G-b, G-c(selectable) - !CPU_CP15 : G-e Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r--arch/arm/mm/Kconfig33
1 files changed, 33 insertions, 0 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index b59c74100a84..c7fb835c148c 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -15,6 +15,7 @@ config CPU_ARM610
15 select CPU_32v3 15 select CPU_32v3
16 select CPU_CACHE_V3 16 select CPU_CACHE_V3
17 select CPU_CACHE_VIVT 17 select CPU_CACHE_VIVT
18 select CPU_CP15_MMU
18 select CPU_COPY_V3 if MMU 19 select CPU_COPY_V3 if MMU
19 select CPU_TLB_V3 if MMU 20 select CPU_TLB_V3 if MMU
20 help 21 help
@@ -31,6 +32,7 @@ config CPU_ARM710
31 select CPU_32v3 32 select CPU_32v3
32 select CPU_CACHE_V3 33 select CPU_CACHE_V3
33 select CPU_CACHE_VIVT 34 select CPU_CACHE_VIVT
35 select CPU_CP15_MMU
34 select CPU_COPY_V3 if MMU 36 select CPU_COPY_V3 if MMU
35 select CPU_TLB_V3 if MMU 37 select CPU_TLB_V3 if MMU
36 help 38 help
@@ -50,6 +52,7 @@ config CPU_ARM720T
50 select CPU_ABRT_LV4T 52 select CPU_ABRT_LV4T
51 select CPU_CACHE_V4 53 select CPU_CACHE_V4
52 select CPU_CACHE_VIVT 54 select CPU_CACHE_VIVT
55 select CPU_CP15_MMU
53 select CPU_COPY_V4WT if MMU 56 select CPU_COPY_V4WT if MMU
54 select CPU_TLB_V4WT if MMU 57 select CPU_TLB_V4WT if MMU
55 help 58 help
@@ -68,6 +71,7 @@ config CPU_ARM920T
68 select CPU_ABRT_EV4T 71 select CPU_ABRT_EV4T
69 select CPU_CACHE_V4WT 72 select CPU_CACHE_V4WT
70 select CPU_CACHE_VIVT 73 select CPU_CACHE_VIVT
74 select CPU_CP15_MMU
71 select CPU_COPY_V4WB if MMU 75 select CPU_COPY_V4WB if MMU
72 select CPU_TLB_V4WBI if MMU 76 select CPU_TLB_V4WBI if MMU
73 help 77 help
@@ -89,6 +93,7 @@ config CPU_ARM922T
89 select CPU_ABRT_EV4T 93 select CPU_ABRT_EV4T
90 select CPU_CACHE_V4WT 94 select CPU_CACHE_V4WT
91 select CPU_CACHE_VIVT 95 select CPU_CACHE_VIVT
96 select CPU_CP15_MMU
92 select CPU_COPY_V4WB if MMU 97 select CPU_COPY_V4WB if MMU
93 select CPU_TLB_V4WBI if MMU 98 select CPU_TLB_V4WBI if MMU
94 help 99 help
@@ -108,6 +113,7 @@ config CPU_ARM925T
108 select CPU_ABRT_EV4T 113 select CPU_ABRT_EV4T
109 select CPU_CACHE_V4WT 114 select CPU_CACHE_V4WT
110 select CPU_CACHE_VIVT 115 select CPU_CACHE_VIVT
116 select CPU_CP15_MMU
111 select CPU_COPY_V4WB if MMU 117 select CPU_COPY_V4WB if MMU
112 select CPU_TLB_V4WBI if MMU 118 select CPU_TLB_V4WBI if MMU
113 help 119 help
@@ -126,6 +132,7 @@ config CPU_ARM926T
126 select CPU_32v5 132 select CPU_32v5
127 select CPU_ABRT_EV5TJ 133 select CPU_ABRT_EV5TJ
128 select CPU_CACHE_VIVT 134 select CPU_CACHE_VIVT
135 select CPU_CP15_MMU
129 select CPU_COPY_V4WB if MMU 136 select CPU_COPY_V4WB if MMU
130 select CPU_TLB_V4WBI if MMU 137 select CPU_TLB_V4WBI if MMU
131 help 138 help
@@ -144,6 +151,7 @@ config CPU_ARM1020
144 select CPU_ABRT_EV4T 151 select CPU_ABRT_EV4T
145 select CPU_CACHE_V4WT 152 select CPU_CACHE_V4WT
146 select CPU_CACHE_VIVT 153 select CPU_CACHE_VIVT
154 select CPU_CP15_MMU
147 select CPU_COPY_V4WB if MMU 155 select CPU_COPY_V4WB if MMU
148 select CPU_TLB_V4WBI if MMU 156 select CPU_TLB_V4WBI if MMU
149 help 157 help
@@ -161,6 +169,7 @@ config CPU_ARM1020E
161 select CPU_ABRT_EV4T 169 select CPU_ABRT_EV4T
162 select CPU_CACHE_V4WT 170 select CPU_CACHE_V4WT
163 select CPU_CACHE_VIVT 171 select CPU_CACHE_VIVT
172 select CPU_CP15_MMU
164 select CPU_COPY_V4WB if MMU 173 select CPU_COPY_V4WB if MMU
165 select CPU_TLB_V4WBI if MMU 174 select CPU_TLB_V4WBI if MMU
166 depends on n 175 depends on n
@@ -172,6 +181,7 @@ config CPU_ARM1022
172 select CPU_32v5 181 select CPU_32v5
173 select CPU_ABRT_EV4T 182 select CPU_ABRT_EV4T
174 select CPU_CACHE_VIVT 183 select CPU_CACHE_VIVT
184 select CPU_CP15_MMU
175 select CPU_COPY_V4WB if MMU # can probably do better 185 select CPU_COPY_V4WB if MMU # can probably do better
176 select CPU_TLB_V4WBI if MMU 186 select CPU_TLB_V4WBI if MMU
177 help 187 help
@@ -189,6 +199,7 @@ config CPU_ARM1026
189 select CPU_32v5 199 select CPU_32v5
190 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 200 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
191 select CPU_CACHE_VIVT 201 select CPU_CACHE_VIVT
202 select CPU_CP15_MMU
192 select CPU_COPY_V4WB if MMU # can probably do better 203 select CPU_COPY_V4WB if MMU # can probably do better
193 select CPU_TLB_V4WBI if MMU 204 select CPU_TLB_V4WBI if MMU
194 help 205 help
@@ -207,6 +218,7 @@ config CPU_SA110
207 select CPU_ABRT_EV4 218 select CPU_ABRT_EV4
208 select CPU_CACHE_V4WB 219 select CPU_CACHE_V4WB
209 select CPU_CACHE_VIVT 220 select CPU_CACHE_VIVT
221 select CPU_CP15_MMU
210 select CPU_COPY_V4WB if MMU 222 select CPU_COPY_V4WB if MMU
211 select CPU_TLB_V4WB if MMU 223 select CPU_TLB_V4WB if MMU
212 help 224 help
@@ -227,6 +239,7 @@ config CPU_SA1100
227 select CPU_ABRT_EV4 239 select CPU_ABRT_EV4
228 select CPU_CACHE_V4WB 240 select CPU_CACHE_V4WB
229 select CPU_CACHE_VIVT 241 select CPU_CACHE_VIVT
242 select CPU_CP15_MMU
230 select CPU_TLB_V4WB if MMU 243 select CPU_TLB_V4WB if MMU
231 244
232# XScale 245# XScale
@@ -237,6 +250,7 @@ config CPU_XSCALE
237 select CPU_32v5 250 select CPU_32v5
238 select CPU_ABRT_EV5T 251 select CPU_ABRT_EV5T
239 select CPU_CACHE_VIVT 252 select CPU_CACHE_VIVT
253 select CPU_CP15_MMU
240 select CPU_TLB_V4WBI if MMU 254 select CPU_TLB_V4WBI if MMU
241 255
242# XScale Core Version 3 256# XScale Core Version 3
@@ -247,6 +261,7 @@ config CPU_XSC3
247 select CPU_32v5 261 select CPU_32v5
248 select CPU_ABRT_EV5T 262 select CPU_ABRT_EV5T
249 select CPU_CACHE_VIVT 263 select CPU_CACHE_VIVT
264 select CPU_CP15_MMU
250 select CPU_TLB_V4WBI if MMU 265 select CPU_TLB_V4WBI if MMU
251 select IO_36 266 select IO_36
252 267
@@ -258,6 +273,7 @@ config CPU_V6
258 select CPU_ABRT_EV6 273 select CPU_ABRT_EV6
259 select CPU_CACHE_V6 274 select CPU_CACHE_V6
260 select CPU_CACHE_VIPT 275 select CPU_CACHE_VIPT
276 select CPU_CP15_MMU
261 select CPU_COPY_V6 if MMU 277 select CPU_COPY_V6 if MMU
262 select CPU_TLB_V6 if MMU 278 select CPU_TLB_V6 if MMU
263 279
@@ -380,6 +396,23 @@ config CPU_TLB_V6
380 396
381endif 397endif
382 398
399config CPU_CP15
400 bool
401 help
402 Processor has the CP15 register.
403
404config CPU_CP15_MMU
405 bool
406 select CPU_CP15
407 help
408 Processor has the CP15 register, which has MMU related registers.
409
410config CPU_CP15_MPU
411 bool
412 select CPU_CP15
413 help
414 Processor has the CP15 register, which has MPU related registers.
415
383# 416#
384# CPU supports 36-bit I/O 417# CPU supports 36-bit I/O
385# 418#