drm: Fix ordering of bit fields in EDID structure leading huge vsync values.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@linux.ie>

1 files changed, 2 insertions, 2 deletions

diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index c707c15f5164..ff8d27af4786 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -58,10 +58,10 @@ struct detailed_pixel_timing {
         u8 hsync_pulse_width_lo;
         u8 vsync_pulse_width_lo:4;
         u8 vsync_offset_lo:4;
-        u8 hsync_pulse_width_hi:2;
-        u8 hsync_offset_hi:2;
         u8 vsync_pulse_width_hi:2;
         u8 vsync_offset_hi:2;
+        u8 hsync_pulse_width_hi:2;
+        u8 hsync_offset_hi:2;
         u8 width_mm_lo;
         u8 height_mm_lo;
         u8 height_mm_hi:4;