diff options
| author | Sergei Shtylyov <sshtylyov@ru.mvista.com> | 2009-12-07 14:38:11 -0500 |
|---|---|---|
| committer | Jeff Garzik <jgarzik@redhat.com> | 2010-03-01 14:58:43 -0500 |
| commit | fd5e62e22db29a067d3f26ba54caac308eb5e3a8 (patch) | |
| tree | 5e2c85e6f923d3ad50cd72b8707afc66a6bcdb2c | |
| parent | 859faa875ed6760fcdfaf6f1fec1155a7e43dc21 (diff) | |
pata_hpt{37x|3x2n}: improve timing register documentation
Describe UDMA timing bits 18-20 and 21 separately; add a note to bit
31 about it being meaningful for PIO only. Reformat the whole comment,
while at it...
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
| -rw-r--r-- | drivers/ata/pata_hpt37x.c | 31 | ||||
| -rw-r--r-- | drivers/ata/pata_hpt3x2n.c | 31 |
2 files changed, 30 insertions, 32 deletions
diff --git a/drivers/ata/pata_hpt37x.c b/drivers/ata/pata_hpt37x.c index 9b191763e6e5..228dc1a8992f 100644 --- a/drivers/ata/pata_hpt37x.c +++ b/drivers/ata/pata_hpt37x.c | |||
| @@ -39,25 +39,24 @@ struct hpt_chip { | |||
| 39 | 39 | ||
| 40 | /* key for bus clock timings | 40 | /* key for bus clock timings |
| 41 | * bit | 41 | * bit |
| 42 | * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW | 42 | * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA. |
| 43 | * DMA. cycles = value + 1 | 43 | * cycles = value + 1 |
| 44 | * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW | 44 | * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA. |
| 45 | * DMA. cycles = value + 1 | 45 | * cycles = value + 1 |
| 46 | * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file | 46 | * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file |
| 47 | * register access. | 47 | * register access. |
| 48 | * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file | 48 | * 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file |
| 49 | * register access. | 49 | * register access. |
| 50 | * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer. | 50 | * 18:20 udma_cycle_time. Clock cycles for UDMA xfer. |
| 51 | * during task file register access. | 51 | * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock. |
| 52 | * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA | 52 | * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer. |
| 53 | * xfer. | 53 | * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file |
| 54 | * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task | ||
| 55 | * register access. | 54 | * register access. |
| 56 | * 28 UDMA enable | 55 | * 28 UDMA enable. |
| 57 | * 29 DMA enable | 56 | * 29 DMA enable. |
| 58 | * 30 PIO_MST enable. if set, the chip is in bus master mode during | 57 | * 30 PIO_MST enable. If set, the chip is in bus master mode during |
| 59 | * PIO. | 58 | * PIO xfer. |
| 60 | * 31 FIFO enable. | 59 | * 31 FIFO enable. Only for PIO. |
| 61 | */ | 60 | */ |
| 62 | 61 | ||
| 63 | static struct hpt_clock hpt37x_timings_33[] = { | 62 | static struct hpt_clock hpt37x_timings_33[] = { |
diff --git a/drivers/ata/pata_hpt3x2n.c b/drivers/ata/pata_hpt3x2n.c index b131c8f824d7..4a291221f277 100644 --- a/drivers/ata/pata_hpt3x2n.c +++ b/drivers/ata/pata_hpt3x2n.c | |||
| @@ -45,25 +45,24 @@ struct hpt_chip { | |||
| 45 | 45 | ||
| 46 | /* key for bus clock timings | 46 | /* key for bus clock timings |
| 47 | * bit | 47 | * bit |
| 48 | * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW | 48 | * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA. |
| 49 | * DMA. cycles = value + 1 | 49 | * cycles = value + 1 |
| 50 | * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW | 50 | * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA. |
| 51 | * DMA. cycles = value + 1 | 51 | * cycles = value + 1 |
| 52 | * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file | 52 | * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file |
| 53 | * register access. | 53 | * register access. |
| 54 | * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file | 54 | * 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file |
| 55 | * register access. | 55 | * register access. |
| 56 | * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer. | 56 | * 18:20 udma_cycle_time. Clock cycles for UDMA xfer. |
| 57 | * during task file register access. | 57 | * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock. |
| 58 | * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA | 58 | * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer. |
| 59 | * xfer. | 59 | * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file |
| 60 | * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task | ||
| 61 | * register access. | 60 | * register access. |
| 62 | * 28 UDMA enable | 61 | * 28 UDMA enable. |
| 63 | * 29 DMA enable | 62 | * 29 DMA enable. |
| 64 | * 30 PIO_MST enable. if set, the chip is in bus master mode during | 63 | * 30 PIO_MST enable. If set, the chip is in bus master mode during |
| 65 | * PIO. | 64 | * PIO xfer. |
| 66 | * 31 FIFO enable. | 65 | * 31 FIFO enable. Only for PIO. |
| 67 | */ | 66 | */ |
| 68 | 67 | ||
| 69 | /* 66MHz DPLL clocks */ | 68 | /* 66MHz DPLL clocks */ |