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authorKenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>2005-11-23 21:39:29 -0500
committerGreg Kroah-Hartman <gregkh@suse.de>2006-01-09 15:13:17 -0500
commitf467f6187fc60c954a9509b3a3e17ef89a4f6f22 (patch)
tree0ca31955b2de33ec04d22336d0648c2150160e7e
parent0455986cce45d28511f59a29d6cecc17d6b65720 (diff)
[PATCH] shpchp: fix improper write to Command Completion Detect bit
Current SHPCHP driver writes a '0' to the Command Completion Detect bit to clear the Command Complete Interrupt Pending. But according to the SHPC spec (See 4.7.3.1 System Interrupts), SHPCHP driver must write '1'. This patch fixes this bug. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
-rw-r--r--drivers/pci/hotplug/shpchp_hpc.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/pci/hotplug/shpchp_hpc.c b/drivers/pci/hotplug/shpchp_hpc.c
index d82987f075b2..f25e11645071 100644
--- a/drivers/pci/hotplug/shpchp_hpc.c
+++ b/drivers/pci/hotplug/shpchp_hpc.c
@@ -1058,11 +1058,11 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
1058 if (intr_loc & 0x0001) { 1058 if (intr_loc & 0x0001) {
1059 /* 1059 /*
1060 * Command Complete Interrupt Pending 1060 * Command Complete Interrupt Pending
1061 * RO only - clear by writing 0 to the Command Completion 1061 * RO only - clear by writing 1 to the Command Completion
1062 * Detect bit in Controller SERR-INT register 1062 * Detect bit in Controller SERR-INT register
1063 */ 1063 */
1064 temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE); 1064 temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1065 temp_dword &= 0xfffeffff; 1065 temp_dword &= 0xfffdffff;
1066 writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE); 1066 writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);
1067 wake_up_interruptible(&ctrl->queue); 1067 wake_up_interruptible(&ctrl->queue);
1068 } 1068 }