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authorAdrian Bunk <bunk@stusta.de>2005-06-25 17:59:05 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-06-25 19:25:04 -0400
commitf15313bf42337ade55376303932d8b6a62e6be43 (patch)
treebeed808083b83c2d51972ae24a877377a86ed842
parent681ea4b930768444e9d88651c1362b0bf6d2a42b (diff)
[PATCH] drivers/char/rocket.c: cleanups
This patch contains the following cleanups: - make needlessly global code static - remove the TRUE/FALSE macros Signed-off-by: Adrian Bunk <bunk@stusta.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
-rw-r--r--drivers/char/rocket.c226
-rw-r--r--drivers/char/rocket_int.h40
2 files changed, 119 insertions, 147 deletions
diff --git a/drivers/char/rocket.c b/drivers/char/rocket.c
index 5bcbeb0cb9ae..f463d6baa685 100644
--- a/drivers/char/rocket.c
+++ b/drivers/char/rocket.c
@@ -161,6 +161,64 @@ static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
161 UPCI_AIOP_INTR_BIT_3 161 UPCI_AIOP_INTR_BIT_3
162}; 162};
163 163
164static Byte_t RData[RDATASIZE] = {
165 0x00, 0x09, 0xf6, 0x82,
166 0x02, 0x09, 0x86, 0xfb,
167 0x04, 0x09, 0x00, 0x0a,
168 0x06, 0x09, 0x01, 0x0a,
169 0x08, 0x09, 0x8a, 0x13,
170 0x0a, 0x09, 0xc5, 0x11,
171 0x0c, 0x09, 0x86, 0x85,
172 0x0e, 0x09, 0x20, 0x0a,
173 0x10, 0x09, 0x21, 0x0a,
174 0x12, 0x09, 0x41, 0xff,
175 0x14, 0x09, 0x82, 0x00,
176 0x16, 0x09, 0x82, 0x7b,
177 0x18, 0x09, 0x8a, 0x7d,
178 0x1a, 0x09, 0x88, 0x81,
179 0x1c, 0x09, 0x86, 0x7a,
180 0x1e, 0x09, 0x84, 0x81,
181 0x20, 0x09, 0x82, 0x7c,
182 0x22, 0x09, 0x0a, 0x0a
183};
184
185static Byte_t RRegData[RREGDATASIZE] = {
186 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
187 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
188 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
189 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
190 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
191 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
192 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
193 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
194 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
195 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
196 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
197 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
198 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
199};
200
201static CONTROLLER_T sController[CTL_SIZE] = {
202 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
203 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
204 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
205 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
206 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
207 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
208 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
209 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
210};
211
212static Byte_t sBitMapClrTbl[8] = {
213 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
214};
215
216static Byte_t sBitMapSetTbl[8] = {
217 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
218};
219
220static int sClockPrescale = 0x14;
221
164/* 222/*
165 * Line number is the ttySIx number (x), the Minor number. We 223 * Line number is the ttySIx number (x), the Minor number. We
166 * assign them sequentially, starting at zero. The following 224 * assign them sequentially, starting at zero. The following
@@ -177,6 +235,26 @@ static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model);
177static unsigned char GetLineNumber(int ctrl, int aiop, int ch); 235static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
178static unsigned char SetLineNumber(int ctrl, int aiop, int ch); 236static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
179static void rp_start(struct tty_struct *tty); 237static void rp_start(struct tty_struct *tty);
238static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
239 int ChanNum);
240static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
241static void sFlushRxFIFO(CHANNEL_T * ChP);
242static void sFlushTxFIFO(CHANNEL_T * ChP);
243static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
244static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
245static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
246static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
247static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
248static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
249 ByteIO_t * AiopIOList, int AiopIOListSize,
250 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
251 int PeriodicOnly, int altChanRingIndicator,
252 int UPCIRingInd);
253static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
254 ByteIO_t * AiopIOList, int AiopIOListSize,
255 int IRQNum, Byte_t Frequency, int PeriodicOnly);
256static int sReadAiopID(ByteIO_t io);
257static int sReadAiopNumChan(WordIO_t io);
180 258
181#ifdef MODULE 259#ifdef MODULE
182MODULE_AUTHOR("Theodore Ts'o"); 260MODULE_AUTHOR("Theodore Ts'o");
@@ -1798,7 +1876,7 @@ static void rp_flush_buffer(struct tty_struct *tty)
1798 * init's aiopic and serial port hardware. 1876 * init's aiopic and serial port hardware.
1799 * Inputs: i is the board number (0-n) 1877 * Inputs: i is the board number (0-n)
1800 */ 1878 */
1801__init int register_PCI(int i, struct pci_dev *dev) 1879static __init int register_PCI(int i, struct pci_dev *dev)
1802{ 1880{
1803 int num_aiops, aiop, max_num_aiops, num_chan, chan; 1881 int num_aiops, aiop, max_num_aiops, num_chan, chan;
1804 unsigned int aiopio[MAX_AIOPS_PER_BOARD]; 1882 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
@@ -2453,72 +2531,6 @@ static void rp_cleanup_module(void)
2453} 2531}
2454#endif 2532#endif
2455 2533
2456#ifndef TRUE
2457#define TRUE 1
2458#endif
2459
2460#ifndef FALSE
2461#define FALSE 0
2462#endif
2463
2464static Byte_t RData[RDATASIZE] = {
2465 0x00, 0x09, 0xf6, 0x82,
2466 0x02, 0x09, 0x86, 0xfb,
2467 0x04, 0x09, 0x00, 0x0a,
2468 0x06, 0x09, 0x01, 0x0a,
2469 0x08, 0x09, 0x8a, 0x13,
2470 0x0a, 0x09, 0xc5, 0x11,
2471 0x0c, 0x09, 0x86, 0x85,
2472 0x0e, 0x09, 0x20, 0x0a,
2473 0x10, 0x09, 0x21, 0x0a,
2474 0x12, 0x09, 0x41, 0xff,
2475 0x14, 0x09, 0x82, 0x00,
2476 0x16, 0x09, 0x82, 0x7b,
2477 0x18, 0x09, 0x8a, 0x7d,
2478 0x1a, 0x09, 0x88, 0x81,
2479 0x1c, 0x09, 0x86, 0x7a,
2480 0x1e, 0x09, 0x84, 0x81,
2481 0x20, 0x09, 0x82, 0x7c,
2482 0x22, 0x09, 0x0a, 0x0a
2483};
2484
2485static Byte_t RRegData[RREGDATASIZE] = {
2486 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
2487 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
2488 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
2489 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
2490 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
2491 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
2492 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
2493 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
2494 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
2495 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
2496 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
2497 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
2498 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
2499};
2500
2501CONTROLLER_T sController[CTL_SIZE] = {
2502 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
2503 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
2504 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
2505 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
2506 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
2507 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
2508 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
2509 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
2510};
2511
2512Byte_t sBitMapClrTbl[8] = {
2513 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
2514};
2515
2516Byte_t sBitMapSetTbl[8] = {
2517 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
2518};
2519
2520int sClockPrescale = 0x14;
2521
2522/*************************************************************************** 2534/***************************************************************************
2523Function: sInitController 2535Function: sInitController
2524Purpose: Initialization of controller global registers and controller 2536Purpose: Initialization of controller global registers and controller
@@ -2554,22 +2566,22 @@ Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2554 FREQ_4HZ - 4 Hertz 2566 FREQ_4HZ - 4 Hertz
2555 If IRQNum is set to 0 the Frequency parameter is 2567 If IRQNum is set to 0 the Frequency parameter is
2556 overidden, it is forced to a value of FREQ_DIS. 2568 overidden, it is forced to a value of FREQ_DIS.
2557 int PeriodicOnly: TRUE if all interrupts except the periodic 2569 int PeriodicOnly: 1 if all interrupts except the periodic
2558 interrupt are to be blocked. 2570 interrupt are to be blocked.
2559 FALSE is both the periodic interrupt and 2571 0 is both the periodic interrupt and
2560 other channel interrupts are allowed. 2572 other channel interrupts are allowed.
2561 If IRQNum is set to 0 the PeriodicOnly parameter is 2573 If IRQNum is set to 0 the PeriodicOnly parameter is
2562 overidden, it is forced to a value of FALSE. 2574 overidden, it is forced to a value of 0.
2563Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller 2575Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2564 initialization failed. 2576 initialization failed.
2565 2577
2566Comments: 2578Comments:
2567 If periodic interrupts are to be disabled but AIOP interrupts 2579 If periodic interrupts are to be disabled but AIOP interrupts
2568 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to FALSE. 2580 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2569 2581
2570 If interrupts are to be completely disabled set IRQNum to 0. 2582 If interrupts are to be completely disabled set IRQNum to 0.
2571 2583
2572 Setting Frequency to FREQ_DIS and PeriodicOnly to TRUE is an 2584 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2573 invalid combination. 2585 invalid combination.
2574 2586
2575 This function performs initialization of global interrupt modes, 2587 This function performs initialization of global interrupt modes,
@@ -2589,9 +2601,9 @@ Warnings: No range checking on any of the parameters is done.
2589 After this function all AIOPs on the controller are disabled, 2601 After this function all AIOPs on the controller are disabled,
2590 they can be enabled with sEnAiop(). 2602 they can be enabled with sEnAiop().
2591*/ 2603*/
2592int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO, 2604static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2593 ByteIO_t * AiopIOList, int AiopIOListSize, int IRQNum, 2605 ByteIO_t * AiopIOList, int AiopIOListSize,
2594 Byte_t Frequency, int PeriodicOnly) 2606 int IRQNum, Byte_t Frequency, int PeriodicOnly)
2595{ 2607{
2596 int i; 2608 int i;
2597 ByteIO_t io; 2609 ByteIO_t io;
@@ -2687,22 +2699,22 @@ Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
2687 FREQ_4HZ - 4 Hertz 2699 FREQ_4HZ - 4 Hertz
2688 If IRQNum is set to 0 the Frequency parameter is 2700 If IRQNum is set to 0 the Frequency parameter is
2689 overidden, it is forced to a value of FREQ_DIS. 2701 overidden, it is forced to a value of FREQ_DIS.
2690 int PeriodicOnly: TRUE if all interrupts except the periodic 2702 int PeriodicOnly: 1 if all interrupts except the periodic
2691 interrupt are to be blocked. 2703 interrupt are to be blocked.
2692 FALSE is both the periodic interrupt and 2704 0 is both the periodic interrupt and
2693 other channel interrupts are allowed. 2705 other channel interrupts are allowed.
2694 If IRQNum is set to 0 the PeriodicOnly parameter is 2706 If IRQNum is set to 0 the PeriodicOnly parameter is
2695 overidden, it is forced to a value of FALSE. 2707 overidden, it is forced to a value of 0.
2696Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller 2708Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2697 initialization failed. 2709 initialization failed.
2698 2710
2699Comments: 2711Comments:
2700 If periodic interrupts are to be disabled but AIOP interrupts 2712 If periodic interrupts are to be disabled but AIOP interrupts
2701 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to FALSE. 2713 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2702 2714
2703 If interrupts are to be completely disabled set IRQNum to 0. 2715 If interrupts are to be completely disabled set IRQNum to 0.
2704 2716
2705 Setting Frequency to FREQ_DIS and PeriodicOnly to TRUE is an 2717 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2706 invalid combination. 2718 invalid combination.
2707 2719
2708 This function performs initialization of global interrupt modes, 2720 This function performs initialization of global interrupt modes,
@@ -2722,11 +2734,11 @@ Warnings: No range checking on any of the parameters is done.
2722 After this function all AIOPs on the controller are disabled, 2734 After this function all AIOPs on the controller are disabled,
2723 they can be enabled with sEnAiop(). 2735 they can be enabled with sEnAiop().
2724*/ 2736*/
2725int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum, 2737static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
2726 ByteIO_t * AiopIOList, int AiopIOListSize, 2738 ByteIO_t * AiopIOList, int AiopIOListSize,
2727 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency, 2739 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
2728 int PeriodicOnly, int altChanRingIndicator, 2740 int PeriodicOnly, int altChanRingIndicator,
2729 int UPCIRingInd) 2741 int UPCIRingInd)
2730{ 2742{
2731 int i; 2743 int i;
2732 ByteIO_t io; 2744 ByteIO_t io;
@@ -2784,7 +2796,7 @@ Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2784Warnings: No context switches are allowed while executing this function. 2796Warnings: No context switches are allowed while executing this function.
2785 2797
2786*/ 2798*/
2787int sReadAiopID(ByteIO_t io) 2799static int sReadAiopID(ByteIO_t io)
2788{ 2800{
2789 Byte_t AiopID; /* ID byte from AIOP */ 2801 Byte_t AiopID; /* ID byte from AIOP */
2790 2802
@@ -2810,7 +2822,7 @@ Comments: The number of channels is determined by write/reads from identical
2810 AIOP, otherwise it is an 8 channel. 2822 AIOP, otherwise it is an 8 channel.
2811Warnings: No context switches are allowed while executing this function. 2823Warnings: No context switches are allowed while executing this function.
2812*/ 2824*/
2813int sReadAiopNumChan(WordIO_t io) 2825static int sReadAiopNumChan(WordIO_t io)
2814{ 2826{
2815 Word_t x; 2827 Word_t x;
2816 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 }; 2828 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
@@ -2834,15 +2846,15 @@ Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
2834 CHANNEL_T *ChP; Ptr to channel structure 2846 CHANNEL_T *ChP; Ptr to channel structure
2835 int AiopNum; AIOP number within controller 2847 int AiopNum; AIOP number within controller
2836 int ChanNum; Channel number within AIOP 2848 int ChanNum; Channel number within AIOP
2837Return: int: TRUE if initialization succeeded, FALSE if it fails because channel 2849Return: int: 1 if initialization succeeded, 0 if it fails because channel
2838 number exceeds number of channels available in AIOP. 2850 number exceeds number of channels available in AIOP.
2839Comments: This function must be called before a channel can be used. 2851Comments: This function must be called before a channel can be used.
2840Warnings: No range checking on any of the parameters is done. 2852Warnings: No range checking on any of the parameters is done.
2841 2853
2842 No context switches are allowed while executing this function. 2854 No context switches are allowed while executing this function.
2843*/ 2855*/
2844int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum, 2856static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2845 int ChanNum) 2857 int ChanNum)
2846{ 2858{
2847 int i; 2859 int i;
2848 WordIO_t AiopIO; 2860 WordIO_t AiopIO;
@@ -2853,7 +2865,7 @@ int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2853 int brd9600; 2865 int brd9600;
2854 2866
2855 if (ChanNum >= CtlP->AiopNumChan[AiopNum]) 2867 if (ChanNum >= CtlP->AiopNumChan[AiopNum])
2856 return (FALSE); /* exceeds num chans in AIOP */ 2868 return 0; /* exceeds num chans in AIOP */
2857 2869
2858 /* Channel, AIOP, and controller identifiers */ 2870 /* Channel, AIOP, and controller identifiers */
2859 ChP->CtlP = CtlP; 2871 ChP->CtlP = CtlP;
@@ -2968,7 +2980,7 @@ int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2968 ChP->TxPrioBuf = ChOff + _TXP_BUF; 2980 ChP->TxPrioBuf = ChOff + _TXP_BUF;
2969 sEnRxProcessor(ChP); /* start the Rx processor */ 2981 sEnRxProcessor(ChP); /* start the Rx processor */
2970 2982
2971 return (TRUE); 2983 return 1;
2972} 2984}
2973 2985
2974/*************************************************************************** 2986/***************************************************************************
@@ -2989,7 +3001,7 @@ Warnings: No context switches are allowed while executing this function.
2989 After calling this function a delay of 4 uS is required to ensure 3001 After calling this function a delay of 4 uS is required to ensure
2990 that the receive processor is no longer processing this channel. 3002 that the receive processor is no longer processing this channel.
2991*/ 3003*/
2992void sStopRxProcessor(CHANNEL_T * ChP) 3004static void sStopRxProcessor(CHANNEL_T * ChP)
2993{ 3005{
2994 Byte_t R[4]; 3006 Byte_t R[4];
2995 3007
@@ -3014,18 +3026,18 @@ Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
3014 this function. 3026 this function.
3015Warnings: No context switches are allowed while executing this function. 3027Warnings: No context switches are allowed while executing this function.
3016*/ 3028*/
3017void sFlushRxFIFO(CHANNEL_T * ChP) 3029static void sFlushRxFIFO(CHANNEL_T * ChP)
3018{ 3030{
3019 int i; 3031 int i;
3020 Byte_t Ch; /* channel number within AIOP */ 3032 Byte_t Ch; /* channel number within AIOP */
3021 int RxFIFOEnabled; /* TRUE if Rx FIFO enabled */ 3033 int RxFIFOEnabled; /* 1 if Rx FIFO enabled */
3022 3034
3023 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */ 3035 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
3024 return; /* don't need to flush */ 3036 return; /* don't need to flush */
3025 3037
3026 RxFIFOEnabled = FALSE; 3038 RxFIFOEnabled = 0;
3027 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */ 3039 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
3028 RxFIFOEnabled = TRUE; 3040 RxFIFOEnabled = 1;
3029 sDisRxFIFO(ChP); /* disable it */ 3041 sDisRxFIFO(ChP); /* disable it */
3030 for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */ 3042 for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
3031 sInB(ChP->IntChan); /* depends on bus i/o timing */ 3043 sInB(ChP->IntChan); /* depends on bus i/o timing */
@@ -3056,18 +3068,18 @@ Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
3056 this function. 3068 this function.
3057Warnings: No context switches are allowed while executing this function. 3069Warnings: No context switches are allowed while executing this function.
3058*/ 3070*/
3059void sFlushTxFIFO(CHANNEL_T * ChP) 3071static void sFlushTxFIFO(CHANNEL_T * ChP)
3060{ 3072{
3061 int i; 3073 int i;
3062 Byte_t Ch; /* channel number within AIOP */ 3074 Byte_t Ch; /* channel number within AIOP */
3063 int TxEnabled; /* TRUE if transmitter enabled */ 3075 int TxEnabled; /* 1 if transmitter enabled */
3064 3076
3065 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */ 3077 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
3066 return; /* don't need to flush */ 3078 return; /* don't need to flush */
3067 3079
3068 TxEnabled = FALSE; 3080 TxEnabled = 0;
3069 if (ChP->TxControl[3] & TX_ENABLE) { 3081 if (ChP->TxControl[3] & TX_ENABLE) {
3070 TxEnabled = TRUE; 3082 TxEnabled = 1;
3071 sDisTransmit(ChP); /* disable transmitter */ 3083 sDisTransmit(ChP); /* disable transmitter */
3072 } 3084 }
3073 sStopRxProcessor(ChP); /* stop Rx processor */ 3085 sStopRxProcessor(ChP); /* stop Rx processor */
@@ -3096,7 +3108,7 @@ Comments: The priority byte is transmitted before any data in the Tx FIFO.
3096 3108
3097Warnings: No context switches are allowed while executing this function. 3109Warnings: No context switches are allowed while executing this function.
3098*/ 3110*/
3099int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data) 3111static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
3100{ 3112{
3101 Byte_t DWBuf[4]; /* buffer for double word writes */ 3113 Byte_t DWBuf[4]; /* buffer for double word writes */
3102 Word_t *WordPtr; /* must be far because Win SS != DS */ 3114 Word_t *WordPtr; /* must be far because Win SS != DS */
@@ -3158,7 +3170,7 @@ Comments: If an interrupt enable flag is set in Flags, that interrupt will be
3158 enable channel interrupts. This would allow the global interrupt 3170 enable channel interrupts. This would allow the global interrupt
3159 status register to be used to determine which AIOPs need service. 3171 status register to be used to determine which AIOPs need service.
3160*/ 3172*/
3161void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags) 3173static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
3162{ 3174{
3163 Byte_t Mask; /* Interrupt Mask Register */ 3175 Byte_t Mask; /* Interrupt Mask Register */
3164 3176
@@ -3202,7 +3214,7 @@ Comments: If an interrupt flag is set in Flags, that interrupt will be
3202 this channel's bit from being set in the AIOP's Interrupt Channel 3214 this channel's bit from being set in the AIOP's Interrupt Channel
3203 Register. 3215 Register.
3204*/ 3216*/
3205void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags) 3217static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3206{ 3218{
3207 Byte_t Mask; /* Interrupt Mask Register */ 3219 Byte_t Mask; /* Interrupt Mask Register */
3208 3220
@@ -3218,7 +3230,7 @@ void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3218 } 3230 }
3219} 3231}
3220 3232
3221void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode) 3233static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3222{ 3234{
3223 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum); 3235 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3224} 3236}
@@ -3227,7 +3239,7 @@ void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3227 * Not an official SSCI function, but how to reset RocketModems. 3239 * Not an official SSCI function, but how to reset RocketModems.
3228 * ISA bus version 3240 * ISA bus version
3229 */ 3241 */
3230void sModemReset(CONTROLLER_T * CtlP, int chan, int on) 3242static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
3231{ 3243{
3232 ByteIO_t addr; 3244 ByteIO_t addr;
3233 Byte_t val; 3245 Byte_t val;
@@ -3252,7 +3264,7 @@ void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
3252 * Not an official SSCI function, but how to reset RocketModems. 3264 * Not an official SSCI function, but how to reset RocketModems.
3253 * PCI bus version 3265 * PCI bus version
3254 */ 3266 */
3255void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on) 3267static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
3256{ 3268{
3257 ByteIO_t addr; 3269 ByteIO_t addr;
3258 3270
diff --git a/drivers/char/rocket_int.h b/drivers/char/rocket_int.h
index 802687290ee1..3a8bcc85bc14 100644
--- a/drivers/char/rocket_int.h
+++ b/drivers/char/rocket_int.h
@@ -1130,46 +1130,6 @@ Warnings: This function writes the data byte without checking to see if
1130*/ 1130*/
1131#define sWriteTxByte(IO,DATA) sOutB(IO,DATA) 1131#define sWriteTxByte(IO,DATA) sOutB(IO,DATA)
1132 1132
1133int sInitController(CONTROLLER_T * CtlP,
1134 int CtlNum,
1135 ByteIO_t MudbacIO,
1136 ByteIO_t * AiopIOList,
1137 int AiopIOListSize,
1138 int IRQNum, Byte_t Frequency, int PeriodicOnly);
1139
1140int sPCIInitController(CONTROLLER_T * CtlP,
1141 int CtlNum,
1142 ByteIO_t * AiopIOList,
1143 int AiopIOListSize,
1144 WordIO_t ConfigIO,
1145 int IRQNum,
1146 Byte_t Frequency,
1147 int PeriodicOnly,
1148 int altChanRingIndicator, int UPCIRingInd);
1149
1150int sReadAiopID(ByteIO_t io);
1151int sReadAiopNumChan(WordIO_t io);
1152int sInitChan(CONTROLLER_T * CtlP,
1153 CHANNEL_T * ChP, int AiopNum, int ChanNum);
1154Byte_t sGetRxErrStatus(CHANNEL_T * ChP);
1155void sStopRxProcessor(CHANNEL_T * ChP);
1156void sStopSWInFlowCtl(CHANNEL_T * ChP);
1157void sFlushRxFIFO(CHANNEL_T * ChP);
1158void sFlushTxFIFO(CHANNEL_T * ChP);
1159int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
1160void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
1161void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
1162void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
1163void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
1164void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
1165
1166extern Byte_t R[RDATASIZE];
1167extern CONTROLLER_T sController[CTL_SIZE];
1168extern Byte_t sIRQMap[16];
1169extern Byte_t sBitMapClrTbl[8];
1170extern Byte_t sBitMapSetTbl[8];
1171extern int sClockPrescale;
1172
1173/* 1133/*
1174 * Begin Linux specific definitions for the Rocketport driver 1134 * Begin Linux specific definitions for the Rocketport driver
1175 * 1135 *