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authorDavid Brownell <david-b@pacbell.net>2008-02-14 14:24:02 -0500
committerHaavard Skinnemoen <haavard.skinnemoen@atmel.com>2008-04-19 20:40:08 -0400
commite723ff666a5da8f7fda4e36ebfeafac2175a5c6e (patch)
tree53d2b1a0190795977ddccbda2085598d7ea14e43
parent7e59128f31e0c57d52e86d57730d4c9281494dda (diff)
avr32: Generic clockevents support
This combines three patches from David Brownell: * avr32: tclib support * avr32: simplify clocksources * avr32: Turn count/compare into a oneshot clockevent device Register both TC blocks (instead of just the first one) so that the AT32/AT91 tclib code will pick them up (instead of just the avr32-only PIT-style clocksource). Rename the first one and its resources appropriately. More cleanups to the cycle counter clocksource code - Disable all the weak symbol magic; remove the AVR32-only TCB-based clocksource code (source and header). - Mark the __init code properly. - Don't forget to report IRQF_TIMER. - Make the system work properly with this clocksource, by preventing use of the CPU "idle" sleep state in the idle loop when it's used. Package the avr32 count/compare timekeeping support as a oneshot clockevent device, so it supports NO_HZ and high res timers. This means it also supports plugging in other clockevent devices and clocksources. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Diffstat
-rw-r--r--arch/avr32/Kconfig5
-rw-r--r--arch/avr32/kernel/time.c209
-rw-r--r--arch/avr32/mach-at32ap/Makefile1
-rw-r--r--arch/avr32/mach-at32ap/at32ap700x.c33
-rw-r--r--arch/avr32/mach-at32ap/time-tc.c218
-rw-r--r--include/asm-avr32/arch-at32ap/time.h112
6 files changed, 109 insertions, 469 deletions
diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig
index 28e0caf4156c..09ad7995080c 100644
--- a/arch/avr32/Kconfig
+++ b/arch/avr32/Kconfig
@@ -47,6 +47,9 @@ config RWSEM_GENERIC_SPINLOCK
47config GENERIC_TIME 47config GENERIC_TIME
48 def_bool y 48 def_bool y
49 49
50config GENERIC_CLOCKEVENTS
51 def_bool y
52
50config RWSEM_XCHGADD_ALGORITHM 53config RWSEM_XCHGADD_ALGORITHM
51 def_bool n 54 def_bool n
52 55
@@ -70,6 +73,8 @@ source "init/Kconfig"
70 73
71menu "System Type and features" 74menu "System Type and features"
72 75
76source "kernel/time/Kconfig"
77
73config SUBARCH_AVR32B 78config SUBARCH_AVR32B
74 bool 79 bool
75config MMU 80config MMU
diff --git a/arch/avr32/kernel/time.c b/arch/avr32/kernel/time.c
index bf2f762e6a47..00a9862380ff 100644
--- a/arch/avr32/kernel/time.c
+++ b/arch/avr32/kernel/time.c
@@ -1,16 +1,12 @@
1/* 1/*
2 * Copyright (C) 2004-2007 Atmel Corporation 2 * Copyright (C) 2004-2007 Atmel Corporation
3 * 3 *
4 * Based on MIPS implementation arch/mips/kernel/time.c
5 * Copyright 2001 MontaVista Software Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
10 */ 7 */
11
12#include <linux/clk.h> 8#include <linux/clk.h>
13#include <linux/clocksource.h> 9#include <linux/clockchips.h>
14#include <linux/time.h> 10#include <linux/time.h>
15#include <linux/module.h> 11#include <linux/module.h>
16#include <linux/interrupt.h> 12#include <linux/interrupt.h>
@@ -27,13 +23,10 @@
27#include <asm/io.h> 23#include <asm/io.h>
28#include <asm/sections.h> 24#include <asm/sections.h>
29 25
30/* how many counter cycles in a jiffy? */ 26#include <asm/arch/pm.h>
31static u32 cycles_per_jiffy;
32 27
33/* the count value for the next timer interrupt */
34static u32 expirelo;
35 28
36cycle_t __weak read_cycle_count(void) 29static cycle_t read_cycle_count(void)
37{ 30{
38 return (cycle_t)sysreg_read(COUNT); 31 return (cycle_t)sysreg_read(COUNT);
39} 32}
@@ -42,10 +35,11 @@ cycle_t __weak read_cycle_count(void)
42 * The architectural cycle count registers are a fine clocksource unless 35 * The architectural cycle count registers are a fine clocksource unless
43 * the system idle loop use sleep states like "idle": the CPU cycles 36 * the system idle loop use sleep states like "idle": the CPU cycles
44 * measured by COUNT (and COMPARE) don't happen during sleep states. 37 * measured by COUNT (and COMPARE) don't happen during sleep states.
38 * Their duration also changes if cpufreq changes the CPU clock rate.
45 * So we rate the clocksource using COUNT as very low quality. 39 * So we rate the clocksource using COUNT as very low quality.
46 */ 40 */
47struct clocksource __weak clocksource_avr32 = { 41static struct clocksource counter = {
48 .name = "avr32", 42 .name = "avr32_counter",
49 .rating = 50, 43 .rating = 50,
50 .read = read_cycle_count, 44 .read = read_cycle_count,
51 .mask = CLOCKSOURCE_MASK(32), 45 .mask = CLOCKSOURCE_MASK(32),
@@ -53,152 +47,109 @@ struct clocksource __weak clocksource_avr32 = {
53 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 47 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
54}; 48};
55 49
56irqreturn_t __weak timer_interrupt(int irq, void *dev_id); 50static irqreturn_t timer_interrupt(int irq, void *dev_id)
57
58struct irqaction timer_irqaction = {
59 .handler = timer_interrupt,
60 .flags = IRQF_DISABLED,
61 .name = "timer",
62};
63
64static void avr32_timer_ack(void)
65{
66 u32 count;
67
68 /* Ack this timer interrupt and set the next one */
69 expirelo += cycles_per_jiffy;
70 /* setting COMPARE to 0 stops the COUNT-COMPARE */
71 if (expirelo == 0) {
72 sysreg_write(COMPARE, expirelo + 1);
73 } else {
74 sysreg_write(COMPARE, expirelo);
75 }
76
77 /* Check to see if we have missed any timer interrupts */
78 count = sysreg_read(COUNT);
79 if ((count - expirelo) < 0x7fffffff) {
80 expirelo = count + cycles_per_jiffy;
81 sysreg_write(COMPARE, expirelo);
82 }
83}
84
85int __weak avr32_hpt_init(void)
86{ 51{
87 int ret; 52 struct clock_event_device *evdev = dev_id;
88 unsigned long mult, shift, count_hz;
89
90 count_hz = clk_get_rate(boot_cpu_data.clk);
91 shift = clocksource_avr32.shift;
92 mult = clocksource_hz2mult(count_hz, shift);
93 clocksource_avr32.mult = mult;
94 53
95 { 54 /*
96 u64 tmp; 55 * Disable the interrupt until the clockevent subsystem
56 * reprograms it.
57 */
58 sysreg_write(COMPARE, 0);
97 59
98 tmp = TICK_NSEC; 60 evdev->event_handler(evdev);
99 tmp <<= shift; 61 return IRQ_HANDLED;
100 tmp += mult / 2; 62}
101 do_div(tmp, mult);
102 63
103 cycles_per_jiffy = tmp; 64static struct irqaction timer_irqaction = {
104 } 65 .handler = timer_interrupt,
66 .flags = IRQF_TIMER | IRQF_DISABLED,
67 .name = "avr32_comparator",
68};
105 69
106 ret = setup_irq(0, &timer_irqaction); 70static int comparator_next_event(unsigned long delta,
107 if (ret) { 71 struct clock_event_device *evdev)
108 pr_debug("timer: could not request IRQ 0: %d\n", ret); 72{
109 return -ENODEV; 73 unsigned long flags;
110 }
111 74
112 printk(KERN_INFO "timer: AT32AP COUNT-COMPARE at irq 0, " 75 raw_local_irq_save(flags);
113 "%lu.%03lu MHz\n",
114 ((count_hz + 500) / 1000) / 1000,
115 ((count_hz + 500) / 1000) % 1000);
116 76
117 return 0; 77 /* The time to read COUNT then update COMPARE must be less
118} 78 * than the min_delta_ns value for this clockevent source.
79 */
80 sysreg_write(COMPARE, (sysreg_read(COUNT) + delta) ? : 1);
119 81
120/* 82 raw_local_irq_restore(flags);
121 * Taken from MIPS c0_hpt_timer_init().
122 *
123 * The reason COUNT is written twice is probably to make sure we don't get any
124 * timer interrupts while we are messing with the counter.
125 */
126int __weak avr32_hpt_start(void)
127{
128 u32 count = sysreg_read(COUNT);
129 expirelo = (count / cycles_per_jiffy + 1) * cycles_per_jiffy;
130 sysreg_write(COUNT, expirelo - cycles_per_jiffy);
131 sysreg_write(COMPARE, expirelo);
132 sysreg_write(COUNT, count);
133 83
134 return 0; 84 return 0;
135} 85}
136 86
137/* 87static void comparator_mode(enum clock_event_mode mode,
138 * local_timer_interrupt() does profiling and process accounting on a 88 struct clock_event_device *evdev)
139 * per-CPU basis.
140 *
141 * In UP mode, it is invoked from the (global) timer_interrupt.
142 */
143void local_timer_interrupt(int irq, void *dev_id)
144{ 89{
145 if (current->pid) 90 switch (mode) {
146 profile_tick(CPU_PROFILING); 91 case CLOCK_EVT_MODE_ONESHOT:
147 update_process_times(user_mode(get_irq_regs())); 92 pr_debug("%s: start\n", evdev->name);
93 /* FALLTHROUGH */
94 case CLOCK_EVT_MODE_RESUME:
95 cpu_disable_idle_sleep();
96 break;
97 case CLOCK_EVT_MODE_UNUSED:
98 case CLOCK_EVT_MODE_SHUTDOWN:
99 sysreg_write(COMPARE, 0);
100 pr_debug("%s: stop\n", evdev->name);
101 cpu_enable_idle_sleep();
102 break;
103 default:
104 BUG();
105 }
148} 106}
149 107
150irqreturn_t __weak timer_interrupt(int irq, void *dev_id) 108static struct clock_event_device comparator = {
151{ 109 .name = "avr32_comparator",
152 /* ack timer interrupt and try to set next interrupt */ 110 .features = CLOCK_EVT_FEAT_ONESHOT,
153 avr32_timer_ack(); 111 .shift = 16,
154 112 .rating = 50,
155 /* 113 .cpumask = CPU_MASK_CPU0,
156 * Call the generic timer interrupt handler 114 .set_next_event = comparator_next_event,
157 */ 115 .set_mode = comparator_mode,
158 write_seqlock(&xtime_lock); 116};
159 do_timer(1);
160 write_sequnlock(&xtime_lock);
161
162 /*
163 * In UP mode, we call local_timer_interrupt() to do profiling
164 * and process accounting.
165 *
166 * SMP is not supported yet.
167 */
168 local_timer_interrupt(irq, dev_id);
169
170 return IRQ_HANDLED;
171}
172 117
173void __init time_init(void) 118void __init time_init(void)
174{ 119{
120 unsigned long counter_hz;
175 int ret; 121 int ret;
176 122
177 /*
178 * Make sure we don't get any COMPARE interrupts before we can
179 * handle them.
180 */
181 sysreg_write(COMPARE, 0);
182
183 xtime.tv_sec = mktime(2007, 1, 1, 0, 0, 0); 123 xtime.tv_sec = mktime(2007, 1, 1, 0, 0, 0);
184 xtime.tv_nsec = 0; 124 xtime.tv_nsec = 0;
185 125
186 set_normalized_timespec(&wall_to_monotonic, 126 set_normalized_timespec(&wall_to_monotonic,
187 -xtime.tv_sec, -xtime.tv_nsec); 127 -xtime.tv_sec, -xtime.tv_nsec);
188 128
189 ret = avr32_hpt_init(); 129 /* figure rate for counter */
190 if (ret) { 130 counter_hz = clk_get_rate(boot_cpu_data.clk);
191 pr_debug("timer: failed setup: %d\n", ret); 131 counter.mult = clocksource_hz2mult(counter_hz, counter.shift);
192 return;
193 }
194 132
195 ret = clocksource_register(&clocksource_avr32); 133 ret = clocksource_register(&counter);
196 if (ret) 134 if (ret)
197 pr_debug("timer: could not register clocksource: %d\n", ret); 135 pr_debug("timer: could not register clocksource: %d\n", ret);
198 136
199 ret = avr32_hpt_start(); 137 /* setup COMPARE clockevent */
200 if (ret) { 138 comparator.mult = div_sc(counter_hz, NSEC_PER_SEC, comparator.shift);
201 pr_debug("timer: failed starting: %d\n", ret); 139 comparator.max_delta_ns = clockevent_delta2ns((u32)~0, &comparator);
202 return; 140 comparator.min_delta_ns = clockevent_delta2ns(50, &comparator) + 1;
141
142 sysreg_write(COMPARE, 0);
143 timer_irqaction.dev_id = &comparator;
144
145 ret = setup_irq(0, &timer_irqaction);
146 if (ret)
147 pr_debug("timer: could not request IRQ 0: %d\n", ret);
148 else {
149 clockevents_register_device(&comparator);
150
151 pr_info("%s: irq 0, %lu.%03lu MHz\n", comparator.name,
152 ((counter_hz + 500) / 1000) / 1000,
153 ((counter_hz + 500) / 1000) % 1000);
203 } 154 }
204} 155}
diff --git a/arch/avr32/mach-at32ap/Makefile b/arch/avr32/mach-at32ap/Makefile
index 83cab2abb6c3..e89009439e4a 100644
--- a/arch/avr32/mach-at32ap/Makefile
+++ b/arch/avr32/mach-at32ap/Makefile
@@ -1,4 +1,3 @@
1obj-y += at32ap.o clock.o intc.o extint.o pio.o hsmc.o 1obj-y += at32ap.o clock.o intc.o extint.o pio.o hsmc.o
2obj-$(CONFIG_CPU_AT32AP700X) += at32ap700x.o pm-at32ap700x.o 2obj-$(CONFIG_CPU_AT32AP700X) += at32ap700x.o pm-at32ap700x.o
3obj-$(CONFIG_CPU_AT32AP700X) += time-tc.o
4obj-$(CONFIG_CPU_FREQ_AT32AP) += cpufreq.o 3obj-$(CONFIG_CPU_FREQ_AT32AP) += cpufreq.o
diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c
index 6302bfd58514..22c302ad9b3f 100644
--- a/arch/avr32/mach-at32ap/at32ap700x.c
+++ b/arch/avr32/mach-at32ap/at32ap700x.c
@@ -606,19 +606,32 @@ static inline void set_ebi_sfr_bits(u32 mask)
606} 606}
607 607
608/* -------------------------------------------------------------------- 608/* --------------------------------------------------------------------
609 * System Timer/Counter (TC) 609 * Timer/Counter (TC)
610 * -------------------------------------------------------------------- */ 610 * -------------------------------------------------------------------- */
611static struct resource at32_systc0_resource[] = { 611
612static struct resource at32_tcb0_resource[] = {
612 PBMEM(0xfff00c00), 613 PBMEM(0xfff00c00),
613 IRQ(22), 614 IRQ(22),
614}; 615};
615struct platform_device at32_systc0_device = { 616static struct platform_device at32_tcb0_device = {
616 .name = "systc", 617 .name = "atmel_tcb",
617 .id = 0, 618 .id = 0,
618 .resource = at32_systc0_resource, 619 .resource = at32_tcb0_resource,
619 .num_resources = ARRAY_SIZE(at32_systc0_resource), 620 .num_resources = ARRAY_SIZE(at32_tcb0_resource),
621};
622DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
623
624static struct resource at32_tcb1_resource[] = {
625 PBMEM(0xfff01000),
626 IRQ(23),
627};
628static struct platform_device at32_tcb1_device = {
629 .name = "atmel_tcb",
630 .id = 1,
631 .resource = at32_tcb1_resource,
632 .num_resources = ARRAY_SIZE(at32_tcb1_resource),
620}; 633};
621DEV_CLK(pclk, at32_systc0, pbb, 3); 634DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
622 635
623/* -------------------------------------------------------------------- 636/* --------------------------------------------------------------------
624 * PIO 637 * PIO
@@ -670,7 +683,8 @@ void __init at32_add_system_devices(void)
670 platform_device_register(&pdc_device); 683 platform_device_register(&pdc_device);
671 platform_device_register(&dmaca0_device); 684 platform_device_register(&dmaca0_device);
672 685
673 platform_device_register(&at32_systc0_device); 686 platform_device_register(&at32_tcb0_device);
687 platform_device_register(&at32_tcb1_device);
674 688
675 platform_device_register(&pio0_device); 689 platform_device_register(&pio0_device);
676 platform_device_register(&pio1_device); 690 platform_device_register(&pio1_device);
@@ -1737,7 +1751,8 @@ struct clk *at32_clock_list[] = {
1737 &pio2_mck, 1751 &pio2_mck,
1738 &pio3_mck, 1752 &pio3_mck,
1739 &pio4_mck, 1753 &pio4_mck,
1740 &at32_systc0_pclk, 1754 &at32_tcb0_t0_clk,
1755 &at32_tcb1_t0_clk,
1741 &atmel_usart0_usart, 1756 &atmel_usart0_usart,
1742 &atmel_usart1_usart, 1757 &atmel_usart1_usart,
1743 &atmel_usart2_usart, 1758 &atmel_usart2_usart,
diff --git a/arch/avr32/mach-at32ap/time-tc.c b/arch/avr32/mach-at32ap/time-tc.c
deleted file mode 100644
index 10265863c982..000000000000
--- a/arch/avr32/mach-at32ap/time-tc.c
+++ /dev/null
@@ -1,218 +0,0 @@
1/*
2 * Copyright (C) 2004-2007 Atmel Corporation
3 *
4 * Based on MIPS implementation arch/mips/kernel/time.c
5 * Copyright 2001 MontaVista Software Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/clk.h>
13#include <linux/clocksource.h>
14#include <linux/time.h>
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/irq.h>
18#include <linux/kernel_stat.h>
19#include <linux/errno.h>
20#include <linux/init.h>
21#include <linux/profile.h>
22#include <linux/sysdev.h>
23#include <linux/err.h>
24
25#include <asm/div64.h>
26#include <asm/sysreg.h>
27#include <asm/io.h>
28#include <asm/sections.h>
29
30#include <asm/arch/time.h>
31
32/* how many counter cycles in a jiffy? */
33static u32 cycles_per_jiffy;
34
35/* the count value for the next timer interrupt */
36static u32 expirelo;
37
38/* the I/O registers of the TC module */
39static void __iomem *ioregs;
40
41cycle_t read_cycle_count(void)
42{
43 return (cycle_t)timer_read(ioregs, 0, CV);
44}
45
46struct clocksource clocksource_avr32 = {
47 .name = "avr32",
48 .rating = 342,
49 .read = read_cycle_count,
50 .mask = CLOCKSOURCE_MASK(16),
51 .shift = 16,
52 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
53};
54
55static void avr32_timer_ack(void)
56{
57 u16 count = expirelo;
58
59 /* Ack this timer interrupt and set the next one, use a u16
60 * variable so it will wrap around correctly */
61 count += cycles_per_jiffy;
62 expirelo = count;
63 timer_write(ioregs, 0, RC, expirelo);
64
65 /* Check to see if we have missed any timer interrupts */
66 count = timer_read(ioregs, 0, CV);
67 if ((count - expirelo) < 0x7fff) {
68 expirelo = count + cycles_per_jiffy;
69 timer_write(ioregs, 0, RC, expirelo);
70 }
71}
72
73u32 avr32_hpt_read(void)
74{
75 return timer_read(ioregs, 0, CV);
76}
77
78static int avr32_timer_calc_div_and_set_jiffies(struct clk *pclk)
79{
80 unsigned int cycles_max = (clocksource_avr32.mask + 1) / 2;
81 unsigned int divs[] = { 4, 8, 16, 32 };
82 int divs_size = ARRAY_SIZE(divs);
83 int i = 0;
84 unsigned long count_hz;
85 unsigned long shift;
86 unsigned long mult;
87 int clock_div = -1;
88 u64 tmp;
89
90 shift = clocksource_avr32.shift;
91
92 do {
93 count_hz = clk_get_rate(pclk) / divs[i];
94 mult = clocksource_hz2mult(count_hz, shift);
95 clocksource_avr32.mult = mult;
96
97 tmp = TICK_NSEC;
98 tmp <<= shift;
99 tmp += mult / 2;
100 do_div(tmp, mult);
101
102 cycles_per_jiffy = tmp;
103 } while (cycles_per_jiffy > cycles_max && ++i < divs_size);
104
105 clock_div = i + 1;
106
107 if (clock_div > divs_size) {
108 pr_debug("timer: could not calculate clock divider\n");
109 return -EFAULT;
110 }
111
112 /* Set the clock divider */
113 timer_write(ioregs, 0, CMR, TIMER_BF(CMR_TCCLKS, clock_div));
114
115 return 0;
116}
117
118int avr32_hpt_init(unsigned int count)
119{
120 struct resource *regs;
121 struct clk *pclk;
122 int irq = -1;
123 int ret = 0;
124
125 ret = -ENXIO;
126
127 irq = platform_get_irq(&at32_systc0_device, 0);
128 if (irq < 0) {
129 pr_debug("timer: could not get irq\n");
130 goto out_error;
131 }
132
133 pclk = clk_get(&at32_systc0_device.dev, "pclk");
134 if (IS_ERR(pclk)) {
135 pr_debug("timer: could not get clk: %ld\n", PTR_ERR(pclk));
136 goto out_error;
137 }
138 clk_enable(pclk);
139
140 regs = platform_get_resource(&at32_systc0_device, IORESOURCE_MEM, 0);
141 if (!regs) {
142 pr_debug("timer: could not get resource\n");
143 goto out_error_clk;
144 }
145
146 ioregs = ioremap(regs->start, regs->end - regs->start + 1);
147 if (!ioregs) {
148 pr_debug("timer: could not get ioregs\n");
149 goto out_error_clk;
150 }
151
152 ret = avr32_timer_calc_div_and_set_jiffies(pclk);
153 if (ret)
154 goto out_error_io;
155
156 ret = setup_irq(irq, &timer_irqaction);
157 if (ret) {
158 pr_debug("timer: could not request irq %d: %d\n",
159 irq, ret);
160 goto out_error_io;
161 }
162
163 expirelo = (timer_read(ioregs, 0, CV) / cycles_per_jiffy + 1)
164 * cycles_per_jiffy;
165
166 /* Enable clock and interrupts on RC compare */
167 timer_write(ioregs, 0, CCR, TIMER_BIT(CCR_CLKEN));
168 timer_write(ioregs, 0, IER, TIMER_BIT(IER_CPCS));
169 /* Set cycles to first interrupt */
170 timer_write(ioregs, 0, RC, expirelo);
171
172 printk(KERN_INFO "timer: AT32AP system timer/counter at 0x%p irq %d\n",
173 ioregs, irq);
174
175 return 0;
176
177out_error_io:
178 iounmap(ioregs);
179out_error_clk:
180 clk_put(pclk);
181out_error:
182 return ret;
183}
184
185int avr32_hpt_start(void)
186{
187 timer_write(ioregs, 0, CCR, TIMER_BIT(CCR_SWTRG));
188 return 0;
189}
190
191irqreturn_t timer_interrupt(int irq, void *dev_id)
192{
193 unsigned int sr = timer_read(ioregs, 0, SR);
194
195 if (sr & TIMER_BIT(SR_CPCS)) {
196 /* ack timer interrupt and try to set next interrupt */
197 avr32_timer_ack();
198
199 /*
200 * Call the generic timer interrupt handler
201 */
202 write_seqlock(&xtime_lock);
203 do_timer(1);
204 write_sequnlock(&xtime_lock);
205
206 /*
207 * In UP mode, we call local_timer_interrupt() to do profiling
208 * and process accounting.
209 *
210 * SMP is not supported yet.
211 */
212 local_timer_interrupt(irq, dev_id);
213
214 return IRQ_HANDLED;
215 }
216
217 return IRQ_NONE;
218}
diff --git a/include/asm-avr32/arch-at32ap/time.h b/include/asm-avr32/arch-at32ap/time.h
deleted file mode 100644
index cc8a43418a4d..000000000000
--- a/include/asm-avr32/arch-at32ap/time.h
+++ /dev/null
@@ -1,112 +0,0 @@
1/*
2 * Copyright (C) 2007 Atmel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef _ASM_AVR32_ARCH_AT32AP_TIME_H
10#define _ASM_AVR32_ARCH_AT32AP_TIME_H
11
12#include <linux/platform_device.h>
13
14extern struct irqaction timer_irqaction;
15extern struct platform_device at32_systc0_device;
16extern void local_timer_interrupt(int irq, void *dev_id);
17
18#define TIMER_BCR 0x000000c0
19#define TIMER_BCR_SYNC 0
20#define TIMER_BMR 0x000000c4
21#define TIMER_BMR_TC0XC0S 0
22#define TIMER_BMR_TC1XC1S 2
23#define TIMER_BMR_TC2XC2S 4
24#define TIMER_CCR 0x00000000
25#define TIMER_CCR_CLKDIS 1
26#define TIMER_CCR_CLKEN 0
27#define TIMER_CCR_SWTRG 2
28#define TIMER_CMR 0x00000004
29#define TIMER_CMR_ABETRG 10
30#define TIMER_CMR_ACPA 16
31#define TIMER_CMR_ACPC 18
32#define TIMER_CMR_AEEVT 20
33#define TIMER_CMR_ASWTRG 22
34#define TIMER_CMR_BCPB 24
35#define TIMER_CMR_BCPC 26
36#define TIMER_CMR_BEEVT 28
37#define TIMER_CMR_BSWTRG 30
38#define TIMER_CMR_BURST 4
39#define TIMER_CMR_CLKI 3
40#define TIMER_CMR_CPCDIS 7
41#define TIMER_CMR_CPCSTOP 6
42#define TIMER_CMR_CPCTRG 14
43#define TIMER_CMR_EEVT 10
44#define TIMER_CMR_EEVTEDG 8
45#define TIMER_CMR_ENETRG 12
46#define TIMER_CMR_ETRGEDG 8
47#define TIMER_CMR_LDBDIS 7
48#define TIMER_CMR_LDBSTOP 6
49#define TIMER_CMR_LDRA 16
50#define TIMER_CMR_LDRB 18
51#define TIMER_CMR_TCCLKS 0
52#define TIMER_CMR_WAVE 15
53#define TIMER_CMR_WAVSEL 13
54#define TIMER_CV 0x00000010
55#define TIMER_CV_CV 0
56#define TIMER_IDR 0x00000028
57#define TIMER_IDR_COVFS 0
58#define TIMER_IDR_CPAS 2
59#define TIMER_IDR_CPBS 3
60#define TIMER_IDR_CPCS 4
61#define TIMER_IDR_ETRGS 7
62#define TIMER_IDR_LDRAS 5
63#define TIMER_IDR_LDRBS 6
64#define TIMER_IDR_LOVRS 1
65#define TIMER_IER 0x00000024
66#define TIMER_IER_COVFS 0
67#define TIMER_IER_CPAS 2
68#define TIMER_IER_CPBS 3
69#define TIMER_IER_CPCS 4
70#define TIMER_IER_ETRGS 7
71#define TIMER_IER_LDRAS 5
72#define TIMER_IER_LDRBS 6
73#define TIMER_IER_LOVRS 1
74#define TIMER_IMR 0x0000002c
75#define TIMER_IMR_COVFS 0
76#define TIMER_IMR_CPAS 2
77#define TIMER_IMR_CPBS 3
78#define TIMER_IMR_CPCS 4
79#define TIMER_IMR_ETRGS 7
80#define TIMER_IMR_LDRAS 5
81#define TIMER_IMR_LDRBS 6
82#define TIMER_IMR_LOVRS 1
83#define TIMER_RA 0x00000014
84#define TIMER_RA_RA 0
85#define TIMER_RB 0x00000018
86#define TIMER_RB_RB 0
87#define TIMER_RC 0x0000001c
88#define TIMER_RC_RC 0
89#define TIMER_SR 0x00000020
90#define TIMER_SR_CLKSTA 16
91#define TIMER_SR_COVFS 0
92#define TIMER_SR_CPAS 2
93#define TIMER_SR_CPBS 3
94#define TIMER_SR_CPCS 4
95#define TIMER_SR_ETRGS 7
96#define TIMER_SR_LDRAS 5
97#define TIMER_SR_LDRBS 6
98#define TIMER_SR_LOVRS 1
99#define TIMER_SR_MTIOA 17
100#define TIMER_SR_MTIOB 18
101
102/* Bit manipulation macros */
103#define TIMER_BIT(name) (1 << TIMER_##name)
104#define TIMER_BF(name,value) ((value) << TIMER_##name)
105
106/* Register access macros */
107#define timer_read(port,instance,reg) \
108 __raw_readl(port + (0x40 * instance) + TIMER_##reg)
109#define timer_write(port,instance,reg,value) \
110 __raw_writel((value), port + (0x40 * instance) + TIMER_##reg)
111
112#endif /* _ASM_AVR32_ARCH_AT32AP_TIME_H */
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