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authorLinus Torvalds <torvalds@linux-foundation.org>2009-12-17 19:38:06 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2009-12-17 19:38:06 -0500
commitdbfc985195410dad803c845743c63cd73bd1fe32 (patch)
tree6bf6dbecb92539285ebb89948e63e691a0947941
parent7c508e50be47737b9a72d0f15c3ef1146925e2d2 (diff)
parent606d62fa02cf1da43c6e21521650fff07a2e56d1 (diff)
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (71 commits) MIPS: Lasat: Fix botched changes to sysctl code. RTC: rtc-cmos.c: Fix warning on MIPS MIPS: Cleanup random differences beween lmo and Linus' kernel. MIPS: No longer hardwire CONFIG_EMBEDDED to y MIPS: Fix and enhance built-in kernel command line MIPS: eXcite: Remove platform. MIPS: Loongson: Cleanups of serial port support MIPS: Lemote 2F: Suspend CS5536 MFGPT Timer MIPS: Excite: move iodev_remove to .devexit.text MIPS: Lasat: Convert to proc_fops / seq_file MIPS: Cleanup signal code initialization MIPS: Modularize COP2 handling MIPS: Move EARLY_PRINTK to Kconfig.debug MIPS: Yeeloong 2F: Cleanup reset logic using the new ec_write function MIPS: Yeeloong 2F: Add LID open event as the wakeup event MIPS: Yeeloong 2F: Add basic EC operations MIPS: Move several variables from .bss to .init.data MIPS: Tracing: Make function graph tracer work with -mmcount-ra-address MIPS: Tracing: Reserve $12(t0) for mcount-ra-address of gcc 4.5 MIPS: Tracing: Make ftrace for MIPS work without -fno-omit-frame-pointer ...
Diffstat
-rw-r--r--arch/mips/Kconfig119
-rw-r--r--arch/mips/Kconfig.debug59
-rw-r--r--arch/mips/Makefile57
-rw-r--r--arch/mips/ar7/platform.c2
-rw-r--r--arch/mips/basler/excite/Kconfig9
-rw-r--r--arch/mips/basler/excite/Makefile8
-rw-r--r--arch/mips/basler/excite/excite_device.c403
-rw-r--r--arch/mips/basler/excite/excite_iodev.c178
-rw-r--r--arch/mips/basler/excite/excite_iodev.h10
-rw-r--r--arch/mips/basler/excite/excite_irq.c122
-rw-r--r--arch/mips/basler/excite/excite_procfs.c92
-rw-r--r--arch/mips/basler/excite/excite_prom.c144
-rw-r--r--arch/mips/basler/excite/excite_setup.c302
-rw-r--r--arch/mips/bcm47xx/prom.c10
-rw-r--r--arch/mips/boot/Makefile8
-rw-r--r--arch/mips/boot/addinitrd.c131
-rw-r--r--arch/mips/boot/compressed/Makefile100
-rw-r--r--arch/mips/boot/compressed/dbg.c37
-rw-r--r--arch/mips/boot/compressed/decompress.c126
-rw-r--r--arch/mips/boot/compressed/dummy.c4
-rw-r--r--arch/mips/boot/compressed/head.S56
-rw-r--r--arch/mips/boot/compressed/ld.script150
-rw-r--r--arch/mips/boot/compressed/uart-16550.c43
-rw-r--r--arch/mips/cavium-octeon/Makefile2
-rw-r--r--arch/mips/cavium-octeon/cpu.c52
-rw-r--r--arch/mips/cavium-octeon/octeon-platform.c88
-rw-r--r--arch/mips/configs/ar7_defconfig4
-rw-r--r--arch/mips/configs/bcm47xx_defconfig3
-rw-r--r--arch/mips/configs/bcm63xx_defconfig3
-rw-r--r--arch/mips/configs/bigsur_defconfig3
-rw-r--r--arch/mips/configs/capcella_defconfig3
-rw-r--r--arch/mips/configs/cavium-octeon_defconfig4
-rw-r--r--arch/mips/configs/cobalt_defconfig3
-rw-r--r--arch/mips/configs/db1000_defconfig3
-rw-r--r--arch/mips/configs/db1100_defconfig3
-rw-r--r--arch/mips/configs/db1200_defconfig3
-rw-r--r--arch/mips/configs/db1500_defconfig3
-rw-r--r--arch/mips/configs/db1550_defconfig3
-rw-r--r--arch/mips/configs/decstation_defconfig3
-rw-r--r--arch/mips/configs/e55_defconfig3
-rw-r--r--arch/mips/configs/excite_defconfig1335
-rw-r--r--arch/mips/configs/fuloong2e_defconfig96
-rw-r--r--arch/mips/configs/ip22_defconfig3
-rw-r--r--arch/mips/configs/ip27_defconfig3
-rw-r--r--arch/mips/configs/ip28_defconfig3
-rw-r--r--arch/mips/configs/ip32_defconfig3
-rw-r--r--arch/mips/configs/jazz_defconfig3
-rw-r--r--arch/mips/configs/jmr3927_defconfig3
-rw-r--r--arch/mips/configs/lasat_defconfig3
-rw-r--r--arch/mips/configs/lemote2f_defconfig1835
-rw-r--r--arch/mips/configs/malta_defconfig3
-rw-r--r--arch/mips/configs/markeins_defconfig3
-rw-r--r--arch/mips/configs/mipssim_defconfig3
-rw-r--r--arch/mips/configs/mpc30x_defconfig3
-rw-r--r--arch/mips/configs/msp71xx_defconfig3
-rw-r--r--arch/mips/configs/mtx1_defconfig3
-rw-r--r--arch/mips/configs/pb1100_defconfig3
-rw-r--r--arch/mips/configs/pb1500_defconfig3
-rw-r--r--arch/mips/configs/pb1550_defconfig3
-rw-r--r--arch/mips/configs/pnx8335-stb225_defconfig3
-rw-r--r--arch/mips/configs/pnx8550-jbs_defconfig3
-rw-r--r--arch/mips/configs/pnx8550-stb810_defconfig3
-rw-r--r--arch/mips/configs/powertv_defconfig1550
-rw-r--r--arch/mips/configs/rb532_defconfig3
-rw-r--r--arch/mips/configs/rbtx49xx_defconfig4
-rw-r--r--arch/mips/configs/rm200_defconfig3
-rw-r--r--arch/mips/configs/sb1250-swarm_defconfig3
-rw-r--r--arch/mips/configs/tb0219_defconfig3
-rw-r--r--arch/mips/configs/tb0226_defconfig3
-rw-r--r--arch/mips/configs/tb0287_defconfig3
-rw-r--r--arch/mips/configs/workpad_defconfig3
-rw-r--r--arch/mips/configs/wrppmc_defconfig3
-rw-r--r--arch/mips/configs/yosemite_defconfig3
-rw-r--r--arch/mips/fw/arc/cmdline.c5
-rw-r--r--arch/mips/include/asm/bootinfo.h8
-rw-r--r--arch/mips/include/asm/clock.h64
-rw-r--r--arch/mips/include/asm/cop2.h23
-rw-r--r--arch/mips/include/asm/cpu.h2
-rw-r--r--arch/mips/include/asm/fpu.h8
-rw-r--r--arch/mips/include/asm/fpu_emulator.h24
-rw-r--r--arch/mips/include/asm/ftrace.h91
-rw-r--r--arch/mips/include/asm/irq.h29
-rw-r--r--arch/mips/include/asm/mach-excite/cpu-feature-overrides.h48
-rw-r--r--arch/mips/include/asm/mach-excite/excite.h154
-rw-r--r--arch/mips/include/asm/mach-excite/excite_fpga.h80
-rw-r--r--arch/mips/include/asm/mach-excite/excite_nandflash.h7
-rw-r--r--arch/mips/include/asm/mach-excite/rm9k_eth.h23
-rw-r--r--arch/mips/include/asm/mach-excite/rm9k_wdt.h12
-rw-r--r--arch/mips/include/asm/mach-excite/rm9k_xicap.h16
-rw-r--r--arch/mips/include/asm/mach-loongson/cs5536/cs5536.h305
-rw-r--r--arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h35
-rw-r--r--arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h153
-rw-r--r--arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h31
-rw-r--r--arch/mips/include/asm/mach-loongson/dma-coherence.h4
-rw-r--r--arch/mips/include/asm/mach-loongson/loongson.h290
-rw-r--r--arch/mips/include/asm/mach-loongson/machine.h9
-rw-r--r--arch/mips/include/asm/mach-loongson/mem.h27
-rw-r--r--arch/mips/include/asm/mach-loongson/pci.h34
-rw-r--r--arch/mips/include/asm/mach-powertv/asic.h107
-rw-r--r--arch/mips/include/asm/mach-powertv/asic_regs.h155
-rw-r--r--arch/mips/include/asm/mach-powertv/dma-coherence.h119
-rw-r--r--arch/mips/include/asm/mach-powertv/interrupts.h254
-rw-r--r--arch/mips/include/asm/mach-powertv/ioremap.h90
-rw-r--r--arch/mips/include/asm/mach-powertv/irq.h25
-rw-r--r--arch/mips/include/asm/mach-powertv/powertv-clock.h29
-rw-r--r--arch/mips/include/asm/mach-powertv/war.h (renamed from arch/mips/include/asm/mach-excite/war.h)19
-rw-r--r--arch/mips/include/asm/mips-boards/bonito64.h5
-rw-r--r--arch/mips/include/asm/mmu_context.h29
-rw-r--r--arch/mips/include/asm/octeon/cvmx-agl-defs.h1194
-rw-r--r--arch/mips/include/asm/octeon/cvmx-mixx-defs.h248
-rw-r--r--arch/mips/include/asm/octeon/cvmx-smix-defs.h178
-rw-r--r--arch/mips/include/asm/octeon/octeon.h1
-rw-r--r--arch/mips/include/asm/pgtable.h13
-rw-r--r--arch/mips/include/asm/sgialib.h3
-rw-r--r--arch/mips/include/asm/stackframe.h40
-rw-r--r--arch/mips/kernel/Makefile14
-rw-r--r--arch/mips/kernel/cpu-probe.c2
-rw-r--r--arch/mips/kernel/cpufreq/Kconfig41
-rw-r--r--arch/mips/kernel/cpufreq/Makefile5
-rw-r--r--arch/mips/kernel/cpufreq/loongson2_clock.c166
-rw-r--r--arch/mips/kernel/cpufreq/loongson2_cpufreq.c227
-rw-r--r--arch/mips/kernel/csrc-powertv.c180
-rw-r--r--arch/mips/kernel/ftrace.c275
-rw-r--r--arch/mips/kernel/irq.c30
-rw-r--r--arch/mips/kernel/mcount.S189
-rw-r--r--arch/mips/kernel/mips_ksyms.c5
-rw-r--r--arch/mips/kernel/setup.c44
-rw-r--r--arch/mips/kernel/signal.c46
-rw-r--r--arch/mips/kernel/signal32.c24
-rw-r--r--arch/mips/kernel/smp.c3
-rw-r--r--arch/mips/kernel/smtc.c21
-rw-r--r--arch/mips/kernel/traps.c136
-rw-r--r--arch/mips/kernel/unaligned.c25
-rw-r--r--arch/mips/kernel/vmlinux.lds.S1
-rw-r--r--arch/mips/lasat/picvue_proc.c113
-rw-r--r--arch/mips/lasat/prom.c4
-rw-r--r--arch/mips/lasat/sysctl.c2
-rw-r--r--arch/mips/loongson/Kconfig108
-rw-r--r--arch/mips/loongson/Makefile6
-rw-r--r--arch/mips/loongson/common/Makefile18
-rw-r--r--arch/mips/loongson/common/bonito-irq.c13
-rw-r--r--arch/mips/loongson/common/cmdline.c4
-rw-r--r--arch/mips/loongson/common/cs5536/Makefile13
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_acc.c140
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_ehci.c158
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_ide.c179
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_isa.c316
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_mfgpt.c217
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_ohci.c147
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_pci.c87
-rw-r--r--arch/mips/loongson/common/early_printk.c17
-rw-r--r--arch/mips/loongson/common/env.c3
-rw-r--r--arch/mips/loongson/common/init.c19
-rw-r--r--arch/mips/loongson/common/irq.c12
-rw-r--r--arch/mips/loongson/common/machtype.c25
-rw-r--r--arch/mips/loongson/common/mem.c91
-rw-r--r--arch/mips/loongson/common/pci.c20
-rw-r--r--arch/mips/loongson/common/platform.c30
-rw-r--r--arch/mips/loongson/common/pm.c161
-rw-r--r--arch/mips/loongson/common/reset.c2
-rw-r--r--arch/mips/loongson/common/serial.c76
-rw-r--r--arch/mips/loongson/common/time.c3
-rw-r--r--arch/mips/loongson/common/uart_base.c45
-rw-r--r--arch/mips/loongson/fuloong-2e/irq.c4
-rw-r--r--arch/mips/loongson/fuloong-2e/reset.c4
-rw-r--r--arch/mips/loongson/lemote-2f/Makefile11
-rw-r--r--arch/mips/loongson/lemote-2f/ec_kb3310b.c130
-rw-r--r--arch/mips/loongson/lemote-2f/ec_kb3310b.h188
-rw-r--r--arch/mips/loongson/lemote-2f/irq.c134
-rw-r--r--arch/mips/loongson/lemote-2f/pm.c149
-rw-r--r--arch/mips/loongson/lemote-2f/reset.c159
-rw-r--r--arch/mips/math-emu/cp1emu.c102
-rw-r--r--arch/mips/math-emu/dsemul.c4
-rw-r--r--arch/mips/mipssim/Makefile3
-rw-r--r--arch/mips/mipssim/sim_setup.c1
-rw-r--r--arch/mips/mm/cerr-sb1.c7
-rw-r--r--arch/mips/mm/init.c2
-rw-r--r--arch/mips/mm/tlbex.c28
-rw-r--r--arch/mips/mm/uasm.c16
-rw-r--r--arch/mips/mm/uasm.h7
-rw-r--r--arch/mips/mti-malta/malta-memory.c2
-rw-r--r--arch/mips/nxp/pnx833x/common/interrupts.c4
-rw-r--r--arch/mips/oprofile/op_model_loongson2.c5
-rw-r--r--arch/mips/pci/Makefile4
-rw-r--r--arch/mips/pci/fixup-excite.c36
-rw-r--r--arch/mips/pci/fixup-fuloong2e.c5
-rw-r--r--arch/mips/pci/fixup-lemote2f.c160
-rw-r--r--arch/mips/pci/ops-bonito64.c7
-rw-r--r--arch/mips/pci/ops-loongson2.c208
-rw-r--r--arch/mips/pci/pci-excite.c149
-rw-r--r--arch/mips/powertv/Kconfig21
-rw-r--r--arch/mips/powertv/Makefile28
-rw-r--r--arch/mips/powertv/asic/Kconfig28
-rw-r--r--arch/mips/powertv/asic/Makefile23
-rw-r--r--arch/mips/powertv/asic/asic-calliope.c98
-rw-r--r--arch/mips/powertv/asic/asic-cronus.c98
-rw-r--r--arch/mips/powertv/asic/asic-zeus.c98
-rw-r--r--arch/mips/powertv/asic/asic_devices.c787
-rw-r--r--arch/mips/powertv/asic/asic_int.c125
-rw-r--r--arch/mips/powertv/asic/irq_asic.c116
-rw-r--r--arch/mips/powertv/asic/prealloc-calliope.c620
-rw-r--r--arch/mips/powertv/asic/prealloc-cronus.c608
-rw-r--r--arch/mips/powertv/asic/prealloc-cronuslite.c290
-rw-r--r--arch/mips/powertv/asic/prealloc-zeus.c459
-rw-r--r--arch/mips/powertv/cmdline.c52
-rw-r--r--arch/mips/powertv/init.c128
-rw-r--r--arch/mips/powertv/init.h28
-rw-r--r--arch/mips/powertv/memory.c186
-rw-r--r--arch/mips/powertv/pci/Makefile21
-rw-r--r--arch/mips/powertv/pci/fixup-powertv.c36
-rw-r--r--arch/mips/powertv/pci/powertv-pci.h31
-rw-r--r--arch/mips/powertv/powertv-clock.h26
-rw-r--r--arch/mips/powertv/powertv_setup.c351
-rw-r--r--arch/mips/powertv/reset.c65
-rw-r--r--arch/mips/powertv/reset.h26
-rw-r--r--arch/mips/powertv/time.c (renamed from arch/mips/mipssim/sim_cmdline.c)21
-rw-r--r--arch/mips/rb532/prom.c4
-rw-r--r--arch/mips/sgi-ip22/ip22-eisa.c4
-rw-r--r--arch/mips/sgi-ip22/ip22-int.c3
-rw-r--r--arch/mips/sgi-ip22/ip22-setup.c2
-rw-r--r--arch/mips/sgi-ip22/ip22-time.c3
-rw-r--r--arch/mips/sgi-ip32/ip32-setup.c2
-rw-r--r--arch/mips/sibyte/common/cfe.c4
-rw-r--r--arch/mips/sni/a20r.c2
-rw-r--r--arch/mips/sni/pcimt.c2
-rw-r--r--arch/mips/sni/pcit.c2
-rw-r--r--arch/mips/sni/rm200.c2
-rw-r--r--arch/mips/sni/setup.c2
-rw-r--r--arch/mips/txx9/generic/setup.c4
-rw-r--r--drivers/mtd/nand/Kconfig8
-rw-r--r--drivers/mtd/nand/Makefile1
-rw-r--r--drivers/mtd/nand/excite_nandflash.c248
-rw-r--r--drivers/net/Kconfig2
-rw-r--r--drivers/net/Makefile2
-rw-r--r--drivers/net/octeon/Kconfig10
-rw-r--r--drivers/net/octeon/Makefile2
-rw-r--r--drivers/net/octeon/octeon_mgmt.c1176
-rw-r--r--drivers/net/phy/Kconfig11
-rw-r--r--drivers/net/phy/Makefile1
-rw-r--r--drivers/net/phy/mdio-octeon.c180
-rw-r--r--drivers/rtc/rtc-cmos.c3
-rw-r--r--drivers/staging/octeon/Kconfig3
-rw-r--r--drivers/staging/octeon/ethernet-mdio.c204
-rw-r--r--drivers/staging/octeon/ethernet-mdio.h2
-rw-r--r--drivers/staging/octeon/ethernet-proc.c112
-rw-r--r--drivers/staging/octeon/ethernet-rgmii.c52
-rw-r--r--drivers/staging/octeon/ethernet-sgmii.c2
-rw-r--r--drivers/staging/octeon/ethernet-xaui.c2
-rw-r--r--drivers/staging/octeon/ethernet.c23
-rw-r--r--drivers/staging/octeon/octeon-ethernet.h6
-rw-r--r--drivers/watchdog/Kconfig10
-rw-r--r--drivers/watchdog/Makefile1
-rw-r--r--drivers/watchdog/rm9k_wdt.c419
-rw-r--r--scripts/Makefile.build1
-rwxr-xr-xscripts/recordmcount.pl58
255 files changed, 18310 insertions, 4878 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index fd7620f025fa..9541171f1220 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -5,9 +5,12 @@ config MIPS
5 select HAVE_IDE 5 select HAVE_IDE
6 select HAVE_OPROFILE 6 select HAVE_OPROFILE
7 select HAVE_ARCH_KGDB 7 select HAVE_ARCH_KGDB
8 # Horrible source of confusion. Die, die, die ... 8 select HAVE_FUNCTION_TRACER
9 select EMBEDDED 9 select HAVE_FUNCTION_TRACE_MCOUNT_TEST
10 select RTC_LIB if !LEMOTE_FULOONG2E 10 select HAVE_DYNAMIC_FTRACE
11 select HAVE_FTRACE_MCOUNT_RECORD
12 select HAVE_FUNCTION_GRAPH_TRACER
13 select RTC_LIB if !MACH_LOONGSON
11 14
12mainmenu "Linux/MIPS Kernel Configuration" 15mainmenu "Linux/MIPS Kernel Configuration"
13 16
@@ -22,6 +25,7 @@ choice
22 25
23config MACH_ALCHEMY 26config MACH_ALCHEMY
24 bool "Alchemy processor based machines" 27 bool "Alchemy processor based machines"
28 select SYS_SUPPORTS_ZBOOT
25 29
26config AR7 30config AR7
27 bool "Texas Instruments AR7" 31 bool "Texas Instruments AR7"
@@ -36,6 +40,7 @@ config AR7
36 select SYS_HAS_EARLY_PRINTK 40 select SYS_HAS_EARLY_PRINTK
37 select SYS_SUPPORTS_32BIT_KERNEL 41 select SYS_SUPPORTS_32BIT_KERNEL
38 select SYS_SUPPORTS_LITTLE_ENDIAN 42 select SYS_SUPPORTS_LITTLE_ENDIAN
43 select SYS_SUPPORTS_ZBOOT_UART16550
39 select GENERIC_GPIO 44 select GENERIC_GPIO
40 select GCD 45 select GCD
41 select VLYNQ 46 select VLYNQ
@@ -43,23 +48,6 @@ config AR7
43 Support for the Texas Instruments AR7 System-on-a-Chip 48 Support for the Texas Instruments AR7 System-on-a-Chip
44 family: TNETD7100, 7200 and 7300. 49 family: TNETD7100, 7200 and 7300.
45 50
46config BASLER_EXCITE
47 bool "Basler eXcite smart camera"
48 select CEVT_R4K
49 select CSRC_R4K
50 select DMA_COHERENT
51 select HW_HAS_PCI
52 select IRQ_CPU
53 select IRQ_CPU_RM7K
54 select IRQ_CPU_RM9K
55 select MIPS_RM9122
56 select SYS_HAS_CPU_RM9000
57 select SYS_SUPPORTS_32BIT_KERNEL
58 select SYS_SUPPORTS_BIG_ENDIAN
59 help
60 The eXcite is a smart camera platform manufactured by
61 Basler Vision Technologies AG.
62
63config BCM47XX 51config BCM47XX
64 bool "BCM47XX based boards" 52 bool "BCM47XX based boards"
65 select CEVT_R4K 53 select CEVT_R4K
@@ -192,6 +180,7 @@ config LASAT
192 180
193config MACH_LOONGSON 181config MACH_LOONGSON
194 bool "Loongson family of machines" 182 bool "Loongson family of machines"
183 select SYS_SUPPORTS_ZBOOT_UART16550
195 help 184 help
196 This enables the support of Loongson family of machines. 185 This enables the support of Loongson family of machines.
197 186
@@ -233,6 +222,7 @@ config MIPS_MALTA
233 select SYS_SUPPORTS_MIPS_CMP 222 select SYS_SUPPORTS_MIPS_CMP
234 select SYS_SUPPORTS_MULTITHREADING 223 select SYS_SUPPORTS_MULTITHREADING
235 select SYS_SUPPORTS_SMARTMIPS 224 select SYS_SUPPORTS_SMARTMIPS
225 select SYS_SUPPORTS_ZBOOT
236 help 226 help
237 This enables support for the MIPS Technologies Malta evaluation 227 This enables support for the MIPS Technologies Malta evaluation
238 board. 228 board.
@@ -334,6 +324,24 @@ config PMC_YOSEMITE
334 Yosemite is an evaluation board for the RM9000x2 processor 324 Yosemite is an evaluation board for the RM9000x2 processor
335 manufactured by PMC-Sierra. 325 manufactured by PMC-Sierra.
336 326
327config POWERTV
328 bool "Cisco PowerTV"
329 select BOOT_ELF32
330 select CEVT_R4K
331 select CPU_MIPSR2_IRQ_VI
332 select CPU_MIPSR2_IRQ_EI
333 select CSRC_POWERTV
334 select DMA_NONCOHERENT
335 select HW_HAS_PCI
336 select SYS_HAS_EARLY_PRINTK
337 select SYS_HAS_CPU_MIPS32_R2
338 select SYS_SUPPORTS_32BIT_KERNEL
339 select SYS_SUPPORTS_BIG_ENDIAN
340 select SYS_SUPPORTS_HIGHMEM
341 select USB_OHCI_LITTLE_ENDIAN
342 help
343 This enables support for the Cisco PowerTV Platform.
344
337config SGI_IP22 345config SGI_IP22
338 bool "SGI IP22 (Indy/Indigo2)" 346 bool "SGI IP22 (Indy/Indigo2)"
339 select ARC 347 select ARC
@@ -674,11 +682,11 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
674endchoice 682endchoice
675 683
676source "arch/mips/alchemy/Kconfig" 684source "arch/mips/alchemy/Kconfig"
677source "arch/mips/basler/excite/Kconfig"
678source "arch/mips/bcm63xx/Kconfig" 685source "arch/mips/bcm63xx/Kconfig"
679source "arch/mips/jazz/Kconfig" 686source "arch/mips/jazz/Kconfig"
680source "arch/mips/lasat/Kconfig" 687source "arch/mips/lasat/Kconfig"
681source "arch/mips/pmc-sierra/Kconfig" 688source "arch/mips/pmc-sierra/Kconfig"
689source "arch/mips/powertv/Kconfig"
682source "arch/mips/sgi-ip27/Kconfig" 690source "arch/mips/sgi-ip27/Kconfig"
683source "arch/mips/sibyte/Kconfig" 691source "arch/mips/sibyte/Kconfig"
684source "arch/mips/txx9/Kconfig" 692source "arch/mips/txx9/Kconfig"
@@ -778,6 +786,9 @@ config CSRC_BCM1480
778config CSRC_IOASIC 786config CSRC_IOASIC
779 bool 787 bool
780 788
789config CSRC_POWERTV
790 bool
791
781config CSRC_R4K_LIB 792config CSRC_R4K_LIB
782 bool 793 bool
783 794
@@ -806,20 +817,6 @@ config DMA_NONCOHERENT
806config DMA_NEED_PCI_MAP_STATE 817config DMA_NEED_PCI_MAP_STATE
807 bool 818 bool
808 819
809config EARLY_PRINTK
810 bool "Early printk" if EMBEDDED && DEBUG_KERNEL
811 depends on SYS_HAS_EARLY_PRINTK
812 default y
813 help
814 This option enables special console drivers which allow the kernel
815 to print messages very early in the bootup process.
816
817 This is useful for kernel debugging when your machine crashes very
818 early before the console code is initialized. For normal operation,
819 it is not recommended because it looks ugly on some machines and
820 doesn't cooperate with an X server. You should normally say N here,
821 unless you want to debug such a crash.
822
823config SYS_HAS_EARLY_PRINTK 820config SYS_HAS_EARLY_PRINTK
824 bool 821 bool
825 822
@@ -1069,6 +1066,21 @@ config CPU_LOONGSON2E
1069 The Loongson 2E processor implements the MIPS III instruction set 1066 The Loongson 2E processor implements the MIPS III instruction set
1070 with many extensions. 1067 with many extensions.
1071 1068
1069 It has an internal FPGA northbridge, which is compatiable to
1070 bonito64.
1071
1072config CPU_LOONGSON2F
1073 bool "Loongson 2F"
1074 depends on SYS_HAS_CPU_LOONGSON2F
1075 select CPU_LOONGSON2
1076 help
1077 The Loongson 2F processor implements the MIPS III instruction set
1078 with many extensions.
1079
1080 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
1081 have a similar programming interface with FPGA northbridge used in
1082 Loongson2E.
1083
1072config CPU_MIPS32_R1 1084config CPU_MIPS32_R1
1073 bool "MIPS32 Release 1" 1085 bool "MIPS32 Release 1"
1074 depends on SYS_HAS_CPU_MIPS32_R1 1086 depends on SYS_HAS_CPU_MIPS32_R1
@@ -1294,6 +1306,16 @@ config CPU_CAVIUM_OCTEON
1294 1306
1295endchoice 1307endchoice
1296 1308
1309config SYS_SUPPORTS_ZBOOT
1310 bool
1311 select HAVE_KERNEL_GZIP
1312 select HAVE_KERNEL_BZIP2
1313 select HAVE_KERNEL_LZMA
1314
1315config SYS_SUPPORTS_ZBOOT_UART16550
1316 bool
1317 select SYS_SUPPORTS_ZBOOT
1318
1297config CPU_LOONGSON2 1319config CPU_LOONGSON2
1298 bool 1320 bool
1299 select CPU_SUPPORTS_32BIT_KERNEL 1321 select CPU_SUPPORTS_32BIT_KERNEL
@@ -1303,6 +1325,12 @@ config CPU_LOONGSON2
1303config SYS_HAS_CPU_LOONGSON2E 1325config SYS_HAS_CPU_LOONGSON2E
1304 bool 1326 bool
1305 1327
1328config SYS_HAS_CPU_LOONGSON2F
1329 bool
1330 select CPU_SUPPORTS_CPUFREQ
1331 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
1332 select CPU_SUPPORTS_UNCACHED_ACCELERATED
1333
1306config SYS_HAS_CPU_MIPS32_R1 1334config SYS_HAS_CPU_MIPS32_R1
1307 bool 1335 bool
1308 1336
@@ -1411,8 +1439,17 @@ config CPU_SUPPORTS_32BIT_KERNEL
1411 bool 1439 bool
1412config CPU_SUPPORTS_64BIT_KERNEL 1440config CPU_SUPPORTS_64BIT_KERNEL
1413 bool 1441 bool
1442config CPU_SUPPORTS_CPUFREQ
1443 bool
1444config CPU_SUPPORTS_ADDRWINCFG
1445 bool
1414config CPU_SUPPORTS_HUGEPAGES 1446config CPU_SUPPORTS_HUGEPAGES
1415 bool 1447 bool
1448config CPU_SUPPORTS_UNCACHED_ACCELERATED
1449 bool
1450config MIPS_PGD_C0_CONTEXT
1451 bool
1452 default y if 64BIT && CPU_MIPSR2
1416 1453
1417# 1454#
1418# Set to y for ptrace access to watch registers. 1455# Set to y for ptrace access to watch registers.
@@ -2024,15 +2061,6 @@ config STACKTRACE_SUPPORT
2024 2061
2025source "init/Kconfig" 2062source "init/Kconfig"
2026 2063
2027config PROBE_INITRD_HEADER
2028 bool "Probe initrd header created by addinitrd"
2029 depends on BLK_DEV_INITRD
2030 help
2031 Probe initrd header at the last page of kernel image.
2032 Say Y here if you are using arch/mips/boot/addinitrd.c to
2033 add initrd or initramfs image to the kernel image.
2034 Otherwise, say N.
2035
2036source "kernel/Kconfig.freezer" 2064source "kernel/Kconfig.freezer"
2037 2065
2038menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)" 2066menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
@@ -2104,6 +2132,7 @@ config MMU
2104 2132
2105config I8253 2133config I8253
2106 bool 2134 bool
2135 select MIPS_EXTERNAL_TIMER
2107 2136
2108config ZONE_DMA32 2137config ZONE_DMA32
2109 bool 2138 bool
@@ -2180,6 +2209,8 @@ source "kernel/power/Kconfig"
2180 2209
2181endmenu 2210endmenu
2182 2211
2212source "arch/mips/kernel/cpufreq/Kconfig"
2213
2183source "net/Kconfig" 2214source "net/Kconfig"
2184 2215
2185source "drivers/Kconfig" 2216source "drivers/Kconfig"
diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug
index 364ca8938807..d2b88a0be519 100644
--- a/arch/mips/Kconfig.debug
+++ b/arch/mips/Kconfig.debug
@@ -6,15 +6,66 @@ config TRACE_IRQFLAGS_SUPPORT
6 6
7source "lib/Kconfig.debug" 7source "lib/Kconfig.debug"
8 8
9config EARLY_PRINTK
10 bool "Early printk" if EMBEDDED
11 depends on SYS_HAS_EARLY_PRINTK
12 default y
13 help
14 This option enables special console drivers which allow the kernel
15 to print messages very early in the bootup process.
16
17 This is useful for kernel debugging when your machine crashes very
18 early before the console code is initialized. For normal operation,
19 it is not recommended because it looks ugly on some machines and
20 doesn't cooperate with an X server. You should normally say N here,
21 unless you want to debug such a crash.
22
23config CMDLINE_BOOL
24 bool "Built-in kernel command line"
25 default n
26 help
27 For most systems, it is firmware or second stage bootloader that
28 by default specifies the kernel command line options. However,
29 it might be necessary or advantageous to either override the
30 default kernel command line or add a few extra options to it.
31 For such cases, this option allows you to hardcode your own
32 command line options directly into the kernel. For that, you
33 should choose 'Y' here, and fill in the extra boot arguments
34 in CONFIG_CMDLINE.
35
36 The built-in options will be concatenated to the default command
37 line if CMDLINE_OVERRIDE is set to 'N'. Otherwise, the default
38 command line will be ignored and replaced by the built-in string.
39
40 Most MIPS systems will normally expect 'N' here and rely upon
41 the command line from the firmware or the second-stage bootloader.
42
9config CMDLINE 43config CMDLINE
10 string "Default kernel command string" 44 string "Default kernel command string"
45 depends on CMDLINE_BOOL
11 default "" 46 default ""
12 help 47 help
13 On some platforms, there is currently no way for the boot loader to 48 On some platforms, there is currently no way for the boot loader to
14 pass arguments to the kernel. For these platforms, you can supply 49 pass arguments to the kernel. For these platforms, and for the cases
15 some command-line options at build time by entering them here. In 50 when you want to add some extra options to the command line or ignore
16 other cases you can specify kernel args so that you don't have 51 the default command line, you can supply some command-line options at
17 to set them up in board prom initialization routines. 52 build time by entering them here. In other cases you can specify
53 kernel args so that you don't have to set them up in board prom
54 initialization routines.
55
56 For more information, see the CMDLINE_BOOL and CMDLINE_OVERRIDE
57 options.
58
59config CMDLINE_OVERRIDE
60 bool "Built-in command line overrides firware arguments"
61 default n
62 depends on CMDLINE_BOOL
63 help
64 By setting this option to 'Y' you will have your kernel ignore
65 command line arguments from firmware or second stage bootloader.
66 Instead, the built-in command line will be used exclusively.
67
68 Normally, you will choose 'N' here.
18 69
19config DEBUG_STACK_USAGE 70config DEBUG_STACK_USAGE
20 bool "Enable stack utilization instrumentation" 71 bool "Enable stack utilization instrumentation"
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 77f5021218d3..1893efd43fca 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -48,7 +48,16 @@ ifneq ($(SUBARCH),$(ARCH))
48 endif 48 endif
49endif 49endif
50 50
51ifndef CONFIG_FUNCTION_TRACER
51cflags-y := -ffunction-sections 52cflags-y := -ffunction-sections
53endif
54ifdef CONFIG_FUNCTION_GRAPH_TRACER
55 ifndef KBUILD_MCOUNT_RA_ADDRESS
56 ifeq ($(call cc-option-yn,-mmcount-ra-address), y)
57 cflags-y += -mmcount-ra-address -DKBUILD_MCOUNT_RA_ADDRESS
58 endif
59 endif
60endif
52cflags-y += $(call cc-option, -mno-check-zero-division) 61cflags-y += $(call cc-option, -mno-check-zero-division)
53 62
54ifdef CONFIG_32BIT 63ifdef CONFIG_32BIT
@@ -69,6 +78,7 @@ endif
69 78
70all-$(CONFIG_BOOT_ELF32) := $(vmlinux-32) 79all-$(CONFIG_BOOT_ELF32) := $(vmlinux-32)
71all-$(CONFIG_BOOT_ELF64) := $(vmlinux-64) 80all-$(CONFIG_BOOT_ELF64) := $(vmlinux-64)
81all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlinuz
72 82
73# 83#
74# GCC uses -G 0 -mabicalls -fpic as default. We don't want PIC in the kernel 84# GCC uses -G 0 -mabicalls -fpic as default. We don't want PIC in the kernel
@@ -124,6 +134,8 @@ cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap
124cflags-$(CONFIG_CPU_LOONGSON2) += -Wa,--trap 134cflags-$(CONFIG_CPU_LOONGSON2) += -Wa,--trap
125cflags-$(CONFIG_CPU_LOONGSON2E) += \ 135cflags-$(CONFIG_CPU_LOONGSON2E) += \
126 $(call cc-option,-march=loongson2e,-march=r4600) 136 $(call cc-option,-march=loongson2e,-march=r4600)
137cflags-$(CONFIG_CPU_LOONGSON2F) += \
138 $(call cc-option,-march=loongson2f,-march=r4600)
127 139
128cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ 140cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
129 -Wa,-mips32 -Wa,--trap 141 -Wa,-mips32 -Wa,--trap
@@ -324,6 +336,7 @@ core-$(CONFIG_MACH_LOONGSON) +=arch/mips/loongson/
324cflags-$(CONFIG_MACH_LOONGSON) += -I$(srctree)/arch/mips/include/asm/mach-loongson \ 336cflags-$(CONFIG_MACH_LOONGSON) += -I$(srctree)/arch/mips/include/asm/mach-loongson \
325 -mno-branch-likely 337 -mno-branch-likely
326load-$(CONFIG_LEMOTE_FULOONG2E) +=0xffffffff80100000 338load-$(CONFIG_LEMOTE_FULOONG2E) +=0xffffffff80100000
339load-$(CONFIG_LEMOTE_MACH2F) +=0xffffffff80200000
327 340
328# 341#
329# MIPS Malta board 342# MIPS Malta board
@@ -331,7 +344,7 @@ load-$(CONFIG_LEMOTE_FULOONG2E) +=0xffffffff80100000
331core-$(CONFIG_MIPS_MALTA) += arch/mips/mti-malta/ 344core-$(CONFIG_MIPS_MALTA) += arch/mips/mti-malta/
332cflags-$(CONFIG_MIPS_MALTA) += -I$(srctree)/arch/mips/include/asm/mach-malta 345cflags-$(CONFIG_MIPS_MALTA) += -I$(srctree)/arch/mips/include/asm/mach-malta
333load-$(CONFIG_MIPS_MALTA) += 0xffffffff80100000 346load-$(CONFIG_MIPS_MALTA) += 0xffffffff80100000
334all-$(CONFIG_MIPS_MALTA) := vmlinux.bin 347all-$(CONFIG_MIPS_MALTA) := vmlinuz.bin
335 348
336# 349#
337# MIPS SIM 350# MIPS SIM
@@ -356,13 +369,6 @@ cflags-$(CONFIG_PMC_YOSEMITE) += -I$(srctree)/arch/mips/include/asm/mach-yosemit
356load-$(CONFIG_PMC_YOSEMITE) += 0xffffffff80100000 369load-$(CONFIG_PMC_YOSEMITE) += 0xffffffff80100000
357 370
358# 371#
359# Basler eXcite
360#
361core-$(CONFIG_BASLER_EXCITE) += arch/mips/basler/excite/
362cflags-$(CONFIG_BASLER_EXCITE) += -I$(srctree)/arch/mips/include/asm/mach-excite
363load-$(CONFIG_BASLER_EXCITE) += 0x80100000
364
365#
366# LASAT platforms 372# LASAT platforms
367# 373#
368core-$(CONFIG_LASAT) += arch/mips/lasat/ 374core-$(CONFIG_LASAT) += arch/mips/lasat/
@@ -441,6 +447,13 @@ core-$(CONFIG_NEC_MARKEINS) += arch/mips/emma/markeins/
441load-$(CONFIG_NEC_MARKEINS) += 0xffffffff88100000 447load-$(CONFIG_NEC_MARKEINS) += 0xffffffff88100000
442 448
443# 449#
450# Cisco PowerTV Platform
451#
452core-$(CONFIG_POWERTV) += arch/mips/powertv/
453cflags-$(CONFIG_POWERTV) += -I$(srctree)/arch/mips/include/asm/mach-powertv
454load-$(CONFIG_POWERTV) += 0xffffffff90800000
455
456#
444# SGI IP22 (Indy/Indigo2) 457# SGI IP22 (Indy/Indigo2)
445# 458#
446# Set the load address to >= 0xffffffff88069000 if you want to leave space for 459# Set the load address to >= 0xffffffff88069000 if you want to leave space for
@@ -581,7 +594,7 @@ load-$(CONFIG_SNI_RM) += 0xffffffff80600000
581else 594else
582load-$(CONFIG_SNI_RM) += 0xffffffff80030000 595load-$(CONFIG_SNI_RM) += 0xffffffff80030000
583endif 596endif
584all-$(CONFIG_SNI_RM) := vmlinux.ecoff 597all-$(CONFIG_SNI_RM) := vmlinuz.ecoff
585 598
586# 599#
587# Common TXx9 600# Common TXx9
@@ -699,9 +712,23 @@ vmlinux.64: vmlinux
699 $(OBJCOPY) -O $(64bit-bfd) $(OBJCOPYFLAGS) $< $@ 712 $(OBJCOPY) -O $(64bit-bfd) $(OBJCOPYFLAGS) $< $@
700 713
701makeboot =$(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) $(1) 714makeboot =$(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) $(1)
715makezboot =$(Q)$(MAKE) $(build)=arch/mips/boot/compressed \
716 VMLINUX_LOAD_ADDRESS=$(load-y) 32bit-bfd=$(32bit-bfd) $(1)
702 717
703all: $(all-y) 718all: $(all-y)
704 719
720vmlinuz: vmlinux FORCE
721 +@$(call makezboot,$@)
722
723vmlinuz.bin: vmlinux
724 +@$(call makezboot,$@)
725
726vmlinuz.ecoff: vmlinux
727 +@$(call makezboot,$@)
728
729vmlinuz.srec: vmlinux
730 +@$(call makezboot,$@)
731
705vmlinux.bin: $(vmlinux-32) 732vmlinux.bin: $(vmlinux-32)
706 +@$(call makeboot,$@) 733 +@$(call makeboot,$@)
707 734
@@ -726,11 +753,13 @@ endif
726 753
727install: 754install:
728 $(Q)install -D -m 755 vmlinux $(INSTALL_PATH)/vmlinux-$(KERNELRELEASE) 755 $(Q)install -D -m 755 vmlinux $(INSTALL_PATH)/vmlinux-$(KERNELRELEASE)
756 $(Q)install -D -m 755 vmlinuz $(INSTALL_PATH)/vmlinuz-$(KERNELRELEASE)
729 $(Q)install -D -m 644 .config $(INSTALL_PATH)/config-$(KERNELRELEASE) 757 $(Q)install -D -m 644 .config $(INSTALL_PATH)/config-$(KERNELRELEASE)
730 $(Q)install -D -m 644 System.map $(INSTALL_PATH)/System.map-$(KERNELRELEASE) 758 $(Q)install -D -m 644 System.map $(INSTALL_PATH)/System.map-$(KERNELRELEASE)
731 759
732archclean: 760archclean:
733 @$(MAKE) $(clean)=arch/mips/boot 761 @$(MAKE) $(clean)=arch/mips/boot
762 @$(MAKE) $(clean)=arch/mips/boot/compressed
734 @$(MAKE) $(clean)=arch/mips/lasat 763 @$(MAKE) $(clean)=arch/mips/lasat
735 764
736define archhelp 765define archhelp
@@ -738,10 +767,18 @@ define archhelp
738 echo ' vmlinux.ecoff - ECOFF boot image' 767 echo ' vmlinux.ecoff - ECOFF boot image'
739 echo ' vmlinux.bin - Raw binary boot image' 768 echo ' vmlinux.bin - Raw binary boot image'
740 echo ' vmlinux.srec - SREC boot image' 769 echo ' vmlinux.srec - SREC boot image'
770 echo ' vmlinuz - Compressed boot(zboot) image'
771 echo ' vmlinuz.ecoff - ECOFF zboot image'
772 echo ' vmlinuz.bin - Raw binary zboot image'
773 echo ' vmlinuz.srec - SREC zboot image'
741 echo 774 echo
742 echo ' These will be default as apropriate for a configured platform.' 775 echo ' These will be default as apropriate for a configured platform.'
743endef 776endef
744 777
745CLEAN_FILES += vmlinux.32 \ 778CLEAN_FILES += vmlinux.32 \
746 vmlinux.64 \ 779 vmlinux.64 \
747 vmlinux.ecoff 780 vmlinux.ecoff \
781 vmlinuz \
782 vmlinuz.ecoff \
783 vmlinuz.bin \
784 vmlinuz.srec
diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c
index 835f3f0319ca..85169c08d8dc 100644
--- a/arch/mips/ar7/platform.c
+++ b/arch/mips/ar7/platform.c
@@ -505,7 +505,7 @@ static int __init ar7_register_devices(void)
505 int res; 505 int res;
506 u32 *bootcr, val; 506 u32 *bootcr, val;
507#ifdef CONFIG_SERIAL_8250 507#ifdef CONFIG_SERIAL_8250
508 static struct uart_port uart_port[2]; 508 static struct uart_port uart_port[2] __initdata;
509 509
510 memset(uart_port, 0, sizeof(struct uart_port) * 2); 510 memset(uart_port, 0, sizeof(struct uart_port) * 2);
511 511
diff --git a/arch/mips/basler/excite/Kconfig b/arch/mips/basler/excite/Kconfig
deleted file mode 100644
index ba506075608b..000000000000
--- a/arch/mips/basler/excite/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
1config BASLER_EXCITE_PROTOTYPE
2 bool "Support for pre-release units"
3 depends on BASLER_EXCITE
4 default n
5 help
6 Pre-series (prototype) units are different from later ones in
7 some ways. Select this option if you have one of these. Please
8 note that a kernel built with this option selected will not be
9 able to run on normal units.
diff --git a/arch/mips/basler/excite/Makefile b/arch/mips/basler/excite/Makefile
deleted file mode 100644
index cff29cf46d03..000000000000
--- a/arch/mips/basler/excite/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
1#
2# Makefile for Basler eXcite
3#
4
5obj-$(CONFIG_BASLER_EXCITE) += excite_irq.o excite_prom.o excite_setup.o \
6 excite_device.o excite_procfs.o
7
8obj-m += excite_iodev.o
diff --git a/arch/mips/basler/excite/excite_device.c b/arch/mips/basler/excite/excite_device.c
deleted file mode 100644
index e00bc2d7f301..000000000000
--- a/arch/mips/basler/excite/excite_device.c
+++ /dev/null
@@ -1,403 +0,0 @@
1/*
2 * Copyright (C) 2004 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/platform_device.h>
23#include <linux/ioport.h>
24#include <linux/err.h>
25#include <linux/jiffies.h>
26#include <linux/sched.h>
27#include <asm/types.h>
28#include <asm/rm9k-ocd.h>
29
30#include <excite.h>
31#include <rm9k_eth.h>
32#include <rm9k_wdt.h>
33#include <rm9k_xicap.h>
34#include <excite_nandflash.h>
35
36#include "excite_iodev.h"
37
38#define RM9K_GE_UNIT 0
39#define XICAP_UNIT 0
40#define NAND_UNIT 0
41
42#define DLL_TIMEOUT 3 /* seconds */
43
44
45#define RINIT(__start__, __end__, __name__, __parent__) { \
46 .name = __name__ "_0", \
47 .start = (__start__), \
48 .end = (__end__), \
49 .flags = 0, \
50 .parent = (__parent__) \
51}
52
53#define RINIT_IRQ(__irq__, __name__) { \
54 .name = __name__ "_0", \
55 .start = (__irq__), \
56 .end = (__irq__), \
57 .flags = IORESOURCE_IRQ, \
58 .parent = NULL \
59}
60
61
62
63enum {
64 slice_xicap,
65 slice_eth
66};
67
68
69
70static struct resource
71 excite_ctr_resource __maybe_unused = {
72 .name = "GPI counters",
73 .start = 0,
74 .end = 5,
75 .flags = 0,
76 .parent = NULL,
77 .sibling = NULL,
78 .child = NULL
79 },
80 excite_gpislice_resource __maybe_unused = {
81 .name = "GPI slices",
82 .start = 0,
83 .end = 1,
84 .flags = 0,
85 .parent = NULL,
86 .sibling = NULL,
87 .child = NULL
88 },
89 excite_mdio_channel_resource __maybe_unused = {
90 .name = "MDIO channels",
91 .start = 0,
92 .end = 1,
93 .flags = 0,
94 .parent = NULL,
95 .sibling = NULL,
96 .child = NULL
97 },
98 excite_fifomem_resource __maybe_unused = {
99 .name = "FIFO memory",
100 .start = 0,
101 .end = 767,
102 .flags = 0,
103 .parent = NULL,
104 .sibling = NULL,
105 .child = NULL
106 },
107 excite_scram_resource __maybe_unused = {
108 .name = "Scratch RAM",
109 .start = EXCITE_PHYS_SCRAM,
110 .end = EXCITE_PHYS_SCRAM + EXCITE_SIZE_SCRAM - 1,
111 .flags = IORESOURCE_MEM,
112 .parent = NULL,
113 .sibling = NULL,
114 .child = NULL
115 },
116 excite_fpga_resource __maybe_unused = {
117 .name = "System FPGA",
118 .start = EXCITE_PHYS_FPGA,
119 .end = EXCITE_PHYS_FPGA + EXCITE_SIZE_FPGA - 1,
120 .flags = IORESOURCE_MEM,
121 .parent = NULL,
122 .sibling = NULL,
123 .child = NULL
124 },
125 excite_nand_resource __maybe_unused = {
126 .name = "NAND flash control",
127 .start = EXCITE_PHYS_NAND,
128 .end = EXCITE_PHYS_NAND + EXCITE_SIZE_NAND - 1,
129 .flags = IORESOURCE_MEM,
130 .parent = NULL,
131 .sibling = NULL,
132 .child = NULL
133 },
134 excite_titan_resource __maybe_unused = {
135 .name = "TITAN registers",
136 .start = EXCITE_PHYS_TITAN,
137 .end = EXCITE_PHYS_TITAN + EXCITE_SIZE_TITAN - 1,
138 .flags = IORESOURCE_MEM,
139 .parent = NULL,
140 .sibling = NULL,
141 .child = NULL
142 };
143
144
145
146static void adjust_resources(struct resource *res, unsigned int n)
147{
148 struct resource *p;
149 const unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM
150 | IORESOURCE_IRQ | IORESOURCE_DMA;
151
152 for (p = res; p < res + n; p++) {
153 const struct resource * const parent = p->parent;
154 if (parent) {
155 p->start += parent->start;
156 p->end += parent->start;
157 p->flags = parent->flags & mask;
158 }
159 }
160}
161
162
163
164#if defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE)
165static struct resource xicap_rsrc[] = {
166 RINIT(0x4840, 0x486f, XICAP_RESOURCE_FIFO_RX, &excite_titan_resource),
167 RINIT(0x4940, 0x494b, XICAP_RESOURCE_FIFO_TX, &excite_titan_resource),
168 RINIT(0x5040, 0x5127, XICAP_RESOURCE_XDMA, &excite_titan_resource),
169 RINIT(0x1000, 0x112f, XICAP_RESOURCE_PKTPROC, &excite_titan_resource),
170 RINIT(0x1100, 0x110f, XICAP_RESOURCE_PKT_STREAM, &excite_fpga_resource),
171 RINIT(0x0800, 0x0bff, XICAP_RESOURCE_DMADESC, &excite_scram_resource),
172 RINIT(slice_xicap, slice_xicap, XICAP_RESOURCE_GPI_SLICE, &excite_gpislice_resource),
173 RINIT(0x0100, 0x02ff, XICAP_RESOURCE_FIFO_BLK, &excite_fifomem_resource),
174 RINIT_IRQ(TITAN_IRQ, XICAP_RESOURCE_IRQ)
175};
176
177static struct platform_device xicap_pdev = {
178 .name = XICAP_NAME,
179 .id = XICAP_UNIT,
180 .num_resources = ARRAY_SIZE(xicap_rsrc),
181 .resource = xicap_rsrc
182};
183
184/*
185 * Create a platform device for the GPI port that receives the
186 * image data from the embedded camera.
187 */
188static int __init xicap_devinit(void)
189{
190 unsigned long tend;
191 u32 reg;
192 int retval;
193
194 adjust_resources(xicap_rsrc, ARRAY_SIZE(xicap_rsrc));
195
196 /* Power up the slice and configure it. */
197 reg = titan_readl(CPTC1R);
198 reg &= ~(0x11100 << slice_xicap);
199 titan_writel(reg, CPTC1R);
200
201 /* Enable slice & DLL. */
202 reg= titan_readl(CPRR);
203 reg &= ~(0x00030003 << (slice_xicap * 2));
204 titan_writel(reg, CPRR);
205
206 /* Wait for DLLs to lock */
207 tend = jiffies + DLL_TIMEOUT * HZ;
208 while (time_before(jiffies, tend)) {
209 if (!(~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))))
210 break;
211 yield();
212 }
213
214 if (~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))) {
215 printk(KERN_ERR "%s: DLL not locked after %u seconds\n",
216 xicap_pdev.name, DLL_TIMEOUT);
217 retval = -ETIME;
218 } else {
219 /* Register platform device */
220 retval = platform_device_register(&xicap_pdev);
221 }
222
223 return retval;
224}
225
226device_initcall(xicap_devinit);
227#endif /* defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE) */
228
229
230
231#if defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE)
232static struct resource wdt_rsrc[] = {
233 RINIT(0, 0, WDT_RESOURCE_COUNTER, &excite_ctr_resource),
234 RINIT(0x0084, 0x008f, WDT_RESOURCE_REGS, &excite_titan_resource),
235 RINIT_IRQ(TITAN_IRQ, WDT_RESOURCE_IRQ)
236};
237
238static struct platform_device wdt_pdev = {
239 .name = WDT_NAME,
240 .id = -1,
241 .num_resources = ARRAY_SIZE(wdt_rsrc),
242 .resource = wdt_rsrc
243};
244
245/*
246 * Create a platform device for the GPI port that receives the
247 * image data from the embedded camera.
248 */
249static int __init wdt_devinit(void)
250{
251 adjust_resources(wdt_rsrc, ARRAY_SIZE(wdt_rsrc));
252 return platform_device_register(&wdt_pdev);
253}
254
255device_initcall(wdt_devinit);
256#endif /* defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE) */
257
258
259
260static struct resource excite_nandflash_rsrc[] = {
261 RINIT(0x2000, 0x201f, EXCITE_NANDFLASH_RESOURCE_REGS, &excite_nand_resource)
262};
263
264static struct platform_device excite_nandflash_pdev = {
265 .name = "excite_nand",
266 .id = NAND_UNIT,
267 .num_resources = ARRAY_SIZE(excite_nandflash_rsrc),
268 .resource = excite_nandflash_rsrc
269};
270
271/*
272 * Create a platform device for the access to the nand-flash
273 * port
274 */
275static int __init excite_nandflash_devinit(void)
276{
277 adjust_resources(excite_nandflash_rsrc, ARRAY_SIZE(excite_nandflash_rsrc));
278
279 /* nothing to be done here */
280
281 /* Register platform device */
282 return platform_device_register(&excite_nandflash_pdev);
283}
284
285device_initcall(excite_nandflash_devinit);
286
287
288
289static struct resource iodev_rsrc[] = {
290 RINIT_IRQ(FPGA1_IRQ, IODEV_RESOURCE_IRQ)
291};
292
293static struct platform_device io_pdev = {
294 .name = IODEV_NAME,
295 .id = -1,
296 .num_resources = ARRAY_SIZE(iodev_rsrc),
297 .resource = iodev_rsrc
298};
299
300/*
301 * Create a platform device for the external I/O ports.
302 */
303static int __init io_devinit(void)
304{
305 adjust_resources(iodev_rsrc, ARRAY_SIZE(iodev_rsrc));
306 return platform_device_register(&io_pdev);
307}
308
309device_initcall(io_devinit);
310
311
312
313
314#if defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE)
315static struct resource rm9k_ge_rsrc[] = {
316 RINIT(0x2200, 0x27ff, RM9K_GE_RESOURCE_MAC, &excite_titan_resource),
317 RINIT(0x1800, 0x1fff, RM9K_GE_RESOURCE_MSTAT, &excite_titan_resource),
318 RINIT(0x2000, 0x212f, RM9K_GE_RESOURCE_PKTPROC, &excite_titan_resource),
319 RINIT(0x5140, 0x5227, RM9K_GE_RESOURCE_XDMA, &excite_titan_resource),
320 RINIT(0x4870, 0x489f, RM9K_GE_RESOURCE_FIFO_RX, &excite_titan_resource),
321 RINIT(0x494c, 0x4957, RM9K_GE_RESOURCE_FIFO_TX, &excite_titan_resource),
322 RINIT(0x0000, 0x007f, RM9K_GE_RESOURCE_FIFOMEM_RX, &excite_fifomem_resource),
323 RINIT(0x0080, 0x00ff, RM9K_GE_RESOURCE_FIFOMEM_TX, &excite_fifomem_resource),
324 RINIT(0x0180, 0x019f, RM9K_GE_RESOURCE_PHY, &excite_titan_resource),
325 RINIT(0x0000, 0x03ff, RM9K_GE_RESOURCE_DMADESC_RX, &excite_scram_resource),
326 RINIT(0x0400, 0x07ff, RM9K_GE_RESOURCE_DMADESC_TX, &excite_scram_resource),
327 RINIT(slice_eth, slice_eth, RM9K_GE_RESOURCE_GPI_SLICE, &excite_gpislice_resource),
328 RINIT(0, 0, RM9K_GE_RESOURCE_MDIO_CHANNEL, &excite_mdio_channel_resource),
329 RINIT_IRQ(TITAN_IRQ, RM9K_GE_RESOURCE_IRQ_MAIN),
330 RINIT_IRQ(PHY_IRQ, RM9K_GE_RESOURCE_IRQ_PHY)
331};
332
333static struct platform_device rm9k_ge_pdev = {
334 .name = RM9K_GE_NAME,
335 .id = RM9K_GE_UNIT,
336 .num_resources = ARRAY_SIZE(rm9k_ge_rsrc),
337 .resource = rm9k_ge_rsrc
338};
339
340
341
342/*
343 * Create a platform device for the Ethernet port.
344 */
345static int __init rm9k_ge_devinit(void)
346{
347 u32 reg;
348
349 adjust_resources(rm9k_ge_rsrc, ARRAY_SIZE(rm9k_ge_rsrc));
350
351 /* Power up the slice and configure it. */
352 reg = titan_readl(CPTC1R);
353 reg &= ~(0x11000 << slice_eth);
354 reg |= 0x100 << slice_eth;
355 titan_writel(reg, CPTC1R);
356
357 /* Take the MAC out of reset, reset the DLLs. */
358 reg = titan_readl(CPRR);
359 reg &= ~(0x00030000 << (slice_eth * 2));
360 reg |= 0x3 << (slice_eth * 2);
361 titan_writel(reg, CPRR);
362
363 return platform_device_register(&rm9k_ge_pdev);
364}
365
366device_initcall(rm9k_ge_devinit);
367#endif /* defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE) */
368
369
370
371static int __init excite_setup_devs(void)
372{
373 int res;
374 u32 reg;
375
376 /* Enable xdma and fifo interrupts */
377 reg = titan_readl(0x0050);
378 titan_writel(reg | 0x18000000, 0x0050);
379
380 res = request_resource(&iomem_resource, &excite_titan_resource);
381 if (res)
382 return res;
383 res = request_resource(&iomem_resource, &excite_scram_resource);
384 if (res)
385 return res;
386 res = request_resource(&iomem_resource, &excite_fpga_resource);
387 if (res)
388 return res;
389 res = request_resource(&iomem_resource, &excite_nand_resource);
390 if (res)
391 return res;
392 excite_fpga_resource.flags = excite_fpga_resource.parent->flags &
393 ( IORESOURCE_IO | IORESOURCE_MEM
394 | IORESOURCE_IRQ | IORESOURCE_DMA);
395 excite_nand_resource.flags = excite_nand_resource.parent->flags &
396 ( IORESOURCE_IO | IORESOURCE_MEM
397 | IORESOURCE_IRQ | IORESOURCE_DMA);
398
399 return 0;
400}
401
402arch_initcall(excite_setup_devs);
403
diff --git a/arch/mips/basler/excite/excite_iodev.c b/arch/mips/basler/excite/excite_iodev.c
deleted file mode 100644
index 938b1d0b7652..000000000000
--- a/arch/mips/basler/excite/excite_iodev.c
+++ /dev/null
@@ -1,178 +0,0 @@
1/*
2 * Copyright (C) 2005 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/compiler.h>
21#include <linux/init.h>
22#include <linux/module.h>
23#include <linux/sched.h>
24#include <linux/wait.h>
25#include <linux/poll.h>
26#include <linux/interrupt.h>
27#include <linux/platform_device.h>
28#include <linux/miscdevice.h>
29#include <linux/smp_lock.h>
30
31#include "excite_iodev.h"
32
33
34
35static const struct resource *iodev_get_resource(struct platform_device *, const char *, unsigned int);
36static int __init iodev_probe(struct platform_device *);
37static int __exit iodev_remove(struct platform_device *);
38static int iodev_open(struct inode *, struct file *);
39static int iodev_release(struct inode *, struct file *);
40static ssize_t iodev_read(struct file *, char __user *, size_t s, loff_t *);
41static unsigned int iodev_poll(struct file *, struct poll_table_struct *);
42static irqreturn_t iodev_irqhdl(int, void *);
43
44
45
46static const char iodev_name[] = "iodev";
47static unsigned int iodev_irq;
48static DECLARE_WAIT_QUEUE_HEAD(wq);
49
50
51
52static const struct file_operations fops =
53{
54 .owner = THIS_MODULE,
55 .open = iodev_open,
56 .release = iodev_release,
57 .read = iodev_read,
58 .poll = iodev_poll
59};
60
61static struct miscdevice miscdev =
62{
63 .minor = MISC_DYNAMIC_MINOR,
64 .name = iodev_name,
65 .fops = &fops
66};
67
68static struct platform_driver iodev_driver = {
69 .driver = {
70 .name = iodev_name,
71 .owner = THIS_MODULE,
72 },
73 .probe = iodev_probe,
74 .remove = __devexit_p(iodev_remove),
75};
76
77
78
79static const struct resource *
80iodev_get_resource(struct platform_device *pdv, const char *name,
81 unsigned int type)
82{
83 char buf[80];
84 if (snprintf(buf, sizeof buf, "%s_0", name) >= sizeof buf)
85 return NULL;
86 return platform_get_resource_byname(pdv, type, buf);
87}
88
89
90
91/* No hotplugging on the platform bus - use __init */
92static int __init iodev_probe(struct platform_device *dev)
93{
94 const struct resource * const ri =
95 iodev_get_resource(dev, IODEV_RESOURCE_IRQ, IORESOURCE_IRQ);
96
97 if (unlikely(!ri))
98 return -ENXIO;
99
100 iodev_irq = ri->start;
101 return misc_register(&miscdev);
102}
103
104
105
106static int __exit iodev_remove(struct platform_device *dev)
107{
108 return misc_deregister(&miscdev);
109}
110
111static int iodev_open(struct inode *i, struct file *f)
112{
113 int ret;
114
115 ret = request_irq(iodev_irq, iodev_irqhdl, IRQF_DISABLED,
116 iodev_name, &miscdev);
117
118 return ret;
119}
120
121static int iodev_release(struct inode *i, struct file *f)
122{
123 free_irq(iodev_irq, &miscdev);
124 return 0;
125}
126
127
128
129
130static ssize_t
131iodev_read(struct file *f, char __user *d, size_t s, loff_t *o)
132{
133 ssize_t ret;
134 DEFINE_WAIT(w);
135
136 prepare_to_wait(&wq, &w, TASK_INTERRUPTIBLE);
137 if (!signal_pending(current))
138 schedule();
139 ret = signal_pending(current) ? -ERESTARTSYS : 0;
140 finish_wait(&wq, &w);
141 return ret;
142}
143
144
145static unsigned int iodev_poll(struct file *f, struct poll_table_struct *p)
146{
147 poll_wait(f, &wq, p);
148 return POLLOUT | POLLWRNORM;
149}
150
151static irqreturn_t iodev_irqhdl(int irq, void *ctxt)
152{
153 wake_up(&wq);
154
155 return IRQ_HANDLED;
156}
157
158static int __init iodev_init_module(void)
159{
160 return platform_driver_register(&iodev_driver);
161}
162
163
164
165static void __exit iodev_cleanup_module(void)
166{
167 platform_driver_unregister(&iodev_driver);
168}
169
170module_init(iodev_init_module);
171module_exit(iodev_cleanup_module);
172
173
174
175MODULE_AUTHOR("Thomas Koeller <thomas.koeller@baslerweb.com>");
176MODULE_DESCRIPTION("Basler eXcite i/o interrupt handler");
177MODULE_VERSION("0.0");
178MODULE_LICENSE("GPL");
diff --git a/arch/mips/basler/excite/excite_iodev.h b/arch/mips/basler/excite/excite_iodev.h
deleted file mode 100644
index cbfbb5d2ee62..000000000000
--- a/arch/mips/basler/excite/excite_iodev.h
+++ /dev/null
@@ -1,10 +0,0 @@
1#ifndef __EXCITE_IODEV_H__
2#define __EXCITE_IODEV_H__
3
4/* Device name */
5#define IODEV_NAME "iodev"
6
7/* Resource names */
8#define IODEV_RESOURCE_IRQ "excite_iodev_irq"
9
10#endif /* __EXCITE_IODEV_H__ */
diff --git a/arch/mips/basler/excite/excite_irq.c b/arch/mips/basler/excite/excite_irq.c
deleted file mode 100644
index 934e0a6b1011..000000000000
--- a/arch/mips/basler/excite/excite_irq.c
+++ /dev/null
@@ -1,122 +0,0 @@
1/*
2 * Copyright (C) by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslereb.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/errno.h>
21#include <linux/init.h>
22#include <linux/kernel_stat.h>
23#include <linux/module.h>
24#include <linux/signal.h>
25#include <linux/sched.h>
26#include <linux/types.h>
27#include <linux/interrupt.h>
28#include <linux/ioport.h>
29#include <linux/timex.h>
30#include <linux/slab.h>
31#include <linux/random.h>
32#include <linux/bitops.h>
33#include <asm/bootinfo.h>
34#include <asm/io.h>
35#include <asm/irq.h>
36#include <asm/irq_cpu.h>
37#include <asm/mipsregs.h>
38#include <asm/system.h>
39#include <asm/rm9k-ocd.h>
40
41#include <excite.h>
42
43extern asmlinkage void excite_handle_int(void);
44
45/*
46 * Initialize the interrupt handler
47 */
48void __init arch_init_irq(void)
49{
50 mips_cpu_irq_init();
51 rm7k_cpu_irq_init();
52 rm9k_cpu_irq_init();
53}
54
55asmlinkage void plat_irq_dispatch(void)
56{
57 const u32
58 interrupts = read_c0_cause() >> 8,
59 mask = ((read_c0_status() >> 8) & 0x000000ff) |
60 (read_c0_intcontrol() & 0x0000ff00),
61 pending = interrupts & mask;
62 u32 msgintflags, msgintmask, msgint;
63
64 /* process timer interrupt */
65 if (pending & (1 << TIMER_IRQ)) {
66 do_IRQ(TIMER_IRQ);
67 return;
68 }
69
70 /* Process PCI interrupts */
71#if USB_IRQ < 10
72 msgintflags = ocd_readl(INTP0Status0 + (USB_MSGINT / 0x20 * 0x10));
73 msgintmask = ocd_readl(INTP0Mask0 + (USB_MSGINT / 0x20 * 0x10));
74 msgint = msgintflags & msgintmask & (0x1 << (USB_MSGINT % 0x20));
75 if ((pending & (1 << USB_IRQ)) && msgint) {
76#else
77 if (pending & (1 << USB_IRQ)) {
78#endif
79 do_IRQ(USB_IRQ);
80 return;
81 }
82
83 /* Process TITAN interrupts */
84 msgintflags = ocd_readl(INTP0Status0 + (TITAN_MSGINT / 0x20 * 0x10));
85 msgintmask = ocd_readl(INTP0Mask0 + (TITAN_MSGINT / 0x20 * 0x10));
86 msgint = msgintflags & msgintmask & (0x1 << (TITAN_MSGINT % 0x20));
87 if ((pending & (1 << TITAN_IRQ)) && msgint) {
88 ocd_writel(msgint, INTP0Clear0 + (TITAN_MSGINT / 0x20 * 0x10));
89 do_IRQ(TITAN_IRQ);
90 return;
91 }
92
93 /* Process FPGA line #0 interrupts */
94 msgintflags = ocd_readl(INTP0Status0 + (FPGA0_MSGINT / 0x20 * 0x10));
95 msgintmask = ocd_readl(INTP0Mask0 + (FPGA0_MSGINT / 0x20 * 0x10));
96 msgint = msgintflags & msgintmask & (0x1 << (FPGA0_MSGINT % 0x20));
97 if ((pending & (1 << FPGA0_IRQ)) && msgint) {
98 do_IRQ(FPGA0_IRQ);
99 return;
100 }
101
102 /* Process FPGA line #1 interrupts */
103 msgintflags = ocd_readl(INTP0Status0 + (FPGA1_MSGINT / 0x20 * 0x10));
104 msgintmask = ocd_readl(INTP0Mask0 + (FPGA1_MSGINT / 0x20 * 0x10));
105 msgint = msgintflags & msgintmask & (0x1 << (FPGA1_MSGINT % 0x20));
106 if ((pending & (1 << FPGA1_IRQ)) && msgint) {
107 do_IRQ(FPGA1_IRQ);
108 return;
109 }
110
111 /* Process PHY interrupts */
112 msgintflags = ocd_readl(INTP0Status0 + (PHY_MSGINT / 0x20 * 0x10));
113 msgintmask = ocd_readl(INTP0Mask0 + (PHY_MSGINT / 0x20 * 0x10));
114 msgint = msgintflags & msgintmask & (0x1 << (PHY_MSGINT % 0x20));
115 if ((pending & (1 << PHY_IRQ)) && msgint) {
116 do_IRQ(PHY_IRQ);
117 return;
118 }
119
120 /* Process spurious interrupts */
121 spurious_interrupt();
122}
diff --git a/arch/mips/basler/excite/excite_procfs.c b/arch/mips/basler/excite/excite_procfs.c
deleted file mode 100644
index 08923e6825b5..000000000000
--- a/arch/mips/basler/excite/excite_procfs.c
+++ /dev/null
@@ -1,92 +0,0 @@
1/*
2 * Copyright (C) 2004, 2005 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 *
5 * Procfs support for Basler eXcite
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/module.h>
22#include <linux/proc_fs.h>
23#include <linux/seq_file.h>
24#include <linux/stat.h>
25#include <asm/page.h>
26#include <asm/io.h>
27#include <asm/system.h>
28#include <asm/rm9k-ocd.h>
29
30#include <excite.h>
31
32static int excite_unit_id_proc_show(struct seq_file *m, void *v)
33{
34 seq_printf(m, "%06x", unit_id);
35 return 0;
36}
37
38static int excite_unit_id_proc_open(struct inode *inode, struct file *file)
39{
40 return single_open(file, excite_unit_id_proc_show, NULL);
41}
42
43static const struct file_operations excite_unit_id_proc_fops = {
44 .owner = THIS_MODULE,
45 .open = excite_unit_id_proc_open,
46 .read = seq_read,
47 .llseek = seq_lseek,
48 .release = single_release,
49};
50
51static int
52excite_bootrom_read(char *page, char **start, off_t off, int count,
53 int *eof, void *data)
54{
55 void __iomem * src;
56
57 if (off >= EXCITE_SIZE_BOOTROM) {
58 *eof = 1;
59 return 0;
60 }
61
62 if ((off + count) > EXCITE_SIZE_BOOTROM)
63 count = EXCITE_SIZE_BOOTROM - off;
64
65 src = ioremap(EXCITE_PHYS_BOOTROM + off, count);
66 if (src) {
67 memcpy_fromio(page, src, count);
68 iounmap(src);
69 *start = page;
70 } else {
71 count = -ENOMEM;
72 }
73
74 return count;
75}
76
77void excite_procfs_init(void)
78{
79 /* Create & populate /proc/excite */
80 struct proc_dir_entry * const pdir = proc_mkdir("excite", NULL);
81 if (pdir) {
82 struct proc_dir_entry * e;
83
84 e = proc_create("unit_id", S_IRUGO, pdir,
85 &excite_unit_id_proc_fops);
86 if (e) e->size = 6;
87
88 e = create_proc_read_entry("bootrom", S_IRUGO, pdir,
89 excite_bootrom_read, NULL);
90 if (e) e->size = EXCITE_SIZE_BOOTROM;
91 }
92}
diff --git a/arch/mips/basler/excite/excite_prom.c b/arch/mips/basler/excite/excite_prom.c
deleted file mode 100644
index 68d8bc597e34..000000000000
--- a/arch/mips/basler/excite/excite_prom.c
+++ /dev/null
@@ -1,144 +0,0 @@
1/*
2 * Copyright (C) 2004, 2005 by Thomas Koeller (thomas.koeller@baslerweb.com)
3 * Based on the PMC-Sierra Yosemite board support by Ralf Baechle and
4 * Manish Lachwani.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/init.h>
22#include <linux/sched.h>
23#include <linux/mm.h>
24#include <linux/delay.h>
25#include <linux/smp.h>
26#include <linux/module.h>
27#include <asm/io.h>
28#include <asm/pgtable.h>
29#include <asm/processor.h>
30#include <asm/reboot.h>
31#include <asm/system.h>
32#include <asm/bootinfo.h>
33#include <asm/string.h>
34
35#include <excite.h>
36
37/* This struct is used by Redboot to pass arguments to the kernel */
38typedef struct
39{
40 char *name;
41 char *val;
42} t_env_var;
43
44struct parmblock {
45 t_env_var memsize;
46 t_env_var modetty0;
47 t_env_var ethaddr;
48 t_env_var env_end;
49 char *argv[2];
50 char text[0];
51};
52
53static unsigned int prom_argc;
54static const char ** prom_argv;
55static const t_env_var * prom_env;
56
57static void prom_halt(void) __attribute__((noreturn));
58static void prom_exit(void) __attribute__((noreturn));
59
60
61
62const char *get_system_type(void)
63{
64 return "Basler eXcite";
65}
66
67/*
68 * Halt the system
69 */
70static void prom_halt(void)
71{
72 printk(KERN_NOTICE "\n** System halted.\n");
73 while (1)
74 asm volatile (
75 "\t.set\tmips3\n"
76 "\twait\n"
77 "\t.set\tmips0\n"
78 );
79}
80
81/*
82 * Reset the CPU and re-enter Redboot
83 */
84static void prom_exit(void)
85{
86 unsigned int i;
87 volatile unsigned char * const flg =
88 (volatile unsigned char *) (EXCITE_ADDR_FPGA + EXCITE_FPGA_DPR);
89
90 /* Clear the watchdog reset flag, set the reboot flag */
91 *flg &= ~0x01;
92 *flg |= 0x80;
93
94 for (i = 0; i < 10; i++) {
95 *(volatile unsigned char *) (EXCITE_ADDR_FPGA + EXCITE_FPGA_SYSCTL) = 0x02;
96 iob();
97 mdelay(1000);
98 }
99
100 printk(KERN_NOTICE "Reset failed\n");
101 prom_halt();
102}
103
104static const char __init *prom_getenv(char *name)
105{
106 const t_env_var * p;
107 for (p = prom_env; p->name != NULL; p++)
108 if(strcmp(name, p->name) == 0)
109 break;
110 return p->val;
111}
112
113/*
114 * Init routine which accepts the variables from Redboot
115 */
116void __init prom_init(void)
117{
118 const struct parmblock * const pb = (struct parmblock *) fw_arg2;
119
120 prom_argc = fw_arg0;
121 prom_argv = (const char **) fw_arg1;
122 prom_env = &pb->memsize;
123
124 /* Callbacks for halt, restart */
125 _machine_restart = (void (*)(char *)) prom_exit;
126 _machine_halt = prom_halt;
127
128#ifdef CONFIG_32BIT
129 /* copy command line */
130 strcpy(arcs_cmdline, prom_argv[1]);
131 memsize = simple_strtol(prom_getenv("memsize"), NULL, 16);
132 strcpy(modetty, prom_getenv("modetty0"));
133#endif /* CONFIG_32BIT */
134
135#ifdef CONFIG_64BIT
136# error 64 bit support not implemented
137#endif /* CONFIG_64BIT */
138}
139
140/* This is called from free_initmem(), so we need to provide it */
141void __init prom_free_prom_memory(void)
142{
143 /* Nothing to do */
144}
diff --git a/arch/mips/basler/excite/excite_setup.c b/arch/mips/basler/excite/excite_setup.c
deleted file mode 100644
index d66b3b8edf2a..000000000000
--- a/arch/mips/basler/excite/excite_setup.c
+++ /dev/null
@@ -1,302 +0,0 @@
1/*
2 * Copyright (C) 2004, 2005 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 * Based on the PMC-Sierra Yosemite board support by Ralf Baechle and
5 * Manish Lachwani.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/types.h>
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/string.h>
26#include <linux/tty.h>
27#include <linux/serial_core.h>
28#include <linux/serial.h>
29#include <linux/serial_8250.h>
30#include <linux/ioport.h>
31#include <linux/spinlock.h>
32#include <asm/bootinfo.h>
33#include <asm/mipsregs.h>
34#include <asm/pgtable-32.h>
35#include <asm/io.h>
36#include <asm/time.h>
37#include <asm/rm9k-ocd.h>
38
39#include <excite.h>
40
41#define TITAN_UART_CLK 25000000
42
43#if 1
44/* normal serial port assignment */
45#define REGBASE_SER0 0x0208
46#define REGBASE_SER1 0x0238
47#define MASK_SER0 0x1
48#define MASK_SER1 0x2
49#else
50/* serial ports swapped */
51#define REGBASE_SER0 0x0238
52#define REGBASE_SER1 0x0208
53#define MASK_SER0 0x2
54#define MASK_SER1 0x1
55#endif
56
57unsigned long memsize;
58char modetty[30];
59unsigned int titan_irq = TITAN_IRQ;
60static void __iomem * ctl_regs;
61u32 unit_id;
62
63volatile void __iomem * const ocd_base = (void *) (EXCITE_ADDR_OCD);
64volatile void __iomem * const titan_base = (void *) (EXCITE_ADDR_TITAN);
65
66/* Protect access to shared GPI registers */
67DEFINE_SPINLOCK(titan_lock);
68int titan_irqflags;
69
70
71/*
72 * The eXcite platform uses the alternate timer interrupt
73 *
74 * Fixme: At the time of this writing cevt-r4k.c doesn't yet know about how
75 * to handle the alternate timer interrupt of the RM9000.
76 */
77void __init plat_time_init(void)
78{
79 const u32 modebit5 = ocd_readl(0x00e4);
80 unsigned int mult = ((modebit5 >> 11) & 0x1f) + 2;
81 unsigned int div = ((modebit5 >> 16) & 0x1f) + 2;
82
83 if (div == 33)
84 div = 1;
85 mips_hpt_frequency = EXCITE_CPU_EXT_CLOCK * mult / div / 2;
86}
87
88static int __init excite_init_console(void)
89{
90#if defined(CONFIG_SERIAL_8250)
91 static __initdata char serr[] =
92 KERN_ERR "Serial port #%u setup failed\n";
93 struct uart_port up;
94
95 /* Take the DUART out of reset */
96 titan_writel(0x00ff1cff, CPRR);
97
98#if (CONFIG_SERIAL_8250_NR_UARTS > 1)
99 /* Enable both ports */
100 titan_writel(MASK_SER0 | MASK_SER1, UACFG);
101#else
102 /* Enable port #0 only */
103 titan_writel(MASK_SER0, UACFG);
104#endif
105
106 /*
107 * Set up serial port #0. Do not use autodetection; the result is
108 * not what we want.
109 */
110 memset(&up, 0, sizeof(up));
111 up.membase = (char *) titan_addr(REGBASE_SER0);
112 up.irq = TITAN_IRQ;
113 up.uartclk = TITAN_UART_CLK;
114 up.regshift = 0;
115 up.iotype = UPIO_RM9000;
116 up.type = PORT_RM9000;
117 up.flags = UPF_SHARE_IRQ;
118 up.line = 0;
119 if (early_serial_setup(&up))
120 printk(serr, up.line);
121
122#if CONFIG_SERIAL_8250_NR_UARTS > 1
123 /* And now for port #1. */
124 up.membase = (char *) titan_addr(REGBASE_SER1);
125 up.line = 1;
126 if (early_serial_setup(&up))
127 printk(serr, up.line);
128#endif /* CONFIG_SERIAL_8250_NR_UARTS > 1 */
129#else
130 /* Leave the DUART in reset */
131 titan_writel(0x00ff3cff, CPRR);
132#endif /* defined(CONFIG_SERIAL_8250) */
133
134 return 0;
135}
136
137static int __init excite_platform_init(void)
138{
139 unsigned int i;
140 unsigned char buf[3];
141 u8 reg;
142 void __iomem * dpr;
143
144 /* BIU buffer allocations */
145 ocd_writel(8, CPURSLMT); /* CPU */
146 titan_writel(4, CPGRWL); /* GPI / Ethernet */
147
148 /* Map control registers located in FPGA */
149 ctl_regs = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_SYSCTL, 16);
150 if (!ctl_regs)
151 panic("eXcite: failed to map platform control registers\n");
152 memcpy_fromio(buf, ctl_regs + 2, ARRAY_SIZE(buf));
153 unit_id = buf[0] | (buf[1] << 8) | (buf[2] << 16);
154
155 /* Clear the reboot flag */
156 dpr = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_DPR, 1);
157 reg = __raw_readb(dpr);
158 __raw_writeb(reg & 0x7f, dpr);
159 iounmap(dpr);
160
161 /* Interrupt controller setup */
162 for (i = INTP0Status0; i < INTP0Status0 + 0x80; i += 0x10) {
163 ocd_writel(0x00000000, i + 0x04);
164 ocd_writel(0xffffffff, i + 0x0c);
165 }
166 ocd_writel(0x2, NMICONFIG);
167
168 ocd_writel(0x1 << (TITAN_MSGINT % 0x20),
169 INTP0Mask0 + (0x10 * (TITAN_MSGINT / 0x20)));
170 ocd_writel((0x1 << (FPGA0_MSGINT % 0x20))
171 | ocd_readl(INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20))),
172 INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20)));
173 ocd_writel((0x1 << (FPGA1_MSGINT % 0x20))
174 | ocd_readl(INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20))),
175 INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20)));
176 ocd_writel((0x1 << (PHY_MSGINT % 0x20))
177 | ocd_readl(INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20))),
178 INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20)));
179#if USB_IRQ < 10
180 ocd_writel((0x1 << (USB_MSGINT % 0x20))
181 | ocd_readl(INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20))),
182 INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20)));
183#endif
184 /* Enable the packet FIFO, XDMA and XDMA arbiter */
185 titan_writel(0x00ff18ff, CPRR);
186
187 /*
188 * Set up the PADMUX. Power down all ethernet slices,
189 * they will be powered up and configured at device startup.
190 */
191 titan_writel(0x00878206, CPTC1R);
192 titan_writel(0x00001100, CPTC0R); /* latch PADMUX, enable WCIMODE */
193
194 /* Reset and enable the FIFO block */
195 titan_writel(0x00000001, SDRXFCIE);
196 titan_writel(0x00000001, SDTXFCIE);
197 titan_writel(0x00000100, SDRXFCIE);
198 titan_writel(0x00000000, SDTXFCIE);
199
200 /*
201 * Initialize the common interrupt shared by all components of
202 * the GPI/Ethernet subsystem.
203 */
204 titan_writel((EXCITE_PHYS_OCD >> 12), CPCFG0);
205 titan_writel(TITAN_MSGINT, CPCFG1);
206
207 /*
208 * XDMA configuration.
209 * In order for the XDMA to be sharable among multiple drivers,
210 * the setup must be done here in the platform. The reason is that
211 * this setup can only be done while the XDMA is in reset. If this
212 * were done in a driver, it would interrupt all other drivers
213 * using the XDMA.
214 */
215 titan_writel(0x80021dff, GXCFG); /* XDMA reset */
216 titan_writel(0x00000000, CPXCISRA);
217 titan_writel(0x00000000, CPXCISRB); /* clear pending interrupts */
218#if defined(CONFIG_HIGHMEM)
219# error change for HIGHMEM support!
220#else
221 titan_writel(0x00000000, GXDMADRPFX); /* buffer address prefix */
222#endif
223 titan_writel(0, GXDMA_DESCADR);
224
225 for (i = 0x5040; i <= 0x5300; i += 0x0040)
226 titan_writel(0x80080000, i); /* reset channel */
227
228 titan_writel((0x1 << 29) /* no sparse tx descr. */
229 | (0x1 << 28) /* no sparse rx descr. */
230 | (0x1 << 23) | (0x1 << 24) /* descriptor coherency */
231 | (0x1 << 21) | (0x1 << 22) /* data coherency */
232 | (0x1 << 17)
233 | 0x1dff,
234 GXCFG);
235
236#if defined(CONFIG_SMP)
237# error No SMP support
238#else
239 /* All interrupts go to core #0 only. */
240 titan_writel(0x1f007fff, CPDST0A);
241 titan_writel(0x00000000, CPDST0B);
242 titan_writel(0x0000ff3f, CPDST1A);
243 titan_writel(0x00000000, CPDST1B);
244 titan_writel(0x00ffffff, CPXDSTA);
245 titan_writel(0x00000000, CPXDSTB);
246#endif
247
248 /* Enable DUART interrupts, disable everything else. */
249 titan_writel(0x04000000, CPGIG0ER);
250 titan_writel(0x000000c0, CPGIG1ER);
251
252 excite_procfs_init();
253 return 0;
254}
255
256void __init plat_mem_setup(void)
257{
258 volatile u32 * const boot_ocd_base = (u32 *) 0xbf7fc000;
259
260 /* Announce RAM to system */
261 add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
262
263 /* Set up the peripheral address map */
264 *(boot_ocd_base + (LKB9 / sizeof(u32))) = 0;
265 *(boot_ocd_base + (LKB10 / sizeof(u32))) = 0;
266 *(boot_ocd_base + (LKB11 / sizeof(u32))) = 0;
267 *(boot_ocd_base + (LKB12 / sizeof(u32))) = 0;
268 wmb();
269 *(boot_ocd_base + (LKB0 / sizeof(u32))) = EXCITE_PHYS_OCD >> 4;
270 wmb();
271
272 ocd_writel((EXCITE_PHYS_TITAN >> 4) | 0x1UL, LKB5);
273 ocd_writel(((EXCITE_SIZE_TITAN >> 4) & 0x7fffff00) - 0x100, LKM5);
274 ocd_writel((EXCITE_PHYS_SCRAM >> 4) | 0x1UL, LKB13);
275 ocd_writel(((EXCITE_SIZE_SCRAM >> 4) & 0xffffff00) - 0x100, LKM13);
276
277 /* Local bus slot #0 */
278 ocd_writel(0x00040510, LDP0);
279 ocd_writel((EXCITE_PHYS_BOOTROM >> 4) | 0x1UL, LKB9);
280 ocd_writel(((EXCITE_SIZE_BOOTROM >> 4) & 0x03ffff00) - 0x100, LKM9);
281
282 /* Local bus slot #2 */
283 ocd_writel(0x00000330, LDP2);
284 ocd_writel((EXCITE_PHYS_FPGA >> 4) | 0x1, LKB11);
285 ocd_writel(((EXCITE_SIZE_FPGA >> 4) - 0x100) & 0x03ffff00, LKM11);
286
287 /* Local bus slot #3 */
288 ocd_writel(0x00123413, LDP3);
289 ocd_writel((EXCITE_PHYS_NAND >> 4) | 0x1, LKB12);
290 ocd_writel(((EXCITE_SIZE_NAND >> 4) - 0x100) & 0x03ffff00, LKM12);
291}
292
293
294
295console_initcall(excite_init_console);
296arch_initcall(excite_platform_init);
297
298EXPORT_SYMBOL(titan_lock);
299EXPORT_SYMBOL(titan_irqflags);
300EXPORT_SYMBOL(titan_irq);
301EXPORT_SYMBOL(ocd_base);
302EXPORT_SYMBOL(titan_base);
diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c
index fb284c3b2cff..c51405e57921 100644
--- a/arch/mips/bcm47xx/prom.c
+++ b/arch/mips/bcm47xx/prom.c
@@ -100,11 +100,11 @@ static __init void prom_init_console(void)
100 100
101static __init void prom_init_cmdline(void) 101static __init void prom_init_cmdline(void)
102{ 102{
103 static char buf[CL_SIZE] __initdata; 103 static char buf[COMMAND_LINE_SIZE] __initdata;
104 104
105 /* Get the kernel command line from CFE */ 105 /* Get the kernel command line from CFE */
106 if (cfe_getenv("LINUX_CMDLINE", buf, CL_SIZE) >= 0) { 106 if (cfe_getenv("LINUX_CMDLINE", buf, COMMAND_LINE_SIZE) >= 0) {
107 buf[CL_SIZE-1] = 0; 107 buf[COMMAND_LINE_SIZE - 1] = 0;
108 strcpy(arcs_cmdline, buf); 108 strcpy(arcs_cmdline, buf);
109 } 109 }
110 110
@@ -112,13 +112,13 @@ static __init void prom_init_cmdline(void)
112 * as CFE is not available anymore later in the boot process. */ 112 * as CFE is not available anymore later in the boot process. */
113 if ((strstr(arcs_cmdline, "console=")) == NULL) { 113 if ((strstr(arcs_cmdline, "console=")) == NULL) {
114 /* Try to read the default serial port used by CFE */ 114 /* Try to read the default serial port used by CFE */
115 if ((cfe_getenv("BOOT_CONSOLE", buf, CL_SIZE) < 0) 115 if ((cfe_getenv("BOOT_CONSOLE", buf, COMMAND_LINE_SIZE) < 0)
116 || (strncmp("uart", buf, 4))) 116 || (strncmp("uart", buf, 4)))
117 /* Default to uart0 */ 117 /* Default to uart0 */
118 strcpy(buf, "uart0"); 118 strcpy(buf, "uart0");
119 119
120 /* Compute the new command line */ 120 /* Compute the new command line */
121 snprintf(arcs_cmdline, CL_SIZE, "%s console=ttyS%c,115200", 121 snprintf(arcs_cmdline, COMMAND_LINE_SIZE, "%s console=ttyS%c,115200",
122 arcs_cmdline, buf[4]); 122 arcs_cmdline, buf[4]);
123 } 123 }
124} 124}
diff --git a/arch/mips/boot/Makefile b/arch/mips/boot/Makefile
index 2a209d74f0b4..094bc84765a3 100644
--- a/arch/mips/boot/Makefile
+++ b/arch/mips/boot/Makefile
@@ -25,7 +25,7 @@ strip-flags = $(addprefix --remove-section=,$(drop-sections))
25 25
26VMLINUX = vmlinux 26VMLINUX = vmlinux
27 27
28all: vmlinux.ecoff vmlinux.srec addinitrd 28all: vmlinux.ecoff vmlinux.srec
29 29
30vmlinux.ecoff: $(obj)/elf2ecoff $(VMLINUX) 30vmlinux.ecoff: $(obj)/elf2ecoff $(VMLINUX)
31 $(obj)/elf2ecoff $(VMLINUX) vmlinux.ecoff $(E2EFLAGS) 31 $(obj)/elf2ecoff $(VMLINUX) vmlinux.ecoff $(E2EFLAGS)
@@ -39,11 +39,7 @@ vmlinux.bin: $(VMLINUX)
39vmlinux.srec: $(VMLINUX) 39vmlinux.srec: $(VMLINUX)
40 $(OBJCOPY) -S -O srec $(strip-flags) $(VMLINUX) $(obj)/vmlinux.srec 40 $(OBJCOPY) -S -O srec $(strip-flags) $(VMLINUX) $(obj)/vmlinux.srec
41 41
42$(obj)/addinitrd: $(obj)/addinitrd.c 42clean-files += elf2ecoff \
43 $(HOSTCC) -o $@ $^
44
45clean-files += addinitrd \
46 elf2ecoff \
47 vmlinux.bin \ 43 vmlinux.bin \
48 vmlinux.ecoff \ 44 vmlinux.ecoff \
49 vmlinux.srec 45 vmlinux.srec
diff --git a/arch/mips/boot/addinitrd.c b/arch/mips/boot/addinitrd.c
deleted file mode 100644
index b5b3febc10cc..000000000000
--- a/arch/mips/boot/addinitrd.c
+++ /dev/null
@@ -1,131 +0,0 @@
1/*
2 * addinitrd - program to add a initrd image to an ecoff kernel
3 *
4 * (C) 1999 Thomas Bogendoerfer
5 * minor modifications, cleanup: Guido Guenther <agx@sigxcpu.org>
6 * further cleanup: Maciej W. Rozycki
7 */
8
9#include <sys/types.h>
10#include <sys/stat.h>
11#include <fcntl.h>
12#include <unistd.h>
13#include <stdio.h>
14#include <netinet/in.h>
15
16#include "ecoff.h"
17
18#define MIPS_PAGE_SIZE 4096
19#define MIPS_PAGE_MASK (MIPS_PAGE_SIZE-1)
20
21#define swab16(x) \
22 ((unsigned short)( \
23 (((unsigned short)(x) & (unsigned short)0x00ffU) << 8) | \
24 (((unsigned short)(x) & (unsigned short)0xff00U) >> 8) ))
25
26#define swab32(x) \
27 ((unsigned int)( \
28 (((unsigned int)(x) & (unsigned int)0x000000ffUL) << 24) | \
29 (((unsigned int)(x) & (unsigned int)0x0000ff00UL) << 8) | \
30 (((unsigned int)(x) & (unsigned int)0x00ff0000UL) >> 8) | \
31 (((unsigned int)(x) & (unsigned int)0xff000000UL) >> 24) ))
32
33#define SWAB(a) (swab ? swab32(a) : (a))
34
35void die(char *s)
36{
37 perror(s);
38 exit(1);
39}
40
41int main(int argc, char *argv[])
42{
43 int fd_vmlinux, fd_initrd, fd_outfile;
44 FILHDR efile;
45 AOUTHDR eaout;
46 SCNHDR esecs[3];
47 struct stat st;
48 char buf[1024];
49 unsigned long loadaddr;
50 unsigned long initrd_header[2];
51 int i, cnt;
52 int swab = 0;
53
54 if (argc != 4) {
55 printf("Usage: %s <vmlinux> <initrd> <outfile>\n", argv[0]);
56 exit(1);
57 }
58
59 if ((fd_vmlinux = open (argv[1], O_RDONLY)) < 0)
60 die("open vmlinux");
61 if (read (fd_vmlinux, &efile, sizeof efile) != sizeof efile)
62 die("read file header");
63 if (read (fd_vmlinux, &eaout, sizeof eaout) != sizeof eaout)
64 die("read aout header");
65 if (read (fd_vmlinux, esecs, sizeof esecs) != sizeof esecs)
66 die("read section headers");
67 /*
68 * check whether the file is good for us
69 */
70 /* TBD */
71
72 /*
73 * check, if we have to swab words
74 */
75 if (ntohs(0xaa55) == 0xaa55) {
76 if (efile.f_magic == swab16(MIPSELMAGIC))
77 swab = 1;
78 } else {
79 if (efile.f_magic == swab16(MIPSEBMAGIC))
80 swab = 1;
81 }
82
83 /* make sure we have an empty data segment for the initrd */
84 if (eaout.dsize || esecs[1].s_size) {
85 fprintf(stderr, "Data segment not empty. Giving up!\n");
86 exit(1);
87 }
88 if ((fd_initrd = open (argv[2], O_RDONLY)) < 0)
89 die("open initrd");
90 if (fstat (fd_initrd, &st) < 0)
91 die("fstat initrd");
92 loadaddr = ((SWAB(esecs[2].s_vaddr) + SWAB(esecs[2].s_size)
93 + MIPS_PAGE_SIZE-1) & ~MIPS_PAGE_MASK) - 8;
94 if (loadaddr < (SWAB(esecs[2].s_vaddr) + SWAB(esecs[2].s_size)))
95 loadaddr += MIPS_PAGE_SIZE;
96 initrd_header[0] = SWAB(0x494E5244);
97 initrd_header[1] = SWAB(st.st_size);
98 eaout.dsize = esecs[1].s_size = initrd_header[1] = SWAB(st.st_size+8);
99 eaout.data_start = esecs[1].s_vaddr = esecs[1].s_paddr = SWAB(loadaddr);
100
101 if ((fd_outfile = open (argv[3], O_RDWR|O_CREAT|O_TRUNC, 0666)) < 0)
102 die("open outfile");
103 if (write (fd_outfile, &efile, sizeof efile) != sizeof efile)
104 die("write file header");
105 if (write (fd_outfile, &eaout, sizeof eaout) != sizeof eaout)
106 die("write aout header");
107 if (write (fd_outfile, esecs, sizeof esecs) != sizeof esecs)
108 die("write section headers");
109 /* skip padding */
110 if(lseek(fd_vmlinux, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1)
111 die("lseek vmlinux");
112 if(lseek(fd_outfile, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1)
113 die("lseek outfile");
114 /* copy text segment */
115 cnt = SWAB(eaout.tsize);
116 while (cnt) {
117 if ((i = read (fd_vmlinux, buf, sizeof buf)) <= 0)
118 die("read vmlinux");
119 if (write (fd_outfile, buf, i) != i)
120 die("write vmlinux");
121 cnt -= i;
122 }
123 if (write (fd_outfile, initrd_header, sizeof initrd_header) != sizeof initrd_header)
124 die("write initrd header");
125 while ((i = read (fd_initrd, buf, sizeof buf)) > 0)
126 if (write (fd_outfile, buf, i) != i)
127 die("write initrd");
128 close(fd_vmlinux);
129 close(fd_initrd);
130 return 0;
131}
diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile
new file mode 100644
index 000000000000..e27f40bbd4e5
--- /dev/null
+++ b/arch/mips/boot/compressed/Makefile
@@ -0,0 +1,100 @@
1#
2# This file is subject to the terms and conditions of the GNU General Public
3# License.
4#
5# Adapted for MIPS Pete Popov, Dan Malek
6#
7# Copyright (C) 1994 by Linus Torvalds
8# Adapted for PowerPC by Gary Thomas
9# modified by Cort (cort@cs.nmt.edu)
10#
11# Copyright (C) 2009 Lemote Inc. & DSLab, Lanzhou University
12# Author: Wu Zhangjin <wuzj@lemote.com>
13#
14
15# compressed kernel load addr: VMLINUZ_LOAD_ADDRESS > VMLINUX_LOAD_ADDRESS + VMLINUX_SIZE
16VMLINUX_SIZE := $(shell wc -c $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | cut -d' ' -f1)
17VMLINUX_SIZE := $(shell [ -n "$(VMLINUX_SIZE)" ] && echo $$(($(VMLINUX_SIZE) + (65536 - $(VMLINUX_SIZE) % 65536))))
18VMLINUZ_LOAD_ADDRESS := 0x$(shell [ -n "$(VMLINUX_SIZE)" ] && printf %x $$(($(VMLINUX_LOAD_ADDRESS) + $(VMLINUX_SIZE))))
19
20# set the default size of the mallocing area for decompressing
21BOOT_HEAP_SIZE := 0x400000
22
23# Disable Function Tracer
24KBUILD_CFLAGS := $(shell echo $(KBUILD_CFLAGS) | sed -e "s/-pg//")
25
26KBUILD_CFLAGS := $(LINUXINCLUDE) $(KBUILD_CFLAGS) -D__KERNEL__ \
27 -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) -D"VMLINUX_LOAD_ADDRESS_ULL=$(VMLINUX_LOAD_ADDRESS)ull" \
28
29KBUILD_AFLAGS := $(LINUXINCLUDE) $(KBUILD_AFLAGS) -D__ASSEMBLY__ \
30 -DKERNEL_ENTRY=0x$(shell $(NM) $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | grep " kernel_entry" | cut -f1 -d \ ) \
31 -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE)
32
33obj-y := $(obj)/head.o $(obj)/decompress.o $(obj)/dbg.o
34
35obj-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o
36
37OBJCOPYFLAGS_vmlinux.bin := $(OBJCOPYFLAGS) -O binary -R .comment -S
38$(obj)/vmlinux.bin: $(KBUILD_IMAGE)
39 $(call if_changed,objcopy)
40
41suffix_$(CONFIG_KERNEL_GZIP) = gz
42suffix_$(CONFIG_KERNEL_BZIP2) = bz2
43suffix_$(CONFIG_KERNEL_LZMA) = lzma
44tool_$(CONFIG_KERNEL_GZIP) = gzip
45tool_$(CONFIG_KERNEL_BZIP2) = bzip2
46tool_$(CONFIG_KERNEL_LZMA) = lzma
47$(obj)/vmlinux.$(suffix_y): $(obj)/vmlinux.bin
48 $(call if_changed,$(tool_y))
49
50$(obj)/piggy.o: $(obj)/vmlinux.$(suffix_y) $(obj)/dummy.o
51 $(Q)$(OBJCOPY) $(OBJCOPYFLAGS) \
52 --add-section=.image=$< \
53 --set-section-flags=.image=contents,alloc,load,readonly,data \
54 $(obj)/dummy.o $@
55
56LDFLAGS_vmlinuz := $(LDFLAGS) -Ttext $(VMLINUZ_LOAD_ADDRESS) -T
57vmlinuz: $(src)/ld.script $(obj-y) $(obj)/piggy.o
58 $(call if_changed,ld)
59 $(Q)$(OBJCOPY) $(OBJCOPYFLAGS) -R .comment -R .stab -R .stabstr -R .initrd -R .sysmap $@
60
61#
62# Some DECstations need all possible sections of an ECOFF executable
63#
64ifdef CONFIG_MACH_DECSTATION
65 E2EFLAGS = -a
66else
67 E2EFLAGS =
68endif
69
70# elf2ecoff can only handle 32bit image
71
72ifdef CONFIG_32BIT
73 VMLINUZ = vmlinuz
74else
75 VMLINUZ = vmlinuz.32
76endif
77
78vmlinuz.32: vmlinuz
79 $(Q)$(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@
80
81vmlinuz.ecoff: $(obj)/../elf2ecoff $(VMLINUZ)
82 $(Q)$(obj)/../elf2ecoff $(VMLINUZ) vmlinuz.ecoff $(E2EFLAGS)
83
84$(obj)/../elf2ecoff: $(src)/../elf2ecoff.c
85 $(Q)$(HOSTCC) -o $@ $^
86
87drop-sections = .reginfo .mdebug .comment .note .pdr .options .MIPS.options
88strip-flags = $(addprefix --remove-section=,$(drop-sections))
89
90OBJCOPYFLAGS_vmlinuz.bin := $(OBJCOPYFLAGS) -O binary $(strip-flags)
91vmlinuz.bin: vmlinuz
92 $(call if_changed,objcopy)
93
94OBJCOPYFLAGS_vmlinuz.srec := $(OBJCOPYFLAGS) -S -O srec $(strip-flags)
95vmlinuz.srec: vmlinuz
96 $(call if_changed,objcopy)
97
98clean:
99clean-files += *.o \
100 vmlinu*
diff --git a/arch/mips/boot/compressed/dbg.c b/arch/mips/boot/compressed/dbg.c
new file mode 100644
index 000000000000..ff4dc7a33a9f
--- /dev/null
+++ b/arch/mips/boot/compressed/dbg.c
@@ -0,0 +1,37 @@
1/*
2 * MIPS-specific debug support for pre-boot environment
3 *
4 * NOTE: putc() is board specific, if your board have a 16550 compatible uart,
5 * please select SYS_SUPPORTS_ZBOOT_UART16550 for your machine. othewise, you
6 * need to implement your own putc().
7 */
8
9#include <linux/init.h>
10#include <linux/types.h>
11
12void __attribute__ ((weak)) putc(char c)
13{
14}
15
16void puts(const char *s)
17{
18 char c;
19 while ((c = *s++) != '\0') {
20 putc(c);
21 if (c == '\n')
22 putc('\r');
23 }
24}
25
26void puthex(unsigned long long val)
27{
28
29 unsigned char buf[10];
30 int i;
31 for (i = 7; i >= 0; i--) {
32 buf[i] = "0123456789ABCDEF"[val & 0x0F];
33 val >>= 4;
34 }
35 buf[8] = '\0';
36 puts(buf);
37}
diff --git a/arch/mips/boot/compressed/decompress.c b/arch/mips/boot/compressed/decompress.c
new file mode 100644
index 000000000000..67330c2f7318
--- /dev/null
+++ b/arch/mips/boot/compressed/decompress.c
@@ -0,0 +1,126 @@
1/*
2 * Misc. bootloader code for many machines.
3 *
4 * Copyright 2001 MontaVista Software Inc.
5 * Author: Matt Porter <mporter@mvista.com> Derived from
6 * arch/ppc/boot/prep/misc.c
7 *
8 * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology
9 * Author: Wu Zhangjin <wuzj@lemote.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17#include <linux/types.h>
18#include <linux/kernel.h>
19
20#include <asm/addrspace.h>
21
22/* These two variables specify the free mem region
23 * that can be used for temporary malloc area
24 */
25unsigned long free_mem_ptr;
26unsigned long free_mem_end_ptr;
27char *zimage_start;
28
29/* The linker tells us where the image is. */
30extern unsigned char __image_begin, __image_end;
31extern unsigned char __ramdisk_begin, __ramdisk_end;
32unsigned long initrd_size;
33
34/* debug interfaces */
35extern void puts(const char *s);
36extern void puthex(unsigned long long val);
37
38void error(char *x)
39{
40 puts("\n\n");
41 puts(x);
42 puts("\n\n -- System halted");
43
44 while (1)
45 ; /* Halt */
46}
47
48/* activate the code for pre-boot environment */
49#define STATIC static
50
51#ifdef CONFIG_KERNEL_GZIP
52void *memcpy(void *dest, const void *src, size_t n)
53{
54 int i;
55 const char *s = src;
56 char *d = dest;
57
58 for (i = 0; i < n; i++)
59 d[i] = s[i];
60 return dest;
61}
62#include "../../../../lib/decompress_inflate.c"
63#endif
64
65#ifdef CONFIG_KERNEL_BZIP2
66void *memset(void *s, int c, size_t n)
67{
68 int i;
69 char *ss = s;
70
71 for (i = 0; i < n; i++)
72 ss[i] = c;
73 return s;
74}
75#include "../../../../lib/decompress_bunzip2.c"
76#endif
77
78#ifdef CONFIG_KERNEL_LZMA
79#include "../../../../lib/decompress_unlzma.c"
80#endif
81
82void decompress_kernel(unsigned long boot_heap_start)
83{
84 int zimage_size;
85
86 /*
87 * We link ourself to an arbitrary low address. When we run, we
88 * relocate outself to that address. __image_beign points to
89 * the part of the image where the zImage is. -- Tom
90 */
91 zimage_start = (char *)(unsigned long)(&__image_begin);
92 zimage_size = (unsigned long)(&__image_end) -
93 (unsigned long)(&__image_begin);
94
95 /*
96 * The zImage and initrd will be between start and _end, so they've
97 * already been moved once. We're good to go now. -- Tom
98 */
99 puts("zimage at: ");
100 puthex((unsigned long)zimage_start);
101 puts(" ");
102 puthex((unsigned long)(zimage_size + zimage_start));
103 puts("\n");
104
105 if (initrd_size) {
106 puts("initrd at: ");
107 puthex((unsigned long)(&__ramdisk_begin));
108 puts(" ");
109 puthex((unsigned long)(&__ramdisk_end));
110 puts("\n");
111 }
112
113 /* this area are prepared for mallocing when decompressing */
114 free_mem_ptr = boot_heap_start;
115 free_mem_end_ptr = boot_heap_start + BOOT_HEAP_SIZE;
116
117 /* Display standard Linux/MIPS boot prompt for kernel args */
118 puts("Uncompressing Linux at load address ");
119 puthex(VMLINUX_LOAD_ADDRESS_ULL);
120 puts("\n");
121 /* Decompress the kernel with according algorithm */
122 decompress(zimage_start, zimage_size, 0, 0,
123 (void *)VMLINUX_LOAD_ADDRESS_ULL, 0, error);
124 /* FIXME: is there a need to flush cache here? */
125 puts("Now, booting the kernel...\n");
126}
diff --git a/arch/mips/boot/compressed/dummy.c b/arch/mips/boot/compressed/dummy.c
new file mode 100644
index 000000000000..31dbf45bf99c
--- /dev/null
+++ b/arch/mips/boot/compressed/dummy.c
@@ -0,0 +1,4 @@
1int main(void)
2{
3 return 0;
4}
diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/head.S
new file mode 100644
index 000000000000..4e65a8420bee
--- /dev/null
+++ b/arch/mips/boot/compressed/head.S
@@ -0,0 +1,56 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995 Waldorf Electronics
7 * Written by Ralf Baechle and Andreas Busse
8 * Copyright (C) 1995 - 1999 Ralf Baechle
9 * Copyright (C) 1996 Paul M. Antoine
10 * Modified for DECStation and hence R3000 support by Paul M. Antoine
11 * Further modifications by David S. Miller and Harald Koerfgen
12 * Copyright (C) 1999 Silicon Graphics, Inc.
13 */
14
15#include <asm/asm.h>
16#include <asm/regdef.h>
17
18 .set noreorder
19 .cprestore
20 LEAF(start)
21start:
22 /* Save boot rom start args */
23 move s0, a0
24 move s1, a1
25 move s2, a2
26 move s3, a3
27
28 /* Clear BSS */
29 PTR_LA a0, _edata
30 PTR_LA a2, _end
311: sw zero, 0(a0)
32 bne a2, a0, 1b
33 addiu a0, a0, 4
34
35 PTR_LA a0, (.heap) /* heap address */
36 PTR_LA sp, (.stack + 8192) /* stack address */
37
38 PTR_LA ra, 2f
39 PTR_LA k0, decompress_kernel
40 jr k0
41 nop
422:
43 move a0, s0
44 move a1, s1
45 move a2, s2
46 move a3, s3
47 PTR_LI k0, KERNEL_ENTRY
48 jr k0
49 nop
503:
51 b 3b
52 nop
53 END(start)
54
55 .comm .heap,BOOT_HEAP_SIZE,4
56 .comm .stack,4096*2,4
diff --git a/arch/mips/boot/compressed/ld.script b/arch/mips/boot/compressed/ld.script
new file mode 100644
index 000000000000..29e9f4c0d5d8
--- /dev/null
+++ b/arch/mips/boot/compressed/ld.script
@@ -0,0 +1,150 @@
1OUTPUT_ARCH(mips)
2ENTRY(start)
3SECTIONS
4{
5 /* Read-only sections, merged into text segment: */
6 .init : { *(.init) } =0
7 .text :
8 {
9 _ftext = . ;
10 *(.text)
11 *(.rodata)
12 *(.rodata1)
13 /* .gnu.warning sections are handled specially by elf32.em. */
14 *(.gnu.warning)
15 } =0
16 .kstrtab : { *(.kstrtab) }
17
18 . = ALIGN(16); /* Exception table */
19 __start___ex_table = .;
20 __ex_table : { *(__ex_table) }
21 __stop___ex_table = .;
22
23 __start___dbe_table = .; /* Exception table for data bus errors */
24 __dbe_table : { *(__dbe_table) }
25 __stop___dbe_table = .;
26
27 __start___ksymtab = .; /* Kernel symbol table */
28 __ksymtab : { *(__ksymtab) }
29 __stop___ksymtab = .;
30
31 _etext = .;
32
33 . = ALIGN(8192);
34 .data.init_task : { *(.data.init_task) }
35
36 /* Startup code */
37 . = ALIGN(4096);
38 __init_begin = .;
39 .text.init : { *(.text.init) }
40 .data.init : { *(.data.init) }
41 . = ALIGN(16);
42 __setup_start = .;
43 .setup.init : { *(.setup.init) }
44 __setup_end = .;
45 __initcall_start = .;
46 .initcall.init : { *(.initcall.init) }
47 __initcall_end = .;
48 . = ALIGN(4096); /* Align double page for init_task_union */
49 __init_end = .;
50
51 . = ALIGN(4096);
52 .data.page_aligned : { *(.data.idt) }
53
54 . = ALIGN(32);
55 .data.cacheline_aligned : { *(.data.cacheline_aligned) }
56
57 .fini : { *(.fini) } =0
58 .reginfo : { *(.reginfo) }
59 /* Adjust the address for the data segment. We want to adjust up to
60 the same address within the page on the next page up. It would
61 be more correct to do this:
62 . = .;
63 The current expression does not correctly handle the case of a
64 text segment ending precisely at the end of a page; it causes the
65 data segment to skip a page. The above expression does not have
66 this problem, but it will currently (2/95) cause BFD to allocate
67 a single segment, combining both text and data, for this case.
68 This will prevent the text segment from being shared among
69 multiple executions of the program; I think that is more
70 important than losing a page of the virtual address space (note
71 that no actual memory is lost; the page which is skipped can not
72 be referenced). */
73 . = .;
74 .data :
75 {
76 _fdata = . ;
77 *(.data)
78
79 /* Put the compressed image here, so bss is on the end. */
80 __image_begin = .;
81 *(.image)
82 __image_end = .;
83 /* Align the initial ramdisk image (INITRD) on page boundaries. */
84 . = ALIGN(4096);
85 __ramdisk_begin = .;
86 *(.initrd)
87 __ramdisk_end = .;
88 . = ALIGN(4096);
89
90 CONSTRUCTORS
91 }
92 .data1 : { *(.data1) }
93 _gp = . + 0x8000;
94 .lit8 : { *(.lit8) }
95 .lit4 : { *(.lit4) }
96 .ctors : { *(.ctors) }
97 .dtors : { *(.dtors) }
98 .got : { *(.got.plt) *(.got) }
99 .dynamic : { *(.dynamic) }
100 /* We want the small data sections together, so single-instruction offsets
101 can access them all, and initialized data all before uninitialized, so
102 we can shorten the on-disk segment size. */
103 .sdata : { *(.sdata) }
104 . = ALIGN(4);
105 _edata = .;
106 PROVIDE (edata = .);
107
108 __bss_start = .;
109 _fbss = .;
110 .sbss : { *(.sbss) *(.scommon) }
111 .bss :
112 {
113 *(.dynbss)
114 *(.bss)
115 *(COMMON)
116 . = ALIGN(4);
117 _end = . ;
118 PROVIDE (end = .);
119 }
120
121 /* Sections to be discarded */
122 /DISCARD/ :
123 {
124 *(.text.exit)
125 *(.data.exit)
126 *(.exitcall.exit)
127 }
128
129 /* This is the MIPS specific mdebug section. */
130 .mdebug : { *(.mdebug) }
131 /* These are needed for ELF backends which have not yet been
132 converted to the new style linker. */
133 .stab 0 : { *(.stab) }
134 .stabstr 0 : { *(.stabstr) }
135 /* DWARF debug sections.
136 Symbols in the .debug DWARF section are relative to the beginning of the
137 section so we begin .debug at 0. It's not clear yet what needs to happen
138 for the others. */
139 .debug 0 : { *(.debug) }
140 .debug_srcinfo 0 : { *(.debug_srcinfo) }
141 .debug_aranges 0 : { *(.debug_aranges) }
142 .debug_pubnames 0 : { *(.debug_pubnames) }
143 .debug_sfnames 0 : { *(.debug_sfnames) }
144 .line 0 : { *(.line) }
145 /* These must appear regardless of . */
146 .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
147 .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
148 .comment : { *(.comment) }
149 .note : { *(.note) }
150}
diff --git a/arch/mips/boot/compressed/uart-16550.c b/arch/mips/boot/compressed/uart-16550.c
new file mode 100644
index 000000000000..c9caaf4fbf60
--- /dev/null
+++ b/arch/mips/boot/compressed/uart-16550.c
@@ -0,0 +1,43 @@
1/*
2 * 16550 compatible uart based serial debug support for zboot
3 */
4
5#include <linux/types.h>
6#include <linux/serial_reg.h>
7#include <linux/init.h>
8
9#include <asm/addrspace.h>
10
11#if defined(CONFIG_MACH_LOONGSON) || defined(CONFIG_MIPS_MALTA)
12#define UART_BASE 0x1fd003f8
13#define PORT(offset) (CKSEG1ADDR(UART_BASE) + (offset))
14#endif
15
16#ifdef CONFIG_AR7
17#include <ar7.h>
18#define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset))
19#endif
20
21#ifndef PORT
22#error please define the serial port address for your own machine
23#endif
24
25static inline unsigned int serial_in(int offset)
26{
27 return *((char *)PORT(offset));
28}
29
30static inline void serial_out(int offset, int value)
31{
32 *((char *)PORT(offset)) = value;
33}
34
35void putc(char c)
36{
37 int timeout = 1024;
38
39 while (((serial_in(UART_LSR) & UART_LSR_THRE) == 0) && (timeout-- > 0))
40 ;
41
42 serial_out(UART_TX, c);
43}
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 139436280520..3e9876317e61 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -9,7 +9,7 @@
9# Copyright (C) 2005-2009 Cavium Networks 9# Copyright (C) 2005-2009 Cavium Networks
10# 10#
11 11
12obj-y := setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o 12obj-y := cpu.o setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o
13obj-y += dma-octeon.o flash_setup.o 13obj-y += dma-octeon.o flash_setup.o
14obj-y += octeon-memcpy.o 14obj-y += octeon-memcpy.o
15 15
diff --git a/arch/mips/cavium-octeon/cpu.c b/arch/mips/cavium-octeon/cpu.c
new file mode 100644
index 000000000000..b6df5387e855
--- /dev/null
+++ b/arch/mips/cavium-octeon/cpu.c
@@ -0,0 +1,52 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2009 Wind River Systems,
7 * written by Ralf Baechle <ralf@linux-mips.org>
8 */
9#include <linux/init.h>
10#include <linux/irqflags.h>
11#include <linux/notifier.h>
12#include <linux/prefetch.h>
13#include <linux/sched.h>
14
15#include <asm/cop2.h>
16#include <asm/current.h>
17#include <asm/mipsregs.h>
18#include <asm/page.h>
19#include <asm/octeon/octeon.h>
20
21static int cnmips_cu2_call(struct notifier_block *nfb, unsigned long action,
22 void *data)
23{
24 unsigned long flags;
25 unsigned int status;
26
27 switch (action) {
28 case CU2_EXCEPTION:
29 prefetch(&current->thread.cp2);
30 local_irq_save(flags);
31 KSTK_STATUS(current) |= ST0_CU2;
32 status = read_c0_status();
33 write_c0_status(status | ST0_CU2);
34 octeon_cop2_restore(&(current->thread.cp2));
35 write_c0_status(status & ~ST0_CU2);
36 local_irq_restore(flags);
37
38 return NOTIFY_BAD; /* Don't call default notifier */
39 }
40
41 return NOTIFY_OK; /* Let default notifier send signals */
42}
43
44static struct notifier_block cnmips_cu2_notifier = {
45 .notifier_call = cnmips_cu2_call,
46};
47
48static int cnmips_cu2_setup(void)
49{
50 return register_cu2_notifier(&cnmips_cu2_notifier);
51}
52early_initcall(cnmips_cu2_setup);
diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c
index be711dd2d918..cfdb4c2ac5c3 100644
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -159,6 +159,94 @@ out:
159} 159}
160device_initcall(octeon_rng_device_init); 160device_initcall(octeon_rng_device_init);
161 161
162/* Octeon SMI/MDIO interface. */
163static int __init octeon_mdiobus_device_init(void)
164{
165 struct platform_device *pd;
166 int ret = 0;
167
168 if (octeon_is_simulation())
169 return 0; /* No mdio in the simulator. */
170
171 /* The bus number is the platform_device id. */
172 pd = platform_device_alloc("mdio-octeon", 0);
173 if (!pd) {
174 ret = -ENOMEM;
175 goto out;
176 }
177
178 ret = platform_device_add(pd);
179 if (ret)
180 goto fail;
181
182 return ret;
183fail:
184 platform_device_put(pd);
185
186out:
187 return ret;
188
189}
190device_initcall(octeon_mdiobus_device_init);
191
192/* Octeon mgmt port Ethernet interface. */
193static int __init octeon_mgmt_device_init(void)
194{
195 struct platform_device *pd;
196 int ret = 0;
197 int port, num_ports;
198
199 struct resource mgmt_port_resource = {
200 .flags = IORESOURCE_IRQ,
201 .start = -1,
202 .end = -1
203 };
204
205 if (!OCTEON_IS_MODEL(OCTEON_CN56XX) && !OCTEON_IS_MODEL(OCTEON_CN52XX))
206 return 0;
207
208 if (OCTEON_IS_MODEL(OCTEON_CN56XX))
209 num_ports = 1;
210 else
211 num_ports = 2;
212
213 for (port = 0; port < num_ports; port++) {
214 pd = platform_device_alloc("octeon_mgmt", port);
215 if (!pd) {
216 ret = -ENOMEM;
217 goto out;
218 }
219 switch (port) {
220 case 0:
221 mgmt_port_resource.start = OCTEON_IRQ_MII0;
222 break;
223 case 1:
224 mgmt_port_resource.start = OCTEON_IRQ_MII1;
225 break;
226 default:
227 BUG();
228 }
229 mgmt_port_resource.end = mgmt_port_resource.start;
230
231 ret = platform_device_add_resources(pd, &mgmt_port_resource, 1);
232
233 if (ret)
234 goto fail;
235
236 ret = platform_device_add(pd);
237 if (ret)
238 goto fail;
239 }
240 return ret;
241fail:
242 platform_device_put(pd);
243
244out:
245 return ret;
246
247}
248device_initcall(octeon_mgmt_device_init);
249
162MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>"); 250MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
163MODULE_LICENSE("GPL"); 251MODULE_LICENSE("GPL");
164MODULE_DESCRIPTION("Platform driver for Octeon SOC"); 252MODULE_DESCRIPTION("Platform driver for Octeon SOC");
diff --git a/arch/mips/configs/ar7_defconfig b/arch/mips/configs/ar7_defconfig
index 35648302f7cc..5a5b6ba7514e 100644
--- a/arch/mips/configs/ar7_defconfig
+++ b/arch/mips/configs/ar7_defconfig
@@ -10,7 +10,6 @@ CONFIG_MIPS=y
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12CONFIG_AR7=y 12CONFIG_AR7=y
13# CONFIG_BASLER_EXCITE is not set
14# CONFIG_BCM47XX is not set 13# CONFIG_BCM47XX is not set
15# CONFIG_MIPS_COBALT is not set 14# CONFIG_MIPS_COBALT is not set
16# CONFIG_MACH_DECSTATION is not set 15# CONFIG_MACH_DECSTATION is not set
@@ -265,7 +264,6 @@ CONFIG_DEFAULT_DEADLINE=y
265# CONFIG_DEFAULT_CFQ is not set 264# CONFIG_DEFAULT_CFQ is not set
266# CONFIG_DEFAULT_NOOP is not set 265# CONFIG_DEFAULT_NOOP is not set
267CONFIG_DEFAULT_IOSCHED="deadline" 266CONFIG_DEFAULT_IOSCHED="deadline"
268CONFIG_PROBE_INITRD_HEADER=y
269# CONFIG_FREEZER is not set 267# CONFIG_FREEZER is not set
270 268
271# 269#
@@ -1053,7 +1051,9 @@ CONFIG_TRACING_SUPPORT=y
1053# CONFIG_DYNAMIC_DEBUG is not set 1051# CONFIG_DYNAMIC_DEBUG is not set
1054# CONFIG_SAMPLES is not set 1052# CONFIG_SAMPLES is not set
1055CONFIG_HAVE_ARCH_KGDB=y 1053CONFIG_HAVE_ARCH_KGDB=y
1054CONFIG_CMDLINE_BOOL=y
1056CONFIG_CMDLINE="rootfstype=squashfs,jffs2" 1055CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
1056# CONFIG_CMDLINE_OVERRIDE is not set
1057 1057
1058# 1058#
1059# Security options 1059# Security options
diff --git a/arch/mips/configs/bcm47xx_defconfig b/arch/mips/configs/bcm47xx_defconfig
index 94b7d57f906d..267bd46120bc 100644
--- a/arch/mips/configs/bcm47xx_defconfig
+++ b/arch/mips/configs/bcm47xx_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13CONFIG_BCM47XX=y 12CONFIG_BCM47XX=y
14# CONFIG_MIPS_COBALT is not set 13# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set 14# CONFIG_MACH_DECSTATION is not set
@@ -1853,7 +1852,7 @@ CONFIG_DEBUG_FS=y
1853# CONFIG_HEADERS_CHECK is not set 1852# CONFIG_HEADERS_CHECK is not set
1854# CONFIG_DEBUG_KERNEL is not set 1853# CONFIG_DEBUG_KERNEL is not set
1855# CONFIG_SAMPLES is not set 1854# CONFIG_SAMPLES is not set
1856CONFIG_CMDLINE="" 1855# CONFIG_CMDLINE_BOOL is not set
1857 1856
1858# 1857#
1859# Security options 1858# Security options
diff --git a/arch/mips/configs/bcm63xx_defconfig b/arch/mips/configs/bcm63xx_defconfig
index ea00c18d1f7b..7fee0273c829 100644
--- a/arch/mips/configs/bcm63xx_defconfig
+++ b/arch/mips/configs/bcm63xx_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set 12# CONFIG_BCM47XX is not set
14CONFIG_BCM63XX=y 13CONFIG_BCM63XX=y
15# CONFIG_MIPS_COBALT is not set 14# CONFIG_MIPS_COBALT is not set
@@ -942,7 +941,9 @@ CONFIG_TRACING_SUPPORT=y
942# CONFIG_BLK_DEV_IO_TRACE is not set 941# CONFIG_BLK_DEV_IO_TRACE is not set
943# CONFIG_SAMPLES is not set 942# CONFIG_SAMPLES is not set
944CONFIG_HAVE_ARCH_KGDB=y 943CONFIG_HAVE_ARCH_KGDB=y
944CONFIG_CMDLINE_BOOL=y
945CONFIG_CMDLINE="console=ttyS0,115200" 945CONFIG_CMDLINE="console=ttyS0,115200"
946# CONFIG_CMDLINE_OVERRIDE is not set
946 947
947# 948#
948# Security options 949# Security options
diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig
index 13d9eb4736c0..c2f06e38c854 100644
--- a/arch/mips/configs/bigsur_defconfig
+++ b/arch/mips/configs/bigsur_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set 12# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set 13# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set 14# CONFIG_MACH_DECSTATION is not set
@@ -1237,7 +1236,7 @@ CONFIG_DEBUG_MUTEXES=y
1237# CONFIG_BACKTRACE_SELF_TEST is not set 1236# CONFIG_BACKTRACE_SELF_TEST is not set
1238# CONFIG_FAULT_INJECTION is not set 1237# CONFIG_FAULT_INJECTION is not set
1239# CONFIG_SAMPLES is not set 1238# CONFIG_SAMPLES is not set
1240CONFIG_CMDLINE="" 1239# CONFIG_CMDLINE_BOOL is not set
1241# CONFIG_DEBUG_STACK_USAGE is not set 1240# CONFIG_DEBUG_STACK_USAGE is not set
1242# CONFIG_SB1XXX_CORELIS is not set 1241# CONFIG_SB1XXX_CORELIS is not set
1243# CONFIG_RUNTIME_DEBUG is not set 1242# CONFIG_RUNTIME_DEBUG is not set
diff --git a/arch/mips/configs/capcella_defconfig b/arch/mips/configs/capcella_defconfig
index 185df23fd460..72b7e456916e 100644
--- a/arch/mips/configs/capcella_defconfig
+++ b/arch/mips/configs/capcella_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_MIPS_COBALT is not set 12# CONFIG_MIPS_COBALT is not set
14# CONFIG_MACH_DECSTATION is not set 13# CONFIG_MACH_DECSTATION is not set
15# CONFIG_MACH_JAZZ is not set 14# CONFIG_MACH_JAZZ is not set
@@ -783,7 +782,9 @@ CONFIG_ENABLE_MUST_CHECK=y
783# CONFIG_HEADERS_CHECK is not set 782# CONFIG_HEADERS_CHECK is not set
784# CONFIG_DEBUG_KERNEL is not set 783# CONFIG_DEBUG_KERNEL is not set
785CONFIG_CROSSCOMPILE=y 784CONFIG_CROSSCOMPILE=y
785CONFIG_CMDLINE_BOOL=y
786CONFIG_CMDLINE="mem=32M console=ttyVR0,38400" 786CONFIG_CMDLINE="mem=32M console=ttyVR0,38400"
787# CONFIG_CMDLINE_OVERRIDE is not set
787 788
788# 789#
789# Security options 790# Security options
diff --git a/arch/mips/configs/cavium-octeon_defconfig b/arch/mips/configs/cavium-octeon_defconfig
index 7afaa28a3768..c8507bc8e925 100644
--- a/arch/mips/configs/cavium-octeon_defconfig
+++ b/arch/mips/configs/cavium-octeon_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set 12# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set 13# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set 14# CONFIG_MACH_DECSTATION is not set
@@ -269,7 +268,6 @@ CONFIG_DEFAULT_CFQ=y
269# CONFIG_DEFAULT_NOOP is not set 268# CONFIG_DEFAULT_NOOP is not set
270CONFIG_DEFAULT_IOSCHED="cfq" 269CONFIG_DEFAULT_IOSCHED="cfq"
271CONFIG_CLASSIC_RCU=y 270CONFIG_CLASSIC_RCU=y
272# CONFIG_PROBE_INITRD_HEADER is not set
273# CONFIG_FREEZER is not set 271# CONFIG_FREEZER is not set
274 272
275# 273#
@@ -822,7 +820,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y
822# CONFIG_SAMPLES is not set 820# CONFIG_SAMPLES is not set
823CONFIG_HAVE_ARCH_KGDB=y 821CONFIG_HAVE_ARCH_KGDB=y
824# CONFIG_KGDB is not set 822# CONFIG_KGDB is not set
825CONFIG_CMDLINE="" 823# CONFIG_CMDLINE_BOOL is not set
826# CONFIG_DEBUG_STACK_USAGE is not set 824# CONFIG_DEBUG_STACK_USAGE is not set
827# CONFIG_RUNTIME_DEBUG is not set 825# CONFIG_RUNTIME_DEBUG is not set
828 826
diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig
index 6c8cca8589ba..49e61312e006 100644
--- a/arch/mips/configs/cobalt_defconfig
+++ b/arch/mips/configs/cobalt_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set 12# CONFIG_BCM47XX is not set
14CONFIG_MIPS_COBALT=y 13CONFIG_MIPS_COBALT=y
15# CONFIG_MACH_DECSTATION is not set 14# CONFIG_MACH_DECSTATION is not set
@@ -1126,7 +1125,7 @@ CONFIG_FRAME_WARN=1024
1126# CONFIG_SLUB_STATS is not set 1125# CONFIG_SLUB_STATS is not set
1127# CONFIG_DEBUG_MEMORY_INIT is not set 1126# CONFIG_DEBUG_MEMORY_INIT is not set
1128# CONFIG_SAMPLES is not set 1127# CONFIG_SAMPLES is not set
1129CONFIG_CMDLINE="" 1128# CONFIG_CMDLINE_BOOL is not set
1130 1129
1131# 1130#
1132# Security options 1131# Security options
diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig
index dbdf3bb1a34a..68e90cd6b2d4 100644
--- a/arch/mips/configs/db1000_defconfig
+++ b/arch/mips/configs/db1000_defconfig
@@ -23,7 +23,6 @@ CONFIG_MIPS_DB1000=y
23# CONFIG_MIPS_DB1550 is not set 23# CONFIG_MIPS_DB1550 is not set
24# CONFIG_MIPS_DB1200 is not set 24# CONFIG_MIPS_DB1200 is not set
25# CONFIG_MIPS_MIRAGE is not set 25# CONFIG_MIPS_MIRAGE is not set
26# CONFIG_BASLER_EXCITE is not set
27# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
28# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
@@ -1090,7 +1089,7 @@ CONFIG_ENABLE_MUST_CHECK=y
1090# CONFIG_DEBUG_KERNEL is not set 1089# CONFIG_DEBUG_KERNEL is not set
1091CONFIG_LOG_BUF_SHIFT=14 1090CONFIG_LOG_BUF_SHIFT=14
1092CONFIG_CROSSCOMPILE=y 1091CONFIG_CROSSCOMPILE=y
1093CONFIG_CMDLINE="" 1092# CONFIG_CMDLINE_BOOL is not set
1094 1093
1095# 1094#
1096# Security options 1095# Security options
diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig
index fa6814475898..90812830e940 100644
--- a/arch/mips/configs/db1100_defconfig
+++ b/arch/mips/configs/db1100_defconfig
@@ -23,7 +23,6 @@ CONFIG_MIPS_DB1100=y
23# CONFIG_MIPS_DB1550 is not set 23# CONFIG_MIPS_DB1550 is not set
24# CONFIG_MIPS_DB1200 is not set 24# CONFIG_MIPS_DB1200 is not set
25# CONFIG_MIPS_MIRAGE is not set 25# CONFIG_MIPS_MIRAGE is not set
26# CONFIG_BASLER_EXCITE is not set
27# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
28# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
@@ -1090,7 +1089,7 @@ CONFIG_ENABLE_MUST_CHECK=y
1090# CONFIG_DEBUG_KERNEL is not set 1089# CONFIG_DEBUG_KERNEL is not set
1091CONFIG_LOG_BUF_SHIFT=14 1090CONFIG_LOG_BUF_SHIFT=14
1092CONFIG_CROSSCOMPILE=y 1091CONFIG_CROSSCOMPILE=y
1093CONFIG_CMDLINE="" 1092# CONFIG_CMDLINE_BOOL is not set
1094 1093
1095# 1094#
1096# Security options 1095# Security options
diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig
index d73f1de43b5d..dabf03032e06 100644
--- a/arch/mips/configs/db1200_defconfig
+++ b/arch/mips/configs/db1200_defconfig
@@ -23,7 +23,6 @@ CONFIG_MACH_ALCHEMY=y
23# CONFIG_MIPS_DB1550 is not set 23# CONFIG_MIPS_DB1550 is not set
24CONFIG_MIPS_DB1200=y 24CONFIG_MIPS_DB1200=y
25# CONFIG_MIPS_MIRAGE is not set 25# CONFIG_MIPS_MIRAGE is not set
26# CONFIG_BASLER_EXCITE is not set
27# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
28# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
@@ -1172,7 +1171,9 @@ CONFIG_ENABLE_MUST_CHECK=y
1172# CONFIG_DEBUG_KERNEL is not set 1171# CONFIG_DEBUG_KERNEL is not set
1173CONFIG_LOG_BUF_SHIFT=14 1172CONFIG_LOG_BUF_SHIFT=14
1174CONFIG_CROSSCOMPILE=y 1173CONFIG_CROSSCOMPILE=y
1174CONFIG_CMDLINE_BOOL=y
1175CONFIG_CMDLINE="mem=48M" 1175CONFIG_CMDLINE="mem=48M"
1176# CONFIG_CMDLINE_OVERRIDE is not set
1176 1177
1177# 1178#
1178# Security options 1179# Security options
diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig
index ec3e028a5b2e..a15131373138 100644
--- a/arch/mips/configs/db1500_defconfig
+++ b/arch/mips/configs/db1500_defconfig
@@ -23,7 +23,6 @@ CONFIG_MIPS_DB1500=y
23# CONFIG_MIPS_DB1550 is not set 23# CONFIG_MIPS_DB1550 is not set
24# CONFIG_MIPS_DB1200 is not set 24# CONFIG_MIPS_DB1200 is not set
25# CONFIG_MIPS_MIRAGE is not set 25# CONFIG_MIPS_MIRAGE is not set
26# CONFIG_BASLER_EXCITE is not set
27# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
28# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
@@ -1390,7 +1389,7 @@ CONFIG_ENABLE_MUST_CHECK=y
1390# CONFIG_DEBUG_KERNEL is not set 1389# CONFIG_DEBUG_KERNEL is not set
1391CONFIG_LOG_BUF_SHIFT=14 1390CONFIG_LOG_BUF_SHIFT=14
1392CONFIG_CROSSCOMPILE=y 1391CONFIG_CROSSCOMPILE=y
1393CONFIG_CMDLINE="" 1392# CONFIG_CMDLINE_BOOL is not set
1394 1393
1395# 1394#
1396# Security options 1395# Security options
diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig
index 7631dae51be9..6b64339c0014 100644
--- a/arch/mips/configs/db1550_defconfig
+++ b/arch/mips/configs/db1550_defconfig
@@ -23,7 +23,6 @@ CONFIG_MACH_ALCHEMY=y
23CONFIG_MIPS_DB1550=y 23CONFIG_MIPS_DB1550=y
24# CONFIG_MIPS_DB1200 is not set 24# CONFIG_MIPS_DB1200 is not set
25# CONFIG_MIPS_MIRAGE is not set 25# CONFIG_MIPS_MIRAGE is not set
26# CONFIG_BASLER_EXCITE is not set
27# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
28# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
@@ -1207,7 +1206,7 @@ CONFIG_ENABLE_MUST_CHECK=y
1207# CONFIG_DEBUG_KERNEL is not set 1206# CONFIG_DEBUG_KERNEL is not set
1208CONFIG_LOG_BUF_SHIFT=14 1207CONFIG_LOG_BUF_SHIFT=14
1209CONFIG_CROSSCOMPILE=y 1208CONFIG_CROSSCOMPILE=y
1210CONFIG_CMDLINE="" 1209# CONFIG_CMDLINE_BOOL is not set
1211 1210
1212# 1211#
1213# Security options 1212# Security options
diff --git a/arch/mips/configs/decstation_defconfig b/arch/mips/configs/decstation_defconfig
index 9e65e6a2dcb3..cbb4d86f2912 100644
--- a/arch/mips/configs/decstation_defconfig
+++ b/arch/mips/configs/decstation_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
22# CONFIG_MIPS_DB1550 is not set 22# CONFIG_MIPS_DB1550 is not set
23# CONFIG_MIPS_DB1200 is not set 23# CONFIG_MIPS_DB1200 is not set
24# CONFIG_MIPS_MIRAGE is not set 24# CONFIG_MIPS_MIRAGE is not set
25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 25# CONFIG_MIPS_COBALT is not set
27CONFIG_MACH_DECSTATION=y 26CONFIG_MACH_DECSTATION=y
28# CONFIG_MACH_JAZZ is not set 27# CONFIG_MACH_JAZZ is not set
@@ -882,7 +881,7 @@ CONFIG_MAGIC_SYSRQ=y
882# CONFIG_DEBUG_KERNEL is not set 881# CONFIG_DEBUG_KERNEL is not set
883CONFIG_LOG_BUF_SHIFT=14 882CONFIG_LOG_BUF_SHIFT=14
884CONFIG_CROSSCOMPILE=y 883CONFIG_CROSSCOMPILE=y
885CONFIG_CMDLINE="" 884# CONFIG_CMDLINE_BOOL is not set
886 885
887# 886#
888# Security options 887# Security options
diff --git a/arch/mips/configs/e55_defconfig b/arch/mips/configs/e55_defconfig
index 1bd84d42b14f..52968c46c806 100644
--- a/arch/mips/configs/e55_defconfig
+++ b/arch/mips/configs/e55_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_MIPS_COBALT is not set 12# CONFIG_MIPS_COBALT is not set
14# CONFIG_MACH_DECSTATION is not set 13# CONFIG_MACH_DECSTATION is not set
15# CONFIG_MACH_JAZZ is not set 14# CONFIG_MACH_JAZZ is not set
@@ -561,7 +560,9 @@ CONFIG_ENABLE_MUST_CHECK=y
561# CONFIG_HEADERS_CHECK is not set 560# CONFIG_HEADERS_CHECK is not set
562# CONFIG_DEBUG_KERNEL is not set 561# CONFIG_DEBUG_KERNEL is not set
563CONFIG_CROSSCOMPILE=y 562CONFIG_CROSSCOMPILE=y
563CONFIG_CMDLINE_BOOL=y
564CONFIG_CMDLINE="console=ttyVR0,19200 ide0=0x1f0,0x3f6,40 mem=8M" 564CONFIG_CMDLINE="console=ttyVR0,19200 ide0=0x1f0,0x3f6,40 mem=8M"
565# CONFIG_CMDLINE_OVERRIDE is not set
565 566
566# 567#
567# Security options 568# Security options
diff --git a/arch/mips/configs/excite_defconfig b/arch/mips/configs/excite_defconfig
deleted file mode 100644
index 1995d43a2ed1..000000000000
--- a/arch/mips/configs/excite_defconfig
+++ /dev/null
@@ -1,1335 +0,0 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.20
4# Tue Feb 20 21:47:31 2007
5#
6CONFIG_MIPS=y
7
8#
9# Machine selection
10#
11CONFIG_ZONE_DMA=y
12# CONFIG_MIPS_MTX1 is not set
13# CONFIG_MIPS_BOSPORUS is not set
14# CONFIG_MIPS_PB1000 is not set
15# CONFIG_MIPS_PB1100 is not set
16# CONFIG_MIPS_PB1500 is not set
17# CONFIG_MIPS_PB1550 is not set
18# CONFIG_MIPS_PB1200 is not set
19# CONFIG_MIPS_DB1000 is not set
20# CONFIG_MIPS_DB1100 is not set
21# CONFIG_MIPS_DB1500 is not set
22# CONFIG_MIPS_DB1550 is not set
23# CONFIG_MIPS_DB1200 is not set
24# CONFIG_MIPS_MIRAGE is not set
25CONFIG_BASLER_EXCITE=y
26# CONFIG_BASLER_EXCITE_PROTOTYPE is not set
27# CONFIG_MIPS_COBALT is not set
28# CONFIG_MACH_DECSTATION is not set
29# CONFIG_MACH_JAZZ is not set
30# CONFIG_MIPS_MALTA is not set
31# CONFIG_WR_PPMC is not set
32# CONFIG_MIPS_SIM is not set
33# CONFIG_MOMENCO_JAGUAR_ATX is not set
34# CONFIG_MIPS_XXS1500 is not set
35# CONFIG_PNX8550_JBS is not set
36# CONFIG_PNX8550_STB810 is not set
37# CONFIG_MACH_VR41XX is not set
38# CONFIG_PMC_YOSEMITE is not set
39# CONFIG_MARKEINS is not set
40# CONFIG_SGI_IP22 is not set
41# CONFIG_SGI_IP27 is not set
42# CONFIG_SGI_IP32 is not set
43# CONFIG_SIBYTE_BIGSUR is not set
44# CONFIG_SIBYTE_SWARM is not set
45# CONFIG_SIBYTE_SENTOSA is not set
46# CONFIG_SIBYTE_RHONE is not set
47# CONFIG_SIBYTE_CARMEL is not set
48# CONFIG_SIBYTE_LITTLESUR is not set
49# CONFIG_SIBYTE_CRHINE is not set
50# CONFIG_SIBYTE_CRHONE is not set
51# CONFIG_SNI_RM is not set
52# CONFIG_TOSHIBA_JMR3927 is not set
53# CONFIG_TOSHIBA_RBTX4927 is not set
54# CONFIG_TOSHIBA_RBTX4938 is not set
55CONFIG_RWSEM_GENERIC_SPINLOCK=y
56# CONFIG_ARCH_HAS_ILOG2_U32 is not set
57# CONFIG_ARCH_HAS_ILOG2_U64 is not set
58CONFIG_GENERIC_FIND_NEXT_BIT=y
59CONFIG_GENERIC_HWEIGHT=y
60CONFIG_GENERIC_CALIBRATE_DELAY=y
61CONFIG_GENERIC_TIME=y
62CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
63# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
64CONFIG_DMA_COHERENT=y
65CONFIG_CPU_BIG_ENDIAN=y
66# CONFIG_CPU_LITTLE_ENDIAN is not set
67CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
68CONFIG_IRQ_CPU=y
69CONFIG_IRQ_CPU_RM7K=y
70CONFIG_IRQ_CPU_RM9K=y
71CONFIG_MIPS_RM9122=y
72CONFIG_SERIAL_RM9000=y
73CONFIG_GPI_RM9000=y
74CONFIG_WDT_RM9000=y
75CONFIG_MIPS_L1_CACHE_SHIFT=5
76
77#
78# CPU selection
79#
80# CONFIG_CPU_MIPS32_R1 is not set
81# CONFIG_CPU_MIPS32_R2 is not set
82# CONFIG_CPU_MIPS64_R1 is not set
83# CONFIG_CPU_MIPS64_R2 is not set
84# CONFIG_CPU_R3000 is not set
85# CONFIG_CPU_TX39XX is not set
86# CONFIG_CPU_VR41XX is not set
87# CONFIG_CPU_R4300 is not set
88# CONFIG_CPU_R4X00 is not set
89# CONFIG_CPU_TX49XX is not set
90# CONFIG_CPU_R5000 is not set
91# CONFIG_CPU_R5432 is not set
92# CONFIG_CPU_R6000 is not set
93# CONFIG_CPU_NEVADA is not set
94# CONFIG_CPU_R8000 is not set
95# CONFIG_CPU_R10000 is not set
96# CONFIG_CPU_RM7000 is not set
97CONFIG_CPU_RM9000=y
98# CONFIG_CPU_SB1 is not set
99CONFIG_SYS_HAS_CPU_RM9000=y
100CONFIG_WEAK_ORDERING=y
101CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
102CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
103CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
104CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
105
106#
107# Kernel type
108#
109CONFIG_32BIT=y
110# CONFIG_64BIT is not set
111CONFIG_PAGE_SIZE_4KB=y
112# CONFIG_PAGE_SIZE_8KB is not set
113# CONFIG_PAGE_SIZE_16KB is not set
114# CONFIG_PAGE_SIZE_64KB is not set
115CONFIG_CPU_HAS_PREFETCH=y
116CONFIG_MIPS_MT_DISABLED=y
117# CONFIG_MIPS_MT_SMP is not set
118# CONFIG_MIPS_MT_SMTC is not set
119# CONFIG_MIPS_VPE_LOADER is not set
120# CONFIG_64BIT_PHYS_ADDR is not set
121CONFIG_CPU_HAS_SYNC=y
122CONFIG_GENERIC_HARDIRQS=y
123CONFIG_GENERIC_IRQ_PROBE=y
124CONFIG_CPU_SUPPORTS_HIGHMEM=y
125CONFIG_ARCH_FLATMEM_ENABLE=y
126CONFIG_SELECT_MEMORY_MODEL=y
127CONFIG_FLATMEM_MANUAL=y
128# CONFIG_DISCONTIGMEM_MANUAL is not set
129# CONFIG_SPARSEMEM_MANUAL is not set
130CONFIG_FLATMEM=y
131CONFIG_FLAT_NODE_MEM_MAP=y
132# CONFIG_SPARSEMEM_STATIC is not set
133CONFIG_SPLIT_PTLOCK_CPUS=4
134# CONFIG_RESOURCES_64BIT is not set
135CONFIG_ZONE_DMA_FLAG=1
136# CONFIG_HZ_48 is not set
137# CONFIG_HZ_100 is not set
138# CONFIG_HZ_128 is not set
139# CONFIG_HZ_250 is not set
140# CONFIG_HZ_256 is not set
141CONFIG_HZ_1000=y
142# CONFIG_HZ_1024 is not set
143CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
144CONFIG_HZ=1000
145# CONFIG_PREEMPT_NONE is not set
146# CONFIG_PREEMPT_VOLUNTARY is not set
147CONFIG_PREEMPT=y
148CONFIG_PREEMPT_BKL=y
149# CONFIG_KEXEC is not set
150CONFIG_LOCKDEP_SUPPORT=y
151CONFIG_STACKTRACE_SUPPORT=y
152CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
153
154#
155# Code maturity level options
156#
157CONFIG_EXPERIMENTAL=y
158CONFIG_BROKEN_ON_SMP=y
159CONFIG_LOCK_KERNEL=y
160CONFIG_INIT_ENV_ARG_LIMIT=32
161
162#
163# General setup
164#
165CONFIG_LOCALVERSION=""
166# CONFIG_LOCALVERSION_AUTO is not set
167CONFIG_SWAP=y
168CONFIG_SYSVIPC=y
169# CONFIG_IPC_NS is not set
170CONFIG_SYSVIPC_SYSCTL=y
171CONFIG_POSIX_MQUEUE=y
172# CONFIG_BSD_PROCESS_ACCT is not set
173# CONFIG_TASKSTATS is not set
174# CONFIG_UTS_NS is not set
175# CONFIG_AUDIT is not set
176# CONFIG_IKCONFIG is not set
177CONFIG_SYSFS_DEPRECATED=y
178# CONFIG_RELAY is not set
179CONFIG_CC_OPTIMIZE_FOR_SIZE=y
180CONFIG_SYSCTL=y
181CONFIG_EMBEDDED=y
182CONFIG_SYSCTL_SYSCALL=y
183CONFIG_KALLSYMS=y
184# CONFIG_KALLSYMS_EXTRA_PASS is not set
185CONFIG_HOTPLUG=y
186CONFIG_PRINTK=y
187CONFIG_BUG=y
188CONFIG_ELF_CORE=y
189CONFIG_BASE_FULL=y
190CONFIG_FUTEX=y
191CONFIG_EPOLL=y
192CONFIG_SHMEM=y
193CONFIG_SLAB=y
194CONFIG_VM_EVENT_COUNTERS=y
195CONFIG_RT_MUTEXES=y
196# CONFIG_TINY_SHMEM is not set
197CONFIG_BASE_SMALL=0
198# CONFIG_SLOB is not set
199
200#
201# Loadable module support
202#
203CONFIG_MODULES=y
204CONFIG_MODULE_UNLOAD=y
205# CONFIG_MODULE_FORCE_UNLOAD is not set
206# CONFIG_MODVERSIONS is not set
207# CONFIG_MODULE_SRCVERSION_ALL is not set
208CONFIG_KMOD=y
209
210#
211# Block layer
212#
213CONFIG_BLOCK=y
214# CONFIG_LBD is not set
215# CONFIG_BLK_DEV_IO_TRACE is not set
216# CONFIG_LSF is not set
217
218#
219# IO Schedulers
220#
221CONFIG_IOSCHED_NOOP=y
222CONFIG_IOSCHED_AS=y
223CONFIG_IOSCHED_DEADLINE=y
224CONFIG_IOSCHED_CFQ=y
225CONFIG_DEFAULT_AS=y
226# CONFIG_DEFAULT_DEADLINE is not set
227# CONFIG_DEFAULT_CFQ is not set
228# CONFIG_DEFAULT_NOOP is not set
229CONFIG_DEFAULT_IOSCHED="anticipatory"
230
231#
232# Bus options (PCI, PCMCIA, EISA, ISA, TC)
233#
234CONFIG_HW_HAS_PCI=y
235CONFIG_PCI=y
236CONFIG_MMU=y
237
238#
239# PCCARD (PCMCIA/CardBus) support
240#
241# CONFIG_PCCARD is not set
242
243#
244# PCI Hotplug Support
245#
246# CONFIG_HOTPLUG_PCI is not set
247
248#
249# Executable file formats
250#
251CONFIG_BINFMT_ELF=y
252# CONFIG_BINFMT_MISC is not set
253CONFIG_TRAD_SIGNALS=y
254
255#
256# Power management options
257#
258CONFIG_PM=y
259# CONFIG_PM_LEGACY is not set
260# CONFIG_PM_DEBUG is not set
261# CONFIG_PM_SYSFS_DEPRECATED is not set
262
263#
264# Networking
265#
266CONFIG_NET=y
267
268#
269# Networking options
270#
271# CONFIG_NETDEBUG is not set
272CONFIG_PACKET=y
273CONFIG_PACKET_MMAP=y
274CONFIG_UNIX=y
275CONFIG_XFRM=y
276# CONFIG_XFRM_USER is not set
277# CONFIG_XFRM_SUB_POLICY is not set
278CONFIG_XFRM_MIGRATE=y
279# CONFIG_NET_KEY is not set
280CONFIG_INET=y
281# CONFIG_IP_MULTICAST is not set
282# CONFIG_IP_ADVANCED_ROUTER is not set
283CONFIG_IP_FIB_HASH=y
284CONFIG_IP_PNP=y
285CONFIG_IP_PNP_DHCP=y
286# CONFIG_IP_PNP_BOOTP is not set
287# CONFIG_IP_PNP_RARP is not set
288# CONFIG_NET_IPIP is not set
289# CONFIG_NET_IPGRE is not set
290# CONFIG_ARPD is not set
291# CONFIG_SYN_COOKIES is not set
292# CONFIG_INET_AH is not set
293# CONFIG_INET_ESP is not set
294# CONFIG_INET_IPCOMP is not set
295# CONFIG_INET_XFRM_TUNNEL is not set
296# CONFIG_INET_TUNNEL is not set
297CONFIG_INET_XFRM_MODE_TRANSPORT=m
298CONFIG_INET_XFRM_MODE_TUNNEL=m
299CONFIG_INET_XFRM_MODE_BEET=m
300CONFIG_INET_DIAG=y
301CONFIG_INET_TCP_DIAG=y
302# CONFIG_TCP_CONG_ADVANCED is not set
303CONFIG_TCP_CONG_CUBIC=y
304CONFIG_DEFAULT_TCP_CONG="cubic"
305CONFIG_TCP_MD5SIG=y
306# CONFIG_IPV6 is not set
307# CONFIG_INET6_XFRM_TUNNEL is not set
308# CONFIG_INET6_TUNNEL is not set
309CONFIG_NETWORK_SECMARK=y
310# CONFIG_NETFILTER is not set
311
312#
313# DCCP Configuration (EXPERIMENTAL)
314#
315# CONFIG_IP_DCCP is not set
316
317#
318# SCTP Configuration (EXPERIMENTAL)
319#
320# CONFIG_IP_SCTP is not set
321
322#
323# TIPC Configuration (EXPERIMENTAL)
324#
325# CONFIG_TIPC is not set
326# CONFIG_ATM is not set
327# CONFIG_BRIDGE is not set
328# CONFIG_VLAN_8021Q is not set
329# CONFIG_DECNET is not set
330# CONFIG_LLC2 is not set
331# CONFIG_IPX is not set
332# CONFIG_ATALK is not set
333# CONFIG_X25 is not set
334# CONFIG_LAPB is not set
335# CONFIG_ECONET is not set
336# CONFIG_WAN_ROUTER is not set
337
338#
339# QoS and/or fair queueing
340#
341# CONFIG_NET_SCHED is not set
342
343#
344# Network testing
345#
346# CONFIG_NET_PKTGEN is not set
347# CONFIG_HAMRADIO is not set
348# CONFIG_IRDA is not set
349# CONFIG_BT is not set
350# CONFIG_IEEE80211 is not set
351
352#
353# Device Drivers
354#
355
356#
357# Generic Driver Options
358#
359CONFIG_STANDALONE=y
360CONFIG_PREVENT_FIRMWARE_BUILD=y
361CONFIG_FW_LOADER=m
362# CONFIG_SYS_HYPERVISOR is not set
363
364#
365# Connector - unified userspace <-> kernelspace linker
366#
367# CONFIG_CONNECTOR is not set
368
369#
370# Memory Technology Devices (MTD)
371#
372CONFIG_MTD=y
373# CONFIG_MTD_DEBUG is not set
374# CONFIG_MTD_CONCAT is not set
375CONFIG_MTD_PARTITIONS=y
376# CONFIG_MTD_REDBOOT_PARTS is not set
377# CONFIG_MTD_CMDLINE_PARTS is not set
378
379#
380# User Modules And Translation Layers
381#
382CONFIG_MTD_CHAR=y
383CONFIG_MTD_BLKDEVS=y
384CONFIG_MTD_BLOCK=y
385# CONFIG_FTL is not set
386# CONFIG_NFTL is not set
387# CONFIG_INFTL is not set
388# CONFIG_RFD_FTL is not set
389# CONFIG_SSFDC is not set
390
391#
392# RAM/ROM/Flash chip drivers
393#
394# CONFIG_MTD_CFI is not set
395# CONFIG_MTD_JEDECPROBE is not set
396CONFIG_MTD_MAP_BANK_WIDTH_1=y
397CONFIG_MTD_MAP_BANK_WIDTH_2=y
398CONFIG_MTD_MAP_BANK_WIDTH_4=y
399# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
400# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
401# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
402CONFIG_MTD_CFI_I1=y
403CONFIG_MTD_CFI_I2=y
404# CONFIG_MTD_CFI_I4 is not set
405# CONFIG_MTD_CFI_I8 is not set
406# CONFIG_MTD_RAM is not set
407# CONFIG_MTD_ROM is not set
408# CONFIG_MTD_ABSENT is not set
409# CONFIG_MTD_OBSOLETE_CHIPS is not set
410
411#
412# Mapping drivers for chip access
413#
414# CONFIG_MTD_COMPLEX_MAPPINGS is not set
415# CONFIG_MTD_PLATRAM is not set
416
417#
418# Self-contained MTD device drivers
419#
420# CONFIG_MTD_PMC551 is not set
421# CONFIG_MTD_SLRAM is not set
422# CONFIG_MTD_PHRAM is not set
423# CONFIG_MTD_MTDRAM is not set
424# CONFIG_MTD_BLOCK2MTD is not set
425
426#
427# Disk-On-Chip Device Drivers
428#
429# CONFIG_MTD_DOC2000 is not set
430# CONFIG_MTD_DOC2001 is not set
431# CONFIG_MTD_DOC2001PLUS is not set
432
433#
434# NAND Flash Device Drivers
435#
436CONFIG_MTD_NAND=y
437CONFIG_MTD_NAND_VERIFY_WRITE=y
438# CONFIG_MTD_NAND_ECC_SMC is not set
439CONFIG_MTD_NAND_IDS=y
440# CONFIG_MTD_NAND_DISKONCHIP is not set
441# CONFIG_MTD_NAND_BASLER_EXCITE is not set
442# CONFIG_MTD_NAND_CAFE is not set
443# CONFIG_MTD_NAND_NANDSIM is not set
444
445#
446# OneNAND Flash Device Drivers
447#
448# CONFIG_MTD_ONENAND is not set
449
450#
451# Parallel port support
452#
453# CONFIG_PARPORT is not set
454
455#
456# Plug and Play support
457#
458# CONFIG_PNPACPI is not set
459
460#
461# Block devices
462#
463# CONFIG_BLK_CPQ_DA is not set
464# CONFIG_BLK_CPQ_CISS_DA is not set
465# CONFIG_BLK_DEV_DAC960 is not set
466# CONFIG_BLK_DEV_UMEM is not set
467# CONFIG_BLK_DEV_COW_COMMON is not set
468CONFIG_BLK_DEV_LOOP=m
469# CONFIG_BLK_DEV_CRYPTOLOOP is not set
470# CONFIG_BLK_DEV_NBD is not set
471# CONFIG_BLK_DEV_SX8 is not set
472# CONFIG_BLK_DEV_UB is not set
473# CONFIG_BLK_DEV_RAM is not set
474# CONFIG_BLK_DEV_INITRD is not set
475# CONFIG_CDROM_PKTCDVD is not set
476# CONFIG_ATA_OVER_ETH is not set
477
478#
479# Misc devices
480#
481CONFIG_SGI_IOC4=m
482# CONFIG_TIFM_CORE is not set
483
484#
485# ATA/ATAPI/MFM/RLL support
486#
487# CONFIG_IDE is not set
488
489#
490# SCSI device support
491#
492# CONFIG_RAID_ATTRS is not set
493CONFIG_SCSI=y
494CONFIG_SCSI_TGT=m
495# CONFIG_SCSI_NETLINK is not set
496# CONFIG_SCSI_PROC_FS is not set
497
498#
499# SCSI support type (disk, tape, CD-ROM)
500#
501CONFIG_BLK_DEV_SD=y
502# CONFIG_CHR_DEV_ST is not set
503# CONFIG_CHR_DEV_OSST is not set
504# CONFIG_BLK_DEV_SR is not set
505# CONFIG_CHR_DEV_SG is not set
506# CONFIG_CHR_DEV_SCH is not set
507
508#
509# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
510#
511# CONFIG_SCSI_MULTI_LUN is not set
512# CONFIG_SCSI_CONSTANTS is not set
513# CONFIG_SCSI_LOGGING is not set
514CONFIG_SCSI_SCAN_ASYNC=y
515
516#
517# SCSI Transports
518#
519# CONFIG_SCSI_SPI_ATTRS is not set
520# CONFIG_SCSI_FC_ATTRS is not set
521# CONFIG_SCSI_ISCSI_ATTRS is not set
522CONFIG_SCSI_SAS_ATTRS=m
523CONFIG_SCSI_SAS_LIBSAS=m
524# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
525
526#
527# SCSI low-level drivers
528#
529# CONFIG_ISCSI_TCP is not set
530# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
531# CONFIG_SCSI_3W_9XXX is not set
532# CONFIG_SCSI_ACARD is not set
533# CONFIG_SCSI_AACRAID is not set
534# CONFIG_SCSI_AIC7XXX is not set
535# CONFIG_SCSI_AIC7XXX_OLD is not set
536# CONFIG_SCSI_AIC79XX is not set
537CONFIG_SCSI_AIC94XX=m
538# CONFIG_AIC94XX_DEBUG is not set
539# CONFIG_SCSI_DPT_I2O is not set
540# CONFIG_SCSI_ARCMSR is not set
541# CONFIG_MEGARAID_NEWGEN is not set
542# CONFIG_MEGARAID_LEGACY is not set
543# CONFIG_MEGARAID_SAS is not set
544# CONFIG_SCSI_HPTIOP is not set
545# CONFIG_SCSI_DMX3191D is not set
546# CONFIG_SCSI_FUTURE_DOMAIN is not set
547# CONFIG_SCSI_IPS is not set
548# CONFIG_SCSI_INITIO is not set
549# CONFIG_SCSI_INIA100 is not set
550# CONFIG_SCSI_STEX is not set
551# CONFIG_SCSI_SYM53C8XX_2 is not set
552# CONFIG_SCSI_QLOGIC_1280 is not set
553# CONFIG_SCSI_QLA_FC is not set
554# CONFIG_SCSI_QLA_ISCSI is not set
555# CONFIG_SCSI_LPFC is not set
556# CONFIG_SCSI_DC395x is not set
557# CONFIG_SCSI_DC390T is not set
558# CONFIG_SCSI_NSP32 is not set
559# CONFIG_SCSI_DEBUG is not set
560# CONFIG_SCSI_SRP is not set
561
562#
563# Serial ATA (prod) and Parallel ATA (experimental) drivers
564#
565# CONFIG_ATA is not set
566
567#
568# Multi-device support (RAID and LVM)
569#
570# CONFIG_MD is not set
571
572#
573# Fusion MPT device support
574#
575# CONFIG_FUSION is not set
576# CONFIG_FUSION_SPI is not set
577# CONFIG_FUSION_FC is not set
578# CONFIG_FUSION_SAS is not set
579
580#
581# IEEE 1394 (FireWire) support
582#
583# CONFIG_IEEE1394 is not set
584
585#
586# I2O device support
587#
588# CONFIG_I2O is not set
589
590#
591# Network device support
592#
593CONFIG_NETDEVICES=y
594# CONFIG_DUMMY is not set
595# CONFIG_BONDING is not set
596# CONFIG_EQUALIZER is not set
597# CONFIG_TUN is not set
598
599#
600# ARCnet devices
601#
602# CONFIG_ARCNET is not set
603
604#
605# PHY device support
606#
607
608#
609# Ethernet (10 or 100Mbit)
610#
611# CONFIG_NET_ETHERNET is not set
612
613#
614# Ethernet (1000 Mbit)
615#
616# CONFIG_ACENIC is not set
617# CONFIG_DL2K is not set
618# CONFIG_E1000 is not set
619# CONFIG_NS83820 is not set
620# CONFIG_HAMACHI is not set
621# CONFIG_YELLOWFIN is not set
622# CONFIG_R8169 is not set
623# CONFIG_SIS190 is not set
624# CONFIG_SKGE is not set
625# CONFIG_SKY2 is not set
626# CONFIG_SK98LIN is not set
627# CONFIG_TIGON3 is not set
628# CONFIG_BNX2 is not set
629CONFIG_QLA3XXX=m
630# CONFIG_ATL1 is not set
631
632#
633# Ethernet (10000 Mbit)
634#
635# CONFIG_CHELSIO_T1 is not set
636CONFIG_CHELSIO_T3=m
637# CONFIG_IXGB is not set
638# CONFIG_S2IO is not set
639# CONFIG_MYRI10GE is not set
640CONFIG_NETXEN_NIC=m
641
642#
643# Token Ring devices
644#
645# CONFIG_TR is not set
646
647#
648# Wireless LAN (non-hamradio)
649#
650# CONFIG_NET_RADIO is not set
651
652#
653# Wan interfaces
654#
655# CONFIG_WAN is not set
656# CONFIG_FDDI is not set
657# CONFIG_HIPPI is not set
658# CONFIG_PPP is not set
659# CONFIG_SLIP is not set
660# CONFIG_NET_FC is not set
661# CONFIG_SHAPER is not set
662# CONFIG_NETCONSOLE is not set
663# CONFIG_NETPOLL is not set
664# CONFIG_NET_POLL_CONTROLLER is not set
665
666#
667# ISDN subsystem
668#
669# CONFIG_ISDN is not set
670
671#
672# Telephony Support
673#
674# CONFIG_PHONE is not set
675
676#
677# Input device support
678#
679CONFIG_INPUT=y
680# CONFIG_INPUT_FF_MEMLESS is not set
681
682#
683# Userland interfaces
684#
685CONFIG_INPUT_MOUSEDEV=m
686CONFIG_INPUT_MOUSEDEV_PSAUX=y
687CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
688CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
689# CONFIG_INPUT_JOYDEV is not set
690# CONFIG_INPUT_TSDEV is not set
691CONFIG_INPUT_EVDEV=m
692# CONFIG_INPUT_EVBUG is not set
693
694#
695# Input Device Drivers
696#
697# CONFIG_INPUT_KEYBOARD is not set
698# CONFIG_INPUT_MOUSE is not set
699# CONFIG_INPUT_JOYSTICK is not set
700# CONFIG_INPUT_TOUCHSCREEN is not set
701# CONFIG_INPUT_MISC is not set
702
703#
704# Hardware I/O ports
705#
706# CONFIG_SERIO is not set
707# CONFIG_GAMEPORT is not set
708
709#
710# Character devices
711#
712CONFIG_VT=y
713CONFIG_VT_CONSOLE=y
714CONFIG_HW_CONSOLE=y
715CONFIG_VT_HW_CONSOLE_BINDING=y
716# CONFIG_SERIAL_NONSTANDARD is not set
717
718#
719# Serial drivers
720#
721CONFIG_SERIAL_8250=y
722CONFIG_SERIAL_8250_CONSOLE=y
723CONFIG_SERIAL_8250_PCI=y
724CONFIG_SERIAL_8250_NR_UARTS=2
725CONFIG_SERIAL_8250_RUNTIME_UARTS=2
726CONFIG_SERIAL_8250_EXTENDED=y
727# CONFIG_SERIAL_8250_MANY_PORTS is not set
728CONFIG_SERIAL_8250_SHARE_IRQ=y
729# CONFIG_SERIAL_8250_DETECT_IRQ is not set
730# CONFIG_SERIAL_8250_RSA is not set
731
732#
733# Non-8250 serial port support
734#
735CONFIG_SERIAL_CORE=y
736CONFIG_SERIAL_CORE_CONSOLE=y
737# CONFIG_SERIAL_JSM is not set
738CONFIG_UNIX98_PTYS=y
739# CONFIG_LEGACY_PTYS is not set
740
741#
742# IPMI
743#
744# CONFIG_IPMI_HANDLER is not set
745
746#
747# Watchdog Cards
748#
749CONFIG_WATCHDOG=y
750# CONFIG_WATCHDOG_NOWAYOUT is not set
751
752#
753# Watchdog Device Drivers
754#
755# CONFIG_SOFT_WATCHDOG is not set
756CONFIG_WDT_RM9K_GPI=m
757
758#
759# PCI-based Watchdog Cards
760#
761# CONFIG_PCIPCWATCHDOG is not set
762# CONFIG_WDTPCI is not set
763
764#
765# USB-based Watchdog Cards
766#
767# CONFIG_USBPCWATCHDOG is not set
768# CONFIG_HW_RANDOM is not set
769# CONFIG_RTC is not set
770# CONFIG_GEN_RTC is not set
771# CONFIG_DTLK is not set
772# CONFIG_R3964 is not set
773# CONFIG_APPLICOM is not set
774# CONFIG_DRM is not set
775# CONFIG_RAW_DRIVER is not set
776
777#
778# TPM devices
779#
780# CONFIG_TCG_TPM is not set
781
782#
783# I2C support
784#
785# CONFIG_I2C is not set
786
787#
788# SPI support
789#
790# CONFIG_SPI is not set
791# CONFIG_SPI_MASTER is not set
792
793#
794# Dallas's 1-wire bus
795#
796# CONFIG_W1 is not set
797
798#
799# Hardware Monitoring support
800#
801# CONFIG_HWMON is not set
802# CONFIG_HWMON_VID is not set
803
804#
805# Multimedia devices
806#
807# CONFIG_VIDEO_DEV is not set
808
809#
810# Digital Video Broadcasting Devices
811#
812# CONFIG_DVB is not set
813# CONFIG_USB_DABUSB is not set
814
815#
816# Graphics support
817#
818# CONFIG_FIRMWARE_EDID is not set
819CONFIG_FB=y
820# CONFIG_FB_CFB_FILLRECT is not set
821# CONFIG_FB_CFB_COPYAREA is not set
822# CONFIG_FB_CFB_IMAGEBLIT is not set
823# CONFIG_FB_SVGALIB is not set
824# CONFIG_FB_MACMODES is not set
825# CONFIG_FB_BACKLIGHT is not set
826# CONFIG_FB_MODE_HELPERS is not set
827# CONFIG_FB_TILEBLITTING is not set
828# CONFIG_FB_CIRRUS is not set
829# CONFIG_FB_PM2 is not set
830# CONFIG_FB_CYBER2000 is not set
831# CONFIG_FB_ASILIANT is not set
832# CONFIG_FB_IMSTT is not set
833# CONFIG_FB_S1D13XXX is not set
834# CONFIG_FB_NVIDIA is not set
835# CONFIG_FB_RIVA is not set
836# CONFIG_FB_MATROX is not set
837# CONFIG_FB_RADEON is not set
838# CONFIG_FB_ATY128 is not set
839# CONFIG_FB_ATY is not set
840# CONFIG_FB_S3 is not set
841# CONFIG_FB_SAVAGE is not set
842# CONFIG_FB_SIS is not set
843# CONFIG_FB_NEOMAGIC is not set
844# CONFIG_FB_KYRO is not set
845# CONFIG_FB_3DFX is not set
846# CONFIG_FB_VOODOO1 is not set
847# CONFIG_FB_SMIVGX is not set
848# CONFIG_FB_TRIDENT is not set
849# CONFIG_FB_VIRTUAL is not set
850
851#
852# Console display driver support
853#
854# CONFIG_VGA_CONSOLE is not set
855CONFIG_DUMMY_CONSOLE=y
856CONFIG_FRAMEBUFFER_CONSOLE=m
857# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
858# CONFIG_FONTS is not set
859CONFIG_FONT_8x8=y
860CONFIG_FONT_8x16=y
861
862#
863# Logo configuration
864#
865# CONFIG_LOGO is not set
866# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
867
868#
869# Sound
870#
871# CONFIG_SOUND is not set
872
873#
874# HID Devices
875#
876CONFIG_HID=y
877# CONFIG_HID_DEBUG is not set
878
879#
880# USB support
881#
882CONFIG_USB_ARCH_HAS_HCD=y
883CONFIG_USB_ARCH_HAS_OHCI=y
884CONFIG_USB_ARCH_HAS_EHCI=y
885CONFIG_USB=y
886# CONFIG_USB_DEBUG is not set
887
888#
889# Miscellaneous USB options
890#
891CONFIG_USB_DEVICEFS=y
892# CONFIG_USB_DYNAMIC_MINORS is not set
893# CONFIG_USB_SUSPEND is not set
894# CONFIG_USB_OTG is not set
895
896#
897# USB Host Controller Drivers
898#
899CONFIG_USB_EHCI_HCD=y
900# CONFIG_USB_EHCI_SPLIT_ISO is not set
901# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
902# CONFIG_USB_EHCI_TT_NEWSCHED is not set
903# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set
904# CONFIG_USB_ISP116X_HCD is not set
905CONFIG_USB_OHCI_HCD=y
906# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
907# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
908CONFIG_USB_OHCI_LITTLE_ENDIAN=y
909# CONFIG_USB_UHCI_HCD is not set
910# CONFIG_USB_SL811_HCD is not set
911
912#
913# USB Device Class drivers
914#
915# CONFIG_USB_ACM is not set
916# CONFIG_USB_PRINTER is not set
917
918#
919# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
920#
921
922#
923# may also be needed; see USB_STORAGE Help for more information
924#
925CONFIG_USB_STORAGE=y
926# CONFIG_USB_STORAGE_DEBUG is not set
927# CONFIG_USB_STORAGE_DATAFAB is not set
928# CONFIG_USB_STORAGE_FREECOM is not set
929# CONFIG_USB_STORAGE_DPCM is not set
930# CONFIG_USB_STORAGE_USBAT is not set
931# CONFIG_USB_STORAGE_SDDR09 is not set
932# CONFIG_USB_STORAGE_SDDR55 is not set
933# CONFIG_USB_STORAGE_JUMPSHOT is not set
934# CONFIG_USB_STORAGE_ALAUDA is not set
935# CONFIG_USB_STORAGE_KARMA is not set
936# CONFIG_USB_LIBUSUAL is not set
937
938#
939# USB Input Devices
940#
941CONFIG_USB_HID=m
942# CONFIG_USB_HIDINPUT_POWERBOOK is not set
943# CONFIG_HID_FF is not set
944# CONFIG_USB_HIDDEV is not set
945
946#
947# USB HID Boot Protocol drivers
948#
949# CONFIG_USB_KBD is not set
950# CONFIG_USB_MOUSE is not set
951# CONFIG_USB_AIPTEK is not set
952# CONFIG_USB_WACOM is not set
953# CONFIG_USB_ACECAD is not set
954# CONFIG_USB_KBTAB is not set
955# CONFIG_USB_POWERMATE is not set
956# CONFIG_USB_TOUCHSCREEN is not set
957# CONFIG_USB_YEALINK is not set
958# CONFIG_USB_XPAD is not set
959# CONFIG_USB_ATI_REMOTE is not set
960# CONFIG_USB_ATI_REMOTE2 is not set
961# CONFIG_USB_KEYSPAN_REMOTE is not set
962# CONFIG_USB_APPLETOUCH is not set
963# CONFIG_USB_GTCO is not set
964
965#
966# USB Imaging devices
967#
968# CONFIG_USB_MDC800 is not set
969# CONFIG_USB_MICROTEK is not set
970
971#
972# USB Network Adapters
973#
974# CONFIG_USB_CATC is not set
975# CONFIG_USB_KAWETH is not set
976# CONFIG_USB_PEGASUS is not set
977# CONFIG_USB_RTL8150 is not set
978# CONFIG_USB_USBNET_MII is not set
979# CONFIG_USB_USBNET is not set
980# CONFIG_USB_MON is not set
981
982#
983# USB port drivers
984#
985
986#
987# USB Serial Converter support
988#
989# CONFIG_USB_SERIAL is not set
990
991#
992# USB Miscellaneous drivers
993#
994# CONFIG_USB_EMI62 is not set
995# CONFIG_USB_EMI26 is not set
996# CONFIG_USB_ADUTUX is not set
997# CONFIG_USB_AUERSWALD is not set
998# CONFIG_USB_RIO500 is not set
999# CONFIG_USB_LEGOTOWER is not set
1000# CONFIG_USB_LCD is not set
1001# CONFIG_USB_BERRY_CHARGE is not set
1002# CONFIG_USB_LED is not set
1003# CONFIG_USB_CYPRESS_CY7C63 is not set
1004# CONFIG_USB_CYTHERM is not set
1005# CONFIG_USB_PHIDGET is not set
1006# CONFIG_USB_IDMOUSE is not set
1007# CONFIG_USB_FTDI_ELAN is not set
1008# CONFIG_USB_APPLEDISPLAY is not set
1009# CONFIG_USB_SISUSBVGA is not set
1010# CONFIG_USB_LD is not set
1011# CONFIG_USB_TRANCEVIBRATOR is not set
1012# CONFIG_USB_TEST is not set
1013
1014#
1015# USB DSL modem support
1016#
1017
1018#
1019# USB Gadget Support
1020#
1021# CONFIG_USB_GADGET is not set
1022
1023#
1024# MMC/SD Card support
1025#
1026# CONFIG_MMC is not set
1027
1028#
1029# LED devices
1030#
1031# CONFIG_NEW_LEDS is not set
1032
1033#
1034# LED drivers
1035#
1036
1037#
1038# LED Triggers
1039#
1040
1041#
1042# InfiniBand support
1043#
1044# CONFIG_INFINIBAND is not set
1045
1046#
1047# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
1048#
1049
1050#
1051# Real Time Clock
1052#
1053# CONFIG_RTC_CLASS is not set
1054
1055#
1056# DMA Engine support
1057#
1058# CONFIG_DMA_ENGINE is not set
1059
1060#
1061# DMA Clients
1062#
1063
1064#
1065# DMA Devices
1066#
1067
1068#
1069# Auxiliary Display support
1070#
1071
1072#
1073# Virtualization
1074#
1075
1076#
1077# File systems
1078#
1079CONFIG_EXT2_FS=y
1080# CONFIG_EXT2_FS_XATTR is not set
1081# CONFIG_EXT2_FS_XIP is not set
1082# CONFIG_EXT3_FS is not set
1083# CONFIG_EXT4DEV_FS is not set
1084# CONFIG_REISERFS_FS is not set
1085# CONFIG_JFS_FS is not set
1086CONFIG_FS_POSIX_ACL=y
1087# CONFIG_XFS_FS is not set
1088# CONFIG_GFS2_FS is not set
1089# CONFIG_OCFS2_FS is not set
1090# CONFIG_MINIX_FS is not set
1091# CONFIG_ROMFS_FS is not set
1092CONFIG_INOTIFY=y
1093CONFIG_INOTIFY_USER=y
1094# CONFIG_QUOTA is not set
1095# CONFIG_DNOTIFY is not set
1096# CONFIG_AUTOFS_FS is not set
1097# CONFIG_AUTOFS4_FS is not set
1098# CONFIG_FUSE_FS is not set
1099CONFIG_GENERIC_ACL=y
1100
1101#
1102# CD-ROM/DVD Filesystems
1103#
1104# CONFIG_ISO9660_FS is not set
1105# CONFIG_UDF_FS is not set
1106
1107#
1108# DOS/FAT/NT Filesystems
1109#
1110CONFIG_FAT_FS=m
1111CONFIG_MSDOS_FS=m
1112CONFIG_VFAT_FS=m
1113CONFIG_FAT_DEFAULT_CODEPAGE=437
1114CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1115# CONFIG_NTFS_FS is not set
1116
1117#
1118# Pseudo filesystems
1119#
1120CONFIG_PROC_FS=y
1121CONFIG_PROC_KCORE=y
1122CONFIG_PROC_SYSCTL=y
1123CONFIG_SYSFS=y
1124CONFIG_TMPFS=y
1125CONFIG_TMPFS_POSIX_ACL=y
1126# CONFIG_HUGETLB_PAGE is not set
1127CONFIG_RAMFS=y
1128CONFIG_CONFIGFS_FS=m
1129
1130#
1131# Miscellaneous filesystems
1132#
1133# CONFIG_ADFS_FS is not set
1134# CONFIG_AFFS_FS is not set
1135# CONFIG_HFS_FS is not set
1136# CONFIG_HFSPLUS_FS is not set
1137# CONFIG_BEFS_FS is not set
1138# CONFIG_BFS_FS is not set
1139# CONFIG_EFS_FS is not set
1140CONFIG_JFFS2_FS=y
1141CONFIG_JFFS2_FS_DEBUG=0
1142CONFIG_JFFS2_FS_WRITEBUFFER=y
1143# CONFIG_JFFS2_SUMMARY is not set
1144# CONFIG_JFFS2_FS_XATTR is not set
1145# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1146CONFIG_JFFS2_ZLIB=y
1147CONFIG_JFFS2_RTIME=y
1148# CONFIG_JFFS2_RUBIN is not set
1149# CONFIG_CRAMFS is not set
1150# CONFIG_VXFS_FS is not set
1151# CONFIG_HPFS_FS is not set
1152# CONFIG_QNX4FS_FS is not set
1153# CONFIG_SYSV_FS is not set
1154# CONFIG_UFS_FS is not set
1155
1156#
1157# Network File Systems
1158#
1159CONFIG_NFS_FS=y
1160CONFIG_NFS_V3=y
1161# CONFIG_NFS_V3_ACL is not set
1162# CONFIG_NFS_V4 is not set
1163# CONFIG_NFS_DIRECTIO is not set
1164# CONFIG_NFSD is not set
1165CONFIG_ROOT_NFS=y
1166CONFIG_LOCKD=y
1167CONFIG_LOCKD_V4=y
1168CONFIG_NFS_COMMON=y
1169CONFIG_SUNRPC=y
1170# CONFIG_RPCSEC_GSS_KRB5 is not set
1171# CONFIG_RPCSEC_GSS_SPKM3 is not set
1172# CONFIG_SMB_FS is not set
1173# CONFIG_CIFS is not set
1174# CONFIG_NCP_FS is not set
1175# CONFIG_CODA_FS is not set
1176# CONFIG_AFS_FS is not set
1177# CONFIG_9P_FS is not set
1178
1179#
1180# Partition Types
1181#
1182CONFIG_PARTITION_ADVANCED=y
1183# CONFIG_ACORN_PARTITION is not set
1184# CONFIG_OSF_PARTITION is not set
1185# CONFIG_AMIGA_PARTITION is not set
1186# CONFIG_ATARI_PARTITION is not set
1187# CONFIG_MAC_PARTITION is not set
1188CONFIG_MSDOS_PARTITION=y
1189# CONFIG_BSD_DISKLABEL is not set
1190# CONFIG_MINIX_SUBPARTITION is not set
1191# CONFIG_SOLARIS_X86_PARTITION is not set
1192# CONFIG_UNIXWARE_DISKLABEL is not set
1193# CONFIG_LDM_PARTITION is not set
1194# CONFIG_SGI_PARTITION is not set
1195# CONFIG_ULTRIX_PARTITION is not set
1196# CONFIG_SUN_PARTITION is not set
1197# CONFIG_KARMA_PARTITION is not set
1198# CONFIG_EFI_PARTITION is not set
1199
1200#
1201# Native Language Support
1202#
1203CONFIG_NLS=y
1204CONFIG_NLS_DEFAULT="iso8859-1"
1205CONFIG_NLS_CODEPAGE_437=m
1206# CONFIG_NLS_CODEPAGE_737 is not set
1207# CONFIG_NLS_CODEPAGE_775 is not set
1208CONFIG_NLS_CODEPAGE_850=m
1209# CONFIG_NLS_CODEPAGE_852 is not set
1210# CONFIG_NLS_CODEPAGE_855 is not set
1211# CONFIG_NLS_CODEPAGE_857 is not set
1212# CONFIG_NLS_CODEPAGE_860 is not set
1213# CONFIG_NLS_CODEPAGE_861 is not set
1214# CONFIG_NLS_CODEPAGE_862 is not set
1215# CONFIG_NLS_CODEPAGE_863 is not set
1216# CONFIG_NLS_CODEPAGE_864 is not set
1217# CONFIG_NLS_CODEPAGE_865 is not set
1218# CONFIG_NLS_CODEPAGE_866 is not set
1219# CONFIG_NLS_CODEPAGE_869 is not set
1220# CONFIG_NLS_CODEPAGE_936 is not set
1221# CONFIG_NLS_CODEPAGE_950 is not set
1222# CONFIG_NLS_CODEPAGE_932 is not set
1223# CONFIG_NLS_CODEPAGE_949 is not set
1224# CONFIG_NLS_CODEPAGE_874 is not set
1225# CONFIG_NLS_ISO8859_8 is not set
1226# CONFIG_NLS_CODEPAGE_1250 is not set
1227# CONFIG_NLS_CODEPAGE_1251 is not set
1228# CONFIG_NLS_ASCII is not set
1229CONFIG_NLS_ISO8859_1=m
1230# CONFIG_NLS_ISO8859_2 is not set
1231# CONFIG_NLS_ISO8859_3 is not set
1232# CONFIG_NLS_ISO8859_4 is not set
1233# CONFIG_NLS_ISO8859_5 is not set
1234# CONFIG_NLS_ISO8859_6 is not set
1235# CONFIG_NLS_ISO8859_7 is not set
1236# CONFIG_NLS_ISO8859_9 is not set
1237# CONFIG_NLS_ISO8859_13 is not set
1238# CONFIG_NLS_ISO8859_14 is not set
1239# CONFIG_NLS_ISO8859_15 is not set
1240# CONFIG_NLS_KOI8_R is not set
1241# CONFIG_NLS_KOI8_U is not set
1242# CONFIG_NLS_UTF8 is not set
1243
1244#
1245# Distributed Lock Manager
1246#
1247CONFIG_DLM=m
1248CONFIG_DLM_TCP=y
1249# CONFIG_DLM_SCTP is not set
1250# CONFIG_DLM_DEBUG is not set
1251
1252#
1253# Profiling support
1254#
1255# CONFIG_PROFILING is not set
1256
1257#
1258# Kernel hacking
1259#
1260CONFIG_TRACE_IRQFLAGS_SUPPORT=y
1261# CONFIG_PRINTK_TIME is not set
1262CONFIG_ENABLE_MUST_CHECK=y
1263# CONFIG_MAGIC_SYSRQ is not set
1264# CONFIG_UNUSED_SYMBOLS is not set
1265# CONFIG_DEBUG_FS is not set
1266# CONFIG_HEADERS_CHECK is not set
1267# CONFIG_DEBUG_KERNEL is not set
1268CONFIG_LOG_BUF_SHIFT=14
1269CONFIG_CROSSCOMPILE=y
1270CONFIG_CMDLINE=""
1271
1272#
1273# Security options
1274#
1275# CONFIG_KEYS is not set
1276# CONFIG_SECURITY is not set
1277
1278#
1279# Cryptographic options
1280#
1281CONFIG_CRYPTO=y
1282CONFIG_CRYPTO_ALGAPI=y
1283CONFIG_CRYPTO_BLKCIPHER=m
1284CONFIG_CRYPTO_HASH=m
1285CONFIG_CRYPTO_MANAGER=m
1286# CONFIG_CRYPTO_HMAC is not set
1287CONFIG_CRYPTO_XCBC=m
1288# CONFIG_CRYPTO_NULL is not set
1289# CONFIG_CRYPTO_MD4 is not set
1290CONFIG_CRYPTO_MD5=y
1291# CONFIG_CRYPTO_SHA1 is not set
1292# CONFIG_CRYPTO_SHA256 is not set
1293# CONFIG_CRYPTO_SHA512 is not set
1294# CONFIG_CRYPTO_WP512 is not set
1295# CONFIG_CRYPTO_TGR192 is not set
1296CONFIG_CRYPTO_GF128MUL=m
1297CONFIG_CRYPTO_ECB=m
1298CONFIG_CRYPTO_CBC=m
1299CONFIG_CRYPTO_PCBC=m
1300CONFIG_CRYPTO_LRW=m
1301# CONFIG_CRYPTO_DES is not set
1302CONFIG_CRYPTO_FCRYPT=m
1303# CONFIG_CRYPTO_BLOWFISH is not set
1304# CONFIG_CRYPTO_TWOFISH is not set
1305# CONFIG_CRYPTO_SERPENT is not set
1306# CONFIG_CRYPTO_AES is not set
1307# CONFIG_CRYPTO_CAST5 is not set
1308# CONFIG_CRYPTO_CAST6 is not set
1309# CONFIG_CRYPTO_TEA is not set
1310# CONFIG_CRYPTO_ARC4 is not set
1311# CONFIG_CRYPTO_KHAZAD is not set
1312# CONFIG_CRYPTO_ANUBIS is not set
1313# CONFIG_CRYPTO_DEFLATE is not set
1314# CONFIG_CRYPTO_MICHAEL_MIC is not set
1315# CONFIG_CRYPTO_CRC32C is not set
1316CONFIG_CRYPTO_CAMELLIA=m
1317# CONFIG_CRYPTO_TEST is not set
1318
1319#
1320# Hardware crypto devices
1321#
1322
1323#
1324# Library routines
1325#
1326CONFIG_BITREVERSE=y
1327# CONFIG_CRC_CCITT is not set
1328# CONFIG_CRC16 is not set
1329CONFIG_CRC32=y
1330# CONFIG_LIBCRC32C is not set
1331CONFIG_ZLIB_INFLATE=y
1332CONFIG_ZLIB_DEFLATE=y
1333CONFIG_PLIST=y
1334CONFIG_HAS_IOMEM=y
1335CONFIG_HAS_IOPORT=y
diff --git a/arch/mips/configs/fuloong2e_defconfig b/arch/mips/configs/fuloong2e_defconfig
index 0197f0de6b3f..a09dd03aa8c8 100644
--- a/arch/mips/configs/fuloong2e_defconfig
+++ b/arch/mips/configs/fuloong2e_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.31-rc1 3# Linux kernel version: 2.6.32-rc4
4# Thu Jul 2 22:37:00 2009 4# Fri Oct 16 13:18:01 2009
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7 7
@@ -10,8 +10,8 @@ CONFIG_MIPS=y
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_AR7 is not set 12# CONFIG_AR7 is not set
13# CONFIG_BASLER_EXCITE is not set
14# CONFIG_BCM47XX is not set 13# CONFIG_BCM47XX is not set
14# CONFIG_BCM63XX is not set
15# CONFIG_MIPS_COBALT is not set 15# CONFIG_MIPS_COBALT is not set
16# CONFIG_MACH_DECSTATION is not set 16# CONFIG_MACH_DECSTATION is not set
17# CONFIG_MACH_JAZZ is not set 17# CONFIG_MACH_JAZZ is not set
@@ -105,6 +105,8 @@ CONFIG_CPU_LOONGSON2E=y
105# CONFIG_CPU_RM9000 is not set 105# CONFIG_CPU_RM9000 is not set
106# CONFIG_CPU_SB1 is not set 106# CONFIG_CPU_SB1 is not set
107# CONFIG_CPU_CAVIUM_OCTEON is not set 107# CONFIG_CPU_CAVIUM_OCTEON is not set
108CONFIG_SYS_SUPPORTS_ZBOOT=y
109CONFIG_SYS_SUPPORTS_ZBOOT_UART16550=y
108CONFIG_CPU_LOONGSON2=y 110CONFIG_CPU_LOONGSON2=y
109CONFIG_SYS_HAS_CPU_LOONGSON2E=y 111CONFIG_SYS_HAS_CPU_LOONGSON2E=y
110CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y 112CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
@@ -135,12 +137,16 @@ CONFIG_SYS_SUPPORTS_HIGHMEM=y
135CONFIG_ARCH_FLATMEM_ENABLE=y 137CONFIG_ARCH_FLATMEM_ENABLE=y
136CONFIG_ARCH_POPULATES_NODE_MAP=y 138CONFIG_ARCH_POPULATES_NODE_MAP=y
137CONFIG_SELECT_MEMORY_MODEL=y 139CONFIG_SELECT_MEMORY_MODEL=y
138CONFIG_FLATMEM_MANUAL=y 140# CONFIG_FLATMEM_MANUAL is not set
139# CONFIG_DISCONTIGMEM_MANUAL is not set 141# CONFIG_DISCONTIGMEM_MANUAL is not set
140# CONFIG_SPARSEMEM_MANUAL is not set 142CONFIG_SPARSEMEM_MANUAL=y
141CONFIG_FLATMEM=y 143CONFIG_SPARSEMEM=y
142CONFIG_FLAT_NODE_MEM_MAP=y 144CONFIG_HAVE_MEMORY_PRESENT=y
143CONFIG_SPARSEMEM_STATIC=y 145CONFIG_SPARSEMEM_STATIC=y
146
147#
148# Memory hotplug is currently incompatible with Software Suspend
149#
144CONFIG_PAGEFLAGS_EXTENDED=y 150CONFIG_PAGEFLAGS_EXTENDED=y
145CONFIG_SPLIT_PTLOCK_CPUS=4 151CONFIG_SPLIT_PTLOCK_CPUS=4
146CONFIG_PHYS_ADDR_T_64BIT=y 152CONFIG_PHYS_ADDR_T_64BIT=y
@@ -148,6 +154,7 @@ CONFIG_ZONE_DMA_FLAG=0
148CONFIG_VIRT_TO_BUS=y 154CONFIG_VIRT_TO_BUS=y
149CONFIG_HAVE_MLOCK=y 155CONFIG_HAVE_MLOCK=y
150CONFIG_HAVE_MLOCKED_PAGE_BIT=y 156CONFIG_HAVE_MLOCKED_PAGE_BIT=y
157# CONFIG_KSM is not set
151CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 158CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
152CONFIG_TICK_ONESHOT=y 159CONFIG_TICK_ONESHOT=y
153CONFIG_NO_HZ=y 160CONFIG_NO_HZ=y
@@ -180,6 +187,12 @@ CONFIG_BROKEN_ON_SMP=y
180CONFIG_INIT_ENV_ARG_LIMIT=32 187CONFIG_INIT_ENV_ARG_LIMIT=32
181CONFIG_LOCALVERSION="-fuloong2e" 188CONFIG_LOCALVERSION="-fuloong2e"
182# CONFIG_LOCALVERSION_AUTO is not set 189# CONFIG_LOCALVERSION_AUTO is not set
190CONFIG_HAVE_KERNEL_GZIP=y
191CONFIG_HAVE_KERNEL_BZIP2=y
192CONFIG_HAVE_KERNEL_LZMA=y
193CONFIG_KERNEL_GZIP=y
194# CONFIG_KERNEL_BZIP2 is not set
195# CONFIG_KERNEL_LZMA is not set
183CONFIG_SWAP=y 196CONFIG_SWAP=y
184CONFIG_SYSVIPC=y 197CONFIG_SYSVIPC=y
185CONFIG_SYSVIPC_SYSCTL=y 198CONFIG_SYSVIPC_SYSCTL=y
@@ -193,11 +206,12 @@ CONFIG_BSD_PROCESS_ACCT=y
193# 206#
194# RCU Subsystem 207# RCU Subsystem
195# 208#
196CONFIG_CLASSIC_RCU=y 209CONFIG_TREE_RCU=y
197# CONFIG_TREE_RCU is not set 210# CONFIG_TREE_PREEMPT_RCU is not set
198# CONFIG_PREEMPT_RCU is not set 211# CONFIG_RCU_TRACE is not set
212CONFIG_RCU_FANOUT=64
213# CONFIG_RCU_FANOUT_EXACT is not set
199# CONFIG_TREE_RCU_TRACE is not set 214# CONFIG_TREE_RCU_TRACE is not set
200# CONFIG_PREEMPT_RCU_TRACE is not set
201CONFIG_IKCONFIG=y 215CONFIG_IKCONFIG=y
202CONFIG_IKCONFIG_PROC=y 216CONFIG_IKCONFIG_PROC=y
203CONFIG_LOG_BUF_SHIFT=14 217CONFIG_LOG_BUF_SHIFT=14
@@ -235,18 +249,16 @@ CONFIG_SHMEM=y
235CONFIG_AIO=y 249CONFIG_AIO=y
236 250
237# 251#
238# Performance Counters 252# Kernel Performance Events And Counters
239# 253#
240CONFIG_VM_EVENT_COUNTERS=y 254CONFIG_VM_EVENT_COUNTERS=y
241CONFIG_PCI_QUIRKS=y 255CONFIG_PCI_QUIRKS=y
242# CONFIG_STRIP_ASM_SYMS is not set
243# CONFIG_COMPAT_BRK is not set 256# CONFIG_COMPAT_BRK is not set
244CONFIG_SLAB=y 257CONFIG_SLAB=y
245# CONFIG_SLUB is not set 258# CONFIG_SLUB is not set
246# CONFIG_SLOB is not set 259# CONFIG_SLOB is not set
247CONFIG_PROFILING=y 260CONFIG_PROFILING=y
248CONFIG_TRACEPOINTS=y 261CONFIG_TRACEPOINTS=y
249CONFIG_MARKERS=y
250CONFIG_OPROFILE=m 262CONFIG_OPROFILE=m
251CONFIG_HAVE_OPROFILE=y 263CONFIG_HAVE_OPROFILE=y
252CONFIG_HAVE_SYSCALL_WRAPPERS=y 264CONFIG_HAVE_SYSCALL_WRAPPERS=y
@@ -255,8 +267,8 @@ CONFIG_HAVE_SYSCALL_WRAPPERS=y
255# GCOV-based kernel profiling 267# GCOV-based kernel profiling
256# 268#
257# CONFIG_GCOV_KERNEL is not set 269# CONFIG_GCOV_KERNEL is not set
258# CONFIG_SLOW_WORK is not set 270CONFIG_SLOW_WORK=y
259# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set 271CONFIG_HAVE_GENERIC_DMA_COHERENT=y
260CONFIG_SLABINFO=y 272CONFIG_SLABINFO=y
261CONFIG_RT_MUTEXES=y 273CONFIG_RT_MUTEXES=y
262CONFIG_BASE_SMALL=0 274CONFIG_BASE_SMALL=0
@@ -283,7 +295,7 @@ CONFIG_IOSCHED_CFQ=y
283CONFIG_DEFAULT_CFQ=y 295CONFIG_DEFAULT_CFQ=y
284# CONFIG_DEFAULT_NOOP is not set 296# CONFIG_DEFAULT_NOOP is not set
285CONFIG_DEFAULT_IOSCHED="cfq" 297CONFIG_DEFAULT_IOSCHED="cfq"
286# CONFIG_FREEZER is not set 298CONFIG_FREEZER=y
287 299
288# 300#
289# Bus options (PCI, PCMCIA, EISA, ISA, TC) 301# Bus options (PCI, PCMCIA, EISA, ISA, TC)
@@ -321,9 +333,14 @@ CONFIG_ARCH_HIBERNATION_POSSIBLE=y
321CONFIG_ARCH_SUSPEND_POSSIBLE=y 333CONFIG_ARCH_SUSPEND_POSSIBLE=y
322CONFIG_PM=y 334CONFIG_PM=y
323# CONFIG_PM_DEBUG is not set 335# CONFIG_PM_DEBUG is not set
336CONFIG_PM_SLEEP=y
324# CONFIG_SUSPEND is not set 337# CONFIG_SUSPEND is not set
325# CONFIG_HIBERNATION is not set 338CONFIG_HIBERNATION_NVS=y
339CONFIG_HIBERNATION=y
340CONFIG_PM_STD_PARTITION="/dev/hda3"
341# CONFIG_PM_RUNTIME is not set
326CONFIG_NET=y 342CONFIG_NET=y
343CONFIG_COMPAT_NETLINK_MESSAGES=y
327 344
328# 345#
329# Networking options 346# Networking options
@@ -442,6 +459,7 @@ CONFIG_IP_NF_ARPFILTER=m
442CONFIG_IP_NF_ARP_MANGLE=m 459CONFIG_IP_NF_ARP_MANGLE=m
443# CONFIG_IP_DCCP is not set 460# CONFIG_IP_DCCP is not set
444# CONFIG_IP_SCTP is not set 461# CONFIG_IP_SCTP is not set
462# CONFIG_RDS is not set
445# CONFIG_TIPC is not set 463# CONFIG_TIPC is not set
446# CONFIG_ATM is not set 464# CONFIG_ATM is not set
447# CONFIG_BRIDGE is not set 465# CONFIG_BRIDGE is not set
@@ -473,6 +491,7 @@ CONFIG_NET_CLS_ROUTE=y
473# CONFIG_AF_RXRPC is not set 491# CONFIG_AF_RXRPC is not set
474CONFIG_WIRELESS=y 492CONFIG_WIRELESS=y
475# CONFIG_CFG80211 is not set 493# CONFIG_CFG80211 is not set
494CONFIG_CFG80211_DEFAULT_PS_VALUE=0
476CONFIG_WIRELESS_OLD_REGULATORY=y 495CONFIG_WIRELESS_OLD_REGULATORY=y
477CONFIG_WIRELESS_EXT=y 496CONFIG_WIRELESS_EXT=y
478CONFIG_WIRELESS_EXT_SYSFS=y 497CONFIG_WIRELESS_EXT_SYSFS=y
@@ -481,7 +500,6 @@ CONFIG_WIRELESS_EXT_SYSFS=y
481# 500#
482# CFG80211 needs to be enabled for MAC80211 501# CFG80211 needs to be enabled for MAC80211
483# 502#
484CONFIG_MAC80211_DEFAULT_PS_VALUE=0
485# CONFIG_WIMAX is not set 503# CONFIG_WIMAX is not set
486# CONFIG_RFKILL is not set 504# CONFIG_RFKILL is not set
487CONFIG_NET_9P=m 505CONFIG_NET_9P=m
@@ -495,6 +513,7 @@ CONFIG_NET_9P=m
495# Generic Driver Options 513# Generic Driver Options
496# 514#
497CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 515CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
516# CONFIG_DEVTMPFS is not set
498CONFIG_STANDALONE=y 517CONFIG_STANDALONE=y
499CONFIG_PREVENT_FIRMWARE_BUILD=y 518CONFIG_PREVENT_FIRMWARE_BUILD=y
500CONFIG_FW_LOADER=m 519CONFIG_FW_LOADER=m
@@ -504,9 +523,9 @@ CONFIG_EXTRA_FIRMWARE=""
504# CONFIG_CONNECTOR is not set 523# CONFIG_CONNECTOR is not set
505CONFIG_MTD=m 524CONFIG_MTD=m
506# CONFIG_MTD_DEBUG is not set 525# CONFIG_MTD_DEBUG is not set
526# CONFIG_MTD_TESTS is not set
507# CONFIG_MTD_CONCAT is not set 527# CONFIG_MTD_CONCAT is not set
508# CONFIG_MTD_PARTITIONS is not set 528# CONFIG_MTD_PARTITIONS is not set
509# CONFIG_MTD_TESTS is not set
510 529
511# 530#
512# User Modules And Translation Layers 531# User Modules And Translation Layers
@@ -820,6 +839,7 @@ CONFIG_8139TOO=y
820# CONFIG_SUNDANCE is not set 839# CONFIG_SUNDANCE is not set
821# CONFIG_TLAN is not set 840# CONFIG_TLAN is not set
822# CONFIG_KS8842 is not set 841# CONFIG_KS8842 is not set
842# CONFIG_KS8851_MLL is not set
823# CONFIG_VIA_RHINE is not set 843# CONFIG_VIA_RHINE is not set
824# CONFIG_SC92031 is not set 844# CONFIG_SC92031 is not set
825# CONFIG_ATL2 is not set 845# CONFIG_ATL2 is not set
@@ -867,10 +887,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y
867# CONFIG_SFC is not set 887# CONFIG_SFC is not set
868# CONFIG_BE2NET is not set 888# CONFIG_BE2NET is not set
869# CONFIG_TR is not set 889# CONFIG_TR is not set
870 890CONFIG_WLAN=y
871#
872# Wireless LAN
873#
874# CONFIG_WLAN_PRE80211 is not set 891# CONFIG_WLAN_PRE80211 is not set
875# CONFIG_WLAN_80211 is not set 892# CONFIG_WLAN_80211 is not set
876 893
@@ -886,6 +903,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y
886# CONFIG_USB_PEGASUS is not set 903# CONFIG_USB_PEGASUS is not set
887# CONFIG_USB_RTL8150 is not set 904# CONFIG_USB_RTL8150 is not set
888# CONFIG_USB_USBNET is not set 905# CONFIG_USB_USBNET is not set
906# CONFIG_USB_CDC_PHONET is not set
889# CONFIG_WAN is not set 907# CONFIG_WAN is not set
890# CONFIG_FDDI is not set 908# CONFIG_FDDI is not set
891# CONFIG_HIPPI is not set 909# CONFIG_HIPPI is not set
@@ -933,12 +951,16 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
933# Input Device Drivers 951# Input Device Drivers
934# 952#
935CONFIG_INPUT_KEYBOARD=y 953CONFIG_INPUT_KEYBOARD=y
954# CONFIG_KEYBOARD_ADP5588 is not set
936CONFIG_KEYBOARD_ATKBD=y 955CONFIG_KEYBOARD_ATKBD=y
937# CONFIG_KEYBOARD_SUNKBD is not set 956# CONFIG_QT2160 is not set
938# CONFIG_KEYBOARD_LKKBD is not set 957# CONFIG_KEYBOARD_LKKBD is not set
939# CONFIG_KEYBOARD_XTKBD is not set 958# CONFIG_KEYBOARD_MAX7359 is not set
940# CONFIG_KEYBOARD_NEWTON is not set 959# CONFIG_KEYBOARD_NEWTON is not set
960# CONFIG_KEYBOARD_OPENCORES is not set
941# CONFIG_KEYBOARD_STOWAWAY is not set 961# CONFIG_KEYBOARD_STOWAWAY is not set
962# CONFIG_KEYBOARD_SUNKBD is not set
963# CONFIG_KEYBOARD_XTKBD is not set
942CONFIG_INPUT_MOUSE=y 964CONFIG_INPUT_MOUSE=y
943CONFIG_MOUSE_PS2=y 965CONFIG_MOUSE_PS2=y
944CONFIG_MOUSE_PS2_ALPS=y 966CONFIG_MOUSE_PS2_ALPS=y
@@ -946,6 +968,7 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y
946CONFIG_MOUSE_PS2_SYNAPTICS=y 968CONFIG_MOUSE_PS2_SYNAPTICS=y
947CONFIG_MOUSE_PS2_TRACKPOINT=y 969CONFIG_MOUSE_PS2_TRACKPOINT=y
948# CONFIG_MOUSE_PS2_ELANTECH is not set 970# CONFIG_MOUSE_PS2_ELANTECH is not set
971# CONFIG_MOUSE_PS2_SENTELIC is not set
949# CONFIG_MOUSE_PS2_TOUCHKIT is not set 972# CONFIG_MOUSE_PS2_TOUCHKIT is not set
950CONFIG_MOUSE_SERIAL=y 973CONFIG_MOUSE_SERIAL=y
951# CONFIG_MOUSE_APPLETOUCH is not set 974# CONFIG_MOUSE_APPLETOUCH is not set
@@ -1015,6 +1038,7 @@ CONFIG_RTC=y
1015CONFIG_DEVPORT=y 1038CONFIG_DEVPORT=y
1016CONFIG_I2C=m 1039CONFIG_I2C=m
1017CONFIG_I2C_BOARDINFO=y 1040CONFIG_I2C_BOARDINFO=y
1041CONFIG_I2C_COMPAT=y
1018CONFIG_I2C_CHARDEV=m 1042CONFIG_I2C_CHARDEV=m
1019CONFIG_I2C_HELPER_AUTO=y 1043CONFIG_I2C_HELPER_AUTO=y
1020 1044
@@ -1070,9 +1094,6 @@ CONFIG_I2C_VIAPRO=m
1070# Miscellaneous I2C Chip support 1094# Miscellaneous I2C Chip support
1071# 1095#
1072# CONFIG_DS1682 is not set 1096# CONFIG_DS1682 is not set
1073# CONFIG_SENSORS_PCF8574 is not set
1074# CONFIG_PCF8575 is not set
1075# CONFIG_SENSORS_PCA9539 is not set
1076# CONFIG_SENSORS_TSL2550 is not set 1097# CONFIG_SENSORS_TSL2550 is not set
1077# CONFIG_I2C_DEBUG_CORE is not set 1098# CONFIG_I2C_DEBUG_CORE is not set
1078# CONFIG_I2C_DEBUG_ALGO is not set 1099# CONFIG_I2C_DEBUG_ALGO is not set
@@ -1088,7 +1109,6 @@ CONFIG_I2C_VIAPRO=m
1088# CONFIG_POWER_SUPPLY is not set 1109# CONFIG_POWER_SUPPLY is not set
1089# CONFIG_HWMON is not set 1110# CONFIG_HWMON is not set
1090# CONFIG_THERMAL is not set 1111# CONFIG_THERMAL is not set
1091# CONFIG_THERMAL_HWMON is not set
1092# CONFIG_WATCHDOG is not set 1112# CONFIG_WATCHDOG is not set
1093CONFIG_SSB_POSSIBLE=y 1113CONFIG_SSB_POSSIBLE=y
1094 1114
@@ -1105,6 +1125,7 @@ CONFIG_SSB_POSSIBLE=y
1105# CONFIG_HTC_PASIC3 is not set 1125# CONFIG_HTC_PASIC3 is not set
1106# CONFIG_MFD_TMIO is not set 1126# CONFIG_MFD_TMIO is not set
1107# CONFIG_MFD_WM8400 is not set 1127# CONFIG_MFD_WM8400 is not set
1128# CONFIG_MFD_WM831X is not set
1108# CONFIG_MFD_WM8350_I2C is not set 1129# CONFIG_MFD_WM8350_I2C is not set
1109# CONFIG_MFD_PCF50633 is not set 1130# CONFIG_MFD_PCF50633 is not set
1110# CONFIG_AB3100_CORE is not set 1131# CONFIG_AB3100_CORE is not set
@@ -1114,6 +1135,7 @@ CONFIG_SSB_POSSIBLE=y
1114# 1135#
1115# Graphics support 1136# Graphics support
1116# 1137#
1138CONFIG_VGA_ARB=y
1117# CONFIG_DRM is not set 1139# CONFIG_DRM is not set
1118# CONFIG_VGASTATE is not set 1140# CONFIG_VGASTATE is not set
1119CONFIG_VIDEO_OUTPUT_CONTROL=m 1141CONFIG_VIDEO_OUTPUT_CONTROL=m
@@ -1198,6 +1220,7 @@ CONFIG_FONT_8x16=y
1198# CONFIG_LOGO is not set 1220# CONFIG_LOGO is not set
1199CONFIG_SOUND=y 1221CONFIG_SOUND=y
1200CONFIG_SOUND_OSS_CORE=y 1222CONFIG_SOUND_OSS_CORE=y
1223CONFIG_SOUND_OSS_CORE_PRECLAIM=y
1201CONFIG_SND=m 1224CONFIG_SND=m
1202CONFIG_SND_TIMER=m 1225CONFIG_SND_TIMER=m
1203CONFIG_SND_PCM=m 1226CONFIG_SND_PCM=m
@@ -1304,7 +1327,6 @@ CONFIG_SND_USB=y
1304CONFIG_AC97_BUS=m 1327CONFIG_AC97_BUS=m
1305CONFIG_HID_SUPPORT=y 1328CONFIG_HID_SUPPORT=y
1306CONFIG_HID=y 1329CONFIG_HID=y
1307# CONFIG_HID_DEBUG is not set
1308CONFIG_HIDRAW=y 1330CONFIG_HIDRAW=y
1309 1331
1310# 1332#
@@ -1356,6 +1378,7 @@ CONFIG_USB_EHCI_TT_NEWSCHED=y
1356# CONFIG_USB_OXU210HP_HCD is not set 1378# CONFIG_USB_OXU210HP_HCD is not set
1357# CONFIG_USB_ISP116X_HCD is not set 1379# CONFIG_USB_ISP116X_HCD is not set
1358CONFIG_USB_ISP1760_HCD=m 1380CONFIG_USB_ISP1760_HCD=m
1381# CONFIG_USB_ISP1362_HCD is not set
1359CONFIG_USB_OHCI_HCD=y 1382CONFIG_USB_OHCI_HCD=y
1360# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set 1383# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
1361# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set 1384# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
@@ -1453,6 +1476,7 @@ CONFIG_UIO_CIF=m
1453# CONFIG_UIO_SMX is not set 1476# CONFIG_UIO_SMX is not set
1454# CONFIG_UIO_AEC is not set 1477# CONFIG_UIO_AEC is not set
1455# CONFIG_UIO_SERCOS3 is not set 1478# CONFIG_UIO_SERCOS3 is not set
1479# CONFIG_UIO_PCI_GENERIC is not set
1456 1480
1457# 1481#
1458# TI VLYNQ 1482# TI VLYNQ
@@ -1469,10 +1493,10 @@ CONFIG_EXT3_FS=y
1469# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set 1493# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
1470# CONFIG_EXT3_FS_XATTR is not set 1494# CONFIG_EXT3_FS_XATTR is not set
1471CONFIG_EXT4_FS=m 1495CONFIG_EXT4_FS=m
1472CONFIG_EXT4DEV_COMPAT=y
1473CONFIG_EXT4_FS_XATTR=y 1496CONFIG_EXT4_FS_XATTR=y
1474CONFIG_EXT4_FS_POSIX_ACL=y 1497CONFIG_EXT4_FS_POSIX_ACL=y
1475CONFIG_EXT4_FS_SECURITY=y 1498CONFIG_EXT4_FS_SECURITY=y
1499# CONFIG_EXT4_DEBUG is not set
1476CONFIG_FS_XIP=y 1500CONFIG_FS_XIP=y
1477CONFIG_JBD=y 1501CONFIG_JBD=y
1478# CONFIG_JBD_DEBUG is not set 1502# CONFIG_JBD_DEBUG is not set
@@ -1489,6 +1513,7 @@ CONFIG_FS_POSIX_ACL=y
1489# CONFIG_GFS2_FS is not set 1513# CONFIG_GFS2_FS is not set
1490# CONFIG_OCFS2_FS is not set 1514# CONFIG_OCFS2_FS is not set
1491# CONFIG_BTRFS_FS is not set 1515# CONFIG_BTRFS_FS is not set
1516# CONFIG_NILFS2_FS is not set
1492CONFIG_FILE_LOCKING=y 1517CONFIG_FILE_LOCKING=y
1493CONFIG_FSNOTIFY=y 1518CONFIG_FSNOTIFY=y
1494CONFIG_DNOTIFY=y 1519CONFIG_DNOTIFY=y
@@ -1557,7 +1582,6 @@ CONFIG_OMFS_FS=m
1557# CONFIG_ROMFS_FS is not set 1582# CONFIG_ROMFS_FS is not set
1558# CONFIG_SYSV_FS is not set 1583# CONFIG_SYSV_FS is not set
1559# CONFIG_UFS_FS is not set 1584# CONFIG_UFS_FS is not set
1560# CONFIG_NILFS2_FS is not set
1561CONFIG_NETWORK_FILESYSTEMS=y 1585CONFIG_NETWORK_FILESYSTEMS=y
1562CONFIG_NFS_FS=m 1586CONFIG_NFS_FS=m
1563CONFIG_NFS_V3=y 1587CONFIG_NFS_V3=y
@@ -1666,6 +1690,7 @@ CONFIG_ENABLE_WARN_DEPRECATED=y
1666# CONFIG_ENABLE_MUST_CHECK is not set 1690# CONFIG_ENABLE_MUST_CHECK is not set
1667CONFIG_FRAME_WARN=2048 1691CONFIG_FRAME_WARN=2048
1668# CONFIG_MAGIC_SYSRQ is not set 1692# CONFIG_MAGIC_SYSRQ is not set
1693# CONFIG_STRIP_ASM_SYMS is not set
1669# CONFIG_UNUSED_SYMBOLS is not set 1694# CONFIG_UNUSED_SYMBOLS is not set
1670CONFIG_DEBUG_FS=y 1695CONFIG_DEBUG_FS=y
1671# CONFIG_HEADERS_CHECK is not set 1696# CONFIG_HEADERS_CHECK is not set
@@ -1678,13 +1703,14 @@ CONFIG_NOP_TRACER=y
1678CONFIG_RING_BUFFER=y 1703CONFIG_RING_BUFFER=y
1679CONFIG_EVENT_TRACING=y 1704CONFIG_EVENT_TRACING=y
1680CONFIG_CONTEXT_SWITCH_TRACER=y 1705CONFIG_CONTEXT_SWITCH_TRACER=y
1706CONFIG_RING_BUFFER_ALLOW_SWAP=y
1681CONFIG_TRACING=y 1707CONFIG_TRACING=y
1682CONFIG_TRACING_SUPPORT=y 1708CONFIG_TRACING_SUPPORT=y
1683# CONFIG_FTRACE is not set 1709# CONFIG_FTRACE is not set
1684# CONFIG_DYNAMIC_DEBUG is not set 1710# CONFIG_DYNAMIC_DEBUG is not set
1685# CONFIG_SAMPLES is not set 1711# CONFIG_SAMPLES is not set
1686CONFIG_HAVE_ARCH_KGDB=y 1712CONFIG_HAVE_ARCH_KGDB=y
1687CONFIG_CMDLINE="" 1713# CONFIG_CMDLINE_BOOL is not set
1688 1714
1689# 1715#
1690# Security options 1716# Security options
@@ -1742,11 +1768,13 @@ CONFIG_CRYPTO_XTS=m
1742# 1768#
1743CONFIG_CRYPTO_HMAC=y 1769CONFIG_CRYPTO_HMAC=y
1744# CONFIG_CRYPTO_XCBC is not set 1770# CONFIG_CRYPTO_XCBC is not set
1771# CONFIG_CRYPTO_VMAC is not set
1745 1772
1746# 1773#
1747# Digest 1774# Digest
1748# 1775#
1749# CONFIG_CRYPTO_CRC32C is not set 1776# CONFIG_CRYPTO_CRC32C is not set
1777CONFIG_CRYPTO_GHASH=m
1750# CONFIG_CRYPTO_MD4 is not set 1778# CONFIG_CRYPTO_MD4 is not set
1751CONFIG_CRYPTO_MD5=m 1779CONFIG_CRYPTO_MD5=m
1752# CONFIG_CRYPTO_MICHAEL_MIC is not set 1780# CONFIG_CRYPTO_MICHAEL_MIC is not set
diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig
index f14d38ba6034..222d7eca2fe4 100644
--- a/arch/mips/configs/ip22_defconfig
+++ b/arch/mips/configs/ip22_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set 12# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set 13# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set 14# CONFIG_MACH_DECSTATION is not set
@@ -1188,7 +1187,7 @@ CONFIG_DEBUG_MEMORY_INIT=y
1188CONFIG_DYNAMIC_PRINTK_DEBUG=y 1187CONFIG_DYNAMIC_PRINTK_DEBUG=y
1189# CONFIG_SAMPLES is not set 1188# CONFIG_SAMPLES is not set
1190CONFIG_HAVE_ARCH_KGDB=y 1189CONFIG_HAVE_ARCH_KGDB=y
1191CONFIG_CMDLINE="" 1190# CONFIG_CMDLINE_BOOL is not set
1192 1191
1193# 1192#
1194# Security options 1193# Security options
diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig
index 1fc73aa7b509..ed84b4cb3c8d 100644
--- a/arch/mips/configs/ip27_defconfig
+++ b/arch/mips/configs/ip27_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_MIPS_COBALT is not set 12# CONFIG_MIPS_COBALT is not set
14# CONFIG_MACH_DECSTATION is not set 13# CONFIG_MACH_DECSTATION is not set
15# CONFIG_MACH_JAZZ is not set 14# CONFIG_MACH_JAZZ is not set
@@ -940,7 +939,7 @@ CONFIG_ENABLE_MUST_CHECK=y
940# CONFIG_HEADERS_CHECK is not set 939# CONFIG_HEADERS_CHECK is not set
941# CONFIG_DEBUG_KERNEL is not set 940# CONFIG_DEBUG_KERNEL is not set
942CONFIG_CROSSCOMPILE=y 941CONFIG_CROSSCOMPILE=y
943CONFIG_CMDLINE="" 942# CONFIG_CMDLINE_BOOL is not set
944 943
945# 944#
946# Security options 945# Security options
diff --git a/arch/mips/configs/ip28_defconfig b/arch/mips/configs/ip28_defconfig
index 539dccb0345d..dab2e5aaadaf 100644
--- a/arch/mips/configs/ip28_defconfig
+++ b/arch/mips/configs/ip28_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set 12# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set 13# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set 14# CONFIG_MACH_DECSTATION is not set
@@ -816,7 +815,7 @@ CONFIG_MAGIC_SYSRQ=y
816# CONFIG_HEADERS_CHECK is not set 815# CONFIG_HEADERS_CHECK is not set
817# CONFIG_DEBUG_KERNEL is not set 816# CONFIG_DEBUG_KERNEL is not set
818# CONFIG_SAMPLES is not set 817# CONFIG_SAMPLES is not set
819CONFIG_CMDLINE="" 818# CONFIG_CMDLINE_BOOL is not set
820 819
821# 820#
822# Security options 821# Security options
diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig
index d934bdefb393..1841c88d3d24 100644
--- a/arch/mips/configs/ip32_defconfig
+++ b/arch/mips/configs/ip32_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set 12# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set 13# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set 14# CONFIG_MACH_DECSTATION is not set
@@ -1126,7 +1125,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y
1126# CONFIG_DYNAMIC_PRINTK_DEBUG is not set 1125# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
1127# CONFIG_SAMPLES is not set 1126# CONFIG_SAMPLES is not set
1128CONFIG_HAVE_ARCH_KGDB=y 1127CONFIG_HAVE_ARCH_KGDB=y
1129CONFIG_CMDLINE="" 1128# CONFIG_CMDLINE_BOOL is not set
1130 1129
1131# 1130#
1132# Security options 1131# Security options
diff --git a/arch/mips/configs/jazz_defconfig b/arch/mips/configs/jazz_defconfig
index d22df61833a8..14c2ab3b2674 100644
--- a/arch/mips/configs/jazz_defconfig
+++ b/arch/mips/configs/jazz_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
22# CONFIG_MIPS_DB1550 is not set 22# CONFIG_MIPS_DB1550 is not set
23# CONFIG_MIPS_DB1200 is not set 23# CONFIG_MIPS_DB1200 is not set
24# CONFIG_MIPS_MIRAGE is not set 24# CONFIG_MIPS_MIRAGE is not set
25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 25# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 26# CONFIG_MACH_DECSTATION is not set
28CONFIG_MACH_JAZZ=y 27CONFIG_MACH_JAZZ=y
@@ -1374,7 +1373,7 @@ CONFIG_ENABLE_MUST_CHECK=y
1374# CONFIG_DEBUG_KERNEL is not set 1373# CONFIG_DEBUG_KERNEL is not set
1375CONFIG_LOG_BUF_SHIFT=14 1374CONFIG_LOG_BUF_SHIFT=14
1376CONFIG_CROSSCOMPILE=y 1375CONFIG_CROSSCOMPILE=y
1377CONFIG_CMDLINE="" 1376# CONFIG_CMDLINE_BOOL is not set
1378 1377
1379# 1378#
1380# Security options 1379# Security options
diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig
index 5380f1f582d9..4d66c44cced8 100644
--- a/arch/mips/configs/jmr3927_defconfig
+++ b/arch/mips/configs/jmr3927_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set 12# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set 13# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set 14# CONFIG_MACH_DECSTATION is not set
@@ -835,7 +834,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y
835# CONFIG_DYNAMIC_PRINTK_DEBUG is not set 834# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
836# CONFIG_SAMPLES is not set 835# CONFIG_SAMPLES is not set
837CONFIG_HAVE_ARCH_KGDB=y 836CONFIG_HAVE_ARCH_KGDB=y
838CONFIG_CMDLINE="" 837# CONFIG_CMDLINE_BOOL is not set
839 838
840# 839#
841# Security options 840# Security options
diff --git a/arch/mips/configs/lasat_defconfig b/arch/mips/configs/lasat_defconfig
index 044074db7e55..08d481e3d42a 100644
--- a/arch/mips/configs/lasat_defconfig
+++ b/arch/mips/configs/lasat_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_MIPS_COBALT is not set 12# CONFIG_MIPS_COBALT is not set
14# CONFIG_MACH_DECSTATION is not set 13# CONFIG_MACH_DECSTATION is not set
15# CONFIG_MACH_JAZZ is not set 14# CONFIG_MACH_JAZZ is not set
@@ -798,7 +797,7 @@ CONFIG_MAGIC_SYSRQ=y
798# CONFIG_HEADERS_CHECK is not set 797# CONFIG_HEADERS_CHECK is not set
799# CONFIG_DEBUG_KERNEL is not set 798# CONFIG_DEBUG_KERNEL is not set
800CONFIG_CROSSCOMPILE=y 799CONFIG_CROSSCOMPILE=y
801CONFIG_CMDLINE="" 800# CONFIG_CMDLINE_BOOL is not set
802 801
803# 802#
804# Security options 803# Security options
diff --git a/arch/mips/configs/lemote2f_defconfig b/arch/mips/configs/lemote2f_defconfig
new file mode 100644
index 000000000000..b71a0a4fb95f
--- /dev/null
+++ b/arch/mips/configs/lemote2f_defconfig
@@ -0,0 +1,1835 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.32-rc6
4# Mon Nov 9 23:42:42 2009
5#
6CONFIG_MIPS=y
7
8#
9# Machine selection
10#
11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_AR7 is not set
13# CONFIG_BCM47XX is not set
14# CONFIG_BCM63XX is not set
15# CONFIG_MIPS_COBALT is not set
16# CONFIG_MACH_DECSTATION is not set
17# CONFIG_MACH_JAZZ is not set
18# CONFIG_LASAT is not set
19CONFIG_MACH_LOONGSON=y
20# CONFIG_MIPS_MALTA is not set
21# CONFIG_MIPS_SIM is not set
22# CONFIG_NEC_MARKEINS is not set
23# CONFIG_MACH_VR41XX is not set
24# CONFIG_NXP_STB220 is not set
25# CONFIG_NXP_STB225 is not set
26# CONFIG_PNX8550_JBS is not set
27# CONFIG_PNX8550_STB810 is not set
28# CONFIG_PMC_MSP is not set
29# CONFIG_PMC_YOSEMITE is not set
30# CONFIG_SGI_IP22 is not set
31# CONFIG_SGI_IP27 is not set
32# CONFIG_SGI_IP28 is not set
33# CONFIG_SGI_IP32 is not set
34# CONFIG_SIBYTE_CRHINE is not set
35# CONFIG_SIBYTE_CARMEL is not set
36# CONFIG_SIBYTE_CRHONE is not set
37# CONFIG_SIBYTE_RHONE is not set
38# CONFIG_SIBYTE_SWARM is not set
39# CONFIG_SIBYTE_LITTLESUR is not set
40# CONFIG_SIBYTE_SENTOSA is not set
41# CONFIG_SIBYTE_BIGSUR is not set
42# CONFIG_SNI_RM is not set
43# CONFIG_MACH_TX39XX is not set
44# CONFIG_MACH_TX49XX is not set
45# CONFIG_MIKROTIK_RB532 is not set
46# CONFIG_WR_PPMC is not set
47# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
48# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
49# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
50CONFIG_ARCH_SPARSEMEM_ENABLE=y
51# CONFIG_LEMOTE_FULOONG2E is not set
52CONFIG_LEMOTE_MACH2F=y
53CONFIG_CS5536=y
54CONFIG_RWSEM_GENERIC_SPINLOCK=y
55# CONFIG_ARCH_HAS_ILOG2_U32 is not set
56# CONFIG_ARCH_HAS_ILOG2_U64 is not set
57CONFIG_ARCH_SUPPORTS_OPROFILE=y
58CONFIG_GENERIC_FIND_NEXT_BIT=y
59CONFIG_GENERIC_HWEIGHT=y
60CONFIG_GENERIC_CALIBRATE_DELAY=y
61CONFIG_GENERIC_CLOCKEVENTS=y
62CONFIG_GENERIC_TIME=y
63CONFIG_GENERIC_CMOS_UPDATE=y
64CONFIG_SCHED_OMIT_FRAME_POINTER=y
65CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
66CONFIG_CEVT_R4K_LIB=y
67CONFIG_CEVT_R4K=y
68CONFIG_CSRC_R4K_LIB=y
69CONFIG_CSRC_R4K=y
70CONFIG_DMA_NONCOHERENT=y
71CONFIG_DMA_NEED_PCI_MAP_STATE=y
72CONFIG_EARLY_PRINTK=y
73CONFIG_SYS_HAS_EARLY_PRINTK=y
74CONFIG_I8259=y
75# CONFIG_NO_IOPORT is not set
76CONFIG_GENERIC_ISA_DMA=y
77CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y
78# CONFIG_CPU_BIG_ENDIAN is not set
79CONFIG_CPU_LITTLE_ENDIAN=y
80CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
81CONFIG_IRQ_CPU=y
82CONFIG_BOOT_ELF32=y
83CONFIG_MIPS_L1_CACHE_SHIFT=5
84
85#
86# CPU selection
87#
88# CONFIG_CPU_LOONGSON2E is not set
89CONFIG_CPU_LOONGSON2F=y
90# CONFIG_CPU_MIPS32_R1 is not set
91# CONFIG_CPU_MIPS32_R2 is not set
92# CONFIG_CPU_MIPS64_R1 is not set
93# CONFIG_CPU_MIPS64_R2 is not set
94# CONFIG_CPU_R3000 is not set
95# CONFIG_CPU_TX39XX is not set
96# CONFIG_CPU_VR41XX is not set
97# CONFIG_CPU_R4300 is not set
98# CONFIG_CPU_R4X00 is not set
99# CONFIG_CPU_TX49XX is not set
100# CONFIG_CPU_R5000 is not set
101# CONFIG_CPU_R5432 is not set
102# CONFIG_CPU_R5500 is not set
103# CONFIG_CPU_R6000 is not set
104# CONFIG_CPU_NEVADA is not set
105# CONFIG_CPU_R8000 is not set
106# CONFIG_CPU_R10000 is not set
107# CONFIG_CPU_RM7000 is not set
108# CONFIG_CPU_RM9000 is not set
109# CONFIG_CPU_SB1 is not set
110# CONFIG_CPU_CAVIUM_OCTEON is not set
111CONFIG_SYS_SUPPORTS_ZBOOT=y
112CONFIG_SYS_SUPPORTS_ZBOOT_UART16550=y
113CONFIG_CPU_LOONGSON2=y
114CONFIG_SYS_HAS_CPU_LOONGSON2F=y
115CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
116CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
117CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
118CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
119
120#
121# Kernel type
122#
123# CONFIG_32BIT is not set
124CONFIG_64BIT=y
125# CONFIG_PAGE_SIZE_4KB is not set
126# CONFIG_PAGE_SIZE_8KB is not set
127CONFIG_PAGE_SIZE_16KB=y
128# CONFIG_PAGE_SIZE_32KB is not set
129# CONFIG_PAGE_SIZE_64KB is not set
130CONFIG_BOARD_SCACHE=y
131CONFIG_MIPS_MT_DISABLED=y
132# CONFIG_MIPS_MT_SMP is not set
133# CONFIG_MIPS_MT_SMTC is not set
134CONFIG_CPU_HAS_WB=y
135CONFIG_CPU_HAS_SYNC=y
136CONFIG_GENERIC_HARDIRQS=y
137CONFIG_GENERIC_IRQ_PROBE=y
138CONFIG_CPU_SUPPORTS_HIGHMEM=y
139CONFIG_SYS_SUPPORTS_HIGHMEM=y
140CONFIG_ARCH_FLATMEM_ENABLE=y
141CONFIG_ARCH_POPULATES_NODE_MAP=y
142CONFIG_SELECT_MEMORY_MODEL=y
143# CONFIG_FLATMEM_MANUAL is not set
144# CONFIG_DISCONTIGMEM_MANUAL is not set
145CONFIG_SPARSEMEM_MANUAL=y
146CONFIG_SPARSEMEM=y
147CONFIG_HAVE_MEMORY_PRESENT=y
148CONFIG_SPARSEMEM_STATIC=y
149
150#
151# Memory hotplug is currently incompatible with Software Suspend
152#
153CONFIG_PAGEFLAGS_EXTENDED=y
154CONFIG_SPLIT_PTLOCK_CPUS=4
155CONFIG_PHYS_ADDR_T_64BIT=y
156CONFIG_ZONE_DMA_FLAG=0
157CONFIG_VIRT_TO_BUS=y
158CONFIG_HAVE_MLOCK=y
159CONFIG_HAVE_MLOCKED_PAGE_BIT=y
160# CONFIG_KSM is not set
161CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
162CONFIG_TICK_ONESHOT=y
163CONFIG_NO_HZ=y
164CONFIG_HIGH_RES_TIMERS=y
165CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
166# CONFIG_HZ_48 is not set
167# CONFIG_HZ_100 is not set
168# CONFIG_HZ_128 is not set
169CONFIG_HZ_250=y
170# CONFIG_HZ_256 is not set
171# CONFIG_HZ_1000 is not set
172# CONFIG_HZ_1024 is not set
173CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
174CONFIG_HZ=250
175# CONFIG_PREEMPT_NONE is not set
176# CONFIG_PREEMPT_VOLUNTARY is not set
177CONFIG_PREEMPT=y
178# CONFIG_KEXEC is not set
179# CONFIG_SECCOMP is not set
180CONFIG_LOCKDEP_SUPPORT=y
181CONFIG_STACKTRACE_SUPPORT=y
182CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
183CONFIG_CONSTRUCTORS=y
184
185#
186# General setup
187#
188CONFIG_EXPERIMENTAL=y
189CONFIG_BROKEN_ON_SMP=y
190CONFIG_LOCK_KERNEL=y
191CONFIG_INIT_ENV_ARG_LIMIT=32
192CONFIG_LOCALVERSION=""
193# CONFIG_LOCALVERSION_AUTO is not set
194CONFIG_HAVE_KERNEL_GZIP=y
195CONFIG_HAVE_KERNEL_BZIP2=y
196CONFIG_HAVE_KERNEL_LZMA=y
197# CONFIG_KERNEL_GZIP is not set
198# CONFIG_KERNEL_BZIP2 is not set
199CONFIG_KERNEL_LZMA=y
200CONFIG_SWAP=y
201CONFIG_SYSVIPC=y
202CONFIG_SYSVIPC_SYSCTL=y
203# CONFIG_POSIX_MQUEUE is not set
204CONFIG_BSD_PROCESS_ACCT=y
205CONFIG_BSD_PROCESS_ACCT_V3=y
206# CONFIG_TASKSTATS is not set
207CONFIG_AUDIT=y
208
209#
210# RCU Subsystem
211#
212CONFIG_TREE_RCU=y
213# CONFIG_TREE_PREEMPT_RCU is not set
214# CONFIG_RCU_TRACE is not set
215CONFIG_RCU_FANOUT=64
216# CONFIG_RCU_FANOUT_EXACT is not set
217# CONFIG_TREE_RCU_TRACE is not set
218CONFIG_IKCONFIG=y
219CONFIG_IKCONFIG_PROC=y
220CONFIG_LOG_BUF_SHIFT=15
221# CONFIG_GROUP_SCHED is not set
222# CONFIG_CGROUPS is not set
223CONFIG_SYSFS_DEPRECATED=y
224CONFIG_SYSFS_DEPRECATED_V2=y
225# CONFIG_RELAY is not set
226# CONFIG_NAMESPACES is not set
227# CONFIG_BLK_DEV_INITRD is not set
228# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
229CONFIG_SYSCTL=y
230CONFIG_ANON_INODES=y
231CONFIG_EMBEDDED=y
232CONFIG_SYSCTL_SYSCALL=y
233CONFIG_KALLSYMS=y
234# CONFIG_KALLSYMS_EXTRA_PASS is not set
235CONFIG_HOTPLUG=y
236CONFIG_PRINTK=y
237CONFIG_BUG=y
238CONFIG_ELF_CORE=y
239CONFIG_PCSPKR_PLATFORM=y
240CONFIG_BASE_FULL=y
241CONFIG_FUTEX=y
242CONFIG_EPOLL=y
243CONFIG_SIGNALFD=y
244CONFIG_TIMERFD=y
245CONFIG_EVENTFD=y
246CONFIG_SHMEM=y
247CONFIG_AIO=y
248
249#
250# Kernel Performance Events And Counters
251#
252CONFIG_VM_EVENT_COUNTERS=y
253CONFIG_PCI_QUIRKS=y
254CONFIG_SLUB_DEBUG=y
255CONFIG_COMPAT_BRK=y
256# CONFIG_SLAB is not set
257CONFIG_SLUB=y
258# CONFIG_SLOB is not set
259# CONFIG_PROFILING is not set
260CONFIG_HAVE_OPROFILE=y
261CONFIG_HAVE_SYSCALL_WRAPPERS=y
262
263#
264# GCOV-based kernel profiling
265#
266# CONFIG_SLOW_WORK is not set
267CONFIG_HAVE_GENERIC_DMA_COHERENT=y
268CONFIG_SLABINFO=y
269CONFIG_RT_MUTEXES=y
270CONFIG_BASE_SMALL=0
271CONFIG_MODULES=y
272# CONFIG_MODULE_FORCE_LOAD is not set
273CONFIG_MODULE_UNLOAD=y
274# CONFIG_MODULE_FORCE_UNLOAD is not set
275CONFIG_MODVERSIONS=y
276# CONFIG_MODULE_SRCVERSION_ALL is not set
277CONFIG_BLOCK=y
278CONFIG_BLK_DEV_BSG=y
279CONFIG_BLK_DEV_INTEGRITY=y
280CONFIG_BLOCK_COMPAT=y
281
282#
283# IO Schedulers
284#
285CONFIG_IOSCHED_NOOP=y
286CONFIG_IOSCHED_AS=y
287CONFIG_IOSCHED_DEADLINE=y
288CONFIG_IOSCHED_CFQ=y
289# CONFIG_DEFAULT_AS is not set
290# CONFIG_DEFAULT_DEADLINE is not set
291CONFIG_DEFAULT_CFQ=y
292# CONFIG_DEFAULT_NOOP is not set
293CONFIG_DEFAULT_IOSCHED="cfq"
294CONFIG_FREEZER=y
295
296#
297# Bus options (PCI, PCMCIA, EISA, ISA, TC)
298#
299CONFIG_HW_HAS_PCI=y
300CONFIG_PCI=y
301CONFIG_PCI_DOMAINS=y
302# CONFIG_ARCH_SUPPORTS_MSI is not set
303CONFIG_PCI_LEGACY=y
304# CONFIG_PCI_STUB is not set
305# CONFIG_PCI_IOV is not set
306CONFIG_ISA=y
307CONFIG_MMU=y
308# CONFIG_PCCARD is not set
309# CONFIG_HOTPLUG_PCI is not set
310
311#
312# Executable file formats
313#
314CONFIG_BINFMT_ELF=y
315# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
316# CONFIG_HAVE_AOUT is not set
317# CONFIG_BINFMT_MISC is not set
318CONFIG_MIPS32_COMPAT=y
319CONFIG_COMPAT=y
320CONFIG_SYSVIPC_COMPAT=y
321CONFIG_MIPS32_O32=y
322CONFIG_MIPS32_N32=y
323CONFIG_BINFMT_ELF32=y
324
325#
326# Power management options
327#
328CONFIG_ARCH_HIBERNATION_POSSIBLE=y
329CONFIG_ARCH_SUSPEND_POSSIBLE=y
330CONFIG_PM=y
331# CONFIG_PM_DEBUG is not set
332CONFIG_PM_SLEEP=y
333CONFIG_SUSPEND=y
334CONFIG_SUSPEND_FREEZER=y
335CONFIG_HIBERNATION_NVS=y
336CONFIG_HIBERNATION=y
337CONFIG_PM_STD_PARTITION="/dev/hda3"
338# CONFIG_PM_RUNTIME is not set
339CONFIG_NET=y
340CONFIG_COMPAT_NETLINK_MESSAGES=y
341
342#
343# Networking options
344#
345CONFIG_PACKET=y
346CONFIG_PACKET_MMAP=y
347CONFIG_UNIX=y
348CONFIG_XFRM=y
349# CONFIG_XFRM_USER is not set
350# CONFIG_XFRM_SUB_POLICY is not set
351# CONFIG_XFRM_MIGRATE is not set
352# CONFIG_XFRM_STATISTICS is not set
353# CONFIG_NET_KEY is not set
354CONFIG_INET=y
355CONFIG_IP_MULTICAST=y
356CONFIG_IP_ADVANCED_ROUTER=y
357CONFIG_ASK_IP_FIB_HASH=y
358# CONFIG_IP_FIB_TRIE is not set
359CONFIG_IP_FIB_HASH=y
360CONFIG_IP_MULTIPLE_TABLES=y
361CONFIG_IP_ROUTE_MULTIPATH=y
362CONFIG_IP_ROUTE_VERBOSE=y
363# CONFIG_IP_PNP is not set
364# CONFIG_NET_IPIP is not set
365# CONFIG_NET_IPGRE is not set
366CONFIG_IP_MROUTE=y
367CONFIG_IP_PIMSM_V1=y
368CONFIG_IP_PIMSM_V2=y
369# CONFIG_ARPD is not set
370CONFIG_SYN_COOKIES=y
371# CONFIG_INET_AH is not set
372# CONFIG_INET_ESP is not set
373# CONFIG_INET_IPCOMP is not set
374# CONFIG_INET_XFRM_TUNNEL is not set
375CONFIG_INET_TUNNEL=m
376CONFIG_INET_XFRM_MODE_TRANSPORT=m
377CONFIG_INET_XFRM_MODE_TUNNEL=m
378CONFIG_INET_XFRM_MODE_BEET=m
379CONFIG_INET_LRO=y
380CONFIG_INET_DIAG=y
381CONFIG_INET_TCP_DIAG=y
382CONFIG_TCP_CONG_ADVANCED=y
383CONFIG_TCP_CONG_BIC=y
384CONFIG_TCP_CONG_CUBIC=y
385CONFIG_TCP_CONG_WESTWOOD=m
386CONFIG_TCP_CONG_HTCP=m
387# CONFIG_TCP_CONG_HSTCP is not set
388# CONFIG_TCP_CONG_HYBLA is not set
389# CONFIG_TCP_CONG_VEGAS is not set
390# CONFIG_TCP_CONG_SCALABLE is not set
391# CONFIG_TCP_CONG_LP is not set
392# CONFIG_TCP_CONG_VENO is not set
393# CONFIG_TCP_CONG_YEAH is not set
394# CONFIG_TCP_CONG_ILLINOIS is not set
395CONFIG_DEFAULT_BIC=y
396# CONFIG_DEFAULT_CUBIC is not set
397# CONFIG_DEFAULT_HTCP is not set
398# CONFIG_DEFAULT_VEGAS is not set
399# CONFIG_DEFAULT_WESTWOOD is not set
400# CONFIG_DEFAULT_RENO is not set
401CONFIG_DEFAULT_TCP_CONG="bic"
402# CONFIG_TCP_MD5SIG is not set
403CONFIG_IPV6=m
404CONFIG_IPV6_PRIVACY=y
405# CONFIG_IPV6_ROUTER_PREF is not set
406# CONFIG_IPV6_OPTIMISTIC_DAD is not set
407# CONFIG_INET6_AH is not set
408# CONFIG_INET6_ESP is not set
409# CONFIG_INET6_IPCOMP is not set
410# CONFIG_IPV6_MIP6 is not set
411# CONFIG_INET6_XFRM_TUNNEL is not set
412# CONFIG_INET6_TUNNEL is not set
413CONFIG_INET6_XFRM_MODE_TRANSPORT=m
414CONFIG_INET6_XFRM_MODE_TUNNEL=m
415CONFIG_INET6_XFRM_MODE_BEET=m
416# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
417CONFIG_IPV6_SIT=m
418CONFIG_IPV6_NDISC_NODETYPE=y
419# CONFIG_IPV6_TUNNEL is not set
420# CONFIG_IPV6_MULTIPLE_TABLES is not set
421# CONFIG_IPV6_MROUTE is not set
422CONFIG_NETWORK_SECMARK=y
423CONFIG_NETFILTER=y
424# CONFIG_NETFILTER_DEBUG is not set
425CONFIG_NETFILTER_ADVANCED=y
426
427#
428# Core Netfilter Configuration
429#
430# CONFIG_NETFILTER_NETLINK_QUEUE is not set
431# CONFIG_NETFILTER_NETLINK_LOG is not set
432# CONFIG_NF_CONNTRACK is not set
433# CONFIG_NETFILTER_XTABLES is not set
434# CONFIG_IP_VS is not set
435
436#
437# IP: Netfilter Configuration
438#
439# CONFIG_NF_DEFRAG_IPV4 is not set
440# CONFIG_IP_NF_QUEUE is not set
441# CONFIG_IP_NF_IPTABLES is not set
442# CONFIG_IP_NF_ARPTABLES is not set
443
444#
445# IPv6: Netfilter Configuration
446#
447# CONFIG_IP6_NF_QUEUE is not set
448# CONFIG_IP6_NF_IPTABLES is not set
449# CONFIG_IP_DCCP is not set
450# CONFIG_IP_SCTP is not set
451# CONFIG_RDS is not set
452# CONFIG_TIPC is not set
453# CONFIG_ATM is not set
454# CONFIG_BRIDGE is not set
455# CONFIG_NET_DSA is not set
456# CONFIG_VLAN_8021Q is not set
457# CONFIG_DECNET is not set
458# CONFIG_LLC2 is not set
459# CONFIG_IPX is not set
460# CONFIG_ATALK is not set
461# CONFIG_X25 is not set
462# CONFIG_LAPB is not set
463# CONFIG_ECONET is not set
464# CONFIG_WAN_ROUTER is not set
465# CONFIG_PHONET is not set
466# CONFIG_IEEE802154 is not set
467CONFIG_NET_SCHED=y
468
469#
470# Queueing/Scheduling
471#
472# CONFIG_NET_SCH_CBQ is not set
473# CONFIG_NET_SCH_HTB is not set
474# CONFIG_NET_SCH_HFSC is not set
475# CONFIG_NET_SCH_PRIO is not set
476# CONFIG_NET_SCH_MULTIQ is not set
477# CONFIG_NET_SCH_RED is not set
478# CONFIG_NET_SCH_SFQ is not set
479# CONFIG_NET_SCH_TEQL is not set
480# CONFIG_NET_SCH_TBF is not set
481# CONFIG_NET_SCH_GRED is not set
482# CONFIG_NET_SCH_DSMARK is not set
483# CONFIG_NET_SCH_NETEM is not set
484# CONFIG_NET_SCH_DRR is not set
485# CONFIG_NET_SCH_INGRESS is not set
486
487#
488# Classification
489#
490CONFIG_NET_CLS=y
491# CONFIG_NET_CLS_BASIC is not set
492# CONFIG_NET_CLS_TCINDEX is not set
493# CONFIG_NET_CLS_ROUTE4 is not set
494# CONFIG_NET_CLS_FW is not set
495# CONFIG_NET_CLS_U32 is not set
496# CONFIG_NET_CLS_RSVP is not set
497# CONFIG_NET_CLS_RSVP6 is not set
498# CONFIG_NET_CLS_FLOW is not set
499CONFIG_NET_EMATCH=y
500CONFIG_NET_EMATCH_STACK=32
501# CONFIG_NET_EMATCH_CMP is not set
502# CONFIG_NET_EMATCH_NBYTE is not set
503# CONFIG_NET_EMATCH_U32 is not set
504# CONFIG_NET_EMATCH_META is not set
505# CONFIG_NET_EMATCH_TEXT is not set
506CONFIG_NET_CLS_ACT=y
507# CONFIG_NET_ACT_POLICE is not set
508# CONFIG_NET_ACT_GACT is not set
509# CONFIG_NET_ACT_MIRRED is not set
510# CONFIG_NET_ACT_NAT is not set
511# CONFIG_NET_ACT_PEDIT is not set
512# CONFIG_NET_ACT_SIMP is not set
513# CONFIG_NET_ACT_SKBEDIT is not set
514CONFIG_NET_SCH_FIFO=y
515# CONFIG_DCB is not set
516
517#
518# Network testing
519#
520# CONFIG_NET_PKTGEN is not set
521# CONFIG_HAMRADIO is not set
522# CONFIG_CAN is not set
523# CONFIG_IRDA is not set
524# CONFIG_BT is not set
525# CONFIG_AF_RXRPC is not set
526CONFIG_FIB_RULES=y
527CONFIG_WIRELESS=y
528# CONFIG_CFG80211 is not set
529CONFIG_CFG80211_DEFAULT_PS_VALUE=0
530# CONFIG_WIRELESS_OLD_REGULATORY is not set
531CONFIG_WIRELESS_EXT=y
532CONFIG_WIRELESS_EXT_SYSFS=y
533# CONFIG_LIB80211 is not set
534
535#
536# CFG80211 needs to be enabled for MAC80211
537#
538# CONFIG_WIMAX is not set
539CONFIG_RFKILL=m
540# CONFIG_RFKILL_INPUT is not set
541# CONFIG_NET_9P is not set
542
543#
544# Device Drivers
545#
546
547#
548# Generic Driver Options
549#
550CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
551# CONFIG_DEVTMPFS is not set
552CONFIG_STANDALONE=y
553CONFIG_PREVENT_FIRMWARE_BUILD=y
554CONFIG_FW_LOADER=y
555CONFIG_FIRMWARE_IN_KERNEL=y
556CONFIG_EXTRA_FIRMWARE=""
557# CONFIG_SYS_HYPERVISOR is not set
558# CONFIG_CONNECTOR is not set
559# CONFIG_MTD is not set
560# CONFIG_PARPORT is not set
561# CONFIG_PNP is not set
562CONFIG_BLK_DEV=y
563# CONFIG_BLK_CPQ_DA is not set
564# CONFIG_BLK_CPQ_CISS_DA is not set
565# CONFIG_BLK_DEV_DAC960 is not set
566# CONFIG_BLK_DEV_UMEM is not set
567# CONFIG_BLK_DEV_COW_COMMON is not set
568CONFIG_BLK_DEV_LOOP=y
569CONFIG_BLK_DEV_CRYPTOLOOP=y
570# CONFIG_BLK_DEV_NBD is not set
571# CONFIG_BLK_DEV_SX8 is not set
572# CONFIG_BLK_DEV_UB is not set
573CONFIG_BLK_DEV_RAM=y
574CONFIG_BLK_DEV_RAM_COUNT=16
575CONFIG_BLK_DEV_RAM_SIZE=8192
576# CONFIG_BLK_DEV_XIP is not set
577# CONFIG_CDROM_PKTCDVD is not set
578# CONFIG_ATA_OVER_ETH is not set
579# CONFIG_BLK_DEV_HD is not set
580CONFIG_MISC_DEVICES=y
581# CONFIG_PHANTOM is not set
582# CONFIG_SGI_IOC4 is not set
583# CONFIG_TIFM_CORE is not set
584# CONFIG_ENCLOSURE_SERVICES is not set
585# CONFIG_HP_ILO is not set
586# CONFIG_C2PORT is not set
587
588#
589# EEPROM support
590#
591# CONFIG_EEPROM_93CX6 is not set
592# CONFIG_CB710_CORE is not set
593CONFIG_HAVE_IDE=y
594CONFIG_IDE=y
595
596#
597# Please see Documentation/ide/ide.txt for help/info on IDE drives
598#
599CONFIG_IDE_XFER_MODE=y
600CONFIG_IDE_TIMINGS=y
601# CONFIG_BLK_DEV_IDE_SATA is not set
602CONFIG_IDE_GD=y
603CONFIG_IDE_GD_ATA=y
604# CONFIG_IDE_GD_ATAPI is not set
605# CONFIG_BLK_DEV_IDECD is not set
606# CONFIG_BLK_DEV_IDETAPE is not set
607CONFIG_IDE_TASK_IOCTL=y
608CONFIG_IDE_PROC_FS=y
609
610#
611# IDE chipset support/bugfixes
612#
613# CONFIG_IDE_GENERIC is not set
614# CONFIG_BLK_DEV_PLATFORM is not set
615CONFIG_BLK_DEV_IDEDMA_SFF=y
616
617#
618# PCI IDE chipsets support
619#
620CONFIG_BLK_DEV_IDEPCI=y
621# CONFIG_IDEPCI_PCIBUS_ORDER is not set
622# CONFIG_BLK_DEV_OFFBOARD is not set
623CONFIG_BLK_DEV_GENERIC=y
624# CONFIG_BLK_DEV_OPTI621 is not set
625CONFIG_BLK_DEV_IDEDMA_PCI=y
626# CONFIG_BLK_DEV_AEC62XX is not set
627# CONFIG_BLK_DEV_ALI15X3 is not set
628CONFIG_BLK_DEV_AMD74XX=y
629# CONFIG_BLK_DEV_CMD64X is not set
630# CONFIG_BLK_DEV_TRIFLEX is not set
631# CONFIG_BLK_DEV_CS5520 is not set
632# CONFIG_BLK_DEV_CS5530 is not set
633# CONFIG_BLK_DEV_HPT366 is not set
634# CONFIG_BLK_DEV_JMICRON is not set
635# CONFIG_BLK_DEV_SC1200 is not set
636# CONFIG_BLK_DEV_PIIX is not set
637# CONFIG_BLK_DEV_IT8172 is not set
638# CONFIG_BLK_DEV_IT8213 is not set
639# CONFIG_BLK_DEV_IT821X is not set
640# CONFIG_BLK_DEV_NS87415 is not set
641# CONFIG_BLK_DEV_PDC202XX_OLD is not set
642# CONFIG_BLK_DEV_PDC202XX_NEW is not set
643# CONFIG_BLK_DEV_SVWKS is not set
644# CONFIG_BLK_DEV_SIIMAGE is not set
645# CONFIG_BLK_DEV_SLC90E66 is not set
646# CONFIG_BLK_DEV_TRM290 is not set
647# CONFIG_BLK_DEV_VIA82CXXX is not set
648# CONFIG_BLK_DEV_TC86C001 is not set
649
650#
651# Other IDE chipsets support
652#
653
654#
655# Note: most of these also require special kernel boot parameters
656#
657# CONFIG_BLK_DEV_4DRIVES is not set
658# CONFIG_BLK_DEV_ALI14XX is not set
659# CONFIG_BLK_DEV_DTC2278 is not set
660# CONFIG_BLK_DEV_HT6560B is not set
661# CONFIG_BLK_DEV_QD65XX is not set
662# CONFIG_BLK_DEV_UMC8672 is not set
663CONFIG_BLK_DEV_IDEDMA=y
664
665#
666# SCSI device support
667#
668# CONFIG_RAID_ATTRS is not set
669CONFIG_SCSI=m
670CONFIG_SCSI_DMA=y
671# CONFIG_SCSI_TGT is not set
672# CONFIG_SCSI_NETLINK is not set
673CONFIG_SCSI_PROC_FS=y
674
675#
676# SCSI support type (disk, tape, CD-ROM)
677#
678CONFIG_BLK_DEV_SD=m
679# CONFIG_CHR_DEV_ST is not set
680# CONFIG_CHR_DEV_OSST is not set
681# CONFIG_BLK_DEV_SR is not set
682CONFIG_CHR_DEV_SG=m
683# CONFIG_CHR_DEV_SCH is not set
684CONFIG_SCSI_MULTI_LUN=y
685# CONFIG_SCSI_CONSTANTS is not set
686# CONFIG_SCSI_LOGGING is not set
687# CONFIG_SCSI_SCAN_ASYNC is not set
688CONFIG_SCSI_WAIT_SCAN=m
689
690#
691# SCSI Transports
692#
693# CONFIG_SCSI_SPI_ATTRS is not set
694# CONFIG_SCSI_FC_ATTRS is not set
695# CONFIG_SCSI_ISCSI_ATTRS is not set
696# CONFIG_SCSI_SAS_ATTRS is not set
697# CONFIG_SCSI_SAS_LIBSAS is not set
698# CONFIG_SCSI_SRP_ATTRS is not set
699# CONFIG_SCSI_LOWLEVEL is not set
700# CONFIG_SCSI_DH is not set
701# CONFIG_SCSI_OSD_INITIATOR is not set
702# CONFIG_ATA is not set
703# CONFIG_MD is not set
704# CONFIG_FUSION is not set
705
706#
707# IEEE 1394 (FireWire) support
708#
709
710#
711# You can enable one or both FireWire driver stacks.
712#
713
714#
715# See the help texts for more information.
716#
717# CONFIG_FIREWIRE is not set
718# CONFIG_IEEE1394 is not set
719# CONFIG_I2O is not set
720CONFIG_NETDEVICES=y
721# CONFIG_IFB is not set
722# CONFIG_DUMMY is not set
723# CONFIG_BONDING is not set
724# CONFIG_MACVLAN is not set
725# CONFIG_EQUALIZER is not set
726# CONFIG_TUN is not set
727# CONFIG_VETH is not set
728# CONFIG_ARCNET is not set
729# CONFIG_PHYLIB is not set
730CONFIG_NET_ETHERNET=y
731CONFIG_MII=y
732# CONFIG_AX88796 is not set
733# CONFIG_HAPPYMEAL is not set
734# CONFIG_SUNGEM is not set
735# CONFIG_CASSINI is not set
736# CONFIG_NET_VENDOR_3COM is not set
737# CONFIG_NET_VENDOR_SMC is not set
738# CONFIG_SMC91X is not set
739# CONFIG_DM9000 is not set
740# CONFIG_ETHOC is not set
741# CONFIG_NET_VENDOR_RACAL is not set
742# CONFIG_DNET is not set
743# CONFIG_NET_TULIP is not set
744# CONFIG_AT1700 is not set
745# CONFIG_DEPCA is not set
746# CONFIG_HP100 is not set
747# CONFIG_NET_ISA is not set
748# CONFIG_IBM_NEW_EMAC_ZMII is not set
749# CONFIG_IBM_NEW_EMAC_RGMII is not set
750# CONFIG_IBM_NEW_EMAC_TAH is not set
751# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
752# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
753# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
754# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
755CONFIG_NET_PCI=y
756# CONFIG_PCNET32 is not set
757# CONFIG_AMD8111_ETH is not set
758# CONFIG_ADAPTEC_STARFIRE is not set
759# CONFIG_AC3200 is not set
760# CONFIG_APRICOT is not set
761# CONFIG_B44 is not set
762# CONFIG_FORCEDETH is not set
763# CONFIG_CS89x0 is not set
764# CONFIG_TC35815 is not set
765# CONFIG_E100 is not set
766# CONFIG_FEALNX is not set
767# CONFIG_NATSEMI is not set
768# CONFIG_NE2K_PCI is not set
769# CONFIG_8139CP is not set
770CONFIG_8139TOO=y
771# CONFIG_8139TOO_PIO is not set
772CONFIG_8139TOO_TUNE_TWISTER=y
773# CONFIG_8139TOO_8129 is not set
774# CONFIG_8139_OLD_RX_RESET is not set
775# CONFIG_R6040 is not set
776# CONFIG_SIS900 is not set
777# CONFIG_EPIC100 is not set
778# CONFIG_SMSC9420 is not set
779# CONFIG_SUNDANCE is not set
780# CONFIG_TLAN is not set
781# CONFIG_KS8842 is not set
782# CONFIG_KS8851_MLL is not set
783# CONFIG_VIA_RHINE is not set
784# CONFIG_SC92031 is not set
785# CONFIG_ATL2 is not set
786CONFIG_NETDEV_1000=y
787# CONFIG_ACENIC is not set
788# CONFIG_DL2K is not set
789# CONFIG_E1000 is not set
790# CONFIG_E1000E is not set
791# CONFIG_IP1000 is not set
792# CONFIG_IGB is not set
793# CONFIG_IGBVF is not set
794# CONFIG_NS83820 is not set
795# CONFIG_HAMACHI is not set
796# CONFIG_YELLOWFIN is not set
797CONFIG_R8169=y
798# CONFIG_SIS190 is not set
799# CONFIG_SKGE is not set
800# CONFIG_SKY2 is not set
801# CONFIG_VIA_VELOCITY is not set
802# CONFIG_TIGON3 is not set
803# CONFIG_BNX2 is not set
804# CONFIG_CNIC is not set
805# CONFIG_QLA3XXX is not set
806# CONFIG_ATL1 is not set
807# CONFIG_ATL1E is not set
808# CONFIG_ATL1C is not set
809# CONFIG_JME is not set
810# CONFIG_NETDEV_10000 is not set
811# CONFIG_TR is not set
812CONFIG_WLAN=y
813CONFIG_WLAN_PRE80211=y
814# CONFIG_STRIP is not set
815# CONFIG_WAVELAN is not set
816CONFIG_WLAN_80211=y
817# CONFIG_LIBERTAS is not set
818# CONFIG_ATMEL is not set
819# CONFIG_PRISM54 is not set
820# CONFIG_USB_ZD1201 is not set
821# CONFIG_HOSTAP is not set
822
823#
824# Enable WiMAX (Networking options) to see the WiMAX drivers
825#
826
827#
828# USB Network Adapters
829#
830# CONFIG_USB_CATC is not set
831# CONFIG_USB_KAWETH is not set
832# CONFIG_USB_PEGASUS is not set
833# CONFIG_USB_RTL8150 is not set
834# CONFIG_USB_USBNET is not set
835# CONFIG_USB_HSO is not set
836# CONFIG_WAN is not set
837# CONFIG_FDDI is not set
838# CONFIG_HIPPI is not set
839# CONFIG_PPP is not set
840# CONFIG_SLIP is not set
841# CONFIG_NET_FC is not set
842# CONFIG_NETCONSOLE is not set
843# CONFIG_NETPOLL is not set
844# CONFIG_NET_POLL_CONTROLLER is not set
845# CONFIG_ISDN is not set
846# CONFIG_PHONE is not set
847
848#
849# Input device support
850#
851CONFIG_INPUT=y
852# CONFIG_INPUT_FF_MEMLESS is not set
853# CONFIG_INPUT_POLLDEV is not set
854
855#
856# Userland interfaces
857#
858CONFIG_INPUT_MOUSEDEV=y
859CONFIG_INPUT_MOUSEDEV_PSAUX=y
860CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
861CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
862# CONFIG_INPUT_JOYDEV is not set
863CONFIG_INPUT_EVDEV=y
864# CONFIG_INPUT_EVBUG is not set
865
866#
867# Input Device Drivers
868#
869CONFIG_INPUT_KEYBOARD=y
870CONFIG_KEYBOARD_ATKBD=y
871# CONFIG_KEYBOARD_LKKBD is not set
872# CONFIG_KEYBOARD_NEWTON is not set
873# CONFIG_KEYBOARD_OPENCORES is not set
874# CONFIG_KEYBOARD_STOWAWAY is not set
875# CONFIG_KEYBOARD_SUNKBD is not set
876# CONFIG_KEYBOARD_XTKBD is not set
877CONFIG_INPUT_MOUSE=y
878CONFIG_MOUSE_PS2=y
879# CONFIG_MOUSE_PS2_ALPS is not set
880# CONFIG_MOUSE_PS2_LOGIPS2PP is not set
881CONFIG_MOUSE_PS2_SYNAPTICS=y
882# CONFIG_MOUSE_PS2_TRACKPOINT is not set
883# CONFIG_MOUSE_PS2_ELANTECH is not set
884# CONFIG_MOUSE_PS2_SENTELIC is not set
885# CONFIG_MOUSE_PS2_TOUCHKIT is not set
886# CONFIG_MOUSE_SERIAL is not set
887# CONFIG_MOUSE_APPLETOUCH is not set
888# CONFIG_MOUSE_BCM5974 is not set
889# CONFIG_MOUSE_INPORT is not set
890# CONFIG_MOUSE_LOGIBM is not set
891# CONFIG_MOUSE_PC110PAD is not set
892# CONFIG_MOUSE_VSXXXAA is not set
893# CONFIG_INPUT_JOYSTICK is not set
894# CONFIG_INPUT_TABLET is not set
895# CONFIG_INPUT_TOUCHSCREEN is not set
896# CONFIG_INPUT_MISC is not set
897
898#
899# Hardware I/O ports
900#
901CONFIG_SERIO=y
902CONFIG_SERIO_I8042=y
903# CONFIG_SERIO_SERPORT is not set
904# CONFIG_SERIO_PCIPS2 is not set
905CONFIG_SERIO_LIBPS2=y
906# CONFIG_SERIO_RAW is not set
907# CONFIG_GAMEPORT is not set
908
909#
910# Character devices
911#
912CONFIG_VT=y
913CONFIG_CONSOLE_TRANSLATIONS=y
914CONFIG_VT_CONSOLE=y
915CONFIG_HW_CONSOLE=y
916# CONFIG_VT_HW_CONSOLE_BINDING is not set
917CONFIG_DEVKMEM=y
918CONFIG_SERIAL_NONSTANDARD=y
919# CONFIG_COMPUTONE is not set
920# CONFIG_ROCKETPORT is not set
921# CONFIG_CYCLADES is not set
922# CONFIG_DIGIEPCA is not set
923# CONFIG_MOXA_INTELLIO is not set
924# CONFIG_MOXA_SMARTIO is not set
925# CONFIG_ISI is not set
926# CONFIG_SYNCLINKMP is not set
927# CONFIG_SYNCLINK_GT is not set
928# CONFIG_N_HDLC is not set
929# CONFIG_RISCOM8 is not set
930# CONFIG_SPECIALIX is not set
931# CONFIG_STALDRV is not set
932# CONFIG_NOZOMI is not set
933
934#
935# Serial drivers
936#
937CONFIG_SERIAL_8250=y
938CONFIG_SERIAL_8250_CONSOLE=y
939# CONFIG_SERIAL_8250_PCI is not set
940CONFIG_SERIAL_8250_NR_UARTS=16
941CONFIG_SERIAL_8250_RUNTIME_UARTS=4
942CONFIG_SERIAL_8250_EXTENDED=y
943CONFIG_SERIAL_8250_MANY_PORTS=y
944CONFIG_SERIAL_8250_FOURPORT=y
945# CONFIG_SERIAL_8250_ACCENT is not set
946# CONFIG_SERIAL_8250_BOCA is not set
947# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set
948# CONFIG_SERIAL_8250_HUB6 is not set
949# CONFIG_SERIAL_8250_SHARE_IRQ is not set
950# CONFIG_SERIAL_8250_DETECT_IRQ is not set
951# CONFIG_SERIAL_8250_RSA is not set
952
953#
954# Non-8250 serial port support
955#
956CONFIG_SERIAL_CORE=y
957CONFIG_SERIAL_CORE_CONSOLE=y
958# CONFIG_SERIAL_JSM is not set
959CONFIG_UNIX98_PTYS=y
960# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
961CONFIG_LEGACY_PTYS=y
962CONFIG_LEGACY_PTY_COUNT=16
963# CONFIG_IPMI_HANDLER is not set
964CONFIG_HW_RANDOM=y
965# CONFIG_HW_RANDOM_TIMERIOMEM is not set
966CONFIG_RTC=y
967# CONFIG_DTLK is not set
968# CONFIG_R3964 is not set
969# CONFIG_APPLICOM is not set
970# CONFIG_RAW_DRIVER is not set
971# CONFIG_TCG_TPM is not set
972CONFIG_DEVPORT=y
973# CONFIG_I2C is not set
974# CONFIG_SPI is not set
975
976#
977# PPS support
978#
979# CONFIG_PPS is not set
980# CONFIG_W1 is not set
981# CONFIG_POWER_SUPPLY is not set
982CONFIG_HWMON=y
983# CONFIG_HWMON_VID is not set
984# CONFIG_HWMON_DEBUG_CHIP is not set
985
986#
987# Native drivers
988#
989# CONFIG_SENSORS_I5K_AMB is not set
990# CONFIG_SENSORS_F71805F is not set
991# CONFIG_SENSORS_F71882FG is not set
992# CONFIG_SENSORS_IT87 is not set
993# CONFIG_SENSORS_PC87360 is not set
994# CONFIG_SENSORS_PC87427 is not set
995# CONFIG_SENSORS_SIS5595 is not set
996# CONFIG_SENSORS_SMSC47M1 is not set
997# CONFIG_SENSORS_SMSC47B397 is not set
998# CONFIG_SENSORS_VIA686A is not set
999# CONFIG_SENSORS_VT1211 is not set
1000# CONFIG_SENSORS_VT8231 is not set
1001# CONFIG_SENSORS_W83627HF is not set
1002# CONFIG_SENSORS_W83627EHF is not set
1003CONFIG_THERMAL=y
1004# CONFIG_THERMAL_HWMON is not set
1005# CONFIG_WATCHDOG is not set
1006CONFIG_SSB_POSSIBLE=y
1007
1008#
1009# Sonics Silicon Backplane
1010#
1011# CONFIG_SSB is not set
1012
1013#
1014# Multifunction device drivers
1015#
1016# CONFIG_MFD_CORE is not set
1017# CONFIG_MFD_SM501 is not set
1018# CONFIG_HTC_PASIC3 is not set
1019# CONFIG_MFD_TMIO is not set
1020# CONFIG_REGULATOR is not set
1021CONFIG_MEDIA_SUPPORT=m
1022
1023#
1024# Multimedia core support
1025#
1026CONFIG_VIDEO_DEV=m
1027CONFIG_VIDEO_V4L2_COMMON=m
1028CONFIG_VIDEO_ALLOW_V4L1=y
1029CONFIG_VIDEO_V4L1_COMPAT=y
1030# CONFIG_DVB_CORE is not set
1031CONFIG_VIDEO_MEDIA=m
1032
1033#
1034# Multimedia drivers
1035#
1036# CONFIG_MEDIA_ATTACH is not set
1037CONFIG_VIDEO_V4L2=m
1038CONFIG_VIDEO_V4L1=m
1039CONFIG_VIDEO_CAPTURE_DRIVERS=y
1040# CONFIG_VIDEO_ADV_DEBUG is not set
1041# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
1042CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
1043# CONFIG_VIDEO_VIVI is not set
1044# CONFIG_VIDEO_PMS is not set
1045# CONFIG_VIDEO_CPIA is not set
1046# CONFIG_VIDEO_CPIA2 is not set
1047# CONFIG_VIDEO_STRADIS is not set
1048CONFIG_V4L_USB_DRIVERS=y
1049CONFIG_USB_VIDEO_CLASS=m
1050CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
1051CONFIG_USB_GSPCA=m
1052# CONFIG_USB_M5602 is not set
1053# CONFIG_USB_STV06XX is not set
1054# CONFIG_USB_GL860 is not set
1055# CONFIG_USB_GSPCA_CONEX is not set
1056# CONFIG_USB_GSPCA_ETOMS is not set
1057# CONFIG_USB_GSPCA_FINEPIX is not set
1058# CONFIG_USB_GSPCA_JEILINJ is not set
1059# CONFIG_USB_GSPCA_MARS is not set
1060# CONFIG_USB_GSPCA_MR97310A is not set
1061# CONFIG_USB_GSPCA_OV519 is not set
1062# CONFIG_USB_GSPCA_OV534 is not set
1063# CONFIG_USB_GSPCA_PAC207 is not set
1064# CONFIG_USB_GSPCA_PAC7311 is not set
1065# CONFIG_USB_GSPCA_SN9C20X is not set
1066# CONFIG_USB_GSPCA_SONIXB is not set
1067# CONFIG_USB_GSPCA_SONIXJ is not set
1068# CONFIG_USB_GSPCA_SPCA500 is not set
1069# CONFIG_USB_GSPCA_SPCA501 is not set
1070# CONFIG_USB_GSPCA_SPCA505 is not set
1071# CONFIG_USB_GSPCA_SPCA506 is not set
1072# CONFIG_USB_GSPCA_SPCA508 is not set
1073# CONFIG_USB_GSPCA_SPCA561 is not set
1074# CONFIG_USB_GSPCA_SQ905 is not set
1075# CONFIG_USB_GSPCA_SQ905C is not set
1076# CONFIG_USB_GSPCA_STK014 is not set
1077# CONFIG_USB_GSPCA_SUNPLUS is not set
1078# CONFIG_USB_GSPCA_T613 is not set
1079# CONFIG_USB_GSPCA_TV8532 is not set
1080# CONFIG_USB_GSPCA_VC032X is not set
1081# CONFIG_USB_GSPCA_ZC3XX is not set
1082# CONFIG_VIDEO_HDPVR is not set
1083# CONFIG_USB_VICAM is not set
1084# CONFIG_USB_IBMCAM is not set
1085# CONFIG_USB_KONICAWC is not set
1086# CONFIG_USB_QUICKCAM_MESSENGER is not set
1087# CONFIG_USB_ET61X251 is not set
1088# CONFIG_USB_OV511 is not set
1089# CONFIG_USB_SE401 is not set
1090# CONFIG_USB_SN9C102 is not set
1091# CONFIG_USB_STV680 is not set
1092# CONFIG_USB_ZC0301 is not set
1093# CONFIG_USB_PWC is not set
1094CONFIG_USB_PWC_INPUT_EVDEV=y
1095# CONFIG_USB_ZR364XX is not set
1096# CONFIG_USB_STKWEBCAM is not set
1097# CONFIG_USB_S2255 is not set
1098# CONFIG_RADIO_ADAPTERS is not set
1099# CONFIG_DAB is not set
1100
1101#
1102# Graphics support
1103#
1104CONFIG_VGA_ARB=y
1105# CONFIG_DRM is not set
1106# CONFIG_VGASTATE is not set
1107CONFIG_VIDEO_OUTPUT_CONTROL=y
1108CONFIG_FB=y
1109CONFIG_FIRMWARE_EDID=y
1110# CONFIG_FB_DDC is not set
1111CONFIG_FB_BOOT_VESA_SUPPORT=y
1112CONFIG_FB_CFB_FILLRECT=y
1113CONFIG_FB_CFB_COPYAREA=y
1114CONFIG_FB_CFB_IMAGEBLIT=y
1115# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
1116# CONFIG_FB_SYS_FILLRECT is not set
1117# CONFIG_FB_SYS_COPYAREA is not set
1118# CONFIG_FB_SYS_IMAGEBLIT is not set
1119# CONFIG_FB_FOREIGN_ENDIAN is not set
1120# CONFIG_FB_SYS_FOPS is not set
1121# CONFIG_FB_SVGALIB is not set
1122# CONFIG_FB_MACMODES is not set
1123# CONFIG_FB_BACKLIGHT is not set
1124CONFIG_FB_MODE_HELPERS=y
1125CONFIG_FB_TILEBLITTING=y
1126
1127#
1128# Frame buffer hardware drivers
1129#
1130# CONFIG_FB_CIRRUS is not set
1131# CONFIG_FB_PM2 is not set
1132# CONFIG_FB_CYBER2000 is not set
1133# CONFIG_FB_ASILIANT is not set
1134# CONFIG_FB_IMSTT is not set
1135# CONFIG_FB_S1D13XXX is not set
1136# CONFIG_FB_NVIDIA is not set
1137# CONFIG_FB_RIVA is not set
1138# CONFIG_FB_MATROX is not set
1139# CONFIG_FB_RADEON is not set
1140# CONFIG_FB_ATY128 is not set
1141# CONFIG_FB_ATY is not set
1142# CONFIG_FB_S3 is not set
1143# CONFIG_FB_SAVAGE is not set
1144CONFIG_FB_SIS=y
1145CONFIG_FB_SIS_300=y
1146CONFIG_FB_SIS_315=y
1147# CONFIG_FB_VIA is not set
1148# CONFIG_FB_NEOMAGIC is not set
1149# CONFIG_FB_KYRO is not set
1150# CONFIG_FB_3DFX is not set
1151# CONFIG_FB_VOODOO1 is not set
1152# CONFIG_FB_VT8623 is not set
1153# CONFIG_FB_TRIDENT is not set
1154# CONFIG_FB_ARK is not set
1155# CONFIG_FB_PM3 is not set
1156# CONFIG_FB_CARMINE is not set
1157# CONFIG_FB_VIRTUAL is not set
1158# CONFIG_FB_METRONOME is not set
1159# CONFIG_FB_MB862XX is not set
1160# CONFIG_FB_BROADSHEET is not set
1161CONFIG_BACKLIGHT_LCD_SUPPORT=y
1162# CONFIG_LCD_CLASS_DEVICE is not set
1163CONFIG_BACKLIGHT_CLASS_DEVICE=y
1164CONFIG_BACKLIGHT_GENERIC=y
1165
1166#
1167# Display device support
1168#
1169# CONFIG_DISPLAY_SUPPORT is not set
1170
1171#
1172# Console display driver support
1173#
1174# CONFIG_VGA_CONSOLE is not set
1175# CONFIG_MDA_CONSOLE is not set
1176CONFIG_DUMMY_CONSOLE=y
1177CONFIG_FRAMEBUFFER_CONSOLE=y
1178# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
1179CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
1180CONFIG_FONTS=y
1181CONFIG_FONT_8x8=y
1182CONFIG_FONT_8x16=y
1183CONFIG_FONT_6x11=y
1184CONFIG_FONT_7x14=y
1185CONFIG_FONT_PEARL_8x8=y
1186CONFIG_FONT_ACORN_8x8=y
1187CONFIG_FONT_MINI_4x6=y
1188CONFIG_FONT_SUN8x16=y
1189CONFIG_FONT_SUN12x22=y
1190CONFIG_FONT_10x18=y
1191CONFIG_LOGO=y
1192# CONFIG_LOGO_LINUX_MONO is not set
1193# CONFIG_LOGO_LINUX_VGA16 is not set
1194CONFIG_LOGO_LINUX_CLUT224=y
1195CONFIG_SOUND=m
1196# CONFIG_SOUND_OSS_CORE is not set
1197CONFIG_SND=m
1198CONFIG_SND_TIMER=m
1199CONFIG_SND_PCM=m
1200# CONFIG_SND_SEQUENCER is not set
1201# CONFIG_SND_MIXER_OSS is not set
1202# CONFIG_SND_PCM_OSS is not set
1203# CONFIG_SND_HRTIMER is not set
1204# CONFIG_SND_RTCTIMER is not set
1205# CONFIG_SND_DYNAMIC_MINORS is not set
1206# CONFIG_SND_SUPPORT_OLD_API is not set
1207# CONFIG_SND_VERBOSE_PROCFS is not set
1208# CONFIG_SND_VERBOSE_PRINTK is not set
1209# CONFIG_SND_DEBUG is not set
1210CONFIG_SND_VMASTER=y
1211# CONFIG_SND_RAWMIDI_SEQ is not set
1212# CONFIG_SND_OPL3_LIB_SEQ is not set
1213# CONFIG_SND_OPL4_LIB_SEQ is not set
1214# CONFIG_SND_SBAWE_SEQ is not set
1215# CONFIG_SND_EMU10K1_SEQ is not set
1216CONFIG_SND_AC97_CODEC=m
1217# CONFIG_SND_DRIVERS is not set
1218CONFIG_SND_PCI=y
1219# CONFIG_SND_AD1889 is not set
1220# CONFIG_SND_ALS300 is not set
1221# CONFIG_SND_ALI5451 is not set
1222# CONFIG_SND_ATIIXP is not set
1223# CONFIG_SND_ATIIXP_MODEM is not set
1224# CONFIG_SND_AU8810 is not set
1225# CONFIG_SND_AU8820 is not set
1226# CONFIG_SND_AU8830 is not set
1227# CONFIG_SND_AW2 is not set
1228# CONFIG_SND_AZT3328 is not set
1229# CONFIG_SND_BT87X is not set
1230# CONFIG_SND_CA0106 is not set
1231# CONFIG_SND_CMIPCI is not set
1232# CONFIG_SND_OXYGEN is not set
1233# CONFIG_SND_CS4281 is not set
1234# CONFIG_SND_CS46XX is not set
1235CONFIG_SND_CS5535AUDIO=m
1236# CONFIG_SND_CTXFI is not set
1237# CONFIG_SND_DARLA20 is not set
1238# CONFIG_SND_GINA20 is not set
1239# CONFIG_SND_LAYLA20 is not set
1240# CONFIG_SND_DARLA24 is not set
1241# CONFIG_SND_GINA24 is not set
1242# CONFIG_SND_LAYLA24 is not set
1243# CONFIG_SND_MONA is not set
1244# CONFIG_SND_MIA is not set
1245# CONFIG_SND_ECHO3G is not set
1246# CONFIG_SND_INDIGO is not set
1247# CONFIG_SND_INDIGOIO is not set
1248# CONFIG_SND_INDIGODJ is not set
1249# CONFIG_SND_INDIGOIOX is not set
1250# CONFIG_SND_INDIGODJX is not set
1251# CONFIG_SND_EMU10K1 is not set
1252# CONFIG_SND_EMU10K1X is not set
1253# CONFIG_SND_ENS1370 is not set
1254# CONFIG_SND_ENS1371 is not set
1255# CONFIG_SND_ES1938 is not set
1256# CONFIG_SND_ES1968 is not set
1257# CONFIG_SND_FM801 is not set
1258# CONFIG_SND_HDA_INTEL is not set
1259# CONFIG_SND_HDSP is not set
1260# CONFIG_SND_HDSPM is not set
1261# CONFIG_SND_HIFIER is not set
1262# CONFIG_SND_ICE1712 is not set
1263# CONFIG_SND_ICE1724 is not set
1264# CONFIG_SND_INTEL8X0 is not set
1265# CONFIG_SND_INTEL8X0M is not set
1266# CONFIG_SND_KORG1212 is not set
1267# CONFIG_SND_LX6464ES is not set
1268# CONFIG_SND_MAESTRO3 is not set
1269# CONFIG_SND_MIXART is not set
1270# CONFIG_SND_NM256 is not set
1271# CONFIG_SND_PCXHR is not set
1272# CONFIG_SND_RIPTIDE is not set
1273# CONFIG_SND_RME32 is not set
1274# CONFIG_SND_RME96 is not set
1275# CONFIG_SND_RME9652 is not set
1276# CONFIG_SND_SONICVIBES is not set
1277# CONFIG_SND_TRIDENT is not set
1278# CONFIG_SND_VIA82XX is not set
1279# CONFIG_SND_VIA82XX_MODEM is not set
1280# CONFIG_SND_VIRTUOSO is not set
1281# CONFIG_SND_VX222 is not set
1282# CONFIG_SND_YMFPCI is not set
1283# CONFIG_SND_MIPS is not set
1284# CONFIG_SND_USB is not set
1285# CONFIG_SND_SOC is not set
1286# CONFIG_SOUND_PRIME is not set
1287CONFIG_AC97_BUS=m
1288CONFIG_HID_SUPPORT=y
1289CONFIG_HID=y
1290CONFIG_HIDRAW=y
1291
1292#
1293# USB Input Devices
1294#
1295CONFIG_USB_HID=y
1296# CONFIG_HID_PID is not set
1297CONFIG_USB_HIDDEV=y
1298
1299#
1300# Special HID drivers
1301#
1302# CONFIG_HID_A4TECH is not set
1303# CONFIG_HID_APPLE is not set
1304# CONFIG_HID_BELKIN is not set
1305# CONFIG_HID_CHERRY is not set
1306# CONFIG_HID_CHICONY is not set
1307# CONFIG_HID_CYPRESS is not set
1308# CONFIG_HID_DRAGONRISE is not set
1309# CONFIG_HID_EZKEY is not set
1310# CONFIG_HID_KYE is not set
1311# CONFIG_HID_GYRATION is not set
1312# CONFIG_HID_TWINHAN is not set
1313# CONFIG_HID_KENSINGTON is not set
1314# CONFIG_HID_LOGITECH is not set
1315# CONFIG_HID_MICROSOFT is not set
1316# CONFIG_HID_MONTEREY is not set
1317# CONFIG_HID_NTRIG is not set
1318# CONFIG_HID_PANTHERLORD is not set
1319# CONFIG_HID_PETALYNX is not set
1320# CONFIG_HID_SAMSUNG is not set
1321# CONFIG_HID_SONY is not set
1322# CONFIG_HID_SUNPLUS is not set
1323# CONFIG_HID_GREENASIA is not set
1324# CONFIG_HID_SMARTJOYPLUS is not set
1325# CONFIG_HID_TOPSEED is not set
1326# CONFIG_HID_THRUSTMASTER is not set
1327# CONFIG_HID_ZEROPLUS is not set
1328CONFIG_USB_SUPPORT=y
1329CONFIG_USB_ARCH_HAS_HCD=y
1330CONFIG_USB_ARCH_HAS_OHCI=y
1331CONFIG_USB_ARCH_HAS_EHCI=y
1332CONFIG_USB=y
1333# CONFIG_USB_DEBUG is not set
1334# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
1335
1336#
1337# Miscellaneous USB options
1338#
1339CONFIG_USB_DEVICEFS=y
1340# CONFIG_USB_DEVICE_CLASS is not set
1341CONFIG_USB_DYNAMIC_MINORS=y
1342CONFIG_USB_SUSPEND=y
1343# CONFIG_USB_OTG is not set
1344CONFIG_USB_OTG_WHITELIST=y
1345# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1346CONFIG_USB_MON=y
1347# CONFIG_USB_WUSB is not set
1348# CONFIG_USB_WUSB_CBAF is not set
1349
1350#
1351# USB Host Controller Drivers
1352#
1353# CONFIG_USB_C67X00_HCD is not set
1354# CONFIG_USB_XHCI_HCD is not set
1355CONFIG_USB_EHCI_HCD=y
1356CONFIG_USB_EHCI_ROOT_HUB_TT=y
1357# CONFIG_USB_EHCI_TT_NEWSCHED is not set
1358# CONFIG_USB_OXU210HP_HCD is not set
1359# CONFIG_USB_ISP116X_HCD is not set
1360# CONFIG_USB_ISP1760_HCD is not set
1361# CONFIG_USB_ISP1362_HCD is not set
1362CONFIG_USB_OHCI_HCD=y
1363# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
1364# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
1365CONFIG_USB_OHCI_LITTLE_ENDIAN=y
1366CONFIG_USB_UHCI_HCD=m
1367# CONFIG_USB_SL811_HCD is not set
1368# CONFIG_USB_R8A66597_HCD is not set
1369# CONFIG_USB_WHCI_HCD is not set
1370# CONFIG_USB_HWA_HCD is not set
1371
1372#
1373# USB Device Class drivers
1374#
1375CONFIG_USB_ACM=m
1376# CONFIG_USB_PRINTER is not set
1377CONFIG_USB_WDM=m
1378# CONFIG_USB_TMC is not set
1379
1380#
1381# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
1382#
1383
1384#
1385# also be needed; see USB_STORAGE Help for more info
1386#
1387CONFIG_USB_STORAGE=m
1388# CONFIG_USB_STORAGE_DEBUG is not set
1389CONFIG_USB_STORAGE_DATAFAB=m
1390CONFIG_USB_STORAGE_FREECOM=m
1391CONFIG_USB_STORAGE_ISD200=m
1392CONFIG_USB_STORAGE_USBAT=m
1393CONFIG_USB_STORAGE_SDDR09=m
1394CONFIG_USB_STORAGE_SDDR55=m
1395CONFIG_USB_STORAGE_JUMPSHOT=m
1396CONFIG_USB_STORAGE_ALAUDA=m
1397# CONFIG_USB_STORAGE_ONETOUCH is not set
1398# CONFIG_USB_STORAGE_KARMA is not set
1399# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1400# CONFIG_USB_LIBUSUAL is not set
1401
1402#
1403# USB Imaging devices
1404#
1405# CONFIG_USB_MDC800 is not set
1406# CONFIG_USB_MICROTEK is not set
1407
1408#
1409# USB port drivers
1410#
1411CONFIG_USB_SERIAL=m
1412# CONFIG_USB_EZUSB is not set
1413CONFIG_USB_SERIAL_GENERIC=y
1414# CONFIG_USB_SERIAL_AIRCABLE is not set
1415# CONFIG_USB_SERIAL_ARK3116 is not set
1416# CONFIG_USB_SERIAL_BELKIN is not set
1417# CONFIG_USB_SERIAL_CH341 is not set
1418# CONFIG_USB_SERIAL_WHITEHEAT is not set
1419# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
1420# CONFIG_USB_SERIAL_CP210X is not set
1421# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
1422# CONFIG_USB_SERIAL_EMPEG is not set
1423# CONFIG_USB_SERIAL_FTDI_SIO is not set
1424# CONFIG_USB_SERIAL_FUNSOFT is not set
1425# CONFIG_USB_SERIAL_VISOR is not set
1426# CONFIG_USB_SERIAL_IPAQ is not set
1427# CONFIG_USB_SERIAL_IR is not set
1428# CONFIG_USB_SERIAL_EDGEPORT is not set
1429# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
1430# CONFIG_USB_SERIAL_GARMIN is not set
1431# CONFIG_USB_SERIAL_IPW is not set
1432# CONFIG_USB_SERIAL_IUU is not set
1433# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
1434# CONFIG_USB_SERIAL_KEYSPAN is not set
1435# CONFIG_USB_SERIAL_KLSI is not set
1436# CONFIG_USB_SERIAL_KOBIL_SCT is not set
1437# CONFIG_USB_SERIAL_MCT_U232 is not set
1438# CONFIG_USB_SERIAL_MOS7720 is not set
1439# CONFIG_USB_SERIAL_MOS7840 is not set
1440# CONFIG_USB_SERIAL_MOTOROLA is not set
1441# CONFIG_USB_SERIAL_NAVMAN is not set
1442# CONFIG_USB_SERIAL_PL2303 is not set
1443# CONFIG_USB_SERIAL_OTI6858 is not set
1444# CONFIG_USB_SERIAL_QUALCOMM is not set
1445# CONFIG_USB_SERIAL_SPCP8X5 is not set
1446# CONFIG_USB_SERIAL_HP4X is not set
1447# CONFIG_USB_SERIAL_SAFE is not set
1448# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
1449# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
1450# CONFIG_USB_SERIAL_SYMBOL is not set
1451# CONFIG_USB_SERIAL_TI is not set
1452# CONFIG_USB_SERIAL_CYBERJACK is not set
1453# CONFIG_USB_SERIAL_XIRCOM is not set
1454# CONFIG_USB_SERIAL_OPTION is not set
1455# CONFIG_USB_SERIAL_OMNINET is not set
1456# CONFIG_USB_SERIAL_OPTICON is not set
1457# CONFIG_USB_SERIAL_DEBUG is not set
1458
1459#
1460# USB Miscellaneous drivers
1461#
1462# CONFIG_USB_EMI62 is not set
1463# CONFIG_USB_EMI26 is not set
1464# CONFIG_USB_ADUTUX is not set
1465# CONFIG_USB_SEVSEG is not set
1466# CONFIG_USB_RIO500 is not set
1467# CONFIG_USB_LEGOTOWER is not set
1468# CONFIG_USB_LCD is not set
1469# CONFIG_USB_BERRY_CHARGE is not set
1470# CONFIG_USB_LED is not set
1471# CONFIG_USB_CYPRESS_CY7C63 is not set
1472# CONFIG_USB_CYTHERM is not set
1473# CONFIG_USB_IDMOUSE is not set
1474# CONFIG_USB_FTDI_ELAN is not set
1475# CONFIG_USB_APPLEDISPLAY is not set
1476# CONFIG_USB_SISUSBVGA is not set
1477# CONFIG_USB_LD is not set
1478# CONFIG_USB_TRANCEVIBRATOR is not set
1479# CONFIG_USB_IOWARRIOR is not set
1480# CONFIG_USB_TEST is not set
1481# CONFIG_USB_ISIGHTFW is not set
1482# CONFIG_USB_VST is not set
1483# CONFIG_USB_GADGET is not set
1484
1485#
1486# OTG and related infrastructure
1487#
1488# CONFIG_NOP_USB_XCEIV is not set
1489# CONFIG_UWB is not set
1490# CONFIG_MMC is not set
1491# CONFIG_MEMSTICK is not set
1492# CONFIG_NEW_LEDS is not set
1493# CONFIG_ACCESSIBILITY is not set
1494# CONFIG_INFINIBAND is not set
1495# CONFIG_RTC_CLASS is not set
1496# CONFIG_DMADEVICES is not set
1497# CONFIG_AUXDISPLAY is not set
1498# CONFIG_UIO is not set
1499
1500#
1501# TI VLYNQ
1502#
1503CONFIG_STAGING=y
1504# CONFIG_STAGING_EXCLUDE_BUILD is not set
1505# CONFIG_ET131X is not set
1506# CONFIG_USB_IP_COMMON is not set
1507# CONFIG_PRISM2_USB is not set
1508# CONFIG_ECHO is not set
1509# CONFIG_COMEDI is not set
1510# CONFIG_ASUS_OLED is not set
1511# CONFIG_ALTERA_PCIE_CHDMA is not set
1512# CONFIG_RTL8187SE is not set
1513# CONFIG_RTL8192SU is not set
1514# CONFIG_RTL8192E is not set
1515# CONFIG_INPUT_MIMIO is not set
1516# CONFIG_TRANZPORT is not set
1517
1518#
1519# Android
1520#
1521
1522#
1523# Qualcomm MSM Camera And Video
1524#
1525
1526#
1527# Camera Sensor Selection
1528#
1529# CONFIG_INPUT_GPIO is not set
1530# CONFIG_DST is not set
1531# CONFIG_POHMELFS is not set
1532# CONFIG_B3DFG is not set
1533# CONFIG_PLAN9AUTH is not set
1534# CONFIG_LINE6_USB is not set
1535# CONFIG_USB_SERIAL_QUATECH2 is not set
1536# CONFIG_USB_SERIAL_QUATECH_USB2 is not set
1537# CONFIG_VT6655 is not set
1538# CONFIG_VT6656 is not set
1539# CONFIG_FB_UDL is not set
1540# CONFIG_VME_BUS is not set
1541
1542#
1543# RAR Register Driver
1544#
1545# CONFIG_RAR_REGISTER is not set
1546# CONFIG_IIO is not set
1547CONFIG_FB_SM7XX=y
1548CONFIG_FB_SM7XX_ACCEL=y
1549
1550#
1551# File systems
1552#
1553# CONFIG_EXT2_FS is not set
1554CONFIG_EXT3_FS=y
1555# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
1556CONFIG_EXT3_FS_XATTR=y
1557CONFIG_EXT3_FS_POSIX_ACL=y
1558CONFIG_EXT3_FS_SECURITY=y
1559# CONFIG_EXT4_FS is not set
1560CONFIG_JBD=y
1561CONFIG_FS_MBCACHE=y
1562# CONFIG_REISERFS_FS is not set
1563# CONFIG_JFS_FS is not set
1564CONFIG_FS_POSIX_ACL=y
1565# CONFIG_XFS_FS is not set
1566# CONFIG_GFS2_FS is not set
1567# CONFIG_OCFS2_FS is not set
1568# CONFIG_BTRFS_FS is not set
1569# CONFIG_NILFS2_FS is not set
1570CONFIG_FILE_LOCKING=y
1571CONFIG_FSNOTIFY=y
1572CONFIG_DNOTIFY=y
1573CONFIG_INOTIFY=y
1574CONFIG_INOTIFY_USER=y
1575CONFIG_QUOTA=y
1576# CONFIG_QUOTA_NETLINK_INTERFACE is not set
1577CONFIG_PRINT_QUOTA_WARNING=y
1578# CONFIG_QFMT_V1 is not set
1579# CONFIG_QFMT_V2 is not set
1580CONFIG_QUOTACTL=y
1581# CONFIG_AUTOFS_FS is not set
1582# CONFIG_AUTOFS4_FS is not set
1583# CONFIG_FUSE_FS is not set
1584
1585#
1586# Caches
1587#
1588# CONFIG_FSCACHE is not set
1589
1590#
1591# CD-ROM/DVD Filesystems
1592#
1593CONFIG_ISO9660_FS=m
1594CONFIG_JOLIET=y
1595CONFIG_ZISOFS=y
1596# CONFIG_UDF_FS is not set
1597
1598#
1599# DOS/FAT/NT Filesystems
1600#
1601CONFIG_FAT_FS=m
1602# CONFIG_MSDOS_FS is not set
1603CONFIG_VFAT_FS=m
1604CONFIG_FAT_DEFAULT_CODEPAGE=437
1605CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1606# CONFIG_NTFS_FS is not set
1607
1608#
1609# Pseudo filesystems
1610#
1611CONFIG_PROC_FS=y
1612CONFIG_PROC_KCORE=y
1613CONFIG_PROC_SYSCTL=y
1614CONFIG_PROC_PAGE_MONITOR=y
1615CONFIG_SYSFS=y
1616CONFIG_TMPFS=y
1617# CONFIG_TMPFS_POSIX_ACL is not set
1618# CONFIG_HUGETLB_PAGE is not set
1619# CONFIG_CONFIGFS_FS is not set
1620# CONFIG_MISC_FILESYSTEMS is not set
1621CONFIG_NETWORK_FILESYSTEMS=y
1622CONFIG_NFS_FS=m
1623CONFIG_NFS_V3=y
1624CONFIG_NFS_V3_ACL=y
1625# CONFIG_NFS_V4 is not set
1626# CONFIG_NFSD is not set
1627CONFIG_LOCKD=m
1628CONFIG_LOCKD_V4=y
1629CONFIG_NFS_ACL_SUPPORT=m
1630CONFIG_NFS_COMMON=y
1631CONFIG_SUNRPC=m
1632# CONFIG_RPCSEC_GSS_KRB5 is not set
1633# CONFIG_RPCSEC_GSS_SPKM3 is not set
1634# CONFIG_SMB_FS is not set
1635# CONFIG_CIFS is not set
1636# CONFIG_NCP_FS is not set
1637# CONFIG_CODA_FS is not set
1638# CONFIG_AFS_FS is not set
1639
1640#
1641# Partition Types
1642#
1643# CONFIG_PARTITION_ADVANCED is not set
1644CONFIG_MSDOS_PARTITION=y
1645CONFIG_NLS=y
1646CONFIG_NLS_DEFAULT="utf-8"
1647# CONFIG_NLS_CODEPAGE_437 is not set
1648# CONFIG_NLS_CODEPAGE_737 is not set
1649# CONFIG_NLS_CODEPAGE_775 is not set
1650# CONFIG_NLS_CODEPAGE_850 is not set
1651# CONFIG_NLS_CODEPAGE_852 is not set
1652# CONFIG_NLS_CODEPAGE_855 is not set
1653# CONFIG_NLS_CODEPAGE_857 is not set
1654# CONFIG_NLS_CODEPAGE_860 is not set
1655# CONFIG_NLS_CODEPAGE_861 is not set
1656# CONFIG_NLS_CODEPAGE_862 is not set
1657# CONFIG_NLS_CODEPAGE_863 is not set
1658# CONFIG_NLS_CODEPAGE_864 is not set
1659# CONFIG_NLS_CODEPAGE_865 is not set
1660# CONFIG_NLS_CODEPAGE_866 is not set
1661# CONFIG_NLS_CODEPAGE_869 is not set
1662# CONFIG_NLS_CODEPAGE_936 is not set
1663# CONFIG_NLS_CODEPAGE_950 is not set
1664# CONFIG_NLS_CODEPAGE_932 is not set
1665# CONFIG_NLS_CODEPAGE_949 is not set
1666# CONFIG_NLS_CODEPAGE_874 is not set
1667# CONFIG_NLS_ISO8859_8 is not set
1668# CONFIG_NLS_CODEPAGE_1250 is not set
1669# CONFIG_NLS_CODEPAGE_1251 is not set
1670# CONFIG_NLS_ASCII is not set
1671# CONFIG_NLS_ISO8859_1 is not set
1672# CONFIG_NLS_ISO8859_2 is not set
1673# CONFIG_NLS_ISO8859_3 is not set
1674# CONFIG_NLS_ISO8859_4 is not set
1675# CONFIG_NLS_ISO8859_5 is not set
1676# CONFIG_NLS_ISO8859_6 is not set
1677# CONFIG_NLS_ISO8859_7 is not set
1678# CONFIG_NLS_ISO8859_9 is not set
1679# CONFIG_NLS_ISO8859_13 is not set
1680# CONFIG_NLS_ISO8859_14 is not set
1681# CONFIG_NLS_ISO8859_15 is not set
1682# CONFIG_NLS_KOI8_R is not set
1683# CONFIG_NLS_KOI8_U is not set
1684# CONFIG_NLS_UTF8 is not set
1685# CONFIG_DLM is not set
1686
1687#
1688# Kernel hacking
1689#
1690CONFIG_TRACE_IRQFLAGS_SUPPORT=y
1691CONFIG_PRINTK_TIME=y
1692CONFIG_ENABLE_WARN_DEPRECATED=y
1693CONFIG_ENABLE_MUST_CHECK=y
1694CONFIG_FRAME_WARN=1024
1695# CONFIG_MAGIC_SYSRQ is not set
1696CONFIG_STRIP_ASM_SYMS=y
1697# CONFIG_UNUSED_SYMBOLS is not set
1698# CONFIG_DEBUG_FS is not set
1699# CONFIG_HEADERS_CHECK is not set
1700# CONFIG_DEBUG_KERNEL is not set
1701# CONFIG_SLUB_DEBUG_ON is not set
1702# CONFIG_SLUB_STATS is not set
1703# CONFIG_DEBUG_MEMORY_INIT is not set
1704# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1705CONFIG_SYSCTL_SYSCALL_CHECK=y
1706CONFIG_TRACING_SUPPORT=y
1707# CONFIG_FTRACE is not set
1708# CONFIG_SAMPLES is not set
1709CONFIG_HAVE_ARCH_KGDB=y
1710# CONFIG_CMDLINE_BOOL is not set
1711
1712#
1713# Security options
1714#
1715# CONFIG_KEYS is not set
1716# CONFIG_SECURITY is not set
1717# CONFIG_SECURITYFS is not set
1718# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1719CONFIG_CRYPTO=y
1720
1721#
1722# Crypto core or helper
1723#
1724CONFIG_CRYPTO_ALGAPI=y
1725CONFIG_CRYPTO_ALGAPI2=y
1726CONFIG_CRYPTO_AEAD2=y
1727CONFIG_CRYPTO_BLKCIPHER=y
1728CONFIG_CRYPTO_BLKCIPHER2=y
1729CONFIG_CRYPTO_HASH2=y
1730CONFIG_CRYPTO_RNG2=y
1731CONFIG_CRYPTO_PCOMP=y
1732CONFIG_CRYPTO_MANAGER=y
1733CONFIG_CRYPTO_MANAGER2=y
1734# CONFIG_CRYPTO_GF128MUL is not set
1735# CONFIG_CRYPTO_NULL is not set
1736CONFIG_CRYPTO_WORKQUEUE=y
1737# CONFIG_CRYPTO_CRYPTD is not set
1738# CONFIG_CRYPTO_AUTHENC is not set
1739# CONFIG_CRYPTO_TEST is not set
1740
1741#
1742# Authenticated Encryption with Associated Data
1743#
1744# CONFIG_CRYPTO_CCM is not set
1745# CONFIG_CRYPTO_GCM is not set
1746# CONFIG_CRYPTO_SEQIV is not set
1747
1748#
1749# Block modes
1750#
1751CONFIG_CRYPTO_CBC=y
1752# CONFIG_CRYPTO_CTR is not set
1753# CONFIG_CRYPTO_CTS is not set
1754# CONFIG_CRYPTO_ECB is not set
1755# CONFIG_CRYPTO_LRW is not set
1756# CONFIG_CRYPTO_PCBC is not set
1757# CONFIG_CRYPTO_XTS is not set
1758
1759#
1760# Hash modes
1761#
1762# CONFIG_CRYPTO_HMAC is not set
1763# CONFIG_CRYPTO_XCBC is not set
1764# CONFIG_CRYPTO_VMAC is not set
1765
1766#
1767# Digest
1768#
1769# CONFIG_CRYPTO_CRC32C is not set
1770# CONFIG_CRYPTO_GHASH is not set
1771# CONFIG_CRYPTO_MD4 is not set
1772# CONFIG_CRYPTO_MD5 is not set
1773# CONFIG_CRYPTO_MICHAEL_MIC is not set
1774# CONFIG_CRYPTO_RMD128 is not set
1775# CONFIG_CRYPTO_RMD160 is not set
1776# CONFIG_CRYPTO_RMD256 is not set
1777# CONFIG_CRYPTO_RMD320 is not set
1778# CONFIG_CRYPTO_SHA1 is not set
1779# CONFIG_CRYPTO_SHA256 is not set
1780# CONFIG_CRYPTO_SHA512 is not set
1781# CONFIG_CRYPTO_TGR192 is not set
1782# CONFIG_CRYPTO_WP512 is not set
1783
1784#
1785# Ciphers
1786#
1787# CONFIG_CRYPTO_AES is not set
1788# CONFIG_CRYPTO_ANUBIS is not set
1789# CONFIG_CRYPTO_ARC4 is not set
1790# CONFIG_CRYPTO_BLOWFISH is not set
1791# CONFIG_CRYPTO_CAMELLIA is not set
1792# CONFIG_CRYPTO_CAST5 is not set
1793# CONFIG_CRYPTO_CAST6 is not set
1794# CONFIG_CRYPTO_DES is not set
1795# CONFIG_CRYPTO_FCRYPT is not set
1796# CONFIG_CRYPTO_KHAZAD is not set
1797# CONFIG_CRYPTO_SALSA20 is not set
1798# CONFIG_CRYPTO_SEED is not set
1799# CONFIG_CRYPTO_SERPENT is not set
1800# CONFIG_CRYPTO_TEA is not set
1801# CONFIG_CRYPTO_TWOFISH is not set
1802
1803#
1804# Compression
1805#
1806# CONFIG_CRYPTO_DEFLATE is not set
1807# CONFIG_CRYPTO_ZLIB is not set
1808# CONFIG_CRYPTO_LZO is not set
1809
1810#
1811# Random Number Generation
1812#
1813# CONFIG_CRYPTO_ANSI_CPRNG is not set
1814CONFIG_CRYPTO_HW=y
1815# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1816# CONFIG_BINARY_PRINTF is not set
1817
1818#
1819# Library routines
1820#
1821CONFIG_BITREVERSE=y
1822CONFIG_GENERIC_FIND_LAST_BIT=y
1823# CONFIG_CRC_CCITT is not set
1824# CONFIG_CRC16 is not set
1825CONFIG_CRC_T10DIF=y
1826# CONFIG_CRC_ITU_T is not set
1827CONFIG_CRC32=y
1828# CONFIG_CRC7 is not set
1829# CONFIG_LIBCRC32C is not set
1830CONFIG_AUDIT_GENERIC=y
1831CONFIG_ZLIB_INFLATE=m
1832CONFIG_HAS_IOMEM=y
1833CONFIG_HAS_IOPORT=y
1834CONFIG_HAS_DMA=y
1835CONFIG_NLATTR=y
diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig
index 3f01870b4d65..d3c601206db2 100644
--- a/arch/mips/configs/malta_defconfig
+++ b/arch/mips/configs/malta_defconfig
@@ -10,7 +10,6 @@ CONFIG_MIPS=y
10# 10#
11CONFIG_ZONE_DMA=y 11CONFIG_ZONE_DMA=y
12# CONFIG_MACH_ALCHEMY is not set 12# CONFIG_MACH_ALCHEMY is not set
13# CONFIG_BASLER_EXCITE is not set
14# CONFIG_BCM47XX is not set 13# CONFIG_BCM47XX is not set
15# CONFIG_MIPS_COBALT is not set 14# CONFIG_MIPS_COBALT is not set
16# CONFIG_MACH_DECSTATION is not set 15# CONFIG_MACH_DECSTATION is not set
@@ -1591,7 +1590,7 @@ CONFIG_FRAME_WARN=1024
1591# CONFIG_DYNAMIC_PRINTK_DEBUG is not set 1590# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
1592# CONFIG_SAMPLES is not set 1591# CONFIG_SAMPLES is not set
1593CONFIG_HAVE_ARCH_KGDB=y 1592CONFIG_HAVE_ARCH_KGDB=y
1594CONFIG_CMDLINE="" 1593# CONFIG_CMDLINE_BOOL is not set
1595 1594
1596# 1595#
1597# Security options 1596# Security options
diff --git a/arch/mips/configs/markeins_defconfig b/arch/mips/configs/markeins_defconfig
index d001f7e87418..6a325c02b63c 100644
--- a/arch/mips/configs/markeins_defconfig
+++ b/arch/mips/configs/markeins_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
22# CONFIG_MIPS_DB1550 is not set 22# CONFIG_MIPS_DB1550 is not set
23# CONFIG_MIPS_DB1200 is not set 23# CONFIG_MIPS_DB1200 is not set
24# CONFIG_MIPS_MIRAGE is not set 24# CONFIG_MIPS_MIRAGE is not set
25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 25# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 26# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MACH_JAZZ is not set 27# CONFIG_MACH_JAZZ is not set
@@ -1366,7 +1365,9 @@ CONFIG_ENABLE_MUST_CHECK=y
1366# CONFIG_DEBUG_KERNEL is not set 1365# CONFIG_DEBUG_KERNEL is not set
1367CONFIG_LOG_BUF_SHIFT=14 1366CONFIG_LOG_BUF_SHIFT=14
1368CONFIG_CROSSCOMPILE=y 1367CONFIG_CROSSCOMPILE=y
1368CONFIG_CMDLINE_BOOL=y
1369CONFIG_CMDLINE="console=ttyS0,115200 mem=192m ip=bootp root=/dev/nfs rw" 1369CONFIG_CMDLINE="console=ttyS0,115200 mem=192m ip=bootp root=/dev/nfs rw"
1370# CONFIG_CMDLINE_OVERRIDE is not set
1370 1371
1371# 1372#
1372# Security options 1373# Security options
diff --git a/arch/mips/configs/mipssim_defconfig b/arch/mips/configs/mipssim_defconfig
index 7358454deaa6..f77a34e0f938 100644
--- a/arch/mips/configs/mipssim_defconfig
+++ b/arch/mips/configs/mipssim_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set 12# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set 13# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set 14# CONFIG_MACH_DECSTATION is not set
@@ -635,7 +634,9 @@ CONFIG_FORCED_INLINING=y
635# CONFIG_RCU_TORTURE_TEST is not set 634# CONFIG_RCU_TORTURE_TEST is not set
636# CONFIG_FAULT_INJECTION is not set 635# CONFIG_FAULT_INJECTION is not set
637CONFIG_CROSSCOMPILE=y 636CONFIG_CROSSCOMPILE=y
637CONFIG_CMDLINE_BOOL=y
638CONFIG_CMDLINE="nfsroot=192.168.192.169:/u1/mipsel,timeo=20 ip=dhcp" 638CONFIG_CMDLINE="nfsroot=192.168.192.169:/u1/mipsel,timeo=20 ip=dhcp"
639# CONFIG_CMDLINE_OVERRIDE is not set
639# CONFIG_DEBUG_STACK_USAGE is not set 640# CONFIG_DEBUG_STACK_USAGE is not set
640# CONFIG_RUNTIME_DEBUG is not set 641# CONFIG_RUNTIME_DEBUG is not set
641 642
diff --git a/arch/mips/configs/mpc30x_defconfig b/arch/mips/configs/mpc30x_defconfig
index 8c720e51795b..17203056b22b 100644
--- a/arch/mips/configs/mpc30x_defconfig
+++ b/arch/mips/configs/mpc30x_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_MIPS_COBALT is not set 12# CONFIG_MIPS_COBALT is not set
14# CONFIG_MACH_DECSTATION is not set 13# CONFIG_MACH_DECSTATION is not set
15# CONFIG_MACH_JAZZ is not set 14# CONFIG_MACH_JAZZ is not set
@@ -817,7 +816,9 @@ CONFIG_ENABLE_MUST_CHECK=y
817# CONFIG_HEADERS_CHECK is not set 816# CONFIG_HEADERS_CHECK is not set
818# CONFIG_DEBUG_KERNEL is not set 817# CONFIG_DEBUG_KERNEL is not set
819CONFIG_CROSSCOMPILE=y 818CONFIG_CROSSCOMPILE=y
819CONFIG_CMDLINE_BOOL=y
820CONFIG_CMDLINE="mem=32M console=ttyVR0,19200 ide0=0x170,0x376,73" 820CONFIG_CMDLINE="mem=32M console=ttyVR0,19200 ide0=0x170,0x376,73"
821# CONFIG_CMDLINE_OVERRIDE is not set
821 822
822# 823#
823# Security options 824# Security options
diff --git a/arch/mips/configs/msp71xx_defconfig b/arch/mips/configs/msp71xx_defconfig
index ecbc030b7b6c..000d185ddf42 100644
--- a/arch/mips/configs/msp71xx_defconfig
+++ b/arch/mips/configs/msp71xx_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
22# CONFIG_MIPS_DB1550 is not set 22# CONFIG_MIPS_DB1550 is not set
23# CONFIG_MIPS_DB1200 is not set 23# CONFIG_MIPS_DB1200 is not set
24# CONFIG_MIPS_MIRAGE is not set 24# CONFIG_MIPS_MIRAGE is not set
25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 25# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 26# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MACH_JAZZ is not set 27# CONFIG_MACH_JAZZ is not set
@@ -1412,7 +1411,7 @@ CONFIG_FORCED_INLINING=y
1412# CONFIG_RCU_TORTURE_TEST is not set 1411# CONFIG_RCU_TORTURE_TEST is not set
1413# CONFIG_FAULT_INJECTION is not set 1412# CONFIG_FAULT_INJECTION is not set
1414CONFIG_CROSSCOMPILE=y 1413CONFIG_CROSSCOMPILE=y
1415CONFIG_CMDLINE="" 1414# CONFIG_CMDLINE_BOOL is not set
1416# CONFIG_DEBUG_STACK_USAGE is not set 1415# CONFIG_DEBUG_STACK_USAGE is not set
1417# CONFIG_RUNTIME_DEBUG is not set 1416# CONFIG_RUNTIME_DEBUG is not set
1418# CONFIG_MIPS_UNCACHED is not set 1417# CONFIG_MIPS_UNCACHED is not set
diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig
index 9477f040796d..144b94d9a6ad 100644
--- a/arch/mips/configs/mtx1_defconfig
+++ b/arch/mips/configs/mtx1_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11CONFIG_MACH_ALCHEMY=y 11CONFIG_MACH_ALCHEMY=y
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_MIPS_COBALT is not set 12# CONFIG_MIPS_COBALT is not set
14# CONFIG_MACH_DECSTATION is not set 13# CONFIG_MACH_DECSTATION is not set
15# CONFIG_MACH_JAZZ is not set 14# CONFIG_MACH_JAZZ is not set
@@ -3018,7 +3017,7 @@ CONFIG_MAGIC_SYSRQ=y
3018# CONFIG_HEADERS_CHECK is not set 3017# CONFIG_HEADERS_CHECK is not set
3019# CONFIG_DEBUG_KERNEL is not set 3018# CONFIG_DEBUG_KERNEL is not set
3020CONFIG_CROSSCOMPILE=y 3019CONFIG_CROSSCOMPILE=y
3021CONFIG_CMDLINE="" 3020# CONFIG_CMDLINE_BOOL is not set
3022 3021
3023# 3022#
3024# Security options 3023# Security options
diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig
index be8091ef0a79..ddf67f639194 100644
--- a/arch/mips/configs/pb1100_defconfig
+++ b/arch/mips/configs/pb1100_defconfig
@@ -23,7 +23,6 @@ CONFIG_MIPS_PB1100=y
23# CONFIG_MIPS_DB1550 is not set 23# CONFIG_MIPS_DB1550 is not set
24# CONFIG_MIPS_DB1200 is not set 24# CONFIG_MIPS_DB1200 is not set
25# CONFIG_MIPS_MIRAGE is not set 25# CONFIG_MIPS_MIRAGE is not set
26# CONFIG_BASLER_EXCITE is not set
27# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
28# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
@@ -1083,7 +1082,7 @@ CONFIG_ENABLE_MUST_CHECK=y
1083# CONFIG_DEBUG_KERNEL is not set 1082# CONFIG_DEBUG_KERNEL is not set
1084CONFIG_LOG_BUF_SHIFT=14 1083CONFIG_LOG_BUF_SHIFT=14
1085CONFIG_CROSSCOMPILE=y 1084CONFIG_CROSSCOMPILE=y
1086CONFIG_CMDLINE="" 1085# CONFIG_CMDLINE_BOOL is not set
1087 1086
1088# 1087#
1089# Security options 1088# Security options
diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig
index e74ba794c789..5ec60836b645 100644
--- a/arch/mips/configs/pb1500_defconfig
+++ b/arch/mips/configs/pb1500_defconfig
@@ -23,7 +23,6 @@ CONFIG_MIPS_PB1500=y
23# CONFIG_MIPS_DB1550 is not set 23# CONFIG_MIPS_DB1550 is not set
24# CONFIG_MIPS_DB1200 is not set 24# CONFIG_MIPS_DB1200 is not set
25# CONFIG_MIPS_MIRAGE is not set 25# CONFIG_MIPS_MIRAGE is not set
26# CONFIG_BASLER_EXCITE is not set
27# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
28# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
@@ -1200,7 +1199,7 @@ CONFIG_ENABLE_MUST_CHECK=y
1200# CONFIG_DEBUG_KERNEL is not set 1199# CONFIG_DEBUG_KERNEL is not set
1201CONFIG_LOG_BUF_SHIFT=14 1200CONFIG_LOG_BUF_SHIFT=14
1202CONFIG_CROSSCOMPILE=y 1201CONFIG_CROSSCOMPILE=y
1203CONFIG_CMDLINE="" 1202# CONFIG_CMDLINE_BOOL is not set
1204 1203
1205# 1204#
1206# Security options 1205# Security options
diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig
index 1d896fd830da..6647642b5d97 100644
--- a/arch/mips/configs/pb1550_defconfig
+++ b/arch/mips/configs/pb1550_defconfig
@@ -23,7 +23,6 @@ CONFIG_MIPS_PB1550=y
23# CONFIG_MIPS_DB1550 is not set 23# CONFIG_MIPS_DB1550 is not set
24# CONFIG_MIPS_DB1200 is not set 24# CONFIG_MIPS_DB1200 is not set
25# CONFIG_MIPS_MIRAGE is not set 25# CONFIG_MIPS_MIRAGE is not set
26# CONFIG_BASLER_EXCITE is not set
27# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
28# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
@@ -1193,7 +1192,7 @@ CONFIG_ENABLE_MUST_CHECK=y
1193# CONFIG_DEBUG_KERNEL is not set 1192# CONFIG_DEBUG_KERNEL is not set
1194CONFIG_LOG_BUF_SHIFT=14 1193CONFIG_LOG_BUF_SHIFT=14
1195CONFIG_CROSSCOMPILE=y 1194CONFIG_CROSSCOMPILE=y
1196CONFIG_CMDLINE="" 1195# CONFIG_CMDLINE_BOOL is not set
1197 1196
1198# 1197#
1199# Security options 1198# Security options
diff --git a/arch/mips/configs/pnx8335-stb225_defconfig b/arch/mips/configs/pnx8335-stb225_defconfig
index fef4d31c2055..848344d588d1 100644
--- a/arch/mips/configs/pnx8335-stb225_defconfig
+++ b/arch/mips/configs/pnx8335-stb225_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set 12# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set 13# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set 14# CONFIG_MACH_DECSTATION is not set
@@ -1034,7 +1033,7 @@ CONFIG_FRAME_WARN=1024
1034# CONFIG_DEBUG_KERNEL is not set 1033# CONFIG_DEBUG_KERNEL is not set
1035# CONFIG_SAMPLES is not set 1034# CONFIG_SAMPLES is not set
1036# CONFIG_KERNEL_TESTS is not set 1035# CONFIG_KERNEL_TESTS is not set
1037CONFIG_CMDLINE="" 1036# CONFIG_CMDLINE_BOOL is not set
1038 1037
1039# 1038#
1040# Security options 1039# Security options
diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550-jbs_defconfig
index e10c7116c3c2..9d721fdccb30 100644
--- a/arch/mips/configs/pnx8550-jbs_defconfig
+++ b/arch/mips/configs/pnx8550-jbs_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
22# CONFIG_MIPS_DB1550 is not set 22# CONFIG_MIPS_DB1550 is not set
23# CONFIG_MIPS_DB1200 is not set 23# CONFIG_MIPS_DB1200 is not set
24# CONFIG_MIPS_MIRAGE is not set 24# CONFIG_MIPS_MIRAGE is not set
25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 25# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 26# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MACH_JAZZ is not set 27# CONFIG_MACH_JAZZ is not set
@@ -1215,7 +1214,9 @@ CONFIG_DEBUG_MUTEXES=y
1215CONFIG_FORCED_INLINING=y 1214CONFIG_FORCED_INLINING=y
1216# CONFIG_RCU_TORTURE_TEST is not set 1215# CONFIG_RCU_TORTURE_TEST is not set
1217CONFIG_CROSSCOMPILE=y 1216CONFIG_CROSSCOMPILE=y
1217CONFIG_CMDLINE_BOOL=y
1218CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp" 1218CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp"
1219# CONFIG_CMDLINE_OVERRIDE is not set
1219# CONFIG_DEBUG_STACK_USAGE is not set 1220# CONFIG_DEBUG_STACK_USAGE is not set
1220# CONFIG_RUNTIME_DEBUG is not set 1221# CONFIG_RUNTIME_DEBUG is not set
1221 1222
diff --git a/arch/mips/configs/pnx8550-stb810_defconfig b/arch/mips/configs/pnx8550-stb810_defconfig
index 5ed3c8dfa0a1..ab07ec08c6fa 100644
--- a/arch/mips/configs/pnx8550-stb810_defconfig
+++ b/arch/mips/configs/pnx8550-stb810_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
22# CONFIG_MIPS_DB1550 is not set 22# CONFIG_MIPS_DB1550 is not set
23# CONFIG_MIPS_DB1200 is not set 23# CONFIG_MIPS_DB1200 is not set
24# CONFIG_MIPS_MIRAGE is not set 24# CONFIG_MIPS_MIRAGE is not set
25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 25# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 26# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MACH_JAZZ is not set 27# CONFIG_MACH_JAZZ is not set
@@ -1205,7 +1204,9 @@ CONFIG_DEBUG_SLAB=y
1205CONFIG_FORCED_INLINING=y 1204CONFIG_FORCED_INLINING=y
1206# CONFIG_RCU_TORTURE_TEST is not set 1205# CONFIG_RCU_TORTURE_TEST is not set
1207CONFIG_CROSSCOMPILE=y 1206CONFIG_CROSSCOMPILE=y
1207CONFIG_CMDLINE_BOOL=y
1208CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp" 1208CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp"
1209# CONFIG_CMDLINE_OVERRIDE is not set
1209# CONFIG_DEBUG_STACK_USAGE is not set 1210# CONFIG_DEBUG_STACK_USAGE is not set
1210# CONFIG_RUNTIME_DEBUG is not set 1211# CONFIG_RUNTIME_DEBUG is not set
1211 1212
diff --git a/arch/mips/configs/powertv_defconfig b/arch/mips/configs/powertv_defconfig
new file mode 100644
index 000000000000..7291633d81cc
--- /dev/null
+++ b/arch/mips/configs/powertv_defconfig
@@ -0,0 +1,1550 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.31-rc5
4# Fri Aug 28 14:49:33 2009
5#
6CONFIG_MIPS=y
7
8#
9# Machine selection
10#
11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_AR7 is not set
13# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set
16# CONFIG_MACH_JAZZ is not set
17# CONFIG_LASAT is not set
18# CONFIG_LEMOTE_FULONG is not set
19# CONFIG_MIPS_MALTA is not set
20# CONFIG_MIPS_SIM is not set
21# CONFIG_NEC_MARKEINS is not set
22# CONFIG_MACH_VR41XX is not set
23# CONFIG_NXP_STB220 is not set
24# CONFIG_NXP_STB225 is not set
25# CONFIG_PNX8550_JBS is not set
26# CONFIG_PNX8550_STB810 is not set
27# CONFIG_PMC_MSP is not set
28# CONFIG_PMC_YOSEMITE is not set
29CONFIG_POWERTV=y
30# CONFIG_SGI_IP22 is not set
31# CONFIG_SGI_IP27 is not set
32# CONFIG_SGI_IP28 is not set
33# CONFIG_SGI_IP32 is not set
34# CONFIG_SIBYTE_CRHINE is not set
35# CONFIG_SIBYTE_CARMEL is not set
36# CONFIG_SIBYTE_CRHONE is not set
37# CONFIG_SIBYTE_RHONE is not set
38# CONFIG_SIBYTE_SWARM is not set
39# CONFIG_SIBYTE_LITTLESUR is not set
40# CONFIG_SIBYTE_SENTOSA is not set
41# CONFIG_SIBYTE_BIGSUR is not set
42# CONFIG_SNI_RM is not set
43# CONFIG_MACH_TX39XX is not set
44# CONFIG_MACH_TX49XX is not set
45# CONFIG_MIKROTIK_RB532 is not set
46# CONFIG_WR_PPMC is not set
47# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
48# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
49# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
50# CONFIG_MIN_RUNTIME_RESOURCES is not set
51# CONFIG_BOOTLOADER_DRIVER is not set
52CONFIG_BOOTLOADER_FAMILY="R2"
53CONFIG_CSRC_POWERTV=y
54CONFIG_RWSEM_GENERIC_SPINLOCK=y
55# CONFIG_ARCH_HAS_ILOG2_U32 is not set
56# CONFIG_ARCH_HAS_ILOG2_U64 is not set
57CONFIG_ARCH_SUPPORTS_OPROFILE=y
58CONFIG_GENERIC_FIND_NEXT_BIT=y
59CONFIG_GENERIC_HWEIGHT=y
60CONFIG_GENERIC_CALIBRATE_DELAY=y
61CONFIG_GENERIC_CLOCKEVENTS=y
62CONFIG_GENERIC_TIME=y
63CONFIG_GENERIC_CMOS_UPDATE=y
64CONFIG_SCHED_OMIT_FRAME_POINTER=y
65CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
66CONFIG_CEVT_R4K_LIB=y
67CONFIG_CEVT_R4K=y
68CONFIG_DMA_NONCOHERENT=y
69CONFIG_DMA_NEED_PCI_MAP_STATE=y
70# CONFIG_EARLY_PRINTK is not set
71CONFIG_SYS_HAS_EARLY_PRINTK=y
72# CONFIG_NO_IOPORT is not set
73CONFIG_CPU_BIG_ENDIAN=y
74# CONFIG_CPU_LITTLE_ENDIAN is not set
75CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
76CONFIG_BOOT_ELF32=y
77CONFIG_MIPS_L1_CACHE_SHIFT=5
78
79#
80# CPU selection
81#
82# CONFIG_CPU_LOONGSON2 is not set
83# CONFIG_CPU_MIPS32_R1 is not set
84CONFIG_CPU_MIPS32_R2=y
85# CONFIG_CPU_MIPS64_R1 is not set
86# CONFIG_CPU_MIPS64_R2 is not set
87# CONFIG_CPU_R3000 is not set
88# CONFIG_CPU_TX39XX is not set
89# CONFIG_CPU_VR41XX is not set
90# CONFIG_CPU_R4300 is not set
91# CONFIG_CPU_R4X00 is not set
92# CONFIG_CPU_TX49XX is not set
93# CONFIG_CPU_R5000 is not set
94# CONFIG_CPU_R5432 is not set
95# CONFIG_CPU_R5500 is not set
96# CONFIG_CPU_R6000 is not set
97# CONFIG_CPU_NEVADA is not set
98# CONFIG_CPU_R8000 is not set
99# CONFIG_CPU_R10000 is not set
100# CONFIG_CPU_RM7000 is not set
101# CONFIG_CPU_RM9000 is not set
102# CONFIG_CPU_SB1 is not set
103# CONFIG_CPU_CAVIUM_OCTEON is not set
104CONFIG_SYS_HAS_CPU_MIPS32_R2=y
105CONFIG_CPU_MIPS32=y
106CONFIG_CPU_MIPSR2=y
107CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
108CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
109CONFIG_HARDWARE_WATCHPOINTS=y
110
111#
112# Kernel type
113#
114CONFIG_32BIT=y
115# CONFIG_64BIT is not set
116CONFIG_PAGE_SIZE_4KB=y
117# CONFIG_PAGE_SIZE_8KB is not set
118# CONFIG_PAGE_SIZE_16KB is not set
119# CONFIG_PAGE_SIZE_32KB is not set
120# CONFIG_PAGE_SIZE_64KB is not set
121CONFIG_CPU_HAS_PREFETCH=y
122CONFIG_MIPS_MT_DISABLED=y
123# CONFIG_MIPS_MT_SMP is not set
124# CONFIG_MIPS_MT_SMTC is not set
125CONFIG_CPU_HAS_LLSC=y
126CONFIG_CPU_MIPSR2_IRQ_VI=y
127CONFIG_CPU_MIPSR2_IRQ_EI=y
128CONFIG_CPU_HAS_SYNC=y
129CONFIG_GENERIC_HARDIRQS=y
130CONFIG_GENERIC_IRQ_PROBE=y
131# CONFIG_HIGHMEM is not set
132CONFIG_CPU_SUPPORTS_HIGHMEM=y
133CONFIG_SYS_SUPPORTS_HIGHMEM=y
134CONFIG_ARCH_FLATMEM_ENABLE=y
135CONFIG_ARCH_POPULATES_NODE_MAP=y
136CONFIG_SELECT_MEMORY_MODEL=y
137CONFIG_FLATMEM_MANUAL=y
138# CONFIG_DISCONTIGMEM_MANUAL is not set
139# CONFIG_SPARSEMEM_MANUAL is not set
140CONFIG_FLATMEM=y
141CONFIG_FLAT_NODE_MEM_MAP=y
142CONFIG_PAGEFLAGS_EXTENDED=y
143CONFIG_SPLIT_PTLOCK_CPUS=4
144# CONFIG_PHYS_ADDR_T_64BIT is not set
145CONFIG_ZONE_DMA_FLAG=0
146CONFIG_VIRT_TO_BUS=y
147CONFIG_HAVE_MLOCK=y
148CONFIG_HAVE_MLOCKED_PAGE_BIT=y
149CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
150CONFIG_TICK_ONESHOT=y
151CONFIG_NO_HZ=y
152CONFIG_HIGH_RES_TIMERS=y
153CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
154# CONFIG_HZ_48 is not set
155# CONFIG_HZ_100 is not set
156# CONFIG_HZ_128 is not set
157# CONFIG_HZ_250 is not set
158# CONFIG_HZ_256 is not set
159CONFIG_HZ_1000=y
160# CONFIG_HZ_1024 is not set
161CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
162CONFIG_HZ=1000
163# CONFIG_PREEMPT_NONE is not set
164# CONFIG_PREEMPT_VOLUNTARY is not set
165CONFIG_PREEMPT=y
166# CONFIG_KEXEC is not set
167# CONFIG_SECCOMP is not set
168CONFIG_LOCKDEP_SUPPORT=y
169CONFIG_STACKTRACE_SUPPORT=y
170CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
171CONFIG_CONSTRUCTORS=y
172
173#
174# General setup
175#
176CONFIG_EXPERIMENTAL=y
177CONFIG_BROKEN_ON_SMP=y
178CONFIG_LOCK_KERNEL=y
179CONFIG_INIT_ENV_ARG_LIMIT=32
180CONFIG_LOCALVERSION=""
181CONFIG_LOCALVERSION_AUTO=y
182# CONFIG_SWAP is not set
183CONFIG_SYSVIPC=y
184CONFIG_SYSVIPC_SYSCTL=y
185# CONFIG_POSIX_MQUEUE is not set
186# CONFIG_BSD_PROCESS_ACCT is not set
187# CONFIG_TASKSTATS is not set
188# CONFIG_AUDIT is not set
189
190#
191# RCU Subsystem
192#
193CONFIG_CLASSIC_RCU=y
194# CONFIG_TREE_RCU is not set
195# CONFIG_PREEMPT_RCU is not set
196# CONFIG_TREE_RCU_TRACE is not set
197# CONFIG_PREEMPT_RCU_TRACE is not set
198# CONFIG_IKCONFIG is not set
199CONFIG_LOG_BUF_SHIFT=16
200CONFIG_GROUP_SCHED=y
201CONFIG_FAIR_GROUP_SCHED=y
202# CONFIG_RT_GROUP_SCHED is not set
203CONFIG_USER_SCHED=y
204# CONFIG_CGROUP_SCHED is not set
205# CONFIG_CGROUPS is not set
206# CONFIG_SYSFS_DEPRECATED_V2 is not set
207CONFIG_RELAY=y
208# CONFIG_NAMESPACES is not set
209CONFIG_BLK_DEV_INITRD=y
210CONFIG_INITRAMFS_SOURCE=""
211# CONFIG_RD_GZIP is not set
212# CONFIG_RD_BZIP2 is not set
213# CONFIG_RD_LZMA is not set
214# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
215CONFIG_SYSCTL=y
216CONFIG_ANON_INODES=y
217CONFIG_EMBEDDED=y
218# CONFIG_SYSCTL_SYSCALL is not set
219CONFIG_KALLSYMS=y
220CONFIG_KALLSYMS_ALL=y
221# CONFIG_KALLSYMS_EXTRA_PASS is not set
222CONFIG_HOTPLUG=y
223CONFIG_PRINTK=y
224CONFIG_BUG=y
225CONFIG_ELF_CORE=y
226# CONFIG_PCSPKR_PLATFORM is not set
227CONFIG_BASE_FULL=y
228CONFIG_FUTEX=y
229# CONFIG_EPOLL is not set
230# CONFIG_SIGNALFD is not set
231CONFIG_TIMERFD=y
232# CONFIG_EVENTFD is not set
233CONFIG_SHMEM=y
234CONFIG_AIO=y
235
236#
237# Performance Counters
238#
239# CONFIG_VM_EVENT_COUNTERS is not set
240CONFIG_PCI_QUIRKS=y
241# CONFIG_SLUB_DEBUG is not set
242# CONFIG_STRIP_ASM_SYMS is not set
243CONFIG_COMPAT_BRK=y
244# CONFIG_SLAB is not set
245CONFIG_SLUB=y
246# CONFIG_SLOB is not set
247# CONFIG_PROFILING is not set
248# CONFIG_MARKERS is not set
249CONFIG_HAVE_OPROFILE=y
250
251#
252# GCOV-based kernel profiling
253#
254# CONFIG_GCOV_KERNEL is not set
255# CONFIG_SLOW_WORK is not set
256# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
257CONFIG_RT_MUTEXES=y
258CONFIG_BASE_SMALL=0
259CONFIG_MODULES=y
260# CONFIG_MODULE_FORCE_LOAD is not set
261CONFIG_MODULE_UNLOAD=y
262# CONFIG_MODULE_FORCE_UNLOAD is not set
263CONFIG_MODVERSIONS=y
264CONFIG_MODULE_SRCVERSION_ALL=y
265CONFIG_BLOCK=y
266CONFIG_LBDAF=y
267# CONFIG_BLK_DEV_BSG is not set
268# CONFIG_BLK_DEV_INTEGRITY is not set
269
270#
271# IO Schedulers
272#
273CONFIG_IOSCHED_NOOP=y
274# CONFIG_IOSCHED_AS is not set
275# CONFIG_IOSCHED_DEADLINE is not set
276# CONFIG_IOSCHED_CFQ is not set
277# CONFIG_DEFAULT_AS is not set
278# CONFIG_DEFAULT_DEADLINE is not set
279# CONFIG_DEFAULT_CFQ is not set
280CONFIG_DEFAULT_NOOP=y
281CONFIG_DEFAULT_IOSCHED="noop"
282# CONFIG_PROBE_INITRD_HEADER is not set
283# CONFIG_FREEZER is not set
284
285#
286# Bus options (PCI, PCMCIA, EISA, ISA, TC)
287#
288CONFIG_HW_HAS_PCI=y
289CONFIG_PCI=y
290CONFIG_PCI_DOMAINS=y
291# CONFIG_ARCH_SUPPORTS_MSI is not set
292# CONFIG_PCI_LEGACY is not set
293# CONFIG_PCI_DEBUG is not set
294# CONFIG_PCI_STUB is not set
295# CONFIG_PCI_IOV is not set
296CONFIG_MMU=y
297# CONFIG_PCCARD is not set
298# CONFIG_HOTPLUG_PCI is not set
299
300#
301# Executable file formats
302#
303CONFIG_BINFMT_ELF=y
304# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
305# CONFIG_HAVE_AOUT is not set
306# CONFIG_BINFMT_MISC is not set
307CONFIG_TRAD_SIGNALS=y
308
309#
310# Power management options
311#
312CONFIG_ARCH_HIBERNATION_POSSIBLE=y
313CONFIG_ARCH_SUSPEND_POSSIBLE=y
314# CONFIG_PM is not set
315CONFIG_NET=y
316
317#
318# Networking options
319#
320CONFIG_PACKET=y
321CONFIG_PACKET_MMAP=y
322CONFIG_UNIX=y
323CONFIG_XFRM=y
324# CONFIG_XFRM_USER is not set
325# CONFIG_XFRM_SUB_POLICY is not set
326# CONFIG_XFRM_MIGRATE is not set
327# CONFIG_XFRM_STATISTICS is not set
328CONFIG_XFRM_IPCOMP=y
329# CONFIG_NET_KEY is not set
330CONFIG_INET=y
331CONFIG_IP_MULTICAST=y
332CONFIG_IP_ADVANCED_ROUTER=y
333CONFIG_ASK_IP_FIB_HASH=y
334# CONFIG_IP_FIB_TRIE is not set
335CONFIG_IP_FIB_HASH=y
336# CONFIG_IP_MULTIPLE_TABLES is not set
337# CONFIG_IP_ROUTE_MULTIPATH is not set
338# CONFIG_IP_ROUTE_VERBOSE is not set
339CONFIG_IP_PNP=y
340# CONFIG_IP_PNP_DHCP is not set
341# CONFIG_IP_PNP_BOOTP is not set
342# CONFIG_IP_PNP_RARP is not set
343# CONFIG_NET_IPIP is not set
344# CONFIG_NET_IPGRE is not set
345# CONFIG_IP_MROUTE is not set
346# CONFIG_ARPD is not set
347CONFIG_SYN_COOKIES=y
348# CONFIG_INET_AH is not set
349# CONFIG_INET_ESP is not set
350# CONFIG_INET_IPCOMP is not set
351# CONFIG_INET_XFRM_TUNNEL is not set
352# CONFIG_INET_TUNNEL is not set
353# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
354# CONFIG_INET_XFRM_MODE_TUNNEL is not set
355# CONFIG_INET_XFRM_MODE_BEET is not set
356# CONFIG_INET_LRO is not set
357# CONFIG_INET_DIAG is not set
358# CONFIG_TCP_CONG_ADVANCED is not set
359CONFIG_TCP_CONG_CUBIC=y
360CONFIG_DEFAULT_TCP_CONG="cubic"
361# CONFIG_TCP_MD5SIG is not set
362CONFIG_IPV6=y
363CONFIG_IPV6_PRIVACY=y
364# CONFIG_IPV6_ROUTER_PREF is not set
365# CONFIG_IPV6_OPTIMISTIC_DAD is not set
366CONFIG_INET6_AH=y
367CONFIG_INET6_ESP=y
368CONFIG_INET6_IPCOMP=y
369# CONFIG_IPV6_MIP6 is not set
370CONFIG_INET6_XFRM_TUNNEL=y
371CONFIG_INET6_TUNNEL=y
372# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
373# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
374# CONFIG_INET6_XFRM_MODE_BEET is not set
375# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
376# CONFIG_IPV6_SIT is not set
377CONFIG_IPV6_TUNNEL=y
378# CONFIG_IPV6_MULTIPLE_TABLES is not set
379# CONFIG_IPV6_MROUTE is not set
380# CONFIG_NETWORK_SECMARK is not set
381CONFIG_NETFILTER=y
382# CONFIG_NETFILTER_DEBUG is not set
383CONFIG_NETFILTER_ADVANCED=y
384# CONFIG_BRIDGE_NETFILTER is not set
385
386#
387# Core Netfilter Configuration
388#
389# CONFIG_NETFILTER_NETLINK_QUEUE is not set
390# CONFIG_NETFILTER_NETLINK_LOG is not set
391# CONFIG_NF_CONNTRACK is not set
392CONFIG_NETFILTER_XTABLES=y
393# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
394# CONFIG_NETFILTER_XT_TARGET_MARK is not set
395# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
396# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
397# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
398# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
399# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
400# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
401# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
402# CONFIG_NETFILTER_XT_MATCH_ESP is not set
403# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
404# CONFIG_NETFILTER_XT_MATCH_HL is not set
405# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
406# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
407# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
408# CONFIG_NETFILTER_XT_MATCH_MAC is not set
409# CONFIG_NETFILTER_XT_MATCH_MARK is not set
410CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
411# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
412# CONFIG_NETFILTER_XT_MATCH_POLICY is not set
413# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
414# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
415# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
416# CONFIG_NETFILTER_XT_MATCH_REALM is not set
417# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
418# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
419# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
420# CONFIG_NETFILTER_XT_MATCH_STRING is not set
421# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
422# CONFIG_NETFILTER_XT_MATCH_TIME is not set
423# CONFIG_NETFILTER_XT_MATCH_U32 is not set
424# CONFIG_IP_VS is not set
425
426#
427# IP: Netfilter Configuration
428#
429# CONFIG_NF_DEFRAG_IPV4 is not set
430# CONFIG_IP_NF_QUEUE is not set
431CONFIG_IP_NF_IPTABLES=y
432# CONFIG_IP_NF_MATCH_ADDRTYPE is not set
433# CONFIG_IP_NF_MATCH_AH is not set
434# CONFIG_IP_NF_MATCH_ECN is not set
435# CONFIG_IP_NF_MATCH_TTL is not set
436CONFIG_IP_NF_FILTER=y
437# CONFIG_IP_NF_TARGET_REJECT is not set
438# CONFIG_IP_NF_TARGET_LOG is not set
439# CONFIG_IP_NF_TARGET_ULOG is not set
440# CONFIG_IP_NF_MANGLE is not set
441# CONFIG_IP_NF_TARGET_TTL is not set
442# CONFIG_IP_NF_RAW is not set
443CONFIG_IP_NF_ARPTABLES=y
444CONFIG_IP_NF_ARPFILTER=y
445# CONFIG_IP_NF_ARP_MANGLE is not set
446
447#
448# IPv6: Netfilter Configuration
449#
450# CONFIG_IP6_NF_QUEUE is not set
451CONFIG_IP6_NF_IPTABLES=y
452# CONFIG_IP6_NF_MATCH_AH is not set
453# CONFIG_IP6_NF_MATCH_EUI64 is not set
454# CONFIG_IP6_NF_MATCH_FRAG is not set
455# CONFIG_IP6_NF_MATCH_OPTS is not set
456# CONFIG_IP6_NF_MATCH_HL is not set
457# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set
458# CONFIG_IP6_NF_MATCH_MH is not set
459# CONFIG_IP6_NF_MATCH_RT is not set
460# CONFIG_IP6_NF_TARGET_HL is not set
461# CONFIG_IP6_NF_TARGET_LOG is not set
462CONFIG_IP6_NF_FILTER=y
463# CONFIG_IP6_NF_TARGET_REJECT is not set
464# CONFIG_IP6_NF_MANGLE is not set
465# CONFIG_IP6_NF_RAW is not set
466# CONFIG_IP_DCCP is not set
467# CONFIG_IP_SCTP is not set
468# CONFIG_TIPC is not set
469# CONFIG_ATM is not set
470CONFIG_STP=y
471CONFIG_BRIDGE=y
472# CONFIG_NET_DSA is not set
473# CONFIG_VLAN_8021Q is not set
474# CONFIG_DECNET is not set
475CONFIG_LLC=y
476# CONFIG_LLC2 is not set
477# CONFIG_IPX is not set
478# CONFIG_ATALK is not set
479# CONFIG_X25 is not set
480# CONFIG_LAPB is not set
481# CONFIG_ECONET is not set
482# CONFIG_WAN_ROUTER is not set
483# CONFIG_PHONET is not set
484# CONFIG_IEEE802154 is not set
485CONFIG_NET_SCHED=y
486
487#
488# Queueing/Scheduling
489#
490# CONFIG_NET_SCH_CBQ is not set
491# CONFIG_NET_SCH_HTB is not set
492# CONFIG_NET_SCH_HFSC is not set
493# CONFIG_NET_SCH_PRIO is not set
494# CONFIG_NET_SCH_MULTIQ is not set
495# CONFIG_NET_SCH_RED is not set
496# CONFIG_NET_SCH_SFQ is not set
497# CONFIG_NET_SCH_TEQL is not set
498CONFIG_NET_SCH_TBF=y
499# CONFIG_NET_SCH_GRED is not set
500# CONFIG_NET_SCH_DSMARK is not set
501# CONFIG_NET_SCH_NETEM is not set
502# CONFIG_NET_SCH_DRR is not set
503
504#
505# Classification
506#
507# CONFIG_NET_CLS_BASIC is not set
508# CONFIG_NET_CLS_TCINDEX is not set
509# CONFIG_NET_CLS_ROUTE4 is not set
510# CONFIG_NET_CLS_FW is not set
511# CONFIG_NET_CLS_U32 is not set
512# CONFIG_NET_CLS_RSVP is not set
513# CONFIG_NET_CLS_RSVP6 is not set
514# CONFIG_NET_CLS_FLOW is not set
515# CONFIG_NET_EMATCH is not set
516# CONFIG_NET_CLS_ACT is not set
517CONFIG_NET_SCH_FIFO=y
518# CONFIG_DCB is not set
519
520#
521# Network testing
522#
523# CONFIG_NET_PKTGEN is not set
524# CONFIG_HAMRADIO is not set
525# CONFIG_CAN is not set
526# CONFIG_IRDA is not set
527# CONFIG_BT is not set
528# CONFIG_AF_RXRPC is not set
529# CONFIG_WIRELESS is not set
530# CONFIG_WIMAX is not set
531# CONFIG_RFKILL is not set
532# CONFIG_NET_9P is not set
533
534#
535# Device Drivers
536#
537
538#
539# Generic Driver Options
540#
541CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
542CONFIG_STANDALONE=y
543CONFIG_PREVENT_FIRMWARE_BUILD=y
544CONFIG_FW_LOADER=y
545CONFIG_FIRMWARE_IN_KERNEL=y
546CONFIG_EXTRA_FIRMWARE=""
547# CONFIG_DEBUG_DRIVER is not set
548# CONFIG_DEBUG_DEVRES is not set
549# CONFIG_SYS_HYPERVISOR is not set
550# CONFIG_CONNECTOR is not set
551CONFIG_MTD=y
552# CONFIG_MTD_DEBUG is not set
553# CONFIG_MTD_CONCAT is not set
554CONFIG_MTD_PARTITIONS=y
555# CONFIG_MTD_TESTS is not set
556# CONFIG_MTD_REDBOOT_PARTS is not set
557CONFIG_MTD_CMDLINE_PARTS=y
558# CONFIG_MTD_AR7_PARTS is not set
559
560#
561# User Modules And Translation Layers
562#
563CONFIG_MTD_CHAR=y
564CONFIG_MTD_BLKDEVS=y
565CONFIG_MTD_BLOCK=y
566# CONFIG_FTL is not set
567# CONFIG_NFTL is not set
568# CONFIG_INFTL is not set
569# CONFIG_RFD_FTL is not set
570# CONFIG_SSFDC is not set
571# CONFIG_MTD_OOPS is not set
572
573#
574# RAM/ROM/Flash chip drivers
575#
576# CONFIG_MTD_CFI is not set
577# CONFIG_MTD_JEDECPROBE is not set
578CONFIG_MTD_MAP_BANK_WIDTH_1=y
579CONFIG_MTD_MAP_BANK_WIDTH_2=y
580CONFIG_MTD_MAP_BANK_WIDTH_4=y
581# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
582# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
583# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
584CONFIG_MTD_CFI_I1=y
585CONFIG_MTD_CFI_I2=y
586# CONFIG_MTD_CFI_I4 is not set
587# CONFIG_MTD_CFI_I8 is not set
588# CONFIG_MTD_RAM is not set
589# CONFIG_MTD_ROM is not set
590# CONFIG_MTD_ABSENT is not set
591
592#
593# Mapping drivers for chip access
594#
595# CONFIG_MTD_COMPLEX_MAPPINGS is not set
596# CONFIG_MTD_INTEL_VR_NOR is not set
597# CONFIG_MTD_PLATRAM is not set
598
599#
600# Self-contained MTD device drivers
601#
602# CONFIG_MTD_PMC551 is not set
603# CONFIG_MTD_SLRAM is not set
604# CONFIG_MTD_PHRAM is not set
605# CONFIG_MTD_MTDRAM is not set
606# CONFIG_MTD_BLOCK2MTD is not set
607
608#
609# Disk-On-Chip Device Drivers
610#
611# CONFIG_MTD_DOC2000 is not set
612# CONFIG_MTD_DOC2001 is not set
613# CONFIG_MTD_DOC2001PLUS is not set
614CONFIG_MTD_NAND=y
615# CONFIG_MTD_NAND_VERIFY_WRITE is not set
616# CONFIG_MTD_NAND_ECC_SMC is not set
617# CONFIG_MTD_NAND_MUSEUM_IDS is not set
618CONFIG_MTD_NAND_IDS=y
619# CONFIG_MTD_NAND_DISKONCHIP is not set
620# CONFIG_MTD_NAND_CAFE is not set
621# CONFIG_MTD_NAND_NANDSIM is not set
622# CONFIG_MTD_NAND_PLATFORM is not set
623# CONFIG_MTD_ALAUDA is not set
624# CONFIG_MTD_ONENAND is not set
625
626#
627# LPDDR flash memory drivers
628#
629# CONFIG_MTD_LPDDR is not set
630
631#
632# UBI - Unsorted block images
633#
634# CONFIG_MTD_UBI is not set
635# CONFIG_PARPORT is not set
636CONFIG_BLK_DEV=y
637# CONFIG_BLK_CPQ_DA is not set
638# CONFIG_BLK_CPQ_CISS_DA is not set
639# CONFIG_BLK_DEV_DAC960 is not set
640# CONFIG_BLK_DEV_UMEM is not set
641# CONFIG_BLK_DEV_COW_COMMON is not set
642CONFIG_BLK_DEV_LOOP=y
643# CONFIG_BLK_DEV_CRYPTOLOOP is not set
644# CONFIG_BLK_DEV_NBD is not set
645# CONFIG_BLK_DEV_SX8 is not set
646# CONFIG_BLK_DEV_UB is not set
647CONFIG_BLK_DEV_RAM=y
648CONFIG_BLK_DEV_RAM_COUNT=16
649CONFIG_BLK_DEV_RAM_SIZE=32768
650# CONFIG_BLK_DEV_XIP is not set
651# CONFIG_CDROM_PKTCDVD is not set
652# CONFIG_ATA_OVER_ETH is not set
653# CONFIG_BLK_DEV_HD is not set
654# CONFIG_MISC_DEVICES is not set
655CONFIG_HAVE_IDE=y
656# CONFIG_IDE is not set
657
658#
659# SCSI device support
660#
661# CONFIG_RAID_ATTRS is not set
662CONFIG_SCSI=y
663CONFIG_SCSI_DMA=y
664# CONFIG_SCSI_TGT is not set
665# CONFIG_SCSI_NETLINK is not set
666# CONFIG_SCSI_PROC_FS is not set
667
668#
669# SCSI support type (disk, tape, CD-ROM)
670#
671CONFIG_BLK_DEV_SD=y
672# CONFIG_CHR_DEV_ST is not set
673# CONFIG_CHR_DEV_OSST is not set
674# CONFIG_BLK_DEV_SR is not set
675# CONFIG_CHR_DEV_SG is not set
676# CONFIG_CHR_DEV_SCH is not set
677# CONFIG_SCSI_MULTI_LUN is not set
678# CONFIG_SCSI_CONSTANTS is not set
679# CONFIG_SCSI_LOGGING is not set
680# CONFIG_SCSI_SCAN_ASYNC is not set
681CONFIG_SCSI_WAIT_SCAN=m
682
683#
684# SCSI Transports
685#
686# CONFIG_SCSI_SPI_ATTRS is not set
687# CONFIG_SCSI_FC_ATTRS is not set
688# CONFIG_SCSI_ISCSI_ATTRS is not set
689# CONFIG_SCSI_SAS_LIBSAS is not set
690# CONFIG_SCSI_SRP_ATTRS is not set
691# CONFIG_SCSI_LOWLEVEL is not set
692# CONFIG_SCSI_DH is not set
693# CONFIG_SCSI_OSD_INITIATOR is not set
694CONFIG_ATA=y
695# CONFIG_ATA_NONSTANDARD is not set
696CONFIG_SATA_PMP=y
697# CONFIG_SATA_AHCI is not set
698# CONFIG_SATA_SIL24 is not set
699CONFIG_ATA_SFF=y
700# CONFIG_SATA_SVW is not set
701# CONFIG_ATA_PIIX is not set
702# CONFIG_SATA_MV is not set
703# CONFIG_SATA_NV is not set
704# CONFIG_PDC_ADMA is not set
705# CONFIG_SATA_QSTOR is not set
706# CONFIG_SATA_PROMISE is not set
707# CONFIG_SATA_SX4 is not set
708# CONFIG_SATA_SIL is not set
709# CONFIG_SATA_SIS is not set
710# CONFIG_SATA_ULI is not set
711# CONFIG_SATA_VIA is not set
712# CONFIG_SATA_VITESSE is not set
713# CONFIG_SATA_INIC162X is not set
714# CONFIG_PATA_ALI is not set
715# CONFIG_PATA_AMD is not set
716# CONFIG_PATA_ARTOP is not set
717# CONFIG_PATA_ATIIXP is not set
718# CONFIG_PATA_CMD640_PCI is not set
719# CONFIG_PATA_CMD64X is not set
720# CONFIG_PATA_CS5520 is not set
721# CONFIG_PATA_CS5530 is not set
722# CONFIG_PATA_CYPRESS is not set
723# CONFIG_PATA_EFAR is not set
724# CONFIG_ATA_GENERIC is not set
725# CONFIG_PATA_HPT366 is not set
726# CONFIG_PATA_HPT37X is not set
727# CONFIG_PATA_HPT3X2N is not set
728# CONFIG_PATA_HPT3X3 is not set
729# CONFIG_PATA_IT821X is not set
730# CONFIG_PATA_IT8213 is not set
731# CONFIG_PATA_JMICRON is not set
732# CONFIG_PATA_TRIFLEX is not set
733# CONFIG_PATA_MARVELL is not set
734# CONFIG_PATA_MPIIX is not set
735# CONFIG_PATA_OLDPIIX is not set
736# CONFIG_PATA_NETCELL is not set
737# CONFIG_PATA_NINJA32 is not set
738# CONFIG_PATA_NS87410 is not set
739# CONFIG_PATA_NS87415 is not set
740# CONFIG_PATA_OPTI is not set
741# CONFIG_PATA_OPTIDMA is not set
742# CONFIG_PATA_PDC_OLD is not set
743# CONFIG_PATA_RADISYS is not set
744# CONFIG_PATA_RZ1000 is not set
745# CONFIG_PATA_SC1200 is not set
746# CONFIG_PATA_SERVERWORKS is not set
747# CONFIG_PATA_PDC2027X is not set
748# CONFIG_PATA_SIL680 is not set
749# CONFIG_PATA_SIS is not set
750# CONFIG_PATA_VIA is not set
751# CONFIG_PATA_WINBOND is not set
752# CONFIG_PATA_PLATFORM is not set
753# CONFIG_PATA_SCH is not set
754# CONFIG_MD is not set
755# CONFIG_FUSION is not set
756
757#
758# IEEE 1394 (FireWire) support
759#
760
761#
762# You can enable one or both FireWire driver stacks.
763#
764
765#
766# See the help texts for more information.
767#
768# CONFIG_FIREWIRE is not set
769# CONFIG_IEEE1394 is not set
770# CONFIG_I2O is not set
771CONFIG_NETDEVICES=y
772# CONFIG_DUMMY is not set
773# CONFIG_BONDING is not set
774# CONFIG_MACVLAN is not set
775# CONFIG_EQUALIZER is not set
776# CONFIG_TUN is not set
777# CONFIG_VETH is not set
778# CONFIG_ARCNET is not set
779# CONFIG_PHYLIB is not set
780CONFIG_NET_ETHERNET=y
781CONFIG_MII=y
782# CONFIG_AX88796 is not set
783# CONFIG_HAPPYMEAL is not set
784# CONFIG_SUNGEM is not set
785# CONFIG_CASSINI is not set
786# CONFIG_NET_VENDOR_3COM is not set
787# CONFIG_SMC91X is not set
788# CONFIG_DM9000 is not set
789# CONFIG_ETHOC is not set
790# CONFIG_DNET is not set
791# CONFIG_NET_TULIP is not set
792# CONFIG_HP100 is not set
793# CONFIG_IBM_NEW_EMAC_ZMII is not set
794# CONFIG_IBM_NEW_EMAC_RGMII is not set
795# CONFIG_IBM_NEW_EMAC_TAH is not set
796# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
797# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
798# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
799# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
800# CONFIG_NET_PCI is not set
801# CONFIG_B44 is not set
802# CONFIG_KS8842 is not set
803# CONFIG_ATL2 is not set
804CONFIG_NETDEV_1000=y
805# CONFIG_ACENIC is not set
806# CONFIG_DL2K is not set
807# CONFIG_E1000 is not set
808# CONFIG_E1000E is not set
809# CONFIG_IP1000 is not set
810# CONFIG_IGB is not set
811# CONFIG_IGBVF is not set
812# CONFIG_NS83820 is not set
813# CONFIG_HAMACHI is not set
814# CONFIG_YELLOWFIN is not set
815# CONFIG_R8169 is not set
816# CONFIG_SIS190 is not set
817# CONFIG_SKGE is not set
818# CONFIG_SKY2 is not set
819# CONFIG_VIA_VELOCITY is not set
820# CONFIG_TIGON3 is not set
821# CONFIG_BNX2 is not set
822# CONFIG_CNIC is not set
823# CONFIG_QLA3XXX is not set
824# CONFIG_ATL1 is not set
825# CONFIG_ATL1E is not set
826# CONFIG_ATL1C is not set
827# CONFIG_JME is not set
828CONFIG_NETDEV_10000=y
829# CONFIG_CHELSIO_T1 is not set
830CONFIG_CHELSIO_T3_DEPENDS=y
831# CONFIG_CHELSIO_T3 is not set
832# CONFIG_ENIC is not set
833# CONFIG_IXGBE is not set
834# CONFIG_IXGB is not set
835# CONFIG_S2IO is not set
836# CONFIG_VXGE is not set
837# CONFIG_MYRI10GE is not set
838# CONFIG_NETXEN_NIC is not set
839# CONFIG_NIU is not set
840# CONFIG_MLX4_EN is not set
841# CONFIG_MLX4_CORE is not set
842# CONFIG_TEHUTI is not set
843# CONFIG_BNX2X is not set
844# CONFIG_QLGE is not set
845# CONFIG_SFC is not set
846# CONFIG_BE2NET is not set
847# CONFIG_TR is not set
848
849#
850# Wireless LAN
851#
852# CONFIG_WLAN_PRE80211 is not set
853# CONFIG_WLAN_80211 is not set
854
855#
856# Enable WiMAX (Networking options) to see the WiMAX drivers
857#
858
859#
860# USB Network Adapters
861#
862# CONFIG_USB_CATC is not set
863# CONFIG_USB_KAWETH is not set
864# CONFIG_USB_PEGASUS is not set
865CONFIG_USB_RTL8150=y
866# CONFIG_USB_USBNET is not set
867# CONFIG_WAN is not set
868# CONFIG_FDDI is not set
869# CONFIG_HIPPI is not set
870# CONFIG_PPP is not set
871# CONFIG_SLIP is not set
872# CONFIG_NET_FC is not set
873# CONFIG_NETCONSOLE is not set
874# CONFIG_NETPOLL is not set
875# CONFIG_NET_POLL_CONTROLLER is not set
876# CONFIG_ISDN is not set
877# CONFIG_PHONE is not set
878
879#
880# Input device support
881#
882CONFIG_INPUT=y
883# CONFIG_INPUT_FF_MEMLESS is not set
884# CONFIG_INPUT_POLLDEV is not set
885
886#
887# Userland interfaces
888#
889# CONFIG_INPUT_MOUSEDEV is not set
890# CONFIG_INPUT_JOYDEV is not set
891CONFIG_INPUT_EVDEV=y
892# CONFIG_INPUT_EVBUG is not set
893
894#
895# Input Device Drivers
896#
897# CONFIG_INPUT_KEYBOARD is not set
898# CONFIG_INPUT_MOUSE is not set
899# CONFIG_INPUT_JOYSTICK is not set
900# CONFIG_INPUT_TABLET is not set
901# CONFIG_INPUT_TOUCHSCREEN is not set
902# CONFIG_INPUT_MISC is not set
903
904#
905# Hardware I/O ports
906#
907# CONFIG_SERIO is not set
908# CONFIG_GAMEPORT is not set
909
910#
911# Character devices
912#
913# CONFIG_VT is not set
914# CONFIG_DEVKMEM is not set
915# CONFIG_SERIAL_NONSTANDARD is not set
916# CONFIG_NOZOMI is not set
917
918#
919# Serial drivers
920#
921# CONFIG_SERIAL_8250 is not set
922
923#
924# Non-8250 serial port support
925#
926# CONFIG_SERIAL_JSM is not set
927CONFIG_UNIX98_PTYS=y
928# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
929# CONFIG_LEGACY_PTYS is not set
930# CONFIG_IPMI_HANDLER is not set
931# CONFIG_HW_RANDOM is not set
932# CONFIG_R3964 is not set
933# CONFIG_APPLICOM is not set
934# CONFIG_RAW_DRIVER is not set
935# CONFIG_TCG_TPM is not set
936CONFIG_DEVPORT=y
937# CONFIG_I2C is not set
938# CONFIG_SPI is not set
939
940#
941# PPS support
942#
943# CONFIG_PPS is not set
944# CONFIG_W1 is not set
945# CONFIG_POWER_SUPPLY is not set
946# CONFIG_HWMON is not set
947# CONFIG_THERMAL is not set
948# CONFIG_THERMAL_HWMON is not set
949# CONFIG_WATCHDOG is not set
950CONFIG_SSB_POSSIBLE=y
951
952#
953# Sonics Silicon Backplane
954#
955# CONFIG_SSB is not set
956
957#
958# Multifunction device drivers
959#
960# CONFIG_MFD_CORE is not set
961# CONFIG_MFD_SM501 is not set
962# CONFIG_HTC_PASIC3 is not set
963# CONFIG_MFD_TMIO is not set
964# CONFIG_REGULATOR is not set
965# CONFIG_MEDIA_SUPPORT is not set
966
967#
968# Graphics support
969#
970# CONFIG_DRM is not set
971# CONFIG_VGASTATE is not set
972# CONFIG_VIDEO_OUTPUT_CONTROL is not set
973# CONFIG_FB is not set
974# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
975
976#
977# Display device support
978#
979# CONFIG_DISPLAY_SUPPORT is not set
980# CONFIG_SOUND is not set
981CONFIG_HID_SUPPORT=y
982CONFIG_HID=y
983# CONFIG_HID_DEBUG is not set
984# CONFIG_HIDRAW is not set
985
986#
987# USB Input Devices
988#
989CONFIG_USB_HID=y
990# CONFIG_HID_PID is not set
991CONFIG_USB_HIDDEV=y
992
993#
994# Special HID drivers
995#
996# CONFIG_HID_A4TECH is not set
997# CONFIG_HID_APPLE is not set
998# CONFIG_HID_BELKIN is not set
999# CONFIG_HID_CHERRY is not set
1000# CONFIG_HID_CHICONY is not set
1001# CONFIG_HID_CYPRESS is not set
1002# CONFIG_HID_DRAGONRISE is not set
1003# CONFIG_HID_EZKEY is not set
1004# CONFIG_HID_KYE is not set
1005# CONFIG_HID_GYRATION is not set
1006# CONFIG_HID_KENSINGTON is not set
1007# CONFIG_HID_LOGITECH is not set
1008# CONFIG_HID_MICROSOFT is not set
1009# CONFIG_HID_MONTEREY is not set
1010# CONFIG_HID_NTRIG is not set
1011# CONFIG_HID_PANTHERLORD is not set
1012# CONFIG_HID_PETALYNX is not set
1013# CONFIG_HID_SAMSUNG is not set
1014# CONFIG_HID_SONY is not set
1015# CONFIG_HID_SUNPLUS is not set
1016# CONFIG_HID_GREENASIA is not set
1017# CONFIG_HID_SMARTJOYPLUS is not set
1018# CONFIG_HID_TOPSEED is not set
1019# CONFIG_HID_THRUSTMASTER is not set
1020# CONFIG_HID_ZEROPLUS is not set
1021CONFIG_USB_SUPPORT=y
1022CONFIG_USB_ARCH_HAS_HCD=y
1023CONFIG_USB_ARCH_HAS_OHCI=y
1024CONFIG_USB_ARCH_HAS_EHCI=y
1025CONFIG_USB=y
1026# CONFIG_USB_DEBUG is not set
1027CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
1028
1029#
1030# Miscellaneous USB options
1031#
1032CONFIG_USB_DEVICEFS=y
1033# CONFIG_USB_DEVICE_CLASS is not set
1034# CONFIG_USB_DYNAMIC_MINORS is not set
1035# CONFIG_USB_OTG is not set
1036# CONFIG_USB_OTG_WHITELIST is not set
1037# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1038# CONFIG_USB_MON is not set
1039# CONFIG_USB_WUSB is not set
1040# CONFIG_USB_WUSB_CBAF is not set
1041
1042#
1043# USB Host Controller Drivers
1044#
1045# CONFIG_USB_C67X00_HCD is not set
1046# CONFIG_USB_XHCI_HCD is not set
1047CONFIG_USB_EHCI_HCD=y
1048# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
1049# CONFIG_USB_EHCI_TT_NEWSCHED is not set
1050# CONFIG_USB_OXU210HP_HCD is not set
1051# CONFIG_USB_ISP116X_HCD is not set
1052# CONFIG_USB_ISP1760_HCD is not set
1053CONFIG_USB_OHCI_HCD=y
1054# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
1055# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
1056CONFIG_USB_OHCI_LITTLE_ENDIAN=y
1057# CONFIG_USB_UHCI_HCD is not set
1058# CONFIG_USB_SL811_HCD is not set
1059# CONFIG_USB_R8A66597_HCD is not set
1060# CONFIG_USB_WHCI_HCD is not set
1061# CONFIG_USB_HWA_HCD is not set
1062
1063#
1064# USB Device Class drivers
1065#
1066# CONFIG_USB_ACM is not set
1067# CONFIG_USB_PRINTER is not set
1068# CONFIG_USB_WDM is not set
1069# CONFIG_USB_TMC is not set
1070
1071#
1072# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
1073#
1074
1075#
1076# also be needed; see USB_STORAGE Help for more info
1077#
1078CONFIG_USB_STORAGE=y
1079# CONFIG_USB_STORAGE_DEBUG is not set
1080# CONFIG_USB_STORAGE_DATAFAB is not set
1081# CONFIG_USB_STORAGE_FREECOM is not set
1082# CONFIG_USB_STORAGE_ISD200 is not set
1083# CONFIG_USB_STORAGE_USBAT is not set
1084# CONFIG_USB_STORAGE_SDDR09 is not set
1085# CONFIG_USB_STORAGE_SDDR55 is not set
1086# CONFIG_USB_STORAGE_JUMPSHOT is not set
1087# CONFIG_USB_STORAGE_ALAUDA is not set
1088# CONFIG_USB_STORAGE_ONETOUCH is not set
1089# CONFIG_USB_STORAGE_KARMA is not set
1090# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1091# CONFIG_USB_LIBUSUAL is not set
1092
1093#
1094# USB Imaging devices
1095#
1096# CONFIG_USB_MDC800 is not set
1097# CONFIG_USB_MICROTEK is not set
1098
1099#
1100# USB port drivers
1101#
1102CONFIG_USB_SERIAL=y
1103CONFIG_USB_SERIAL_CONSOLE=y
1104# CONFIG_USB_EZUSB is not set
1105# CONFIG_USB_SERIAL_GENERIC is not set
1106# CONFIG_USB_SERIAL_AIRCABLE is not set
1107# CONFIG_USB_SERIAL_ARK3116 is not set
1108# CONFIG_USB_SERIAL_BELKIN is not set
1109# CONFIG_USB_SERIAL_CH341 is not set
1110# CONFIG_USB_SERIAL_WHITEHEAT is not set
1111# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
1112CONFIG_USB_SERIAL_CP210X=y
1113# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
1114# CONFIG_USB_SERIAL_EMPEG is not set
1115# CONFIG_USB_SERIAL_FTDI_SIO is not set
1116# CONFIG_USB_SERIAL_FUNSOFT is not set
1117# CONFIG_USB_SERIAL_VISOR is not set
1118# CONFIG_USB_SERIAL_IPAQ is not set
1119# CONFIG_USB_SERIAL_IR is not set
1120# CONFIG_USB_SERIAL_EDGEPORT is not set
1121# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
1122# CONFIG_USB_SERIAL_GARMIN is not set
1123# CONFIG_USB_SERIAL_IPW is not set
1124# CONFIG_USB_SERIAL_IUU is not set
1125# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
1126# CONFIG_USB_SERIAL_KEYSPAN is not set
1127# CONFIG_USB_SERIAL_KLSI is not set
1128# CONFIG_USB_SERIAL_KOBIL_SCT is not set
1129# CONFIG_USB_SERIAL_MCT_U232 is not set
1130# CONFIG_USB_SERIAL_MOS7720 is not set
1131# CONFIG_USB_SERIAL_MOS7840 is not set
1132# CONFIG_USB_SERIAL_MOTOROLA is not set
1133# CONFIG_USB_SERIAL_NAVMAN is not set
1134# CONFIG_USB_SERIAL_PL2303 is not set
1135# CONFIG_USB_SERIAL_OTI6858 is not set
1136# CONFIG_USB_SERIAL_QUALCOMM is not set
1137# CONFIG_USB_SERIAL_SPCP8X5 is not set
1138# CONFIG_USB_SERIAL_HP4X is not set
1139# CONFIG_USB_SERIAL_SAFE is not set
1140# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
1141# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
1142# CONFIG_USB_SERIAL_SYMBOL is not set
1143# CONFIG_USB_SERIAL_TI is not set
1144# CONFIG_USB_SERIAL_CYBERJACK is not set
1145# CONFIG_USB_SERIAL_XIRCOM is not set
1146# CONFIG_USB_SERIAL_OPTION is not set
1147# CONFIG_USB_SERIAL_OMNINET is not set
1148# CONFIG_USB_SERIAL_OPTICON is not set
1149# CONFIG_USB_SERIAL_DEBUG is not set
1150
1151#
1152# USB Miscellaneous drivers
1153#
1154# CONFIG_USB_EMI62 is not set
1155# CONFIG_USB_EMI26 is not set
1156# CONFIG_USB_ADUTUX is not set
1157# CONFIG_USB_SEVSEG is not set
1158# CONFIG_USB_RIO500 is not set
1159# CONFIG_USB_LEGOTOWER is not set
1160# CONFIG_USB_LCD is not set
1161# CONFIG_USB_BERRY_CHARGE is not set
1162# CONFIG_USB_LED is not set
1163# CONFIG_USB_CYPRESS_CY7C63 is not set
1164# CONFIG_USB_CYTHERM is not set
1165# CONFIG_USB_IDMOUSE is not set
1166# CONFIG_USB_FTDI_ELAN is not set
1167# CONFIG_USB_APPLEDISPLAY is not set
1168# CONFIG_USB_SISUSBVGA is not set
1169# CONFIG_USB_LD is not set
1170# CONFIG_USB_TRANCEVIBRATOR is not set
1171# CONFIG_USB_IOWARRIOR is not set
1172# CONFIG_USB_TEST is not set
1173# CONFIG_USB_ISIGHTFW is not set
1174# CONFIG_USB_VST is not set
1175# CONFIG_USB_GADGET is not set
1176
1177#
1178# OTG and related infrastructure
1179#
1180# CONFIG_NOP_USB_XCEIV is not set
1181# CONFIG_UWB is not set
1182# CONFIG_MMC is not set
1183# CONFIG_MEMSTICK is not set
1184# CONFIG_NEW_LEDS is not set
1185# CONFIG_ACCESSIBILITY is not set
1186# CONFIG_INFINIBAND is not set
1187CONFIG_RTC_LIB=y
1188# CONFIG_RTC_CLASS is not set
1189# CONFIG_DMADEVICES is not set
1190# CONFIG_AUXDISPLAY is not set
1191# CONFIG_UIO is not set
1192
1193#
1194# TI VLYNQ
1195#
1196# CONFIG_STAGING is not set
1197
1198#
1199# File systems
1200#
1201CONFIG_EXT2_FS=y
1202# CONFIG_EXT2_FS_XATTR is not set
1203# CONFIG_EXT2_FS_XIP is not set
1204CONFIG_EXT3_FS=y
1205# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
1206# CONFIG_EXT3_FS_XATTR is not set
1207# CONFIG_EXT4_FS is not set
1208CONFIG_JBD=y
1209# CONFIG_JBD_DEBUG is not set
1210# CONFIG_REISERFS_FS is not set
1211# CONFIG_JFS_FS is not set
1212# CONFIG_FS_POSIX_ACL is not set
1213# CONFIG_XFS_FS is not set
1214# CONFIG_GFS2_FS is not set
1215# CONFIG_OCFS2_FS is not set
1216# CONFIG_BTRFS_FS is not set
1217CONFIG_FILE_LOCKING=y
1218CONFIG_FSNOTIFY=y
1219# CONFIG_DNOTIFY is not set
1220CONFIG_INOTIFY=y
1221CONFIG_INOTIFY_USER=y
1222# CONFIG_QUOTA is not set
1223# CONFIG_AUTOFS_FS is not set
1224# CONFIG_AUTOFS4_FS is not set
1225CONFIG_FUSE_FS=y
1226# CONFIG_CUSE is not set
1227
1228#
1229# Caches
1230#
1231# CONFIG_FSCACHE is not set
1232
1233#
1234# CD-ROM/DVD Filesystems
1235#
1236# CONFIG_ISO9660_FS is not set
1237# CONFIG_UDF_FS is not set
1238
1239#
1240# DOS/FAT/NT Filesystems
1241#
1242# CONFIG_MSDOS_FS is not set
1243# CONFIG_VFAT_FS is not set
1244# CONFIG_NTFS_FS is not set
1245
1246#
1247# Pseudo filesystems
1248#
1249CONFIG_PROC_FS=y
1250CONFIG_PROC_KCORE=y
1251CONFIG_PROC_SYSCTL=y
1252CONFIG_PROC_PAGE_MONITOR=y
1253CONFIG_SYSFS=y
1254CONFIG_TMPFS=y
1255# CONFIG_TMPFS_POSIX_ACL is not set
1256# CONFIG_HUGETLB_PAGE is not set
1257# CONFIG_CONFIGFS_FS is not set
1258CONFIG_MISC_FILESYSTEMS=y
1259# CONFIG_ADFS_FS is not set
1260# CONFIG_AFFS_FS is not set
1261# CONFIG_HFS_FS is not set
1262# CONFIG_HFSPLUS_FS is not set
1263# CONFIG_BEFS_FS is not set
1264# CONFIG_BFS_FS is not set
1265# CONFIG_EFS_FS is not set
1266CONFIG_JFFS2_FS=y
1267CONFIG_JFFS2_FS_DEBUG=0
1268CONFIG_JFFS2_FS_WRITEBUFFER=y
1269# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
1270# CONFIG_JFFS2_SUMMARY is not set
1271# CONFIG_JFFS2_FS_XATTR is not set
1272# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1273CONFIG_JFFS2_ZLIB=y
1274# CONFIG_JFFS2_LZO is not set
1275CONFIG_JFFS2_RTIME=y
1276# CONFIG_JFFS2_RUBIN is not set
1277CONFIG_CRAMFS=y
1278# CONFIG_SQUASHFS is not set
1279# CONFIG_VXFS_FS is not set
1280# CONFIG_MINIX_FS is not set
1281# CONFIG_OMFS_FS is not set
1282# CONFIG_HPFS_FS is not set
1283# CONFIG_QNX4FS_FS is not set
1284# CONFIG_ROMFS_FS is not set
1285# CONFIG_SYSV_FS is not set
1286# CONFIG_UFS_FS is not set
1287# CONFIG_NILFS2_FS is not set
1288CONFIG_NETWORK_FILESYSTEMS=y
1289CONFIG_NFS_FS=y
1290CONFIG_NFS_V3=y
1291# CONFIG_NFS_V3_ACL is not set
1292# CONFIG_NFS_V4 is not set
1293CONFIG_ROOT_NFS=y
1294# CONFIG_NFSD is not set
1295CONFIG_LOCKD=y
1296CONFIG_LOCKD_V4=y
1297CONFIG_NFS_COMMON=y
1298CONFIG_SUNRPC=y
1299# CONFIG_RPCSEC_GSS_KRB5 is not set
1300# CONFIG_RPCSEC_GSS_SPKM3 is not set
1301# CONFIG_SMB_FS is not set
1302# CONFIG_CIFS is not set
1303# CONFIG_NCP_FS is not set
1304# CONFIG_CODA_FS is not set
1305# CONFIG_AFS_FS is not set
1306
1307#
1308# Partition Types
1309#
1310# CONFIG_PARTITION_ADVANCED is not set
1311CONFIG_MSDOS_PARTITION=y
1312CONFIG_NLS=y
1313CONFIG_NLS_DEFAULT="iso8859-1"
1314# CONFIG_NLS_CODEPAGE_437 is not set
1315# CONFIG_NLS_CODEPAGE_737 is not set
1316# CONFIG_NLS_CODEPAGE_775 is not set
1317# CONFIG_NLS_CODEPAGE_850 is not set
1318# CONFIG_NLS_CODEPAGE_852 is not set
1319# CONFIG_NLS_CODEPAGE_855 is not set
1320# CONFIG_NLS_CODEPAGE_857 is not set
1321# CONFIG_NLS_CODEPAGE_860 is not set
1322# CONFIG_NLS_CODEPAGE_861 is not set
1323# CONFIG_NLS_CODEPAGE_862 is not set
1324# CONFIG_NLS_CODEPAGE_863 is not set
1325# CONFIG_NLS_CODEPAGE_864 is not set
1326# CONFIG_NLS_CODEPAGE_865 is not set
1327# CONFIG_NLS_CODEPAGE_866 is not set
1328# CONFIG_NLS_CODEPAGE_869 is not set
1329# CONFIG_NLS_CODEPAGE_936 is not set
1330# CONFIG_NLS_CODEPAGE_950 is not set
1331# CONFIG_NLS_CODEPAGE_932 is not set
1332# CONFIG_NLS_CODEPAGE_949 is not set
1333# CONFIG_NLS_CODEPAGE_874 is not set
1334# CONFIG_NLS_ISO8859_8 is not set
1335# CONFIG_NLS_CODEPAGE_1250 is not set
1336# CONFIG_NLS_CODEPAGE_1251 is not set
1337# CONFIG_NLS_ASCII is not set
1338# CONFIG_NLS_ISO8859_1 is not set
1339# CONFIG_NLS_ISO8859_2 is not set
1340# CONFIG_NLS_ISO8859_3 is not set
1341# CONFIG_NLS_ISO8859_4 is not set
1342# CONFIG_NLS_ISO8859_5 is not set
1343# CONFIG_NLS_ISO8859_6 is not set
1344# CONFIG_NLS_ISO8859_7 is not set
1345# CONFIG_NLS_ISO8859_9 is not set
1346# CONFIG_NLS_ISO8859_13 is not set
1347# CONFIG_NLS_ISO8859_14 is not set
1348# CONFIG_NLS_ISO8859_15 is not set
1349# CONFIG_NLS_KOI8_R is not set
1350# CONFIG_NLS_KOI8_U is not set
1351# CONFIG_NLS_UTF8 is not set
1352# CONFIG_DLM is not set
1353
1354#
1355# Kernel hacking
1356#
1357CONFIG_TRACE_IRQFLAGS_SUPPORT=y
1358CONFIG_PRINTK_TIME=y
1359CONFIG_ENABLE_WARN_DEPRECATED=y
1360CONFIG_ENABLE_MUST_CHECK=y
1361CONFIG_FRAME_WARN=1024
1362# CONFIG_MAGIC_SYSRQ is not set
1363# CONFIG_UNUSED_SYMBOLS is not set
1364CONFIG_DEBUG_FS=y
1365# CONFIG_HEADERS_CHECK is not set
1366CONFIG_DEBUG_KERNEL=y
1367# CONFIG_DEBUG_SHIRQ is not set
1368CONFIG_DETECT_SOFTLOCKUP=y
1369# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1370CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1371CONFIG_DETECT_HUNG_TASK=y
1372# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
1373CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
1374# CONFIG_SCHED_DEBUG is not set
1375# CONFIG_SCHEDSTATS is not set
1376# CONFIG_TIMER_STATS is not set
1377# CONFIG_DEBUG_OBJECTS is not set
1378# CONFIG_DEBUG_PREEMPT is not set
1379# CONFIG_DEBUG_RT_MUTEXES is not set
1380# CONFIG_RT_MUTEX_TESTER is not set
1381# CONFIG_DEBUG_SPINLOCK is not set
1382# CONFIG_DEBUG_MUTEXES is not set
1383# CONFIG_DEBUG_LOCK_ALLOC is not set
1384# CONFIG_PROVE_LOCKING is not set
1385# CONFIG_LOCK_STAT is not set
1386# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1387# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1388# CONFIG_DEBUG_KOBJECT is not set
1389CONFIG_DEBUG_INFO=y
1390# CONFIG_DEBUG_VM is not set
1391# CONFIG_DEBUG_WRITECOUNT is not set
1392# CONFIG_DEBUG_MEMORY_INIT is not set
1393# CONFIG_DEBUG_LIST is not set
1394# CONFIG_DEBUG_SG is not set
1395# CONFIG_DEBUG_NOTIFIERS is not set
1396# CONFIG_BOOT_PRINTK_DELAY is not set
1397# CONFIG_RCU_TORTURE_TEST is not set
1398# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1399# CONFIG_BACKTRACE_SELF_TEST is not set
1400# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1401# CONFIG_FAULT_INJECTION is not set
1402# CONFIG_PAGE_POISONING is not set
1403CONFIG_TRACING_SUPPORT=y
1404CONFIG_FTRACE=y
1405# CONFIG_IRQSOFF_TRACER is not set
1406# CONFIG_PREEMPT_TRACER is not set
1407# CONFIG_SCHED_TRACER is not set
1408# CONFIG_ENABLE_DEFAULT_TRACERS is not set
1409# CONFIG_BOOT_TRACER is not set
1410CONFIG_BRANCH_PROFILE_NONE=y
1411# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
1412# CONFIG_PROFILE_ALL_BRANCHES is not set
1413# CONFIG_KMEMTRACE is not set
1414# CONFIG_WORKQUEUE_TRACER is not set
1415# CONFIG_BLK_DEV_IO_TRACE is not set
1416# CONFIG_DYNAMIC_DEBUG is not set
1417# CONFIG_SAMPLES is not set
1418CONFIG_HAVE_ARCH_KGDB=y
1419# CONFIG_KGDB is not set
1420# CONFIG_KMEMCHECK is not set
1421CONFIG_CMDLINE_BOOL=y
1422CONFIG_CMDLINE="rw dhash_entries=1024 ihash_entries=1024 ip=10.0.1.3:10.0.1.1:10.0.1.1:255.255.255.0:zeus:eth0: root=/dev/nfs nfsroot=/nfsroot/cramfs,wsize=512,rsize=512,tcp nokgdb console=ttyUSB0,115200 memsize=252M"
1423# CONFIG_CMDLINE_OVERRIDE is not set
1424# CONFIG_DEBUG_STACK_USAGE is not set
1425# CONFIG_RUNTIME_DEBUG is not set
1426
1427#
1428# Security options
1429#
1430# CONFIG_KEYS is not set
1431# CONFIG_SECURITY is not set
1432# CONFIG_SECURITYFS is not set
1433# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1434CONFIG_CRYPTO=y
1435
1436#
1437# Crypto core or helper
1438#
1439# CONFIG_CRYPTO_FIPS is not set
1440CONFIG_CRYPTO_ALGAPI=y
1441CONFIG_CRYPTO_ALGAPI2=y
1442CONFIG_CRYPTO_AEAD=y
1443CONFIG_CRYPTO_AEAD2=y
1444CONFIG_CRYPTO_BLKCIPHER=y
1445CONFIG_CRYPTO_BLKCIPHER2=y
1446CONFIG_CRYPTO_HASH=y
1447CONFIG_CRYPTO_HASH2=y
1448CONFIG_CRYPTO_RNG2=y
1449CONFIG_CRYPTO_PCOMP=y
1450CONFIG_CRYPTO_MANAGER=y
1451CONFIG_CRYPTO_MANAGER2=y
1452# CONFIG_CRYPTO_GF128MUL is not set
1453# CONFIG_CRYPTO_NULL is not set
1454CONFIG_CRYPTO_WORKQUEUE=y
1455# CONFIG_CRYPTO_CRYPTD is not set
1456CONFIG_CRYPTO_AUTHENC=y
1457# CONFIG_CRYPTO_TEST is not set
1458
1459#
1460# Authenticated Encryption with Associated Data
1461#
1462# CONFIG_CRYPTO_CCM is not set
1463# CONFIG_CRYPTO_GCM is not set
1464# CONFIG_CRYPTO_SEQIV is not set
1465
1466#
1467# Block modes
1468#
1469CONFIG_CRYPTO_CBC=y
1470# CONFIG_CRYPTO_CTR is not set
1471# CONFIG_CRYPTO_CTS is not set
1472# CONFIG_CRYPTO_ECB is not set
1473# CONFIG_CRYPTO_LRW is not set
1474# CONFIG_CRYPTO_PCBC is not set
1475# CONFIG_CRYPTO_XTS is not set
1476
1477#
1478# Hash modes
1479#
1480CONFIG_CRYPTO_HMAC=y
1481# CONFIG_CRYPTO_XCBC is not set
1482
1483#
1484# Digest
1485#
1486# CONFIG_CRYPTO_CRC32C is not set
1487# CONFIG_CRYPTO_MD4 is not set
1488CONFIG_CRYPTO_MD5=y
1489# CONFIG_CRYPTO_MICHAEL_MIC is not set
1490# CONFIG_CRYPTO_RMD128 is not set
1491# CONFIG_CRYPTO_RMD160 is not set
1492# CONFIG_CRYPTO_RMD256 is not set
1493# CONFIG_CRYPTO_RMD320 is not set
1494CONFIG_CRYPTO_SHA1=y
1495# CONFIG_CRYPTO_SHA256 is not set
1496# CONFIG_CRYPTO_SHA512 is not set
1497# CONFIG_CRYPTO_TGR192 is not set
1498# CONFIG_CRYPTO_WP512 is not set
1499
1500#
1501# Ciphers
1502#
1503# CONFIG_CRYPTO_AES is not set
1504# CONFIG_CRYPTO_ANUBIS is not set
1505# CONFIG_CRYPTO_ARC4 is not set
1506# CONFIG_CRYPTO_BLOWFISH is not set
1507# CONFIG_CRYPTO_CAMELLIA is not set
1508# CONFIG_CRYPTO_CAST5 is not set
1509# CONFIG_CRYPTO_CAST6 is not set
1510CONFIG_CRYPTO_DES=y
1511# CONFIG_CRYPTO_FCRYPT is not set
1512# CONFIG_CRYPTO_KHAZAD is not set
1513# CONFIG_CRYPTO_SALSA20 is not set
1514# CONFIG_CRYPTO_SEED is not set
1515# CONFIG_CRYPTO_SERPENT is not set
1516# CONFIG_CRYPTO_TEA is not set
1517# CONFIG_CRYPTO_TWOFISH is not set
1518
1519#
1520# Compression
1521#
1522CONFIG_CRYPTO_DEFLATE=y
1523# CONFIG_CRYPTO_ZLIB is not set
1524# CONFIG_CRYPTO_LZO is not set
1525
1526#
1527# Random Number Generation
1528#
1529# CONFIG_CRYPTO_ANSI_CPRNG is not set
1530# CONFIG_CRYPTO_HW is not set
1531# CONFIG_BINARY_PRINTF is not set
1532
1533#
1534# Library routines
1535#
1536CONFIG_BITREVERSE=y
1537CONFIG_GENERIC_FIND_LAST_BIT=y
1538# CONFIG_CRC_CCITT is not set
1539# CONFIG_CRC16 is not set
1540# CONFIG_CRC_T10DIF is not set
1541# CONFIG_CRC_ITU_T is not set
1542CONFIG_CRC32=y
1543# CONFIG_CRC7 is not set
1544# CONFIG_LIBCRC32C is not set
1545CONFIG_ZLIB_INFLATE=y
1546CONFIG_ZLIB_DEFLATE=y
1547CONFIG_HAS_IOMEM=y
1548CONFIG_HAS_IOPORT=y
1549CONFIG_HAS_DMA=y
1550CONFIG_NLATTR=y
diff --git a/arch/mips/configs/rb532_defconfig b/arch/mips/configs/rb532_defconfig
index f40c3a04739d..57a50483abdf 100644
--- a/arch/mips/configs/rb532_defconfig
+++ b/arch/mips/configs/rb532_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set 12# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set 13# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set 14# CONFIG_MACH_DECSTATION is not set
@@ -1204,7 +1203,7 @@ CONFIG_FRAME_WARN=1024
1204# CONFIG_HEADERS_CHECK is not set 1203# CONFIG_HEADERS_CHECK is not set
1205# CONFIG_DEBUG_KERNEL is not set 1204# CONFIG_DEBUG_KERNEL is not set
1206# CONFIG_SAMPLES is not set 1205# CONFIG_SAMPLES is not set
1207CONFIG_CMDLINE="" 1206# CONFIG_CMDLINE_BOOL is not set
1208 1207
1209# 1208#
1210# Security options 1209# Security options
diff --git a/arch/mips/configs/rbtx49xx_defconfig b/arch/mips/configs/rbtx49xx_defconfig
index 6c6a19aebe1f..21c2022d46ee 100644
--- a/arch/mips/configs/rbtx49xx_defconfig
+++ b/arch/mips/configs/rbtx49xx_defconfig
@@ -10,7 +10,6 @@ CONFIG_MIPS=y
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_AR7 is not set 12# CONFIG_AR7 is not set
13# CONFIG_BASLER_EXCITE is not set
14# CONFIG_BCM47XX is not set 13# CONFIG_BCM47XX is not set
15# CONFIG_BCM63XX is not set 14# CONFIG_BCM63XX is not set
16# CONFIG_MIPS_COBALT is not set 15# CONFIG_MIPS_COBALT is not set
@@ -284,7 +283,6 @@ CONFIG_DEFAULT_AS=y
284# CONFIG_DEFAULT_CFQ is not set 283# CONFIG_DEFAULT_CFQ is not set
285# CONFIG_DEFAULT_NOOP is not set 284# CONFIG_DEFAULT_NOOP is not set
286CONFIG_DEFAULT_IOSCHED="anticipatory" 285CONFIG_DEFAULT_IOSCHED="anticipatory"
287# CONFIG_PROBE_INITRD_HEADER is not set
288# CONFIG_FREEZER is not set 286# CONFIG_FREEZER is not set
289 287
290# 288#
@@ -1063,7 +1061,7 @@ CONFIG_TRACING_SUPPORT=y
1063# CONFIG_DYNAMIC_DEBUG is not set 1061# CONFIG_DYNAMIC_DEBUG is not set
1064# CONFIG_SAMPLES is not set 1062# CONFIG_SAMPLES is not set
1065CONFIG_HAVE_ARCH_KGDB=y 1063CONFIG_HAVE_ARCH_KGDB=y
1066CONFIG_CMDLINE="" 1064# CONFIG_CMDLINE_BOOL is not set
1067 1065
1068# 1066#
1069# Security options 1067# Security options
diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig
index e53b8d096cfc..790362890033 100644
--- a/arch/mips/configs/rm200_defconfig
+++ b/arch/mips/configs/rm200_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
22# CONFIG_MIPS_DB1550 is not set 22# CONFIG_MIPS_DB1550 is not set
23# CONFIG_MIPS_DB1200 is not set 23# CONFIG_MIPS_DB1200 is not set
24# CONFIG_MIPS_MIRAGE is not set 24# CONFIG_MIPS_MIRAGE is not set
25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 25# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 26# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MACH_JAZZ is not set 27# CONFIG_MACH_JAZZ is not set
@@ -1694,7 +1693,7 @@ CONFIG_ENABLE_MUST_CHECK=y
1694# CONFIG_DEBUG_KERNEL is not set 1693# CONFIG_DEBUG_KERNEL is not set
1695CONFIG_LOG_BUF_SHIFT=14 1694CONFIG_LOG_BUF_SHIFT=14
1696CONFIG_CROSSCOMPILE=y 1695CONFIG_CROSSCOMPILE=y
1697CONFIG_CMDLINE="" 1696# CONFIG_CMDLINE_BOOL is not set
1698 1697
1699# 1698#
1700# Security options 1699# Security options
diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig
index 7f38c0b956f3..7f07bf02b838 100644
--- a/arch/mips/configs/sb1250-swarm_defconfig
+++ b/arch/mips/configs/sb1250-swarm_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set 12# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set 13# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set 14# CONFIG_MACH_DECSTATION is not set
@@ -961,7 +960,7 @@ CONFIG_ENABLE_MUST_CHECK=y
961# CONFIG_HEADERS_CHECK is not set 960# CONFIG_HEADERS_CHECK is not set
962# CONFIG_DEBUG_KERNEL is not set 961# CONFIG_DEBUG_KERNEL is not set
963# CONFIG_SAMPLES is not set 962# CONFIG_SAMPLES is not set
964CONFIG_CMDLINE="" 963# CONFIG_CMDLINE_BOOL is not set
965# CONFIG_SB1XXX_CORELIS is not set 964# CONFIG_SB1XXX_CORELIS is not set
966 965
967# 966#
diff --git a/arch/mips/configs/tb0219_defconfig b/arch/mips/configs/tb0219_defconfig
index b5059881bc7e..c54d1128f9a3 100644
--- a/arch/mips/configs/tb0219_defconfig
+++ b/arch/mips/configs/tb0219_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set 12# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set 13# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set 14# CONFIG_MACH_DECSTATION is not set
@@ -892,7 +891,9 @@ CONFIG_FRAME_WARN=1024
892# CONFIG_HEADERS_CHECK is not set 891# CONFIG_HEADERS_CHECK is not set
893# CONFIG_DEBUG_KERNEL is not set 892# CONFIG_DEBUG_KERNEL is not set
894# CONFIG_SAMPLES is not set 893# CONFIG_SAMPLES is not set
894CONFIG_CMDLINE_BOOL=y
895CONFIG_CMDLINE="cca=3 mem=64M console=ttyVR0,115200 ip=any root=/dev/nfs" 895CONFIG_CMDLINE="cca=3 mem=64M console=ttyVR0,115200 ip=any root=/dev/nfs"
896# CONFIG_CMDLINE_OVERRIDE is not set
896 897
897# 898#
898# Security options 899# Security options
diff --git a/arch/mips/configs/tb0226_defconfig b/arch/mips/configs/tb0226_defconfig
index b06a716bf23f..e7c5cd32a2bd 100644
--- a/arch/mips/configs/tb0226_defconfig
+++ b/arch/mips/configs/tb0226_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set 12# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set 13# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set 14# CONFIG_MACH_DECSTATION is not set
@@ -895,7 +894,9 @@ CONFIG_FRAME_WARN=1024
895# CONFIG_HEADERS_CHECK is not set 894# CONFIG_HEADERS_CHECK is not set
896# CONFIG_DEBUG_KERNEL is not set 895# CONFIG_DEBUG_KERNEL is not set
897# CONFIG_SAMPLES is not set 896# CONFIG_SAMPLES is not set
897CONFIG_CMDLINE_BOOL=y
898CONFIG_CMDLINE="cca=3 mem=32M console=ttyVR0,115200" 898CONFIG_CMDLINE="cca=3 mem=32M console=ttyVR0,115200"
899# CONFIG_CMDLINE_OVERRIDE is not set
899 900
900# 901#
901# Security options 902# Security options
diff --git a/arch/mips/configs/tb0287_defconfig b/arch/mips/configs/tb0287_defconfig
index 46512cf7ce04..b50032ba4d01 100644
--- a/arch/mips/configs/tb0287_defconfig
+++ b/arch/mips/configs/tb0287_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set 12# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set 13# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set 14# CONFIG_MACH_DECSTATION is not set
@@ -1077,7 +1076,9 @@ CONFIG_FRAME_WARN=1024
1077# CONFIG_HEADERS_CHECK is not set 1076# CONFIG_HEADERS_CHECK is not set
1078# CONFIG_DEBUG_KERNEL is not set 1077# CONFIG_DEBUG_KERNEL is not set
1079# CONFIG_SAMPLES is not set 1078# CONFIG_SAMPLES is not set
1079CONFIG_CMDLINE_BOOL=y
1080CONFIG_CMDLINE="cca=3 mem=64M console=ttyVR0,115200 ip=any root=/dev/nfs" 1080CONFIG_CMDLINE="cca=3 mem=64M console=ttyVR0,115200 ip=any root=/dev/nfs"
1081# CONFIG_CMDLINE_OVERRIDE is not set
1081 1082
1082# 1083#
1083# Security options 1084# Security options
diff --git a/arch/mips/configs/workpad_defconfig b/arch/mips/configs/workpad_defconfig
index b437eb7f8672..c02ba08b69ab 100644
--- a/arch/mips/configs/workpad_defconfig
+++ b/arch/mips/configs/workpad_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_MIPS_COBALT is not set 12# CONFIG_MIPS_COBALT is not set
14# CONFIG_MACH_DECSTATION is not set 13# CONFIG_MACH_DECSTATION is not set
15# CONFIG_MACH_JAZZ is not set 14# CONFIG_MACH_JAZZ is not set
@@ -755,7 +754,9 @@ CONFIG_ENABLE_MUST_CHECK=y
755# CONFIG_HEADERS_CHECK is not set 754# CONFIG_HEADERS_CHECK is not set
756# CONFIG_DEBUG_KERNEL is not set 755# CONFIG_DEBUG_KERNEL is not set
757CONFIG_CROSSCOMPILE=y 756CONFIG_CROSSCOMPILE=y
757CONFIG_CMDLINE_BOOL=y
758CONFIG_CMDLINE="console=ttyVR0,19200 ide0=0x170,0x376,49 mem=16M" 758CONFIG_CMDLINE="console=ttyVR0,19200 ide0=0x170,0x376,49 mem=16M"
759# CONFIG_CMDLINE_OVERRIDE is not set
759 760
760# 761#
761# Security options 762# Security options
diff --git a/arch/mips/configs/wrppmc_defconfig b/arch/mips/configs/wrppmc_defconfig
index 06acc7482e4c..a35bc41389e5 100644
--- a/arch/mips/configs/wrppmc_defconfig
+++ b/arch/mips/configs/wrppmc_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
22# CONFIG_MIPS_DB1550 is not set 22# CONFIG_MIPS_DB1550 is not set
23# CONFIG_MIPS_DB1200 is not set 23# CONFIG_MIPS_DB1200 is not set
24# CONFIG_MIPS_MIRAGE is not set 24# CONFIG_MIPS_MIRAGE is not set
25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 25# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 26# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MACH_JAZZ is not set 27# CONFIG_MACH_JAZZ is not set
@@ -887,7 +886,9 @@ CONFIG_ENABLE_MUST_CHECK=y
887# CONFIG_DEBUG_KERNEL is not set 886# CONFIG_DEBUG_KERNEL is not set
888CONFIG_LOG_BUF_SHIFT=14 887CONFIG_LOG_BUF_SHIFT=14
889CONFIG_CROSSCOMPILE=y 888CONFIG_CROSSCOMPILE=y
889CONFIG_CMDLINE_BOOL=y
890CONFIG_CMDLINE="console=ttyS0,115200n8" 890CONFIG_CMDLINE="console=ttyS0,115200n8"
891# CONFIG_CMDLINE_OVERRIDE is not set
891 892
892# 893#
893# Security options 894# Security options
diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig
index 69feaf88b510..e3d68d651e7d 100644
--- a/arch/mips/configs/yosemite_defconfig
+++ b/arch/mips/configs/yosemite_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
22# CONFIG_MIPS_DB1550 is not set 22# CONFIG_MIPS_DB1550 is not set
23# CONFIG_MIPS_DB1200 is not set 23# CONFIG_MIPS_DB1200 is not set
24# CONFIG_MIPS_MIRAGE is not set 24# CONFIG_MIPS_MIRAGE is not set
25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 25# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 26# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MACH_JAZZ is not set 27# CONFIG_MACH_JAZZ is not set
@@ -824,7 +823,7 @@ CONFIG_DEBUG_MUTEXES=y
824CONFIG_FORCED_INLINING=y 823CONFIG_FORCED_INLINING=y
825# CONFIG_RCU_TORTURE_TEST is not set 824# CONFIG_RCU_TORTURE_TEST is not set
826CONFIG_CROSSCOMPILE=y 825CONFIG_CROSSCOMPILE=y
827CONFIG_CMDLINE="" 826# CONFIG_CMDLINE_BOOL is not set
828# CONFIG_DEBUG_STACK_USAGE is not set 827# CONFIG_DEBUG_STACK_USAGE is not set
829# CONFIG_RUNTIME_DEBUG is not set 828# CONFIG_RUNTIME_DEBUG is not set
830 829
diff --git a/arch/mips/fw/arc/cmdline.c b/arch/mips/fw/arc/cmdline.c
index 4ca4eef934a5..5c8603c85f20 100644
--- a/arch/mips/fw/arc/cmdline.c
+++ b/arch/mips/fw/arc/cmdline.c
@@ -16,11 +16,6 @@
16 16
17#undef DEBUG_CMDLINE 17#undef DEBUG_CMDLINE
18 18
19char * __init prom_getcmdline(void)
20{
21 return arcs_cmdline;
22}
23
24static char *ignored[] = { 19static char *ignored[] = {
25 "ConsoleIn=", 20 "ConsoleIn=",
26 "ConsoleOut=", 21 "ConsoleOut=",
diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index f5dfaf6a1606..09eee09780f2 100644
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -67,9 +67,9 @@
67#define MACH_LEMOTE_ML2F7 3 67#define MACH_LEMOTE_ML2F7 3
68#define MACH_LEMOTE_YL2F89 4 68#define MACH_LEMOTE_YL2F89 4
69#define MACH_DEXXON_GDIUM2F10 5 69#define MACH_DEXXON_GDIUM2F10 5
70#define MACH_LOONGSON_END 6 70#define MACH_LEMOTE_NAS 6
71 71#define MACH_LEMOTE_LL2F 7
72#define CL_SIZE COMMAND_LINE_SIZE 72#define MACH_LOONGSON_END 8
73 73
74extern char *system_type; 74extern char *system_type;
75const char *get_system_type(void); 75const char *get_system_type(void);
@@ -107,7 +107,7 @@ extern void free_init_pages(const char *what,
107/* 107/*
108 * Initial kernel command line, usually setup by prom_init() 108 * Initial kernel command line, usually setup by prom_init()
109 */ 109 */
110extern char arcs_cmdline[CL_SIZE]; 110extern char arcs_cmdline[COMMAND_LINE_SIZE];
111 111
112/* 112/*
113 * Registers a0, a1, a3 and a4 as passed to the kernel entry by firmware 113 * Registers a0, a1, a3 and a4 as passed to the kernel entry by firmware
diff --git a/arch/mips/include/asm/clock.h b/arch/mips/include/asm/clock.h
new file mode 100644
index 000000000000..83894aa7932c
--- /dev/null
+++ b/arch/mips/include/asm/clock.h
@@ -0,0 +1,64 @@
1#ifndef __ASM_MIPS_CLOCK_H
2#define __ASM_MIPS_CLOCK_H
3
4#include <linux/kref.h>
5#include <linux/list.h>
6#include <linux/seq_file.h>
7#include <linux/clk.h>
8
9extern void (*cpu_wait) (void);
10
11struct clk;
12
13struct clk_ops {
14 void (*init) (struct clk *clk);
15 void (*enable) (struct clk *clk);
16 void (*disable) (struct clk *clk);
17 void (*recalc) (struct clk *clk);
18 int (*set_rate) (struct clk *clk, unsigned long rate, int algo_id);
19 long (*round_rate) (struct clk *clk, unsigned long rate);
20};
21
22struct clk {
23 struct list_head node;
24 const char *name;
25 int id;
26 struct module *owner;
27
28 struct clk *parent;
29 struct clk_ops *ops;
30
31 struct kref kref;
32
33 unsigned long rate;
34 unsigned long flags;
35};
36
37#define CLK_ALWAYS_ENABLED (1 << 0)
38#define CLK_RATE_PROPAGATES (1 << 1)
39
40/* Should be defined by processor-specific code */
41void arch_init_clk_ops(struct clk_ops **, int type);
42
43int clk_init(void);
44
45int __clk_enable(struct clk *);
46void __clk_disable(struct clk *);
47
48void clk_recalc_rate(struct clk *);
49
50int clk_register(struct clk *);
51void clk_unregister(struct clk *);
52
53/* the exported API, in addition to clk_set_rate */
54/**
55 * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter
56 * @clk: clock source
57 * @rate: desired clock rate in Hz
58 * @algo_id: algorithm id to be passed down to ops->set_rate
59 *
60 * Returns success (0) or negative errno.
61 */
62int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id);
63
64#endif /* __ASM_MIPS_CLOCK_H */
diff --git a/arch/mips/include/asm/cop2.h b/arch/mips/include/asm/cop2.h
new file mode 100644
index 000000000000..6b04c98b7fad
--- /dev/null
+++ b/arch/mips/include/asm/cop2.h
@@ -0,0 +1,23 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2009 Wind River Systems,
7 * written by Ralf Baechle <ralf@linux-mips.org>
8 */
9#ifndef __ASM_COP2_H
10#define __ASM_COP2_H
11
12enum cu2_ops {
13 CU2_EXCEPTION,
14 CU2_LWC2_OP,
15 CU2_LDC2_OP,
16 CU2_SWC2_OP,
17 CU2_SDC2_OP,
18};
19
20extern int register_cu2_notifier(struct notifier_block *nb);
21extern int cu2_notifier_call_chain(unsigned long val, void *v);
22
23#endif /* __ASM_COP2_H */
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 4b96d1a36056..cf373a95fe4a 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -154,6 +154,8 @@
154#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ 154#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
155#define PRID_REV_VR4130 0x0080 155#define PRID_REV_VR4130 0x0080
156#define PRID_REV_34K_V1_0_2 0x0022 156#define PRID_REV_34K_V1_0_2 0x0022
157#define PRID_REV_LOONGSON2E 0x0002
158#define PRID_REV_LOONGSON2F 0x0003
157 159
158/* 160/*
159 * Older processors used to encode processor version and revision in two 161 * Older processors used to encode processor version and revision in two
diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h
index 8a3ef247659a..7fcef8ef3fab 100644
--- a/arch/mips/include/asm/fpu.h
+++ b/arch/mips/include/asm/fpu.h
@@ -28,15 +28,7 @@
28struct sigcontext; 28struct sigcontext;
29struct sigcontext32; 29struct sigcontext32;
30 30
31extern asmlinkage int (*save_fp_context)(struct sigcontext __user *sc);
32extern asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc);
33
34extern asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc);
35extern asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc);
36
37extern void fpu_emulator_init_fpu(void); 31extern void fpu_emulator_init_fpu(void);
38extern int fpu_emulator_save_context(struct sigcontext __user *sc);
39extern int fpu_emulator_restore_context(struct sigcontext __user *sc);
40extern void _init_fpu(void); 32extern void _init_fpu(void);
41extern void _save_fp(struct task_struct *); 33extern void _save_fp(struct task_struct *);
42extern void _restore_fp(struct task_struct *); 34extern void _restore_fp(struct task_struct *);
diff --git a/arch/mips/include/asm/fpu_emulator.h b/arch/mips/include/asm/fpu_emulator.h
index e5189572956c..aecada6f6117 100644
--- a/arch/mips/include/asm/fpu_emulator.h
+++ b/arch/mips/include/asm/fpu_emulator.h
@@ -25,17 +25,27 @@
25 25
26#include <asm/break.h> 26#include <asm/break.h>
27#include <asm/inst.h> 27#include <asm/inst.h>
28#include <asm/local.h>
29
30#ifdef CONFIG_DEBUG_FS
28 31
29struct mips_fpu_emulator_stats { 32struct mips_fpu_emulator_stats {
30 unsigned int emulated; 33 local_t emulated;
31 unsigned int loads; 34 local_t loads;
32 unsigned int stores; 35 local_t stores;
33 unsigned int cp1ops; 36 local_t cp1ops;
34 unsigned int cp1xops; 37 local_t cp1xops;
35 unsigned int errors; 38 local_t errors;
36}; 39};
37 40
38extern struct mips_fpu_emulator_stats fpuemustats; 41DECLARE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
42
43#define MIPS_FPU_EMU_INC_STATS(M) \
44 cpu_local_wrap(__local_inc(&__get_cpu_var(fpuemustats).M))
45
46#else
47#define MIPS_FPU_EMU_INC_STATS(M) do { } while (0)
48#endif /* CONFIG_DEBUG_FS */
39 49
40extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, 50extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir,
41 unsigned long cpc); 51 unsigned long cpc);
diff --git a/arch/mips/include/asm/ftrace.h b/arch/mips/include/asm/ftrace.h
index 40a8c178f10d..3986cd8704f3 100644
--- a/arch/mips/include/asm/ftrace.h
+++ b/arch/mips/include/asm/ftrace.h
@@ -1 +1,90 @@
1/* empty */ 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive for
4 * more details.
5 *
6 * Copyright (C) 2009 DSLab, Lanzhou University, China
7 * Author: Wu Zhangjin <wuzj@lemote.com>
8 */
9
10#ifndef _ASM_MIPS_FTRACE_H
11#define _ASM_MIPS_FTRACE_H
12
13#ifdef CONFIG_FUNCTION_TRACER
14
15#define MCOUNT_ADDR ((unsigned long)(_mcount))
16#define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */
17
18#ifndef __ASSEMBLY__
19extern void _mcount(void);
20#define mcount _mcount
21
22#define safe_load(load, src, dst, error) \
23do { \
24 asm volatile ( \
25 "1: " load " %[" STR(dst) "], 0(%[" STR(src) "])\n"\
26 " li %[" STR(error) "], 0\n" \
27 "2:\n" \
28 \
29 ".section .fixup, \"ax\"\n" \
30 "3: li %[" STR(error) "], 1\n" \
31 " j 2b\n" \
32 ".previous\n" \
33 \
34 ".section\t__ex_table,\"a\"\n\t" \
35 STR(PTR) "\t1b, 3b\n\t" \
36 ".previous\n" \
37 \
38 : [dst] "=&r" (dst), [error] "=r" (error)\
39 : [src] "r" (src) \
40 : "memory" \
41 ); \
42} while (0)
43
44#define safe_store(store, src, dst, error) \
45do { \
46 asm volatile ( \
47 "1: " store " %[" STR(src) "], 0(%[" STR(dst) "])\n"\
48 " li %[" STR(error) "], 0\n" \
49 "2:\n" \
50 \
51 ".section .fixup, \"ax\"\n" \
52 "3: li %[" STR(error) "], 1\n" \
53 " j 2b\n" \
54 ".previous\n" \
55 \
56 ".section\t__ex_table,\"a\"\n\t"\
57 STR(PTR) "\t1b, 3b\n\t" \
58 ".previous\n" \
59 \
60 : [error] "=r" (error) \
61 : [dst] "r" (dst), [src] "r" (src)\
62 : "memory" \
63 ); \
64} while (0)
65
66#define safe_load_code(dst, src, error) \
67 safe_load(STR(lw), src, dst, error)
68#define safe_store_code(src, dst, error) \
69 safe_store(STR(sw), src, dst, error)
70
71#define safe_load_stack(dst, src, error) \
72 safe_load(STR(PTR_L), src, dst, error)
73
74#define safe_store_stack(src, dst, error) \
75 safe_store(STR(PTR_S), src, dst, error)
76
77
78#ifdef CONFIG_DYNAMIC_FTRACE
79static inline unsigned long ftrace_call_adjust(unsigned long addr)
80{
81 return addr;
82}
83
84struct dyn_arch_ftrace {
85};
86
87#endif /* CONFIG_DYNAMIC_FTRACE */
88#endif /* __ASSEMBLY__ */
89#endif /* CONFIG_FUNCTION_TRACER */
90#endif /* _ASM_MIPS_FTRACE_H */
diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h
index 09b08d05ff72..06960364c96b 100644
--- a/arch/mips/include/asm/irq.h
+++ b/arch/mips/include/asm/irq.h
@@ -113,36 +113,11 @@ do { \
113 113
114#endif 114#endif
115 115
116/* 116extern void do_IRQ(unsigned int irq);
117 * do_IRQ handles all normal device IRQ's (the special
118 * SMP cross-CPU interrupts have their own specific
119 * handlers).
120 *
121 * Ideally there should be away to get this into kernel/irq/handle.c to
122 * avoid the overhead of a call for just a tiny function ...
123 */
124#define do_IRQ(irq) \
125do { \
126 irq_enter(); \
127 __DO_IRQ_SMTC_HOOK(irq); \
128 generic_handle_irq(irq); \
129 irq_exit(); \
130} while (0)
131 117
132#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF 118#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
133/*
134 * To avoid inefficient and in some cases pathological re-checking of
135 * IRQ affinity, we have this variant that skips the affinity check.
136 */
137
138 119
139#define do_IRQ_no_affinity(irq) \ 120extern void do_IRQ_no_affinity(unsigned int irq);
140do { \
141 irq_enter(); \
142 __NO_AFFINITY_IRQ_SMTC_HOOK(irq); \
143 generic_handle_irq(irq); \
144 irq_exit(); \
145} while (0)
146 121
147#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ 122#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
148 123
diff --git a/arch/mips/include/asm/mach-excite/cpu-feature-overrides.h b/arch/mips/include/asm/mach-excite/cpu-feature-overrides.h
deleted file mode 100644
index 107104c3cd12..000000000000
--- a/arch/mips/include/asm/mach-excite/cpu-feature-overrides.h
+++ /dev/null
@@ -1,48 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004 Thomas Koeller <thomas.koeller@baslerweb.com>
7 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
8 */
9#ifndef __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
10#define __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
11
12/*
13 * Basler eXcite has an RM9122 processor.
14 */
15#define cpu_has_watch 1
16#define cpu_has_mips16 0
17#define cpu_has_divec 0
18#define cpu_has_vce 0
19#define cpu_has_cache_cdex_p 0
20#define cpu_has_cache_cdex_s 0
21#define cpu_has_prefetch 1
22#define cpu_has_mcheck 0
23#define cpu_has_ejtag 0
24
25#define cpu_has_llsc 1
26#define cpu_has_vtag_icache 0
27#define cpu_has_dc_aliases 0
28#define cpu_has_ic_fills_f_dc 0
29#define cpu_has_dsp 0
30#define cpu_icache_snoops_remote_store 0
31#define cpu_has_mipsmt 0
32#define cpu_has_userlocal 0
33
34#define cpu_has_nofpuex 0
35#define cpu_has_64bits 1
36
37#define cpu_has_mips32r1 0
38#define cpu_has_mips32r2 0
39#define cpu_has_mips64r1 0
40#define cpu_has_mips64r2 0
41
42#define cpu_has_inclusive_pcaches 0
43
44#define cpu_dcache_line_size() 32
45#define cpu_icache_line_size() 32
46#define cpu_scache_line_size() 32
47
48#endif /* __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-excite/excite.h b/arch/mips/include/asm/mach-excite/excite.h
deleted file mode 100644
index 4c29ba44992c..000000000000
--- a/arch/mips/include/asm/mach-excite/excite.h
+++ /dev/null
@@ -1,154 +0,0 @@
1#ifndef __EXCITE_H__
2#define __EXCITE_H__
3
4#include <linux/init.h>
5#include <asm/addrspace.h>
6#include <asm/types.h>
7
8#define EXCITE_CPU_EXT_CLOCK 100000000
9
10#if !defined(__ASSEMBLY__)
11void __init excite_kgdb_init(void);
12void excite_procfs_init(void);
13extern unsigned long memsize;
14extern char modetty[];
15extern u32 unit_id;
16#endif
17
18/* Base name for XICAP devices */
19#define XICAP_NAME "xicap_gpi"
20
21/* OCD register offsets */
22#define LKB0 0x0038
23#define LKB5 0x0128
24#define LKM5 0x012C
25#define LKB7 0x0138
26#define LKM7 0x013c
27#define LKB8 0x0140
28#define LKM8 0x0144
29#define LKB9 0x0148
30#define LKM9 0x014c
31#define LKB10 0x0150
32#define LKM10 0x0154
33#define LKB11 0x0158
34#define LKM11 0x015c
35#define LKB12 0x0160
36#define LKM12 0x0164
37#define LKB13 0x0168
38#define LKM13 0x016c
39#define LDP0 0x0200
40#define LDP1 0x0210
41#define LDP2 0x0220
42#define LDP3 0x0230
43#define INTPIN0 0x0A40
44#define INTPIN1 0x0A44
45#define INTPIN2 0x0A48
46#define INTPIN3 0x0A4C
47#define INTPIN4 0x0A50
48#define INTPIN5 0x0A54
49#define INTPIN6 0x0A58
50#define INTPIN7 0x0A5C
51
52
53
54
55/* TITAN register offsets */
56#define CPRR 0x0004
57#define CPDSR 0x0008
58#define CPTC0R 0x000c
59#define CPTC1R 0x0010
60#define CPCFG0 0x0020
61#define CPCFG1 0x0024
62#define CPDST0A 0x0028
63#define CPDST0B 0x002c
64#define CPDST1A 0x0030
65#define CPDST1B 0x0034
66#define CPXDSTA 0x0038
67#define CPXDSTB 0x003c
68#define CPXCISRA 0x0048
69#define CPXCISRB 0x004c
70#define CPGIG0ER 0x0050
71#define CPGIG1ER 0x0054
72#define CPGRWL 0x0068
73#define CPURSLMT 0x00f8
74#define UACFG 0x0200
75#define UAINTS 0x0204
76#define SDRXFCIE 0x4828
77#define SDTXFCIE 0x4928
78#define INTP0Status0 0x1B00
79#define INTP0Mask0 0x1B04
80#define INTP0Set0 0x1B08
81#define INTP0Clear0 0x1B0C
82#define GXCFG 0x5000
83#define GXDMADRPFX 0x5018
84#define GXDMA_DESCADR 0x501c
85#define GXCH0TDESSTRT 0x5054
86
87/* IRQ definitions */
88#define NMICONFIG 0xac0
89#define TITAN_MSGINT 0xc4
90#define TITAN_IRQ ((TITAN_MSGINT / 0x20) + 2)
91#define FPGA0_MSGINT 0x5a
92#define FPGA0_IRQ ((FPGA0_MSGINT / 0x20) + 2)
93#define FPGA1_MSGINT 0x7b
94#define FPGA1_IRQ ((FPGA1_MSGINT / 0x20) + 2)
95#define PHY_MSGINT 0x9c
96#define PHY_IRQ ((PHY_MSGINT / 0x20) + 2)
97
98#if defined(CONFIG_BASLER_EXCITE_PROTOTYPE)
99/* Pre-release units used interrupt pin #9 */
100#define USB_IRQ 11
101#else
102/* Re-designed units use interrupt pin #1 */
103#define USB_MSGINT 0x39
104#define USB_IRQ ((USB_MSGINT / 0x20) + 2)
105#endif
106#define TIMER_IRQ 12
107
108
109/* Device address ranges */
110#define EXCITE_OFFS_OCD 0x1fffc000
111#define EXCITE_SIZE_OCD (16 * 1024)
112#define EXCITE_PHYS_OCD CPHYSADDR(EXCITE_OFFS_OCD)
113#define EXCITE_ADDR_OCD CKSEG1ADDR(EXCITE_OFFS_OCD)
114
115#define EXCITE_OFFS_SCRAM 0x1fffa000
116#define EXCITE_SIZE_SCRAM (8 << 10)
117#define EXCITE_PHYS_SCRAM CPHYSADDR(EXCITE_OFFS_SCRAM)
118#define EXCITE_ADDR_SCRAM CKSEG1ADDR(EXCITE_OFFS_SCRAM)
119
120#define EXCITE_OFFS_PCI_IO 0x1fff8000
121#define EXCITE_SIZE_PCI_IO (8 << 10)
122#define EXCITE_PHYS_PCI_IO CPHYSADDR(EXCITE_OFFS_PCI_IO)
123#define EXCITE_ADDR_PCI_IO CKSEG1ADDR(EXCITE_OFFS_PCI_IO)
124
125#define EXCITE_OFFS_TITAN 0x1fff0000
126#define EXCITE_SIZE_TITAN (32 << 10)
127#define EXCITE_PHYS_TITAN CPHYSADDR(EXCITE_OFFS_TITAN)
128#define EXCITE_ADDR_TITAN CKSEG1ADDR(EXCITE_OFFS_TITAN)
129
130#define EXCITE_OFFS_PCI_MEM 0x1ffe0000
131#define EXCITE_SIZE_PCI_MEM (64 << 10)
132#define EXCITE_PHYS_PCI_MEM CPHYSADDR(EXCITE_OFFS_PCI_MEM)
133#define EXCITE_ADDR_PCI_MEM CKSEG1ADDR(EXCITE_OFFS_PCI_MEM)
134
135#define EXCITE_OFFS_FPGA 0x1ffdc000
136#define EXCITE_SIZE_FPGA (16 << 10)
137#define EXCITE_PHYS_FPGA CPHYSADDR(EXCITE_OFFS_FPGA)
138#define EXCITE_ADDR_FPGA CKSEG1ADDR(EXCITE_OFFS_FPGA)
139
140#define EXCITE_OFFS_NAND 0x1ffd8000
141#define EXCITE_SIZE_NAND (16 << 10)
142#define EXCITE_PHYS_NAND CPHYSADDR(EXCITE_OFFS_NAND)
143#define EXCITE_ADDR_NAND CKSEG1ADDR(EXCITE_OFFS_NAND)
144
145#define EXCITE_OFFS_BOOTROM 0x1f000000
146#define EXCITE_SIZE_BOOTROM (8 << 20)
147#define EXCITE_PHYS_BOOTROM CPHYSADDR(EXCITE_OFFS_BOOTROM)
148#define EXCITE_ADDR_BOOTROM CKSEG1ADDR(EXCITE_OFFS_BOOTROM)
149
150/* FPGA address offsets */
151#define EXCITE_FPGA_DPR 0x0104 /* dual-ported ram */
152#define EXCITE_FPGA_SYSCTL 0x0200 /* system control register block */
153
154#endif /* __EXCITE_H__ */
diff --git a/arch/mips/include/asm/mach-excite/excite_fpga.h b/arch/mips/include/asm/mach-excite/excite_fpga.h
deleted file mode 100644
index 0a1ef69bece7..000000000000
--- a/arch/mips/include/asm/mach-excite/excite_fpga.h
+++ /dev/null
@@ -1,80 +0,0 @@
1#ifndef EXCITE_FPGA_H_INCLUDED
2#define EXCITE_FPGA_H_INCLUDED
3
4
5/**
6 * Address alignment of the individual FPGA bytes.
7 * The address arrangement of the individual bytes of the FPGA is two
8 * byte aligned at the embedded MK2 platform.
9 */
10#ifdef EXCITE_CCI_FPGA_MK2
11typedef unsigned char excite_cci_fpga_align_t __attribute__ ((aligned(2)));
12#else
13typedef unsigned char excite_cci_fpga_align_t;
14#endif
15
16
17/**
18 * Size of Dual Ported RAM.
19 */
20#define EXCITE_DPR_SIZE 263
21
22
23/**
24 * Size of Reserved Status Fields in Dual Ported RAM.
25 */
26#define EXCITE_DPR_STATUS_SIZE 7
27
28
29
30/**
31 * FPGA.
32 * Hardware register layout of the FPGA interface. The FPGA must accessed
33 * byte wise solely.
34 * @see EXCITE_CCI_DPR_MK2
35 */
36typedef struct excite_fpga {
37
38 /**
39 * Dual Ported RAM.
40 */
41 excite_cci_fpga_align_t dpr[EXCITE_DPR_SIZE];
42
43 /**
44 * Status.
45 */
46 excite_cci_fpga_align_t status[EXCITE_DPR_STATUS_SIZE];
47
48#ifdef EXCITE_CCI_FPGA_MK2
49 /**
50 * RM9000 Interrupt.
51 * Write access initiates interrupt at the RM9000 (MIPS) processor of the eXcite.
52 */
53 excite_cci_fpga_align_t rm9k_int;
54#else
55 /**
56 * MK2 Interrupt.
57 * Write access initiates interrupt at the ARM processor of the MK2.
58 */
59 excite_cci_fpga_align_t mk2_int;
60
61 excite_cci_fpga_align_t gap[0x1000-0x10f];
62
63 /**
64 * IRQ Source/Acknowledge.
65 */
66 excite_cci_fpga_align_t rm9k_irq_src;
67
68 /**
69 * IRQ Mask.
70 * Set bits enable the related interrupt.
71 */
72 excite_cci_fpga_align_t rm9k_irq_mask;
73#endif
74
75
76} excite_fpga;
77
78
79
80#endif /* ndef EXCITE_FPGA_H_INCLUDED */
diff --git a/arch/mips/include/asm/mach-excite/excite_nandflash.h b/arch/mips/include/asm/mach-excite/excite_nandflash.h
deleted file mode 100644
index c4cf6140622e..000000000000
--- a/arch/mips/include/asm/mach-excite/excite_nandflash.h
+++ /dev/null
@@ -1,7 +0,0 @@
1#ifndef __EXCITE_NANDFLASH_H__
2#define __EXCITE_NANDFLASH_H__
3
4/* Resource names */
5#define EXCITE_NANDFLASH_RESOURCE_REGS "excite_nandflash_regs"
6
7#endif /* __EXCITE_NANDFLASH_H__ */
diff --git a/arch/mips/include/asm/mach-excite/rm9k_eth.h b/arch/mips/include/asm/mach-excite/rm9k_eth.h
deleted file mode 100644
index 94705a46f72e..000000000000
--- a/arch/mips/include/asm/mach-excite/rm9k_eth.h
+++ /dev/null
@@ -1,23 +0,0 @@
1#if !defined(__RM9K_ETH_H__)
2#define __RM9K_ETH_H__
3
4#define RM9K_GE_NAME "rm9k_ge"
5
6/* Resource names */
7#define RM9K_GE_RESOURCE_MAC "rm9k_ge_mac"
8#define RM9K_GE_RESOURCE_MSTAT "rm9k_ge_mstat"
9#define RM9K_GE_RESOURCE_PKTPROC "rm9k_ge_pktproc"
10#define RM9K_GE_RESOURCE_XDMA "rm9k_ge_xdma"
11#define RM9K_GE_RESOURCE_FIFO_RX "rm9k_ge_fifo_rx"
12#define RM9K_GE_RESOURCE_FIFO_TX "rm9k_ge_fifo_tx"
13#define RM9K_GE_RESOURCE_FIFOMEM_RX "rm9k_ge_fifo_memory_rx"
14#define RM9K_GE_RESOURCE_FIFOMEM_TX "rm9k_ge_fifo_memory_tx"
15#define RM9K_GE_RESOURCE_PHY "rm9k_ge_phy"
16#define RM9K_GE_RESOURCE_DMADESC_RX "rm9k_ge_dmadesc_rx"
17#define RM9K_GE_RESOURCE_DMADESC_TX "rm9k_ge_dmadesc_tx"
18#define RM9K_GE_RESOURCE_IRQ_MAIN "rm9k_ge_irq_main"
19#define RM9K_GE_RESOURCE_IRQ_PHY "rm9k_ge_irq_phy"
20#define RM9K_GE_RESOURCE_GPI_SLICE "rm9k_ge_gpi_slice"
21#define RM9K_GE_RESOURCE_MDIO_CHANNEL "rm9k_ge_mdio_channel"
22
23#endif /* !defined(__RM9K_ETH_H__) */
diff --git a/arch/mips/include/asm/mach-excite/rm9k_wdt.h b/arch/mips/include/asm/mach-excite/rm9k_wdt.h
deleted file mode 100644
index 3fa3c08d2da7..000000000000
--- a/arch/mips/include/asm/mach-excite/rm9k_wdt.h
+++ /dev/null
@@ -1,12 +0,0 @@
1#ifndef __RM9K_WDT_H__
2#define __RM9K_WDT_H__
3
4/* Device name */
5#define WDT_NAME "wdt_gpi"
6
7/* Resource names */
8#define WDT_RESOURCE_REGS "excite_watchdog_regs"
9#define WDT_RESOURCE_IRQ "excite_watchdog_irq"
10#define WDT_RESOURCE_COUNTER "excite_watchdog_counter"
11
12#endif /* __RM9K_WDT_H__ */
diff --git a/arch/mips/include/asm/mach-excite/rm9k_xicap.h b/arch/mips/include/asm/mach-excite/rm9k_xicap.h
deleted file mode 100644
index 009577734a8d..000000000000
--- a/arch/mips/include/asm/mach-excite/rm9k_xicap.h
+++ /dev/null
@@ -1,16 +0,0 @@
1#ifndef __EXCITE_XICAP_H__
2#define __EXCITE_XICAP_H__
3
4
5/* Resource names */
6#define XICAP_RESOURCE_FIFO_RX "xicap_fifo_rx"
7#define XICAP_RESOURCE_FIFO_TX "xicap_fifo_tx"
8#define XICAP_RESOURCE_XDMA "xicap_xdma"
9#define XICAP_RESOURCE_DMADESC "xicap_dmadesc"
10#define XICAP_RESOURCE_PKTPROC "xicap_pktproc"
11#define XICAP_RESOURCE_IRQ "xicap_irq"
12#define XICAP_RESOURCE_GPI_SLICE "xicap_gpi_slice"
13#define XICAP_RESOURCE_FIFO_BLK "xicap_fifo_blocks"
14#define XICAP_RESOURCE_PKT_STREAM "xicap_pkt_stream"
15
16#endif /* __EXCITE_XICAP_H__ */
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h
new file mode 100644
index 000000000000..021f77ca59ec
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h
@@ -0,0 +1,305 @@
1/*
2 * The header file of cs5536 sourth bridge.
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu <liujl@lemote.com>
6 */
7
8#ifndef _CS5536_H
9#define _CS5536_H
10
11#include <linux/types.h>
12
13extern void _rdmsr(u32 msr, u32 *hi, u32 *lo);
14extern void _wrmsr(u32 msr, u32 hi, u32 lo);
15
16/*
17 * MSR module base
18 */
19#define CS5536_SB_MSR_BASE (0x00000000)
20#define CS5536_GLIU_MSR_BASE (0x10000000)
21#define CS5536_ILLEGAL_MSR_BASE (0x20000000)
22#define CS5536_USB_MSR_BASE (0x40000000)
23#define CS5536_IDE_MSR_BASE (0x60000000)
24#define CS5536_DIVIL_MSR_BASE (0x80000000)
25#define CS5536_ACC_MSR_BASE (0xa0000000)
26#define CS5536_UNUSED_MSR_BASE (0xc0000000)
27#define CS5536_GLCP_MSR_BASE (0xe0000000)
28
29#define SB_MSR_REG(offset) (CS5536_SB_MSR_BASE | (offset))
30#define GLIU_MSR_REG(offset) (CS5536_GLIU_MSR_BASE | (offset))
31#define ILLEGAL_MSR_REG(offset) (CS5536_ILLEGAL_MSR_BASE | (offset))
32#define USB_MSR_REG(offset) (CS5536_USB_MSR_BASE | (offset))
33#define IDE_MSR_REG(offset) (CS5536_IDE_MSR_BASE | (offset))
34#define DIVIL_MSR_REG(offset) (CS5536_DIVIL_MSR_BASE | (offset))
35#define ACC_MSR_REG(offset) (CS5536_ACC_MSR_BASE | (offset))
36#define UNUSED_MSR_REG(offset) (CS5536_UNUSED_MSR_BASE | (offset))
37#define GLCP_MSR_REG(offset) (CS5536_GLCP_MSR_BASE | (offset))
38
39/*
40 * BAR SPACE OF VIRTUAL PCI :
41 * range for pci probe use, length is the actual size.
42 */
43/* IO space for all DIVIL modules */
44#define CS5536_IRQ_RANGE 0xffffffe0 /* USERD FOR PCI PROBE */
45#define CS5536_IRQ_LENGTH 0x20 /* THE REGS ACTUAL LENGTH */
46#define CS5536_SMB_RANGE 0xfffffff8
47#define CS5536_SMB_LENGTH 0x08
48#define CS5536_GPIO_RANGE 0xffffff00
49#define CS5536_GPIO_LENGTH 0x100
50#define CS5536_MFGPT_RANGE 0xffffffc0
51#define CS5536_MFGPT_LENGTH 0x40
52#define CS5536_ACPI_RANGE 0xffffffe0
53#define CS5536_ACPI_LENGTH 0x20
54#define CS5536_PMS_RANGE 0xffffff80
55#define CS5536_PMS_LENGTH 0x80
56/* IO space for IDE */
57#define CS5536_IDE_RANGE 0xfffffff0
58#define CS5536_IDE_LENGTH 0x10
59/* IO space for ACC */
60#define CS5536_ACC_RANGE 0xffffff80
61#define CS5536_ACC_LENGTH 0x80
62/* MEM space for ALL USB modules */
63#define CS5536_OHCI_RANGE 0xfffff000
64#define CS5536_OHCI_LENGTH 0x1000
65#define CS5536_EHCI_RANGE 0xfffff000
66#define CS5536_EHCI_LENGTH 0x1000
67
68/*
69 * PCI MSR ACCESS
70 */
71#define PCI_MSR_CTRL 0xF0
72#define PCI_MSR_ADDR 0xF4
73#define PCI_MSR_DATA_LO 0xF8
74#define PCI_MSR_DATA_HI 0xFC
75
76/**************** MSR *****************************/
77
78/*
79 * GLIU STANDARD MSR
80 */
81#define GLIU_CAP 0x00
82#define GLIU_CONFIG 0x01
83#define GLIU_SMI 0x02
84#define GLIU_ERROR 0x03
85#define GLIU_PM 0x04
86#define GLIU_DIAG 0x05
87
88/*
89 * GLIU SPEC. MSR
90 */
91#define GLIU_P2D_BM0 0x20
92#define GLIU_P2D_BM1 0x21
93#define GLIU_P2D_BM2 0x22
94#define GLIU_P2D_BMK0 0x23
95#define GLIU_P2D_BMK1 0x24
96#define GLIU_P2D_BM3 0x25
97#define GLIU_P2D_BM4 0x26
98#define GLIU_COH 0x80
99#define GLIU_PAE 0x81
100#define GLIU_ARB 0x82
101#define GLIU_ASMI 0x83
102#define GLIU_AERR 0x84
103#define GLIU_DEBUG 0x85
104#define GLIU_PHY_CAP 0x86
105#define GLIU_NOUT_RESP 0x87
106#define GLIU_NOUT_WDATA 0x88
107#define GLIU_WHOAMI 0x8B
108#define GLIU_SLV_DIS 0x8C
109#define GLIU_IOD_BM0 0xE0
110#define GLIU_IOD_BM1 0xE1
111#define GLIU_IOD_BM2 0xE2
112#define GLIU_IOD_BM3 0xE3
113#define GLIU_IOD_BM4 0xE4
114#define GLIU_IOD_BM5 0xE5
115#define GLIU_IOD_BM6 0xE6
116#define GLIU_IOD_BM7 0xE7
117#define GLIU_IOD_BM8 0xE8
118#define GLIU_IOD_BM9 0xE9
119#define GLIU_IOD_SC0 0xEA
120#define GLIU_IOD_SC1 0xEB
121#define GLIU_IOD_SC2 0xEC
122#define GLIU_IOD_SC3 0xED
123#define GLIU_IOD_SC4 0xEE
124#define GLIU_IOD_SC5 0xEF
125#define GLIU_IOD_SC6 0xF0
126#define GLIU_IOD_SC7 0xF1
127
128/*
129 * SB STANDARD
130 */
131#define SB_CAP 0x00
132#define SB_CONFIG 0x01
133#define SB_SMI 0x02
134#define SB_ERROR 0x03
135#define SB_MAR_ERR_EN 0x00000001
136#define SB_TAR_ERR_EN 0x00000002
137#define SB_RSVD_BIT1 0x00000004
138#define SB_EXCEP_ERR_EN 0x00000008
139#define SB_SYSE_ERR_EN 0x00000010
140#define SB_PARE_ERR_EN 0x00000020
141#define SB_TAS_ERR_EN 0x00000040
142#define SB_MAR_ERR_FLAG 0x00010000
143#define SB_TAR_ERR_FLAG 0x00020000
144#define SB_RSVD_BIT2 0x00040000
145#define SB_EXCEP_ERR_FLAG 0x00080000
146#define SB_SYSE_ERR_FLAG 0x00100000
147#define SB_PARE_ERR_FLAG 0x00200000
148#define SB_TAS_ERR_FLAG 0x00400000
149#define SB_PM 0x04
150#define SB_DIAG 0x05
151
152/*
153 * SB SPEC.
154 */
155#define SB_CTRL 0x10
156#define SB_R0 0x20
157#define SB_R1 0x21
158#define SB_R2 0x22
159#define SB_R3 0x23
160#define SB_R4 0x24
161#define SB_R5 0x25
162#define SB_R6 0x26
163#define SB_R7 0x27
164#define SB_R8 0x28
165#define SB_R9 0x29
166#define SB_R10 0x2A
167#define SB_R11 0x2B
168#define SB_R12 0x2C
169#define SB_R13 0x2D
170#define SB_R14 0x2E
171#define SB_R15 0x2F
172
173/*
174 * GLCP STANDARD
175 */
176#define GLCP_CAP 0x00
177#define GLCP_CONFIG 0x01
178#define GLCP_SMI 0x02
179#define GLCP_ERROR 0x03
180#define GLCP_PM 0x04
181#define GLCP_DIAG 0x05
182
183/*
184 * GLCP SPEC.
185 */
186#define GLCP_CLK_DIS_DELAY 0x08
187#define GLCP_PM_CLK_DISABLE 0x09
188#define GLCP_GLB_PM 0x0B
189#define GLCP_DBG_OUT 0x0C
190#define GLCP_RSVD1 0x0D
191#define GLCP_SOFT_COM 0x0E
192#define SOFT_BAR_SMB_FLAG 0x00000001
193#define SOFT_BAR_GPIO_FLAG 0x00000002
194#define SOFT_BAR_MFGPT_FLAG 0x00000004
195#define SOFT_BAR_IRQ_FLAG 0x00000008
196#define SOFT_BAR_PMS_FLAG 0x00000010
197#define SOFT_BAR_ACPI_FLAG 0x00000020
198#define SOFT_BAR_IDE_FLAG 0x00000400
199#define SOFT_BAR_ACC_FLAG 0x00000800
200#define SOFT_BAR_OHCI_FLAG 0x00001000
201#define SOFT_BAR_EHCI_FLAG 0x00002000
202#define GLCP_RSVD2 0x0F
203#define GLCP_CLK_OFF 0x10
204#define GLCP_CLK_ACTIVE 0x11
205#define GLCP_CLK_DISABLE 0x12
206#define GLCP_CLK4ACK 0x13
207#define GLCP_SYS_RST 0x14
208#define GLCP_RSVD3 0x15
209#define GLCP_DBG_CLK_CTRL 0x16
210#define GLCP_CHIP_REV_ID 0x17
211
212/* PIC */
213#define PIC_YSEL_LOW 0x20
214#define PIC_YSEL_LOW_USB_SHIFT 8
215#define PIC_YSEL_LOW_ACC_SHIFT 16
216#define PIC_YSEL_LOW_FLASH_SHIFT 24
217#define PIC_YSEL_HIGH 0x21
218#define PIC_ZSEL_LOW 0x22
219#define PIC_ZSEL_HIGH 0x23
220#define PIC_IRQM_PRIM 0x24
221#define PIC_IRQM_LPC 0x25
222#define PIC_XIRR_STS_LOW 0x26
223#define PIC_XIRR_STS_HIGH 0x27
224#define PCI_SHDW 0x34
225
226/*
227 * DIVIL STANDARD
228 */
229#define DIVIL_CAP 0x00
230#define DIVIL_CONFIG 0x01
231#define DIVIL_SMI 0x02
232#define DIVIL_ERROR 0x03
233#define DIVIL_PM 0x04
234#define DIVIL_DIAG 0x05
235
236/*
237 * DIVIL SPEC.
238 */
239#define DIVIL_LBAR_IRQ 0x08
240#define DIVIL_LBAR_KEL 0x09
241#define DIVIL_LBAR_SMB 0x0B
242#define DIVIL_LBAR_GPIO 0x0C
243#define DIVIL_LBAR_MFGPT 0x0D
244#define DIVIL_LBAR_ACPI 0x0E
245#define DIVIL_LBAR_PMS 0x0F
246#define DIVIL_LEG_IO 0x14
247#define DIVIL_BALL_OPTS 0x15
248#define DIVIL_SOFT_IRQ 0x16
249#define DIVIL_SOFT_RESET 0x17
250
251/* MFGPT */
252#define MFGPT_IRQ 0x28
253
254/*
255 * IDE STANDARD
256 */
257#define IDE_CAP 0x00
258#define IDE_CONFIG 0x01
259#define IDE_SMI 0x02
260#define IDE_ERROR 0x03
261#define IDE_PM 0x04
262#define IDE_DIAG 0x05
263
264/*
265 * IDE SPEC.
266 */
267#define IDE_IO_BAR 0x08
268#define IDE_CFG 0x10
269#define IDE_DTC 0x12
270#define IDE_CAST 0x13
271#define IDE_ETC 0x14
272#define IDE_INTERNAL_PM 0x15
273
274/*
275 * ACC STANDARD
276 */
277#define ACC_CAP 0x00
278#define ACC_CONFIG 0x01
279#define ACC_SMI 0x02
280#define ACC_ERROR 0x03
281#define ACC_PM 0x04
282#define ACC_DIAG 0x05
283
284/*
285 * USB STANDARD
286 */
287#define USB_CAP 0x00
288#define USB_CONFIG 0x01
289#define USB_SMI 0x02
290#define USB_ERROR 0x03
291#define USB_PM 0x04
292#define USB_DIAG 0x05
293
294/*
295 * USB SPEC.
296 */
297#define USB_OHCI 0x08
298#define USB_EHCI 0x09
299
300/****************** NATIVE ***************************/
301/* GPIO : I/O SPACE; REG : 32BITS */
302#define GPIOL_OUT_VAL 0x00
303#define GPIOL_OUT_EN 0x04
304
305#endif /* _CS5536_H */
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h
new file mode 100644
index 000000000000..4b493d6772c2
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h
@@ -0,0 +1,35 @@
1/*
2 * cs5536 mfgpt header file
3 */
4
5#ifndef _CS5536_MFGPT_H
6#define _CS5536_MFGPT_H
7
8#include <cs5536/cs5536.h>
9#include <cs5536/cs5536_pci.h>
10
11#ifdef CONFIG_CS5536_MFGPT
12extern void setup_mfgpt0_timer(void);
13extern void disable_mfgpt0_counter(void);
14extern void enable_mfgpt0_counter(void);
15#else
16static inline void __maybe_unused setup_mfgpt0_timer(void)
17{
18}
19static inline void __maybe_unused disable_mfgpt0_counter(void)
20{
21}
22static inline void __maybe_unused enable_mfgpt0_counter(void)
23{
24}
25#endif
26
27#define MFGPT_TICK_RATE 14318000
28#define COMPARE ((MFGPT_TICK_RATE + HZ/2) / HZ)
29
30#define MFGPT_BASE mfgpt_base
31#define MFGPT0_CMP2 (MFGPT_BASE + 2)
32#define MFGPT0_CNT (MFGPT_BASE + 4)
33#define MFGPT0_SETUP (MFGPT_BASE + 6)
34
35#endif /*!_CS5536_MFGPT_H */
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h
new file mode 100644
index 000000000000..0dca9c89ee7c
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h
@@ -0,0 +1,153 @@
1/*
2 * the definition file of cs5536 Virtual Support Module(VSM).
3 * pci configuration space can be accessed through the VSM, so
4 * there is no need of the MSR read/write now, except the spec.
5 * MSR registers which are not implemented yet.
6 *
7 * Copyright (C) 2007 Lemote Inc.
8 * Author : jlliu, liujl@lemote.com
9 */
10
11#ifndef _CS5536_PCI_H
12#define _CS5536_PCI_H
13
14#include <linux/types.h>
15#include <linux/pci_regs.h>
16
17extern void cs5536_pci_conf_write4(int function, int reg, u32 value);
18extern u32 cs5536_pci_conf_read4(int function, int reg);
19
20#define CS5536_ACC_INTR 9
21#define CS5536_IDE_INTR 14
22#define CS5536_USB_INTR 11
23#define CS5536_MFGPT_INTR 5
24#define CS5536_UART1_INTR 4
25#define CS5536_UART2_INTR 3
26
27/************** PCI BUS DEVICE FUNCTION ***************/
28
29/*
30 * PCI bus device function
31 */
32#define PCI_BUS_CS5536 0
33#define PCI_IDSEL_CS5536 14
34
35/********** STANDARD PCI-2.2 EXPANSION ****************/
36
37/*
38 * PCI configuration space
39 * we have to virtualize the PCI configure space head, so we should
40 * define the necessary IDs and some others.
41 */
42
43/* CONFIG of PCI VENDOR ID*/
44#define CFG_PCI_VENDOR_ID(mod_dev_id, sys_vendor_id) \
45 (((mod_dev_id) << 16) | (sys_vendor_id))
46
47/* VENDOR ID */
48#define CS5536_VENDOR_ID 0x1022
49
50/* DEVICE ID */
51#define CS5536_ISA_DEVICE_ID 0x2090
52#define CS5536_IDE_DEVICE_ID 0x209a
53#define CS5536_ACC_DEVICE_ID 0x2093
54#define CS5536_OHCI_DEVICE_ID 0x2094
55#define CS5536_EHCI_DEVICE_ID 0x2095
56
57/* CLASS CODE : CLASS SUB-CLASS INTERFACE */
58#define CS5536_ISA_CLASS_CODE 0x060100
59#define CS5536_IDE_CLASS_CODE 0x010180
60#define CS5536_ACC_CLASS_CODE 0x040100
61#define CS5536_OHCI_CLASS_CODE 0x0C0310
62#define CS5536_EHCI_CLASS_CODE 0x0C0320
63
64/* BHLC : BIST HEADER-TYPE LATENCY-TIMER CACHE-LINE-SIZE */
65
66#define CFG_PCI_CACHE_LINE_SIZE(header_type, latency_timer) \
67 ((PCI_NONE_BIST << 24) | ((header_type) << 16) \
68 | ((latency_timer) << 8) | PCI_NORMAL_CACHE_LINE_SIZE);
69
70#define PCI_NONE_BIST 0x00 /* RO not implemented yet. */
71#define PCI_BRIDGE_HEADER_TYPE 0x80 /* RO */
72#define PCI_NORMAL_HEADER_TYPE 0x00
73#define PCI_NORMAL_LATENCY_TIMER 0x00
74#define PCI_NORMAL_CACHE_LINE_SIZE 0x08 /* RW */
75
76/* BAR */
77#define PCI_BAR0_REG 0x10
78#define PCI_BAR1_REG 0x14
79#define PCI_BAR2_REG 0x18
80#define PCI_BAR3_REG 0x1c
81#define PCI_BAR4_REG 0x20
82#define PCI_BAR5_REG 0x24
83#define PCI_BAR_COUNT 6
84#define PCI_BAR_RANGE_MASK 0xFFFFFFFF
85
86/* CARDBUS CIS POINTER */
87#define PCI_CARDBUS_CIS_POINTER 0x00000000
88
89/* SUBSYSTEM VENDOR ID */
90#define CS5536_SUB_VENDOR_ID CS5536_VENDOR_ID
91
92/* SUBSYSTEM ID */
93#define CS5536_ISA_SUB_ID CS5536_ISA_DEVICE_ID
94#define CS5536_IDE_SUB_ID CS5536_IDE_DEVICE_ID
95#define CS5536_ACC_SUB_ID CS5536_ACC_DEVICE_ID
96#define CS5536_OHCI_SUB_ID CS5536_OHCI_DEVICE_ID
97#define CS5536_EHCI_SUB_ID CS5536_EHCI_DEVICE_ID
98
99/* EXPANSION ROM BAR */
100#define PCI_EXPANSION_ROM_BAR 0x00000000
101
102/* CAPABILITIES POINTER */
103#define PCI_CAPLIST_POINTER 0x00000000
104#define PCI_CAPLIST_USB_POINTER 0x40
105/* INTERRUPT */
106
107#define CFG_PCI_INTERRUPT_LINE(pin, mod_intr) \
108 ((PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | \
109 ((pin) << 8) | (mod_intr))
110
111#define PCI_MAX_LATENCY 0x40
112#define PCI_MIN_GRANT 0x00
113#define PCI_DEFAULT_PIN 0x01
114
115/*********** EXPANSION PCI REG ************************/
116
117/*
118 * ISA EXPANSION
119 */
120#define PCI_UART1_INT_REG 0x50
121#define PCI_UART2_INT_REG 0x54
122#define PCI_ISA_FIXUP_REG 0x58
123
124/*
125 * IDE EXPANSION
126 */
127#define PCI_IDE_CFG_REG 0x40
128#define CS5536_IDE_FLASH_SIGNATURE 0xDEADBEEF
129#define PCI_IDE_DTC_REG 0x48
130#define PCI_IDE_CAST_REG 0x4C
131#define PCI_IDE_ETC_REG 0x50
132#define PCI_IDE_PM_REG 0x54
133#define PCI_IDE_INT_REG 0x60
134
135/*
136 * ACC EXPANSION
137 */
138#define PCI_ACC_INT_REG 0x50
139
140/*
141 * OHCI EXPANSION : INTTERUPT IS IMPLEMENTED BY THE OHCI
142 */
143#define PCI_OHCI_PM_REG 0x40
144#define PCI_OHCI_INT_REG 0x50
145
146/*
147 * EHCI EXPANSION
148 */
149#define PCI_EHCI_LEGSMIEN_REG 0x50
150#define PCI_EHCI_LEGSMISTS_REG 0x54
151#define PCI_EHCI_FLADJ_REG 0x60
152
153#endif /* _CS5536_PCI_H_ */
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h
new file mode 100644
index 000000000000..6305bea7e18e
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h
@@ -0,0 +1,31 @@
1/*
2 * the read/write interfaces for Virtual Support Module(VSM)
3 *
4 * Copyright (C) 2009 Lemote, Inc.
5 * Author: Wu Zhangjin <wuzj@lemote.com>
6 */
7
8#ifndef _CS5536_VSM_H
9#define _CS5536_VSM_H
10
11#include <linux/types.h>
12
13typedef void (*cs5536_pci_vsm_write)(int reg, u32 value);
14typedef u32 (*cs5536_pci_vsm_read)(int reg);
15
16#define DECLARE_CS5536_MODULE(name) \
17extern void pci_##name##_write_reg(int reg, u32 value); \
18extern u32 pci_##name##_read_reg(int reg);
19
20/* ide module */
21DECLARE_CS5536_MODULE(ide)
22/* acc module */
23DECLARE_CS5536_MODULE(acc)
24/* ohci module */
25DECLARE_CS5536_MODULE(ohci)
26/* isa module */
27DECLARE_CS5536_MODULE(isa)
28/* ehci module */
29DECLARE_CS5536_MODULE(ehci)
30
31#endif /* _CS5536_VSM_H */
diff --git a/arch/mips/include/asm/mach-loongson/dma-coherence.h b/arch/mips/include/asm/mach-loongson/dma-coherence.h
index 71a6851ba833..981c75f91a7d 100644
--- a/arch/mips/include/asm/mach-loongson/dma-coherence.h
+++ b/arch/mips/include/asm/mach-loongson/dma-coherence.h
@@ -28,7 +28,11 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
28static inline unsigned long plat_dma_addr_to_phys(struct device *dev, 28static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
29 dma_addr_t dma_addr) 29 dma_addr_t dma_addr)
30{ 30{
31#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT)
32 return (dma_addr > 0x8fffffff) ? dma_addr : (dma_addr & 0x0fffffff);
33#else
31 return dma_addr & 0x7fffffff; 34 return dma_addr & 0x7fffffff;
35#endif
32} 36}
33 37
34static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, 38static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h
index da70bcf2304e..ee8bc8376972 100644
--- a/arch/mips/include/asm/mach-loongson/loongson.h
+++ b/arch/mips/include/asm/mach-loongson/loongson.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology 2 * Copyright (C) 2009 Lemote, Inc.
3 * Author: Wu Zhangjin <wuzj@lemote.com> 3 * Author: Wu Zhangjin <wuzj@lemote.com>
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
@@ -15,9 +15,6 @@
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/init.h> 16#include <linux/init.h>
17 17
18/* there is an internal bonito64-compatiable northbridge in loongson2e/2f */
19#include <asm/mips-boards/bonito64.h>
20
21/* loongson internal northbridge initialization */ 18/* loongson internal northbridge initialization */
22extern void bonito_irq_init(void); 19extern void bonito_irq_init(void);
23 20
@@ -32,7 +29,19 @@ extern unsigned long memsize, highmemsize;
32/* loongson-specific command line, env and memory initialization */ 29/* loongson-specific command line, env and memory initialization */
33extern void __init prom_init_memory(void); 30extern void __init prom_init_memory(void);
34extern void __init prom_init_cmdline(void); 31extern void __init prom_init_cmdline(void);
32extern void __init prom_init_machtype(void);
35extern void __init prom_init_env(void); 33extern void __init prom_init_env(void);
34#ifdef CONFIG_LOONGSON_UART_BASE
35extern unsigned long _loongson_uart_base, loongson_uart_base;
36extern void prom_init_loongson_uart_base(void);
37#endif
38
39static inline void prom_init_uart_base(void)
40{
41#ifdef CONFIG_LOONGSON_UART_BASE
42 prom_init_loongson_uart_base();
43#endif
44}
36 45
37/* irq operation functions */ 46/* irq operation functions */
38extern void bonito_irqdispatch(void); 47extern void bonito_irqdispatch(void);
@@ -40,25 +49,276 @@ extern void __init bonito_irq_init(void);
40extern void __init set_irq_trigger_mode(void); 49extern void __init set_irq_trigger_mode(void);
41extern void __init mach_init_irq(void); 50extern void __init mach_init_irq(void);
42extern void mach_irq_dispatch(unsigned int pending); 51extern void mach_irq_dispatch(unsigned int pending);
52extern int mach_i8259_irq(void);
53
54/* We need this in some places... */
55#define delay() ({ \
56 int x; \
57 for (x = 0; x < 100000; x++) \
58 __asm__ __volatile__(""); \
59})
60
61#define LOONGSON_REG(x) \
62 (*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))
63
64#define LOONGSON_IRQ_BASE 32
65#define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
66
67#define LOONGSON_FLASH_BASE 0x1c000000
68#define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
69#define LOONGSON_FLASH_TOP (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1)
70
71#define LOONGSON_LIO0_BASE 0x1e000000
72#define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
73#define LOONGSON_LIO0_TOP (LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1)
74
75#define LOONGSON_BOOT_BASE 0x1fc00000
76#define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
77#define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
78#define LOONGSON_REG_BASE 0x1fe00000
79#define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
80#define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
81
82#define LOONGSON_LIO1_BASE 0x1ff00000
83#define LOONGSON_LIO1_SIZE 0x00100000 /* 1M */
84#define LOONGSON_LIO1_TOP (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1)
85
86#define LOONGSON_PCILO0_BASE 0x10000000
87#define LOONGSON_PCILO1_BASE 0x14000000
88#define LOONGSON_PCILO2_BASE 0x18000000
89#define LOONGSON_PCILO_BASE LOONGSON_PCILO0_BASE
90#define LOONGSON_PCILO_SIZE 0x0c000000 /* 64M * 3 */
91#define LOONGSON_PCILO_TOP (LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1)
92
93#define LOONGSON_PCICFG_BASE 0x1fe80000
94#define LOONGSON_PCICFG_SIZE 0x00000800 /* 2K */
95#define LOONGSON_PCICFG_TOP (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
96#define LOONGSON_PCIIO_BASE 0x1fd00000
97#define LOONGSON_PCIIO_SIZE 0x00100000 /* 1M */
98#define LOONGSON_PCIIO_TOP (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1)
99
100/* Loongson Register Bases */
101
102#define LOONGSON_PCICONFIGBASE 0x00
103#define LOONGSON_REGBASE 0x100
43 104
44/* PCI Configuration Registers */ 105/* PCI Configuration Registers */
45#define LOONGSON_PCI_ISR4C BONITO_PCI_REG(0x4c) 106
107#define LOONGSON_PCI_REG(x) LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x))
108#define LOONGSON_PCIDID LOONGSON_PCI_REG(0x00)
109#define LOONGSON_PCICMD LOONGSON_PCI_REG(0x04)
110#define LOONGSON_PCICLASS LOONGSON_PCI_REG(0x08)
111#define LOONGSON_PCILTIMER LOONGSON_PCI_REG(0x0c)
112#define LOONGSON_PCIBASE0 LOONGSON_PCI_REG(0x10)
113#define LOONGSON_PCIBASE1 LOONGSON_PCI_REG(0x14)
114#define LOONGSON_PCIBASE2 LOONGSON_PCI_REG(0x18)
115#define LOONGSON_PCIBASE3 LOONGSON_PCI_REG(0x1c)
116#define LOONGSON_PCIBASE4 LOONGSON_PCI_REG(0x20)
117#define LOONGSON_PCIEXPRBASE LOONGSON_PCI_REG(0x30)
118#define LOONGSON_PCIINT LOONGSON_PCI_REG(0x3c)
119
120#define LOONGSON_PCI_ISR4C LOONGSON_PCI_REG(0x4c)
121
122#define LOONGSON_PCICMD_PERR_CLR 0x80000000
123#define LOONGSON_PCICMD_SERR_CLR 0x40000000
124#define LOONGSON_PCICMD_MABORT_CLR 0x20000000
125#define LOONGSON_PCICMD_MTABORT_CLR 0x10000000
126#define LOONGSON_PCICMD_TABORT_CLR 0x08000000
127#define LOONGSON_PCICMD_MPERR_CLR 0x01000000
128#define LOONGSON_PCICMD_PERRRESPEN 0x00000040
129#define LOONGSON_PCICMD_ASTEPEN 0x00000080
130#define LOONGSON_PCICMD_SERREN 0x00000100
131#define LOONGSON_PCILTIMER_BUSLATENCY 0x0000ff00
132#define LOONGSON_PCILTIMER_BUSLATENCY_SHIFT 8
133
134/* Loongson h/w Configuration */
135
136#define LOONGSON_GENCFG_OFFSET 0x4
137#define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET)
138
139#define LOONGSON_GENCFG_DEBUGMODE 0x00000001
140#define LOONGSON_GENCFG_SNOOPEN 0x00000002
141#define LOONGSON_GENCFG_CPUSELFRESET 0x00000004
142
143#define LOONGSON_GENCFG_FORCE_IRQA 0x00000008
144#define LOONGSON_GENCFG_IRQA_ISOUT 0x00000010
145#define LOONGSON_GENCFG_IRQA_FROM_INT1 0x00000020
146#define LOONGSON_GENCFG_BYTESWAP 0x00000040
147
148#define LOONGSON_GENCFG_UNCACHED 0x00000080
149#define LOONGSON_GENCFG_PREFETCHEN 0x00000100
150#define LOONGSON_GENCFG_WBEHINDEN 0x00000200
151#define LOONGSON_GENCFG_CACHEALG 0x00000c00
152#define LOONGSON_GENCFG_CACHEALG_SHIFT 10
153#define LOONGSON_GENCFG_PCIQUEUE 0x00001000
154#define LOONGSON_GENCFG_CACHESTOP 0x00002000
155#define LOONGSON_GENCFG_MSTRBYTESWAP 0x00004000
156#define LOONGSON_GENCFG_BUSERREN 0x00008000
157#define LOONGSON_GENCFG_NORETRYTIMEOUT 0x00010000
158#define LOONGSON_GENCFG_SHORTCOPYTIMEOUT 0x00020000
159
160/* PCI address map control */
161
162#define LOONGSON_PCIMAP LOONGSON_REG(LOONGSON_REGBASE + 0x10)
163#define LOONGSON_PCIMEMBASECFG LOONGSON_REG(LOONGSON_REGBASE + 0x14)
164#define LOONGSON_PCIMAP_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x18)
165
166/* GPIO Regs - r/w */
167
168#define LOONGSON_GPIODATA LOONGSON_REG(LOONGSON_REGBASE + 0x1c)
169#define LOONGSON_GPIOIE LOONGSON_REG(LOONGSON_REGBASE + 0x20)
170
171/* ICU Configuration Regs - r/w */
172
173#define LOONGSON_INTEDGE LOONGSON_REG(LOONGSON_REGBASE + 0x24)
174#define LOONGSON_INTSTEER LOONGSON_REG(LOONGSON_REGBASE + 0x28)
175#define LOONGSON_INTPOL LOONGSON_REG(LOONGSON_REGBASE + 0x2c)
176
177/* ICU Enable Regs - IntEn & IntISR are r/o. */
178
179#define LOONGSON_INTENSET LOONGSON_REG(LOONGSON_REGBASE + 0x30)
180#define LOONGSON_INTENCLR LOONGSON_REG(LOONGSON_REGBASE + 0x34)
181#define LOONGSON_INTEN LOONGSON_REG(LOONGSON_REGBASE + 0x38)
182#define LOONGSON_INTISR LOONGSON_REG(LOONGSON_REGBASE + 0x3c)
183
184/* ICU */
185#define LOONGSON_ICU_MBOXES 0x0000000f
186#define LOONGSON_ICU_MBOXES_SHIFT 0
187#define LOONGSON_ICU_DMARDY 0x00000010
188#define LOONGSON_ICU_DMAEMPTY 0x00000020
189#define LOONGSON_ICU_COPYRDY 0x00000040
190#define LOONGSON_ICU_COPYEMPTY 0x00000080
191#define LOONGSON_ICU_COPYERR 0x00000100
192#define LOONGSON_ICU_PCIIRQ 0x00000200
193#define LOONGSON_ICU_MASTERERR 0x00000400
194#define LOONGSON_ICU_SYSTEMERR 0x00000800
195#define LOONGSON_ICU_DRAMPERR 0x00001000
196#define LOONGSON_ICU_RETRYERR 0x00002000
197#define LOONGSON_ICU_GPIOS 0x01ff0000
198#define LOONGSON_ICU_GPIOS_SHIFT 16
199#define LOONGSON_ICU_GPINS 0x7e000000
200#define LOONGSON_ICU_GPINS_SHIFT 25
201#define LOONGSON_ICU_MBOX(N) (1<<(LOONGSON_ICU_MBOXES_SHIFT+(N)))
202#define LOONGSON_ICU_GPIO(N) (1<<(LOONGSON_ICU_GPIOS_SHIFT+(N)))
203#define LOONGSON_ICU_GPIN(N) (1<<(LOONGSON_ICU_GPINS_SHIFT+(N)))
204
205/* PCI prefetch window base & mask */
206
207#define LOONGSON_MEM_WIN_BASE_L LOONGSON_REG(LOONGSON_REGBASE + 0x40)
208#define LOONGSON_MEM_WIN_BASE_H LOONGSON_REG(LOONGSON_REGBASE + 0x44)
209#define LOONGSON_MEM_WIN_MASK_L LOONGSON_REG(LOONGSON_REGBASE + 0x48)
210#define LOONGSON_MEM_WIN_MASK_H LOONGSON_REG(LOONGSON_REGBASE + 0x4c)
46 211
47/* PCI_Hit*_Sel_* */ 212/* PCI_Hit*_Sel_* */
48 213
49#define LOONGSON_PCI_HIT0_SEL_L BONITO(BONITO_REGBASE + 0x50) 214#define LOONGSON_PCI_HIT0_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x50)
50#define LOONGSON_PCI_HIT0_SEL_H BONITO(BONITO_REGBASE + 0x54) 215#define LOONGSON_PCI_HIT0_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x54)
51#define LOONGSON_PCI_HIT1_SEL_L BONITO(BONITO_REGBASE + 0x58) 216#define LOONGSON_PCI_HIT1_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x58)
52#define LOONGSON_PCI_HIT1_SEL_H BONITO(BONITO_REGBASE + 0x5c) 217#define LOONGSON_PCI_HIT1_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x5c)
53#define LOONGSON_PCI_HIT2_SEL_L BONITO(BONITO_REGBASE + 0x60) 218#define LOONGSON_PCI_HIT2_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x60)
54#define LOONGSON_PCI_HIT2_SEL_H BONITO(BONITO_REGBASE + 0x64) 219#define LOONGSON_PCI_HIT2_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x64)
55 220
56/* PXArb Config & Status */ 221/* PXArb Config & Status */
57 222
58#define LOONGSON_PXARB_CFG BONITO(BONITO_REGBASE + 0x68) 223#define LOONGSON_PXARB_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x68)
59#define LOONGSON_PXARB_STATUS BONITO(BONITO_REGBASE + 0x6c) 224#define LOONGSON_PXARB_STATUS LOONGSON_REG(LOONGSON_REGBASE + 0x6c)
225
226/* pcimap */
227
228#define LOONGSON_PCIMAP_PCIMAP_LO0 0x0000003f
229#define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT 0
230#define LOONGSON_PCIMAP_PCIMAP_LO1 0x00000fc0
231#define LOONGSON_PCIMAP_PCIMAP_LO1_SHIFT 6
232#define LOONGSON_PCIMAP_PCIMAP_LO2 0x0003f000
233#define LOONGSON_PCIMAP_PCIMAP_LO2_SHIFT 12
234#define LOONGSON_PCIMAP_PCIMAP_2 0x00040000
235#define LOONGSON_PCIMAP_WIN(WIN, ADDR) \
236 ((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
237
238#ifdef CONFIG_CPU_SUPPORTS_CPUFREQ
239#include <linux/cpufreq.h>
240extern void loongson2_cpu_wait(void);
241extern struct cpufreq_frequency_table loongson2_clockmod_table[];
242
243/* Chip Config */
244#define LOONGSON_CHIPCFG0 LOONGSON_REG(LOONGSON_REGBASE + 0x80)
245#endif
246
247/*
248 * address windows configuration module
249 *
250 * loongson2e do not have this module
251 */
252#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
253
254/* address window config module base address */
255#define LOONGSON_ADDRWINCFG_BASE 0x3ff00000ul
256#define LOONGSON_ADDRWINCFG_SIZE 0x180
257
258extern unsigned long _loongson_addrwincfg_base;
259#define LOONGSON_ADDRWINCFG(offset) \
260 (*(volatile u64 *)(_loongson_addrwincfg_base + (offset)))
261
262#define CPU_WIN0_BASE LOONGSON_ADDRWINCFG(0x00)
263#define CPU_WIN1_BASE LOONGSON_ADDRWINCFG(0x08)
264#define CPU_WIN2_BASE LOONGSON_ADDRWINCFG(0x10)
265#define CPU_WIN3_BASE LOONGSON_ADDRWINCFG(0x18)
266
267#define CPU_WIN0_MASK LOONGSON_ADDRWINCFG(0x20)
268#define CPU_WIN1_MASK LOONGSON_ADDRWINCFG(0x28)
269#define CPU_WIN2_MASK LOONGSON_ADDRWINCFG(0x30)
270#define CPU_WIN3_MASK LOONGSON_ADDRWINCFG(0x38)
271
272#define CPU_WIN0_MMAP LOONGSON_ADDRWINCFG(0x40)
273#define CPU_WIN1_MMAP LOONGSON_ADDRWINCFG(0x48)
274#define CPU_WIN2_MMAP LOONGSON_ADDRWINCFG(0x50)
275#define CPU_WIN3_MMAP LOONGSON_ADDRWINCFG(0x58)
276
277#define PCIDMA_WIN0_BASE LOONGSON_ADDRWINCFG(0x60)
278#define PCIDMA_WIN1_BASE LOONGSON_ADDRWINCFG(0x68)
279#define PCIDMA_WIN2_BASE LOONGSON_ADDRWINCFG(0x70)
280#define PCIDMA_WIN3_BASE LOONGSON_ADDRWINCFG(0x78)
281
282#define PCIDMA_WIN0_MASK LOONGSON_ADDRWINCFG(0x80)
283#define PCIDMA_WIN1_MASK LOONGSON_ADDRWINCFG(0x88)
284#define PCIDMA_WIN2_MASK LOONGSON_ADDRWINCFG(0x90)
285#define PCIDMA_WIN3_MASK LOONGSON_ADDRWINCFG(0x98)
286
287#define PCIDMA_WIN0_MMAP LOONGSON_ADDRWINCFG(0xa0)
288#define PCIDMA_WIN1_MMAP LOONGSON_ADDRWINCFG(0xa8)
289#define PCIDMA_WIN2_MMAP LOONGSON_ADDRWINCFG(0xb0)
290#define PCIDMA_WIN3_MMAP LOONGSON_ADDRWINCFG(0xb8)
291
292#define ADDRWIN_WIN0 0
293#define ADDRWIN_WIN1 1
294#define ADDRWIN_WIN2 2
295#define ADDRWIN_WIN3 3
296
297#define ADDRWIN_MAP_DST_DDR 0
298#define ADDRWIN_MAP_DST_PCI 1
299#define ADDRWIN_MAP_DST_LIO 1
300
301/*
302 * s: CPU, PCIDMA
303 * d: DDR, PCI, LIO
304 * win: 0, 1, 2, 3
305 * src: map source
306 * dst: map destination
307 * size: ~mask + 1
308 */
309#define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\
310 s##_WIN##w##_BASE = (src); \
311 s##_WIN##w##_MMAP = (src) | ADDRWIN_MAP_DST_##d; \
312 s##_WIN##w##_MASK = ~(size-1); \
313} while (0)
314
315#define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \
316 LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size)
317#define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \
318 LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size)
319#define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \
320 LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size)
60 321
61/* loongson2-specific perf counter IRQ */ 322#endif /* ! CONFIG_CPU_SUPPORTS_ADDRWINCFG */
62#define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6)
63 323
64#endif /* __ASM_MACH_LOONGSON_LOONGSON_H */ 324#endif /* __ASM_MACH_LOONGSON_LOONGSON_H */
diff --git a/arch/mips/include/asm/mach-loongson/machine.h b/arch/mips/include/asm/mach-loongson/machine.h
index 206ea2067916..acf8359cb135 100644
--- a/arch/mips/include/asm/mach-loongson/machine.h
+++ b/arch/mips/include/asm/mach-loongson/machine.h
@@ -13,10 +13,15 @@
13 13
14#ifdef CONFIG_LEMOTE_FULOONG2E 14#ifdef CONFIG_LEMOTE_FULOONG2E
15 15
16#define LOONGSON_UART_BASE (BONITO_PCIIO_BASE + 0x3f8)
17
18#define LOONGSON_MACHTYPE MACH_LEMOTE_FL2E 16#define LOONGSON_MACHTYPE MACH_LEMOTE_FL2E
19 17
20#endif 18#endif
21 19
20/* use fuloong2f as the default machine of LEMOTE_MACH2F */
21#ifdef CONFIG_LEMOTE_MACH2F
22
23#define LOONGSON_MACHTYPE MACH_LEMOTE_FL2F
24
25#endif
26
22#endif /* __ASM_MACH_LOONGSON_MACHINE_H */ 27#endif /* __ASM_MACH_LOONGSON_MACHINE_H */
diff --git a/arch/mips/include/asm/mach-loongson/mem.h b/arch/mips/include/asm/mach-loongson/mem.h
index bd7b3cba7e35..e9960f341b96 100644
--- a/arch/mips/include/asm/mach-loongson/mem.h
+++ b/arch/mips/include/asm/mach-loongson/mem.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology 2 * Copyright (C) 2009 Lemote, Inc.
3 * Author: Wu Zhangjin <wuzj@lemote.com> 3 * Author: Wu Zhangjin <wuzj@lemote.com>
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
@@ -12,19 +12,30 @@
12#define __ASM_MACH_LOONGSON_MEM_H 12#define __ASM_MACH_LOONGSON_MEM_H
13 13
14/* 14/*
15 * On Lemote Loongson 2e 15 * high memory space
16 * 16 *
17 * the high memory space starts from 512M. 17 * in loongson2e, starts from 512M
18 * the peripheral registers reside between 0x1000:0000 and 0x2000:0000. 18 * in loongson2f, starts from 2G 256M
19 */ 19 */
20#ifdef CONFIG_CPU_LOONGSON2E
21#define LOONGSON_HIGHMEM_START 0x20000000
22#else
23#define LOONGSON_HIGHMEM_START 0x90000000
24#endif
20 25
21#ifdef CONFIG_LEMOTE_FULOONG2E 26/*
22 27 * the peripheral registers(MMIO):
23#define LOONGSON_HIGHMEM_START 0x20000000 28 *
29 * On the Lemote Loongson 2e system, reside between 0x1000:0000 and 0x2000:0000.
30 * On the Lemote Loongson 2f system, reside between 0x1000:0000 and 0x8000:0000.
31 */
24 32
25#define LOONGSON_MMIO_MEM_START 0x10000000 33#define LOONGSON_MMIO_MEM_START 0x10000000
26#define LOONGSON_MMIO_MEM_END 0x20000000
27 34
35#ifdef CONFIG_CPU_LOONGSON2E
36#define LOONGSON_MMIO_MEM_END 0x20000000
37#else
38#define LOONGSON_MMIO_MEM_END 0x80000000
28#endif 39#endif
29 40
30#endif /* __ASM_MACH_LOONGSON_MEM_H */ 41#endif /* __ASM_MACH_LOONGSON_MEM_H */
diff --git a/arch/mips/include/asm/mach-loongson/pci.h b/arch/mips/include/asm/mach-loongson/pci.h
index f1663ca81da0..a199a4f6de4e 100644
--- a/arch/mips/include/asm/mach-loongson/pci.h
+++ b/arch/mips/include/asm/mach-loongson/pci.h
@@ -1,5 +1,6 @@
1/* 1/*
2 * Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org> 2 * Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org>
3 * Copyright (c) 2009 Wu Zhangjin <wuzj@lemote.com>
3 * 4 *
4 * This program is free software; you can redistribute it 5 * This program is free software; you can redistribute it
5 * and/or modify it under the terms of the GNU General 6 * and/or modify it under the terms of the GNU General
@@ -22,16 +23,39 @@
22#ifndef __ASM_MACH_LOONGSON_PCI_H_ 23#ifndef __ASM_MACH_LOONGSON_PCI_H_
23#define __ASM_MACH_LOONGSON_PCI_H_ 24#define __ASM_MACH_LOONGSON_PCI_H_
24 25
25extern struct pci_ops bonito64_pci_ops; 26extern struct pci_ops loongson_pci_ops;
26 27
27#ifdef CONFIG_LEMOTE_FULOONG2E 28/* this is an offset from mips_io_port_base */
29#define LOONGSON_PCI_IO_START 0x00004000UL
30
31#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
32
33/*
34 * we use address window2 to map cpu address space to pci space
35 * window2: cpu [1G, 2G] -> pci [1G, 2G]
36 * why not use window 0 & 1? because they are used by cpu when booting.
37 * window0: cpu [0, 256M] -> ddr [0, 256M]
38 * window1: cpu [256M, 512M] -> pci [256M, 512M]
39 */
40
41/* the smallest LOONGSON_CPU_MEM_SRC can be 512M */
42#define LOONGSON_CPU_MEM_SRC 0x40000000ul /* 1G */
43#define LOONGSON_PCI_MEM_DST LOONGSON_CPU_MEM_SRC
44
45#define LOONGSON_PCI_MEM_START LOONGSON_PCI_MEM_DST
46#define LOONGSON_PCI_MEM_END (0x80000000ul-1) /* 2G */
47
48#define MMAP_CPUTOPCI_SIZE (LOONGSON_PCI_MEM_END - \
49 LOONGSON_PCI_MEM_START + 1)
50
51#else /* loongson2f/32bit & loongson2e */
28 52
29/* this pci memory space is mapped by pcimap in pci.c */ 53/* this pci memory space is mapped by pcimap in pci.c */
30#define LOONGSON_PCI_MEM_START BONITO_PCILO1_BASE 54#define LOONGSON_PCI_MEM_START LOONGSON_PCILO1_BASE
31#define LOONGSON_PCI_MEM_END (BONITO_PCILO1_BASE + 0x04000000 * 2) 55#define LOONGSON_PCI_MEM_END (LOONGSON_PCILO1_BASE + 0x04000000 * 2)
32/* this is an offset from mips_io_port_base */ 56/* this is an offset from mips_io_port_base */
33#define LOONGSON_PCI_IO_START 0x00004000UL 57#define LOONGSON_PCI_IO_START 0x00004000UL
34 58
35#endif 59#endif /* !CONFIG_CPU_SUPPORTS_ADDRWINCFG */
36 60
37#endif /* !__ASM_MACH_LOONGSON_PCI_H_ */ 61#endif /* !__ASM_MACH_LOONGSON_PCI_H_ */
diff --git a/arch/mips/include/asm/mach-powertv/asic.h b/arch/mips/include/asm/mach-powertv/asic.h
new file mode 100644
index 000000000000..bcad43a93ebf
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/asic.h
@@ -0,0 +1,107 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef _ASM_MACH_POWERTV_ASIC_H
20#define _ASM_MACH_POWERTV_ASIC_H
21
22#include <linux/ioport.h>
23#include <asm/mach-powertv/asic_regs.h>
24
25#define DVR_CAPABLE (1<<0)
26#define PCIE_CAPABLE (1<<1)
27#define FFS_CAPABLE (1<<2)
28#define DISPLAY_CAPABLE (1<<3)
29
30/* Platform Family types
31 * For compitability, the new value must be added in the end */
32enum family_type {
33 FAMILY_8500,
34 FAMILY_8500RNG,
35 FAMILY_4500,
36 FAMILY_1500,
37 FAMILY_8600,
38 FAMILY_4600,
39 FAMILY_4600VZA,
40 FAMILY_8600VZB,
41 FAMILY_1500VZE,
42 FAMILY_1500VZF,
43 FAMILIES
44};
45
46/* Register maps for each ASIC */
47extern const struct register_map calliope_register_map;
48extern const struct register_map cronus_register_map;
49extern const struct register_map zeus_register_map;
50
51extern struct resource dvr_cronus_resources[];
52extern struct resource dvr_zeus_resources[];
53extern struct resource non_dvr_calliope_resources[];
54extern struct resource non_dvr_cronus_resources[];
55extern struct resource non_dvr_cronuslite_resources[];
56extern struct resource non_dvr_vz_calliope_resources[];
57extern struct resource non_dvr_vze_calliope_resources[];
58extern struct resource non_dvr_vzf_calliope_resources[];
59extern struct resource non_dvr_zeus_resources[];
60
61extern void powertv_platform_init(void);
62extern void platform_alloc_bootmem(void);
63extern enum asic_type platform_get_asic(void);
64extern enum family_type platform_get_family(void);
65extern int platform_supports_dvr(void);
66extern int platform_supports_ffs(void);
67extern int platform_supports_pcie(void);
68extern int platform_supports_display(void);
69extern void configure_platform(void);
70extern void platform_configure_usb_ehci(void);
71extern void platform_unconfigure_usb_ehci(void);
72extern void platform_configure_usb_ohci(void);
73extern void platform_unconfigure_usb_ohci(void);
74
75/* Platform Resources */
76#define ASIC_RESOURCE_GET_EXISTS 1
77extern struct resource *asic_resource_get(const char *name);
78extern void platform_release_memory(void *baddr, int size);
79
80/* Reboot Cause */
81extern void set_reboot_cause(char code, unsigned int data, unsigned int data2);
82extern void set_locked_reboot_cause(char code, unsigned int data,
83 unsigned int data2);
84
85enum sys_reboot_type {
86 sys_unknown_reboot = 0x00, /* Unknown reboot cause */
87 sys_davic_change = 0x01, /* Reboot due to change in DAVIC
88 * mode */
89 sys_user_reboot = 0x02, /* Reboot initiated by user */
90 sys_system_reboot = 0x03, /* Reboot initiated by OS */
91 sys_trap_reboot = 0x04, /* Reboot due to a CPU trap */
92 sys_silent_reboot = 0x05, /* Silent reboot */
93 sys_boot_ldr_reboot = 0x06, /* Bootloader reboot */
94 sys_power_up_reboot = 0x07, /* Power on bootup. Older
95 * drivers may report as
96 * userReboot. */
97 sys_code_change = 0x08, /* Reboot to take code change.
98 * Older drivers may report as
99 * userReboot. */
100 sys_hardware_reset = 0x09, /* HW watchdog or front-panel
101 * reset button reset. Older
102 * drivers may report as
103 * userReboot. */
104 sys_watchdogInterrupt = 0x0A /* Pre-watchdog interrupt */
105};
106
107#endif /* _ASM_MACH_POWERTV_ASIC_H */
diff --git a/arch/mips/include/asm/mach-powertv/asic_regs.h b/arch/mips/include/asm/mach-powertv/asic_regs.h
new file mode 100644
index 000000000000..9a65c93782f9
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/asic_regs.h
@@ -0,0 +1,155 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef __ASM_MACH_POWERTV_ASIC_H_
20#define __ASM_MACH_POWERTV_ASIC_H_
21#include <linux/io.h>
22
23/* ASIC types */
24enum asic_type {
25 ASIC_UNKNOWN,
26 ASIC_ZEUS,
27 ASIC_CALLIOPE,
28 ASIC_CRONUS,
29 ASIC_CRONUSLITE,
30 ASICS
31};
32
33/* hardcoded values read from Chip Version registers */
34#define CRONUS_10 0x0B4C1C20
35#define CRONUS_11 0x0B4C1C21
36#define CRONUSLITE_10 0x0B4C1C40
37
38#define NAND_FLASH_BASE 0x03000000
39#define ZEUS_IO_BASE 0x09000000
40#define CALLIOPE_IO_BASE 0x08000000
41#define CRONUS_IO_BASE 0x09000000
42#define ASIC_IO_SIZE 0x01000000
43
44/* Definitions for backward compatibility */
45#define UART1_INTSTAT uart1_intstat
46#define UART1_INTEN uart1_inten
47#define UART1_CONFIG1 uart1_config1
48#define UART1_CONFIG2 uart1_config2
49#define UART1_DIVISORHI uart1_divisorhi
50#define UART1_DIVISORLO uart1_divisorlo
51#define UART1_DATA uart1_data
52#define UART1_STATUS uart1_status
53
54/* ASIC register enumeration */
55struct register_map {
56 u32 eic_slow0_strt_add;
57 u32 eic_cfg_bits;
58 u32 eic_ready_status;
59
60 u32 chipver3;
61 u32 chipver2;
62 u32 chipver1;
63 u32 chipver0;
64
65 u32 uart1_intstat;
66 u32 uart1_inten;
67 u32 uart1_config1;
68 u32 uart1_config2;
69 u32 uart1_divisorhi;
70 u32 uart1_divisorlo;
71 u32 uart1_data;
72 u32 uart1_status;
73
74 u32 int_stat_3;
75 u32 int_stat_2;
76 u32 int_stat_1;
77 u32 int_stat_0;
78 u32 int_config;
79 u32 int_int_scan;
80 u32 ien_int_3;
81 u32 ien_int_2;
82 u32 ien_int_1;
83 u32 ien_int_0;
84 u32 int_level_3_3;
85 u32 int_level_3_2;
86 u32 int_level_3_1;
87 u32 int_level_3_0;
88 u32 int_level_2_3;
89 u32 int_level_2_2;
90 u32 int_level_2_1;
91 u32 int_level_2_0;
92 u32 int_level_1_3;
93 u32 int_level_1_2;
94 u32 int_level_1_1;
95 u32 int_level_1_0;
96 u32 int_level_0_3;
97 u32 int_level_0_2;
98 u32 int_level_0_1;
99 u32 int_level_0_0;
100 u32 int_docsis_en;
101
102 u32 mips_pll_setup;
103 u32 usb_fs;
104 u32 test_bus;
105 u32 crt_spare;
106 u32 usb2_ohci_int_mask;
107 u32 usb2_strap;
108 u32 ehci_hcapbase;
109 u32 ohci_hc_revision;
110 u32 bcm1_bs_lmi_steer;
111 u32 usb2_control;
112 u32 usb2_stbus_obc;
113 u32 usb2_stbus_mess_size;
114 u32 usb2_stbus_chunk_size;
115
116 u32 pcie_regs;
117 u32 tim_ch;
118 u32 tim_cl;
119 u32 gpio_dout;
120 u32 gpio_din;
121 u32 gpio_dir;
122 u32 watchdog;
123 u32 front_panel;
124
125 u32 register_maps;
126};
127
128extern enum asic_type asic;
129extern const struct register_map *register_map;
130extern unsigned long asic_phy_base; /* Physical address of ASIC */
131extern unsigned long asic_base; /* Virtual address of ASIC */
132
133/*
134 * Macros to interface to registers through their ioremapped address
135 * asic_reg_offset Returns the offset of a given register from the start
136 * of the ASIC address space
137 * asic_reg_phys_addr Returns the physical address of the given register
138 * asic_reg_addr Returns the iomapped virtual address of the given
139 * register.
140 */
141#define asic_reg_offset(x) (register_map->x)
142#define asic_reg_phys_addr(x) (asic_phy_base + asic_reg_offset(x))
143#define asic_reg_addr(x) \
144 ((unsigned int *) (asic_base + asic_reg_offset(x)))
145
146/*
147 * The asic_reg macro is gone. It should be replaced by either asic_read or
148 * asic_write, as appropriate.
149 */
150
151#define asic_read(x) readl(asic_reg_addr(x))
152#define asic_write(v, x) writel(v, asic_reg_addr(x))
153
154extern void asic_irq_init(void);
155#endif
diff --git a/arch/mips/include/asm/mach-powertv/dma-coherence.h b/arch/mips/include/asm/mach-powertv/dma-coherence.h
new file mode 100644
index 000000000000..5b8d5ebeb838
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/dma-coherence.h
@@ -0,0 +1,119 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Version from mach-generic modified to support PowerTV port
7 * Portions Copyright (C) 2009 Cisco Systems, Inc.
8 * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
9 *
10 */
11
12#ifndef __ASM_MACH_POWERTV_DMA_COHERENCE_H
13#define __ASM_MACH_POWERTV_DMA_COHERENCE_H
14
15#include <linux/sched.h>
16#include <linux/version.h>
17#include <linux/device.h>
18#include <asm/mach-powertv/asic.h>
19
20static inline bool is_kseg2(void *addr)
21{
22 return (unsigned long)addr >= KSEG2;
23}
24
25static inline unsigned long virt_to_phys_from_pte(void *addr)
26{
27 pgd_t *pgd;
28 pud_t *pud;
29 pmd_t *pmd;
30 pte_t *ptep, pte;
31
32 unsigned long virt_addr = (unsigned long)addr;
33 unsigned long phys_addr = 0UL;
34
35 /* get the page global directory. */
36 pgd = pgd_offset_k(virt_addr);
37
38 if (!pgd_none(*pgd)) {
39 /* get the page upper directory */
40 pud = pud_offset(pgd, virt_addr);
41 if (!pud_none(*pud)) {
42 /* get the page middle directory */
43 pmd = pmd_offset(pud, virt_addr);
44 if (!pmd_none(*pmd)) {
45 /* get a pointer to the page table entry */
46 ptep = pte_offset(pmd, virt_addr);
47 pte = *ptep;
48 /* check for a valid page */
49 if (pte_present(pte)) {
50 /* get the physical address the page is
51 * refering to */
52 phys_addr = (unsigned long)
53 page_to_phys(pte_page(pte));
54 /* add the offset within the page */
55 phys_addr |= (virt_addr & ~PAGE_MASK);
56 }
57 }
58 }
59 }
60
61 return phys_addr;
62}
63
64static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
65 size_t size)
66{
67 if (is_kseg2(addr))
68 return phys_to_bus(virt_to_phys_from_pte(addr));
69 else
70 return phys_to_bus(virt_to_phys(addr));
71}
72
73static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
74 struct page *page)
75{
76 return phys_to_bus(page_to_phys(page));
77}
78
79static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
80 dma_addr_t dma_addr)
81{
82 return bus_to_phys(dma_addr);
83}
84
85static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
86 size_t size, enum dma_data_direction direction)
87{
88}
89
90static inline int plat_dma_supported(struct device *dev, u64 mask)
91{
92 /*
93 * we fall back to GFP_DMA when the mask isn't all 1s,
94 * so we can't guarantee allocations that must be
95 * within a tighter range than GFP_DMA..
96 */
97 if (mask < DMA_BIT_MASK(24))
98 return 0;
99
100 return 1;
101}
102
103static inline void plat_extra_sync_for_device(struct device *dev)
104{
105 return;
106}
107
108static inline int plat_dma_mapping_error(struct device *dev,
109 dma_addr_t dma_addr)
110{
111 return 0;
112}
113
114static inline int plat_device_is_coherent(struct device *dev)
115{
116 return 0;
117}
118
119#endif /* __ASM_MACH_POWERTV_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-powertv/interrupts.h b/arch/mips/include/asm/mach-powertv/interrupts.h
new file mode 100644
index 000000000000..629a57413657
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/interrupts.h
@@ -0,0 +1,254 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef _ASM_MACH_POWERTV_INTERRUPTS_H_
20#define _ASM_MACH_POWERTV_INTERRUPTS_H_
21
22/*
23 * Defines for all of the interrupt lines
24 */
25
26/* Definitions for backward compatibility */
27#define kIrq_Uart1 irq_uart1
28
29#define ibase 0
30
31/*------------- Register: int_stat_3 */
32/* 126 unused (bit 31) */
33#define irq_asc2video (ibase+126) /* ASC 2 Video Interrupt */
34#define irq_asc1video (ibase+125) /* ASC 1 Video Interrupt */
35#define irq_comms_block_wd (ibase+124) /* ASC 1 Video Interrupt */
36#define irq_fdma_mailbox (ibase+123) /* FDMA Mailbox Output */
37#define irq_fdma_gp (ibase+122) /* FDMA GP Output */
38#define irq_mips_pic (ibase+121) /* MIPS Performance Counter
39 * Interrupt */
40#define irq_mips_timer (ibase+120) /* MIPS Timer Interrupt */
41#define irq_memory_protect (ibase+119) /* Memory Protection Interrupt
42 * -- Ored by glue logic inside
43 * SPARC ILC (see
44 * INT_MEM_PROT_STAT, below,
45 * for individual interrupts)
46 */
47/* 118 unused (bit 22) */
48#define irq_sbag (ibase+117) /* SBAG Interrupt -- Ored by
49 * glue logic inside SPARC ILC
50 * (see INT_SBAG_STAT, below,
51 * for individual interrupts) */
52#define irq_qam_b_fec (ibase+116) /* QAM B FEC Interrupt */
53#define irq_qam_a_fec (ibase+115) /* QAM A FEC Interrupt */
54/* 114 unused (bit 18) */
55#define irq_mailbox (ibase+113) /* Mailbox Debug Interrupt --
56 * Ored by glue logic inside
57 * SPARC ILC (see
58 * INT_MAILBOX_STAT, below, for
59 * individual interrupts) */
60#define irq_fuse_stat1 (ibase+112) /* Fuse Status 1 */
61#define irq_fuse_stat2 (ibase+111) /* Fuse Status 2 */
62#define irq_fuse_stat3 (ibase+110) /* Blitter Interrupt / Fuse
63 * Status 3 */
64#define irq_blitter (ibase+110) /* Blitter Interrupt / Fuse
65 * Status 3 */
66#define irq_avc1_pp0 (ibase+109) /* AVC Decoder #1 PP0
67 * Interrupt */
68#define irq_avc1_pp1 (ibase+108) /* AVC Decoder #1 PP1
69 * Interrupt */
70#define irq_avc1_mbe (ibase+107) /* AVC Decoder #1 MBE
71 * Interrupt */
72#define irq_avc2_pp0 (ibase+106) /* AVC Decoder #2 PP0
73 * Interrupt */
74#define irq_avc2_pp1 (ibase+105) /* AVC Decoder #2 PP1
75 * Interrupt */
76#define irq_avc2_mbe (ibase+104) /* AVC Decoder #2 MBE
77 * Interrupt */
78#define irq_zbug_spi (ibase+103) /* Zbug SPI Slave Interrupt */
79#define irq_qam_mod2 (ibase+102) /* QAM Modulator 2 DMA
80 * Interrupt */
81#define irq_ir_rx (ibase+101) /* IR RX 2 Interrupt */
82#define irq_aud_dsp2 (ibase+100) /* Audio DSP #2 Interrupt */
83#define irq_aud_dsp1 (ibase+99) /* Audio DSP #1 Interrupt */
84#define irq_docsis (ibase+98) /* DOCSIS Debug Interrupt */
85#define irq_sd_dvp1 (ibase+97) /* SD DVP #1 Interrupt */
86#define irq_sd_dvp2 (ibase+96) /* SD DVP #2 Interrupt */
87/*------------- Register: int_stat_2 */
88#define irq_hd_dvp (ibase+95) /* HD DVP Interrupt */
89#define kIrq_Prewatchdog (ibase+94) /* watchdog Pre-Interrupt */
90#define irq_timer2 (ibase+93) /* Programmable Timer
91 * Interrupt 2 */
92#define irq_1394 (ibase+92) /* 1394 Firewire Interrupt */
93#define irq_usbohci (ibase+91) /* USB 2.0 OHCI Interrupt */
94#define irq_usbehci (ibase+90) /* USB 2.0 EHCI Interrupt */
95#define irq_pciexp (ibase+89) /* PCI Express 0 Interrupt */
96#define irq_pciexp0 (ibase+89) /* PCI Express 0 Interrupt */
97#define irq_afe1 (ibase+88) /* AFE 1 Interrupt */
98#define irq_sata (ibase+87) /* SATA 1 Interrupt */
99#define irq_sata1 (ibase+87) /* SATA 1 Interrupt */
100#define irq_dtcp (ibase+86) /* DTCP Interrupt */
101#define irq_pciexp1 (ibase+85) /* PCI Express 1 Interrupt */
102/* 84 unused (bit 20) */
103/* 83 unused (bit 19) */
104/* 82 unused (bit 18) */
105#define irq_sata2 (ibase+81) /* SATA2 Interrupt */
106#define irq_uart2 (ibase+80) /* UART2 Interrupt */
107#define irq_legacy_usb (ibase+79) /* Legacy USB Host ISR (1.1
108 * Host module) */
109#define irq_pod (ibase+78) /* POD Interrupt */
110#define irq_slave_usb (ibase+77) /* Slave USB */
111#define irq_denc1 (ibase+76) /* DENC #1 VTG Interrupt */
112#define irq_vbi_vtg (ibase+75) /* VBI VTG Interrupt */
113#define irq_afe2 (ibase+74) /* AFE 2 Interrupt */
114#define irq_denc2 (ibase+73) /* DENC #2 VTG Interrupt */
115#define irq_asc2 (ibase+72) /* ASC #2 Interrupt */
116#define irq_asc1 (ibase+71) /* ASC #1 Interrupt */
117#define irq_mod_dma (ibase+70) /* Modulator DMA Interrupt */
118#define irq_byte_eng1 (ibase+69) /* Byte Engine Interrupt [1] */
119#define irq_byte_eng0 (ibase+68) /* Byte Engine Interrupt [0] */
120/* 67 unused (bit 03) */
121/* 66 unused (bit 02) */
122/* 65 unused (bit 01) */
123/* 64 unused (bit 00) */
124/*------------- Register: int_stat_1 */
125/* 63 unused (bit 31) */
126/* 62 unused (bit 30) */
127/* 61 unused (bit 29) */
128/* 60 unused (bit 28) */
129/* 59 unused (bit 27) */
130/* 58 unused (bit 26) */
131/* 57 unused (bit 25) */
132/* 56 unused (bit 24) */
133#define irq_buf_dma_mem2mem (ibase+55) /* BufDMA Memory to Memory
134 * Interrupt */
135#define irq_buf_dma_usbtransmit (ibase+54) /* BufDMA USB Transmit
136 * Interrupt */
137#define irq_buf_dma_qpskpodtransmit (ibase+53) /* BufDMA QPSK/POD Tramsit
138 * Interrupt */
139#define irq_buf_dma_transmit_error (ibase+52) /* BufDMA Transmit Error
140 * Interrupt */
141#define irq_buf_dma_usbrecv (ibase+51) /* BufDMA USB Receive
142 * Interrupt */
143#define irq_buf_dma_qpskpodrecv (ibase+50) /* BufDMA QPSK/POD Receive
144 * Interrupt */
145#define irq_buf_dma_recv_error (ibase+49) /* BufDMA Receive Error
146 * Interrupt */
147#define irq_qamdma_transmit_play (ibase+48) /* QAMDMA Transmit/Play
148 * Interrupt */
149#define irq_qamdma_transmit_error (ibase+47) /* QAMDMA Transmit Error
150 * Interrupt */
151#define irq_qamdma_recv2high (ibase+46) /* QAMDMA Receive 2 High
152 * (Chans 63-32) */
153#define irq_qamdma_recv2low (ibase+45) /* QAMDMA Receive 2 Low
154 * (Chans 31-0) */
155#define irq_qamdma_recv1high (ibase+44) /* QAMDMA Receive 1 High
156 * (Chans 63-32) */
157#define irq_qamdma_recv1low (ibase+43) /* QAMDMA Receive 1 Low
158 * (Chans 31-0) */
159#define irq_qamdma_recv_error (ibase+42) /* QAMDMA Receive Error
160 * Interrupt */
161#define irq_mpegsplice (ibase+41) /* MPEG Splice Interrupt */
162#define irq_deinterlace_rdy (ibase+40) /* Deinterlacer Frame Ready
163 * Interrupt */
164#define irq_ext_in0 (ibase+39) /* External Interrupt irq_in0 */
165#define irq_gpio3 (ibase+38) /* GP I/O IRQ 3 - From GP I/O
166 * Module */
167#define irq_gpio2 (ibase+37) /* GP I/O IRQ 2 - From GP I/O
168 * Module (ABE_intN) */
169#define irq_pcrcmplt1 (ibase+36) /* PCR Capture Complete or
170 * Discontinuity 1 */
171#define irq_pcrcmplt2 (ibase+35) /* PCR Capture Complete or
172 * Discontinuity 2 */
173#define irq_parse_peierr (ibase+34) /* PID Parser Error Detect
174 * (PEI) */
175#define irq_parse_cont_err (ibase+33) /* PID Parser continuity error
176 * detect */
177#define irq_ds1framer (ibase+32) /* DS1 Framer Interrupt */
178/*------------- Register: int_stat_0 */
179#define irq_gpio1 (ibase+31) /* GP I/O IRQ 1 - From GP I/O
180 * Module */
181#define irq_gpio0 (ibase+30) /* GP I/O IRQ 0 - From GP I/O
182 * Module */
183#define irq_qpsk_out_aloha (ibase+29) /* QPSK Output Slotted Aloha
184 * (chan 3) Transmission
185 * Completed OK */
186#define irq_qpsk_out_tdma (ibase+28) /* QPSK Output TDMA (chan 2)
187 * Transmission Completed OK */
188#define irq_qpsk_out_reserve (ibase+27) /* QPSK Output Reservation
189 * (chan 1) Transmission
190 * Completed OK */
191#define irq_qpsk_out_aloha_err (ibase+26) /* QPSK Output Slotted Aloha
192 * (chan 3)Transmission
193 * completed with Errors. */
194#define irq_qpsk_out_tdma_err (ibase+25) /* QPSK Output TDMA (chan 2)
195 * Transmission completed with
196 * Errors. */
197#define irq_qpsk_out_rsrv_err (ibase+24) /* QPSK Output Reservation
198 * (chan 1) Transmission
199 * completed with Errors */
200#define irq_aloha_fail (ibase+23) /* Unsuccessful Resend of Aloha
201 * for N times. Aloha retry
202 * timeout for channel 3. */
203#define irq_timer1 (ibase+22) /* Programmable Timer
204 * Interrupt */
205#define irq_keyboard (ibase+21) /* Keyboard Module Interrupt */
206#define irq_i2c (ibase+20) /* I2C Module Interrupt */
207#define irq_spi (ibase+19) /* SPI Module Interrupt */
208#define irq_irblaster (ibase+18) /* IR Blaster Interrupt */
209#define irq_splice_detect (ibase+17) /* PID Key Change Interrupt or
210 * Splice Detect Interrupt */
211#define irq_se_micro (ibase+16) /* Secure Micro I/F Module
212 * Interrupt */
213#define irq_uart1 (ibase+15) /* UART Interrupt */
214#define irq_irrecv (ibase+14) /* IR Receiver Interrupt */
215#define irq_host_int1 (ibase+13) /* Host-to-Host Interrupt 1 */
216#define irq_host_int0 (ibase+12) /* Host-to-Host Interrupt 0 */
217#define irq_qpsk_hecerr (ibase+11) /* QPSK HEC Error Interrupt */
218#define irq_qpsk_crcerr (ibase+10) /* QPSK AAL-5 CRC Error
219 * Interrupt */
220/* 9 unused (bit 09) */
221/* 8 unused (bit 08) */
222#define irq_psicrcerr (ibase+7) /* QAM PSI CRC Error
223 * Interrupt */
224#define irq_psilength_err (ibase+6) /* QAM PSI Length Error
225 * Interrupt */
226#define irq_esfforward (ibase+5) /* ESF Interrupt Mark From
227 * Forward Path Reference -
228 * every 3ms when forward Mbits
229 * and forward slot control
230 * bytes are updated. */
231#define irq_esfreverse (ibase+4) /* ESF Interrupt Mark from
232 * Reverse Path Reference -
233 * delayed from forward mark by
234 * the ranging delay plus a
235 * fixed amount. When reverse
236 * Mbits and reverse slot
237 * control bytes are updated.
238 * Occurs every 3ms for 3.0M and
239 * 1.554 M upstream rates and
240 * every 6 ms for 256K upstream
241 * rate. */
242#define irq_aloha_timeout (ibase+3) /* Slotted-Aloha timeout on
243 * Channel 1. */
244#define irq_reservation (ibase+2) /* Partial (or Incremental)
245 * Reservation Message Completed
246 * or Slotted aloha verify for
247 * channel 1. */
248#define irq_aloha3 (ibase+1) /* Slotted-Aloha Message Verify
249 * Interrupt or Reservation
250 * increment completed for
251 * channel 3. */
252#define irq_mpeg_d (ibase+0) /* MPEG Decoder Interrupt */
253#endif /* _ASM_MACH_POWERTV_INTERRUPTS_H_ */
254
diff --git a/arch/mips/include/asm/mach-powertv/ioremap.h b/arch/mips/include/asm/mach-powertv/ioremap.h
new file mode 100644
index 000000000000..e6276d5146e8
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/ioremap.h
@@ -0,0 +1,90 @@
1/*
2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version
5 * 2 of the License, or (at your option) any later version.
6 *
7 * Portions Copyright (C) Cisco Systems, Inc.
8 */
9#ifndef __ASM_MACH_POWERTV_IOREMAP_H
10#define __ASM_MACH_POWERTV_IOREMAP_H
11
12#include <linux/types.h>
13
14#define LOW_MEM_BOUNDARY_PHYS 0x20000000
15#define LOW_MEM_BOUNDARY_MASK (~(LOW_MEM_BOUNDARY_PHYS - 1))
16
17/*
18 * The bus addresses are different than the physical addresses that
19 * the processor sees by an offset. This offset varies by ASIC
20 * version. Define a variable to hold the offset and some macros to
21 * make the conversion simpler. */
22extern unsigned long phys_to_bus_offset;
23
24#ifdef CONFIG_HIGHMEM
25#define MEM_GAP_PHYS 0x60000000
26/*
27 * TODO: We will use the hard code for conversion between physical and
28 * bus until the bootloader releases their device tree to us.
29 */
30#define phys_to_bus(x) (((x) < LOW_MEM_BOUNDARY_PHYS) ? \
31 ((x) + phys_to_bus_offset) : (x))
32#define bus_to_phys(x) (((x) < MEM_GAP_PHYS_ADDR) ? \
33 ((x) - phys_to_bus_offset) : (x))
34#else
35#define phys_to_bus(x) ((x) + phys_to_bus_offset)
36#define bus_to_phys(x) ((x) - phys_to_bus_offset)
37#endif
38
39/*
40 * Determine whether the address we are given is for an ASIC device
41 * Params: addr Address to check
42 * Returns: Zero if the address is not for ASIC devices, non-zero
43 * if it is.
44 */
45static inline int asic_is_device_addr(phys_t addr)
46{
47 return !((phys_t)addr & (phys_t) LOW_MEM_BOUNDARY_MASK);
48}
49
50/*
51 * Determine whether the address we are given is external RAM mappable
52 * into KSEG1.
53 * Params: addr Address to check
54 * Returns: Zero if the address is not for external RAM and
55 */
56static inline int asic_is_lowmem_ram_addr(phys_t addr)
57{
58 /*
59 * The RAM always starts at the following address in the processor's
60 * physical address space
61 */
62 static const phys_t phys_ram_base = 0x10000000;
63 phys_t bus_ram_base;
64
65 bus_ram_base = phys_to_bus_offset + phys_ram_base;
66
67 return addr >= bus_ram_base &&
68 addr < (bus_ram_base + (LOW_MEM_BOUNDARY_PHYS - phys_ram_base));
69}
70
71/*
72 * Allow physical addresses to be fixed up to help peripherals located
73 * outside the low 32-bit range -- generic pass-through version.
74 */
75static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
76{
77 return phys_addr;
78}
79
80static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
81 unsigned long flags)
82{
83 return NULL;
84}
85
86static inline int plat_iounmap(const volatile void __iomem *addr)
87{
88 return 0;
89}
90#endif /* __ASM_MACH_POWERTV_IOREMAP_H */
diff --git a/arch/mips/include/asm/mach-powertv/irq.h b/arch/mips/include/asm/mach-powertv/irq.h
new file mode 100644
index 000000000000..4bd5d0c61a91
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/irq.h
@@ -0,0 +1,25 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef _ASM_MACH_POWERTV_IRQ_H
20#define _ASM_MACH_POWERTV_IRQ_H
21#include <asm/mach-powertv/interrupts.h>
22
23#define MIPS_CPU_IRQ_BASE ibase
24#define NR_IRQS 127
25#endif
diff --git a/arch/mips/include/asm/mach-powertv/powertv-clock.h b/arch/mips/include/asm/mach-powertv/powertv-clock.h
new file mode 100644
index 000000000000..6f3e9a0fcf8c
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/powertv-clock.h
@@ -0,0 +1,29 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18/*
19 * Local definitions for the powertv PCI code
20 */
21
22#ifndef _POWERTV_PCI_POWERTV_PCI_H_
23#define _POWERTV_PCI_POWERTV_PCI_H_
24extern int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
25extern int asic_pcie_init(void);
26extern int asic_pcie_init(void);
27
28extern int log_level;
29#endif
diff --git a/arch/mips/include/asm/mach-excite/war.h b/arch/mips/include/asm/mach-powertv/war.h
index 1f82180c1598..7ac05ecc512b 100644
--- a/arch/mips/include/asm/mach-excite/war.h
+++ b/arch/mips/include/asm/mach-powertv/war.h
@@ -3,10 +3,13 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * This version for the PowerTV platform copied from the Malta version.
7 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> 8 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
9 * Portions copyright (C) 2009 Cisco Systems, Inc.
7 */ 10 */
8#ifndef __ASM_MIPS_MACH_EXCITE_WAR_H 11#ifndef __ASM_MACH_POWERTV_WAR_H
9#define __ASM_MIPS_MACH_EXCITE_WAR_H 12#define __ASM_MACH_POWERTV_WAR_H
10 13
11#define R4600_V1_INDEX_ICACHEOP_WAR 0 14#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0 15#define R4600_V1_HIT_CACHEOP_WAR 0
@@ -14,12 +17,12 @@
14#define R5432_CP0_INTERRUPT_WAR 0 17#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0 18#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0 19#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0 20#define MIPS4K_ICACHE_REFILL_WAR 1
18#define MIPS_CACHE_SYNC_WAR 0 21#define MIPS_CACHE_SYNC_WAR 1
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 22#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 1 23#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 1 24#define ICACHE_REFILLS_WORKAROUND_WAR 1
22#define R10000_LLSC_WAR 0 25#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 26#define MIPS34K_MISSED_ITLB_WAR 0
24 27
25#endif /* __ASM_MIPS_MACH_EXCITE_WAR_H */ 28#endif /* __ASM_MACH_POWERTV_WAR_H */
diff --git a/arch/mips/include/asm/mips-boards/bonito64.h b/arch/mips/include/asm/mips-boards/bonito64.h
index a576ce044c3c..d14e2adc4be5 100644
--- a/arch/mips/include/asm/mips-boards/bonito64.h
+++ b/arch/mips/include/asm/mips-boards/bonito64.h
@@ -26,11 +26,6 @@
26/* offsets from base register */ 26/* offsets from base register */
27#define BONITO(x) (x) 27#define BONITO(x) (x)
28 28
29#elif defined(CONFIG_LEMOTE_FULOONG2E)
30
31#define BONITO(x) (*(volatile u32 *)((char *)CKSEG1ADDR(BONITO_REG_BASE) + (x)))
32#define BONITO_IRQ_BASE 32
33
34#else 29#else
35 30
36/* 31/*
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index 6083db586500..145bb81ccaa5 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -24,6 +24,33 @@
24#endif /* SMTC */ 24#endif /* SMTC */
25#include <asm-generic/mm_hooks.h> 25#include <asm-generic/mm_hooks.h>
26 26
27#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
28
29#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
30 tlbmiss_handler_setup_pgd((unsigned long)(pgd))
31
32static inline void tlbmiss_handler_setup_pgd(unsigned long pgd)
33{
34 /* Check for swapper_pg_dir and convert to physical address. */
35 if ((pgd & CKSEG3) == CKSEG0)
36 pgd = CPHYSADDR(pgd);
37 write_c0_context(pgd << 11);
38}
39
40#define TLBMISS_HANDLER_SETUP() \
41 do { \
42 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \
43 write_c0_xcontext((unsigned long) smp_processor_id() << 51); \
44 } while (0)
45
46
47static inline unsigned long get_current_pgd(void)
48{
49 return PHYS_TO_XKSEG_CACHED((read_c0_context() >> 11) & ~0xfffUL);
50}
51
52#else /* CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/
53
27/* 54/*
28 * For the fast tlb miss handlers, we keep a per cpu array of pointers 55 * For the fast tlb miss handlers, we keep a per cpu array of pointers
29 * to the current pgd for each processor. Also, the proc. id is stuffed 56 * to the current pgd for each processor. Also, the proc. id is stuffed
@@ -46,7 +73,7 @@ extern unsigned long pgd_current[];
46 back_to_back_c0_hazard(); \ 73 back_to_back_c0_hazard(); \
47 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 74 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
48#endif 75#endif
49 76#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
50#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 77#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
51 78
52#define ASID_INC 0x40 79#define ASID_INC 0x40
diff --git a/arch/mips/include/asm/octeon/cvmx-agl-defs.h b/arch/mips/include/asm/octeon/cvmx-agl-defs.h
new file mode 100644
index 000000000000..ec94b9ab7be1
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-agl-defs.h
@@ -0,0 +1,1194 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_AGL_DEFS_H__
29#define __CVMX_AGL_DEFS_H__
30
31#define CVMX_AGL_GMX_BAD_REG \
32 CVMX_ADD_IO_SEG(0x00011800E0000518ull)
33#define CVMX_AGL_GMX_BIST \
34 CVMX_ADD_IO_SEG(0x00011800E0000400ull)
35#define CVMX_AGL_GMX_DRV_CTL \
36 CVMX_ADD_IO_SEG(0x00011800E00007F0ull)
37#define CVMX_AGL_GMX_INF_MODE \
38 CVMX_ADD_IO_SEG(0x00011800E00007F8ull)
39#define CVMX_AGL_GMX_PRTX_CFG(offset) \
40 CVMX_ADD_IO_SEG(0x00011800E0000010ull + (((offset) & 1) * 2048))
41#define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) \
42 CVMX_ADD_IO_SEG(0x00011800E0000180ull + (((offset) & 1) * 2048))
43#define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) \
44 CVMX_ADD_IO_SEG(0x00011800E0000188ull + (((offset) & 1) * 2048))
45#define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) \
46 CVMX_ADD_IO_SEG(0x00011800E0000190ull + (((offset) & 1) * 2048))
47#define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) \
48 CVMX_ADD_IO_SEG(0x00011800E0000198ull + (((offset) & 1) * 2048))
49#define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) \
50 CVMX_ADD_IO_SEG(0x00011800E00001A0ull + (((offset) & 1) * 2048))
51#define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) \
52 CVMX_ADD_IO_SEG(0x00011800E00001A8ull + (((offset) & 1) * 2048))
53#define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) \
54 CVMX_ADD_IO_SEG(0x00011800E0000108ull + (((offset) & 1) * 2048))
55#define CVMX_AGL_GMX_RXX_ADR_CTL(offset) \
56 CVMX_ADD_IO_SEG(0x00011800E0000100ull + (((offset) & 1) * 2048))
57#define CVMX_AGL_GMX_RXX_DECISION(offset) \
58 CVMX_ADD_IO_SEG(0x00011800E0000040ull + (((offset) & 1) * 2048))
59#define CVMX_AGL_GMX_RXX_FRM_CHK(offset) \
60 CVMX_ADD_IO_SEG(0x00011800E0000020ull + (((offset) & 1) * 2048))
61#define CVMX_AGL_GMX_RXX_FRM_CTL(offset) \
62 CVMX_ADD_IO_SEG(0x00011800E0000018ull + (((offset) & 1) * 2048))
63#define CVMX_AGL_GMX_RXX_FRM_MAX(offset) \
64 CVMX_ADD_IO_SEG(0x00011800E0000030ull + (((offset) & 1) * 2048))
65#define CVMX_AGL_GMX_RXX_FRM_MIN(offset) \
66 CVMX_ADD_IO_SEG(0x00011800E0000028ull + (((offset) & 1) * 2048))
67#define CVMX_AGL_GMX_RXX_IFG(offset) \
68 CVMX_ADD_IO_SEG(0x00011800E0000058ull + (((offset) & 1) * 2048))
69#define CVMX_AGL_GMX_RXX_INT_EN(offset) \
70 CVMX_ADD_IO_SEG(0x00011800E0000008ull + (((offset) & 1) * 2048))
71#define CVMX_AGL_GMX_RXX_INT_REG(offset) \
72 CVMX_ADD_IO_SEG(0x00011800E0000000ull + (((offset) & 1) * 2048))
73#define CVMX_AGL_GMX_RXX_JABBER(offset) \
74 CVMX_ADD_IO_SEG(0x00011800E0000038ull + (((offset) & 1) * 2048))
75#define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) \
76 CVMX_ADD_IO_SEG(0x00011800E0000068ull + (((offset) & 1) * 2048))
77#define CVMX_AGL_GMX_RXX_STATS_CTL(offset) \
78 CVMX_ADD_IO_SEG(0x00011800E0000050ull + (((offset) & 1) * 2048))
79#define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) \
80 CVMX_ADD_IO_SEG(0x00011800E0000088ull + (((offset) & 1) * 2048))
81#define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) \
82 CVMX_ADD_IO_SEG(0x00011800E0000098ull + (((offset) & 1) * 2048))
83#define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) \
84 CVMX_ADD_IO_SEG(0x00011800E00000A8ull + (((offset) & 1) * 2048))
85#define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) \
86 CVMX_ADD_IO_SEG(0x00011800E00000B8ull + (((offset) & 1) * 2048))
87#define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) \
88 CVMX_ADD_IO_SEG(0x00011800E0000080ull + (((offset) & 1) * 2048))
89#define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) \
90 CVMX_ADD_IO_SEG(0x00011800E00000C0ull + (((offset) & 1) * 2048))
91#define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) \
92 CVMX_ADD_IO_SEG(0x00011800E0000090ull + (((offset) & 1) * 2048))
93#define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) \
94 CVMX_ADD_IO_SEG(0x00011800E00000A0ull + (((offset) & 1) * 2048))
95#define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) \
96 CVMX_ADD_IO_SEG(0x00011800E00000B0ull + (((offset) & 1) * 2048))
97#define CVMX_AGL_GMX_RXX_UDD_SKP(offset) \
98 CVMX_ADD_IO_SEG(0x00011800E0000048ull + (((offset) & 1) * 2048))
99#define CVMX_AGL_GMX_RX_BP_DROPX(offset) \
100 CVMX_ADD_IO_SEG(0x00011800E0000420ull + (((offset) & 1) * 8))
101#define CVMX_AGL_GMX_RX_BP_OFFX(offset) \
102 CVMX_ADD_IO_SEG(0x00011800E0000460ull + (((offset) & 1) * 8))
103#define CVMX_AGL_GMX_RX_BP_ONX(offset) \
104 CVMX_ADD_IO_SEG(0x00011800E0000440ull + (((offset) & 1) * 8))
105#define CVMX_AGL_GMX_RX_PRT_INFO \
106 CVMX_ADD_IO_SEG(0x00011800E00004E8ull)
107#define CVMX_AGL_GMX_RX_TX_STATUS \
108 CVMX_ADD_IO_SEG(0x00011800E00007E8ull)
109#define CVMX_AGL_GMX_SMACX(offset) \
110 CVMX_ADD_IO_SEG(0x00011800E0000230ull + (((offset) & 1) * 2048))
111#define CVMX_AGL_GMX_STAT_BP \
112 CVMX_ADD_IO_SEG(0x00011800E0000520ull)
113#define CVMX_AGL_GMX_TXX_APPEND(offset) \
114 CVMX_ADD_IO_SEG(0x00011800E0000218ull + (((offset) & 1) * 2048))
115#define CVMX_AGL_GMX_TXX_CTL(offset) \
116 CVMX_ADD_IO_SEG(0x00011800E0000270ull + (((offset) & 1) * 2048))
117#define CVMX_AGL_GMX_TXX_MIN_PKT(offset) \
118 CVMX_ADD_IO_SEG(0x00011800E0000240ull + (((offset) & 1) * 2048))
119#define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) \
120 CVMX_ADD_IO_SEG(0x00011800E0000248ull + (((offset) & 1) * 2048))
121#define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) \
122 CVMX_ADD_IO_SEG(0x00011800E0000238ull + (((offset) & 1) * 2048))
123#define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) \
124 CVMX_ADD_IO_SEG(0x00011800E0000258ull + (((offset) & 1) * 2048))
125#define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) \
126 CVMX_ADD_IO_SEG(0x00011800E0000260ull + (((offset) & 1) * 2048))
127#define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) \
128 CVMX_ADD_IO_SEG(0x00011800E0000250ull + (((offset) & 1) * 2048))
129#define CVMX_AGL_GMX_TXX_STAT0(offset) \
130 CVMX_ADD_IO_SEG(0x00011800E0000280ull + (((offset) & 1) * 2048))
131#define CVMX_AGL_GMX_TXX_STAT1(offset) \
132 CVMX_ADD_IO_SEG(0x00011800E0000288ull + (((offset) & 1) * 2048))
133#define CVMX_AGL_GMX_TXX_STAT2(offset) \
134 CVMX_ADD_IO_SEG(0x00011800E0000290ull + (((offset) & 1) * 2048))
135#define CVMX_AGL_GMX_TXX_STAT3(offset) \
136 CVMX_ADD_IO_SEG(0x00011800E0000298ull + (((offset) & 1) * 2048))
137#define CVMX_AGL_GMX_TXX_STAT4(offset) \
138 CVMX_ADD_IO_SEG(0x00011800E00002A0ull + (((offset) & 1) * 2048))
139#define CVMX_AGL_GMX_TXX_STAT5(offset) \
140 CVMX_ADD_IO_SEG(0x00011800E00002A8ull + (((offset) & 1) * 2048))
141#define CVMX_AGL_GMX_TXX_STAT6(offset) \
142 CVMX_ADD_IO_SEG(0x00011800E00002B0ull + (((offset) & 1) * 2048))
143#define CVMX_AGL_GMX_TXX_STAT7(offset) \
144 CVMX_ADD_IO_SEG(0x00011800E00002B8ull + (((offset) & 1) * 2048))
145#define CVMX_AGL_GMX_TXX_STAT8(offset) \
146 CVMX_ADD_IO_SEG(0x00011800E00002C0ull + (((offset) & 1) * 2048))
147#define CVMX_AGL_GMX_TXX_STAT9(offset) \
148 CVMX_ADD_IO_SEG(0x00011800E00002C8ull + (((offset) & 1) * 2048))
149#define CVMX_AGL_GMX_TXX_STATS_CTL(offset) \
150 CVMX_ADD_IO_SEG(0x00011800E0000268ull + (((offset) & 1) * 2048))
151#define CVMX_AGL_GMX_TXX_THRESH(offset) \
152 CVMX_ADD_IO_SEG(0x00011800E0000210ull + (((offset) & 1) * 2048))
153#define CVMX_AGL_GMX_TX_BP \
154 CVMX_ADD_IO_SEG(0x00011800E00004D0ull)
155#define CVMX_AGL_GMX_TX_COL_ATTEMPT \
156 CVMX_ADD_IO_SEG(0x00011800E0000498ull)
157#define CVMX_AGL_GMX_TX_IFG \
158 CVMX_ADD_IO_SEG(0x00011800E0000488ull)
159#define CVMX_AGL_GMX_TX_INT_EN \
160 CVMX_ADD_IO_SEG(0x00011800E0000508ull)
161#define CVMX_AGL_GMX_TX_INT_REG \
162 CVMX_ADD_IO_SEG(0x00011800E0000500ull)
163#define CVMX_AGL_GMX_TX_JAM \
164 CVMX_ADD_IO_SEG(0x00011800E0000490ull)
165#define CVMX_AGL_GMX_TX_LFSR \
166 CVMX_ADD_IO_SEG(0x00011800E00004F8ull)
167#define CVMX_AGL_GMX_TX_OVR_BP \
168 CVMX_ADD_IO_SEG(0x00011800E00004C8ull)
169#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC \
170 CVMX_ADD_IO_SEG(0x00011800E00004A0ull)
171#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE \
172 CVMX_ADD_IO_SEG(0x00011800E00004A8ull)
173
174union cvmx_agl_gmx_bad_reg {
175 uint64_t u64;
176 struct cvmx_agl_gmx_bad_reg_s {
177 uint64_t reserved_38_63:26;
178 uint64_t txpsh1:1;
179 uint64_t txpop1:1;
180 uint64_t ovrflw1:1;
181 uint64_t txpsh:1;
182 uint64_t txpop:1;
183 uint64_t ovrflw:1;
184 uint64_t reserved_27_31:5;
185 uint64_t statovr:1;
186 uint64_t reserved_23_25:3;
187 uint64_t loststat:1;
188 uint64_t reserved_4_21:18;
189 uint64_t out_ovr:2;
190 uint64_t reserved_0_1:2;
191 } s;
192 struct cvmx_agl_gmx_bad_reg_s cn52xx;
193 struct cvmx_agl_gmx_bad_reg_s cn52xxp1;
194 struct cvmx_agl_gmx_bad_reg_cn56xx {
195 uint64_t reserved_35_63:29;
196 uint64_t txpsh:1;
197 uint64_t txpop:1;
198 uint64_t ovrflw:1;
199 uint64_t reserved_27_31:5;
200 uint64_t statovr:1;
201 uint64_t reserved_23_25:3;
202 uint64_t loststat:1;
203 uint64_t reserved_3_21:19;
204 uint64_t out_ovr:1;
205 uint64_t reserved_0_1:2;
206 } cn56xx;
207 struct cvmx_agl_gmx_bad_reg_cn56xx cn56xxp1;
208};
209
210union cvmx_agl_gmx_bist {
211 uint64_t u64;
212 struct cvmx_agl_gmx_bist_s {
213 uint64_t reserved_10_63:54;
214 uint64_t status:10;
215 } s;
216 struct cvmx_agl_gmx_bist_s cn52xx;
217 struct cvmx_agl_gmx_bist_s cn52xxp1;
218 struct cvmx_agl_gmx_bist_s cn56xx;
219 struct cvmx_agl_gmx_bist_s cn56xxp1;
220};
221
222union cvmx_agl_gmx_drv_ctl {
223 uint64_t u64;
224 struct cvmx_agl_gmx_drv_ctl_s {
225 uint64_t reserved_49_63:15;
226 uint64_t byp_en1:1;
227 uint64_t reserved_45_47:3;
228 uint64_t pctl1:5;
229 uint64_t reserved_37_39:3;
230 uint64_t nctl1:5;
231 uint64_t reserved_17_31:15;
232 uint64_t byp_en:1;
233 uint64_t reserved_13_15:3;
234 uint64_t pctl:5;
235 uint64_t reserved_5_7:3;
236 uint64_t nctl:5;
237 } s;
238 struct cvmx_agl_gmx_drv_ctl_s cn52xx;
239 struct cvmx_agl_gmx_drv_ctl_s cn52xxp1;
240 struct cvmx_agl_gmx_drv_ctl_cn56xx {
241 uint64_t reserved_17_63:47;
242 uint64_t byp_en:1;
243 uint64_t reserved_13_15:3;
244 uint64_t pctl:5;
245 uint64_t reserved_5_7:3;
246 uint64_t nctl:5;
247 } cn56xx;
248 struct cvmx_agl_gmx_drv_ctl_cn56xx cn56xxp1;
249};
250
251union cvmx_agl_gmx_inf_mode {
252 uint64_t u64;
253 struct cvmx_agl_gmx_inf_mode_s {
254 uint64_t reserved_2_63:62;
255 uint64_t en:1;
256 uint64_t reserved_0_0:1;
257 } s;
258 struct cvmx_agl_gmx_inf_mode_s cn52xx;
259 struct cvmx_agl_gmx_inf_mode_s cn52xxp1;
260 struct cvmx_agl_gmx_inf_mode_s cn56xx;
261 struct cvmx_agl_gmx_inf_mode_s cn56xxp1;
262};
263
264union cvmx_agl_gmx_prtx_cfg {
265 uint64_t u64;
266 struct cvmx_agl_gmx_prtx_cfg_s {
267 uint64_t reserved_6_63:58;
268 uint64_t tx_en:1;
269 uint64_t rx_en:1;
270 uint64_t slottime:1;
271 uint64_t duplex:1;
272 uint64_t speed:1;
273 uint64_t en:1;
274 } s;
275 struct cvmx_agl_gmx_prtx_cfg_s cn52xx;
276 struct cvmx_agl_gmx_prtx_cfg_s cn52xxp1;
277 struct cvmx_agl_gmx_prtx_cfg_s cn56xx;
278 struct cvmx_agl_gmx_prtx_cfg_s cn56xxp1;
279};
280
281union cvmx_agl_gmx_rxx_adr_cam0 {
282 uint64_t u64;
283 struct cvmx_agl_gmx_rxx_adr_cam0_s {
284 uint64_t adr:64;
285 } s;
286 struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xx;
287 struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xxp1;
288 struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xx;
289 struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xxp1;
290};
291
292union cvmx_agl_gmx_rxx_adr_cam1 {
293 uint64_t u64;
294 struct cvmx_agl_gmx_rxx_adr_cam1_s {
295 uint64_t adr:64;
296 } s;
297 struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xx;
298 struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xxp1;
299 struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xx;
300 struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xxp1;
301};
302
303union cvmx_agl_gmx_rxx_adr_cam2 {
304 uint64_t u64;
305 struct cvmx_agl_gmx_rxx_adr_cam2_s {
306 uint64_t adr:64;
307 } s;
308 struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xx;
309 struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xxp1;
310 struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xx;
311 struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xxp1;
312};
313
314union cvmx_agl_gmx_rxx_adr_cam3 {
315 uint64_t u64;
316 struct cvmx_agl_gmx_rxx_adr_cam3_s {
317 uint64_t adr:64;
318 } s;
319 struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xx;
320 struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xxp1;
321 struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xx;
322 struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xxp1;
323};
324
325union cvmx_agl_gmx_rxx_adr_cam4 {
326 uint64_t u64;
327 struct cvmx_agl_gmx_rxx_adr_cam4_s {
328 uint64_t adr:64;
329 } s;
330 struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xx;
331 struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xxp1;
332 struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xx;
333 struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xxp1;
334};
335
336union cvmx_agl_gmx_rxx_adr_cam5 {
337 uint64_t u64;
338 struct cvmx_agl_gmx_rxx_adr_cam5_s {
339 uint64_t adr:64;
340 } s;
341 struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xx;
342 struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xxp1;
343 struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xx;
344 struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xxp1;
345};
346
347union cvmx_agl_gmx_rxx_adr_cam_en {
348 uint64_t u64;
349 struct cvmx_agl_gmx_rxx_adr_cam_en_s {
350 uint64_t reserved_8_63:56;
351 uint64_t en:8;
352 } s;
353 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xx;
354 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1;
355 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx;
356 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1;
357};
358
359union cvmx_agl_gmx_rxx_adr_ctl {
360 uint64_t u64;
361 struct cvmx_agl_gmx_rxx_adr_ctl_s {
362 uint64_t reserved_4_63:60;
363 uint64_t cam_mode:1;
364 uint64_t mcst:2;
365 uint64_t bcst:1;
366 } s;
367 struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xx;
368 struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xxp1;
369 struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xx;
370 struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xxp1;
371};
372
373union cvmx_agl_gmx_rxx_decision {
374 uint64_t u64;
375 struct cvmx_agl_gmx_rxx_decision_s {
376 uint64_t reserved_5_63:59;
377 uint64_t cnt:5;
378 } s;
379 struct cvmx_agl_gmx_rxx_decision_s cn52xx;
380 struct cvmx_agl_gmx_rxx_decision_s cn52xxp1;
381 struct cvmx_agl_gmx_rxx_decision_s cn56xx;
382 struct cvmx_agl_gmx_rxx_decision_s cn56xxp1;
383};
384
385union cvmx_agl_gmx_rxx_frm_chk {
386 uint64_t u64;
387 struct cvmx_agl_gmx_rxx_frm_chk_s {
388 uint64_t reserved_9_63:55;
389 uint64_t skperr:1;
390 uint64_t rcverr:1;
391 uint64_t lenerr:1;
392 uint64_t alnerr:1;
393 uint64_t fcserr:1;
394 uint64_t jabber:1;
395 uint64_t maxerr:1;
396 uint64_t reserved_1_1:1;
397 uint64_t minerr:1;
398 } s;
399 struct cvmx_agl_gmx_rxx_frm_chk_s cn52xx;
400 struct cvmx_agl_gmx_rxx_frm_chk_s cn52xxp1;
401 struct cvmx_agl_gmx_rxx_frm_chk_s cn56xx;
402 struct cvmx_agl_gmx_rxx_frm_chk_s cn56xxp1;
403};
404
405union cvmx_agl_gmx_rxx_frm_ctl {
406 uint64_t u64;
407 struct cvmx_agl_gmx_rxx_frm_ctl_s {
408 uint64_t reserved_10_63:54;
409 uint64_t pre_align:1;
410 uint64_t pad_len:1;
411 uint64_t vlan_len:1;
412 uint64_t pre_free:1;
413 uint64_t ctl_smac:1;
414 uint64_t ctl_mcst:1;
415 uint64_t ctl_bck:1;
416 uint64_t ctl_drp:1;
417 uint64_t pre_strp:1;
418 uint64_t pre_chk:1;
419 } s;
420 struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xx;
421 struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xxp1;
422 struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xx;
423 struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xxp1;
424};
425
426union cvmx_agl_gmx_rxx_frm_max {
427 uint64_t u64;
428 struct cvmx_agl_gmx_rxx_frm_max_s {
429 uint64_t reserved_16_63:48;
430 uint64_t len:16;
431 } s;
432 struct cvmx_agl_gmx_rxx_frm_max_s cn52xx;
433 struct cvmx_agl_gmx_rxx_frm_max_s cn52xxp1;
434 struct cvmx_agl_gmx_rxx_frm_max_s cn56xx;
435 struct cvmx_agl_gmx_rxx_frm_max_s cn56xxp1;
436};
437
438union cvmx_agl_gmx_rxx_frm_min {
439 uint64_t u64;
440 struct cvmx_agl_gmx_rxx_frm_min_s {
441 uint64_t reserved_16_63:48;
442 uint64_t len:16;
443 } s;
444 struct cvmx_agl_gmx_rxx_frm_min_s cn52xx;
445 struct cvmx_agl_gmx_rxx_frm_min_s cn52xxp1;
446 struct cvmx_agl_gmx_rxx_frm_min_s cn56xx;
447 struct cvmx_agl_gmx_rxx_frm_min_s cn56xxp1;
448};
449
450union cvmx_agl_gmx_rxx_ifg {
451 uint64_t u64;
452 struct cvmx_agl_gmx_rxx_ifg_s {
453 uint64_t reserved_4_63:60;
454 uint64_t ifg:4;
455 } s;
456 struct cvmx_agl_gmx_rxx_ifg_s cn52xx;
457 struct cvmx_agl_gmx_rxx_ifg_s cn52xxp1;
458 struct cvmx_agl_gmx_rxx_ifg_s cn56xx;
459 struct cvmx_agl_gmx_rxx_ifg_s cn56xxp1;
460};
461
462union cvmx_agl_gmx_rxx_int_en {
463 uint64_t u64;
464 struct cvmx_agl_gmx_rxx_int_en_s {
465 uint64_t reserved_20_63:44;
466 uint64_t pause_drp:1;
467 uint64_t reserved_16_18:3;
468 uint64_t ifgerr:1;
469 uint64_t coldet:1;
470 uint64_t falerr:1;
471 uint64_t rsverr:1;
472 uint64_t pcterr:1;
473 uint64_t ovrerr:1;
474 uint64_t reserved_9_9:1;
475 uint64_t skperr:1;
476 uint64_t rcverr:1;
477 uint64_t lenerr:1;
478 uint64_t alnerr:1;
479 uint64_t fcserr:1;
480 uint64_t jabber:1;
481 uint64_t maxerr:1;
482 uint64_t reserved_1_1:1;
483 uint64_t minerr:1;
484 } s;
485 struct cvmx_agl_gmx_rxx_int_en_s cn52xx;
486 struct cvmx_agl_gmx_rxx_int_en_s cn52xxp1;
487 struct cvmx_agl_gmx_rxx_int_en_s cn56xx;
488 struct cvmx_agl_gmx_rxx_int_en_s cn56xxp1;
489};
490
491union cvmx_agl_gmx_rxx_int_reg {
492 uint64_t u64;
493 struct cvmx_agl_gmx_rxx_int_reg_s {
494 uint64_t reserved_20_63:44;
495 uint64_t pause_drp:1;
496 uint64_t reserved_16_18:3;
497 uint64_t ifgerr:1;
498 uint64_t coldet:1;
499 uint64_t falerr:1;
500 uint64_t rsverr:1;
501 uint64_t pcterr:1;
502 uint64_t ovrerr:1;
503 uint64_t reserved_9_9:1;
504 uint64_t skperr:1;
505 uint64_t rcverr:1;
506 uint64_t lenerr:1;
507 uint64_t alnerr:1;
508 uint64_t fcserr:1;
509 uint64_t jabber:1;
510 uint64_t maxerr:1;
511 uint64_t reserved_1_1:1;
512 uint64_t minerr:1;
513 } s;
514 struct cvmx_agl_gmx_rxx_int_reg_s cn52xx;
515 struct cvmx_agl_gmx_rxx_int_reg_s cn52xxp1;
516 struct cvmx_agl_gmx_rxx_int_reg_s cn56xx;
517 struct cvmx_agl_gmx_rxx_int_reg_s cn56xxp1;
518};
519
520union cvmx_agl_gmx_rxx_jabber {
521 uint64_t u64;
522 struct cvmx_agl_gmx_rxx_jabber_s {
523 uint64_t reserved_16_63:48;
524 uint64_t cnt:16;
525 } s;
526 struct cvmx_agl_gmx_rxx_jabber_s cn52xx;
527 struct cvmx_agl_gmx_rxx_jabber_s cn52xxp1;
528 struct cvmx_agl_gmx_rxx_jabber_s cn56xx;
529 struct cvmx_agl_gmx_rxx_jabber_s cn56xxp1;
530};
531
532union cvmx_agl_gmx_rxx_pause_drop_time {
533 uint64_t u64;
534 struct cvmx_agl_gmx_rxx_pause_drop_time_s {
535 uint64_t reserved_16_63:48;
536 uint64_t status:16;
537 } s;
538 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xx;
539 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1;
540 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx;
541 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1;
542};
543
544union cvmx_agl_gmx_rxx_stats_ctl {
545 uint64_t u64;
546 struct cvmx_agl_gmx_rxx_stats_ctl_s {
547 uint64_t reserved_1_63:63;
548 uint64_t rd_clr:1;
549 } s;
550 struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xx;
551 struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xxp1;
552 struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xx;
553 struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xxp1;
554};
555
556union cvmx_agl_gmx_rxx_stats_octs {
557 uint64_t u64;
558 struct cvmx_agl_gmx_rxx_stats_octs_s {
559 uint64_t reserved_48_63:16;
560 uint64_t cnt:48;
561 } s;
562 struct cvmx_agl_gmx_rxx_stats_octs_s cn52xx;
563 struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1;
564 struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx;
565 struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1;
566};
567
568union cvmx_agl_gmx_rxx_stats_octs_ctl {
569 uint64_t u64;
570 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s {
571 uint64_t reserved_48_63:16;
572 uint64_t cnt:48;
573 } s;
574 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xx;
575 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1;
576 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx;
577 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1;
578};
579
580union cvmx_agl_gmx_rxx_stats_octs_dmac {
581 uint64_t u64;
582 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s {
583 uint64_t reserved_48_63:16;
584 uint64_t cnt:48;
585 } s;
586 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xx;
587 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1;
588 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx;
589 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1;
590};
591
592union cvmx_agl_gmx_rxx_stats_octs_drp {
593 uint64_t u64;
594 struct cvmx_agl_gmx_rxx_stats_octs_drp_s {
595 uint64_t reserved_48_63:16;
596 uint64_t cnt:48;
597 } s;
598 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xx;
599 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1;
600 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx;
601 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1;
602};
603
604union cvmx_agl_gmx_rxx_stats_pkts {
605 uint64_t u64;
606 struct cvmx_agl_gmx_rxx_stats_pkts_s {
607 uint64_t reserved_32_63:32;
608 uint64_t cnt:32;
609 } s;
610 struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xx;
611 struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1;
612 struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx;
613 struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1;
614};
615
616union cvmx_agl_gmx_rxx_stats_pkts_bad {
617 uint64_t u64;
618 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s {
619 uint64_t reserved_32_63:32;
620 uint64_t cnt:32;
621 } s;
622 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xx;
623 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1;
624 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx;
625 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1;
626};
627
628union cvmx_agl_gmx_rxx_stats_pkts_ctl {
629 uint64_t u64;
630 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s {
631 uint64_t reserved_32_63:32;
632 uint64_t cnt:32;
633 } s;
634 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xx;
635 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1;
636 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx;
637 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1;
638};
639
640union cvmx_agl_gmx_rxx_stats_pkts_dmac {
641 uint64_t u64;
642 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s {
643 uint64_t reserved_32_63:32;
644 uint64_t cnt:32;
645 } s;
646 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xx;
647 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1;
648 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx;
649 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1;
650};
651
652union cvmx_agl_gmx_rxx_stats_pkts_drp {
653 uint64_t u64;
654 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s {
655 uint64_t reserved_32_63:32;
656 uint64_t cnt:32;
657 } s;
658 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xx;
659 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1;
660 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx;
661 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1;
662};
663
664union cvmx_agl_gmx_rxx_udd_skp {
665 uint64_t u64;
666 struct cvmx_agl_gmx_rxx_udd_skp_s {
667 uint64_t reserved_9_63:55;
668 uint64_t fcssel:1;
669 uint64_t reserved_7_7:1;
670 uint64_t len:7;
671 } s;
672 struct cvmx_agl_gmx_rxx_udd_skp_s cn52xx;
673 struct cvmx_agl_gmx_rxx_udd_skp_s cn52xxp1;
674 struct cvmx_agl_gmx_rxx_udd_skp_s cn56xx;
675 struct cvmx_agl_gmx_rxx_udd_skp_s cn56xxp1;
676};
677
678union cvmx_agl_gmx_rx_bp_dropx {
679 uint64_t u64;
680 struct cvmx_agl_gmx_rx_bp_dropx_s {
681 uint64_t reserved_6_63:58;
682 uint64_t mark:6;
683 } s;
684 struct cvmx_agl_gmx_rx_bp_dropx_s cn52xx;
685 struct cvmx_agl_gmx_rx_bp_dropx_s cn52xxp1;
686 struct cvmx_agl_gmx_rx_bp_dropx_s cn56xx;
687 struct cvmx_agl_gmx_rx_bp_dropx_s cn56xxp1;
688};
689
690union cvmx_agl_gmx_rx_bp_offx {
691 uint64_t u64;
692 struct cvmx_agl_gmx_rx_bp_offx_s {
693 uint64_t reserved_6_63:58;
694 uint64_t mark:6;
695 } s;
696 struct cvmx_agl_gmx_rx_bp_offx_s cn52xx;
697 struct cvmx_agl_gmx_rx_bp_offx_s cn52xxp1;
698 struct cvmx_agl_gmx_rx_bp_offx_s cn56xx;
699 struct cvmx_agl_gmx_rx_bp_offx_s cn56xxp1;
700};
701
702union cvmx_agl_gmx_rx_bp_onx {
703 uint64_t u64;
704 struct cvmx_agl_gmx_rx_bp_onx_s {
705 uint64_t reserved_9_63:55;
706 uint64_t mark:9;
707 } s;
708 struct cvmx_agl_gmx_rx_bp_onx_s cn52xx;
709 struct cvmx_agl_gmx_rx_bp_onx_s cn52xxp1;
710 struct cvmx_agl_gmx_rx_bp_onx_s cn56xx;
711 struct cvmx_agl_gmx_rx_bp_onx_s cn56xxp1;
712};
713
714union cvmx_agl_gmx_rx_prt_info {
715 uint64_t u64;
716 struct cvmx_agl_gmx_rx_prt_info_s {
717 uint64_t reserved_18_63:46;
718 uint64_t drop:2;
719 uint64_t reserved_2_15:14;
720 uint64_t commit:2;
721 } s;
722 struct cvmx_agl_gmx_rx_prt_info_s cn52xx;
723 struct cvmx_agl_gmx_rx_prt_info_s cn52xxp1;
724 struct cvmx_agl_gmx_rx_prt_info_cn56xx {
725 uint64_t reserved_17_63:47;
726 uint64_t drop:1;
727 uint64_t reserved_1_15:15;
728 uint64_t commit:1;
729 } cn56xx;
730 struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1;
731};
732
733union cvmx_agl_gmx_rx_tx_status {
734 uint64_t u64;
735 struct cvmx_agl_gmx_rx_tx_status_s {
736 uint64_t reserved_6_63:58;
737 uint64_t tx:2;
738 uint64_t reserved_2_3:2;
739 uint64_t rx:2;
740 } s;
741 struct cvmx_agl_gmx_rx_tx_status_s cn52xx;
742 struct cvmx_agl_gmx_rx_tx_status_s cn52xxp1;
743 struct cvmx_agl_gmx_rx_tx_status_cn56xx {
744 uint64_t reserved_5_63:59;
745 uint64_t tx:1;
746 uint64_t reserved_1_3:3;
747 uint64_t rx:1;
748 } cn56xx;
749 struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1;
750};
751
752union cvmx_agl_gmx_smacx {
753 uint64_t u64;
754 struct cvmx_agl_gmx_smacx_s {
755 uint64_t reserved_48_63:16;
756 uint64_t smac:48;
757 } s;
758 struct cvmx_agl_gmx_smacx_s cn52xx;
759 struct cvmx_agl_gmx_smacx_s cn52xxp1;
760 struct cvmx_agl_gmx_smacx_s cn56xx;
761 struct cvmx_agl_gmx_smacx_s cn56xxp1;
762};
763
764union cvmx_agl_gmx_stat_bp {
765 uint64_t u64;
766 struct cvmx_agl_gmx_stat_bp_s {
767 uint64_t reserved_17_63:47;
768 uint64_t bp:1;
769 uint64_t cnt:16;
770 } s;
771 struct cvmx_agl_gmx_stat_bp_s cn52xx;
772 struct cvmx_agl_gmx_stat_bp_s cn52xxp1;
773 struct cvmx_agl_gmx_stat_bp_s cn56xx;
774 struct cvmx_agl_gmx_stat_bp_s cn56xxp1;
775};
776
777union cvmx_agl_gmx_txx_append {
778 uint64_t u64;
779 struct cvmx_agl_gmx_txx_append_s {
780 uint64_t reserved_4_63:60;
781 uint64_t force_fcs:1;
782 uint64_t fcs:1;
783 uint64_t pad:1;
784 uint64_t preamble:1;
785 } s;
786 struct cvmx_agl_gmx_txx_append_s cn52xx;
787 struct cvmx_agl_gmx_txx_append_s cn52xxp1;
788 struct cvmx_agl_gmx_txx_append_s cn56xx;
789 struct cvmx_agl_gmx_txx_append_s cn56xxp1;
790};
791
792union cvmx_agl_gmx_txx_ctl {
793 uint64_t u64;
794 struct cvmx_agl_gmx_txx_ctl_s {
795 uint64_t reserved_2_63:62;
796 uint64_t xsdef_en:1;
797 uint64_t xscol_en:1;
798 } s;
799 struct cvmx_agl_gmx_txx_ctl_s cn52xx;
800 struct cvmx_agl_gmx_txx_ctl_s cn52xxp1;
801 struct cvmx_agl_gmx_txx_ctl_s cn56xx;
802 struct cvmx_agl_gmx_txx_ctl_s cn56xxp1;
803};
804
805union cvmx_agl_gmx_txx_min_pkt {
806 uint64_t u64;
807 struct cvmx_agl_gmx_txx_min_pkt_s {
808 uint64_t reserved_8_63:56;
809 uint64_t min_size:8;
810 } s;
811 struct cvmx_agl_gmx_txx_min_pkt_s cn52xx;
812 struct cvmx_agl_gmx_txx_min_pkt_s cn52xxp1;
813 struct cvmx_agl_gmx_txx_min_pkt_s cn56xx;
814 struct cvmx_agl_gmx_txx_min_pkt_s cn56xxp1;
815};
816
817union cvmx_agl_gmx_txx_pause_pkt_interval {
818 uint64_t u64;
819 struct cvmx_agl_gmx_txx_pause_pkt_interval_s {
820 uint64_t reserved_16_63:48;
821 uint64_t interval:16;
822 } s;
823 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xx;
824 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1;
825 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx;
826 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1;
827};
828
829union cvmx_agl_gmx_txx_pause_pkt_time {
830 uint64_t u64;
831 struct cvmx_agl_gmx_txx_pause_pkt_time_s {
832 uint64_t reserved_16_63:48;
833 uint64_t time:16;
834 } s;
835 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xx;
836 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1;
837 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx;
838 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1;
839};
840
841union cvmx_agl_gmx_txx_pause_togo {
842 uint64_t u64;
843 struct cvmx_agl_gmx_txx_pause_togo_s {
844 uint64_t reserved_16_63:48;
845 uint64_t time:16;
846 } s;
847 struct cvmx_agl_gmx_txx_pause_togo_s cn52xx;
848 struct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1;
849 struct cvmx_agl_gmx_txx_pause_togo_s cn56xx;
850 struct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1;
851};
852
853union cvmx_agl_gmx_txx_pause_zero {
854 uint64_t u64;
855 struct cvmx_agl_gmx_txx_pause_zero_s {
856 uint64_t reserved_1_63:63;
857 uint64_t send:1;
858 } s;
859 struct cvmx_agl_gmx_txx_pause_zero_s cn52xx;
860 struct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1;
861 struct cvmx_agl_gmx_txx_pause_zero_s cn56xx;
862 struct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1;
863};
864
865union cvmx_agl_gmx_txx_soft_pause {
866 uint64_t u64;
867 struct cvmx_agl_gmx_txx_soft_pause_s {
868 uint64_t reserved_16_63:48;
869 uint64_t time:16;
870 } s;
871 struct cvmx_agl_gmx_txx_soft_pause_s cn52xx;
872 struct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1;
873 struct cvmx_agl_gmx_txx_soft_pause_s cn56xx;
874 struct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1;
875};
876
877union cvmx_agl_gmx_txx_stat0 {
878 uint64_t u64;
879 struct cvmx_agl_gmx_txx_stat0_s {
880 uint64_t xsdef:32;
881 uint64_t xscol:32;
882 } s;
883 struct cvmx_agl_gmx_txx_stat0_s cn52xx;
884 struct cvmx_agl_gmx_txx_stat0_s cn52xxp1;
885 struct cvmx_agl_gmx_txx_stat0_s cn56xx;
886 struct cvmx_agl_gmx_txx_stat0_s cn56xxp1;
887};
888
889union cvmx_agl_gmx_txx_stat1 {
890 uint64_t u64;
891 struct cvmx_agl_gmx_txx_stat1_s {
892 uint64_t scol:32;
893 uint64_t mcol:32;
894 } s;
895 struct cvmx_agl_gmx_txx_stat1_s cn52xx;
896 struct cvmx_agl_gmx_txx_stat1_s cn52xxp1;
897 struct cvmx_agl_gmx_txx_stat1_s cn56xx;
898 struct cvmx_agl_gmx_txx_stat1_s cn56xxp1;
899};
900
901union cvmx_agl_gmx_txx_stat2 {
902 uint64_t u64;
903 struct cvmx_agl_gmx_txx_stat2_s {
904 uint64_t reserved_48_63:16;
905 uint64_t octs:48;
906 } s;
907 struct cvmx_agl_gmx_txx_stat2_s cn52xx;
908 struct cvmx_agl_gmx_txx_stat2_s cn52xxp1;
909 struct cvmx_agl_gmx_txx_stat2_s cn56xx;
910 struct cvmx_agl_gmx_txx_stat2_s cn56xxp1;
911};
912
913union cvmx_agl_gmx_txx_stat3 {
914 uint64_t u64;
915 struct cvmx_agl_gmx_txx_stat3_s {
916 uint64_t reserved_32_63:32;
917 uint64_t pkts:32;
918 } s;
919 struct cvmx_agl_gmx_txx_stat3_s cn52xx;
920 struct cvmx_agl_gmx_txx_stat3_s cn52xxp1;
921 struct cvmx_agl_gmx_txx_stat3_s cn56xx;
922 struct cvmx_agl_gmx_txx_stat3_s cn56xxp1;
923};
924
925union cvmx_agl_gmx_txx_stat4 {
926 uint64_t u64;
927 struct cvmx_agl_gmx_txx_stat4_s {
928 uint64_t hist1:32;
929 uint64_t hist0:32;
930 } s;
931 struct cvmx_agl_gmx_txx_stat4_s cn52xx;
932 struct cvmx_agl_gmx_txx_stat4_s cn52xxp1;
933 struct cvmx_agl_gmx_txx_stat4_s cn56xx;
934 struct cvmx_agl_gmx_txx_stat4_s cn56xxp1;
935};
936
937union cvmx_agl_gmx_txx_stat5 {
938 uint64_t u64;
939 struct cvmx_agl_gmx_txx_stat5_s {
940 uint64_t hist3:32;
941 uint64_t hist2:32;
942 } s;
943 struct cvmx_agl_gmx_txx_stat5_s cn52xx;
944 struct cvmx_agl_gmx_txx_stat5_s cn52xxp1;
945 struct cvmx_agl_gmx_txx_stat5_s cn56xx;
946 struct cvmx_agl_gmx_txx_stat5_s cn56xxp1;
947};
948
949union cvmx_agl_gmx_txx_stat6 {
950 uint64_t u64;
951 struct cvmx_agl_gmx_txx_stat6_s {
952 uint64_t hist5:32;
953 uint64_t hist4:32;
954 } s;
955 struct cvmx_agl_gmx_txx_stat6_s cn52xx;
956 struct cvmx_agl_gmx_txx_stat6_s cn52xxp1;
957 struct cvmx_agl_gmx_txx_stat6_s cn56xx;
958 struct cvmx_agl_gmx_txx_stat6_s cn56xxp1;
959};
960
961union cvmx_agl_gmx_txx_stat7 {
962 uint64_t u64;
963 struct cvmx_agl_gmx_txx_stat7_s {
964 uint64_t hist7:32;
965 uint64_t hist6:32;
966 } s;
967 struct cvmx_agl_gmx_txx_stat7_s cn52xx;
968 struct cvmx_agl_gmx_txx_stat7_s cn52xxp1;
969 struct cvmx_agl_gmx_txx_stat7_s cn56xx;
970 struct cvmx_agl_gmx_txx_stat7_s cn56xxp1;
971};
972
973union cvmx_agl_gmx_txx_stat8 {
974 uint64_t u64;
975 struct cvmx_agl_gmx_txx_stat8_s {
976 uint64_t mcst:32;
977 uint64_t bcst:32;
978 } s;
979 struct cvmx_agl_gmx_txx_stat8_s cn52xx;
980 struct cvmx_agl_gmx_txx_stat8_s cn52xxp1;
981 struct cvmx_agl_gmx_txx_stat8_s cn56xx;
982 struct cvmx_agl_gmx_txx_stat8_s cn56xxp1;
983};
984
985union cvmx_agl_gmx_txx_stat9 {
986 uint64_t u64;
987 struct cvmx_agl_gmx_txx_stat9_s {
988 uint64_t undflw:32;
989 uint64_t ctl:32;
990 } s;
991 struct cvmx_agl_gmx_txx_stat9_s cn52xx;
992 struct cvmx_agl_gmx_txx_stat9_s cn52xxp1;
993 struct cvmx_agl_gmx_txx_stat9_s cn56xx;
994 struct cvmx_agl_gmx_txx_stat9_s cn56xxp1;
995};
996
997union cvmx_agl_gmx_txx_stats_ctl {
998 uint64_t u64;
999 struct cvmx_agl_gmx_txx_stats_ctl_s {
1000 uint64_t reserved_1_63:63;
1001 uint64_t rd_clr:1;
1002 } s;
1003 struct cvmx_agl_gmx_txx_stats_ctl_s cn52xx;
1004 struct cvmx_agl_gmx_txx_stats_ctl_s cn52xxp1;
1005 struct cvmx_agl_gmx_txx_stats_ctl_s cn56xx;
1006 struct cvmx_agl_gmx_txx_stats_ctl_s cn56xxp1;
1007};
1008
1009union cvmx_agl_gmx_txx_thresh {
1010 uint64_t u64;
1011 struct cvmx_agl_gmx_txx_thresh_s {
1012 uint64_t reserved_6_63:58;
1013 uint64_t cnt:6;
1014 } s;
1015 struct cvmx_agl_gmx_txx_thresh_s cn52xx;
1016 struct cvmx_agl_gmx_txx_thresh_s cn52xxp1;
1017 struct cvmx_agl_gmx_txx_thresh_s cn56xx;
1018 struct cvmx_agl_gmx_txx_thresh_s cn56xxp1;
1019};
1020
1021union cvmx_agl_gmx_tx_bp {
1022 uint64_t u64;
1023 struct cvmx_agl_gmx_tx_bp_s {
1024 uint64_t reserved_2_63:62;
1025 uint64_t bp:2;
1026 } s;
1027 struct cvmx_agl_gmx_tx_bp_s cn52xx;
1028 struct cvmx_agl_gmx_tx_bp_s cn52xxp1;
1029 struct cvmx_agl_gmx_tx_bp_cn56xx {
1030 uint64_t reserved_1_63:63;
1031 uint64_t bp:1;
1032 } cn56xx;
1033 struct cvmx_agl_gmx_tx_bp_cn56xx cn56xxp1;
1034};
1035
1036union cvmx_agl_gmx_tx_col_attempt {
1037 uint64_t u64;
1038 struct cvmx_agl_gmx_tx_col_attempt_s {
1039 uint64_t reserved_5_63:59;
1040 uint64_t limit:5;
1041 } s;
1042 struct cvmx_agl_gmx_tx_col_attempt_s cn52xx;
1043 struct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1;
1044 struct cvmx_agl_gmx_tx_col_attempt_s cn56xx;
1045 struct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1;
1046};
1047
1048union cvmx_agl_gmx_tx_ifg {
1049 uint64_t u64;
1050 struct cvmx_agl_gmx_tx_ifg_s {
1051 uint64_t reserved_8_63:56;
1052 uint64_t ifg2:4;
1053 uint64_t ifg1:4;
1054 } s;
1055 struct cvmx_agl_gmx_tx_ifg_s cn52xx;
1056 struct cvmx_agl_gmx_tx_ifg_s cn52xxp1;
1057 struct cvmx_agl_gmx_tx_ifg_s cn56xx;
1058 struct cvmx_agl_gmx_tx_ifg_s cn56xxp1;
1059};
1060
1061union cvmx_agl_gmx_tx_int_en {
1062 uint64_t u64;
1063 struct cvmx_agl_gmx_tx_int_en_s {
1064 uint64_t reserved_18_63:46;
1065 uint64_t late_col:2;
1066 uint64_t reserved_14_15:2;
1067 uint64_t xsdef:2;
1068 uint64_t reserved_10_11:2;
1069 uint64_t xscol:2;
1070 uint64_t reserved_4_7:4;
1071 uint64_t undflw:2;
1072 uint64_t reserved_1_1:1;
1073 uint64_t pko_nxa:1;
1074 } s;
1075 struct cvmx_agl_gmx_tx_int_en_s cn52xx;
1076 struct cvmx_agl_gmx_tx_int_en_s cn52xxp1;
1077 struct cvmx_agl_gmx_tx_int_en_cn56xx {
1078 uint64_t reserved_17_63:47;
1079 uint64_t late_col:1;
1080 uint64_t reserved_13_15:3;
1081 uint64_t xsdef:1;
1082 uint64_t reserved_9_11:3;
1083 uint64_t xscol:1;
1084 uint64_t reserved_3_7:5;
1085 uint64_t undflw:1;
1086 uint64_t reserved_1_1:1;
1087 uint64_t pko_nxa:1;
1088 } cn56xx;
1089 struct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1;
1090};
1091
1092union cvmx_agl_gmx_tx_int_reg {
1093 uint64_t u64;
1094 struct cvmx_agl_gmx_tx_int_reg_s {
1095 uint64_t reserved_18_63:46;
1096 uint64_t late_col:2;
1097 uint64_t reserved_14_15:2;
1098 uint64_t xsdef:2;
1099 uint64_t reserved_10_11:2;
1100 uint64_t xscol:2;
1101 uint64_t reserved_4_7:4;
1102 uint64_t undflw:2;
1103 uint64_t reserved_1_1:1;
1104 uint64_t pko_nxa:1;
1105 } s;
1106 struct cvmx_agl_gmx_tx_int_reg_s cn52xx;
1107 struct cvmx_agl_gmx_tx_int_reg_s cn52xxp1;
1108 struct cvmx_agl_gmx_tx_int_reg_cn56xx {
1109 uint64_t reserved_17_63:47;
1110 uint64_t late_col:1;
1111 uint64_t reserved_13_15:3;
1112 uint64_t xsdef:1;
1113 uint64_t reserved_9_11:3;
1114 uint64_t xscol:1;
1115 uint64_t reserved_3_7:5;
1116 uint64_t undflw:1;
1117 uint64_t reserved_1_1:1;
1118 uint64_t pko_nxa:1;
1119 } cn56xx;
1120 struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1;
1121};
1122
1123union cvmx_agl_gmx_tx_jam {
1124 uint64_t u64;
1125 struct cvmx_agl_gmx_tx_jam_s {
1126 uint64_t reserved_8_63:56;
1127 uint64_t jam:8;
1128 } s;
1129 struct cvmx_agl_gmx_tx_jam_s cn52xx;
1130 struct cvmx_agl_gmx_tx_jam_s cn52xxp1;
1131 struct cvmx_agl_gmx_tx_jam_s cn56xx;
1132 struct cvmx_agl_gmx_tx_jam_s cn56xxp1;
1133};
1134
1135union cvmx_agl_gmx_tx_lfsr {
1136 uint64_t u64;
1137 struct cvmx_agl_gmx_tx_lfsr_s {
1138 uint64_t reserved_16_63:48;
1139 uint64_t lfsr:16;
1140 } s;
1141 struct cvmx_agl_gmx_tx_lfsr_s cn52xx;
1142 struct cvmx_agl_gmx_tx_lfsr_s cn52xxp1;
1143 struct cvmx_agl_gmx_tx_lfsr_s cn56xx;
1144 struct cvmx_agl_gmx_tx_lfsr_s cn56xxp1;
1145};
1146
1147union cvmx_agl_gmx_tx_ovr_bp {
1148 uint64_t u64;
1149 struct cvmx_agl_gmx_tx_ovr_bp_s {
1150 uint64_t reserved_10_63:54;
1151 uint64_t en:2;
1152 uint64_t reserved_6_7:2;
1153 uint64_t bp:2;
1154 uint64_t reserved_2_3:2;
1155 uint64_t ign_full:2;
1156 } s;
1157 struct cvmx_agl_gmx_tx_ovr_bp_s cn52xx;
1158 struct cvmx_agl_gmx_tx_ovr_bp_s cn52xxp1;
1159 struct cvmx_agl_gmx_tx_ovr_bp_cn56xx {
1160 uint64_t reserved_9_63:55;
1161 uint64_t en:1;
1162 uint64_t reserved_5_7:3;
1163 uint64_t bp:1;
1164 uint64_t reserved_1_3:3;
1165 uint64_t ign_full:1;
1166 } cn56xx;
1167 struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1;
1168};
1169
1170union cvmx_agl_gmx_tx_pause_pkt_dmac {
1171 uint64_t u64;
1172 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s {
1173 uint64_t reserved_48_63:16;
1174 uint64_t dmac:48;
1175 } s;
1176 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xx;
1177 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1;
1178 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx;
1179 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1;
1180};
1181
1182union cvmx_agl_gmx_tx_pause_pkt_type {
1183 uint64_t u64;
1184 struct cvmx_agl_gmx_tx_pause_pkt_type_s {
1185 uint64_t reserved_16_63:48;
1186 uint64_t type:16;
1187 } s;
1188 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xx;
1189 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1;
1190 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx;
1191 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1;
1192};
1193
1194#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-mixx-defs.h b/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
new file mode 100644
index 000000000000..dab6dca492f9
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
@@ -0,0 +1,248 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_MIXX_DEFS_H__
29#define __CVMX_MIXX_DEFS_H__
30
31#define CVMX_MIXX_BIST(offset) \
32 CVMX_ADD_IO_SEG(0x0001070000100078ull + (((offset) & 1) * 2048))
33#define CVMX_MIXX_CTL(offset) \
34 CVMX_ADD_IO_SEG(0x0001070000100020ull + (((offset) & 1) * 2048))
35#define CVMX_MIXX_INTENA(offset) \
36 CVMX_ADD_IO_SEG(0x0001070000100050ull + (((offset) & 1) * 2048))
37#define CVMX_MIXX_IRCNT(offset) \
38 CVMX_ADD_IO_SEG(0x0001070000100030ull + (((offset) & 1) * 2048))
39#define CVMX_MIXX_IRHWM(offset) \
40 CVMX_ADD_IO_SEG(0x0001070000100028ull + (((offset) & 1) * 2048))
41#define CVMX_MIXX_IRING1(offset) \
42 CVMX_ADD_IO_SEG(0x0001070000100010ull + (((offset) & 1) * 2048))
43#define CVMX_MIXX_IRING2(offset) \
44 CVMX_ADD_IO_SEG(0x0001070000100018ull + (((offset) & 1) * 2048))
45#define CVMX_MIXX_ISR(offset) \
46 CVMX_ADD_IO_SEG(0x0001070000100048ull + (((offset) & 1) * 2048))
47#define CVMX_MIXX_ORCNT(offset) \
48 CVMX_ADD_IO_SEG(0x0001070000100040ull + (((offset) & 1) * 2048))
49#define CVMX_MIXX_ORHWM(offset) \
50 CVMX_ADD_IO_SEG(0x0001070000100038ull + (((offset) & 1) * 2048))
51#define CVMX_MIXX_ORING1(offset) \
52 CVMX_ADD_IO_SEG(0x0001070000100000ull + (((offset) & 1) * 2048))
53#define CVMX_MIXX_ORING2(offset) \
54 CVMX_ADD_IO_SEG(0x0001070000100008ull + (((offset) & 1) * 2048))
55#define CVMX_MIXX_REMCNT(offset) \
56 CVMX_ADD_IO_SEG(0x0001070000100058ull + (((offset) & 1) * 2048))
57
58union cvmx_mixx_bist {
59 uint64_t u64;
60 struct cvmx_mixx_bist_s {
61 uint64_t reserved_4_63:60;
62 uint64_t mrqdat:1;
63 uint64_t ipfdat:1;
64 uint64_t irfdat:1;
65 uint64_t orfdat:1;
66 } s;
67 struct cvmx_mixx_bist_s cn52xx;
68 struct cvmx_mixx_bist_s cn52xxp1;
69 struct cvmx_mixx_bist_s cn56xx;
70 struct cvmx_mixx_bist_s cn56xxp1;
71};
72
73union cvmx_mixx_ctl {
74 uint64_t u64;
75 struct cvmx_mixx_ctl_s {
76 uint64_t reserved_8_63:56;
77 uint64_t crc_strip:1;
78 uint64_t busy:1;
79 uint64_t en:1;
80 uint64_t reset:1;
81 uint64_t lendian:1;
82 uint64_t nbtarb:1;
83 uint64_t mrq_hwm:2;
84 } s;
85 struct cvmx_mixx_ctl_s cn52xx;
86 struct cvmx_mixx_ctl_s cn52xxp1;
87 struct cvmx_mixx_ctl_s cn56xx;
88 struct cvmx_mixx_ctl_s cn56xxp1;
89};
90
91union cvmx_mixx_intena {
92 uint64_t u64;
93 struct cvmx_mixx_intena_s {
94 uint64_t reserved_7_63:57;
95 uint64_t orunena:1;
96 uint64_t irunena:1;
97 uint64_t data_drpena:1;
98 uint64_t ithena:1;
99 uint64_t othena:1;
100 uint64_t ivfena:1;
101 uint64_t ovfena:1;
102 } s;
103 struct cvmx_mixx_intena_s cn52xx;
104 struct cvmx_mixx_intena_s cn52xxp1;
105 struct cvmx_mixx_intena_s cn56xx;
106 struct cvmx_mixx_intena_s cn56xxp1;
107};
108
109union cvmx_mixx_ircnt {
110 uint64_t u64;
111 struct cvmx_mixx_ircnt_s {
112 uint64_t reserved_20_63:44;
113 uint64_t ircnt:20;
114 } s;
115 struct cvmx_mixx_ircnt_s cn52xx;
116 struct cvmx_mixx_ircnt_s cn52xxp1;
117 struct cvmx_mixx_ircnt_s cn56xx;
118 struct cvmx_mixx_ircnt_s cn56xxp1;
119};
120
121union cvmx_mixx_irhwm {
122 uint64_t u64;
123 struct cvmx_mixx_irhwm_s {
124 uint64_t reserved_40_63:24;
125 uint64_t ibplwm:20;
126 uint64_t irhwm:20;
127 } s;
128 struct cvmx_mixx_irhwm_s cn52xx;
129 struct cvmx_mixx_irhwm_s cn52xxp1;
130 struct cvmx_mixx_irhwm_s cn56xx;
131 struct cvmx_mixx_irhwm_s cn56xxp1;
132};
133
134union cvmx_mixx_iring1 {
135 uint64_t u64;
136 struct cvmx_mixx_iring1_s {
137 uint64_t reserved_60_63:4;
138 uint64_t isize:20;
139 uint64_t reserved_36_39:4;
140 uint64_t ibase:33;
141 uint64_t reserved_0_2:3;
142 } s;
143 struct cvmx_mixx_iring1_s cn52xx;
144 struct cvmx_mixx_iring1_s cn52xxp1;
145 struct cvmx_mixx_iring1_s cn56xx;
146 struct cvmx_mixx_iring1_s cn56xxp1;
147};
148
149union cvmx_mixx_iring2 {
150 uint64_t u64;
151 struct cvmx_mixx_iring2_s {
152 uint64_t reserved_52_63:12;
153 uint64_t itlptr:20;
154 uint64_t reserved_20_31:12;
155 uint64_t idbell:20;
156 } s;
157 struct cvmx_mixx_iring2_s cn52xx;
158 struct cvmx_mixx_iring2_s cn52xxp1;
159 struct cvmx_mixx_iring2_s cn56xx;
160 struct cvmx_mixx_iring2_s cn56xxp1;
161};
162
163union cvmx_mixx_isr {
164 uint64_t u64;
165 struct cvmx_mixx_isr_s {
166 uint64_t reserved_7_63:57;
167 uint64_t orun:1;
168 uint64_t irun:1;
169 uint64_t data_drp:1;
170 uint64_t irthresh:1;
171 uint64_t orthresh:1;
172 uint64_t idblovf:1;
173 uint64_t odblovf:1;
174 } s;
175 struct cvmx_mixx_isr_s cn52xx;
176 struct cvmx_mixx_isr_s cn52xxp1;
177 struct cvmx_mixx_isr_s cn56xx;
178 struct cvmx_mixx_isr_s cn56xxp1;
179};
180
181union cvmx_mixx_orcnt {
182 uint64_t u64;
183 struct cvmx_mixx_orcnt_s {
184 uint64_t reserved_20_63:44;
185 uint64_t orcnt:20;
186 } s;
187 struct cvmx_mixx_orcnt_s cn52xx;
188 struct cvmx_mixx_orcnt_s cn52xxp1;
189 struct cvmx_mixx_orcnt_s cn56xx;
190 struct cvmx_mixx_orcnt_s cn56xxp1;
191};
192
193union cvmx_mixx_orhwm {
194 uint64_t u64;
195 struct cvmx_mixx_orhwm_s {
196 uint64_t reserved_20_63:44;
197 uint64_t orhwm:20;
198 } s;
199 struct cvmx_mixx_orhwm_s cn52xx;
200 struct cvmx_mixx_orhwm_s cn52xxp1;
201 struct cvmx_mixx_orhwm_s cn56xx;
202 struct cvmx_mixx_orhwm_s cn56xxp1;
203};
204
205union cvmx_mixx_oring1 {
206 uint64_t u64;
207 struct cvmx_mixx_oring1_s {
208 uint64_t reserved_60_63:4;
209 uint64_t osize:20;
210 uint64_t reserved_36_39:4;
211 uint64_t obase:33;
212 uint64_t reserved_0_2:3;
213 } s;
214 struct cvmx_mixx_oring1_s cn52xx;
215 struct cvmx_mixx_oring1_s cn52xxp1;
216 struct cvmx_mixx_oring1_s cn56xx;
217 struct cvmx_mixx_oring1_s cn56xxp1;
218};
219
220union cvmx_mixx_oring2 {
221 uint64_t u64;
222 struct cvmx_mixx_oring2_s {
223 uint64_t reserved_52_63:12;
224 uint64_t otlptr:20;
225 uint64_t reserved_20_31:12;
226 uint64_t odbell:20;
227 } s;
228 struct cvmx_mixx_oring2_s cn52xx;
229 struct cvmx_mixx_oring2_s cn52xxp1;
230 struct cvmx_mixx_oring2_s cn56xx;
231 struct cvmx_mixx_oring2_s cn56xxp1;
232};
233
234union cvmx_mixx_remcnt {
235 uint64_t u64;
236 struct cvmx_mixx_remcnt_s {
237 uint64_t reserved_52_63:12;
238 uint64_t iremcnt:20;
239 uint64_t reserved_20_31:12;
240 uint64_t oremcnt:20;
241 } s;
242 struct cvmx_mixx_remcnt_s cn52xx;
243 struct cvmx_mixx_remcnt_s cn52xxp1;
244 struct cvmx_mixx_remcnt_s cn56xx;
245 struct cvmx_mixx_remcnt_s cn56xxp1;
246};
247
248#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-smix-defs.h b/arch/mips/include/asm/octeon/cvmx-smix-defs.h
new file mode 100644
index 000000000000..9ae45fcbe3e3
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-smix-defs.h
@@ -0,0 +1,178 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_SMIX_DEFS_H__
29#define __CVMX_SMIX_DEFS_H__
30
31#define CVMX_SMIX_CLK(offset) \
32 CVMX_ADD_IO_SEG(0x0001180000001818ull + (((offset) & 1) * 256))
33#define CVMX_SMIX_CMD(offset) \
34 CVMX_ADD_IO_SEG(0x0001180000001800ull + (((offset) & 1) * 256))
35#define CVMX_SMIX_EN(offset) \
36 CVMX_ADD_IO_SEG(0x0001180000001820ull + (((offset) & 1) * 256))
37#define CVMX_SMIX_RD_DAT(offset) \
38 CVMX_ADD_IO_SEG(0x0001180000001810ull + (((offset) & 1) * 256))
39#define CVMX_SMIX_WR_DAT(offset) \
40 CVMX_ADD_IO_SEG(0x0001180000001808ull + (((offset) & 1) * 256))
41
42union cvmx_smix_clk {
43 uint64_t u64;
44 struct cvmx_smix_clk_s {
45 uint64_t reserved_25_63:39;
46 uint64_t mode:1;
47 uint64_t reserved_21_23:3;
48 uint64_t sample_hi:5;
49 uint64_t sample_mode:1;
50 uint64_t reserved_14_14:1;
51 uint64_t clk_idle:1;
52 uint64_t preamble:1;
53 uint64_t sample:4;
54 uint64_t phase:8;
55 } s;
56 struct cvmx_smix_clk_cn30xx {
57 uint64_t reserved_21_63:43;
58 uint64_t sample_hi:5;
59 uint64_t reserved_14_15:2;
60 uint64_t clk_idle:1;
61 uint64_t preamble:1;
62 uint64_t sample:4;
63 uint64_t phase:8;
64 } cn30xx;
65 struct cvmx_smix_clk_cn30xx cn31xx;
66 struct cvmx_smix_clk_cn30xx cn38xx;
67 struct cvmx_smix_clk_cn30xx cn38xxp2;
68 struct cvmx_smix_clk_cn50xx {
69 uint64_t reserved_25_63:39;
70 uint64_t mode:1;
71 uint64_t reserved_21_23:3;
72 uint64_t sample_hi:5;
73 uint64_t reserved_14_15:2;
74 uint64_t clk_idle:1;
75 uint64_t preamble:1;
76 uint64_t sample:4;
77 uint64_t phase:8;
78 } cn50xx;
79 struct cvmx_smix_clk_s cn52xx;
80 struct cvmx_smix_clk_cn50xx cn52xxp1;
81 struct cvmx_smix_clk_s cn56xx;
82 struct cvmx_smix_clk_cn50xx cn56xxp1;
83 struct cvmx_smix_clk_cn30xx cn58xx;
84 struct cvmx_smix_clk_cn30xx cn58xxp1;
85};
86
87union cvmx_smix_cmd {
88 uint64_t u64;
89 struct cvmx_smix_cmd_s {
90 uint64_t reserved_18_63:46;
91 uint64_t phy_op:2;
92 uint64_t reserved_13_15:3;
93 uint64_t phy_adr:5;
94 uint64_t reserved_5_7:3;
95 uint64_t reg_adr:5;
96 } s;
97 struct cvmx_smix_cmd_cn30xx {
98 uint64_t reserved_17_63:47;
99 uint64_t phy_op:1;
100 uint64_t reserved_13_15:3;
101 uint64_t phy_adr:5;
102 uint64_t reserved_5_7:3;
103 uint64_t reg_adr:5;
104 } cn30xx;
105 struct cvmx_smix_cmd_cn30xx cn31xx;
106 struct cvmx_smix_cmd_cn30xx cn38xx;
107 struct cvmx_smix_cmd_cn30xx cn38xxp2;
108 struct cvmx_smix_cmd_s cn50xx;
109 struct cvmx_smix_cmd_s cn52xx;
110 struct cvmx_smix_cmd_s cn52xxp1;
111 struct cvmx_smix_cmd_s cn56xx;
112 struct cvmx_smix_cmd_s cn56xxp1;
113 struct cvmx_smix_cmd_cn30xx cn58xx;
114 struct cvmx_smix_cmd_cn30xx cn58xxp1;
115};
116
117union cvmx_smix_en {
118 uint64_t u64;
119 struct cvmx_smix_en_s {
120 uint64_t reserved_1_63:63;
121 uint64_t en:1;
122 } s;
123 struct cvmx_smix_en_s cn30xx;
124 struct cvmx_smix_en_s cn31xx;
125 struct cvmx_smix_en_s cn38xx;
126 struct cvmx_smix_en_s cn38xxp2;
127 struct cvmx_smix_en_s cn50xx;
128 struct cvmx_smix_en_s cn52xx;
129 struct cvmx_smix_en_s cn52xxp1;
130 struct cvmx_smix_en_s cn56xx;
131 struct cvmx_smix_en_s cn56xxp1;
132 struct cvmx_smix_en_s cn58xx;
133 struct cvmx_smix_en_s cn58xxp1;
134};
135
136union cvmx_smix_rd_dat {
137 uint64_t u64;
138 struct cvmx_smix_rd_dat_s {
139 uint64_t reserved_18_63:46;
140 uint64_t pending:1;
141 uint64_t val:1;
142 uint64_t dat:16;
143 } s;
144 struct cvmx_smix_rd_dat_s cn30xx;
145 struct cvmx_smix_rd_dat_s cn31xx;
146 struct cvmx_smix_rd_dat_s cn38xx;
147 struct cvmx_smix_rd_dat_s cn38xxp2;
148 struct cvmx_smix_rd_dat_s cn50xx;
149 struct cvmx_smix_rd_dat_s cn52xx;
150 struct cvmx_smix_rd_dat_s cn52xxp1;
151 struct cvmx_smix_rd_dat_s cn56xx;
152 struct cvmx_smix_rd_dat_s cn56xxp1;
153 struct cvmx_smix_rd_dat_s cn58xx;
154 struct cvmx_smix_rd_dat_s cn58xxp1;
155};
156
157union cvmx_smix_wr_dat {
158 uint64_t u64;
159 struct cvmx_smix_wr_dat_s {
160 uint64_t reserved_18_63:46;
161 uint64_t pending:1;
162 uint64_t val:1;
163 uint64_t dat:16;
164 } s;
165 struct cvmx_smix_wr_dat_s cn30xx;
166 struct cvmx_smix_wr_dat_s cn31xx;
167 struct cvmx_smix_wr_dat_s cn38xx;
168 struct cvmx_smix_wr_dat_s cn38xxp2;
169 struct cvmx_smix_wr_dat_s cn50xx;
170 struct cvmx_smix_wr_dat_s cn52xx;
171 struct cvmx_smix_wr_dat_s cn52xxp1;
172 struct cvmx_smix_wr_dat_s cn56xx;
173 struct cvmx_smix_wr_dat_s cn56xxp1;
174 struct cvmx_smix_wr_dat_s cn58xx;
175 struct cvmx_smix_wr_dat_s cn58xxp1;
176};
177
178#endif
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index cac9b1a206fc..4d0a8c61fc3e 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -47,6 +47,7 @@ struct octeon_cop2_state;
47extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state); 47extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state);
48extern void octeon_crypto_disable(struct octeon_cop2_state *state, 48extern void octeon_crypto_disable(struct octeon_cop2_state *state,
49 unsigned long flags); 49 unsigned long flags);
50extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task);
50 51
51extern void octeon_init_cvmcount(void); 52extern void octeon_init_cvmcount(void);
52 53
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index d6eb6134abec..1854336e56a2 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -390,6 +390,19 @@ static inline int io_remap_pfn_range(struct vm_area_struct *vma,
390#include <asm-generic/pgtable.h> 390#include <asm-generic/pgtable.h>
391 391
392/* 392/*
393 * uncached accelerated TLB map for video memory access
394 */
395#ifdef CONFIG_CPU_SUPPORTS_UNCACHED_ACCELERATED
396#define __HAVE_PHYS_MEM_ACCESS_PROT
397
398struct file;
399pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
400 unsigned long size, pgprot_t vma_prot);
401int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn,
402 unsigned long size, pgprot_t *vma_prot);
403#endif
404
405/*
393 * We provide our own get_unmapped area to cope with the virtual aliasing 406 * We provide our own get_unmapped area to cope with the virtual aliasing
394 * constraints placed on us by the cache architecture. 407 * constraints placed on us by the cache architecture.
395 */ 408 */
diff --git a/arch/mips/include/asm/sgialib.h b/arch/mips/include/asm/sgialib.h
index bfce5c786f1c..63741ca1e422 100644
--- a/arch/mips/include/asm/sgialib.h
+++ b/arch/mips/include/asm/sgialib.h
@@ -85,8 +85,7 @@ extern void prom_identify_arch(void);
85extern PCHAR ArcGetEnvironmentVariable(PCHAR name); 85extern PCHAR ArcGetEnvironmentVariable(PCHAR name);
86extern LONG ArcSetEnvironmentVariable(PCHAR name, PCHAR value); 86extern LONG ArcSetEnvironmentVariable(PCHAR name, PCHAR value);
87 87
88/* ARCS command line acquisition and parsing. */ 88/* ARCS command line parsing. */
89extern char *prom_getcmdline(void);
90extern void prom_init_cmdline(void); 89extern void prom_init_cmdline(void);
91 90
92/* Acquiring info about the current time, etc. */ 91/* Acquiring info about the current time, etc. */
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index db0fa7b5aeaf..3b6da3330e32 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -51,9 +51,6 @@
51 LONG_S v1, PT_ACX(sp) 51 LONG_S v1, PT_ACX(sp)
52#else 52#else
53 mfhi v1 53 mfhi v1
54 LONG_S v1, PT_HI(sp)
55 mflo v1
56 LONG_S v1, PT_LO(sp)
57#endif 54#endif
58#ifdef CONFIG_32BIT 55#ifdef CONFIG_32BIT
59 LONG_S $8, PT_R8(sp) 56 LONG_S $8, PT_R8(sp)
@@ -62,10 +59,17 @@
62 LONG_S $10, PT_R10(sp) 59 LONG_S $10, PT_R10(sp)
63 LONG_S $11, PT_R11(sp) 60 LONG_S $11, PT_R11(sp)
64 LONG_S $12, PT_R12(sp) 61 LONG_S $12, PT_R12(sp)
62#ifndef CONFIG_CPU_HAS_SMARTMIPS
63 LONG_S v1, PT_HI(sp)
64 mflo v1
65#endif
65 LONG_S $13, PT_R13(sp) 66 LONG_S $13, PT_R13(sp)
66 LONG_S $14, PT_R14(sp) 67 LONG_S $14, PT_R14(sp)
67 LONG_S $15, PT_R15(sp) 68 LONG_S $15, PT_R15(sp)
68 LONG_S $24, PT_R24(sp) 69 LONG_S $24, PT_R24(sp)
70#ifndef CONFIG_CPU_HAS_SMARTMIPS
71 LONG_S v1, PT_LO(sp)
72#endif
69 .endm 73 .endm
70 74
71 .macro SAVE_STATIC 75 .macro SAVE_STATIC
@@ -83,15 +87,19 @@
83#ifdef CONFIG_SMP 87#ifdef CONFIG_SMP
84#ifdef CONFIG_MIPS_MT_SMTC 88#ifdef CONFIG_MIPS_MT_SMTC
85#define PTEBASE_SHIFT 19 /* TCBIND */ 89#define PTEBASE_SHIFT 19 /* TCBIND */
90#define CPU_ID_REG CP0_TCBIND
91#define CPU_ID_MFC0 mfc0
92#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT)
93#define PTEBASE_SHIFT 48 /* XCONTEXT */
94#define CPU_ID_REG CP0_XCONTEXT
95#define CPU_ID_MFC0 MFC0
86#else 96#else
87#define PTEBASE_SHIFT 23 /* CONTEXT */ 97#define PTEBASE_SHIFT 23 /* CONTEXT */
98#define CPU_ID_REG CP0_CONTEXT
99#define CPU_ID_MFC0 MFC0
88#endif 100#endif
89 .macro get_saved_sp /* SMP variation */ 101 .macro get_saved_sp /* SMP variation */
90#ifdef CONFIG_MIPS_MT_SMTC 102 CPU_ID_MFC0 k0, CPU_ID_REG
91 mfc0 k0, CP0_TCBIND
92#else
93 MFC0 k0, CP0_CONTEXT
94#endif
95#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) 103#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
96 lui k1, %hi(kernelsp) 104 lui k1, %hi(kernelsp)
97#else 105#else
@@ -107,11 +115,7 @@
107 .endm 115 .endm
108 116
109 .macro set_saved_sp stackp temp temp2 117 .macro set_saved_sp stackp temp temp2
110#ifdef CONFIG_MIPS_MT_SMTC 118 CPU_ID_MFC0 \temp, CPU_ID_REG
111 mfc0 \temp, CP0_TCBIND
112#else
113 MFC0 \temp, CP0_CONTEXT
114#endif
115 LONG_SRL \temp, PTEBASE_SHIFT 119 LONG_SRL \temp, PTEBASE_SHIFT
116 LONG_S \stackp, kernelsp(\temp) 120 LONG_S \stackp, kernelsp(\temp)
117 .endm 121 .endm
@@ -166,7 +170,6 @@
166 LONG_S $0, PT_R0(sp) 170 LONG_S $0, PT_R0(sp)
167 mfc0 v1, CP0_STATUS 171 mfc0 v1, CP0_STATUS
168 LONG_S $2, PT_R2(sp) 172 LONG_S $2, PT_R2(sp)
169 LONG_S v1, PT_STATUS(sp)
170#ifdef CONFIG_MIPS_MT_SMTC 173#ifdef CONFIG_MIPS_MT_SMTC
171 /* 174 /*
172 * Ideally, these instructions would be shuffled in 175 * Ideally, these instructions would be shuffled in
@@ -178,20 +181,21 @@
178 LONG_S v1, PT_TCSTATUS(sp) 181 LONG_S v1, PT_TCSTATUS(sp)
179#endif /* CONFIG_MIPS_MT_SMTC */ 182#endif /* CONFIG_MIPS_MT_SMTC */
180 LONG_S $4, PT_R4(sp) 183 LONG_S $4, PT_R4(sp)
181 mfc0 v1, CP0_CAUSE
182 LONG_S $5, PT_R5(sp) 184 LONG_S $5, PT_R5(sp)
183 LONG_S v1, PT_CAUSE(sp) 185 LONG_S v1, PT_STATUS(sp)
186 mfc0 v1, CP0_CAUSE
184 LONG_S $6, PT_R6(sp) 187 LONG_S $6, PT_R6(sp)
185 MFC0 v1, CP0_EPC
186 LONG_S $7, PT_R7(sp) 188 LONG_S $7, PT_R7(sp)
189 LONG_S v1, PT_CAUSE(sp)
190 MFC0 v1, CP0_EPC
187#ifdef CONFIG_64BIT 191#ifdef CONFIG_64BIT
188 LONG_S $8, PT_R8(sp) 192 LONG_S $8, PT_R8(sp)
189 LONG_S $9, PT_R9(sp) 193 LONG_S $9, PT_R9(sp)
190#endif 194#endif
191 LONG_S v1, PT_EPC(sp)
192 LONG_S $25, PT_R25(sp) 195 LONG_S $25, PT_R25(sp)
193 LONG_S $28, PT_R28(sp) 196 LONG_S $28, PT_R28(sp)
194 LONG_S $31, PT_R31(sp) 197 LONG_S $31, PT_R31(sp)
198 LONG_S v1, PT_EPC(sp)
195 ori $28, sp, _THREAD_MASK 199 ori $28, sp, _THREAD_MASK
196 xori $28, _THREAD_MASK 200 xori $28, _THREAD_MASK
197#ifdef CONFIG_CPU_CAVIUM_OCTEON 201#ifdef CONFIG_CPU_CAVIUM_OCTEON
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index eecd2a9f155c..9326af5186fe 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -2,14 +2,17 @@
2# Makefile for the Linux/MIPS kernel. 2# Makefile for the Linux/MIPS kernel.
3# 3#
4 4
5CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS)
6
7extra-y := head.o init_task.o vmlinux.lds 5extra-y := head.o init_task.o vmlinux.lds
8 6
9obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \ 7obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \
10 ptrace.o reset.o setup.o signal.o syscall.o \ 8 ptrace.o reset.o setup.o signal.o syscall.o \
11 time.o topology.o traps.o unaligned.o watch.o 9 time.o topology.o traps.o unaligned.o watch.o
12 10
11ifdef CONFIG_FUNCTION_TRACER
12CFLAGS_REMOVE_ftrace.o = -pg
13CFLAGS_REMOVE_early_printk.o = -pg
14endif
15
13obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o 16obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o
14obj-$(CONFIG_CEVT_R4K_LIB) += cevt-r4k.o 17obj-$(CONFIG_CEVT_R4K_LIB) += cevt-r4k.o
15obj-$(CONFIG_MIPS_MT_SMTC) += cevt-smtc.o 18obj-$(CONFIG_MIPS_MT_SMTC) += cevt-smtc.o
@@ -19,6 +22,7 @@ obj-$(CONFIG_CEVT_SB1250) += cevt-sb1250.o
19obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o 22obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o
20obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o 23obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o
21obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o 24obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o
25obj-$(CONFIG_CSRC_POWERTV) += csrc-powertv.o
22obj-$(CONFIG_CSRC_R4K_LIB) += csrc-r4k.o 26obj-$(CONFIG_CSRC_R4K_LIB) += csrc-r4k.o
23obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o 27obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o
24obj-$(CONFIG_SYNC_R4K) += sync-r4k.o 28obj-$(CONFIG_SYNC_R4K) += sync-r4k.o
@@ -26,6 +30,8 @@ obj-$(CONFIG_SYNC_R4K) += sync-r4k.o
26obj-$(CONFIG_STACKTRACE) += stacktrace.o 30obj-$(CONFIG_STACKTRACE) += stacktrace.o
27obj-$(CONFIG_MODULES) += mips_ksyms.o module.o 31obj-$(CONFIG_MODULES) += mips_ksyms.o module.o
28 32
33obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o
34
29obj-$(CONFIG_CPU_LOONGSON2) += r4k_fpu.o r4k_switch.o 35obj-$(CONFIG_CPU_LOONGSON2) += r4k_fpu.o r4k_switch.o
30obj-$(CONFIG_CPU_MIPS32) += r4k_fpu.o r4k_switch.o 36obj-$(CONFIG_CPU_MIPS32) += r4k_fpu.o r4k_switch.o
31obj-$(CONFIG_CPU_MIPS64) += r4k_fpu.o r4k_switch.o 37obj-$(CONFIG_CPU_MIPS64) += r4k_fpu.o r4k_switch.o
@@ -92,4 +98,8 @@ CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(KBUILD_CFLAGS) -Wa,-mdaddi -c -o /dev/n
92 98
93obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT) += 8250-platform.o 99obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT) += 8250-platform.o
94 100
101obj-$(CONFIG_MIPS_CPUFREQ) += cpufreq/
102
95EXTRA_CFLAGS += -Werror 103EXTRA_CFLAGS += -Werror
104
105CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 7a51866068a4..80e202eca056 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -16,6 +16,7 @@
16#include <linux/ptrace.h> 16#include <linux/ptrace.h>
17#include <linux/smp.h> 17#include <linux/smp.h>
18#include <linux/stddef.h> 18#include <linux/stddef.h>
19#include <linux/module.h>
19 20
20#include <asm/bugs.h> 21#include <asm/bugs.h>
21#include <asm/cpu.h> 22#include <asm/cpu.h>
@@ -32,6 +33,7 @@
32 * the CPU very much. 33 * the CPU very much.
33 */ 34 */
34void (*cpu_wait)(void); 35void (*cpu_wait)(void);
36EXPORT_SYMBOL(cpu_wait);
35 37
36static void r3081_wait(void) 38static void r3081_wait(void)
37{ 39{
diff --git a/arch/mips/kernel/cpufreq/Kconfig b/arch/mips/kernel/cpufreq/Kconfig
new file mode 100644
index 000000000000..58c601eee6fd
--- /dev/null
+++ b/arch/mips/kernel/cpufreq/Kconfig
@@ -0,0 +1,41 @@
1#
2# CPU Frequency scaling
3#
4
5config MIPS_EXTERNAL_TIMER
6 bool
7
8config MIPS_CPUFREQ
9 bool
10 default y
11 depends on CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
12
13if MIPS_CPUFREQ
14
15menu "CPU Frequency scaling"
16
17source "drivers/cpufreq/Kconfig"
18
19if CPU_FREQ
20
21comment "CPUFreq processor drivers"
22
23config LOONGSON2_CPUFREQ
24 tristate "Loongson2 CPUFreq Driver"
25 select CPU_FREQ_TABLE
26 depends on MIPS_CPUFREQ
27 help
28 This option adds a CPUFreq driver for loongson processors which
29 support software configurable cpu frequency.
30
31 Loongson2F and it's successors support this feature.
32
33 For details, take a look at <file:Documentation/cpu-freq/>.
34
35 If in doubt, say N.
36
37endif # CPU_FREQ
38
39endmenu
40
41endif # MIPS_CPUFREQ
diff --git a/arch/mips/kernel/cpufreq/Makefile b/arch/mips/kernel/cpufreq/Makefile
new file mode 100644
index 000000000000..c3479a432efe
--- /dev/null
+++ b/arch/mips/kernel/cpufreq/Makefile
@@ -0,0 +1,5 @@
1#
2# Makefile for the Linux/MIPS cpufreq.
3#
4
5obj-$(CONFIG_LOONGSON2_CPUFREQ) += loongson2_cpufreq.o loongson2_clock.o
diff --git a/arch/mips/kernel/cpufreq/loongson2_clock.c b/arch/mips/kernel/cpufreq/loongson2_clock.c
new file mode 100644
index 000000000000..d7ca256e33ef
--- /dev/null
+++ b/arch/mips/kernel/cpufreq/loongson2_clock.c
@@ -0,0 +1,166 @@
1/*
2 * Copyright (C) 2006 - 2008 Lemote Inc. & Insititute of Computing Technology
3 * Author: Yanhua, yanh@lemote.com
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 */
9
10#include <linux/cpufreq.h>
11#include <linux/platform_device.h>
12
13#include <asm/clock.h>
14
15#include <loongson.h>
16
17static LIST_HEAD(clock_list);
18static DEFINE_SPINLOCK(clock_lock);
19static DEFINE_MUTEX(clock_list_sem);
20
21/* Minimum CLK support */
22enum {
23 DC_ZERO, DC_25PT = 2, DC_37PT, DC_50PT, DC_62PT, DC_75PT,
24 DC_87PT, DC_DISABLE, DC_RESV
25};
26
27struct cpufreq_frequency_table loongson2_clockmod_table[] = {
28 {DC_RESV, CPUFREQ_ENTRY_INVALID},
29 {DC_ZERO, CPUFREQ_ENTRY_INVALID},
30 {DC_25PT, 0},
31 {DC_37PT, 0},
32 {DC_50PT, 0},
33 {DC_62PT, 0},
34 {DC_75PT, 0},
35 {DC_87PT, 0},
36 {DC_DISABLE, 0},
37 {DC_RESV, CPUFREQ_TABLE_END},
38};
39EXPORT_SYMBOL_GPL(loongson2_clockmod_table);
40
41static struct clk cpu_clk = {
42 .name = "cpu_clk",
43 .flags = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
44 .rate = 800000000,
45};
46
47struct clk *clk_get(struct device *dev, const char *id)
48{
49 return &cpu_clk;
50}
51EXPORT_SYMBOL(clk_get);
52
53static void propagate_rate(struct clk *clk)
54{
55 struct clk *clkp;
56
57 list_for_each_entry(clkp, &clock_list, node) {
58 if (likely(clkp->parent != clk))
59 continue;
60 if (likely(clkp->ops && clkp->ops->recalc))
61 clkp->ops->recalc(clkp);
62 if (unlikely(clkp->flags & CLK_RATE_PROPAGATES))
63 propagate_rate(clkp);
64 }
65}
66
67int clk_enable(struct clk *clk)
68{
69 return 0;
70}
71EXPORT_SYMBOL(clk_enable);
72
73void clk_disable(struct clk *clk)
74{
75}
76EXPORT_SYMBOL(clk_disable);
77
78unsigned long clk_get_rate(struct clk *clk)
79{
80 return (unsigned long)clk->rate;
81}
82EXPORT_SYMBOL(clk_get_rate);
83
84void clk_put(struct clk *clk)
85{
86}
87EXPORT_SYMBOL(clk_put);
88
89int clk_set_rate(struct clk *clk, unsigned long rate)
90{
91 return clk_set_rate_ex(clk, rate, 0);
92}
93EXPORT_SYMBOL_GPL(clk_set_rate);
94
95int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id)
96{
97 int ret = 0;
98 int regval;
99 int i;
100
101 if (likely(clk->ops && clk->ops->set_rate)) {
102 unsigned long flags;
103
104 spin_lock_irqsave(&clock_lock, flags);
105 ret = clk->ops->set_rate(clk, rate, algo_id);
106 spin_unlock_irqrestore(&clock_lock, flags);
107 }
108
109 if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
110 propagate_rate(clk);
111
112 for (i = 0; loongson2_clockmod_table[i].frequency != CPUFREQ_TABLE_END;
113 i++) {
114 if (loongson2_clockmod_table[i].frequency ==
115 CPUFREQ_ENTRY_INVALID)
116 continue;
117 if (rate == loongson2_clockmod_table[i].frequency)
118 break;
119 }
120 if (rate != loongson2_clockmod_table[i].frequency)
121 return -ENOTSUPP;
122
123 clk->rate = rate;
124
125 regval = LOONGSON_CHIPCFG0;
126 regval = (regval & ~0x7) | (loongson2_clockmod_table[i].index - 1);
127 LOONGSON_CHIPCFG0 = regval;
128
129 return ret;
130}
131EXPORT_SYMBOL_GPL(clk_set_rate_ex);
132
133long clk_round_rate(struct clk *clk, unsigned long rate)
134{
135 if (likely(clk->ops && clk->ops->round_rate)) {
136 unsigned long flags, rounded;
137
138 spin_lock_irqsave(&clock_lock, flags);
139 rounded = clk->ops->round_rate(clk, rate);
140 spin_unlock_irqrestore(&clock_lock, flags);
141
142 return rounded;
143 }
144
145 return rate;
146}
147EXPORT_SYMBOL_GPL(clk_round_rate);
148
149/*
150 * This is the simple version of Loongson-2 wait, Maybe we need do this in
151 * interrupt disabled content
152 */
153
154DEFINE_SPINLOCK(loongson2_wait_lock);
155void loongson2_cpu_wait(void)
156{
157 u32 cpu_freq;
158 unsigned long flags;
159
160 spin_lock_irqsave(&loongson2_wait_lock, flags);
161 cpu_freq = LOONGSON_CHIPCFG0;
162 LOONGSON_CHIPCFG0 &= ~0x7; /* Put CPU into wait mode */
163 LOONGSON_CHIPCFG0 = cpu_freq; /* Restore CPU state */
164 spin_unlock_irqrestore(&loongson2_wait_lock, flags);
165}
166EXPORT_SYMBOL_GPL(loongson2_cpu_wait);
diff --git a/arch/mips/kernel/cpufreq/loongson2_cpufreq.c b/arch/mips/kernel/cpufreq/loongson2_cpufreq.c
new file mode 100644
index 000000000000..2f6a0b147ab8
--- /dev/null
+++ b/arch/mips/kernel/cpufreq/loongson2_cpufreq.c
@@ -0,0 +1,227 @@
1/*
2 * Cpufreq driver for the loongson-2 processors
3 *
4 * The 2E revision of loongson processor not support this feature.
5 *
6 * Copyright (C) 2006 - 2008 Lemote Inc. & Insititute of Computing Technology
7 * Author: Yanhua, yanh@lemote.com
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/cpufreq.h>
14#include <linux/module.h>
15#include <linux/err.h>
16#include <linux/sched.h> /* set_cpus_allowed() */
17#include <linux/delay.h>
18#include <linux/platform_device.h>
19
20#include <asm/clock.h>
21
22#include <loongson.h>
23
24static uint nowait;
25
26static struct clk *cpuclk;
27
28static void (*saved_cpu_wait) (void);
29
30static int loongson2_cpu_freq_notifier(struct notifier_block *nb,
31 unsigned long val, void *data);
32
33static struct notifier_block loongson2_cpufreq_notifier_block = {
34 .notifier_call = loongson2_cpu_freq_notifier
35};
36
37static int loongson2_cpu_freq_notifier(struct notifier_block *nb,
38 unsigned long val, void *data)
39{
40 if (val == CPUFREQ_POSTCHANGE)
41 current_cpu_data.udelay_val = loops_per_jiffy;
42
43 return 0;
44}
45
46static unsigned int loongson2_cpufreq_get(unsigned int cpu)
47{
48 return clk_get_rate(cpuclk);
49}
50
51/*
52 * Here we notify other drivers of the proposed change and the final change.
53 */
54static int loongson2_cpufreq_target(struct cpufreq_policy *policy,
55 unsigned int target_freq,
56 unsigned int relation)
57{
58 unsigned int cpu = policy->cpu;
59 unsigned int newstate = 0;
60 cpumask_t cpus_allowed;
61 struct cpufreq_freqs freqs;
62 unsigned int freq;
63
64 if (!cpu_online(cpu))
65 return -ENODEV;
66
67 cpus_allowed = current->cpus_allowed;
68 set_cpus_allowed(current, cpumask_of_cpu(cpu));
69
70 if (cpufreq_frequency_table_target
71 (policy, &loongson2_clockmod_table[0], target_freq, relation,
72 &newstate))
73 return -EINVAL;
74
75 freq =
76 ((cpu_clock_freq / 1000) *
77 loongson2_clockmod_table[newstate].index) / 8;
78 if (freq < policy->min || freq > policy->max)
79 return -EINVAL;
80
81 pr_debug("cpufreq: requested frequency %u Hz\n", target_freq * 1000);
82
83 freqs.cpu = cpu;
84 freqs.old = loongson2_cpufreq_get(cpu);
85 freqs.new = freq;
86 freqs.flags = 0;
87
88 if (freqs.new == freqs.old)
89 return 0;
90
91 /* notifiers */
92 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
93
94 set_cpus_allowed(current, cpus_allowed);
95
96 /* setting the cpu frequency */
97 clk_set_rate(cpuclk, freq);
98
99 /* notifiers */
100 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
101
102 pr_debug("cpufreq: set frequency %u kHz\n", freq);
103
104 return 0;
105}
106
107static int loongson2_cpufreq_cpu_init(struct cpufreq_policy *policy)
108{
109 int i;
110
111 if (!cpu_online(policy->cpu))
112 return -ENODEV;
113
114 cpuclk = clk_get(NULL, "cpu_clk");
115 if (IS_ERR(cpuclk)) {
116 printk(KERN_ERR "cpufreq: couldn't get CPU clk\n");
117 return PTR_ERR(cpuclk);
118 }
119
120 cpuclk->rate = cpu_clock_freq / 1000;
121 if (!cpuclk->rate)
122 return -EINVAL;
123
124 /* clock table init */
125 for (i = 2;
126 (loongson2_clockmod_table[i].frequency != CPUFREQ_TABLE_END);
127 i++)
128 loongson2_clockmod_table[i].frequency = (cpuclk->rate * i) / 8;
129
130 policy->cur = loongson2_cpufreq_get(policy->cpu);
131
132 cpufreq_frequency_table_get_attr(&loongson2_clockmod_table[0],
133 policy->cpu);
134
135 return cpufreq_frequency_table_cpuinfo(policy,
136 &loongson2_clockmod_table[0]);
137}
138
139static int loongson2_cpufreq_verify(struct cpufreq_policy *policy)
140{
141 return cpufreq_frequency_table_verify(policy,
142 &loongson2_clockmod_table[0]);
143}
144
145static int loongson2_cpufreq_exit(struct cpufreq_policy *policy)
146{
147 clk_put(cpuclk);
148 return 0;
149}
150
151static struct freq_attr *loongson2_table_attr[] = {
152 &cpufreq_freq_attr_scaling_available_freqs,
153 NULL,
154};
155
156static struct cpufreq_driver loongson2_cpufreq_driver = {
157 .owner = THIS_MODULE,
158 .name = "loongson2",
159 .init = loongson2_cpufreq_cpu_init,
160 .verify = loongson2_cpufreq_verify,
161 .target = loongson2_cpufreq_target,
162 .get = loongson2_cpufreq_get,
163 .exit = loongson2_cpufreq_exit,
164 .attr = loongson2_table_attr,
165};
166
167static struct platform_device_id platform_device_ids[] = {
168 {
169 .name = "loongson2_cpufreq",
170 },
171 {}
172};
173
174MODULE_DEVICE_TABLE(platform, platform_device_ids);
175
176static struct platform_driver platform_driver = {
177 .driver = {
178 .name = "loongson2_cpufreq",
179 .owner = THIS_MODULE,
180 },
181 .id_table = platform_device_ids,
182};
183
184static int __init cpufreq_init(void)
185{
186 int ret;
187
188 /* Register platform stuff */
189 ret = platform_driver_register(&platform_driver);
190 if (ret)
191 return ret;
192
193 pr_info("cpufreq: Loongson-2F CPU frequency driver.\n");
194
195 cpufreq_register_notifier(&loongson2_cpufreq_notifier_block,
196 CPUFREQ_TRANSITION_NOTIFIER);
197
198 ret = cpufreq_register_driver(&loongson2_cpufreq_driver);
199
200 if (!ret && !nowait) {
201 saved_cpu_wait = cpu_wait;
202 cpu_wait = loongson2_cpu_wait;
203 }
204
205 return ret;
206}
207
208static void __exit cpufreq_exit(void)
209{
210 if (!nowait && saved_cpu_wait)
211 cpu_wait = saved_cpu_wait;
212 cpufreq_unregister_driver(&loongson2_cpufreq_driver);
213 cpufreq_unregister_notifier(&loongson2_cpufreq_notifier_block,
214 CPUFREQ_TRANSITION_NOTIFIER);
215
216 platform_driver_unregister(&platform_driver);
217}
218
219module_init(cpufreq_init);
220module_exit(cpufreq_exit);
221
222module_param(nowait, uint, 0644);
223MODULE_PARM_DESC(nowait, "Disable Loongson-2F specific wait");
224
225MODULE_AUTHOR("Yanhua <yanh@lemote.com>");
226MODULE_DESCRIPTION("cpufreq driver for Loongson2F");
227MODULE_LICENSE("GPL");
diff --git a/arch/mips/kernel/csrc-powertv.c b/arch/mips/kernel/csrc-powertv.c
new file mode 100644
index 000000000000..a27c16c8690e
--- /dev/null
+++ b/arch/mips/kernel/csrc-powertv.c
@@ -0,0 +1,180 @@
1/*
2 * Copyright (C) 2008 Scientific-Atlanta, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18/*
19 * The file comes from kernel/csrc-r4k.c
20 */
21#include <linux/clocksource.h>
22#include <linux/init.h>
23
24#include <asm/time.h> /* Not included in linux/time.h */
25
26#include <asm/mach-powertv/asic_regs.h>
27#include "powertv-clock.h"
28
29/* MIPS PLL Register Definitions */
30#define PLL_GET_M(x) (((x) >> 8) & 0x000000FF)
31#define PLL_GET_N(x) (((x) >> 16) & 0x000000FF)
32#define PLL_GET_P(x) (((x) >> 24) & 0x00000007)
33
34/*
35 * returns: Clock frequency in kHz
36 */
37unsigned int __init mips_get_pll_freq(void)
38{
39 unsigned int pll_reg, m, n, p;
40 unsigned int fin = 54000; /* Base frequency in kHz */
41 unsigned int fout;
42
43 /* Read PLL register setting */
44 pll_reg = asic_read(mips_pll_setup);
45 m = PLL_GET_M(pll_reg);
46 n = PLL_GET_N(pll_reg);
47 p = PLL_GET_P(pll_reg);
48 pr_info("MIPS PLL Register:0x%x M=%d N=%d P=%d\n", pll_reg, m, n, p);
49
50 /* Calculate clock frequency = (2 * N * 54MHz) / (M * (2**P)) */
51 fout = ((2 * n * fin) / (m * (0x01 << p)));
52
53 pr_info("MIPS Clock Freq=%d kHz\n", fout);
54
55 return fout;
56}
57
58static cycle_t c0_hpt_read(struct clocksource *cs)
59{
60 return read_c0_count();
61}
62
63static struct clocksource clocksource_mips = {
64 .name = "powertv-counter",
65 .read = c0_hpt_read,
66 .mask = CLOCKSOURCE_MASK(32),
67 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
68};
69
70static void __init powertv_c0_hpt_clocksource_init(void)
71{
72 unsigned int pll_freq = mips_get_pll_freq();
73
74 pr_info("CPU frequency %d.%02d MHz\n", pll_freq / 1000,
75 (pll_freq % 1000) * 100 / 1000);
76
77 mips_hpt_frequency = pll_freq / 2 * 1000;
78
79 clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
80
81 clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
82
83 clocksource_register(&clocksource_mips);
84}
85
86/**
87 * struct tim_c - free running counter
88 * @hi: High 16 bits of the counter
89 * @lo: Low 32 bits of the counter
90 *
91 * Lays out the structure of the free running counter in memory. This counter
92 * increments at a rate of 27 MHz/8 on all platforms.
93 */
94struct tim_c {
95 unsigned int hi;
96 unsigned int lo;
97};
98
99static struct tim_c *tim_c;
100
101static cycle_t tim_c_read(struct clocksource *cs)
102{
103 unsigned int hi;
104 unsigned int next_hi;
105 unsigned int lo;
106
107 hi = readl(&tim_c->hi);
108
109 for (;;) {
110 lo = readl(&tim_c->lo);
111 next_hi = readl(&tim_c->hi);
112 if (next_hi == hi)
113 break;
114 hi = next_hi;
115 }
116
117pr_crit("%s: read %llx\n", __func__, ((u64) hi << 32) | lo);
118 return ((u64) hi << 32) | lo;
119}
120
121#define TIM_C_SIZE 48 /* # bits in the timer */
122
123static struct clocksource clocksource_tim_c = {
124 .name = "powertv-tim_c",
125 .read = tim_c_read,
126 .mask = CLOCKSOURCE_MASK(TIM_C_SIZE),
127 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
128};
129
130/**
131 * powertv_tim_c_clocksource_init - set up a clock source for the TIM_C clock
132 *
133 * The hard part here is coming up with a constant k and shift s such that
134 * the 48-bit TIM_C value multiplied by k doesn't overflow and that value,
135 * when shifted right by s, yields the corresponding number of nanoseconds.
136 * We know that TIM_C counts at 27 MHz/8, so each cycle corresponds to
137 * 1 / (27,000,000/8) seconds. Multiply that by a billion and you get the
138 * number of nanoseconds. Since the TIM_C value has 48 bits and the math is
139 * done in 64 bits, avoiding an overflow means that k must be less than
140 * 64 - 48 = 16 bits.
141 */
142static void __init powertv_tim_c_clocksource_init(void)
143{
144 int prescale;
145 unsigned long dividend;
146 unsigned long k;
147 int s;
148 const int max_k_bits = (64 - 48) - 1;
149 const unsigned long billion = 1000000000;
150 const unsigned long counts_per_second = 27000000 / 8;
151
152 prescale = BITS_PER_LONG - ilog2(billion) - 1;
153 dividend = billion << prescale;
154 k = dividend / counts_per_second;
155 s = ilog2(k) - max_k_bits;
156
157 if (s < 0)
158 s = prescale;
159
160 else {
161 k >>= s;
162 s += prescale;
163 }
164
165 clocksource_tim_c.mult = k;
166 clocksource_tim_c.shift = s;
167 clocksource_tim_c.rating = 200;
168
169 clocksource_register(&clocksource_tim_c);
170 tim_c = (struct tim_c *) asic_reg_addr(tim_ch);
171}
172
173/**
174 powertv_clocksource_init - initialize all clocksources
175 */
176void __init powertv_clocksource_init(void)
177{
178 powertv_c0_hpt_clocksource_init();
179 powertv_tim_c_clocksource_init();
180}
diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c
new file mode 100644
index 000000000000..68b067040d8b
--- /dev/null
+++ b/arch/mips/kernel/ftrace.c
@@ -0,0 +1,275 @@
1/*
2 * Code for replacing ftrace calls with jumps.
3 *
4 * Copyright (C) 2007-2008 Steven Rostedt <srostedt@redhat.com>
5 * Copyright (C) 2009 DSLab, Lanzhou University, China
6 * Author: Wu Zhangjin <wuzj@lemote.com>
7 *
8 * Thanks goes to Steven Rostedt for writing the original x86 version.
9 */
10
11#include <linux/uaccess.h>
12#include <linux/init.h>
13#include <linux/ftrace.h>
14
15#include <asm/cacheflush.h>
16#include <asm/asm.h>
17#include <asm/asm-offsets.h>
18
19#ifdef CONFIG_DYNAMIC_FTRACE
20
21#define JAL 0x0c000000 /* jump & link: ip --> ra, jump to target */
22#define ADDR_MASK 0x03ffffff /* op_code|addr : 31...26|25 ....0 */
23#define jump_insn_encode(op_code, addr) \
24 ((unsigned int)((op_code) | (((addr) >> 2) & ADDR_MASK)))
25
26static unsigned int ftrace_nop = 0x00000000;
27
28static int ftrace_modify_code(unsigned long ip, unsigned int new_code)
29{
30 int faulted;
31
32 /* *(unsigned int *)ip = new_code; */
33 safe_store_code(new_code, ip, faulted);
34
35 if (unlikely(faulted))
36 return -EFAULT;
37
38 flush_icache_range(ip, ip + 8);
39
40 return 0;
41}
42
43static int lui_v1;
44static int jal_mcount;
45
46int ftrace_make_nop(struct module *mod,
47 struct dyn_ftrace *rec, unsigned long addr)
48{
49 unsigned int new;
50 int faulted;
51 unsigned long ip = rec->ip;
52
53 /* We have compiled module with -mlong-calls, but compiled the kernel
54 * without it, we need to cope with them respectively. */
55 if (ip & 0x40000000) {
56 /* record it for ftrace_make_call */
57 if (lui_v1 == 0) {
58 /* lui_v1 = *(unsigned int *)ip; */
59 safe_load_code(lui_v1, ip, faulted);
60
61 if (unlikely(faulted))
62 return -EFAULT;
63 }
64
65 /* lui v1, hi_16bit_of_mcount --> b 1f (0x10000004)
66 * addiu v1, v1, low_16bit_of_mcount
67 * move at, ra
68 * jalr v1
69 * nop
70 * 1f: (ip + 12)
71 */
72 new = 0x10000004;
73 } else {
74 /* record/calculate it for ftrace_make_call */
75 if (jal_mcount == 0) {
76 /* We can record it directly like this:
77 * jal_mcount = *(unsigned int *)ip;
78 * Herein, jump over the first two nop instructions */
79 jal_mcount = jump_insn_encode(JAL, (MCOUNT_ADDR + 8));
80 }
81
82 /* move at, ra
83 * jalr v1 --> nop
84 */
85 new = ftrace_nop;
86 }
87 return ftrace_modify_code(ip, new);
88}
89
90static int modified; /* initialized as 0 by default */
91
92int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
93{
94 unsigned int new;
95 unsigned long ip = rec->ip;
96
97 /* We just need to remove the "b ftrace_stub" at the fist time! */
98 if (modified == 0) {
99 modified = 1;
100 ftrace_modify_code(addr, ftrace_nop);
101 }
102 /* ip, module: 0xc0000000, kernel: 0x80000000 */
103 new = (ip & 0x40000000) ? lui_v1 : jal_mcount;
104
105 return ftrace_modify_code(ip, new);
106}
107
108#define FTRACE_CALL_IP ((unsigned long)(&ftrace_call))
109
110int ftrace_update_ftrace_func(ftrace_func_t func)
111{
112 unsigned int new;
113
114 new = jump_insn_encode(JAL, (unsigned long)func);
115
116 return ftrace_modify_code(FTRACE_CALL_IP, new);
117}
118
119int __init ftrace_dyn_arch_init(void *data)
120{
121 /* The return code is retured via data */
122 *(unsigned long *)data = 0;
123
124 return 0;
125}
126#endif /* CONFIG_DYNAMIC_FTRACE */
127
128#ifdef CONFIG_FUNCTION_GRAPH_TRACER
129
130#ifdef CONFIG_DYNAMIC_FTRACE
131
132extern void ftrace_graph_call(void);
133#define JMP 0x08000000 /* jump to target directly */
134#define CALL_FTRACE_GRAPH_CALLER \
135 jump_insn_encode(JMP, (unsigned long)(&ftrace_graph_caller))
136#define FTRACE_GRAPH_CALL_IP ((unsigned long)(&ftrace_graph_call))
137
138int ftrace_enable_ftrace_graph_caller(void)
139{
140 return ftrace_modify_code(FTRACE_GRAPH_CALL_IP,
141 CALL_FTRACE_GRAPH_CALLER);
142}
143
144int ftrace_disable_ftrace_graph_caller(void)
145{
146 return ftrace_modify_code(FTRACE_GRAPH_CALL_IP, ftrace_nop);
147}
148
149#endif /* !CONFIG_DYNAMIC_FTRACE */
150
151#ifndef KBUILD_MCOUNT_RA_ADDRESS
152#define S_RA_SP (0xafbf << 16) /* s{d,w} ra, offset(sp) */
153#define S_R_SP (0xafb0 << 16) /* s{d,w} R, offset(sp) */
154#define OFFSET_MASK 0xffff /* stack offset range: 0 ~ PT_SIZE */
155
156unsigned long ftrace_get_parent_addr(unsigned long self_addr,
157 unsigned long parent,
158 unsigned long parent_addr,
159 unsigned long fp)
160{
161 unsigned long sp, ip, ra;
162 unsigned int code;
163 int faulted;
164
165 /* in module or kernel? */
166 if (self_addr & 0x40000000) {
167 /* module: move to the instruction "lui v1, HI_16BIT_OF_MCOUNT" */
168 ip = self_addr - 20;
169 } else {
170 /* kernel: move to the instruction "move ra, at" */
171 ip = self_addr - 12;
172 }
173
174 /* search the text until finding the non-store instruction or "s{d,w}
175 * ra, offset(sp)" instruction */
176 do {
177 ip -= 4;
178
179 /* get the code at "ip": code = *(unsigned int *)ip; */
180 safe_load_code(code, ip, faulted);
181
182 if (unlikely(faulted))
183 return 0;
184
185 /* If we hit the non-store instruction before finding where the
186 * ra is stored, then this is a leaf function and it does not
187 * store the ra on the stack. */
188 if ((code & S_R_SP) != S_R_SP)
189 return parent_addr;
190
191 } while (((code & S_RA_SP) != S_RA_SP));
192
193 sp = fp + (code & OFFSET_MASK);
194
195 /* ra = *(unsigned long *)sp; */
196 safe_load_stack(ra, sp, faulted);
197 if (unlikely(faulted))
198 return 0;
199
200 if (ra == parent)
201 return sp;
202 return 0;
203}
204
205#endif
206
207/*
208 * Hook the return address and push it in the stack of return addrs
209 * in current thread info.
210 */
211void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr,
212 unsigned long fp)
213{
214 unsigned long old;
215 struct ftrace_graph_ent trace;
216 unsigned long return_hooker = (unsigned long)
217 &return_to_handler;
218 int faulted;
219
220 if (unlikely(atomic_read(&current->tracing_graph_pause)))
221 return;
222
223 /* "parent" is the stack address saved the return address of the caller
224 * of _mcount.
225 *
226 * if the gcc < 4.5, a leaf function does not save the return address
227 * in the stack address, so, we "emulate" one in _mcount's stack space,
228 * and hijack it directly, but for a non-leaf function, it save the
229 * return address to the its own stack space, we can not hijack it
230 * directly, but need to find the real stack address,
231 * ftrace_get_parent_addr() does it!
232 *
233 * if gcc>= 4.5, with the new -mmcount-ra-address option, for a
234 * non-leaf function, the location of the return address will be saved
235 * to $12 for us, and for a leaf function, only put a zero into $12. we
236 * do it in ftrace_graph_caller of mcount.S.
237 */
238
239 /* old = *parent; */
240 safe_load_stack(old, parent, faulted);
241 if (unlikely(faulted))
242 goto out;
243#ifndef KBUILD_MCOUNT_RA_ADDRESS
244 parent = (unsigned long *)ftrace_get_parent_addr(self_addr, old,
245 (unsigned long)parent,
246 fp);
247 /* If fails when getting the stack address of the non-leaf function's
248 * ra, stop function graph tracer and return */
249 if (parent == 0)
250 goto out;
251#endif
252 /* *parent = return_hooker; */
253 safe_store_stack(return_hooker, parent, faulted);
254 if (unlikely(faulted))
255 goto out;
256
257 if (ftrace_push_return_trace(old, self_addr, &trace.depth, fp) ==
258 -EBUSY) {
259 *parent = old;
260 return;
261 }
262
263 trace.func = self_addr;
264
265 /* Only trace if the calling function expects to */
266 if (!ftrace_graph_entry(&trace)) {
267 current->curr_ret_stack--;
268 *parent = old;
269 }
270 return;
271out:
272 ftrace_graph_stop();
273 WARN_ON(1);
274}
275#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index 8b0b4181219f..981f86c26168 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -22,6 +22,7 @@
22#include <linux/seq_file.h> 22#include <linux/seq_file.h>
23#include <linux/kallsyms.h> 23#include <linux/kallsyms.h>
24#include <linux/kgdb.h> 24#include <linux/kgdb.h>
25#include <linux/ftrace.h>
25 26
26#include <asm/atomic.h> 27#include <asm/atomic.h>
27#include <asm/system.h> 28#include <asm/system.h>
@@ -150,3 +151,32 @@ void __init init_IRQ(void)
150 kgdb_early_setup = 1; 151 kgdb_early_setup = 1;
151#endif 152#endif
152} 153}
154
155/*
156 * do_IRQ handles all normal device IRQ's (the special
157 * SMP cross-CPU interrupts have their own specific
158 * handlers).
159 */
160void __irq_entry do_IRQ(unsigned int irq)
161{
162 irq_enter();
163 __DO_IRQ_SMTC_HOOK(irq);
164 generic_handle_irq(irq);
165 irq_exit();
166}
167
168#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
169/*
170 * To avoid inefficient and in some cases pathological re-checking of
171 * IRQ affinity, we have this variant that skips the affinity check.
172 */
173
174void __irq_entry do_IRQ_no_affinity(unsigned int irq)
175{
176 irq_enter();
177 __NO_AFFINITY_IRQ_SMTC_HOOK(irq);
178 generic_handle_irq(irq);
179 irq_exit();
180}
181
182#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
diff --git a/arch/mips/kernel/mcount.S b/arch/mips/kernel/mcount.S
new file mode 100644
index 000000000000..0a9cfdb271dd
--- /dev/null
+++ b/arch/mips/kernel/mcount.S
@@ -0,0 +1,189 @@
1/*
2 * MIPS specific _mcount support
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive for
6 * more details.
7 *
8 * Copyright (C) 2009 Lemote Inc. & DSLab, Lanzhou University, China
9 * Author: Wu Zhangjin <wuzj@lemote.com>
10 */
11
12#include <asm/regdef.h>
13#include <asm/stackframe.h>
14#include <asm/ftrace.h>
15
16 .text
17 .set noreorder
18 .set noat
19
20 .macro MCOUNT_SAVE_REGS
21 PTR_SUBU sp, PT_SIZE
22 PTR_S ra, PT_R31(sp)
23 PTR_S AT, PT_R1(sp)
24 PTR_S a0, PT_R4(sp)
25 PTR_S a1, PT_R5(sp)
26 PTR_S a2, PT_R6(sp)
27 PTR_S a3, PT_R7(sp)
28#ifdef CONFIG_64BIT
29 PTR_S a4, PT_R8(sp)
30 PTR_S a5, PT_R9(sp)
31 PTR_S a6, PT_R10(sp)
32 PTR_S a7, PT_R11(sp)
33#endif
34 .endm
35
36 .macro MCOUNT_RESTORE_REGS
37 PTR_L ra, PT_R31(sp)
38 PTR_L AT, PT_R1(sp)
39 PTR_L a0, PT_R4(sp)
40 PTR_L a1, PT_R5(sp)
41 PTR_L a2, PT_R6(sp)
42 PTR_L a3, PT_R7(sp)
43#ifdef CONFIG_64BIT
44 PTR_L a4, PT_R8(sp)
45 PTR_L a5, PT_R9(sp)
46 PTR_L a6, PT_R10(sp)
47 PTR_L a7, PT_R11(sp)
48#endif
49#ifdef CONFIG_64BIT
50 PTR_ADDIU sp, PT_SIZE
51#else
52 PTR_ADDIU sp, (PT_SIZE + 8)
53#endif
54.endm
55
56 .macro RETURN_BACK
57 jr ra
58 move ra, AT
59 .endm
60
61#ifdef CONFIG_DYNAMIC_FTRACE
62
63NESTED(ftrace_caller, PT_SIZE, ra)
64 .globl _mcount
65_mcount:
66 b ftrace_stub
67 nop
68 lw t1, function_trace_stop
69 bnez t1, ftrace_stub
70 nop
71
72 MCOUNT_SAVE_REGS
73#ifdef KBUILD_MCOUNT_RA_ADDRESS
74 PTR_S t0, PT_R12(sp) /* t0 saved the location of the return address(at) by -mmcount-ra-address */
75#endif
76
77 move a0, ra /* arg1: next ip, selfaddr */
78 .globl ftrace_call
79ftrace_call:
80 nop /* a placeholder for the call to a real tracing function */
81 move a1, AT /* arg2: the caller's next ip, parent */
82
83#ifdef CONFIG_FUNCTION_GRAPH_TRACER
84 .globl ftrace_graph_call
85ftrace_graph_call:
86 nop
87 nop
88#endif
89
90 MCOUNT_RESTORE_REGS
91 .globl ftrace_stub
92ftrace_stub:
93 RETURN_BACK
94 END(ftrace_caller)
95
96#else /* ! CONFIG_DYNAMIC_FTRACE */
97
98NESTED(_mcount, PT_SIZE, ra)
99 lw t1, function_trace_stop
100 bnez t1, ftrace_stub
101 nop
102 PTR_LA t1, ftrace_stub
103 PTR_L t2, ftrace_trace_function /* Prepare t2 for (1) */
104 bne t1, t2, static_trace
105 nop
106
107#ifdef CONFIG_FUNCTION_GRAPH_TRACER
108 PTR_L t3, ftrace_graph_return
109 bne t1, t3, ftrace_graph_caller
110 nop
111 PTR_LA t1, ftrace_graph_entry_stub
112 PTR_L t3, ftrace_graph_entry
113 bne t1, t3, ftrace_graph_caller
114 nop
115#endif
116 b ftrace_stub
117 nop
118
119static_trace:
120 MCOUNT_SAVE_REGS
121
122 move a0, ra /* arg1: next ip, selfaddr */
123 jalr t2 /* (1) call *ftrace_trace_function */
124 move a1, AT /* arg2: the caller's next ip, parent */
125
126 MCOUNT_RESTORE_REGS
127 .globl ftrace_stub
128ftrace_stub:
129 RETURN_BACK
130 END(_mcount)
131
132#endif /* ! CONFIG_DYNAMIC_FTRACE */
133
134#ifdef CONFIG_FUNCTION_GRAPH_TRACER
135
136NESTED(ftrace_graph_caller, PT_SIZE, ra)
137#ifdef CONFIG_DYNAMIC_FTRACE
138 PTR_L a1, PT_R31(sp) /* load the original ra from the stack */
139#ifdef KBUILD_MCOUNT_RA_ADDRESS
140 PTR_L t0, PT_R12(sp) /* load the original t0 from the stack */
141#endif
142#else
143 MCOUNT_SAVE_REGS
144 move a1, ra /* arg2: next ip, selfaddr */
145#endif
146
147#ifdef KBUILD_MCOUNT_RA_ADDRESS
148 bnez t0, 1f /* non-leaf func: t0 saved the location of the return address */
149 nop
150 PTR_LA t0, PT_R1(sp) /* leaf func: get the location of at(old ra) from our own stack */
1511: move a0, t0 /* arg1: the location of the return address */
152#else
153 PTR_LA a0, PT_R1(sp) /* arg1: &AT -> a0 */
154#endif
155 jal prepare_ftrace_return
156#ifdef CONFIG_FRAME_POINTER
157 move a2, fp /* arg3: frame pointer */
158#else
159#ifdef CONFIG_64BIT
160 PTR_LA a2, PT_SIZE(sp)
161#else
162 PTR_LA a2, (PT_SIZE+8)(sp)
163#endif
164#endif
165
166 MCOUNT_RESTORE_REGS
167 RETURN_BACK
168 END(ftrace_graph_caller)
169
170 .align 2
171 .globl return_to_handler
172return_to_handler:
173 PTR_SUBU sp, PT_SIZE
174 PTR_S v0, PT_R2(sp)
175
176 jal ftrace_return_to_handler
177 PTR_S v1, PT_R3(sp)
178
179 /* restore the real parent address: v0 -> ra */
180 move ra, v0
181
182 PTR_L v0, PT_R2(sp)
183 PTR_L v1, PT_R3(sp)
184 jr ra
185 PTR_ADDIU sp, PT_SIZE
186#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
187
188 .set at
189 .set reorder
diff --git a/arch/mips/kernel/mips_ksyms.c b/arch/mips/kernel/mips_ksyms.c
index 225755d0c1f6..1d04807874db 100644
--- a/arch/mips/kernel/mips_ksyms.c
+++ b/arch/mips/kernel/mips_ksyms.c
@@ -13,6 +13,7 @@
13#include <asm/checksum.h> 13#include <asm/checksum.h>
14#include <asm/pgtable.h> 14#include <asm/pgtable.h>
15#include <asm/uaccess.h> 15#include <asm/uaccess.h>
16#include <asm/ftrace.h>
16 17
17extern void *__bzero(void *__s, size_t __count); 18extern void *__bzero(void *__s, size_t __count);
18extern long __strncpy_from_user_nocheck_asm(char *__to, 19extern long __strncpy_from_user_nocheck_asm(char *__to,
@@ -51,3 +52,7 @@ EXPORT_SYMBOL(csum_partial_copy_nocheck);
51EXPORT_SYMBOL(__csum_partial_copy_user); 52EXPORT_SYMBOL(__csum_partial_copy_user);
52 53
53EXPORT_SYMBOL(invalid_pte_table); 54EXPORT_SYMBOL(invalid_pte_table);
55#ifdef CONFIG_FUNCTION_TRACER
56/* _mcount is defined in arch/mips/kernel/mcount.S */
57EXPORT_SYMBOL(_mcount);
58#endif
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 2b290d70083e..f9513f9e61d3 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -58,8 +58,12 @@ EXPORT_SYMBOL(mips_machtype);
58 58
59struct boot_mem_map boot_mem_map; 59struct boot_mem_map boot_mem_map;
60 60
61static char command_line[CL_SIZE]; 61static char __initdata command_line[COMMAND_LINE_SIZE];
62 char arcs_cmdline[CL_SIZE]=CONFIG_CMDLINE; 62char __initdata arcs_cmdline[COMMAND_LINE_SIZE];
63
64#ifdef CONFIG_CMDLINE_BOOL
65static char __initdata builtin_cmdline[COMMAND_LINE_SIZE] = CONFIG_CMDLINE;
66#endif
63 67
64/* 68/*
65 * mips_io_port_base is the begin of the address space to which x86 style 69 * mips_io_port_base is the begin of the address space to which x86 style
@@ -166,26 +170,8 @@ static unsigned long __init init_initrd(void)
166 * already set up initrd_start and initrd_end. In these cases 170 * already set up initrd_start and initrd_end. In these cases
167 * perfom sanity checks and use them if all looks good. 171 * perfom sanity checks and use them if all looks good.
168 */ 172 */
169 if (!initrd_start || initrd_end <= initrd_start) { 173 if (!initrd_start || initrd_end <= initrd_start)
170#ifdef CONFIG_PROBE_INITRD_HEADER
171 u32 *initrd_header;
172
173 /*
174 * See if initrd has been added to the kernel image by
175 * arch/mips/boot/addinitrd.c. In that case a header is
176 * prepended to initrd and is made up by 8 bytes. The first
177 * word is a magic number and the second one is the size of
178 * initrd. Initrd start must be page aligned in any cases.
179 */
180 initrd_header = __va(PAGE_ALIGN(__pa_symbol(&_end) + 8)) - 8;
181 if (initrd_header[0] != 0x494E5244)
182 goto disable;
183 initrd_start = (unsigned long)(initrd_header + 2);
184 initrd_end = initrd_start + initrd_header[1];
185#else
186 goto disable; 174 goto disable;
187#endif
188 }
189 175
190 if (initrd_start & ~PAGE_MASK) { 176 if (initrd_start & ~PAGE_MASK) {
191 pr_err("initrd start must be page aligned\n"); 177 pr_err("initrd start must be page aligned\n");
@@ -476,8 +462,20 @@ static void __init arch_mem_init(char **cmdline_p)
476 pr_info("Determined physical RAM map:\n"); 462 pr_info("Determined physical RAM map:\n");
477 print_memory_map(); 463 print_memory_map();
478 464
479 strlcpy(command_line, arcs_cmdline, sizeof(command_line)); 465#ifdef CONFIG_CMDLINE_BOOL
480 strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE); 466#ifdef CONFIG_CMDLINE_OVERRIDE
467 strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE);
468#else
469 if (builtin_cmdline[0]) {
470 strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
471 strlcat(arcs_cmdline, builtin_cmdline, COMMAND_LINE_SIZE);
472 }
473 strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
474#endif
475#else
476 strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
477#endif
478 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
481 479
482 *cmdline_p = command_line; 480 *cmdline_p = command_line;
483 481
diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
index 6254041b942f..d0c68b5d717b 100644
--- a/arch/mips/kernel/signal.c
+++ b/arch/mips/kernel/signal.c
@@ -35,6 +35,15 @@
35 35
36#include "signal-common.h" 36#include "signal-common.h"
37 37
38static int (*save_fp_context)(struct sigcontext __user *sc);
39static int (*restore_fp_context)(struct sigcontext __user *sc);
40
41extern asmlinkage int _save_fp_context(struct sigcontext __user *sc);
42extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc);
43
44extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc);
45extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc);
46
38/* 47/*
39 * Horribly complicated - with the bloody RM9000 workarounds enabled 48 * Horribly complicated - with the bloody RM9000 workarounds enabled
40 * the signal trampolines is moving to the end of the structure so we can 49 * the signal trampolines is moving to the end of the structure so we can
@@ -709,3 +718,40 @@ asmlinkage void do_notify_resume(struct pt_regs *regs, void *unused,
709 key_replace_session_keyring(); 718 key_replace_session_keyring();
710 } 719 }
711} 720}
721
722#ifdef CONFIG_SMP
723static int smp_save_fp_context(struct sigcontext __user *sc)
724{
725 return raw_cpu_has_fpu
726 ? _save_fp_context(sc)
727 : fpu_emulator_save_context(sc);
728}
729
730static int smp_restore_fp_context(struct sigcontext __user *sc)
731{
732 return raw_cpu_has_fpu
733 ? _restore_fp_context(sc)
734 : fpu_emulator_restore_context(sc);
735}
736#endif
737
738static int signal_setup(void)
739{
740#ifdef CONFIG_SMP
741 /* For now just do the cpu_has_fpu check when the functions are invoked */
742 save_fp_context = smp_save_fp_context;
743 restore_fp_context = smp_restore_fp_context;
744#else
745 if (cpu_has_fpu) {
746 save_fp_context = _save_fp_context;
747 restore_fp_context = _restore_fp_context;
748 } else {
749 save_fp_context = fpu_emulator_save_context;
750 restore_fp_context = fpu_emulator_restore_context;
751 }
752#endif
753
754 return 0;
755}
756
757arch_initcall(signal_setup);
diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c
index 2e74075ac0ca..03abaf048f09 100644
--- a/arch/mips/kernel/signal32.c
+++ b/arch/mips/kernel/signal32.c
@@ -35,6 +35,15 @@
35 35
36#include "signal-common.h" 36#include "signal-common.h"
37 37
38static int (*save_fp_context32)(struct sigcontext32 __user *sc);
39static int (*restore_fp_context32)(struct sigcontext32 __user *sc);
40
41extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc);
42extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc);
43
44extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc);
45extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc);
46
38/* 47/*
39 * Including <asm/unistd.h> would give use the 64-bit syscall numbers ... 48 * Including <asm/unistd.h> would give use the 64-bit syscall numbers ...
40 */ 49 */
@@ -828,3 +837,18 @@ SYSCALL_DEFINE5(32_waitid, int, which, compat_pid_t, pid,
828 info.si_code |= __SI_CHLD; 837 info.si_code |= __SI_CHLD;
829 return copy_siginfo_to_user32(uinfo, &info); 838 return copy_siginfo_to_user32(uinfo, &info);
830} 839}
840
841static int signal32_init(void)
842{
843 if (cpu_has_fpu) {
844 save_fp_context32 = _save_fp_context32;
845 restore_fp_context32 = _restore_fp_context32;
846 } else {
847 save_fp_context32 = fpu_emulator_save_context32;
848 restore_fp_context32 = fpu_emulator_restore_context32;
849 }
850
851 return 0;
852}
853
854arch_initcall(signal32_init);
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index e72e6844d134..6cdca1956b77 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -32,6 +32,7 @@
32#include <linux/cpumask.h> 32#include <linux/cpumask.h>
33#include <linux/cpu.h> 33#include <linux/cpu.h>
34#include <linux/err.h> 34#include <linux/err.h>
35#include <linux/ftrace.h>
35 36
36#include <asm/atomic.h> 37#include <asm/atomic.h>
37#include <asm/cpu.h> 38#include <asm/cpu.h>
@@ -130,7 +131,7 @@ asmlinkage __cpuinit void start_secondary(void)
130/* 131/*
131 * Call into both interrupt handlers, as we share the IPI for them 132 * Call into both interrupt handlers, as we share the IPI for them
132 */ 133 */
133void smp_call_function_interrupt(void) 134void __irq_entry smp_call_function_interrupt(void)
134{ 135{
135 irq_enter(); 136 irq_enter();
136 generic_smp_call_function_single_interrupt(); 137 generic_smp_call_function_single_interrupt();
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index a38e3ee95515..23499b5bd9c3 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -25,6 +25,7 @@
25#include <linux/interrupt.h> 25#include <linux/interrupt.h>
26#include <linux/kernel_stat.h> 26#include <linux/kernel_stat.h>
27#include <linux/module.h> 27#include <linux/module.h>
28#include <linux/ftrace.h>
28 29
29#include <asm/cpu.h> 30#include <asm/cpu.h>
30#include <asm/processor.h> 31#include <asm/processor.h>
@@ -939,23 +940,29 @@ static void ipi_call_interrupt(void)
939 940
940DECLARE_PER_CPU(struct clock_event_device, mips_clockevent_device); 941DECLARE_PER_CPU(struct clock_event_device, mips_clockevent_device);
941 942
942void ipi_decode(struct smtc_ipi *pipi) 943static void __irq_entry smtc_clock_tick_interrupt(void)
943{ 944{
944 unsigned int cpu = smp_processor_id(); 945 unsigned int cpu = smp_processor_id();
945 struct clock_event_device *cd; 946 struct clock_event_device *cd;
947 int irq = MIPS_CPU_IRQ_BASE + 1;
948
949 irq_enter();
950 kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq));
951 cd = &per_cpu(mips_clockevent_device, cpu);
952 cd->event_handler(cd);
953 irq_exit();
954}
955
956void ipi_decode(struct smtc_ipi *pipi)
957{
946 void *arg_copy = pipi->arg; 958 void *arg_copy = pipi->arg;
947 int type_copy = pipi->type; 959 int type_copy = pipi->type;
948 int irq = MIPS_CPU_IRQ_BASE + 1;
949 960
950 smtc_ipi_nq(&freeIPIq, pipi); 961 smtc_ipi_nq(&freeIPIq, pipi);
951 962
952 switch (type_copy) { 963 switch (type_copy) {
953 case SMTC_CLOCK_TICK: 964 case SMTC_CLOCK_TICK:
954 irq_enter(); 965 smtc_clock_tick_interrupt();
955 kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq));
956 cd = &per_cpu(mips_clockevent_device, cpu);
957 cd->event_handler(cd);
958 irq_exit();
959 break; 966 break;
960 967
961 case LINUX_SMP_IPI: 968 case LINUX_SMP_IPI:
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 0a18b4c62afb..308e43460864 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -25,10 +25,12 @@
25#include <linux/ptrace.h> 25#include <linux/ptrace.h>
26#include <linux/kgdb.h> 26#include <linux/kgdb.h>
27#include <linux/kdebug.h> 27#include <linux/kdebug.h>
28#include <linux/notifier.h>
28 29
29#include <asm/bootinfo.h> 30#include <asm/bootinfo.h>
30#include <asm/branch.h> 31#include <asm/branch.h>
31#include <asm/break.h> 32#include <asm/break.h>
33#include <asm/cop2.h>
32#include <asm/cpu.h> 34#include <asm/cpu.h>
33#include <asm/dsp.h> 35#include <asm/dsp.h>
34#include <asm/fpu.h> 36#include <asm/fpu.h>
@@ -79,10 +81,6 @@ extern asmlinkage void handle_reserved(void);
79extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, 81extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
80 struct mips_fpu_struct *ctx, int has_fpu); 82 struct mips_fpu_struct *ctx, int has_fpu);
81 83
82#ifdef CONFIG_CPU_CAVIUM_OCTEON
83extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task);
84#endif
85
86void (*board_be_init)(void); 84void (*board_be_init)(void);
87int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 85int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
88void (*board_nmi_handler_setup)(void); 86void (*board_nmi_handler_setup)(void);
@@ -857,6 +855,44 @@ static void mt_ase_fp_affinity(void)
857#endif /* CONFIG_MIPS_MT_FPAFF */ 855#endif /* CONFIG_MIPS_MT_FPAFF */
858} 856}
859 857
858/*
859 * No lock; only written during early bootup by CPU 0.
860 */
861static RAW_NOTIFIER_HEAD(cu2_chain);
862
863int __ref register_cu2_notifier(struct notifier_block *nb)
864{
865 return raw_notifier_chain_register(&cu2_chain, nb);
866}
867
868int cu2_notifier_call_chain(unsigned long val, void *v)
869{
870 return raw_notifier_call_chain(&cu2_chain, val, v);
871}
872
873static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
874 void *data)
875{
876 struct pt_regs *regs = data;
877
878 switch (action) {
879 default:
880 die_if_kernel("Unhandled kernel unaligned access or invalid "
881 "instruction", regs);
882 /* Fall through */
883
884 case CU2_EXCEPTION:
885 force_sig(SIGILL, current);
886 }
887
888 return NOTIFY_OK;
889}
890
891static struct notifier_block default_cu2_notifier = {
892 .notifier_call = default_cu2_call,
893 .priority = 0x80000000, /* Run last */
894};
895
860asmlinkage void do_cpu(struct pt_regs *regs) 896asmlinkage void do_cpu(struct pt_regs *regs)
861{ 897{
862 unsigned int __user *epc; 898 unsigned int __user *epc;
@@ -920,17 +956,9 @@ asmlinkage void do_cpu(struct pt_regs *regs)
920 return; 956 return;
921 957
922 case 2: 958 case 2:
923#ifdef CONFIG_CPU_CAVIUM_OCTEON 959 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
924 prefetch(&current->thread.cp2); 960 break;
925 local_irq_save(flags); 961
926 KSTK_STATUS(current) |= ST0_CU2;
927 status = read_c0_status();
928 write_c0_status(status | ST0_CU2);
929 octeon_cop2_restore(&(current->thread.cp2));
930 write_c0_status(status & ~ST0_CU2);
931 local_irq_restore(flags);
932 return;
933#endif
934 case 3: 962 case 3:
935 break; 963 break;
936 } 964 }
@@ -1367,77 +1395,6 @@ void *set_vi_handler(int n, vi_handler_t addr)
1367 return set_vi_srs_handler(n, addr, 0); 1395 return set_vi_srs_handler(n, addr, 0);
1368} 1396}
1369 1397
1370/*
1371 * This is used by native signal handling
1372 */
1373asmlinkage int (*save_fp_context)(struct sigcontext __user *sc);
1374asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc);
1375
1376extern asmlinkage int _save_fp_context(struct sigcontext __user *sc);
1377extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc);
1378
1379extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc);
1380extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc);
1381
1382#ifdef CONFIG_SMP
1383static int smp_save_fp_context(struct sigcontext __user *sc)
1384{
1385 return raw_cpu_has_fpu
1386 ? _save_fp_context(sc)
1387 : fpu_emulator_save_context(sc);
1388}
1389
1390static int smp_restore_fp_context(struct sigcontext __user *sc)
1391{
1392 return raw_cpu_has_fpu
1393 ? _restore_fp_context(sc)
1394 : fpu_emulator_restore_context(sc);
1395}
1396#endif
1397
1398static inline void signal_init(void)
1399{
1400#ifdef CONFIG_SMP
1401 /* For now just do the cpu_has_fpu check when the functions are invoked */
1402 save_fp_context = smp_save_fp_context;
1403 restore_fp_context = smp_restore_fp_context;
1404#else
1405 if (cpu_has_fpu) {
1406 save_fp_context = _save_fp_context;
1407 restore_fp_context = _restore_fp_context;
1408 } else {
1409 save_fp_context = fpu_emulator_save_context;
1410 restore_fp_context = fpu_emulator_restore_context;
1411 }
1412#endif
1413}
1414
1415#ifdef CONFIG_MIPS32_COMPAT
1416
1417/*
1418 * This is used by 32-bit signal stuff on the 64-bit kernel
1419 */
1420asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc);
1421asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc);
1422
1423extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc);
1424extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc);
1425
1426extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc);
1427extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc);
1428
1429static inline void signal32_init(void)
1430{
1431 if (cpu_has_fpu) {
1432 save_fp_context32 = _save_fp_context32;
1433 restore_fp_context32 = _restore_fp_context32;
1434 } else {
1435 save_fp_context32 = fpu_emulator_save_context32;
1436 restore_fp_context32 = fpu_emulator_restore_context32;
1437 }
1438}
1439#endif
1440
1441extern void cpu_cache_init(void); 1398extern void cpu_cache_init(void);
1442extern void tlb_init(void); 1399extern void tlb_init(void);
1443extern void flush_tlb_handlers(void); 1400extern void flush_tlb_handlers(void);
@@ -1751,13 +1708,10 @@ void __init trap_init(void)
1751 else 1708 else
1752 memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80); 1709 memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80);
1753 1710
1754 signal_init();
1755#ifdef CONFIG_MIPS32_COMPAT
1756 signal32_init();
1757#endif
1758
1759 local_flush_icache_range(ebase, ebase + 0x400); 1711 local_flush_icache_range(ebase, ebase + 0x400);
1760 flush_tlb_handlers(); 1712 flush_tlb_handlers();
1761 1713
1762 sort_extable(__start___dbe_table, __stop___dbe_table); 1714 sort_extable(__start___dbe_table, __stop___dbe_table);
1715
1716 register_cu2_notifier(&default_cu2_notifier);
1763} 1717}
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index 67bd626942ab..69b039ca8d83 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -81,6 +81,7 @@
81#include <asm/asm.h> 81#include <asm/asm.h>
82#include <asm/branch.h> 82#include <asm/branch.h>
83#include <asm/byteorder.h> 83#include <asm/byteorder.h>
84#include <asm/cop2.h>
84#include <asm/inst.h> 85#include <asm/inst.h>
85#include <asm/uaccess.h> 86#include <asm/uaccess.h>
86#include <asm/system.h> 87#include <asm/system.h>
@@ -451,17 +452,27 @@ static void emulate_load_store_insn(struct pt_regs *regs,
451 */ 452 */
452 goto sigbus; 453 goto sigbus;
453 454
455 /*
456 * COP2 is available to implementor for application specific use.
457 * It's up to applications to register a notifier chain and do
458 * whatever they have to do, including possible sending of signals.
459 */
454 case lwc2_op: 460 case lwc2_op:
461 cu2_notifier_call_chain(CU2_LWC2_OP, regs);
462 break;
463
455 case ldc2_op: 464 case ldc2_op:
465 cu2_notifier_call_chain(CU2_LDC2_OP, regs);
466 break;
467
456 case swc2_op: 468 case swc2_op:
469 cu2_notifier_call_chain(CU2_SWC2_OP, regs);
470 break;
471
457 case sdc2_op: 472 case sdc2_op:
458 /* 473 cu2_notifier_call_chain(CU2_SDC2_OP, regs);
459 * These are the coprocessor 2 load/stores. The current 474 break;
460 * implementations don't use cp2 and cp2 should always be 475
461 * disabled in c0_status. So send SIGILL.
462 * (No longer true: The Sony Praystation uses cp2 for
463 * 3D matrix operations. Dunno if that thingy has a MMU ...)
464 */
465 default: 476 default:
466 /* 477 /*
467 * Pheeee... We encountered an yet unknown instruction or 478 * Pheeee... We encountered an yet unknown instruction or
diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
index 162b29954baa..f25df73db923 100644
--- a/arch/mips/kernel/vmlinux.lds.S
+++ b/arch/mips/kernel/vmlinux.lds.S
@@ -46,6 +46,7 @@ SECTIONS
46 SCHED_TEXT 46 SCHED_TEXT
47 LOCK_TEXT 47 LOCK_TEXT
48 KPROBES_TEXT 48 KPROBES_TEXT
49 IRQENTRY_TEXT
49 *(.text.*) 50 *(.text.*)
50 *(.fixup) 51 *(.fixup)
51 *(.gnu.warning) 52 *(.gnu.warning)
diff --git a/arch/mips/lasat/picvue_proc.c b/arch/mips/lasat/picvue_proc.c
index 0bb6037afba3..8e388da1926f 100644
--- a/arch/mips/lasat/picvue_proc.c
+++ b/arch/mips/lasat/picvue_proc.c
@@ -4,12 +4,14 @@
4 * Brian Murphy <brian.murphy@eicon.com> 4 * Brian Murphy <brian.murphy@eicon.com>
5 * 5 *
6 */ 6 */
7#include <linux/bug.h>
7#include <linux/kernel.h> 8#include <linux/kernel.h>
8#include <linux/module.h> 9#include <linux/module.h>
9#include <linux/init.h> 10#include <linux/init.h>
10#include <linux/errno.h> 11#include <linux/errno.h>
11 12
12#include <linux/proc_fs.h> 13#include <linux/proc_fs.h>
14#include <linux/seq_file.h>
13#include <linux/interrupt.h> 15#include <linux/interrupt.h>
14 16
15#include <linux/timer.h> 17#include <linux/timer.h>
@@ -38,12 +40,9 @@ static void pvc_display(unsigned long data)
38 40
39static DECLARE_TASKLET(pvc_display_tasklet, &pvc_display, 0); 41static DECLARE_TASKLET(pvc_display_tasklet, &pvc_display, 0);
40 42
41static int pvc_proc_read_line(char *page, char **start, 43static int pvc_line_proc_show(struct seq_file *m, void *v)
42 off_t off, int count,
43 int *eof, void *data)
44{ 44{
45 char *origpage = page; 45 int lineno = *(int *)m->private;
46 int lineno = *(int *)data;
47 46
48 if (lineno < 0 || lineno > PVC_NLINES) { 47 if (lineno < 0 || lineno > PVC_NLINES) {
49 printk(KERN_WARNING "proc_read_line: invalid lineno %d\n", lineno); 48 printk(KERN_WARNING "proc_read_line: invalid lineno %d\n", lineno);
@@ -51,45 +50,66 @@ static int pvc_proc_read_line(char *page, char **start,
51 } 50 }
52 51
53 mutex_lock(&pvc_mutex); 52 mutex_lock(&pvc_mutex);
54 page += sprintf(page, "%s\n", pvc_lines[lineno]); 53 seq_printf(m, "%s\n", pvc_lines[lineno]);
55 mutex_unlock(&pvc_mutex); 54 mutex_unlock(&pvc_mutex);
56 55
57 return page - origpage; 56 return 0;
58} 57}
59 58
60static int pvc_proc_write_line(struct file *file, const char *buffer, 59static int pvc_line_proc_open(struct inode *inode, struct file *file)
61 unsigned long count, void *data)
62{ 60{
63 int origcount = count; 61 return single_open(file, pvc_line_proc_show, PDE(inode)->data);
64 int lineno = *(int *)data; 62}
65 63
66 if (lineno < 0 || lineno > PVC_NLINES) { 64static ssize_t pvc_line_proc_write(struct file *file, const char __user *buf,
67 printk(KERN_WARNING "proc_write_line: invalid lineno %d\n", 65 size_t count, loff_t *pos)
68 lineno); 66{
69 return origcount; 67 int lineno = *(int *)PDE(file->f_path.dentry->d_inode)->data;
70 } 68 char kbuf[PVC_LINELEN];
69 size_t len;
70
71 BUG_ON(lineno < 0 || lineno > PVC_NLINES);
71 72
72 if (count > PVC_LINELEN) 73 len = min(count, sizeof(kbuf) - 1);
73 count = PVC_LINELEN; 74 if (copy_from_user(kbuf, buf, len))
75 return -EFAULT;
76 kbuf[len] = '\0';
74 77
75 if (buffer[count-1] == '\n') 78 if (len > 0 && kbuf[len - 1] == '\n')
76 count--; 79 len--;
77 80
78 mutex_lock(&pvc_mutex); 81 mutex_lock(&pvc_mutex);
79 strncpy(pvc_lines[lineno], buffer, count); 82 strncpy(pvc_lines[lineno], kbuf, len);
80 pvc_lines[lineno][count] = '\0'; 83 pvc_lines[lineno][len] = '\0';
81 mutex_unlock(&pvc_mutex); 84 mutex_unlock(&pvc_mutex);
82 85
83 tasklet_schedule(&pvc_display_tasklet); 86 tasklet_schedule(&pvc_display_tasklet);
84 87
85 return origcount; 88 return count;
86} 89}
87 90
88static int pvc_proc_write_scroll(struct file *file, const char *buffer, 91static const struct file_operations pvc_line_proc_fops = {
89 unsigned long count, void *data) 92 .owner = THIS_MODULE,
93 .open = pvc_line_proc_open,
94 .read = seq_read,
95 .llseek = seq_lseek,
96 .release = single_release,
97 .write = pvc_line_proc_write,
98};
99
100static ssize_t pvc_scroll_proc_write(struct file *file, const char __user *buf,
101 size_t count, loff_t *pos)
90{ 102{
91 int origcount = count; 103 char kbuf[42];
92 int cmd = simple_strtol(buffer, NULL, 10); 104 size_t len;
105 int cmd;
106
107 len = min(count, sizeof(kbuf) - 1);
108 if (copy_from_user(kbuf, buf, len))
109 return -EFAULT;
110 kbuf[len] = '\0';
111
112 cmd = simple_strtol(kbuf, NULL, 10);
93 113
94 mutex_lock(&pvc_mutex); 114 mutex_lock(&pvc_mutex);
95 if (scroll_interval != 0) 115 if (scroll_interval != 0)
@@ -110,22 +130,31 @@ static int pvc_proc_write_scroll(struct file *file, const char *buffer,
110 } 130 }
111 mutex_unlock(&pvc_mutex); 131 mutex_unlock(&pvc_mutex);
112 132
113 return origcount; 133 return count;
114} 134}
115 135
116static int pvc_proc_read_scroll(char *page, char **start, 136static int pvc_scroll_proc_show(struct seq_file *m, void *v)
117 off_t off, int count,
118 int *eof, void *data)
119{ 137{
120 char *origpage = page;
121
122 mutex_lock(&pvc_mutex); 138 mutex_lock(&pvc_mutex);
123 page += sprintf(page, "%d\n", scroll_dir * scroll_interval); 139 seq_printf(m, "%d\n", scroll_dir * scroll_interval);
124 mutex_unlock(&pvc_mutex); 140 mutex_unlock(&pvc_mutex);
125 141
126 return page - origpage; 142 return 0;
127} 143}
128 144
145static int pvc_scroll_proc_open(struct inode *inode, struct file *file)
146{
147 return single_open(file, pvc_scroll_proc_show, NULL);
148}
149
150static const struct file_operations pvc_scroll_proc_fops = {
151 .owner = THIS_MODULE,
152 .open = pvc_scroll_proc_open,
153 .read = seq_read,
154 .llseek = seq_lseek,
155 .release = single_release,
156 .write = pvc_scroll_proc_write,
157};
129 158
130void pvc_proc_timerfunc(unsigned long data) 159void pvc_proc_timerfunc(unsigned long data)
131{ 160{
@@ -163,22 +192,16 @@ static int __init pvc_proc_init(void)
163 pvc_linedata[i] = i; 192 pvc_linedata[i] = i;
164 } 193 }
165 for (i = 0; i < PVC_NLINES; i++) { 194 for (i = 0; i < PVC_NLINES; i++) {
166 proc_entry = create_proc_entry(pvc_linename[i], 0644, 195 proc_entry = proc_create_data(pvc_linename[i], 0644, pvc_display_dir,
167 pvc_display_dir); 196 &pvc_line_proc_fops, &pvc_linedata[i]);
168 if (proc_entry == NULL) 197 if (proc_entry == NULL)
169 goto error; 198 goto error;
170
171 proc_entry->read_proc = pvc_proc_read_line;
172 proc_entry->write_proc = pvc_proc_write_line;
173 proc_entry->data = &pvc_linedata[i];
174 } 199 }
175 proc_entry = create_proc_entry("scroll", 0644, pvc_display_dir); 200 proc_entry = proc_create("scroll", 0644, pvc_display_dir,
201 &pvc_scroll_proc_fops);
176 if (proc_entry == NULL) 202 if (proc_entry == NULL)
177 goto error; 203 goto error;
178 204
179 proc_entry->write_proc = pvc_proc_write_scroll;
180 proc_entry->read_proc = pvc_proc_read_scroll;
181
182 init_timer(&timer); 205 init_timer(&timer);
183 timer.function = pvc_proc_timerfunc; 206 timer.function = pvc_proc_timerfunc;
184 207
diff --git a/arch/mips/lasat/prom.c b/arch/mips/lasat/prom.c
index 6acc6cb85f0a..20fde19a5fbf 100644
--- a/arch/mips/lasat/prom.c
+++ b/arch/mips/lasat/prom.c
@@ -100,8 +100,8 @@ void __init prom_init(void)
100 100
101 /* Get the command line */ 101 /* Get the command line */
102 if (argc > 0) { 102 if (argc > 0) {
103 strncpy(arcs_cmdline, argv[0], CL_SIZE-1); 103 strncpy(arcs_cmdline, argv[0], COMMAND_LINE_SIZE-1);
104 arcs_cmdline[CL_SIZE-1] = '\0'; 104 arcs_cmdline[COMMAND_LINE_SIZE-1] = '\0';
105 } 105 }
106 106
107 /* Set the I/O base address */ 107 /* Set the I/O base address */
diff --git a/arch/mips/lasat/sysctl.c b/arch/mips/lasat/sysctl.c
index 14b9a28a4aec..d87ffd04cb0a 100644
--- a/arch/mips/lasat/sysctl.c
+++ b/arch/mips/lasat/sysctl.c
@@ -204,7 +204,7 @@ static ctl_table lasat_table[] = {
204 .maxlen = sizeof(int), 204 .maxlen = sizeof(int),
205 .mode = 0644, 205 .mode = 0644,
206 .proc_handler = proc_lasat_prid, 206 .proc_handler = proc_lasat_prid,
207. }, 207 },
208#ifdef CONFIG_INET 208#ifdef CONFIG_INET
209 { 209 {
210 .procname = "ipaddr", 210 .procname = "ipaddr",
diff --git a/arch/mips/loongson/Kconfig b/arch/mips/loongson/Kconfig
index d45092505fa1..3df1967dea08 100644
--- a/arch/mips/loongson/Kconfig
+++ b/arch/mips/loongson/Kconfig
@@ -1,31 +1,85 @@
1choice 1choice
2 prompt "Machine Type" 2 prompt "Machine Type"
3 depends on MACH_LOONGSON 3 depends on MACH_LOONGSON
4 4
5config LEMOTE_FULOONG2E 5config LEMOTE_FULOONG2E
6 bool "Lemote Fuloong(2e) mini-PC" 6 bool "Lemote Fuloong(2e) mini-PC"
7 select ARCH_SPARSEMEM_ENABLE 7 select ARCH_SPARSEMEM_ENABLE
8 select CEVT_R4K 8 select CEVT_R4K
9 select CSRC_R4K 9 select CSRC_R4K
10 select SYS_HAS_CPU_LOONGSON2E 10 select SYS_HAS_CPU_LOONGSON2E
11 select DMA_NONCOHERENT 11 select DMA_NONCOHERENT
12 select BOOT_ELF32 12 select BOOT_ELF32
13 select BOARD_SCACHE 13 select BOARD_SCACHE
14 select HW_HAS_PCI 14 select HW_HAS_PCI
15 select I8259 15 select I8259
16 select ISA 16 select ISA
17 select IRQ_CPU 17 select IRQ_CPU
18 select SYS_SUPPORTS_32BIT_KERNEL 18 select SYS_SUPPORTS_32BIT_KERNEL
19 select SYS_SUPPORTS_64BIT_KERNEL 19 select SYS_SUPPORTS_64BIT_KERNEL
20 select SYS_SUPPORTS_LITTLE_ENDIAN 20 select SYS_SUPPORTS_LITTLE_ENDIAN
21 select SYS_SUPPORTS_HIGHMEM 21 select SYS_SUPPORTS_HIGHMEM
22 select SYS_HAS_EARLY_PRINTK 22 select SYS_HAS_EARLY_PRINTK
23 select GENERIC_HARDIRQS_NO__DO_IRQ 23 select GENERIC_HARDIRQS_NO__DO_IRQ
24 select GENERIC_ISA_DMA_SUPPORT_BROKEN 24 select GENERIC_ISA_DMA_SUPPORT_BROKEN
25 select CPU_HAS_WB 25 select CPU_HAS_WB
26 help 26 help
27 Lemote Fuloong(2e) mini-PC board based on the Chinese Loongson-2E CPU and 27 Lemote Fuloong(2e) mini-PC board based on the Chinese Loongson-2E CPU and
28 an FPGA northbridge 28 an FPGA northbridge
29 29
30 Lemote Fuloong(2e) mini PC have a VIA686B south bridge. 30 Lemote Fuloong(2e) mini PC have a VIA686B south bridge.
31
32config LEMOTE_MACH2F
33 bool "Lemote Loongson 2F family machines"
34 select ARCH_SPARSEMEM_ENABLE
35 select BOARD_SCACHE
36 select BOOT_ELF32
37 select CEVT_R4K if ! MIPS_EXTERNAL_TIMER
38 select CPU_HAS_WB
39 select CS5536
40 select CSRC_R4K if ! MIPS_EXTERNAL_TIMER
41 select DMA_NONCOHERENT
42 select GENERIC_HARDIRQS_NO__DO_IRQ
43 select GENERIC_ISA_DMA_SUPPORT_BROKEN
44 select HW_HAS_PCI
45 select I8259
46 select IRQ_CPU
47 select ISA
48 select SYS_HAS_CPU_LOONGSON2F
49 select SYS_HAS_EARLY_PRINTK
50 select SYS_SUPPORTS_32BIT_KERNEL
51 select SYS_SUPPORTS_64BIT_KERNEL
52 select SYS_SUPPORTS_HIGHMEM
53 select SYS_SUPPORTS_LITTLE_ENDIAN
54 help
55 Lemote Loongson 2F family machines utilize the 2F revision of
56 Loongson processor and the AMD CS5536 south bridge.
57
58 These family machines include fuloong2f mini PC, yeeloong2f notebook,
59 LingLoong allinone PC and so forth.
31endchoice 60endchoice
61
62config CS5536
63 bool
64
65config CS5536_MFGPT
66 bool "CS5536 MFGPT Timer"
67 depends on CS5536
68 select MIPS_EXTERNAL_TIMER
69 help
70 This option enables the mfgpt0 timer of AMD CS5536.
71
72 If you want to enable the Loongson2 CPUFreq Driver, Please enable
73 this option at first, otherwise, You will get wrong system time.
74
75 If unsure, say Yes.
76
77config LOONGSON_SUSPEND
78 bool
79 default y
80 depends on CPU_SUPPORTS_CPUFREQ && SUSPEND
81
82config LOONGSON_UART_BASE
83 bool
84 default y
85 depends on EARLY_PRINTK || SERIAL_8250
diff --git a/arch/mips/loongson/Makefile b/arch/mips/loongson/Makefile
index 39048c455d7d..2b76cb0fb07d 100644
--- a/arch/mips/loongson/Makefile
+++ b/arch/mips/loongson/Makefile
@@ -9,3 +9,9 @@ obj-$(CONFIG_MACH_LOONGSON) += common/
9# 9#
10 10
11obj-$(CONFIG_LEMOTE_FULOONG2E) += fuloong-2e/ 11obj-$(CONFIG_LEMOTE_FULOONG2E) += fuloong-2e/
12
13#
14# Lemote loongson2f family machines
15#
16
17obj-$(CONFIG_LEMOTE_MACH2F) += lemote-2f/
diff --git a/arch/mips/loongson/common/Makefile b/arch/mips/loongson/common/Makefile
index 656b3cc0a2a6..7668c4de1151 100644
--- a/arch/mips/loongson/common/Makefile
+++ b/arch/mips/loongson/common/Makefile
@@ -3,9 +3,23 @@
3# 3#
4 4
5obj-y += setup.o init.o cmdline.o env.o time.o reset.o irq.o \ 5obj-y += setup.o init.o cmdline.o env.o time.o reset.o irq.o \
6 pci.o bonito-irq.o mem.o machtype.o 6 pci.o bonito-irq.o mem.o machtype.o platform.o
7 7
8# 8#
9# Early printk support 9# Serial port support
10# 10#
11obj-$(CONFIG_EARLY_PRINTK) += early_printk.o 11obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
12obj-$(CONFIG_SERIAL_8250) += serial.o
13obj-$(CONFIG_LOONGSON_UART_BASE) += uart_base.o
14
15#
16# Enable CS5536 Virtual Support Module(VSM) to virtulize the PCI configure
17# space
18#
19obj-$(CONFIG_CS5536) += cs5536/
20
21#
22# Suspend Support
23#
24
25obj-$(CONFIG_LOONGSON_SUSPEND) += pm.o
diff --git a/arch/mips/loongson/common/bonito-irq.c b/arch/mips/loongson/common/bonito-irq.c
index 3e31e7ad713e..2dc2a4cc632a 100644
--- a/arch/mips/loongson/common/bonito-irq.c
+++ b/arch/mips/loongson/common/bonito-irq.c
@@ -12,18 +12,19 @@
12 * option) any later version. 12 * option) any later version.
13 */ 13 */
14#include <linux/interrupt.h> 14#include <linux/interrupt.h>
15#include <linux/compiler.h>
15 16
16#include <loongson.h> 17#include <loongson.h>
17 18
18static inline void bonito_irq_enable(unsigned int irq) 19static inline void bonito_irq_enable(unsigned int irq)
19{ 20{
20 BONITO_INTENSET = (1 << (irq - BONITO_IRQ_BASE)); 21 LOONGSON_INTENSET = (1 << (irq - LOONGSON_IRQ_BASE));
21 mmiowb(); 22 mmiowb();
22} 23}
23 24
24static inline void bonito_irq_disable(unsigned int irq) 25static inline void bonito_irq_disable(unsigned int irq)
25{ 26{
26 BONITO_INTENCLR = (1 << (irq - BONITO_IRQ_BASE)); 27 LOONGSON_INTENCLR = (1 << (irq - LOONGSON_IRQ_BASE));
27 mmiowb(); 28 mmiowb();
28} 29}
29 30
@@ -35,7 +36,7 @@ static struct irq_chip bonito_irq_type = {
35 .unmask = bonito_irq_enable, 36 .unmask = bonito_irq_enable,
36}; 37};
37 38
38static struct irqaction dma_timeout_irqaction = { 39static struct irqaction __maybe_unused dma_timeout_irqaction = {
39 .handler = no_action, 40 .handler = no_action,
40 .name = "dma_timeout", 41 .name = "dma_timeout",
41}; 42};
@@ -44,8 +45,10 @@ void bonito_irq_init(void)
44{ 45{
45 u32 i; 46 u32 i;
46 47
47 for (i = BONITO_IRQ_BASE; i < BONITO_IRQ_BASE + 32; i++) 48 for (i = LOONGSON_IRQ_BASE; i < LOONGSON_IRQ_BASE + 32; i++)
48 set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq); 49 set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq);
49 50
50 setup_irq(BONITO_IRQ_BASE + 10, &dma_timeout_irqaction); 51#ifdef CONFIG_CPU_LOONGSON2E
52 setup_irq(LOONGSON_IRQ_BASE + 10, &dma_timeout_irqaction);
53#endif
51} 54}
diff --git a/arch/mips/loongson/common/cmdline.c b/arch/mips/loongson/common/cmdline.c
index 75f1b243ee4e..7ad47f227477 100644
--- a/arch/mips/loongson/common/cmdline.c
+++ b/arch/mips/loongson/common/cmdline.c
@@ -9,7 +9,7 @@
9 * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology 9 * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
10 * Author: Fuxin Zhang, zhangfx@lemote.com 10 * Author: Fuxin Zhang, zhangfx@lemote.com
11 * 11 *
12 * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology 12 * Copyright (C) 2009 Lemote Inc.
13 * Author: Wu Zhangjin, wuzj@lemote.com 13 * Author: Wu Zhangjin, wuzj@lemote.com
14 * 14 *
15 * This program is free software; you can redistribute it and/or modify it 15 * This program is free software; you can redistribute it and/or modify it
@@ -49,4 +49,6 @@ void __init prom_init_cmdline(void)
49 strcat(arcs_cmdline, " console=ttyS0,115200"); 49 strcat(arcs_cmdline, " console=ttyS0,115200");
50 if ((strstr(arcs_cmdline, "root=")) == NULL) 50 if ((strstr(arcs_cmdline, "root=")) == NULL)
51 strcat(arcs_cmdline, " root=/dev/hda1"); 51 strcat(arcs_cmdline, " root=/dev/hda1");
52
53 prom_init_machtype();
52} 54}
diff --git a/arch/mips/loongson/common/cs5536/Makefile b/arch/mips/loongson/common/cs5536/Makefile
new file mode 100644
index 000000000000..510d4cdc2378
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/Makefile
@@ -0,0 +1,13 @@
1#
2# Makefile for CS5536 support.
3#
4
5obj-$(CONFIG_CS5536) += cs5536_pci.o cs5536_ide.o cs5536_acc.o cs5536_ohci.o \
6 cs5536_isa.o cs5536_ehci.o
7
8#
9# Enable cs5536 mfgpt Timer
10#
11obj-$(CONFIG_CS5536_MFGPT) += cs5536_mfgpt.o
12
13EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/loongson/common/cs5536/cs5536_acc.c b/arch/mips/loongson/common/cs5536/cs5536_acc.c
new file mode 100644
index 000000000000..b49485f187e0
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_acc.c
@@ -0,0 +1,140 @@
1/*
2 * the ACC Virtual Support Module of AMD CS5536
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu, liujl@lemote.com
6 *
7 * Copyright (C) 2009 Lemote, Inc.
8 * Author: Wu Zhangjin, wuzj@lemote.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <cs5536/cs5536.h>
17#include <cs5536/cs5536_pci.h>
18
19void pci_acc_write_reg(int reg, u32 value)
20{
21 u32 hi = 0, lo = value;
22
23 switch (reg) {
24 case PCI_COMMAND:
25 _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
26 if (value & PCI_COMMAND_MASTER)
27 lo |= (0x03 << 8);
28 else
29 lo &= ~(0x03 << 8);
30 _wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo);
31 break;
32 case PCI_STATUS:
33 if (value & PCI_STATUS_PARITY) {
34 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
35 if (lo & SB_PARE_ERR_FLAG) {
36 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
37 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
38 }
39 }
40 break;
41 case PCI_BAR0_REG:
42 if (value == PCI_BAR_RANGE_MASK) {
43 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
44 lo |= SOFT_BAR_ACC_FLAG;
45 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
46 } else if (value & 0x01) {
47 value &= 0xfffffffc;
48 hi = 0xA0000000 | ((value & 0x000ff000) >> 12);
49 lo = 0x000fff80 | ((value & 0x00000fff) << 20);
50 _wrmsr(GLIU_MSR_REG(GLIU_IOD_BM1), hi, lo);
51 }
52 break;
53 case PCI_ACC_INT_REG:
54 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
55 /* disable all the usb interrupt in PIC */
56 lo &= ~(0xf << PIC_YSEL_LOW_ACC_SHIFT);
57 if (value) /* enable all the acc interrupt in PIC */
58 lo |= (CS5536_ACC_INTR << PIC_YSEL_LOW_ACC_SHIFT);
59 _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo);
60 break;
61 default:
62 break;
63 }
64}
65
66u32 pci_acc_read_reg(int reg)
67{
68 u32 hi, lo;
69 u32 conf_data = 0;
70
71 switch (reg) {
72 case PCI_VENDOR_ID:
73 conf_data =
74 CFG_PCI_VENDOR_ID(CS5536_ACC_DEVICE_ID, CS5536_VENDOR_ID);
75 break;
76 case PCI_COMMAND:
77 _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo);
78 if (((lo & 0xfff00000) || (hi & 0x000000ff))
79 && ((hi & 0xf0000000) == 0xa0000000))
80 conf_data |= PCI_COMMAND_IO;
81 _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
82 if ((lo & 0x300) == 0x300)
83 conf_data |= PCI_COMMAND_MASTER;
84 break;
85 case PCI_STATUS:
86 conf_data |= PCI_STATUS_66MHZ;
87 conf_data |= PCI_STATUS_FAST_BACK;
88 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
89 if (lo & SB_PARE_ERR_FLAG)
90 conf_data |= PCI_STATUS_PARITY;
91 conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
92 break;
93 case PCI_CLASS_REVISION:
94 _rdmsr(ACC_MSR_REG(ACC_CAP), &hi, &lo);
95 conf_data = lo & 0x000000ff;
96 conf_data |= (CS5536_ACC_CLASS_CODE << 8);
97 break;
98 case PCI_CACHE_LINE_SIZE:
99 conf_data =
100 CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
101 PCI_NORMAL_LATENCY_TIMER);
102 break;
103 case PCI_BAR0_REG:
104 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
105 if (lo & SOFT_BAR_ACC_FLAG) {
106 conf_data = CS5536_ACC_RANGE |
107 PCI_BASE_ADDRESS_SPACE_IO;
108 lo &= ~SOFT_BAR_ACC_FLAG;
109 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
110 } else {
111 _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo);
112 conf_data = (hi & 0x000000ff) << 12;
113 conf_data |= (lo & 0xfff00000) >> 20;
114 conf_data |= 0x01;
115 conf_data &= ~0x02;
116 }
117 break;
118 case PCI_CARDBUS_CIS:
119 conf_data = PCI_CARDBUS_CIS_POINTER;
120 break;
121 case PCI_SUBSYSTEM_VENDOR_ID:
122 conf_data =
123 CFG_PCI_VENDOR_ID(CS5536_ACC_SUB_ID, CS5536_SUB_VENDOR_ID);
124 break;
125 case PCI_ROM_ADDRESS:
126 conf_data = PCI_EXPANSION_ROM_BAR;
127 break;
128 case PCI_CAPABILITY_LIST:
129 conf_data = PCI_CAPLIST_USB_POINTER;
130 break;
131 case PCI_INTERRUPT_LINE:
132 conf_data =
133 CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_ACC_INTR);
134 break;
135 default:
136 break;
137 }
138
139 return conf_data;
140}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_ehci.c b/arch/mips/loongson/common/cs5536/cs5536_ehci.c
new file mode 100644
index 000000000000..74f9c59d36af
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_ehci.c
@@ -0,0 +1,158 @@
1/*
2 * the EHCI Virtual Support Module of AMD CS5536
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu, liujl@lemote.com
6 *
7 * Copyright (C) 2009 Lemote, Inc.
8 * Author: Wu Zhangjin, wuzj@lemote.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <cs5536/cs5536.h>
17#include <cs5536/cs5536_pci.h>
18
19void pci_ehci_write_reg(int reg, u32 value)
20{
21 u32 hi = 0, lo = value;
22
23 switch (reg) {
24 case PCI_COMMAND:
25 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
26 if (value & PCI_COMMAND_MASTER)
27 hi |= PCI_COMMAND_MASTER;
28 else
29 hi &= ~PCI_COMMAND_MASTER;
30
31 if (value & PCI_COMMAND_MEMORY)
32 hi |= PCI_COMMAND_MEMORY;
33 else
34 hi &= ~PCI_COMMAND_MEMORY;
35 _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
36 break;
37 case PCI_STATUS:
38 if (value & PCI_STATUS_PARITY) {
39 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
40 if (lo & SB_PARE_ERR_FLAG) {
41 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
42 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
43 }
44 }
45 break;
46 case PCI_BAR0_REG:
47 if (value == PCI_BAR_RANGE_MASK) {
48 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
49 lo |= SOFT_BAR_EHCI_FLAG;
50 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
51 } else if ((value & 0x01) == 0x00) {
52 _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
53
54 value &= 0xfffffff0;
55 hi = 0x40000000 | ((value & 0xff000000) >> 24);
56 lo = 0x000fffff | ((value & 0x00fff000) << 8);
57 _wrmsr(GLIU_MSR_REG(GLIU_P2D_BM4), hi, lo);
58 }
59 break;
60 case PCI_EHCI_LEGSMIEN_REG:
61 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
62 hi &= 0x003f0000;
63 hi |= (value & 0x3f) << 16;
64 _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
65 break;
66 case PCI_EHCI_FLADJ_REG:
67 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
68 hi &= ~0x00003f00;
69 hi |= value & 0x00003f00;
70 _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
71 break;
72 default:
73 break;
74 }
75}
76
77u32 pci_ehci_read_reg(int reg)
78{
79 u32 conf_data = 0;
80 u32 hi, lo;
81
82 switch (reg) {
83 case PCI_VENDOR_ID:
84 conf_data =
85 CFG_PCI_VENDOR_ID(CS5536_EHCI_DEVICE_ID, CS5536_VENDOR_ID);
86 break;
87 case PCI_COMMAND:
88 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
89 if (hi & PCI_COMMAND_MASTER)
90 conf_data |= PCI_COMMAND_MASTER;
91 if (hi & PCI_COMMAND_MEMORY)
92 conf_data |= PCI_COMMAND_MEMORY;
93 break;
94 case PCI_STATUS:
95 conf_data |= PCI_STATUS_66MHZ;
96 conf_data |= PCI_STATUS_FAST_BACK;
97 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
98 if (lo & SB_PARE_ERR_FLAG)
99 conf_data |= PCI_STATUS_PARITY;
100 conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
101 break;
102 case PCI_CLASS_REVISION:
103 _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo);
104 conf_data = lo & 0x000000ff;
105 conf_data |= (CS5536_EHCI_CLASS_CODE << 8);
106 break;
107 case PCI_CACHE_LINE_SIZE:
108 conf_data =
109 CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
110 PCI_NORMAL_LATENCY_TIMER);
111 break;
112 case PCI_BAR0_REG:
113 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
114 if (lo & SOFT_BAR_EHCI_FLAG) {
115 conf_data = CS5536_EHCI_RANGE |
116 PCI_BASE_ADDRESS_SPACE_MEMORY;
117 lo &= ~SOFT_BAR_EHCI_FLAG;
118 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
119 } else {
120 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
121 conf_data = lo & 0xfffff000;
122 }
123 break;
124 case PCI_CARDBUS_CIS:
125 conf_data = PCI_CARDBUS_CIS_POINTER;
126 break;
127 case PCI_SUBSYSTEM_VENDOR_ID:
128 conf_data =
129 CFG_PCI_VENDOR_ID(CS5536_EHCI_SUB_ID, CS5536_SUB_VENDOR_ID);
130 break;
131 case PCI_ROM_ADDRESS:
132 conf_data = PCI_EXPANSION_ROM_BAR;
133 break;
134 case PCI_CAPABILITY_LIST:
135 conf_data = PCI_CAPLIST_USB_POINTER;
136 break;
137 case PCI_INTERRUPT_LINE:
138 conf_data =
139 CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR);
140 break;
141 case PCI_EHCI_LEGSMIEN_REG:
142 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
143 conf_data = (hi & 0x003f0000) >> 16;
144 break;
145 case PCI_EHCI_LEGSMISTS_REG:
146 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
147 conf_data = (hi & 0x3f000000) >> 24;
148 break;
149 case PCI_EHCI_FLADJ_REG:
150 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
151 conf_data = hi & 0x00003f00;
152 break;
153 default:
154 break;
155 }
156
157 return conf_data;
158}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_ide.c b/arch/mips/loongson/common/cs5536/cs5536_ide.c
new file mode 100644
index 000000000000..3f61594b3884
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_ide.c
@@ -0,0 +1,179 @@
1/*
2 * the IDE Virtual Support Module of AMD CS5536
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu, liujl@lemote.com
6 *
7 * Copyright (C) 2009 Lemote, Inc.
8 * Author: Wu Zhangjin, wuzj@lemote.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <cs5536/cs5536.h>
17#include <cs5536/cs5536_pci.h>
18
19void pci_ide_write_reg(int reg, u32 value)
20{
21 u32 hi = 0, lo = value;
22
23 switch (reg) {
24 case PCI_COMMAND:
25 _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
26 if (value & PCI_COMMAND_MASTER)
27 lo |= (0x03 << 4);
28 else
29 lo &= ~(0x03 << 4);
30 _wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo);
31 break;
32 case PCI_STATUS:
33 if (value & PCI_STATUS_PARITY) {
34 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
35 if (lo & SB_PARE_ERR_FLAG) {
36 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
37 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
38 }
39 }
40 break;
41 case PCI_CACHE_LINE_SIZE:
42 value &= 0x0000ff00;
43 _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
44 hi &= 0xffffff00;
45 hi |= (value >> 8);
46 _wrmsr(SB_MSR_REG(SB_CTRL), hi, lo);
47 break;
48 case PCI_BAR4_REG:
49 if (value == PCI_BAR_RANGE_MASK) {
50 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
51 lo |= SOFT_BAR_IDE_FLAG;
52 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
53 } else if (value & 0x01) {
54 lo = (value & 0xfffffff0) | 0x1;
55 _wrmsr(IDE_MSR_REG(IDE_IO_BAR), hi, lo);
56
57 value &= 0xfffffffc;
58 hi = 0x60000000 | ((value & 0x000ff000) >> 12);
59 lo = 0x000ffff0 | ((value & 0x00000fff) << 20);
60 _wrmsr(GLIU_MSR_REG(GLIU_IOD_BM2), hi, lo);
61 }
62 break;
63 case PCI_IDE_CFG_REG:
64 if (value == CS5536_IDE_FLASH_SIGNATURE) {
65 _rdmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), &hi, &lo);
66 lo |= 0x01;
67 _wrmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), hi, lo);
68 } else
69 _wrmsr(IDE_MSR_REG(IDE_CFG), hi, lo);
70 break;
71 case PCI_IDE_DTC_REG:
72 _wrmsr(IDE_MSR_REG(IDE_DTC), hi, lo);
73 break;
74 case PCI_IDE_CAST_REG:
75 _wrmsr(IDE_MSR_REG(IDE_CAST), hi, lo);
76 break;
77 case PCI_IDE_ETC_REG:
78 _wrmsr(IDE_MSR_REG(IDE_ETC), hi, lo);
79 break;
80 case PCI_IDE_PM_REG:
81 _wrmsr(IDE_MSR_REG(IDE_INTERNAL_PM), hi, lo);
82 break;
83 default:
84 break;
85 }
86}
87
88u32 pci_ide_read_reg(int reg)
89{
90 u32 conf_data = 0;
91 u32 hi, lo;
92
93 switch (reg) {
94 case PCI_VENDOR_ID:
95 conf_data =
96 CFG_PCI_VENDOR_ID(CS5536_IDE_DEVICE_ID, CS5536_VENDOR_ID);
97 break;
98 case PCI_COMMAND:
99 _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo);
100 if (lo & 0xfffffff0)
101 conf_data |= PCI_COMMAND_IO;
102 _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
103 if ((lo & 0x30) == 0x30)
104 conf_data |= PCI_COMMAND_MASTER;
105 break;
106 case PCI_STATUS:
107 conf_data |= PCI_STATUS_66MHZ;
108 conf_data |= PCI_STATUS_FAST_BACK;
109 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
110 if (lo & SB_PARE_ERR_FLAG)
111 conf_data |= PCI_STATUS_PARITY;
112 conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
113 break;
114 case PCI_CLASS_REVISION:
115 _rdmsr(IDE_MSR_REG(IDE_CAP), &hi, &lo);
116 conf_data = lo & 0x000000ff;
117 conf_data |= (CS5536_IDE_CLASS_CODE << 8);
118 break;
119 case PCI_CACHE_LINE_SIZE:
120 _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
121 hi &= 0x000000f8;
122 conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, hi);
123 break;
124 case PCI_BAR4_REG:
125 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
126 if (lo & SOFT_BAR_IDE_FLAG) {
127 conf_data = CS5536_IDE_RANGE |
128 PCI_BASE_ADDRESS_SPACE_IO;
129 lo &= ~SOFT_BAR_IDE_FLAG;
130 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
131 } else {
132 _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo);
133 conf_data = lo & 0xfffffff0;
134 conf_data |= 0x01;
135 conf_data &= ~0x02;
136 }
137 break;
138 case PCI_CARDBUS_CIS:
139 conf_data = PCI_CARDBUS_CIS_POINTER;
140 break;
141 case PCI_SUBSYSTEM_VENDOR_ID:
142 conf_data =
143 CFG_PCI_VENDOR_ID(CS5536_IDE_SUB_ID, CS5536_SUB_VENDOR_ID);
144 break;
145 case PCI_ROM_ADDRESS:
146 conf_data = PCI_EXPANSION_ROM_BAR;
147 break;
148 case PCI_CAPABILITY_LIST:
149 conf_data = PCI_CAPLIST_POINTER;
150 break;
151 case PCI_INTERRUPT_LINE:
152 conf_data =
153 CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_IDE_INTR);
154 break;
155 case PCI_IDE_CFG_REG:
156 _rdmsr(IDE_MSR_REG(IDE_CFG), &hi, &lo);
157 conf_data = lo;
158 break;
159 case PCI_IDE_DTC_REG:
160 _rdmsr(IDE_MSR_REG(IDE_DTC), &hi, &lo);
161 conf_data = lo;
162 break;
163 case PCI_IDE_CAST_REG:
164 _rdmsr(IDE_MSR_REG(IDE_CAST), &hi, &lo);
165 conf_data = lo;
166 break;
167 case PCI_IDE_ETC_REG:
168 _rdmsr(IDE_MSR_REG(IDE_ETC), &hi, &lo);
169 conf_data = lo;
170 case PCI_IDE_PM_REG:
171 _rdmsr(IDE_MSR_REG(IDE_INTERNAL_PM), &hi, &lo);
172 conf_data = lo;
173 break;
174 default:
175 break;
176 }
177
178 return conf_data;
179}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_isa.c b/arch/mips/loongson/common/cs5536/cs5536_isa.c
new file mode 100644
index 000000000000..b6f17f538e48
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_isa.c
@@ -0,0 +1,316 @@
1/*
2 * the ISA Virtual Support Module of AMD CS5536
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu, liujl@lemote.com
6 *
7 * Copyright (C) 2009 Lemote, Inc.
8 * Author: Wu Zhangjin, wuzj@lemote.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <cs5536/cs5536.h>
17#include <cs5536/cs5536_pci.h>
18
19/* common variables for PCI_ISA_READ/WRITE_BAR */
20static const u32 divil_msr_reg[6] = {
21 DIVIL_MSR_REG(DIVIL_LBAR_SMB), DIVIL_MSR_REG(DIVIL_LBAR_GPIO),
22 DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), DIVIL_MSR_REG(DIVIL_LBAR_IRQ),
23 DIVIL_MSR_REG(DIVIL_LBAR_PMS), DIVIL_MSR_REG(DIVIL_LBAR_ACPI),
24};
25
26static const u32 soft_bar_flag[6] = {
27 SOFT_BAR_SMB_FLAG, SOFT_BAR_GPIO_FLAG, SOFT_BAR_MFGPT_FLAG,
28 SOFT_BAR_IRQ_FLAG, SOFT_BAR_PMS_FLAG, SOFT_BAR_ACPI_FLAG,
29};
30
31static const u32 sb_msr_reg[6] = {
32 SB_MSR_REG(SB_R0), SB_MSR_REG(SB_R1), SB_MSR_REG(SB_R2),
33 SB_MSR_REG(SB_R3), SB_MSR_REG(SB_R4), SB_MSR_REG(SB_R5),
34};
35
36static const u32 bar_space_range[6] = {
37 CS5536_SMB_RANGE, CS5536_GPIO_RANGE, CS5536_MFGPT_RANGE,
38 CS5536_IRQ_RANGE, CS5536_PMS_RANGE, CS5536_ACPI_RANGE,
39};
40
41static const int bar_space_len[6] = {
42 CS5536_SMB_LENGTH, CS5536_GPIO_LENGTH, CS5536_MFGPT_LENGTH,
43 CS5536_IRQ_LENGTH, CS5536_PMS_LENGTH, CS5536_ACPI_LENGTH,
44};
45
46/*
47 * enable the divil module bar space.
48 *
49 * For all the DIVIL module LBAR, you should control the DIVIL LBAR reg
50 * and the RCONFx(0~5) reg to use the modules.
51 */
52static void divil_lbar_enable(void)
53{
54 u32 hi, lo;
55 int offset;
56
57 /*
58 * The DIVIL IRQ is not used yet. and make the RCONF0 reserved.
59 */
60
61 for (offset = DIVIL_LBAR_SMB; offset <= DIVIL_LBAR_PMS; offset++) {
62 _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo);
63 hi |= 0x01;
64 _wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), hi, lo);
65 }
66}
67
68/*
69 * disable the divil module bar space.
70 */
71static void divil_lbar_disable(void)
72{
73 u32 hi, lo;
74 int offset;
75
76 for (offset = DIVIL_LBAR_SMB; offset <= DIVIL_LBAR_PMS; offset++) {
77 _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo);
78 hi &= ~0x01;
79 _wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), hi, lo);
80 }
81}
82
83/*
84 * BAR write: write value to the n BAR
85 */
86
87void pci_isa_write_bar(int n, u32 value)
88{
89 u32 hi = 0, lo = value;
90
91 if (value == PCI_BAR_RANGE_MASK) {
92 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
93 lo |= soft_bar_flag[n];
94 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
95 } else if (value & 0x01) {
96 /* NATIVE reg */
97 hi = 0x0000f001;
98 lo &= bar_space_range[n];
99 _wrmsr(divil_msr_reg[n], hi, lo);
100
101 /* RCONFx is 4bytes in units for I/O space */
102 hi = ((value & 0x000ffffc) << 12) |
103 ((bar_space_len[n] - 4) << 12) | 0x01;
104 lo = ((value & 0x000ffffc) << 12) | 0x01;
105 _wrmsr(sb_msr_reg[n], hi, lo);
106 }
107}
108
109/*
110 * BAR read: read the n BAR
111 */
112
113u32 pci_isa_read_bar(int n)
114{
115 u32 conf_data = 0;
116 u32 hi, lo;
117
118 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
119 if (lo & soft_bar_flag[n]) {
120 conf_data = bar_space_range[n] | PCI_BASE_ADDRESS_SPACE_IO;
121 lo &= ~soft_bar_flag[n];
122 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
123 } else {
124 _rdmsr(divil_msr_reg[n], &hi, &lo);
125 conf_data = lo & bar_space_range[n];
126 conf_data |= 0x01;
127 conf_data &= ~0x02;
128 }
129 return conf_data;
130}
131
132/*
133 * isa_write: ISA write transfer
134 *
135 * We assume that this is not a bus master transfer.
136 */
137void pci_isa_write_reg(int reg, u32 value)
138{
139 u32 hi = 0, lo = value;
140 u32 temp;
141
142 switch (reg) {
143 case PCI_COMMAND:
144 if (value & PCI_COMMAND_IO)
145 divil_lbar_enable();
146 else
147 divil_lbar_disable();
148 break;
149 case PCI_STATUS:
150 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
151 temp = lo & 0x0000ffff;
152 if ((value & PCI_STATUS_SIG_TARGET_ABORT) &&
153 (lo & SB_TAS_ERR_EN))
154 temp |= SB_TAS_ERR_FLAG;
155
156 if ((value & PCI_STATUS_REC_TARGET_ABORT) &&
157 (lo & SB_TAR_ERR_EN))
158 temp |= SB_TAR_ERR_FLAG;
159
160 if ((value & PCI_STATUS_REC_MASTER_ABORT)
161 && (lo & SB_MAR_ERR_EN))
162 temp |= SB_MAR_ERR_FLAG;
163
164 if ((value & PCI_STATUS_DETECTED_PARITY)
165 && (lo & SB_PARE_ERR_EN))
166 temp |= SB_PARE_ERR_FLAG;
167
168 lo = temp;
169 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
170 break;
171 case PCI_CACHE_LINE_SIZE:
172 value &= 0x0000ff00;
173 _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
174 hi &= 0xffffff00;
175 hi |= (value >> 8);
176 _wrmsr(SB_MSR_REG(SB_CTRL), hi, lo);
177 break;
178 case PCI_BAR0_REG:
179 pci_isa_write_bar(0, value);
180 break;
181 case PCI_BAR1_REG:
182 pci_isa_write_bar(1, value);
183 break;
184 case PCI_BAR2_REG:
185 pci_isa_write_bar(2, value);
186 break;
187 case PCI_BAR3_REG:
188 pci_isa_write_bar(3, value);
189 break;
190 case PCI_BAR4_REG:
191 pci_isa_write_bar(4, value);
192 break;
193 case PCI_BAR5_REG:
194 pci_isa_write_bar(5, value);
195 break;
196 case PCI_UART1_INT_REG:
197 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo);
198 /* disable uart1 interrupt in PIC */
199 lo &= ~(0xf << 24);
200 if (value) /* enable uart1 interrupt in PIC */
201 lo |= (CS5536_UART1_INTR << 24);
202 _wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo);
203 break;
204 case PCI_UART2_INT_REG:
205 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo);
206 /* disable uart2 interrupt in PIC */
207 lo &= ~(0xf << 28);
208 if (value) /* enable uart2 interrupt in PIC */
209 lo |= (CS5536_UART2_INTR << 28);
210 _wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo);
211 break;
212 case PCI_ISA_FIXUP_REG:
213 if (value) {
214 /* enable the TARGET ABORT/MASTER ABORT etc. */
215 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
216 lo |= 0x00000063;
217 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
218 }
219
220 default:
221 /* ALL OTHER PCI CONFIG SPACE HEADER IS NOT IMPLEMENTED. */
222 break;
223 }
224}
225
226/*
227 * isa_read: ISA read transfers
228 *
229 * We assume that this is not a bus master transfer.
230 */
231u32 pci_isa_read_reg(int reg)
232{
233 u32 conf_data = 0;
234 u32 hi, lo;
235
236 switch (reg) {
237 case PCI_VENDOR_ID:
238 conf_data =
239 CFG_PCI_VENDOR_ID(CS5536_ISA_DEVICE_ID, CS5536_VENDOR_ID);
240 break;
241 case PCI_COMMAND:
242 /* we just check the first LBAR for the IO enable bit, */
243 /* maybe we should changed later. */
244 _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), &hi, &lo);
245 if (hi & 0x01)
246 conf_data |= PCI_COMMAND_IO;
247 break;
248 case PCI_STATUS:
249 conf_data |= PCI_STATUS_66MHZ;
250 conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
251 conf_data |= PCI_STATUS_FAST_BACK;
252
253 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
254 if (lo & SB_TAS_ERR_FLAG)
255 conf_data |= PCI_STATUS_SIG_TARGET_ABORT;
256 if (lo & SB_TAR_ERR_FLAG)
257 conf_data |= PCI_STATUS_REC_TARGET_ABORT;
258 if (lo & SB_MAR_ERR_FLAG)
259 conf_data |= PCI_STATUS_REC_MASTER_ABORT;
260 if (lo & SB_PARE_ERR_FLAG)
261 conf_data |= PCI_STATUS_DETECTED_PARITY;
262 break;
263 case PCI_CLASS_REVISION:
264 _rdmsr(GLCP_MSR_REG(GLCP_CHIP_REV_ID), &hi, &lo);
265 conf_data = lo & 0x000000ff;
266 conf_data |= (CS5536_ISA_CLASS_CODE << 8);
267 break;
268 case PCI_CACHE_LINE_SIZE:
269 _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
270 hi &= 0x000000f8;
271 conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_BRIDGE_HEADER_TYPE, hi);
272 break;
273 /*
274 * we only use the LBAR of DIVIL, no RCONF used.
275 * all of them are IO space.
276 */
277 case PCI_BAR0_REG:
278 return pci_isa_read_bar(0);
279 break;
280 case PCI_BAR1_REG:
281 return pci_isa_read_bar(1);
282 break;
283 case PCI_BAR2_REG:
284 return pci_isa_read_bar(2);
285 break;
286 case PCI_BAR3_REG:
287 break;
288 case PCI_BAR4_REG:
289 return pci_isa_read_bar(4);
290 break;
291 case PCI_BAR5_REG:
292 return pci_isa_read_bar(5);
293 break;
294 case PCI_CARDBUS_CIS:
295 conf_data = PCI_CARDBUS_CIS_POINTER;
296 break;
297 case PCI_SUBSYSTEM_VENDOR_ID:
298 conf_data =
299 CFG_PCI_VENDOR_ID(CS5536_ISA_SUB_ID, CS5536_SUB_VENDOR_ID);
300 break;
301 case PCI_ROM_ADDRESS:
302 conf_data = PCI_EXPANSION_ROM_BAR;
303 break;
304 case PCI_CAPABILITY_LIST:
305 conf_data = PCI_CAPLIST_POINTER;
306 break;
307 case PCI_INTERRUPT_LINE:
308 /* no interrupt used here */
309 conf_data = CFG_PCI_INTERRUPT_LINE(0x00, 0x00);
310 break;
311 default:
312 break;
313 }
314
315 return conf_data;
316}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c b/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
new file mode 100644
index 000000000000..6cb44dbaeec2
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
@@ -0,0 +1,217 @@
1/*
2 * CS5536 General timer functions
3 *
4 * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
5 * Author: Yanhua, yanh@lemote.com
6 *
7 * Copyright (C) 2009 Lemote Inc.
8 * Author: Wu zhangjin, wuzj@lemote.com
9 *
10 * Reference: AMD Geode(TM) CS5536 Companion Device Data Book
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17
18#include <linux/io.h>
19#include <linux/init.h>
20#include <linux/module.h>
21#include <linux/jiffies.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/clockchips.h>
25
26#include <asm/time.h>
27
28#include <cs5536/cs5536_mfgpt.h>
29
30DEFINE_SPINLOCK(mfgpt_lock);
31EXPORT_SYMBOL(mfgpt_lock);
32
33static u32 mfgpt_base;
34
35/*
36 * Initialize the MFGPT timer.
37 *
38 * This is also called after resume to bring the MFGPT into operation again.
39 */
40
41/* disable counter */
42void disable_mfgpt0_counter(void)
43{
44 outw(inw(MFGPT0_SETUP) & 0x7fff, MFGPT0_SETUP);
45}
46EXPORT_SYMBOL(disable_mfgpt0_counter);
47
48/* enable counter, comparator2 to event mode, 14.318MHz clock */
49void enable_mfgpt0_counter(void)
50{
51 outw(0xe310, MFGPT0_SETUP);
52}
53EXPORT_SYMBOL(enable_mfgpt0_counter);
54
55static void init_mfgpt_timer(enum clock_event_mode mode,
56 struct clock_event_device *evt)
57{
58 spin_lock(&mfgpt_lock);
59
60 switch (mode) {
61 case CLOCK_EVT_MODE_PERIODIC:
62 outw(COMPARE, MFGPT0_CMP2); /* set comparator2 */
63 outw(0, MFGPT0_CNT); /* set counter to 0 */
64 enable_mfgpt0_counter();
65 break;
66
67 case CLOCK_EVT_MODE_SHUTDOWN:
68 case CLOCK_EVT_MODE_UNUSED:
69 if (evt->mode == CLOCK_EVT_MODE_PERIODIC ||
70 evt->mode == CLOCK_EVT_MODE_ONESHOT)
71 disable_mfgpt0_counter();
72 break;
73
74 case CLOCK_EVT_MODE_ONESHOT:
75 /* The oneshot mode have very high deviation, Not use it! */
76 break;
77
78 case CLOCK_EVT_MODE_RESUME:
79 /* Nothing to do here */
80 break;
81 }
82 spin_unlock(&mfgpt_lock);
83}
84
85static struct clock_event_device mfgpt_clockevent = {
86 .name = "mfgpt",
87 .features = CLOCK_EVT_FEAT_PERIODIC,
88 .set_mode = init_mfgpt_timer,
89 .irq = CS5536_MFGPT_INTR,
90};
91
92static irqreturn_t timer_interrupt(int irq, void *dev_id)
93{
94 u32 basehi;
95
96 /*
97 * get MFGPT base address
98 *
99 * NOTE: do not remove me, it's need for the value of mfgpt_base is
100 * variable
101 */
102 _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base);
103
104 /* ack */
105 outw(inw(MFGPT0_SETUP) | 0x4000, MFGPT0_SETUP);
106
107 mfgpt_clockevent.event_handler(&mfgpt_clockevent);
108
109 return IRQ_HANDLED;
110}
111
112static struct irqaction irq5 = {
113 .handler = timer_interrupt,
114 .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER,
115 .name = "timer"
116};
117
118/*
119 * Initialize the conversion factor and the min/max deltas of the clock event
120 * structure and register the clock event source with the framework.
121 */
122void __init setup_mfgpt0_timer(void)
123{
124 u32 basehi;
125 struct clock_event_device *cd = &mfgpt_clockevent;
126 unsigned int cpu = smp_processor_id();
127
128 cd->cpumask = cpumask_of(cpu);
129 clockevent_set_clock(cd, MFGPT_TICK_RATE);
130 cd->max_delta_ns = clockevent_delta2ns(0xffff, cd);
131 cd->min_delta_ns = clockevent_delta2ns(0xf, cd);
132
133 /* Enable MFGPT0 Comparator 2 Output to the Interrupt Mapper */
134 _wrmsr(DIVIL_MSR_REG(MFGPT_IRQ), 0, 0x100);
135
136 /* Enable Interrupt Gate 5 */
137 _wrmsr(DIVIL_MSR_REG(PIC_ZSEL_LOW), 0, 0x50000);
138
139 /* get MFGPT base address */
140 _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base);
141
142 clockevents_register_device(cd);
143
144 setup_irq(CS5536_MFGPT_INTR, &irq5);
145}
146
147/*
148 * Since the MFGPT overflows every tick, its not very useful
149 * to just read by itself. So use jiffies to emulate a free
150 * running counter:
151 */
152static cycle_t mfgpt_read(struct clocksource *cs)
153{
154 unsigned long flags;
155 int count;
156 u32 jifs;
157 static int old_count;
158 static u32 old_jifs;
159
160 spin_lock_irqsave(&mfgpt_lock, flags);
161 /*
162 * Although our caller may have the read side of xtime_lock,
163 * this is now a seqlock, and we are cheating in this routine
164 * by having side effects on state that we cannot undo if
165 * there is a collision on the seqlock and our caller has to
166 * retry. (Namely, old_jifs and old_count.) So we must treat
167 * jiffies as volatile despite the lock. We read jiffies
168 * before latching the timer count to guarantee that although
169 * the jiffies value might be older than the count (that is,
170 * the counter may underflow between the last point where
171 * jiffies was incremented and the point where we latch the
172 * count), it cannot be newer.
173 */
174 jifs = jiffies;
175 /* read the count */
176 count = inw(MFGPT0_CNT);
177
178 /*
179 * It's possible for count to appear to go the wrong way for this
180 * reason:
181 *
182 * The timer counter underflows, but we haven't handled the resulting
183 * interrupt and incremented jiffies yet.
184 *
185 * Previous attempts to handle these cases intelligently were buggy, so
186 * we just do the simple thing now.
187 */
188 if (count < old_count && jifs == old_jifs)
189 count = old_count;
190
191 old_count = count;
192 old_jifs = jifs;
193
194 spin_unlock_irqrestore(&mfgpt_lock, flags);
195
196 return (cycle_t) (jifs * COMPARE) + count;
197}
198
199static struct clocksource clocksource_mfgpt = {
200 .name = "mfgpt",
201 .rating = 120, /* Functional for real use, but not desired */
202 .read = mfgpt_read,
203 .mask = CLOCKSOURCE_MASK(32),
204 .mult = 0,
205 .shift = 22,
206};
207
208int __init init_mfgpt_clocksource(void)
209{
210 if (num_possible_cpus() > 1) /* MFGPT does not scale! */
211 return 0;
212
213 clocksource_mfgpt.mult = clocksource_hz2mult(MFGPT_TICK_RATE, 22);
214 return clocksource_register(&clocksource_mfgpt);
215}
216
217arch_initcall(init_mfgpt_clocksource);
diff --git a/arch/mips/loongson/common/cs5536/cs5536_ohci.c b/arch/mips/loongson/common/cs5536/cs5536_ohci.c
new file mode 100644
index 000000000000..8fdb02b6e90f
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_ohci.c
@@ -0,0 +1,147 @@
1/*
2 * the OHCI Virtual Support Module of AMD CS5536
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu, liujl@lemote.com
6 *
7 * Copyright (C) 2009 Lemote, Inc.
8 * Author: Wu Zhangjin, wuzj@lemote.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <cs5536/cs5536.h>
17#include <cs5536/cs5536_pci.h>
18
19void pci_ohci_write_reg(int reg, u32 value)
20{
21 u32 hi = 0, lo = value;
22
23 switch (reg) {
24 case PCI_COMMAND:
25 _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
26 if (value & PCI_COMMAND_MASTER)
27 hi |= PCI_COMMAND_MASTER;
28 else
29 hi &= ~PCI_COMMAND_MASTER;
30
31 if (value & PCI_COMMAND_MEMORY)
32 hi |= PCI_COMMAND_MEMORY;
33 else
34 hi &= ~PCI_COMMAND_MEMORY;
35 _wrmsr(USB_MSR_REG(USB_OHCI), hi, lo);
36 break;
37 case PCI_STATUS:
38 if (value & PCI_STATUS_PARITY) {
39 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
40 if (lo & SB_PARE_ERR_FLAG) {
41 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
42 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
43 }
44 }
45 break;
46 case PCI_BAR0_REG:
47 if (value == PCI_BAR_RANGE_MASK) {
48 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
49 lo |= SOFT_BAR_OHCI_FLAG;
50 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
51 } else if ((value & 0x01) == 0x00) {
52 _wrmsr(USB_MSR_REG(USB_OHCI), hi, lo);
53
54 value &= 0xfffffff0;
55 hi = 0x40000000 | ((value & 0xff000000) >> 24);
56 lo = 0x000fffff | ((value & 0x00fff000) << 8);
57 _wrmsr(GLIU_MSR_REG(GLIU_P2D_BM3), hi, lo);
58 }
59 break;
60 case PCI_OHCI_INT_REG:
61 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
62 lo &= ~(0xf << PIC_YSEL_LOW_USB_SHIFT);
63 if (value) /* enable all the usb interrupt in PIC */
64 lo |= (CS5536_USB_INTR << PIC_YSEL_LOW_USB_SHIFT);
65 _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo);
66 break;
67 default:
68 break;
69 }
70}
71
72u32 pci_ohci_read_reg(int reg)
73{
74 u32 conf_data = 0;
75 u32 hi, lo;
76
77 switch (reg) {
78 case PCI_VENDOR_ID:
79 conf_data =
80 CFG_PCI_VENDOR_ID(CS5536_OHCI_DEVICE_ID, CS5536_VENDOR_ID);
81 break;
82 case PCI_COMMAND:
83 _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
84 if (hi & PCI_COMMAND_MASTER)
85 conf_data |= PCI_COMMAND_MASTER;
86 if (hi & PCI_COMMAND_MEMORY)
87 conf_data |= PCI_COMMAND_MEMORY;
88 break;
89 case PCI_STATUS:
90 conf_data |= PCI_STATUS_66MHZ;
91 conf_data |= PCI_STATUS_FAST_BACK;
92 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
93 if (lo & SB_PARE_ERR_FLAG)
94 conf_data |= PCI_STATUS_PARITY;
95 conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
96 break;
97 case PCI_CLASS_REVISION:
98 _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo);
99 conf_data = lo & 0x000000ff;
100 conf_data |= (CS5536_OHCI_CLASS_CODE << 8);
101 break;
102 case PCI_CACHE_LINE_SIZE:
103 conf_data =
104 CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
105 PCI_NORMAL_LATENCY_TIMER);
106 break;
107 case PCI_BAR0_REG:
108 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
109 if (lo & SOFT_BAR_OHCI_FLAG) {
110 conf_data = CS5536_OHCI_RANGE |
111 PCI_BASE_ADDRESS_SPACE_MEMORY;
112 lo &= ~SOFT_BAR_OHCI_FLAG;
113 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
114 } else {
115 _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
116 conf_data = lo & 0xffffff00;
117 conf_data &= ~0x0000000f; /* 32bit mem */
118 }
119 break;
120 case PCI_CARDBUS_CIS:
121 conf_data = PCI_CARDBUS_CIS_POINTER;
122 break;
123 case PCI_SUBSYSTEM_VENDOR_ID:
124 conf_data =
125 CFG_PCI_VENDOR_ID(CS5536_OHCI_SUB_ID, CS5536_SUB_VENDOR_ID);
126 break;
127 case PCI_ROM_ADDRESS:
128 conf_data = PCI_EXPANSION_ROM_BAR;
129 break;
130 case PCI_CAPABILITY_LIST:
131 conf_data = PCI_CAPLIST_USB_POINTER;
132 break;
133 case PCI_INTERRUPT_LINE:
134 conf_data =
135 CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR);
136 break;
137 case PCI_OHCI_INT_REG:
138 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
139 if ((lo & 0x00000f00) == CS5536_USB_INTR)
140 conf_data = 1;
141 break;
142 default:
143 break;
144 }
145
146 return conf_data;
147}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_pci.c b/arch/mips/loongson/common/cs5536/cs5536_pci.c
new file mode 100644
index 000000000000..e23f3d7d2c1d
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_pci.c
@@ -0,0 +1,87 @@
1/*
2 * read/write operation to the PCI config space of CS5536
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu, liujl@lemote.com
6 *
7 * Copyright (C) 2009 Lemote, Inc.
8 * Author: Wu Zhangjin, wuzj@lemote.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * the Virtual Support Module(VSM) for virtulizing the PCI
16 * configure space are defined in cs5536_modulename.c respectively,
17 *
18 * after this virtulizing, user can access the PCI configure space
19 * directly as a normal multi-function PCI device which follows
20 * the PCI-2.2 spec.
21 */
22
23#include <linux/types.h>
24#include <cs5536/cs5536_vsm.h>
25
26enum {
27 CS5536_FUNC_START = -1,
28 CS5536_ISA_FUNC,
29 reserved_func,
30 CS5536_IDE_FUNC,
31 CS5536_ACC_FUNC,
32 CS5536_OHCI_FUNC,
33 CS5536_EHCI_FUNC,
34 CS5536_FUNC_END,
35};
36
37static const cs5536_pci_vsm_write vsm_conf_write[] = {
38 [CS5536_ISA_FUNC] pci_isa_write_reg,
39 [reserved_func] NULL,
40 [CS5536_IDE_FUNC] pci_ide_write_reg,
41 [CS5536_ACC_FUNC] pci_acc_write_reg,
42 [CS5536_OHCI_FUNC] pci_ohci_write_reg,
43 [CS5536_EHCI_FUNC] pci_ehci_write_reg,
44};
45
46static const cs5536_pci_vsm_read vsm_conf_read[] = {
47 [CS5536_ISA_FUNC] pci_isa_read_reg,
48 [reserved_func] NULL,
49 [CS5536_IDE_FUNC] pci_ide_read_reg,
50 [CS5536_ACC_FUNC] pci_acc_read_reg,
51 [CS5536_OHCI_FUNC] pci_ohci_read_reg,
52 [CS5536_EHCI_FUNC] pci_ehci_read_reg,
53};
54
55/*
56 * write to PCI config space and transfer it to MSR write.
57 */
58void cs5536_pci_conf_write4(int function, int reg, u32 value)
59{
60 if ((function <= CS5536_FUNC_START) || (function >= CS5536_FUNC_END))
61 return;
62 if ((reg < 0) || (reg > 0x100) || ((reg & 0x03) != 0))
63 return;
64
65 if (vsm_conf_write[function] != NULL)
66 vsm_conf_write[function](reg, value);
67}
68
69/*
70 * read PCI config space and transfer it to MSR access.
71 */
72u32 cs5536_pci_conf_read4(int function, int reg)
73{
74 u32 data = 0;
75
76 if ((function <= CS5536_FUNC_START) || (function >= CS5536_FUNC_END))
77 return 0;
78 if ((reg < 0) || ((reg & 0x03) != 0))
79 return 0;
80 if (reg > 0x100)
81 return 0xffffffff;
82
83 if (vsm_conf_read[function] != NULL)
84 data = vsm_conf_read[function](reg);
85
86 return data;
87}
diff --git a/arch/mips/loongson/common/early_printk.c b/arch/mips/loongson/common/early_printk.c
index bc73edc0cfd8..23e7a8f8897f 100644
--- a/arch/mips/loongson/common/early_printk.c
+++ b/arch/mips/loongson/common/early_printk.c
@@ -1,7 +1,7 @@
1/* early printk support 1/* early printk support
2 * 2 *
3 * Copyright (c) 2009 Philippe Vachon <philippe@cowpig.ca> 3 * Copyright (c) 2009 Philippe Vachon <philippe@cowpig.ca>
4 * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology 4 * Copyright (c) 2009 Lemote Inc.
5 * Author: Wu Zhangjin, wuzj@lemote.com 5 * Author: Wu Zhangjin, wuzj@lemote.com
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify it 7 * This program is free software; you can redistribute it and/or modify it
@@ -12,26 +12,29 @@
12#include <linux/serial_reg.h> 12#include <linux/serial_reg.h>
13 13
14#include <loongson.h> 14#include <loongson.h>
15#include <machine.h>
16 15
17#define PORT(base, offset) (u8 *)(base + offset) 16#define PORT(base, offset) (u8 *)(base + offset)
18 17
19static inline unsigned int serial_in(phys_addr_t base, int offset) 18static inline unsigned int serial_in(unsigned char *base, int offset)
20{ 19{
21 return readb(PORT(base, offset)); 20 return readb(PORT(base, offset));
22} 21}
23 22
24static inline void serial_out(phys_addr_t base, int offset, int value) 23static inline void serial_out(unsigned char *base, int offset, int value)
25{ 24{
26 writeb(value, PORT(base, offset)); 25 writeb(value, PORT(base, offset));
27} 26}
28 27
29void prom_putchar(char c) 28void prom_putchar(char c)
30{ 29{
31 phys_addr_t uart_base = 30 int timeout;
32 (phys_addr_t) ioremap_nocache(LOONGSON_UART_BASE, 8); 31 unsigned char *uart_base;
33 32
34 while ((serial_in(uart_base, UART_LSR) & UART_LSR_THRE) == 0) 33 uart_base = (unsigned char *)_loongson_uart_base;
34 timeout = 1024;
35
36 while (((serial_in(uart_base, UART_LSR) & UART_LSR_THRE) == 0) &&
37 (timeout-- > 0))
35 ; 38 ;
36 39
37 serial_out(uart_base, UART_TX, c); 40 serial_out(uart_base, UART_TX, c);
diff --git a/arch/mips/loongson/common/env.c b/arch/mips/loongson/common/env.c
index b9ef50385541..196d947d929a 100644
--- a/arch/mips/loongson/common/env.c
+++ b/arch/mips/loongson/common/env.c
@@ -17,11 +17,14 @@
17 * Free Software Foundation; either version 2 of the License, or (at your 17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version. 18 * option) any later version.
19 */ 19 */
20#include <linux/module.h>
21
20#include <asm/bootinfo.h> 22#include <asm/bootinfo.h>
21 23
22#include <loongson.h> 24#include <loongson.h>
23 25
24unsigned long bus_clock, cpu_clock_freq; 26unsigned long bus_clock, cpu_clock_freq;
27EXPORT_SYMBOL(cpu_clock_freq);
25unsigned long memsize, highmemsize; 28unsigned long memsize, highmemsize;
26 29
27/* pmon passes arguments in 32bit pointers */ 30/* pmon passes arguments in 32bit pointers */
diff --git a/arch/mips/loongson/common/init.c b/arch/mips/loongson/common/init.c
index 3abe927422a3..a2abd9355737 100644
--- a/arch/mips/loongson/common/init.c
+++ b/arch/mips/loongson/common/init.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology 2 * Copyright (C) 2009 Lemote Inc.
3 * Author: Wu Zhangjin, wuzj@lemote.com 3 * Author: Wu Zhangjin, wuzj@lemote.com
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
@@ -10,19 +10,28 @@
10 10
11#include <linux/bootmem.h> 11#include <linux/bootmem.h>
12 12
13#include <asm/bootinfo.h>
14
15#include <loongson.h> 13#include <loongson.h>
16 14
15/* Loongson CPU address windows config space base address */
16unsigned long __maybe_unused _loongson_addrwincfg_base;
17
17void __init prom_init(void) 18void __init prom_init(void)
18{ 19{
19 /* init base address of io space */ 20 /* init base address of io space */
20 set_io_port_base((unsigned long) 21 set_io_port_base((unsigned long)
21 ioremap(BONITO_PCIIO_BASE, BONITO_PCIIO_SIZE)); 22 ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE));
23
24#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
25 _loongson_addrwincfg_base = (unsigned long)
26 ioremap(LOONGSON_ADDRWINCFG_BASE, LOONGSON_ADDRWINCFG_SIZE);
27#endif
22 28
23 prom_init_cmdline(); 29 prom_init_cmdline();
24 prom_init_env(); 30 prom_init_env();
25 prom_init_memory(); 31 prom_init_memory();
32
33 /*init the uart base address */
34 prom_init_uart_base();
26} 35}
27 36
28void __init prom_free_prom_memory(void) 37void __init prom_free_prom_memory(void)
diff --git a/arch/mips/loongson/common/irq.c b/arch/mips/loongson/common/irq.c
index b32b4a3e5137..20e732831978 100644
--- a/arch/mips/loongson/common/irq.c
+++ b/arch/mips/loongson/common/irq.c
@@ -20,21 +20,21 @@ void bonito_irqdispatch(void)
20 int i; 20 int i;
21 21
22 /* workaround the IO dma problem: let cpu looping to allow DMA finish */ 22 /* workaround the IO dma problem: let cpu looping to allow DMA finish */
23 int_status = BONITO_INTISR; 23 int_status = LOONGSON_INTISR;
24 if (int_status & (1 << 10)) { 24 if (int_status & (1 << 10)) {
25 while (int_status & (1 << 10)) { 25 while (int_status & (1 << 10)) {
26 udelay(1); 26 udelay(1);
27 int_status = BONITO_INTISR; 27 int_status = LOONGSON_INTISR;
28 } 28 }
29 } 29 }
30 30
31 /* Get pending sources, masked by current enables */ 31 /* Get pending sources, masked by current enables */
32 int_status = BONITO_INTISR & BONITO_INTEN; 32 int_status = LOONGSON_INTISR & LOONGSON_INTEN;
33 33
34 if (int_status != 0) { 34 if (int_status != 0) {
35 i = __ffs(int_status); 35 i = __ffs(int_status);
36 int_status &= ~(1 << i); 36 int_status &= ~(1 << i);
37 do_IRQ(BONITO_IRQ_BASE + i); 37 do_IRQ(LOONGSON_IRQ_BASE + i);
38 } 38 }
39} 39}
40 40
@@ -60,13 +60,13 @@ void __init arch_init_irq(void)
60 set_irq_trigger_mode(); 60 set_irq_trigger_mode();
61 61
62 /* no steer */ 62 /* no steer */
63 BONITO_INTSTEER = 0; 63 LOONGSON_INTSTEER = 0;
64 64
65 /* 65 /*
66 * Mask out all interrupt by writing "1" to all bit position in 66 * Mask out all interrupt by writing "1" to all bit position in
67 * the interrupt reset reg. 67 * the interrupt reset reg.
68 */ 68 */
69 BONITO_INTENCLR = ~0; 69 LOONGSON_INTENCLR = ~0;
70 70
71 /* machine specific irq init */ 71 /* machine specific irq init */
72 mach_init_irq(); 72 mach_init_irq();
diff --git a/arch/mips/loongson/common/machtype.c b/arch/mips/loongson/common/machtype.c
index 7b348248de7d..0ed52b3f5314 100644
--- a/arch/mips/loongson/common/machtype.c
+++ b/arch/mips/loongson/common/machtype.c
@@ -15,6 +15,9 @@
15#include <loongson.h> 15#include <loongson.h>
16#include <machine.h> 16#include <machine.h>
17 17
18/* please ensure the length of the machtype string is less than 50 */
19#define MACHTYPE_LEN 50
20
18static const char *system_types[] = { 21static const char *system_types[] = {
19 [MACH_LOONGSON_UNKNOWN] "unknown loongson machine", 22 [MACH_LOONGSON_UNKNOWN] "unknown loongson machine",
20 [MACH_LEMOTE_FL2E] "lemote-fuloong-2e-box", 23 [MACH_LEMOTE_FL2E] "lemote-fuloong-2e-box",
@@ -22,29 +25,35 @@ static const char *system_types[] = {
22 [MACH_LEMOTE_ML2F7] "lemote-mengloong-2f-7inches", 25 [MACH_LEMOTE_ML2F7] "lemote-mengloong-2f-7inches",
23 [MACH_LEMOTE_YL2F89] "lemote-yeeloong-2f-8.9inches", 26 [MACH_LEMOTE_YL2F89] "lemote-yeeloong-2f-8.9inches",
24 [MACH_DEXXON_GDIUM2F10] "dexxon-gidum-2f-10inches", 27 [MACH_DEXXON_GDIUM2F10] "dexxon-gidum-2f-10inches",
28 [MACH_LEMOTE_NAS] "lemote-nas-2f",
29 [MACH_LEMOTE_LL2F] "lemote-lynloong-2f",
25 [MACH_LOONGSON_END] NULL, 30 [MACH_LOONGSON_END] NULL,
26}; 31};
27 32
28const char *get_system_type(void) 33const char *get_system_type(void)
29{ 34{
30 if (mips_machtype == MACH_UNKNOWN)
31 mips_machtype = LOONGSON_MACHTYPE;
32
33 return system_types[mips_machtype]; 35 return system_types[mips_machtype];
34} 36}
35 37
36static __init int machtype_setup(char *str) 38void __init prom_init_machtype(void)
37{ 39{
40 char *p, str[MACHTYPE_LEN];
38 int machtype = MACH_LEMOTE_FL2E; 41 int machtype = MACH_LEMOTE_FL2E;
39 42
40 if (!str) 43 mips_machtype = LOONGSON_MACHTYPE;
41 return -EINVAL; 44
45 p = strstr(arcs_cmdline, "machtype=");
46 if (!p)
47 return;
48 p += strlen("machtype=");
49 strncpy(str, p, MACHTYPE_LEN);
50 p = strstr(str, " ");
51 if (p)
52 *p = '\0';
42 53
43 for (; system_types[machtype]; machtype++) 54 for (; system_types[machtype]; machtype++)
44 if (strstr(system_types[machtype], str)) { 55 if (strstr(system_types[machtype], str)) {
45 mips_machtype = machtype; 56 mips_machtype = machtype;
46 break; 57 break;
47 } 58 }
48 return 0;
49} 59}
50__setup("machtype=", machtype_setup);
diff --git a/arch/mips/loongson/common/mem.c b/arch/mips/loongson/common/mem.c
index e94ef158f980..ceacd092b446 100644
--- a/arch/mips/loongson/common/mem.c
+++ b/arch/mips/loongson/common/mem.c
@@ -12,15 +12,40 @@
12 12
13#include <loongson.h> 13#include <loongson.h>
14#include <mem.h> 14#include <mem.h>
15#include <pci.h>
15 16
16void __init prom_init_memory(void) 17void __init prom_init_memory(void)
17{ 18{
18 add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM); 19 add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM);
20
21 add_memory_region(memsize << 20, LOONGSON_PCI_MEM_START - (memsize <<
22 20), BOOT_MEM_RESERVED);
23#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
24 {
25 int bit;
26
27 bit = fls(memsize + highmemsize);
28 if (bit != ffs(memsize + highmemsize))
29 bit += 20;
30 else
31 bit = bit + 20 - 1;
32
33 /* set cpu window3 to map CPU to DDR: 2G -> 2G */
34 LOONGSON_ADDRWIN_CPUTODDR(ADDRWIN_WIN3, 0x80000000ul,
35 0x80000000ul, (1 << bit));
36 mmiowb();
37 }
38#endif /* !CONFIG_CPU_SUPPORTS_ADDRWINCFG */
39
19#ifdef CONFIG_64BIT 40#ifdef CONFIG_64BIT
20 if (highmemsize > 0) 41 if (highmemsize > 0)
21 add_memory_region(LOONGSON_HIGHMEM_START, 42 add_memory_region(LOONGSON_HIGHMEM_START,
22 highmemsize << 20, BOOT_MEM_RAM); 43 highmemsize << 20, BOOT_MEM_RAM);
23#endif /* CONFIG_64BIT */ 44
45 add_memory_region(LOONGSON_PCI_MEM_END + 1, LOONGSON_HIGHMEM_START -
46 LOONGSON_PCI_MEM_END - 1, BOOT_MEM_RESERVED);
47
48#endif /* !CONFIG_64BIT */
24} 49}
25 50
26/* override of arch/mips/mm/cache.c: __uncached_access */ 51/* override of arch/mips/mm/cache.c: __uncached_access */
@@ -33,3 +58,61 @@ int __uncached_access(struct file *file, unsigned long addr)
33 ((addr >= LOONGSON_MMIO_MEM_START) && 58 ((addr >= LOONGSON_MMIO_MEM_START) &&
34 (addr < LOONGSON_MMIO_MEM_END)); 59 (addr < LOONGSON_MMIO_MEM_END));
35} 60}
61
62#ifdef CONFIG_CPU_SUPPORTS_UNCACHED_ACCELERATED
63
64#include <linux/pci.h>
65#include <linux/sched.h>
66#include <asm/current.h>
67
68static unsigned long uca_start, uca_end;
69
70pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
71 unsigned long size, pgprot_t vma_prot)
72{
73 unsigned long offset = pfn << PAGE_SHIFT;
74 unsigned long end = offset + size;
75
76 if (__uncached_access(file, offset)) {
77 if (((uca_start && offset) >= uca_start) &&
78 (end <= uca_end))
79 return __pgprot((pgprot_val(vma_prot) &
80 ~_CACHE_MASK) |
81 _CACHE_UNCACHED_ACCELERATED);
82 else
83 return pgprot_noncached(vma_prot);
84 }
85 return vma_prot;
86}
87
88static int __init find_vga_mem_init(void)
89{
90 struct pci_dev *dev = 0;
91 struct resource *r;
92 int idx;
93
94 if (uca_start)
95 return 0;
96
97 for_each_pci_dev(dev) {
98 if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) {
99 for (idx = 0; idx < PCI_NUM_RESOURCES; idx++) {
100 r = &dev->resource[idx];
101 if (!r->start && r->end)
102 continue;
103 if (r->flags & IORESOURCE_IO)
104 continue;
105 if (r->flags & IORESOURCE_MEM) {
106 uca_start = r->start;
107 uca_end = r->end;
108 return 0;
109 }
110 }
111 }
112 }
113
114 return 0;
115}
116
117late_initcall(find_vga_mem_init);
118#endif /* !CONFIG_CPU_SUPPORTS_UNCACHED_ACCELERATED */
diff --git a/arch/mips/loongson/common/pci.c b/arch/mips/loongson/common/pci.c
index a3a4abfb6c9a..31d8c5ecd16c 100644
--- a/arch/mips/loongson/common/pci.c
+++ b/arch/mips/loongson/common/pci.c
@@ -27,7 +27,7 @@ static struct resource loongson_pci_io_resource = {
27}; 27};
28 28
29static struct pci_controller loongson_pci_controller = { 29static struct pci_controller loongson_pci_controller = {
30 .pci_ops = &bonito64_pci_ops, 30 .pci_ops = &loongson_pci_ops,
31 .io_resource = &loongson_pci_io_resource, 31 .io_resource = &loongson_pci_io_resource,
32 .mem_resource = &loongson_pci_mem_resource, 32 .mem_resource = &loongson_pci_mem_resource,
33 .mem_offset = 0x00000000UL, 33 .mem_offset = 0x00000000UL,
@@ -44,15 +44,15 @@ static void __init setup_pcimap(void)
44 * pcimap: PCI_MAP2 PCI_Mem_Lo2 PCI_Mem_Lo1 PCI_Mem_Lo0 44 * pcimap: PCI_MAP2 PCI_Mem_Lo2 PCI_Mem_Lo1 PCI_Mem_Lo0
45 * [<2G] [384M,448M] [320M,384M] [0M,64M] 45 * [<2G] [384M,448M] [320M,384M] [0M,64M]
46 */ 46 */
47 BONITO_PCIMAP = BONITO_PCIMAP_PCIMAP_2 | 47 LOONGSON_PCIMAP = LOONGSON_PCIMAP_PCIMAP_2 |
48 BONITO_PCIMAP_WIN(2, BONITO_PCILO2_BASE) | 48 LOONGSON_PCIMAP_WIN(2, LOONGSON_PCILO2_BASE) |
49 BONITO_PCIMAP_WIN(1, BONITO_PCILO1_BASE) | 49 LOONGSON_PCIMAP_WIN(1, LOONGSON_PCILO1_BASE) |
50 BONITO_PCIMAP_WIN(0, 0); 50 LOONGSON_PCIMAP_WIN(0, 0);
51 51
52 /* 52 /*
53 * PCI-DMA to local mapping: [2G,2G+256M] -> [0M,256M] 53 * PCI-DMA to local mapping: [2G,2G+256M] -> [0M,256M]
54 */ 54 */
55 BONITO_PCIBASE0 = 0x80000000ul; /* base: 2G -> mmap: 0M */ 55 LOONGSON_PCIBASE0 = 0x80000000ul; /* base: 2G -> mmap: 0M */
56 /* size: 256M, burst transmission, pre-fetch enable, 64bit */ 56 /* size: 256M, burst transmission, pre-fetch enable, 64bit */
57 LOONGSON_PCI_HIT0_SEL_L = 0xc000000cul; 57 LOONGSON_PCI_HIT0_SEL_L = 0xc000000cul;
58 LOONGSON_PCI_HIT0_SEL_H = 0xfffffffful; 58 LOONGSON_PCI_HIT0_SEL_H = 0xfffffffful;
@@ -67,6 +67,14 @@ static void __init setup_pcimap(void)
67 /* can not change gnt to break pci transfer when device's gnt not 67 /* can not change gnt to break pci transfer when device's gnt not
68 deassert for some broken device */ 68 deassert for some broken device */
69 LOONGSON_PXARB_CFG = 0x00fe0105ul; 69 LOONGSON_PXARB_CFG = 0x00fe0105ul;
70
71#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
72 /*
73 * set cpu addr window2 to map CPU address space to PCI address space
74 */
75 LOONGSON_ADDRWIN_CPUTOPCI(ADDRWIN_WIN2, LOONGSON_CPU_MEM_SRC,
76 LOONGSON_PCI_MEM_DST, MMAP_CPUTOPCI_SIZE);
77#endif
70} 78}
71 79
72static int __init pcibios_init(void) 80static int __init pcibios_init(void)
diff --git a/arch/mips/loongson/common/platform.c b/arch/mips/loongson/common/platform.c
new file mode 100644
index 000000000000..be81777eb94d
--- /dev/null
+++ b/arch/mips/loongson/common/platform.c
@@ -0,0 +1,30 @@
1/*
2 * Copyright (C) 2009 Lemote Inc.
3 * Author: Wu Zhangjin, wuzj@lemote.com
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#include <linux/err.h>
12#include <linux/platform_device.h>
13
14static struct platform_device loongson2_cpufreq_device = {
15 .name = "loongson2_cpufreq",
16 .id = -1,
17};
18
19static int __init loongson2_cpufreq_init(void)
20{
21 struct cpuinfo_mips *c = &current_cpu_data;
22
23 /* Only 2F revision and it's successors support CPUFreq */
24 if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_LOONGSON2F)
25 return platform_device_register(&loongson2_cpufreq_device);
26
27 return -ENODEV;
28}
29
30arch_initcall(loongson2_cpufreq_init);
diff --git a/arch/mips/loongson/common/pm.c b/arch/mips/loongson/common/pm.c
new file mode 100644
index 000000000000..b625fec8a4d5
--- /dev/null
+++ b/arch/mips/loongson/common/pm.c
@@ -0,0 +1,161 @@
1/*
2 * loongson-specific suspend support
3 *
4 * Copyright (C) 2009 Lemote Inc.
5 * Author: Wu Zhangjin <wuzj@lemote.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12#include <linux/suspend.h>
13#include <linux/interrupt.h>
14#include <linux/pm.h>
15
16#include <asm/i8259.h>
17#include <asm/mipsregs.h>
18
19#include <loongson.h>
20
21static unsigned int __maybe_unused cached_master_mask; /* i8259A */
22static unsigned int __maybe_unused cached_slave_mask;
23static unsigned int __maybe_unused cached_bonito_irq_mask; /* bonito */
24
25void arch_suspend_disable_irqs(void)
26{
27 /* disable all mips events */
28 local_irq_disable();
29
30#ifdef CONFIG_I8259
31 /* disable all events of i8259A */
32 cached_slave_mask = inb(PIC_SLAVE_IMR);
33 cached_master_mask = inb(PIC_MASTER_IMR);
34
35 outb(0xff, PIC_SLAVE_IMR);
36 inb(PIC_SLAVE_IMR);
37 outb(0xff, PIC_MASTER_IMR);
38 inb(PIC_MASTER_IMR);
39#endif
40 /* disable all events of bonito */
41 cached_bonito_irq_mask = LOONGSON_INTEN;
42 LOONGSON_INTENCLR = 0xffff;
43 (void)LOONGSON_INTENCLR;
44}
45
46void arch_suspend_enable_irqs(void)
47{
48 /* enable all mips events */
49 local_irq_enable();
50#ifdef CONFIG_I8259
51 /* only enable the cached events of i8259A */
52 outb(cached_slave_mask, PIC_SLAVE_IMR);
53 outb(cached_master_mask, PIC_MASTER_IMR);
54#endif
55 /* enable all cached events of bonito */
56 LOONGSON_INTENSET = cached_bonito_irq_mask;
57 (void)LOONGSON_INTENSET;
58}
59
60/*
61 * Setup the board-specific events for waking up loongson from wait mode
62 */
63void __weak setup_wakeup_events(void)
64{
65}
66
67/*
68 * Check wakeup events
69 */
70int __weak wakeup_loongson(void)
71{
72 return 1;
73}
74
75/*
76 * If the events are really what we want to wakeup the CPU, wake it up
77 * otherwise put the CPU asleep again.
78 */
79static void wait_for_wakeup_events(void)
80{
81 while (!wakeup_loongson())
82 LOONGSON_CHIPCFG0 &= ~0x7;
83}
84
85/*
86 * Stop all perf counters
87 *
88 * $24 is the control register of Loongson perf counter
89 */
90static inline void stop_perf_counters(void)
91{
92 __write_64bit_c0_register($24, 0, 0);
93}
94
95
96static void loongson_suspend_enter(void)
97{
98 static unsigned int cached_cpu_freq;
99
100 /* setup wakeup events via enabling the IRQs */
101 setup_wakeup_events();
102
103 stop_perf_counters();
104
105 cached_cpu_freq = LOONGSON_CHIPCFG0;
106
107 /* Put CPU into wait mode */
108 LOONGSON_CHIPCFG0 &= ~0x7;
109
110 /* wait for the given events to wakeup cpu from wait mode */
111 wait_for_wakeup_events();
112
113 LOONGSON_CHIPCFG0 = cached_cpu_freq;
114 mmiowb();
115}
116
117void __weak mach_suspend(void)
118{
119}
120
121void __weak mach_resume(void)
122{
123}
124
125static int loongson_pm_enter(suspend_state_t state)
126{
127 mach_suspend();
128
129 /* processor specific suspend */
130 loongson_suspend_enter();
131
132 mach_resume();
133
134 return 0;
135}
136
137static int loongson_pm_valid_state(suspend_state_t state)
138{
139 switch (state) {
140 case PM_SUSPEND_ON:
141 case PM_SUSPEND_STANDBY:
142 case PM_SUSPEND_MEM:
143 return 1;
144
145 default:
146 return 0;
147 }
148}
149
150static struct platform_suspend_ops loongson_pm_ops = {
151 .valid = loongson_pm_valid_state,
152 .enter = loongson_pm_enter,
153};
154
155static int __init loongson_pm_init(void)
156{
157 suspend_set_ops(&loongson_pm_ops);
158
159 return 0;
160}
161arch_initcall(loongson_pm_init);
diff --git a/arch/mips/loongson/common/reset.c b/arch/mips/loongson/common/reset.c
index 97e918251edd..d57f1719da95 100644
--- a/arch/mips/loongson/common/reset.c
+++ b/arch/mips/loongson/common/reset.c
@@ -22,7 +22,7 @@ static void loongson_restart(char *command)
22 mach_prepare_reboot(); 22 mach_prepare_reboot();
23 23
24 /* reboot via jumping to boot base address */ 24 /* reboot via jumping to boot base address */
25 ((void (*)(void))ioremap_nocache(BONITO_BOOT_BASE, 4)) (); 25 ((void (*)(void))ioremap_nocache(LOONGSON_BOOT_BASE, 4)) ();
26} 26}
27 27
28static void loongson_halt(void) 28static void loongson_halt(void)
diff --git a/arch/mips/loongson/common/serial.c b/arch/mips/loongson/common/serial.c
new file mode 100644
index 000000000000..23b66a5f88cb
--- /dev/null
+++ b/arch/mips/loongson/common/serial.c
@@ -0,0 +1,76 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
7 *
8 * Copyright (C) 2009 Lemote, Inc.
9 * Author: Yan hua (yanhua@lemote.com)
10 * Author: Wu Zhangjin (wuzj@lemote.com)
11 */
12
13#include <linux/io.h>
14#include <linux/init.h>
15#include <linux/serial_8250.h>
16
17#include <asm/bootinfo.h>
18
19#include <loongson.h>
20#include <machine.h>
21
22#define PORT(int) \
23{ \
24 .irq = int, \
25 .uartclk = 1843200, \
26 .iotype = UPIO_PORT, \
27 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \
28 .regshift = 0, \
29}
30
31#define PORT_M(int) \
32{ \
33 .irq = MIPS_CPU_IRQ_BASE + (int), \
34 .uartclk = 3686400, \
35 .iotype = UPIO_MEM, \
36 .membase = (void __iomem *)NULL, \
37 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \
38 .regshift = 0, \
39}
40
41static struct plat_serial8250_port uart8250_data[][2] = {
42 [MACH_LOONGSON_UNKNOWN] {},
43 [MACH_LEMOTE_FL2E] {PORT(4), {} },
44 [MACH_LEMOTE_FL2F] {PORT(3), {} },
45 [MACH_LEMOTE_ML2F7] {PORT_M(3), {} },
46 [MACH_LEMOTE_YL2F89] {PORT_M(3), {} },
47 [MACH_DEXXON_GDIUM2F10] {PORT_M(3), {} },
48 [MACH_LEMOTE_NAS] {PORT_M(3), {} },
49 [MACH_LEMOTE_LL2F] {PORT(3), {} },
50 [MACH_LOONGSON_END] {},
51};
52
53static struct platform_device uart8250_device = {
54 .name = "serial8250",
55 .id = PLAT8250_DEV_PLATFORM,
56};
57
58static int __init serial_init(void)
59{
60 unsigned char iotype;
61
62 iotype = uart8250_data[mips_machtype][0].iotype;
63
64 if (UPIO_MEM == iotype)
65 uart8250_data[mips_machtype][0].membase =
66 (void __iomem *)_loongson_uart_base;
67 else if (UPIO_PORT == iotype)
68 uart8250_data[mips_machtype][0].iobase =
69 loongson_uart_base - LOONGSON_PCIIO_BASE;
70
71 uart8250_device.dev.platform_data = uart8250_data[mips_machtype];
72
73 return platform_device_register(&uart8250_device);
74}
75
76device_initcall(serial_init);
diff --git a/arch/mips/loongson/common/time.c b/arch/mips/loongson/common/time.c
index 6e08c8270abe..35f0b66a94f5 100644
--- a/arch/mips/loongson/common/time.c
+++ b/arch/mips/loongson/common/time.c
@@ -14,11 +14,14 @@
14#include <asm/time.h> 14#include <asm/time.h>
15 15
16#include <loongson.h> 16#include <loongson.h>
17#include <cs5536/cs5536_mfgpt.h>
17 18
18void __init plat_time_init(void) 19void __init plat_time_init(void)
19{ 20{
20 /* setup mips r4k timer */ 21 /* setup mips r4k timer */
21 mips_hpt_frequency = cpu_clock_freq / 2; 22 mips_hpt_frequency = cpu_clock_freq / 2;
23
24 setup_mfgpt0_timer();
22} 25}
23 26
24void read_persistent_clock(struct timespec *ts) 27void read_persistent_clock(struct timespec *ts)
diff --git a/arch/mips/loongson/common/uart_base.c b/arch/mips/loongson/common/uart_base.c
new file mode 100644
index 000000000000..78ff66ae749e
--- /dev/null
+++ b/arch/mips/loongson/common/uart_base.c
@@ -0,0 +1,45 @@
1/*
2 * Copyright (C) 2009 Lemote Inc.
3 * Author: Wu Zhangjin, wuzj@lemote.com
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#include <linux/module.h>
12#include <asm/bootinfo.h>
13
14#include <loongson.h>
15
16/* ioremapped */
17unsigned long _loongson_uart_base;
18EXPORT_SYMBOL(_loongson_uart_base);
19/* raw */
20unsigned long loongson_uart_base;
21EXPORT_SYMBOL(loongson_uart_base);
22
23void prom_init_loongson_uart_base(void)
24{
25 switch (mips_machtype) {
26 case MACH_LEMOTE_FL2E:
27 loongson_uart_base = LOONGSON_PCIIO_BASE + 0x3f8;
28 break;
29 case MACH_LEMOTE_FL2F:
30 case MACH_LEMOTE_LL2F:
31 loongson_uart_base = LOONGSON_PCIIO_BASE + 0x2f8;
32 break;
33 case MACH_LEMOTE_ML2F7:
34 case MACH_LEMOTE_YL2F89:
35 case MACH_DEXXON_GDIUM2F10:
36 case MACH_LEMOTE_NAS:
37 default:
38 /* The CPU provided serial port */
39 loongson_uart_base = LOONGSON_LIO1_BASE + 0x3f8;
40 break;
41 }
42
43 _loongson_uart_base =
44 (unsigned long)ioremap_nocache(loongson_uart_base, 8);
45}
diff --git a/arch/mips/loongson/fuloong-2e/irq.c b/arch/mips/loongson/fuloong-2e/irq.c
index 7888cf69424a..320e9379bdd7 100644
--- a/arch/mips/loongson/fuloong-2e/irq.c
+++ b/arch/mips/loongson/fuloong-2e/irq.c
@@ -47,8 +47,8 @@ static struct irqaction cascade_irqaction = {
47void __init set_irq_trigger_mode(void) 47void __init set_irq_trigger_mode(void)
48{ 48{
49 /* most bonito irq should be level triggered */ 49 /* most bonito irq should be level triggered */
50 BONITO_INTEDGE = BONITO_ICU_SYSTEMERR | BONITO_ICU_MASTERERR | 50 LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR |
51 BONITO_ICU_RETRYERR | BONITO_ICU_MBOXES; 51 LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES;
52} 52}
53 53
54void __init mach_init_irq(void) 54void __init mach_init_irq(void)
diff --git a/arch/mips/loongson/fuloong-2e/reset.c b/arch/mips/loongson/fuloong-2e/reset.c
index 677fe186db95..fc16c677d476 100644
--- a/arch/mips/loongson/fuloong-2e/reset.c
+++ b/arch/mips/loongson/fuloong-2e/reset.c
@@ -14,8 +14,8 @@
14 14
15void mach_prepare_reboot(void) 15void mach_prepare_reboot(void)
16{ 16{
17 BONITO_BONGENCFG &= ~(1 << 2); 17 LOONGSON_GENCFG &= ~(1 << 2);
18 BONITO_BONGENCFG |= (1 << 2); 18 LOONGSON_GENCFG |= (1 << 2);
19} 19}
20 20
21void mach_prepare_shutdown(void) 21void mach_prepare_shutdown(void)
diff --git a/arch/mips/loongson/lemote-2f/Makefile b/arch/mips/loongson/lemote-2f/Makefile
new file mode 100644
index 000000000000..4d84b27dc41b
--- /dev/null
+++ b/arch/mips/loongson/lemote-2f/Makefile
@@ -0,0 +1,11 @@
1#
2# Makefile for lemote loongson2f family machines
3#
4
5obj-y += irq.o reset.o ec_kb3310b.o
6
7#
8# Suspend Support
9#
10
11obj-$(CONFIG_LOONGSON_SUSPEND) += pm.o
diff --git a/arch/mips/loongson/lemote-2f/ec_kb3310b.c b/arch/mips/loongson/lemote-2f/ec_kb3310b.c
new file mode 100644
index 000000000000..4d84111a2cd4
--- /dev/null
+++ b/arch/mips/loongson/lemote-2f/ec_kb3310b.c
@@ -0,0 +1,130 @@
1/*
2 * Basic KB3310B Embedded Controller support for the YeeLoong 2F netbook
3 *
4 * Copyright (C) 2008 Lemote Inc.
5 * Author: liujl <liujl@lemote.com>, 2008-04-20
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/spinlock.h>
15#include <linux/delay.h>
16
17#include "ec_kb3310b.h"
18
19static DEFINE_SPINLOCK(index_access_lock);
20static DEFINE_SPINLOCK(port_access_lock);
21
22unsigned char ec_read(unsigned short addr)
23{
24 unsigned char value;
25 unsigned long flags;
26
27 spin_lock_irqsave(&index_access_lock, flags);
28 outb((addr & 0xff00) >> 8, EC_IO_PORT_HIGH);
29 outb((addr & 0x00ff), EC_IO_PORT_LOW);
30 value = inb(EC_IO_PORT_DATA);
31 spin_unlock_irqrestore(&index_access_lock, flags);
32
33 return value;
34}
35EXPORT_SYMBOL_GPL(ec_read);
36
37void ec_write(unsigned short addr, unsigned char val)
38{
39 unsigned long flags;
40
41 spin_lock_irqsave(&index_access_lock, flags);
42 outb((addr & 0xff00) >> 8, EC_IO_PORT_HIGH);
43 outb((addr & 0x00ff), EC_IO_PORT_LOW);
44 outb(val, EC_IO_PORT_DATA);
45 /* flush the write action */
46 inb(EC_IO_PORT_DATA);
47 spin_unlock_irqrestore(&index_access_lock, flags);
48
49 return;
50}
51EXPORT_SYMBOL_GPL(ec_write);
52
53/*
54 * This function is used for EC command writes and corresponding status queries.
55 */
56int ec_query_seq(unsigned char cmd)
57{
58 int timeout;
59 unsigned char status;
60 unsigned long flags;
61 int ret = 0;
62
63 spin_lock_irqsave(&port_access_lock, flags);
64
65 /* make chip goto reset mode */
66 udelay(EC_REG_DELAY);
67 outb(cmd, EC_CMD_PORT);
68 udelay(EC_REG_DELAY);
69
70 /* check if the command is received by ec */
71 timeout = EC_CMD_TIMEOUT;
72 status = inb(EC_STS_PORT);
73 while (timeout-- && (status & (1 << 1))) {
74 status = inb(EC_STS_PORT);
75 udelay(EC_REG_DELAY);
76 }
77
78 if (timeout <= 0) {
79 printk(KERN_ERR "%s: deadable error : timeout...\n", __func__);
80 ret = -EINVAL;
81 } else
82 printk(KERN_INFO
83 "(%x/%d)ec issued command %d status : 0x%x\n",
84 timeout, EC_CMD_TIMEOUT - timeout, cmd, status);
85
86 spin_unlock_irqrestore(&port_access_lock, flags);
87
88 return ret;
89}
90EXPORT_SYMBOL_GPL(ec_query_seq);
91
92/*
93 * Send query command to EC to get the proper event number
94 */
95int ec_query_event_num(void)
96{
97 return ec_query_seq(CMD_GET_EVENT_NUM);
98}
99EXPORT_SYMBOL(ec_query_event_num);
100
101/*
102 * Get event number from EC
103 *
104 * NOTE: This routine must follow the query_event_num function in the
105 * interrupt.
106 */
107int ec_get_event_num(void)
108{
109 int timeout = 100;
110 unsigned char value;
111 unsigned char status;
112
113 udelay(EC_REG_DELAY);
114 status = inb(EC_STS_PORT);
115 udelay(EC_REG_DELAY);
116 while (timeout-- && !(status & (1 << 0))) {
117 status = inb(EC_STS_PORT);
118 udelay(EC_REG_DELAY);
119 }
120 if (timeout <= 0) {
121 pr_info("%s: get event number timeout.\n", __func__);
122
123 return -EINVAL;
124 }
125 value = inb(EC_DAT_PORT);
126 udelay(EC_REG_DELAY);
127
128 return value;
129}
130EXPORT_SYMBOL(ec_get_event_num);
diff --git a/arch/mips/loongson/lemote-2f/ec_kb3310b.h b/arch/mips/loongson/lemote-2f/ec_kb3310b.h
new file mode 100644
index 000000000000..1595a21b315b
--- /dev/null
+++ b/arch/mips/loongson/lemote-2f/ec_kb3310b.h
@@ -0,0 +1,188 @@
1/*
2 * KB3310B Embedded Controller
3 *
4 * Copyright (C) 2008 Lemote Inc.
5 * Author: liujl <liujl@lemote.com>, 2008-03-14
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#ifndef _EC_KB3310B_H
14#define _EC_KB3310B_H
15
16extern unsigned char ec_read(unsigned short addr);
17extern void ec_write(unsigned short addr, unsigned char val);
18extern int ec_query_seq(unsigned char cmd);
19extern int ec_query_event_num(void);
20extern int ec_get_event_num(void);
21
22typedef int (*sci_handler) (int status);
23extern sci_handler yeeloong_report_lid_status;
24
25#define SCI_IRQ_NUM 0x0A
26
27/*
28 * The following registers are determined by the EC index configuration.
29 * 1, fill the PORT_HIGH as EC register high part.
30 * 2, fill the PORT_LOW as EC register low part.
31 * 3, fill the PORT_DATA as EC register write data or get the data from it.
32 */
33#define EC_IO_PORT_HIGH 0x0381
34#define EC_IO_PORT_LOW 0x0382
35#define EC_IO_PORT_DATA 0x0383
36
37/*
38 * EC delay time is 500us for register and status access
39 */
40#define EC_REG_DELAY 500 /* unit : us */
41#define EC_CMD_TIMEOUT 0x1000
42
43/*
44 * EC access port for SCI communication
45 */
46#define EC_CMD_PORT 0x66
47#define EC_STS_PORT 0x66
48#define EC_DAT_PORT 0x62
49#define CMD_INIT_IDLE_MODE 0xdd
50#define CMD_EXIT_IDLE_MODE 0xdf
51#define CMD_INIT_RESET_MODE 0xd8
52#define CMD_REBOOT_SYSTEM 0x8c
53#define CMD_GET_EVENT_NUM 0x84
54#define CMD_PROGRAM_PIECE 0xda
55
56/* temperature & fan registers */
57#define REG_TEMPERATURE_VALUE 0xF458
58#define REG_FAN_AUTO_MAN_SWITCH 0xF459
59#define BIT_FAN_AUTO 0
60#define BIT_FAN_MANUAL 1
61#define REG_FAN_CONTROL 0xF4D2
62#define BIT_FAN_CONTROL_ON (1 << 0)
63#define BIT_FAN_CONTROL_OFF (0 << 0)
64#define REG_FAN_STATUS 0xF4DA
65#define BIT_FAN_STATUS_ON (1 << 0)
66#define BIT_FAN_STATUS_OFF (0 << 0)
67#define REG_FAN_SPEED_HIGH 0xFE22
68#define REG_FAN_SPEED_LOW 0xFE23
69#define REG_FAN_SPEED_LEVEL 0xF4CC
70/* fan speed divider */
71#define FAN_SPEED_DIVIDER 480000 /* (60*1000*1000/62.5/2)*/
72
73/* battery registers */
74#define REG_BAT_DESIGN_CAP_HIGH 0xF77D
75#define REG_BAT_DESIGN_CAP_LOW 0xF77E
76#define REG_BAT_FULLCHG_CAP_HIGH 0xF780
77#define REG_BAT_FULLCHG_CAP_LOW 0xF781
78#define REG_BAT_DESIGN_VOL_HIGH 0xF782
79#define REG_BAT_DESIGN_VOL_LOW 0xF783
80#define REG_BAT_CURRENT_HIGH 0xF784
81#define REG_BAT_CURRENT_LOW 0xF785
82#define REG_BAT_VOLTAGE_HIGH 0xF786
83#define REG_BAT_VOLTAGE_LOW 0xF787
84#define REG_BAT_TEMPERATURE_HIGH 0xF788
85#define REG_BAT_TEMPERATURE_LOW 0xF789
86#define REG_BAT_RELATIVE_CAP_HIGH 0xF492
87#define REG_BAT_RELATIVE_CAP_LOW 0xF493
88#define REG_BAT_VENDOR 0xF4C4
89#define FLAG_BAT_VENDOR_SANYO 0x01
90#define FLAG_BAT_VENDOR_SIMPLO 0x02
91#define REG_BAT_CELL_COUNT 0xF4C6
92#define FLAG_BAT_CELL_3S1P 0x03
93#define FLAG_BAT_CELL_3S2P 0x06
94#define REG_BAT_CHARGE 0xF4A2
95#define FLAG_BAT_CHARGE_DISCHARGE 0x01
96#define FLAG_BAT_CHARGE_CHARGE 0x02
97#define FLAG_BAT_CHARGE_ACPOWER 0x00
98#define REG_BAT_STATUS 0xF4B0
99#define BIT_BAT_STATUS_LOW (1 << 5)
100#define BIT_BAT_STATUS_DESTROY (1 << 2)
101#define BIT_BAT_STATUS_FULL (1 << 1)
102#define BIT_BAT_STATUS_IN (1 << 0)
103#define REG_BAT_CHARGE_STATUS 0xF4B1
104#define BIT_BAT_CHARGE_STATUS_OVERTEMP (1 << 2)
105#define BIT_BAT_CHARGE_STATUS_PRECHG (1 << 1)
106#define REG_BAT_STATE 0xF482
107#define BIT_BAT_STATE_CHARGING (1 << 1)
108#define BIT_BAT_STATE_DISCHARGING (1 << 0)
109#define REG_BAT_POWER 0xF440
110#define BIT_BAT_POWER_S3 (1 << 2)
111#define BIT_BAT_POWER_ON (1 << 1)
112#define BIT_BAT_POWER_ACIN (1 << 0)
113
114/* other registers */
115/* Audio: rd/wr */
116#define REG_AUDIO_VOLUME 0xF46C
117#define REG_AUDIO_MUTE 0xF4E7
118#define REG_AUDIO_BEEP 0xF4D0
119/* USB port power or not: rd/wr */
120#define REG_USB0_FLAG 0xF461
121#define REG_USB1_FLAG 0xF462
122#define REG_USB2_FLAG 0xF463
123#define BIT_USB_FLAG_ON 1
124#define BIT_USB_FLAG_OFF 0
125/* LID */
126#define REG_LID_DETECT 0xF4BD
127#define BIT_LID_DETECT_ON 1
128#define BIT_LID_DETECT_OFF 0
129/* CRT */
130#define REG_CRT_DETECT 0xF4AD
131#define BIT_CRT_DETECT_PLUG 1
132#define BIT_CRT_DETECT_UNPLUG 0
133/* LCD backlight brightness adjust: 9 levels */
134#define REG_DISPLAY_BRIGHTNESS 0xF4F5
135/* Black screen Status */
136#define BIT_DISPLAY_LCD_ON 1
137#define BIT_DISPLAY_LCD_OFF 0
138/* LCD backlight control: off/restore */
139#define REG_BACKLIGHT_CTRL 0xF7BD
140#define BIT_BACKLIGHT_ON 1
141#define BIT_BACKLIGHT_OFF 0
142/* Reset the machine auto-clear: rd/wr */
143#define REG_RESET 0xF4EC
144#define BIT_RESET_ON 1
145/* Light the led: rd/wr */
146#define REG_LED 0xF4C8
147#define BIT_LED_RED_POWER (1 << 0)
148#define BIT_LED_ORANGE_POWER (1 << 1)
149#define BIT_LED_GREEN_CHARGE (1 << 2)
150#define BIT_LED_RED_CHARGE (1 << 3)
151#define BIT_LED_NUMLOCK (1 << 4)
152/* Test led mode, all led on/off */
153#define REG_LED_TEST 0xF4C2
154#define BIT_LED_TEST_IN 1
155#define BIT_LED_TEST_OUT 0
156/* Camera on/off */
157#define REG_CAMERA_STATUS 0xF46A
158#define BIT_CAMERA_STATUS_ON 1
159#define BIT_CAMERA_STATUS_OFF 0
160#define REG_CAMERA_CONTROL 0xF7B7
161#define BIT_CAMERA_CONTROL_OFF 0
162#define BIT_CAMERA_CONTROL_ON 1
163/* Wlan Status */
164#define REG_WLAN 0xF4FA
165#define BIT_WLAN_ON 1
166#define BIT_WLAN_OFF 0
167#define REG_DISPLAY_LCD 0xF79F
168
169/* SCI Event Number from EC */
170enum {
171 EVENT_LID = 0x23, /* LID open/close */
172 EVENT_DISPLAY_TOGGLE, /* Fn+F3 for display switch */
173 EVENT_SLEEP, /* Fn+F1 for entering sleep mode */
174 EVENT_OVERTEMP, /* Over-temperature happened */
175 EVENT_CRT_DETECT, /* CRT is connected */
176 EVENT_CAMERA, /* Camera on/off */
177 EVENT_USB_OC2, /* USB2 Over Current occurred */
178 EVENT_USB_OC0, /* USB0 Over Current occurred */
179 EVENT_BLACK_SCREEN, /* Turn on/off backlight */
180 EVENT_AUDIO_MUTE, /* Mute on/off */
181 EVENT_DISPLAY_BRIGHTNESS,/* LCD backlight brightness adjust */
182 EVENT_AC_BAT, /* AC & Battery relative issue */
183 EVENT_AUDIO_VOLUME, /* Volume adjust */
184 EVENT_WLAN, /* Wlan on/off */
185 EVENT_END
186};
187
188#endif /* !_EC_KB3310B_H */
diff --git a/arch/mips/loongson/lemote-2f/irq.c b/arch/mips/loongson/lemote-2f/irq.c
new file mode 100644
index 000000000000..77d32f9cf31e
--- /dev/null
+++ b/arch/mips/loongson/lemote-2f/irq.c
@@ -0,0 +1,134 @@
1/*
2 * Copyright (C) 2007 Lemote Inc.
3 * Author: Fuxin Zhang, zhangfx@lemote.com
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#include <linux/interrupt.h>
12#include <linux/module.h>
13
14#include <asm/irq_cpu.h>
15#include <asm/i8259.h>
16#include <asm/mipsregs.h>
17
18#include <loongson.h>
19#include <machine.h>
20
21#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */
22#define LOONGSON_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
23#define LOONGSON_NORTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 6) /* bonito */
24#define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 3) /* cpu serial port */
25#define LOONGSON_SOUTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 2) /* i8259 */
26
27#define LOONGSON_INT_BIT_INT0 (1 << 11)
28#define LOONGSON_INT_BIT_INT1 (1 << 12)
29
30/*
31 * The generic i8259_irq() make the kernel hang on booting. Since we cannot
32 * get the irq via the IRR directly, we access the ISR instead.
33 */
34int mach_i8259_irq(void)
35{
36 int irq, isr;
37
38 irq = -1;
39
40 if ((LOONGSON_INTISR & LOONGSON_INTEN) & LOONGSON_INT_BIT_INT0) {
41 spin_lock(&i8259A_lock);
42 isr = inb(PIC_MASTER_CMD) &
43 ~inb(PIC_MASTER_IMR) & ~(1 << PIC_CASCADE_IR);
44 if (!isr)
45 isr = (inb(PIC_SLAVE_CMD) & ~inb(PIC_SLAVE_IMR)) << 8;
46 irq = ffs(isr) - 1;
47 if (unlikely(irq == 7)) {
48 /*
49 * This may be a spurious interrupt.
50 *
51 * Read the interrupt status register (ISR). If the most
52 * significant bit is not set then there is no valid
53 * interrupt.
54 */
55 outb(0x0B, PIC_MASTER_ISR); /* ISR register */
56 if (~inb(PIC_MASTER_ISR) & 0x80)
57 irq = -1;
58 }
59 spin_unlock(&i8259A_lock);
60 }
61
62 return irq;
63}
64EXPORT_SYMBOL(mach_i8259_irq);
65
66static void i8259_irqdispatch(void)
67{
68 int irq;
69
70 irq = mach_i8259_irq();
71 if (irq >= 0)
72 do_IRQ(irq);
73 else
74 spurious_interrupt();
75}
76
77void mach_irq_dispatch(unsigned int pending)
78{
79 if (pending & CAUSEF_IP7)
80 do_IRQ(LOONGSON_TIMER_IRQ);
81 else if (pending & CAUSEF_IP6) { /* North Bridge, Perf counter */
82#ifdef CONFIG_OPROFILE
83 do_IRQ(LOONGSON2_PERFCNT_IRQ);
84#endif
85 bonito_irqdispatch();
86 } else if (pending & CAUSEF_IP3) /* CPU UART */
87 do_IRQ(LOONGSON_UART_IRQ);
88 else if (pending & CAUSEF_IP2) /* South Bridge */
89 i8259_irqdispatch();
90 else
91 spurious_interrupt();
92}
93
94void __init set_irq_trigger_mode(void)
95{
96 /* setup cs5536 as high level trigger */
97 LOONGSON_INTPOL = LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1;
98 LOONGSON_INTEDGE &= ~(LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1);
99}
100
101static irqreturn_t ip6_action(int cpl, void *dev_id)
102{
103 return IRQ_HANDLED;
104}
105
106struct irqaction ip6_irqaction = {
107 .handler = ip6_action,
108 .name = "cascade",
109 .flags = IRQF_SHARED,
110};
111
112struct irqaction cascade_irqaction = {
113 .handler = no_action,
114 .name = "cascade",
115};
116
117void __init mach_init_irq(void)
118{
119 /* init all controller
120 * 0-15 ------> i8259 interrupt
121 * 16-23 ------> mips cpu interrupt
122 * 32-63 ------> bonito irq
123 */
124
125 /* Sets the first-level interrupt dispatcher. */
126 mips_cpu_irq_init();
127 init_i8259_irqs();
128 bonito_irq_init();
129
130 /* setup north bridge irq (bonito) */
131 setup_irq(LOONGSON_NORTH_BRIDGE_IRQ, &ip6_irqaction);
132 /* setup source bridge irq (i8259) */
133 setup_irq(LOONGSON_SOUTH_BRIDGE_IRQ, &cascade_irqaction);
134}
diff --git a/arch/mips/loongson/lemote-2f/pm.c b/arch/mips/loongson/lemote-2f/pm.c
new file mode 100644
index 000000000000..d7af2e616592
--- /dev/null
+++ b/arch/mips/loongson/lemote-2f/pm.c
@@ -0,0 +1,149 @@
1/*
2 * Lemote loongson2f family machines' specific suspend support
3 *
4 * Copyright (C) 2009 Lemote Inc.
5 * Author: Wu Zhangjin <wuzj@lemote.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/suspend.h>
14#include <linux/interrupt.h>
15#include <linux/pm.h>
16#include <linux/i8042.h>
17#include <linux/module.h>
18
19#include <asm/i8259.h>
20#include <asm/mipsregs.h>
21#include <asm/bootinfo.h>
22
23#include <loongson.h>
24
25#include <cs5536/cs5536_mfgpt.h>
26#include "ec_kb3310b.h"
27
28#define I8042_KBD_IRQ 1
29#define I8042_CTR_KBDINT 0x01
30#define I8042_CTR_KBDDIS 0x10
31
32static unsigned char i8042_ctr;
33
34static int i8042_enable_kbd_port(void)
35{
36 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_RCTR)) {
37 pr_err("i8042.c: Can't read CTR while enabling i8042 kbd port."
38 "\n");
39 return -EIO;
40 }
41
42 i8042_ctr &= ~I8042_CTR_KBDDIS;
43 i8042_ctr |= I8042_CTR_KBDINT;
44
45 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
46 i8042_ctr &= ~I8042_CTR_KBDINT;
47 i8042_ctr |= I8042_CTR_KBDDIS;
48 pr_err("i8042.c: Failed to enable KBD port.\n");
49
50 return -EIO;
51 }
52
53 return 0;
54}
55
56void setup_wakeup_events(void)
57{
58 int irq_mask;
59
60 switch (mips_machtype) {
61 case MACH_LEMOTE_ML2F7:
62 case MACH_LEMOTE_YL2F89:
63 /* open the keyboard irq in i8259A */
64 outb((0xff & ~(1 << I8042_KBD_IRQ)), PIC_MASTER_IMR);
65 irq_mask = inb(PIC_MASTER_IMR);
66
67 /* enable keyboard port */
68 i8042_enable_kbd_port();
69
70 /* Wakeup CPU via SCI lid open event */
71 outb(irq_mask & ~(1 << PIC_CASCADE_IR), PIC_MASTER_IMR);
72 inb(PIC_MASTER_IMR);
73 outb(0xff & ~(1 << (SCI_IRQ_NUM - 8)), PIC_SLAVE_IMR);
74 inb(PIC_SLAVE_IMR);
75
76 break;
77
78 default:
79 break;
80 }
81}
82
83static struct delayed_work lid_task;
84static int initialized;
85/* yeeloong_report_lid_status will be implemented in yeeloong_laptop.c */
86sci_handler yeeloong_report_lid_status;
87EXPORT_SYMBOL(yeeloong_report_lid_status);
88static void yeeloong_lid_update_task(struct work_struct *work)
89{
90 if (yeeloong_report_lid_status)
91 yeeloong_report_lid_status(BIT_LID_DETECT_ON);
92}
93
94int wakeup_loongson(void)
95{
96 int irq;
97
98 /* query the interrupt number */
99 irq = mach_i8259_irq();
100 if (irq < 0)
101 return 0;
102
103 printk(KERN_INFO "%s: irq = %d\n", __func__, irq);
104
105 if (irq == I8042_KBD_IRQ)
106 return 1;
107 else if (irq == SCI_IRQ_NUM) {
108 int ret, sci_event;
109 /* query the event number */
110 ret = ec_query_seq(CMD_GET_EVENT_NUM);
111 if (ret < 0)
112 return 0;
113 sci_event = ec_get_event_num();
114 if (sci_event < 0)
115 return 0;
116 if (sci_event == EVENT_LID) {
117 int lid_status;
118 /* check the LID status */
119 lid_status = ec_read(REG_LID_DETECT);
120 /* wakeup cpu when people open the LID */
121 if (lid_status == BIT_LID_DETECT_ON) {
122 /* If we call it directly here, the WARNING
123 * will be sent out by getnstimeofday
124 * via "WARN_ON(timekeeping_suspended);"
125 * because we can not schedule in suspend mode.
126 */
127 if (initialized == 0) {
128 INIT_DELAYED_WORK(&lid_task,
129 yeeloong_lid_update_task);
130 initialized = 1;
131 }
132 schedule_delayed_work(&lid_task, 1);
133 return 1;
134 }
135 }
136 }
137
138 return 0;
139}
140
141void __weak mach_suspend(void)
142{
143 disable_mfgpt0_counter();
144}
145
146void __weak mach_resume(void)
147{
148 enable_mfgpt0_counter();
149}
diff --git a/arch/mips/loongson/lemote-2f/reset.c b/arch/mips/loongson/lemote-2f/reset.c
new file mode 100644
index 000000000000..51d1a60d5349
--- /dev/null
+++ b/arch/mips/loongson/lemote-2f/reset.c
@@ -0,0 +1,159 @@
1/* Board-specific reboot/shutdown routines
2 *
3 * Copyright (c) 2009 Philippe Vachon <philippe@cowpig.ca>
4 *
5 * Copyright (C) 2009 Lemote Inc.
6 * Author: Wu Zhangjin, wuzj@lemote.com
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/io.h>
15#include <linux/delay.h>
16#include <linux/types.h>
17
18#include <asm/bootinfo.h>
19
20#include <loongson.h>
21
22#include <cs5536/cs5536.h>
23#include "ec_kb3310b.h"
24
25static void reset_cpu(void)
26{
27 /*
28 * reset cpu to full speed, this is needed when enabling cpu frequency
29 * scalling
30 */
31 LOONGSON_CHIPCFG0 |= 0x7;
32}
33
34/* reset support for fuloong2f */
35
36static void fl2f_reboot(void)
37{
38 reset_cpu();
39
40 /* send a reset signal to south bridge.
41 *
42 * NOTE: if enable "Power Management" in kernel, rtl8169 will not reset
43 * normally with this reset operation and it will not work in PMON, but
44 * you can type halt command and then reboot, seems the hardware reset
45 * logic not work normally.
46 */
47 {
48 u32 hi, lo;
49 _rdmsr(DIVIL_MSR_REG(DIVIL_SOFT_RESET), &hi, &lo);
50 lo |= 0x00000001;
51 _wrmsr(DIVIL_MSR_REG(DIVIL_SOFT_RESET), hi, lo);
52 }
53}
54
55static void fl2f_shutdown(void)
56{
57 u32 hi, lo, val;
58 int gpio_base;
59
60 /* get gpio base */
61 _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_GPIO), &hi, &lo);
62 gpio_base = lo & 0xff00;
63
64 /* make cs5536 gpio13 output enable */
65 val = inl(gpio_base + GPIOL_OUT_EN);
66 val &= ~(1 << (16 + 13));
67 val |= (1 << 13);
68 outl(val, gpio_base + GPIOL_OUT_EN);
69 mmiowb();
70 /* make cs5536 gpio13 output low level voltage. */
71 val = inl(gpio_base + GPIOL_OUT_VAL) & ~(1 << (13));
72 val |= (1 << (16 + 13));
73 outl(val, gpio_base + GPIOL_OUT_VAL);
74 mmiowb();
75}
76
77/* reset support for yeeloong2f and mengloong2f notebook */
78
79void ml2f_reboot(void)
80{
81 reset_cpu();
82
83 /* sending an reset signal to EC(embedded controller) */
84 ec_write(REG_RESET, BIT_RESET_ON);
85}
86
87#define yl2f89_reboot ml2f_reboot
88
89/* menglong(7inches) laptop has different shutdown logic from 8.9inches */
90#define EC_SHUTDOWN_IO_PORT_HIGH 0xff2d
91#define EC_SHUTDOWN_IO_PORT_LOW 0xff2e
92#define EC_SHUTDOWN_IO_PORT_DATA 0xff2f
93#define REG_SHUTDOWN_HIGH 0xFC
94#define REG_SHUTDOWN_LOW 0x29
95#define BIT_SHUTDOWN_ON (1 << 1)
96
97static void ml2f_shutdown(void)
98{
99 u8 val;
100 u64 i;
101
102 outb(REG_SHUTDOWN_HIGH, EC_SHUTDOWN_IO_PORT_HIGH);
103 outb(REG_SHUTDOWN_LOW, EC_SHUTDOWN_IO_PORT_LOW);
104 mmiowb();
105 val = inb(EC_SHUTDOWN_IO_PORT_DATA);
106 outb(val & (~BIT_SHUTDOWN_ON), EC_SHUTDOWN_IO_PORT_DATA);
107 mmiowb();
108 /* need enough wait here... how many microseconds needs? */
109 for (i = 0; i < 0x10000; i++)
110 delay();
111 outb(val | BIT_SHUTDOWN_ON, EC_SHUTDOWN_IO_PORT_DATA);
112 mmiowb();
113}
114
115static void yl2f89_shutdown(void)
116{
117 /* cpu-gpio0 output low */
118 LOONGSON_GPIODATA &= ~0x00000001;
119 /* cpu-gpio0 as output */
120 LOONGSON_GPIOIE &= ~0x00000001;
121}
122
123void mach_prepare_reboot(void)
124{
125 switch (mips_machtype) {
126 case MACH_LEMOTE_FL2F:
127 case MACH_LEMOTE_NAS:
128 case MACH_LEMOTE_LL2F:
129 fl2f_reboot();
130 break;
131 case MACH_LEMOTE_ML2F7:
132 ml2f_reboot();
133 break;
134 case MACH_LEMOTE_YL2F89:
135 yl2f89_reboot();
136 break;
137 default:
138 break;
139 }
140}
141
142void mach_prepare_shutdown(void)
143{
144 switch (mips_machtype) {
145 case MACH_LEMOTE_FL2F:
146 case MACH_LEMOTE_NAS:
147 case MACH_LEMOTE_LL2F:
148 fl2f_shutdown();
149 break;
150 case MACH_LEMOTE_ML2F7:
151 ml2f_shutdown();
152 break;
153 case MACH_LEMOTE_YL2F89:
154 yl2f89_shutdown();
155 break;
156 default:
157 break;
158 }
159}
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 454b53924490..8f2f8e9d8b21 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -35,6 +35,7 @@
35 * better performance by compiling with -msoft-float! 35 * better performance by compiling with -msoft-float!
36 */ 36 */
37#include <linux/sched.h> 37#include <linux/sched.h>
38#include <linux/module.h>
38#include <linux/debugfs.h> 39#include <linux/debugfs.h>
39 40
40#include <asm/inst.h> 41#include <asm/inst.h>
@@ -68,7 +69,9 @@ static int fpux_emu(struct pt_regs *,
68 69
69/* Further private data for which no space exists in mips_fpu_struct */ 70/* Further private data for which no space exists in mips_fpu_struct */
70 71
71struct mips_fpu_emulator_stats fpuemustats; 72#ifdef CONFIG_DEBUG_FS
73DEFINE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
74#endif
72 75
73/* Control registers */ 76/* Control registers */
74 77
@@ -209,7 +212,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
209 unsigned int cond; 212 unsigned int cond;
210 213
211 if (get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) { 214 if (get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) {
212 fpuemustats.errors++; 215 MIPS_FPU_EMU_INC_STATS(errors);
213 return SIGBUS; 216 return SIGBUS;
214 } 217 }
215 218
@@ -240,7 +243,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
240 return SIGILL; 243 return SIGILL;
241 } 244 }
242 if (get_user(ir, (mips_instruction __user *) emulpc)) { 245 if (get_user(ir, (mips_instruction __user *) emulpc)) {
243 fpuemustats.errors++; 246 MIPS_FPU_EMU_INC_STATS(errors);
244 return SIGBUS; 247 return SIGBUS;
245 } 248 }
246 /* __compute_return_epc() will have updated cp0_epc */ 249 /* __compute_return_epc() will have updated cp0_epc */
@@ -253,16 +256,16 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
253 } 256 }
254 257
255 emul: 258 emul:
256 fpuemustats.emulated++; 259 MIPS_FPU_EMU_INC_STATS(emulated);
257 switch (MIPSInst_OPCODE(ir)) { 260 switch (MIPSInst_OPCODE(ir)) {
258 case ldc1_op:{ 261 case ldc1_op:{
259 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + 262 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
260 MIPSInst_SIMM(ir)); 263 MIPSInst_SIMM(ir));
261 u64 val; 264 u64 val;
262 265
263 fpuemustats.loads++; 266 MIPS_FPU_EMU_INC_STATS(loads);
264 if (get_user(val, va)) { 267 if (get_user(val, va)) {
265 fpuemustats.errors++; 268 MIPS_FPU_EMU_INC_STATS(errors);
266 return SIGBUS; 269 return SIGBUS;
267 } 270 }
268 DITOREG(val, MIPSInst_RT(ir)); 271 DITOREG(val, MIPSInst_RT(ir));
@@ -274,10 +277,10 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
274 MIPSInst_SIMM(ir)); 277 MIPSInst_SIMM(ir));
275 u64 val; 278 u64 val;
276 279
277 fpuemustats.stores++; 280 MIPS_FPU_EMU_INC_STATS(stores);
278 DIFROMREG(val, MIPSInst_RT(ir)); 281 DIFROMREG(val, MIPSInst_RT(ir));
279 if (put_user(val, va)) { 282 if (put_user(val, va)) {
280 fpuemustats.errors++; 283 MIPS_FPU_EMU_INC_STATS(errors);
281 return SIGBUS; 284 return SIGBUS;
282 } 285 }
283 break; 286 break;
@@ -288,9 +291,9 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
288 MIPSInst_SIMM(ir)); 291 MIPSInst_SIMM(ir));
289 u32 val; 292 u32 val;
290 293
291 fpuemustats.loads++; 294 MIPS_FPU_EMU_INC_STATS(loads);
292 if (get_user(val, va)) { 295 if (get_user(val, va)) {
293 fpuemustats.errors++; 296 MIPS_FPU_EMU_INC_STATS(errors);
294 return SIGBUS; 297 return SIGBUS;
295 } 298 }
296 SITOREG(val, MIPSInst_RT(ir)); 299 SITOREG(val, MIPSInst_RT(ir));
@@ -302,10 +305,10 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
302 MIPSInst_SIMM(ir)); 305 MIPSInst_SIMM(ir));
303 u32 val; 306 u32 val;
304 307
305 fpuemustats.stores++; 308 MIPS_FPU_EMU_INC_STATS(stores);
306 SIFROMREG(val, MIPSInst_RT(ir)); 309 SIFROMREG(val, MIPSInst_RT(ir));
307 if (put_user(val, va)) { 310 if (put_user(val, va)) {
308 fpuemustats.errors++; 311 MIPS_FPU_EMU_INC_STATS(errors);
309 return SIGBUS; 312 return SIGBUS;
310 } 313 }
311 break; 314 break;
@@ -429,7 +432,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
429 432
430 if (get_user(ir, 433 if (get_user(ir,
431 (mips_instruction __user *) xcp->cp0_epc)) { 434 (mips_instruction __user *) xcp->cp0_epc)) {
432 fpuemustats.errors++; 435 MIPS_FPU_EMU_INC_STATS(errors);
433 return SIGBUS; 436 return SIGBUS;
434 } 437 }
435 438
@@ -595,7 +598,7 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
595{ 598{
596 unsigned rcsr = 0; /* resulting csr */ 599 unsigned rcsr = 0; /* resulting csr */
597 600
598 fpuemustats.cp1xops++; 601 MIPS_FPU_EMU_INC_STATS(cp1xops);
599 602
600 switch (MIPSInst_FMA_FFMT(ir)) { 603 switch (MIPSInst_FMA_FFMT(ir)) {
601 case s_fmt:{ /* 0 */ 604 case s_fmt:{ /* 0 */
@@ -610,9 +613,9 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
610 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 613 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
611 xcp->regs[MIPSInst_FT(ir)]); 614 xcp->regs[MIPSInst_FT(ir)]);
612 615
613 fpuemustats.loads++; 616 MIPS_FPU_EMU_INC_STATS(loads);
614 if (get_user(val, va)) { 617 if (get_user(val, va)) {
615 fpuemustats.errors++; 618 MIPS_FPU_EMU_INC_STATS(errors);
616 return SIGBUS; 619 return SIGBUS;
617 } 620 }
618 SITOREG(val, MIPSInst_FD(ir)); 621 SITOREG(val, MIPSInst_FD(ir));
@@ -622,11 +625,11 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
622 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 625 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
623 xcp->regs[MIPSInst_FT(ir)]); 626 xcp->regs[MIPSInst_FT(ir)]);
624 627
625 fpuemustats.stores++; 628 MIPS_FPU_EMU_INC_STATS(stores);
626 629
627 SIFROMREG(val, MIPSInst_FS(ir)); 630 SIFROMREG(val, MIPSInst_FS(ir));
628 if (put_user(val, va)) { 631 if (put_user(val, va)) {
629 fpuemustats.errors++; 632 MIPS_FPU_EMU_INC_STATS(errors);
630 return SIGBUS; 633 return SIGBUS;
631 } 634 }
632 break; 635 break;
@@ -687,9 +690,9 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
687 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 690 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
688 xcp->regs[MIPSInst_FT(ir)]); 691 xcp->regs[MIPSInst_FT(ir)]);
689 692
690 fpuemustats.loads++; 693 MIPS_FPU_EMU_INC_STATS(loads);
691 if (get_user(val, va)) { 694 if (get_user(val, va)) {
692 fpuemustats.errors++; 695 MIPS_FPU_EMU_INC_STATS(errors);
693 return SIGBUS; 696 return SIGBUS;
694 } 697 }
695 DITOREG(val, MIPSInst_FD(ir)); 698 DITOREG(val, MIPSInst_FD(ir));
@@ -699,10 +702,10 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
699 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 702 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
700 xcp->regs[MIPSInst_FT(ir)]); 703 xcp->regs[MIPSInst_FT(ir)]);
701 704
702 fpuemustats.stores++; 705 MIPS_FPU_EMU_INC_STATS(stores);
703 DIFROMREG(val, MIPSInst_FS(ir)); 706 DIFROMREG(val, MIPSInst_FS(ir));
704 if (put_user(val, va)) { 707 if (put_user(val, va)) {
705 fpuemustats.errors++; 708 MIPS_FPU_EMU_INC_STATS(errors);
706 return SIGBUS; 709 return SIGBUS;
707 } 710 }
708 break; 711 break;
@@ -769,7 +772,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
769#endif 772#endif
770 } rv; /* resulting value */ 773 } rv; /* resulting value */
771 774
772 fpuemustats.cp1ops++; 775 MIPS_FPU_EMU_INC_STATS(cp1ops);
773 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { 776 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
774 case s_fmt:{ /* 0 */ 777 case s_fmt:{ /* 0 */
775 union { 778 union {
@@ -1240,7 +1243,7 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1240 prevepc = xcp->cp0_epc; 1243 prevepc = xcp->cp0_epc;
1241 1244
1242 if (get_user(insn, (mips_instruction __user *) xcp->cp0_epc)) { 1245 if (get_user(insn, (mips_instruction __user *) xcp->cp0_epc)) {
1243 fpuemustats.errors++; 1246 MIPS_FPU_EMU_INC_STATS(errors);
1244 return SIGBUS; 1247 return SIGBUS;
1245 } 1248 }
1246 if (insn == 0) 1249 if (insn == 0)
@@ -1276,33 +1279,50 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1276} 1279}
1277 1280
1278#ifdef CONFIG_DEBUG_FS 1281#ifdef CONFIG_DEBUG_FS
1282
1283static int fpuemu_stat_get(void *data, u64 *val)
1284{
1285 int cpu;
1286 unsigned long sum = 0;
1287 for_each_online_cpu(cpu) {
1288 struct mips_fpu_emulator_stats *ps;
1289 local_t *pv;
1290 ps = &per_cpu(fpuemustats, cpu);
1291 pv = (void *)ps + (unsigned long)data;
1292 sum += local_read(pv);
1293 }
1294 *val = sum;
1295 return 0;
1296}
1297DEFINE_SIMPLE_ATTRIBUTE(fops_fpuemu_stat, fpuemu_stat_get, NULL, "%llu\n");
1298
1279extern struct dentry *mips_debugfs_dir; 1299extern struct dentry *mips_debugfs_dir;
1280static int __init debugfs_fpuemu(void) 1300static int __init debugfs_fpuemu(void)
1281{ 1301{
1282 struct dentry *d, *dir; 1302 struct dentry *d, *dir;
1283 int i;
1284 static struct {
1285 const char *name;
1286 unsigned int *v;
1287 } vars[] __initdata = {
1288 { "emulated", &fpuemustats.emulated },
1289 { "loads", &fpuemustats.loads },
1290 { "stores", &fpuemustats.stores },
1291 { "cp1ops", &fpuemustats.cp1ops },
1292 { "cp1xops", &fpuemustats.cp1xops },
1293 { "errors", &fpuemustats.errors },
1294 };
1295 1303
1296 if (!mips_debugfs_dir) 1304 if (!mips_debugfs_dir)
1297 return -ENODEV; 1305 return -ENODEV;
1298 dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir); 1306 dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir);
1299 if (!dir) 1307 if (!dir)
1300 return -ENOMEM; 1308 return -ENOMEM;
1301 for (i = 0; i < ARRAY_SIZE(vars); i++) { 1309
1302 d = debugfs_create_u32(vars[i].name, S_IRUGO, dir, vars[i].v); 1310#define FPU_STAT_CREATE(M) \
1303 if (!d) 1311 do { \
1304 return -ENOMEM; 1312 d = debugfs_create_file(#M , S_IRUGO, dir, \
1305 } 1313 (void *)offsetof(struct mips_fpu_emulator_stats, M), \
1314 &fops_fpuemu_stat); \
1315 if (!d) \
1316 return -ENOMEM; \
1317 } while (0)
1318
1319 FPU_STAT_CREATE(emulated);
1320 FPU_STAT_CREATE(loads);
1321 FPU_STAT_CREATE(stores);
1322 FPU_STAT_CREATE(cp1ops);
1323 FPU_STAT_CREATE(cp1xops);
1324 FPU_STAT_CREATE(errors);
1325
1306 return 0; 1326 return 0;
1307} 1327}
1308__initcall(debugfs_fpuemu); 1328__initcall(debugfs_fpuemu);
diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c
index df7b9d928efc..36d975ae08f8 100644
--- a/arch/mips/math-emu/dsemul.c
+++ b/arch/mips/math-emu/dsemul.c
@@ -98,7 +98,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc)
98 err |= __put_user(cpc, &fr->epc); 98 err |= __put_user(cpc, &fr->epc);
99 99
100 if (unlikely(err)) { 100 if (unlikely(err)) {
101 fpuemustats.errors++; 101 MIPS_FPU_EMU_INC_STATS(errors);
102 return SIGBUS; 102 return SIGBUS;
103 } 103 }
104 104
@@ -136,7 +136,7 @@ int do_dsemulret(struct pt_regs *xcp)
136 err |= __get_user(cookie, &fr->cookie); 136 err |= __get_user(cookie, &fr->cookie);
137 137
138 if (unlikely(err || (insn != BREAK_MATH) || (cookie != BD_COOKIE))) { 138 if (unlikely(err || (insn != BREAK_MATH) || (cookie != BD_COOKIE))) {
139 fpuemustats.errors++; 139 MIPS_FPU_EMU_INC_STATS(errors);
140 return 0; 140 return 0;
141 } 141 }
142 142
diff --git a/arch/mips/mipssim/Makefile b/arch/mips/mipssim/Makefile
index 57f43c1c7882..41b96571315e 100644
--- a/arch/mips/mipssim/Makefile
+++ b/arch/mips/mipssim/Makefile
@@ -17,8 +17,7 @@
17# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 17# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18# 18#
19 19
20obj-y := sim_platform.o sim_setup.o sim_mem.o sim_time.o sim_int.o \ 20obj-y := sim_platform.o sim_setup.o sim_mem.o sim_time.o sim_int.o
21 sim_cmdline.o
22 21
23obj-$(CONFIG_EARLY_PRINTK) += sim_console.o 22obj-$(CONFIG_EARLY_PRINTK) += sim_console.o
24obj-$(CONFIG_MIPS_MT_SMTC) += sim_smtc.o 23obj-$(CONFIG_MIPS_MT_SMTC) += sim_smtc.o
diff --git a/arch/mips/mipssim/sim_setup.c b/arch/mips/mipssim/sim_setup.c
index 2877675c5f0d..0824f6af4777 100644
--- a/arch/mips/mipssim/sim_setup.c
+++ b/arch/mips/mipssim/sim_setup.c
@@ -61,7 +61,6 @@ void __init prom_init(void)
61 set_io_port_base(0xbfd00000); 61 set_io_port_base(0xbfd00000);
62 62
63 pr_info("\nLINUX started...\n"); 63 pr_info("\nLINUX started...\n");
64 prom_init_cmdline();
65 prom_meminit(); 64 prom_meminit();
66 65
67#ifdef CONFIG_MIPS_MT_SMP 66#ifdef CONFIG_MIPS_MT_SMP
diff --git a/arch/mips/mm/cerr-sb1.c b/arch/mips/mm/cerr-sb1.c
index 1bd1f18ac23c..3571090ba178 100644
--- a/arch/mips/mm/cerr-sb1.c
+++ b/arch/mips/mm/cerr-sb1.c
@@ -567,13 +567,10 @@ static uint32_t extract_dc(unsigned short addr, int data)
567 datalo = ((unsigned long long)datalohi << 32) | datalolo; 567 datalo = ((unsigned long long)datalohi << 32) | datalolo;
568 ecc = dc_ecc(datalo); 568 ecc = dc_ecc(datalo);
569 if (ecc != datahi) { 569 if (ecc != datahi) {
570 int bits = 0; 570 int bits;
571 bad_ecc |= 1 << (3-offset); 571 bad_ecc |= 1 << (3-offset);
572 ecc ^= datahi; 572 ecc ^= datahi;
573 while (ecc) { 573 bits = hweight8(ecc);
574 if (ecc & 1) bits++;
575 ecc >>= 1;
576 }
577 res |= (bits == 1) ? CP0_CERRD_DATA_SBE : CP0_CERRD_DATA_DBE; 574 res |= (bits == 1) ? CP0_CERRD_DATA_SBE : CP0_CERRD_DATA_DBE;
578 } 575 }
579 printk(" %02X-%016llX", datahi, datalo); 576 printk(" %02X-%016llX", datahi, datalo);
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 8d1f4f363049..9e8d00389eef 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -462,7 +462,9 @@ void __init_refok free_initmem(void)
462 __pa_symbol(&__init_end)); 462 __pa_symbol(&__init_end));
463} 463}
464 464
465#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
465unsigned long pgd_current[NR_CPUS]; 466unsigned long pgd_current[NR_CPUS];
467#endif
466/* 468/*
467 * On 64-bit we've got three-level pagetables with a slightly 469 * On 64-bit we've got three-level pagetables with a slightly
468 * different layout ... 470 * different layout ...
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index bb1719a55d22..3d0baa4a842d 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -160,6 +160,12 @@ static u32 tlb_handler[128] __cpuinitdata;
160static struct uasm_label labels[128] __cpuinitdata; 160static struct uasm_label labels[128] __cpuinitdata;
161static struct uasm_reloc relocs[128] __cpuinitdata; 161static struct uasm_reloc relocs[128] __cpuinitdata;
162 162
163#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
164/*
165 * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current,
166 * we cannot do r3000 under these circumstances.
167 */
168
163/* 169/*
164 * The R3000 TLB handler is simple. 170 * The R3000 TLB handler is simple.
165 */ 171 */
@@ -199,6 +205,7 @@ static void __cpuinit build_r3000_tlb_refill_handler(void)
199 205
200 dump_handler((u32 *)ebase, 32); 206 dump_handler((u32 *)ebase, 32);
201} 207}
208#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
202 209
203/* 210/*
204 * The R4000 TLB handler is much more complicated. We have two 211 * The R4000 TLB handler is much more complicated. We have two
@@ -497,8 +504,9 @@ static void __cpuinit
497build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 504build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
498 unsigned int tmp, unsigned int ptr) 505 unsigned int tmp, unsigned int ptr)
499{ 506{
507#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
500 long pgdc = (long)pgd_current; 508 long pgdc = (long)pgd_current;
501 509#endif
502 /* 510 /*
503 * The vmalloc handling is not in the hotpath. 511 * The vmalloc handling is not in the hotpath.
504 */ 512 */
@@ -506,7 +514,15 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
506 uasm_il_bltz(p, r, tmp, label_vmalloc); 514 uasm_il_bltz(p, r, tmp, label_vmalloc);
507 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ 515 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
508 516
509#ifdef CONFIG_SMP 517#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
518 /*
519 * &pgd << 11 stored in CONTEXT [23..63].
520 */
521 UASM_i_MFC0(p, ptr, C0_CONTEXT);
522 uasm_i_dins(p, ptr, 0, 0, 23); /* Clear lower 23 bits of context. */
523 uasm_i_ori(p, ptr, ptr, 0x540); /* 1 0 1 0 1 << 6 xkphys cached */
524 uasm_i_drotr(p, ptr, ptr, 11);
525#elif defined(CONFIG_SMP)
510# ifdef CONFIG_MIPS_MT_SMTC 526# ifdef CONFIG_MIPS_MT_SMTC
511 /* 527 /*
512 * SMTC uses TCBind value as "CPU" index 528 * SMTC uses TCBind value as "CPU" index
@@ -520,7 +536,7 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
520 */ 536 */
521 uasm_i_dmfc0(p, ptr, C0_CONTEXT); 537 uasm_i_dmfc0(p, ptr, C0_CONTEXT);
522 uasm_i_dsrl(p, ptr, ptr, 23); 538 uasm_i_dsrl(p, ptr, ptr, 23);
523#endif 539# endif
524 UASM_i_LA_mostly(p, tmp, pgdc); 540 UASM_i_LA_mostly(p, tmp, pgdc);
525 uasm_i_daddu(p, ptr, ptr, tmp); 541 uasm_i_daddu(p, ptr, ptr, tmp);
526 uasm_i_dmfc0(p, tmp, C0_BADVADDR); 542 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
@@ -1033,6 +1049,7 @@ build_pte_modifiable(u32 **p, struct uasm_reloc **r,
1033 iPTE_LW(p, pte, ptr); 1049 iPTE_LW(p, pte, ptr);
1034} 1050}
1035 1051
1052#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1036/* 1053/*
1037 * R3000 style TLB load/store/modify handlers. 1054 * R3000 style TLB load/store/modify handlers.
1038 */ 1055 */
@@ -1184,6 +1201,7 @@ static void __cpuinit build_r3000_tlb_modify_handler(void)
1184 1201
1185 dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm)); 1202 dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm));
1186} 1203}
1204#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
1187 1205
1188/* 1206/*
1189 * R4000 style TLB load/store/modify handlers. 1207 * R4000 style TLB load/store/modify handlers.
@@ -1400,6 +1418,7 @@ void __cpuinit build_tlb_refill_handler(void)
1400 case CPU_TX3912: 1418 case CPU_TX3912:
1401 case CPU_TX3922: 1419 case CPU_TX3922:
1402 case CPU_TX3927: 1420 case CPU_TX3927:
1421#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1403 build_r3000_tlb_refill_handler(); 1422 build_r3000_tlb_refill_handler();
1404 if (!run_once) { 1423 if (!run_once) {
1405 build_r3000_tlb_load_handler(); 1424 build_r3000_tlb_load_handler();
@@ -1407,6 +1426,9 @@ void __cpuinit build_tlb_refill_handler(void)
1407 build_r3000_tlb_modify_handler(); 1426 build_r3000_tlb_modify_handler();
1408 run_once++; 1427 run_once++;
1409 } 1428 }
1429#else
1430 panic("No R3000 TLB refill handler");
1431#endif
1410 break; 1432 break;
1411 1433
1412 case CPU_R6000: 1434 case CPU_R6000:
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index f467199676a8..0a165c5179a1 100644
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -60,11 +60,11 @@ enum opcode {
60 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl, 60 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
61 insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0, 61 insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0,
62 insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, 62 insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
63 insn_dsrl32, insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr, 63 insn_dsrl32, insn_drotr, insn_dsubu, insn_eret, insn_j, insn_jal,
64 insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, 64 insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0,
65 insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd, 65 insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd,
66 insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw, 66 insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw,
67 insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori 67 insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, insn_dins
68}; 68};
69 69
70struct insn { 70struct insn {
@@ -104,6 +104,7 @@ static struct insn insn_table[] __cpuinitdata = {
104 { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE }, 104 { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
105 { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE }, 105 { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
106 { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE }, 106 { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
107 { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
107 { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD }, 108 { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
108 { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 }, 109 { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 },
109 { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM }, 110 { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
@@ -132,6 +133,7 @@ static struct insn insn_table[] __cpuinitdata = {
132 { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 }, 133 { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 },
133 { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD }, 134 { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD },
134 { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, 135 { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
136 { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
135 { insn_invalid, 0, 0 } 137 { insn_invalid, 0, 0 }
136}; 138};
137 139
@@ -304,6 +306,12 @@ Ip_u2u1s3(op) \
304 build_insn(buf, insn##op, b, a, c); \ 306 build_insn(buf, insn##op, b, a, c); \
305} 307}
306 308
309#define I_u2u1msbu3(op) \
310Ip_u2u1msbu3(op) \
311{ \
312 build_insn(buf, insn##op, b, a, c+d-1, c); \
313}
314
307#define I_u1u2(op) \ 315#define I_u1u2(op) \
308Ip_u1u2(op) \ 316Ip_u1u2(op) \
309{ \ 317{ \
@@ -349,6 +357,7 @@ I_u2u1u3(_dsll32)
349I_u2u1u3(_dsra) 357I_u2u1u3(_dsra)
350I_u2u1u3(_dsrl) 358I_u2u1u3(_dsrl)
351I_u2u1u3(_dsrl32) 359I_u2u1u3(_dsrl32)
360I_u2u1u3(_drotr)
352I_u3u1u2(_dsubu) 361I_u3u1u2(_dsubu)
353I_0(_eret) 362I_0(_eret)
354I_u1(_j) 363I_u1(_j)
@@ -377,6 +386,7 @@ I_0(_tlbwi)
377I_0(_tlbwr) 386I_0(_tlbwr)
378I_u3u1u2(_xor) 387I_u3u1u2(_xor)
379I_u2u1u3(_xori) 388I_u2u1u3(_xori)
389I_u2u1msbu3(_dins);
380 390
381/* Handle labels. */ 391/* Handle labels. */
382void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid) 392void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
diff --git a/arch/mips/mm/uasm.h b/arch/mips/mm/uasm.h
index c6d1e3dd82d4..3d153edaa51e 100644
--- a/arch/mips/mm/uasm.h
+++ b/arch/mips/mm/uasm.h
@@ -34,6 +34,11 @@ uasm_i##op(u32 **buf, unsigned int a, signed int b, unsigned int c)
34void __cpuinit \ 34void __cpuinit \
35uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c) 35uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c)
36 36
37#define Ip_u2u1msbu3(op) \
38void __cpuinit \
39uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \
40 unsigned int d)
41
37#define Ip_u1u2(op) \ 42#define Ip_u1u2(op) \
38void __cpuinit uasm_i##op(u32 **buf, unsigned int a, unsigned int b) 43void __cpuinit uasm_i##op(u32 **buf, unsigned int a, unsigned int b)
39 44
@@ -65,6 +70,7 @@ Ip_u2u1u3(_dsll32);
65Ip_u2u1u3(_dsra); 70Ip_u2u1u3(_dsra);
66Ip_u2u1u3(_dsrl); 71Ip_u2u1u3(_dsrl);
67Ip_u2u1u3(_dsrl32); 72Ip_u2u1u3(_dsrl32);
73Ip_u2u1u3(_drotr);
68Ip_u3u1u2(_dsubu); 74Ip_u3u1u2(_dsubu);
69Ip_0(_eret); 75Ip_0(_eret);
70Ip_u1(_j); 76Ip_u1(_j);
@@ -93,6 +99,7 @@ Ip_0(_tlbwi);
93Ip_0(_tlbwr); 99Ip_0(_tlbwr);
94Ip_u3u1u2(_xor); 100Ip_u3u1u2(_xor);
95Ip_u2u1u3(_xori); 101Ip_u2u1u3(_xori);
102Ip_u2u1msbu3(_dins);
96 103
97/* Handle labels. */ 104/* Handle labels. */
98struct uasm_label { 105struct uasm_label {
diff --git a/arch/mips/mti-malta/malta-memory.c b/arch/mips/mti-malta/malta-memory.c
index 9035c64bc5ed..b27419c84919 100644
--- a/arch/mips/mti-malta/malta-memory.c
+++ b/arch/mips/mti-malta/malta-memory.c
@@ -55,7 +55,7 @@ static struct prom_pmemblock * __init prom_getmdesc(void)
55 char *memsize_str; 55 char *memsize_str;
56 unsigned int memsize; 56 unsigned int memsize;
57 char *ptr; 57 char *ptr;
58 static char cmdline[CL_SIZE] __initdata; 58 static char cmdline[COMMAND_LINE_SIZE] __initdata;
59 59
60 /* otherwise look in the environment */ 60 /* otherwise look in the environment */
61 memsize_str = prom_getenv("memsize"); 61 memsize_str = prom_getenv("memsize");
diff --git a/arch/mips/nxp/pnx833x/common/interrupts.c b/arch/mips/nxp/pnx833x/common/interrupts.c
index 30533ba200e2..3a467c04f811 100644
--- a/arch/mips/nxp/pnx833x/common/interrupts.c
+++ b/arch/mips/nxp/pnx833x/common/interrupts.c
@@ -295,7 +295,7 @@ static int pnx833x_set_type_gpio_irq(unsigned int irq, unsigned int flow_type)
295} 295}
296 296
297static struct irq_chip pnx833x_pic_irq_type = { 297static struct irq_chip pnx833x_pic_irq_type = {
298 .typename = "PNX-PIC", 298 .name = "PNX-PIC",
299 .startup = pnx833x_startup_pic_irq, 299 .startup = pnx833x_startup_pic_irq,
300 .shutdown = pnx833x_shutdown_pic_irq, 300 .shutdown = pnx833x_shutdown_pic_irq,
301 .enable = pnx833x_enable_pic_irq, 301 .enable = pnx833x_enable_pic_irq,
@@ -305,7 +305,7 @@ static struct irq_chip pnx833x_pic_irq_type = {
305}; 305};
306 306
307static struct irq_chip pnx833x_gpio_irq_type = { 307static struct irq_chip pnx833x_gpio_irq_type = {
308 .typename = "PNX-GPIO", 308 .name = "PNX-GPIO",
309 .startup = pnx833x_startup_gpio_irq, 309 .startup = pnx833x_startup_gpio_irq,
310 .shutdown = pnx833x_disable_gpio_irq, 310 .shutdown = pnx833x_disable_gpio_irq,
311 .enable = pnx833x_enable_gpio_irq, 311 .enable = pnx833x_enable_gpio_irq,
diff --git a/arch/mips/oprofile/op_model_loongson2.c b/arch/mips/oprofile/op_model_loongson2.c
index 575cd1473475..475ff46712ab 100644
--- a/arch/mips/oprofile/op_model_loongson2.c
+++ b/arch/mips/oprofile/op_model_loongson2.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Loongson2 performance counter driver for oprofile 2 * Loongson2 performance counter driver for oprofile
3 * 3 *
4 * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology 4 * Copyright (C) 2009 Lemote Inc.
5 * Author: Yanhua <yanh@lemote.com> 5 * Author: Yanhua <yanh@lemote.com>
6 * Author: Wu Zhangjin <wuzj@lemote.com> 6 * Author: Wu Zhangjin <wuzj@lemote.com>
7 * 7 *
@@ -125,6 +125,9 @@ static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id)
125 */ 125 */
126 126
127 /* Check whether the irq belongs to me */ 127 /* Check whether the irq belongs to me */
128 enabled = read_c0_perfcnt() & LOONGSON2_PERFCNT_INT_EN;
129 if (!enabled)
130 return IRQ_NONE;
128 enabled = reg.cnt1_enabled | reg.cnt2_enabled; 131 enabled = reg.cnt1_enabled | reg.cnt2_enabled;
129 if (!enabled) 132 if (!enabled)
130 return IRQ_NONE; 133 return IRQ_NONE;
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 91bfe73a7f60..c9209ca6c8e7 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -22,13 +22,13 @@ obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
22# 22#
23# These are still pretty much in the old state, watch, go blind. 23# These are still pretty much in the old state, watch, go blind.
24# 24#
25obj-$(CONFIG_BASLER_EXCITE) += ops-titan.o pci-excite.o fixup-excite.o
26obj-$(CONFIG_LASAT) += pci-lasat.o 25obj-$(CONFIG_LASAT) += pci-lasat.o
27obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o 26obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
28obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o 27obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o
29obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o 28obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o
30obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o 29obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o
31obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-bonito64.o 30obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o
31obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o
32obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o 32obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o
33obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o 33obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o
34obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o 34obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o
diff --git a/arch/mips/pci/fixup-excite.c b/arch/mips/pci/fixup-excite.c
deleted file mode 100644
index cd64d9f177c4..000000000000
--- a/arch/mips/pci/fixup-excite.c
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * Copyright (C) 2004 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/pci.h>
22#include <excite.h>
23
24int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
25{
26 if (pin == 0)
27 return -1;
28
29 return USB_IRQ; /* USB controller is the only PCI device */
30}
31
32/* Do platform specific device initialization at pci_enable_device() time */
33int pcibios_plat_dev_init(struct pci_dev *dev)
34{
35 return 0;
36}
diff --git a/arch/mips/pci/fixup-fuloong2e.c b/arch/mips/pci/fixup-fuloong2e.c
index 0c4c7a81213f..4f6d8da07f93 100644
--- a/arch/mips/pci/fixup-fuloong2e.c
+++ b/arch/mips/pci/fixup-fuloong2e.c
@@ -13,7 +13,8 @@
13 */ 13 */
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/pci.h> 15#include <linux/pci.h>
16#include <asm/mips-boards/bonito64.h> 16
17#include <loongson.h>
17 18
18/* South bridge slot number is set by the pci probe process */ 19/* South bridge slot number is set by the pci probe process */
19static u8 sb_slot = 5; 20static u8 sb_slot = 5;
@@ -35,7 +36,7 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
35 break; 36 break;
36 } 37 }
37 } else { 38 } else {
38 irq = BONITO_IRQ_BASE + 25 + pin; 39 irq = LOONGSON_IRQ_BASE + 25 + pin;
39 } 40 }
40 return irq; 41 return irq;
41 42
diff --git a/arch/mips/pci/fixup-lemote2f.c b/arch/mips/pci/fixup-lemote2f.c
new file mode 100644
index 000000000000..caf2edeb02f0
--- /dev/null
+++ b/arch/mips/pci/fixup-lemote2f.c
@@ -0,0 +1,160 @@
1/*
2 * Copyright (C) 2008 Lemote Technology
3 * Copyright (C) 2004 ICT CAS
4 * Author: Li xiaoyu, lixy@ict.ac.cn
5 *
6 * Copyright (C) 2007 Lemote, Inc.
7 * Author: Fuxin Zhang, zhangfx@lemote.com
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14#include <linux/init.h>
15#include <linux/pci.h>
16
17#include <loongson.h>
18#include <cs5536/cs5536.h>
19#include <cs5536/cs5536_pci.h>
20
21/* PCI interrupt pins
22 *
23 * These should not be changed, or you should consider loongson2f interrupt
24 * register and your pci card dispatch
25 */
26
27#define PCIA 4
28#define PCIB 5
29#define PCIC 6
30#define PCID 7
31
32/* all the pci device has the PCIA pin, check the datasheet. */
33static char irq_tab[][5] __initdata = {
34 /* INTA INTB INTC INTD */
35 {0, 0, 0, 0, 0}, /* 11: Unused */
36 {0, 0, 0, 0, 0}, /* 12: Unused */
37 {0, 0, 0, 0, 0}, /* 13: Unused */
38 {0, 0, 0, 0, 0}, /* 14: Unused */
39 {0, 0, 0, 0, 0}, /* 15: Unused */
40 {0, 0, 0, 0, 0}, /* 16: Unused */
41 {0, PCIA, 0, 0, 0}, /* 17: RTL8110-0 */
42 {0, PCIB, 0, 0, 0}, /* 18: RTL8110-1 */
43 {0, PCIC, 0, 0, 0}, /* 19: SiI3114 */
44 {0, PCID, 0, 0, 0}, /* 20: 3-ports nec usb */
45 {0, PCIA, PCIB, PCIC, PCID}, /* 21: PCI-SLOT */
46 {0, 0, 0, 0, 0}, /* 22: Unused */
47 {0, 0, 0, 0, 0}, /* 23: Unused */
48 {0, 0, 0, 0, 0}, /* 24: Unused */
49 {0, 0, 0, 0, 0}, /* 25: Unused */
50 {0, 0, 0, 0, 0}, /* 26: Unused */
51 {0, 0, 0, 0, 0}, /* 27: Unused */
52};
53
54int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
55{
56 int virq;
57
58 if ((PCI_SLOT(dev->devfn) != PCI_IDSEL_CS5536)
59 && (PCI_SLOT(dev->devfn) < 32)) {
60 virq = irq_tab[slot][pin];
61 printk(KERN_INFO "slot: %d, pin: %d, irq: %d\n", slot, pin,
62 virq + LOONGSON_IRQ_BASE);
63 if (virq != 0)
64 return LOONGSON_IRQ_BASE + virq;
65 else
66 return 0;
67 } else if (PCI_SLOT(dev->devfn) == PCI_IDSEL_CS5536) { /* cs5536 */
68 switch (PCI_FUNC(dev->devfn)) {
69 case 2:
70 pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
71 CS5536_IDE_INTR);
72 return CS5536_IDE_INTR; /* for IDE */
73 case 3:
74 pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
75 CS5536_ACC_INTR);
76 return CS5536_ACC_INTR; /* for AUDIO */
77 case 4: /* for OHCI */
78 case 5: /* for EHCI */
79 case 6: /* for UDC */
80 case 7: /* for OTG */
81 pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
82 CS5536_USB_INTR);
83 return CS5536_USB_INTR;
84 }
85 return dev->irq;
86 } else {
87 printk(KERN_INFO " strange pci slot number.\n");
88 return 0;
89 }
90}
91
92/* Do platform specific device initialization at pci_enable_device() time */
93int pcibios_plat_dev_init(struct pci_dev *dev)
94{
95 return 0;
96}
97
98/* CS5536 SPEC. fixup */
99static void __init loongson_cs5536_isa_fixup(struct pci_dev *pdev)
100{
101 /* the uart1 and uart2 interrupt in PIC is enabled as default */
102 pci_write_config_dword(pdev, PCI_UART1_INT_REG, 1);
103 pci_write_config_dword(pdev, PCI_UART2_INT_REG, 1);
104}
105
106static void __init loongson_cs5536_ide_fixup(struct pci_dev *pdev)
107{
108 /* setting the mutex pin as IDE function */
109 pci_write_config_dword(pdev, PCI_IDE_CFG_REG,
110 CS5536_IDE_FLASH_SIGNATURE);
111}
112
113static void __init loongson_cs5536_acc_fixup(struct pci_dev *pdev)
114{
115 /* enable the AUDIO interrupt in PIC */
116 pci_write_config_dword(pdev, PCI_ACC_INT_REG, 1);
117
118 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xc0);
119}
120
121static void __init loongson_cs5536_ohci_fixup(struct pci_dev *pdev)
122{
123 /* enable the OHCI interrupt in PIC */
124 /* THE OHCI, EHCI, UDC, OTG are shared with interrupt in PIC */
125 pci_write_config_dword(pdev, PCI_OHCI_INT_REG, 1);
126}
127
128static void __init loongson_cs5536_ehci_fixup(struct pci_dev *pdev)
129{
130 u32 hi, lo;
131
132 /* Serial short detect enable */
133 _rdmsr(USB_MSR_REG(USB_CONFIG), &hi, &lo);
134 _wrmsr(USB_MSR_REG(USB_CONFIG), (1 << 1) | (1 << 2) | (1 << 3), lo);
135
136 /* setting the USB2.0 micro frame length */
137 pci_write_config_dword(pdev, PCI_EHCI_FLADJ_REG, 0x2000);
138}
139
140static void __init loongson_nec_fixup(struct pci_dev *pdev)
141{
142 unsigned int val;
143
144 pci_read_config_dword(pdev, 0xe0, &val);
145 /* Only 2 port be used */
146 pci_write_config_dword(pdev, 0xe0, (val & ~3) | 0x2);
147}
148
149DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA,
150 loongson_cs5536_isa_fixup);
151DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OHC,
152 loongson_cs5536_ohci_fixup);
153DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_EHC,
154 loongson_cs5536_ehci_fixup);
155DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_AUDIO,
156 loongson_cs5536_acc_fixup);
157DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_IDE,
158 loongson_cs5536_ide_fixup);
159DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
160 loongson_nec_fixup);
diff --git a/arch/mips/pci/ops-bonito64.c b/arch/mips/pci/ops-bonito64.c
index 54e55e7a2431..1b3e03f20c54 100644
--- a/arch/mips/pci/ops-bonito64.c
+++ b/arch/mips/pci/ops-bonito64.c
@@ -29,13 +29,8 @@
29#define PCI_ACCESS_READ 0 29#define PCI_ACCESS_READ 0
30#define PCI_ACCESS_WRITE 1 30#define PCI_ACCESS_WRITE 1
31 31
32#ifdef CONFIG_LEMOTE_FULOONG2E
33#define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(BONITO_PCICFG_BASE | (offset))
34#define ID_SEL_BEGIN 11
35#else
36#define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(_pcictrl_bonito_pcicfg + (offset)) 32#define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(_pcictrl_bonito_pcicfg + (offset))
37#define ID_SEL_BEGIN 10 33#define ID_SEL_BEGIN 10
38#endif
39#define MAX_DEV_NUM (31 - ID_SEL_BEGIN) 34#define MAX_DEV_NUM (31 - ID_SEL_BEGIN)
40 35
41 36
@@ -77,10 +72,8 @@ static int bonito64_pcibios_config_access(unsigned char access_type,
77 addrp = CFG_SPACE_REG(addr & 0xffff); 72 addrp = CFG_SPACE_REG(addr & 0xffff);
78 if (access_type == PCI_ACCESS_WRITE) { 73 if (access_type == PCI_ACCESS_WRITE) {
79 writel(cpu_to_le32(*data), addrp); 74 writel(cpu_to_le32(*data), addrp);
80#ifndef CONFIG_LEMOTE_FULOONG2E
81 /* Wait till done */ 75 /* Wait till done */
82 while (BONITO_PCIMSTAT & 0xF); 76 while (BONITO_PCIMSTAT & 0xF);
83#endif
84 } else { 77 } else {
85 *data = le32_to_cpu(readl(addrp)); 78 *data = le32_to_cpu(readl(addrp));
86 } 79 }
diff --git a/arch/mips/pci/ops-loongson2.c b/arch/mips/pci/ops-loongson2.c
new file mode 100644
index 000000000000..aa5d3da27212
--- /dev/null
+++ b/arch/mips/pci/ops-loongson2.c
@@ -0,0 +1,208 @@
1/*
2 * fuloong2e specific PCI support.
3 *
4 * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc.
5 * All rights reserved.
6 * Authors: Carsten Langgaard <carstenl@mips.com>
7 * Maciej W. Rozycki <macro@mips.com>
8 *
9 * Copyright (C) 2009 Lemote Inc.
10 * Author: Wu Zhangjin <wuzj@lemote.com>
11 *
12 * This program is free software; you can distribute it and/or modify it
13 * under the terms of the GNU General Public License (Version 2) as
14 * published by the Free Software Foundation.
15 */
16#include <linux/types.h>
17#include <linux/pci.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20
21#include <loongson.h>
22
23#ifdef CONFIG_CS5536
24#include <cs5536/cs5536_pci.h>
25#include <cs5536/cs5536.h>
26#endif
27
28#define PCI_ACCESS_READ 0
29#define PCI_ACCESS_WRITE 1
30
31#define CFG_SPACE_REG(offset) \
32 (void *)CKSEG1ADDR(LOONGSON_PCICFG_BASE | (offset))
33#define ID_SEL_BEGIN 11
34#define MAX_DEV_NUM (31 - ID_SEL_BEGIN)
35
36
37static int loongson_pcibios_config_access(unsigned char access_type,
38 struct pci_bus *bus,
39 unsigned int devfn, int where,
40 u32 *data)
41{
42 u32 busnum = bus->number;
43 u32 addr, type;
44 u32 dummy;
45 void *addrp;
46 int device = PCI_SLOT(devfn);
47 int function = PCI_FUNC(devfn);
48 int reg = where & ~3;
49
50 if (busnum == 0) {
51 /* board-specific part,currently,only fuloong2f,yeeloong2f
52 * use CS5536, fuloong2e use via686b, gdium has no
53 * south bridge
54 */
55#ifdef CONFIG_CS5536
56 /* cs5536_pci_conf_read4/write4() will call _rdmsr/_wrmsr() to
57 * access the regsters PCI_MSR_ADDR, PCI_MSR_DATA_LO,
58 * PCI_MSR_DATA_HI, which is bigger than PCI_MSR_CTRL, so, it
59 * will not go this branch, but the others. so, no calling dead
60 * loop here.
61 */
62 if ((PCI_IDSEL_CS5536 == device) && (reg < PCI_MSR_CTRL)) {
63 switch (access_type) {
64 case PCI_ACCESS_READ:
65 *data = cs5536_pci_conf_read4(function, reg);
66 break;
67 case PCI_ACCESS_WRITE:
68 cs5536_pci_conf_write4(function, reg, *data);
69 break;
70 }
71 return 0;
72 }
73#endif
74 /* Type 0 configuration for onboard PCI bus */
75 if (device > MAX_DEV_NUM)
76 return -1;
77
78 addr = (1 << (device + ID_SEL_BEGIN)) | (function << 8) | reg;
79 type = 0;
80 } else {
81 /* Type 1 configuration for offboard PCI bus */
82 addr = (busnum << 16) | (device << 11) | (function << 8) | reg;
83 type = 0x10000;
84 }
85
86 /* Clear aborts */
87 LOONGSON_PCICMD |= LOONGSON_PCICMD_MABORT_CLR | \
88 LOONGSON_PCICMD_MTABORT_CLR;
89
90 LOONGSON_PCIMAP_CFG = (addr >> 16) | type;
91
92 /* Flush Bonito register block */
93 dummy = LOONGSON_PCIMAP_CFG;
94 mmiowb();
95
96 addrp = CFG_SPACE_REG(addr & 0xffff);
97 if (access_type == PCI_ACCESS_WRITE)
98 writel(cpu_to_le32(*data), addrp);
99 else
100 *data = le32_to_cpu(readl(addrp));
101
102 /* Detect Master/Target abort */
103 if (LOONGSON_PCICMD & (LOONGSON_PCICMD_MABORT_CLR |
104 LOONGSON_PCICMD_MTABORT_CLR)) {
105 /* Error occurred */
106
107 /* Clear bits */
108 LOONGSON_PCICMD |= (LOONGSON_PCICMD_MABORT_CLR |
109 LOONGSON_PCICMD_MTABORT_CLR);
110
111 return -1;
112 }
113
114 return 0;
115
116}
117
118
119/*
120 * We can't address 8 and 16 bit words directly. Instead we have to
121 * read/write a 32bit word and mask/modify the data we actually want.
122 */
123static int loongson_pcibios_read(struct pci_bus *bus, unsigned int devfn,
124 int where, int size, u32 *val)
125{
126 u32 data = 0;
127
128 if ((size == 2) && (where & 1))
129 return PCIBIOS_BAD_REGISTER_NUMBER;
130 else if ((size == 4) && (where & 3))
131 return PCIBIOS_BAD_REGISTER_NUMBER;
132
133 if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
134 &data))
135 return -1;
136
137 if (size == 1)
138 *val = (data >> ((where & 3) << 3)) & 0xff;
139 else if (size == 2)
140 *val = (data >> ((where & 3) << 3)) & 0xffff;
141 else
142 *val = data;
143
144 return PCIBIOS_SUCCESSFUL;
145}
146
147static int loongson_pcibios_write(struct pci_bus *bus, unsigned int devfn,
148 int where, int size, u32 val)
149{
150 u32 data = 0;
151
152 if ((size == 2) && (where & 1))
153 return PCIBIOS_BAD_REGISTER_NUMBER;
154 else if ((size == 4) && (where & 3))
155 return PCIBIOS_BAD_REGISTER_NUMBER;
156
157 if (size == 4)
158 data = val;
159 else {
160 if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
161 where, &data))
162 return -1;
163
164 if (size == 1)
165 data = (data & ~(0xff << ((where & 3) << 3))) |
166 (val << ((where & 3) << 3));
167 else if (size == 2)
168 data = (data & ~(0xffff << ((where & 3) << 3))) |
169 (val << ((where & 3) << 3));
170 }
171
172 if (loongson_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where,
173 &data))
174 return -1;
175
176 return PCIBIOS_SUCCESSFUL;
177}
178
179struct pci_ops loongson_pci_ops = {
180 .read = loongson_pcibios_read,
181 .write = loongson_pcibios_write
182};
183
184#ifdef CONFIG_CS5536
185void _rdmsr(u32 msr, u32 *hi, u32 *lo)
186{
187 struct pci_bus bus = {
188 .number = PCI_BUS_CS5536
189 };
190 u32 devfn = PCI_DEVFN(PCI_IDSEL_CS5536, 0);
191 loongson_pcibios_write(&bus, devfn, PCI_MSR_ADDR, 4, msr);
192 loongson_pcibios_read(&bus, devfn, PCI_MSR_DATA_LO, 4, lo);
193 loongson_pcibios_read(&bus, devfn, PCI_MSR_DATA_HI, 4, hi);
194}
195EXPORT_SYMBOL(_rdmsr);
196
197void _wrmsr(u32 msr, u32 hi, u32 lo)
198{
199 struct pci_bus bus = {
200 .number = PCI_BUS_CS5536
201 };
202 u32 devfn = PCI_DEVFN(PCI_IDSEL_CS5536, 0);
203 loongson_pcibios_write(&bus, devfn, PCI_MSR_ADDR, 4, msr);
204 loongson_pcibios_write(&bus, devfn, PCI_MSR_DATA_LO, 4, lo);
205 loongson_pcibios_write(&bus, devfn, PCI_MSR_DATA_HI, 4, hi);
206}
207EXPORT_SYMBOL(_wrmsr);
208#endif
diff --git a/arch/mips/pci/pci-excite.c b/arch/mips/pci/pci-excite.c
deleted file mode 100644
index 8a56876afcc6..000000000000
--- a/arch/mips/pci/pci-excite.c
+++ /dev/null
@@ -1,149 +0,0 @@
1/*
2 * Copyright (C) 2004 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 * Based on the PMC-Sierra Yosemite board support by Ralf Baechle.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/pci.h>
24#include <linux/bitops.h>
25#include <asm/rm9k-ocd.h>
26#include <excite.h>
27
28
29extern struct pci_ops titan_pci_ops;
30
31
32static struct resource
33 mem_resource = {
34 .name = "PCI memory",
35 .start = EXCITE_PHYS_PCI_MEM,
36 .end = EXCITE_PHYS_PCI_MEM + EXCITE_SIZE_PCI_MEM - 1,
37 .flags = IORESOURCE_MEM
38 },
39 io_resource = {
40 .name = "PCI I/O",
41 .start = EXCITE_PHYS_PCI_IO,
42 .end = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1,
43 .flags = IORESOURCE_IO
44 };
45
46
47static struct pci_controller bx_controller = {
48 .pci_ops = &titan_pci_ops,
49 .mem_resource = &mem_resource,
50 .mem_offset = 0x00000000UL,
51 .io_resource = &io_resource,
52 .io_offset = 0x00000000UL
53};
54
55
56static char
57 iopage_failed[] __initdata = "Cannot allocate PCI I/O page",
58 modebits_no_pci[] __initdata = "PCI is not configured in mode bits";
59
60#define RM9000x2_OCD_HTSC 0x0604
61#define RM9000x2_OCD_HTBHL 0x060c
62#define RM9000x2_OCD_PCIHRST 0x078c
63
64#define RM9K_OCD_MODEBIT1 0x00d4 /* (MODEBIT1) Mode Bit 1 */
65#define RM9K_OCD_CPHDCR 0x00f4 /* CPU-PCI/HT Data Control. */
66
67#define PCISC_FB2B 0x00000200
68#define PCISC_MWICG 0x00000010
69#define PCISC_EMC 0x00000004
70#define PCISC_ERMA 0x00000002
71
72
73
74static int __init basler_excite_pci_setup(void)
75{
76 const unsigned int fullbars = memsize / (256 << 20);
77 unsigned int i;
78
79 /* Check modebits to see if PCI is really enabled. */
80 if (!((ocd_readl(RM9K_OCD_MODEBIT1) >> (47-32)) & 0x1))
81 panic(modebits_no_pci);
82
83 if (NULL == request_mem_region(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO,
84 "Memory-mapped PCI I/O page"))
85 panic(iopage_failed);
86
87 /* Enable PCI 0 as master for config cycles */
88 ocd_writel(PCISC_EMC | PCISC_ERMA, RM9000x2_OCD_HTSC);
89
90
91 /* Set up latency timer */
92 ocd_writel(0x8008, RM9000x2_OCD_HTBHL);
93
94 /* Setup host IO and Memory space */
95 ocd_writel((EXCITE_PHYS_PCI_IO >> 4) | 1, LKB7);
96 ocd_writel(((EXCITE_SIZE_PCI_IO >> 4) & 0x7fffff00) - 0x100, LKM7);
97 ocd_writel((EXCITE_PHYS_PCI_MEM >> 4) | 1, LKB8);
98 ocd_writel(((EXCITE_SIZE_PCI_MEM >> 4) & 0x7fffff00) - 0x100, LKM8);
99
100 /* Set up PCI BARs to map all installed memory */
101 for (i = 0; i < 6; i++) {
102 const unsigned int bar = 0x610 + i * 4;
103
104 if (i < fullbars) {
105 ocd_writel(0x10000000 * i, bar);
106 ocd_writel(0x01000000 * i, bar + 0x140);
107 ocd_writel(0x0ffff029, bar + 0x100);
108 continue;
109 }
110
111 if (i == fullbars) {
112 int o;
113 u32 mask;
114
115 const unsigned long rem = memsize - i * 0x10000000;
116 if (!rem) {
117 ocd_writel(0x00000000, bar + 0x100);
118 continue;
119 }
120
121 o = ffs(rem) - 1;
122 if (rem & ~(0x1 << o))
123 o++;
124 mask = ((0x1 << o) & 0x0ffff000) - 0x1000;
125 ocd_writel(0x10000000 * i, bar);
126 ocd_writel(0x01000000 * i, bar + 0x140);
127 ocd_writel(0x00000029 | mask, bar + 0x100);
128 continue;
129 }
130
131 ocd_writel(0x00000000, bar + 0x100);
132 }
133
134 /* Finally, enable the PCI interrupt */
135#if USB_IRQ > 7
136 set_c0_intcontrol(1 << USB_IRQ);
137#else
138 set_c0_status(1 << (USB_IRQ + 8));
139#endif
140
141 ioport_resource.start = EXCITE_PHYS_PCI_IO;
142 ioport_resource.end = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1;
143 set_io_port_base((unsigned long) ioremap_nocache(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO));
144 register_pci_controller(&bx_controller);
145 return 0;
146}
147
148
149arch_initcall(basler_excite_pci_setup);
diff --git a/arch/mips/powertv/Kconfig b/arch/mips/powertv/Kconfig
new file mode 100644
index 000000000000..ff0e7e3e6954
--- /dev/null
+++ b/arch/mips/powertv/Kconfig
@@ -0,0 +1,21 @@
1source "arch/mips/powertv/asic/Kconfig"
2
3config BOOTLOADER_DRIVER
4 bool "PowerTV Bootloader Driver Support"
5 default n
6 depends on POWERTV
7 help
8 Use this option if you want to load bootloader driver.
9
10config BOOTLOADER_FAMILY
11 string "POWERTV Bootloader Family string"
12 default "85"
13 depends on POWERTV && !BOOTLOADER_DRIVER
14 help
15 This value should be specified when the bootloader driver is disabled
16 and must be exactly two characters long. Families supported are:
17 R1 - RNG-100 R2 - RNG-200
18 A1 - Class A B1 - Class B
19 E1 - Class E F1 - Class F
20 44 - 45xx 46 - 46xx
21 85 - 85xx 86 - 86xx
diff --git a/arch/mips/powertv/Makefile b/arch/mips/powertv/Makefile
new file mode 100644
index 000000000000..2c516718affe
--- /dev/null
+++ b/arch/mips/powertv/Makefile
@@ -0,0 +1,28 @@
1#
2# Carsten Langgaard, carstenl@mips.com
3# Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4#
5# Carsten Langgaard, carstenl@mips.com
6# Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
7# Portions copyright (C) 2009 Cisco Systems, Inc.
8#
9# This program is free software; you can distribute it and/or modify it
10# under the terms of the GNU General Public License (Version 2) as
11# published by the Free Software Foundation.
12#
13# This program is distributed in the hope it will be useful, but WITHOUT
14# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16# for more details.
17#
18# You should have received a copy of the GNU General Public License along
19# with this program; if not, write to the Free Software Foundation, Inc.,
20# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21#
22# Makefile for the Cisco PowerTV-specific kernel interface routines
23# under Linux.
24#
25
26obj-y += cmdline.o init.o memory.o reset.o time.o powertv_setup.o asic/ pci/
27
28EXTRA_CFLAGS += -Wall -Werror
diff --git a/arch/mips/powertv/asic/Kconfig b/arch/mips/powertv/asic/Kconfig
new file mode 100644
index 000000000000..2016bfe94d66
--- /dev/null
+++ b/arch/mips/powertv/asic/Kconfig
@@ -0,0 +1,28 @@
1config MIN_RUNTIME_RESOURCES
2 bool "Support for minimum runtime resources"
3 default n
4 depends on POWERTV
5 help
6 Enables support for minimizing the number of (SA asic) runtime
7 resources that are preallocated by the kernel.
8
9config MIN_RUNTIME_DOCSIS
10 bool "Support for minimum DOCSIS resource"
11 default y
12 depends on MIN_RUNTIME_RESOURCES
13 help
14 Enables support for the preallocated DOCSIS resource.
15
16config MIN_RUNTIME_PMEM
17 bool "Support for minimum PMEM resource"
18 default y
19 depends on MIN_RUNTIME_RESOURCES
20 help
21 Enables support for the preallocated Memory resource.
22
23config MIN_RUNTIME_TFTP
24 bool "Support for minimum TFTP resource"
25 default y
26 depends on MIN_RUNTIME_RESOURCES
27 help
28 Enables support for the preallocated TFTP resource.
diff --git a/arch/mips/powertv/asic/Makefile b/arch/mips/powertv/asic/Makefile
new file mode 100644
index 000000000000..bebfdcff0443
--- /dev/null
+++ b/arch/mips/powertv/asic/Makefile
@@ -0,0 +1,23 @@
1#
2# Copyright (C) 2009 Scientific-Atlanta, Inc.
3#
4# This program is free software; you can redistribute it and/or modify
5# it under the terms of the GNU General Public License as published by
6# the Free Software Foundation; either version 2 of the License, or
7# (at your option) any later version.
8#
9# This program is distributed in the hope that it will be useful,
10# but WITHOUT ANY WARRANTY; without even the implied warranty of
11# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12# GNU General Public License for more details.
13#
14# You should have received a copy of the GNU General Public License
15# along with this program; if not, write to the Free Software
16# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17#
18
19obj-y += asic-calliope.o asic-cronus.o asic-zeus.o asic_devices.o asic_int.o \
20 irq_asic.o prealloc-calliope.o prealloc-cronus.o \
21 prealloc-cronuslite.o prealloc-zeus.o
22
23EXTRA_CFLAGS += -Wall -Werror
diff --git a/arch/mips/powertv/asic/asic-calliope.c b/arch/mips/powertv/asic/asic-calliope.c
new file mode 100644
index 000000000000..03d3884c6270
--- /dev/null
+++ b/arch/mips/powertv/asic/asic-calliope.c
@@ -0,0 +1,98 @@
1/*
2 * Locations of devices in the Calliope ASIC.
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: Ken Eppinett
21 * David Schleef <ds@schleef.org>
22 *
23 * Description: Defines the platform resources for the SA settop.
24 */
25
26#include <asm/mach-powertv/asic.h>
27
28const struct register_map calliope_register_map = {
29 .eic_slow0_strt_add = 0x800000,
30 .eic_cfg_bits = 0x800038,
31 .eic_ready_status = 0x80004c,
32
33 .chipver3 = 0xA00800,
34 .chipver2 = 0xA00804,
35 .chipver1 = 0xA00808,
36 .chipver0 = 0xA0080c,
37
38 /* The registers of IRBlaster */
39 .uart1_intstat = 0xA01800,
40 .uart1_inten = 0xA01804,
41 .uart1_config1 = 0xA01808,
42 .uart1_config2 = 0xA0180C,
43 .uart1_divisorhi = 0xA01810,
44 .uart1_divisorlo = 0xA01814,
45 .uart1_data = 0xA01818,
46 .uart1_status = 0xA0181C,
47
48 .int_stat_3 = 0xA02800,
49 .int_stat_2 = 0xA02804,
50 .int_stat_1 = 0xA02808,
51 .int_stat_0 = 0xA0280c,
52 .int_config = 0xA02810,
53 .int_int_scan = 0xA02818,
54 .ien_int_3 = 0xA02830,
55 .ien_int_2 = 0xA02834,
56 .ien_int_1 = 0xA02838,
57 .ien_int_0 = 0xA0283c,
58 .int_level_3_3 = 0xA02880,
59 .int_level_3_2 = 0xA02884,
60 .int_level_3_1 = 0xA02888,
61 .int_level_3_0 = 0xA0288c,
62 .int_level_2_3 = 0xA02890,
63 .int_level_2_2 = 0xA02894,
64 .int_level_2_1 = 0xA02898,
65 .int_level_2_0 = 0xA0289c,
66 .int_level_1_3 = 0xA028a0,
67 .int_level_1_2 = 0xA028a4,
68 .int_level_1_1 = 0xA028a8,
69 .int_level_1_0 = 0xA028ac,
70 .int_level_0_3 = 0xA028b0,
71 .int_level_0_2 = 0xA028b4,
72 .int_level_0_1 = 0xA028b8,
73 .int_level_0_0 = 0xA028bc,
74 .int_docsis_en = 0xA028F4,
75
76 .mips_pll_setup = 0x980000,
77 .usb_fs = 0x980030, /* -default 72800028- */
78 .test_bus = 0x9800CC,
79 .crt_spare = 0x9800d4,
80 .usb2_ohci_int_mask = 0x9A000c,
81 .usb2_strap = 0x9A0014,
82 .ehci_hcapbase = 0x9BFE00,
83 .ohci_hc_revision = 0x9BFC00,
84 .bcm1_bs_lmi_steer = 0x9E0004,
85 .usb2_control = 0x9E0054,
86 .usb2_stbus_obc = 0x9BFF00,
87 .usb2_stbus_mess_size = 0x9BFF04,
88 .usb2_stbus_chunk_size = 0x9BFF08,
89
90 .pcie_regs = 0x000000, /* -doesn't exist- */
91 .tim_ch = 0xA02C10,
92 .tim_cl = 0xA02C14,
93 .gpio_dout = 0xA02c20,
94 .gpio_din = 0xA02c24,
95 .gpio_dir = 0xA02c2C,
96 .watchdog = 0xA02c30,
97 .front_panel = 0x000000, /* -not used- */
98};
diff --git a/arch/mips/powertv/asic/asic-cronus.c b/arch/mips/powertv/asic/asic-cronus.c
new file mode 100644
index 000000000000..5f4589c9f83d
--- /dev/null
+++ b/arch/mips/powertv/asic/asic-cronus.c
@@ -0,0 +1,98 @@
1/*
2 * Locations of devices in the Cronus ASIC
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: Ken Eppinett
21 * David Schleef <ds@schleef.org>
22 *
23 * Description: Defines the platform resources for the SA settop.
24 */
25
26#include <asm/mach-powertv/asic.h>
27
28const struct register_map cronus_register_map = {
29 .eic_slow0_strt_add = 0x000000,
30 .eic_cfg_bits = 0x000038,
31 .eic_ready_status = 0x00004C,
32
33 .chipver3 = 0x2A0800,
34 .chipver2 = 0x2A0804,
35 .chipver1 = 0x2A0808,
36 .chipver0 = 0x2A080C,
37
38 /* The registers of IRBlaster */
39 .uart1_intstat = 0x2A1800,
40 .uart1_inten = 0x2A1804,
41 .uart1_config1 = 0x2A1808,
42 .uart1_config2 = 0x2A180C,
43 .uart1_divisorhi = 0x2A1810,
44 .uart1_divisorlo = 0x2A1814,
45 .uart1_data = 0x2A1818,
46 .uart1_status = 0x2A181C,
47
48 .int_stat_3 = 0x2A2800,
49 .int_stat_2 = 0x2A2804,
50 .int_stat_1 = 0x2A2808,
51 .int_stat_0 = 0x2A280C,
52 .int_config = 0x2A2810,
53 .int_int_scan = 0x2A2818,
54 .ien_int_3 = 0x2A2830,
55 .ien_int_2 = 0x2A2834,
56 .ien_int_1 = 0x2A2838,
57 .ien_int_0 = 0x2A283C,
58 .int_level_3_3 = 0x2A2880,
59 .int_level_3_2 = 0x2A2884,
60 .int_level_3_1 = 0x2A2888,
61 .int_level_3_0 = 0x2A288C,
62 .int_level_2_3 = 0x2A2890,
63 .int_level_2_2 = 0x2A2894,
64 .int_level_2_1 = 0x2A2898,
65 .int_level_2_0 = 0x2A289C,
66 .int_level_1_3 = 0x2A28A0,
67 .int_level_1_2 = 0x2A28A4,
68 .int_level_1_1 = 0x2A28A8,
69 .int_level_1_0 = 0x2A28AC,
70 .int_level_0_3 = 0x2A28B0,
71 .int_level_0_2 = 0x2A28B4,
72 .int_level_0_1 = 0x2A28B8,
73 .int_level_0_0 = 0x2A28BC,
74 .int_docsis_en = 0x2A28F4,
75
76 .mips_pll_setup = 0x1C0000,
77 .usb_fs = 0x1C0018,
78 .test_bus = 0x1C00CC,
79 .crt_spare = 0x1c00d4,
80 .usb2_ohci_int_mask = 0x20000C,
81 .usb2_strap = 0x200014,
82 .ehci_hcapbase = 0x21FE00,
83 .ohci_hc_revision = 0x1E0000,
84 .bcm1_bs_lmi_steer = 0x2E0008,
85 .usb2_control = 0x2E004C,
86 .usb2_stbus_obc = 0x21FF00,
87 .usb2_stbus_mess_size = 0x21FF04,
88 .usb2_stbus_chunk_size = 0x21FF08,
89
90 .pcie_regs = 0x220000,
91 .tim_ch = 0x2A2C10,
92 .tim_cl = 0x2A2C14,
93 .gpio_dout = 0x2A2C20,
94 .gpio_din = 0x2A2C24,
95 .gpio_dir = 0x2A2C2C,
96 .watchdog = 0x2A2C30,
97 .front_panel = 0x2A3800,
98};
diff --git a/arch/mips/powertv/asic/asic-zeus.c b/arch/mips/powertv/asic/asic-zeus.c
new file mode 100644
index 000000000000..1469daab920e
--- /dev/null
+++ b/arch/mips/powertv/asic/asic-zeus.c
@@ -0,0 +1,98 @@
1/*
2 * Locations of devices in the Zeus ASIC
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: Ken Eppinett
21 * David Schleef <ds@schleef.org>
22 *
23 * Description: Defines the platform resources for the SA settop.
24 */
25
26#include <asm/mach-powertv/asic.h>
27
28const struct register_map zeus_register_map = {
29 .eic_slow0_strt_add = 0x000000,
30 .eic_cfg_bits = 0x000038,
31 .eic_ready_status = 0x00004c,
32
33 .chipver3 = 0x280800,
34 .chipver2 = 0x280804,
35 .chipver1 = 0x280808,
36 .chipver0 = 0x28080c,
37
38 /* The registers of IRBlaster */
39 .uart1_intstat = 0x281800,
40 .uart1_inten = 0x281804,
41 .uart1_config1 = 0x281808,
42 .uart1_config2 = 0x28180C,
43 .uart1_divisorhi = 0x281810,
44 .uart1_divisorlo = 0x281814,
45 .uart1_data = 0x281818,
46 .uart1_status = 0x28181C,
47
48 .int_stat_3 = 0x282800,
49 .int_stat_2 = 0x282804,
50 .int_stat_1 = 0x282808,
51 .int_stat_0 = 0x28280c,
52 .int_config = 0x282810,
53 .int_int_scan = 0x282818,
54 .ien_int_3 = 0x282830,
55 .ien_int_2 = 0x282834,
56 .ien_int_1 = 0x282838,
57 .ien_int_0 = 0x28283c,
58 .int_level_3_3 = 0x282880,
59 .int_level_3_2 = 0x282884,
60 .int_level_3_1 = 0x282888,
61 .int_level_3_0 = 0x28288c,
62 .int_level_2_3 = 0x282890,
63 .int_level_2_2 = 0x282894,
64 .int_level_2_1 = 0x282898,
65 .int_level_2_0 = 0x28289c,
66 .int_level_1_3 = 0x2828a0,
67 .int_level_1_2 = 0x2828a4,
68 .int_level_1_1 = 0x2828a8,
69 .int_level_1_0 = 0x2828ac,
70 .int_level_0_3 = 0x2828b0,
71 .int_level_0_2 = 0x2828b4,
72 .int_level_0_1 = 0x2828b8,
73 .int_level_0_0 = 0x2828bc,
74 .int_docsis_en = 0x2828F4,
75
76 .mips_pll_setup = 0x1a0000,
77 .usb_fs = 0x1a0018,
78 .test_bus = 0x1a0238,
79 .crt_spare = 0x1a0090,
80 .usb2_ohci_int_mask = 0x1e000c,
81 .usb2_strap = 0x1e0014,
82 .ehci_hcapbase = 0x1FFE00,
83 .ohci_hc_revision = 0x1FFC00,
84 .bcm1_bs_lmi_steer = 0x2C0008,
85 .usb2_control = 0x2c01a0,
86 .usb2_stbus_obc = 0x1FFF00,
87 .usb2_stbus_mess_size = 0x1FFF04,
88 .usb2_stbus_chunk_size = 0x1FFF08,
89
90 .pcie_regs = 0x200000,
91 .tim_ch = 0x282C10,
92 .tim_cl = 0x282C14,
93 .gpio_dout = 0x282c20,
94 .gpio_din = 0x282c24,
95 .gpio_dir = 0x282c2C,
96 .watchdog = 0x282c30,
97 .front_panel = 0x283800,
98};
diff --git a/arch/mips/powertv/asic/asic_devices.c b/arch/mips/powertv/asic/asic_devices.c
new file mode 100644
index 000000000000..bae82880b6b5
--- /dev/null
+++ b/arch/mips/powertv/asic/asic_devices.c
@@ -0,0 +1,787 @@
1/*
2 * ASIC Device List Intialization
3 *
4 * Description: Defines the platform resources for the SA settop.
5 *
6 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 *
22 * Author: Ken Eppinett
23 * David Schleef <ds@schleef.org>
24 *
25 * Description: Defines the platform resources for the SA settop.
26 *
27 * NOTE: The bootloader allocates persistent memory at an address which is
28 * 16 MiB below the end of the highest address in KSEG0. All fixed
29 * address memory reservations must avoid this region.
30 */
31
32#include <linux/device.h>
33#include <linux/kernel.h>
34#include <linux/init.h>
35#include <linux/resource.h>
36#include <linux/serial_reg.h>
37#include <linux/io.h>
38#include <linux/bootmem.h>
39#include <linux/mm.h>
40#include <linux/platform_device.h>
41#include <linux/module.h>
42#include <asm/page.h>
43#include <linux/swap.h>
44#include <linux/highmem.h>
45#include <linux/dma-mapping.h>
46
47#include <asm/mach-powertv/asic.h>
48#include <asm/mach-powertv/asic_regs.h>
49#include <asm/mach-powertv/interrupts.h>
50
51#ifdef CONFIG_BOOTLOADER_DRIVER
52#include <asm/mach-powertv/kbldr.h>
53#endif
54#include <asm/bootinfo.h>
55
56#define BOOTLDRFAMILY(byte1, byte0) (((byte1) << 8) | (byte0))
57
58/*
59 * Forward Prototypes
60 */
61static void pmem_setup_resource(void);
62
63/*
64 * Global Variables
65 */
66enum asic_type asic;
67
68unsigned int platform_features;
69unsigned int platform_family;
70const struct register_map *register_map;
71EXPORT_SYMBOL(register_map); /* Exported for testing */
72unsigned long asic_phy_base;
73unsigned long asic_base;
74EXPORT_SYMBOL(asic_base); /* Exported for testing */
75struct resource *gp_resources;
76static bool usb_configured;
77
78/*
79 * Don't recommend to use it directly, it is usually used by kernel internally.
80 * Portable code should be using interfaces such as ioremp, dma_map_single, etc.
81 */
82unsigned long phys_to_bus_offset;
83EXPORT_SYMBOL(phys_to_bus_offset);
84
85/*
86 *
87 * IO Resource Definition
88 *
89 */
90
91struct resource asic_resource = {
92 .name = "ASIC Resource",
93 .start = 0,
94 .end = ASIC_IO_SIZE,
95 .flags = IORESOURCE_MEM,
96};
97
98/*
99 *
100 * USB Host Resource Definition
101 *
102 */
103
104static struct resource ehci_resources[] = {
105 {
106 .parent = &asic_resource,
107 .start = 0,
108 .end = 0xff,
109 .flags = IORESOURCE_MEM,
110 },
111 {
112 .start = irq_usbehci,
113 .end = irq_usbehci,
114 .flags = IORESOURCE_IRQ,
115 },
116};
117
118static u64 ehci_dmamask = DMA_BIT_MASK(32);
119
120static struct platform_device ehci_device = {
121 .name = "powertv-ehci",
122 .id = 0,
123 .num_resources = 2,
124 .resource = ehci_resources,
125 .dev = {
126 .dma_mask = &ehci_dmamask,
127 .coherent_dma_mask = DMA_BIT_MASK(32),
128 },
129};
130
131static struct resource ohci_resources[] = {
132 {
133 .parent = &asic_resource,
134 .start = 0,
135 .end = 0xff,
136 .flags = IORESOURCE_MEM,
137 },
138 {
139 .start = irq_usbohci,
140 .end = irq_usbohci,
141 .flags = IORESOURCE_IRQ,
142 },
143};
144
145static u64 ohci_dmamask = DMA_BIT_MASK(32);
146
147static struct platform_device ohci_device = {
148 .name = "powertv-ohci",
149 .id = 0,
150 .num_resources = 2,
151 .resource = ohci_resources,
152 .dev = {
153 .dma_mask = &ohci_dmamask,
154 .coherent_dma_mask = DMA_BIT_MASK(32),
155 },
156};
157
158static struct platform_device *platform_devices[] = {
159 &ehci_device,
160 &ohci_device,
161};
162
163/*
164 *
165 * Platform Configuration and Device Initialization
166 *
167 */
168static void __init fs_update(int pe, int md, int sdiv, int disable_div_by_3)
169{
170 int en_prg, byp, pwr, nsb, val;
171 int sout;
172
173 sout = 1;
174 en_prg = 1;
175 byp = 0;
176 nsb = 1;
177 pwr = 1;
178
179 val = ((sdiv << 29) | (md << 24) | (pe<<8) | (sout<<3) | (byp<<2) |
180 (nsb<<1) | (disable_div_by_3<<5));
181
182 asic_write(val, usb_fs);
183 asic_write(val | (en_prg<<4), usb_fs);
184 asic_write(val | (en_prg<<4) | pwr, usb_fs);
185}
186
187/*
188 * Allow override of bootloader-specified model
189 */
190static char __initdata cmdline[COMMAND_LINE_SIZE];
191
192#define FORCEFAMILY_PARAM "forcefamily"
193
194static __init int check_forcefamily(unsigned char forced_family[2])
195{
196 const char *p;
197
198 forced_family[0] = '\0';
199 forced_family[1] = '\0';
200
201 /* Check the command line for a forcefamily directive */
202 strncpy(cmdline, arcs_cmdline, COMMAND_LINE_SIZE - 1);
203 p = strstr(cmdline, FORCEFAMILY_PARAM);
204 if (p && (p != cmdline) && (*(p - 1) != ' '))
205 p = strstr(p, " " FORCEFAMILY_PARAM "=");
206
207 if (p) {
208 p += strlen(FORCEFAMILY_PARAM "=");
209
210 if (*p == '\0' || *(p + 1) == '\0' ||
211 (*(p + 2) != '\0' && *(p + 2) != ' '))
212 pr_err(FORCEFAMILY_PARAM " must be exactly two "
213 "characters long, ignoring value\n");
214
215 else {
216 forced_family[0] = *p;
217 forced_family[1] = *(p + 1);
218 }
219 }
220
221 return 0;
222}
223
224/*
225 * platform_set_family - determine major platform family type.
226 *
227 * Returns family type; -1 if none
228 * Returns the family type; -1 if none
229 *
230 */
231static __init noinline void platform_set_family(void)
232{
233#define BOOTLDRFAMILY(byte1, byte0) (((byte1) << 8) | (byte0))
234
235 unsigned char forced_family[2];
236 unsigned short bootldr_family;
237
238 check_forcefamily(forced_family);
239
240 if (forced_family[0] != '\0' && forced_family[1] != '\0')
241 bootldr_family = BOOTLDRFAMILY(forced_family[0],
242 forced_family[1]);
243 else {
244
245#ifdef CONFIG_BOOTLOADER_DRIVER
246 bootldr_family = (unsigned short) kbldr_GetSWFamily();
247#else
248#if defined(CONFIG_BOOTLOADER_FAMILY)
249 bootldr_family = (unsigned short) BOOTLDRFAMILY(
250 CONFIG_BOOTLOADER_FAMILY[0],
251 CONFIG_BOOTLOADER_FAMILY[1]);
252#else
253#error "Unknown Bootloader Family"
254#endif
255#endif
256 }
257
258 pr_info("Bootloader Family = 0x%04X\n", bootldr_family);
259
260 switch (bootldr_family) {
261 case BOOTLDRFAMILY('R', '1'):
262 platform_family = FAMILY_1500;
263 break;
264 case BOOTLDRFAMILY('4', '4'):
265 platform_family = FAMILY_4500;
266 break;
267 case BOOTLDRFAMILY('4', '6'):
268 platform_family = FAMILY_4600;
269 break;
270 case BOOTLDRFAMILY('A', '1'):
271 platform_family = FAMILY_4600VZA;
272 break;
273 case BOOTLDRFAMILY('8', '5'):
274 platform_family = FAMILY_8500;
275 break;
276 case BOOTLDRFAMILY('R', '2'):
277 platform_family = FAMILY_8500RNG;
278 break;
279 case BOOTLDRFAMILY('8', '6'):
280 platform_family = FAMILY_8600;
281 break;
282 case BOOTLDRFAMILY('B', '1'):
283 platform_family = FAMILY_8600VZB;
284 break;
285 case BOOTLDRFAMILY('E', '1'):
286 platform_family = FAMILY_1500VZE;
287 break;
288 case BOOTLDRFAMILY('F', '1'):
289 platform_family = FAMILY_1500VZF;
290 break;
291 default:
292 platform_family = -1;
293 }
294}
295
296unsigned int platform_get_family(void)
297{
298 return platform_family;
299}
300EXPORT_SYMBOL(platform_get_family);
301
302/*
303 * \brief usb_eye_configure() for optimizing the USB eye on Calliope.
304 *
305 * \param unsigned int value saved to the register.
306 *
307 * \return none
308 *
309 */
310static void __init usb_eye_configure(unsigned int value)
311{
312 asic_write(asic_read(crt_spare) | value, crt_spare);
313}
314
315/*
316 * platform_get_asic - determine the ASIC type.
317 *
318 * \param none
319 *
320 * \return ASIC type; ASIC_UNKNOWN if none
321 *
322 */
323enum asic_type platform_get_asic(void)
324{
325 return asic;
326}
327EXPORT_SYMBOL(platform_get_asic);
328
329/*
330 * platform_configure_usb - usb configuration based on platform type.
331 * @bcm1_usb2_ctl: value for the BCM1_USB2_CTL register, which is
332 * quirky
333 */
334static void __init platform_configure_usb(void)
335{
336 u32 bcm1_usb2_ctl;
337
338 if (usb_configured)
339 return;
340
341 switch (asic) {
342 case ASIC_ZEUS:
343 fs_update(0x0000, 0x11, 0x02, 0);
344 bcm1_usb2_ctl = 0x803;
345 break;
346
347 case ASIC_CRONUS:
348 case ASIC_CRONUSLITE:
349 fs_update(0x0000, 0x11, 0x02, 0);
350 bcm1_usb2_ctl = 0x803;
351 break;
352
353 case ASIC_CALLIOPE:
354 fs_update(0x0000, 0x11, 0x02, 1);
355
356 switch (platform_family) {
357 case FAMILY_1500VZE:
358 break;
359
360 case FAMILY_1500VZF:
361 usb_eye_configure(0x003c0000);
362 break;
363
364 default:
365 usb_eye_configure(0x00300000);
366 break;
367 }
368
369 bcm1_usb2_ctl = 0x803;
370 break;
371
372 default:
373 pr_err("Unknown ASIC type: %d\n", asic);
374 break;
375 }
376
377 /* turn on USB power */
378 asic_write(0, usb2_strap);
379 /* Enable all OHCI interrupts */
380 asic_write(bcm1_usb2_ctl, usb2_control);
381 /* USB2_STBUS_OBC store32/load32 */
382 asic_write(3, usb2_stbus_obc);
383 /* USB2_STBUS_MESS_SIZE 2 packets */
384 asic_write(1, usb2_stbus_mess_size);
385 /* USB2_STBUS_CHUNK_SIZE 2 packets */
386 asic_write(1, usb2_stbus_chunk_size);
387
388 usb_configured = true;
389}
390
391/*
392 * Set up the USB EHCI interface
393 */
394void platform_configure_usb_ehci()
395{
396 platform_configure_usb();
397}
398
399/*
400 * Set up the USB OHCI interface
401 */
402void platform_configure_usb_ohci()
403{
404 platform_configure_usb();
405}
406
407/*
408 * Shut the USB EHCI interface down--currently a NOP
409 */
410void platform_unconfigure_usb_ehci()
411{
412}
413
414/*
415 * Shut the USB OHCI interface down--currently a NOP
416 */
417void platform_unconfigure_usb_ohci()
418{
419}
420
421/**
422 * configure_platform - configuration based on platform type.
423 */
424void __init configure_platform(void)
425{
426 platform_set_family();
427
428 switch (platform_family) {
429 case FAMILY_1500:
430 case FAMILY_1500VZE:
431 case FAMILY_1500VZF:
432 platform_features = FFS_CAPABLE;
433 asic = ASIC_CALLIOPE;
434 asic_phy_base = CALLIOPE_IO_BASE;
435 register_map = &calliope_register_map;
436 asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
437 ASIC_IO_SIZE);
438
439 if (platform_family == FAMILY_1500VZE) {
440 gp_resources = non_dvr_vze_calliope_resources;
441 pr_info("Platform: 1500/Vz Class E - "
442 "CALLIOPE, NON_DVR_CAPABLE\n");
443 } else if (platform_family == FAMILY_1500VZF) {
444 gp_resources = non_dvr_vzf_calliope_resources;
445 pr_info("Platform: 1500/Vz Class F - "
446 "CALLIOPE, NON_DVR_CAPABLE\n");
447 } else {
448 gp_resources = non_dvr_calliope_resources;
449 pr_info("Platform: 1500/RNG100 - CALLIOPE, "
450 "NON_DVR_CAPABLE\n");
451 }
452 break;
453
454 case FAMILY_4500:
455 platform_features = FFS_CAPABLE | PCIE_CAPABLE |
456 DISPLAY_CAPABLE;
457 asic = ASIC_ZEUS;
458 asic_phy_base = ZEUS_IO_BASE;
459 register_map = &zeus_register_map;
460 asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
461 ASIC_IO_SIZE);
462 gp_resources = non_dvr_zeus_resources;
463
464 pr_info("Platform: 4500 - ZEUS, NON_DVR_CAPABLE\n");
465 break;
466
467 case FAMILY_4600:
468 {
469 unsigned int chipversion = 0;
470
471 /* The settop has PCIE but it isn't used, so don't advertise
472 * it*/
473 platform_features = FFS_CAPABLE | DISPLAY_CAPABLE;
474 asic_phy_base = CRONUS_IO_BASE; /* same as Cronus */
475 register_map = &cronus_register_map; /* same as Cronus */
476 asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
477 ASIC_IO_SIZE);
478 gp_resources = non_dvr_cronuslite_resources;
479
480 /* ASIC version will determine if this is a real CronusLite or
481 * Castrati(Cronus) */
482 chipversion = asic_read(chipver3) << 24;
483 chipversion |= asic_read(chipver2) << 16;
484 chipversion |= asic_read(chipver1) << 8;
485 chipversion |= asic_read(chipver0);
486
487 if ((chipversion == CRONUS_10) || (chipversion == CRONUS_11))
488 asic = ASIC_CRONUS;
489 else
490 asic = ASIC_CRONUSLITE;
491
492 pr_info("Platform: 4600 - %s, NON_DVR_CAPABLE, "
493 "chipversion=0x%08X\n",
494 (asic == ASIC_CRONUS) ? "CRONUS" : "CRONUS LITE",
495 chipversion);
496 break;
497 }
498 case FAMILY_4600VZA:
499 platform_features = FFS_CAPABLE | DISPLAY_CAPABLE;
500 asic = ASIC_CRONUS;
501 asic_phy_base = CRONUS_IO_BASE;
502 register_map = &cronus_register_map;
503 asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
504 ASIC_IO_SIZE);
505 gp_resources = non_dvr_cronus_resources;
506
507 pr_info("Platform: Vz Class A - CRONUS, NON_DVR_CAPABLE\n");
508 break;
509
510 case FAMILY_8500:
511 case FAMILY_8500RNG:
512 platform_features = DVR_CAPABLE | PCIE_CAPABLE |
513 DISPLAY_CAPABLE;
514 asic = ASIC_ZEUS;
515 asic_phy_base = ZEUS_IO_BASE;
516 register_map = &zeus_register_map;
517 asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
518 ASIC_IO_SIZE);
519 gp_resources = dvr_zeus_resources;
520
521 pr_info("Platform: 8500/RNG200 - ZEUS, DVR_CAPABLE\n");
522 break;
523
524 case FAMILY_8600:
525 case FAMILY_8600VZB:
526 platform_features = DVR_CAPABLE | PCIE_CAPABLE |
527 DISPLAY_CAPABLE;
528 asic = ASIC_CRONUS;
529 asic_phy_base = CRONUS_IO_BASE;
530 register_map = &cronus_register_map;
531 asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
532 ASIC_IO_SIZE);
533 gp_resources = dvr_cronus_resources;
534
535 pr_info("Platform: 8600/Vz Class B - CRONUS, "
536 "DVR_CAPABLE\n");
537 break;
538
539 default:
540 pr_crit("Platform: UNKNOWN PLATFORM\n");
541 break;
542 }
543
544 switch (asic) {
545 case ASIC_ZEUS:
546 phys_to_bus_offset = 0x30000000;
547 break;
548 case ASIC_CALLIOPE:
549 phys_to_bus_offset = 0x10000000;
550 break;
551 case ASIC_CRONUSLITE:
552 /* Fall through */
553 case ASIC_CRONUS:
554 /*
555 * TODO: We suppose 0x10000000 aliases into 0x20000000-
556 * 0x2XXXXXXX. If 0x10000000 aliases into 0x60000000-
557 * 0x6XXXXXXX, the offset should be 0x50000000, not 0x10000000.
558 */
559 phys_to_bus_offset = 0x10000000;
560 break;
561 default:
562 phys_to_bus_offset = 0x00000000;
563 break;
564 }
565}
566
567/**
568 * platform_devices_init - sets up USB device resourse.
569 */
570static int __init platform_devices_init(void)
571{
572 pr_notice("%s: ----- Initializing USB resources -----\n", __func__);
573
574 asic_resource.start = asic_phy_base;
575 asic_resource.end += asic_resource.start;
576
577 ehci_resources[0].start = asic_reg_phys_addr(ehci_hcapbase);
578 ehci_resources[0].end += ehci_resources[0].start;
579
580 ohci_resources[0].start = asic_reg_phys_addr(ohci_hc_revision);
581 ohci_resources[0].end += ohci_resources[0].start;
582
583 set_io_port_base(0);
584
585 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
586
587 return 0;
588}
589
590arch_initcall(platform_devices_init);
591
592/*
593 *
594 * BOOTMEM ALLOCATION
595 *
596 */
597/*
598 * Allocates/reserves the Platform memory resources early in the boot process.
599 * This ignores any resources that are designated IORESOURCE_IO
600 */
601void __init platform_alloc_bootmem(void)
602{
603 int i;
604 int total = 0;
605
606 /* Get persistent memory data from command line before allocating
607 * resources. This need to happen before normal command line parsing
608 * has been done */
609 pmem_setup_resource();
610
611 /* Loop through looking for resources that want a particular address */
612 for (i = 0; gp_resources[i].flags != 0; i++) {
613 int size = gp_resources[i].end - gp_resources[i].start + 1;
614 if ((gp_resources[i].start != 0) &&
615 ((gp_resources[i].flags & IORESOURCE_MEM) != 0)) {
616 reserve_bootmem(bus_to_phys(gp_resources[i].start),
617 size, 0);
618 total += gp_resources[i].end -
619 gp_resources[i].start + 1;
620 pr_info("reserve resource %s at %08x (%u bytes)\n",
621 gp_resources[i].name, gp_resources[i].start,
622 gp_resources[i].end -
623 gp_resources[i].start + 1);
624 }
625 }
626
627 /* Loop through assigning addresses for those that are left */
628 for (i = 0; gp_resources[i].flags != 0; i++) {
629 int size = gp_resources[i].end - gp_resources[i].start + 1;
630 if ((gp_resources[i].start == 0) &&
631 ((gp_resources[i].flags & IORESOURCE_MEM) != 0)) {
632 void *mem = alloc_bootmem_pages(size);
633
634 if (mem == NULL)
635 pr_err("Unable to allocate bootmem pages "
636 "for %s\n", gp_resources[i].name);
637
638 else {
639 gp_resources[i].start =
640 phys_to_bus(virt_to_phys(mem));
641 gp_resources[i].end =
642 gp_resources[i].start + size - 1;
643 total += size;
644 pr_info("allocate resource %s at %08x "
645 "(%u bytes)\n",
646 gp_resources[i].name,
647 gp_resources[i].start, size);
648 }
649 }
650 }
651
652 pr_info("Total Platform driver memory allocation: 0x%08x\n", total);
653
654 /* indicate resources that are platform I/O related */
655 for (i = 0; gp_resources[i].flags != 0; i++) {
656 if ((gp_resources[i].start != 0) &&
657 ((gp_resources[i].flags & IORESOURCE_IO) != 0)) {
658 pr_info("reserved platform resource %s at %08x\n",
659 gp_resources[i].name, gp_resources[i].start);
660 }
661 }
662}
663
664/*
665 *
666 * PERSISTENT MEMORY (PMEM) CONFIGURATION
667 *
668 */
669static unsigned long pmemaddr __initdata;
670
671static int __init early_param_pmemaddr(char *p)
672{
673 pmemaddr = (unsigned long)simple_strtoul(p, NULL, 0);
674 return 0;
675}
676early_param("pmemaddr", early_param_pmemaddr);
677
678static long pmemlen __initdata;
679
680static int __init early_param_pmemlen(char *p)
681{
682/* TODO: we can use this code when and if the bootloader ever changes this */
683#if 0
684 pmemlen = (unsigned long)simple_strtoul(p, NULL, 0);
685#else
686 pmemlen = 0x20000;
687#endif
688 return 0;
689}
690early_param("pmemlen", early_param_pmemlen);
691
692/*
693 * Set up persistent memory. If we were given values, we patch the array of
694 * resources. Otherwise, persistent memory may be allocated anywhere at all.
695 */
696static void __init pmem_setup_resource(void)
697{
698 struct resource *resource;
699 resource = asic_resource_get("DiagPersistentMemory");
700
701 if (resource && pmemaddr && pmemlen) {
702 /* The address provided by bootloader is in kseg0. Convert to
703 * a bus address. */
704 resource->start = phys_to_bus(pmemaddr - 0x80000000);
705 resource->end = resource->start + pmemlen - 1;
706
707 pr_info("persistent memory: start=0x%x end=0x%x\n",
708 resource->start, resource->end);
709 }
710}
711
712/*
713 *
714 * RESOURCE ACCESS FUNCTIONS
715 *
716 */
717
718/**
719 * asic_resource_get - retrieves parameters for a platform resource.
720 * @name: string to match resource
721 *
722 * Returns a pointer to a struct resource corresponding to the given name.
723 *
724 * CANNOT BE NAMED platform_resource_get, which would be the obvious choice,
725 * as this function name is already declared
726 */
727struct resource *asic_resource_get(const char *name)
728{
729 int i;
730
731 for (i = 0; gp_resources[i].flags != 0; i++) {
732 if (strcmp(gp_resources[i].name, name) == 0)
733 return &gp_resources[i];
734 }
735
736 return NULL;
737}
738EXPORT_SYMBOL(asic_resource_get);
739
740/**
741 * platform_release_memory - release pre-allocated memory
742 * @ptr: pointer to memory to release
743 * @size: size of resource
744 *
745 * This must only be called for memory allocated or reserved via the boot
746 * memory allocator.
747 */
748void platform_release_memory(void *ptr, int size)
749{
750 unsigned long addr;
751 unsigned long end;
752
753 addr = ((unsigned long)ptr + (PAGE_SIZE - 1)) & PAGE_MASK;
754 end = ((unsigned long)ptr + size) & PAGE_MASK;
755
756 for (; addr < end; addr += PAGE_SIZE) {
757 ClearPageReserved(virt_to_page(__va(addr)));
758 init_page_count(virt_to_page(__va(addr)));
759 free_page((unsigned long)__va(addr));
760 }
761}
762EXPORT_SYMBOL(platform_release_memory);
763
764/*
765 *
766 * FEATURE AVAILABILITY FUNCTIONS
767 *
768 */
769int platform_supports_dvr(void)
770{
771 return (platform_features & DVR_CAPABLE) != 0;
772}
773
774int platform_supports_ffs(void)
775{
776 return (platform_features & FFS_CAPABLE) != 0;
777}
778
779int platform_supports_pcie(void)
780{
781 return (platform_features & PCIE_CAPABLE) != 0;
782}
783
784int platform_supports_display(void)
785{
786 return (platform_features & DISPLAY_CAPABLE) != 0;
787}
diff --git a/arch/mips/powertv/asic/asic_int.c b/arch/mips/powertv/asic/asic_int.c
new file mode 100644
index 000000000000..80b2eed21ac3
--- /dev/null
+++ b/arch/mips/powertv/asic/asic_int.c
@@ -0,0 +1,125 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
4 * Copyright (C) 2001 Ralf Baechle
5 * Portions copyright (C) 2009 Cisco Systems, Inc.
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * Routines for generic manipulation of the interrupts found on the PowerTV
21 * platform.
22 *
23 * The interrupt controller is located in the South Bridge a PIIX4 device
24 * with two internal 82C95 interrupt controllers.
25 */
26#include <linux/init.h>
27#include <linux/irq.h>
28#include <linux/sched.h>
29#include <linux/slab.h>
30#include <linux/interrupt.h>
31#include <linux/kernel_stat.h>
32#include <linux/kernel.h>
33#include <linux/random.h>
34
35#include <asm/irq_cpu.h>
36#include <linux/io.h>
37#include <asm/irq_regs.h>
38#include <asm/mips-boards/generic.h>
39
40#include <asm/mach-powertv/asic_regs.h>
41
42static DEFINE_SPINLOCK(asic_irq_lock);
43
44static inline int get_int(void)
45{
46 unsigned long flags;
47 int irq;
48
49 spin_lock_irqsave(&asic_irq_lock, flags);
50
51 irq = (asic_read(int_int_scan) >> 4) - 1;
52
53 if (irq == 0 || irq >= NR_IRQS)
54 irq = -1;
55
56 spin_unlock_irqrestore(&asic_irq_lock, flags);
57
58 return irq;
59}
60
61static void asic_irqdispatch(void)
62{
63 int irq;
64
65 irq = get_int();
66 if (irq < 0)
67 return; /* interrupt has already been cleared */
68
69 do_IRQ(irq);
70}
71
72static inline int clz(unsigned long x)
73{
74 __asm__(
75 " .set push \n"
76 " .set mips32 \n"
77 " clz %0, %1 \n"
78 " .set pop \n"
79 : "=r" (x)
80 : "r" (x));
81
82 return x;
83}
84
85/*
86 * Version of ffs that only looks at bits 12..15.
87 */
88static inline unsigned int irq_ffs(unsigned int pending)
89{
90 return fls(pending) - 1 + CAUSEB_IP;
91}
92
93/*
94 * TODO: check how it works under EIC mode.
95 */
96asmlinkage void plat_irq_dispatch(void)
97{
98 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
99 int irq;
100
101 irq = irq_ffs(pending);
102
103 if (irq == CAUSEF_IP3)
104 asic_irqdispatch();
105 else if (irq >= 0)
106 do_IRQ(irq);
107 else
108 spurious_interrupt();
109}
110
111void __init arch_init_irq(void)
112{
113 int i;
114
115 asic_irq_init();
116
117 /*
118 * Initialize interrupt exception vectors.
119 */
120 if (cpu_has_veic || cpu_has_vint) {
121 int nvec = cpu_has_veic ? 64 : 8;
122 for (i = 0; i < nvec; i++)
123 set_vi_handler(i, asic_irqdispatch);
124 }
125}
diff --git a/arch/mips/powertv/asic/irq_asic.c b/arch/mips/powertv/asic/irq_asic.c
new file mode 100644
index 000000000000..b54d24499b06
--- /dev/null
+++ b/arch/mips/powertv/asic/irq_asic.c
@@ -0,0 +1,116 @@
1/*
2 * Portions copyright (C) 2005-2009 Scientific Atlanta
3 * Portions copyright (C) 2009 Cisco Systems, Inc.
4 *
5 * Modified from arch/mips/kernel/irq-rm7000.c:
6 * Copyright (C) 2003 Ralf Baechle
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16
17#include <asm/irq_cpu.h>
18#include <asm/mipsregs.h>
19#include <asm/system.h>
20
21#include <asm/mach-powertv/asic_regs.h>
22
23static inline void unmask_asic_irq(unsigned int irq)
24{
25 unsigned long enable_bit;
26
27 enable_bit = (1 << (irq & 0x1f));
28
29 switch (irq >> 5) {
30 case 0:
31 asic_write(asic_read(ien_int_0) | enable_bit, ien_int_0);
32 break;
33 case 1:
34 asic_write(asic_read(ien_int_1) | enable_bit, ien_int_1);
35 break;
36 case 2:
37 asic_write(asic_read(ien_int_2) | enable_bit, ien_int_2);
38 break;
39 case 3:
40 asic_write(asic_read(ien_int_3) | enable_bit, ien_int_3);
41 break;
42 default:
43 BUG();
44 }
45}
46
47static inline void mask_asic_irq(unsigned int irq)
48{
49 unsigned long disable_mask;
50
51 disable_mask = ~(1 << (irq & 0x1f));
52
53 switch (irq >> 5) {
54 case 0:
55 asic_write(asic_read(ien_int_0) & disable_mask, ien_int_0);
56 break;
57 case 1:
58 asic_write(asic_read(ien_int_1) & disable_mask, ien_int_1);
59 break;
60 case 2:
61 asic_write(asic_read(ien_int_2) & disable_mask, ien_int_2);
62 break;
63 case 3:
64 asic_write(asic_read(ien_int_3) & disable_mask, ien_int_3);
65 break;
66 default:
67 BUG();
68 }
69}
70
71static struct irq_chip asic_irq_chip = {
72 .name = "ASIC Level",
73 .ack = mask_asic_irq,
74 .mask = mask_asic_irq,
75 .mask_ack = mask_asic_irq,
76 .unmask = unmask_asic_irq,
77 .eoi = unmask_asic_irq,
78};
79
80void __init asic_irq_init(void)
81{
82 int i;
83
84 /* set priority to 0 */
85 write_c0_status(read_c0_status() & ~(0x0000fc00));
86
87 asic_write(0, ien_int_0);
88 asic_write(0, ien_int_1);
89 asic_write(0, ien_int_2);
90 asic_write(0, ien_int_3);
91
92 asic_write(0x0fffffff, int_level_3_3);
93 asic_write(0xffffffff, int_level_3_2);
94 asic_write(0xffffffff, int_level_3_1);
95 asic_write(0xffffffff, int_level_3_0);
96 asic_write(0xffffffff, int_level_2_3);
97 asic_write(0xffffffff, int_level_2_2);
98 asic_write(0xffffffff, int_level_2_1);
99 asic_write(0xffffffff, int_level_2_0);
100 asic_write(0xffffffff, int_level_1_3);
101 asic_write(0xffffffff, int_level_1_2);
102 asic_write(0xffffffff, int_level_1_1);
103 asic_write(0xffffffff, int_level_1_0);
104 asic_write(0xffffffff, int_level_0_3);
105 asic_write(0xffffffff, int_level_0_2);
106 asic_write(0xffffffff, int_level_0_1);
107 asic_write(0xffffffff, int_level_0_0);
108
109 asic_write(0xf, int_int_scan);
110
111 /*
112 * Initialize interrupt handlers.
113 */
114 for (i = 0; i < NR_IRQS; i++)
115 set_irq_chip_and_handler(i, &asic_irq_chip, handle_level_irq);
116}
diff --git a/arch/mips/powertv/asic/prealloc-calliope.c b/arch/mips/powertv/asic/prealloc-calliope.c
new file mode 100644
index 000000000000..cd5b76a1c951
--- /dev/null
+++ b/arch/mips/powertv/asic/prealloc-calliope.c
@@ -0,0 +1,620 @@
1/*
2 * Memory pre-allocations for Calliope boxes.
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: Ken Eppinett
21 * David Schleef <ds@schleef.org>
22 */
23
24#include <linux/init.h>
25#include <asm/mach-powertv/asic.h>
26
27/*
28 * NON_DVR_CAPABLE CALLIOPE RESOURCES
29 */
30struct resource non_dvr_calliope_resources[] __initdata =
31{
32 /*
33 * VIDEO / LX1
34 */
35 {
36 .name = "ST231aImage", /* Delta-Mu 1 image and ram */
37 .start = 0x24000000,
38 .end = 0x24200000 - 1, /*2MiB */
39 .flags = IORESOURCE_MEM,
40 },
41 {
42 .name = "ST231aMonitor", /*8KiB block ST231a monitor */
43 .start = 0x24200000,
44 .end = 0x24202000 - 1,
45 .flags = IORESOURCE_MEM,
46 },
47 {
48 .name = "MediaMemory1",
49 .start = 0x24202000,
50 .end = 0x26700000 - 1, /*~36.9MiB (32MiB - (2MiB + 8KiB)) */
51 .flags = IORESOURCE_MEM,
52 },
53 /*
54 * Sysaudio Driver
55 */
56 {
57 .name = "DSP_Image_Buff",
58 .start = 0x00000000,
59 .end = 0x000FFFFF,
60 .flags = IORESOURCE_MEM,
61 },
62 {
63 .name = "ADSC_CPU_PCM_Buff",
64 .start = 0x00000000,
65 .end = 0x00009FFF,
66 .flags = IORESOURCE_MEM,
67 },
68 {
69 .name = "ADSC_AUX_Buff",
70 .start = 0x00000000,
71 .end = 0x00003FFF,
72 .flags = IORESOURCE_MEM,
73 },
74 {
75 .name = "ADSC_Main_Buff",
76 .start = 0x00000000,
77 .end = 0x00003FFF,
78 .flags = IORESOURCE_MEM,
79 },
80 /*
81 * STAVEM driver/STAPI
82 */
83 {
84 .name = "AVMEMPartition0",
85 .start = 0x00000000,
86 .end = 0x00600000 - 1, /* 6 MB total */
87 .flags = IORESOURCE_MEM,
88 },
89 /*
90 * DOCSIS Subsystem
91 */
92 {
93 .name = "Docsis",
94 .start = 0x22000000,
95 .end = 0x22700000 - 1,
96 .flags = IORESOURCE_MEM,
97 },
98 /*
99 * GHW HAL Driver
100 */
101 {
102 .name = "GraphicsHeap",
103 .start = 0x22700000,
104 .end = 0x23500000 - 1, /* 14 MB total */
105 .flags = IORESOURCE_MEM,
106 },
107 /*
108 * multi com buffer area
109 */
110 {
111 .name = "MulticomSHM",
112 .start = 0x23700000,
113 .end = 0x23720000 - 1,
114 .flags = IORESOURCE_MEM,
115 },
116 /*
117 * DMA Ring buffer (don't need recording buffers)
118 */
119 {
120 .name = "BMM_Buffer",
121 .start = 0x00000000,
122 .end = 0x000AA000 - 1,
123 .flags = IORESOURCE_MEM,
124 },
125 /*
126 * Display bins buffer for unit0
127 */
128 {
129 .name = "DisplayBins0",
130 .start = 0x00000000,
131 .end = 0x00000FFF, /* 4 KB total */
132 .flags = IORESOURCE_MEM,
133 },
134 /*
135 *
136 * AVFS: player HAL memory
137 *
138 *
139 */
140 {
141 .name = "AvfsDmaMem",
142 .start = 0x00000000,
143 .end = 0x002c4c00 - 1, /* 945K * 3 for playback */
144 .flags = IORESOURCE_MEM,
145 },
146 /*
147 * PMEM
148 */
149 {
150 .name = "DiagPersistentMemory",
151 .start = 0x00000000,
152 .end = 0x10000 - 1,
153 .flags = IORESOURCE_MEM,
154 },
155 /*
156 * Smartcard
157 */
158 {
159 .name = "SmartCardInfo",
160 .start = 0x00000000,
161 .end = 0x2800 - 1,
162 .flags = IORESOURCE_MEM,
163 },
164 /*
165 * NAND Flash
166 */
167 {
168 .name = "NandFlash",
169 .start = NAND_FLASH_BASE,
170 .end = NAND_FLASH_BASE + 0x400 - 1,
171 .flags = IORESOURCE_IO,
172 },
173 /*
174 * Synopsys GMAC Memory Region
175 */
176 {
177 .name = "GMAC",
178 .start = 0x00000000,
179 .end = 0x00010000 - 1,
180 .flags = IORESOURCE_MEM,
181 },
182 /*
183 * Add other resources here
184 *
185 */
186 { },
187};
188
189struct resource non_dvr_vz_calliope_resources[] __initdata =
190{
191 /*
192 * VIDEO / LX1
193 */
194 {
195 .name = "ST231aImage", /* Delta-Mu 1 image and ram */
196 .start = 0x24000000,
197 .end = 0x24200000 - 1, /*2 Meg */
198 .flags = IORESOURCE_MEM,
199 },
200 {
201 .name = "ST231aMonitor", /* 8k block ST231a monitor */
202 .start = 0x24200000,
203 .end = 0x24202000 - 1,
204 .flags = IORESOURCE_MEM,
205 },
206 {
207 .name = "MediaMemory1",
208 .start = 0x22202000,
209 .end = 0x22C20B85 - 1, /* 10.12 Meg */
210 .flags = IORESOURCE_MEM,
211 },
212 /*
213 * Sysaudio Driver
214 */
215 {
216 .name = "DSP_Image_Buff",
217 .start = 0x00000000,
218 .end = 0x000FFFFF,
219 .flags = IORESOURCE_MEM,
220 },
221 {
222 .name = "ADSC_CPU_PCM_Buff",
223 .start = 0x00000000,
224 .end = 0x00009FFF,
225 .flags = IORESOURCE_MEM,
226 },
227 {
228 .name = "ADSC_AUX_Buff",
229 .start = 0x00000000,
230 .end = 0x00003FFF,
231 .flags = IORESOURCE_MEM,
232 },
233 {
234 .name = "ADSC_Main_Buff",
235 .start = 0x00000000,
236 .end = 0x00003FFF,
237 .flags = IORESOURCE_MEM,
238 },
239 /*
240 * STAVEM driver/STAPI
241 */
242 {
243 .name = "AVMEMPartition0",
244 .start = 0x20300000,
245 .end = 0x20620000-1, /*3.125 MB total */
246 .flags = IORESOURCE_MEM,
247 },
248 /*
249 * GHW HAL Driver
250 */
251 {
252 .name = "GraphicsHeap",
253 .start = 0x20100000,
254 .end = 0x20300000 - 1,
255 .flags = IORESOURCE_MEM,
256 },
257 /*
258 * multi com buffer area
259 */
260 {
261 .name = "MulticomSHM",
262 .start = 0x23900000,
263 .end = 0x23920000 - 1,
264 .flags = IORESOURCE_MEM,
265 },
266 /*
267 * DMA Ring buffer
268 */
269 {
270 .name = "BMM_Buffer",
271 .start = 0x00000000,
272 .end = 0x000AA000 - 1,
273 .flags = IORESOURCE_MEM,
274 },
275 /*
276 * Display bins buffer for unit0
277 */
278 {
279 .name = "DisplayBins0",
280 .start = 0x00000000,
281 .end = 0x00000FFF,
282 .flags = IORESOURCE_MEM,
283 },
284 /*
285 * PMEM
286 */
287 {
288 .name = "DiagPersistentMemory",
289 .start = 0x00000000,
290 .end = 0x10000 - 1,
291 .flags = IORESOURCE_MEM,
292 },
293 /*
294 * Smartcard
295 */
296 {
297 .name = "SmartCardInfo",
298 .start = 0x00000000,
299 .end = 0x2800 - 1,
300 .flags = IORESOURCE_MEM,
301 },
302 /*
303 * NAND Flash
304 */
305 {
306 .name = "NandFlash",
307 .start = NAND_FLASH_BASE,
308 .end = NAND_FLASH_BASE+0x400 - 1,
309 .flags = IORESOURCE_IO,
310 },
311 /*
312 * Synopsys GMAC Memory Region
313 */
314 {
315 .name = "GMAC",
316 .start = 0x00000000,
317 .end = 0x00010000 - 1,
318 .flags = IORESOURCE_MEM,
319 },
320 /*
321 * Add other resources here
322 */
323 { },
324};
325
326struct resource non_dvr_vze_calliope_resources[] __initdata =
327{
328 /*
329 * VIDEO / LX1
330 */
331 {
332 .name = "ST231aImage", /* Delta-Mu 1 image and ram */
333 .start = 0x22000000,
334 .end = 0x22200000 - 1, /*2 Meg */
335 .flags = IORESOURCE_MEM,
336 },
337 {
338 .name = "ST231aMonitor", /* 8k block ST231a monitor */
339 .start = 0x22200000,
340 .end = 0x22202000 - 1,
341 .flags = IORESOURCE_MEM,
342 },
343 {
344 .name = "MediaMemory1",
345 .start = 0x22202000,
346 .end = 0x22C20B85 - 1, /* 10.12 Meg */
347 .flags = IORESOURCE_MEM,
348 },
349 /*
350 * Sysaudio Driver
351 */
352 {
353 .name = "DSP_Image_Buff",
354 .start = 0x00000000,
355 .end = 0x000FFFFF,
356 .flags = IORESOURCE_MEM,
357 },
358 {
359 .name = "ADSC_CPU_PCM_Buff",
360 .start = 0x00000000,
361 .end = 0x00009FFF,
362 .flags = IORESOURCE_MEM,
363 },
364 {
365 .name = "ADSC_AUX_Buff",
366 .start = 0x00000000,
367 .end = 0x00003FFF,
368 .flags = IORESOURCE_MEM,
369 },
370 {
371 .name = "ADSC_Main_Buff",
372 .start = 0x00000000,
373 .end = 0x00003FFF,
374 .flags = IORESOURCE_MEM,
375 },
376 /*
377 * STAVEM driver/STAPI
378 */
379 {
380 .name = "AVMEMPartition0",
381 .start = 0x20396000,
382 .end = 0x206B6000 - 1, /* 3.125 MB total */
383 .flags = IORESOURCE_MEM,
384 },
385 /*
386 * GHW HAL Driver
387 */
388 {
389 .name = "GraphicsHeap",
390 .start = 0x20100000,
391 .end = 0x20396000 - 1,
392 .flags = IORESOURCE_MEM,
393 },
394 /*
395 * multi com buffer area
396 */
397 {
398 .name = "MulticomSHM",
399 .start = 0x206B6000,
400 .end = 0x206D6000 - 1,
401 .flags = IORESOURCE_MEM,
402 },
403 /*
404 * DMA Ring buffer
405 */
406 {
407 .name = "BMM_Buffer",
408 .start = 0x00000000,
409 .end = 0x000AA000 - 1,
410 .flags = IORESOURCE_MEM,
411 },
412 /*
413 * Display bins buffer for unit0
414 */
415 {
416 .name = "DisplayBins0",
417 .start = 0x00000000,
418 .end = 0x00000FFF,
419 .flags = IORESOURCE_MEM,
420 },
421 /*
422 * PMEM
423 */
424 {
425 .name = "DiagPersistentMemory",
426 .start = 0x00000000,
427 .end = 0x10000 - 1,
428 .flags = IORESOURCE_MEM,
429 },
430 /*
431 * Smartcard
432 */
433 {
434 .name = "SmartCardInfo",
435 .start = 0x00000000,
436 .end = 0x2800 - 1,
437 .flags = IORESOURCE_MEM,
438 },
439 /*
440 * NAND Flash
441 */
442 {
443 .name = "NandFlash",
444 .start = NAND_FLASH_BASE,
445 .end = NAND_FLASH_BASE+0x400 - 1,
446 .flags = IORESOURCE_MEM,
447 },
448 /*
449 * Synopsys GMAC Memory Region
450 */
451 {
452 .name = "GMAC",
453 .start = 0x00000000,
454 .end = 0x00010000 - 1,
455 .flags = IORESOURCE_MEM,
456 },
457 /*
458 * Add other resources here
459 */
460 { },
461};
462
463struct resource non_dvr_vzf_calliope_resources[] __initdata =
464{
465 /*
466 * VIDEO / LX1
467 */
468 {
469 .name = "ST231aImage", /*Delta-Mu 1 image and ram */
470 .start = 0x24000000,
471 .end = 0x24200000 - 1, /*2MiB */
472 .flags = IORESOURCE_MEM,
473 },
474 {
475 .name = "ST231aMonitor", /*8KiB block ST231a monitor */
476 .start = 0x24200000,
477 .end = 0x24202000 - 1,
478 .flags = IORESOURCE_MEM,
479 },
480 {
481 .name = "MediaMemory1",
482 .start = 0x24202000,
483 /* ~19.4 (21.5MiB - (2MiB + 8KiB)) */
484 .end = 0x25580000 - 1,
485 .flags = IORESOURCE_MEM,
486 },
487 /*
488 * Sysaudio Driver
489 */
490 {
491 .name = "DSP_Image_Buff",
492 .start = 0x00000000,
493 .end = 0x000FFFFF,
494 .flags = IORESOURCE_MEM,
495 },
496 {
497 .name = "ADSC_CPU_PCM_Buff",
498 .start = 0x00000000,
499 .end = 0x00009FFF,
500 .flags = IORESOURCE_MEM,
501 },
502 {
503 .name = "ADSC_AUX_Buff",
504 .start = 0x00000000,
505 .end = 0x00003FFF,
506 .flags = IORESOURCE_MEM,
507 },
508 {
509 .name = "ADSC_Main_Buff",
510 .start = 0x00000000,
511 .end = 0x00003FFF,
512 .flags = IORESOURCE_MEM,
513 },
514 /*
515 * STAVEM driver/STAPI
516 */
517 {
518 .name = "AVMEMPartition0",
519 .start = 0x00000000,
520 .end = 0x00480000 - 1, /* 4.5 MB total */
521 .flags = IORESOURCE_MEM,
522 },
523 /*
524 * GHW HAL Driver
525 */
526 {
527 .name = "GraphicsHeap",
528 .start = 0x22700000,
529 .end = 0x23500000 - 1, /* 14 MB total */
530 .flags = IORESOURCE_MEM,
531 },
532 /*
533 * multi com buffer area
534 */
535 {
536 .name = "MulticomSHM",
537 .start = 0x23700000,
538 .end = 0x23720000 - 1,
539 .flags = IORESOURCE_MEM,
540 },
541 /*
542 * DMA Ring buffer (don't need recording buffers)
543 */
544 {
545 .name = "BMM_Buffer",
546 .start = 0x00000000,
547 .end = 0x000AA000 - 1,
548 .flags = IORESOURCE_MEM,
549 },
550 /*
551 * Display bins buffer for unit0
552 */
553 {
554 .name = "DisplayBins0",
555 .start = 0x00000000,
556 .end = 0x00000FFF, /* 4 KB total */
557 .flags = IORESOURCE_MEM,
558 },
559 /*
560 * Display bins buffer for unit1
561 */
562 {
563 .name = "DisplayBins1",
564 .start = 0x00000000,
565 .end = 0x00000FFF, /* 4 KB total */
566 .flags = IORESOURCE_MEM,
567 },
568 /*
569 *
570 * AVFS: player HAL memory
571 *
572 *
573 */
574 {
575 .name = "AvfsDmaMem",
576 .start = 0x00000000,
577 .end = 0x002c4c00 - 1, /* 945K * 3 for playback */
578 .flags = IORESOURCE_MEM,
579 },
580 /*
581 * PMEM
582 */
583 {
584 .name = "DiagPersistentMemory",
585 .start = 0x00000000,
586 .end = 0x10000 - 1,
587 .flags = IORESOURCE_MEM,
588 },
589 /*
590 * Smartcard
591 */
592 {
593 .name = "SmartCardInfo",
594 .start = 0x00000000,
595 .end = 0x2800 - 1,
596 .flags = IORESOURCE_MEM,
597 },
598 /*
599 * NAND Flash
600 */
601 {
602 .name = "NandFlash",
603 .start = NAND_FLASH_BASE,
604 .end = NAND_FLASH_BASE + 0x400 - 1,
605 .flags = IORESOURCE_MEM,
606 },
607 /*
608 * Synopsys GMAC Memory Region
609 */
610 {
611 .name = "GMAC",
612 .start = 0x00000000,
613 .end = 0x00010000 - 1,
614 .flags = IORESOURCE_MEM,
615 },
616 /*
617 * Add other resources here
618 */
619 { },
620};
diff --git a/arch/mips/powertv/asic/prealloc-cronus.c b/arch/mips/powertv/asic/prealloc-cronus.c
new file mode 100644
index 000000000000..45a5c3ea718c
--- /dev/null
+++ b/arch/mips/powertv/asic/prealloc-cronus.c
@@ -0,0 +1,608 @@
1/*
2 * Memory pre-allocations for Cronus boxes.
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: Ken Eppinett
21 * David Schleef <ds@schleef.org>
22 */
23
24#include <linux/init.h>
25#include <asm/mach-powertv/asic.h>
26
27/*
28 * DVR_CAPABLE CRONUS RESOURCES
29 */
30struct resource dvr_cronus_resources[] __initdata =
31{
32 /*
33 *
34 * VIDEO1 / LX1
35 *
36 */
37 {
38 .name = "ST231aImage", /* Delta-Mu 1 image and ram */
39 .start = 0x24000000,
40 .end = 0x241FFFFF, /* 2MiB */
41 .flags = IORESOURCE_MEM,
42 },
43 {
44 .name = "ST231aMonitor", /* 8KiB block ST231a monitor */
45 .start = 0x24200000,
46 .end = 0x24201FFF,
47 .flags = IORESOURCE_MEM,
48 },
49 {
50 .name = "MediaMemory1",
51 .start = 0x24202000,
52 .end = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
53 .flags = IORESOURCE_MEM,
54 },
55 /*
56 *
57 * VIDEO2 / LX2
58 *
59 */
60 {
61 .name = "ST231bImage", /* Delta-Mu 2 image and ram */
62 .start = 0x60000000,
63 .end = 0x601FFFFF, /* 2MiB */
64 .flags = IORESOURCE_IO,
65 },
66 {
67 .name = "ST231bMonitor", /* 8KiB block ST231b monitor */
68 .start = 0x60200000,
69 .end = 0x60201FFF,
70 .flags = IORESOURCE_IO,
71 },
72 {
73 .name = "MediaMemory2",
74 .start = 0x60202000,
75 .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
76 .flags = IORESOURCE_IO,
77 },
78 /*
79 *
80 * Sysaudio Driver
81 *
82 * This driver requires:
83 *
84 * Arbitrary Based Buffers:
85 * DSP_Image_Buff - DSP code and data images (1MB)
86 * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB)
87 * ADSC_AUX_Buff - ADSC AUX buffer (16KB)
88 * ADSC_Main_Buff - ADSC Main buffer (16KB)
89 *
90 */
91 {
92 .name = "DSP_Image_Buff",
93 .start = 0x00000000,
94 .end = 0x000FFFFF,
95 .flags = IORESOURCE_MEM,
96 },
97 {
98 .name = "ADSC_CPU_PCM_Buff",
99 .start = 0x00000000,
100 .end = 0x00009FFF,
101 .flags = IORESOURCE_MEM,
102 },
103 {
104 .name = "ADSC_AUX_Buff",
105 .start = 0x00000000,
106 .end = 0x00003FFF,
107 .flags = IORESOURCE_MEM,
108 },
109 {
110 .name = "ADSC_Main_Buff",
111 .start = 0x00000000,
112 .end = 0x00003FFF,
113 .flags = IORESOURCE_MEM,
114 },
115 /*
116 *
117 * STAVEM driver/STAPI
118 *
119 * This driver requires:
120 *
121 * Arbitrary Based Buffers:
122 * This memory area is used for allocating buffers for Video decoding
123 * purposes. Allocation/De-allocation within this buffer is managed
124 * by the STAVMEM driver of the STAPI. They could be Decimated
125 * Picture Buffers, Intermediate Buffers, as deemed necessary for
126 * video decoding purposes, for any video decoders on Zeus.
127 *
128 */
129 {
130 .name = "AVMEMPartition0",
131 .start = 0x63580000,
132 .end = 0x64180000 - 1, /* 12 MB total */
133 .flags = IORESOURCE_IO,
134 },
135 /*
136 *
137 * DOCSIS Subsystem
138 *
139 * This driver requires:
140 *
141 * Arbitrary Based Buffers:
142 * Docsis -
143 *
144 */
145 {
146 .name = "Docsis",
147 .start = 0x62000000,
148 .end = 0x62700000 - 1, /* 7 MB total */
149 .flags = IORESOURCE_IO,
150 },
151 /*
152 *
153 * GHW HAL Driver
154 *
155 * This driver requires:
156 *
157 * Arbitrary Based Buffers:
158 * GraphicsHeap - PowerTV Graphics Heap
159 *
160 */
161 {
162 .name = "GraphicsHeap",
163 .start = 0x62700000,
164 .end = 0x63500000 - 1, /* 14 MB total */
165 .flags = IORESOURCE_IO,
166 },
167 /*
168 *
169 * multi com buffer area
170 *
171 * This driver requires:
172 *
173 * Arbitrary Based Buffers:
174 * Docsis -
175 *
176 */
177 {
178 .name = "MulticomSHM",
179 .start = 0x26000000,
180 .end = 0x26020000 - 1,
181 .flags = IORESOURCE_MEM,
182 },
183 /*
184 *
185 * DMA Ring buffer
186 *
187 * This driver requires:
188 *
189 * Arbitrary Based Buffers:
190 * Docsis -
191 *
192 */
193 {
194 .name = "BMM_Buffer",
195 .start = 0x00000000,
196 .end = 0x00280000 - 1,
197 .flags = IORESOURCE_MEM,
198 },
199 /*
200 *
201 * Display bins buffer for unit0
202 *
203 * This driver requires:
204 *
205 * Arbitrary Based Buffers:
206 * Display Bins for unit0
207 *
208 */
209 {
210 .name = "DisplayBins0",
211 .start = 0x00000000,
212 .end = 0x00000FFF, /* 4 KB total */
213 .flags = IORESOURCE_MEM,
214 },
215 /*
216 *
217 * Display bins buffer
218 *
219 * This driver requires:
220 *
221 * Arbitrary Based Buffers:
222 * Display Bins for unit1
223 *
224 */
225 {
226 .name = "DisplayBins1",
227 .start = 0x64AD4000,
228 .end = 0x64AD5000 - 1, /* 4 KB total */
229 .flags = IORESOURCE_IO,
230 },
231 /*
232 *
233 * ITFS
234 *
235 * This driver requires:
236 *
237 * Arbitrary Based Buffers:
238 * Docsis -
239 *
240 */
241 {
242 .name = "ITFS",
243 .start = 0x64180000,
244 /* 815,104 bytes each for 2 ITFS partitions. */
245 .end = 0x6430DFFF,
246 .flags = IORESOURCE_IO,
247 },
248 /*
249 *
250 * AVFS
251 *
252 * This driver requires:
253 *
254 * Arbitrary Based Buffers:
255 * Docsis -
256 *
257 */
258 {
259 .name = "AvfsDmaMem",
260 .start = 0x6430E000,
261 /* (945K * 8) = (128K *3) 5 playbacks / 3 server */
262 .end = 0x64AD0000 - 1,
263 .flags = IORESOURCE_IO,
264 },
265 {
266 .name = "AvfsFileSys",
267 .start = 0x64AD0000,
268 .end = 0x64AD1000 - 1, /* 4K */
269 .flags = IORESOURCE_IO,
270 },
271 /*
272 *
273 * PMEM
274 *
275 * This driver requires:
276 *
277 * Arbitrary Based Buffers:
278 * Persistent memory for diagnostics.
279 *
280 */
281 {
282 .name = "DiagPersistentMemory",
283 .start = 0x00000000,
284 .end = 0x10000 - 1,
285 .flags = IORESOURCE_MEM,
286 },
287 /*
288 *
289 * Smartcard
290 *
291 * This driver requires:
292 *
293 * Arbitrary Based Buffers:
294 * Read and write buffers for Internal/External cards
295 *
296 */
297 {
298 .name = "SmartCardInfo",
299 .start = 0x64AD1000,
300 .end = 0x64AD3800 - 1,
301 .flags = IORESOURCE_IO,
302 },
303 /*
304 *
305 * KAVNET
306 * NP Reset Vector - must be of the form xxCxxxxx
307 * NP Image - must be video bank 1
308 * NP IPC - must be video bank 2
309 */
310 {
311 .name = "NP_Reset_Vector",
312 .start = 0x27c00000,
313 .end = 0x27c01000 - 1,
314 .flags = IORESOURCE_MEM,
315 },
316 {
317 .name = "NP_Image",
318 .start = 0x27020000,
319 .end = 0x27060000 - 1,
320 .flags = IORESOURCE_MEM,
321 },
322 {
323 .name = "NP_IPC",
324 .start = 0x63500000,
325 .end = 0x63580000 - 1,
326 .flags = IORESOURCE_IO,
327 },
328 /*
329 * Add other resources here
330 */
331 { },
332};
333
334/*
335 * NON_DVR_CAPABLE CRONUS RESOURCES
336 */
337struct resource non_dvr_cronus_resources[] __initdata =
338{
339 /*
340 *
341 * VIDEO1 / LX1
342 *
343 */
344 {
345 .name = "ST231aImage", /* Delta-Mu 1 image and ram */
346 .start = 0x24000000,
347 .end = 0x241FFFFF, /* 2MiB */
348 .flags = IORESOURCE_MEM,
349 },
350 {
351 .name = "ST231aMonitor", /* 8KiB block ST231a monitor */
352 .start = 0x24200000,
353 .end = 0x24201FFF,
354 .flags = IORESOURCE_MEM,
355 },
356 {
357 .name = "MediaMemory1",
358 .start = 0x24202000,
359 .end = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
360 .flags = IORESOURCE_MEM,
361 },
362 /*
363 *
364 * VIDEO2 / LX2
365 *
366 */
367 {
368 .name = "ST231bImage", /* Delta-Mu 2 image and ram */
369 .start = 0x60000000,
370 .end = 0x601FFFFF, /* 2MiB */
371 .flags = IORESOURCE_IO,
372 },
373 {
374 .name = "ST231bMonitor", /* 8KiB block ST231b monitor */
375 .start = 0x60200000,
376 .end = 0x60201FFF,
377 .flags = IORESOURCE_IO,
378 },
379 {
380 .name = "MediaMemory2",
381 .start = 0x60202000,
382 .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
383 .flags = IORESOURCE_IO,
384 },
385 /*
386 *
387 * Sysaudio Driver
388 *
389 * This driver requires:
390 *
391 * Arbitrary Based Buffers:
392 * DSP_Image_Buff - DSP code and data images (1MB)
393 * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB)
394 * ADSC_AUX_Buff - ADSC AUX buffer (16KB)
395 * ADSC_Main_Buff - ADSC Main buffer (16KB)
396 *
397 */
398 {
399 .name = "DSP_Image_Buff",
400 .start = 0x00000000,
401 .end = 0x000FFFFF,
402 .flags = IORESOURCE_MEM,
403 },
404 {
405 .name = "ADSC_CPU_PCM_Buff",
406 .start = 0x00000000,
407 .end = 0x00009FFF,
408 .flags = IORESOURCE_MEM,
409 },
410 {
411 .name = "ADSC_AUX_Buff",
412 .start = 0x00000000,
413 .end = 0x00003FFF,
414 .flags = IORESOURCE_MEM,
415 },
416 {
417 .name = "ADSC_Main_Buff",
418 .start = 0x00000000,
419 .end = 0x00003FFF,
420 .flags = IORESOURCE_MEM,
421 },
422 /*
423 *
424 * STAVEM driver/STAPI
425 *
426 * This driver requires:
427 *
428 * Arbitrary Based Buffers:
429 * This memory area is used for allocating buffers for Video decoding
430 * purposes. Allocation/De-allocation within this buffer is managed
431 * by the STAVMEM driver of the STAPI. They could be Decimated
432 * Picture Buffers, Intermediate Buffers, as deemed necessary for
433 * video decoding purposes, for any video decoders on Zeus.
434 *
435 */
436 {
437 .name = "AVMEMPartition0",
438 .start = 0x63580000,
439 .end = 0x64180000 - 1, /* 12 MB total */
440 .flags = IORESOURCE_IO,
441 },
442 /*
443 *
444 * DOCSIS Subsystem
445 *
446 * This driver requires:
447 *
448 * Arbitrary Based Buffers:
449 * Docsis -
450 *
451 */
452 {
453 .name = "Docsis",
454 .start = 0x62000000,
455 .end = 0x62700000 - 1, /* 7 MB total */
456 .flags = IORESOURCE_IO,
457 },
458 /*
459 *
460 * GHW HAL Driver
461 *
462 * This driver requires:
463 *
464 * Arbitrary Based Buffers:
465 * GraphicsHeap - PowerTV Graphics Heap
466 *
467 */
468 {
469 .name = "GraphicsHeap",
470 .start = 0x62700000,
471 .end = 0x63500000 - 1, /* 14 MB total */
472 .flags = IORESOURCE_IO,
473 },
474 /*
475 *
476 * multi com buffer area
477 *
478 * This driver requires:
479 *
480 * Arbitrary Based Buffers:
481 * Docsis -
482 *
483 */
484 {
485 .name = "MulticomSHM",
486 .start = 0x26000000,
487 .end = 0x26020000 - 1,
488 .flags = IORESOURCE_MEM,
489 },
490 /*
491 *
492 * DMA Ring buffer
493 *
494 * This driver requires:
495 *
496 * Arbitrary Based Buffers:
497 * Docsis -
498 *
499 */
500 {
501 .name = "BMM_Buffer",
502 .start = 0x00000000,
503 .end = 0x000AA000 - 1,
504 .flags = IORESOURCE_MEM,
505 },
506 /*
507 *
508 * Display bins buffer for unit0
509 *
510 * This driver requires:
511 *
512 * Arbitrary Based Buffers:
513 * Display Bins for unit0
514 *
515 */
516 {
517 .name = "DisplayBins0",
518 .start = 0x00000000,
519 .end = 0x00000FFF, /* 4 KB total */
520 .flags = IORESOURCE_MEM,
521 },
522 /*
523 *
524 * Display bins buffer
525 *
526 * This driver requires:
527 *
528 * Arbitrary Based Buffers:
529 * Display Bins for unit1
530 *
531 */
532 {
533 .name = "DisplayBins1",
534 .start = 0x64AD4000,
535 .end = 0x64AD5000 - 1, /* 4 KB total */
536 .flags = IORESOURCE_IO,
537 },
538 /*
539 *
540 * AVFS: player HAL memory
541 *
542 *
543 */
544 {
545 .name = "AvfsDmaMem",
546 .start = 0x6430E000,
547 .end = 0x645D2C00 - 1, /* 945K * 3 for playback */
548 .flags = IORESOURCE_IO,
549 },
550 /*
551 *
552 * PMEM
553 *
554 * This driver requires:
555 *
556 * Arbitrary Based Buffers:
557 * Persistent memory for diagnostics.
558 *
559 */
560 {
561 .name = "DiagPersistentMemory",
562 .start = 0x00000000,
563 .end = 0x10000 - 1,
564 .flags = IORESOURCE_MEM,
565 },
566 /*
567 *
568 * Smartcard
569 *
570 * This driver requires:
571 *
572 * Arbitrary Based Buffers:
573 * Read and write buffers for Internal/External cards
574 *
575 */
576 {
577 .name = "SmartCardInfo",
578 .start = 0x64AD1000,
579 .end = 0x64AD3800 - 1,
580 .flags = IORESOURCE_IO,
581 },
582 /*
583 *
584 * KAVNET
585 * NP Reset Vector - must be of the form xxCxxxxx
586 * NP Image - must be video bank 1
587 * NP IPC - must be video bank 2
588 */
589 {
590 .name = "NP_Reset_Vector",
591 .start = 0x27c00000,
592 .end = 0x27c01000 - 1,
593 .flags = IORESOURCE_MEM,
594 },
595 {
596 .name = "NP_Image",
597 .start = 0x27020000,
598 .end = 0x27060000 - 1,
599 .flags = IORESOURCE_MEM,
600 },
601 {
602 .name = "NP_IPC",
603 .start = 0x63500000,
604 .end = 0x63580000 - 1,
605 .flags = IORESOURCE_IO,
606 },
607 { },
608};
diff --git a/arch/mips/powertv/asic/prealloc-cronuslite.c b/arch/mips/powertv/asic/prealloc-cronuslite.c
new file mode 100644
index 000000000000..23a905613c04
--- /dev/null
+++ b/arch/mips/powertv/asic/prealloc-cronuslite.c
@@ -0,0 +1,290 @@
1/*
2 * Memory pre-allocations for Cronus Lite boxes.
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: Ken Eppinett
21 * David Schleef <ds@schleef.org>
22 */
23
24#include <linux/init.h>
25#include <asm/mach-powertv/asic.h>
26
27/*
28 * NON_DVR_CAPABLE CRONUSLITE RESOURCES
29 */
30struct resource non_dvr_cronuslite_resources[] __initdata =
31{
32 /*
33 *
34 * VIDEO2 / LX2
35 *
36 */
37 {
38 .name = "ST231aImage", /* Delta-Mu 2 image and ram */
39 .start = 0x60000000,
40 .end = 0x601FFFFF, /* 2MiB */
41 .flags = IORESOURCE_IO,
42 },
43 {
44 .name = "ST231aMonitor", /* 8KiB block ST231b monitor */
45 .start = 0x60200000,
46 .end = 0x60201FFF,
47 .flags = IORESOURCE_IO,
48 },
49 {
50 .name = "MediaMemory1",
51 .start = 0x60202000,
52 .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
53 .flags = IORESOURCE_IO,
54 },
55 /*
56 *
57 * Sysaudio Driver
58 *
59 * This driver requires:
60 *
61 * Arbitrary Based Buffers:
62 * DSP_Image_Buff - DSP code and data images (1MB)
63 * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB)
64 * ADSC_AUX_Buff - ADSC AUX buffer (16KB)
65 * ADSC_Main_Buff - ADSC Main buffer (16KB)
66 *
67 */
68 {
69 .name = "DSP_Image_Buff",
70 .start = 0x00000000,
71 .end = 0x000FFFFF,
72 .flags = IORESOURCE_MEM,
73 },
74 {
75 .name = "ADSC_CPU_PCM_Buff",
76 .start = 0x00000000,
77 .end = 0x00009FFF,
78 .flags = IORESOURCE_MEM,
79 },
80 {
81 .name = "ADSC_AUX_Buff",
82 .start = 0x00000000,
83 .end = 0x00003FFF,
84 .flags = IORESOURCE_MEM,
85 },
86 {
87 .name = "ADSC_Main_Buff",
88 .start = 0x00000000,
89 .end = 0x00003FFF,
90 .flags = IORESOURCE_MEM,
91 },
92 /*
93 *
94 * STAVEM driver/STAPI
95 *
96 * This driver requires:
97 *
98 * Arbitrary Based Buffers:
99 * This memory area is used for allocating buffers for Video decoding
100 * purposes. Allocation/De-allocation within this buffer is managed
101 * by the STAVMEM driver of the STAPI. They could be Decimated
102 * Picture Buffers, Intermediate Buffers, as deemed necessary for
103 * video decoding purposes, for any video decoders on Zeus.
104 *
105 */
106 {
107 .name = "AVMEMPartition0",
108 .start = 0x63580000,
109 .end = 0x63B80000 - 1, /* 6 MB total */
110 .flags = IORESOURCE_IO,
111 },
112 /*
113 *
114 * DOCSIS Subsystem
115 *
116 * This driver requires:
117 *
118 * Arbitrary Based Buffers:
119 * Docsis -
120 *
121 */
122 {
123 .name = "Docsis",
124 .start = 0x62000000,
125 .end = 0x62700000 - 1, /* 7 MB total */
126 .flags = IORESOURCE_IO,
127 },
128 /*
129 *
130 * GHW HAL Driver
131 *
132 * This driver requires:
133 *
134 * Arbitrary Based Buffers:
135 * GraphicsHeap - PowerTV Graphics Heap
136 *
137 */
138 {
139 .name = "GraphicsHeap",
140 .start = 0x62700000,
141 .end = 0x63500000 - 1, /* 14 MB total */
142 .flags = IORESOURCE_IO,
143 },
144 /*
145 *
146 * multi com buffer area
147 *
148 * This driver requires:
149 *
150 * Arbitrary Based Buffers:
151 * Docsis -
152 *
153 */
154 {
155 .name = "MulticomSHM",
156 .start = 0x26000000,
157 .end = 0x26020000 - 1,
158 .flags = IORESOURCE_MEM,
159 },
160 /*
161 *
162 * DMA Ring buffer
163 *
164 * This driver requires:
165 *
166 * Arbitrary Based Buffers:
167 * Docsis -
168 *
169 */
170 {
171 .name = "BMM_Buffer",
172 .start = 0x00000000,
173 .end = 0x000AA000 - 1,
174 .flags = IORESOURCE_MEM,
175 },
176 /*
177 *
178 * Display bins buffer for unit0
179 *
180 * This driver requires:
181 *
182 * Arbitrary Based Buffers:
183 * Display Bins for unit0
184 *
185 */
186 {
187 .name = "DisplayBins0",
188 .start = 0x00000000,
189 .end = 0x00000FFF, /* 4 KB total */
190 .flags = IORESOURCE_MEM,
191 },
192 /*
193 *
194 * Display bins buffer
195 *
196 * This driver requires:
197 *
198 * Arbitrary Based Buffers:
199 * Display Bins for unit1
200 *
201 */
202 {
203 .name = "DisplayBins1",
204 .start = 0x63B83000,
205 .end = 0x63B84000 - 1, /* 4 KB total */
206 .flags = IORESOURCE_IO,
207 },
208 /*
209 *
210 * AVFS: player HAL memory
211 *
212 *
213 */
214 {
215 .name = "AvfsDmaMem",
216 .start = 0x63B84000,
217 .end = 0x63E48C00 - 1, /* 945K * 3 for playback */
218 .flags = IORESOURCE_IO,
219 },
220 /*
221 *
222 * PMEM
223 *
224 * This driver requires:
225 *
226 * Arbitrary Based Buffers:
227 * Persistent memory for diagnostics.
228 *
229 */
230 {
231 .name = "DiagPersistentMemory",
232 .start = 0x00000000,
233 .end = 0x10000 - 1,
234 .flags = IORESOURCE_MEM,
235 },
236 /*
237 *
238 * Smartcard
239 *
240 * This driver requires:
241 *
242 * Arbitrary Based Buffers:
243 * Read and write buffers for Internal/External cards
244 *
245 */
246 {
247 .name = "SmartCardInfo",
248 .start = 0x63B80000,
249 .end = 0x63B82800 - 1,
250 .flags = IORESOURCE_IO,
251 },
252 /*
253 *
254 * KAVNET
255 * NP Reset Vector - must be of the form xxCxxxxx
256 * NP Image - must be video bank 1
257 * NP IPC - must be video bank 2
258 */
259 {
260 .name = "NP_Reset_Vector",
261 .start = 0x27c00000,
262 .end = 0x27c01000 - 1,
263 .flags = IORESOURCE_MEM,
264 },
265 {
266 .name = "NP_Image",
267 .start = 0x27020000,
268 .end = 0x27060000 - 1,
269 .flags = IORESOURCE_MEM,
270 },
271 {
272 .name = "NP_IPC",
273 .start = 0x63500000,
274 .end = 0x63580000 - 1,
275 .flags = IORESOURCE_IO,
276 },
277 /*
278 * NAND Flash
279 */
280 {
281 .name = "NandFlash",
282 .start = NAND_FLASH_BASE,
283 .end = NAND_FLASH_BASE + 0x400 - 1,
284 .flags = IORESOURCE_IO,
285 },
286 /*
287 * Add other resources here
288 */
289 { },
290};
diff --git a/arch/mips/powertv/asic/prealloc-zeus.c b/arch/mips/powertv/asic/prealloc-zeus.c
new file mode 100644
index 000000000000..018d4514dbe3
--- /dev/null
+++ b/arch/mips/powertv/asic/prealloc-zeus.c
@@ -0,0 +1,459 @@
1/*
2 * Memory pre-allocations for Zeus boxes.
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: Ken Eppinett
21 * David Schleef <ds@schleef.org>
22 */
23
24#include <linux/init.h>
25#include <asm/mach-powertv/asic.h>
26
27/*
28 * DVR_CAPABLE RESOURCES
29 */
30struct resource dvr_zeus_resources[] __initdata =
31{
32 /*
33 *
34 * VIDEO1 / LX1
35 *
36 */
37 {
38 .name = "ST231aImage", /* Delta-Mu 1 image and ram */
39 .start = 0x20000000,
40 .end = 0x201FFFFF, /* 2MiB */
41 .flags = IORESOURCE_IO,
42 },
43 {
44 .name = "ST231aMonitor", /* 8KiB block ST231a monitor */
45 .start = 0x20200000,
46 .end = 0x20201FFF,
47 .flags = IORESOURCE_IO,
48 },
49 {
50 .name = "MediaMemory1",
51 .start = 0x20202000,
52 .end = 0x21FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
53 .flags = IORESOURCE_IO,
54 },
55 /*
56 *
57 * VIDEO2 / LX2
58 *
59 */
60 {
61 .name = "ST231bImage", /* Delta-Mu 2 image and ram */
62 .start = 0x30000000,
63 .end = 0x301FFFFF, /* 2MiB */
64 .flags = IORESOURCE_IO,
65 },
66 {
67 .name = "ST231bMonitor", /* 8KiB block ST231b monitor */
68 .start = 0x30200000,
69 .end = 0x30201FFF,
70 .flags = IORESOURCE_IO,
71 },
72 {
73 .name = "MediaMemory2",
74 .start = 0x30202000,
75 .end = 0x31FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
76 .flags = IORESOURCE_IO,
77 },
78 /*
79 *
80 * Sysaudio Driver
81 *
82 * This driver requires:
83 *
84 * Arbitrary Based Buffers:
85 * DSP_Image_Buff - DSP code and data images (1MB)
86 * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB)
87 * ADSC_AUX_Buff - ADSC AUX buffer (16KB)
88 * ADSC_Main_Buff - ADSC Main buffer (16KB)
89 *
90 */
91 {
92 .name = "DSP_Image_Buff",
93 .start = 0x00000000,
94 .end = 0x000FFFFF,
95 .flags = IORESOURCE_MEM,
96 },
97 {
98 .name = "ADSC_CPU_PCM_Buff",
99 .start = 0x00000000,
100 .end = 0x00009FFF,
101 .flags = IORESOURCE_MEM,
102 },
103 {
104 .name = "ADSC_AUX_Buff",
105 .start = 0x00000000,
106 .end = 0x00003FFF,
107 .flags = IORESOURCE_MEM,
108 },
109 {
110 .name = "ADSC_Main_Buff",
111 .start = 0x00000000,
112 .end = 0x00003FFF,
113 .flags = IORESOURCE_MEM,
114 },
115 /*
116 *
117 * STAVEM driver/STAPI
118 *
119 * This driver requires:
120 *
121 * Arbitrary Based Buffers:
122 * This memory area is used for allocating buffers for Video decoding
123 * purposes. Allocation/De-allocation within this buffer is managed
124 * by the STAVMEM driver of the STAPI. They could be Decimated
125 * Picture Buffers, Intermediate Buffers, as deemed necessary for
126 * video decoding purposes, for any video decoders on Zeus.
127 *
128 */
129 {
130 .name = "AVMEMPartition0",
131 .start = 0x00000000,
132 .end = 0x00c00000 - 1, /* 12 MB total */
133 .flags = IORESOURCE_MEM,
134 },
135 /*
136 *
137 * DOCSIS Subsystem
138 *
139 * This driver requires:
140 *
141 * Arbitrary Based Buffers:
142 * Docsis -
143 *
144 */
145 {
146 .name = "Docsis",
147 .start = 0x40100000,
148 .end = 0x407fffff,
149 .flags = IORESOURCE_MEM,
150 },
151 /*
152 *
153 * GHW HAL Driver
154 *
155 * This driver requires:
156 *
157 * Arbitrary Based Buffers:
158 * GraphicsHeap - PowerTV Graphics Heap
159 *
160 */
161 {
162 .name = "GraphicsHeap",
163 .start = 0x46900000,
164 .end = 0x47700000 - 1, /* 14 MB total */
165 .flags = IORESOURCE_MEM,
166 },
167 /*
168 *
169 * multi com buffer area
170 *
171 * This driver requires:
172 *
173 * Arbitrary Based Buffers:
174 * Docsis -
175 *
176 */
177 {
178 .name = "MulticomSHM",
179 .start = 0x47900000,
180 .end = 0x47920000 - 1,
181 .flags = IORESOURCE_MEM,
182 },
183 /*
184 *
185 * DMA Ring buffer
186 *
187 * This driver requires:
188 *
189 * Arbitrary Based Buffers:
190 * Docsis -
191 *
192 */
193 {
194 .name = "BMM_Buffer",
195 .start = 0x00000000,
196 .end = 0x00280000 - 1,
197 .flags = IORESOURCE_MEM,
198 },
199 /*
200 *
201 * Display bins buffer for unit0
202 *
203 * This driver requires:
204 *
205 * Arbitrary Based Buffers:
206 * Display Bins for unit0
207 *
208 */
209 {
210 .name = "DisplayBins0",
211 .start = 0x00000000,
212 .end = 0x00000FFF, /* 4 KB total */
213 .flags = IORESOURCE_MEM,
214 },
215 /*
216 *
217 * Display bins buffer
218 *
219 * This driver requires:
220 *
221 * Arbitrary Based Buffers:
222 * Display Bins for unit1
223 *
224 */
225 {
226 .name = "DisplayBins1",
227 .start = 0x00000000,
228 .end = 0x00000FFF, /* 4 KB total */
229 .flags = IORESOURCE_MEM,
230 },
231 /*
232 *
233 * ITFS
234 *
235 * This driver requires:
236 *
237 * Arbitrary Based Buffers:
238 * Docsis -
239 *
240 */
241 {
242 .name = "ITFS",
243 .start = 0x00000000,
244 /* 815,104 bytes each for 2 ITFS partitions. */
245 .end = 0x0018DFFF,
246 .flags = IORESOURCE_MEM,
247 },
248 /*
249 *
250 * AVFS
251 *
252 * This driver requires:
253 *
254 * Arbitrary Based Buffers:
255 * Docsis -
256 *
257 */
258 {
259 .name = "AvfsDmaMem",
260 .start = 0x00000000,
261 /* (945K * 8) = (128K * 3) 5 playbacks / 3 server */
262 .end = 0x007c2000 - 1,
263 .flags = IORESOURCE_MEM,
264 },
265 {
266 .name = "AvfsFileSys",
267 .start = 0x00000000,
268 .end = 0x00001000 - 1, /* 4K */
269 .flags = IORESOURCE_MEM,
270 },
271 /*
272 *
273 * PMEM
274 *
275 * This driver requires:
276 *
277 * Arbitrary Based Buffers:
278 * Persistent memory for diagnostics.
279 *
280 */
281 {
282 .name = "DiagPersistentMemory",
283 .start = 0x00000000,
284 .end = 0x10000 - 1,
285 .flags = IORESOURCE_MEM,
286 },
287 /*
288 *
289 * Smartcard
290 *
291 * This driver requires:
292 *
293 * Arbitrary Based Buffers:
294 * Read and write buffers for Internal/External cards
295 *
296 */
297 {
298 .name = "SmartCardInfo",
299 .start = 0x00000000,
300 .end = 0x2800 - 1,
301 .flags = IORESOURCE_MEM,
302 },
303 /*
304 * Add other resources here
305 */
306 { },
307};
308
309/*
310 * NON_DVR_CAPABLE ZEUS RESOURCES
311 */
312struct resource non_dvr_zeus_resources[] __initdata =
313{
314 /*
315 * VIDEO1 / LX1
316 */
317 {
318 .name = "ST231aImage", /* Delta-Mu 1 image and ram */
319 .start = 0x20000000,
320 .end = 0x201FFFFF, /* 2MiB */
321 .flags = IORESOURCE_IO,
322 },
323 {
324 .name = "ST231aMonitor", /* 8KiB block ST231a monitor */
325 .start = 0x20200000,
326 .end = 0x20201FFF,
327 .flags = IORESOURCE_IO,
328 },
329 {
330 .name = "MediaMemory1",
331 .start = 0x20202000,
332 .end = 0x21FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
333 .flags = IORESOURCE_IO,
334 },
335 /*
336 * Sysaudio Driver
337 */
338 {
339 .name = "DSP_Image_Buff",
340 .start = 0x00000000,
341 .end = 0x000FFFFF,
342 .flags = IORESOURCE_MEM,
343 },
344 {
345 .name = "ADSC_CPU_PCM_Buff",
346 .start = 0x00000000,
347 .end = 0x00009FFF,
348 .flags = IORESOURCE_MEM,
349 },
350 {
351 .name = "ADSC_AUX_Buff",
352 .start = 0x00000000,
353 .end = 0x00003FFF,
354 .flags = IORESOURCE_MEM,
355 },
356 {
357 .name = "ADSC_Main_Buff",
358 .start = 0x00000000,
359 .end = 0x00003FFF,
360 .flags = IORESOURCE_MEM,
361 },
362 /*
363 * STAVEM driver/STAPI
364 */
365 {
366 .name = "AVMEMPartition0",
367 .start = 0x00000000,
368 .end = 0x00600000 - 1, /* 6 MB total */
369 .flags = IORESOURCE_MEM,
370 },
371 /*
372 * DOCSIS Subsystem
373 */
374 {
375 .name = "Docsis",
376 .start = 0x40100000,
377 .end = 0x407fffff,
378 .flags = IORESOURCE_MEM,
379 },
380 /*
381 * GHW HAL Driver
382 */
383 {
384 .name = "GraphicsHeap",
385 .start = 0x46900000,
386 .end = 0x47700000 - 1, /* 14 MB total */
387 .flags = IORESOURCE_MEM,
388 },
389 /*
390 * multi com buffer area
391 */
392 {
393 .name = "MulticomSHM",
394 .start = 0x47900000,
395 .end = 0x47920000 - 1,
396 .flags = IORESOURCE_MEM,
397 },
398 /*
399 * DMA Ring buffer
400 */
401 {
402 .name = "BMM_Buffer",
403 .start = 0x00000000,
404 .end = 0x00280000 - 1,
405 .flags = IORESOURCE_MEM,
406 },
407 /*
408 * Display bins buffer for unit0
409 */
410 {
411 .name = "DisplayBins0",
412 .start = 0x00000000,
413 .end = 0x00000FFF, /* 4 KB total */
414 .flags = IORESOURCE_MEM,
415 },
416 /*
417 *
418 * AVFS: player HAL memory
419 *
420 *
421 */
422 {
423 .name = "AvfsDmaMem",
424 .start = 0x00000000,
425 .end = 0x002c4c00 - 1, /* 945K * 3 for playback */
426 .flags = IORESOURCE_MEM,
427 },
428 /*
429 * PMEM
430 */
431 {
432 .name = "DiagPersistentMemory",
433 .start = 0x00000000,
434 .end = 0x10000 - 1,
435 .flags = IORESOURCE_MEM,
436 },
437 /*
438 * Smartcard
439 */
440 {
441 .name = "SmartCardInfo",
442 .start = 0x00000000,
443 .end = 0x2800 - 1,
444 .flags = IORESOURCE_MEM,
445 },
446 /*
447 * NAND Flash
448 */
449 {
450 .name = "NandFlash",
451 .start = NAND_FLASH_BASE,
452 .end = NAND_FLASH_BASE + 0x400 - 1,
453 .flags = IORESOURCE_IO,
454 },
455 /*
456 * Add other resources here
457 */
458 { },
459};
diff --git a/arch/mips/powertv/cmdline.c b/arch/mips/powertv/cmdline.c
new file mode 100644
index 000000000000..98d73cb0d452
--- /dev/null
+++ b/arch/mips/powertv/cmdline.c
@@ -0,0 +1,52 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 * Portions copyright (C) 2009 Cisco Systems, Inc.
5 *
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 *
19 * Kernel command line creation using the prom monitor (YAMON) argc/argv.
20 */
21#include <linux/init.h>
22#include <linux/string.h>
23
24#include <asm/bootinfo.h>
25
26#include "init.h"
27
28/*
29 * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
30 * This macro take care of sign extension.
31 */
32#define prom_argv(index) ((char *)(long)_prom_argv[(index)])
33
34char * __init prom_getcmdline(void)
35{
36 return &(arcs_cmdline[0]);
37}
38
39void __init prom_init_cmdline(void)
40{
41 int len;
42
43 if (prom_argc != 1)
44 return;
45
46 len = strlen(arcs_cmdline);
47
48 arcs_cmdline[len] = ' ';
49
50 strlcpy(arcs_cmdline + len + 1, (char *)_prom_argv,
51 COMMAND_LINE_SIZE - len - 1);
52}
diff --git a/arch/mips/powertv/init.c b/arch/mips/powertv/init.c
new file mode 100644
index 000000000000..5f4e4c304e48
--- /dev/null
+++ b/arch/mips/powertv/init.c
@@ -0,0 +1,128 @@
1/*
2 * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc.
3 * All rights reserved.
4 * Authors: Carsten Langgaard <carstenl@mips.com>
5 * Maciej W. Rozycki <macro@mips.com>
6 * Portions copyright (C) 2009 Cisco Systems, Inc.
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 *
21 * PROM library initialisation code.
22 */
23#include <linux/init.h>
24#include <linux/string.h>
25#include <linux/kernel.h>
26
27#include <asm/bootinfo.h>
28#include <linux/io.h>
29#include <asm/system.h>
30#include <asm/cacheflush.h>
31#include <asm/traps.h>
32
33#include <asm/mips-boards/prom.h>
34#include <asm/mips-boards/generic.h>
35#include <asm/mach-powertv/asic.h>
36
37#include "init.h"
38
39int prom_argc;
40int *_prom_argv, *_prom_envp;
41unsigned long _prom_memsize;
42
43/*
44 * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
45 * This macro take care of sign extension, if running in 64-bit mode.
46 */
47#define prom_envp(index) ((char *)(long)_prom_envp[(index)])
48
49char *prom_getenv(char *envname)
50{
51 char *result = NULL;
52
53 if (_prom_envp != NULL) {
54 /*
55 * Return a pointer to the given environment variable.
56 * In 64-bit mode: we're using 64-bit pointers, but all pointers
57 * in the PROM structures are only 32-bit, so we need some
58 * workarounds, if we are running in 64-bit mode.
59 */
60 int i, index = 0;
61
62 i = strlen(envname);
63
64 while (prom_envp(index)) {
65 if (strncmp(envname, prom_envp(index), i) == 0) {
66 result = prom_envp(index + 1);
67 break;
68 }
69 index += 2;
70 }
71 }
72
73 return result;
74}
75
76/* TODO: Verify on linux-mips mailing list that the following two */
77/* functions are correct */
78/* TODO: Copy NMI and EJTAG exception vectors to memory from the */
79/* BootROM exception vectors. Flush their cache entries. test it. */
80
81static void __init mips_nmi_setup(void)
82{
83 void *base;
84#if defined(CONFIG_CPU_MIPS32_R1)
85 base = cpu_has_veic ?
86 (void *)(CAC_BASE + 0xa80) :
87 (void *)(CAC_BASE + 0x380);
88#elif defined(CONFIG_CPU_MIPS32_R2)
89 base = (void *)0xbfc00000;
90#else
91#error NMI exception handler address not defined
92#endif
93}
94
95static void __init mips_ejtag_setup(void)
96{
97 void *base;
98
99#if defined(CONFIG_CPU_MIPS32_R1)
100 base = cpu_has_veic ?
101 (void *)(CAC_BASE + 0xa00) :
102 (void *)(CAC_BASE + 0x300);
103#elif defined(CONFIG_CPU_MIPS32_R2)
104 base = (void *)0xbfc00480;
105#else
106#error EJTAG exception handler address not defined
107#endif
108}
109
110void __init prom_init(void)
111{
112 prom_argc = fw_arg0;
113 _prom_argv = (int *) fw_arg1;
114 _prom_envp = (int *) fw_arg2;
115 _prom_memsize = (unsigned long) fw_arg3;
116
117 board_nmi_handler_setup = mips_nmi_setup;
118 board_ejtag_handler_setup = mips_ejtag_setup;
119
120 pr_info("\nLINUX started...\n");
121 prom_init_cmdline();
122 configure_platform();
123 prom_meminit();
124
125#ifndef CONFIG_BOOTLOADER_DRIVER
126 pr_info("\nBootloader driver isn't loaded...\n");
127#endif
128}
diff --git a/arch/mips/powertv/init.h b/arch/mips/powertv/init.h
new file mode 100644
index 000000000000..7af6bf25008c
--- /dev/null
+++ b/arch/mips/powertv/init.h
@@ -0,0 +1,28 @@
1/*
2 * Definitions from powertv init.c file
3 *
4 * Copyright (C) 2009 Cisco Systems, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: David VomLehn
21 */
22
23#ifndef _POWERTV_INIT_H
24#define _POWERTV_INIT_H
25extern int prom_argc;
26extern int *_prom_argv;
27extern unsigned long _prom_memsize;
28#endif
diff --git a/arch/mips/powertv/memory.c b/arch/mips/powertv/memory.c
new file mode 100644
index 000000000000..28d06605fff6
--- /dev/null
+++ b/arch/mips/powertv/memory.c
@@ -0,0 +1,186 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 * Portions copyright (C) 2009 Cisco Systems, Inc.
5 *
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 *
19 * Apparently originally from arch/mips/malta-memory.c. Modified to work
20 * with the PowerTV bootloader.
21 */
22#include <linux/init.h>
23#include <linux/mm.h>
24#include <linux/bootmem.h>
25#include <linux/pfn.h>
26#include <linux/string.h>
27
28#include <asm/bootinfo.h>
29#include <asm/page.h>
30#include <asm/sections.h>
31
32#include <asm/mips-boards/prom.h>
33
34#include "init.h"
35
36/* Memory constants */
37#define KIBIBYTE(n) ((n) * 1024) /* Number of kibibytes */
38#define MEBIBYTE(n) ((n) * KIBIBYTE(1024)) /* Number of mebibytes */
39#define DEFAULT_MEMSIZE MEBIBYTE(256) /* If no memsize provided */
40#define LOW_MEM_MAX MEBIBYTE(252) /* Max usable low mem */
41#define RES_BOOTLDR_MEMSIZE MEBIBYTE(1) /* Memory reserved for bldr */
42#define BOOT_MEM_SIZE KIBIBYTE(256) /* Memory reserved for bldr */
43#define PHYS_MEM_START 0x10000000 /* Start of physical memory */
44
45unsigned long ptv_memsize;
46
47char __initdata cmdline[COMMAND_LINE_SIZE];
48
49void __init prom_meminit(void)
50{
51 char *memsize_str;
52 unsigned long memsize = 0;
53 unsigned int physend;
54 char *ptr;
55 int low_mem;
56 int high_mem;
57
58 /* Check the command line first for a memsize directive */
59 strcpy(cmdline, arcs_cmdline);
60 ptr = strstr(cmdline, "memsize=");
61 if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' '))
62 ptr = strstr(ptr, " memsize=");
63
64 if (ptr) {
65 memsize = memparse(ptr + 8, &ptr);
66 } else {
67 /* otherwise look in the environment */
68 memsize_str = prom_getenv("memsize");
69
70 if (memsize_str != NULL) {
71 pr_info("prom memsize = %s\n", memsize_str);
72 memsize = simple_strtol(memsize_str, NULL, 0);
73 }
74
75 if (memsize == 0) {
76 if (_prom_memsize != 0) {
77 memsize = _prom_memsize;
78 pr_info("_prom_memsize = 0x%lx\n", memsize);
79 /* add in memory that the bootloader doesn't
80 * report */
81 memsize += BOOT_MEM_SIZE;
82 } else {
83 memsize = DEFAULT_MEMSIZE;
84 pr_info("Memsize not passed by bootloader, "
85 "defaulting to 0x%lx\n", memsize);
86 }
87 }
88 }
89
90 /* Store memsize for diagnostic purposes */
91 ptv_memsize = memsize;
92
93 physend = PFN_ALIGN(&_end) - 0x80000000;
94 if (memsize > LOW_MEM_MAX) {
95 low_mem = LOW_MEM_MAX;
96 high_mem = memsize - low_mem;
97 } else {
98 low_mem = memsize;
99 high_mem = 0;
100 }
101
102/*
103 * TODO: We will use the hard code for memory configuration until
104 * the bootloader releases their device tree to us.
105 */
106 /*
107 * Add the memory reserved for use by the bootloader to the
108 * memory map.
109 */
110 add_memory_region(PHYS_MEM_START, RES_BOOTLDR_MEMSIZE,
111 BOOT_MEM_RESERVED);
112#ifdef CONFIG_HIGHMEM_256_128
113 /*
114 * Add memory in low for general use by the kernel and its friends
115 * (like drivers, applications, etc).
116 */
117 add_memory_region(PHYS_MEM_START + RES_BOOTLDR_MEMSIZE,
118 LOW_MEM_MAX - RES_BOOTLDR_MEMSIZE, BOOT_MEM_RAM);
119 /*
120 * Add the memory reserved for reset vector.
121 */
122 add_memory_region(0x1fc00000, MEBIBYTE(4), BOOT_MEM_RESERVED);
123 /*
124 * Add the memory reserved.
125 */
126 add_memory_region(0x20000000, MEBIBYTE(1024 + 75), BOOT_MEM_RESERVED);
127 /*
128 * Add memory in high for general use by the kernel and its friends
129 * (like drivers, applications, etc).
130 *
131 * 75MB is reserved for devices which are using the memory in high.
132 */
133 add_memory_region(0x60000000 + MEBIBYTE(75), MEBIBYTE(128 - 75),
134 BOOT_MEM_RAM);
135#elif defined CONFIG_HIGHMEM_128_128
136 /*
137 * Add memory in low for general use by the kernel and its friends
138 * (like drivers, applications, etc).
139 */
140 add_memory_region(PHYS_MEM_START + RES_BOOTLDR_MEMSIZE,
141 MEBIBYTE(128) - RES_BOOTLDR_MEMSIZE, BOOT_MEM_RAM);
142 /*
143 * Add the memory reserved.
144 */
145 add_memory_region(PHYS_MEM_START + MEBIBYTE(128),
146 MEBIBYTE(128 + 1024 + 75), BOOT_MEM_RESERVED);
147 /*
148 * Add memory in high for general use by the kernel and its friends
149 * (like drivers, applications, etc).
150 *
151 * 75MB is reserved for devices which are using the memory in high.
152 */
153 add_memory_region(0x60000000 + MEBIBYTE(75), MEBIBYTE(128 - 75),
154 BOOT_MEM_RAM);
155#else
156 /* Add low memory regions for either:
157 * - no-highmemory configuration case -OR-
158 * - highmemory "HIGHMEM_LOWBANK_ONLY" case
159 */
160 /*
161 * Add memory for general use by the kernel and its friends
162 * (like drivers, applications, etc).
163 */
164 add_memory_region(PHYS_MEM_START + RES_BOOTLDR_MEMSIZE,
165 low_mem - RES_BOOTLDR_MEMSIZE, BOOT_MEM_RAM);
166 /*
167 * Add the memory reserved for reset vector.
168 */
169 add_memory_region(0x1fc00000, MEBIBYTE(4), BOOT_MEM_RESERVED);
170#endif
171}
172
173void __init prom_free_prom_memory(void)
174{
175 unsigned long addr;
176 int i;
177
178 for (i = 0; i < boot_mem_map.nr_map; i++) {
179 if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
180 continue;
181
182 addr = boot_mem_map.map[i].addr;
183 free_init_pages("prom memory",
184 addr, addr + boot_mem_map.map[i].size);
185 }
186}
diff --git a/arch/mips/powertv/pci/Makefile b/arch/mips/powertv/pci/Makefile
new file mode 100644
index 000000000000..f5c62462fc9d
--- /dev/null
+++ b/arch/mips/powertv/pci/Makefile
@@ -0,0 +1,21 @@
1#
2# Copyright (C) 2009 Scientific-Atlanta, Inc.
3#
4# This program is free software; you can redistribute it and/or modify
5# it under the terms of the GNU General Public License as published by
6# the Free Software Foundation; either version 2 of the License, or
7# (at your option) any later version.
8#
9# This program is distributed in the hope that it will be useful,
10# but WITHOUT ANY WARRANTY; without even the implied warranty of
11# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12# GNU General Public License for more details.
13#
14# You should have received a copy of the GNU General Public License
15# along with this program; if not, write to the Free Software
16# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17#
18
19obj-$(CONFIG_PCI) += fixup-powertv.o
20
21EXTRA_CFLAGS += -Wall -Werror
diff --git a/arch/mips/powertv/pci/fixup-powertv.c b/arch/mips/powertv/pci/fixup-powertv.c
new file mode 100644
index 000000000000..726bc2e824b3
--- /dev/null
+++ b/arch/mips/powertv/pci/fixup-powertv.c
@@ -0,0 +1,36 @@
1#include <linux/init.h>
2#include <linux/pci.h>
3#include <asm/mach-powertv/interrupts.h>
4#include "powertv-pci.h"
5
6int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
7{
8 return asic_pcie_map_irq(dev, slot, pin);
9}
10
11/* Do platform specific device initialization at pci_enable_device() time */
12int pcibios_plat_dev_init(struct pci_dev *dev)
13{
14 return 0;
15}
16
17/*
18 * asic_pcie_map_irq
19 *
20 * Parameters:
21 * *dev - pointer to a pci_dev structure (not used)
22 * slot - slot number (not used)
23 * pin - pin number (not used)
24 *
25 * Return Value:
26 * Returns: IRQ number (always the PCI Express IRQ number)
27 *
28 * Description:
29 * asic_pcie_map_irq will return the IRQ number of the PCI Express interrupt.
30 *
31 */
32int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
33{
34 return irq_pciexp;
35}
36EXPORT_SYMBOL(asic_pcie_map_irq);
diff --git a/arch/mips/powertv/pci/powertv-pci.h b/arch/mips/powertv/pci/powertv-pci.h
new file mode 100644
index 000000000000..1b5886bbd759
--- /dev/null
+++ b/arch/mips/powertv/pci/powertv-pci.h
@@ -0,0 +1,31 @@
1/*
2 * powertv-pci.c
3 *
4 * Copyright (C) 2009 Cisco Systems, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20/*
21 * Local definitions for the powertv PCI code
22 */
23
24#ifndef _POWERTV_PCI_POWERTV_PCI_H_
25#define _POWERTV_PCI_POWERTV_PCI_H_
26extern int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
27extern int asic_pcie_init(void);
28extern int asic_pcie_init(void);
29
30extern int log_level;
31#endif
diff --git a/arch/mips/powertv/powertv-clock.h b/arch/mips/powertv/powertv-clock.h
new file mode 100644
index 000000000000..d94c54311485
--- /dev/null
+++ b/arch/mips/powertv/powertv-clock.h
@@ -0,0 +1,26 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 *
18 * Author: David VomLehn
19 */
20
21#ifndef _POWERTV_POWERTV_CLOCK_H
22#define _POWERTV_POWERTV_CLOCK_H
23extern int powertv_clockevent_init(void);
24extern void powertv_clocksource_init(void);
25extern unsigned int mips_get_pll_freq(void);
26#endif
diff --git a/arch/mips/powertv/powertv_setup.c b/arch/mips/powertv/powertv_setup.c
new file mode 100644
index 000000000000..bd8ebf128f29
--- /dev/null
+++ b/arch/mips/powertv/powertv_setup.c
@@ -0,0 +1,351 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4 * Portions copyright (C) 2009 Cisco Systems, Inc.
5 *
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 */
19#include <linux/init.h>
20#include <linux/sched.h>
21#include <linux/ioport.h>
22#include <linux/pci.h>
23#include <linux/screen_info.h>
24#include <linux/notifier.h>
25#include <linux/etherdevice.h>
26#include <linux/if_ether.h>
27#include <linux/ctype.h>
28
29#include <linux/cpu.h>
30#include <asm/bootinfo.h>
31#include <asm/irq.h>
32#include <asm/mips-boards/generic.h>
33#include <asm/mips-boards/prom.h>
34#include <asm/dma.h>
35#include <linux/time.h>
36#include <asm/traps.h>
37#include <asm/asm-offsets.h>
38#include "reset.h"
39
40#define VAL(n) STR(n)
41
42/*
43 * Macros for loading addresses and storing registers:
44 * PTR_LA Load the address into a register
45 * LONG_S Store the full width of the given register.
46 * LONG_L Load the full width of the given register
47 * PTR_ADDIU Add a constant value to a register used as a pointer
48 * REG_SIZE Number of 8-bit bytes in a full width register
49 */
50#ifdef CONFIG_64BIT
51#warning TODO: 64-bit code needs to be verified
52#define PTR_LA "dla "
53#define LONG_S "sd "
54#define LONG_L "ld "
55#define PTR_ADDIU "daddiu "
56#define REG_SIZE "8" /* In bytes */
57#endif
58
59#ifdef CONFIG_32BIT
60#define PTR_LA "la "
61#define LONG_S "sw "
62#define LONG_L "lw "
63#define PTR_ADDIU "addiu "
64#define REG_SIZE "4" /* In bytes */
65#endif
66
67static struct pt_regs die_regs;
68static bool have_die_regs;
69
70static void register_panic_notifier(void);
71static int panic_handler(struct notifier_block *notifier_block,
72 unsigned long event, void *cause_string);
73
74const char *get_system_type(void)
75{
76 return "PowerTV";
77}
78
79void __init plat_mem_setup(void)
80{
81 panic_on_oops = 1;
82 register_panic_notifier();
83
84#if 0
85 mips_pcibios_init();
86#endif
87 mips_reboot_setup();
88}
89
90/*
91 * Install a panic notifier for platform-specific diagnostics
92 */
93static void register_panic_notifier()
94{
95 static struct notifier_block panic_notifier = {
96 .notifier_call = panic_handler,
97 .next = NULL,
98 .priority = INT_MAX
99 };
100 atomic_notifier_chain_register(&panic_notifier_list, &panic_notifier);
101}
102
103static int panic_handler(struct notifier_block *notifier_block,
104 unsigned long event, void *cause_string)
105{
106 struct pt_regs my_regs;
107
108 /* Save all of the registers */
109 {
110 unsigned long at, v0, v1; /* Must be on the stack */
111
112 /* Start by saving $at and v0 on the stack. We use $at
113 * ourselves, but it looks like the compiler may use v0 or v1
114 * to load the address of the pt_regs structure. We'll come
115 * back later to store the registers in the pt_regs
116 * structure. */
117 __asm__ __volatile__ (
118 ".set noat\n"
119 LONG_S "$at, %[at]\n"
120 LONG_S "$2, %[v0]\n"
121 LONG_S "$3, %[v1]\n"
122 :
123 [at] "=m" (at),
124 [v0] "=m" (v0),
125 [v1] "=m" (v1)
126 :
127 : "at"
128 );
129
130 __asm__ __volatile__ (
131 ".set noat\n"
132 "move $at, %[pt_regs]\n"
133
134 /* Argument registers */
135 LONG_S "$4, " VAL(PT_R4) "($at)\n"
136 LONG_S "$5, " VAL(PT_R5) "($at)\n"
137 LONG_S "$6, " VAL(PT_R6) "($at)\n"
138 LONG_S "$7, " VAL(PT_R7) "($at)\n"
139
140 /* Temporary regs */
141 LONG_S "$8, " VAL(PT_R8) "($at)\n"
142 LONG_S "$9, " VAL(PT_R9) "($at)\n"
143 LONG_S "$10, " VAL(PT_R10) "($at)\n"
144 LONG_S "$11, " VAL(PT_R11) "($at)\n"
145 LONG_S "$12, " VAL(PT_R12) "($at)\n"
146 LONG_S "$13, " VAL(PT_R13) "($at)\n"
147 LONG_S "$14, " VAL(PT_R14) "($at)\n"
148 LONG_S "$15, " VAL(PT_R15) "($at)\n"
149
150 /* "Saved" registers */
151 LONG_S "$16, " VAL(PT_R16) "($at)\n"
152 LONG_S "$17, " VAL(PT_R17) "($at)\n"
153 LONG_S "$18, " VAL(PT_R18) "($at)\n"
154 LONG_S "$19, " VAL(PT_R19) "($at)\n"
155 LONG_S "$20, " VAL(PT_R20) "($at)\n"
156 LONG_S "$21, " VAL(PT_R21) "($at)\n"
157 LONG_S "$22, " VAL(PT_R22) "($at)\n"
158 LONG_S "$23, " VAL(PT_R23) "($at)\n"
159
160 /* Add'l temp regs */
161 LONG_S "$24, " VAL(PT_R24) "($at)\n"
162 LONG_S "$25, " VAL(PT_R25) "($at)\n"
163
164 /* Kernel temp regs */
165 LONG_S "$26, " VAL(PT_R26) "($at)\n"
166 LONG_S "$27, " VAL(PT_R27) "($at)\n"
167
168 /* Global pointer, stack pointer, frame pointer and
169 * return address */
170 LONG_S "$gp, " VAL(PT_R28) "($at)\n"
171 LONG_S "$sp, " VAL(PT_R29) "($at)\n"
172 LONG_S "$fp, " VAL(PT_R30) "($at)\n"
173 LONG_S "$ra, " VAL(PT_R31) "($at)\n"
174
175 /* Now we can get the $at and v0 registers back and
176 * store them */
177 LONG_L "$8, %[at]\n"
178 LONG_S "$8, " VAL(PT_R1) "($at)\n"
179 LONG_L "$8, %[v0]\n"
180 LONG_S "$8, " VAL(PT_R2) "($at)\n"
181 LONG_L "$8, %[v1]\n"
182 LONG_S "$8, " VAL(PT_R3) "($at)\n"
183 :
184 :
185 [at] "m" (at),
186 [v0] "m" (v0),
187 [v1] "m" (v1),
188 [pt_regs] "r" (&my_regs)
189 : "at", "t0"
190 );
191
192 /* Set the current EPC value to be the current location in this
193 * function */
194 __asm__ __volatile__ (
195 ".set noat\n"
196 "1:\n"
197 PTR_LA "$at, 1b\n"
198 LONG_S "$at, %[cp0_epc]\n"
199 :
200 [cp0_epc] "=m" (my_regs.cp0_epc)
201 :
202 : "at"
203 );
204
205 my_regs.cp0_cause = read_c0_cause();
206 my_regs.cp0_status = read_c0_status();
207 }
208
209#ifdef CONFIG_DIAGNOSTICS
210 failure_report((char *) cause_string,
211 have_die_regs ? &die_regs : &my_regs);
212 have_die_regs = false;
213#else
214 pr_crit("I'm feeling a bit sleepy. hmmmmm... perhaps a nap would... "
215 "zzzz... \n");
216#endif
217
218 return NOTIFY_DONE;
219}
220
221/**
222 * Platform-specific handling of oops
223 * @str: Pointer to the oops string
224 * @regs: Pointer to the oops registers
225 * All we do here is to save the registers for subsequent printing through
226 * the panic notifier.
227 */
228void platform_die(const char *str, const struct pt_regs *regs)
229{
230 /* If we already have saved registers, don't overwrite them as they
231 * they apply to the initial fault */
232
233 if (!have_die_regs) {
234 have_die_regs = true;
235 die_regs = *regs;
236 }
237}
238
239/* Information about the RF MAC address, if one was supplied on the
240 * command line. */
241static bool have_rfmac;
242static u8 rfmac[ETH_ALEN];
243
244static int rfmac_param(char *p)
245{
246 u8 *q;
247 bool is_high_nibble;
248 int c;
249
250 /* Skip a leading "0x", if present */
251 if (*p == '0' && *(p+1) == 'x')
252 p += 2;
253
254 q = rfmac;
255 is_high_nibble = true;
256
257 for (c = (unsigned char) *p++;
258 isxdigit(c) && q - rfmac < ETH_ALEN;
259 c = (unsigned char) *p++) {
260 int nibble;
261
262 nibble = (isdigit(c) ? (c - '0') :
263 (isupper(c) ? c - 'A' + 10 : c - 'a' + 10));
264
265 if (is_high_nibble)
266 *q = nibble << 4;
267 else
268 *q++ |= nibble;
269
270 is_high_nibble = !is_high_nibble;
271 }
272
273 /* If we parsed all the way to the end of the parameter value and
274 * parsed all ETH_ALEN bytes, we have a usable RF MAC address */
275 have_rfmac = (c == '\0' && q - rfmac == ETH_ALEN);
276
277 return 0;
278}
279
280early_param("rfmac", rfmac_param);
281
282/*
283 * Generate an Ethernet MAC address that has a good chance of being unique.
284 * @addr: Pointer to six-byte array containing the Ethernet address
285 * Generates an Ethernet MAC address that is highly likely to be unique for
286 * this particular system on a network with other systems of the same type.
287 *
288 * The problem we are solving is that, when random_ether_addr() is used to
289 * generate MAC addresses at startup, there isn't much entropy for the random
290 * number generator to use and the addresses it produces are fairly likely to
291 * be the same as those of other identical systems on the same local network.
292 * This is true even for relatively small numbers of systems (for the reason
293 * why, see the Wikipedia entry for "Birthday problem" at:
294 * http://en.wikipedia.org/wiki/Birthday_problem
295 *
296 * The good news is that we already have a MAC address known to be unique, the
297 * RF MAC address. The bad news is that this address is already in use on the
298 * RF interface. Worse, the obvious trick, taking the RF MAC address and
299 * turning on the locally managed bit, has already been used for other devices.
300 * Still, this does give us something to work with.
301 *
302 * The approach we take is:
303 * 1. If we can't get the RF MAC Address, just call random_ether_addr.
304 * 2. Use the 24-bit NIC-specific bits of the RF MAC address as the last 24
305 * bits of the new address. This is very likely to be unique, except for
306 * the current box.
307 * 3. To avoid using addresses already on the current box, we set the top
308 * six bits of the address with a value different from any currently
309 * registered Scientific Atlanta organizationally unique identifyer
310 * (OUI). This avoids duplication with any addresses on the system that
311 * were generated from valid Scientific Atlanta-registered address by
312 * simply flipping the locally managed bit.
313 * 4. We aren't generating a multicast address, so we leave the multicast
314 * bit off. Since we aren't using a registered address, we have to set
315 * the locally managed bit.
316 * 5. We then randomly generate the remaining 16-bits. This does two
317 * things:
318 * a. It allows us to call this function for more than one device
319 * in this system
320 * b. It ensures that things will probably still work even if
321 * some device on the device network has a locally managed
322 * address that matches the top six bits from step 2.
323 */
324void platform_random_ether_addr(u8 addr[ETH_ALEN])
325{
326 const int num_random_bytes = 2;
327 const unsigned char non_sciatl_oui_bits = 0xc0u;
328 const unsigned char mac_addr_locally_managed = (1 << 1);
329
330 if (!have_rfmac) {
331 pr_warning("rfmac not available on command line; "
332 "generating random MAC address\n");
333 random_ether_addr(addr);
334 }
335
336 else {
337 int i;
338
339 /* Set the first byte to something that won't match a Scientific
340 * Atlanta OUI, is locally managed, and isn't a multicast
341 * address */
342 addr[0] = non_sciatl_oui_bits | mac_addr_locally_managed;
343
344 /* Get some bytes of random address information */
345 get_random_bytes(&addr[1], num_random_bytes);
346
347 /* Copy over the NIC-specific bits of the RF MAC address */
348 for (i = 1 + num_random_bytes; i < ETH_ALEN; i++)
349 addr[i] = rfmac[i];
350 }
351}
diff --git a/arch/mips/powertv/reset.c b/arch/mips/powertv/reset.c
new file mode 100644
index 000000000000..494c652c984b
--- /dev/null
+++ b/arch/mips/powertv/reset.c
@@ -0,0 +1,65 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 * Portions copyright (C) 2009 Cisco Systems, Inc.
5 *
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 */
19#include <linux/pm.h>
20
21#include <linux/io.h>
22#include <asm/reboot.h> /* Not included by linux/reboot.h */
23
24#ifdef CONFIG_BOOTLOADER_DRIVER
25#include <asm/mach-powertv/kbldr.h>
26#endif
27
28#include <asm/mach-powertv/asic_regs.h>
29#include "reset.h"
30
31static void mips_machine_restart(char *command);
32static void mips_machine_halt(void);
33
34static void mips_machine_restart(char *command)
35{
36#ifdef CONFIG_BOOTLOADER_DRIVER
37 /*
38 * Call the bootloader's reset function to ensure
39 * that persistent data is flushed before hard reset
40 */
41 kbldr_SetCauseAndReset();
42#else
43 writel(0x1, asic_reg_addr(watchdog));
44#endif
45}
46
47static void mips_machine_halt(void)
48{
49#ifdef CONFIG_BOOTLOADER_DRIVER
50 /*
51 * Call the bootloader's reset function to ensure
52 * that persistent data is flushed before hard reset
53 */
54 kbldr_SetCauseAndReset();
55#else
56 writel(0x1, asic_reg_addr(watchdog));
57#endif
58}
59
60void mips_reboot_setup(void)
61{
62 _machine_restart = mips_machine_restart;
63 _machine_halt = mips_machine_halt;
64 pm_power_off = mips_machine_halt;
65}
diff --git a/arch/mips/powertv/reset.h b/arch/mips/powertv/reset.h
new file mode 100644
index 000000000000..888fd09e2620
--- /dev/null
+++ b/arch/mips/powertv/reset.h
@@ -0,0 +1,26 @@
1/*
2 * Definitions from powertv reset.c file
3 *
4 * Copyright (C) 2009 Cisco Systems, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: David VomLehn
21 */
22
23#ifndef _POWERTV_POWERTV_RESET_H
24#define _POWERTV_POWERTV_RESET_H
25extern void mips_reboot_setup(void);
26#endif
diff --git a/arch/mips/mipssim/sim_cmdline.c b/arch/mips/powertv/time.c
index 74240e1ce5a5..1e0a5ef4c8c7 100644
--- a/arch/mips/mipssim/sim_cmdline.c
+++ b/arch/mips/powertv/time.c
@@ -1,5 +1,7 @@
1/* 1/*
2 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. 2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 * Portions copyright (C) 2009 Cisco Systems, Inc.
3 * 5 *
4 * This program is free software; you can distribute it and/or modify it 6 * This program is free software; you can distribute it and/or modify it
5 * under the terms of the GNU General Public License (Version 2) as 7 * under the terms of the GNU General Public License (Version 2) as
@@ -14,19 +16,22 @@
14 * with this program; if not, write to the Free Software Foundation, Inc., 16 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 * 18 *
19 * Setting up the clock on the MIPS boards.
17 */ 20 */
21
18#include <linux/init.h> 22#include <linux/init.h>
19#include <linux/string.h> 23#include <asm/mach-powertv/interrupts.h>
20#include <asm/bootinfo.h> 24#include <asm/time.h>
21 25
22extern char arcs_cmdline[]; 26#include "powertv-clock.h"
23 27
24char * __init prom_getcmdline(void) 28unsigned int __cpuinit get_c0_compare_int(void)
25{ 29{
26 return arcs_cmdline; 30 return irq_mips_timer;
27} 31}
28 32
29void __init prom_init_cmdline(void) 33void __init plat_time_init(void)
30{ 34{
31 /* XXX: Get boot line from environment? */ 35 powertv_clocksource_init();
36 r4k_clockevent_init();
32} 37}
diff --git a/arch/mips/rb532/prom.c b/arch/mips/rb532/prom.c
index ad5bd1097974..d7c26d00cfef 100644
--- a/arch/mips/rb532/prom.c
+++ b/arch/mips/rb532/prom.c
@@ -69,7 +69,7 @@ static inline unsigned long tag2ul(char *arg, const char *tag)
69 69
70void __init prom_setup_cmdline(void) 70void __init prom_setup_cmdline(void)
71{ 71{
72 static char cmd_line[CL_SIZE] __initdata; 72 static char cmd_line[COMMAND_LINE_SIZE] __initdata;
73 char *cp, *board; 73 char *cp, *board;
74 int prom_argc; 74 int prom_argc;
75 char **prom_argv, **prom_envp; 75 char **prom_argv, **prom_envp;
@@ -115,7 +115,7 @@ void __init prom_setup_cmdline(void)
115 strcpy(cp, arcs_cmdline); 115 strcpy(cp, arcs_cmdline);
116 cp += strlen(arcs_cmdline); 116 cp += strlen(arcs_cmdline);
117 } 117 }
118 cmd_line[CL_SIZE-1] = '\0'; 118 cmd_line[COMMAND_LINE_SIZE - 1] = '\0';
119 119
120 strcpy(arcs_cmdline, cmd_line); 120 strcpy(arcs_cmdline, cmd_line);
121} 121}
diff --git a/arch/mips/sgi-ip22/ip22-eisa.c b/arch/mips/sgi-ip22/ip22-eisa.c
index 1617241d2737..da44ccb20829 100644
--- a/arch/mips/sgi-ip22/ip22-eisa.c
+++ b/arch/mips/sgi-ip22/ip22-eisa.c
@@ -50,9 +50,9 @@
50 50
51static char __init *decode_eisa_sig(unsigned long addr) 51static char __init *decode_eisa_sig(unsigned long addr)
52{ 52{
53 static char sig_str[EISA_SIG_LEN]; 53 static char sig_str[EISA_SIG_LEN] __initdata;
54 u8 sig[4]; 54 u8 sig[4];
55 u16 rev; 55 u16 rev;
56 int i; 56 int i;
57 57
58 for (i = 0; i < 4; i++) { 58 for (i = 0; i < 4; i++) {
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c
index 0ecd5fe9486e..383f11d7f442 100644
--- a/arch/mips/sgi-ip22/ip22-int.c
+++ b/arch/mips/sgi-ip22/ip22-int.c
@@ -13,6 +13,7 @@
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/kernel_stat.h> 14#include <linux/kernel_stat.h>
15#include <linux/interrupt.h> 15#include <linux/interrupt.h>
16#include <linux/ftrace.h>
16 17
17#include <asm/irq_cpu.h> 18#include <asm/irq_cpu.h>
18#include <asm/sgi/hpc3.h> 19#include <asm/sgi/hpc3.h>
@@ -150,7 +151,7 @@ static void indy_local1_irqdispatch(void)
150 151
151extern void ip22_be_interrupt(int irq); 152extern void ip22_be_interrupt(int irq);
152 153
153static void indy_buserror_irq(void) 154static void __irq_entry indy_buserror_irq(void)
154{ 155{
155 int irq = SGI_BUSERR_IRQ; 156 int irq = SGI_BUSERR_IRQ;
156 157
diff --git a/arch/mips/sgi-ip22/ip22-setup.c b/arch/mips/sgi-ip22/ip22-setup.c
index b9a931358e23..5deeb68b6c9c 100644
--- a/arch/mips/sgi-ip22/ip22-setup.c
+++ b/arch/mips/sgi-ip22/ip22-setup.c
@@ -67,7 +67,7 @@ void __init plat_mem_setup(void)
67 cserial = ArcGetEnvironmentVariable("ConsoleOut"); 67 cserial = ArcGetEnvironmentVariable("ConsoleOut");
68 68
69 if ((ctype && *ctype == 'd') || (cserial && *cserial == 's')) { 69 if ((ctype && *ctype == 'd') || (cserial && *cserial == 's')) {
70 static char options[8]; 70 static char options[8] __initdata;
71 char *baud = ArcGetEnvironmentVariable("dbaud"); 71 char *baud = ArcGetEnvironmentVariable("dbaud");
72 if (baud) 72 if (baud)
73 strcpy(options, baud); 73 strcpy(options, baud);
diff --git a/arch/mips/sgi-ip22/ip22-time.c b/arch/mips/sgi-ip22/ip22-time.c
index c8f7d2328b24..603fc91c1030 100644
--- a/arch/mips/sgi-ip22/ip22-time.c
+++ b/arch/mips/sgi-ip22/ip22-time.c
@@ -16,6 +16,7 @@
16#include <linux/interrupt.h> 16#include <linux/interrupt.h>
17#include <linux/kernel_stat.h> 17#include <linux/kernel_stat.h>
18#include <linux/time.h> 18#include <linux/time.h>
19#include <linux/ftrace.h>
19 20
20#include <asm/cpu.h> 21#include <asm/cpu.h>
21#include <asm/mipsregs.h> 22#include <asm/mipsregs.h>
@@ -115,7 +116,7 @@ __init void plat_time_init(void)
115} 116}
116 117
117/* Generic SGI handler for (spurious) 8254 interrupts */ 118/* Generic SGI handler for (spurious) 8254 interrupts */
118void indy_8254timer_irq(void) 119void __irq_entry indy_8254timer_irq(void)
119{ 120{
120 int irq = SGI_8254_0_IRQ; 121 int irq = SGI_8254_0_IRQ;
121 ULONG cnt; 122 ULONG cnt;
diff --git a/arch/mips/sgi-ip32/ip32-setup.c b/arch/mips/sgi-ip32/ip32-setup.c
index c5a5d4a31b4b..3abd1465ec02 100644
--- a/arch/mips/sgi-ip32/ip32-setup.c
+++ b/arch/mips/sgi-ip32/ip32-setup.c
@@ -90,7 +90,7 @@ void __init plat_mem_setup(void)
90 { 90 {
91 char* con = ArcGetEnvironmentVariable("console"); 91 char* con = ArcGetEnvironmentVariable("console");
92 if (con && *con == 'd') { 92 if (con && *con == 'd') {
93 static char options[8]; 93 static char options[8] __initdata;
94 char *baud = ArcGetEnvironmentVariable("dbaud"); 94 char *baud = ArcGetEnvironmentVariable("dbaud");
95 if (baud) 95 if (baud)
96 strcpy(options, baud); 96 strcpy(options, baud);
diff --git a/arch/mips/sibyte/common/cfe.c b/arch/mips/sibyte/common/cfe.c
index eb5396cf81bb..6343011e9902 100644
--- a/arch/mips/sibyte/common/cfe.c
+++ b/arch/mips/sibyte/common/cfe.c
@@ -287,7 +287,7 @@ void __init prom_init(void)
287 * boot console 287 * boot console
288 */ 288 */
289 cfe_cons_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE); 289 cfe_cons_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
290 if (cfe_getenv("LINUX_CMDLINE", arcs_cmdline, CL_SIZE) < 0) { 290 if (cfe_getenv("LINUX_CMDLINE", arcs_cmdline, COMMAND_LINE_SIZE) < 0) {
291 if (argc >= 0) { 291 if (argc >= 0) {
292 /* The loader should have set the command line */ 292 /* The loader should have set the command line */
293 /* too early for panic to do any good */ 293 /* too early for panic to do any good */
@@ -318,7 +318,7 @@ void __init prom_init(void)
318#endif /* CONFIG_BLK_DEV_INITRD */ 318#endif /* CONFIG_BLK_DEV_INITRD */
319 319
320 /* Not sure this is needed, but it's the safe way. */ 320 /* Not sure this is needed, but it's the safe way. */
321 arcs_cmdline[CL_SIZE-1] = 0; 321 arcs_cmdline[COMMAND_LINE_SIZE-1] = 0;
322 322
323 prom_meminit(); 323 prom_meminit();
324 324
diff --git a/arch/mips/sni/a20r.c b/arch/mips/sni/a20r.c
index 7dd76fb3b645..e6980892834a 100644
--- a/arch/mips/sni/a20r.c
+++ b/arch/mips/sni/a20r.c
@@ -188,7 +188,7 @@ static void end_a20r_irq(unsigned int irq)
188} 188}
189 189
190static struct irq_chip a20r_irq_type = { 190static struct irq_chip a20r_irq_type = {
191 .typename = "A20R", 191 .name = "A20R",
192 .ack = mask_a20r_irq, 192 .ack = mask_a20r_irq,
193 .mask = mask_a20r_irq, 193 .mask = mask_a20r_irq,
194 .mask_ack = mask_a20r_irq, 194 .mask_ack = mask_a20r_irq,
diff --git a/arch/mips/sni/pcimt.c b/arch/mips/sni/pcimt.c
index 74e6c67982fb..51e62bbaa23b 100644
--- a/arch/mips/sni/pcimt.c
+++ b/arch/mips/sni/pcimt.c
@@ -214,7 +214,7 @@ static void end_pcimt_irq(unsigned int irq)
214} 214}
215 215
216static struct irq_chip pcimt_irq_type = { 216static struct irq_chip pcimt_irq_type = {
217 .typename = "PCIMT", 217 .name = "PCIMT",
218 .ack = disable_pcimt_irq, 218 .ack = disable_pcimt_irq,
219 .mask = disable_pcimt_irq, 219 .mask = disable_pcimt_irq,
220 .mask_ack = disable_pcimt_irq, 220 .mask_ack = disable_pcimt_irq,
diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c
index 071a9573ac7f..f4699d35858b 100644
--- a/arch/mips/sni/pcit.c
+++ b/arch/mips/sni/pcit.c
@@ -176,7 +176,7 @@ void end_pcit_irq(unsigned int irq)
176} 176}
177 177
178static struct irq_chip pcit_irq_type = { 178static struct irq_chip pcit_irq_type = {
179 .typename = "PCIT", 179 .name = "PCIT",
180 .ack = disable_pcit_irq, 180 .ack = disable_pcit_irq,
181 .mask = disable_pcit_irq, 181 .mask = disable_pcit_irq,
182 .mask_ack = disable_pcit_irq, 182 .mask_ack = disable_pcit_irq,
diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c
index 5e687819cbc2..46f00691f448 100644
--- a/arch/mips/sni/rm200.c
+++ b/arch/mips/sni/rm200.c
@@ -449,7 +449,7 @@ void end_rm200_irq(unsigned int irq)
449} 449}
450 450
451static struct irq_chip rm200_irq_type = { 451static struct irq_chip rm200_irq_type = {
452 .typename = "RM200", 452 .name = "RM200",
453 .ack = disable_rm200_irq, 453 .ack = disable_rm200_irq,
454 .mask = disable_rm200_irq, 454 .mask = disable_rm200_irq,
455 .mask_ack = disable_rm200_irq, 455 .mask_ack = disable_rm200_irq,
diff --git a/arch/mips/sni/setup.c b/arch/mips/sni/setup.c
index a49272ce7ef5..d16b462154c3 100644
--- a/arch/mips/sni/setup.c
+++ b/arch/mips/sni/setup.c
@@ -60,7 +60,7 @@ static void __init sni_console_setup(void)
60 char *cdev; 60 char *cdev;
61 char *baud; 61 char *baud;
62 int port; 62 int port;
63 static char options[8]; 63 static char options[8] __initdata;
64 64
65 cdev = prom_getenv("console_dev"); 65 cdev = prom_getenv("console_dev");
66 if (strncmp(cdev, "tty", 3) == 0) { 66 if (strncmp(cdev, "tty", 3) == 0) {
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index d66802edebb2..06e801c7e258 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -160,7 +160,7 @@ static void __init prom_init_cmdline(void)
160 int argc; 160 int argc;
161 int *argv32; 161 int *argv32;
162 int i; /* Always ignore the "-c" at argv[0] */ 162 int i; /* Always ignore the "-c" at argv[0] */
163 static char builtin[CL_SIZE] __initdata; 163 static char builtin[COMMAND_LINE_SIZE] __initdata;
164 164
165 if (fw_arg0 >= CKSEG0 || fw_arg1 < CKSEG0) { 165 if (fw_arg0 >= CKSEG0 || fw_arg1 < CKSEG0) {
166 /* 166 /*
@@ -315,7 +315,7 @@ static inline void txx9_cache_fixup(void)
315 315
316static void __init preprocess_cmdline(void) 316static void __init preprocess_cmdline(void)
317{ 317{
318 static char cmdline[CL_SIZE] __initdata; 318 static char cmdline[COMMAND_LINE_SIZE] __initdata;
319 char *s; 319 char *s;
320 320
321 strcpy(cmdline, arcs_cmdline); 321 strcpy(cmdline, arcs_cmdline);
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 7678538344f4..677cd53f18c3 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -291,14 +291,6 @@ config MTD_NAND_SHARPSL
291 tristate "Support for NAND Flash on Sharp SL Series (C7xx + others)" 291 tristate "Support for NAND Flash on Sharp SL Series (C7xx + others)"
292 depends on ARCH_PXA 292 depends on ARCH_PXA
293 293
294config MTD_NAND_BASLER_EXCITE
295 tristate "Support for NAND Flash on Basler eXcite"
296 depends on BASLER_EXCITE
297 help
298 This enables the driver for the NAND flash device found on the
299 Basler eXcite Smart Camera. If built as a module, the driver
300 will be named excite_nandflash.
301
302config MTD_NAND_CAFE 294config MTD_NAND_CAFE
303 tristate "NAND support for OLPC CAFÉ chip" 295 tristate "NAND support for OLPC CAFÉ chip"
304 depends on PCI 296 depends on PCI
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 460a1f39a8d1..1407bd144015 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -27,7 +27,6 @@ obj-$(CONFIG_MTD_NAND_ATMEL) += atmel_nand.o
27obj-$(CONFIG_MTD_NAND_GPIO) += gpio.o 27obj-$(CONFIG_MTD_NAND_GPIO) += gpio.o
28obj-$(CONFIG_MTD_NAND_OMAP2) += omap2.o 28obj-$(CONFIG_MTD_NAND_OMAP2) += omap2.o
29obj-$(CONFIG_MTD_NAND_CM_X270) += cmx270_nand.o 29obj-$(CONFIG_MTD_NAND_CM_X270) += cmx270_nand.o
30obj-$(CONFIG_MTD_NAND_BASLER_EXCITE) += excite_nandflash.o
31obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o 30obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o
32obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o 31obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o
33obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o 32obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
diff --git a/drivers/mtd/nand/excite_nandflash.c b/drivers/mtd/nand/excite_nandflash.c
deleted file mode 100644
index af6a6a5399e1..000000000000
--- a/drivers/mtd/nand/excite_nandflash.c
+++ /dev/null
@@ -1,248 +0,0 @@
1/*
2* Copyright (C) 2005 - 2007 by Basler Vision Technologies AG
3* Author: Thomas Koeller <thomas.koeller.qbaslerweb.com>
4* Original code by Thies Moeller <thies.moeller@baslerweb.com>
5*
6* This program is free software; you can redistribute it and/or modify
7* it under the terms of the GNU General Public License as published by
8* the Free Software Foundation; either version 2 of the License, or
9* (at your option) any later version.
10*
11* This program is distributed in the hope that it will be useful,
12* but WITHOUT ANY WARRANTY; without even the implied warranty of
13* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14* GNU General Public License for more details.
15*
16* You should have received a copy of the GNU General Public License
17* along with this program; if not, write to the Free Software
18* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19*/
20
21#include <linux/module.h>
22#include <linux/types.h>
23#include <linux/init.h>
24#include <linux/kernel.h>
25#include <linux/string.h>
26#include <linux/ioport.h>
27#include <linux/platform_device.h>
28#include <linux/delay.h>
29#include <linux/err.h>
30
31#include <linux/mtd/mtd.h>
32#include <linux/mtd/nand.h>
33#include <linux/mtd/nand_ecc.h>
34#include <linux/mtd/partitions.h>
35
36#include <asm/io.h>
37#include <asm/rm9k-ocd.h>
38
39#include <excite_nandflash.h>
40
41#define EXCITE_NANDFLASH_VERSION "0.1"
42
43/* I/O register offsets */
44#define EXCITE_NANDFLASH_DATA_BYTE 0x00
45#define EXCITE_NANDFLASH_STATUS_BYTE 0x0c
46#define EXCITE_NANDFLASH_ADDR_BYTE 0x10
47#define EXCITE_NANDFLASH_CMD_BYTE 0x14
48
49/* prefix for debug output */
50static const char module_id[] = "excite_nandflash";
51
52/*
53 * partition definition
54 */
55static const struct mtd_partition partition_info[] = {
56 {
57 .name = "eXcite RootFS",
58 .offset = 0,
59 .size = MTDPART_SIZ_FULL
60 }
61};
62
63static inline const struct resource *
64excite_nand_get_resource(struct platform_device *d, unsigned long flags,
65 const char *basename)
66{
67 char buf[80];
68
69 if (snprintf(buf, sizeof buf, "%s_%u", basename, d->id) >= sizeof buf)
70 return NULL;
71 return platform_get_resource_byname(d, flags, buf);
72}
73
74static inline void __iomem *
75excite_nand_map_regs(struct platform_device *d, const char *basename)
76{
77 void *result = NULL;
78 const struct resource *const r =
79 excite_nand_get_resource(d, IORESOURCE_MEM, basename);
80
81 if (r)
82 result = ioremap_nocache(r->start, r->end + 1 - r->start);
83 return result;
84}
85
86/* controller and mtd information */
87struct excite_nand_drvdata {
88 struct mtd_info board_mtd;
89 struct nand_chip board_chip;
90 void __iomem *regs;
91 void __iomem *tgt;
92};
93
94/* Control function */
95static void excite_nand_control(struct mtd_info *mtd, int cmd,
96 unsigned int ctrl)
97{
98 struct excite_nand_drvdata * const d =
99 container_of(mtd, struct excite_nand_drvdata, board_mtd);
100
101 switch (ctrl) {
102 case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
103 d->tgt = d->regs + EXCITE_NANDFLASH_CMD_BYTE;
104 break;
105 case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
106 d->tgt = d->regs + EXCITE_NANDFLASH_ADDR_BYTE;
107 break;
108 case NAND_CTRL_CHANGE | NAND_NCE:
109 d->tgt = d->regs + EXCITE_NANDFLASH_DATA_BYTE;
110 break;
111 }
112
113 if (cmd != NAND_CMD_NONE)
114 __raw_writeb(cmd, d->tgt);
115}
116
117/* Return 0 if flash is busy, 1 if ready */
118static int excite_nand_devready(struct mtd_info *mtd)
119{
120 struct excite_nand_drvdata * const drvdata =
121 container_of(mtd, struct excite_nand_drvdata, board_mtd);
122
123 return __raw_readb(drvdata->regs + EXCITE_NANDFLASH_STATUS_BYTE);
124}
125
126/*
127 * Called by device layer to remove the driver.
128 * The binding to the mtd and all allocated
129 * resources are released.
130 */
131static int __devexit excite_nand_remove(struct platform_device *dev)
132{
133 struct excite_nand_drvdata * const this = platform_get_drvdata(dev);
134
135 platform_set_drvdata(dev, NULL);
136
137 if (unlikely(!this)) {
138 printk(KERN_ERR "%s: called %s without private data!!",
139 module_id, __func__);
140 return -EINVAL;
141 }
142
143 /* first thing we need to do is release our mtd
144 * then go through freeing the resource used
145 */
146 nand_release(&this->board_mtd);
147
148 /* free the common resources */
149 iounmap(this->regs);
150 kfree(this);
151
152 DEBUG(MTD_DEBUG_LEVEL1, "%s: removed\n", module_id);
153 return 0;
154}
155
156/*
157 * Called by device layer when it finds a device matching
158 * one our driver can handle. This code checks to see if
159 * it can allocate all necessary resources then calls the
160 * nand layer to look for devices.
161*/
162static int __init excite_nand_probe(struct platform_device *pdev)
163{
164 struct excite_nand_drvdata *drvdata; /* private driver data */
165 struct nand_chip *board_chip; /* private flash chip data */
166 struct mtd_info *board_mtd; /* mtd info for this board */
167 int scan_res;
168
169 drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL);
170 if (unlikely(!drvdata)) {
171 printk(KERN_ERR "%s: no memory for drvdata\n",
172 module_id);
173 return -ENOMEM;
174 }
175
176 /* bind private data into driver */
177 platform_set_drvdata(pdev, drvdata);
178
179 /* allocate and map the resource */
180 drvdata->regs =
181 excite_nand_map_regs(pdev, EXCITE_NANDFLASH_RESOURCE_REGS);
182
183 if (unlikely(!drvdata->regs)) {
184 printk(KERN_ERR "%s: cannot reserve register region\n",
185 module_id);
186 kfree(drvdata);
187 return -ENXIO;
188 }
189
190 drvdata->tgt = drvdata->regs + EXCITE_NANDFLASH_DATA_BYTE;
191
192 /* initialise our chip */
193 board_chip = &drvdata->board_chip;
194 board_chip->IO_ADDR_R = board_chip->IO_ADDR_W =
195 drvdata->regs + EXCITE_NANDFLASH_DATA_BYTE;
196 board_chip->cmd_ctrl = excite_nand_control;
197 board_chip->dev_ready = excite_nand_devready;
198 board_chip->chip_delay = 25;
199 board_chip->ecc.mode = NAND_ECC_SOFT;
200
201 /* link chip to mtd */
202 board_mtd = &drvdata->board_mtd;
203 board_mtd->priv = board_chip;
204
205 DEBUG(MTD_DEBUG_LEVEL2, "%s: device scan\n", module_id);
206 scan_res = nand_scan(&drvdata->board_mtd, 1);
207
208 if (likely(!scan_res)) {
209 DEBUG(MTD_DEBUG_LEVEL2, "%s: register partitions\n", module_id);
210 add_mtd_partitions(&drvdata->board_mtd, partition_info,
211 ARRAY_SIZE(partition_info));
212 } else {
213 iounmap(drvdata->regs);
214 kfree(drvdata);
215 printk(KERN_ERR "%s: device scan failed\n", module_id);
216 return -EIO;
217 }
218 return 0;
219}
220
221static struct platform_driver excite_nand_driver = {
222 .driver = {
223 .name = "excite_nand",
224 .owner = THIS_MODULE,
225 },
226 .probe = excite_nand_probe,
227 .remove = __devexit_p(excite_nand_remove)
228};
229
230static int __init excite_nand_init(void)
231{
232 pr_info("Basler eXcite nand flash driver Version "
233 EXCITE_NANDFLASH_VERSION "\n");
234 return platform_driver_register(&excite_nand_driver);
235}
236
237static void __exit excite_nand_exit(void)
238{
239 platform_driver_unregister(&excite_nand_driver);
240}
241
242module_init(excite_nand_init);
243module_exit(excite_nand_exit);
244
245MODULE_AUTHOR("Thomas Koeller <thomas.koeller@baslerweb.com>");
246MODULE_DESCRIPTION("Basler eXcite NAND-Flash driver");
247MODULE_LICENSE("GPL");
248MODULE_VERSION(EXCITE_NANDFLASH_VERSION)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index a5be9ac6405c..e58a65391ad2 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1953,6 +1953,8 @@ config BCM63XX_ENET
1953 1953
1954source "drivers/net/fs_enet/Kconfig" 1954source "drivers/net/fs_enet/Kconfig"
1955 1955
1956source "drivers/net/octeon/Kconfig"
1957
1956endif # NET_ETHERNET 1958endif # NET_ETHERNET
1957 1959
1958# 1960#
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 246323d7f161..ad1346dd9da9 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -285,3 +285,5 @@ obj-$(CONFIG_VIRTIO_NET) += virtio_net.o
285obj-$(CONFIG_SFC) += sfc/ 285obj-$(CONFIG_SFC) += sfc/
286 286
287obj-$(CONFIG_WIMAX) += wimax/ 287obj-$(CONFIG_WIMAX) += wimax/
288
289obj-$(CONFIG_OCTEON_MGMT_ETHERNET) += octeon/
diff --git a/drivers/net/octeon/Kconfig b/drivers/net/octeon/Kconfig
new file mode 100644
index 000000000000..1e56bbf3f5c0
--- /dev/null
+++ b/drivers/net/octeon/Kconfig
@@ -0,0 +1,10 @@
1config OCTEON_MGMT_ETHERNET
2 tristate "Octeon Management port ethernet driver (CN5XXX, CN6XXX)"
3 depends on CPU_CAVIUM_OCTEON
4 select PHYLIB
5 select MDIO_OCTEON
6 default y
7 help
8 This option enables the ethernet driver for the management
9 port on Cavium Networks' Octeon CN57XX, CN56XX, CN55XX,
10 CN54XX, CN52XX, and CN6XXX chips.
diff --git a/drivers/net/octeon/Makefile b/drivers/net/octeon/Makefile
new file mode 100644
index 000000000000..906edecacfd3
--- /dev/null
+++ b/drivers/net/octeon/Makefile
@@ -0,0 +1,2 @@
1
2obj-$(CONFIG_OCTEON_MGMT_ETHERNET) += octeon_mgmt.o
diff --git a/drivers/net/octeon/octeon_mgmt.c b/drivers/net/octeon/octeon_mgmt.c
new file mode 100644
index 000000000000..050538bf155a
--- /dev/null
+++ b/drivers/net/octeon/octeon_mgmt.c
@@ -0,0 +1,1176 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2009 Cavium Networks
7 */
8
9#include <linux/capability.h>
10#include <linux/dma-mapping.h>
11#include <linux/init.h>
12#include <linux/platform_device.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/if_vlan.h>
16#include <linux/phy.h>
17#include <linux/spinlock.h>
18
19#include <asm/octeon/octeon.h>
20#include <asm/octeon/cvmx-mixx-defs.h>
21#include <asm/octeon/cvmx-agl-defs.h>
22
23#define DRV_NAME "octeon_mgmt"
24#define DRV_VERSION "2.0"
25#define DRV_DESCRIPTION \
26 "Cavium Networks Octeon MII (management) port Network Driver"
27
28#define OCTEON_MGMT_NAPI_WEIGHT 16
29
30/*
31 * Ring sizes that are powers of two allow for more efficient modulo
32 * opertions.
33 */
34#define OCTEON_MGMT_RX_RING_SIZE 512
35#define OCTEON_MGMT_TX_RING_SIZE 128
36
37/* Allow 8 bytes for vlan and FCS. */
38#define OCTEON_MGMT_RX_HEADROOM (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN)
39
40union mgmt_port_ring_entry {
41 u64 d64;
42 struct {
43 u64 reserved_62_63:2;
44 /* Length of the buffer/packet in bytes */
45 u64 len:14;
46 /* For TX, signals that the packet should be timestamped */
47 u64 tstamp:1;
48 /* The RX error code */
49 u64 code:7;
50#define RING_ENTRY_CODE_DONE 0xf
51#define RING_ENTRY_CODE_MORE 0x10
52 /* Physical address of the buffer */
53 u64 addr:40;
54 } s;
55};
56
57struct octeon_mgmt {
58 struct net_device *netdev;
59 int port;
60 int irq;
61 u64 *tx_ring;
62 dma_addr_t tx_ring_handle;
63 unsigned int tx_next;
64 unsigned int tx_next_clean;
65 unsigned int tx_current_fill;
66 /* The tx_list lock also protects the ring related variables */
67 struct sk_buff_head tx_list;
68
69 /* RX variables only touched in napi_poll. No locking necessary. */
70 u64 *rx_ring;
71 dma_addr_t rx_ring_handle;
72 unsigned int rx_next;
73 unsigned int rx_next_fill;
74 unsigned int rx_current_fill;
75 struct sk_buff_head rx_list;
76
77 spinlock_t lock;
78 unsigned int last_duplex;
79 unsigned int last_link;
80 struct device *dev;
81 struct napi_struct napi;
82 struct tasklet_struct tx_clean_tasklet;
83 struct phy_device *phydev;
84};
85
86static void octeon_mgmt_set_rx_irq(struct octeon_mgmt *p, int enable)
87{
88 int port = p->port;
89 union cvmx_mixx_intena mix_intena;
90 unsigned long flags;
91
92 spin_lock_irqsave(&p->lock, flags);
93 mix_intena.u64 = cvmx_read_csr(CVMX_MIXX_INTENA(port));
94 mix_intena.s.ithena = enable ? 1 : 0;
95 cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64);
96 spin_unlock_irqrestore(&p->lock, flags);
97}
98
99static void octeon_mgmt_set_tx_irq(struct octeon_mgmt *p, int enable)
100{
101 int port = p->port;
102 union cvmx_mixx_intena mix_intena;
103 unsigned long flags;
104
105 spin_lock_irqsave(&p->lock, flags);
106 mix_intena.u64 = cvmx_read_csr(CVMX_MIXX_INTENA(port));
107 mix_intena.s.othena = enable ? 1 : 0;
108 cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64);
109 spin_unlock_irqrestore(&p->lock, flags);
110}
111
112static inline void octeon_mgmt_enable_rx_irq(struct octeon_mgmt *p)
113{
114 octeon_mgmt_set_rx_irq(p, 1);
115}
116
117static inline void octeon_mgmt_disable_rx_irq(struct octeon_mgmt *p)
118{
119 octeon_mgmt_set_rx_irq(p, 0);
120}
121
122static inline void octeon_mgmt_enable_tx_irq(struct octeon_mgmt *p)
123{
124 octeon_mgmt_set_tx_irq(p, 1);
125}
126
127static inline void octeon_mgmt_disable_tx_irq(struct octeon_mgmt *p)
128{
129 octeon_mgmt_set_tx_irq(p, 0);
130}
131
132static unsigned int ring_max_fill(unsigned int ring_size)
133{
134 return ring_size - 8;
135}
136
137static unsigned int ring_size_to_bytes(unsigned int ring_size)
138{
139 return ring_size * sizeof(union mgmt_port_ring_entry);
140}
141
142static void octeon_mgmt_rx_fill_ring(struct net_device *netdev)
143{
144 struct octeon_mgmt *p = netdev_priv(netdev);
145 int port = p->port;
146
147 while (p->rx_current_fill < ring_max_fill(OCTEON_MGMT_RX_RING_SIZE)) {
148 unsigned int size;
149 union mgmt_port_ring_entry re;
150 struct sk_buff *skb;
151
152 /* CN56XX pass 1 needs 8 bytes of padding. */
153 size = netdev->mtu + OCTEON_MGMT_RX_HEADROOM + 8 + NET_IP_ALIGN;
154
155 skb = netdev_alloc_skb(netdev, size);
156 if (!skb)
157 break;
158 skb_reserve(skb, NET_IP_ALIGN);
159 __skb_queue_tail(&p->rx_list, skb);
160
161 re.d64 = 0;
162 re.s.len = size;
163 re.s.addr = dma_map_single(p->dev, skb->data,
164 size,
165 DMA_FROM_DEVICE);
166
167 /* Put it in the ring. */
168 p->rx_ring[p->rx_next_fill] = re.d64;
169 dma_sync_single_for_device(p->dev, p->rx_ring_handle,
170 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
171 DMA_BIDIRECTIONAL);
172 p->rx_next_fill =
173 (p->rx_next_fill + 1) % OCTEON_MGMT_RX_RING_SIZE;
174 p->rx_current_fill++;
175 /* Ring the bell. */
176 cvmx_write_csr(CVMX_MIXX_IRING2(port), 1);
177 }
178}
179
180static void octeon_mgmt_clean_tx_buffers(struct octeon_mgmt *p)
181{
182 int port = p->port;
183 union cvmx_mixx_orcnt mix_orcnt;
184 union mgmt_port_ring_entry re;
185 struct sk_buff *skb;
186 int cleaned = 0;
187 unsigned long flags;
188
189 mix_orcnt.u64 = cvmx_read_csr(CVMX_MIXX_ORCNT(port));
190 while (mix_orcnt.s.orcnt) {
191 dma_sync_single_for_cpu(p->dev, p->tx_ring_handle,
192 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
193 DMA_BIDIRECTIONAL);
194
195 spin_lock_irqsave(&p->tx_list.lock, flags);
196
197 re.d64 = p->tx_ring[p->tx_next_clean];
198 p->tx_next_clean =
199 (p->tx_next_clean + 1) % OCTEON_MGMT_TX_RING_SIZE;
200 skb = __skb_dequeue(&p->tx_list);
201
202 mix_orcnt.u64 = 0;
203 mix_orcnt.s.orcnt = 1;
204
205 /* Acknowledge to hardware that we have the buffer. */
206 cvmx_write_csr(CVMX_MIXX_ORCNT(port), mix_orcnt.u64);
207 p->tx_current_fill--;
208
209 spin_unlock_irqrestore(&p->tx_list.lock, flags);
210
211 dma_unmap_single(p->dev, re.s.addr, re.s.len,
212 DMA_TO_DEVICE);
213 dev_kfree_skb_any(skb);
214 cleaned++;
215
216 mix_orcnt.u64 = cvmx_read_csr(CVMX_MIXX_ORCNT(port));
217 }
218
219 if (cleaned && netif_queue_stopped(p->netdev))
220 netif_wake_queue(p->netdev);
221}
222
223static void octeon_mgmt_clean_tx_tasklet(unsigned long arg)
224{
225 struct octeon_mgmt *p = (struct octeon_mgmt *)arg;
226 octeon_mgmt_clean_tx_buffers(p);
227 octeon_mgmt_enable_tx_irq(p);
228}
229
230static void octeon_mgmt_update_rx_stats(struct net_device *netdev)
231{
232 struct octeon_mgmt *p = netdev_priv(netdev);
233 int port = p->port;
234 unsigned long flags;
235 u64 drop, bad;
236
237 /* These reads also clear the count registers. */
238 drop = cvmx_read_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(port));
239 bad = cvmx_read_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(port));
240
241 if (drop || bad) {
242 /* Do an atomic update. */
243 spin_lock_irqsave(&p->lock, flags);
244 netdev->stats.rx_errors += bad;
245 netdev->stats.rx_dropped += drop;
246 spin_unlock_irqrestore(&p->lock, flags);
247 }
248}
249
250static void octeon_mgmt_update_tx_stats(struct net_device *netdev)
251{
252 struct octeon_mgmt *p = netdev_priv(netdev);
253 int port = p->port;
254 unsigned long flags;
255
256 union cvmx_agl_gmx_txx_stat0 s0;
257 union cvmx_agl_gmx_txx_stat1 s1;
258
259 /* These reads also clear the count registers. */
260 s0.u64 = cvmx_read_csr(CVMX_AGL_GMX_TXX_STAT0(port));
261 s1.u64 = cvmx_read_csr(CVMX_AGL_GMX_TXX_STAT1(port));
262
263 if (s0.s.xsdef || s0.s.xscol || s1.s.scol || s1.s.mcol) {
264 /* Do an atomic update. */
265 spin_lock_irqsave(&p->lock, flags);
266 netdev->stats.tx_errors += s0.s.xsdef + s0.s.xscol;
267 netdev->stats.collisions += s1.s.scol + s1.s.mcol;
268 spin_unlock_irqrestore(&p->lock, flags);
269 }
270}
271
272/*
273 * Dequeue a receive skb and its corresponding ring entry. The ring
274 * entry is returned, *pskb is updated to point to the skb.
275 */
276static u64 octeon_mgmt_dequeue_rx_buffer(struct octeon_mgmt *p,
277 struct sk_buff **pskb)
278{
279 union mgmt_port_ring_entry re;
280
281 dma_sync_single_for_cpu(p->dev, p->rx_ring_handle,
282 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
283 DMA_BIDIRECTIONAL);
284
285 re.d64 = p->rx_ring[p->rx_next];
286 p->rx_next = (p->rx_next + 1) % OCTEON_MGMT_RX_RING_SIZE;
287 p->rx_current_fill--;
288 *pskb = __skb_dequeue(&p->rx_list);
289
290 dma_unmap_single(p->dev, re.s.addr,
291 ETH_FRAME_LEN + OCTEON_MGMT_RX_HEADROOM,
292 DMA_FROM_DEVICE);
293
294 return re.d64;
295}
296
297
298static int octeon_mgmt_receive_one(struct octeon_mgmt *p)
299{
300 int port = p->port;
301 struct net_device *netdev = p->netdev;
302 union cvmx_mixx_ircnt mix_ircnt;
303 union mgmt_port_ring_entry re;
304 struct sk_buff *skb;
305 struct sk_buff *skb2;
306 struct sk_buff *skb_new;
307 union mgmt_port_ring_entry re2;
308 int rc = 1;
309
310
311 re.d64 = octeon_mgmt_dequeue_rx_buffer(p, &skb);
312 if (likely(re.s.code == RING_ENTRY_CODE_DONE)) {
313 /* A good packet, send it up. */
314 skb_put(skb, re.s.len);
315good:
316 skb->protocol = eth_type_trans(skb, netdev);
317 netdev->stats.rx_packets++;
318 netdev->stats.rx_bytes += skb->len;
319 netdev->last_rx = jiffies;
320 netif_receive_skb(skb);
321 rc = 0;
322 } else if (re.s.code == RING_ENTRY_CODE_MORE) {
323 /*
324 * Packet split across skbs. This can happen if we
325 * increase the MTU. Buffers that are already in the
326 * rx ring can then end up being too small. As the rx
327 * ring is refilled, buffers sized for the new MTU
328 * will be used and we should go back to the normal
329 * non-split case.
330 */
331 skb_put(skb, re.s.len);
332 do {
333 re2.d64 = octeon_mgmt_dequeue_rx_buffer(p, &skb2);
334 if (re2.s.code != RING_ENTRY_CODE_MORE
335 && re2.s.code != RING_ENTRY_CODE_DONE)
336 goto split_error;
337 skb_put(skb2, re2.s.len);
338 skb_new = skb_copy_expand(skb, 0, skb2->len,
339 GFP_ATOMIC);
340 if (!skb_new)
341 goto split_error;
342 if (skb_copy_bits(skb2, 0, skb_tail_pointer(skb_new),
343 skb2->len))
344 goto split_error;
345 skb_put(skb_new, skb2->len);
346 dev_kfree_skb_any(skb);
347 dev_kfree_skb_any(skb2);
348 skb = skb_new;
349 } while (re2.s.code == RING_ENTRY_CODE_MORE);
350 goto good;
351 } else {
352 /* Some other error, discard it. */
353 dev_kfree_skb_any(skb);
354 /*
355 * Error statistics are accumulated in
356 * octeon_mgmt_update_rx_stats.
357 */
358 }
359 goto done;
360split_error:
361 /* Discard the whole mess. */
362 dev_kfree_skb_any(skb);
363 dev_kfree_skb_any(skb2);
364 while (re2.s.code == RING_ENTRY_CODE_MORE) {
365 re2.d64 = octeon_mgmt_dequeue_rx_buffer(p, &skb2);
366 dev_kfree_skb_any(skb2);
367 }
368 netdev->stats.rx_errors++;
369
370done:
371 /* Tell the hardware we processed a packet. */
372 mix_ircnt.u64 = 0;
373 mix_ircnt.s.ircnt = 1;
374 cvmx_write_csr(CVMX_MIXX_IRCNT(port), mix_ircnt.u64);
375 return rc;
376
377}
378
379static int octeon_mgmt_receive_packets(struct octeon_mgmt *p, int budget)
380{
381 int port = p->port;
382 unsigned int work_done = 0;
383 union cvmx_mixx_ircnt mix_ircnt;
384 int rc;
385
386
387 mix_ircnt.u64 = cvmx_read_csr(CVMX_MIXX_IRCNT(port));
388 while (work_done < budget && mix_ircnt.s.ircnt) {
389
390 rc = octeon_mgmt_receive_one(p);
391 if (!rc)
392 work_done++;
393
394 /* Check for more packets. */
395 mix_ircnt.u64 = cvmx_read_csr(CVMX_MIXX_IRCNT(port));
396 }
397
398 octeon_mgmt_rx_fill_ring(p->netdev);
399
400 return work_done;
401}
402
403static int octeon_mgmt_napi_poll(struct napi_struct *napi, int budget)
404{
405 struct octeon_mgmt *p = container_of(napi, struct octeon_mgmt, napi);
406 struct net_device *netdev = p->netdev;
407 unsigned int work_done = 0;
408
409 work_done = octeon_mgmt_receive_packets(p, budget);
410
411 if (work_done < budget) {
412 /* We stopped because no more packets were available. */
413 napi_complete(napi);
414 octeon_mgmt_enable_rx_irq(p);
415 }
416 octeon_mgmt_update_rx_stats(netdev);
417
418 return work_done;
419}
420
421/* Reset the hardware to clean state. */
422static void octeon_mgmt_reset_hw(struct octeon_mgmt *p)
423{
424 union cvmx_mixx_ctl mix_ctl;
425 union cvmx_mixx_bist mix_bist;
426 union cvmx_agl_gmx_bist agl_gmx_bist;
427
428 mix_ctl.u64 = 0;
429 cvmx_write_csr(CVMX_MIXX_CTL(p->port), mix_ctl.u64);
430 do {
431 mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(p->port));
432 } while (mix_ctl.s.busy);
433 mix_ctl.s.reset = 1;
434 cvmx_write_csr(CVMX_MIXX_CTL(p->port), mix_ctl.u64);
435 cvmx_read_csr(CVMX_MIXX_CTL(p->port));
436 cvmx_wait(64);
437
438 mix_bist.u64 = cvmx_read_csr(CVMX_MIXX_BIST(p->port));
439 if (mix_bist.u64)
440 dev_warn(p->dev, "MIX failed BIST (0x%016llx)\n",
441 (unsigned long long)mix_bist.u64);
442
443 agl_gmx_bist.u64 = cvmx_read_csr(CVMX_AGL_GMX_BIST);
444 if (agl_gmx_bist.u64)
445 dev_warn(p->dev, "AGL failed BIST (0x%016llx)\n",
446 (unsigned long long)agl_gmx_bist.u64);
447}
448
449struct octeon_mgmt_cam_state {
450 u64 cam[6];
451 u64 cam_mask;
452 int cam_index;
453};
454
455static void octeon_mgmt_cam_state_add(struct octeon_mgmt_cam_state *cs,
456 unsigned char *addr)
457{
458 int i;
459
460 for (i = 0; i < 6; i++)
461 cs->cam[i] |= (u64)addr[i] << (8 * (cs->cam_index));
462 cs->cam_mask |= (1ULL << cs->cam_index);
463 cs->cam_index++;
464}
465
466static void octeon_mgmt_set_rx_filtering(struct net_device *netdev)
467{
468 struct octeon_mgmt *p = netdev_priv(netdev);
469 int port = p->port;
470 int i;
471 union cvmx_agl_gmx_rxx_adr_ctl adr_ctl;
472 union cvmx_agl_gmx_prtx_cfg agl_gmx_prtx;
473 unsigned long flags;
474 unsigned int prev_packet_enable;
475 unsigned int cam_mode = 1; /* 1 - Accept on CAM match */
476 unsigned int multicast_mode = 1; /* 1 - Reject all multicast. */
477 struct octeon_mgmt_cam_state cam_state;
478 struct dev_addr_list *list;
479 struct list_head *pos;
480 int available_cam_entries;
481
482 memset(&cam_state, 0, sizeof(cam_state));
483
484 if ((netdev->flags & IFF_PROMISC) || netdev->dev_addrs.count > 7) {
485 cam_mode = 0;
486 available_cam_entries = 8;
487 } else {
488 /*
489 * One CAM entry for the primary address, leaves seven
490 * for the secondary addresses.
491 */
492 available_cam_entries = 7 - netdev->dev_addrs.count;
493 }
494
495 if (netdev->flags & IFF_MULTICAST) {
496 if (cam_mode == 0 || (netdev->flags & IFF_ALLMULTI)
497 || netdev->mc_count > available_cam_entries)
498 multicast_mode = 2; /* 1 - Accept all multicast. */
499 else
500 multicast_mode = 0; /* 0 - Use CAM. */
501 }
502
503 if (cam_mode == 1) {
504 /* Add primary address. */
505 octeon_mgmt_cam_state_add(&cam_state, netdev->dev_addr);
506 list_for_each(pos, &netdev->dev_addrs.list) {
507 struct netdev_hw_addr *hw_addr;
508 hw_addr = list_entry(pos, struct netdev_hw_addr, list);
509 octeon_mgmt_cam_state_add(&cam_state, hw_addr->addr);
510 list = list->next;
511 }
512 }
513 if (multicast_mode == 0) {
514 i = netdev->mc_count;
515 list = netdev->mc_list;
516 while (i--) {
517 octeon_mgmt_cam_state_add(&cam_state, list->da_addr);
518 list = list->next;
519 }
520 }
521
522
523 spin_lock_irqsave(&p->lock, flags);
524
525 /* Disable packet I/O. */
526 agl_gmx_prtx.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
527 prev_packet_enable = agl_gmx_prtx.s.en;
528 agl_gmx_prtx.s.en = 0;
529 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64);
530
531
532 adr_ctl.u64 = 0;
533 adr_ctl.s.cam_mode = cam_mode;
534 adr_ctl.s.mcst = multicast_mode;
535 adr_ctl.s.bcst = 1; /* Allow broadcast */
536
537 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CTL(port), adr_ctl.u64);
538
539 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM0(port), cam_state.cam[0]);
540 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM1(port), cam_state.cam[1]);
541 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM2(port), cam_state.cam[2]);
542 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM3(port), cam_state.cam[3]);
543 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM4(port), cam_state.cam[4]);
544 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM5(port), cam_state.cam[5]);
545 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM_EN(port), cam_state.cam_mask);
546
547 /* Restore packet I/O. */
548 agl_gmx_prtx.s.en = prev_packet_enable;
549 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64);
550
551 spin_unlock_irqrestore(&p->lock, flags);
552}
553
554static int octeon_mgmt_set_mac_address(struct net_device *netdev, void *addr)
555{
556 struct sockaddr *sa = addr;
557
558 if (!is_valid_ether_addr(sa->sa_data))
559 return -EADDRNOTAVAIL;
560
561 memcpy(netdev->dev_addr, sa->sa_data, ETH_ALEN);
562
563 octeon_mgmt_set_rx_filtering(netdev);
564
565 return 0;
566}
567
568static int octeon_mgmt_change_mtu(struct net_device *netdev, int new_mtu)
569{
570 struct octeon_mgmt *p = netdev_priv(netdev);
571 int port = p->port;
572 int size_without_fcs = new_mtu + OCTEON_MGMT_RX_HEADROOM;
573
574 /*
575 * Limit the MTU to make sure the ethernet packets are between
576 * 64 bytes and 16383 bytes.
577 */
578 if (size_without_fcs < 64 || size_without_fcs > 16383) {
579 dev_warn(p->dev, "MTU must be between %d and %d.\n",
580 64 - OCTEON_MGMT_RX_HEADROOM,
581 16383 - OCTEON_MGMT_RX_HEADROOM);
582 return -EINVAL;
583 }
584
585 netdev->mtu = new_mtu;
586
587 cvmx_write_csr(CVMX_AGL_GMX_RXX_FRM_MAX(port), size_without_fcs);
588 cvmx_write_csr(CVMX_AGL_GMX_RXX_JABBER(port),
589 (size_without_fcs + 7) & 0xfff8);
590
591 return 0;
592}
593
594static irqreturn_t octeon_mgmt_interrupt(int cpl, void *dev_id)
595{
596 struct net_device *netdev = dev_id;
597 struct octeon_mgmt *p = netdev_priv(netdev);
598 int port = p->port;
599 union cvmx_mixx_isr mixx_isr;
600
601 mixx_isr.u64 = cvmx_read_csr(CVMX_MIXX_ISR(port));
602
603 /* Clear any pending interrupts */
604 cvmx_write_csr(CVMX_MIXX_ISR(port),
605 cvmx_read_csr(CVMX_MIXX_ISR(port)));
606 cvmx_read_csr(CVMX_MIXX_ISR(port));
607
608 if (mixx_isr.s.irthresh) {
609 octeon_mgmt_disable_rx_irq(p);
610 napi_schedule(&p->napi);
611 }
612 if (mixx_isr.s.orthresh) {
613 octeon_mgmt_disable_tx_irq(p);
614 tasklet_schedule(&p->tx_clean_tasklet);
615 }
616
617 return IRQ_HANDLED;
618}
619
620static int octeon_mgmt_ioctl(struct net_device *netdev,
621 struct ifreq *rq, int cmd)
622{
623 struct octeon_mgmt *p = netdev_priv(netdev);
624
625 if (!netif_running(netdev))
626 return -EINVAL;
627
628 if (!p->phydev)
629 return -EINVAL;
630
631 return phy_mii_ioctl(p->phydev, if_mii(rq), cmd);
632}
633
634static void octeon_mgmt_adjust_link(struct net_device *netdev)
635{
636 struct octeon_mgmt *p = netdev_priv(netdev);
637 int port = p->port;
638 union cvmx_agl_gmx_prtx_cfg prtx_cfg;
639 unsigned long flags;
640 int link_changed = 0;
641
642 spin_lock_irqsave(&p->lock, flags);
643 if (p->phydev->link) {
644 if (!p->last_link)
645 link_changed = 1;
646 if (p->last_duplex != p->phydev->duplex) {
647 p->last_duplex = p->phydev->duplex;
648 prtx_cfg.u64 =
649 cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
650 prtx_cfg.s.duplex = p->phydev->duplex;
651 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port),
652 prtx_cfg.u64);
653 }
654 } else {
655 if (p->last_link)
656 link_changed = -1;
657 }
658 p->last_link = p->phydev->link;
659 spin_unlock_irqrestore(&p->lock, flags);
660
661 if (link_changed != 0) {
662 if (link_changed > 0) {
663 netif_carrier_on(netdev);
664 pr_info("%s: Link is up - %d/%s\n", netdev->name,
665 p->phydev->speed,
666 DUPLEX_FULL == p->phydev->duplex ?
667 "Full" : "Half");
668 } else {
669 netif_carrier_off(netdev);
670 pr_info("%s: Link is down\n", netdev->name);
671 }
672 }
673}
674
675static int octeon_mgmt_init_phy(struct net_device *netdev)
676{
677 struct octeon_mgmt *p = netdev_priv(netdev);
678 char phy_id[20];
679
680 if (octeon_is_simulation()) {
681 /* No PHYs in the simulator. */
682 netif_carrier_on(netdev);
683 return 0;
684 }
685
686 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, "0", p->port);
687
688 p->phydev = phy_connect(netdev, phy_id, octeon_mgmt_adjust_link, 0,
689 PHY_INTERFACE_MODE_MII);
690
691 if (IS_ERR(p->phydev)) {
692 p->phydev = NULL;
693 return -1;
694 }
695
696 phy_start_aneg(p->phydev);
697
698 return 0;
699}
700
701static int octeon_mgmt_open(struct net_device *netdev)
702{
703 struct octeon_mgmt *p = netdev_priv(netdev);
704 int port = p->port;
705 union cvmx_mixx_ctl mix_ctl;
706 union cvmx_agl_gmx_inf_mode agl_gmx_inf_mode;
707 union cvmx_mixx_oring1 oring1;
708 union cvmx_mixx_iring1 iring1;
709 union cvmx_agl_gmx_prtx_cfg prtx_cfg;
710 union cvmx_agl_gmx_rxx_frm_ctl rxx_frm_ctl;
711 union cvmx_mixx_irhwm mix_irhwm;
712 union cvmx_mixx_orhwm mix_orhwm;
713 union cvmx_mixx_intena mix_intena;
714 struct sockaddr sa;
715
716 /* Allocate ring buffers. */
717 p->tx_ring = kzalloc(ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
718 GFP_KERNEL);
719 if (!p->tx_ring)
720 return -ENOMEM;
721 p->tx_ring_handle =
722 dma_map_single(p->dev, p->tx_ring,
723 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
724 DMA_BIDIRECTIONAL);
725 p->tx_next = 0;
726 p->tx_next_clean = 0;
727 p->tx_current_fill = 0;
728
729
730 p->rx_ring = kzalloc(ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
731 GFP_KERNEL);
732 if (!p->rx_ring)
733 goto err_nomem;
734 p->rx_ring_handle =
735 dma_map_single(p->dev, p->rx_ring,
736 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
737 DMA_BIDIRECTIONAL);
738
739 p->rx_next = 0;
740 p->rx_next_fill = 0;
741 p->rx_current_fill = 0;
742
743 octeon_mgmt_reset_hw(p);
744
745 mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port));
746
747 /* Bring it out of reset if needed. */
748 if (mix_ctl.s.reset) {
749 mix_ctl.s.reset = 0;
750 cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64);
751 do {
752 mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port));
753 } while (mix_ctl.s.reset);
754 }
755
756 agl_gmx_inf_mode.u64 = 0;
757 agl_gmx_inf_mode.s.en = 1;
758 cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64);
759
760 oring1.u64 = 0;
761 oring1.s.obase = p->tx_ring_handle >> 3;
762 oring1.s.osize = OCTEON_MGMT_TX_RING_SIZE;
763 cvmx_write_csr(CVMX_MIXX_ORING1(port), oring1.u64);
764
765 iring1.u64 = 0;
766 iring1.s.ibase = p->rx_ring_handle >> 3;
767 iring1.s.isize = OCTEON_MGMT_RX_RING_SIZE;
768 cvmx_write_csr(CVMX_MIXX_IRING1(port), iring1.u64);
769
770 /* Disable packet I/O. */
771 prtx_cfg.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
772 prtx_cfg.s.en = 0;
773 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), prtx_cfg.u64);
774
775 memcpy(sa.sa_data, netdev->dev_addr, ETH_ALEN);
776 octeon_mgmt_set_mac_address(netdev, &sa);
777
778 octeon_mgmt_change_mtu(netdev, netdev->mtu);
779
780 /*
781 * Enable the port HW. Packets are not allowed until
782 * cvmx_mgmt_port_enable() is called.
783 */
784 mix_ctl.u64 = 0;
785 mix_ctl.s.crc_strip = 1; /* Strip the ending CRC */
786 mix_ctl.s.en = 1; /* Enable the port */
787 mix_ctl.s.nbtarb = 0; /* Arbitration mode */
788 /* MII CB-request FIFO programmable high watermark */
789 mix_ctl.s.mrq_hwm = 1;
790 cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64);
791
792 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
793 || OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
794 /*
795 * Force compensation values, as they are not
796 * determined properly by HW
797 */
798 union cvmx_agl_gmx_drv_ctl drv_ctl;
799
800 drv_ctl.u64 = cvmx_read_csr(CVMX_AGL_GMX_DRV_CTL);
801 if (port) {
802 drv_ctl.s.byp_en1 = 1;
803 drv_ctl.s.nctl1 = 6;
804 drv_ctl.s.pctl1 = 6;
805 } else {
806 drv_ctl.s.byp_en = 1;
807 drv_ctl.s.nctl = 6;
808 drv_ctl.s.pctl = 6;
809 }
810 cvmx_write_csr(CVMX_AGL_GMX_DRV_CTL, drv_ctl.u64);
811 }
812
813 octeon_mgmt_rx_fill_ring(netdev);
814
815 /* Clear statistics. */
816 /* Clear on read. */
817 cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_CTL(port), 1);
818 cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(port), 0);
819 cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(port), 0);
820
821 cvmx_write_csr(CVMX_AGL_GMX_TXX_STATS_CTL(port), 1);
822 cvmx_write_csr(CVMX_AGL_GMX_TXX_STAT0(port), 0);
823 cvmx_write_csr(CVMX_AGL_GMX_TXX_STAT1(port), 0);
824
825 /* Clear any pending interrupts */
826 cvmx_write_csr(CVMX_MIXX_ISR(port), cvmx_read_csr(CVMX_MIXX_ISR(port)));
827
828 if (request_irq(p->irq, octeon_mgmt_interrupt, 0, netdev->name,
829 netdev)) {
830 dev_err(p->dev, "request_irq(%d) failed.\n", p->irq);
831 goto err_noirq;
832 }
833
834 /* Interrupt every single RX packet */
835 mix_irhwm.u64 = 0;
836 mix_irhwm.s.irhwm = 0;
837 cvmx_write_csr(CVMX_MIXX_IRHWM(port), mix_irhwm.u64);
838
839 /* Interrupt when we have 5 or more packets to clean. */
840 mix_orhwm.u64 = 0;
841 mix_orhwm.s.orhwm = 5;
842 cvmx_write_csr(CVMX_MIXX_ORHWM(port), mix_orhwm.u64);
843
844 /* Enable receive and transmit interrupts */
845 mix_intena.u64 = 0;
846 mix_intena.s.ithena = 1;
847 mix_intena.s.othena = 1;
848 cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64);
849
850
851 /* Enable packet I/O. */
852
853 rxx_frm_ctl.u64 = 0;
854 rxx_frm_ctl.s.pre_align = 1;
855 /*
856 * When set, disables the length check for non-min sized pkts
857 * with padding in the client data.
858 */
859 rxx_frm_ctl.s.pad_len = 1;
860 /* When set, disables the length check for VLAN pkts */
861 rxx_frm_ctl.s.vlan_len = 1;
862 /* When set, PREAMBLE checking is less strict */
863 rxx_frm_ctl.s.pre_free = 1;
864 /* Control Pause Frames can match station SMAC */
865 rxx_frm_ctl.s.ctl_smac = 0;
866 /* Control Pause Frames can match globally assign Multicast address */
867 rxx_frm_ctl.s.ctl_mcst = 1;
868 /* Forward pause information to TX block */
869 rxx_frm_ctl.s.ctl_bck = 1;
870 /* Drop Control Pause Frames */
871 rxx_frm_ctl.s.ctl_drp = 1;
872 /* Strip off the preamble */
873 rxx_frm_ctl.s.pre_strp = 1;
874 /*
875 * This port is configured to send PREAMBLE+SFD to begin every
876 * frame. GMX checks that the PREAMBLE is sent correctly.
877 */
878 rxx_frm_ctl.s.pre_chk = 1;
879 cvmx_write_csr(CVMX_AGL_GMX_RXX_FRM_CTL(port), rxx_frm_ctl.u64);
880
881 /* Enable the AGL block */
882 agl_gmx_inf_mode.u64 = 0;
883 agl_gmx_inf_mode.s.en = 1;
884 cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64);
885
886 /* Configure the port duplex and enables */
887 prtx_cfg.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
888 prtx_cfg.s.tx_en = 1;
889 prtx_cfg.s.rx_en = 1;
890 prtx_cfg.s.en = 1;
891 p->last_duplex = 1;
892 prtx_cfg.s.duplex = p->last_duplex;
893 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), prtx_cfg.u64);
894
895 p->last_link = 0;
896 netif_carrier_off(netdev);
897
898 if (octeon_mgmt_init_phy(netdev)) {
899 dev_err(p->dev, "Cannot initialize PHY.\n");
900 goto err_noirq;
901 }
902
903 netif_wake_queue(netdev);
904 napi_enable(&p->napi);
905
906 return 0;
907err_noirq:
908 octeon_mgmt_reset_hw(p);
909 dma_unmap_single(p->dev, p->rx_ring_handle,
910 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
911 DMA_BIDIRECTIONAL);
912 kfree(p->rx_ring);
913err_nomem:
914 dma_unmap_single(p->dev, p->tx_ring_handle,
915 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
916 DMA_BIDIRECTIONAL);
917 kfree(p->tx_ring);
918 return -ENOMEM;
919}
920
921static int octeon_mgmt_stop(struct net_device *netdev)
922{
923 struct octeon_mgmt *p = netdev_priv(netdev);
924
925 napi_disable(&p->napi);
926 netif_stop_queue(netdev);
927
928 if (p->phydev)
929 phy_disconnect(p->phydev);
930
931 netif_carrier_off(netdev);
932
933 octeon_mgmt_reset_hw(p);
934
935
936 free_irq(p->irq, netdev);
937
938 /* dma_unmap is a nop on Octeon, so just free everything. */
939 skb_queue_purge(&p->tx_list);
940 skb_queue_purge(&p->rx_list);
941
942 dma_unmap_single(p->dev, p->rx_ring_handle,
943 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
944 DMA_BIDIRECTIONAL);
945 kfree(p->rx_ring);
946
947 dma_unmap_single(p->dev, p->tx_ring_handle,
948 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
949 DMA_BIDIRECTIONAL);
950 kfree(p->tx_ring);
951
952
953 return 0;
954}
955
956static int octeon_mgmt_xmit(struct sk_buff *skb, struct net_device *netdev)
957{
958 struct octeon_mgmt *p = netdev_priv(netdev);
959 int port = p->port;
960 union mgmt_port_ring_entry re;
961 unsigned long flags;
962
963 re.d64 = 0;
964 re.s.len = skb->len;
965 re.s.addr = dma_map_single(p->dev, skb->data,
966 skb->len,
967 DMA_TO_DEVICE);
968
969 spin_lock_irqsave(&p->tx_list.lock, flags);
970
971 if (unlikely(p->tx_current_fill >=
972 ring_max_fill(OCTEON_MGMT_TX_RING_SIZE))) {
973 spin_unlock_irqrestore(&p->tx_list.lock, flags);
974
975 dma_unmap_single(p->dev, re.s.addr, re.s.len,
976 DMA_TO_DEVICE);
977
978 netif_stop_queue(netdev);
979 return NETDEV_TX_BUSY;
980 }
981
982 __skb_queue_tail(&p->tx_list, skb);
983
984 /* Put it in the ring. */
985 p->tx_ring[p->tx_next] = re.d64;
986 p->tx_next = (p->tx_next + 1) % OCTEON_MGMT_TX_RING_SIZE;
987 p->tx_current_fill++;
988
989 spin_unlock_irqrestore(&p->tx_list.lock, flags);
990
991 dma_sync_single_for_device(p->dev, p->tx_ring_handle,
992 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
993 DMA_BIDIRECTIONAL);
994
995 netdev->stats.tx_packets++;
996 netdev->stats.tx_bytes += skb->len;
997
998 /* Ring the bell. */
999 cvmx_write_csr(CVMX_MIXX_ORING2(port), 1);
1000
1001 netdev->trans_start = jiffies;
1002 octeon_mgmt_clean_tx_buffers(p);
1003 octeon_mgmt_update_tx_stats(netdev);
1004 return NETDEV_TX_OK;
1005}
1006
1007#ifdef CONFIG_NET_POLL_CONTROLLER
1008static void octeon_mgmt_poll_controller(struct net_device *netdev)
1009{
1010 struct octeon_mgmt *p = netdev_priv(netdev);
1011
1012 octeon_mgmt_receive_packets(p, 16);
1013 octeon_mgmt_update_rx_stats(netdev);
1014 return;
1015}
1016#endif
1017
1018static void octeon_mgmt_get_drvinfo(struct net_device *netdev,
1019 struct ethtool_drvinfo *info)
1020{
1021 strncpy(info->driver, DRV_NAME, sizeof(info->driver));
1022 strncpy(info->version, DRV_VERSION, sizeof(info->version));
1023 strncpy(info->fw_version, "N/A", sizeof(info->fw_version));
1024 strncpy(info->bus_info, "N/A", sizeof(info->bus_info));
1025 info->n_stats = 0;
1026 info->testinfo_len = 0;
1027 info->regdump_len = 0;
1028 info->eedump_len = 0;
1029}
1030
1031static int octeon_mgmt_get_settings(struct net_device *netdev,
1032 struct ethtool_cmd *cmd)
1033{
1034 struct octeon_mgmt *p = netdev_priv(netdev);
1035
1036 if (p->phydev)
1037 return phy_ethtool_gset(p->phydev, cmd);
1038
1039 return -EINVAL;
1040}
1041
1042static int octeon_mgmt_set_settings(struct net_device *netdev,
1043 struct ethtool_cmd *cmd)
1044{
1045 struct octeon_mgmt *p = netdev_priv(netdev);
1046
1047 if (!capable(CAP_NET_ADMIN))
1048 return -EPERM;
1049
1050 if (p->phydev)
1051 return phy_ethtool_sset(p->phydev, cmd);
1052
1053 return -EINVAL;
1054}
1055
1056static const struct ethtool_ops octeon_mgmt_ethtool_ops = {
1057 .get_drvinfo = octeon_mgmt_get_drvinfo,
1058 .get_link = ethtool_op_get_link,
1059 .get_settings = octeon_mgmt_get_settings,
1060 .set_settings = octeon_mgmt_set_settings
1061};
1062
1063static const struct net_device_ops octeon_mgmt_ops = {
1064 .ndo_open = octeon_mgmt_open,
1065 .ndo_stop = octeon_mgmt_stop,
1066 .ndo_start_xmit = octeon_mgmt_xmit,
1067 .ndo_set_rx_mode = octeon_mgmt_set_rx_filtering,
1068 .ndo_set_multicast_list = octeon_mgmt_set_rx_filtering,
1069 .ndo_set_mac_address = octeon_mgmt_set_mac_address,
1070 .ndo_do_ioctl = octeon_mgmt_ioctl,
1071 .ndo_change_mtu = octeon_mgmt_change_mtu,
1072#ifdef CONFIG_NET_POLL_CONTROLLER
1073 .ndo_poll_controller = octeon_mgmt_poll_controller,
1074#endif
1075};
1076
1077static int __init octeon_mgmt_probe(struct platform_device *pdev)
1078{
1079 struct resource *res_irq;
1080 struct net_device *netdev;
1081 struct octeon_mgmt *p;
1082 int i;
1083
1084 netdev = alloc_etherdev(sizeof(struct octeon_mgmt));
1085 if (netdev == NULL)
1086 return -ENOMEM;
1087
1088 dev_set_drvdata(&pdev->dev, netdev);
1089 p = netdev_priv(netdev);
1090 netif_napi_add(netdev, &p->napi, octeon_mgmt_napi_poll,
1091 OCTEON_MGMT_NAPI_WEIGHT);
1092
1093 p->netdev = netdev;
1094 p->dev = &pdev->dev;
1095
1096 p->port = pdev->id;
1097 snprintf(netdev->name, IFNAMSIZ, "mgmt%d", p->port);
1098
1099 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1100 if (!res_irq)
1101 goto err;
1102
1103 p->irq = res_irq->start;
1104 spin_lock_init(&p->lock);
1105
1106 skb_queue_head_init(&p->tx_list);
1107 skb_queue_head_init(&p->rx_list);
1108 tasklet_init(&p->tx_clean_tasklet,
1109 octeon_mgmt_clean_tx_tasklet, (unsigned long)p);
1110
1111 netdev->netdev_ops = &octeon_mgmt_ops;
1112 netdev->ethtool_ops = &octeon_mgmt_ethtool_ops;
1113
1114
1115 /* The mgmt ports get the first N MACs. */
1116 for (i = 0; i < 6; i++)
1117 netdev->dev_addr[i] = octeon_bootinfo->mac_addr_base[i];
1118 netdev->dev_addr[5] += p->port;
1119
1120 if (p->port >= octeon_bootinfo->mac_addr_count)
1121 dev_err(&pdev->dev,
1122 "Error %s: Using MAC outside of the assigned range: "
1123 "%02x:%02x:%02x:%02x:%02x:%02x\n", netdev->name,
1124 netdev->dev_addr[0], netdev->dev_addr[1],
1125 netdev->dev_addr[2], netdev->dev_addr[3],
1126 netdev->dev_addr[4], netdev->dev_addr[5]);
1127
1128 if (register_netdev(netdev))
1129 goto err;
1130
1131 dev_info(&pdev->dev, "Version " DRV_VERSION "\n");
1132 return 0;
1133err:
1134 free_netdev(netdev);
1135 return -ENOENT;
1136}
1137
1138static int __exit octeon_mgmt_remove(struct platform_device *pdev)
1139{
1140 struct net_device *netdev = dev_get_drvdata(&pdev->dev);
1141
1142 unregister_netdev(netdev);
1143 free_netdev(netdev);
1144 return 0;
1145}
1146
1147static struct platform_driver octeon_mgmt_driver = {
1148 .driver = {
1149 .name = "octeon_mgmt",
1150 .owner = THIS_MODULE,
1151 },
1152 .probe = octeon_mgmt_probe,
1153 .remove = __exit_p(octeon_mgmt_remove),
1154};
1155
1156extern void octeon_mdiobus_force_mod_depencency(void);
1157
1158static int __init octeon_mgmt_mod_init(void)
1159{
1160 /* Force our mdiobus driver module to be loaded first. */
1161 octeon_mdiobus_force_mod_depencency();
1162 return platform_driver_register(&octeon_mgmt_driver);
1163}
1164
1165static void __exit octeon_mgmt_mod_exit(void)
1166{
1167 platform_driver_unregister(&octeon_mgmt_driver);
1168}
1169
1170module_init(octeon_mgmt_mod_init);
1171module_exit(octeon_mgmt_mod_exit);
1172
1173MODULE_DESCRIPTION(DRV_DESCRIPTION);
1174MODULE_AUTHOR("David Daney");
1175MODULE_LICENSE("GPL");
1176MODULE_VERSION(DRV_VERSION);
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index d5d8e1c5bc91..fc5938ba3d78 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -115,4 +115,15 @@ config MDIO_GPIO
115 To compile this driver as a module, choose M here: the module 115 To compile this driver as a module, choose M here: the module
116 will be called mdio-gpio. 116 will be called mdio-gpio.
117 117
118config MDIO_OCTEON
119 tristate "Support for MDIO buses on Octeon SOCs"
120 depends on CPU_CAVIUM_OCTEON
121 default y
122 help
123
124 This module provides a driver for the Octeon MDIO busses.
125 It is required by the Octeon Ethernet device drivers.
126
127 If in doubt, say Y.
128
118endif # PHYLIB 129endif # PHYLIB
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index edfaac48cbd5..1342585af381 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -20,3 +20,4 @@ obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o
20obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o 20obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o
21obj-$(CONFIG_NATIONAL_PHY) += national.o 21obj-$(CONFIG_NATIONAL_PHY) += national.o
22obj-$(CONFIG_STE10XP) += ste10Xp.o 22obj-$(CONFIG_STE10XP) += ste10Xp.o
23obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
diff --git a/drivers/net/phy/mdio-octeon.c b/drivers/net/phy/mdio-octeon.c
new file mode 100644
index 000000000000..61a4461cbda5
--- /dev/null
+++ b/drivers/net/phy/mdio-octeon.c
@@ -0,0 +1,180 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2009 Cavium Networks
7 */
8
9#include <linux/init.h>
10#include <linux/module.h>
11#include <linux/platform_device.h>
12#include <linux/phy.h>
13
14#include <asm/octeon/octeon.h>
15#include <asm/octeon/cvmx-smix-defs.h>
16
17#define DRV_VERSION "1.0"
18#define DRV_DESCRIPTION "Cavium Networks Octeon SMI/MDIO driver"
19
20struct octeon_mdiobus {
21 struct mii_bus *mii_bus;
22 int unit;
23 int phy_irq[PHY_MAX_ADDR];
24};
25
26static int octeon_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum)
27{
28 struct octeon_mdiobus *p = bus->priv;
29 union cvmx_smix_cmd smi_cmd;
30 union cvmx_smix_rd_dat smi_rd;
31 int timeout = 1000;
32
33 smi_cmd.u64 = 0;
34 smi_cmd.s.phy_op = 1; /* MDIO_CLAUSE_22_READ */
35 smi_cmd.s.phy_adr = phy_id;
36 smi_cmd.s.reg_adr = regnum;
37 cvmx_write_csr(CVMX_SMIX_CMD(p->unit), smi_cmd.u64);
38
39 do {
40 /*
41 * Wait 1000 clocks so we don't saturate the RSL bus
42 * doing reads.
43 */
44 cvmx_wait(1000);
45 smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(p->unit));
46 } while (smi_rd.s.pending && --timeout);
47
48 if (smi_rd.s.val)
49 return smi_rd.s.dat;
50 else
51 return -EIO;
52}
53
54static int octeon_mdiobus_write(struct mii_bus *bus, int phy_id,
55 int regnum, u16 val)
56{
57 struct octeon_mdiobus *p = bus->priv;
58 union cvmx_smix_cmd smi_cmd;
59 union cvmx_smix_wr_dat smi_wr;
60 int timeout = 1000;
61
62 smi_wr.u64 = 0;
63 smi_wr.s.dat = val;
64 cvmx_write_csr(CVMX_SMIX_WR_DAT(p->unit), smi_wr.u64);
65
66 smi_cmd.u64 = 0;
67 smi_cmd.s.phy_op = 0; /* MDIO_CLAUSE_22_WRITE */
68 smi_cmd.s.phy_adr = phy_id;
69 smi_cmd.s.reg_adr = regnum;
70 cvmx_write_csr(CVMX_SMIX_CMD(p->unit), smi_cmd.u64);
71
72 do {
73 /*
74 * Wait 1000 clocks so we don't saturate the RSL bus
75 * doing reads.
76 */
77 cvmx_wait(1000);
78 smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(p->unit));
79 } while (smi_wr.s.pending && --timeout);
80
81 if (timeout <= 0)
82 return -EIO;
83
84 return 0;
85}
86
87static int __init octeon_mdiobus_probe(struct platform_device *pdev)
88{
89 struct octeon_mdiobus *bus;
90 int i;
91 int err = -ENOENT;
92
93 bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
94 if (!bus)
95 return -ENOMEM;
96
97 /* The platform_device id is our unit number. */
98 bus->unit = pdev->id;
99
100 bus->mii_bus = mdiobus_alloc();
101
102 if (!bus->mii_bus)
103 goto err;
104
105 /*
106 * Standard Octeon evaluation boards don't support phy
107 * interrupts, we need to poll.
108 */
109 for (i = 0; i < PHY_MAX_ADDR; i++)
110 bus->phy_irq[i] = PHY_POLL;
111
112 bus->mii_bus->priv = bus;
113 bus->mii_bus->irq = bus->phy_irq;
114 bus->mii_bus->name = "mdio-octeon";
115 snprintf(bus->mii_bus->id, MII_BUS_ID_SIZE, "%x", bus->unit);
116 bus->mii_bus->parent = &pdev->dev;
117
118 bus->mii_bus->read = octeon_mdiobus_read;
119 bus->mii_bus->write = octeon_mdiobus_write;
120
121 dev_set_drvdata(&pdev->dev, bus);
122
123 err = mdiobus_register(bus->mii_bus);
124 if (err)
125 goto err_register;
126
127 dev_info(&pdev->dev, "Version " DRV_VERSION "\n");
128
129 return 0;
130err_register:
131 mdiobus_free(bus->mii_bus);
132
133err:
134 devm_kfree(&pdev->dev, bus);
135 return err;
136}
137
138static int __exit octeon_mdiobus_remove(struct platform_device *pdev)
139{
140 struct octeon_mdiobus *bus;
141
142 bus = dev_get_drvdata(&pdev->dev);
143
144 mdiobus_unregister(bus->mii_bus);
145 mdiobus_free(bus->mii_bus);
146 return 0;
147}
148
149static struct platform_driver octeon_mdiobus_driver = {
150 .driver = {
151 .name = "mdio-octeon",
152 .owner = THIS_MODULE,
153 },
154 .probe = octeon_mdiobus_probe,
155 .remove = __exit_p(octeon_mdiobus_remove),
156};
157
158void octeon_mdiobus_force_mod_depencency(void)
159{
160 /* Let ethernet drivers force us to be loaded. */
161}
162EXPORT_SYMBOL(octeon_mdiobus_force_mod_depencency);
163
164static int __init octeon_mdiobus_mod_init(void)
165{
166 return platform_driver_register(&octeon_mdiobus_driver);
167}
168
169static void __exit octeon_mdiobus_mod_exit(void)
170{
171 platform_driver_unregister(&octeon_mdiobus_driver);
172}
173
174module_init(octeon_mdiobus_mod_init);
175module_exit(octeon_mdiobus_mod_exit);
176
177MODULE_DESCRIPTION(DRV_DESCRIPTION);
178MODULE_VERSION(DRV_VERSION);
179MODULE_AUTHOR("David Daney");
180MODULE_LICENSE("GPL");
diff --git a/drivers/rtc/rtc-cmos.c b/drivers/rtc/rtc-cmos.c
index eb154dc57164..c8c12325e69b 100644
--- a/drivers/rtc/rtc-cmos.c
+++ b/drivers/rtc/rtc-cmos.c
@@ -686,7 +686,8 @@ cmos_do_probe(struct device *dev, struct resource *ports, int rtc_irq)
686 */ 686 */
687#if defined(CONFIG_ATARI) 687#if defined(CONFIG_ATARI)
688 address_space = 64; 688 address_space = 64;
689#elif defined(__i386__) || defined(__x86_64__) || defined(__arm__) || defined(__sparc__) 689#elif defined(__i386__) || defined(__x86_64__) || defined(__arm__) \
690 || defined(__sparc__) || defined(__mips__)
690 address_space = 128; 691 address_space = 128;
691#else 692#else
692#warning Assuming 128 bytes of RTC+NVRAM address space, not 64 bytes. 693#warning Assuming 128 bytes of RTC+NVRAM address space, not 64 bytes.
diff --git a/drivers/staging/octeon/Kconfig b/drivers/staging/octeon/Kconfig
index 536e2382de54..638ad6b35891 100644
--- a/drivers/staging/octeon/Kconfig
+++ b/drivers/staging/octeon/Kconfig
@@ -1,7 +1,8 @@
1config OCTEON_ETHERNET 1config OCTEON_ETHERNET
2 tristate "Cavium Networks Octeon Ethernet support" 2 tristate "Cavium Networks Octeon Ethernet support"
3 depends on CPU_CAVIUM_OCTEON 3 depends on CPU_CAVIUM_OCTEON
4 select MII 4 select PHYLIB
5 select MDIO_OCTEON
5 help 6 help
6 This driver supports the builtin ethernet ports on Cavium 7 This driver supports the builtin ethernet ports on Cavium
7 Networks' products in the Octeon family. This driver supports the 8 Networks' products in the Octeon family. This driver supports the
diff --git a/drivers/staging/octeon/ethernet-mdio.c b/drivers/staging/octeon/ethernet-mdio.c
index 31a58e508924..05a5cc0f43ed 100644
--- a/drivers/staging/octeon/ethernet-mdio.c
+++ b/drivers/staging/octeon/ethernet-mdio.c
@@ -26,7 +26,8 @@
26**********************************************************************/ 26**********************************************************************/
27#include <linux/kernel.h> 27#include <linux/kernel.h>
28#include <linux/ethtool.h> 28#include <linux/ethtool.h>
29#include <linux/mii.h> 29#include <linux/phy.h>
30
30#include <net/dst.h> 31#include <net/dst.h>
31 32
32#include <asm/octeon/octeon.h> 33#include <asm/octeon/octeon.h>
@@ -34,86 +35,12 @@
34#include "ethernet-defines.h" 35#include "ethernet-defines.h"
35#include "octeon-ethernet.h" 36#include "octeon-ethernet.h"
36#include "ethernet-mdio.h" 37#include "ethernet-mdio.h"
38#include "ethernet-util.h"
37 39
38#include "cvmx-helper-board.h" 40#include "cvmx-helper-board.h"
39 41
40#include "cvmx-smix-defs.h" 42#include "cvmx-smix-defs.h"
41 43
42DECLARE_MUTEX(mdio_sem);
43
44/**
45 * Perform an MII read. Called by the generic MII routines
46 *
47 * @dev: Device to perform read for
48 * @phy_id: The MII phy id
49 * @location: Register location to read
50 * Returns Result from the read or zero on failure
51 */
52static int cvm_oct_mdio_read(struct net_device *dev, int phy_id, int location)
53{
54 union cvmx_smix_cmd smi_cmd;
55 union cvmx_smix_rd_dat smi_rd;
56
57 smi_cmd.u64 = 0;
58 smi_cmd.s.phy_op = 1;
59 smi_cmd.s.phy_adr = phy_id;
60 smi_cmd.s.reg_adr = location;
61 cvmx_write_csr(CVMX_SMIX_CMD(0), smi_cmd.u64);
62
63 do {
64 if (!in_interrupt())
65 yield();
66 smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(0));
67 } while (smi_rd.s.pending);
68
69 if (smi_rd.s.val)
70 return smi_rd.s.dat;
71 else
72 return 0;
73}
74
75static int cvm_oct_mdio_dummy_read(struct net_device *dev, int phy_id,
76 int location)
77{
78 return 0xffff;
79}
80
81/**
82 * Perform an MII write. Called by the generic MII routines
83 *
84 * @dev: Device to perform write for
85 * @phy_id: The MII phy id
86 * @location: Register location to write
87 * @val: Value to write
88 */
89static void cvm_oct_mdio_write(struct net_device *dev, int phy_id, int location,
90 int val)
91{
92 union cvmx_smix_cmd smi_cmd;
93 union cvmx_smix_wr_dat smi_wr;
94
95 smi_wr.u64 = 0;
96 smi_wr.s.dat = val;
97 cvmx_write_csr(CVMX_SMIX_WR_DAT(0), smi_wr.u64);
98
99 smi_cmd.u64 = 0;
100 smi_cmd.s.phy_op = 0;
101 smi_cmd.s.phy_adr = phy_id;
102 smi_cmd.s.reg_adr = location;
103 cvmx_write_csr(CVMX_SMIX_CMD(0), smi_cmd.u64);
104
105 do {
106 if (!in_interrupt())
107 yield();
108 smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(0));
109 } while (smi_wr.s.pending);
110}
111
112static void cvm_oct_mdio_dummy_write(struct net_device *dev, int phy_id,
113 int location, int val)
114{
115}
116
117static void cvm_oct_get_drvinfo(struct net_device *dev, 44static void cvm_oct_get_drvinfo(struct net_device *dev,
118 struct ethtool_drvinfo *info) 45 struct ethtool_drvinfo *info)
119{ 46{
@@ -125,49 +52,37 @@ static void cvm_oct_get_drvinfo(struct net_device *dev,
125static int cvm_oct_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 52static int cvm_oct_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
126{ 53{
127 struct octeon_ethernet *priv = netdev_priv(dev); 54 struct octeon_ethernet *priv = netdev_priv(dev);
128 int ret;
129 55
130 down(&mdio_sem); 56 if (priv->phydev)
131 ret = mii_ethtool_gset(&priv->mii_info, cmd); 57 return phy_ethtool_gset(priv->phydev, cmd);
132 up(&mdio_sem);
133 58
134 return ret; 59 return -EINVAL;
135} 60}
136 61
137static int cvm_oct_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 62static int cvm_oct_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
138{ 63{
139 struct octeon_ethernet *priv = netdev_priv(dev); 64 struct octeon_ethernet *priv = netdev_priv(dev);
140 int ret;
141 65
142 down(&mdio_sem); 66 if (!capable(CAP_NET_ADMIN))
143 ret = mii_ethtool_sset(&priv->mii_info, cmd); 67 return -EPERM;
144 up(&mdio_sem); 68
69 if (priv->phydev)
70 return phy_ethtool_sset(priv->phydev, cmd);
145 71
146 return ret; 72 return -EINVAL;
147} 73}
148 74
149static int cvm_oct_nway_reset(struct net_device *dev) 75static int cvm_oct_nway_reset(struct net_device *dev)
150{ 76{
151 struct octeon_ethernet *priv = netdev_priv(dev); 77 struct octeon_ethernet *priv = netdev_priv(dev);
152 int ret;
153 78
154 down(&mdio_sem); 79 if (!capable(CAP_NET_ADMIN))
155 ret = mii_nway_restart(&priv->mii_info); 80 return -EPERM;
156 up(&mdio_sem);
157 81
158 return ret; 82 if (priv->phydev)
159} 83 return phy_start_aneg(priv->phydev);
160 84
161static u32 cvm_oct_get_link(struct net_device *dev) 85 return -EINVAL;
162{
163 struct octeon_ethernet *priv = netdev_priv(dev);
164 u32 ret;
165
166 down(&mdio_sem);
167 ret = mii_link_ok(&priv->mii_info);
168 up(&mdio_sem);
169
170 return ret;
171} 86}
172 87
173const struct ethtool_ops cvm_oct_ethtool_ops = { 88const struct ethtool_ops cvm_oct_ethtool_ops = {
@@ -175,7 +90,7 @@ const struct ethtool_ops cvm_oct_ethtool_ops = {
175 .get_settings = cvm_oct_get_settings, 90 .get_settings = cvm_oct_get_settings,
176 .set_settings = cvm_oct_set_settings, 91 .set_settings = cvm_oct_set_settings,
177 .nway_reset = cvm_oct_nway_reset, 92 .nway_reset = cvm_oct_nway_reset,
178 .get_link = cvm_oct_get_link, 93 .get_link = ethtool_op_get_link,
179 .get_sg = ethtool_op_get_sg, 94 .get_sg = ethtool_op_get_sg,
180 .get_tx_csum = ethtool_op_get_tx_csum, 95 .get_tx_csum = ethtool_op_get_tx_csum,
181}; 96};
@@ -191,41 +106,78 @@ const struct ethtool_ops cvm_oct_ethtool_ops = {
191int cvm_oct_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 106int cvm_oct_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
192{ 107{
193 struct octeon_ethernet *priv = netdev_priv(dev); 108 struct octeon_ethernet *priv = netdev_priv(dev);
194 struct mii_ioctl_data *data = if_mii(rq);
195 unsigned int duplex_chg;
196 int ret;
197 109
198 down(&mdio_sem); 110 if (!netif_running(dev))
199 ret = generic_mii_ioctl(&priv->mii_info, data, cmd, &duplex_chg); 111 return -EINVAL;
200 up(&mdio_sem); 112
113 if (!priv->phydev)
114 return -EINVAL;
115
116 return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
117}
201 118
202 return ret; 119static void cvm_oct_adjust_link(struct net_device *dev)
120{
121 struct octeon_ethernet *priv = netdev_priv(dev);
122 cvmx_helper_link_info_t link_info;
123
124 if (priv->last_link != priv->phydev->link) {
125 priv->last_link = priv->phydev->link;
126 link_info.u64 = 0;
127 link_info.s.link_up = priv->last_link ? 1 : 0;
128 link_info.s.full_duplex = priv->phydev->duplex ? 1 : 0;
129 link_info.s.speed = priv->phydev->speed;
130 cvmx_helper_link_set( priv->port, link_info);
131 if (priv->last_link) {
132 netif_carrier_on(dev);
133 if (priv->queue != -1)
134 DEBUGPRINT("%s: %u Mbps %s duplex, "
135 "port %2d, queue %2d\n",
136 dev->name, priv->phydev->speed,
137 priv->phydev->duplex ?
138 "Full" : "Half",
139 priv->port, priv->queue);
140 else
141 DEBUGPRINT("%s: %u Mbps %s duplex, "
142 "port %2d, POW\n",
143 dev->name, priv->phydev->speed,
144 priv->phydev->duplex ?
145 "Full" : "Half",
146 priv->port);
147 } else {
148 netif_carrier_off(dev);
149 DEBUGPRINT("%s: Link down\n", dev->name);
150 }
151 }
203} 152}
204 153
154
205/** 155/**
206 * Setup the MDIO device structures 156 * Setup the PHY
207 * 157 *
208 * @dev: Device to setup 158 * @dev: Device to setup
209 * 159 *
210 * Returns Zero on success, negative on failure 160 * Returns Zero on success, negative on failure
211 */ 161 */
212int cvm_oct_mdio_setup_device(struct net_device *dev) 162int cvm_oct_phy_setup_device(struct net_device *dev)
213{ 163{
214 struct octeon_ethernet *priv = netdev_priv(dev); 164 struct octeon_ethernet *priv = netdev_priv(dev);
215 int phy_id = cvmx_helper_board_get_mii_address(priv->port); 165
216 if (phy_id != -1) { 166 int phy_addr = cvmx_helper_board_get_mii_address(priv->port);
217 priv->mii_info.dev = dev; 167 if (phy_addr != -1) {
218 priv->mii_info.phy_id = phy_id; 168 char phy_id[20];
219 priv->mii_info.phy_id_mask = 0xff; 169
220 priv->mii_info.supports_gmii = 1; 170 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, "0", phy_addr);
221 priv->mii_info.reg_num_mask = 0x1f; 171
222 priv->mii_info.mdio_read = cvm_oct_mdio_read; 172 priv->phydev = phy_connect(dev, phy_id, cvm_oct_adjust_link, 0,
223 priv->mii_info.mdio_write = cvm_oct_mdio_write; 173 PHY_INTERFACE_MODE_GMII);
224 } else { 174
225 /* Supply dummy MDIO routines so the kernel won't crash 175 if (IS_ERR(priv->phydev)) {
226 if the user tries to read them */ 176 priv->phydev = NULL;
227 priv->mii_info.mdio_read = cvm_oct_mdio_dummy_read; 177 return -1;
228 priv->mii_info.mdio_write = cvm_oct_mdio_dummy_write; 178 }
179 priv->last_link = 0;
180 phy_start_aneg(priv->phydev);
229 } 181 }
230 return 0; 182 return 0;
231} 183}
diff --git a/drivers/staging/octeon/ethernet-mdio.h b/drivers/staging/octeon/ethernet-mdio.h
index b3328aeec2df..55d0614a7cd9 100644
--- a/drivers/staging/octeon/ethernet-mdio.h
+++ b/drivers/staging/octeon/ethernet-mdio.h
@@ -43,4 +43,4 @@
43 43
44extern const struct ethtool_ops cvm_oct_ethtool_ops; 44extern const struct ethtool_ops cvm_oct_ethtool_ops;
45int cvm_oct_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 45int cvm_oct_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
46int cvm_oct_mdio_setup_device(struct net_device *dev); 46int cvm_oct_phy_setup_device(struct net_device *dev);
diff --git a/drivers/staging/octeon/ethernet-proc.c b/drivers/staging/octeon/ethernet-proc.c
index 8fa88fc419b7..16308d484d3b 100644
--- a/drivers/staging/octeon/ethernet-proc.c
+++ b/drivers/staging/octeon/ethernet-proc.c
@@ -25,7 +25,6 @@
25 * Contact Cavium Networks for more information 25 * Contact Cavium Networks for more information
26**********************************************************************/ 26**********************************************************************/
27#include <linux/kernel.h> 27#include <linux/kernel.h>
28#include <linux/mii.h>
29#include <linux/seq_file.h> 28#include <linux/seq_file.h>
30#include <linux/proc_fs.h> 29#include <linux/proc_fs.h>
31#include <net/dst.h> 30#include <net/dst.h>
@@ -38,112 +37,6 @@
38#include "cvmx-helper.h" 37#include "cvmx-helper.h"
39#include "cvmx-pip.h" 38#include "cvmx-pip.h"
40 39
41static unsigned long long cvm_oct_stats_read_switch(struct net_device *dev,
42 int phy_id, int offset)
43{
44 struct octeon_ethernet *priv = netdev_priv(dev);
45
46 priv->mii_info.mdio_write(dev, phy_id, 0x1d, 0xcc00 | offset);
47 return ((uint64_t) priv->mii_info.
48 mdio_read(dev, phy_id,
49 0x1e) << 16) | (uint64_t) priv->mii_info.
50 mdio_read(dev, phy_id, 0x1f);
51}
52
53static int cvm_oct_stats_switch_show(struct seq_file *m, void *v)
54{
55 static const int ports[] = { 0, 1, 2, 3, 9, -1 };
56 struct net_device *dev = cvm_oct_device[0];
57 int index = 0;
58
59 while (ports[index] != -1) {
60
61 /* Latch port */
62 struct octeon_ethernet *priv = netdev_priv(dev);
63
64 priv->mii_info.mdio_write(dev, 0x1b, 0x1d,
65 0xdc00 | ports[index]);
66 seq_printf(m, "\nSwitch Port %d\n", ports[index]);
67 seq_printf(m, "InGoodOctets: %12llu\t"
68 "OutOctets: %12llu\t"
69 "64 Octets: %12llu\n",
70 cvm_oct_stats_read_switch(dev, 0x1b,
71 0x00) |
72 (cvm_oct_stats_read_switch(dev, 0x1b, 0x01) << 32),
73 cvm_oct_stats_read_switch(dev, 0x1b,
74 0x0E) |
75 (cvm_oct_stats_read_switch(dev, 0x1b, 0x0F) << 32),
76 cvm_oct_stats_read_switch(dev, 0x1b, 0x08));
77
78 seq_printf(m, "InBadOctets: %12llu\t"
79 "OutUnicast: %12llu\t"
80 "65-127 Octets: %12llu\n",
81 cvm_oct_stats_read_switch(dev, 0x1b, 0x02),
82 cvm_oct_stats_read_switch(dev, 0x1b, 0x10),
83 cvm_oct_stats_read_switch(dev, 0x1b, 0x09));
84
85 seq_printf(m, "InUnicast: %12llu\t"
86 "OutBroadcasts: %12llu\t"
87 "128-255 Octets: %12llu\n",
88 cvm_oct_stats_read_switch(dev, 0x1b, 0x04),
89 cvm_oct_stats_read_switch(dev, 0x1b, 0x13),
90 cvm_oct_stats_read_switch(dev, 0x1b, 0x0A));
91
92 seq_printf(m, "InBroadcasts: %12llu\t"
93 "OutMulticasts: %12llu\t"
94 "256-511 Octets: %12llu\n",
95 cvm_oct_stats_read_switch(dev, 0x1b, 0x06),
96 cvm_oct_stats_read_switch(dev, 0x1b, 0x12),
97 cvm_oct_stats_read_switch(dev, 0x1b, 0x0B));
98
99 seq_printf(m, "InMulticasts: %12llu\t"
100 "OutPause: %12llu\t"
101 "512-1023 Octets:%12llu\n",
102 cvm_oct_stats_read_switch(dev, 0x1b, 0x07),
103 cvm_oct_stats_read_switch(dev, 0x1b, 0x15),
104 cvm_oct_stats_read_switch(dev, 0x1b, 0x0C));
105
106 seq_printf(m, "InPause: %12llu\t"
107 "Excessive: %12llu\t"
108 "1024-Max Octets:%12llu\n",
109 cvm_oct_stats_read_switch(dev, 0x1b, 0x16),
110 cvm_oct_stats_read_switch(dev, 0x1b, 0x11),
111 cvm_oct_stats_read_switch(dev, 0x1b, 0x0D));
112
113 seq_printf(m, "InUndersize: %12llu\t"
114 "Collisions: %12llu\n",
115 cvm_oct_stats_read_switch(dev, 0x1b, 0x18),
116 cvm_oct_stats_read_switch(dev, 0x1b, 0x1E));
117
118 seq_printf(m, "InFragments: %12llu\t"
119 "Deferred: %12llu\n",
120 cvm_oct_stats_read_switch(dev, 0x1b, 0x19),
121 cvm_oct_stats_read_switch(dev, 0x1b, 0x05));
122
123 seq_printf(m, "InOversize: %12llu\t"
124 "Single: %12llu\n",
125 cvm_oct_stats_read_switch(dev, 0x1b, 0x1A),
126 cvm_oct_stats_read_switch(dev, 0x1b, 0x14));
127
128 seq_printf(m, "InJabber: %12llu\t"
129 "Multiple: %12llu\n",
130 cvm_oct_stats_read_switch(dev, 0x1b, 0x1B),
131 cvm_oct_stats_read_switch(dev, 0x1b, 0x17));
132
133 seq_printf(m, "In RxErr: %12llu\t"
134 "OutFCSErr: %12llu\n",
135 cvm_oct_stats_read_switch(dev, 0x1b, 0x1C),
136 cvm_oct_stats_read_switch(dev, 0x1b, 0x03));
137
138 seq_printf(m, "InFCSErr: %12llu\t"
139 "Late: %12llu\n",
140 cvm_oct_stats_read_switch(dev, 0x1b, 0x1D),
141 cvm_oct_stats_read_switch(dev, 0x1b, 0x1F));
142 index++;
143 }
144 return 0;
145}
146
147/** 40/**
148 * User is reading /proc/octeon_ethernet_stats 41 * User is reading /proc/octeon_ethernet_stats
149 * 42 *
@@ -215,11 +108,6 @@ static int cvm_oct_stats_show(struct seq_file *m, void *v)
215 } 108 }
216 } 109 }
217 110
218 if (cvm_oct_device[0]) {
219 priv = netdev_priv(cvm_oct_device[0]);
220 if (priv->imode == CVMX_HELPER_INTERFACE_MODE_GMII)
221 cvm_oct_stats_switch_show(m, v);
222 }
223 return 0; 111 return 0;
224} 112}
225 113
diff --git a/drivers/staging/octeon/ethernet-rgmii.c b/drivers/staging/octeon/ethernet-rgmii.c
index fbaa465d2fac..3820f1ec11d1 100644
--- a/drivers/staging/octeon/ethernet-rgmii.c
+++ b/drivers/staging/octeon/ethernet-rgmii.c
@@ -147,32 +147,36 @@ static void cvm_oct_rgmii_poll(struct net_device *dev)
147 cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, interface), 147 cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, interface),
148 gmxx_rxx_int_reg.u64); 148 gmxx_rxx_int_reg.u64);
149 } 149 }
150 150 if (priv->phydev == NULL) {
151 link_info = cvmx_helper_link_autoconf(priv->port); 151 link_info = cvmx_helper_link_autoconf(priv->port);
152 priv->link_info = link_info.u64; 152 priv->link_info = link_info.u64;
153 }
153 spin_unlock_irqrestore(&global_register_lock, flags); 154 spin_unlock_irqrestore(&global_register_lock, flags);
154 155
155 /* Tell Linux */ 156 if (priv->phydev == NULL) {
156 if (link_info.s.link_up) { 157 /* Tell core. */
157 158 if (link_info.s.link_up) {
158 if (!netif_carrier_ok(dev)) 159 if (!netif_carrier_ok(dev))
159 netif_carrier_on(dev); 160 netif_carrier_on(dev);
160 if (priv->queue != -1) 161 if (priv->queue != -1)
161 DEBUGPRINT 162 DEBUGPRINT("%s: %u Mbps %s duplex, "
162 ("%s: %u Mbps %s duplex, port %2d, queue %2d\n", 163 "port %2d, queue %2d\n",
163 dev->name, link_info.s.speed, 164 dev->name, link_info.s.speed,
164 (link_info.s.full_duplex) ? "Full" : "Half", 165 (link_info.s.full_duplex) ?
165 priv->port, priv->queue); 166 "Full" : "Half",
166 else 167 priv->port, priv->queue);
167 DEBUGPRINT("%s: %u Mbps %s duplex, port %2d, POW\n", 168 else
168 dev->name, link_info.s.speed, 169 DEBUGPRINT("%s: %u Mbps %s duplex, "
169 (link_info.s.full_duplex) ? "Full" : "Half", 170 "port %2d, POW\n",
170 priv->port); 171 dev->name, link_info.s.speed,
171 } else { 172 (link_info.s.full_duplex) ?
172 173 "Full" : "Half",
173 if (netif_carrier_ok(dev)) 174 priv->port);
174 netif_carrier_off(dev); 175 } else {
175 DEBUGPRINT("%s: Link down\n", dev->name); 176 if (netif_carrier_ok(dev))
177 netif_carrier_off(dev);
178 DEBUGPRINT("%s: Link down\n", dev->name);
179 }
176 } 180 }
177} 181}
178 182
diff --git a/drivers/staging/octeon/ethernet-sgmii.c b/drivers/staging/octeon/ethernet-sgmii.c
index 2b54996bd85d..6061d01eca2d 100644
--- a/drivers/staging/octeon/ethernet-sgmii.c
+++ b/drivers/staging/octeon/ethernet-sgmii.c
@@ -113,7 +113,7 @@ int cvm_oct_sgmii_init(struct net_device *dev)
113 struct octeon_ethernet *priv = netdev_priv(dev); 113 struct octeon_ethernet *priv = netdev_priv(dev);
114 cvm_oct_common_init(dev); 114 cvm_oct_common_init(dev);
115 dev->netdev_ops->ndo_stop(dev); 115 dev->netdev_ops->ndo_stop(dev);
116 if (!octeon_is_simulation()) 116 if (!octeon_is_simulation() && priv->phydev == NULL)
117 priv->poll = cvm_oct_sgmii_poll; 117 priv->poll = cvm_oct_sgmii_poll;
118 118
119 /* FIXME: Need autoneg logic */ 119 /* FIXME: Need autoneg logic */
diff --git a/drivers/staging/octeon/ethernet-xaui.c b/drivers/staging/octeon/ethernet-xaui.c
index 0c2e7cc40f35..ee3dc41b2c53 100644
--- a/drivers/staging/octeon/ethernet-xaui.c
+++ b/drivers/staging/octeon/ethernet-xaui.c
@@ -112,7 +112,7 @@ int cvm_oct_xaui_init(struct net_device *dev)
112 struct octeon_ethernet *priv = netdev_priv(dev); 112 struct octeon_ethernet *priv = netdev_priv(dev);
113 cvm_oct_common_init(dev); 113 cvm_oct_common_init(dev);
114 dev->netdev_ops->ndo_stop(dev); 114 dev->netdev_ops->ndo_stop(dev);
115 if (!octeon_is_simulation()) 115 if (!octeon_is_simulation() && priv->phydev == NULL)
116 priv->poll = cvm_oct_xaui_poll; 116 priv->poll = cvm_oct_xaui_poll;
117 117
118 return 0; 118 return 0;
diff --git a/drivers/staging/octeon/ethernet.c b/drivers/staging/octeon/ethernet.c
index 492c5029992d..4cfd4b136b32 100644
--- a/drivers/staging/octeon/ethernet.c
+++ b/drivers/staging/octeon/ethernet.c
@@ -30,7 +30,7 @@
30#include <linux/netdevice.h> 30#include <linux/netdevice.h>
31#include <linux/etherdevice.h> 31#include <linux/etherdevice.h>
32#include <linux/delay.h> 32#include <linux/delay.h>
33#include <linux/mii.h> 33#include <linux/phy.h>
34 34
35#include <net/dst.h> 35#include <net/dst.h>
36 36
@@ -132,8 +132,6 @@ static struct timer_list cvm_oct_poll_timer;
132 */ 132 */
133struct net_device *cvm_oct_device[TOTAL_NUMBER_OF_PORTS]; 133struct net_device *cvm_oct_device[TOTAL_NUMBER_OF_PORTS];
134 134
135extern struct semaphore mdio_sem;
136
137/** 135/**
138 * Periodic timer tick for slow management operations 136 * Periodic timer tick for slow management operations
139 * 137 *
@@ -160,13 +158,8 @@ static void cvm_do_timer(unsigned long arg)
160 goto out; 158 goto out;
161 159
162 priv = netdev_priv(cvm_oct_device[port]); 160 priv = netdev_priv(cvm_oct_device[port]);
163 if (priv->poll) { 161 if (priv->poll)
164 /* skip polling if we don't get the lock */ 162 priv->poll(cvm_oct_device[port]);
165 if (!down_trylock(&mdio_sem)) {
166 priv->poll(cvm_oct_device[port]);
167 up(&mdio_sem);
168 }
169 }
170 163
171 queues_per_port = cvmx_pko_get_num_queues(port); 164 queues_per_port = cvmx_pko_get_num_queues(port);
172 /* Drain any pending packets in the free list */ 165 /* Drain any pending packets in the free list */
@@ -524,7 +517,7 @@ int cvm_oct_common_init(struct net_device *dev)
524 dev->features |= NETIF_F_LLTX; 517 dev->features |= NETIF_F_LLTX;
525 SET_ETHTOOL_OPS(dev, &cvm_oct_ethtool_ops); 518 SET_ETHTOOL_OPS(dev, &cvm_oct_ethtool_ops);
526 519
527 cvm_oct_mdio_setup_device(dev); 520 cvm_oct_phy_setup_device(dev);
528 dev->netdev_ops->ndo_set_mac_address(dev, &sa); 521 dev->netdev_ops->ndo_set_mac_address(dev, &sa);
529 dev->netdev_ops->ndo_change_mtu(dev, dev->mtu); 522 dev->netdev_ops->ndo_change_mtu(dev, dev->mtu);
530 523
@@ -540,7 +533,10 @@ int cvm_oct_common_init(struct net_device *dev)
540 533
541void cvm_oct_common_uninit(struct net_device *dev) 534void cvm_oct_common_uninit(struct net_device *dev)
542{ 535{
543 /* Currently nothing to do */ 536 struct octeon_ethernet *priv = netdev_priv(dev);
537
538 if (priv->phydev)
539 phy_disconnect(priv->phydev);
544} 540}
545 541
546static const struct net_device_ops cvm_oct_npi_netdev_ops = { 542static const struct net_device_ops cvm_oct_npi_netdev_ops = {
@@ -627,6 +623,8 @@ static const struct net_device_ops cvm_oct_pow_netdev_ops = {
627#endif 623#endif
628}; 624};
629 625
626extern void octeon_mdiobus_force_mod_depencency(void);
627
630/** 628/**
631 * Module/ driver initialization. Creates the linux network 629 * Module/ driver initialization. Creates the linux network
632 * devices. 630 * devices.
@@ -640,6 +638,7 @@ static int __init cvm_oct_init_module(void)
640 int fau = FAU_NUM_PACKET_BUFFERS_TO_FREE; 638 int fau = FAU_NUM_PACKET_BUFFERS_TO_FREE;
641 int qos; 639 int qos;
642 640
641 octeon_mdiobus_force_mod_depencency();
643 pr_notice("cavium-ethernet %s\n", OCTEON_ETHERNET_VERSION); 642 pr_notice("cavium-ethernet %s\n", OCTEON_ETHERNET_VERSION);
644 643
645 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) 644 if (OCTEON_IS_MODEL(OCTEON_CN52XX))
diff --git a/drivers/staging/octeon/octeon-ethernet.h b/drivers/staging/octeon/octeon-ethernet.h
index 3aef9878fc0a..402a15b9bb0e 100644
--- a/drivers/staging/octeon/octeon-ethernet.h
+++ b/drivers/staging/octeon/octeon-ethernet.h
@@ -50,9 +50,9 @@ struct octeon_ethernet {
50 /* List of outstanding tx buffers per queue */ 50 /* List of outstanding tx buffers per queue */
51 struct sk_buff_head tx_free_list[16]; 51 struct sk_buff_head tx_free_list[16];
52 /* Device statistics */ 52 /* Device statistics */
53 struct net_device_stats stats 53 struct net_device_stats stats;
54; /* Generic MII info structure */ 54 struct phy_device *phydev;
55 struct mii_if_info mii_info; 55 unsigned int last_link;
56 /* Last negotiated link state */ 56 /* Last negotiated link state */
57 uint64_t link_info; 57 uint64_t link_info;
58 /* Called periodically to check link status */ 58 /* Called periodically to check link status */
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index d958b76430a2..da84fd03850f 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -815,16 +815,6 @@ config PNX833X_WDT
815 timer has expired and no process has written to /dev/watchdog during 815 timer has expired and no process has written to /dev/watchdog during
816 that time. 816 that time.
817 817
818config WDT_RM9K_GPI
819 tristate "RM9000/GPI hardware watchdog"
820 depends on CPU_RM9000
821 help
822 Watchdog implementation using the GPI hardware found on
823 PMC-Sierra RM9xxx CPUs.
824
825 To compile this driver as a module, choose M here: the
826 module will be called rm9k_wdt.
827
828config SIBYTE_WDOG 818config SIBYTE_WDOG
829 tristate "Sibyte SoC hardware watchdog" 819 tristate "Sibyte SoC hardware watchdog"
830 depends on CPU_SB1 820 depends on CPU_SB1
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 89c045dc468e..475c61100069 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -109,7 +109,6 @@ obj-$(CONFIG_RC32434_WDT) += rc32434_wdt.o
109obj-$(CONFIG_INDYDOG) += indydog.o 109obj-$(CONFIG_INDYDOG) += indydog.o
110obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o 110obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o
111obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt.o 111obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt.o
112obj-$(CONFIG_WDT_RM9K_GPI) += rm9k_wdt.o
113obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o 112obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o
114obj-$(CONFIG_AR7_WDT) += ar7_wdt.o 113obj-$(CONFIG_AR7_WDT) += ar7_wdt.o
115obj-$(CONFIG_TXX9_WDT) += txx9wdt.o 114obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
diff --git a/drivers/watchdog/rm9k_wdt.c b/drivers/watchdog/rm9k_wdt.c
deleted file mode 100644
index bb66958b9433..000000000000
--- a/drivers/watchdog/rm9k_wdt.c
+++ /dev/null
@@ -1,419 +0,0 @@
1/*
2 * Watchdog implementation for GPI h/w found on PMC-Sierra RM9xxx
3 * chips.
4 *
5 * Copyright (C) 2004 by Basler Vision Technologies AG
6 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/platform_device.h>
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/interrupt.h>
27#include <linux/fs.h>
28#include <linux/reboot.h>
29#include <linux/notifier.h>
30#include <linux/miscdevice.h>
31#include <linux/watchdog.h>
32#include <linux/io.h>
33#include <linux/uaccess.h>
34#include <asm/atomic.h>
35#include <asm/processor.h>
36#include <asm/system.h>
37#include <asm/rm9k-ocd.h>
38
39#include <rm9k_wdt.h>
40
41
42#define CLOCK 125000000
43#define MAX_TIMEOUT_SECONDS 32
44#define CPCCR 0x0080
45#define CPGIG1SR 0x0044
46#define CPGIG1ER 0x0054
47
48
49/* Function prototypes */
50static irqreturn_t wdt_gpi_irqhdl(int, void *);
51static void wdt_gpi_start(void);
52static void wdt_gpi_stop(void);
53static void wdt_gpi_set_timeout(unsigned int);
54static int wdt_gpi_open(struct inode *, struct file *);
55static int wdt_gpi_release(struct inode *, struct file *);
56static ssize_t wdt_gpi_write(struct file *, const char __user *, size_t,
57 loff_t *);
58static long wdt_gpi_ioctl(struct file *, unsigned int, unsigned long);
59static int wdt_gpi_notify(struct notifier_block *, unsigned long, void *);
60static const struct resource *wdt_gpi_get_resource(struct platform_device *,
61 const char *, unsigned int);
62static int __init wdt_gpi_probe(struct platform_device *);
63static int __exit wdt_gpi_remove(struct platform_device *);
64
65
66static const char wdt_gpi_name[] = "wdt_gpi";
67static atomic_t opencnt;
68static int expect_close;
69static int locked;
70
71
72/* These are set from device resources */
73static void __iomem *wd_regs;
74static unsigned int wd_irq, wd_ctr;
75
76
77/* Module arguments */
78static int timeout = MAX_TIMEOUT_SECONDS;
79module_param(timeout, int, 0444);
80MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds");
81
82static unsigned long resetaddr = 0xbffdc200;
83module_param(resetaddr, ulong, 0444);
84MODULE_PARM_DESC(resetaddr, "Address to write to to force a reset");
85
86static unsigned long flagaddr = 0xbffdc104;
87module_param(flagaddr, ulong, 0444);
88MODULE_PARM_DESC(flagaddr, "Address to write to boot flags to");
89
90static int powercycle;
91module_param(powercycle, bool, 0444);
92MODULE_PARM_DESC(powercycle, "Cycle power if watchdog expires");
93
94static int nowayout = WATCHDOG_NOWAYOUT;
95module_param(nowayout, bool, 0444);
96MODULE_PARM_DESC(nowayout, "Watchdog cannot be disabled once started");
97
98
99/* Kernel interfaces */
100static const struct file_operations fops = {
101 .owner = THIS_MODULE,
102 .open = wdt_gpi_open,
103 .release = wdt_gpi_release,
104 .write = wdt_gpi_write,
105 .unlocked_ioctl = wdt_gpi_ioctl,
106};
107
108static struct miscdevice miscdev = {
109 .minor = WATCHDOG_MINOR,
110 .name = wdt_gpi_name,
111 .fops = &fops,
112};
113
114static struct notifier_block wdt_gpi_shutdown = {
115 .notifier_call = wdt_gpi_notify,
116};
117
118
119/* Interrupt handler */
120static irqreturn_t wdt_gpi_irqhdl(int irq, void *ctxt)
121{
122 if (!unlikely(__raw_readl(wd_regs + 0x0008) & 0x1))
123 return IRQ_NONE;
124 __raw_writel(0x1, wd_regs + 0x0008);
125
126
127 printk(KERN_CRIT "%s: watchdog expired - resetting system\n",
128 wdt_gpi_name);
129
130 *(volatile char *) flagaddr |= 0x01;
131 *(volatile char *) resetaddr = powercycle ? 0x01 : 0x2;
132 iob();
133 while (1)
134 cpu_relax();
135}
136
137
138/* Watchdog functions */
139static void wdt_gpi_start(void)
140{
141 u32 reg;
142
143 lock_titan_regs();
144 reg = titan_readl(CPGIG1ER);
145 titan_writel(reg | (0x100 << wd_ctr), CPGIG1ER);
146 iob();
147 unlock_titan_regs();
148}
149
150static void wdt_gpi_stop(void)
151{
152 u32 reg;
153
154 lock_titan_regs();
155 reg = titan_readl(CPCCR) & ~(0xf << (wd_ctr * 4));
156 titan_writel(reg, CPCCR);
157 reg = titan_readl(CPGIG1ER);
158 titan_writel(reg & ~(0x100 << wd_ctr), CPGIG1ER);
159 iob();
160 unlock_titan_regs();
161}
162
163static void wdt_gpi_set_timeout(unsigned int to)
164{
165 u32 reg;
166 const u32 wdval = (to * CLOCK) & ~0x0000000f;
167
168 lock_titan_regs();
169 reg = titan_readl(CPCCR) & ~(0xf << (wd_ctr * 4));
170 titan_writel(reg, CPCCR);
171 wmb();
172 __raw_writel(wdval, wd_regs + 0x0000);
173 wmb();
174 titan_writel(reg | (0x2 << (wd_ctr * 4)), CPCCR);
175 wmb();
176 titan_writel(reg | (0x5 << (wd_ctr * 4)), CPCCR);
177 iob();
178 unlock_titan_regs();
179}
180
181
182/* /dev/watchdog operations */
183static int wdt_gpi_open(struct inode *inode, struct file *file)
184{
185 int res;
186
187 if (unlikely(atomic_dec_if_positive(&opencnt) < 0))
188 return -EBUSY;
189
190 expect_close = 0;
191 if (locked) {
192 module_put(THIS_MODULE);
193 free_irq(wd_irq, &miscdev);
194 locked = 0;
195 }
196
197 res = request_irq(wd_irq, wdt_gpi_irqhdl, IRQF_SHARED | IRQF_DISABLED,
198 wdt_gpi_name, &miscdev);
199 if (unlikely(res))
200 return res;
201
202 wdt_gpi_set_timeout(timeout);
203 wdt_gpi_start();
204
205 printk(KERN_INFO "%s: watchdog started, timeout = %u seconds\n",
206 wdt_gpi_name, timeout);
207 return nonseekable_open(inode, file);
208}
209
210static int wdt_gpi_release(struct inode *inode, struct file *file)
211{
212 if (nowayout) {
213 printk(KERN_INFO "%s: no way out - watchdog left running\n",
214 wdt_gpi_name);
215 __module_get(THIS_MODULE);
216 locked = 1;
217 } else {
218 if (expect_close) {
219 wdt_gpi_stop();
220 free_irq(wd_irq, &miscdev);
221 printk(KERN_INFO "%s: watchdog stopped\n",
222 wdt_gpi_name);
223 } else {
224 printk(KERN_CRIT "%s: unexpected close() -"
225 " watchdog left running\n",
226 wdt_gpi_name);
227 wdt_gpi_set_timeout(timeout);
228 __module_get(THIS_MODULE);
229 locked = 1;
230 }
231 }
232
233 atomic_inc(&opencnt);
234 return 0;
235}
236
237static ssize_t wdt_gpi_write(struct file *f, const char __user *d, size_t s,
238 loff_t *o)
239{
240 char val;
241
242 wdt_gpi_set_timeout(timeout);
243 expect_close = (s > 0) && !get_user(val, d) && (val == 'V');
244 return s ? 1 : 0;
245}
246
247static long wdt_gpi_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
248{
249 long res = -ENOTTY;
250 const long size = _IOC_SIZE(cmd);
251 int stat;
252 void __user *argp = (void __user *)arg;
253 static struct watchdog_info wdinfo = {
254 .identity = "RM9xxx/GPI watchdog",
255 .firmware_version = 0,
256 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING
257 };
258
259 if (unlikely(_IOC_TYPE(cmd) != WATCHDOG_IOCTL_BASE))
260 return -ENOTTY;
261
262 if ((_IOC_DIR(cmd) & _IOC_READ)
263 && !access_ok(VERIFY_WRITE, arg, size))
264 return -EFAULT;
265
266 if ((_IOC_DIR(cmd) & _IOC_WRITE)
267 && !access_ok(VERIFY_READ, arg, size))
268 return -EFAULT;
269
270 expect_close = 0;
271
272 switch (cmd) {
273 case WDIOC_GETSUPPORT:
274 wdinfo.options = nowayout ?
275 WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING :
276 WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
277 WDIOF_MAGICCLOSE;
278 res = __copy_to_user(argp, &wdinfo, size) ? -EFAULT : size;
279 break;
280
281 case WDIOC_GETSTATUS:
282 break;
283
284 case WDIOC_GETBOOTSTATUS:
285 stat = (*(volatile char *) flagaddr & 0x01)
286 ? WDIOF_CARDRESET : 0;
287 res = __copy_to_user(argp, &stat, size) ?
288 -EFAULT : size;
289 break;
290
291 case WDIOC_SETOPTIONS:
292 break;
293
294 case WDIOC_KEEPALIVE:
295 wdt_gpi_set_timeout(timeout);
296 res = size;
297 break;
298
299 case WDIOC_SETTIMEOUT:
300 {
301 int val;
302 if (unlikely(__copy_from_user(&val, argp, size))) {
303 res = -EFAULT;
304 break;
305 }
306
307 if (val > MAX_TIMEOUT_SECONDS)
308 val = MAX_TIMEOUT_SECONDS;
309 timeout = val;
310 wdt_gpi_set_timeout(val);
311 res = size;
312 printk(KERN_INFO "%s: timeout set to %u seconds\n",
313 wdt_gpi_name, timeout);
314 }
315 break;
316
317 case WDIOC_GETTIMEOUT:
318 res = __copy_to_user(argp, &timeout, size) ?
319 -EFAULT : size;
320 break;
321 }
322
323 return res;
324}
325
326
327/* Shutdown notifier */
328static int wdt_gpi_notify(struct notifier_block *this, unsigned long code,
329 void *unused)
330{
331 if (code == SYS_DOWN || code == SYS_HALT)
332 wdt_gpi_stop();
333
334 return NOTIFY_DONE;
335}
336
337
338/* Init & exit procedures */
339static const struct resource *wdt_gpi_get_resource(struct platform_device *pdv,
340 const char *name, unsigned int type)
341{
342 char buf[80];
343 if (snprintf(buf, sizeof(buf), "%s_0", name) >= sizeof(buf))
344 return NULL;
345 return platform_get_resource_byname(pdv, type, buf);
346}
347
348/* No hotplugging on the platform bus - use __devinit */
349static int __devinit wdt_gpi_probe(struct platform_device *pdv)
350{
351 int res;
352 const struct resource
353 * const rr = wdt_gpi_get_resource(pdv, WDT_RESOURCE_REGS,
354 IORESOURCE_MEM),
355 * const ri = wdt_gpi_get_resource(pdv, WDT_RESOURCE_IRQ,
356 IORESOURCE_IRQ),
357 * const rc = wdt_gpi_get_resource(pdv, WDT_RESOURCE_COUNTER,
358 0);
359
360 if (unlikely(!rr || !ri || !rc))
361 return -ENXIO;
362
363 wd_regs = ioremap_nocache(rr->start, rr->end + 1 - rr->start);
364 if (unlikely(!wd_regs))
365 return -ENOMEM;
366 wd_irq = ri->start;
367 wd_ctr = rc->start;
368 res = misc_register(&miscdev);
369 if (res)
370 iounmap(wd_regs);
371 else
372 register_reboot_notifier(&wdt_gpi_shutdown);
373 return res;
374}
375
376static int __devexit wdt_gpi_remove(struct platform_device *dev)
377{
378 int res;
379
380 unregister_reboot_notifier(&wdt_gpi_shutdown);
381 res = misc_deregister(&miscdev);
382 iounmap(wd_regs);
383 wd_regs = NULL;
384 return res;
385}
386
387
388/* Device driver init & exit */
389static struct platform_driver wgt_gpi_driver = {
390 .driver = {
391 .name = wdt_gpi_name,
392 .owner = THIS_MODULE,
393 },
394 .probe = wdt_gpi_probe,
395 .remove = __devexit_p(wdt_gpi_remove),
396};
397
398static int __init wdt_gpi_init_module(void)
399{
400 atomic_set(&opencnt, 1);
401 if (timeout > MAX_TIMEOUT_SECONDS)
402 timeout = MAX_TIMEOUT_SECONDS;
403 return platform_driver_register(&wdt_gpi_driver);
404}
405
406static void __exit wdt_gpi_cleanup_module(void)
407{
408 platform_driver_unregister(&wdt_gpi_driver);
409}
410
411module_init(wdt_gpi_init_module);
412module_exit(wdt_gpi_cleanup_module);
413
414MODULE_AUTHOR("Thomas Koeller <thomas.koeller@baslerweb.com>");
415MODULE_DESCRIPTION("Basler eXcite watchdog driver for gpi devices");
416MODULE_VERSION("0.1");
417MODULE_LICENSE("GPL");
418MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
419
diff --git a/scripts/Makefile.build b/scripts/Makefile.build
index 341b58902ffc..0b94d2fa3a88 100644
--- a/scripts/Makefile.build
+++ b/scripts/Makefile.build
@@ -207,6 +207,7 @@ endif
207 207
208ifdef CONFIG_FTRACE_MCOUNT_RECORD 208ifdef CONFIG_FTRACE_MCOUNT_RECORD
209cmd_record_mcount = set -e ; perl $(srctree)/scripts/recordmcount.pl "$(ARCH)" \ 209cmd_record_mcount = set -e ; perl $(srctree)/scripts/recordmcount.pl "$(ARCH)" \
210 "$(if $(CONFIG_CPU_BIG_ENDIAN),big,little)" \
210 "$(if $(CONFIG_64BIT),64,32)" \ 211 "$(if $(CONFIG_64BIT),64,32)" \
211 "$(OBJDUMP)" "$(OBJCOPY)" "$(CC)" "$(LD)" "$(NM)" "$(RM)" "$(MV)" \ 212 "$(OBJDUMP)" "$(OBJCOPY)" "$(CC)" "$(LD)" "$(NM)" "$(RM)" "$(MV)" \
212 "$(if $(part-of-module),1,0)" "$(@)"; 213 "$(if $(part-of-module),1,0)" "$(@)";
diff --git a/scripts/recordmcount.pl b/scripts/recordmcount.pl
index 9cf0a6fad6ba..92f09fe9639e 100755
--- a/scripts/recordmcount.pl
+++ b/scripts/recordmcount.pl
@@ -113,13 +113,13 @@ $P =~ s@.*/@@g;
113 113
114my $V = '0.1'; 114my $V = '0.1';
115 115
116if ($#ARGV != 10) { 116if ($#ARGV != 11) {
117 print "usage: $P arch bits objdump objcopy cc ld nm rm mv is_module inputfile\n"; 117 print "usage: $P arch endian bits objdump objcopy cc ld nm rm mv is_module inputfile\n";
118 print "version: $V\n"; 118 print "version: $V\n";
119 exit(1); 119 exit(1);
120} 120}
121 121
122my ($arch, $bits, $objdump, $objcopy, $cc, 122my ($arch, $endian, $bits, $objdump, $objcopy, $cc,
123 $ld, $nm, $rm, $mv, $is_module, $inputfile) = @ARGV; 123 $ld, $nm, $rm, $mv, $is_module, $inputfile) = @ARGV;
124 124
125# This file refers to mcount and shouldn't be ftraced, so lets' ignore it 125# This file refers to mcount and shouldn't be ftraced, so lets' ignore it
@@ -295,6 +295,58 @@ if ($arch eq "x86_64") {
295 $ld .= " -m elf64_sparc"; 295 $ld .= " -m elf64_sparc";
296 $cc .= " -m64"; 296 $cc .= " -m64";
297 $objcopy .= " -O elf64-sparc"; 297 $objcopy .= " -O elf64-sparc";
298} elsif ($arch eq "mips") {
299 # To enable module support, we need to enable the -mlong-calls option
300 # of gcc for module, after using this option, we can not get the real
301 # offset of the calling to _mcount, but the offset of the lui
302 # instruction or the addiu one. herein, we record the address of the
303 # first one, and then we can replace this instruction by a branch
304 # instruction to jump over the profiling function to filter the
305 # indicated functions, or swith back to the lui instruction to trace
306 # them, which means dynamic tracing.
307 #
308 # c: 3c030000 lui v1,0x0
309 # c: R_MIPS_HI16 _mcount
310 # c: R_MIPS_NONE *ABS*
311 # c: R_MIPS_NONE *ABS*
312 # 10: 64630000 daddiu v1,v1,0
313 # 10: R_MIPS_LO16 _mcount
314 # 10: R_MIPS_NONE *ABS*
315 # 10: R_MIPS_NONE *ABS*
316 # 14: 03e0082d move at,ra
317 # 18: 0060f809 jalr v1
318 #
319 # for the kernel:
320 #
321 # 10: 03e0082d move at,ra
322 # 14: 0c000000 jal 0 <loongson_halt>
323 # 14: R_MIPS_26 _mcount
324 # 14: R_MIPS_NONE *ABS*
325 # 14: R_MIPS_NONE *ABS*
326 # 18: 00020021 nop
327 if ($is_module eq "0") {
328 $mcount_regex = "^\\s*([0-9a-fA-F]+):.*\\s_mcount\$";
329 } else {
330 $mcount_regex = "^\\s*([0-9a-fA-F]+): R_MIPS_HI16\\s+_mcount\$";
331 }
332 $objdump .= " -Melf-trad".$endian."mips ";
333
334 if ($endian eq "big") {
335 $endian = " -EB ";
336 $ld .= " -melf".$bits."btsmip";
337 } else {
338 $endian = " -EL ";
339 $ld .= " -melf".$bits."ltsmip";
340 }
341
342 $cc .= " -mno-abicalls -fno-pic -mabi=" . $bits . $endian;
343 $ld .= $endian;
344
345 if ($bits == 64) {
346 $function_regex =
347 "^([0-9a-fA-F]+)\\s+<(.|[^\$]L.*?|\$[^L].*?|[^\$][^L].*?)>:";
348 $type = ".dword";
349 }
298} elsif ($arch eq "microblaze") { 350} elsif ($arch eq "microblaze") {
299 # Microblaze calls '_mcount' instead of plain 'mcount'. 351 # Microblaze calls '_mcount' instead of plain 'mcount'.
300 $mcount_regex = "^\\s*([0-9a-fA-F]+):.*\\s_mcount\$"; 352 $mcount_regex = "^\\s*([0-9a-fA-F]+):.*\\s_mcount\$";
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-20 10:57:56 -0500