diff options
author | Sonic Zhang <sonic.zhang@analog.com> | 2008-02-02 04:05:02 -0500 |
---|---|---|
committer | Bryan Wu <cooloney@kernel.org> | 2008-02-02 04:05:02 -0500 |
commit | db288381e26e592b11572ce8199bedeadf0c0830 (patch) | |
tree | e10eaa7b1a5b0bfefecd9417be43d12f5e82e006 | |
parent | 4cb4f22b19237e63c460c53fbd1c417cdaf63014 (diff) |
[Blackfin] serial driver: Add flow control support to bf54x
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
-rw-r--r-- | drivers/serial/Kconfig | 4 | ||||
-rw-r--r-- | drivers/serial/bfin_5xx.c | 12 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf548/bfin_serial_5xx.h | 3 |
3 files changed, 17 insertions, 2 deletions
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 202fb5c99b83..cf627cd1b4c8 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig | |||
@@ -699,14 +699,14 @@ config BFIN_UART1_CTSRTS | |||
699 | 699 | ||
700 | config UART1_CTS_PIN | 700 | config UART1_CTS_PIN |
701 | int "UART1 CTS pin" | 701 | int "UART1 CTS pin" |
702 | depends on BFIN_UART1_CTSRTS && (BF53x || BF561) | 702 | depends on BFIN_UART1_CTSRTS && !BF54x |
703 | default -1 | 703 | default -1 |
704 | help | 704 | help |
705 | Refer to ./include/asm-blackfin/gpio.h to see the GPIO map. | 705 | Refer to ./include/asm-blackfin/gpio.h to see the GPIO map. |
706 | 706 | ||
707 | config UART1_RTS_PIN | 707 | config UART1_RTS_PIN |
708 | int "UART1 RTS pin" | 708 | int "UART1 RTS pin" |
709 | depends on BFIN_UART1_CTSRTS && (BF53x || BF561) | 709 | depends on BFIN_UART1_CTSRTS && !BF54x |
710 | default -1 | 710 | default -1 |
711 | help | 711 | help |
712 | Refer to ./include/asm-blackfin/gpio.h to see the GPIO map. | 712 | Refer to ./include/asm-blackfin/gpio.h to see the GPIO map. |
diff --git a/drivers/serial/bfin_5xx.c b/drivers/serial/bfin_5xx.c index af866ab3f5a1..69ac7007682e 100644 --- a/drivers/serial/bfin_5xx.c +++ b/drivers/serial/bfin_5xx.c | |||
@@ -579,7 +579,11 @@ static unsigned int bfin_serial_get_mctrl(struct uart_port *port) | |||
579 | if (uart->cts_pin < 0) | 579 | if (uart->cts_pin < 0) |
580 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | 580 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; |
581 | 581 | ||
582 | # ifdef BF54x | ||
583 | if (UART_GET_MSR(uart) & CTS) | ||
584 | # else | ||
582 | if (gpio_get_value(uart->cts_pin)) | 585 | if (gpio_get_value(uart->cts_pin)) |
586 | # endif | ||
583 | return TIOCM_DSR | TIOCM_CAR; | 587 | return TIOCM_DSR | TIOCM_CAR; |
584 | else | 588 | else |
585 | #endif | 589 | #endif |
@@ -594,9 +598,17 @@ static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) | |||
594 | return; | 598 | return; |
595 | 599 | ||
596 | if (mctrl & TIOCM_RTS) | 600 | if (mctrl & TIOCM_RTS) |
601 | # ifdef BF54x | ||
602 | UART_PUT_MCR(uart, UART_GET_MCR(uart) & ~MRTS); | ||
603 | # else | ||
597 | gpio_set_value(uart->rts_pin, 0); | 604 | gpio_set_value(uart->rts_pin, 0); |
605 | # endif | ||
598 | else | 606 | else |
607 | # ifdef BF54x | ||
608 | UART_PUT_MCR(uart, UART_GET_MCR(uart) | MRTS); | ||
609 | # else | ||
599 | gpio_set_value(uart->rts_pin, 1); | 610 | gpio_set_value(uart->rts_pin, 1); |
611 | # endif | ||
600 | #endif | 612 | #endif |
601 | } | 613 | } |
602 | 614 | ||
diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h index c459c4846469..7e6339f62a50 100644 --- a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h | |||
@@ -24,6 +24,8 @@ | |||
24 | #define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) | 24 | #define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) |
25 | #define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR)) | 25 | #define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR)) |
26 | #define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) | 26 | #define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) |
27 | #define UART_GET_MSR(uart) bfin_read16(((uart)->port.membase + OFFSET_MSR)) | ||
28 | #define UART_GET_MCR(uart) bfin_read16(((uart)->port.membase + OFFSET_MCR)) | ||
27 | 29 | ||
28 | #define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) | 30 | #define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) |
29 | #define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) | 31 | #define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) |
@@ -34,6 +36,7 @@ | |||
34 | #define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) | 36 | #define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) |
35 | #define UART_CLEAR_LSR(uart) bfin_write16(((uart)->port.membase + OFFSET_LSR), -1) | 37 | #define UART_CLEAR_LSR(uart) bfin_write16(((uart)->port.membase + OFFSET_LSR), -1) |
36 | #define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) | 38 | #define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) |
39 | #define UART_PUT_MCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_MCR),v) | ||
37 | 40 | ||
38 | #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) | 41 | #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) |
39 | # define CONFIG_SERIAL_BFIN_CTSRTS | 42 | # define CONFIG_SERIAL_BFIN_CTSRTS |