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authorAndrew Victor <andrew@sanpeople.com>2007-05-11 16:01:28 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-05-11 17:02:48 -0400
commitc53c9cf60e49119e97d38390849cac5b2f0a0981 (patch)
tree37615dedbbd8980b8357df47d90843eb86d017ff
parentc42dcb3dcfd3a473ab7c79c2ae91fc1c2e4dc5db (diff)
[ARM] 4331/3: Support for Micrel/Kendin KS8695 processor
Add core support for the Kendin/Micrel KS8695 processor family. It is an ARM922-T based SoC with integrated USART, 4-port Ethernet Switch, WAN Ethernet port, and optional PCI Host bridge, etc. http://www.micrel.com/page.do?page=product-info/sys_on_chip.jsp This patch is based on earlier patches from Lennert Buytenhek, Ben Dooks and Greg Ungerer posted to the arm-linux-kernel mailing list in March 2006; and Micrel's 2.6.9 port. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat
-rw-r--r--arch/arm/Kconfig13
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/mach-ks8695/Kconfig8
-rw-r--r--arch/arm/mach-ks8695/Makefile14
-rw-r--r--arch/arm/mach-ks8695/Makefile.boot8
-rw-r--r--arch/arm/mach-ks8695/cpu.c73
-rw-r--r--arch/arm/mach-ks8695/devices.c191
-rw-r--r--arch/arm/mach-ks8695/generic.h15
-rw-r--r--arch/arm/mach-ks8695/irq.c175
-rw-r--r--arch/arm/mach-ks8695/time.c114
-rw-r--r--arch/arm/mm/Kconfig6
-rw-r--r--include/asm-arm/arch-ks8695/debug-macro.S38
-rw-r--r--include/asm-arm/arch-ks8695/devices.h32
-rw-r--r--include/asm-arm/arch-ks8695/dma.h17
-rw-r--r--include/asm-arm/arch-ks8695/entry-macro.S53
-rw-r--r--include/asm-arm/arch-ks8695/hardware.h49
-rw-r--r--include/asm-arm/arch-ks8695/io.h19
-rw-r--r--include/asm-arm/arch-ks8695/irqs.h54
-rw-r--r--include/asm-arm/arch-ks8695/memory.h49
-rw-r--r--include/asm-arm/arch-ks8695/regs-gpio.h53
-rw-r--r--include/asm-arm/arch-ks8695/regs-hpna.h25
-rw-r--r--include/asm-arm/arch-ks8695/regs-irq.h41
-rw-r--r--include/asm-arm/arch-ks8695/regs-lan.h65
-rw-r--r--include/asm-arm/arch-ks8695/regs-mem.h89
-rw-r--r--include/asm-arm/arch-ks8695/regs-misc.h97
-rw-r--r--include/asm-arm/arch-ks8695/regs-pci.h53
-rw-r--r--include/asm-arm/arch-ks8695/regs-switch.h66
-rw-r--r--include/asm-arm/arch-ks8695/regs-sys.h34
-rw-r--r--include/asm-arm/arch-ks8695/regs-timer.h40
-rw-r--r--include/asm-arm/arch-ks8695/regs-uart.h92
-rw-r--r--include/asm-arm/arch-ks8695/regs-wan.h65
-rw-r--r--include/asm-arm/arch-ks8695/system.h48
-rw-r--r--include/asm-arm/arch-ks8695/timex.h20
-rw-r--r--include/asm-arm/arch-ks8695/uncompress.h37
-rw-r--r--include/asm-arm/arch-ks8695/vmalloc.h19
35 files changed, 1768 insertions, 5 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 52c209ef58b8..638f1d8080a9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -305,6 +305,12 @@ config ARCH_L7200
305 If you have any questions or comments about the Linux kernel port 305 If you have any questions or comments about the Linux kernel port
306 to this board, send e-mail to <sjhill@cotw.com>. 306 to this board, send e-mail to <sjhill@cotw.com>.
307 307
308config ARCH_KS8695
309 bool "Micrel/Kendin KS8695"
310 help
311 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
312 System-on-Chip devices.
313
308config ARCH_NS9XXX 314config ARCH_NS9XXX
309 bool "NetSilicon NS9xxx" 315 bool "NetSilicon NS9xxx"
310 help 316 help
@@ -451,6 +457,8 @@ source "arch/arm/mach-ns9xxx/Kconfig"
451 457
452source "arch/arm/mach-davinci/Kconfig" 458source "arch/arm/mach-davinci/Kconfig"
453 459
460source "arch/arm/mach-ks8695/Kconfig"
461
454# Definitions to make life easier 462# Definitions to make life easier
455config ARCH_ACORN 463config ARCH_ACORN
456 bool 464 bool
@@ -511,7 +519,7 @@ config ISA_DMA_API
511 bool 519 bool
512 520
513config PCI 521config PCI
514 bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX 522 bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695
515 help 523 help
516 Find out whether you have a PCI motherboard. PCI is the name of a 524 Find out whether you have a PCI motherboard. PCI is the name of a
517 bus system, i.e. the way the CPU talks to the other stuff inside 525 bus system, i.e. the way the CPU talks to the other stuff inside
@@ -680,7 +688,8 @@ config LEDS
680 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \ 688 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
681 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ 689 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
682 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \ 690 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
683 ARCH_AT91 || MACH_TRIZEPS4 || ARCH_DAVINCI 691 ARCH_AT91 || MACH_TRIZEPS4 || ARCH_DAVINCI || \
692 ARCH_KS8695
684 help 693 help
685 If you say Y here, the LEDs on your machine will be used 694 If you say Y here, the LEDs on your machine will be used
686 to provide useful information about your current system status. 695 to provide useful information about your current system status.
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index d568d86b0729..cbd5010d3bc3 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -136,6 +136,7 @@ endif
136 machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx 136 machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx
137 textofs-$(CONFIG_ARCH_NS9XXX) := 0x00108000 137 textofs-$(CONFIG_ARCH_NS9XXX) := 0x00108000
138 machine-$(CONFIG_ARCH_DAVINCI) := davinci 138 machine-$(CONFIG_ARCH_DAVINCI) := davinci
139 machine-$(CONFIG_ARCH_KS8695) := ks8695
139 140
140ifeq ($(CONFIG_ARCH_EBSA110),y) 141ifeq ($(CONFIG_ARCH_EBSA110),y)
141# This is what happens if you forget the IOCS16 line. 142# This is what happens if you forget the IOCS16 line.
diff --git a/arch/arm/mach-ks8695/Kconfig b/arch/arm/mach-ks8695/Kconfig
new file mode 100644
index 000000000000..44d14aa0baa7
--- /dev/null
+++ b/arch/arm/mach-ks8695/Kconfig
@@ -0,0 +1,8 @@
1if ARCH_KS8695
2
3menu "Kendin/Micrel KS8695 Implementations"
4
5
6endmenu
7
8endif
diff --git a/arch/arm/mach-ks8695/Makefile b/arch/arm/mach-ks8695/Makefile
new file mode 100644
index 000000000000..0a0f496e8ccf
--- /dev/null
+++ b/arch/arm/mach-ks8695/Makefile
@@ -0,0 +1,14 @@
1# arch/arm/mach-ks8695/Makefile
2#
3# Makefile for KS8695 architecture support
4#
5
6obj-y := cpu.o irq.o time.o devices.o
7obj-m :=
8obj-n :=
9obj- :=
10
11# PCI support is optional
12#obj-$(CONFIG_PCI) += pci.o
13
14# Board-specific support
diff --git a/arch/arm/mach-ks8695/Makefile.boot b/arch/arm/mach-ks8695/Makefile.boot
new file mode 100644
index 000000000000..48eb2cb3ac77
--- /dev/null
+++ b/arch/arm/mach-ks8695/Makefile.boot
@@ -0,0 +1,8 @@
1# Note: the following conditions must always be true:
2# ZRELADDR == virt_to_phys(TEXTADDR)
3# PARAMS_PHYS must be within 4MB of ZRELADDR
4# INITRD_PHYS must be in RAM
5
6 zreladdr-y := 0x00008000
7params_phys-y := 0x00000100
8initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-ks8695/cpu.c b/arch/arm/mach-ks8695/cpu.c
new file mode 100644
index 000000000000..407d255e42bf
--- /dev/null
+++ b/arch/arm/mach-ks8695/cpu.c
@@ -0,0 +1,73 @@
1/*
2 * arch/arm/mach-ks8695/cpu.c
3 *
4 * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
5 * Copyright (C) 2006 Simtec Electronics
6 *
7 * KS8695 CPU support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/init.h>
27
28#include <asm/hardware.h>
29#include <asm/io.h>
30#include <asm/mach/arch.h>
31#include <asm/mach/map.h>
32
33#include <asm/arch/regs-sys.h>
34#include <asm/arch/regs-misc.h>
35
36
37static struct __initdata map_desc ks8695_io_desc[] = {
38 {
39 .virtual = KS8695_IO_VA,
40 .pfn = __phys_to_pfn(KS8695_IO_PA),
41 .length = KS8695_IO_SIZE,
42 .type = MT_DEVICE,
43 }
44};
45
46static void __init ks8695_processor_info(void)
47{
48 unsigned long id, rev;
49
50 id = __raw_readl(KS8695_MISC_VA + KS8695_DID);
51 rev = __raw_readl(KS8695_MISC_VA + KS8695_RID);
52
53 printk("KS8695 ID=%04lx SubID=%02lx Revision=%02lx\n", (id & DID_ID), (rev & RID_SUBID), (rev & RID_REVISION));
54}
55
56static unsigned int sysclk[8] = { 125000000, 100000000, 62500000, 50000000, 41700000, 33300000, 31300000, 25000000 };
57static unsigned int cpuclk[8] = { 166000000, 166000000, 83000000, 83000000, 55300000, 55300000, 41500000, 41500000 };
58
59static void __init ks8695_clock_info(void)
60{
61 unsigned int scdc = __raw_readl(KS8695_SYS_VA + KS8695_CLKCON) & CLKCON_SCDC;
62
63 printk("Clocks: System %u MHz, CPU %u MHz\n",
64 sysclk[scdc] / 1000000, cpuclk[scdc] / 1000000);
65}
66
67void __init ks8695_map_io(void)
68{
69 iotable_init(ks8695_io_desc, ARRAY_SIZE(ks8695_io_desc));
70
71 ks8695_processor_info();
72 ks8695_clock_info();
73}
diff --git a/arch/arm/mach-ks8695/devices.c b/arch/arm/mach-ks8695/devices.c
new file mode 100644
index 000000000000..386593f8ac65
--- /dev/null
+++ b/arch/arm/mach-ks8695/devices.c
@@ -0,0 +1,191 @@
1/*
2 * arch/arm/mach-ks8695/devices.c
3 *
4 * Copyright (C) 2006 Andrew Victor
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <asm/mach/arch.h>
21#include <asm/mach/map.h>
22
23#include <linux/platform_device.h>
24
25#include <asm/arch/regs-wan.h>
26#include <asm/arch/regs-lan.h>
27#include <asm/arch/regs-hpna.h>
28
29
30/* --------------------------------------------------------------------
31 * Ethernet
32 * -------------------------------------------------------------------- */
33
34#if defined(CONFIG_ARM_KS8695_ETHER) || defined(CONFIG_ARM_KS8695_ETHER_MODULE)
35static u64 eth_dmamask = 0xffffffffUL;
36
37static struct resource ks8695_wan_resources[] = {
38 [0] = {
39 .start = KS8695_WAN_VA,
40 .end = KS8695_WAN_VA + 0x00ff,
41 .flags = IORESOURCE_MEM,
42 },
43 [1] = {
44 .name = "WAN RX",
45 .start = KS8695_IRQ_WAN_RX_STATUS,
46 .end = KS8695_IRQ_WAN_RX_STATUS,
47 .flags = IORESOURCE_IRQ,
48 },
49 [2] = {
50 .name = "WAN TX",
51 .start = KS8695_IRQ_WAN_TX_STATUS,
52 .end = KS8695_IRQ_WAN_TX_STATUS,
53 .flags = IORESOURCE_IRQ,
54 },
55 [3] = {
56 .name = "WAN Link",
57 .start = KS8695_IRQ_WAN_LINK,
58 .end = KS8695_IRQ_WAN_LINK,
59 .flags = IORESOURCE_IRQ,
60 },
61};
62
63static struct platform_device ks8695_wan_device = {
64 .name = "ks8695_ether",
65 .id = 0,
66 .dev = {
67 .dma_mask = &eth_dmamask,
68 .coherent_dma_mask = 0xffffffff,
69 },
70 .resource = ks8695_wan_resources,
71 .num_resources = ARRAY_SIZE(ks8695_wan_resources),
72};
73
74
75static struct resource ks8695_lan_resources[] = {
76 [0] = {
77 .start = KS8695_LAN_VA,
78 .end = KS8695_LAN_VA + 0x00ff,
79 .flags = IORESOURCE_MEM,
80 },
81 [1] = {
82 .name = "LAN RX",
83 .start = KS8695_IRQ_LAN_RX_STATUS,
84 .end = KS8695_IRQ_LAN_RX_STATUS,
85 .flags = IORESOURCE_IRQ,
86 },
87 [2] = {
88 .name = "LAN TX",
89 .start = KS8695_IRQ_LAN_TX_STATUS,
90 .end = KS8695_IRQ_LAN_TX_STATUS,
91 .flags = IORESOURCE_IRQ,
92 },
93};
94
95static struct platform_device ks8695_lan_device = {
96 .name = "ks8695_ether",
97 .id = 1,
98 .dev = {
99 .dma_mask = &eth_dmamask,
100 .coherent_dma_mask = 0xffffffff,
101 },
102 .resource = ks8695_lan_resources,
103 .num_resources = ARRAY_SIZE(ks8695_lan_resources),
104};
105
106
107static struct resource ks8695_hpna_resources[] = {
108 [0] = {
109 .start = KS8695_HPNA_VA,
110 .end = KS8695_HPNA_VA + 0x00ff,
111 .flags = IORESOURCE_MEM,
112 },
113 [1] = {
114 .name = "HPNA RX",
115 .start = KS8695_IRQ_HPNA_RX_STATUS,
116 .end = KS8695_IRQ_HPNA_RX_STATUS,
117 .flags = IORESOURCE_IRQ,
118 },
119 [2] = {
120 .name = "HPNA TX",
121 .start = KS8695_IRQ_HPNA_TX_STATUS,
122 .end = KS8695_IRQ_HPNA_TX_STATUS,
123 .flags = IORESOURCE_IRQ,
124 },
125};
126
127static struct platform_device ks8695_hpna_device = {
128 .name = "ks8695_ether",
129 .id = 2,
130 .dev = {
131 .dma_mask = &eth_dmamask,
132 .coherent_dma_mask = 0xffffffff,
133 },
134 .resource = ks8695_hpna_resources,
135 .num_resources = ARRAY_SIZE(ks8695_hpna_resources),
136};
137
138void __init ks8695_add_device_wan(void)
139{
140 platform_device_register(&ks8695_wan_device);
141}
142
143void __init ks8695_add_device_lan(void)
144{
145 platform_device_register(&ks8695_lan_device);
146}
147
148void __init ks8696_add_device_hpna(void)
149{
150 platform_device_register(&ks8695_hpna_device);
151}
152#else
153void __init ks8695_add_device_wan(void) {}
154void __init ks8695_add_device_lan(void) {}
155void __init ks8696_add_device_hpna(void) {}
156#endif
157
158
159/* --------------------------------------------------------------------
160 * Watchdog
161 * -------------------------------------------------------------------- */
162
163#if defined(CONFIG_KS8695_WATCHDOG) || defined(CONFIG_KS8695_WATCHDOG_MODULE)
164static struct platform_device ks8695_wdt_device = {
165 .name = "ks8695_wdt",
166 .id = -1,
167 .num_resources = 0,
168};
169
170static void __init ks8695_add_device_watchdog(void)
171{
172 platform_device_register(&ks8695_wdt_device);
173}
174#else
175static void __init ks8695_add_device_watchdog(void) {}
176#endif
177
178
179/* -------------------------------------------------------------------- */
180
181/*
182 * These devices are always present and don't need any board-specific
183 * setup.
184 */
185static int __init ks8695_add_standard_devices(void)
186{
187 ks8695_add_device_watchdog();
188 return 0;
189}
190
191arch_initcall(ks8695_add_standard_devices);
diff --git a/arch/arm/mach-ks8695/generic.h b/arch/arm/mach-ks8695/generic.h
new file mode 100644
index 000000000000..2fbfab8d5fae
--- /dev/null
+++ b/arch/arm/mach-ks8695/generic.h
@@ -0,0 +1,15 @@
1/*
2 * arch/arm/mach-ks8695/generic.h
3 *
4 * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
5 * Copyright (C) 2006 Simtec Electronics
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11*/
12
13extern __init void ks8695_map_io(void);
14extern __init void ks8695_init_irq(void);
15extern struct sys_timer ks8695_timer;
diff --git a/arch/arm/mach-ks8695/irq.c b/arch/arm/mach-ks8695/irq.c
new file mode 100644
index 000000000000..2407bba00547
--- /dev/null
+++ b/arch/arm/mach-ks8695/irq.c
@@ -0,0 +1,175 @@
1/*
2 * arch/arm/mach-ks8695/irq.c
3 *
4 * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
5 * Copyright (C) 2006 Simtec Electronics
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/interrupt.h>
25#include <linux/ioport.h>
26#include <linux/ptrace.h>
27#include <linux/sysdev.h>
28
29#include <asm/hardware.h>
30#include <asm/irq.h>
31#include <asm/io.h>
32
33#include <asm/mach/irq.h>
34
35#include <asm/arch/regs-irq.h>
36#include <asm/arch/regs-gpio.h>
37
38static void ks8695_irq_mask(unsigned int irqno)
39{
40 unsigned long inten;
41
42 inten = __raw_readl(KS8695_IRQ_VA + KS8695_INTEN);
43 inten &= ~(1 << irqno);
44
45 __raw_writel(inten, KS8695_IRQ_VA + KS8695_INTEN);
46}
47
48static void ks8695_irq_unmask(unsigned int irqno)
49{
50 unsigned long inten;
51
52 inten = __raw_readl(KS8695_IRQ_VA + KS8695_INTEN);
53 inten |= (1 << irqno);
54
55 __raw_writel(inten, KS8695_IRQ_VA + KS8695_INTEN);
56}
57
58static void ks8695_irq_ack(unsigned int irqno)
59{
60 __raw_writel((1 << irqno), KS8695_IRQ_VA + KS8695_INTST);
61}
62
63
64static struct irq_chip ks8695_irq_level_chip;
65static struct irq_chip ks8695_irq_edge_chip;
66
67
68static int ks8695_irq_set_type(unsigned int irqno, unsigned int type)
69{
70 unsigned long ctrl, mode;
71 unsigned short level_triggered = 0;
72
73 ctrl = __raw_readl(KS8695_GPIO_VA + KS8695_IOPC);
74
75 switch (type) {
76 case IRQT_HIGH:
77 mode = IOPC_TM_HIGH;
78 level_triggered = 1;
79 break;
80 case IRQT_LOW:
81 mode = IOPC_TM_LOW;
82 level_triggered = 1;
83 break;
84 case IRQT_RISING:
85 mode = IOPC_TM_RISING;
86 break;
87 case IRQT_FALLING:
88 mode = IOPC_TM_FALLING;
89 break;
90 case IRQT_BOTHEDGE:
91 mode = IOPC_TM_EDGE;
92 break;
93 default:
94 return -EINVAL;
95 }
96
97 switch (irqno) {
98 case KS8695_IRQ_EXTERN0:
99 ctrl &= ~IOPC_IOEINT0TM;
100 ctrl |= IOPC_IOEINT0_MODE(mode);
101 break;
102 case KS8695_IRQ_EXTERN1:
103 ctrl &= ~IOPC_IOEINT1TM;
104 ctrl |= IOPC_IOEINT1_MODE(mode);
105 break;
106 case KS8695_IRQ_EXTERN2:
107 ctrl &= ~IOPC_IOEINT2TM;
108 ctrl |= IOPC_IOEINT2_MODE(mode);
109 break;
110 case KS8695_IRQ_EXTERN3:
111 ctrl &= ~IOPC_IOEINT3TM;
112 ctrl |= IOPC_IOEINT3_MODE(mode);
113 break;
114 default:
115 return -EINVAL;
116 }
117
118 if (level_triggered) {
119 set_irq_chip(irqno, &ks8695_irq_level_chip);
120 set_irq_handler(irqno, handle_level_irq);
121 }
122 else {
123 set_irq_chip(irqno, &ks8695_irq_edge_chip);
124 set_irq_handler(irqno, handle_edge_irq);
125 }
126
127 __raw_writel(ctrl, KS8695_GPIO_VA + KS8695_IOPC);
128 return 0;
129}
130
131static struct irq_chip ks8695_irq_level_chip = {
132 .ack = ks8695_irq_mask,
133 .mask = ks8695_irq_mask,
134 .unmask = ks8695_irq_unmask,
135 .set_type = ks8695_irq_set_type,
136};
137
138static struct irq_chip ks8695_irq_edge_chip = {
139 .ack = ks8695_irq_ack,
140 .mask = ks8695_irq_mask,
141 .unmask = ks8695_irq_unmask,
142 .set_type = ks8695_irq_set_type,
143};
144
145void __init ks8695_init_irq(void)
146{
147 unsigned int irq;
148
149 /* Disable all interrupts initially */
150 __raw_writel(0, KS8695_IRQ_VA + KS8695_INTMC);
151 __raw_writel(0, KS8695_IRQ_VA + KS8695_INTEN);
152
153 for (irq = 0; irq < NR_IRQS; irq++) {
154 switch (irq) {
155 /* Level-triggered interrupts */
156 case KS8695_IRQ_BUS_ERROR:
157 case KS8695_IRQ_UART_MODEM_STATUS:
158 case KS8695_IRQ_UART_LINE_STATUS:
159 case KS8695_IRQ_UART_RX:
160 case KS8695_IRQ_COMM_TX:
161 case KS8695_IRQ_COMM_RX:
162 set_irq_chip(irq, &ks8695_irq_level_chip);
163 set_irq_handler(irq, handle_level_irq);
164 break;
165
166 /* Edge-triggered interrupts */
167 default:
168 ks8695_irq_ack(irq); /* clear pending bit */
169 set_irq_chip(irq, &ks8695_irq_edge_chip);
170 set_irq_handler(irq, handle_edge_irq);
171 }
172
173 set_irq_flags(irq, IRQF_VALID);
174 }
175}
diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c
new file mode 100644
index 000000000000..d2c86e4a72eb
--- /dev/null
+++ b/arch/arm/mach-ks8695/time.c
@@ -0,0 +1,114 @@
1/*
2 * arch/arm/mach-ks8695/time.c
3 *
4 * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
5 * Copyright (C) 2006 Simtec Electronics
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/kernel.h>
26#include <linux/sched.h>
27
28#include <asm/io.h>
29#include <asm/mach/time.h>
30
31#include <asm/arch/regs-timer.h>
32#include <asm/arch/regs-irq.h>
33
34#include "generic.h"
35
36/*
37 * Returns number of ms since last clock interrupt. Note that interrupts
38 * will have been disabled by do_gettimeoffset()
39 */
40static unsigned long ks8695_gettimeoffset (void)
41{
42 unsigned long elapsed, tick2, intpending;
43
44 /*
45 * Get the current number of ticks. Note that there is a race
46 * condition between us reading the timer and checking for an
47 * interrupt. We solve this by ensuring that the counter has not
48 * reloaded between our two reads.
49 */
50 elapsed = __raw_readl(KS8695_TMR_VA + KS8695_T1TC) + __raw_readl(KS8695_TMR_VA + KS8695_T1PD);
51 do {
52 tick2 = elapsed;
53 intpending = __raw_readl(KS8695_IRQ_VA + KS8695_INTST) & (1 << KS8695_IRQ_TIMER1);
54 elapsed = __raw_readl(KS8695_TMR_VA + KS8695_T1TC) + __raw_readl(KS8695_TMR_VA + KS8695_T1PD);
55 } while (elapsed > tick2);
56
57 /* Convert to number of ticks expired (not remaining) */
58 elapsed = (CLOCK_TICK_RATE / HZ) - elapsed;
59
60 /* Is interrupt pending? If so, then timer has been reloaded already. */
61 if (intpending)
62 elapsed += (CLOCK_TICK_RATE / HZ);
63
64 /* Convert ticks to usecs */
65 return (unsigned long)(elapsed * (tick_nsec / 1000)) / LATCH;
66}
67
68/*
69 * IRQ handler for the timer.
70 */
71static irqreturn_t ks8695_timer_interrupt(int irq, void *dev_id)
72{
73 write_seqlock(&xtime_lock);
74 timer_tick();
75 write_sequnlock(&xtime_lock);
76
77 return IRQ_HANDLED;
78}
79
80static struct irqaction ks8695_timer_irq = {
81 .name = "ks8695_tick",
82 .flags = IRQF_DISABLED | IRQF_TIMER,
83 .handler = ks8695_timer_interrupt,
84};
85
86static void ks8695_timer_setup(void)
87{
88 unsigned long tmout = CLOCK_TICK_RATE / HZ;
89 unsigned long tmcon;
90
91 /* disable timer1 */
92 tmcon = __raw_readl(KS8695_TMR_VA + KS8695_TMCON);
93 __raw_writel(tmcon & ~TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON);
94
95 __raw_writel(tmout / 2, KS8695_TMR_VA + KS8695_T1TC);
96 __raw_writel(tmout / 2, KS8695_TMR_VA + KS8695_T1PD);
97
98 /* re-enable timer1 */
99 __raw_writel(tmcon | TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON);
100}
101
102static void __init ks8695_timer_init (void)
103{
104 ks8695_timer_setup();
105
106 /* Enable timer interrupts */
107 setup_irq(KS8695_IRQ_TIMER1, &ks8695_timer_irq);
108}
109
110struct sys_timer ks8695_timer = {
111 .init = ks8695_timer_init,
112 .offset = ks8695_gettimeoffset,
113 .resume = ks8695_timer_setup,
114};
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index b8320a12e6b7..15f0284010ca 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -131,8 +131,8 @@ config CPU_ARM920T
131# ARM922T 131# ARM922T
132config CPU_ARM922T 132config CPU_ARM922T
133 bool "Support ARM922T processor" if ARCH_INTEGRATOR 133 bool "Support ARM922T processor" if ARCH_INTEGRATOR
134 depends on ARCH_LH7A40X || ARCH_INTEGRATOR 134 depends on ARCH_LH7A40X || ARCH_INTEGRATOR || ARCH_KS8695
135 default y if ARCH_LH7A40X 135 default y if ARCH_LH7A40X || ARCH_KS8695
136 select CPU_32v4T 136 select CPU_32v4T
137 select CPU_ABRT_EV4T 137 select CPU_ABRT_EV4T
138 select CPU_CACHE_V4WT 138 select CPU_CACHE_V4WT
@@ -143,7 +143,7 @@ config CPU_ARM922T
143 help 143 help
144 The ARM922T is a version of the ARM920T, but with smaller 144 The ARM922T is a version of the ARM920T, but with smaller
145 instruction and data caches. It is used in Altera's 145 instruction and data caches. It is used in Altera's
146 Excalibur XA device family. 146 Excalibur XA device family and Micrel's KS8695 Centaur.
147 147
148 Say Y if you want support for the ARM922T processor. 148 Say Y if you want support for the ARM922T processor.
149 Otherwise, say N. 149 Otherwise, say N.
diff --git a/include/asm-arm/arch-ks8695/debug-macro.S b/include/asm-arm/arch-ks8695/debug-macro.S
new file mode 100644
index 000000000000..cd5f2fb1f06e
--- /dev/null
+++ b/include/asm-arm/arch-ks8695/debug-macro.S
@@ -0,0 +1,38 @@
1/*
2 * include/asm-arm/arch-ks8695/debug-macro.S
3 *
4 * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
5 * Copyright (C) 2006 Simtec Electronics
6 *
7 * KS8695 - Debug macros
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <asm/hardware.h>
15#include <asm/arch/regs-uart.h>
16
17 .macro addruart, rx
18 mrc p15, 0, \rx, c1, c0
19 tst \rx, #1 @ MMU enabled?
20 ldreq \rx, =KS8695_UART_PA @ physical base address
21 ldrne \rx, =KS8695_UART_VA @ virtual base address
22 .endm
23
24 .macro senduart, rd, rx
25 str \rd, [\rx, #KS8695_URTH] @ Write to Transmit Holding Register
26 .endm
27
28 .macro busyuart, rd, rx
291001: ldr \rd, [\rx, #KS8695_URLS] @ Read Line Status Register
30 tst \rd, #URLS_URTE @ Holding & Shift registers empty?
31 beq 1001b
32 .endm
33
34 .macro waituart, rd, rx
351001: ldr \rd, [\rx, #KS8695_URLS] @ Read Line Status Register
36 tst \rd, #URLS_URTHRE @ Holding Register empty?
37 beq 1001b
38 .endm
diff --git a/include/asm-arm/arch-ks8695/devices.h b/include/asm-arm/arch-ks8695/devices.h
new file mode 100644
index 000000000000..b0364dce463f
--- /dev/null
+++ b/include/asm-arm/arch-ks8695/devices.h
@@ -0,0 +1,32 @@
1/*
2 * include/asm-arm/arch-ks8695/devices.h
3 *
4 * Copyright (C) 2006 Andrew Victor
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_DEVICES_H
12#define __ASM_ARCH_DEVICES_H
13
14#include <linux/pci.h>
15
16 /* Ethernet */
17extern void __init ks8695_add_device_wan(void);
18extern void __init ks8695_add_device_lan(void);
19extern void __init ks8695_add_device_hpna(void);
20
21 /* PCI */
22#define KS8695_MODE_PCI 0
23#define KS8695_MODE_MINIPCI 1
24#define KS8695_MODE_CARDBUS 2
25
26struct ks8695_pci_cfg {
27 short mode;
28 int (*map_irq)(struct pci_dev *, u8, u8);
29};
30extern __init void ks8695_init_pci(struct ks8695_pci_cfg *);
31
32#endif
diff --git a/include/asm-arm/arch-ks8695/dma.h b/include/asm-arm/arch-ks8695/dma.h
new file mode 100644
index 000000000000..e5159ed42a4b
--- /dev/null
+++ b/include/asm-arm/arch-ks8695/dma.h
@@ -0,0 +1,17 @@
1/*
2 * include/asm-arm/arch-ks8695/dma.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
diff --git a/include/asm-arm/arch-ks8695/entry-macro.S b/include/asm-arm/arch-ks8695/entry-macro.S
new file mode 100644
index 000000000000..e34bdf85920e
--- /dev/null
+++ b/include/asm-arm/arch-ks8695/entry-macro.S
@@ -0,0 +1,53 @@
1/*
2 * include/asm-arm/arch-ks8695/entry-macro.S
3 *
4 * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
5 * Copyright (C) 2006 Simtec Electronics
6 *
7 * Low-level IRQ helper macros for KS8695
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12*/
13
14#include <asm/hardware.h>
15#include <asm/arch/regs-irq.h>
16
17 .macro disable_fiq
18 .endm
19
20 .macro get_irqnr_preamble, base, tmp
21 ldr \base, =KS8695_IRQ_VA @ Base address of interrupt controller
22 .endm
23
24 .macro arch_ret_to_user, tmp1, tmp2
25 .endm
26
27 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
28 ldr \irqstat, [\base, #KS8695_INTMS] @ Mask Status register
29
30 teq \irqstat, #0
31 beq 1001f
32
33 mov \irqnr, #0
34
35 tst \irqstat, #0xff
36 moveq \irqstat, \irqstat, lsr #8
37 addeq \irqnr, \irqnr, #8
38 tsteq \irqstat, #0xff
39 moveq \irqstat, \irqstat, lsr #8
40 addeq \irqnr, \irqnr, #8
41 tsteq \irqstat, #0xff
42 moveq \irqstat, \irqstat, lsr #8
43 addeq \irqnr, \irqnr, #8
44 tst \irqstat, #0x0f
45 moveq \irqstat, \irqstat, lsr #4
46 addeq \irqnr, \irqnr, #4
47 tst \irqstat, #0x03
48 moveq \irqstat, \irqstat, lsr #2
49 addeq \irqnr, \irqnr, #2
50 tst \irqstat, #0x01
51 addeqs \irqnr, \irqnr, #1
521001:
53 .endm
diff --git a/include/asm-arm/arch-ks8695/hardware.h b/include/asm-arm/arch-ks8695/hardware.h
new file mode 100644
index 000000000000..cb732bff3288
--- /dev/null
+++ b/include/asm-arm/arch-ks8695/hardware.h
@@ -0,0 +1,49 @@
1/*
2 * include/asm-arm/arch-ks8695/hardware.h
3 *
4 * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
5 * Copyright (C) 2006 Simtec Electronics
6 *
7 * KS8695 - Memory Map definitions
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_ARCH_HARDWARE_H
15#define __ASM_ARCH_HARDWARE_H
16
17#include <asm/sizes.h>
18
19/*
20 * Physical RAM address.
21 */
22#define KS8695_SDRAM_PA 0x00000000
23
24
25/*
26 * We map an entire MiB with the System Configuration Registers in even
27 * though only 64KiB is needed. This makes it easier for use with the
28 * head debug code as the initial MMU setup only deals in L1 sections.
29 */
30#define KS8695_IO_PA 0x03F00000
31#define KS8695_IO_VA 0xF0000000
32#define KS8695_IO_SIZE SZ_1M
33
34#define KS8695_PCIMEM_PA 0x60000000
35#define KS8695_PCIMEM_SIZE SZ_512M
36
37#define KS8695_PCIIO_PA 0x80000000
38#define KS8695_PCIIO_SIZE SZ_64K
39
40
41/*
42 * PCI support
43 */
44#define pcibios_assign_all_busses() 1
45
46#define PCIBIOS_MIN_IO 0
47#define PCIBIOS_MIN_MEM 0
48
49#endif
diff --git a/include/asm-arm/arch-ks8695/io.h b/include/asm-arm/arch-ks8695/io.h
new file mode 100644
index 000000000000..8edc4bd6aadf
--- /dev/null
+++ b/include/asm-arm/arch-ks8695/io.h
@@ -0,0 +1,19 @@
1/*
2 * include/asm-arm/arch-ks8695/io.h
3 *
4 * Copyright (C) 2006 Andrew Victor
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARCH_IO_H
12#define __ASM_ARCH_IO_H
13
14#define IO_SPACE_LIMIT 0xffffffff
15
16#define __io(a) ((void __iomem *)(a))
17#define __mem_pci(a) (a)
18
19#endif
diff --git a/include/asm-arm/arch-ks8695/irqs.h b/include/asm-arm/arch-ks8695/irqs.h
new file mode 100644
index 000000000000..8b1c4fe96a81
--- /dev/null
+++ b/include/asm-arm/arch-ks8695/irqs.h
@@ -0,0 +1,54 @@
1/*
2 * linux/include/asm-arm/arch-ks8695/irqs.h
3 *
4 * Copyright (C) 2006 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __ASM_ARCH_IRQS_H
13#define __ASM_ARCH_IRQS_H
14
15
16#define NR_IRQS 32
17
18/*
19 * IRQ definitions
20 */
21#define KS8695_IRQ_COMM_RX 0
22#define KS8695_IRQ_COMM_TX 1
23#define KS8695_IRQ_EXTERN0 2
24#define KS8695_IRQ_EXTERN1 3
25#define KS8695_IRQ_EXTERN2 4
26#define KS8695_IRQ_EXTERN3 5
27#define KS8695_IRQ_TIMER0 6
28#define KS8695_IRQ_TIMER1 7
29#define KS8695_IRQ_UART_TX 8
30#define KS8695_IRQ_UART_RX 9
31#define KS8695_IRQ_UART_LINE_STATUS 10
32#define KS8695_IRQ_UART_MODEM_STATUS 11
33#define KS8695_IRQ_LAN_RX_STOP 12
34#define KS8695_IRQ_LAN_TX_STOP 13
35#define KS8695_IRQ_LAN_RX_BUF 14
36#define KS8695_IRQ_LAN_TX_BUF 15
37#define KS8695_IRQ_LAN_RX_STATUS 16
38#define KS8695_IRQ_LAN_TX_STATUS 17
39#define KS8695_IRQ_HPNA_RX_STOP 18
40#define KS8695_IRQ_HPNA_TX_STOP 19
41#define KS8695_IRQ_HPNA_RX_BUF 20
42#define KS8695_IRQ_HPNA_TX_BUF 21
43#define KS8695_IRQ_HPNA_RX_STATUS 22
44#define KS8695_IRQ_HPNA_TX_STATUS 23
45#define KS8695_IRQ_BUS_ERROR 24
46#define KS8695_IRQ_WAN_RX_STOP 25
47#define KS8695_IRQ_WAN_TX_STOP 26
48#define KS8695_IRQ_WAN_RX_BUF 27
49#define KS8695_IRQ_WAN_TX_BUF 28
50#define KS8695_IRQ_WAN_RX_STATUS 29
51#define KS8695_IRQ_WAN_TX_STATUS 30
52#define KS8695_IRQ_WAN_LINK 31
53
54#endif
diff --git a/include/asm-arm/arch-ks8695/memory.h b/include/asm-arm/arch-ks8695/memory.h
new file mode 100644
index 000000000000..24f6a6e4a302
--- /dev/null
+++ b/include/asm-arm/arch-ks8695/memory.h
@@ -0,0 +1,49 @@
1/*
2 * include/asm-arm/arch-ks8695/memory.h
3 *
4 * Copyright (C) 2006 Andrew Victor
5 *
6 * KS8695 Memory definitions
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#ifndef __ASM_ARCH_MEMORY_H
14#define __ASM_ARCH_MEMORY_H
15
16#include <asm/hardware.h>
17
18/*
19 * Physical SRAM offset.
20 */
21#define PHYS_OFFSET KS8695_SDRAM_PA
22
23#ifndef __ASSEMBLY__
24
25#ifdef CONFIG_PCI
26
27/* PCI mappings */
28#define __virt_to_bus(x) ((x) - PAGE_OFFSET + KS8695_PCIMEM_PA)
29#define __bus_to_virt(x) ((x) - KS8695_PCIMEM_PA + PAGE_OFFSET)
30
31/* Platform-bus mapping */
32extern struct bus_type platform_bus_type;
33#define is_lbus_device(dev) (dev && dev->bus == &platform_bus_type)
34#define __arch_dma_to_virt(dev, x) ({ is_lbus_device(dev) ? \
35 __phys_to_virt(x) : __bus_to_virt(x); })
36#define __arch_virt_to_dma(dev, x) ({ is_lbus_device(dev) ? \
37 (dma_addr_t)__virt_to_phys(x) : (dma_addr_t)__virt_to_bus(x); })
38#define __arch_page_to_dma(dev, x) __arch_virt_to_dma(dev, page_address(x))
39
40#else
41
42#define __virt_to_bus(x) __virt_to_phys(x)
43#define __bus_to_virt(x) __phys_to_virt(x)
44
45#endif
46
47#endif
48
49#endif
diff --git a/include/asm-arm/arch-ks8695/regs-gpio.h b/include/asm-arm/arch-ks8695/regs-gpio.h
new file mode 100644
index 000000000000..57fcf9fc82e4
--- /dev/null
+++ b/include/asm-arm/arch-ks8695/regs-gpio.h
@@ -0,0 +1,53 @@
1/*
2 * include/asm-arm/arch-ks8695/regs-gpio.h
3 *
4 * Copyright (C) 2007 Andrew Victor
5 *
6 * KS8695 - GPIO control registers and bit definitions.
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#ifndef KS8695_GPIO_H
14#define KS8695_GPIO_H
15
16#define KS8695_GPIO_OFFSET (0xF0000 + 0xE600)
17#define KS8695_GPIO_VA (KS8695_IO_VA + KS8695_GPIO_OFFSET)
18#define KS8695_GPIO_PA (KS8695_IO_PA + KS8695_GPIO_OFFSET)
19
20
21#define KS8695_IOPM (0x00) /* I/O Port Mode Register */
22#define KS8695_IOPC (0x04) /* I/O Port Control Register */
23#define KS8695_IOPD (0x08) /* I/O Port Data Register */
24
25
26/* Port Mode Register */
27#define IOPM_(x) (1 << (x)) /* Mode for GPIO Pin x */
28
29/* Port Control Register */
30#define IOPC_IOTIM1EN (1 << 17) /* GPIO Pin for Timer1 Enable */
31#define IOPC_IOTIM0EN (1 << 16) /* GPIO Pin for Timer0 Enable */
32#define IOPC_IOEINT3EN (1 << 15) /* GPIO Pin for External/Soft Interrupt 3 Enable */
33#define IOPC_IOEINT3TM (7 << 12) /* GPIO Pin for External/Soft Interrupt 3 Trigger Mode */
34#define IOPC_IOEINT3_MODE(x) ((x) << 12)
35#define IOPC_IOEINT2EN (1 << 11) /* GPIO Pin for External/Soft Interrupt 2 Enable */
36#define IOPC_IOEINT2TM (7 << 8) /* GPIO Pin for External/Soft Interrupt 2 Trigger Mode */
37#define IOPC_IOEINT2_MODE(x) ((x) << 8)
38#define IOPC_IOEINT1EN (1 << 7) /* GPIO Pin for External/Soft Interrupt 1 Enable */
39#define IOPC_IOEINT1TM (7 << 4) /* GPIO Pin for External/Soft Interrupt 1 Trigger Mode */
40#define IOPC_IOEINT1_MODE(x) ((x) << 4)
41#define IOPC_IOEINT0EN (1 << 3) /* GPIO Pin for External/Soft Interrupt 0 Enable */
42#define IOPC_IOEINT0TM (7 << 0) /* GPIO Pin for External/Soft Interrupt 0 Trigger Mode */
43#define IOPC_IOEINT0_MODE(x) ((x) << 0)
44
45 /* Trigger Modes */
46#define IOPC_TM_LOW (0) /* Level Detection (Active Low) */
47#define IOPC_TM_HIGH (1) /* Level Detection (Active High) */
48#define IOPC_TM_RISING (2) /* Rising Edge Detection */
49#define IOPC_TM_FALLING (4) /* Falling Edge Detection */
50#define IOPC_TM_EDGE (6) /* Both Edge Detection */
51
52
53#endif
diff --git a/include/asm-arm/arch-ks8695/regs-hpna.h b/include/asm-arm/arch-ks8695/regs-hpna.h
new file mode 100644
index 000000000000..14091cdec103
--- /dev/null
+++ b/include/asm-arm/arch-ks8695/regs-hpna.h
@@ -0,0 +1,25 @@
1/*
2 * include/asm-arm/arch-ks8695/regs-wan.h
3 *
4 * Copyright (C) 2006 Andrew Victor
5 *
6 * KS8695 - HPNA Registers and bit definitions.
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#ifndef KS8695_HPNA_H
14#define KS8695_HPNA_H
15
16#define KS8695_HPNA_OFFSET (0xF0000 + 0xA000)
17#define KS8695_HPNA_VA (KS8695_IO_VA + KS8695_HPNA_OFFSET)
18#define KS8695_HPNA_PA (KS8695_IO_PA + KS8695_HPNA_OFFSET)
19
20
21/*
22 * HPNA registers
23 */
24
25#endif
diff --git a/include/asm-arm/arch-ks8695/regs-irq.h b/include/asm-arm/arch-ks8695/regs-irq.h
new file mode 100644
index 000000000000..70b193f6b756
--- /dev/null
+++ b/include/asm-arm/arch-ks8695/regs-irq.h
@@ -0,0 +1,41 @@
1/*
2 * include/asm-arm/arch-ks8695/regs-irq.h
3 *
4 * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
5 * Copyright (C) 2006 Simtec Electronics
6 *
7 * KS8695 - IRQ registers and bit definitions
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef KS8695_IRQ_H
15#define KS8695_IRQ_H
16
17#define KS8695_IRQ_OFFSET (0xF0000 + 0xE200)
18#define KS8695_IRQ_VA (KS8695_IO_VA + KS8695_IRQ_OFFSET)
19#define KS8695_IRQ_PA (KS8695_IO_PA + KS8695_IRQ_OFFSET)
20
21
22/*
23 * Interrupt Controller registers
24 */
25#define KS8695_INTMC (0x00) /* Mode Control Register */
26#define KS8695_INTEN (0x04) /* Interrupt Enable Register */
27#define KS8695_INTST (0x08) /* Interrupt Status Register */
28#define KS8695_INTPW (0x0c) /* Interrupt Priority (WAN MAC) */
29#define KS8695_INTPH (0x10) /* Interrupt Priority (HPNA) [KS8695 only] */
30#define KS8695_INTPL (0x14) /* Interrupt Priority (LAN MAC) */
31#define KS8695_INTPT (0x18) /* Interrupt Priority (Timer) */
32#define KS8695_INTPU (0x1c) /* Interrupt Priority (UART) */
33#define KS8695_INTPE (0x20) /* Interrupt Priority (External Interrupt) */
34#define KS8695_INTPC (0x24) /* Interrupt Priority (Communications Channel) */
35#define KS8695_INTPBE (0x28) /* Interrupt Priority (Bus Error Response) */
36#define KS8695_INTMS (0x2c) /* Interrupt Mask Status Register */
37#define KS8695_INTHPF (0x30) /* Interrupt Pending Highest Priority (FIQ) */
38#define KS8695_INTHPI (0x34) /* Interrupt Pending Highest Priority (IRQ) */
39
40
41#endif
diff --git a/include/asm-arm/arch-ks8695/regs-lan.h b/include/asm-arm/arch-ks8695/regs-lan.h
new file mode 100644
index 000000000000..a63bd61c64ed
--- /dev/null
+++ b/include/asm-arm/arch-ks8695/regs-lan.h
@@ -0,0 +1,65 @@
1/*
2 * include/asm-arm/arch-ks8695/regs-lan.h
3 *
4 * Copyright (C) 2006 Andrew Victor
5 *
6 * KS8695 - LAN Registers and bit definitions.
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#ifndef KS8695_LAN_H
14#define KS8695_LAN_H
15
16#define KS8695_LAN_OFFSET (0xF0000 + 0x8000)
17#define KS8695_LAN_VA (KS8695_IO_VA + KS8695_LAN_OFFSET)
18#define KS8695_LAN_PA (KS8695_IO_PA + KS8695_LAN_OFFSET)
19
20
21/*
22 * LAN registers
23 */
24#define KS8695_LMDTXC (0x00) /* DMA Transmit Control */
25#define KS8695_LMDRXC (0x04) /* DMA Receive Control */
26#define KS8695_LMDTSC (0x08) /* DMA Transmit Start Command */
27#define KS8695_LMDRSC (0x0c) /* DMA Receive Start Command */
28#define KS8695_LTDLB (0x10) /* Transmit Descriptor List Base Address */
29#define KS8695_LRDLB (0x14) /* Receive Descriptor List Base Address */
30#define KS8695_LMAL (0x18) /* MAC Station Address Low */
31#define KS8695_LMAH (0x1c) /* MAC Station Address High */
32#define KS8695_LMAAL_(n) (0x80 + ((n)*8)) /* MAC Additional Station Address (0..15) Low */
33#define KS8695_LMAAH_(n) (0x84 + ((n)*8)) /* MAC Additional Station Address (0..15) High */
34
35
36/* DMA Transmit Control Register */
37#define LMDTXC_LMTRST (1 << 31) /* Soft Reset */
38#define LMDTXC_LMTBS (0x3f << 24) /* Transmit Burst Size */
39#define LMDTXC_LMTUCG (1 << 18) /* Transmit UDP Checksum Generate */
40#define LMDTXC_LMTTCG (1 << 17) /* Transmit TCP Checksum Generate */
41#define LMDTXC_LMTICG (1 << 16) /* Transmit IP Checksum Generate */
42#define LMDTXC_LMTFCE (1 << 9) /* Transmit Flow Control Enable */
43#define LMDTXC_LMTLB (1 << 8) /* Loopback mode */
44#define LMDTXC_LMTEP (1 << 2) /* Transmit Enable Padding */
45#define LMDTXC_LMTAC (1 << 1) /* Transmit Add CRC */
46#define LMDTXC_LMTE (1 << 0) /* TX Enable */
47
48/* DMA Receive Control Register */
49#define LMDRXC_LMRBS (0x3f << 24) /* Receive Burst Size */
50#define LMDRXC_LMRUCC (1 << 18) /* Receive UDP Checksum check */
51#define LMDRXC_LMRTCG (1 << 17) /* Receive TCP Checksum check */
52#define LMDRXC_LMRICG (1 << 16) /* Receive IP Checksum check */
53#define LMDRXC_LMRFCE (1 << 9) /* Receive Flow Control Enable */
54#define LMDRXC_LMRB (1 << 6) /* Receive Broadcast */
55#define LMDRXC_LMRM (1 << 5) /* Receive Multicast */
56#define LMDRXC_LMRU (1 << 4) /* Receive Unicast */
57#define LMDRXC_LMRERR (1 << 3) /* Receive Error Frame */
58#define LMDRXC_LMRA (1 << 2) /* Receive All */
59#define LMDRXC_LMRE (1 << 1) /* RX Enable */
60
61/* Additional Station Address High */
62#define LMAAH_E (1 << 31) /* Address Enabled */
63
64
65#endif
diff --git a/include/asm-arm/arch-ks8695/regs-mem.h b/include/asm-arm/arch-ks8695/regs-mem.h
new file mode 100644
index 000000000000..76b38e0862e6
--- /dev/null
+++ b/include/asm-arm/arch-ks8695/regs-mem.h
@@ -0,0 +1,89 @@
1/*
2 * include/asm-arm/arch-ks8695/regs-mem.h
3 *
4 * Copyright (C) 2006 Andrew Victor
5 *
6 * KS8695 - Memory Controller registers and bit definitions
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#ifndef KS8695_MEM_H
14#define KS8695_MEM_H
15
16#define KS8695_MEM_OFFSET (0xF0000 + 0x4000)
17#define KS8695_MEM_VA (KS8695_IO_VA + KS8695_MEM_OFFSET)
18#define KS8695_MEM_PA (KS8695_IO_PA + KS8695_MEM_OFFSET)
19
20
21/*
22 * Memory Controller Registers
23 */
24#define KS8695_EXTACON0 (0x00) /* External I/O 0 Access Control */
25#define KS8695_EXTACON1 (0x04) /* External I/O 1 Access Control */
26#define KS8695_EXTACON2 (0x08) /* External I/O 2 Access Control */
27#define KS8695_ROMCON0 (0x10) /* ROM/SRAM/Flash 1 Control Register */
28#define KS8695_ROMCON1 (0x14) /* ROM/SRAM/Flash 2 Control Register */
29#define KS8695_ERGCON (0x20) /* External I/O and ROM/SRAM/Flash General Register */
30#define KS8695_SDCON0 (0x30) /* SDRAM Control Register 0 */
31#define KS8695_SDCON1 (0x34) /* SDRAM Control Register 1 */
32#define KS8695_SDGCON (0x38) /* SDRAM General Control */
33#define KS8695_SDBCON (0x3c) /* SDRAM Buffer Control */
34#define KS8695_REFTIM (0x40) /* SDRAM Refresh Timer */
35
36
37/* External I/O Access Control Registers */
38#define EXTACON_EBNPTR (0x3ff << 22) /* Last Address Pointer */
39#define EXTACON_EBBPTR (0x3ff << 12) /* Base Pointer */
40#define EXTACON_EBTACT (7 << 9) /* Write Enable/Output Enable Active Time */
41#define EXTACON_EBTCOH (7 << 6) /* Chip Select Hold Time */
42#define EXTACON_EBTACS (7 << 3) /* Address Setup Time before ECSN */
43#define EXTACON_EBTCOS (7 << 0) /* Chip Select Time before OEN */
44
45/* ROM/SRAM/Flash Control Register */
46#define ROMCON_RBNPTR (0x3ff << 22) /* Next Pointer */
47#define ROMCON_RBBPTR (0x3ff << 12) /* Base Pointer */
48#define ROMCON_RBTACC (7 << 4) /* Access Cycle Time */
49#define ROMCON_RBTPA (3 << 2) /* Page Address Access Time */
50#define ROMCON_PMC (3 << 0) /* Page Mode Configuration */
51#define PMC_NORMAL (0 << 0)
52#define PMC_4WORD (1 << 0)
53#define PMC_8WORD (2 << 0)
54#define PMC_16WORD (3 << 0)
55
56/* External I/O and ROM/SRAM/Flash General Register */
57#define ERGCON_TMULT (3 << 28) /* Time Multiplier */
58#define ERGCON_DSX2 (3 << 20) /* Data Width (External I/O Bank 2) */
59#define ERGCON_DSX1 (3 << 18) /* Data Width (External I/O Bank 1) */
60#define ERGCON_DSX0 (3 << 16) /* Data Width (External I/O Bank 0) */
61#define ERGCON_DSR1 (3 << 2) /* Data Width (ROM/SRAM/Flash Bank 1) */
62#define ERGCON_DSR0 (3 << 0) /* Data Width (ROM/SRAM/Flash Bank 0) */
63
64/* SDRAM Control Register */
65#define SDCON_DBNPTR (0x3ff << 22) /* Last Address Pointer */
66#define SDCON_DBBPTR (0x3ff << 12) /* Base Pointer */
67#define SDCON_DBCAB (3 << 8) /* Column Address Bits */
68#define SDCON_DBBNUM (1 << 3) /* Number of Banks */
69#define SDCON_DBDBW (3 << 1) /* Data Bus Width */
70
71/* SDRAM General Control Register */
72#define SDGCON_SDTRC (3 << 2) /* RAS to CAS latency */
73#define SDGCON_SDCAS (3 << 0) /* CAS latency */
74
75/* SDRAM Buffer Control Register */
76#define SDBCON_SDESTA (1 << 31) /* SDRAM Engine Status */
77#define SDBCON_RBUFBDIS (1 << 24) /* Read Buffer Burst Enable */
78#define SDBCON_WFIFOEN (1 << 23) /* Write FIFO Enable */
79#define SDBCON_RBUFEN (1 << 22) /* Read Buffer Enable */
80#define SDBCON_FLUSHWFIFO (1 << 21) /* Flush Write FIFO */
81#define SDBCON_RBUFINV (1 << 20) /* Read Buffer Invalidate */
82#define SDBCON_SDINI (3 << 16) /* SDRAM Initialization Control */
83#define SDBCON_SDMODE (0x3fff << 0) /* SDRAM Mode Register Value Program */
84
85/* SDRAM Refresh Timer Register */
86#define REFTIM_REFTIM (0xffff << 0) /* Refresh Timer Value */
87
88
89#endif
diff --git a/include/asm-arm/arch-ks8695/regs-misc.h b/include/asm-arm/arch-ks8695/regs-misc.h
new file mode 100644
index 000000000000..632ca6601a94
--- /dev/null
+++ b/include/asm-arm/arch-ks8695/regs-misc.h
@@ -0,0 +1,97 @@
1/*
2 * include/asm-arm/arch-ks8695/regs-misc.h
3 *
4 * Copyright (C) 2006 Andrew Victor
5 *
6 * KS8695 - Miscellaneous Registers
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#ifndef KS8695_MISC_H
14#define KS8695_MISC_H
15
16#define KS8695_MISC_OFFSET (0xF0000 + 0xEA00)
17#define KS8695_MISC_VA (KS8695_IO_VA + KS8695_MISC_OFFSET)
18#define KS8695_MISC_PA (KS8695_IO_PA + KS8695_MISC_OFFSET)
19
20
21/*
22 * Miscellaneous registers
23 */
24#define KS8695_DID (0x00) /* Device ID */
25#define KS8695_RID (0x04) /* Revision ID */
26#define KS8695_HMC (0x08) /* HPNA Miscellaneous Control [KS8695 only] */
27#define KS8695_WMC (0x0c) /* WAN Miscellaneous Control */
28#define KS8695_WPPM (0x10) /* WAN PHY Power Management */
29#define KS8695_PPS (0x1c) /* PHY PowerSave */
30
31/* Device ID Register */
32#define DID_ID (0xffff << 0) /* Device ID */
33
34/* Revision ID Register */
35#define RID_SUBID (0xf << 4) /* Sub-Device ID */
36#define RID_REVISION (0xf << 0) /* Revision ID */
37
38/* HPNA Miscellaneous Control Register */
39#define HMC_HSS (1 << 1) /* Speed */
40#define HMC_HDS (1 << 0) /* Duplex */
41
42/* WAN Miscellaneous Control Register */
43#define WMC_WANC (1 << 30) /* Auto-negotiation complete */
44#define WMC_WANR (1 << 29) /* Auto-negotiation restart */
45#define WMC_WANAP (1 << 28) /* Advertise Pause */
46#define WMC_WANA100F (1 << 27) /* Advertise 100 FDX */
47#define WMC_WANA100H (1 << 26) /* Advertise 100 HDX */
48#define WMC_WANA10F (1 << 25) /* Advertise 10 FDX */
49#define WMC_WANA10H (1 << 24) /* Advertise 10 HDX */
50#define WMC_WLS (1 << 23) /* Link status */
51#define WMC_WDS (1 << 22) /* Duplex status */
52#define WMC_WSS (1 << 21) /* Speed status */
53#define WMC_WLPP (1 << 20) /* Link Partner Pause */
54#define WMC_WLP100F (1 << 19) /* Link Partner 100 FDX */
55#define WMC_WLP100H (1 << 18) /* Link Partner 100 HDX */
56#define WMC_WLP10F (1 << 17) /* Link Partner 10 FDX */
57#define WMC_WLP10H (1 << 16) /* Link Partner 10 HDX */
58#define WMC_WAND (1 << 15) /* Auto-negotiation disable */
59#define WMC_WANF100 (1 << 14) /* Force 100 */
60#define WMC_WANFF (1 << 13) /* Force FDX */
61#define WMC_WLED1S (7 << 4) /* LED1 Select */
62#define WLED1S_SPEED (0 << 4)
63#define WLED1S_LINK (1 << 4)
64#define WLED1S_DUPLEX (2 << 4)
65#define WLED1S_COLLISION (3 << 4)
66#define WLED1S_ACTIVITY (4 << 4)
67#define WLED1S_FDX_COLLISION (5 << 4)
68#define WLED1S_LINK_ACTIVITY (6 << 4)
69#define WMC_WLED0S (7 << 0) /* LED0 Select */
70#define WLED0S_SPEED (0 << 0)
71#define WLED0S_LINK (1 << 0)
72#define WLED0S_DUPLEX (2 << 0)
73#define WLED0S_COLLISION (3 << 0)
74#define WLED0S_ACTIVITY (4 << 0)
75#define WLED0S_FDX_COLLISION (5 << 0)
76#define WLED0S_LINK_ACTIVITY (6 << 0)
77
78/* WAN PHY Power Management Register */
79#define WPPM_WLPBK (1 << 14) /* Local Loopback */
80#define WPPM_WRLPKB (1 << 13) /* Remove Loopback */
81#define WPPM_WPI (1 << 12) /* PHY isolate */
82#define WPPM_WFL (1 << 10) /* Force link */
83#define WPPM_MDIXS (1 << 9) /* MDIX Status */
84#define WPPM_FEF (1 << 8) /* Far End Fault */
85#define WPPM_AMDIXP (1 << 7) /* Auto MDIX Parameter */
86#define WPPM_TXDIS (1 << 6) /* Disable transmitter */
87#define WPPM_DFEF (1 << 5) /* Disable Far End Fault */
88#define WPPM_PD (1 << 4) /* Power Down */
89#define WPPM_DMDX (1 << 3) /* Disable Auto MDI/MDIX */
90#define WPPM_FMDX (1 << 2) /* Force MDIX */
91#define WPPM_LPBK (1 << 1) /* MAX Loopback */
92
93/* PHY Power Save Register */
94#define PPS_PPSM (1 << 0) /* PHY Power Save Mode */
95
96
97#endif
diff --git a/include/asm-arm/arch-ks8695/regs-pci.h b/include/asm-arm/arch-ks8695/regs-pci.h
new file mode 100644
index 000000000000..286d6d488df8
--- /dev/null
+++ b/include/asm-arm/arch-ks8695/regs-pci.h
@@ -0,0 +1,53 @@
1/*
2 * include/asm-arm/arch-ks8695/regs-pci.h
3 *
4 * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
5 * Copyright (C) 2006 Simtec Electronics
6 *
7 * KS8695 - PCI bridge registers and bit definitions.
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#define KS8695_PCI_OFFSET (0xF0000 + 0x2000)
15#define KS8695_PCI_VA (KS8695_IO_VA + KS8695_PCI_OFFSET)
16#define KS8695_PCI_PA (KS8695_IO_PA + KS8695_PCI_OFFSET)
17
18
19#define KS8695_CRCFID (0x000) /* Configuration: Identification */
20#define KS8695_CRCFCS (0x004) /* Configuration: Command and Status */
21#define KS8695_CRCFRV (0x008) /* Configuration: Revision */
22#define KS8695_CRCFLT (0x00C) /* Configuration: Latency Timer */
23#define KS8695_CRCBMA (0x010) /* Configuration: Base Memory Address */
24#define KS8695_CRCSID (0x02C) /* Configuration: Subsystem ID */
25#define KS8695_CRCFIT (0x03C) /* Configuration: Interrupt */
26#define KS8695_PBCA (0x100) /* Bridge Configuration Address */
27#define KS8695_PBCD (0x104) /* Bridge Configuration Data */
28#define KS8695_PBM (0x200) /* Bridge Mode */
29#define KS8695_PBCS (0x204) /* Bridge Control and Status */
30#define KS8695_PMBA (0x208) /* Bridge Memory Base Address */
31#define KS8695_PMBAC (0x20C) /* Bridge Memory Base Address Control */
32#define KS8695_PMBAM (0x210) /* Bridge Memory Base Address Mask */
33#define KS8695_PMBAT (0x214) /* Bridge Memory Base Address Translation */
34#define KS8695_PIOBA (0x218) /* Bridge I/O Base Address */
35#define KS8695_PIOBAC (0x21C) /* Bridge I/O Base Address Control */
36#define KS8695_PIOBAM (0x220) /* Bridge I/O Base Address Mask */
37#define KS8695_PIOBAT (0x224) /* Bridge I/O Base Address Translation */
38
39
40/* Configuration: Identification */
41
42/* Configuration: Command and Status */
43
44/* Configuration: Revision */
45
46
47
48#define CFRV_GUEST (1 << 23)
49
50#define PBCA_TYPE1 (1)
51#define PBCA_ENABLE (1 << 31)
52
53
diff --git a/include/asm-arm/arch-ks8695/regs-switch.h b/include/asm-arm/arch-ks8695/regs-switch.h
new file mode 100644
index 000000000000..5f37be3f2f60
--- /dev/null
+++ b/include/asm-arm/arch-ks8695/regs-switch.h
@@ -0,0 +1,66 @@
1/*
2 * include/asm-arm/arch-ks8695/regs-switch.h
3 *
4 * Copyright (C) 2006 Andrew Victor
5 *
6 * KS8695 - Switch Registers and bit definitions.
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#ifndef KS8695_SWITCH_H
14#define KS8695_SWITCH_H
15
16#define KS8695_SWITCH_OFFSET (0xF0000 + 0xe800)
17#define KS8695_SWITCH_VA (KS8695_IO_VA + KS8695_SWITCH_OFFSET)
18#define KS8695_SWITCH_PA (KS8695_IO_PA + KS8695_SWITCH_OFFSET)
19
20
21/*
22 * Switch registers
23 */
24#define KS8695_SEC0 (0x00) /* Switch Engine Control 0 */
25#define KS8695_SEC1 (0x04) /* Switch Engine Control 1 */
26#define KS8695_SEC2 (0x08) /* Switch Engine Control 2 */
27
28#define KS8695_P(x)_C(z) (0xc0 + (((x)-1)*3 + ((z)-1))*4) /* Port Configuration Registers */
29
30#define KS8695_SEP12AN (0x48) /* Port 1 & 2 Auto-Negotiation */
31#define KS8695_SEP34AN (0x4c) /* Port 3 & 4 Auto-Negotiation */
32#define KS8695_SEIAC (0x50) /* Indirect Access Control */
33#define KS8695_SEIADH2 (0x54) /* Indirect Access Data High 2 */
34#define KS8695_SEIADH1 (0x58) /* Indirect Access Data High 1 */
35#define KS8695_SEIADL (0x5c) /* Indirect Access Data Low */
36#define KS8695_SEAFC (0x60) /* Advance Feature Control */
37#define KS8695_SEDSCPH (0x64) /* TOS Priority High */
38#define KS8695_SEDSCPL (0x68) /* TOS Priority Low */
39#define KS8695_SEMAH (0x6c) /* Switch Engine MAC Address High */
40#define KS8695_SEMAL (0x70) /* Switch Engine MAC Address Low */
41#define KS8695_LPPM12 (0x74) /* Port 1 & 2 PHY Power Management */
42#define KS8695_LPPM34 (0x78) /* Port 3 & 4 PHY Power Management */
43
44
45/* Switch Engine Control 0 */
46#define SEC0_LLED1S (7 << 25) /* LED1 Select */
47#define LLED1S_SPEED (0 << 25)
48#define LLED1S_LINK (1 << 25)
49#define LLED1S_DUPLEX (2 << 25)
50#define LLED1S_COLLISION (3 << 25)
51#define LLED1S_ACTIVITY (4 << 25)
52#define LLED1S_FDX_COLLISION (5 << 25)
53#define LLED1S_LINK_ACTIVITY (6 << 25)
54#define SEC0_LLED0S (7 << 22) /* LED0 Select */
55#define LLED0S_SPEED (0 << 22)
56#define LLED0S_LINK (1 << 22)
57#define LLED0S_DUPLEX (2 << 22)
58#define LLED0S_COLLISION (3 << 22)
59#define LLED0S_ACTIVITY (4 << 22)
60#define LLED0S_FDX_COLLISION (5 << 22)
61#define LLED0S_LINK_ACTIVITY (6 << 22)
62#define SEC0_ENABLE (1 << 0) /* Enable Switch */
63
64
65
66#endif
diff --git a/include/asm-arm/arch-ks8695/regs-sys.h b/include/asm-arm/arch-ks8695/regs-sys.h
new file mode 100644
index 000000000000..f3179815b8ee
--- /dev/null
+++ b/include/asm-arm/arch-ks8695/regs-sys.h
@@ -0,0 +1,34 @@
1/*
2 * include/asm-arm/arch-ks8695/regs-sys.h
3 *
4 * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
5 * Copyright (C) 2006 Simtec Electronics
6 *
7 * KS8695 - System control registers and bit definitions
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef KS8695_SYS_H
15#define KS8695_SYS_H
16
17#define KS8695_SYS_OFFSET (0xF0000 + 0x0000)
18#define KS8695_SYS_VA (KS8695_IO_VA + KS8695_SYS_OFFSET)
19#define KS8695_SYS_PA (KS8695_IO_PA + KS8695_SYS_OFFSET)
20
21
22#define KS8695_SYSCFG (0x00) /* System Configuration Register */
23#define KS8695_CLKCON (0x04) /* System Clock and Bus Control Register */
24
25
26/* System Configuration Register */
27#define SYSCFG_SPRBP (0x3ff << 16) /* Register Bank Base Pointer */
28
29/* System Clock and Bus Control Register */
30#define CLKCON_SFMODE (1 << 8) /* System Fast Mode for Simulation */
31#define CLKCON_SCDC (7 << 0) /* System Clock Divider Select */
32
33
34#endif
diff --git a/include/asm-arm/arch-ks8695/regs-timer.h b/include/asm-arm/arch-ks8695/regs-timer.h
new file mode 100644
index 000000000000..0a9f7f99ec52
--- /dev/null
+++ b/include/asm-arm/arch-ks8695/regs-timer.h
@@ -0,0 +1,40 @@
1/*
2 * include/asm-arm/arch-ks8695/regs-timer.h
3 *
4 * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
5 * Copyright (C) 2006 Simtec Electronics
6 *
7 * KS8695 - Timer registers and bit definitions.
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef KS8695_TIMER_H
15#define KS8695_TIMER_H
16
17#define KS8695_TMR_OFFSET (0xF0000 + 0xE400)
18#define KS8695_TMR_VA (KS8695_IO_VA + KS8695_TMR_OFFSET)
19#define KS8695_TMR_PA (KS8695_IO_PA + KS8695_TMR_OFFSET)
20
21
22/*
23 * Timer registers
24 */
25#define KS8695_TMCON (0x00) /* Timer Control Register */
26#define KS8695_T1TC (0x04) /* Timer 1 Timeout Count Register */
27#define KS8695_T0TC (0x08) /* Timer 0 Timeout Count Register */
28#define KS8695_T1PD (0x0C) /* Timer 1 Pulse Count Register */
29#define KS8695_T0PD (0x10) /* Timer 0 Pulse Count Register */
30
31
32/* Timer Control Register */
33#define TMCON_T1EN (1 << 1) /* Timer 1 Enable */
34#define TMCON_T0EN (1 << 0) /* Timer 0 Enable */
35
36/* Timer0 Timeout Counter Register */
37#define T0TC_WATCHDOG (0xff) /* Enable watchdog mode */
38
39
40#endif
diff --git a/include/asm-arm/arch-ks8695/regs-uart.h b/include/asm-arm/arch-ks8695/regs-uart.h
new file mode 100644
index 000000000000..a27cb20502a3
--- /dev/null
+++ b/include/asm-arm/arch-ks8695/regs-uart.h
@@ -0,0 +1,92 @@
1/*
2 * linux/include/asm-arm/arch-ks8695/regs-uart.h
3 *
4 * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
5 * Copyright (C) 2006 Simtec Electronics
6 *
7 * KS8695 - UART register and bit definitions.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef KS8695_UART_H
15#define KS8695_UART_H
16
17#define KS8695_UART_OFFSET (0xF0000 + 0xE000)
18#define KS8695_UART_VA (KS8695_IO_VA + KS8695_UART_OFFSET)
19#define KS8695_UART_PA (KS8695_IO_PA + KS8695_UART_OFFSET)
20
21
22/*
23 * UART registers
24 */
25#define KS8695_URRB (0x00) /* Receive Buffer Register */
26#define KS8695_URTH (0x04) /* Transmit Holding Register */
27#define KS8695_URFC (0x08) /* FIFO Control Register */
28#define KS8695_URLC (0x0C) /* Line Control Register */
29#define KS8695_URMC (0x10) /* Modem Control Register */
30#define KS8695_URLS (0x14) /* Line Status Register */
31#define KS8695_URMS (0x18) /* Modem Status Register */
32#define KS8695_URBD (0x1C) /* Baud Rate Divisor Register */
33#define KS8695_USR (0x20) /* Status Register */
34
35
36/* FIFO Control Register */
37#define URFC_URFRT (3 << 6) /* Receive FIFO Trigger Level */
38#define URFC_URFRT_1 (0 << 6)
39#define URFC_URFRT_4 (1 << 6)
40#define URFC_URFRT_8 (2 << 6)
41#define URFC_URFRT_14 (3 << 6)
42#define URFC_URTFR (1 << 2) /* Transmit FIFO Reset */
43#define URFC_URRFR (1 << 1) /* Receive FIFO Reset */
44#define URFC_URFE (1 << 0) /* FIFO Enable */
45
46/* Line Control Register */
47#define URLC_URSBC (1 << 6) /* Set Break Condition */
48#define URLC_PARITY (7 << 3) /* Parity */
49#define URPE_NONE (0 << 3)
50#define URPE_ODD (1 << 3)
51#define URPE_EVEN (3 << 3)
52#define URPE_MARK (5 << 3)
53#define URPE_SPACE (7 << 3)
54#define URLC_URSB (1 << 2) /* Stop Bits */
55#define URLC_URCL (3 << 0) /* Character Length */
56#define URCL_5 (0 << 0)
57#define URCL_6 (1 << 0)
58#define URCL_7 (2 << 0)
59#define URCL_8 (3 << 0)
60
61/* Modem Control Register */
62#define URMC_URLB (1 << 4) /* Loop-back mode */
63#define URMC_UROUT2 (1 << 3) /* OUT2 signal */
64#define URMC_UROUT1 (1 << 2) /* OUT1 signal */
65#define URMC_URRTS (1 << 1) /* Request to Send */
66#define URMC_URDTR (1 << 0) /* Data Terminal Ready */
67
68/* Line Status Register */
69#define URLS_URRFE (1 << 7) /* Receive FIFO Error */
70#define URLS_URTE (1 << 6) /* Transmit Empty */
71#define URLS_URTHRE (1 << 5) /* Transmit Holding Register Empty */
72#define URLS_URBI (1 << 4) /* Break Interrupt */
73#define URLS_URFE (1 << 3) /* Framing Error */
74#define URLS_URPE (1 << 2) /* Parity Error */
75#define URLS_URROE (1 << 1) /* Receive Overrun Error */
76#define URLS_URDR (1 << 0) /* Receive Data Ready */
77
78/* Modem Status Register */
79#define URMS_URDCD (1 << 7) /* Data Carrier Detect */
80#define URMS_URRI (1 << 6) /* Ring Indicator */
81#define URMS_URDSR (1 << 5) /* Data Set Ready */
82#define URMS_URCTS (1 << 4) /* Clear to Send */
83#define URMS_URDDCD (1 << 3) /* Delta Data Carrier Detect */
84#define URMS_URTERI (1 << 2) /* Trailing Edge Ring Indicator */
85#define URMS_URDDST (1 << 1) /* Delta Data Set Ready */
86#define URMS_URDCTS (1 << 0) /* Delta Clear to Send */
87
88/* Status Register */
89#define USR_UTI (1 << 0) /* Timeout Indication */
90
91
92#endif
diff --git a/include/asm-arm/arch-ks8695/regs-wan.h b/include/asm-arm/arch-ks8695/regs-wan.h
new file mode 100644
index 000000000000..52e35b0d65e4
--- /dev/null
+++ b/include/asm-arm/arch-ks8695/regs-wan.h
@@ -0,0 +1,65 @@
1/*
2 * include/asm-arm/arch-ks8695/regs-wan.h
3 *
4 * Copyright (C) 2006 Andrew Victor
5 *
6 * KS8695 - WAN Registers and bit definitions.
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#ifndef KS8695_WAN_H
14#define KS8695_WAN_H
15
16#define KS8695_WAN_OFFSET (0xF0000 + 0x6000)
17#define KS8695_WAN_VA (KS8695_IO_VA + KS8695_WAN_OFFSET)
18#define KS8695_WAN_PA (KS8695_IO_PA + KS8695_WAN_OFFSET)
19
20
21/*
22 * WAN registers
23 */
24#define KS8695_WMDTXC (0x00) /* DMA Transmit Control */
25#define KS8695_WMDRXC (0x04) /* DMA Receive Control */
26#define KS8695_WMDTSC (0x08) /* DMA Transmit Start Command */
27#define KS8695_WMDRSC (0x0c) /* DMA Receive Start Command */
28#define KS8695_WTDLB (0x10) /* Transmit Descriptor List Base Address */
29#define KS8695_WRDLB (0x14) /* Receive Descriptor List Base Address */
30#define KS8695_WMAL (0x18) /* MAC Station Address Low */
31#define KS8695_WMAH (0x1c) /* MAC Station Address High */
32#define KS8695_WMAAL_(n) (0x80 + ((n)*8)) /* MAC Additional Station Address (0..15) Low */
33#define KS8695_WMAAH_(n) (0x84 + ((n)*8)) /* MAC Additional Station Address (0..15) High */
34
35
36/* DMA Transmit Control Register */
37#define WMDTXC_WMTRST (1 << 31) /* Soft Reset */
38#define WMDTXC_WMTBS (0x3f << 24) /* Transmit Burst Size */
39#define WMDTXC_WMTUCG (1 << 18) /* Transmit UDP Checksum Generate */
40#define WMDTXC_WMTTCG (1 << 17) /* Transmit TCP Checksum Generate */
41#define WMDTXC_WMTICG (1 << 16) /* Transmit IP Checksum Generate */
42#define WMDTXC_WMTFCE (1 << 9) /* Transmit Flow Control Enable */
43#define WMDTXC_WMTLB (1 << 8) /* Loopback mode */
44#define WMDTXC_WMTEP (1 << 2) /* Transmit Enable Padding */
45#define WMDTXC_WMTAC (1 << 1) /* Transmit Add CRC */
46#define WMDTXC_WMTE (1 << 0) /* TX Enable */
47
48/* DMA Receive Control Register */
49#define WMDRXC_WMRBS (0x3f << 24) /* Receive Burst Size */
50#define WMDRXC_WMRUCC (1 << 18) /* Receive UDP Checksum check */
51#define WMDRXC_WMRTCG (1 << 17) /* Receive TCP Checksum check */
52#define WMDRXC_WMRICG (1 << 16) /* Receive IP Checksum check */
53#define WMDRXC_WMRFCE (1 << 9) /* Receive Flow Control Enable */
54#define WMDRXC_WMRB (1 << 6) /* Receive Broadcast */
55#define WMDRXC_WMRM (1 << 5) /* Receive Multicast */
56#define WMDRXC_WMRU (1 << 4) /* Receive Unicast */
57#define WMDRXC_WMRERR (1 << 3) /* Receive Error Frame */
58#define WMDRXC_WMRA (1 << 2) /* Receive All */
59#define WMDRXC_WMRE (1 << 0) /* RX Enable */
60
61/* Additional Station Address High */
62#define WMAAH_E (1 << 31) /* Address Enabled */
63
64
65#endif
diff --git a/include/asm-arm/arch-ks8695/system.h b/include/asm-arm/arch-ks8695/system.h
new file mode 100644
index 000000000000..3bc28106d937
--- /dev/null
+++ b/include/asm-arm/arch-ks8695/system.h
@@ -0,0 +1,48 @@
1/*
2 * include/asm-arm/arch-s3c2410/system.h
3 *
4 * Copyright (C) 2006 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * KS8695 - System function defines and includes
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __ASM_ARCH_SYSTEM_H
15#define __ASM_ARCH_SYSTEM_H
16
17#include <asm/io.h>
18#include <asm/arch/regs-timer.h>
19
20static void arch_idle(void)
21{
22 /*
23 * This should do all the clock switching
24 * and wait for interrupt tricks,
25 */
26 cpu_do_idle();
27
28}
29
30static void arch_reset(char mode)
31{
32 unsigned int reg;
33
34 if (mode == 's')
35 cpu_reset(0);
36
37 /* disable timer0 */
38 reg = __raw_readl(KS8695_TMR_VA + KS8695_TMCON);
39 __raw_writel(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
40
41 /* enable watchdog mode */
42 __raw_writel((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC);
43
44 /* re-enable timer0 */
45 __raw_writel(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
46}
47
48#endif
diff --git a/include/asm-arm/arch-ks8695/timex.h b/include/asm-arm/arch-ks8695/timex.h
new file mode 100644
index 000000000000..8320d528b903
--- /dev/null
+++ b/include/asm-arm/arch-ks8695/timex.h
@@ -0,0 +1,20 @@
1/*
2 * include/asm-arm/arch-ks8695/timex.h
3 *
4 * Copyright (C) 2006 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * KS8695 - Time Parameters
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __ASM_ARCH_TIMEX_H
15#define __ASM_ARCH_TIMEX_H
16
17/* timers are derived from MCLK, which is 25MHz */
18#define CLOCK_TICK_RATE 25000000
19
20#endif
diff --git a/include/asm-arm/arch-ks8695/uncompress.h b/include/asm-arm/arch-ks8695/uncompress.h
new file mode 100644
index 000000000000..733a50855b5d
--- /dev/null
+++ b/include/asm-arm/arch-ks8695/uncompress.h
@@ -0,0 +1,37 @@
1/*
2 * include/asm-arm/arch-ks8695/uncompress.h
3 *
4 * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
5 * Copyright (C) 2006 Simtec Electronics
6 *
7 * KS8695 - Kernel uncompressor
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __ASM_ARCH_UNCOMPRESS_H
15#define __ASM_ARCH_UNCOMPRESS_H
16
17#include <asm/io.h>
18#include <asm/arch/regs-uart.h>
19
20static void putc(char c)
21{
22 while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTHRE))
23 barrier();
24
25 __raw_writel(c, KS8695_UART_PA + KS8695_URTH);
26}
27
28static inline void flush(void)
29{
30 while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTE))
31 barrier();
32}
33
34#define arch_decomp_setup()
35#define arch_decomp_wdog()
36
37#endif
diff --git a/include/asm-arm/arch-ks8695/vmalloc.h b/include/asm-arm/arch-ks8695/vmalloc.h
new file mode 100644
index 000000000000..d1d88e58117d
--- /dev/null
+++ b/include/asm-arm/arch-ks8695/vmalloc.h
@@ -0,0 +1,19 @@
1/*
2 * include/asm-arm/arch-ks8695/vmalloc.h
3 *
4 * Copyright (C) 2006 Ben Dooks
5 * Copyright (C) 2006 Simtec Electronics <linux@simtec.co.uk>
6 *
7 * KS8695 vmalloc definition
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __ASM_ARCH_VMALLOC_H
15#define __ASM_ARCH_VMALLOC_H
16
17#define VMALLOC_END (KS8695_IO_VA & PGDIR_MASK)
18
19#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 07:06:39 -0500