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authorKenneth Tan <chong.yin.tan@intel.com>2005-10-29 11:32:14 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2005-10-29 11:32:14 -0400
commitc514e58cb8eac0d21f4ab5011df75a09eb5edd50 (patch)
treec616a79e41bed30d56d3c17ae7b802285c8c3374
parent1a47ebc0d971fbc47cd859a09956f7c7d001f5fd (diff)
[ARM] 3022/1: Missing peripheral devices memory mapping definition for IXP46X processor
Patch from Kenneth Tan Defining IXP46X peripheral devices memory mapping definitions that have been missed out: o Peripheral virtual base address is being adjusted to allow more headroom to add extra peripheral device addresses o Peripheral size is being increased to address the above needs o Virtual address of expansion bus and PCI configuration register needs to be adjusted as new peripheral device memory space is overlapping with their virtual address space Signed-off-by: Kenneth Tan <chong.yin.tan@intel.com> Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r--include/asm-arm/arch-ixp4xx/ixp4xx-regs.h75
1 files changed, 49 insertions, 26 deletions
diff --git a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
index 004696a95bdb..2b149ed59149 100644
--- a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
+++ b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
@@ -36,11 +36,11 @@
36 * 36 *
37 * 0x6000000 0x00004000 ioremap'd QMgr 37 * 0x6000000 0x00004000 ioremap'd QMgr
38 * 38 *
39 * 0xC0000000 0x00001000 0xffbfe000 PCI CFG 39 * 0xC0000000 0x00001000 0xffbff000 PCI CFG
40 * 40 *
41 * 0xC4000000 0x00001000 0xffbfd000 EXP CFG 41 * 0xC4000000 0x00001000 0xffbfe000 EXP CFG
42 * 42 *
43 * 0xC8000000 0x0000C000 0xffbf2000 On-Chip Peripherals 43 * 0xC8000000 0x00013000 0xffbeb000 On-Chip Peripherals
44 */ 44 */
45 45
46/* 46/*
@@ -52,22 +52,22 @@
52 * Expansion BUS Configuration registers 52 * Expansion BUS Configuration registers
53 */ 53 */
54#define IXP4XX_EXP_CFG_BASE_PHYS (0xC4000000) 54#define IXP4XX_EXP_CFG_BASE_PHYS (0xC4000000)
55#define IXP4XX_EXP_CFG_BASE_VIRT (0xFFBFD000) 55#define IXP4XX_EXP_CFG_BASE_VIRT (0xFFBFE000)
56#define IXP4XX_EXP_CFG_REGION_SIZE (0x00001000) 56#define IXP4XX_EXP_CFG_REGION_SIZE (0x00001000)
57 57
58/* 58/*
59 * PCI Config registers 59 * PCI Config registers
60 */ 60 */
61#define IXP4XX_PCI_CFG_BASE_PHYS (0xC0000000) 61#define IXP4XX_PCI_CFG_BASE_PHYS (0xC0000000)
62#define IXP4XX_PCI_CFG_BASE_VIRT (0xFFBFE000) 62#define IXP4XX_PCI_CFG_BASE_VIRT (0xFFBFF000)
63#define IXP4XX_PCI_CFG_REGION_SIZE (0x00001000) 63#define IXP4XX_PCI_CFG_REGION_SIZE (0x00001000)
64 64
65/* 65/*
66 * Peripheral space 66 * Peripheral space
67 */ 67 */
68#define IXP4XX_PERIPHERAL_BASE_PHYS (0xC8000000) 68#define IXP4XX_PERIPHERAL_BASE_PHYS (0xC8000000)
69#define IXP4XX_PERIPHERAL_BASE_VIRT (0xFFBF2000) 69#define IXP4XX_PERIPHERAL_BASE_VIRT (0xFFBEB000)
70#define IXP4XX_PERIPHERAL_REGION_SIZE (0x0000C000) 70#define IXP4XX_PERIPHERAL_REGION_SIZE (0x00013000)
71 71
72/* 72/*
73 * Debug UART 73 * Debug UART
@@ -115,25 +115,48 @@
115/* 115/*
116 * Peripheral Space Register Region Base Addresses 116 * Peripheral Space Register Region Base Addresses
117 */ 117 */
118#define IXP4XX_UART1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000) 118#define IXP4XX_UART1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000)
119#define IXP4XX_UART2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000) 119#define IXP4XX_UART2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000)
120#define IXP4XX_PMU_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000) 120#define IXP4XX_PMU_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000)
121#define IXP4XX_INTC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000) 121#define IXP4XX_INTC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000)
122#define IXP4XX_GPIO_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000) 122#define IXP4XX_GPIO_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000)
123#define IXP4XX_TIMER_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000) 123#define IXP4XX_TIMER_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)
124#define IXP4XX_EthA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000) 124#define IXP4XX_NPEA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000)
125#define IXP4XX_EthB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000) 125#define IXP4XX_NPEB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000)
126#define IXP4XX_USB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000) 126#define IXP4XX_NPEC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000)
127 127#define IXP4XX_EthB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)
128#define IXP4XX_UART1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000) 128#define IXP4XX_EthC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)
129#define IXP4XX_UART2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000) 129#define IXP4XX_USB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000)
130#define IXP4XX_PMU_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000) 130/* ixp46X only */
131#define IXP4XX_INTC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000) 131#define IXP4XX_EthA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xC000)
132#define IXP4XX_GPIO_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000) 132#define IXP4XX_EthB1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xD000)
133#define IXP4XX_TIMER_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000) 133#define IXP4XX_EthB2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xE000)
134#define IXP4XX_EthA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000) 134#define IXP4XX_EthB3_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xF000)
135#define IXP4XX_EthB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000) 135#define IXP4XX_TIMESYNC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x10000)
136#define IXP4XX_USB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000) 136#define IXP4XX_I2C_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x11000)
137#define IXP4XX_SSP_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000)
138
139
140#define IXP4XX_UART1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)
141#define IXP4XX_UART2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)
142#define IXP4XX_PMU_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)
143#define IXP4XX_INTC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)
144#define IXP4XX_GPIO_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)
145#define IXP4XX_TIMER_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
146#define IXP4XX_NPEA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000)
147#define IXP4XX_NPEB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000)
148#define IXP4XX_NPEC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000)
149#define IXP4XX_EthB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000)
150#define IXP4XX_EthC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000)
151#define IXP4XX_USB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000)
152/* ixp46X only */
153#define IXP4XX_EthA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xC000)
154#define IXP4XX_EthB1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xD000)
155#define IXP4XX_EthB2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xE000)
156#define IXP4XX_EthB3_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xF000)
157#define IXP4XX_TIMESYNC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x10000)
158#define IXP4XX_I2C_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x11000)
159#define IXP4XX_SSP_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000)
137 160
138/* 161/*
139 * Constants to make it easy to access Interrupt Controller registers 162 * Constants to make it easy to access Interrupt Controller registers