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authorBruce Allan <bruce.w.allan@intel.com>2009-06-02 07:29:18 -0400
committerDavid S. Miller <davem@davemloft.net>2009-06-03 05:46:34 -0400
commita4f58f5455ba0efda36fb33c37074922d1527a10 (patch)
tree98aa6d14824b7c1b7907e703abedd80219e0abda
parent2adc55c959940fc680074392eddbd5585a76f3d9 (diff)
e1000e: add support for 82577/82578 GbE LOM parts
This patch provides support for the next generation Intel desktop and mobile gigabit ethernet LOM adapters. These adapters are the follow-on parts to the LOMs tied to the prior ICH chipsets and are comprised of a MAC in the PCH chipset and an external PHY (82577 for mobile and 82578 for desktop versions). New features consist of PHY wakeup to save power by completely turning off the MAC while in Sx state, and 4K jumbo frames. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/e1000e/82571.c2
-rw-r--r--drivers/net/e1000e/defines.h21
-rw-r--r--drivers/net/e1000e/e1000.h57
-rw-r--r--drivers/net/e1000e/es2lan.c2
-rw-r--r--drivers/net/e1000e/ethtool.c37
-rw-r--r--drivers/net/e1000e/hw.h16
-rw-r--r--drivers/net/e1000e/ich8lan.c431
-rw-r--r--drivers/net/e1000e/lib.c38
-rw-r--r--drivers/net/e1000e/netdev.c206
-rw-r--r--drivers/net/e1000e/phy.c699
10 files changed, 1441 insertions, 68 deletions
diff --git a/drivers/net/e1000e/82571.c b/drivers/net/e1000e/82571.c
index 8203964373ce..c4b3f4fe91ae 100644
--- a/drivers/net/e1000e/82571.c
+++ b/drivers/net/e1000e/82571.c
@@ -1587,6 +1587,7 @@ static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1587static struct e1000_mac_operations e82571_mac_ops = { 1587static struct e1000_mac_operations e82571_mac_ops = {
1588 /* .check_mng_mode: mac type dependent */ 1588 /* .check_mng_mode: mac type dependent */
1589 /* .check_for_link: media type dependent */ 1589 /* .check_for_link: media type dependent */
1590 .id_led_init = e1000e_id_led_init,
1590 .cleanup_led = e1000e_cleanup_led_generic, 1591 .cleanup_led = e1000e_cleanup_led_generic,
1591 .clear_hw_cntrs = e1000_clear_hw_cntrs_82571, 1592 .clear_hw_cntrs = e1000_clear_hw_cntrs_82571,
1592 .get_bus_info = e1000e_get_bus_info_pcie, 1593 .get_bus_info = e1000e_get_bus_info_pcie,
@@ -1598,6 +1599,7 @@ static struct e1000_mac_operations e82571_mac_ops = {
1598 .init_hw = e1000_init_hw_82571, 1599 .init_hw = e1000_init_hw_82571,
1599 .setup_link = e1000_setup_link_82571, 1600 .setup_link = e1000_setup_link_82571,
1600 /* .setup_physical_interface: media type dependent */ 1601 /* .setup_physical_interface: media type dependent */
1602 .setup_led = e1000e_setup_led_generic,
1601}; 1603};
1602 1604
1603static struct e1000_phy_operations e82_phy_ops_igp = { 1605static struct e1000_phy_operations e82_phy_ops_igp = {
diff --git a/drivers/net/e1000e/defines.h b/drivers/net/e1000e/defines.h
index 9acfecddb273..674a47e43034 100644
--- a/drivers/net/e1000e/defines.h
+++ b/drivers/net/e1000e/defines.h
@@ -56,6 +56,7 @@
56/* Wake Up Control */ 56/* Wake Up Control */
57#define E1000_WUC_APME 0x00000001 /* APM Enable */ 57#define E1000_WUC_APME 0x00000001 /* APM Enable */
58#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 58#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
59#define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
59 60
60/* Wake Up Filter Control */ 61/* Wake Up Filter Control */
61#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 62#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
@@ -65,6 +66,13 @@
65#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 66#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
66#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 67#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
67 68
69/* Wake Up Status */
70#define E1000_WUS_LNKC E1000_WUFC_LNKC
71#define E1000_WUS_MAG E1000_WUFC_MAG
72#define E1000_WUS_EX E1000_WUFC_EX
73#define E1000_WUS_MC E1000_WUFC_MC
74#define E1000_WUS_BC E1000_WUFC_BC
75
68/* Extended Device Control */ 76/* Extended Device Control */
69#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Definable Pin 7 */ 77#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Definable Pin 7 */
70#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 78#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
@@ -77,6 +85,7 @@
77#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ 85#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */
78#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ 86#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */
79#define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ 87#define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */
88#define E1000_CTRL_EXT_PHYPDEN 0x00100000
80 89
81/* Receive Descriptor bit definitions */ 90/* Receive Descriptor bit definitions */
82#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 91#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
@@ -140,6 +149,7 @@
140#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ 149#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
141#define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min threshold size */ 150#define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min threshold size */
142#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 151#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
152#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
143#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 153#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
144/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ 154/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
145#define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */ 155#define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */
@@ -153,6 +163,7 @@
153#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 163#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
154#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 164#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
155#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ 165#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
166#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
156#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ 167#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
157#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 168#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
158 169
@@ -255,11 +266,16 @@
255#define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX 266#define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
256 267
257/* LED Control */ 268/* LED Control */
269#define E1000_PHY_LED0_MODE_MASK 0x00000007
270#define E1000_PHY_LED0_IVRT 0x00000008
271#define E1000_PHY_LED0_MASK 0x0000001F
272
258#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 273#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
259#define E1000_LEDCTL_LED0_MODE_SHIFT 0 274#define E1000_LEDCTL_LED0_MODE_SHIFT 0
260#define E1000_LEDCTL_LED0_IVRT 0x00000040 275#define E1000_LEDCTL_LED0_IVRT 0x00000040
261#define E1000_LEDCTL_LED0_BLINK 0x00000080 276#define E1000_LEDCTL_LED0_BLINK 0x00000080
262 277
278#define E1000_LEDCTL_MODE_LINK_UP 0x2
263#define E1000_LEDCTL_MODE_LED_ON 0xE 279#define E1000_LEDCTL_MODE_LED_ON 0xE
264#define E1000_LEDCTL_MODE_LED_OFF 0xF 280#define E1000_LEDCTL_MODE_LED_OFF 0xF
265 281
@@ -676,6 +692,8 @@
676#define IFE_C_E_PHY_ID 0x02A80310 692#define IFE_C_E_PHY_ID 0x02A80310
677#define BME1000_E_PHY_ID 0x01410CB0 693#define BME1000_E_PHY_ID 0x01410CB0
678#define BME1000_E_PHY_ID_R2 0x01410CB1 694#define BME1000_E_PHY_ID_R2 0x01410CB1
695#define I82577_E_PHY_ID 0x01540050
696#define I82578_E_PHY_ID 0x004DD040
679 697
680/* M88E1000 Specific Registers */ 698/* M88E1000 Specific Registers */
681#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ 699#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
@@ -729,6 +747,9 @@
729#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 747#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
730#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 748#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
731 749
750#define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020
751#define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C
752
732/* BME1000 PHY Specific Control Register */ 753/* BME1000 PHY Specific Control Register */
733#define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */ 754#define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */
734 755
diff --git a/drivers/net/e1000e/e1000.h b/drivers/net/e1000e/e1000.h
index b9dc612082e0..d6e491bc58c9 100644
--- a/drivers/net/e1000e/e1000.h
+++ b/drivers/net/e1000e/e1000.h
@@ -98,6 +98,49 @@ struct e1000_info;
98 98
99#define DEFAULT_JUMBO 9234 99#define DEFAULT_JUMBO 9234
100 100
101/* BM/HV Specific Registers */
102#define BM_PORT_CTRL_PAGE 769
103
104#define PHY_UPPER_SHIFT 21
105#define BM_PHY_REG(page, reg) \
106 (((reg) & MAX_PHY_REG_ADDRESS) |\
107 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
108 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
109
110/* PHY Wakeup Registers and defines */
111#define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
112#define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
113#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
114#define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
115#define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
116#define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
117#define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
118#define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
119#define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
120
121#define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */
122#define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */
123#define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */
124#define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */
125#define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */
126#define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */
127#define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */
128
129#define HV_SCC_UPPER PHY_REG(778, 16) /* Single Collision Count */
130#define HV_SCC_LOWER PHY_REG(778, 17)
131#define HV_ECOL_UPPER PHY_REG(778, 18) /* Excessive Collision Count */
132#define HV_ECOL_LOWER PHY_REG(778, 19)
133#define HV_MCC_UPPER PHY_REG(778, 20) /* Multiple Collision Count */
134#define HV_MCC_LOWER PHY_REG(778, 21)
135#define HV_LATECOL_UPPER PHY_REG(778, 23) /* Late Collision Count */
136#define HV_LATECOL_LOWER PHY_REG(778, 24)
137#define HV_COLC_UPPER PHY_REG(778, 25) /* Collision Count */
138#define HV_COLC_LOWER PHY_REG(778, 26)
139#define HV_DC_UPPER PHY_REG(778, 27) /* Defer Count */
140#define HV_DC_LOWER PHY_REG(778, 28)
141#define HV_TNCRS_UPPER PHY_REG(778, 29) /* Transmit with no CRS */
142#define HV_TNCRS_LOWER PHY_REG(778, 30)
143
101enum e1000_boards { 144enum e1000_boards {
102 board_82571, 145 board_82571,
103 board_82572, 146 board_82572,
@@ -108,6 +151,7 @@ enum e1000_boards {
108 board_ich8lan, 151 board_ich8lan,
109 board_ich9lan, 152 board_ich9lan,
110 board_ich10lan, 153 board_ich10lan,
154 board_pchlan,
111}; 155};
112 156
113struct e1000_queue_stats { 157struct e1000_queue_stats {
@@ -305,6 +349,7 @@ struct e1000_adapter {
305 unsigned int flags2; 349 unsigned int flags2;
306 struct work_struct downshift_task; 350 struct work_struct downshift_task;
307 struct work_struct update_phy_task; 351 struct work_struct update_phy_task;
352 struct work_struct led_blink_task;
308}; 353};
309 354
310struct e1000_info { 355struct e1000_info {
@@ -355,6 +400,7 @@ struct e1000_info {
355 400
356/* CRC Stripping defines */ 401/* CRC Stripping defines */
357#define FLAG2_CRC_STRIPPING (1 << 0) 402#define FLAG2_CRC_STRIPPING (1 << 0)
403#define FLAG2_HAS_PHY_WAKEUP (1 << 1)
358 404
359#define E1000_RX_DESC_PS(R, i) \ 405#define E1000_RX_DESC_PS(R, i) \
360 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i])) 406 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
@@ -408,6 +454,7 @@ extern struct e1000_info e1000_82583_info;
408extern struct e1000_info e1000_ich8_info; 454extern struct e1000_info e1000_ich8_info;
409extern struct e1000_info e1000_ich9_info; 455extern struct e1000_info e1000_ich9_info;
410extern struct e1000_info e1000_ich10_info; 456extern struct e1000_info e1000_ich10_info;
457extern struct e1000_info e1000_pch_info;
411extern struct e1000_info e1000_es2_info; 458extern struct e1000_info e1000_es2_info;
412 459
413extern s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num); 460extern s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num);
@@ -429,6 +476,7 @@ extern void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw);
429extern s32 e1000e_check_for_copper_link(struct e1000_hw *hw); 476extern s32 e1000e_check_for_copper_link(struct e1000_hw *hw);
430extern s32 e1000e_check_for_fiber_link(struct e1000_hw *hw); 477extern s32 e1000e_check_for_fiber_link(struct e1000_hw *hw);
431extern s32 e1000e_check_for_serdes_link(struct e1000_hw *hw); 478extern s32 e1000e_check_for_serdes_link(struct e1000_hw *hw);
479extern s32 e1000e_setup_led_generic(struct e1000_hw *hw);
432extern s32 e1000e_cleanup_led_generic(struct e1000_hw *hw); 480extern s32 e1000e_cleanup_led_generic(struct e1000_hw *hw);
433extern s32 e1000e_led_on_generic(struct e1000_hw *hw); 481extern s32 e1000e_led_on_generic(struct e1000_hw *hw);
434extern s32 e1000e_led_off_generic(struct e1000_hw *hw); 482extern s32 e1000e_led_off_generic(struct e1000_hw *hw);
@@ -497,6 +545,15 @@ extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw);
497extern s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); 545extern s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
498extern s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); 546extern s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
499extern s32 e1000e_check_downshift(struct e1000_hw *hw); 547extern s32 e1000e_check_downshift(struct e1000_hw *hw);
548extern s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
549extern s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
550extern s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw, bool slow);
551extern s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw);
552extern s32 e1000_copper_link_setup_82577(struct e1000_hw *hw);
553extern s32 e1000_check_polarity_82577(struct e1000_hw *hw);
554extern s32 e1000_get_phy_info_82577(struct e1000_hw *hw);
555extern s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
556extern s32 e1000_get_cable_length_82577(struct e1000_hw *hw);
500 557
501static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw) 558static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
502{ 559{
diff --git a/drivers/net/e1000e/es2lan.c b/drivers/net/e1000e/es2lan.c
index 6cc3bdf4acdb..ae5d73689353 100644
--- a/drivers/net/e1000e/es2lan.c
+++ b/drivers/net/e1000e/es2lan.c
@@ -1366,6 +1366,7 @@ static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1366} 1366}
1367 1367
1368static struct e1000_mac_operations es2_mac_ops = { 1368static struct e1000_mac_operations es2_mac_ops = {
1369 .id_led_init = e1000e_id_led_init,
1369 .check_mng_mode = e1000e_check_mng_mode_generic, 1370 .check_mng_mode = e1000e_check_mng_mode_generic,
1370 /* check_for_link dependent on media type */ 1371 /* check_for_link dependent on media type */
1371 .cleanup_led = e1000e_cleanup_led_generic, 1372 .cleanup_led = e1000e_cleanup_led_generic,
@@ -1379,6 +1380,7 @@ static struct e1000_mac_operations es2_mac_ops = {
1379 .init_hw = e1000_init_hw_80003es2lan, 1380 .init_hw = e1000_init_hw_80003es2lan,
1380 .setup_link = e1000e_setup_link, 1381 .setup_link = e1000e_setup_link,
1381 /* setup_physical_interface dependent on media type */ 1382 /* setup_physical_interface dependent on media type */
1383 .setup_led = e1000e_setup_led_generic,
1382}; 1384};
1383 1385
1384static struct e1000_phy_operations es2_phy_ops = { 1386static struct e1000_phy_operations es2_phy_ops = {
diff --git a/drivers/net/e1000e/ethtool.c b/drivers/net/e1000e/ethtool.c
index 4d25ede88369..3d6435617527 100644
--- a/drivers/net/e1000e/ethtool.c
+++ b/drivers/net/e1000e/ethtool.c
@@ -776,6 +776,7 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
776 u32 after; 776 u32 after;
777 u32 i; 777 u32 i;
778 u32 toggle; 778 u32 toggle;
779 u32 mask;
779 780
780 /* 781 /*
781 * The status register is Read Only, so a write should fail. 782 * The status register is Read Only, so a write should fail.
@@ -788,17 +789,9 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
788 case e1000_80003es2lan: 789 case e1000_80003es2lan:
789 toggle = 0x7FFFF3FF; 790 toggle = 0x7FFFF3FF;
790 break; 791 break;
791 case e1000_82573: 792 default:
792 case e1000_82574:
793 case e1000_82583:
794 case e1000_ich8lan:
795 case e1000_ich9lan:
796 case e1000_ich10lan:
797 toggle = 0x7FFFF033; 793 toggle = 0x7FFFF033;
798 break; 794 break;
799 default:
800 toggle = 0xFFFFF833;
801 break;
802 } 795 }
803 796
804 before = er32(STATUS); 797 before = er32(STATUS);
@@ -844,11 +837,18 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
844 REG_PATTERN_TEST(E1000_TXCW, 0xC000FFFF, 0x0000FFFF); 837 REG_PATTERN_TEST(E1000_TXCW, 0xC000FFFF, 0x0000FFFF);
845 REG_PATTERN_TEST(E1000_TDBAL, 0xFFFFFFF0, 0xFFFFFFFF); 838 REG_PATTERN_TEST(E1000_TDBAL, 0xFFFFFFF0, 0xFFFFFFFF);
846 REG_PATTERN_TEST(E1000_TIDV, 0x0000FFFF, 0x0000FFFF); 839 REG_PATTERN_TEST(E1000_TIDV, 0x0000FFFF, 0x0000FFFF);
840 mask = 0x8003FFFF;
841 switch (mac->type) {
842 case e1000_ich10lan:
843 case e1000_pchlan:
844 mask |= (1 << 18);
845 break;
846 default:
847 break;
848 }
847 for (i = 0; i < mac->rar_entry_count; i++) 849 for (i = 0; i < mac->rar_entry_count; i++)
848 REG_PATTERN_TEST_ARRAY(E1000_RA, ((i << 1) + 1), 850 REG_PATTERN_TEST_ARRAY(E1000_RA, ((i << 1) + 1),
849 ((mac->type == e1000_ich10lan) ? 851 mask, 0xFFFFFFFF);
850 0x8007FFFF : 0x8003FFFF),
851 0xFFFFFFFF);
852 852
853 for (i = 0; i < mac->mta_reg_count; i++) 853 for (i = 0; i < mac->mta_reg_count; i++)
854 REG_PATTERN_TEST_ARRAY(E1000_MTA, i, 0xFFFFFFFF, 0xFFFFFFFF); 854 REG_PATTERN_TEST_ARRAY(E1000_MTA, i, 0xFFFFFFFF, 0xFFFFFFFF);
@@ -1786,15 +1786,22 @@ static int e1000_set_wol(struct net_device *netdev,
1786/* bit defines for adapter->led_status */ 1786/* bit defines for adapter->led_status */
1787#define E1000_LED_ON 0 1787#define E1000_LED_ON 0
1788 1788
1789static void e1000_led_blink_callback(unsigned long data) 1789static void e1000e_led_blink_task(struct work_struct *work)
1790{ 1790{
1791 struct e1000_adapter *adapter = (struct e1000_adapter *) data; 1791 struct e1000_adapter *adapter = container_of(work,
1792 struct e1000_adapter, led_blink_task);
1792 1793
1793 if (test_and_change_bit(E1000_LED_ON, &adapter->led_status)) 1794 if (test_and_change_bit(E1000_LED_ON, &adapter->led_status))
1794 adapter->hw.mac.ops.led_off(&adapter->hw); 1795 adapter->hw.mac.ops.led_off(&adapter->hw);
1795 else 1796 else
1796 adapter->hw.mac.ops.led_on(&adapter->hw); 1797 adapter->hw.mac.ops.led_on(&adapter->hw);
1798}
1799
1800static void e1000_led_blink_callback(unsigned long data)
1801{
1802 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
1797 1803
1804 schedule_work(&adapter->led_blink_task);
1798 mod_timer(&adapter->blink_timer, jiffies + E1000_ID_INTERVAL); 1805 mod_timer(&adapter->blink_timer, jiffies + E1000_ID_INTERVAL);
1799} 1806}
1800 1807
@@ -1807,7 +1814,9 @@ static int e1000_phys_id(struct net_device *netdev, u32 data)
1807 data = INT_MAX; 1814 data = INT_MAX;
1808 1815
1809 if ((hw->phy.type == e1000_phy_ife) || 1816 if ((hw->phy.type == e1000_phy_ife) ||
1817 (hw->mac.type == e1000_pchlan) ||
1810 (hw->mac.type == e1000_82574)) { 1818 (hw->mac.type == e1000_82574)) {
1819 INIT_WORK(&adapter->led_blink_task, e1000e_led_blink_task);
1811 if (!adapter->blink_timer.function) { 1820 if (!adapter->blink_timer.function) {
1812 init_timer(&adapter->blink_timer); 1821 init_timer(&adapter->blink_timer);
1813 adapter->blink_timer.function = 1822 adapter->blink_timer.function =
diff --git a/drivers/net/e1000e/hw.h b/drivers/net/e1000e/hw.h
index 6cdb703be951..fce3f0529e4c 100644
--- a/drivers/net/e1000e/hw.h
+++ b/drivers/net/e1000e/hw.h
@@ -193,7 +193,11 @@ enum e1e_registers {
193 E1000_RXCSUM = 0x05000, /* Rx Checksum Control - RW */ 193 E1000_RXCSUM = 0x05000, /* Rx Checksum Control - RW */
194 E1000_RFCTL = 0x05008, /* Receive Filter Control */ 194 E1000_RFCTL = 0x05008, /* Receive Filter Control */
195 E1000_MTA = 0x05200, /* Multicast Table Array - RW Array */ 195 E1000_MTA = 0x05200, /* Multicast Table Array - RW Array */
196 E1000_RA = 0x05400, /* Receive Address - RW Array */ 196 E1000_RAL_BASE = 0x05400, /* Receive Address Low - RW */
197#define E1000_RAL(_n) (E1000_RAL_BASE + ((_n) * 8))
198#define E1000_RA (E1000_RAL(0))
199 E1000_RAH_BASE = 0x05404, /* Receive Address High - RW */
200#define E1000_RAH(_n) (E1000_RAH_BASE + ((_n) * 8))
197 E1000_VFTA = 0x05600, /* VLAN Filter Table Array - RW Array */ 201 E1000_VFTA = 0x05600, /* VLAN Filter Table Array - RW Array */
198 E1000_WUC = 0x05800, /* Wakeup Control - RW */ 202 E1000_WUC = 0x05800, /* Wakeup Control - RW */
199 E1000_WUFC = 0x05808, /* Wakeup Filter Control - RW */ 203 E1000_WUFC = 0x05808, /* Wakeup Filter Control - RW */
@@ -368,6 +372,10 @@ enum e1e_registers {
368#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 372#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
369#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 373#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
370#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 374#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
375#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
376#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
377#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
378#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
371 379
372#define E1000_REVISION_4 4 380#define E1000_REVISION_4 4
373 381
@@ -383,6 +391,7 @@ enum e1000_mac_type {
383 e1000_ich8lan, 391 e1000_ich8lan,
384 e1000_ich9lan, 392 e1000_ich9lan,
385 e1000_ich10lan, 393 e1000_ich10lan,
394 e1000_pchlan,
386}; 395};
387 396
388enum e1000_media_type { 397enum e1000_media_type {
@@ -417,6 +426,8 @@ enum e1000_phy_type {
417 e1000_phy_igp_3, 426 e1000_phy_igp_3,
418 e1000_phy_ife, 427 e1000_phy_ife,
419 e1000_phy_bm, 428 e1000_phy_bm,
429 e1000_phy_82578,
430 e1000_phy_82577,
420}; 431};
421 432
422enum e1000_bus_width { 433enum e1000_bus_width {
@@ -720,6 +731,7 @@ struct e1000_host_mng_command_info {
720 731
721/* Function pointers and static data for the MAC. */ 732/* Function pointers and static data for the MAC. */
722struct e1000_mac_operations { 733struct e1000_mac_operations {
734 s32 (*id_led_init)(struct e1000_hw *);
723 bool (*check_mng_mode)(struct e1000_hw *); 735 bool (*check_mng_mode)(struct e1000_hw *);
724 s32 (*check_for_link)(struct e1000_hw *); 736 s32 (*check_for_link)(struct e1000_hw *);
725 s32 (*cleanup_led)(struct e1000_hw *); 737 s32 (*cleanup_led)(struct e1000_hw *);
@@ -733,11 +745,13 @@ struct e1000_mac_operations {
733 s32 (*init_hw)(struct e1000_hw *); 745 s32 (*init_hw)(struct e1000_hw *);
734 s32 (*setup_link)(struct e1000_hw *); 746 s32 (*setup_link)(struct e1000_hw *);
735 s32 (*setup_physical_interface)(struct e1000_hw *); 747 s32 (*setup_physical_interface)(struct e1000_hw *);
748 s32 (*setup_led)(struct e1000_hw *);
736}; 749};
737 750
738/* Function pointers for the PHY. */ 751/* Function pointers for the PHY. */
739struct e1000_phy_operations { 752struct e1000_phy_operations {
740 s32 (*acquire_phy)(struct e1000_hw *); 753 s32 (*acquire_phy)(struct e1000_hw *);
754 s32 (*check_polarity)(struct e1000_hw *);
741 s32 (*check_reset_block)(struct e1000_hw *); 755 s32 (*check_reset_block)(struct e1000_hw *);
742 s32 (*commit_phy)(struct e1000_hw *); 756 s32 (*commit_phy)(struct e1000_hw *);
743 s32 (*force_speed_duplex)(struct e1000_hw *); 757 s32 (*force_speed_duplex)(struct e1000_hw *);
diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c
index b63d9878b0ac..b69c8190da30 100644
--- a/drivers/net/e1000e/ich8lan.c
+++ b/drivers/net/e1000e/ich8lan.c
@@ -48,6 +48,10 @@
48 * 82567LF-3 Gigabit Network Connection 48 * 82567LF-3 Gigabit Network Connection
49 * 82567LM-3 Gigabit Network Connection 49 * 82567LM-3 Gigabit Network Connection
50 * 82567LM-4 Gigabit Network Connection 50 * 82567LM-4 Gigabit Network Connection
51 * 82577LM Gigabit Network Connection
52 * 82577LC Gigabit Network Connection
53 * 82578DM Gigabit Network Connection
54 * 82578DC Gigabit Network Connection
51 */ 55 */
52 56
53#include <linux/netdevice.h> 57#include <linux/netdevice.h>
@@ -116,6 +120,8 @@
116#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300 120#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
117#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200 121#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
118 122
123#define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
124
119/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 125/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
120/* Offset 04h HSFSTS */ 126/* Offset 04h HSFSTS */
121union ich8_hws_flash_status { 127union ich8_hws_flash_status {
@@ -186,6 +192,14 @@ static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
186static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw); 192static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
187static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 193static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
188static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw); 194static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
195static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
196static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
197static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
198static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
199static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
200static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
201static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
202static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
189 203
190static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) 204static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
191{ 205{
@@ -213,6 +227,41 @@ static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
213#define ew32flash(reg,val) __ew32flash(hw, (reg), (val)) 227#define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
214 228
215/** 229/**
230 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
231 * @hw: pointer to the HW structure
232 *
233 * Initialize family-specific PHY parameters and function pointers.
234 **/
235static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
236{
237 struct e1000_phy_info *phy = &hw->phy;
238 s32 ret_val = 0;
239
240 phy->addr = 1;
241 phy->reset_delay_us = 100;
242
243 phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan;
244 phy->ops.read_phy_reg = e1000_read_phy_reg_hv;
245 phy->ops.write_phy_reg = e1000_write_phy_reg_hv;
246 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
247
248 phy->id = e1000_phy_unknown;
249 e1000e_get_phy_id(hw);
250 phy->type = e1000e_get_phy_type_from_id(phy->id);
251
252 if (phy->type == e1000_phy_82577) {
253 phy->ops.check_polarity = e1000_check_polarity_82577;
254 phy->ops.force_speed_duplex =
255 e1000_phy_force_speed_duplex_82577;
256 phy->ops.get_cable_length = e1000_get_cable_length_82577;
257 phy->ops.get_phy_info = e1000_get_phy_info_82577;
258 phy->ops.commit_phy = e1000e_phy_sw_reset;
259 }
260
261 return ret_val;
262}
263
264/**
216 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers 265 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
217 * @hw: pointer to the HW structure 266 * @hw: pointer to the HW structure
218 * 267 *
@@ -273,6 +322,8 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
273 break; 322 break;
274 } 323 }
275 324
325 phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan;
326
276 return 0; 327 return 0;
277} 328}
278 329
@@ -358,6 +409,36 @@ static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
358 /* Set if manageability features are enabled. */ 409 /* Set if manageability features are enabled. */
359 mac->arc_subsystem_valid = 1; 410 mac->arc_subsystem_valid = 1;
360 411
412 /* LED operations */
413 switch (mac->type) {
414 case e1000_ich8lan:
415 case e1000_ich9lan:
416 case e1000_ich10lan:
417 /* ID LED init */
418 mac->ops.id_led_init = e1000e_id_led_init;
419 /* setup LED */
420 mac->ops.setup_led = e1000e_setup_led_generic;
421 /* cleanup LED */
422 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
423 /* turn on/off LED */
424 mac->ops.led_on = e1000_led_on_ich8lan;
425 mac->ops.led_off = e1000_led_off_ich8lan;
426 break;
427 case e1000_pchlan:
428 /* ID LED init */
429 mac->ops.id_led_init = e1000_id_led_init_pchlan;
430 /* setup LED */
431 mac->ops.setup_led = e1000_setup_led_pchlan;
432 /* cleanup LED */
433 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
434 /* turn on/off LED */
435 mac->ops.led_on = e1000_led_on_pchlan;
436 mac->ops.led_off = e1000_led_off_pchlan;
437 break;
438 default:
439 break;
440 }
441
361 /* Enable PCS Lock-loss workaround for ICH8 */ 442 /* Enable PCS Lock-loss workaround for ICH8 */
362 if (mac->type == e1000_ich8lan) 443 if (mac->type == e1000_ich8lan)
363 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1); 444 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1);
@@ -378,7 +459,10 @@ static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
378 if (rc) 459 if (rc)
379 return rc; 460 return rc;
380 461
381 rc = e1000_init_phy_params_ich8lan(hw); 462 if (hw->mac.type == e1000_pchlan)
463 rc = e1000_init_phy_params_pchlan(hw);
464 else
465 rc = e1000_init_phy_params_ich8lan(hw);
382 if (rc) 466 if (rc)
383 return rc; 467 return rc;
384 468
@@ -415,12 +499,15 @@ static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
415 499
416 while (timeout) { 500 while (timeout) {
417 extcnf_ctrl = er32(EXTCNF_CTRL); 501 extcnf_ctrl = er32(EXTCNF_CTRL);
418 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
419 ew32(EXTCNF_CTRL, extcnf_ctrl);
420 502
421 extcnf_ctrl = er32(EXTCNF_CTRL); 503 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) {
422 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 504 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
423 break; 505 ew32(EXTCNF_CTRL, extcnf_ctrl);
506
507 extcnf_ctrl = er32(EXTCNF_CTRL);
508 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
509 break;
510 }
424 mdelay(1); 511 mdelay(1);
425 timeout--; 512 timeout--;
426 } 513 }
@@ -560,6 +647,53 @@ static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
560} 647}
561 648
562/** 649/**
650 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
651 * done after every PHY reset.
652 **/
653static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
654{
655 s32 ret_val = 0;
656
657 if (hw->mac.type != e1000_pchlan)
658 return ret_val;
659
660 if (((hw->phy.type == e1000_phy_82577) &&
661 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
662 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
663 /* Disable generation of early preamble */
664 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
665 if (ret_val)
666 return ret_val;
667
668 /* Preamble tuning for SSC */
669 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
670 if (ret_val)
671 return ret_val;
672 }
673
674 if (hw->phy.type == e1000_phy_82578) {
675 /*
676 * Return registers to default by doing a soft reset then
677 * writing 0x3140 to the control register.
678 */
679 if (hw->phy.revision < 2) {
680 e1000e_phy_sw_reset(hw);
681 ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
682 }
683 }
684
685 /* Select page 0 */
686 ret_val = hw->phy.ops.acquire_phy(hw);
687 if (ret_val)
688 return ret_val;
689 hw->phy.addr = 1;
690 e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
691 hw->phy.ops.release_phy(hw);
692
693 return ret_val;
694}
695
696/**
563 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 697 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
564 * @hw: pointer to the HW structure 698 * @hw: pointer to the HW structure
565 * 699 *
@@ -580,6 +714,12 @@ static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
580 if (ret_val) 714 if (ret_val)
581 return ret_val; 715 return ret_val;
582 716
717 if (hw->mac.type == e1000_pchlan) {
718 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
719 if (ret_val)
720 return ret_val;
721 }
722
583 /* 723 /*
584 * Initialize the PHY from the NVM on ICH platforms. This 724 * Initialize the PHY from the NVM on ICH platforms. This
585 * is needed due to an issue where the NVM configuration is 725 * is needed due to an issue where the NVM configuration is
@@ -706,7 +846,7 @@ static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
706 phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE)); 846 phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE));
707 847
708 if (phy->polarity_correction) { 848 if (phy->polarity_correction) {
709 ret_val = e1000_check_polarity_ife_ich8lan(hw); 849 ret_val = phy->ops.check_polarity(hw);
710 if (ret_val) 850 if (ret_val)
711 return ret_val; 851 return ret_val;
712 } else { 852 } else {
@@ -746,6 +886,8 @@ static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
746 break; 886 break;
747 case e1000_phy_igp_3: 887 case e1000_phy_igp_3:
748 case e1000_phy_bm: 888 case e1000_phy_bm:
889 case e1000_phy_82578:
890 case e1000_phy_82577:
749 return e1000e_get_phy_info_igp(hw); 891 return e1000e_get_phy_info_igp(hw);
750 break; 892 break;
751 default: 893 default:
@@ -1857,6 +1999,79 @@ static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
1857} 1999}
1858 2000
1859/** 2001/**
2002 * e1000_id_led_init_pchlan - store LED configurations
2003 * @hw: pointer to the HW structure
2004 *
2005 * PCH does not control LEDs via the LEDCTL register, rather it uses
2006 * the PHY LED configuration register.
2007 *
2008 * PCH also does not have an "always on" or "always off" mode which
2009 * complicates the ID feature. Instead of using the "on" mode to indicate
2010 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2011 * use "link_up" mode. The LEDs will still ID on request if there is no
2012 * link based on logic in e1000_led_[on|off]_pchlan().
2013 **/
2014static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2015{
2016 struct e1000_mac_info *mac = &hw->mac;
2017 s32 ret_val;
2018 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2019 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2020 u16 data, i, temp, shift;
2021
2022 /* Get default ID LED modes */
2023 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2024 if (ret_val)
2025 goto out;
2026
2027 mac->ledctl_default = er32(LEDCTL);
2028 mac->ledctl_mode1 = mac->ledctl_default;
2029 mac->ledctl_mode2 = mac->ledctl_default;
2030
2031 for (i = 0; i < 4; i++) {
2032 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2033 shift = (i * 5);
2034 switch (temp) {
2035 case ID_LED_ON1_DEF2:
2036 case ID_LED_ON1_ON2:
2037 case ID_LED_ON1_OFF2:
2038 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2039 mac->ledctl_mode1 |= (ledctl_on << shift);
2040 break;
2041 case ID_LED_OFF1_DEF2:
2042 case ID_LED_OFF1_ON2:
2043 case ID_LED_OFF1_OFF2:
2044 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2045 mac->ledctl_mode1 |= (ledctl_off << shift);
2046 break;
2047 default:
2048 /* Do nothing */
2049 break;
2050 }
2051 switch (temp) {
2052 case ID_LED_DEF1_ON2:
2053 case ID_LED_ON1_ON2:
2054 case ID_LED_OFF1_ON2:
2055 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2056 mac->ledctl_mode2 |= (ledctl_on << shift);
2057 break;
2058 case ID_LED_DEF1_OFF2:
2059 case ID_LED_ON1_OFF2:
2060 case ID_LED_OFF1_OFF2:
2061 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2062 mac->ledctl_mode2 |= (ledctl_off << shift);
2063 break;
2064 default:
2065 /* Do nothing */
2066 break;
2067 }
2068 }
2069
2070out:
2071 return ret_val;
2072}
2073
2074/**
1860 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width 2075 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
1861 * @hw: pointer to the HW structure 2076 * @hw: pointer to the HW structure
1862 * 2077 *
@@ -1965,6 +2180,9 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
1965 kab |= E1000_KABGTXD_BGSQLBIAS; 2180 kab |= E1000_KABGTXD_BGSQLBIAS;
1966 ew32(KABGTXD, kab); 2181 ew32(KABGTXD, kab);
1967 2182
2183 if (hw->mac.type == e1000_pchlan)
2184 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2185
1968 return ret_val; 2186 return ret_val;
1969} 2187}
1970 2188
@@ -1990,7 +2208,7 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
1990 e1000_initialize_hw_bits_ich8lan(hw); 2208 e1000_initialize_hw_bits_ich8lan(hw);
1991 2209
1992 /* Initialize identification LED */ 2210 /* Initialize identification LED */
1993 ret_val = e1000e_id_led_init(hw); 2211 ret_val = mac->ops.id_led_init(hw);
1994 if (ret_val) { 2212 if (ret_val) {
1995 hw_dbg(hw, "Error initializing identification LED\n"); 2213 hw_dbg(hw, "Error initializing identification LED\n");
1996 return ret_val; 2214 return ret_val;
@@ -2036,6 +2254,16 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2036 ew32(CTRL_EXT, ctrl_ext); 2254 ew32(CTRL_EXT, ctrl_ext);
2037 2255
2038 /* 2256 /*
2257 * The 82578 Rx buffer will stall if wakeup is enabled in host and
2258 * the ME. Reading the BM_WUC register will clear the host wakeup bit.
2259 * Reset the phy after disabling host wakeup to reset the Rx buffer.
2260 */
2261 if (hw->phy.type == e1000_phy_82578) {
2262 e1e_rphy(hw, BM_WUC, &i);
2263 e1000e_phy_hw_reset_generic(hw);
2264 }
2265
2266 /*
2039 * Clear all of the statistics registers (clear on read). It is 2267 * Clear all of the statistics registers (clear on read). It is
2040 * important that we do this after we have tried to establish link 2268 * important that we do this after we have tried to establish link
2041 * because the symbol error count will increment wildly if there 2269 * because the symbol error count will increment wildly if there
@@ -2059,6 +2287,9 @@ static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2059 /* Extended Device Control */ 2287 /* Extended Device Control */
2060 reg = er32(CTRL_EXT); 2288 reg = er32(CTRL_EXT);
2061 reg |= (1 << 22); 2289 reg |= (1 << 22);
2290 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
2291 if (hw->mac.type >= e1000_pchlan)
2292 reg |= E1000_CTRL_EXT_PHYPDEN;
2062 ew32(CTRL_EXT, reg); 2293 ew32(CTRL_EXT, reg);
2063 2294
2064 /* Transmit Descriptor Control 0 */ 2295 /* Transmit Descriptor Control 0 */
@@ -2135,6 +2366,14 @@ static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2135 return ret_val; 2366 return ret_val;
2136 2367
2137 ew32(FCTTV, hw->fc.pause_time); 2368 ew32(FCTTV, hw->fc.pause_time);
2369 if ((hw->phy.type == e1000_phy_82578) ||
2370 (hw->phy.type == e1000_phy_82577)) {
2371 ret_val = hw->phy.ops.write_phy_reg(hw,
2372 PHY_REG(BM_PORT_CTRL_PAGE, 27),
2373 hw->fc.pause_time);
2374 if (ret_val)
2375 return ret_val;
2376 }
2138 2377
2139 return e1000e_set_fc_watermarks(hw); 2378 return e1000e_set_fc_watermarks(hw);
2140} 2379}
@@ -2174,18 +2413,26 @@ static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2174 if (ret_val) 2413 if (ret_val)
2175 return ret_val; 2414 return ret_val;
2176 2415
2177 if (hw->phy.type == e1000_phy_igp_3) { 2416 switch (hw->phy.type) {
2417 case e1000_phy_igp_3:
2178 ret_val = e1000e_copper_link_setup_igp(hw); 2418 ret_val = e1000e_copper_link_setup_igp(hw);
2179 if (ret_val) 2419 if (ret_val)
2180 return ret_val; 2420 return ret_val;
2181 } else if (hw->phy.type == e1000_phy_bm) { 2421 break;
2422 case e1000_phy_bm:
2423 case e1000_phy_82578:
2182 ret_val = e1000e_copper_link_setup_m88(hw); 2424 ret_val = e1000e_copper_link_setup_m88(hw);
2183 if (ret_val) 2425 if (ret_val)
2184 return ret_val; 2426 return ret_val;
2185 } 2427 break;
2186 2428 case e1000_phy_82577:
2187 if (hw->phy.type == e1000_phy_ife) { 2429 ret_val = e1000_copper_link_setup_82577(hw);
2188 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data); 2430 if (ret_val)
2431 return ret_val;
2432 break;
2433 case e1000_phy_ife:
2434 ret_val = hw->phy.ops.read_phy_reg(hw, IFE_PHY_MDIX_CONTROL,
2435 &reg_data);
2189 if (ret_val) 2436 if (ret_val)
2190 return ret_val; 2437 return ret_val;
2191 2438
@@ -2203,9 +2450,13 @@ static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2203 reg_data |= IFE_PMC_AUTO_MDIX; 2450 reg_data |= IFE_PMC_AUTO_MDIX;
2204 break; 2451 break;
2205 } 2452 }
2206 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data); 2453 ret_val = hw->phy.ops.write_phy_reg(hw, IFE_PHY_MDIX_CONTROL,
2454 reg_data);
2207 if (ret_val) 2455 if (ret_val)
2208 return ret_val; 2456 return ret_val;
2457 break;
2458 default:
2459 break;
2209 } 2460 }
2210 return e1000e_setup_copper_link(hw); 2461 return e1000e_setup_copper_link(hw);
2211} 2462}
@@ -2422,18 +2673,26 @@ void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
2422 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation 2673 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
2423 * to a lower speed. 2674 * to a lower speed.
2424 * 2675 *
2425 * Should only be called for ICH9 and ICH10 devices. 2676 * Should only be called for applicable parts.
2426 **/ 2677 **/
2427void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw) 2678void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
2428{ 2679{
2429 u32 phy_ctrl; 2680 u32 phy_ctrl;
2430 2681
2431 if ((hw->mac.type == e1000_ich10lan) || 2682 switch (hw->mac.type) {
2432 (hw->mac.type == e1000_ich9lan)) { 2683 case e1000_ich9lan:
2684 case e1000_ich10lan:
2685 case e1000_pchlan:
2433 phy_ctrl = er32(PHY_CTRL); 2686 phy_ctrl = er32(PHY_CTRL);
2434 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | 2687 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
2435 E1000_PHY_CTRL_GBE_DISABLE; 2688 E1000_PHY_CTRL_GBE_DISABLE;
2436 ew32(PHY_CTRL, phy_ctrl); 2689 ew32(PHY_CTRL, phy_ctrl);
2690
2691 /* Workaround SWFLAG unexpectedly set during S0->Sx */
2692 if (hw->mac.type == e1000_pchlan)
2693 udelay(500);
2694 default:
2695 break;
2437 } 2696 }
2438 2697
2439 return; 2698 return;
@@ -2487,13 +2746,99 @@ static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
2487} 2746}
2488 2747
2489/** 2748/**
2749 * e1000_setup_led_pchlan - Configures SW controllable LED
2750 * @hw: pointer to the HW structure
2751 *
2752 * This prepares the SW controllable LED for use.
2753 **/
2754static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
2755{
2756 return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG,
2757 (u16)hw->mac.ledctl_mode1);
2758}
2759
2760/**
2761 * e1000_cleanup_led_pchlan - Restore the default LED operation
2762 * @hw: pointer to the HW structure
2763 *
2764 * Return the LED back to the default configuration.
2765 **/
2766static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
2767{
2768 return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG,
2769 (u16)hw->mac.ledctl_default);
2770}
2771
2772/**
2773 * e1000_led_on_pchlan - Turn LEDs on
2774 * @hw: pointer to the HW structure
2775 *
2776 * Turn on the LEDs.
2777 **/
2778static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
2779{
2780 u16 data = (u16)hw->mac.ledctl_mode2;
2781 u32 i, led;
2782
2783 /*
2784 * If no link, then turn LED on by setting the invert bit
2785 * for each LED that's mode is "link_up" in ledctl_mode2.
2786 */
2787 if (!(er32(STATUS) & E1000_STATUS_LU)) {
2788 for (i = 0; i < 3; i++) {
2789 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
2790 if ((led & E1000_PHY_LED0_MODE_MASK) !=
2791 E1000_LEDCTL_MODE_LINK_UP)
2792 continue;
2793 if (led & E1000_PHY_LED0_IVRT)
2794 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
2795 else
2796 data |= (E1000_PHY_LED0_IVRT << (i * 5));
2797 }
2798 }
2799
2800 return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data);
2801}
2802
2803/**
2804 * e1000_led_off_pchlan - Turn LEDs off
2805 * @hw: pointer to the HW structure
2806 *
2807 * Turn off the LEDs.
2808 **/
2809static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
2810{
2811 u16 data = (u16)hw->mac.ledctl_mode1;
2812 u32 i, led;
2813
2814 /*
2815 * If no link, then turn LED off by clearing the invert bit
2816 * for each LED that's mode is "link_up" in ledctl_mode1.
2817 */
2818 if (!(er32(STATUS) & E1000_STATUS_LU)) {
2819 for (i = 0; i < 3; i++) {
2820 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
2821 if ((led & E1000_PHY_LED0_MODE_MASK) !=
2822 E1000_LEDCTL_MODE_LINK_UP)
2823 continue;
2824 if (led & E1000_PHY_LED0_IVRT)
2825 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
2826 else
2827 data |= (E1000_PHY_LED0_IVRT << (i * 5));
2828 }
2829 }
2830
2831 return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data);
2832}
2833
2834/**
2490 * e1000_get_cfg_done_ich8lan - Read config done bit 2835 * e1000_get_cfg_done_ich8lan - Read config done bit
2491 * @hw: pointer to the HW structure 2836 * @hw: pointer to the HW structure
2492 * 2837 *
2493 * Read the management control register for the config done bit for 2838 * Read the management control register for the config done bit for
2494 * completion status. NOTE: silicon which is EEPROM-less will fail trying 2839 * completion status. NOTE: silicon which is EEPROM-less will fail trying
2495 * to read the config done bit, so an error is *ONLY* logged and returns 2840 * to read the config done bit, so an error is *ONLY* logged and returns
2496 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon 2841 * 0. If we were to return with error, EEPROM-less silicon
2497 * would not be able to be reset or change link. 2842 * would not be able to be reset or change link.
2498 **/ 2843 **/
2499static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) 2844static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
@@ -2503,7 +2848,8 @@ static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
2503 e1000e_get_cfg_done(hw); 2848 e1000e_get_cfg_done(hw);
2504 2849
2505 /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 2850 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
2506 if (hw->mac.type != e1000_ich10lan) { 2851 if ((hw->mac.type != e1000_ich10lan) &&
2852 (hw->mac.type != e1000_pchlan)) {
2507 if (((er32(EECD) & E1000_EECD_PRES) == 0) && 2853 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
2508 (hw->phy.type == e1000_phy_igp_3)) { 2854 (hw->phy.type == e1000_phy_igp_3)) {
2509 e1000e_phy_init_script_igp3(hw); 2855 e1000e_phy_init_script_igp3(hw);
@@ -2529,6 +2875,7 @@ static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
2529static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) 2875static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
2530{ 2876{
2531 u32 temp; 2877 u32 temp;
2878 u16 phy_data;
2532 2879
2533 e1000e_clear_hw_cntrs_base(hw); 2880 e1000e_clear_hw_cntrs_base(hw);
2534 2881
@@ -2546,22 +2893,42 @@ static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
2546 temp = er32(IAC); 2893 temp = er32(IAC);
2547 temp = er32(ICRXOC); 2894 temp = er32(ICRXOC);
2548 2895
2896 /* Clear PHY statistics registers */
2897 if ((hw->phy.type == e1000_phy_82578) ||
2898 (hw->phy.type == e1000_phy_82577)) {
2899 hw->phy.ops.read_phy_reg(hw, HV_SCC_UPPER, &phy_data);
2900 hw->phy.ops.read_phy_reg(hw, HV_SCC_LOWER, &phy_data);
2901 hw->phy.ops.read_phy_reg(hw, HV_ECOL_UPPER, &phy_data);
2902 hw->phy.ops.read_phy_reg(hw, HV_ECOL_LOWER, &phy_data);
2903 hw->phy.ops.read_phy_reg(hw, HV_MCC_UPPER, &phy_data);
2904 hw->phy.ops.read_phy_reg(hw, HV_MCC_LOWER, &phy_data);
2905 hw->phy.ops.read_phy_reg(hw, HV_LATECOL_UPPER, &phy_data);
2906 hw->phy.ops.read_phy_reg(hw, HV_LATECOL_LOWER, &phy_data);
2907 hw->phy.ops.read_phy_reg(hw, HV_COLC_UPPER, &phy_data);
2908 hw->phy.ops.read_phy_reg(hw, HV_COLC_LOWER, &phy_data);
2909 hw->phy.ops.read_phy_reg(hw, HV_DC_UPPER, &phy_data);
2910 hw->phy.ops.read_phy_reg(hw, HV_DC_LOWER, &phy_data);
2911 hw->phy.ops.read_phy_reg(hw, HV_TNCRS_UPPER, &phy_data);
2912 hw->phy.ops.read_phy_reg(hw, HV_TNCRS_LOWER, &phy_data);
2913 }
2549} 2914}
2550 2915
2551static struct e1000_mac_operations ich8_mac_ops = { 2916static struct e1000_mac_operations ich8_mac_ops = {
2917 .id_led_init = e1000e_id_led_init,
2552 .check_mng_mode = e1000_check_mng_mode_ich8lan, 2918 .check_mng_mode = e1000_check_mng_mode_ich8lan,
2553 .check_for_link = e1000e_check_for_copper_link, 2919 .check_for_link = e1000e_check_for_copper_link,
2554 .cleanup_led = e1000_cleanup_led_ich8lan, 2920 /* cleanup_led dependent on mac type */
2555 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan, 2921 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
2556 .get_bus_info = e1000_get_bus_info_ich8lan, 2922 .get_bus_info = e1000_get_bus_info_ich8lan,
2557 .get_link_up_info = e1000_get_link_up_info_ich8lan, 2923 .get_link_up_info = e1000_get_link_up_info_ich8lan,
2558 .led_on = e1000_led_on_ich8lan, 2924 /* led_on dependent on mac type */
2559 .led_off = e1000_led_off_ich8lan, 2925 /* led_off dependent on mac type */
2560 .update_mc_addr_list = e1000e_update_mc_addr_list_generic, 2926 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
2561 .reset_hw = e1000_reset_hw_ich8lan, 2927 .reset_hw = e1000_reset_hw_ich8lan,
2562 .init_hw = e1000_init_hw_ich8lan, 2928 .init_hw = e1000_init_hw_ich8lan,
2563 .setup_link = e1000_setup_link_ich8lan, 2929 .setup_link = e1000_setup_link_ich8lan,
2564 .setup_physical_interface= e1000_setup_copper_link_ich8lan, 2930 .setup_physical_interface= e1000_setup_copper_link_ich8lan,
2931 /* id_led_init dependent on mac type */
2565}; 2932};
2566 2933
2567static struct e1000_phy_operations ich8_phy_ops = { 2934static struct e1000_phy_operations ich8_phy_ops = {
@@ -2644,3 +3011,21 @@ struct e1000_info e1000_ich10_info = {
2644 .phy_ops = &ich8_phy_ops, 3011 .phy_ops = &ich8_phy_ops,
2645 .nvm_ops = &ich8_nvm_ops, 3012 .nvm_ops = &ich8_nvm_ops,
2646}; 3013};
3014
3015struct e1000_info e1000_pch_info = {
3016 .mac = e1000_pchlan,
3017 .flags = FLAG_IS_ICH
3018 | FLAG_HAS_WOL
3019 | FLAG_RX_CSUM_ENABLED
3020 | FLAG_HAS_CTRLEXT_ON_LOAD
3021 | FLAG_HAS_AMT
3022 | FLAG_HAS_FLASH
3023 | FLAG_HAS_JUMBO_FRAMES
3024 | FLAG_APME_IN_WUC,
3025 .pba = 26,
3026 .max_hw_frame_size = 4096,
3027 .get_variants = e1000_get_variants_ich8lan,
3028 .mac_ops = &ich8_mac_ops,
3029 .phy_ops = &ich8_phy_ops,
3030 .nvm_ops = &ich8_nvm_ops,
3031};
diff --git a/drivers/net/e1000e/lib.c b/drivers/net/e1000e/lib.c
index 18a4f5902f3b..be6d9e990374 100644
--- a/drivers/net/e1000e/lib.c
+++ b/drivers/net/e1000e/lib.c
@@ -378,6 +378,12 @@ s32 e1000e_check_for_copper_link(struct e1000_hw *hw)
378 378
379 mac->get_link_status = 0; 379 mac->get_link_status = 0;
380 380
381 if (hw->phy.type == e1000_phy_82578) {
382 ret_val = e1000_link_stall_workaround_hv(hw);
383 if (ret_val)
384 return ret_val;
385 }
386
381 /* 387 /*
382 * Check if there was DownShift, must be checked 388 * Check if there was DownShift, must be checked
383 * immediately after link-up 389 * immediately after link-up
@@ -1406,6 +1412,38 @@ s32 e1000e_id_led_init(struct e1000_hw *hw)
1406} 1412}
1407 1413
1408/** 1414/**
1415 * e1000e_setup_led_generic - Configures SW controllable LED
1416 * @hw: pointer to the HW structure
1417 *
1418 * This prepares the SW controllable LED for use and saves the current state
1419 * of the LED so it can be later restored.
1420 **/
1421s32 e1000e_setup_led_generic(struct e1000_hw *hw)
1422{
1423 u32 ledctl;
1424
1425 if (hw->mac.ops.setup_led != e1000e_setup_led_generic) {
1426 return -E1000_ERR_CONFIG;
1427 }
1428
1429 if (hw->phy.media_type == e1000_media_type_fiber) {
1430 ledctl = er32(LEDCTL);
1431 hw->mac.ledctl_default = ledctl;
1432 /* Turn off LED0 */
1433 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
1434 E1000_LEDCTL_LED0_BLINK |
1435 E1000_LEDCTL_LED0_MODE_MASK);
1436 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1437 E1000_LEDCTL_LED0_MODE_SHIFT);
1438 ew32(LEDCTL, ledctl);
1439 } else if (hw->phy.media_type == e1000_media_type_copper) {
1440 ew32(LEDCTL, hw->mac.ledctl_mode1);
1441 }
1442
1443 return 0;
1444}
1445
1446/**
1409 * e1000e_cleanup_led_generic - Set LED config to default operation 1447 * e1000e_cleanup_led_generic - Set LED config to default operation
1410 * @hw: pointer to the HW structure 1448 * @hw: pointer to the HW structure
1411 * 1449 *
diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c
index 4072fbb6493d..2cb704dd9546 100644
--- a/drivers/net/e1000e/netdev.c
+++ b/drivers/net/e1000e/netdev.c
@@ -62,6 +62,7 @@ static const struct e1000_info *e1000_info_tbl[] = {
62 [board_ich8lan] = &e1000_ich8_info, 62 [board_ich8lan] = &e1000_ich8_info,
63 [board_ich9lan] = &e1000_ich9_info, 63 [board_ich9lan] = &e1000_ich9_info,
64 [board_ich10lan] = &e1000_ich10_info, 64 [board_ich10lan] = &e1000_ich10_info,
65 [board_pchlan] = &e1000_pch_info,
65}; 66};
66 67
67#ifdef DEBUG 68#ifdef DEBUG
@@ -2308,6 +2309,23 @@ static void e1000_setup_rctl(struct e1000_adapter *adapter)
2308 if (adapter->flags2 & FLAG2_CRC_STRIPPING) 2309 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
2309 rctl |= E1000_RCTL_SECRC; 2310 rctl |= E1000_RCTL_SECRC;
2310 2311
2312 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
2313 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
2314 u16 phy_data;
2315
2316 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
2317 phy_data &= 0xfff8;
2318 phy_data |= (1 << 2);
2319 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
2320
2321 e1e_rphy(hw, 22, &phy_data);
2322 phy_data &= 0x0fff;
2323 phy_data |= (1 << 14);
2324 e1e_wphy(hw, 0x10, 0x2823);
2325 e1e_wphy(hw, 0x11, 0x0003);
2326 e1e_wphy(hw, 22, phy_data);
2327 }
2328
2311 /* Setup buffer sizes */ 2329 /* Setup buffer sizes */
2312 rctl &= ~E1000_RCTL_SZ_4096; 2330 rctl &= ~E1000_RCTL_SZ_4096;
2313 rctl |= E1000_RCTL_BSEX; 2331 rctl |= E1000_RCTL_BSEX;
@@ -2789,6 +2807,8 @@ void e1000e_reset(struct e1000_adapter *adapter)
2789 e1000_get_hw_control(adapter); 2807 e1000_get_hw_control(adapter);
2790 2808
2791 ew32(WUC, 0); 2809 ew32(WUC, 0);
2810 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP)
2811 e1e_wphy(&adapter->hw, BM_WUC, 0);
2792 2812
2793 if (mac->ops.init_hw(hw)) 2813 if (mac->ops.init_hw(hw))
2794 e_err("Hardware Error\n"); 2814 e_err("Hardware Error\n");
@@ -3269,6 +3289,7 @@ void e1000e_update_stats(struct e1000_adapter *adapter)
3269{ 3289{
3270 struct e1000_hw *hw = &adapter->hw; 3290 struct e1000_hw *hw = &adapter->hw;
3271 struct pci_dev *pdev = adapter->pdev; 3291 struct pci_dev *pdev = adapter->pdev;
3292 u16 phy_data;
3272 3293
3273 /* 3294 /*
3274 * Prevent stats update while adapter is being reset, or if the pci 3295 * Prevent stats update while adapter is being reset, or if the pci
@@ -3288,11 +3309,34 @@ void e1000e_update_stats(struct e1000_adapter *adapter)
3288 adapter->stats.roc += er32(ROC); 3309 adapter->stats.roc += er32(ROC);
3289 3310
3290 adapter->stats.mpc += er32(MPC); 3311 adapter->stats.mpc += er32(MPC);
3291 adapter->stats.scc += er32(SCC); 3312 if ((hw->phy.type == e1000_phy_82578) ||
3292 adapter->stats.ecol += er32(ECOL); 3313 (hw->phy.type == e1000_phy_82577)) {
3293 adapter->stats.mcc += er32(MCC); 3314 e1e_rphy(hw, HV_SCC_UPPER, &phy_data);
3294 adapter->stats.latecol += er32(LATECOL); 3315 e1e_rphy(hw, HV_SCC_LOWER, &phy_data);
3295 adapter->stats.dc += er32(DC); 3316 adapter->stats.scc += phy_data;
3317
3318 e1e_rphy(hw, HV_ECOL_UPPER, &phy_data);
3319 e1e_rphy(hw, HV_ECOL_LOWER, &phy_data);
3320 adapter->stats.ecol += phy_data;
3321
3322 e1e_rphy(hw, HV_MCC_UPPER, &phy_data);
3323 e1e_rphy(hw, HV_MCC_LOWER, &phy_data);
3324 adapter->stats.mcc += phy_data;
3325
3326 e1e_rphy(hw, HV_LATECOL_UPPER, &phy_data);
3327 e1e_rphy(hw, HV_LATECOL_LOWER, &phy_data);
3328 adapter->stats.latecol += phy_data;
3329
3330 e1e_rphy(hw, HV_DC_UPPER, &phy_data);
3331 e1e_rphy(hw, HV_DC_LOWER, &phy_data);
3332 adapter->stats.dc += phy_data;
3333 } else {
3334 adapter->stats.scc += er32(SCC);
3335 adapter->stats.ecol += er32(ECOL);
3336 adapter->stats.mcc += er32(MCC);
3337 adapter->stats.latecol += er32(LATECOL);
3338 adapter->stats.dc += er32(DC);
3339 }
3296 adapter->stats.xonrxc += er32(XONRXC); 3340 adapter->stats.xonrxc += er32(XONRXC);
3297 adapter->stats.xontxc += er32(XONTXC); 3341 adapter->stats.xontxc += er32(XONTXC);
3298 adapter->stats.xoffrxc += er32(XOFFRXC); 3342 adapter->stats.xoffrxc += er32(XOFFRXC);
@@ -3310,13 +3354,28 @@ void e1000e_update_stats(struct e1000_adapter *adapter)
3310 3354
3311 hw->mac.tx_packet_delta = er32(TPT); 3355 hw->mac.tx_packet_delta = er32(TPT);
3312 adapter->stats.tpt += hw->mac.tx_packet_delta; 3356 adapter->stats.tpt += hw->mac.tx_packet_delta;
3313 hw->mac.collision_delta = er32(COLC); 3357 if ((hw->phy.type == e1000_phy_82578) ||
3358 (hw->phy.type == e1000_phy_82577)) {
3359 e1e_rphy(hw, HV_COLC_UPPER, &phy_data);
3360 e1e_rphy(hw, HV_COLC_LOWER, &phy_data);
3361 hw->mac.collision_delta = phy_data;
3362 } else {
3363 hw->mac.collision_delta = er32(COLC);
3364 }
3314 adapter->stats.colc += hw->mac.collision_delta; 3365 adapter->stats.colc += hw->mac.collision_delta;
3315 3366
3316 adapter->stats.algnerrc += er32(ALGNERRC); 3367 adapter->stats.algnerrc += er32(ALGNERRC);
3317 adapter->stats.rxerrc += er32(RXERRC); 3368 adapter->stats.rxerrc += er32(RXERRC);
3318 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3369 if ((hw->phy.type == e1000_phy_82578) ||
3319 adapter->stats.tncrs += er32(TNCRS); 3370 (hw->phy.type == e1000_phy_82577)) {
3371 e1e_rphy(hw, HV_TNCRS_UPPER, &phy_data);
3372 e1e_rphy(hw, HV_TNCRS_LOWER, &phy_data);
3373 adapter->stats.tncrs += phy_data;
3374 } else {
3375 if ((hw->mac.type != e1000_82574) &&
3376 (hw->mac.type != e1000_82583))
3377 adapter->stats.tncrs += er32(TNCRS);
3378 }
3320 adapter->stats.cexterr += er32(CEXTERR); 3379 adapter->stats.cexterr += er32(CEXTERR);
3321 adapter->stats.tsctc += er32(TSCTC); 3380 adapter->stats.tsctc += er32(TSCTC);
3322 adapter->stats.tsctfc += er32(TSCTFC); 3381 adapter->stats.tsctfc += er32(TSCTFC);
@@ -4342,6 +4401,81 @@ static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4342 } 4401 }
4343} 4402}
4344 4403
4404static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
4405{
4406 struct e1000_hw *hw = &adapter->hw;
4407 u32 i, mac_reg;
4408 u16 phy_reg;
4409 int retval = 0;
4410
4411 /* copy MAC RARs to PHY RARs */
4412 for (i = 0; i < adapter->hw.mac.rar_entry_count; i++) {
4413 mac_reg = er32(RAL(i));
4414 e1e_wphy(hw, BM_RAR_L(i), (u16)(mac_reg & 0xFFFF));
4415 e1e_wphy(hw, BM_RAR_M(i), (u16)((mac_reg >> 16) & 0xFFFF));
4416 mac_reg = er32(RAH(i));
4417 e1e_wphy(hw, BM_RAR_H(i), (u16)(mac_reg & 0xFFFF));
4418 e1e_wphy(hw, BM_RAR_CTRL(i), (u16)((mac_reg >> 16) & 0xFFFF));
4419 }
4420
4421 /* copy MAC MTA to PHY MTA */
4422 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
4423 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
4424 e1e_wphy(hw, BM_MTA(i), (u16)(mac_reg & 0xFFFF));
4425 e1e_wphy(hw, BM_MTA(i) + 1, (u16)((mac_reg >> 16) & 0xFFFF));
4426 }
4427
4428 /* configure PHY Rx Control register */
4429 e1e_rphy(&adapter->hw, BM_RCTL, &phy_reg);
4430 mac_reg = er32(RCTL);
4431 if (mac_reg & E1000_RCTL_UPE)
4432 phy_reg |= BM_RCTL_UPE;
4433 if (mac_reg & E1000_RCTL_MPE)
4434 phy_reg |= BM_RCTL_MPE;
4435 phy_reg &= ~(BM_RCTL_MO_MASK);
4436 if (mac_reg & E1000_RCTL_MO_3)
4437 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
4438 << BM_RCTL_MO_SHIFT);
4439 if (mac_reg & E1000_RCTL_BAM)
4440 phy_reg |= BM_RCTL_BAM;
4441 if (mac_reg & E1000_RCTL_PMCF)
4442 phy_reg |= BM_RCTL_PMCF;
4443 mac_reg = er32(CTRL);
4444 if (mac_reg & E1000_CTRL_RFCE)
4445 phy_reg |= BM_RCTL_RFCE;
4446 e1e_wphy(&adapter->hw, BM_RCTL, phy_reg);
4447
4448 /* enable PHY wakeup in MAC register */
4449 ew32(WUFC, wufc);
4450 ew32(WUC, E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN);
4451
4452 /* configure and enable PHY wakeup in PHY registers */
4453 e1e_wphy(&adapter->hw, BM_WUFC, wufc);
4454 e1e_wphy(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
4455
4456 /* activate PHY wakeup */
4457 retval = hw->phy.ops.acquire_phy(hw);
4458 if (retval) {
4459 e_err("Could not acquire PHY\n");
4460 return retval;
4461 }
4462 e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4463 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
4464 retval = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg);
4465 if (retval) {
4466 e_err("Could not read PHY page 769\n");
4467 goto out;
4468 }
4469 phy_reg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
4470 retval = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
4471 if (retval)
4472 e_err("Could not set PHY Host Wakeup bit\n");
4473out:
4474 hw->phy.ops.release_phy(hw);
4475
4476 return retval;
4477}
4478
4345static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake) 4479static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake)
4346{ 4480{
4347 struct net_device *netdev = pci_get_drvdata(pdev); 4481 struct net_device *netdev = pci_get_drvdata(pdev);
@@ -4384,8 +4518,9 @@ static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake)
4384 #define E1000_CTRL_ADVD3WUC 0x00100000 4518 #define E1000_CTRL_ADVD3WUC 0x00100000
4385 /* phy power management enable */ 4519 /* phy power management enable */
4386 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 4520 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4387 ctrl |= E1000_CTRL_ADVD3WUC | 4521 ctrl |= E1000_CTRL_ADVD3WUC;
4388 E1000_CTRL_EN_PHY_PWR_MGMT; 4522 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
4523 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
4389 ew32(CTRL, ctrl); 4524 ew32(CTRL, ctrl);
4390 4525
4391 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 4526 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
@@ -4403,8 +4538,17 @@ static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake)
4403 /* Allow time for pending master requests to run */ 4538 /* Allow time for pending master requests to run */
4404 e1000e_disable_pcie_master(&adapter->hw); 4539 e1000e_disable_pcie_master(&adapter->hw);
4405 4540
4406 ew32(WUC, E1000_WUC_PME_EN); 4541 if ((adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) &&
4407 ew32(WUFC, wufc); 4542 !(hw->mac.ops.check_mng_mode(hw))) {
4543 /* enable wakeup by the PHY */
4544 retval = e1000_init_phy_wakeup(adapter, wufc);
4545 if (retval)
4546 return retval;
4547 } else {
4548 /* enable wakeup by the MAC */
4549 ew32(WUFC, wufc);
4550 ew32(WUC, E1000_WUC_PME_EN);
4551 }
4408 } else { 4552 } else {
4409 ew32(WUC, 0); 4553 ew32(WUC, 0);
4410 ew32(WUFC, 0); 4554 ew32(WUFC, 0);
@@ -4547,8 +4691,37 @@ static int e1000_resume(struct pci_dev *pdev)
4547 } 4691 }
4548 4692
4549 e1000e_power_up_phy(adapter); 4693 e1000e_power_up_phy(adapter);
4694
4695 /* report the system wakeup cause from S3/S4 */
4696 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
4697 u16 phy_data;
4698
4699 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
4700 if (phy_data) {
4701 e_info("PHY Wakeup cause - %s\n",
4702 phy_data & E1000_WUS_EX ? "Unicast Packet" :
4703 phy_data & E1000_WUS_MC ? "Multicast Packet" :
4704 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
4705 phy_data & E1000_WUS_MAG ? "Magic Packet" :
4706 phy_data & E1000_WUS_LNKC ? "Link Status "
4707 " Change" : "other");
4708 }
4709 e1e_wphy(&adapter->hw, BM_WUS, ~0);
4710 } else {
4711 u32 wus = er32(WUS);
4712 if (wus) {
4713 e_info("MAC Wakeup cause - %s\n",
4714 wus & E1000_WUS_EX ? "Unicast Packet" :
4715 wus & E1000_WUS_MC ? "Multicast Packet" :
4716 wus & E1000_WUS_BC ? "Broadcast Packet" :
4717 wus & E1000_WUS_MAG ? "Magic Packet" :
4718 wus & E1000_WUS_LNKC ? "Link Status Change" :
4719 "other");
4720 }
4721 ew32(WUS, ~0);
4722 }
4723
4550 e1000e_reset(adapter); 4724 e1000e_reset(adapter);
4551 ew32(WUS, ~0);
4552 4725
4553 e1000_init_manageability(adapter); 4726 e1000_init_manageability(adapter);
4554 4727
@@ -4994,6 +5167,8 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
4994 /* APME bit in EEPROM is mapped to WUC.APME */ 5167 /* APME bit in EEPROM is mapped to WUC.APME */
4995 eeprom_data = er32(WUC); 5168 eeprom_data = er32(WUC);
4996 eeprom_apme_mask = E1000_WUC_APME; 5169 eeprom_apme_mask = E1000_WUC_APME;
5170 if (eeprom_data & E1000_WUC_PHY_WAKE)
5171 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
4997 } else if (adapter->flags & FLAG_APME_IN_CTRL3) { 5172 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
4998 if (adapter->flags & FLAG_APME_CHECK_PORT_B && 5173 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
4999 (adapter->hw.bus.func == 1)) 5174 (adapter->hw.bus.func == 1))
@@ -5195,6 +5370,11 @@ static struct pci_device_id e1000_pci_tbl[] = {
5195 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan }, 5370 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
5196 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan }, 5371 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
5197 5372
5373 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
5374 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
5375 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
5376 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
5377
5198 { } /* terminate list */ 5378 { } /* terminate list */
5199}; 5379};
5200MODULE_DEVICE_TABLE(pci, e1000_pci_tbl); 5380MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
diff --git a/drivers/net/e1000e/phy.c b/drivers/net/e1000e/phy.c
index dc4a9cba6a73..e23459cf3d0e 100644
--- a/drivers/net/e1000e/phy.c
+++ b/drivers/net/e1000e/phy.c
@@ -37,6 +37,9 @@ static s32 e1000_wait_autoneg(struct e1000_hw *hw);
37static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg); 37static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
38static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 38static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
39 u16 *data, bool read); 39 u16 *data, bool read);
40static u32 e1000_get_phy_addr_for_hv_page(u32 page);
41static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
42 u16 *data, bool read);
40 43
41/* Cable length tables */ 44/* Cable length tables */
42static const u16 e1000_m88_cable_length_table[] = 45static const u16 e1000_m88_cable_length_table[] =
@@ -54,6 +57,55 @@ static const u16 e1000_igp_2_cable_length_table[] =
54#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 57#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
55 ARRAY_SIZE(e1000_igp_2_cable_length_table) 58 ARRAY_SIZE(e1000_igp_2_cable_length_table)
56 59
60#define BM_PHY_REG_PAGE(offset) \
61 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
62#define BM_PHY_REG_NUM(offset) \
63 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
64 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
65 ~MAX_PHY_REG_ADDRESS)))
66
67#define HV_INTC_FC_PAGE_START 768
68#define I82578_ADDR_REG 29
69#define I82577_ADDR_REG 16
70#define I82577_CFG_REG 22
71#define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15)
72#define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */
73#define I82577_CTRL_REG 23
74#define I82577_CTRL_DOWNSHIFT_MASK (7 << 10)
75
76/* 82577 specific PHY registers */
77#define I82577_PHY_CTRL_2 18
78#define I82577_PHY_STATUS_2 26
79#define I82577_PHY_DIAG_STATUS 31
80
81/* I82577 PHY Status 2 */
82#define I82577_PHY_STATUS2_REV_POLARITY 0x0400
83#define I82577_PHY_STATUS2_MDIX 0x0800
84#define I82577_PHY_STATUS2_SPEED_MASK 0x0300
85#define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
86
87/* I82577 PHY Control 2 */
88#define I82577_PHY_CTRL2_AUTO_MDIX 0x0400
89#define I82577_PHY_CTRL2_FORCE_MDI_MDIX 0x0200
90
91/* I82577 PHY Diagnostics Status */
92#define I82577_DSTATUS_CABLE_LENGTH 0x03FC
93#define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
94
95/* BM PHY Copper Specific Control 1 */
96#define BM_CS_CTRL1 16
97
98/* BM PHY Copper Specific Status */
99#define BM_CS_STATUS 17
100#define BM_CS_STATUS_LINK_UP 0x0400
101#define BM_CS_STATUS_RESOLVED 0x0800
102#define BM_CS_STATUS_SPEED_MASK 0xC000
103#define BM_CS_STATUS_SPEED_1000 0x8000
104
105#define HV_MUX_DATA_CTRL PHY_REG(776, 16)
106#define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400
107#define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004
108
57/** 109/**
58 * e1000e_check_reset_block_generic - Check if PHY reset is blocked 110 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
59 * @hw: pointer to the HW structure 111 * @hw: pointer to the HW structure
@@ -82,23 +134,48 @@ s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
82s32 e1000e_get_phy_id(struct e1000_hw *hw) 134s32 e1000e_get_phy_id(struct e1000_hw *hw)
83{ 135{
84 struct e1000_phy_info *phy = &hw->phy; 136 struct e1000_phy_info *phy = &hw->phy;
85 s32 ret_val; 137 s32 ret_val = 0;
86 u16 phy_id; 138 u16 phy_id;
139 u16 retry_count = 0;
87 140
88 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id); 141 if (!(phy->ops.read_phy_reg))
89 if (ret_val) 142 goto out;
90 return ret_val;
91 143
92 phy->id = (u32)(phy_id << 16); 144 while (retry_count < 2) {
93 udelay(20); 145 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
94 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id); 146 if (ret_val)
95 if (ret_val) 147 goto out;
96 return ret_val;
97 148
98 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 149 phy->id = (u32)(phy_id << 16);
99 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 150 udelay(20);
151 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
152 if (ret_val)
153 goto out;
100 154
101 return 0; 155 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
156 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
157
158 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
159 goto out;
160
161 /*
162 * If the PHY ID is still unknown, we may have an 82577i
163 * without link. We will try again after setting Slow
164 * MDIC mode. No harm in trying again in this case since
165 * the PHY ID is unknown at this point anyway
166 */
167 ret_val = e1000_set_mdio_slow_mode_hv(hw, true);
168 if (ret_val)
169 goto out;
170
171 retry_count++;
172 }
173out:
174 /* Revert to MDIO fast mode, if applicable */
175 if (retry_count)
176 ret_val = e1000_set_mdio_slow_mode_hv(hw, false);
177
178 return ret_val;
102} 179}
103 180
104/** 181/**
@@ -410,6 +487,43 @@ s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
410} 487}
411 488
412/** 489/**
490 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
491 * @hw: pointer to the HW structure
492 *
493 * Sets up Carrier-sense on Transmit and downshift values.
494 **/
495s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
496{
497 struct e1000_phy_info *phy = &hw->phy;
498 s32 ret_val;
499 u16 phy_data;
500
501 /* Enable CRS on TX. This must be set for half-duplex operation. */
502 ret_val = phy->ops.read_phy_reg(hw, I82577_CFG_REG, &phy_data);
503 if (ret_val)
504 goto out;
505
506 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
507
508 /* Enable downshift */
509 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
510
511 ret_val = phy->ops.write_phy_reg(hw, I82577_CFG_REG, phy_data);
512 if (ret_val)
513 goto out;
514
515 /* Set number of link attempts before downshift */
516 ret_val = phy->ops.read_phy_reg(hw, I82577_CTRL_REG, &phy_data);
517 if (ret_val)
518 goto out;
519 phy_data &= ~I82577_CTRL_DOWNSHIFT_MASK;
520 ret_val = phy->ops.write_phy_reg(hw, I82577_CTRL_REG, phy_data);
521
522out:
523 return ret_val;
524}
525
526/**
413 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link 527 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
414 * @hw: pointer to the HW structure 528 * @hw: pointer to the HW structure
415 * 529 *
@@ -427,8 +541,8 @@ s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
427 if (ret_val) 541 if (ret_val)
428 return ret_val; 542 return ret_val;
429 543
430 /* For newer PHYs this bit is downshift enable */ 544 /* For BM PHY this bit is downshift enable */
431 if (phy->type == e1000_phy_m88) 545 if (phy->type != e1000_phy_bm)
432 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 546 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
433 547
434 /* 548 /*
@@ -520,10 +634,27 @@ s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
520 634
521 /* Commit the changes. */ 635 /* Commit the changes. */
522 ret_val = e1000e_commit_phy(hw); 636 ret_val = e1000e_commit_phy(hw);
523 if (ret_val) 637 if (ret_val) {
524 hw_dbg(hw, "Error committing the PHY changes\n"); 638 hw_dbg(hw, "Error committing the PHY changes\n");
639 return ret_val;
640 }
525 641
526 return ret_val; 642 if (phy->type == e1000_phy_82578) {
643 ret_val = phy->ops.read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
644 &phy_data);
645 if (ret_val)
646 return ret_val;
647
648 /* 82578 PHY - set the downshift count to 1x. */
649 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
650 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
651 ret_val = phy->ops.write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
652 phy_data);
653 if (ret_val)
654 return ret_val;
655 }
656
657 return 0;
527} 658}
528 659
529/** 660/**
@@ -1251,6 +1382,8 @@ s32 e1000e_check_downshift(struct e1000_hw *hw)
1251 switch (phy->type) { 1382 switch (phy->type) {
1252 case e1000_phy_m88: 1383 case e1000_phy_m88:
1253 case e1000_phy_gg82563: 1384 case e1000_phy_gg82563:
1385 case e1000_phy_82578:
1386 case e1000_phy_82577:
1254 offset = M88E1000_PHY_SPEC_STATUS; 1387 offset = M88E1000_PHY_SPEC_STATUS;
1255 mask = M88E1000_PSSR_DOWNSHIFT; 1388 mask = M88E1000_PSSR_DOWNSHIFT;
1256 break; 1389 break;
@@ -1886,6 +2019,12 @@ enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
1886 case BME1000_E_PHY_ID_R2: 2019 case BME1000_E_PHY_ID_R2:
1887 phy_type = e1000_phy_bm; 2020 phy_type = e1000_phy_bm;
1888 break; 2021 break;
2022 case I82578_E_PHY_ID:
2023 phy_type = e1000_phy_82578;
2024 break;
2025 case I82577_E_PHY_ID:
2026 phy_type = e1000_phy_82577;
2027 break;
1889 default: 2028 default:
1890 phy_type = e1000_phy_unknown; 2029 phy_type = e1000_phy_unknown;
1891 break; 2030 break;
@@ -2181,11 +2320,16 @@ static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2181 u16 *data, bool read) 2320 u16 *data, bool read)
2182{ 2321{
2183 s32 ret_val; 2322 s32 ret_val;
2184 u16 reg = ((u16)offset) & PHY_REG_MASK; 2323 u16 reg = BM_PHY_REG_NUM(offset);
2185 u16 phy_reg = 0; 2324 u16 phy_reg = 0;
2186 u8 phy_acquired = 1; 2325 u8 phy_acquired = 1;
2187 2326
2188 2327
2328 /* Gig must be disabled for MDIO accesses to page 800 */
2329 if ((hw->mac.type == e1000_pchlan) &&
2330 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
2331 hw_dbg(hw, "Attempting to access page 800 while gig enabled\n");
2332
2189 ret_val = hw->phy.ops.acquire_phy(hw); 2333 ret_val = hw->phy.ops.acquire_phy(hw);
2190 if (ret_val) { 2334 if (ret_val) {
2191 phy_acquired = 0; 2335 phy_acquired = 0;
@@ -2289,3 +2433,524 @@ static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
2289 2433
2290 return 0; 2434 return 0;
2291} 2435}
2436
2437s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw, bool slow)
2438{
2439 s32 ret_val = 0;
2440 u16 data = 0;
2441
2442 ret_val = hw->phy.ops.acquire_phy(hw);
2443 if (ret_val)
2444 return ret_val;
2445
2446 /* Set MDIO mode - page 769, register 16: 0x2580==slow, 0x2180==fast */
2447 hw->phy.addr = 1;
2448 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
2449 (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2450 if (ret_val) {
2451 hw->phy.ops.release_phy(hw);
2452 return ret_val;
2453 }
2454 ret_val = e1000e_write_phy_reg_mdic(hw, BM_CS_CTRL1,
2455 (0x2180 | (slow << 10)));
2456
2457 /* dummy read when reverting to fast mode - throw away result */
2458 if (!slow)
2459 e1000e_read_phy_reg_mdic(hw, BM_CS_CTRL1, &data);
2460
2461 hw->phy.ops.release_phy(hw);
2462
2463 return ret_val;
2464}
2465
2466/**
2467 * e1000_read_phy_reg_hv - Read HV PHY register
2468 * @hw: pointer to the HW structure
2469 * @offset: register offset to be read
2470 * @data: pointer to the read data
2471 *
2472 * Acquires semaphore, if necessary, then reads the PHY register at offset
2473 * and storing the retrieved information in data. Release any acquired
2474 * semaphore before exiting.
2475 **/
2476s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2477{
2478 s32 ret_val;
2479 u16 page = BM_PHY_REG_PAGE(offset);
2480 u16 reg = BM_PHY_REG_NUM(offset);
2481 bool in_slow_mode = false;
2482
2483 /* Workaround failure in MDIO access while cable is disconnected */
2484 if ((hw->phy.type == e1000_phy_82577) &&
2485 !(er32(STATUS) & E1000_STATUS_LU)) {
2486 ret_val = e1000_set_mdio_slow_mode_hv(hw, true);
2487 if (ret_val)
2488 goto out;
2489
2490 in_slow_mode = true;
2491 }
2492
2493 /* Page 800 works differently than the rest so it has its own func */
2494 if (page == BM_WUC_PAGE) {
2495 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset,
2496 data, true);
2497 goto out;
2498 }
2499
2500 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2501 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2502 data, true);
2503 goto out;
2504 }
2505
2506 ret_val = hw->phy.ops.acquire_phy(hw);
2507 if (ret_val)
2508 goto out;
2509
2510 hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2511
2512 if (page == HV_INTC_FC_PAGE_START)
2513 page = 0;
2514
2515 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2516 if ((hw->phy.type != e1000_phy_82578) ||
2517 ((reg != I82578_ADDR_REG) &&
2518 (reg != I82578_ADDR_REG + 1))) {
2519 u32 phy_addr = hw->phy.addr;
2520
2521 hw->phy.addr = 1;
2522
2523 /* Page is shifted left, PHY expects (page x 32) */
2524 ret_val = e1000e_write_phy_reg_mdic(hw,
2525 IGP01E1000_PHY_PAGE_SELECT,
2526 (page << IGP_PAGE_SHIFT));
2527 if (ret_val) {
2528 hw->phy.ops.release_phy(hw);
2529 goto out;
2530 }
2531 hw->phy.addr = phy_addr;
2532 }
2533 }
2534
2535 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2536 data);
2537 hw->phy.ops.release_phy(hw);
2538
2539out:
2540 /* Revert to MDIO fast mode, if applicable */
2541 if ((hw->phy.type == e1000_phy_82577) && in_slow_mode)
2542 ret_val = e1000_set_mdio_slow_mode_hv(hw, false);
2543
2544 return ret_val;
2545}
2546
2547/**
2548 * e1000_write_phy_reg_hv - Write HV PHY register
2549 * @hw: pointer to the HW structure
2550 * @offset: register offset to write to
2551 * @data: data to write at register offset
2552 *
2553 * Acquires semaphore, if necessary, then writes the data to PHY register
2554 * at the offset. Release any acquired semaphores before exiting.
2555 **/
2556s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
2557{
2558 s32 ret_val;
2559 u16 page = BM_PHY_REG_PAGE(offset);
2560 u16 reg = BM_PHY_REG_NUM(offset);
2561 bool in_slow_mode = false;
2562
2563 /* Workaround failure in MDIO access while cable is disconnected */
2564 if ((hw->phy.type == e1000_phy_82577) &&
2565 !(er32(STATUS) & E1000_STATUS_LU)) {
2566 ret_val = e1000_set_mdio_slow_mode_hv(hw, true);
2567 if (ret_val)
2568 goto out;
2569
2570 in_slow_mode = true;
2571 }
2572
2573 /* Page 800 works differently than the rest so it has its own func */
2574 if (page == BM_WUC_PAGE) {
2575 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset,
2576 &data, false);
2577 goto out;
2578 }
2579
2580 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2581 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2582 &data, false);
2583 goto out;
2584 }
2585
2586 ret_val = hw->phy.ops.acquire_phy(hw);
2587 if (ret_val)
2588 goto out;
2589
2590 hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2591
2592 if (page == HV_INTC_FC_PAGE_START)
2593 page = 0;
2594
2595 /*
2596 * Workaround MDIO accesses being disabled after entering IEEE Power
2597 * Down (whenever bit 11 of the PHY Control register is set)
2598 */
2599 if ((hw->phy.type == e1000_phy_82578) &&
2600 (hw->phy.revision >= 1) &&
2601 (hw->phy.addr == 2) &&
2602 ((MAX_PHY_REG_ADDRESS & reg) == 0) &&
2603 (data & (1 << 11))) {
2604 u16 data2 = 0x7EFF;
2605 hw->phy.ops.release_phy(hw);
2606 ret_val = e1000_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3,
2607 &data2, false);
2608 if (ret_val)
2609 goto out;
2610
2611 ret_val = hw->phy.ops.acquire_phy(hw);
2612 if (ret_val)
2613 goto out;
2614 }
2615
2616 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2617 if ((hw->phy.type != e1000_phy_82578) ||
2618 ((reg != I82578_ADDR_REG) &&
2619 (reg != I82578_ADDR_REG + 1))) {
2620 u32 phy_addr = hw->phy.addr;
2621
2622 hw->phy.addr = 1;
2623
2624 /* Page is shifted left, PHY expects (page x 32) */
2625 ret_val = e1000e_write_phy_reg_mdic(hw,
2626 IGP01E1000_PHY_PAGE_SELECT,
2627 (page << IGP_PAGE_SHIFT));
2628 if (ret_val) {
2629 hw->phy.ops.release_phy(hw);
2630 goto out;
2631 }
2632 hw->phy.addr = phy_addr;
2633 }
2634 }
2635
2636 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2637 data);
2638 hw->phy.ops.release_phy(hw);
2639
2640out:
2641 /* Revert to MDIO fast mode, if applicable */
2642 if ((hw->phy.type == e1000_phy_82577) && in_slow_mode)
2643 ret_val = e1000_set_mdio_slow_mode_hv(hw, false);
2644
2645 return ret_val;
2646}
2647
2648/**
2649 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
2650 * @page: page to be accessed
2651 **/
2652static u32 e1000_get_phy_addr_for_hv_page(u32 page)
2653{
2654 u32 phy_addr = 2;
2655
2656 if (page >= HV_INTC_FC_PAGE_START)
2657 phy_addr = 1;
2658
2659 return phy_addr;
2660}
2661
2662/**
2663 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
2664 * @hw: pointer to the HW structure
2665 * @offset: register offset to be read or written
2666 * @data: pointer to the data to be read or written
2667 * @read: determines if operation is read or written
2668 *
2669 * Acquires semaphore, if necessary, then reads the PHY register at offset
2670 * and storing the retreived information in data. Release any acquired
2671 * semaphores before exiting. Note that the procedure to read these regs
2672 * uses the address port and data port to read/write.
2673 **/
2674static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
2675 u16 *data, bool read)
2676{
2677 s32 ret_val;
2678 u32 addr_reg = 0;
2679 u32 data_reg = 0;
2680 u8 phy_acquired = 1;
2681
2682 /* This takes care of the difference with desktop vs mobile phy */
2683 addr_reg = (hw->phy.type == e1000_phy_82578) ?
2684 I82578_ADDR_REG : I82577_ADDR_REG;
2685 data_reg = addr_reg + 1;
2686
2687 ret_val = hw->phy.ops.acquire_phy(hw);
2688 if (ret_val) {
2689 hw_dbg(hw, "Could not acquire PHY\n");
2690 phy_acquired = 0;
2691 goto out;
2692 }
2693
2694 /* All operations in this function are phy address 2 */
2695 hw->phy.addr = 2;
2696
2697 /* masking with 0x3F to remove the page from offset */
2698 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
2699 if (ret_val) {
2700 hw_dbg(hw, "Could not write PHY the HV address register\n");
2701 goto out;
2702 }
2703
2704 /* Read or write the data value next */
2705 if (read)
2706 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data);
2707 else
2708 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data);
2709
2710 if (ret_val) {
2711 hw_dbg(hw, "Could not read data value from HV data register\n");
2712 goto out;
2713 }
2714
2715out:
2716 if (phy_acquired == 1)
2717 hw->phy.ops.release_phy(hw);
2718 return ret_val;
2719}
2720
2721/**
2722 * e1000_link_stall_workaround_hv - Si workaround
2723 * @hw: pointer to the HW structure
2724 *
2725 * This function works around a Si bug where the link partner can get
2726 * a link up indication before the PHY does. If small packets are sent
2727 * by the link partner they can be placed in the packet buffer without
2728 * being properly accounted for by the PHY and will stall preventing
2729 * further packets from being received. The workaround is to clear the
2730 * packet buffer after the PHY detects link up.
2731 **/
2732s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
2733{
2734 s32 ret_val = 0;
2735 u16 data;
2736
2737 if (hw->phy.type != e1000_phy_82578)
2738 goto out;
2739
2740 /* check if link is up and at 1Gbps */
2741 ret_val = hw->phy.ops.read_phy_reg(hw, BM_CS_STATUS, &data);
2742 if (ret_val)
2743 goto out;
2744
2745 data &= BM_CS_STATUS_LINK_UP |
2746 BM_CS_STATUS_RESOLVED |
2747 BM_CS_STATUS_SPEED_MASK;
2748
2749 if (data != (BM_CS_STATUS_LINK_UP |
2750 BM_CS_STATUS_RESOLVED |
2751 BM_CS_STATUS_SPEED_1000))
2752 goto out;
2753
2754 mdelay(200);
2755
2756 /* flush the packets in the fifo buffer */
2757 ret_val = hw->phy.ops.write_phy_reg(hw, HV_MUX_DATA_CTRL,
2758 HV_MUX_DATA_CTRL_GEN_TO_MAC |
2759 HV_MUX_DATA_CTRL_FORCE_SPEED);
2760 if (ret_val)
2761 goto out;
2762
2763 ret_val = hw->phy.ops.write_phy_reg(hw, HV_MUX_DATA_CTRL,
2764 HV_MUX_DATA_CTRL_GEN_TO_MAC);
2765
2766out:
2767 return ret_val;
2768}
2769
2770/**
2771 * e1000_check_polarity_82577 - Checks the polarity.
2772 * @hw: pointer to the HW structure
2773 *
2774 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2775 *
2776 * Polarity is determined based on the PHY specific status register.
2777 **/
2778s32 e1000_check_polarity_82577(struct e1000_hw *hw)
2779{
2780 struct e1000_phy_info *phy = &hw->phy;
2781 s32 ret_val;
2782 u16 data;
2783
2784 ret_val = phy->ops.read_phy_reg(hw, I82577_PHY_STATUS_2, &data);
2785
2786 if (!ret_val)
2787 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
2788 ? e1000_rev_polarity_reversed
2789 : e1000_rev_polarity_normal;
2790
2791 return ret_val;
2792}
2793
2794/**
2795 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
2796 * @hw: pointer to the HW structure
2797 *
2798 * Calls the PHY setup function to force speed and duplex. Clears the
2799 * auto-crossover to force MDI manually. Waits for link and returns
2800 * successful if link up is successful, else -E1000_ERR_PHY (-2).
2801 **/
2802s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
2803{
2804 struct e1000_phy_info *phy = &hw->phy;
2805 s32 ret_val;
2806 u16 phy_data;
2807 bool link;
2808
2809 ret_val = phy->ops.read_phy_reg(hw, PHY_CONTROL, &phy_data);
2810 if (ret_val)
2811 goto out;
2812
2813 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
2814
2815 ret_val = phy->ops.write_phy_reg(hw, PHY_CONTROL, phy_data);
2816 if (ret_val)
2817 goto out;
2818
2819 /*
2820 * Clear Auto-Crossover to force MDI manually. 82577 requires MDI
2821 * forced whenever speed and duplex are forced.
2822 */
2823 ret_val = phy->ops.read_phy_reg(hw, I82577_PHY_CTRL_2, &phy_data);
2824 if (ret_val)
2825 goto out;
2826
2827 phy_data &= ~I82577_PHY_CTRL2_AUTO_MDIX;
2828 phy_data &= ~I82577_PHY_CTRL2_FORCE_MDI_MDIX;
2829
2830 ret_val = phy->ops.write_phy_reg(hw, I82577_PHY_CTRL_2, phy_data);
2831 if (ret_val)
2832 goto out;
2833
2834 hw_dbg(hw, "I82577_PHY_CTRL_2: %X\n", phy_data);
2835
2836 udelay(1);
2837
2838 if (phy->autoneg_wait_to_complete) {
2839 hw_dbg(hw, "Waiting for forced speed/duplex link on 82577 phy\n");
2840
2841 ret_val = e1000e_phy_has_link_generic(hw,
2842 PHY_FORCE_LIMIT,
2843 100000,
2844 &link);
2845 if (ret_val)
2846 goto out;
2847
2848 if (!link)
2849 hw_dbg(hw, "Link taking longer than expected.\n");
2850
2851 /* Try once more */
2852 ret_val = e1000e_phy_has_link_generic(hw,
2853 PHY_FORCE_LIMIT,
2854 100000,
2855 &link);
2856 if (ret_val)
2857 goto out;
2858 }
2859
2860out:
2861 return ret_val;
2862}
2863
2864/**
2865 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
2866 * @hw: pointer to the HW structure
2867 *
2868 * Read PHY status to determine if link is up. If link is up, then
2869 * set/determine 10base-T extended distance and polarity correction. Read
2870 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2871 * determine on the cable length, local and remote receiver.
2872 **/
2873s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
2874{
2875 struct e1000_phy_info *phy = &hw->phy;
2876 s32 ret_val;
2877 u16 data;
2878 bool link;
2879
2880 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2881 if (ret_val)
2882 goto out;
2883
2884 if (!link) {
2885 hw_dbg(hw, "Phy info is only valid if link is up\n");
2886 ret_val = -E1000_ERR_CONFIG;
2887 goto out;
2888 }
2889
2890 phy->polarity_correction = true;
2891
2892 ret_val = e1000_check_polarity_82577(hw);
2893 if (ret_val)
2894 goto out;
2895
2896 ret_val = phy->ops.read_phy_reg(hw, I82577_PHY_STATUS_2, &data);
2897 if (ret_val)
2898 goto out;
2899
2900 phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? true : false;
2901
2902 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
2903 I82577_PHY_STATUS2_SPEED_1000MBPS) {
2904 ret_val = hw->phy.ops.get_cable_length(hw);
2905 if (ret_val)
2906 goto out;
2907
2908 ret_val = phy->ops.read_phy_reg(hw, PHY_1000T_STATUS, &data);
2909 if (ret_val)
2910 goto out;
2911
2912 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2913 ? e1000_1000t_rx_status_ok
2914 : e1000_1000t_rx_status_not_ok;
2915
2916 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2917 ? e1000_1000t_rx_status_ok
2918 : e1000_1000t_rx_status_not_ok;
2919 } else {
2920 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2921 phy->local_rx = e1000_1000t_rx_status_undefined;
2922 phy->remote_rx = e1000_1000t_rx_status_undefined;
2923 }
2924
2925out:
2926 return ret_val;
2927}
2928
2929/**
2930 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
2931 * @hw: pointer to the HW structure
2932 *
2933 * Reads the diagnostic status register and verifies result is valid before
2934 * placing it in the phy_cable_length field.
2935 **/
2936s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
2937{
2938 struct e1000_phy_info *phy = &hw->phy;
2939 s32 ret_val;
2940 u16 phy_data, length;
2941
2942 ret_val = phy->ops.read_phy_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
2943 if (ret_val)
2944 goto out;
2945
2946 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
2947 I82577_DSTATUS_CABLE_LENGTH_SHIFT;
2948
2949 if (length == E1000_CABLE_LENGTH_UNDEFINED)
2950 ret_val = E1000_ERR_PHY;
2951
2952 phy->cable_length = length;
2953
2954out:
2955 return ret_val;
2956}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 09:44:04 -0500