diff options
| author | Kumar Gala <galak@kernel.crashing.org> | 2009-03-17 11:17:50 -0400 |
|---|---|---|
| committer | Grant Likely <grant.likely@secretlab.ca> | 2009-03-17 11:17:50 -0400 |
| commit | a4bd6a93c3f14691c8a29e53eb04dc734b27f0db (patch) | |
| tree | ef9492ba17bc86925bebf91282f286822efcfed2 | |
| parent | c9310920e6e7ae0a5c0accbd57d34c194cb31780 (diff) | |
powerpc/mm: Respect _PAGE_COHERENT on classic ppc32 SW
Since we now set _PAGE_COHERENT in the Linux PTE we shouldn't be clearing
it out before we setup the SW TLB. Today all the SW TLB machines
(603/e300) that we support are non-SMP, however there are some errata on
some devices that cause us to set _PAGE_COHERENT via CPU_FTR_NEED_COHERENT.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| -rw-r--r-- | arch/powerpc/kernel/head_32.S | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S index a1c4cfd25ded..7db2e42d97a2 100644 --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S | |||
| @@ -511,7 +511,7 @@ InstructionTLBMiss: | |||
| 511 | and r1,r1,r2 /* writable if _RW and _DIRTY */ | 511 | and r1,r1,r2 /* writable if _RW and _DIRTY */ |
| 512 | rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */ | 512 | rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */ |
| 513 | rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */ | 513 | rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */ |
| 514 | ori r1,r1,0xe14 /* clear out reserved bits and M */ | 514 | ori r1,r1,0xe04 /* clear out reserved bits */ |
| 515 | andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */ | 515 | andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */ |
| 516 | mtspr SPRN_RPA,r1 | 516 | mtspr SPRN_RPA,r1 |
| 517 | mfspr r3,SPRN_IMISS | 517 | mfspr r3,SPRN_IMISS |
| @@ -585,7 +585,7 @@ DataLoadTLBMiss: | |||
| 585 | and r1,r1,r2 /* writable if _RW and _DIRTY */ | 585 | and r1,r1,r2 /* writable if _RW and _DIRTY */ |
| 586 | rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */ | 586 | rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */ |
| 587 | rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */ | 587 | rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */ |
| 588 | ori r1,r1,0xe14 /* clear out reserved bits and M */ | 588 | ori r1,r1,0xe04 /* clear out reserved bits */ |
| 589 | andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */ | 589 | andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */ |
| 590 | mtspr SPRN_RPA,r1 | 590 | mtspr SPRN_RPA,r1 |
| 591 | mfspr r3,SPRN_DMISS | 591 | mfspr r3,SPRN_DMISS |
| @@ -653,7 +653,7 @@ DataStoreTLBMiss: | |||
| 653 | stw r3,0(r2) /* update PTE (accessed/dirty bits) */ | 653 | stw r3,0(r2) /* update PTE (accessed/dirty bits) */ |
| 654 | /* Convert linux-style PTE to low word of PPC-style PTE */ | 654 | /* Convert linux-style PTE to low word of PPC-style PTE */ |
| 655 | rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */ | 655 | rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */ |
| 656 | li r1,0xe15 /* clear out reserved bits and M */ | 656 | li r1,0xe05 /* clear out reserved bits & PP lsb */ |
| 657 | andc r1,r3,r1 /* PP = user? 2: 0 */ | 657 | andc r1,r3,r1 /* PP = user? 2: 0 */ |
| 658 | mtspr SPRN_RPA,r1 | 658 | mtspr SPRN_RPA,r1 |
| 659 | mfspr r3,SPRN_DMISS | 659 | mfspr r3,SPRN_DMISS |