[ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach

This just leaves include/asm-arm/plat-* to deal with.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

2230 files changed, 52669 insertions, 52688 deletions

diff --git a/Documentation/arm/IXP4xx b/Documentation/arm/IXP4xx
index 43edb4ecf27d..72fbcc4fcab0 100644
--- a/Documentation/arm/IXP4xx
+++ b/Documentation/arm/IXP4xx
@@ -32,7 +32,7 @@ Linux currently supports the following features on the IXP4xx chips:
 - Flash access (MTD/JFFS)
 - I2C through GPIO on IXP42x
 - GPIO for input/output/interrupts 
-  See include/asm-arm/arch-ixp4xx/platform.h for access functions.
+  See arch/arm/mach-ixp4xx/include/mach/platform.h for access functions.
 - Timers (watchdog, OS)
 
 The following components of the chips are not supported by Linux and
diff --git a/Documentation/arm/Interrupts b/Documentation/arm/Interrupts
index c202ed35d7d6..f09ab1b90ef1 100644
--- a/Documentation/arm/Interrupts
+++ b/Documentation/arm/Interrupts
@@ -158,7 +158,7 @@ So, what's changed?
    be re-checked for pending events.  (see the Neponset IRQ handler for
    details).
 
-7. fixup_irq() is gone, as is include/asm-arm/arch-*/irq.h
+7. fixup_irq() is gone, as is arch/arm/mach-*/include/mach/irq.h
 
 Please note that this will not solve all problems - some of them are
 hardware based.  Mixing level-based and edge-based IRQs on the same
diff --git a/Documentation/arm/README b/Documentation/arm/README
index 9b9c8226fdc4..d98783fbe0c7 100644
--- a/Documentation/arm/README
+++ b/Documentation/arm/README
@@ -79,7 +79,7 @@ Machine/Platform support
   To this end, we now have arch/arm/mach-$(MACHINE) directories which are
   designed to house the non-driver files for a particular machine (eg, PCI,
   memory management, architecture definitions etc).  For all future
-  machines, there should be a corresponding include/asm-arm/arch-$(MACHINE)
+  machines, there should be a corresponding arch/arm/mach-$(MACHINE)/include/mach
   directory.
 
 
@@ -176,7 +176,7 @@ Kernel entry (head.S)
   class typically based around one or more system on a chip devices, and
   acts as a natural container around the actual implementations.  These
   classes are given directories - arch/arm/mach-<class> and
-  include/asm-arm/arch-<class> - which contain the source files to
+  arch/arm/mach-<class> - which contain the source files to/include/mach
   support the machine class.  This directories also contain any machine
   specific supporting code.
 
diff --git a/Documentation/arm/Samsung-S3C24XX/GPIO.txt b/Documentation/arm/Samsung-S3C24XX/GPIO.txt
index 8caea8c237ee..b5d20c0b2ab4 100644
--- a/Documentation/arm/Samsung-S3C24XX/GPIO.txt
+++ b/Documentation/arm/Samsung-S3C24XX/GPIO.txt
@@ -16,13 +16,13 @@ Introduction
 Headers
 -------
 
-  See include/asm-arm/arch-s3c2410/regs-gpio.h for the list
+  See arch/arm/mach-s3c2410/include/mach/regs-gpio.h for the list
   of GPIO pins, and the configuration values for them. This
-  is included by using #include <asm/arch/regs-gpio.h>
+  is included by using #include <mach/regs-gpio.h>
 
   The GPIO management functions are defined in the hardware
-  header include/asm-arm/arch-s3c2410/hardware.h which can be
-  included by #include <asm/arch/hardware.h>
+  header arch/arm/mach-s3c2410/include/mach/hardware.h which can be
+  included by #include <mach/hardware.h>
 
   A useful amount of documentation can be found in the hardware
   header on how the GPIO functions (and others) work.
diff --git a/Documentation/arm/Samsung-S3C24XX/Overview.txt b/Documentation/arm/Samsung-S3C24XX/Overview.txt
index d04e1e30c47f..014a8ec4877d 100644
--- a/Documentation/arm/Samsung-S3C24XX/Overview.txt
+++ b/Documentation/arm/Samsung-S3C24XX/Overview.txt
@@ -36,7 +36,7 @@ Layout
   in arch/arm/mach-s3c2410 and S3C2440 in arch/arm/mach-s3c2440
 
   Register, kernel and platform data definitions are held in the
-  include/asm-arm/arch-s3c2410 directory.
+  arch/arm/mach-s3c2410 directory./include/mach
 
 
 Machines
diff --git a/Documentation/arm/Samsung-S3C24XX/USB-Host.txt b/Documentation/arm/Samsung-S3C24XX/USB-Host.txt
index b93b68e2b143..67671eba4231 100644
--- a/Documentation/arm/Samsung-S3C24XX/USB-Host.txt
+++ b/Documentation/arm/Samsung-S3C24XX/USB-Host.txt
@@ -49,7 +49,7 @@ Board Support
 Platform Data
 -------------
 
-  See linux/include/asm-arm/arch-s3c2410/usb-control.h for the
+  See arch/arm/mach-s3c2410/include/mach/usb-control.h for the
   descriptions of the platform device data. An implementation
   can be found in linux/arch/arm/mach-s3c2410/usb-simtec.c .
 
diff --git a/Documentation/spi/pxa2xx b/Documentation/spi/pxa2xx
index f3853cc37bde..bbe8dee681a5 100644
--- a/Documentation/spi/pxa2xx
+++ b/Documentation/spi/pxa2xx
@@ -19,7 +19,7 @@ Declaring PXA2xx Master Controllers
 -----------------------------------
 Typically a SPI master is defined in the arch/.../mach-*/board-*.c as a
 "platform device".  The master configuration is passed to the driver via a table
-found in include/asm-arm/arch-pxa/pxa2xx_spi.h:
+found in arch/arm/mach-pxa/include/mach/pxa2xx_spi.h:
 
 struct pxa2xx_spi_master {
         enum pxa_ssp_type ssp_type;
@@ -94,7 +94,7 @@ using the "spi_board_info" structure found in "linux/spi/spi.h". See
 
 Each slave device attached to the PXA must provide slave specific configuration
 information via the structure "pxa2xx_spi_chip" found in
-"include/asm-arm/arch-pxa/pxa2xx_spi.h".  The pxa2xx_spi master controller driver
+"arch/arm/mach-pxa/include/mach/pxa2xx_spi.h".  The pxa2xx_spi master controller driver
 will uses the configuration whenever the driver communicates with the slave
 device.
 
diff --git a/Documentation/spi/spi-summary b/Documentation/spi/spi-summary
index 6d5f18143c50..8bae2f018d34 100644
--- a/Documentation/spi/spi-summary
+++ b/Documentation/spi/spi-summary
@@ -210,7 +210,7 @@ board should normally be set up and registered.
 
 So for example arch/.../mach-*/board-*.c files might have code like:
 
-        #include <asm/arch/spi.h>       /* for mysoc_spi_data */
+        #include <mach/spi.h>   /* for mysoc_spi_data */
 
         /* if your mach-* infrastructure doesn't support kernels that can
          * run on multiple boards, pdata wouldn't benefit from "__init".
@@ -227,7 +227,7 @@ So for example arch/.../mach-*/board-*.c files might have code like:
 
 And SOC-specific utility code might look something like:
 
-        #include <asm/arch/spi.h>
+        #include <mach/spi.h>
 
         static struct platform_device spi2 = { ... };
 
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 359d224c8c3e..703a44fa0f9b 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -97,9 +97,7 @@ textofs-y	:= 0x00008000
  machine-$(CONFIG_ARCH_RPC)        := rpc
  machine-$(CONFIG_ARCH_EBSA110)    := ebsa110
  machine-$(CONFIG_ARCH_CLPS7500)   := clps7500
-  incdir-$(CONFIG_ARCH_CLPS7500)   := cl7500
  machine-$(CONFIG_FOOTBRIDGE)      := footbridge
-  incdir-$(CONFIG_FOOTBRIDGE)      := ebsa285
  machine-$(CONFIG_ARCH_SHARK)      := shark
  machine-$(CONFIG_ARCH_SA1100)     := sa1100
 ifeq ($(CONFIG_ARCH_SA1100),y)
@@ -120,7 +118,6 @@ endif
  machine-$(CONFIG_ARCH_IXP23XX)    := ixp23xx
  machine-$(CONFIG_ARCH_OMAP1)      := omap1
  machine-$(CONFIG_ARCH_OMAP2)      := omap2
-  incdir-$(CONFIG_ARCH_OMAP)       := omap
     plat-$(CONFIG_ARCH_OMAP)       := omap
  machine-$(CONFIG_ARCH_S3C2410)    := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443
     plat-$(CONFIG_PLAT_S3C24XX)    := s3c24xx
@@ -138,7 +135,6 @@ endif
  machine-$(CONFIG_ARCH_DAVINCI)    := davinci
  machine-$(CONFIG_ARCH_KIRKWOOD)   := kirkwood
  machine-$(CONFIG_ARCH_KS8695)     := ks8695
-  incdir-$(CONFIG_ARCH_MXC)        := mxc
     plat-$(CONFIG_ARCH_MXC)        := mxc
  machine-$(CONFIG_ARCH_MX2)        := mx2
  machine-$(CONFIG_ARCH_MX3)        := mx3
@@ -158,11 +154,6 @@ endif
 # The byte offset of the kernel image in RAM from the start of RAM.
 TEXT_OFFSET := $(textofs-y)
 
-ifeq ($(incdir-y),)
-incdir-y := $(word 1,$(machine-y))
-endif
-INCDIR   := arch-$(incdir-y)
-
 # The first directory contains additional information for the boot setup code
 ifneq ($(machine-y),)
 MACHINE  := arch/arm/mach-$(word 1,$(machine-y))/
@@ -213,20 +204,10 @@ boot := arch/arm/boot
 #       them changed.  We use .arch to indicate when they were updated
 #       last, otherwise make uses the target directory mtime.
 
-include/asm-arm/.arch: $(wildcard include/config/arch/*.h) include/config/auto.conf
-        @echo '  SYMLINK include/asm-arm/arch -> include/asm-arm/$(INCDIR)'
-ifneq ($(KBUILD_SRC),)
-        $(Q)mkdir -p include/asm-arm
-        $(Q)ln -fsn $(srctree)/include/asm-arm/$(INCDIR) include/asm-arm/arch
-else
-        $(Q)ln -fsn $(INCDIR) include/asm-arm/arch
-endif
-        @touch $@
-
 archprepare: maketools
 
 PHONY += maketools FORCE
-maketools: include/linux/version.h include/asm-arm/.arch FORCE
+maketools: include/linux/version.h FORCE
         $(Q)$(MAKE) $(build)=arch/arm/tools include/asm-arm/mach-types.h
 
 # Convert bzImage to zImage
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index de41daeab5e9..d42f89b7760b 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -37,7 +37,7 @@
 
 #else
 
-#include <asm/arch/debug-macro.S>
+#include <mach/debug-macro.S>
 
                 .macro  writeb, ch, rb
                 senduart \ch, \rb
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index 7145cc7c04f0..65ce8fff29db 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -27,7 +27,7 @@ unsigned int __machine_arch_type;
 static void putstr(const char *ptr);
 
 #include <linux/compiler.h>
-#include <asm/arch/uncompress.h>
+#include <mach/uncompress.h>
 
 #ifdef CONFIG_DEBUG_ICEDCC
 
diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c
index 1f0f0adeafb3..283051eaf931 100644
--- a/arch/arm/common/locomo.c
+++ b/arch/arm/common/locomo.c
@@ -25,7 +25,7 @@
 #include <linux/slab.h>
 #include <linux/spinlock.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c
index 64c328d1627f..ec8a5471bf06 100644
--- a/arch/arm/common/sa1111.c
+++ b/arch/arm/common/sa1111.c
@@ -26,7 +26,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/clk.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/io.h>
 #include <asm/irq.h>
diff --git a/arch/arm/common/sharpsl_pm.c b/arch/arm/common/sharpsl_pm.c
index a0d154006889..db8309161408 100644
--- a/arch/arm/common/sharpsl_pm.c
+++ b/arch/arm/common/sharpsl_pm.c
@@ -26,12 +26,12 @@
 #include <linux/apm-emulation.h>
 #include <linux/suspend.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/arch/pm.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-regs.h>
-#include <asm/arch/sharpsl.h>
+#include <mach/pm.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-regs.h>
+#include <mach/sharpsl.h>
 #include <asm/hardware/sharpsl_pm.h>
 
 /*
diff --git a/arch/arm/common/time-acorn.c b/arch/arm/common/time-acorn.c
index af37bfd74f9c..df0983aafe69 100644
--- a/arch/arm/common/time-acorn.c
+++ b/arch/arm/common/time-acorn.c
@@ -18,7 +18,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/hardware/ioc.h>
 
diff --git a/arch/arm/common/uengine.c b/arch/arm/common/uengine.c
index 3e19985ddecb..7ecd3c0ab011 100644
--- a/arch/arm/common/uengine.c
+++ b/arch/arm/common/uengine.c
@@ -16,7 +16,7 @@
 #include <linux/slab.h>
 #include <linux/module.h>
 #include <linux/string.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/hardware/uengine.h>
 #include <asm/io.h>
 
diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h
index 9f2c5305c260..75154b193117 100644
--- a/arch/arm/include/asm/dma.h
+++ b/arch/arm/include/asm/dma.h
@@ -6,7 +6,7 @@ typedef unsigned int dmach_t;
 #include <linux/spinlock.h>
 #include <asm/system.h>
 #include <asm/scatterlist.h>
-#include <asm/arch/dma.h>
+#include <mach/dma.h>
 
 /*
  * This is the maximum virtual address which can be DMA'd from.
diff --git a/arch/arm/include/asm/floppy.h b/arch/arm/include/asm/floppy.h
index dce20c25ab10..c9f03eccc9d8 100644
--- a/arch/arm/include/asm/floppy.h
+++ b/arch/arm/include/asm/floppy.h
@@ -12,7 +12,7 @@
 #ifndef __ASM_ARM_FLOPPY_H
 #define __ASM_ARM_FLOPPY_H
 #if 0
-#include <asm/arch/floppy.h>
+#include <mach/floppy.h>
 #endif
 
 #define fd_outb(val,port)                       \
diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h
index fff4f800ee42..166a7a3e2840 100644
--- a/arch/arm/include/asm/gpio.h
+++ b/arch/arm/include/asm/gpio.h
@@ -2,6 +2,6 @@
 #define _ARCH_ARM_GPIO_H
 
 /* not all ARM platforms necessarily support this API ... */
-#include <asm/arch/gpio.h>
+#include <mach/gpio.h>
 
 #endif /* _ARCH_ARM_GPIO_H */
diff --git a/arch/arm/include/asm/hardware/dec21285.h b/arch/arm/include/asm/hardware/dec21285.h
index cf2578ffd54d..0d7552751aaf 100644
--- a/arch/arm/include/asm/hardware/dec21285.h
+++ b/arch/arm/include/asm/hardware/dec21285.h
@@ -19,7 +19,7 @@
 #define DC21285_PCI_MEM                 0x80000000
 
 #ifndef __ASSEMBLY__
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #define DC21285_IO(x)           ((volatile unsigned long *)(ARMCSR_BASE+(x)))
 #else
 #define DC21285_IO(x)           (x)
diff --git a/arch/arm/include/asm/hardware/iop3xx-adma.h b/arch/arm/include/asm/hardware/iop3xx-adma.h
index df31b15cf6e0..87bff09633aa 100644
--- a/arch/arm/include/asm/hardware/iop3xx-adma.h
+++ b/arch/arm/include/asm/hardware/iop3xx-adma.h
@@ -19,7 +19,7 @@
 #define _ADMA_H
 #include <linux/types.h>
 #include <linux/io.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/hardware/iop_adma.h>
 
 /* Memory copy units */
diff --git a/arch/arm/include/asm/hardware/iop3xx-gpio.h b/arch/arm/include/asm/hardware/iop3xx-gpio.h
index 0ebc91cb42f9..b69d972b1f7d 100644
--- a/arch/arm/include/asm/hardware/iop3xx-gpio.h
+++ b/arch/arm/include/asm/hardware/iop3xx-gpio.h
@@ -25,7 +25,7 @@
 #ifndef __ASM_ARM_HARDWARE_IOP3XX_GPIO_H
 #define __ASM_ARM_HARDWARE_IOP3XX_GPIO_H
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm-generic/gpio.h>
 
 #define IOP3XX_N_GPIOS  8
diff --git a/arch/arm/include/asm/hardware/sa1111.h b/arch/arm/include/asm/hardware/sa1111.h
index 6cf98d4f7dc3..5da2595759e5 100644
--- a/arch/arm/include/asm/hardware/sa1111.h
+++ b/arch/arm/include/asm/hardware/sa1111.h
@@ -12,7 +12,7 @@
 #ifndef _ASM_ARCH_SA1111
 #define _ASM_ARCH_SA1111
 
-#include <asm/arch/bitfield.h>
+#include <mach/bitfield.h>
 
 /*
  * The SA1111 is always located at virtual 0xf4000000, and is always
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index ffe07c0f46d8..94a95d7fafd6 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -82,7 +82,7 @@ extern void __readwrite_bug(const char *fn);
 /*
  * Now, pick up the machine-defined IO definitions
  */
-#include <asm/arch/io.h>
+#include <mach/io.h>
 
 /*
  *  IO port access primitives
diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h
index 9cb01907e43b..d6786090d02c 100644
--- a/arch/arm/include/asm/irq.h
+++ b/arch/arm/include/asm/irq.h
@@ -1,7 +1,7 @@
 #ifndef __ASM_ARM_IRQ_H
 #define __ASM_ARM_IRQ_H
 
-#include <asm/arch/irqs.h>
+#include <mach/irqs.h>
 
 #ifndef irq_canonicalize
 #define irq_canonicalize(i)     (i)
diff --git a/arch/arm/include/asm/mc146818rtc.h b/arch/arm/include/asm/mc146818rtc.h
index 7b81e0c42543..e1ca48a9e973 100644
--- a/arch/arm/include/asm/mc146818rtc.h
+++ b/arch/arm/include/asm/mc146818rtc.h
@@ -4,7 +4,7 @@
 #ifndef _ASM_MC146818RTC_H
 #define _ASM_MC146818RTC_H
 
-#include <asm/arch/irqs.h>
+#include <mach/irqs.h>
 #include <asm/io.h>
 
 #ifndef RTC_PORT
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 92069221dca9..1e070a2b561a 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -24,7 +24,7 @@
 #endif
 
 #include <linux/compiler.h>
-#include <asm/arch/memory.h>
+#include <mach/memory.h>
 #include <asm/sizes.h>
 
 #ifdef CONFIG_MMU
diff --git a/arch/arm/include/asm/mmzone.h b/arch/arm/include/asm/mmzone.h
index f2fbb5084901..ae63a4fd28c8 100644
--- a/arch/arm/include/asm/mmzone.h
+++ b/arch/arm/include/asm/mmzone.h
@@ -25,6 +25,6 @@ extern pg_data_t discontig_node_data[];
  */
 #define NODE_MEM_MAP(nid)       (NODE_DATA(nid)->node_mem_map)
 
-#include <asm/arch/memory.h>
+#include <mach/memory.h>
 
 #endif
diff --git a/arch/arm/include/asm/mtd-xip.h b/arch/arm/include/asm/mtd-xip.h
index 4bc50f9abe38..4225372a26f3 100644
--- a/arch/arm/include/asm/mtd-xip.h
+++ b/arch/arm/include/asm/mtd-xip.h
@@ -17,8 +17,8 @@
 #ifndef __ARM_MTD_XIP_H__
 #define __ARM_MTD_XIP_H__
 
-#include <asm/arch/hardware.h>
-#include <asm/arch/mtd-xip.h>
+#include <mach/hardware.h>
+#include <mach/mtd-xip.h>
 
 /* fill instruction prefetch */
 #define xip_iprefetch()         do { asm volatile (".rep 8; nop; .endr"); } while (0)
diff --git a/arch/arm/include/asm/pci.h b/arch/arm/include/asm/pci.h
index 968b833f3bb7..721c03d53f4b 100644
--- a/arch/arm/include/asm/pci.h
+++ b/arch/arm/include/asm/pci.h
@@ -4,7 +4,7 @@
 #ifdef __KERNEL__
 #include <asm-generic/pci-dma-compat.h>
 
-#include <asm/arch/hardware.h> /* for PCIBIOS_MIN_* */
+#include <mach/hardware.h> /* for PCIBIOS_MIN_* */
 
 #define pcibios_scan_all_fns(a, b)      0
 
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 8ab060a53ab0..8e21ef15bd74 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -20,7 +20,7 @@
 #else
 
 #include <asm/memory.h>
-#include <asm/arch/vmalloc.h>
+#include <mach/vmalloc.h>
 #include <asm/pgtable-hwdef.h>
 
 /*
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index cc12a525a06a..727b5c042e52 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -14,7 +14,7 @@
 #include <linux/cpumask.h>
 #include <linux/thread_info.h>
 
-#include <asm/arch/smp.h>
+#include <mach/smp.h>
 
 #ifndef CONFIG_SMP
 # error "<asm/smp.h> included in non-SMP build"
diff --git a/arch/arm/include/asm/timex.h b/arch/arm/include/asm/timex.h
index e50e2926cd6e..3be8de3adaba 100644
--- a/arch/arm/include/asm/timex.h
+++ b/arch/arm/include/asm/timex.h
@@ -12,7 +12,7 @@
 #ifndef _ASMARM_TIMEX_H
 #define _ASMARM_TIMEX_H
 
-#include <asm/arch/timex.h>
+#include <mach/timex.h>
 
 typedef unsigned long cycles_t;
 
diff --git a/arch/arm/include/asm/vga.h b/arch/arm/include/asm/vga.h
index 4f767ad3a0bb..6a3cd2a2f670 100644
--- a/arch/arm/include/asm/vga.h
+++ b/arch/arm/include/asm/vga.h
@@ -1,7 +1,7 @@
 #ifndef ASMARM_VGA_H
 #define ASMARM_VGA_H
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 
 #define VGA_MAP_MEM(x,s)        (PCIMEM_BASE + (x))
diff --git a/arch/arm/kernel/crunch-bits.S b/arch/arm/kernel/crunch-bits.S
index a26886758c67..0ec9bb48fab9 100644
--- a/arch/arm/kernel/crunch-bits.S
+++ b/arch/arm/kernel/crunch-bits.S
@@ -16,7 +16,7 @@
 #include <asm/ptrace.h>
 #include <asm/thread_info.h>
 #include <asm/asm-offsets.h>
-#include <asm/arch/ep93xx-regs.h>
+#include <mach/ep93xx-regs.h>
 
 /*
  * We can't use hex constants here due to a bug in gas.
diff --git a/arch/arm/kernel/crunch.c b/arch/arm/kernel/crunch.c
index 627d79414c9d..3b6a1c293ee4 100644
--- a/arch/arm/kernel/crunch.c
+++ b/arch/arm/kernel/crunch.c
@@ -15,7 +15,7 @@
 #include <linux/signal.h>
 #include <linux/sched.h>
 #include <linux/init.h>
-#include <asm/arch/ep93xx-regs.h>
+#include <mach/ep93xx-regs.h>
 #include <asm/thread_notify.h>
 #include <asm/io.h>
 
diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S
index 5617566477b4..9550ff0ddde4 100644
--- a/arch/arm/kernel/debug.S
+++ b/arch/arm/kernel/debug.S
@@ -80,7 +80,7 @@
 #endif  /* CONFIG_CPU_V6 */
 
 #else
-#include <asm/arch/debug-macro.S>
+#include <mach/debug-macro.S>
 #endif  /* CONFIG_DEBUG_ICEDCC */
 
 /*
diff --git a/arch/arm/kernel/ecard.c b/arch/arm/kernel/ecard.c
index 8192fe8409d3..7a50575a8d4d 100644
--- a/arch/arm/kernel/ecard.c
+++ b/arch/arm/kernel/ecard.c
@@ -46,7 +46,7 @@
 
 #include <asm/dma.h>
 #include <asm/ecard.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mmu_context.h>
 #include <asm/mach/irq.h>
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 7dca225752c1..617e509d60df 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -18,7 +18,7 @@
 #include <asm/memory.h>
 #include <asm/glue.h>
 #include <asm/vfpmacros.h>
-#include <asm/arch/entry-macro.S>
+#include <mach/entry-macro.S>
 #include <asm/thread_notify.h>
 
 #include "entry-header.S"
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 84694e88b428..060d7e2e9f64 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -10,7 +10,7 @@
 
 #include <asm/unistd.h>
 #include <asm/ftrace.h>
-#include <asm/arch/entry-macro.S>
+#include <mach/entry-macro.S>
 
 #include "entry-header.S"
 
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 89bfded70a1f..3fd882337064 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -51,7 +51,7 @@ extern void setup_mm_for_reboot(char mode);
 
 static volatile int hlt_counter;
 
-#include <asm/arch/system.h>
+#include <mach/system.h>
 
 void disable_hlt(void)
 {
diff --git a/arch/arm/lib/ecard.S b/arch/arm/lib/ecard.S
index 79cf247ad525..8678eb2b7a60 100644
--- a/arch/arm/lib/ecard.S
+++ b/arch/arm/lib/ecard.S
@@ -12,7 +12,7 @@
  */
 #include <linux/linkage.h>
 #include <asm/assembler.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 #define CPSR2SPSR(rt) \
                 mrs     rt, cpsr; \
diff --git a/arch/arm/lib/io-readsw-armv3.S b/arch/arm/lib/io-readsw-armv3.S
index 4cc4411595f5..9aaf7c72065d 100644
--- a/arch/arm/lib/io-readsw-armv3.S
+++ b/arch/arm/lib/io-readsw-armv3.S
@@ -9,7 +9,7 @@
  */
 #include <linux/linkage.h>
 #include <asm/assembler.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 .Linsw_bad_alignment:
                 adr     r0, .Linsw_bad_align_msg
diff --git a/arch/arm/lib/io-writesw-armv3.S b/arch/arm/lib/io-writesw-armv3.S
index 0a34752bc448..cd34503e424d 100644
--- a/arch/arm/lib/io-writesw-armv3.S
+++ b/arch/arm/lib/io-writesw-armv3.S
@@ -9,7 +9,7 @@
  */
 #include <linux/linkage.h>
 #include <asm/assembler.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 .Loutsw_bad_alignment:
                 adr     r0, .Loutsw_bad_align_msg
diff --git a/arch/arm/mach-aaec2000/aaed2000.c b/arch/arm/mach-aaec2000/aaed2000.c
index 08f030d506b8..81a3ecc0d104 100644
--- a/arch/arm/mach-aaec2000/aaed2000.c
+++ b/arch/arm/mach-aaec2000/aaed2000.c
@@ -20,14 +20,14 @@
 #include <asm/setup.h>
 #include <asm/memory.h>
 #include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/aaed2000.h>
+#include <mach/aaed2000.h>
 
 #include "core.h"
 
diff --git a/arch/arm/mach-aaec2000/core.c b/arch/arm/mach-aaec2000/core.c
index 2e0cec2dc997..dfb26bc23d1a 100644
--- a/arch/arm/mach-aaec2000/core.c
+++ b/arch/arm/mach-aaec2000/core.c
@@ -20,7 +20,7 @@
 #include <linux/timex.h>
 #include <linux/signal.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/sizes.h>
 
diff --git a/arch/arm/mach-aaec2000/include/mach/aaec2000.h b/arch/arm/mach-aaec2000/include/mach/aaec2000.h
new file mode 100644
index 000000000000..bc729c42f843
--- /dev/null
+++ b/arch/arm/mach-aaec2000/include/mach/aaec2000.h
@@ -0,0 +1,207 @@
+/*
+ *  arch/arm/mach-aaec2000/include/mach/aaec2000.h
+ *
+ *  AAEC-2000 registers definition
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_AAEC2000_H
+#define __ASM_ARCH_AAEC2000_H
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#error You must include hardware.h not this file
+#endif /* __ASM_ARCH_HARDWARE_H */
+
+/* Chip selects */
+#define AAEC_CS0        0x00000000
+#define AAEC_CS1        0x10000000
+#define AAEC_CS2        0x20000000
+#define AAEC_CS3        0x30000000
+
+/* Flash */
+#define AAEC_FLASH_BASE AAEC_CS0
+#define AAEC_FLASH_SIZE SZ_64M
+
+/* Interrupt controller */
+#define IRQ_BASE        __REG(0x80000500)
+#define IRQ_INTSR       __REG(0x80000500)       /* Int Status Register */
+#define IRQ_INTRSR      __REG(0x80000504)       /* Int Raw (unmasked) Status */
+#define IRQ_INTENS      __REG(0x80000508)       /* Int Enable Set */
+#define IRQ_INTENC      __REG(0x8000050c)       /* Int Enable Clear */
+
+/* UART 1 */
+#define UART1_BASE      __REG(0x80000600)
+#define UART1_DR        __REG(0x80000600) /* Data/FIFO Register */
+#define UART1_LCR       __REG(0x80000604) /* Link Control Register */
+#define UART1_BRCR      __REG(0x80000608) /* Baud Rate Control Register */
+#define UART1_CR        __REG(0x8000060c) /* Control Register */
+#define UART1_SR        __REG(0x80000610) /* Status Register */
+#define UART1_INT       __REG(0x80000614) /* Interrupt Status Register */
+#define UART1_INTM      __REG(0x80000618) /* Interrupt Mask Register */
+#define UART1_INTRES    __REG(0x8000061c) /* Int Result (masked status) Register */
+
+/* UART 2 */
+#define UART2_BASE      __REG(0x80000700)
+#define UART2_DR        __REG(0x80000700) /* Data/FIFO Register */
+#define UART2_LCR       __REG(0x80000704) /* Link Control Register */
+#define UART2_BRCR      __REG(0x80000708) /* Baud Rate Control Register */
+#define UART2_CR        __REG(0x8000070c) /* Control Register */
+#define UART2_SR        __REG(0x80000710) /* Status Register */
+#define UART2_INT       __REG(0x80000714) /* Interrupt Status Register */
+#define UART2_INTM      __REG(0x80000718) /* Interrupt Mask Register */
+#define UART2_INTRES    __REG(0x8000071c) /* Int Result (masked status) Register */
+
+/* UART 3 */
+#define UART3_BASE      __REG(0x80000800)
+#define UART3_DR        __REG(0x80000800) /* Data/FIFO Register */
+#define UART3_LCR       __REG(0x80000804) /* Link Control Register */
+#define UART3_BRCR      __REG(0x80000808) /* Baud Rate Control Register */
+#define UART3_CR        __REG(0x8000080c) /* Control Register */
+#define UART3_SR        __REG(0x80000810) /* Status Register */
+#define UART3_INT       __REG(0x80000814) /* Interrupt Status Register */
+#define UART3_INTM      __REG(0x80000818) /* Interrupt Mask Register */
+#define UART3_INTRES    __REG(0x8000081c) /* Int Result (masked status) Register */
+
+/* These are used in some places */
+#define _UART1_BASE __PREG(UART1_BASE)
+#define _UART2_BASE __PREG(UART2_BASE)
+#define _UART3_BASE __PREG(UART3_BASE)
+
+/* UART Registers Offsets */
+#define UART_DR         0x00
+#define UART_LCR        0x04
+#define UART_BRCR       0x08
+#define UART_CR         0x0c
+#define UART_SR         0x10
+#define UART_INT        0x14
+#define UART_INTM       0x18
+#define UART_INTRES     0x1c
+
+/* UART_LCR Bitmask */
+#define UART_LCR_BRK    (1 << 0) /* Send Break */
+#define UART_LCR_PEN    (1 << 1) /* Parity Enable */
+#define UART_LCR_EP     (1 << 2) /* Even/Odd Parity */
+#define UART_LCR_S2     (1 << 3) /* One/Two Stop bits */
+#define UART_LCR_FIFO   (1 << 4) /* FIFO Enable */
+#define UART_LCR_WL5    (0 << 5) /* Word Length - 5 bits */
+#define UART_LCR_WL6    (1 << 5) /* Word Length - 6 bits */
+#define UART_LCR_WL7    (1 << 6) /* Word Length - 7 bits */
+#define UART_LCR_WL8    (1 << 7) /* Word Length - 8 bits */
+
+/* UART_CR Bitmask */
+#define UART_CR_EN      (1 << 0) /* UART Enable */
+#define UART_CR_SIR     (1 << 1) /* IrDA SIR Enable */
+#define UART_CR_SIRLP   (1 << 2) /* Low Power IrDA Enable */
+#define UART_CR_RXP     (1 << 3) /* Receive Pin Polarity */
+#define UART_CR_TXP     (1 << 4) /* Transmit Pin Polarity */
+#define UART_CR_MXP     (1 << 5) /* Modem Pin Polarity */
+#define UART_CR_LOOP    (1 << 6) /* Loopback Mode */
+
+/* UART_SR Bitmask */
+#define UART_SR_CTS     (1 << 0) /* Clear To Send Status */
+#define UART_SR_DSR     (1 << 1) /* Data Set Ready Status */
+#define UART_SR_DCD     (1 << 2) /* Data Carrier Detect Status */
+#define UART_SR_TxBSY   (1 << 3) /* Transmitter Busy Status */
+#define UART_SR_RxFE    (1 << 4) /* Receive FIFO Empty Status */
+#define UART_SR_TxFF    (1 << 5) /* Transmit FIFO Full Status */
+#define UART_SR_RxFF    (1 << 6) /* Receive FIFO Full Status */
+#define UART_SR_TxFE    (1 << 7) /* Transmit FIFO Empty Status */
+
+/* UART_INT Bitmask */
+#define UART_INT_RIS    (1 << 0) /* Rx Interrupt */
+#define UART_INT_TIS    (1 << 1) /* Tx Interrupt */
+#define UART_INT_MIS    (1 << 2) /* Modem Interrupt */
+#define UART_INT_RTIS   (1 << 3) /* Receive Timeout Interrupt */
+
+/* Timer 1 */
+#define TIMER1_BASE     __REG(0x80000c00)
+#define TIMER1_LOAD     __REG(0x80000c00)       /* Timer 1 Load Register */
+#define TIMER1_VAL      __REG(0x80000c04)       /* Timer 1 Value Register */
+#define TIMER1_CTRL     __REG(0x80000c08)       /* Timer 1 Control Register */
+#define TIMER1_CLEAR    __REG(0x80000c0c)       /* Timer 1 Clear Register */
+
+/* Timer 2 */
+#define TIMER2_BASE     __REG(0x80000d00)
+#define TIMER2_LOAD     __REG(0x80000d00)       /* Timer 2 Load Register */
+#define TIMER2_VAL      __REG(0x80000d04)       /* Timer 2 Value Register */
+#define TIMER2_CTRL     __REG(0x80000d08)       /* Timer 2 Control Register */
+#define TIMER2_CLEAR    __REG(0x80000d0c)       /* Timer 2 Clear Register */
+
+/* Timer 3 */
+#define TIMER3_BASE     __REG(0x80000e00)
+#define TIMER3_LOAD     __REG(0x80000e00)       /* Timer 3 Load Register */
+#define TIMER3_VAL      __REG(0x80000e04)       /* Timer 3 Value Register */
+#define TIMER3_CTRL     __REG(0x80000e08)       /* Timer 3 Control Register */
+#define TIMER3_CLEAR    __REG(0x80000e0c)       /* Timer 3 Clear Register */
+
+/* Timer Control register bits */
+#define TIMER_CTRL_ENABLE       (1 << 7) /* Enable (Start Timer) */
+#define TIMER_CTRL_PERIODIC     (1 << 6) /* Periodic Running Mode */
+#define TIMER_CTRL_FREE_RUNNING (0 << 6) /* Normal Running Mode */
+#define TIMER_CTRL_CLKSEL_508K  (1 << 3) /* 508KHz Clock select (Timer 1, 2) */
+#define TIMER_CTRL_CLKSEL_2K    (0 << 3) /* 2KHz Clock Select (Timer 1, 2) */
+
+/* Power and State Control */
+#define POWER_BASE      __REG(0x80000400)
+#define POWER_PWRSR     __REG(0x80000400) /* Power Status Register */
+#define POWER_PWRCNT    __REG(0x80000404) /* Power/Clock control */
+#define POWER_HALT      __REG(0x80000408) /* Power Idle Mode */
+#define POWER_STDBY     __REG(0x8000040c) /* Power Standby Mode */
+#define POWER_BLEOI     __REG(0x80000410) /* Battery Low End of Interrupt */
+#define POWER_MCEOI     __REG(0x80000414) /* Media Changed EoI */
+#define POWER_TEOI      __REG(0x80000418) /* Tick EoI */
+#define POWER_STFCLR    __REG(0x8000041c) /* NbFlg, RSTFlg, PFFlg, CLDFlg Clear */
+#define POWER_CLKSET    __REG(0x80000420) /* Clock Speed Control */
+
+/* GPIO Registers */
+#define AAEC_GPIO_PHYS  0x80000e00
+
+#define AAEC_GPIO_PADR          __REG(AAEC_GPIO_PHYS + 0x00)
+#define AAEC_GPIO_PBDR          __REG(AAEC_GPIO_PHYS + 0x04)
+#define AAEC_GPIO_PCDR          __REG(AAEC_GPIO_PHYS + 0x08)
+#define AAEC_GPIO_PDDR          __REG(AAEC_GPIO_PHYS + 0x0c)
+#define AAEC_GPIO_PADDR         __REG(AAEC_GPIO_PHYS + 0x10)
+#define AAEC_GPIO_PBDDR         __REG(AAEC_GPIO_PHYS + 0x14)
+#define AAEC_GPIO_PCDDR         __REG(AAEC_GPIO_PHYS + 0x18)
+#define AAEC_GPIO_PDDDR         __REG(AAEC_GPIO_PHYS + 0x1c)
+#define AAEC_GPIO_PEDR          __REG(AAEC_GPIO_PHYS + 0x20)
+#define AAEC_GPIO_PEDDR         __REG(AAEC_GPIO_PHYS + 0x24)
+#define AAEC_GPIO_KSCAN         __REG(AAEC_GPIO_PHYS + 0x28)
+#define AAEC_GPIO_PINMUX        __REG(AAEC_GPIO_PHYS + 0x2c)
+#define AAEC_GPIO_PFDR          __REG(AAEC_GPIO_PHYS + 0x30)
+#define AAEC_GPIO_PFDDR         __REG(AAEC_GPIO_PHYS + 0x34)
+#define AAEC_GPIO_PGDR          __REG(AAEC_GPIO_PHYS + 0x38)
+#define AAEC_GPIO_PGDDR         __REG(AAEC_GPIO_PHYS + 0x3c)
+#define AAEC_GPIO_PHDR          __REG(AAEC_GPIO_PHYS + 0x40)
+#define AAEC_GPIO_PHDDR         __REG(AAEC_GPIO_PHYS + 0x44)
+#define AAEC_GPIO_RAZ           __REG(AAEC_GPIO_PHYS + 0x48)
+#define AAEC_GPIO_INTTYPE1      __REG(AAEC_GPIO_PHYS + 0x4c)
+#define AAEC_GPIO_INTTYPE2      __REG(AAEC_GPIO_PHYS + 0x50)
+#define AAEC_GPIO_FEOI          __REG(AAEC_GPIO_PHYS + 0x54)
+#define AAEC_GPIO_INTEN         __REG(AAEC_GPIO_PHYS + 0x58)
+#define AAEC_GPIO_INTSTATUS     __REG(AAEC_GPIO_PHYS + 0x5c)
+#define AAEC_GPIO_RAWINTSTATUS  __REG(AAEC_GPIO_PHYS + 0x60)
+#define AAEC_GPIO_DB            __REG(AAEC_GPIO_PHYS + 0x64)
+#define AAEC_GPIO_PAPINDR       __REG(AAEC_GPIO_PHYS + 0x68)
+#define AAEC_GPIO_PBPINDR       __REG(AAEC_GPIO_PHYS + 0x6c)
+#define AAEC_GPIO_PCPINDR       __REG(AAEC_GPIO_PHYS + 0x70)
+#define AAEC_GPIO_PDPINDR       __REG(AAEC_GPIO_PHYS + 0x74)
+#define AAEC_GPIO_PEPINDR       __REG(AAEC_GPIO_PHYS + 0x78)
+#define AAEC_GPIO_PFPINDR       __REG(AAEC_GPIO_PHYS + 0x7c)
+#define AAEC_GPIO_PGPINDR       __REG(AAEC_GPIO_PHYS + 0x80)
+#define AAEC_GPIO_PHPINDR       __REG(AAEC_GPIO_PHYS + 0x84)
+
+#define AAEC_GPIO_PINMUX_PE0CON         (1 << 0)
+#define AAEC_GPIO_PINMUX_PD0CON         (1 << 1)
+#define AAEC_GPIO_PINMUX_CODECON        (1 << 2)
+#define AAEC_GPIO_PINMUX_UART3CON       (1 << 3)
+
+/* LCD Controller */
+#define AAEC_CLCD_PHYS  0x80003000
+
+#endif /* __ARM_ARCH_AAEC2000_H */
diff --git a/arch/arm/mach-aaec2000/include/mach/aaed2000.h b/arch/arm/mach-aaec2000/include/mach/aaed2000.h
new file mode 100644
index 000000000000..f821295ca71b
--- /dev/null
+++ b/arch/arm/mach-aaec2000/include/mach/aaed2000.h
@@ -0,0 +1,40 @@
+/*
+ *  arch/arm/mach-aaec2000/include/mach/aaed2000.h
+ *
+ *  AAED-2000 specific bits definition
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_AAED2000_H
+#define __ASM_ARCH_AAED2000_H
+
+/* External GPIOs. */
+
+#define EXT_GPIO_PBASE  AAEC_CS3
+#define EXT_GPIO_VBASE  0xf8100000
+#define EXT_GPIO_LENGTH 0x00001000
+
+#define __ext_gpio_p2v(x)       ((x) - EXT_GPIO_PBASE + EXT_GPIO_VBASE)
+#define __ext_gpio_v2p(x)       ((x) + EXT_GPIO_PBASE - EXT_GPIO_VBASE)
+
+#define __EXT_GPIO_REG(x)       (*((volatile u32 *)__ext_gpio_p2v(x)))
+#define __EXT_GPIO_PREG(x)      (__ext_gpio_v2p((u32)&(x)))
+
+#define AAED_EXT_GPIO   __EXT_GPIO_REG(EXT_GPIO_PBASE)
+
+#define AAED_EGPIO_KBD_SCAN     0x00003fff /* Keyboard scan data */
+#define AAED_EGPIO_PWR_INT      0x00008fff /* Smart battery charger interrupt */
+#define AAED_EGPIO_SWITCHED     0x000f0000 /* DIP Switches */
+#define AAED_EGPIO_USB_VBUS     0x00400000 /* USB Vbus sense */
+#define AAED_EGPIO_LCD_PWR_EN   0x02000000 /* LCD and backlight PWR enable */
+#define AAED_EGPIO_nLED0        0x20000000 /* LED 0 */
+#define AAED_EGPIO_nLED1        0x20000000 /* LED 1 */
+#define AAED_EGPIO_nLED2        0x20000000 /* LED 2 */
+
+
+#endif /* __ARM_ARCH_AAED2000_H */
diff --git a/arch/arm/mach-aaec2000/include/mach/debug-macro.S b/arch/arm/mach-aaec2000/include/mach/debug-macro.S
new file mode 100644
index 000000000000..0b6351d7c389
--- /dev/null
+++ b/arch/arm/mach-aaec2000/include/mach/debug-macro.S
@@ -0,0 +1,37 @@
+/*  arch/arm/mach-aaec2000/include/mach/debug-macro.S
+ *
+ *  Debugging macro include header
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#include "hardware.h"
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx, #0x80000000                @ physical
+                movne   \rx, #io_p2v(0x80000000)        @ virtual
+                orr     \rx, \rx, #0x00000800
+                .endm
+
+                .macro  senduart,rd,rx
+                str     \rd, [\rx, #0]
+                .endm
+
+                .macro  busyuart,rd,rx
+1002:           ldr     \rd, [\rx, #0x10]
+                tst     \rd, #(1 << 7)
+                beq     1002b
+                .endm
+
+                .macro  waituart,rd,rx
+#if 0
+1001:           ldr     \rd, [\rx, #0x10]
+                tst     \rd, #(1 << 5)
+                beq     1001b
+#endif
+                .endm
diff --git a/arch/arm/mach-aaec2000/include/mach/dma.h b/arch/arm/mach-aaec2000/include/mach/dma.h
new file mode 100644
index 000000000000..2da846c72fe7
--- /dev/null
+++ b/arch/arm/mach-aaec2000/include/mach/dma.h
@@ -0,0 +1,9 @@
+/*
+ *  arch/arm/mach-aaec2000/include/mach/dma.h
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
diff --git a/arch/arm/mach-aaec2000/include/mach/entry-macro.S b/arch/arm/mach-aaec2000/include/mach/entry-macro.S
new file mode 100644
index 000000000000..c8fb34469007
--- /dev/null
+++ b/arch/arm/mach-aaec2000/include/mach/entry-macro.S
@@ -0,0 +1,40 @@
+/*
+ *  arch/arm/mach-aaec2000/include/mach/entry-macro.S
+ *
+ *  Low-level IRQ helper for aaec-2000 based platforms
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ */
+#include <mach/irqs.h>
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_preamble, base, tmp
+                .endm
+
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                mov     r4, #0xf8000000
+                add     r4, r4, #0x00000500
+                mov     \base, r4
+                ldr     \irqstat, [\base, #0]
+                cmp     \irqstat, #0
+                bne     1001f
+                ldr     \irqnr, =NR_IRQS+1
+                b       1003f
+1001:           mov     \irqnr, #0
+1002:           ands    \tmp, \irqstat, #1
+                mov     \irqstat, \irqstat, LSR #1
+                add     \irqnr, \irqnr, #1
+                beq     1002b
+                sub     \irqnr, \irqnr, #1
+1003:
+                .endm
diff --git a/arch/arm/mach-aaec2000/include/mach/hardware.h b/arch/arm/mach-aaec2000/include/mach/hardware.h
new file mode 100644
index 000000000000..965a6f6672d6
--- /dev/null
+++ b/arch/arm/mach-aaec2000/include/mach/hardware.h
@@ -0,0 +1,50 @@
+/*
+ *  arch/arm/mach-aaec2000/include/mach/hardware.h
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/sizes.h>
+#include <mach/aaec2000.h>
+
+/* The kernel is loaded at physical address 0xf8000000.
+ * We map the IO space a bit after
+ */
+#define PIO_APB_BASE    0x80000000
+#define VIO_APB_BASE    0xf8000000
+#define IO_APB_LENGTH   0x2000
+#define PIO_AHB_BASE    0x80002000
+#define VIO_AHB_BASE    0xf8002000
+#define IO_AHB_LENGTH   0x2000
+
+#define VIO_BASE    VIO_APB_BASE
+#define PIO_BASE    PIO_APB_BASE
+
+#define io_p2v(x) ( (x) - PIO_BASE + VIO_BASE )
+#define io_v2p(x) ( (x) + PIO_BASE - VIO_BASE )
+
+#ifndef __ASSEMBLY__
+
+#include <asm/types.h>
+
+/* FIXME: Is it needed to optimize this a la pxa ?? */
+#define __REG(x)    (*((volatile u32 *)io_p2v(x)))
+#define __PREG(x)   (io_v2p((u32)&(x)))
+
+#else /* __ASSEMBLY__ */
+
+#define __REG(x)    io_p2v(x)
+#define __PREG(x)   io_v2p(x)
+
+#endif
+
+#include "aaec2000.h"
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-aaec2000/include/mach/io.h b/arch/arm/mach-aaec2000/include/mach/io.h
new file mode 100644
index 000000000000..c87c24de1110
--- /dev/null
+++ b/arch/arm/mach-aaec2000/include/mach/io.h
@@ -0,0 +1,20 @@
+/*
+ *  arch/arm/mach-aaec2000/include/mach/io.h
+ *
+ *  Copied from asm/arch/sa1100/io.h
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#include <mach/hardware.h>
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * We don't actually have real ISA nor PCI buses, but there is so many
+ * drivers out there that might just work if we fake them...
+ */
+#define __io(a)                 ((void __iomem *)(a))
+#define __mem_pci(a)            (a)
+
+#endif
diff --git a/arch/arm/mach-aaec2000/include/mach/irqs.h b/arch/arm/mach-aaec2000/include/mach/irqs.h
new file mode 100644
index 000000000000..bf45c6d2f294
--- /dev/null
+++ b/arch/arm/mach-aaec2000/include/mach/irqs.h
@@ -0,0 +1,46 @@
+/*
+ *  arch/arm/mach-aaec2000/include/mach/irqs.h
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+
+#define INT_GPIOF0_FIQ  0  /* External GPIO Port F O Fast Interrupt Input */
+#define INT_BL_FIQ      1  /* Battery Low Fast Interrupt */
+#define INT_WE_FIQ      2  /* Watchdog Expired Fast Interrupt */
+#define INT_MV_FIQ      3  /* Media Changed Interrupt */
+#define INT_SC          4  /* Sound Codec Interrupt */
+#define INT_GPIO1       5  /* GPIO Port F Configurable Int 1 */
+#define INT_GPIO2       6  /* GPIO Port F Configurable Int 2 */
+#define INT_GPIO3       7  /* GPIO Port F Configurable Int 3 */
+#define INT_TMR1_OFL    8  /* Timer 1 Overflow Interrupt */
+#define INT_TMR2_OFL    9  /* Timer 2 Overflow Interrupt */
+#define INT_RTC_CM      10 /* RTC Compare Match Interrupt */
+#define INT_TICK        11 /* 64Hz Tick Interrupt */
+#define INT_UART1       12 /* UART1 Interrupt */
+#define INT_UART2       13 /* UART2 & Modem State Changed Interrupt */
+#define INT_LCD         14 /* LCD Interrupt */
+#define INT_SSI         15 /* SSI End of Transfer Interrupt */
+#define INT_UART3       16 /* UART3 Interrupt */
+#define INT_SCI         17 /* SCI Interrupt */
+#define INT_AAC         18 /* Advanced Audio Codec Interrupt */
+#define INT_MMC         19 /* MMC Interrupt */
+#define INT_USB         20 /* USB Interrupt */
+#define INT_DMA         21 /* DMA Interrupt */
+#define INT_TMR3_UOFL   22 /* Timer 3 Underflow Interrupt */
+#define INT_GPIO4       23 /* GPIO Port F Configurable Int 4 */
+#define INT_GPIO5       24 /* GPIO Port F Configurable Int 4 */
+#define INT_GPIO6       25 /* GPIO Port F Configurable Int 4 */
+#define INT_GPIO7       26 /* GPIO Port F Configurable Int 4 */
+#define INT_BMI         27 /* BMI Interrupt */
+
+#define NR_IRQS         (INT_BMI + 1)
+
+#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-aaec2000/include/mach/memory.h b/arch/arm/mach-aaec2000/include/mach/memory.h
new file mode 100644
index 000000000000..56ae900a482e
--- /dev/null
+++ b/arch/arm/mach-aaec2000/include/mach/memory.h
@@ -0,0 +1,30 @@
+/*
+ *  arch/arm/mach-aaec2000/include/mach/memory.h
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+
+#define PHYS_OFFSET     UL(0xf0000000)
+
+#define __virt_to_bus(x)        __virt_to_phys(x)
+#define __bus_to_virt(x)        __phys_to_virt(x)
+
+/*
+ * The nodes are the followings:
+ *
+ *   node 0: 0xf000.0000 - 0xf3ff.ffff
+ *   node 1: 0xf400.0000 - 0xf7ff.ffff
+ *   node 2: 0xf800.0000 - 0xfbff.ffff
+ *   node 3: 0xfc00.0000 - 0xffff.ffff
+ */
+#define NODE_MEM_SIZE_BITS      26
+
+#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-aaec2000/include/mach/system.h b/arch/arm/mach-aaec2000/include/mach/system.h
new file mode 100644
index 000000000000..8f4115d734ce
--- /dev/null
+++ b/arch/arm/mach-aaec2000/include/mach/system.h
@@ -0,0 +1,24 @@
+/*
+ *  arch/arm/mach-aaed2000/include/mach/system.h
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        cpu_reset(0);
+}
+
+#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-aaec2000/include/mach/timex.h b/arch/arm/mach-aaec2000/include/mach/timex.h
new file mode 100644
index 000000000000..6c8edf4a8828
--- /dev/null
+++ b/arch/arm/mach-aaec2000/include/mach/timex.h
@@ -0,0 +1,18 @@
+/*
+ *  arch/arm/mach-aaec2000/include/mach/timex.h
+ *
+ *  AAEC-2000 Architecture timex specification
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+
+#define CLOCK_TICK_RATE         508000
+
+#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-aaec2000/include/mach/uncompress.h b/arch/arm/mach-aaec2000/include/mach/uncompress.h
new file mode 100644
index 000000000000..381ecad1a1bb
--- /dev/null
+++ b/arch/arm/mach-aaec2000/include/mach/uncompress.h
@@ -0,0 +1,46 @@
+/*
+ *  arch/arm/mach-aaec2000/include/mach/uncompress.h
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+
+#include "hardware.h"
+
+#define UART(x)         (*(volatile unsigned long *)(serial_port + (x)))
+
+static void putc(int c)
+{
+        unsigned long serial_port;
+        do {
+                serial_port = _UART3_BASE;
+                if (UART(UART_CR) & UART_CR_EN) break;
+                serial_port = _UART1_BASE;
+                if (UART(UART_CR) & UART_CR_EN) break;
+                serial_port = _UART2_BASE;
+                if (UART(UART_CR) & UART_CR_EN) break;
+                return;
+        } while (0);
+
+        /* wait for space in the UART's transmitter */
+        while ((UART(UART_SR) & UART_SR_TxFF))
+                barrier();
+
+        /* send the character out. */
+        UART(UART_DR) = c;
+}
+
+static inline void flush(void)
+{
+}
+
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
+
+#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-aaec2000/include/mach/vmalloc.h b/arch/arm/mach-aaec2000/include/mach/vmalloc.h
new file mode 100644
index 000000000000..551f68f666bf
--- /dev/null
+++ b/arch/arm/mach-aaec2000/include/mach/vmalloc.h
@@ -0,0 +1,16 @@
+/*
+ *  arch/arm/mach-aaec2000/include/mach/vmalloc.h
+ *
+ *  Copyright (c) 2005 Nicolas Bellido Y Ortega
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_VMALLOC_H
+#define __ASM_ARCH_VMALLOC_H
+
+#define VMALLOC_END             (PAGE_OFFSET + 0x10000000)
+
+#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-at91/at91cap9.c b/arch/arm/mach-at91/at91cap9.c
index 933fa8f55cbc..638948c16770 100644
--- a/arch/arm/mach-at91/at91cap9.c
+++ b/arch/arm/mach-at91/at91cap9.c
@@ -17,10 +17,10 @@
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <asm/arch/at91cap9.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
-#include <asm/arch/at91_shdwc.h>
+#include <mach/at91cap9.h>
+#include <mach/at91_pmc.h>
+#include <mach/at91_rstc.h>
+#include <mach/at91_shdwc.h>
 
 #include "generic.h"
 #include "clock.h"
diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c
index 25765f1afca9..abb4aac8fa98 100644
--- a/arch/arm/mach-at91/at91cap9_devices.c
+++ b/arch/arm/mach-at91/at91cap9_devices.c
@@ -20,11 +20,11 @@
 
 #include <video/atmel_lcdc.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/at91cap9.h>
-#include <asm/arch/at91cap9_matrix.h>
-#include <asm/arch/at91sam9_smc.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/at91cap9.h>
+#include <mach/at91cap9_matrix.h>
+#include <mach/at91sam9_smc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index d688c1dbd925..28594fcc88e3 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -14,9 +14,9 @@
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <asm/arch/at91rm9200.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_st.h>
+#include <mach/at91rm9200.h>
+#include <mach/at91_pmc.h>
+#include <mach/at91_st.h>
 
 #include "generic.h"
 #include "clock.h"
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index d2c5c84bf6b8..9338825cfcd7 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -17,10 +17,10 @@
 #include <linux/platform_device.h>
 #include <linux/i2c-gpio.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/at91rm9200.h>
-#include <asm/arch/at91rm9200_mc.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/at91rm9200.h>
+#include <mach/at91rm9200_mc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index 50392ff71513..a72e798a2a40 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -26,7 +26,7 @@
 
 #include <asm/mach/time.h>
 
-#include <asm/arch/at91_st.h>
+#include <mach/at91_st.h>
 
 static unsigned long last_crtr;
 static u32 irqmask;
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 380f12a12200..accb69ec478e 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -15,11 +15,11 @@
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/at91sam9260.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
-#include <asm/arch/at91_shdwc.h>
+#include <mach/cpu.h>
+#include <mach/at91sam9260.h>
+#include <mach/at91_pmc.h>
+#include <mach/at91_rstc.h>
+#include <mach/at91_shdwc.h>
 
 #include "generic.h"
 #include "clock.h"
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index f5fec0a9cf49..7774d17dde74 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -16,12 +16,12 @@
 #include <linux/platform_device.h>
 #include <linux/i2c-gpio.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/at91sam9260.h>
-#include <asm/arch/at91sam9260_matrix.h>
-#include <asm/arch/at91sam9_smc.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/cpu.h>
+#include <mach/at91sam9260.h>
+#include <mach/at91sam9260_matrix.h>
+#include <mach/at91sam9_smc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 35bf6fd52516..7b51a59ae8b3 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -15,10 +15,10 @@
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <asm/arch/at91sam9261.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
-#include <asm/arch/at91_shdwc.h>
+#include <mach/at91sam9261.h>
+#include <mach/at91_pmc.h>
+#include <mach/at91_rstc.h>
+#include <mach/at91_shdwc.h>
 
 #include "generic.h"
 #include "clock.h"
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index b80860e31383..6b89172310c7 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -20,11 +20,11 @@
 #include <linux/fb.h>
 #include <video/atmel_lcdc.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/at91sam9261.h>
-#include <asm/arch/at91sam9261_matrix.h>
-#include <asm/arch/at91sam9_smc.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/at91sam9261.h>
+#include <mach/at91sam9261_matrix.h>
+#include <mach/at91sam9_smc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 052074a9f2d3..80bfab5680e2 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -15,10 +15,10 @@
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <asm/arch/at91sam9263.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
-#include <asm/arch/at91_shdwc.h>
+#include <mach/at91sam9263.h>
+#include <mach/at91_pmc.h>
+#include <mach/at91_rstc.h>
+#include <mach/at91_shdwc.h>
 
 #include "generic.h"
 #include "clock.h"
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 42108d02f593..c93992f55dc9 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -19,11 +19,11 @@
 #include <linux/fb.h>
 #include <video/atmel_lcdc.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/at91sam9263.h>
-#include <asm/arch/at91sam9263_matrix.h>
-#include <asm/arch/at91sam9_smc.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/at91sam9263.h>
+#include <mach/at91sam9263_matrix.h>
+#include <mach/at91sam9_smc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index 5cecbd7de6a6..122fd77ed580 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -17,7 +17,7 @@
 
 #include <asm/mach/time.h>
 
-#include <asm/arch/at91_pit.h>
+#include <mach/at91_pit.h>
 
 
 #define PIT_CPIV(x)     ((x) & AT91_PIT_CPIV)
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 902c79893ec7..556bddf35b45 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -14,11 +14,11 @@
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/at91sam9rl.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
-#include <asm/arch/at91_shdwc.h>
+#include <mach/cpu.h>
+#include <mach/at91sam9rl.h>
+#include <mach/at91_pmc.h>
+#include <mach/at91_rstc.h>
+#include <mach/at91_shdwc.h>
 
 #include "generic.h"
 #include "clock.h"
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index 9c61576f1c8d..620886341fb5 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -16,11 +16,11 @@
 #include <linux/fb.h>
 #include <video/atmel_lcdc.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/at91sam9rl.h>
-#include <asm/arch/at91sam9rl_matrix.h>
-#include <asm/arch/at91sam9_smc.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/at91sam9rl.h>
+#include <mach/at91sam9rl_matrix.h>
+#include <mach/at91sam9_smc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c
index f44647738ee4..ad3ec85b2790 100644
--- a/arch/arm/mach-at91/at91x40.c
+++ b/arch/arm/mach-at91/at91x40.c
@@ -14,9 +14,9 @@
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <asm/mach/arch.h>
-#include <asm/arch/at91x40.h>
-#include <asm/arch/at91_st.h>
-#include <asm/arch/timex.h>
+#include <mach/at91x40.h>
+#include <mach/at91_st.h>
+#include <mach/timex.h>
 #include "generic.h"
 
 /*
diff --git a/arch/arm/mach-at91/at91x40_time.c b/arch/arm/mach-at91/at91x40_time.c
index 44690440e846..869b5e28d195 100644
--- a/arch/arm/mach-at91/at91x40_time.c
+++ b/arch/arm/mach-at91/at91x40_time.c
@@ -23,10 +23,10 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/time.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/mach/time.h>
-#include <asm/arch/at91_tc.h>
+#include <mach/at91_tc.h>
 
 /*
  *      3 counter/timer units present.
diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c
index fc0f293174cb..9b27d167bff0 100644
--- a/arch/arm/mach-at91/board-1arm.c
+++ b/arch/arm/mach-at91/board-1arm.c
@@ -24,7 +24,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -33,8 +33,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/gpio.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
index 17faf3cea12f..cdddca54b938 100644
--- a/arch/arm/mach-at91/board-cam60.c
+++ b/arch/arm/mach-at91/board-cam60.c
@@ -28,7 +28,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -37,8 +37,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/gpio.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-cap9adk.c b/arch/arm/mach-at91/board-cap9adk.c
index fd21d4240e8e..196199552eb6 100644
--- a/arch/arm/mach-at91/board-cap9adk.c
+++ b/arch/arm/mach-at91/board-cap9adk.c
@@ -33,7 +33,7 @@
 
 #include <video/atmel_lcdc.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -42,10 +42,10 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/at91cap9_matrix.h>
-#include <asm/arch/at91sam9_smc.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/at91cap9_matrix.h>
+#include <mach/at91sam9_smc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index 5156fd2883c5..afa1ff0e9577 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -25,7 +25,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -34,8 +34,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/gpio.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index a55e9ca80efd..cb7c9a8fa487 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -28,7 +28,7 @@
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -37,8 +37,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/gpio.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
index dfdd4dda04a8..8db8bd8babd9 100644
--- a/arch/arm/mach-at91/board-csb637.c
+++ b/arch/arm/mach-at91/board-csb637.c
@@ -25,7 +25,7 @@
 #include <linux/platform_device.h>
 #include <linux/mtd/physmap.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -34,8 +34,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/gpio.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-dk.c b/arch/arm/mach-at91/board-dk.c
index 78b5c8b867e2..43e1aa7ecef7 100644
--- a/arch/arm/mach-at91/board-dk.c
+++ b/arch/arm/mach-at91/board-dk.c
@@ -29,7 +29,7 @@
 #include <linux/spi/spi.h>
 #include <linux/mtd/physmap.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -38,9 +38,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/at91rm9200_mc.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/at91rm9200_mc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-eb01.c b/arch/arm/mach-at91/board-eb01.c
index 631af0857d78..1f9d3cb64c50 100644
--- a/arch/arm/mach-at91/board-eb01.c
+++ b/arch/arm/mach-at91/board-eb01.c
@@ -24,10 +24,10 @@
 #include <linux/platform_device.h>
 #include <linux/irq.h>
 #include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <asm/arch/board.h>
+#include <mach/board.h>
 #include "generic.h"
 
 static void __init at91eb01_map_io(void)
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
index 58ae7a6c2405..528656761ff7 100644
--- a/arch/arm/mach-at91/board-eb9200.c
+++ b/arch/arm/mach-at91/board-eb9200.c
@@ -25,7 +25,7 @@
 #include <linux/module.h>
 #include <linux/device.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -34,8 +34,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/gpio.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
index 665d3091bafd..bfeee8a2af28 100644
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ b/arch/arm/mach-at91/board-ecbat91.c
@@ -27,7 +27,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -36,8 +36,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/gpio.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-ek.c b/arch/arm/mach-at91/board-ek.c
index dbe79df1f0ab..60626e7a3490 100644
--- a/arch/arm/mach-at91/board-ek.c
+++ b/arch/arm/mach-at91/board-ek.c
@@ -29,7 +29,7 @@
 #include <linux/spi/spi.h>
 #include <linux/mtd/physmap.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -38,9 +38,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/at91rm9200_mc.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/at91rm9200_mc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
index 16577a064715..a87956c0a74f 100644
--- a/arch/arm/mach-at91/board-kafa.c
+++ b/arch/arm/mach-at91/board-kafa.c
@@ -24,7 +24,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -33,8 +33,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/gpio.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index 6054e982e289..fe9b9913fa3c 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -25,7 +25,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -34,10 +34,10 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/gpio.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
 
-#include <asm/arch/at91rm9200_mc.h>
+#include <mach/at91rm9200_mc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index ea39c6c186eb..dbc912d633c7 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -27,7 +27,7 @@
 #include <linux/spi/spi.h>
 #include <linux/mtd/physmap.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -36,9 +36,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/at91rm9200_mc.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/at91rm9200_mc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
index 5393b8079bd7..4c28413426c2 100644
--- a/arch/arm/mach-at91/board-qil-a9260.c
+++ b/arch/arm/mach-at91/board-qil-a9260.c
@@ -30,7 +30,7 @@
 #include <linux/input.h>
 #include <linux/clk.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -39,9 +39,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/at91_shdwc.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/at91_shdwc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index fe8a8ac89d64..e4910cb26c16 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -27,7 +27,7 @@
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -36,8 +36,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/gpio.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index 6f3b377dc378..cb20e70b3b06 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -28,7 +28,7 @@
 #include <linux/spi/at73c213.h>
 #include <linux/clk.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -37,8 +37,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/gpio.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index 9d3c65e79c36..1a9963b811c7 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -35,7 +35,7 @@
 
 #include <video/atmel_lcdc.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -44,9 +44,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/at91sam9_smc.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/at91sam9_smc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index 334b159285c3..b1d11960a735 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -32,7 +32,7 @@
 
 #include <video/atmel_lcdc.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -41,9 +41,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/at91sam9_smc.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/at91sam9_smc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index f0975bba6d51..d4eba5c0ce02 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -26,7 +26,7 @@
 #include <linux/spi/at73c213.h>
 #include <linux/clk.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -35,8 +35,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/gpio.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index 5271200b6ded..c6dce49c388c 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -18,7 +18,7 @@
 
 #include <video/atmel_lcdc.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -27,9 +27,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/at91sam9_smc.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/at91sam9_smc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-usb-a9260.c b/arch/arm/mach-at91/board-usb-a9260.c
index 4048e47c5190..f9d0b65da40b 100644
--- a/arch/arm/mach-at91/board-usb-a9260.c
+++ b/arch/arm/mach-at91/board-usb-a9260.c
@@ -30,7 +30,7 @@
 #include <linux/input.h>
 #include <linux/clk.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -39,9 +39,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/at91_shdwc.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/at91_shdwc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-usb-a9263.c b/arch/arm/mach-at91/board-usb-a9263.c
index a2b94947f575..673e5c27214d 100644
--- a/arch/arm/mach-at91/board-usb-a9263.c
+++ b/arch/arm/mach-at91/board-usb-a9263.c
@@ -29,7 +29,7 @@
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -38,9 +38,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/at91_shdwc.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/at91_shdwc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index 0aa3ddaf3d65..36b380aad006 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -33,7 +33,7 @@
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -42,9 +42,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/at91rm9200_mc.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/at91rm9200_mc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index daebd72a6294..f5c2847161f5 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -25,9 +25,9 @@
 
 #include <asm/io.h>
 
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/cpu.h>
+#include <mach/hardware.h>
+#include <mach/at91_pmc.h>
+#include <mach/cpu.h>
 
 #include "clock.h"
 
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index 4db221e03457..8392d5b517f1 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -20,9 +20,9 @@
 #include <linux/module.h>
 
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pio.h>
-#include <asm/arch/gpio.h>
+#include <mach/hardware.h>
+#include <mach/at91_pio.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/include/mach/at91_adc.h b/arch/arm/mach-at91/include/mach/at91_adc.h
new file mode 100644
index 000000000000..8e7ed5c90817
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_adc.h
@@ -0,0 +1,61 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91_adc.h
+ *
+ * Copyright (C) SAN People
+ *
+ * Analog-to-Digital Converter (ADC) registers.
+ * Based on AT91SAM9260 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_ADC_H
+#define AT91_ADC_H
+
+#define AT91_ADC_CR             0x00            /* Control Register */
+#define         AT91_ADC_SWRST          (1 << 0)        /* Software Reset */
+#define         AT91_ADC_START          (1 << 1)        /* Start Conversion */
+
+#define AT91_ADC_MR             0x04            /* Mode Register */
+#define         AT91_ADC_TRGEN          (1 << 0)        /* Trigger Enable */
+#define         AT91_ADC_TRGSEL         (7 << 1)        /* Trigger Selection */
+#define                 AT91_ADC_TRGSEL_TC0             (0 << 1)
+#define                 AT91_ADC_TRGSEL_TC1             (1 << 1)
+#define                 AT91_ADC_TRGSEL_TC2             (2 << 1)
+#define                 AT91_ADC_TRGSEL_EXTERNAL        (6 << 1)
+#define         AT91_ADC_LOWRES         (1 << 4)        /* Low Resolution */
+#define         AT91_ADC_SLEEP          (1 << 5)        /* Sleep Mode */
+#define         AT91_ADC_PRESCAL        (0x3f << 8)     /* Prescalar Rate Selection */
+#define                 AT91_ADC_PRESCAL_(x)    ((x) << 8)
+#define         AT91_ADC_STARTUP        (0x1f << 16)    /* Startup Up Time */
+#define                 AT91_ADC_STARTUP_(x)    ((x) << 16)
+#define         AT91_ADC_SHTIM          (0xf  << 24)    /* Sample & Hold Time */
+#define                 AT91_ADC_SHTIM_(x)      ((x) << 24)
+
+#define AT91_ADC_CHER           0x10            /* Channel Enable Register */
+#define AT91_ADC_CHDR           0x14            /* Channel Disable Register */
+#define AT91_ADC_CHSR           0x18            /* Channel Status Register */
+#define         AT91_ADC_CH(n)          (1 << (n))      /* Channel Number */
+
+#define AT91_ADC_SR             0x1C            /* Status Register */
+#define         AT91_ADC_EOC(n)         (1 << (n))      /* End of Conversion on Channel N */
+#define         AT91_ADC_OVRE(n)        (1 << ((n) + 8))/* Overrun Error on Channel N */
+#define         AT91_ADC_DRDY           (1 << 16)       /* Data Ready */
+#define         AT91_ADC_GOVRE          (1 << 17)       /* General Overrun Error */
+#define         AT91_ADC_ENDRX          (1 << 18)       /* End of RX Buffer */
+#define         AT91_ADC_RXFUFF         (1 << 19)       /* RX Buffer Full */
+
+#define AT91_ADC_LCDR           0x20            /* Last Converted Data Register */
+#define         AT91_ADC_LDATA          (0x3ff)
+
+#define AT91_ADC_IER            0x24            /* Interrupt Enable Register */
+#define AT91_ADC_IDR            0x28            /* Interrupt Disable Register */
+#define AT91_ADC_IMR            0x2C            /* Interrupt Mask Register */
+
+#define AT91_ADC_CHR(n)         (0x30 + ((n) * 4))      /* Channel Data Register N */
+#define         AT91_ADC_DATA           (0x3ff)
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_aic.h b/arch/arm/mach-at91/include/mach/at91_aic.h
new file mode 100644
index 000000000000..03566799d3be
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_aic.h
@@ -0,0 +1,53 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91_aic.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Advanced Interrupt Controller (AIC) - System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_AIC_H
+#define AT91_AIC_H
+
+#define AT91_AIC_SMR(n)         (AT91_AIC + ((n) * 4))  /* Source Mode Registers 0-31 */
+#define         AT91_AIC_PRIOR          (7 << 0)                /* Priority Level */
+#define         AT91_AIC_SRCTYPE        (3 << 5)                /* Interrupt Source Type */
+#define                 AT91_AIC_SRCTYPE_LOW            (0 << 5)
+#define                 AT91_AIC_SRCTYPE_FALLING        (1 << 5)
+#define                 AT91_AIC_SRCTYPE_HIGH           (2 << 5)
+#define                 AT91_AIC_SRCTYPE_RISING         (3 << 5)
+
+#define AT91_AIC_SVR(n)         (AT91_AIC + 0x80 + ((n) * 4))   /* Source Vector Registers 0-31 */
+#define AT91_AIC_IVR            (AT91_AIC + 0x100)      /* Interrupt Vector Register */
+#define AT91_AIC_FVR            (AT91_AIC + 0x104)      /* Fast Interrupt Vector Register */
+#define AT91_AIC_ISR            (AT91_AIC + 0x108)      /* Interrupt Status Register */
+#define         AT91_AIC_IRQID          (0x1f << 0)             /* Current Interrupt Identifier */
+
+#define AT91_AIC_IPR            (AT91_AIC + 0x10c)      /* Interrupt Pending Register */
+#define AT91_AIC_IMR            (AT91_AIC + 0x110)      /* Interrupt Mask Register */
+#define AT91_AIC_CISR           (AT91_AIC + 0x114)      /* Core Interrupt Status Register */
+#define         AT91_AIC_NFIQ           (1 << 0)                /* nFIQ Status */
+#define         AT91_AIC_NIRQ           (1 << 1)                /* nIRQ Status */
+
+#define AT91_AIC_IECR           (AT91_AIC + 0x120)      /* Interrupt Enable Command Register */
+#define AT91_AIC_IDCR           (AT91_AIC + 0x124)      /* Interrupt Disable Command Register */
+#define AT91_AIC_ICCR           (AT91_AIC + 0x128)      /* Interrupt Clear Command Register */
+#define AT91_AIC_ISCR           (AT91_AIC + 0x12c)      /* Interrupt Set Command Register */
+#define AT91_AIC_EOICR          (AT91_AIC + 0x130)      /* End of Interrupt Command Register */
+#define AT91_AIC_SPU            (AT91_AIC + 0x134)      /* Spurious Interrupt Vector Register */
+#define AT91_AIC_DCR            (AT91_AIC + 0x138)      /* Debug Control Register */
+#define         AT91_AIC_DCR_PROT       (1 << 0)                /* Protection Mode */
+#define         AT91_AIC_DCR_GMSK       (1 << 1)                /* General Mask */
+
+#define AT91_AIC_FFER           (AT91_AIC + 0x140)      /* Fast Forcing Enable Register [SAM9 only] */
+#define AT91_AIC_FFDR           (AT91_AIC + 0x144)      /* Fast Forcing Disable Register [SAM9 only] */
+#define AT91_AIC_FFSR           (AT91_AIC + 0x148)      /* Fast Forcing Status Register [SAM9 only] */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_dbgu.h b/arch/arm/mach-at91/include/mach/at91_dbgu.h
new file mode 100644
index 000000000000..6dcaa7716871
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_dbgu.h
@@ -0,0 +1,66 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91_dbgu.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Debug Unit (DBGU) - System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_DBGU_H
+#define AT91_DBGU_H
+
+#ifdef AT91_DBGU
+#define AT91_DBGU_CR            (AT91_DBGU + 0x00)      /* Control Register */
+#define AT91_DBGU_MR            (AT91_DBGU + 0x04)      /* Mode Register */
+#define AT91_DBGU_IER           (AT91_DBGU + 0x08)      /* Interrupt Enable Register */
+#define         AT91_DBGU_TXRDY         (1 << 1)                /* Transmitter Ready */
+#define         AT91_DBGU_TXEMPTY       (1 << 9)                /* Transmitter Empty */
+#define AT91_DBGU_IDR           (AT91_DBGU + 0x0c)      /* Interrupt Disable Register */
+#define AT91_DBGU_IMR           (AT91_DBGU + 0x10)      /* Interrupt Mask Register */
+#define AT91_DBGU_SR            (AT91_DBGU + 0x14)      /* Status Register */
+#define AT91_DBGU_RHR           (AT91_DBGU + 0x18)      /* Receiver Holding Register */
+#define AT91_DBGU_THR           (AT91_DBGU + 0x1c)      /* Transmitter Holding Register */
+#define AT91_DBGU_BRGR          (AT91_DBGU + 0x20)      /* Baud Rate Generator Register */
+
+#define AT91_DBGU_CIDR          (AT91_DBGU + 0x40)      /* Chip ID Register */
+#define AT91_DBGU_EXID          (AT91_DBGU + 0x44)      /* Chip ID Extension Register */
+#define AT91_DBGU_FNR           (AT91_DBGU + 0x48)      /* Force NTRST Register [SAM9 only] */
+#define         AT91_DBGU_FNTRST        (1 << 0)                /* Force NTRST */
+
+#endif /* AT91_DBGU */
+
+/*
+ * Some AT91 parts that don't have full DEBUG units still support the ID
+ * and extensions register.
+ */
+#define         AT91_CIDR_VERSION       (0x1f << 0)             /* Version of the Device */
+#define         AT91_CIDR_EPROC         (7    << 5)             /* Embedded Processor */
+#define         AT91_CIDR_NVPSIZ        (0xf  << 8)             /* Nonvolatile Program Memory Size */
+#define         AT91_CIDR_NVPSIZ2       (0xf  << 12)            /* Second Nonvolatile Program Memory Size */
+#define         AT91_CIDR_SRAMSIZ       (0xf  << 16)            /* Internal SRAM Size */
+#define                 AT91_CIDR_SRAMSIZ_1K    (1 << 16)
+#define                 AT91_CIDR_SRAMSIZ_2K    (2 << 16)
+#define                 AT91_CIDR_SRAMSIZ_112K  (4 << 16)
+#define                 AT91_CIDR_SRAMSIZ_4K    (5 << 16)
+#define                 AT91_CIDR_SRAMSIZ_80K   (6 << 16)
+#define                 AT91_CIDR_SRAMSIZ_160K  (7 << 16)
+#define                 AT91_CIDR_SRAMSIZ_8K    (8 << 16)
+#define                 AT91_CIDR_SRAMSIZ_16K   (9 << 16)
+#define                 AT91_CIDR_SRAMSIZ_32K   (10 << 16)
+#define                 AT91_CIDR_SRAMSIZ_64K   (11 << 16)
+#define                 AT91_CIDR_SRAMSIZ_128K  (12 << 16)
+#define                 AT91_CIDR_SRAMSIZ_256K  (13 << 16)
+#define                 AT91_CIDR_SRAMSIZ_96K   (14 << 16)
+#define                 AT91_CIDR_SRAMSIZ_512K  (15 << 16)
+#define         AT91_CIDR_ARCH          (0xff << 20)            /* Architecture Identifier */
+#define         AT91_CIDR_NVPTYP        (7    << 28)            /* Nonvolatile Program Memory Type */
+#define         AT91_CIDR_EXT           (1    << 31)            /* Extension Flag */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_mci.h b/arch/arm/mach-at91/include/mach/at91_mci.h
new file mode 100644
index 000000000000..550d503a1bca
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_mci.h
@@ -0,0 +1,113 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91_mci.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * MultiMedia Card Interface (MCI) registers.
+ * Based on AT91RM9200 datasheet revision F.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_MCI_H
+#define AT91_MCI_H
+
+#define AT91_MCI_CR             0x00            /* Control Register */
+#define         AT91_MCI_MCIEN          (1 <<  0)       /* Multi-Media Interface Enable */
+#define         AT91_MCI_MCIDIS         (1 <<  1)       /* Multi-Media Interface Disable */
+#define         AT91_MCI_PWSEN          (1 <<  2)       /* Power Save Mode Enable */
+#define         AT91_MCI_PWSDIS         (1 <<  3)       /* Power Save Mode Disable */
+#define         AT91_MCI_SWRST          (1 <<  7)       /* Software Reset */
+
+#define AT91_MCI_MR             0x04            /* Mode Register */
+#define         AT91_MCI_CLKDIV         (0xff  <<  0)   /* Clock Divider */
+#define         AT91_MCI_PWSDIV         (7     <<  8)   /* Power Saving Divider */
+#define         AT91_MCI_RDPROOF        (1     << 11)   /* Read Proof Enable [SAM926[03] only] */
+#define         AT91_MCI_WRPROOF        (1     << 12)   /* Write Proof Enable [SAM926[03] only] */
+#define         AT91_MCI_PDCFBYTE       (1     << 13)   /* PDC Force Byte Transfer [SAM926[03] only] */
+#define         AT91_MCI_PDCPADV        (1     << 14)   /* PDC Padding Value */
+#define         AT91_MCI_PDCMODE        (1     << 15)   /* PDC-orientated Mode */
+#define         AT91_MCI_BLKLEN         (0xfff << 18)   /* Data Block Length */
+
+#define AT91_MCI_DTOR           0x08            /* Data Timeout Register */
+#define         AT91_MCI_DTOCYC         (0xf << 0)      /* Data Timeout Cycle Number */
+#define         AT91_MCI_DTOMUL         (7   << 4)      /* Data Timeout Multiplier */
+#define         AT91_MCI_DTOMUL_1               (0 <<  4)
+#define         AT91_MCI_DTOMUL_16              (1 <<  4)
+#define         AT91_MCI_DTOMUL_128             (2 <<  4)
+#define         AT91_MCI_DTOMUL_256             (3 <<  4)
+#define         AT91_MCI_DTOMUL_1K              (4 <<  4)
+#define         AT91_MCI_DTOMUL_4K              (5 <<  4)
+#define         AT91_MCI_DTOMUL_64K             (6 <<  4)
+#define         AT91_MCI_DTOMUL_1M              (7 <<  4)
+
+#define AT91_MCI_SDCR           0x0c            /* SD Card Register */
+#define         AT91_MCI_SDCSEL         (3 << 0)        /* SD Card Selector */
+#define         AT91_MCI_SDCBUS         (1 << 7)        /* 1-bit or 4-bit bus */
+
+#define AT91_MCI_ARGR           0x10            /* Argument Register */
+
+#define AT91_MCI_CMDR           0x14            /* Command Register */
+#define         AT91_MCI_CMDNB          (0x3f << 0)     /* Command Number */
+#define         AT91_MCI_RSPTYP         (3    << 6)     /* Response Type */
+#define                 AT91_MCI_RSPTYP_NONE    (0 <<  6)
+#define                 AT91_MCI_RSPTYP_48      (1 <<  6)
+#define                 AT91_MCI_RSPTYP_136     (2 <<  6)
+#define         AT91_MCI_SPCMD          (7    << 8)     /* Special Command */
+#define                 AT91_MCI_SPCMD_NONE     (0 <<  8)
+#define                 AT91_MCI_SPCMD_INIT     (1 <<  8)
+#define                 AT91_MCI_SPCMD_SYNC     (2 <<  8)
+#define                 AT91_MCI_SPCMD_ICMD     (4 <<  8)
+#define                 AT91_MCI_SPCMD_IRESP    (5 <<  8)
+#define         AT91_MCI_OPDCMD         (1 << 11)       /* Open Drain Command */
+#define         AT91_MCI_MAXLAT         (1 << 12)       /* Max Latency for Command to Response */
+#define         AT91_MCI_TRCMD          (3 << 16)       /* Transfer Command */
+#define                 AT91_MCI_TRCMD_NONE     (0 << 16)
+#define                 AT91_MCI_TRCMD_START    (1 << 16)
+#define                 AT91_MCI_TRCMD_STOP     (2 << 16)
+#define         AT91_MCI_TRDIR          (1 << 18)       /* Transfer Direction */
+#define         AT91_MCI_TRTYP          (3 << 19)       /* Transfer Type */
+#define                 AT91_MCI_TRTYP_BLOCK    (0 << 19)
+#define                 AT91_MCI_TRTYP_MULTIPLE (1 << 19)
+#define                 AT91_MCI_TRTYP_STREAM   (2 << 19)
+
+#define AT91_MCI_BLKR           0x18            /* Block Register */
+#define         AT91_MCI_BLKR_BCNT(n)   ((0xffff & (n)) << 0)   /* Block count */
+#define         AT91_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16)  /* Block lenght */
+
+#define AT91_MCI_RSPR(n)        (0x20 + ((n) * 4))      /* Response Registers 0-3 */
+#define AT91_MCR_RDR            0x30            /* Receive Data Register */
+#define AT91_MCR_TDR            0x34            /* Transmit Data Register */
+
+#define AT91_MCI_SR             0x40            /* Status Register */
+#define         AT91_MCI_CMDRDY         (1 <<  0)       /* Command Ready */
+#define         AT91_MCI_RXRDY          (1 <<  1)       /* Receiver Ready */
+#define         AT91_MCI_TXRDY          (1 <<  2)       /* Transmit Ready */
+#define         AT91_MCI_BLKE           (1 <<  3)       /* Data Block Ended */
+#define         AT91_MCI_DTIP           (1 <<  4)       /* Data Transfer in Progress */
+#define         AT91_MCI_NOTBUSY        (1 <<  5)       /* Data Not Busy */
+#define         AT91_MCI_ENDRX          (1 <<  6)       /* End of RX Buffer */
+#define         AT91_MCI_ENDTX          (1 <<  7)       /* End fo TX Buffer */
+#define         AT91_MCI_SDIOIRQA       (1 <<  8)       /* SDIO Interrupt for Slot A */
+#define         AT91_MCI_SDIOIRQB       (1 <<  9)       /* SDIO Interrupt for Slot B */
+#define         AT91_MCI_RXBUFF         (1 << 14)       /* RX Buffer Full */
+#define         AT91_MCI_TXBUFE         (1 << 15)       /* TX Buffer Empty */
+#define         AT91_MCI_RINDE          (1 << 16)       /* Response Index Error */
+#define         AT91_MCI_RDIRE          (1 << 17)       /* Response Direction Error */
+#define         AT91_MCI_RCRCE          (1 << 18)       /* Response CRC Error */
+#define         AT91_MCI_RENDE          (1 << 19)       /* Response End Bit Error */
+#define         AT91_MCI_RTOE           (1 << 20)       /* Reponse Time-out Error */
+#define         AT91_MCI_DCRCE          (1 << 21)       /* Data CRC Error */
+#define         AT91_MCI_DTOE           (1 << 22)       /* Data Time-out Error */
+#define         AT91_MCI_OVRE           (1 << 30)       /* Overrun */
+#define         AT91_MCI_UNRE           (1 << 31)       /* Underrun */
+
+#define AT91_MCI_IER            0x44            /* Interrupt Enable Register */
+#define AT91_MCI_IDR            0x48            /* Interrupt Disable Register */
+#define AT91_MCI_IMR            0x4c            /* Interrupt Mask Register */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_pio.h b/arch/arm/mach-at91/include/mach/at91_pio.h
new file mode 100644
index 000000000000..c6a31bf8a5c6
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_pio.h
@@ -0,0 +1,49 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91_pio.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Parallel I/O Controller (PIO) - System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_PIO_H
+#define AT91_PIO_H
+
+#define PIO_PER         0x00    /* Enable Register */
+#define PIO_PDR         0x04    /* Disable Register */
+#define PIO_PSR         0x08    /* Status Register */
+#define PIO_OER         0x10    /* Output Enable Register */
+#define PIO_ODR         0x14    /* Output Disable Register */
+#define PIO_OSR         0x18    /* Output Status Register */
+#define PIO_IFER        0x20    /* Glitch Input Filter Enable */
+#define PIO_IFDR        0x24    /* Glitch Input Filter Disable */
+#define PIO_IFSR        0x28    /* Glitch Input Filter Status */
+#define PIO_SODR        0x30    /* Set Output Data Register */
+#define PIO_CODR        0x34    /* Clear Output Data Register */
+#define PIO_ODSR        0x38    /* Output Data Status Register */
+#define PIO_PDSR        0x3c    /* Pin Data Status Register */
+#define PIO_IER         0x40    /* Interrupt Enable Register */
+#define PIO_IDR         0x44    /* Interrupt Disable Register */
+#define PIO_IMR         0x48    /* Interrupt Mask Register */
+#define PIO_ISR         0x4c    /* Interrupt Status Register */
+#define PIO_MDER        0x50    /* Multi-driver Enable Register */
+#define PIO_MDDR        0x54    /* Multi-driver Disable Register */
+#define PIO_MDSR        0x58    /* Multi-driver Status Register */
+#define PIO_PUDR        0x60    /* Pull-up Disable Register */
+#define PIO_PUER        0x64    /* Pull-up Enable Register */
+#define PIO_PUSR        0x68    /* Pull-up Status Register */
+#define PIO_ASR         0x70    /* Peripheral A Select Register */
+#define PIO_BSR         0x74    /* Peripheral B Select Register */
+#define PIO_ABSR        0x78    /* AB Status Register */
+#define PIO_OWER        0xa0    /* Output Write Enable Register */
+#define PIO_OWDR        0xa4    /* Output Write Disable Register */
+#define PIO_OWSR        0xa8    /* Output Write Status Register */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_pit.h b/arch/arm/mach-at91/include/mach/at91_pit.h
new file mode 100644
index 000000000000..0448ac36eadb
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_pit.h
@@ -0,0 +1,29 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91_pit.h
+ *
+ * Periodic Interval Timer (PIT) - System peripherals regsters.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_PIT_H
+#define AT91_PIT_H
+
+#define AT91_PIT_MR             (AT91_PIT + 0x00)       /* Mode Register */
+#define         AT91_PIT_PITIEN         (1 << 25)               /* Timer Interrupt Enable */
+#define         AT91_PIT_PITEN          (1 << 24)               /* Timer Enabled */
+#define         AT91_PIT_PIV            (0xfffff)               /* Periodic Interval Value */
+
+#define AT91_PIT_SR             (AT91_PIT + 0x04)       /* Status Register */
+#define         AT91_PIT_PITS           (1 << 0)                /* Timer Status */
+
+#define AT91_PIT_PIVR           (AT91_PIT + 0x08)       /* Periodic Interval Value Register */
+#define AT91_PIT_PIIR           (AT91_PIT + 0x0c)       /* Periodic Interval Image Register */
+#define         AT91_PIT_PICNT          (0xfff << 20)           /* Interval Counter */
+#define         AT91_PIT_CPIV           (0xfffff)               /* Inverval Value */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
new file mode 100644
index 000000000000..2e3f2894b704
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -0,0 +1,111 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91_pmc.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Power Management Controller (PMC) - System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_PMC_H
+#define AT91_PMC_H
+
+#define AT91_PMC_SCER           (AT91_PMC + 0x00)       /* System Clock Enable Register */
+#define AT91_PMC_SCDR           (AT91_PMC + 0x04)       /* System Clock Disable Register */
+
+#define AT91_PMC_SCSR           (AT91_PMC + 0x08)       /* System Clock Status Register */
+#define         AT91_PMC_PCK            (1 <<  0)               /* Processor Clock */
+#define         AT91RM9200_PMC_UDP      (1 <<  1)               /* USB Devcice Port Clock [AT91RM9200 only] */
+#define         AT91RM9200_PMC_MCKUDP   (1 <<  2)               /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
+#define         AT91RM9200_PMC_UHP      (1 <<  4)               /* USB Host Port Clock [AT91RM9200 only] */
+#define         AT91SAM926x_PMC_UHP     (1 <<  6)               /* USB Host Port Clock [AT91SAM926x only] */
+#define         AT91CAP9_PMC_UHP        (1 <<  6)               /* USB Host Port Clock [AT91CAP9 only] */
+#define         AT91SAM926x_PMC_UDP     (1 <<  7)               /* USB Devcice Port Clock [AT91SAM926x only] */
+#define         AT91_PMC_PCK0           (1 <<  8)               /* Programmable Clock 0 */
+#define         AT91_PMC_PCK1           (1 <<  9)               /* Programmable Clock 1 */
+#define         AT91_PMC_PCK2           (1 << 10)               /* Programmable Clock 2 */
+#define         AT91_PMC_PCK3           (1 << 11)               /* Programmable Clock 3 */
+#define         AT91_PMC_HCK0           (1 << 16)               /* AHB Clock (USB host) [AT91SAM9261 only] */
+#define         AT91_PMC_HCK1           (1 << 17)               /* AHB Clock (LCD) [AT91SAM9261 only] */
+
+#define AT91_PMC_PCER           (AT91_PMC + 0x10)       /* Peripheral Clock Enable Register */
+#define AT91_PMC_PCDR           (AT91_PMC + 0x14)       /* Peripheral Clock Disable Register */
+#define AT91_PMC_PCSR           (AT91_PMC + 0x18)       /* Peripheral Clock Status Register */
+
+#define AT91_CKGR_UCKR          (AT91_PMC + 0x1C)       /* UTMI Clock Register [SAM9RL, CAP9] */
+#define         AT91_PMC_UPLLEN         (1   << 16)             /* UTMI PLL Enable */
+#define         AT91_PMC_UPLLCOUNT      (0xf << 20)             /* UTMI PLL Start-up Time */
+#define         AT91_PMC_BIASEN         (1   << 24)             /* UTMI BIAS Enable */
+#define         AT91_PMC_BIASCOUNT      (0xf << 28)             /* UTMI PLL Start-up Time */
+
+#define AT91_CKGR_MOR           (AT91_PMC + 0x20)       /* Main Oscillator Register [not on SAM9RL] */
+#define         AT91_PMC_MOSCEN         (1    << 0)             /* Main Oscillator Enable */
+#define         AT91_PMC_OSCBYPASS      (1    << 1)             /* Oscillator Bypass [SAM9x, CAP9] */
+#define         AT91_PMC_OSCOUNT        (0xff << 8)             /* Main Oscillator Start-up Time */
+
+#define AT91_CKGR_MCFR          (AT91_PMC + 0x24)       /* Main Clock Frequency Register */
+#define         AT91_PMC_MAINF          (0xffff <<  0)          /* Main Clock Frequency */
+#define         AT91_PMC_MAINRDY        (1      << 16)          /* Main Clock Ready */
+
+#define AT91_CKGR_PLLAR         (AT91_PMC + 0x28)       /* PLL A Register */
+#define AT91_CKGR_PLLBR         (AT91_PMC + 0x2c)       /* PLL B Register */
+#define         AT91_PMC_DIV            (0xff  <<  0)           /* Divider */
+#define         AT91_PMC_PLLCOUNT       (0x3f  <<  8)           /* PLL Counter */
+#define         AT91_PMC_OUT            (3     << 14)           /* PLL Clock Frequency Range */
+#define         AT91_PMC_MUL            (0x7ff << 16)           /* PLL Multiplier */
+#define         AT91_PMC_USBDIV         (3     << 28)           /* USB Divisor (PLLB only) */
+#define                 AT91_PMC_USBDIV_1               (0 << 28)
+#define                 AT91_PMC_USBDIV_2               (1 << 28)
+#define                 AT91_PMC_USBDIV_4               (2 << 28)
+#define         AT91_PMC_USB96M         (1     << 28)           /* Divider by 2 Enable (PLLB only) */
+
+#define AT91_PMC_MCKR           (AT91_PMC + 0x30)       /* Master Clock Register */
+#define         AT91_PMC_CSS            (3 <<  0)               /* Master Clock Selection */
+#define                 AT91_PMC_CSS_SLOW               (0 << 0)
+#define                 AT91_PMC_CSS_MAIN               (1 << 0)
+#define                 AT91_PMC_CSS_PLLA               (2 << 0)
+#define                 AT91_PMC_CSS_PLLB               (3 << 0)
+#define         AT91_PMC_PRES           (7 <<  2)               /* Master Clock Prescaler */
+#define                 AT91_PMC_PRES_1                 (0 << 2)
+#define                 AT91_PMC_PRES_2                 (1 << 2)
+#define                 AT91_PMC_PRES_4                 (2 << 2)
+#define                 AT91_PMC_PRES_8                 (3 << 2)
+#define                 AT91_PMC_PRES_16                (4 << 2)
+#define                 AT91_PMC_PRES_32                (5 << 2)
+#define                 AT91_PMC_PRES_64                (6 << 2)
+#define         AT91_PMC_MDIV           (3 <<  8)               /* Master Clock Division */
+#define                 AT91RM9200_PMC_MDIV_1           (0 << 8)        /* [AT91RM9200 only] */
+#define                 AT91RM9200_PMC_MDIV_2           (1 << 8)
+#define                 AT91RM9200_PMC_MDIV_3           (2 << 8)
+#define                 AT91RM9200_PMC_MDIV_4           (3 << 8)
+#define                 AT91SAM9_PMC_MDIV_1             (0 << 8)        /* [SAM9,CAP9 only] */
+#define                 AT91SAM9_PMC_MDIV_2             (1 << 8)
+#define                 AT91SAM9_PMC_MDIV_4             (2 << 8)
+#define                 AT91SAM9_PMC_MDIV_6             (3 << 8)
+#define         AT91_PMC_PDIV           (1 << 12)               /* Processor Clock Division [some SAM9 only] */
+#define                 AT91_PMC_PDIV_1                 (0 << 12)
+#define                 AT91_PMC_PDIV_2                 (1 << 12)
+
+#define AT91_PMC_PCKR(n)        (AT91_PMC + 0x40 + ((n) * 4))   /* Programmable Clock 0-3 Registers */
+
+#define AT91_PMC_IER            (AT91_PMC + 0x60)       /* Interrupt Enable Register */
+#define AT91_PMC_IDR            (AT91_PMC + 0x64)       /* Interrupt Disable Register */
+#define AT91_PMC_SR             (AT91_PMC + 0x68)       /* Status Register */
+#define         AT91_PMC_MOSCS          (1 <<  0)               /* MOSCS Flag */
+#define         AT91_PMC_LOCKA          (1 <<  1)               /* PLLA Lock */
+#define         AT91_PMC_LOCKB          (1 <<  2)               /* PLLB Lock */
+#define         AT91_PMC_MCKRDY         (1 <<  3)               /* Master Clock */
+#define         AT91_PMC_LOCKU          (1 <<  6)               /* UPLL Lock [AT91CAP9 only] */
+#define         AT91_PMC_PCK0RDY        (1 <<  8)               /* Programmable Clock 0 */
+#define         AT91_PMC_PCK1RDY        (1 <<  9)               /* Programmable Clock 1 */
+#define         AT91_PMC_PCK2RDY        (1 << 10)               /* Programmable Clock 2 */
+#define         AT91_PMC_PCK3RDY        (1 << 11)               /* Programmable Clock 3 */
+#define AT91_PMC_IMR            (AT91_PMC + 0x6c)       /* Interrupt Mask Register */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_rstc.h b/arch/arm/mach-at91/include/mach/at91_rstc.h
new file mode 100644
index 000000000000..7cd1b39aaa43
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_rstc.h
@@ -0,0 +1,38 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91_rstc.h
+ *
+ * Reset Controller (RSTC) - System peripherals regsters.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_RSTC_H
+#define AT91_RSTC_H
+
+#define AT91_RSTC_CR            (AT91_RSTC + 0x00)      /* Reset Controller Control Register */
+#define         AT91_RSTC_PROCRST       (1 << 0)                /* Processor Reset */
+#define         AT91_RSTC_PERRST        (1 << 2)                /* Peripheral Reset */
+#define         AT91_RSTC_EXTRST        (1 << 3)                /* External Reset */
+#define         AT91_RSTC_KEY           (0xa5 << 24)            /* KEY Password */
+
+#define AT91_RSTC_SR            (AT91_RSTC + 0x04)      /* Reset Controller Status Register */
+#define         AT91_RSTC_URSTS         (1 << 0)                /* User Reset Status */
+#define         AT91_RSTC_RSTTYP        (7 << 8)                /* Reset Type */
+#define                 AT91_RSTC_RSTTYP_GENERAL        (0 << 8)
+#define                 AT91_RSTC_RSTTYP_WAKEUP         (1 << 8)
+#define                 AT91_RSTC_RSTTYP_WATCHDOG       (2 << 8)
+#define                 AT91_RSTC_RSTTYP_SOFTWARE       (3 << 8)
+#define                 AT91_RSTC_RSTTYP_USER   (4 << 8)
+#define         AT91_RSTC_NRSTL         (1 << 16)               /* NRST Pin Level */
+#define         AT91_RSTC_SRCMP         (1 << 17)               /* Software Reset Command in Progress */
+
+#define AT91_RSTC_MR            (AT91_RSTC + 0x08)      /* Reset Controller Mode Register */
+#define         AT91_RSTC_URSTEN        (1 << 0)                /* User Reset Enable */
+#define         AT91_RSTC_URSTIEN       (1 << 4)                /* User Reset Interrupt Enable */
+#define         AT91_RSTC_ERSTL         (0xf << 8)              /* External Reset Length */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_rtc.h b/arch/arm/mach-at91/include/mach/at91_rtc.h
new file mode 100644
index 000000000000..e56f4701a3e5
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_rtc.h
@@ -0,0 +1,75 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91_rtc.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Real Time Clock (RTC) - System peripheral registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_RTC_H
+#define AT91_RTC_H
+
+#define AT91_RTC_CR             (AT91_RTC + 0x00)       /* Control Register */
+#define         AT91_RTC_UPDTIM         (1 <<  0)               /* Update Request Time Register */
+#define         AT91_RTC_UPDCAL         (1 <<  1)               /* Update Request Calendar Register */
+#define         AT91_RTC_TIMEVSEL       (3 <<  8)               /* Time Event Selection */
+#define                 AT91_RTC_TIMEVSEL_MINUTE        (0 << 8)
+#define                 AT91_RTC_TIMEVSEL_HOUR          (1 << 8)
+#define                 AT91_RTC_TIMEVSEL_DAY24         (2 << 8)
+#define                 AT91_RTC_TIMEVSEL_DAY12         (3 << 8)
+#define         AT91_RTC_CALEVSEL       (3 << 16)               /* Calendar Event Selection */
+#define                 AT91_RTC_CALEVSEL_WEEK          (0 << 16)
+#define                 AT91_RTC_CALEVSEL_MONTH         (1 << 16)
+#define                 AT91_RTC_CALEVSEL_YEAR          (2 << 16)
+
+#define AT91_RTC_MR             (AT91_RTC + 0x04)       /* Mode Register */
+#define                 AT91_RTC_HRMOD          (1 <<  0)               /* 12/24 Hour Mode */
+
+#define AT91_RTC_TIMR           (AT91_RTC + 0x08)       /* Time Register */
+#define         AT91_RTC_SEC            (0x7f <<  0)            /* Current Second */
+#define         AT91_RTC_MIN            (0x7f <<  8)            /* Current Minute */
+#define         AT91_RTC_HOUR           (0x3f << 16)            /* Current Hour */
+#define         AT91_RTC_AMPM           (1    << 22)            /* Ante Meridiem Post Meridiem Indicator */
+
+#define AT91_RTC_CALR           (AT91_RTC + 0x0c)       /* Calendar Register */
+#define         AT91_RTC_CENT           (0x7f <<  0)            /* Current Century */
+#define         AT91_RTC_YEAR           (0xff <<  8)            /* Current Year */
+#define         AT91_RTC_MONTH          (0x1f << 16)            /* Current Month */
+#define         AT91_RTC_DAY            (7    << 21)            /* Current Day */
+#define         AT91_RTC_DATE           (0x3f << 24)            /* Current Date */
+
+#define AT91_RTC_TIMALR         (AT91_RTC + 0x10)       /* Time Alarm Register */
+#define         AT91_RTC_SECEN          (1 <<  7)               /* Second Alarm Enable */
+#define         AT91_RTC_MINEN          (1 << 15)               /* Minute Alarm Enable */
+#define         AT91_RTC_HOUREN         (1 << 23)               /* Hour Alarm Enable */
+
+#define AT91_RTC_CALALR         (AT91_RTC + 0x14)       /* Calendar Alarm Register */
+#define         AT91_RTC_MTHEN          (1 << 23)               /* Month Alarm Enable */
+#define         AT91_RTC_DATEEN         (1 << 31)               /* Date Alarm Enable */
+
+#define AT91_RTC_SR             (AT91_RTC + 0x18)       /* Status Register */
+#define         AT91_RTC_ACKUPD         (1 <<  0)               /* Acknowledge for Update */
+#define         AT91_RTC_ALARM          (1 <<  1)               /* Alarm Flag */
+#define         AT91_RTC_SECEV          (1 <<  2)               /* Second Event */
+#define         AT91_RTC_TIMEV          (1 <<  3)               /* Time Event */
+#define         AT91_RTC_CALEV          (1 <<  4)               /* Calendar Event */
+
+#define AT91_RTC_SCCR           (AT91_RTC + 0x1c)       /* Status Clear Command Register */
+#define AT91_RTC_IER            (AT91_RTC + 0x20)       /* Interrupt Enable Register */
+#define AT91_RTC_IDR            (AT91_RTC + 0x24)       /* Interrupt Disable Register */
+#define AT91_RTC_IMR            (AT91_RTC + 0x28)       /* Interrupt Mask Register */
+
+#define AT91_RTC_VER            (AT91_RTC + 0x2c)       /* Valid Entry Register */
+#define         AT91_RTC_NVTIM          (1 <<  0)               /* Non valid Time */
+#define         AT91_RTC_NVCAL          (1 <<  1)               /* Non valid Calendar */
+#define         AT91_RTC_NVTIMALR       (1 <<  2)               /* Non valid Time Alarm */
+#define         AT91_RTC_NVCALALR       (1 <<  3)               /* Non valid Calendar Alarm */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_rtt.h b/arch/arm/mach-at91/include/mach/at91_rtt.h
new file mode 100644
index 000000000000..71782e5d2159
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_rtt.h
@@ -0,0 +1,32 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91_rtt.h
+ *
+ * Real-time Timer (RTT) - System peripherals regsters.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_RTT_H
+#define AT91_RTT_H
+
+#define AT91_RTT_MR             0x00                    /* Real-time Mode Register */
+#define         AT91_RTT_RTPRES         (0xffff << 0)           /* Real-time Timer Prescaler Value */
+#define         AT91_RTT_ALMIEN         (1 << 16)               /* Alarm Interrupt Enable */
+#define         AT91_RTT_RTTINCIEN      (1 << 17)               /* Real Time Timer Increment Interrupt Enable */
+#define         AT91_RTT_RTTRST         (1 << 18)               /* Real Time Timer Restart */
+
+#define AT91_RTT_AR             0x04                    /* Real-time Alarm Register */
+#define         AT91_RTT_ALMV           (0xffffffff)            /* Alarm Value */
+
+#define AT91_RTT_VR             0x08                    /* Real-time Value Register */
+#define         AT91_RTT_CRTV           (0xffffffff)            /* Current Real-time Value */
+
+#define AT91_RTT_SR             0x0c                    /* Real-time Status Register */
+#define         AT91_RTT_ALMS           (1 << 0)                /* Real-time Alarm Status */
+#define         AT91_RTT_RTTINC         (1 << 1)                /* Real-time Timer Increment */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_shdwc.h b/arch/arm/mach-at91/include/mach/at91_shdwc.h
new file mode 100644
index 000000000000..60be5ae624f1
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_shdwc.h
@@ -0,0 +1,35 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91_shdwc.h
+ *
+ * Shutdown Controller (SHDWC) - System peripherals regsters.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_SHDWC_H
+#define AT91_SHDWC_H
+
+#define AT91_SHDW_CR            (AT91_SHDWC + 0x00)     /* Shut Down Control Register */
+#define         AT91_SHDW_SHDW          (1    << 0)             /* Shut Down command */
+#define         AT91_SHDW_KEY           (0xa5 << 24)            /* KEY Password */
+
+#define AT91_SHDW_MR            (AT91_SHDWC + 0x04)     /* Shut Down Mode Register */
+#define         AT91_SHDW_WKMODE0       (3 << 0)                /* Wake-up 0 Mode Selection */
+#define                 AT91_SHDW_WKMODE0_NONE          0
+#define                 AT91_SHDW_WKMODE0_HIGH          1
+#define                 AT91_SHDW_WKMODE0_LOW           2
+#define                 AT91_SHDW_WKMODE0_ANYLEVEL      3
+#define         AT91_SHDW_CPTWK0        (0xf << 4)              /* Counter On Wake Up 0 */
+#define                 AT91_SHDW_CPTWK0_(x)    ((x) << 4)
+#define         AT91_SHDW_RTTWKEN       (1   << 16)             /* Real Time Timer Wake-up Enable */
+
+#define AT91_SHDW_SR            (AT91_SHDWC + 0x08)     /* Shut Down Status Register */
+#define         AT91_SHDW_WAKEUP0       (1 <<  0)               /* Wake-up 0 Status */
+#define         AT91_SHDW_RTTWK         (1 << 16)               /* Real-time Timer Wake-up */
+#define         AT91_SHDW_RTCWK         (1 << 17)               /* Real-time Clock Wake-up [SAM9RL] */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_spi.h b/arch/arm/mach-at91/include/mach/at91_spi.h
new file mode 100644
index 000000000000..2f6ba0c5636e
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_spi.h
@@ -0,0 +1,81 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91_spi.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Serial Peripheral Interface (SPI) registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_SPI_H
+#define AT91_SPI_H
+
+#define AT91_SPI_CR                     0x00            /* Control Register */
+#define         AT91_SPI_SPIEN          (1 <<  0)               /* SPI Enable */
+#define         AT91_SPI_SPIDIS         (1 <<  1)               /* SPI Disable */
+#define         AT91_SPI_SWRST          (1 <<  7)               /* SPI Software Reset */
+#define         AT91_SPI_LASTXFER       (1 << 24)               /* Last Transfer [SAM9261 only] */
+
+#define AT91_SPI_MR                     0x04            /* Mode Register */
+#define         AT91_SPI_MSTR           (1    <<  0)            /* Master/Slave Mode */
+#define         AT91_SPI_PS             (1    <<  1)            /* Peripheral Select */
+#define                 AT91_SPI_PS_FIXED       (0 << 1)
+#define                 AT91_SPI_PS_VARIABLE    (1 << 1)
+#define         AT91_SPI_PCSDEC         (1    <<  2)            /* Chip Select Decode */
+#define         AT91_SPI_DIV32          (1    <<  3)            /* Clock Selection [AT91RM9200 only] */
+#define         AT91_SPI_MODFDIS        (1    <<  4)            /* Mode Fault Detection */
+#define         AT91_SPI_LLB            (1    <<  7)            /* Local Loopback Enable */
+#define         AT91_SPI_PCS            (0xf  << 16)            /* Peripheral Chip Select */
+#define         AT91_SPI_DLYBCS         (0xff << 24)            /* Delay Between Chip Selects */
+
+#define AT91_SPI_RDR            0x08                    /* Receive Data Register */
+#define         AT91_SPI_RD             (0xffff <<  0)          /* Receive Data */
+#define         AT91_SPI_PCS            (0xf    << 16)          /* Peripheral Chip Select */
+
+#define AT91_SPI_TDR            0x0c                    /* Transmit Data Register */
+#define         AT91_SPI_TD             (0xffff <<  0)          /* Transmit Data */
+#define         AT91_SPI_PCS            (0xf    << 16)          /* Peripheral Chip Select */
+#define         AT91_SPI_LASTXFER       (1      << 24)          /* Last Transfer [SAM9261 only] */
+
+#define AT91_SPI_SR             0x10                    /* Status Register */
+#define         AT91_SPI_RDRF           (1 <<  0)               /* Receive Data Register Full */
+#define         AT91_SPI_TDRE           (1 <<  1)               /* Transmit Data Register Full */
+#define         AT91_SPI_MODF           (1 <<  2)               /* Mode Fault Error */
+#define         AT91_SPI_OVRES          (1 <<  3)               /* Overrun Error Status */
+#define         AT91_SPI_ENDRX          (1 <<  4)               /* End of RX buffer */
+#define         AT91_SPI_ENDTX          (1 <<  5)               /* End of TX buffer */
+#define         AT91_SPI_RXBUFF         (1 <<  6)               /* RX Buffer Full */
+#define         AT91_SPI_TXBUFE         (1 <<  7)               /* TX Buffer Empty */
+#define         AT91_SPI_NSSR           (1 <<  8)               /* NSS Rising [SAM9261 only] */
+#define         AT91_SPI_TXEMPTY        (1 <<  9)               /* Transmission Register Empty [SAM9261 only] */
+#define         AT91_SPI_SPIENS         (1 << 16)               /* SPI Enable Status */
+
+#define AT91_SPI_IER            0x14                    /* Interrupt Enable Register */
+#define AT91_SPI_IDR            0x18                    /* Interrupt Disable Register */
+#define AT91_SPI_IMR            0x1c                    /* Interrupt Mask Register */
+
+#define AT91_SPI_CSR(n)         (0x30 + ((n) * 4))      /* Chip Select Registers 0-3 */
+#define         AT91_SPI_CPOL           (1    <<  0)            /* Clock Polarity */
+#define         AT91_SPI_NCPHA          (1    <<  1)            /* Clock Phase */
+#define         AT91_SPI_CSAAT          (1    <<  3)            /* Chip Select Active After Transfer [SAM9261 only] */
+#define         AT91_SPI_BITS           (0xf  <<  4)            /* Bits Per Transfer */
+#define                 AT91_SPI_BITS_8         (0 << 4)
+#define                 AT91_SPI_BITS_9         (1 << 4)
+#define                 AT91_SPI_BITS_10        (2 << 4)
+#define                 AT91_SPI_BITS_11        (3 << 4)
+#define                 AT91_SPI_BITS_12        (4 << 4)
+#define                 AT91_SPI_BITS_13        (5 << 4)
+#define                 AT91_SPI_BITS_14        (6 << 4)
+#define                 AT91_SPI_BITS_15        (7 << 4)
+#define                 AT91_SPI_BITS_16        (8 << 4)
+#define         AT91_SPI_SCBR           (0xff <<  8)            /* Serial Clock Baud Rate */
+#define         AT91_SPI_DLYBS          (0xff << 16)            /* Delay before SPCK */
+#define         AT91_SPI_DLYBCT         (0xff << 24)            /* Delay between Consecutive Transfers */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_ssc.h b/arch/arm/mach-at91/include/mach/at91_ssc.h
new file mode 100644
index 000000000000..a81114c11c74
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_ssc.h
@@ -0,0 +1,106 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91_ssc.h
+ *
+ * Copyright (C) SAN People
+ *
+ * Serial Synchronous Controller (SSC) registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_SSC_H
+#define AT91_SSC_H
+
+#define AT91_SSC_CR             0x00    /* Control Register */
+#define         AT91_SSC_RXEN           (1 <<  0)       /* Receive Enable */
+#define         AT91_SSC_RXDIS          (1 <<  1)       /* Receive Disable */
+#define         AT91_SSC_TXEN           (1 <<  8)       /* Transmit Enable */
+#define         AT91_SSC_TXDIS          (1 <<  9)       /* Transmit Disable */
+#define         AT91_SSC_SWRST          (1 << 15)       /* Software Reset */
+
+#define AT91_SSC_CMR            0x04    /* Clock Mode Register */
+#define         AT91_SSC_CMR_DIV        (0xfff << 0)    /* Clock Divider */
+
+#define AT91_SSC_RCMR           0x10    /* Receive Clock Mode Register */
+#define         AT91_SSC_CKS            (3    <<  0)    /* Clock Selection */
+#define                 AT91_SSC_CKS_DIV                (0 << 0)
+#define                 AT91_SSC_CKS_CLOCK              (1 << 0)
+#define                 AT91_SSC_CKS_PIN                (2 << 0)
+#define         AT91_SSC_CKO            (7    <<  2)    /* Clock Output Mode Selection */
+#define                 AT91_SSC_CKO_NONE               (0 << 2)
+#define                 AT91_SSC_CKO_CONTINUOUS         (1 << 2)
+#define         AT91_SSC_CKI            (1    <<  5)    /* Clock Inversion */
+#define                 AT91_SSC_CKI_FALLING            (0 << 5)
+#define                 AT91_SSC_CK_RISING              (1 << 5)
+#define         AT91_SSC_CKG            (1    <<  6)    /* Receive Clock Gating Selection [AT91SAM9261 only] */
+#define                 AT91_SSC_CKG_NONE               (0 << 6)
+#define                 AT91_SSC_CKG_RFLOW              (1 << 6)
+#define                 AT91_SSC_CKG_RFHIGH             (2 << 6)
+#define         AT91_SSC_START          (0xf  <<  8)    /* Start Selection */
+#define                 AT91_SSC_START_CONTINUOUS       (0 << 8)
+#define                 AT91_SSC_START_TX_RX            (1 << 8)
+#define                 AT91_SSC_START_LOW_RF           (2 << 8)
+#define                 AT91_SSC_START_HIGH_RF          (3 << 8)
+#define                 AT91_SSC_START_FALLING_RF       (4 << 8)
+#define                 AT91_SSC_START_RISING_RF        (5 << 8)
+#define                 AT91_SSC_START_LEVEL_RF         (6 << 8)
+#define                 AT91_SSC_START_EDGE_RF          (7 << 8)
+#define         AT91_SSC_STOP           (1    << 12)    /* Receive Stop Selection [AT91SAM9261 only] */
+#define         AT91_SSC_STTDLY         (0xff << 16)    /* Start Delay */
+#define         AT91_SSC_PERIOD         (0xff << 24)    /* Period Divider Selection */
+
+#define AT91_SSC_RFMR           0x14    /* Receive Frame Mode Register */
+#define         AT91_SSC_DATALEN        (0x1f <<  0)    /* Data Length */
+#define         AT91_SSC_LOOP           (1    <<  5)    /* Loop Mode */
+#define         AT91_SSC_MSBF           (1    <<  7)    /* Most Significant Bit First */
+#define         AT91_SSC_DATNB          (0xf  <<  8)    /* Data Number per Frame */
+#define         AT91_SSC_FSLEN          (0xf  << 16)    /* Frame Sync Length */
+#define         AT91_SSC_FSOS           (7    << 20)    /* Frame Sync Output Selection */
+#define                 AT91_SSC_FSOS_NONE              (0 << 20)
+#define                 AT91_SSC_FSOS_NEGATIVE          (1 << 20)
+#define                 AT91_SSC_FSOS_POSITIVE          (2 << 20)
+#define                 AT91_SSC_FSOS_LOW               (3 << 20)
+#define                 AT91_SSC_FSOS_HIGH              (4 << 20)
+#define                 AT91_SSC_FSOS_TOGGLE            (5 << 20)
+#define         AT91_SSC_FSEDGE         (1    << 24)    /* Frame Sync Edge Detection */
+#define                 AT91_SSC_FSEDGE_POSITIVE        (0 << 24)
+#define                 AT91_SSC_FSEDGE_NEGATIVE        (1 << 24)
+
+#define AT91_SSC_TCMR           0x18    /* Transmit Clock Mode Register */
+#define AT91_SSC_TFMR           0x1c    /* Transmit Fram Mode Register */
+#define         AT91_SSC_DATDEF         (1 <<  5)       /* Data Default Value */
+#define         AT91_SSC_FSDEN          (1 << 23)       /* Frame Sync Data Enable */
+
+#define AT91_SSC_RHR            0x20    /* Receive Holding Register */
+#define AT91_SSC_THR            0x24    /* Transmit Holding Register */
+#define AT91_SSC_RSHR           0x30    /* Receive Sync Holding Register */
+#define AT91_SSC_TSHR           0x34    /* Transmit Sync Holding Register */
+
+#define AT91_SSC_RC0R           0x38    /* Receive Compare 0 Register [AT91SAM9261 only] */
+#define AT91_SSC_RC1R           0x3c    /* Receive Compare 1 Register [AT91SAM9261 only] */
+
+#define AT91_SSC_SR             0x40    /* Status Register */
+#define         AT91_SSC_TXRDY          (1 <<  0)       /* Transmit Ready */
+#define         AT91_SSC_TXEMPTY        (1 <<  1)       /* Transmit Empty */
+#define         AT91_SSC_ENDTX          (1 <<  2)       /* End of Transmission */
+#define         AT91_SSC_TXBUFE         (1 <<  3)       /* Transmit Buffer Empty */
+#define         AT91_SSC_RXRDY          (1 <<  4)       /* Receive Ready */
+#define         AT91_SSC_OVRUN          (1 <<  5)       /* Receive Overrun */
+#define         AT91_SSC_ENDRX          (1 <<  6)       /* End of Reception */
+#define         AT91_SSC_RXBUFF         (1 <<  7)       /* Receive Buffer Full */
+#define         AT91_SSC_CP0            (1 <<  8)       /* Compare 0 [AT91SAM9261 only] */
+#define         AT91_SSC_CP1            (1 <<  9)       /* Compare 1 [AT91SAM9261 only] */
+#define         AT91_SSC_TXSYN          (1 << 10)       /* Transmit Sync */
+#define         AT91_SSC_RXSYN          (1 << 11)       /* Receive Sync */
+#define         AT91_SSC_TXENA          (1 << 16)       /* Transmit Enable */
+#define         AT91_SSC_RXENA          (1 << 17)       /* Receive Enable */
+
+#define AT91_SSC_IER            0x44    /* Interrupt Enable Register */
+#define AT91_SSC_IDR            0x48    /* Interrupt Disable Register */
+#define AT91_SSC_IMR            0x4c    /* Interrupt Mask Register */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_st.h b/arch/arm/mach-at91/include/mach/at91_st.h
new file mode 100644
index 000000000000..8847173e4101
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_st.h
@@ -0,0 +1,49 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91_st.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * System Timer (ST) - System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_ST_H
+#define AT91_ST_H
+
+#define AT91_ST_CR              (AT91_ST + 0x00)        /* Control Register */
+#define         AT91_ST_WDRST           (1 << 0)                /* Watchdog Timer Restart */
+
+#define AT91_ST_PIMR            (AT91_ST + 0x04)        /* Period Interval Mode Register */
+#define         AT91_ST_PIV             (0xffff <<  0)          /* Period Interval Value */
+
+#define AT91_ST_WDMR            (AT91_ST + 0x08)        /* Watchdog Mode Register */
+#define         AT91_ST_WDV             (0xffff <<  0)          /* Watchdog Counter Value */
+#define         AT91_ST_RSTEN           (1      << 16)          /* Reset Enable */
+#define         AT91_ST_EXTEN           (1      << 17)          /* External Signal Assertion Enable */
+
+#define AT91_ST_RTMR            (AT91_ST + 0x0c)        /* Real-time Mode Register */
+#define         AT91_ST_RTPRES          (0xffff <<  0)          /* Real-time Prescalar Value */
+
+#define AT91_ST_SR              (AT91_ST + 0x10)        /* Status Register */
+#define         AT91_ST_PITS            (1 << 0)                /* Period Interval Timer Status */
+#define         AT91_ST_WDOVF           (1 << 1)                /* Watchdog Overflow */
+#define         AT91_ST_RTTINC          (1 << 2)                /* Real-time Timer Increment */
+#define         AT91_ST_ALMS            (1 << 3)                /* Alarm Status */
+
+#define AT91_ST_IER             (AT91_ST + 0x14)        /* Interrupt Enable Register */
+#define AT91_ST_IDR             (AT91_ST + 0x18)        /* Interrupt Disable Register */
+#define AT91_ST_IMR             (AT91_ST + 0x1c)        /* Interrupt Mask Register */
+
+#define AT91_ST_RTAR            (AT91_ST + 0x20)        /* Real-time Alarm Register */
+#define         AT91_ST_ALMV            (0xfffff << 0)          /* Alarm Value */
+
+#define AT91_ST_CRTR            (AT91_ST + 0x24)        /* Current Real-time Register */
+#define         AT91_ST_CRTV            (0xfffff << 0)          /* Current Real-Time Value */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_tc.h b/arch/arm/mach-at91/include/mach/at91_tc.h
new file mode 100644
index 000000000000..46a317fd7164
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_tc.h
@@ -0,0 +1,146 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91_tc.h
+ *
+ * Copyright (C) SAN People
+ *
+ * Timer/Counter Unit (TC) registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_TC_H
+#define AT91_TC_H
+
+#define AT91_TC_BCR             0xc0            /* TC Block Control Register */
+#define         AT91_TC_SYNC            (1 << 0)        /* Synchro Command */
+
+#define AT91_TC_BMR             0xc4            /* TC Block Mode Register */
+#define         AT91_TC_TC0XC0S         (3 << 0)        /* External Clock Signal 0 Selection */
+#define                 AT91_TC_TC0XC0S_TCLK0           (0 << 0)
+#define                 AT91_TC_TC0XC0S_NONE            (1 << 0)
+#define                 AT91_TC_TC0XC0S_TIOA1           (2 << 0)
+#define                 AT91_TC_TC0XC0S_TIOA2           (3 << 0)
+#define         AT91_TC_TC1XC1S         (3 << 2)        /* External Clock Signal 1 Selection */
+#define                 AT91_TC_TC1XC1S_TCLK1           (0 << 2)
+#define                 AT91_TC_TC1XC1S_NONE            (1 << 2)
+#define                 AT91_TC_TC1XC1S_TIOA0           (2 << 2)
+#define                 AT91_TC_TC1XC1S_TIOA2           (3 << 2)
+#define         AT91_TC_TC2XC2S         (3 << 4)        /* External Clock Signal 2 Selection */
+#define                 AT91_TC_TC2XC2S_TCLK2           (0 << 4)
+#define                 AT91_TC_TC2XC2S_NONE            (1 << 4)
+#define                 AT91_TC_TC2XC2S_TIOA0           (2 << 4)
+#define                 AT91_TC_TC2XC2S_TIOA1           (3 << 4)
+
+
+#define AT91_TC_CCR             0x00            /* Channel Control Register */
+#define         AT91_TC_CLKEN           (1 << 0)        /* Counter Clock Enable Command */
+#define         AT91_TC_CLKDIS          (1 << 1)        /* Counter CLock Disable Command */
+#define         AT91_TC_SWTRG           (1 << 2)        /* Software Trigger Command */
+
+#define AT91_TC_CMR             0x04            /* Channel Mode Register */
+#define         AT91_TC_TCCLKS          (7 << 0)        /* Capture/Waveform Mode: Clock Selection */
+#define                 AT91_TC_TIMER_CLOCK1            (0 << 0)
+#define                 AT91_TC_TIMER_CLOCK2            (1 << 0)
+#define                 AT91_TC_TIMER_CLOCK3            (2 << 0)
+#define                 AT91_TC_TIMER_CLOCK4            (3 << 0)
+#define                 AT91_TC_TIMER_CLOCK5            (4 << 0)
+#define                 AT91_TC_XC0                     (5 << 0)
+#define                 AT91_TC_XC1                     (6 << 0)
+#define                 AT91_TC_XC2                     (7 << 0)
+#define         AT91_TC_CLKI            (1 << 3)        /* Capture/Waveform Mode: Clock Invert */
+#define         AT91_TC_BURST           (3 << 4)        /* Capture/Waveform Mode: Burst Signal Selection */
+#define         AT91_TC_LDBSTOP         (1 << 6)        /* Capture Mode: Counter Clock Stopped with TB Loading */
+#define         AT91_TC_LDBDIS          (1 << 7)        /* Capture Mode: Counter Clock Disable with RB Loading */
+#define         AT91_TC_ETRGEDG         (3 << 8)        /* Capture Mode: External Trigger Edge Selection */
+#define         AT91_TC_ABETRG          (1 << 10)       /* Capture Mode: TIOA or TIOB External Trigger Selection */
+#define         AT91_TC_CPCTRG          (1 << 14)       /* Capture Mode: RC Compare Trigger Enable */
+#define         AT91_TC_WAVE            (1 << 15)       /* Capture/Waveform mode */
+#define         AT91_TC_LDRA            (3 << 16)       /* Capture Mode: RA Loading Selection */
+#define         AT91_TC_LDRB            (3 << 18)       /* Capture Mode: RB Loading Selection */
+
+#define         AT91_TC_CPCSTOP         (1 <<  6)       /* Waveform Mode: Counter Clock Stopped with RC Compare */
+#define         AT91_TC_CPCDIS          (1 <<  7)       /* Waveform Mode: Counter Clock Disable with RC Compare */
+#define         AT91_TC_EEVTEDG         (3 <<  8)       /* Waveform Mode: External Event Edge Selection */
+#define                 AT91_TC_EEVTEDG_NONE            (0 << 8)
+#define                 AT91_TC_EEVTEDG_RISING          (1 << 8)
+#define                 AT91_TC_EEVTEDG_FALLING         (2 << 8)
+#define                 AT91_TC_EEVTEDG_BOTH            (3 << 8)
+#define         AT91_TC_EEVT            (3 << 10)       /* Waveform Mode: External Event Selection */
+#define                 AT91_TC_EEVT_TIOB               (0 << 10)
+#define                 AT91_TC_EEVT_XC0                (1 << 10)
+#define                 AT91_TC_EEVT_XC1                (2 << 10)
+#define                 AT91_TC_EEVT_XC2                (3 << 10)
+#define         AT91_TC_ENETRG          (1 << 12)       /* Waveform Mode: External Event Trigger Enable */
+#define         AT91_TC_WAVESEL         (3 << 13)       /* Waveform Mode: Waveform Selection */
+#define                 AT91_TC_WAVESEL_UP              (0 << 13)
+#define                 AT91_TC_WAVESEL_UP_AUTO         (2 << 13)
+#define                 AT91_TC_WAVESEL_UPDOWN          (1 << 13)
+#define                 AT91_TC_WAVESEL_UPDOWN_AUTO     (3 << 13)
+#define         AT91_TC_ACPA            (3 << 16)       /* Waveform Mode: RA Compare Effect on TIOA */
+#define                 AT91_TC_ACPA_NONE               (0 << 16)
+#define                 AT91_TC_ACPA_SET                (1 << 16)
+#define                 AT91_TC_ACPA_CLEAR              (2 << 16)
+#define                 AT91_TC_ACPA_TOGGLE             (3 << 16)
+#define         AT91_TC_ACPC            (3 << 18)       /* Waveform Mode: RC Compre Effect on TIOA */
+#define                 AT91_TC_ACPC_NONE               (0 << 18)
+#define                 AT91_TC_ACPC_SET                (1 << 18)
+#define                 AT91_TC_ACPC_CLEAR              (2 << 18)
+#define                 AT91_TC_ACPC_TOGGLE             (3 << 18)
+#define         AT91_TC_AEEVT           (3 << 20)       /* Waveform Mode: External Event Effect on TIOA */
+#define                 AT91_TC_AEEVT_NONE              (0 << 20)
+#define                 AT91_TC_AEEVT_SET               (1 << 20)
+#define                 AT91_TC_AEEVT_CLEAR             (2 << 20)
+#define                 AT91_TC_AEEVT_TOGGLE            (3 << 20)
+#define         AT91_TC_ASWTRG          (3 << 22)       /* Waveform Mode: Software Trigger Effect on TIOA */
+#define                 AT91_TC_ASWTRG_NONE             (0 << 22)
+#define                 AT91_TC_ASWTRG_SET              (1 << 22)
+#define                 AT91_TC_ASWTRG_CLEAR            (2 << 22)
+#define                 AT91_TC_ASWTRG_TOGGLE           (3 << 22)
+#define         AT91_TC_BCPB            (3 << 24)       /* Waveform Mode: RB Compare Effect on TIOB */
+#define                 AT91_TC_BCPB_NONE               (0 << 24)
+#define                 AT91_TC_BCPB_SET                (1 << 24)
+#define                 AT91_TC_BCPB_CLEAR              (2 << 24)
+#define                 AT91_TC_BCPB_TOGGLE             (3 << 24)
+#define         AT91_TC_BCPC            (3 << 26)       /* Waveform Mode: RC Compare Effect on TIOB */
+#define                 AT91_TC_BCPC_NONE               (0 << 26)
+#define                 AT91_TC_BCPC_SET                (1 << 26)
+#define                 AT91_TC_BCPC_CLEAR              (2 << 26)
+#define                 AT91_TC_BCPC_TOGGLE             (3 << 26)
+#define         AT91_TC_BEEVT           (3 << 28)       /* Waveform Mode: External Event Effect on TIOB */
+#define                 AT91_TC_BEEVT_NONE              (0 << 28)
+#define                 AT91_TC_BEEVT_SET               (1 << 28)
+#define                 AT91_TC_BEEVT_CLEAR             (2 << 28)
+#define                 AT91_TC_BEEVT_TOGGLE            (3 << 28)
+#define         AT91_TC_BSWTRG          (3 << 30)       /* Waveform Mode: Software Trigger Effect on TIOB */
+#define                 AT91_TC_BSWTRG_NONE             (0 << 30)
+#define                 AT91_TC_BSWTRG_SET              (1 << 30)
+#define                 AT91_TC_BSWTRG_CLEAR            (2 << 30)
+#define                 AT91_TC_BSWTRG_TOGGLE           (3 << 30)
+
+#define AT91_TC_CV              0x10            /* Counter Value */
+#define AT91_TC_RA              0x14            /* Register A */
+#define AT91_TC_RB              0x18            /* Register B */
+#define AT91_TC_RC              0x1c            /* Register C */
+
+#define AT91_TC_SR              0x20            /* Status Register */
+#define         AT91_TC_COVFS           (1 <<  0)       /* Counter Overflow Status */
+#define         AT91_TC_LOVRS           (1 <<  1)       /* Load Overrun Status */
+#define         AT91_TC_CPAS            (1 <<  2)       /* RA Compare Status */
+#define         AT91_TC_CPBS            (1 <<  3)       /* RB Compare Status */
+#define         AT91_TC_CPCS            (1 <<  4)       /* RC Compare Status */
+#define         AT91_TC_LDRAS           (1 <<  5)       /* RA Loading Status */
+#define         AT91_TC_LDRBS           (1 <<  6)       /* RB Loading Status */
+#define         AT91_TC_ETRGS           (1 <<  7)       /* External Trigger Status */
+#define         AT91_TC_CLKSTA          (1 << 16)       /* Clock Enabling Status */
+#define         AT91_TC_MTIOA           (1 << 17)       /* TIOA Mirror */
+#define         AT91_TC_MTIOB           (1 << 18)       /* TIOB Mirror */
+
+#define AT91_TC_IER             0x24            /* Interrupt Enable Register */
+#define AT91_TC_IDR             0x28            /* Interrupt Disable Register */
+#define AT91_TC_IMR             0x2c            /* Interrupt Mask Register */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_twi.h b/arch/arm/mach-at91/include/mach/at91_twi.h
new file mode 100644
index 000000000000..bb2880f6ba37
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_twi.h
@@ -0,0 +1,68 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91_twi.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Two-wire Interface (TWI) registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_TWI_H
+#define AT91_TWI_H
+
+#define AT91_TWI_CR             0x00            /* Control Register */
+#define         AT91_TWI_START          (1 <<  0)       /* Send a Start Condition */
+#define         AT91_TWI_STOP           (1 <<  1)       /* Send a Stop Condition */
+#define         AT91_TWI_MSEN           (1 <<  2)       /* Master Transfer Enable */
+#define         AT91_TWI_MSDIS          (1 <<  3)       /* Master Transfer Disable */
+#define         AT91_TWI_SVEN           (1 <<  4)       /* Slave Transfer Enable [SAM9260 only] */
+#define         AT91_TWI_SVDIS          (1 <<  5)       /* Slave Transfer Disable [SAM9260 only] */
+#define         AT91_TWI_SWRST          (1 <<  7)       /* Software Reset */
+
+#define AT91_TWI_MMR            0x04            /* Master Mode Register */
+#define         AT91_TWI_IADRSZ         (3    <<  8)    /* Internal Device Address Size */
+#define                 AT91_TWI_IADRSZ_NO              (0 << 8)
+#define                 AT91_TWI_IADRSZ_1               (1 << 8)
+#define                 AT91_TWI_IADRSZ_2               (2 << 8)
+#define                 AT91_TWI_IADRSZ_3               (3 << 8)
+#define         AT91_TWI_MREAD          (1    << 12)    /* Master Read Direction */
+#define         AT91_TWI_DADR           (0x7f << 16)    /* Device Address */
+
+#define AT91_TWI_SMR            0x08            /* Slave Mode Register [SAM9260 only] */
+#define         AT91_TWI_SADR           (0x7f << 16)    /* Slave Address */
+
+#define AT91_TWI_IADR           0x0c            /* Internal Address Register */
+
+#define AT91_TWI_CWGR           0x10            /* Clock Waveform Generator Register */
+#define         AT91_TWI_CLDIV          (0xff <<  0)    /* Clock Low Divisor */
+#define         AT91_TWI_CHDIV          (0xff <<  8)    /* Clock High Divisor */
+#define         AT91_TWI_CKDIV          (7    << 16)    /* Clock Divider */
+
+#define AT91_TWI_SR             0x20            /* Status Register */
+#define         AT91_TWI_TXCOMP         (1 <<  0)       /* Transmission Complete */
+#define         AT91_TWI_RXRDY          (1 <<  1)       /* Receive Holding Register Ready */
+#define         AT91_TWI_TXRDY          (1 <<  2)       /* Transmit Holding Register Ready */
+#define         AT91_TWI_SVREAD         (1 <<  3)       /* Slave Read [SAM9260 only] */
+#define         AT91_TWI_SVACC          (1 <<  4)       /* Slave Access [SAM9260 only] */
+#define         AT91_TWI_GACC           (1 <<  5)       /* General Call Access [SAM9260 only] */
+#define         AT91_TWI_OVRE           (1 <<  6)       /* Overrun Error [AT91RM9200 only] */
+#define         AT91_TWI_UNRE           (1 <<  7)       /* Underrun Error [AT91RM9200 only] */
+#define         AT91_TWI_NACK           (1 <<  8)       /* Not Acknowledged */
+#define         AT91_TWI_ARBLST         (1 <<  9)       /* Arbitration Lost [SAM9260 only] */
+#define         AT91_TWI_SCLWS          (1 << 10)       /* Clock Wait State [SAM9260 only] */
+#define         AT91_TWI_EOSACC         (1 << 11)       /* End of Slave Address [SAM9260 only] */
+
+#define AT91_TWI_IER            0x24            /* Interrupt Enable Register */
+#define AT91_TWI_IDR            0x28            /* Interrupt Disable Register */
+#define AT91_TWI_IMR            0x2c            /* Interrupt Mask Register */
+#define AT91_TWI_RHR            0x30            /* Receive Holding Register */
+#define AT91_TWI_THR            0x34            /* Transmit Holding Register */
+
+#endif
+
diff --git a/arch/arm/mach-at91/include/mach/at91_wdt.h b/arch/arm/mach-at91/include/mach/at91_wdt.h
new file mode 100644
index 000000000000..973b4526a98e
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_wdt.h
@@ -0,0 +1,34 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91_wdt.h
+ *
+ * Watchdog Timer (WDT) - System peripherals regsters.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_WDT_H
+#define AT91_WDT_H
+
+#define AT91_WDT_CR             (AT91_WDT + 0x00)       /* Watchdog Control Register */
+#define         AT91_WDT_WDRSTT         (1    << 0)             /* Restart */
+#define         AT91_WDT_KEY            (0xa5 << 24)            /* KEY Password */
+
+#define AT91_WDT_MR             (AT91_WDT + 0x04)       /* Watchdog Mode Register */
+#define         AT91_WDT_WDV            (0xfff << 0)            /* Counter Value */
+#define         AT91_WDT_WDFIEN         (1     << 12)           /* Fault Interrupt Enable */
+#define         AT91_WDT_WDRSTEN        (1     << 13)           /* Reset Processor */
+#define         AT91_WDT_WDRPROC        (1     << 14)           /* Timer Restart */
+#define         AT91_WDT_WDDIS          (1     << 15)           /* Watchdog Disable */
+#define         AT91_WDT_WDD            (0xfff << 16)           /* Delta Value */
+#define         AT91_WDT_WDDBGHLT       (1     << 28)           /* Debug Halt */
+#define         AT91_WDT_WDIDLEHLT      (1     << 29)           /* Idle Halt */
+
+#define AT91_WDT_SR             (AT91_WDT + 0x08)       /* Watchdog Status Register */
+#define         AT91_WDT_WDUNF          (1 << 0)                /* Watchdog Underflow */
+#define         AT91_WDT_WDERR          (1 << 1)                /* Watchdog Error */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h
new file mode 100644
index 000000000000..4a4b64135a92
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91cap9.h
@@ -0,0 +1,126 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91cap9.h
+ *
+ *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
+ *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
+ *  Copyright (C) 2007 Atmel Corporation.
+ *
+ * Common definitions.
+ * Based on AT91CAP9 datasheet revision B (Preliminary).
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91CAP9_H
+#define AT91CAP9_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS             1       /* System Peripherals */
+#define AT91CAP9_ID_PIOABCD     2       /* Parallel IO Controller A, B, C and D */
+#define AT91CAP9_ID_MPB0        3       /* MP Block Peripheral 0 */
+#define AT91CAP9_ID_MPB1        4       /* MP Block Peripheral 1 */
+#define AT91CAP9_ID_MPB2        5       /* MP Block Peripheral 2 */
+#define AT91CAP9_ID_MPB3        6       /* MP Block Peripheral 3 */
+#define AT91CAP9_ID_MPB4        7       /* MP Block Peripheral 4 */
+#define AT91CAP9_ID_US0         8       /* USART 0 */
+#define AT91CAP9_ID_US1         9       /* USART 1 */
+#define AT91CAP9_ID_US2         10      /* USART 2 */
+#define AT91CAP9_ID_MCI0        11      /* Multimedia Card Interface 0 */
+#define AT91CAP9_ID_MCI1        12      /* Multimedia Card Interface 1 */
+#define AT91CAP9_ID_CAN         13      /* CAN */
+#define AT91CAP9_ID_TWI         14      /* Two-Wire Interface */
+#define AT91CAP9_ID_SPI0        15      /* Serial Peripheral Interface 0 */
+#define AT91CAP9_ID_SPI1        16      /* Serial Peripheral Interface 0 */
+#define AT91CAP9_ID_SSC0        17      /* Serial Synchronous Controller 0 */
+#define AT91CAP9_ID_SSC1        18      /* Serial Synchronous Controller 1 */
+#define AT91CAP9_ID_AC97C       19      /* AC97 Controller */
+#define AT91CAP9_ID_TCB         20      /* Timer Counter 0, 1 and 2 */
+#define AT91CAP9_ID_PWMC        21      /* Pulse Width Modulation Controller */
+#define AT91CAP9_ID_EMAC        22      /* Ethernet */
+#define AT91CAP9_ID_AESTDES     23      /* Advanced Encryption Standard, Triple DES */
+#define AT91CAP9_ID_ADC         24      /* Analog-to-Digital Converter */
+#define AT91CAP9_ID_ISI         25      /* Image Sensor Interface */
+#define AT91CAP9_ID_LCDC        26      /* LCD Controller */
+#define AT91CAP9_ID_DMA         27      /* DMA Controller */
+#define AT91CAP9_ID_UDPHS       28      /* USB High Speed Device Port */
+#define AT91CAP9_ID_UHP         29      /* USB Host Port */
+#define AT91CAP9_ID_IRQ0        30      /* Advanced Interrupt Controller (IRQ0) */
+#define AT91CAP9_ID_IRQ1        31      /* Advanced Interrupt Controller (IRQ1) */
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT91CAP9_BASE_UDPHS             0xfff78000
+#define AT91CAP9_BASE_TCB0              0xfff7c000
+#define AT91CAP9_BASE_TC0               0xfff7c000
+#define AT91CAP9_BASE_TC1               0xfff7c040
+#define AT91CAP9_BASE_TC2               0xfff7c080
+#define AT91CAP9_BASE_MCI0              0xfff80000
+#define AT91CAP9_BASE_MCI1              0xfff84000
+#define AT91CAP9_BASE_TWI               0xfff88000
+#define AT91CAP9_BASE_US0               0xfff8c000
+#define AT91CAP9_BASE_US1               0xfff90000
+#define AT91CAP9_BASE_US2               0xfff94000
+#define AT91CAP9_BASE_SSC0              0xfff98000
+#define AT91CAP9_BASE_SSC1              0xfff9c000
+#define AT91CAP9_BASE_AC97C             0xfffa0000
+#define AT91CAP9_BASE_SPI0              0xfffa4000
+#define AT91CAP9_BASE_SPI1              0xfffa8000
+#define AT91CAP9_BASE_CAN               0xfffac000
+#define AT91CAP9_BASE_PWMC              0xfffb8000
+#define AT91CAP9_BASE_EMAC              0xfffbc000
+#define AT91CAP9_BASE_ADC               0xfffc0000
+#define AT91CAP9_BASE_ISI               0xfffc4000
+#define AT91_BASE_SYS                   0xffffe200
+
+/*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_ECC        (0xffffe200 - AT91_BASE_SYS)
+#define AT91_BCRAMC     (0xffffe400 - AT91_BASE_SYS)
+#define AT91_DDRSDRC    (0xffffe600 - AT91_BASE_SYS)
+#define AT91_SMC        (0xffffe800 - AT91_BASE_SYS)
+#define AT91_MATRIX     (0xffffea00 - AT91_BASE_SYS)
+#define AT91_CCFG       (0xffffeb10 - AT91_BASE_SYS)
+#define AT91_DMA        (0xffffec00 - AT91_BASE_SYS)
+#define AT91_DBGU       (0xffffee00 - AT91_BASE_SYS)
+#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
+#define AT91_PIOA       (0xfffff200 - AT91_BASE_SYS)
+#define AT91_PIOB       (0xfffff400 - AT91_BASE_SYS)
+#define AT91_PIOC       (0xfffff600 - AT91_BASE_SYS)
+#define AT91_PIOD       (0xfffff800 - AT91_BASE_SYS)
+#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
+#define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
+#define AT91_SHDWC      (0xfffffd10 - AT91_BASE_SYS)
+#define AT91_RTT        (0xfffffd20 - AT91_BASE_SYS)
+#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
+#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_GPBR       (0xfffffd50 - AT91_BASE_SYS)
+
+#define AT91_USART0     AT91CAP9_BASE_US0
+#define AT91_USART1     AT91CAP9_BASE_US1
+#define AT91_USART2     AT91CAP9_BASE_US2
+
+
+/*
+ * Internal Memory.
+ */
+#define AT91CAP9_SRAM_BASE      0x00100000      /* Internal SRAM base address */
+#define AT91CAP9_SRAM_SIZE      (32 * SZ_1K)    /* Internal SRAM size (32Kb) */
+
+#define AT91CAP9_ROM_BASE       0x00400000      /* Internal ROM base address */
+#define AT91CAP9_ROM_SIZE       (32 * SZ_1K)    /* Internal ROM size (32Kb) */
+
+#define AT91CAP9_LCDC_BASE      0x00500000      /* LCD Controller */
+#define AT91CAP9_UDPHS_FIFO     0x00600000      /* USB High Speed Device Port */
+#define AT91CAP9_UHP_BASE       0x00700000      /* USB Host controller */
+
+#define CONFIG_DRAM_BASE        AT91_CHIPSELECT_6
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
new file mode 100644
index 000000000000..bca878f3bd87
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
@@ -0,0 +1,100 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
+ *
+ * DDR/SDR Controller (DDRSDRC) - System peripherals registers.
+ * Based on AT91CAP9 datasheet revision B.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91CAP9_DDRSDR_H
+#define AT91CAP9_DDRSDR_H
+
+#define AT91_DDRSDRC_MR         (AT91_DDRSDRC + 0x00)   /* Mode Register */
+#define         AT91_DDRSDRC_MODE       (0xf << 0)              /* Command Mode */
+#define                 AT91_DDRSDRC_MODE_NORMAL                0
+#define                 AT91_DDRSDRC_MODE_NOP           1
+#define                 AT91_DDRSDRC_MODE_PRECHARGE     2
+#define                 AT91_DDRSDRC_MODE_LMR           3
+#define                 AT91_DDRSDRC_MODE_REFRESH       4
+#define                 AT91_DDRSDRC_MODE_EXT_LMR       5
+#define                 AT91_DDRSDRC_MODE_DEEP          6
+
+#define AT91_DDRSDRC_RTR        (AT91_DDRSDRC + 0x04)   /* Refresh Timer Register */
+#define         AT91_DDRSDRC_COUNT      (0xfff << 0)            /* Refresh Timer Counter */
+
+#define AT91_DDRSDRC_CR         (AT91_DDRSDRC + 0x08)   /* Configuration Register */
+#define         AT91_DDRSDRC_NC         (3 << 0)                /* Number of Column Bits */
+#define                 AT91_DDRSDRC_NC_SDR8    (0 << 0)
+#define                 AT91_DDRSDRC_NC_SDR9    (1 << 0)
+#define                 AT91_DDRSDRC_NC_SDR10   (2 << 0)
+#define                 AT91_DDRSDRC_NC_SDR11   (3 << 0)
+#define                 AT91_DDRSDRC_NC_DDR9    (0 << 0)
+#define                 AT91_DDRSDRC_NC_DDR10   (1 << 0)
+#define                 AT91_DDRSDRC_NC_DDR11   (2 << 0)
+#define                 AT91_DDRSDRC_NC_DDR12   (3 << 0)
+#define         AT91_DDRSDRC_NR         (3 << 2)                /* Number of Row Bits */
+#define                 AT91_DDRSDRC_NR_11      (0 << 2)
+#define                 AT91_DDRSDRC_NR_12      (1 << 2)
+#define                 AT91_DDRSDRC_NR_13      (2 << 2)
+#define         AT91_DDRSDRC_CAS        (7 << 4)                /* CAS Latency */
+#define                 AT91_DDRSDRC_CAS_2      (2 << 4)
+#define                 AT91_DDRSDRC_CAS_3      (3 << 4)
+#define                 AT91_DDRSDRC_CAS_25     (6 << 4)
+#define         AT91_DDRSDRC_DLL        (1 << 7)                /* Reset DLL */
+#define         AT91_DDRSDRC_DICDS      (1 << 8)                /* Output impedance control */
+
+#define AT91_DDRSDRC_T0PR       (AT91_DDRSDRC + 0x0C)   /* Timing 0 Register */
+#define         AT91_DDRSDRC_TRAS       (0xf <<  0)             /* Active to Precharge delay */
+#define         AT91_DDRSDRC_TRCD       (0xf <<  4)             /* Row to Column delay */
+#define         AT91_DDRSDRC_TWR        (0xf <<  8)             /* Write recovery delay */
+#define         AT91_DDRSDRC_TRC        (0xf << 12)             /* Row cycle delay */
+#define         AT91_DDRSDRC_TRP        (0xf << 16)             /* Row precharge delay */
+#define         AT91_DDRSDRC_TRRD       (0xf << 20)             /* Active BankA to BankB */
+#define         AT91_DDRSDRC_TWTR       (1   << 24)             /* Internal Write to Read delay */
+#define         AT91_DDRSDRC_TMRD       (0xf << 28)             /* Load mode to active/refresh delay */
+
+#define AT91_DDRSDRC_T1PR       (AT91_DDRSDRC + 0x10)   /* Timing 1 Register */
+#define         AT91_DDRSDRC_TRFC       (0x1f << 0)             /* Row Cycle Delay */
+#define         AT91_DDRSDRC_TXSNR      (0xff << 8)             /* Exit self-refresh to non-read */
+#define         AT91_DDRSDRC_TXSRD      (0xff << 16)            /* Exit self-refresh to read */
+#define         AT91_DDRSDRC_TXP        (0xf  << 24)            /* Exit power-down delay */
+
+#define AT91_DDRSDRC_LPR        (AT91_DDRSDRC + 0x18)   /* Low Power Register */
+#define         AT91_DDRSDRC_LPCB               (3 << 0)        /* Low-power Configurations */
+#define                 AT91_DDRSDRC_LPCB_DISABLE               0
+#define                 AT91_DDRSDRC_LPCB_SELF_REFRESH          1
+#define                 AT91_DDRSDRC_LPCB_POWER_DOWN            2
+#define                 AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN       3
+#define         AT91_DDRSDRC_CLKFR              (1 << 2)        /* Clock Frozen */
+#define         AT91_DDRSDRC_PASR               (7 << 4)        /* Partial Array Self Refresh */
+#define         AT91_DDRSDRC_TCSR               (3 << 8)        /* Temperature Compensated Self Refresh */
+#define         AT91_DDRSDRC_DS                 (3 << 10)       /* Drive Strength */
+#define         AT91_DDRSDRC_TIMEOUT            (3 << 12)       /* Time to define when Low Power Mode is enabled */
+#define                 AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES       (0 << 12)
+#define                 AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES      (1 << 12)
+#define                 AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES     (2 << 12)
+
+#define AT91_DDRSDRC_MDR        (AT91_DDRSDRC + 0x1C)   /* Memory Device Register */
+#define         AT91_DDRSDRC_MD         (3 << 0)                /* Memory Device Type */
+#define                 AT91_DDRSDRC_MD_SDR             0
+#define                 AT91_DDRSDRC_MD_LOW_POWER_SDR   1
+#define                 AT91_DDRSDRC_MD_DDR             2
+#define                 AT91_DDRSDRC_MD_LOW_POWER_DDR   3
+
+#define AT91_DDRSDRC_DLLR       (AT91_DDRSDRC + 0x20)   /* DLL Information Register */
+#define         AT91_DDRSDRC_MDINC      (1 << 0)                /* Master Delay increment */
+#define         AT91_DDRSDRC_MDDEC      (1 << 1)                /* Master Delay decrement */
+#define         AT91_DDRSDRC_MDOVF      (1 << 2)                /* Master Delay Overflow */
+#define         AT91_DDRSDRC_SDCOVF     (1 << 3)                /* Slave Delay Correction Overflow */
+#define         AT91_DDRSDRC_SDCUDF     (1 << 4)                /* Slave Delay Correction Underflow */
+#define         AT91_DDRSDRC_SDERF      (1 << 5)                /* Slave Delay Correction error */
+#define         AT91_DDRSDRC_MDVAL      (0xff <<  8)            /* Master Delay value */
+#define         AT91_DDRSDRC_SDVAL      (0xff << 16)            /* Slave Delay value */
+#define         AT91_DDRSDRC_SDCVAL     (0xff << 24)            /* Slave Delay Correction value */
+
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91cap9_matrix.h b/arch/arm/mach-at91/include/mach/at91cap9_matrix.h
new file mode 100644
index 000000000000..4b9d4aff4b4f
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91cap9_matrix.h
@@ -0,0 +1,137 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91cap9_matrix.h
+ *
+ *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
+ *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
+ *  Copyright (C) 2006 Atmel Corporation.
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91CAP9 datasheet revision B (Preliminary).
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91CAP9_MATRIX_H
+#define AT91CAP9_MATRIX_H
+
+#define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
+#define AT91_MATRIX_MCFG6       (AT91_MATRIX + 0x18)    /* Master Configuration Register 6 */
+#define AT91_MATRIX_MCFG7       (AT91_MATRIX + 0x1C)    /* Master Configuration Register 7 */
+#define AT91_MATRIX_MCFG8       (AT91_MATRIX + 0x20)    /* Master Configuration Register 8 */
+#define AT91_MATRIX_MCFG9       (AT91_MATRIX + 0x24)    /* Master Configuration Register 9 */
+#define AT91_MATRIX_MCFG10      (AT91_MATRIX + 0x28)    /* Master Configuration Register 10 */
+#define AT91_MATRIX_MCFG11      (AT91_MATRIX + 0x2C)    /* Master Configuration Register 11 */
+#define         AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
+#define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
+#define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
+#define                 AT91_MATRIX_ULBT_FOUR           (2 << 0)
+#define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
+#define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
+
+#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
+#define AT91_MATRIX_SCFG5       (AT91_MATRIX + 0x54)    /* Slave Configuration Register 5 */
+#define AT91_MATRIX_SCFG6       (AT91_MATRIX + 0x58)    /* Slave Configuration Register 6 */
+#define AT91_MATRIX_SCFG7       (AT91_MATRIX + 0x5C)    /* Slave Configuration Register 7 */
+#define AT91_MATRIX_SCFG8       (AT91_MATRIX + 0x60)    /* Slave Configuration Register 8 */
+#define AT91_MATRIX_SCFG9       (AT91_MATRIX + 0x64)    /* Slave Configuration Register 9 */
+#define         AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
+#define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
+#define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
+#define         AT91_MATRIX_FIXED_DEFMSTR       (0xf  << 18)    /* Fixed Index of Default Master */
+#define         AT91_MATRIX_ARBT                (3    << 24)    /* Arbitration Type */
+#define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
+#define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
+
+#define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRBS0       (AT91_MATRIX + 0x84)    /* Priority Register B for Slave 0 */
+#define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRBS1       (AT91_MATRIX + 0x8C)    /* Priority Register B for Slave 1 */
+#define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRBS2       (AT91_MATRIX + 0x94)    /* Priority Register B for Slave 2 */
+#define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRBS3       (AT91_MATRIX + 0x9C)    /* Priority Register B for Slave 3 */
+#define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
+#define AT91_MATRIX_PRBS4       (AT91_MATRIX + 0xA4)    /* Priority Register B for Slave 4 */
+#define AT91_MATRIX_PRAS5       (AT91_MATRIX + 0xA8)    /* Priority Register A for Slave 5 */
+#define AT91_MATRIX_PRBS5       (AT91_MATRIX + 0xAC)    /* Priority Register B for Slave 5 */
+#define AT91_MATRIX_PRAS6       (AT91_MATRIX + 0xB0)    /* Priority Register A for Slave 6 */
+#define AT91_MATRIX_PRBS6       (AT91_MATRIX + 0xB4)    /* Priority Register B for Slave 6 */
+#define AT91_MATRIX_PRAS7       (AT91_MATRIX + 0xB8)    /* Priority Register A for Slave 7 */
+#define AT91_MATRIX_PRBS7       (AT91_MATRIX + 0xBC)    /* Priority Register B for Slave 7 */
+#define AT91_MATRIX_PRAS8       (AT91_MATRIX + 0xC0)    /* Priority Register A for Slave 8 */
+#define AT91_MATRIX_PRBS8       (AT91_MATRIX + 0xC4)    /* Priority Register B for Slave 8 */
+#define AT91_MATRIX_PRAS9       (AT91_MATRIX + 0xC8)    /* Priority Register A for Slave 9 */
+#define AT91_MATRIX_PRBS9       (AT91_MATRIX + 0xCC)    /* Priority Register B for Slave 9 */
+#define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
+#define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
+#define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
+#define         AT91_MATRIX_M3PR                (3 << 12)       /* Master 3 Priority */
+#define         AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
+#define         AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
+#define         AT91_MATRIX_M6PR                (3 << 24)       /* Master 6 Priority */
+#define         AT91_MATRIX_M7PR                (3 << 28)       /* Master 7 Priority */
+#define         AT91_MATRIX_M8PR                (3 << 0)        /* Master 8 Priority (in Register B) */
+#define         AT91_MATRIX_M9PR                (3 << 4)        /* Master 9 Priority (in Register B) */
+#define         AT91_MATRIX_M10PR               (3 << 8)        /* Master 10 Priority (in Register B) */
+#define         AT91_MATRIX_M11PR               (3 << 12)       /* Master 11 Priority (in Register B) */
+
+#define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
+#define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define         AT91_MATRIX_RCB2                (1 << 2)
+#define         AT91_MATRIX_RCB3                (1 << 3)
+#define         AT91_MATRIX_RCB4                (1 << 4)
+#define         AT91_MATRIX_RCB5                (1 << 5)
+#define         AT91_MATRIX_RCB6                (1 << 6)
+#define         AT91_MATRIX_RCB7                (1 << 7)
+#define         AT91_MATRIX_RCB8                (1 << 8)
+#define         AT91_MATRIX_RCB9                (1 << 9)
+#define         AT91_MATRIX_RCB10               (1 << 10)
+#define         AT91_MATRIX_RCB11               (1 << 11)
+
+#define AT91_MPBS0_SFR          (AT91_MATRIX + 0x114)   /* MPBlock Slave 0 Special Function Register */
+#define AT91_MPBS1_SFR          (AT91_MATRIX + 0x11C)   /* MPBlock Slave 1 Special Function Register */
+
+#define AT91_MATRIX_UDPHS       (AT91_MATRIX + 0x118)   /* USBHS Special Function Register [AT91CAP9 only] */
+#define         AT91_MATRIX_SELECT_UDPHS        (0 << 31)       /* select High Speed UDP */
+#define         AT91_MATRIX_SELECT_UDP          (1 << 31)       /* select standard UDP */
+#define         AT91_MATRIX_UDPHS_BYPASS_LOCK   (1 << 30)       /* bypass lock bit */
+
+#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x120)   /* EBI Chip Select Assignment Register */
+#define         AT91_MATRIX_EBI_CS1A            (1 << 1)        /* Chip Select 1 Assignment */
+#define                 AT91_MATRIX_EBI_CS1A_SMC                (0 << 1)
+#define                 AT91_MATRIX_EBI_CS1A_BCRAMC             (1 << 1)
+#define         AT91_MATRIX_EBI_CS3A            (1 << 3)        /* Chip Select 3 Assignment */
+#define                 AT91_MATRIX_EBI_CS3A_SMC                (0 << 3)
+#define                 AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA     (1 << 3)
+#define         AT91_MATRIX_EBI_CS4A            (1 << 4)        /* Chip Select 4 Assignment */
+#define                 AT91_MATRIX_EBI_CS4A_SMC                (0 << 4)
+#define                 AT91_MATRIX_EBI_CS4A_SMC_CF1            (1 << 4)
+#define         AT91_MATRIX_EBI_CS5A            (1 << 5)        /* Chip Select 5 Assignment */
+#define                 AT91_MATRIX_EBI_CS5A_SMC                (0 << 5)
+#define                 AT91_MATRIX_EBI_CS5A_SMC_CF2            (1 << 5)
+#define         AT91_MATRIX_EBI_DBPUC           (1 << 8)        /* Data Bus Pull-up Configuration */
+#define         AT91_MATRIX_EBI_DQSPDC          (1 << 9)        /* Data Qualifier Strobe Pull-Down Configuration */
+#define         AT91_MATRIX_EBI_VDDIOMSEL       (1 << 16)       /* Memory voltage selection */
+#define                 AT91_MATRIX_EBI_VDDIOMSEL_1_8V          (0 << 16)
+#define                 AT91_MATRIX_EBI_VDDIOMSEL_3_3V          (1 << 16)
+
+#define AT91_MPBS2_SFR          (AT91_MATRIX + 0x12C)   /* MPBlock Slave 2 Special Function Register */
+#define AT91_MPBS3_SFR          (AT91_MATRIX + 0x130)   /* MPBlock Slave 3 Special Function Register */
+#define AT91_APB_SFR            (AT91_MATRIX + 0x134)   /* APB Bridge Special Function Register */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h
new file mode 100644
index 000000000000..78983155a074
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91rm9200.h
@@ -0,0 +1,115 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91rm9200.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Common definitions.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91RM9200_H
+#define AT91RM9200_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS             1       /* System Peripheral */
+#define AT91RM9200_ID_PIOA      2       /* Parallel IO Controller A */
+#define AT91RM9200_ID_PIOB      3       /* Parallel IO Controller B */
+#define AT91RM9200_ID_PIOC      4       /* Parallel IO Controller C */
+#define AT91RM9200_ID_PIOD      5       /* Parallel IO Controller D */
+#define AT91RM9200_ID_US0       6       /* USART 0 */
+#define AT91RM9200_ID_US1       7       /* USART 1 */
+#define AT91RM9200_ID_US2       8       /* USART 2 */
+#define AT91RM9200_ID_US3       9       /* USART 3 */
+#define AT91RM9200_ID_MCI       10      /* Multimedia Card Interface */
+#define AT91RM9200_ID_UDP       11      /* USB Device Port */
+#define AT91RM9200_ID_TWI       12      /* Two-Wire Interface */
+#define AT91RM9200_ID_SPI       13      /* Serial Peripheral Interface */
+#define AT91RM9200_ID_SSC0      14      /* Serial Synchronous Controller 0 */
+#define AT91RM9200_ID_SSC1      15      /* Serial Synchronous Controller 1 */
+#define AT91RM9200_ID_SSC2      16      /* Serial Synchronous Controller 2 */
+#define AT91RM9200_ID_TC0       17      /* Timer Counter 0 */
+#define AT91RM9200_ID_TC1       18      /* Timer Counter 1 */
+#define AT91RM9200_ID_TC2       19      /* Timer Counter 2 */
+#define AT91RM9200_ID_TC3       20      /* Timer Counter 3 */
+#define AT91RM9200_ID_TC4       21      /* Timer Counter 4 */
+#define AT91RM9200_ID_TC5       22      /* Timer Counter 5 */
+#define AT91RM9200_ID_UHP       23      /* USB Host port */
+#define AT91RM9200_ID_EMAC      24      /* Ethernet MAC */
+#define AT91RM9200_ID_IRQ0      25      /* Advanced Interrupt Controller (IRQ0) */
+#define AT91RM9200_ID_IRQ1      26      /* Advanced Interrupt Controller (IRQ1) */
+#define AT91RM9200_ID_IRQ2      27      /* Advanced Interrupt Controller (IRQ2) */
+#define AT91RM9200_ID_IRQ3      28      /* Advanced Interrupt Controller (IRQ3) */
+#define AT91RM9200_ID_IRQ4      29      /* Advanced Interrupt Controller (IRQ4) */
+#define AT91RM9200_ID_IRQ5      30      /* Advanced Interrupt Controller (IRQ5) */
+#define AT91RM9200_ID_IRQ6      31      /* Advanced Interrupt Controller (IRQ6) */
+
+
+/*
+ * Peripheral physical base addresses.
+ */
+#define AT91RM9200_BASE_TCB0    0xfffa0000
+#define AT91RM9200_BASE_TC0     0xfffa0000
+#define AT91RM9200_BASE_TC1     0xfffa0040
+#define AT91RM9200_BASE_TC2     0xfffa0080
+#define AT91RM9200_BASE_TCB1    0xfffa4000
+#define AT91RM9200_BASE_TC3     0xfffa4000
+#define AT91RM9200_BASE_TC4     0xfffa4040
+#define AT91RM9200_BASE_TC5     0xfffa4080
+#define AT91RM9200_BASE_UDP     0xfffb0000
+#define AT91RM9200_BASE_MCI     0xfffb4000
+#define AT91RM9200_BASE_TWI     0xfffb8000
+#define AT91RM9200_BASE_EMAC    0xfffbc000
+#define AT91RM9200_BASE_US0     0xfffc0000
+#define AT91RM9200_BASE_US1     0xfffc4000
+#define AT91RM9200_BASE_US2     0xfffc8000
+#define AT91RM9200_BASE_US3     0xfffcc000
+#define AT91RM9200_BASE_SSC0    0xfffd0000
+#define AT91RM9200_BASE_SSC1    0xfffd4000
+#define AT91RM9200_BASE_SSC2    0xfffd8000
+#define AT91RM9200_BASE_SPI     0xfffe0000
+#define AT91_BASE_SYS           0xfffff000
+
+
+/*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)    /* Advanced Interrupt Controller */
+#define AT91_DBGU       (0xfffff200 - AT91_BASE_SYS)    /* Debug Unit */
+#define AT91_PIOA       (0xfffff400 - AT91_BASE_SYS)    /* PIO Controller A */
+#define AT91_PIOB       (0xfffff600 - AT91_BASE_SYS)    /* PIO Controller B */
+#define AT91_PIOC       (0xfffff800 - AT91_BASE_SYS)    /* PIO Controller C */
+#define AT91_PIOD       (0xfffffa00 - AT91_BASE_SYS)    /* PIO Controller D */
+#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)    /* Power Management Controller */
+#define AT91_ST         (0xfffffd00 - AT91_BASE_SYS)    /* System Timer */
+#define AT91_RTC        (0xfffffe00 - AT91_BASE_SYS)    /* Real-Time Clock */
+#define AT91_MC         (0xffffff00 - AT91_BASE_SYS)    /* Memory Controllers */
+
+#define AT91_USART0     AT91RM9200_BASE_US0
+#define AT91_USART1     AT91RM9200_BASE_US1
+#define AT91_USART2     AT91RM9200_BASE_US2
+#define AT91_USART3     AT91RM9200_BASE_US3
+
+#define AT91_MATRIX     0       /* not supported */
+
+/*
+ * Internal Memory.
+ */
+#define AT91RM9200_ROM_BASE     0x00100000      /* Internal ROM base address */
+#define AT91RM9200_ROM_SIZE     SZ_128K         /* Internal ROM size (128Kb) */
+
+#define AT91RM9200_SRAM_BASE    0x00200000      /* Internal SRAM base address */
+#define AT91RM9200_SRAM_SIZE    SZ_16K          /* Internal SRAM size (16Kb) */
+
+#define AT91RM9200_UHP_BASE     0x00300000      /* USB Host controller */
+
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_emac.h b/arch/arm/mach-at91/include/mach/at91rm9200_emac.h
new file mode 100644
index 000000000000..b8260cd8041c
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91rm9200_emac.h
@@ -0,0 +1,138 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91rm9200_emac.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Ethernet MAC registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91RM9200_EMAC_H
+#define AT91RM9200_EMAC_H
+
+#define AT91_EMAC_CTL           0x00    /* Control Register */
+#define         AT91_EMAC_LB            (1 <<  0)       /* Loopback */
+#define         AT91_EMAC_LBL           (1 <<  1)       /* Loopback Local */
+#define         AT91_EMAC_RE            (1 <<  2)       /* Receive Enable */
+#define         AT91_EMAC_TE            (1 <<  3)       /* Transmit Enable */
+#define         AT91_EMAC_MPE           (1 <<  4)       /* Management Port Enable */
+#define         AT91_EMAC_CSR           (1 <<  5)       /* Clear Statistics Registers */
+#define         AT91_EMAC_INCSTAT       (1 <<  6)       /* Increment Statistics Registers */
+#define         AT91_EMAC_WES           (1 <<  7)       /* Write Enable for Statistics Registers */
+#define         AT91_EMAC_BP            (1 <<  8)       /* Back Pressure */
+
+#define AT91_EMAC_CFG           0x04    /* Configuration Register */
+#define         AT91_EMAC_SPD           (1 <<  0)       /* Speed */
+#define         AT91_EMAC_FD            (1 <<  1)       /* Full Duplex */
+#define         AT91_EMAC_BR            (1 <<  2)       /* Bit Rate */
+#define         AT91_EMAC_CAF           (1 <<  4)       /* Copy All Frames */
+#define         AT91_EMAC_NBC           (1 <<  5)       /* No Broadcast */
+#define         AT91_EMAC_MTI           (1 <<  6)       /* Multicast Hash Enable */
+#define         AT91_EMAC_UNI           (1 <<  7)       /* Unicast Hash Enable */
+#define         AT91_EMAC_BIG           (1 <<  8)       /* Receive 1522 Bytes */
+#define         AT91_EMAC_EAE           (1 <<  9)       /* External Address Match Enable */
+#define         AT91_EMAC_CLK           (3 << 10)       /* MDC Clock Divisor */
+#define         AT91_EMAC_CLK_DIV8              (0 << 10)
+#define         AT91_EMAC_CLK_DIV16             (1 << 10)
+#define         AT91_EMAC_CLK_DIV32             (2 << 10)
+#define         AT91_EMAC_CLK_DIV64             (3 << 10)
+#define         AT91_EMAC_RTY           (1 << 12)       /* Retry Test */
+#define         AT91_EMAC_RMII          (1 << 13)       /* Reduce MII (RMII) */
+
+#define AT91_EMAC_SR            0x08    /* Status Register */
+#define         AT91_EMAC_SR_LINK       (1 <<  0)       /* Link */
+#define         AT91_EMAC_SR_MDIO       (1 <<  1)       /* MDIO pin */
+#define         AT91_EMAC_SR_IDLE       (1 <<  2)       /* PHY idle */
+
+#define AT91_EMAC_TAR           0x0c    /* Transmit Address Register */
+
+#define AT91_EMAC_TCR           0x10    /* Transmit Control Register */
+#define         AT91_EMAC_LEN           (0x7ff << 0)    /* Transmit Frame Length */
+#define         AT91_EMAC_NCRC          (1     << 15)   /* No CRC */
+
+#define AT91_EMAC_TSR           0x14    /* Transmit Status Register */
+#define         AT91_EMAC_TSR_OVR       (1 <<  0)       /* Transmit Buffer Overrun */
+#define         AT91_EMAC_TSR_COL       (1 <<  1)       /* Collision Occurred */
+#define         AT91_EMAC_TSR_RLE       (1 <<  2)       /* Retry Limit Exceeded */
+#define         AT91_EMAC_TSR_IDLE      (1 <<  3)       /* Transmitter Idle */
+#define         AT91_EMAC_TSR_BNQ       (1 <<  4)       /* Transmit Buffer not Queued */
+#define         AT91_EMAC_TSR_COMP      (1 <<  5)       /* Transmit Complete */
+#define         AT91_EMAC_TSR_UND       (1 <<  6)       /* Transmit Underrun */
+
+#define AT91_EMAC_RBQP          0x18    /* Receive Buffer Queue Pointer */
+
+#define AT91_EMAC_RSR           0x20    /* Receive Status Register */
+#define         AT91_EMAC_RSR_BNA       (1 <<  0)       /* Buffer Not Available */
+#define         AT91_EMAC_RSR_REC       (1 <<  1)       /* Frame Received */
+#define         AT91_EMAC_RSR_OVR       (1 <<  2)       /* RX Overrun */
+
+#define AT91_EMAC_ISR           0x24    /* Interrupt Status Register */
+#define         AT91_EMAC_DONE          (1 <<  0)       /* Management Done */
+#define         AT91_EMAC_RCOM          (1 <<  1)       /* Receive Complete */
+#define         AT91_EMAC_RBNA          (1 <<  2)       /* Receive Buffer Not Available */
+#define         AT91_EMAC_TOVR          (1 <<  3)       /* Transmit Buffer Overrun */
+#define         AT91_EMAC_TUND          (1 <<  4)       /* Transmit Buffer Underrun */
+#define         AT91_EMAC_RTRY          (1 <<  5)       /* Retry Limit */
+#define         AT91_EMAC_TBRE          (1 <<  6)       /* Transmit Buffer Register Empty */
+#define         AT91_EMAC_TCOM          (1 <<  7)       /* Transmit Complete */
+#define         AT91_EMAC_TIDLE         (1 <<  8)       /* Transmit Idle */
+#define         AT91_EMAC_LINK          (1 <<  9)       /* Link */
+#define         AT91_EMAC_ROVR          (1 << 10)       /* RX Overrun */
+#define         AT91_EMAC_ABT           (1 << 11)       /* Abort */
+
+#define AT91_EMAC_IER           0x28    /* Interrupt Enable Register */
+#define AT91_EMAC_IDR           0x2c    /* Interrupt Disable Register */
+#define AT91_EMAC_IMR           0x30    /* Interrupt Mask Register */
+
+#define AT91_EMAC_MAN           0x34    /* PHY Maintenance Register */
+#define         AT91_EMAC_DATA          (0xffff << 0)   /* MDIO Data */
+#define         AT91_EMAC_REGA          (0x1f   << 18)  /* MDIO Register */
+#define         AT91_EMAC_PHYA          (0x1f   << 23)  /* MDIO PHY Address */
+#define         AT91_EMAC_RW            (3      << 28)  /* Read/Write operation */
+#define                 AT91_EMAC_RW_W          (1 << 28)
+#define                 AT91_EMAC_RW_R          (2 << 28)
+#define         AT91_EMAC_MAN_802_3     0x40020000      /* IEEE 802.3 value */
+
+/*
+ * Statistics Registers.
+ */
+#define AT91_EMAC_FRA           0x40    /* Frames Transmitted OK */
+#define AT91_EMAC_SCOL          0x44    /* Single Collision Frame */
+#define AT91_EMAC_MCOL          0x48    /* Multiple Collision Frame */
+#define AT91_EMAC_OK            0x4c    /* Frames Received OK */
+#define AT91_EMAC_SEQE          0x50    /* Frame Check Sequence Error */
+#define AT91_EMAC_ALE           0x54    /* Alignmemt Error */
+#define AT91_EMAC_DTE           0x58    /* Deffered Transmission Frame */
+#define AT91_EMAC_LCOL          0x5c    /* Late Collision */
+#define AT91_EMAC_ECOL          0x60    /* Excessive Collision */
+#define AT91_EMAC_TUE           0x64    /* Transmit Underrun Error */
+#define AT91_EMAC_CSE           0x68    /* Carrier Sense Error */
+#define AT91_EMAC_DRFC          0x6c    /* Discard RX Frame */
+#define AT91_EMAC_ROV           0x70    /* Receive Overrun */
+#define AT91_EMAC_CDE           0x74    /* Code Error */
+#define AT91_EMAC_ELR           0x78    /* Excessive Length Error */
+#define AT91_EMAC_RJB           0x7c    /* Receive Jabber */
+#define AT91_EMAC_USF           0x80    /* Undersize Frame */
+#define AT91_EMAC_SQEE          0x84    /* SQE Test Error */
+
+/*
+ * Address Registers.
+ */
+#define AT91_EMAC_HSL           0x90    /* Hash Address Low [31:0] */
+#define AT91_EMAC_HSH           0x94    /* Hash Address High [63:32] */
+#define AT91_EMAC_SA1L          0x98    /* Specific Address 1 Low, bytes 0-3 */
+#define AT91_EMAC_SA1H          0x9c    /* Specific Address 1 High, bytes 4-5 */
+#define AT91_EMAC_SA2L          0xa0    /* Specific Address 2 Low, bytes 0-3 */
+#define AT91_EMAC_SA2H          0xa4    /* Specific Address 2 High, bytes 4-5 */
+#define AT91_EMAC_SA3L          0xa8    /* Specific Address 3 Low, bytes 0-3 */
+#define AT91_EMAC_SA3H          0xac    /* Specific Address 3 High, bytes 4-5 */
+#define AT91_EMAC_SA4L          0xb0    /* Specific Address 4 Low, bytes 0-3 */
+#define AT91_EMAC_SA4H          0xb4    /* Specific Address 4 High, bytes 4-5 */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
new file mode 100644
index 000000000000..d34e4ed89349
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
@@ -0,0 +1,160 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91rm9200_mc.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91RM9200_MC_H
+#define AT91RM9200_MC_H
+
+/* Memory Controller */
+#define AT91_MC_RCR             (AT91_MC + 0x00)        /* MC Remap Control Register */
+#define         AT91_MC_RCB             (1 <<  0)               /* Remap Command Bit */
+
+#define AT91_MC_ASR             (AT91_MC + 0x04)        /* MC Abort Status Register */
+#define         AT91_MC_UNADD           (1 <<  0)               /* Undefined Address Abort Status */
+#define         AT91_MC_MISADD          (1 <<  1)               /* Misaligned Address Abort Status */
+#define         AT91_MC_ABTSZ           (3 <<  8)               /* Abort Size Status */
+#define                 AT91_MC_ABTSZ_BYTE              (0 << 8)
+#define                 AT91_MC_ABTSZ_HALFWORD          (1 << 8)
+#define                 AT91_MC_ABTSZ_WORD              (2 << 8)
+#define         AT91_MC_ABTTYP          (3 << 10)               /* Abort Type Status */
+#define                 AT91_MC_ABTTYP_DATAREAD         (0 << 10)
+#define                 AT91_MC_ABTTYP_DATAWRITE        (1 << 10)
+#define                 AT91_MC_ABTTYP_FETCH            (2 << 10)
+#define         AT91_MC_MST0            (1 << 16)               /* ARM920T Abort Source */
+#define         AT91_MC_MST1            (1 << 17)               /* PDC Abort Source */
+#define         AT91_MC_MST2            (1 << 18)               /* UHP Abort Source */
+#define         AT91_MC_MST3            (1 << 19)               /* EMAC Abort Source */
+#define         AT91_MC_SVMST0          (1 << 24)               /* Saved ARM920T Abort Source */
+#define         AT91_MC_SVMST1          (1 << 25)               /* Saved PDC Abort Source */
+#define         AT91_MC_SVMST2          (1 << 26)               /* Saved UHP Abort Source */
+#define         AT91_MC_SVMST3          (1 << 27)               /* Saved EMAC Abort Source */
+
+#define AT91_MC_AASR            (AT91_MC + 0x08)        /* MC Abort Address Status Register */
+
+#define AT91_MC_MPR             (AT91_MC + 0x0c)        /* MC Master Priority Register */
+#define         AT91_MPR_MSTP0          (7 <<  0)               /* ARM920T Priority */
+#define         AT91_MPR_MSTP1          (7 <<  4)               /* PDC Priority */
+#define         AT91_MPR_MSTP2          (7 <<  8)               /* UHP Priority */
+#define         AT91_MPR_MSTP3          (7 << 12)               /* EMAC Priority */
+
+/* External Bus Interface (EBI) registers */
+#define AT91_EBI_CSA            (AT91_MC + 0x60)        /* Chip Select Assignment Register */
+#define         AT91_EBI_CS0A           (1 << 0)                /* Chip Select 0 Assignment */
+#define                 AT91_EBI_CS0A_SMC               (0 << 0)
+#define                 AT91_EBI_CS0A_BFC               (1 << 0)
+#define         AT91_EBI_CS1A           (1 << 1)                /* Chip Select 1 Assignment */
+#define                 AT91_EBI_CS1A_SMC               (0 << 1)
+#define                 AT91_EBI_CS1A_SDRAMC            (1 << 1)
+#define         AT91_EBI_CS3A           (1 << 3)                /* Chip Select 2 Assignment */
+#define                 AT91_EBI_CS3A_SMC               (0 << 3)
+#define                 AT91_EBI_CS3A_SMC_SMARTMEDIA    (1 << 3)
+#define         AT91_EBI_CS4A           (1 << 4)                /* Chip Select 3 Assignment */
+#define                 AT91_EBI_CS4A_SMC               (0 << 4)
+#define                 AT91_EBI_CS4A_SMC_COMPACTFLASH  (1 << 4)
+#define AT91_EBI_CFGR           (AT91_MC + 0x64)        /* Configuration Register */
+#define         AT91_EBI_DBPUC          (1 << 0)                /* Data Bus Pull-Up Configuration */
+
+/* Static Memory Controller (SMC) registers */
+#define AT91_SMC_CSR(n)         (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
+#define         AT91_SMC_NWS            (0x7f <<  0)            /* Number of Wait States */
+#define                 AT91_SMC_NWS_(x)        ((x) << 0)
+#define         AT91_SMC_WSEN           (1    <<  7)            /* Wait State Enable */
+#define         AT91_SMC_TDF            (0xf  <<  8)            /* Data Float Time */
+#define                 AT91_SMC_TDF_(x)        ((x) << 8)
+#define         AT91_SMC_BAT            (1    << 12)            /* Byte Access Type */
+#define         AT91_SMC_DBW            (3    << 13)            /* Data Bus Width */
+#define                 AT91_SMC_DBW_16         (1 << 13)
+#define                 AT91_SMC_DBW_8          (2 << 13)
+#define         AT91_SMC_DPR            (1 << 15)               /* Data Read Protocol */
+#define         AT91_SMC_ACSS           (3 << 16)               /* Address to Chip Select Setup */
+#define                 AT91_SMC_ACSS_STD       (0 << 16)
+#define                 AT91_SMC_ACSS_1         (1 << 16)
+#define                 AT91_SMC_ACSS_2         (2 << 16)
+#define                 AT91_SMC_ACSS_3         (3 << 16)
+#define         AT91_SMC_RWSETUP        (7 << 24)               /* Read & Write Signal Time Setup */
+#define                 AT91_SMC_RWSETUP_(x)    ((x) << 24)
+#define         AT91_SMC_RWHOLD         (7 << 28)               /* Read & Write Signal Hold Time */
+#define                 AT91_SMC_RWHOLD_(x)     ((x) << 28)
+
+/* SDRAM Controller registers */
+#define AT91_SDRAMC_MR          (AT91_MC + 0x90)        /* Mode Register */
+#define         AT91_SDRAMC_MODE        (0xf << 0)              /* Command Mode */
+#define                 AT91_SDRAMC_MODE_NORMAL         (0 << 0)
+#define                 AT91_SDRAMC_MODE_NOP            (1 << 0)
+#define                 AT91_SDRAMC_MODE_PRECHARGE      (2 << 0)
+#define                 AT91_SDRAMC_MODE_LMR            (3 << 0)
+#define                 AT91_SDRAMC_MODE_REFRESH        (4 << 0)
+#define         AT91_SDRAMC_DBW         (1   << 4)              /* Data Bus Width */
+#define                 AT91_SDRAMC_DBW_32      (0 << 4)
+#define                 AT91_SDRAMC_DBW_16      (1 << 4)
+
+#define AT91_SDRAMC_TR          (AT91_MC + 0x94)        /* Refresh Timer Register */
+#define         AT91_SDRAMC_COUNT       (0xfff << 0)            /* Refresh Timer Count */
+
+#define AT91_SDRAMC_CR          (AT91_MC + 0x98)        /* Configuration Register */
+#define         AT91_SDRAMC_NC          (3   <<  0)             /* Number of Column Bits */
+#define                 AT91_SDRAMC_NC_8        (0 << 0)
+#define                 AT91_SDRAMC_NC_9        (1 << 0)
+#define                 AT91_SDRAMC_NC_10       (2 << 0)
+#define                 AT91_SDRAMC_NC_11       (3 << 0)
+#define         AT91_SDRAMC_NR          (3   <<  2)             /* Number of Row Bits */
+#define                 AT91_SDRAMC_NR_11       (0 << 2)
+#define                 AT91_SDRAMC_NR_12       (1 << 2)
+#define                 AT91_SDRAMC_NR_13       (2 << 2)
+#define         AT91_SDRAMC_NB          (1   <<  4)             /* Number of Banks */
+#define                 AT91_SDRAMC_NB_2        (0 << 4)
+#define                 AT91_SDRAMC_NB_4        (1 << 4)
+#define         AT91_SDRAMC_CAS         (3   <<  5)             /* CAS Latency */
+#define                 AT91_SDRAMC_CAS_2       (2 << 5)
+#define         AT91_SDRAMC_TWR         (0xf <<  7)             /* Write Recovery Delay */
+#define         AT91_SDRAMC_TRC         (0xf << 11)             /* Row Cycle Delay */
+#define         AT91_SDRAMC_TRP         (0xf << 15)             /* Row Precharge Delay */
+#define         AT91_SDRAMC_TRCD        (0xf << 19)             /* Row to Column Delay */
+#define         AT91_SDRAMC_TRAS        (0xf << 23)             /* Active to Precharge Delay */
+#define         AT91_SDRAMC_TXSR        (0xf << 27)             /* Exit Self Refresh to Active Delay */
+
+#define AT91_SDRAMC_SRR         (AT91_MC + 0x9c)        /* Self Refresh Register */
+#define AT91_SDRAMC_LPR         (AT91_MC + 0xa0)        /* Low Power Register */
+#define AT91_SDRAMC_IER         (AT91_MC + 0xa4)        /* Interrupt Enable Register */
+#define AT91_SDRAMC_IDR         (AT91_MC + 0xa8)        /* Interrupt Disable Register */
+#define AT91_SDRAMC_IMR         (AT91_MC + 0xac)        /* Interrupt Mask Register */
+#define AT91_SDRAMC_ISR         (AT91_MC + 0xb0)        /* Interrupt Status Register */
+
+/* Burst Flash Controller register */
+#define AT91_BFC_MR             (AT91_MC + 0xc0)        /* Mode Register */
+#define         AT91_BFC_BFCOM          (3   <<  0)             /* Burst Flash Controller Operating Mode */
+#define                 AT91_BFC_BFCOM_DISABLED (0 << 0)
+#define                 AT91_BFC_BFCOM_ASYNC    (1 << 0)
+#define                 AT91_BFC_BFCOM_BURST    (2 << 0)
+#define         AT91_BFC_BFCC           (3   <<  2)             /* Burst Flash Controller Clock */
+#define                 AT91_BFC_BFCC_MCK       (1 << 2)
+#define                 AT91_BFC_BFCC_DIV2      (2 << 2)
+#define                 AT91_BFC_BFCC_DIV4      (3 << 2)
+#define         AT91_BFC_AVL            (0xf <<  4)             /* Address Valid Latency */
+#define         AT91_BFC_PAGES          (7   <<  8)             /* Page Size */
+#define                 AT91_BFC_PAGES_NO_PAGE  (0 << 8)
+#define                 AT91_BFC_PAGES_16       (1 << 8)
+#define                 AT91_BFC_PAGES_32       (2 << 8)
+#define                 AT91_BFC_PAGES_64       (3 << 8)
+#define                 AT91_BFC_PAGES_128      (4 << 8)
+#define                 AT91_BFC_PAGES_256      (5 << 8)
+#define                 AT91_BFC_PAGES_512      (6 << 8)
+#define                 AT91_BFC_PAGES_1024     (7 << 8)
+#define         AT91_BFC_OEL            (3   << 12)             /* Output Enable Latency */
+#define         AT91_BFC_BAAEN          (1   << 16)             /* Burst Address Advance Enable */
+#define         AT91_BFC_BFOEH          (1   << 17)             /* Burst Flash Output Enable Handling */
+#define         AT91_BFC_MUXEN          (1   << 18)             /* Multiplexed Bus Enable */
+#define         AT91_BFC_RDYEN          (1   << 19)             /* Ready Enable Mode */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
new file mode 100644
index 000000000000..43c396b9b4cb
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -0,0 +1,138 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91sam9260.h
+ *
+ * (C) 2006 Andrew Victor
+ *
+ * Common definitions.
+ * Based on AT91SAM9260 datasheet revision A (Preliminary).
+ *
+ * Includes also definitions for AT91SAM9XE and AT91SAM9G families
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9260_H
+#define AT91SAM9260_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS             1       /* System Peripherals */
+#define AT91SAM9260_ID_PIOA     2       /* Parallel IO Controller A */
+#define AT91SAM9260_ID_PIOB     3       /* Parallel IO Controller B */
+#define AT91SAM9260_ID_PIOC     4       /* Parallel IO Controller C */
+#define AT91SAM9260_ID_ADC      5       /* Analog-to-Digital Converter */
+#define AT91SAM9260_ID_US0      6       /* USART 0 */
+#define AT91SAM9260_ID_US1      7       /* USART 1 */
+#define AT91SAM9260_ID_US2      8       /* USART 2 */
+#define AT91SAM9260_ID_MCI      9       /* Multimedia Card Interface */
+#define AT91SAM9260_ID_UDP      10      /* USB Device Port */
+#define AT91SAM9260_ID_TWI      11      /* Two-Wire Interface */
+#define AT91SAM9260_ID_SPI0     12      /* Serial Peripheral Interface 0 */
+#define AT91SAM9260_ID_SPI1     13      /* Serial Peripheral Interface 1 */
+#define AT91SAM9260_ID_SSC      14      /* Serial Synchronous Controller */
+#define AT91SAM9260_ID_TC0      17      /* Timer Counter 0 */
+#define AT91SAM9260_ID_TC1      18      /* Timer Counter 1 */
+#define AT91SAM9260_ID_TC2      19      /* Timer Counter 2 */
+#define AT91SAM9260_ID_UHP      20      /* USB Host port */
+#define AT91SAM9260_ID_EMAC     21      /* Ethernet */
+#define AT91SAM9260_ID_ISI      22      /* Image Sensor Interface */
+#define AT91SAM9260_ID_US3      23      /* USART 3 */
+#define AT91SAM9260_ID_US4      24      /* USART 4 */
+#define AT91SAM9260_ID_US5      25      /* USART 5 */
+#define AT91SAM9260_ID_TC3      26      /* Timer Counter 3 */
+#define AT91SAM9260_ID_TC4      27      /* Timer Counter 4 */
+#define AT91SAM9260_ID_TC5      28      /* Timer Counter 5 */
+#define AT91SAM9260_ID_IRQ0     29      /* Advanced Interrupt Controller (IRQ0) */
+#define AT91SAM9260_ID_IRQ1     30      /* Advanced Interrupt Controller (IRQ1) */
+#define AT91SAM9260_ID_IRQ2     31      /* Advanced Interrupt Controller (IRQ2) */
+
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT91SAM9260_BASE_TCB0           0xfffa0000
+#define AT91SAM9260_BASE_TC0            0xfffa0000
+#define AT91SAM9260_BASE_TC1            0xfffa0040
+#define AT91SAM9260_BASE_TC2            0xfffa0080
+#define AT91SAM9260_BASE_UDP            0xfffa4000
+#define AT91SAM9260_BASE_MCI            0xfffa8000
+#define AT91SAM9260_BASE_TWI            0xfffac000
+#define AT91SAM9260_BASE_US0            0xfffb0000
+#define AT91SAM9260_BASE_US1            0xfffb4000
+#define AT91SAM9260_BASE_US2            0xfffb8000
+#define AT91SAM9260_BASE_SSC            0xfffbc000
+#define AT91SAM9260_BASE_ISI            0xfffc0000
+#define AT91SAM9260_BASE_EMAC           0xfffc4000
+#define AT91SAM9260_BASE_SPI0           0xfffc8000
+#define AT91SAM9260_BASE_SPI1           0xfffcc000
+#define AT91SAM9260_BASE_US3            0xfffd0000
+#define AT91SAM9260_BASE_US4            0xfffd4000
+#define AT91SAM9260_BASE_US5            0xfffd8000
+#define AT91SAM9260_BASE_TCB1           0xfffdc000
+#define AT91SAM9260_BASE_TC3            0xfffdc000
+#define AT91SAM9260_BASE_TC4            0xfffdc040
+#define AT91SAM9260_BASE_TC5            0xfffdc080
+#define AT91SAM9260_BASE_ADC            0xfffe0000
+#define AT91_BASE_SYS                   0xffffe800
+
+/*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_ECC        (0xffffe800 - AT91_BASE_SYS)
+#define AT91_SDRAMC     (0xffffea00 - AT91_BASE_SYS)
+#define AT91_SMC        (0xffffec00 - AT91_BASE_SYS)
+#define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
+#define AT91_CCFG       (0xffffef10 - AT91_BASE_SYS)
+#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
+#define AT91_DBGU       (0xfffff200 - AT91_BASE_SYS)
+#define AT91_PIOA       (0xfffff400 - AT91_BASE_SYS)
+#define AT91_PIOB       (0xfffff600 - AT91_BASE_SYS)
+#define AT91_PIOC       (0xfffff800 - AT91_BASE_SYS)
+#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
+#define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
+#define AT91_SHDWC      (0xfffffd10 - AT91_BASE_SYS)
+#define AT91_RTT        (0xfffffd20 - AT91_BASE_SYS)
+#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
+#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_GPBR       (0xfffffd50 - AT91_BASE_SYS)
+
+#define AT91_USART0     AT91SAM9260_BASE_US0
+#define AT91_USART1     AT91SAM9260_BASE_US1
+#define AT91_USART2     AT91SAM9260_BASE_US2
+#define AT91_USART3     AT91SAM9260_BASE_US3
+#define AT91_USART4     AT91SAM9260_BASE_US4
+#define AT91_USART5     AT91SAM9260_BASE_US5
+
+
+/*
+ * Internal Memory.
+ */
+#define AT91SAM9260_ROM_BASE    0x00100000      /* Internal ROM base address */
+#define AT91SAM9260_ROM_SIZE    SZ_32K          /* Internal ROM size (32Kb) */
+
+#define AT91SAM9260_SRAM0_BASE  0x00200000      /* Internal SRAM 0 base address */
+#define AT91SAM9260_SRAM0_SIZE  SZ_4K           /* Internal SRAM 0 size (4Kb) */
+#define AT91SAM9260_SRAM1_BASE  0x00300000      /* Internal SRAM 1 base address */
+#define AT91SAM9260_SRAM1_SIZE  SZ_4K           /* Internal SRAM 1 size (4Kb) */
+
+#define AT91SAM9260_UHP_BASE    0x00500000      /* USB Host controller */
+
+#define AT91SAM9XE_FLASH_BASE   0x00200000      /* Internal FLASH base address */
+#define AT91SAM9XE_SRAM_BASE    0x00300000      /* Internal SRAM base address */
+
+#define AT91SAM9G20_ROM_BASE    0x00100000      /* Internal ROM base address */
+#define AT91SAM9G20_ROM_SIZE    SZ_32K          /* Internal ROM size (32Kb) */
+
+#define AT91SAM9G20_SRAM0_BASE  0x00200000      /* Internal SRAM 0 base address */
+#define AT91SAM9G20_SRAM0_SIZE  SZ_16K          /* Internal SRAM 0 size (16Kb) */
+#define AT91SAM9G20_SRAM1_BASE  0x00300000      /* Internal SRAM 1 base address */
+#define AT91SAM9G20_SRAM1_SIZE  SZ_16K          /* Internal SRAM 1 size (16Kb) */
+
+#define AT91SAM9G20_UHP_BASE    0x00500000      /* USB Host controller */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
new file mode 100644
index 000000000000..f027de5df956
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
@@ -0,0 +1,78 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91SAM9260 datasheet revision B.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9260_MATRIX_H
+#define AT91SAM9260_MATRIX_H
+
+#define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
+#define         AT91_MATRIX_ULBT                (7 << 0)        /* Undefined Length Burst Type */
+#define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
+#define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
+#define                 AT91_MATRIX_ULBT_FOUR           (2 << 0)
+#define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
+#define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
+
+#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
+#define         AT91_MATRIX_SLOT_CYCLE          (0xff <<  0)    /* Maximum Number of Allowed Cycles for a Burst */
+#define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
+#define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
+#define         AT91_MATRIX_FIXED_DEFMSTR       (7    << 18)    /* Fixed Index of Default Master */
+#define         AT91_MATRIX_ARBT                (3    << 24)    /* Arbitration Type */
+#define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
+#define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
+
+#define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
+#define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
+#define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
+#define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
+#define         AT91_MATRIX_M3PR                (3 << 12)       /* Master 3 Priority */
+#define         AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
+#define         AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
+
+#define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
+#define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+
+#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x11C)   /* EBI Chip Select Assignment Register */
+#define         AT91_MATRIX_CS1A                (1 << 1)        /* Chip Select 1 Assignment */
+#define                 AT91_MATRIX_CS1A_SMC            (0 << 1)
+#define                 AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
+#define         AT91_MATRIX_CS3A                (1 << 3)        /* Chip Select 3 Assignment */
+#define                 AT91_MATRIX_CS3A_SMC            (0 << 3)
+#define                 AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define         AT91_MATRIX_CS4A                (1 << 4)        /* Chip Select 4 Assignment */
+#define                 AT91_MATRIX_CS4A_SMC            (0 << 4)
+#define                 AT91_MATRIX_CS4A_SMC_CF1        (1 << 4)
+#define         AT91_MATRIX_CS5A                (1 << 5)        /* Chip Select 5 Assignment */
+#define                 AT91_MATRIX_CS5A_SMC            (0 << 5)
+#define                 AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
+#define         AT91_MATRIX_DBPUC               (1 << 8)        /* Data Bus Pull-up Configuration */
+#define         AT91_MATRIX_VDDIOMSEL           (1 << 16)       /* Memory voltage selection */
+#define                 AT91_MATRIX_VDDIOMSEL_1_8V      (0 << 16)
+#define                 AT91_MATRIX_VDDIOMSEL_3_3V      (1 << 16)
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
new file mode 100644
index 000000000000..3a348ca20773
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -0,0 +1,105 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91sam9261.h
+ *
+ * Copyright (C) SAN People
+ *
+ * Common definitions.
+ * Based on AT91SAM9261 datasheet revision E. (Preliminary)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9261_H
+#define AT91SAM9261_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS             1       /* System Peripherals */
+#define AT91SAM9261_ID_PIOA     2       /* Parallel IO Controller A */
+#define AT91SAM9261_ID_PIOB     3       /* Parallel IO Controller B */
+#define AT91SAM9261_ID_PIOC     4       /* Parallel IO Controller C */
+#define AT91SAM9261_ID_US0      6       /* USART 0 */
+#define AT91SAM9261_ID_US1      7       /* USART 1 */
+#define AT91SAM9261_ID_US2      8       /* USART 2 */
+#define AT91SAM9261_ID_MCI      9       /* Multimedia Card Interface */
+#define AT91SAM9261_ID_UDP      10      /* USB Device Port */
+#define AT91SAM9261_ID_TWI      11      /* Two-Wire Interface */
+#define AT91SAM9261_ID_SPI0     12      /* Serial Peripheral Interface 0 */
+#define AT91SAM9261_ID_SPI1     13      /* Serial Peripheral Interface 1 */
+#define AT91SAM9261_ID_SSC0     14      /* Serial Synchronous Controller 0 */
+#define AT91SAM9261_ID_SSC1     15      /* Serial Synchronous Controller 1 */
+#define AT91SAM9261_ID_SSC2     16      /* Serial Synchronous Controller 2 */
+#define AT91SAM9261_ID_TC0      17      /* Timer Counter 0 */
+#define AT91SAM9261_ID_TC1      18      /* Timer Counter 1 */
+#define AT91SAM9261_ID_TC2      19      /* Timer Counter 2 */
+#define AT91SAM9261_ID_UHP      20      /* USB Host port */
+#define AT91SAM9261_ID_LCDC     21      /* LDC Controller */
+#define AT91SAM9261_ID_IRQ0     29      /* Advanced Interrupt Controller (IRQ0) */
+#define AT91SAM9261_ID_IRQ1     30      /* Advanced Interrupt Controller (IRQ1) */
+#define AT91SAM9261_ID_IRQ2     31      /* Advanced Interrupt Controller (IRQ2) */
+
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT91SAM9261_BASE_TCB0           0xfffa0000
+#define AT91SAM9261_BASE_TC0            0xfffa0000
+#define AT91SAM9261_BASE_TC1            0xfffa0040
+#define AT91SAM9261_BASE_TC2            0xfffa0080
+#define AT91SAM9261_BASE_UDP            0xfffa4000
+#define AT91SAM9261_BASE_MCI            0xfffa8000
+#define AT91SAM9261_BASE_TWI            0xfffac000
+#define AT91SAM9261_BASE_US0            0xfffb0000
+#define AT91SAM9261_BASE_US1            0xfffb4000
+#define AT91SAM9261_BASE_US2            0xfffb8000
+#define AT91SAM9261_BASE_SSC0           0xfffbc000
+#define AT91SAM9261_BASE_SSC1           0xfffc0000
+#define AT91SAM9261_BASE_SSC2           0xfffc4000
+#define AT91SAM9261_BASE_SPI0           0xfffc8000
+#define AT91SAM9261_BASE_SPI1           0xfffcc000
+#define AT91_BASE_SYS                   0xffffea00
+
+
+/*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_SDRAMC     (0xffffea00 - AT91_BASE_SYS)
+#define AT91_SMC        (0xffffec00 - AT91_BASE_SYS)
+#define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
+#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
+#define AT91_DBGU       (0xfffff200 - AT91_BASE_SYS)
+#define AT91_PIOA       (0xfffff400 - AT91_BASE_SYS)
+#define AT91_PIOB       (0xfffff600 - AT91_BASE_SYS)
+#define AT91_PIOC       (0xfffff800 - AT91_BASE_SYS)
+#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
+#define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
+#define AT91_SHDWC      (0xfffffd10 - AT91_BASE_SYS)
+#define AT91_RTT        (0xfffffd20 - AT91_BASE_SYS)
+#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
+#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_GPBR       (0xfffffd50 - AT91_BASE_SYS)
+
+#define AT91_USART0     AT91SAM9261_BASE_US0
+#define AT91_USART1     AT91SAM9261_BASE_US1
+#define AT91_USART2     AT91SAM9261_BASE_US2
+
+
+/*
+ * Internal Memory.
+ */
+#define AT91SAM9261_SRAM_BASE   0x00300000      /* Internal SRAM base address */
+#define AT91SAM9261_SRAM_SIZE   0x00028000      /* Internal SRAM size (160Kb) */
+
+#define AT91SAM9261_ROM_BASE    0x00400000      /* Internal ROM base address */
+#define AT91SAM9261_ROM_SIZE    SZ_32K          /* Internal ROM size (32Kb) */
+
+#define AT91SAM9261_UHP_BASE    0x00500000      /* USB Host controller */
+#define AT91SAM9261_LCDC_BASE   0x00600000      /* LDC controller */
+
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
new file mode 100644
index 000000000000..db62b1f18300
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
@@ -0,0 +1,62 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9261_MATRIX_H
+#define AT91SAM9261_MATRIX_H
+
+#define AT91_MATRIX_MCFG        (AT91_MATRIX + 0x00)    /* Master Configuration Register */
+#define         AT91_MATRIX_RCB0        (1 << 0)                /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define         AT91_MATRIX_RCB1        (1 << 1)                /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+
+#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x04)    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x08)    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x0C)    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x10)    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x14)    /* Slave Configuration Register 4 */
+#define         AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
+#define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
+#define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
+#define         AT91_MATRIX_FIXED_DEFMSTR       (7    << 18)    /* Fixed Index of Default Master */
+
+#define AT91_MATRIX_TCR         (AT91_MATRIX + 0x24)    /* TCM Configuration Register */
+#define         AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
+#define                 AT91_MATRIX_ITCM_0              (0 << 0)
+#define                 AT91_MATRIX_ITCM_16             (5 << 0)
+#define                 AT91_MATRIX_ITCM_32             (6 << 0)
+#define                 AT91_MATRIX_ITCM_64             (7 << 0)
+#define         AT91_MATRIX_DTCM_SIZE           (0xf << 4)      /* Size of DTCM enabled memory block */
+#define                 AT91_MATRIX_DTCM_0              (0 << 4)
+#define                 AT91_MATRIX_DTCM_16             (5 << 4)
+#define                 AT91_MATRIX_DTCM_32             (6 << 4)
+#define                 AT91_MATRIX_DTCM_64             (7 << 4)
+
+#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x30)    /* EBI Chip Select Assignment Register */
+#define         AT91_MATRIX_CS1A                (1 << 1)        /* Chip Select 1 Assignment */
+#define                 AT91_MATRIX_CS1A_SMC            (0 << 1)
+#define                 AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
+#define         AT91_MATRIX_CS3A                (1 << 3)        /* Chip Select 3 Assignment */
+#define                 AT91_MATRIX_CS3A_SMC            (0 << 3)
+#define                 AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define         AT91_MATRIX_CS4A                (1 << 4)        /* Chip Select 4 Assignment */
+#define                 AT91_MATRIX_CS4A_SMC            (0 << 4)
+#define                 AT91_MATRIX_CS4A_SMC_CF1        (1 << 4)
+#define         AT91_MATRIX_CS5A                (1 << 5)        /* Chip Select 5 Assignment */
+#define                 AT91_MATRIX_CS5A_SMC            (0 << 5)
+#define                 AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
+#define         AT91_MATRIX_DBPUC               (1 << 8)        /* Data Bus Pull-up Configuration */
+
+#define AT91_MATRIX_USBPUCR     (AT91_MATRIX + 0x34)    /* USB Pad Pull-Up Control Register */
+#define         AT91_MATRIX_USBPUCR_PUON        (1 << 30)       /* USB Device PAD Pull-up Enable */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
new file mode 100644
index 000000000000..2091f1e42d43
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -0,0 +1,127 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91sam9263.h
+ *
+ * (C) 2007 Atmel Corporation.
+ *
+ * Common definitions.
+ * Based on AT91SAM9263 datasheet revision B (Preliminary).
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9263_H
+#define AT91SAM9263_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS             1       /* System Peripherals */
+#define AT91SAM9263_ID_PIOA     2       /* Parallel IO Controller A */
+#define AT91SAM9263_ID_PIOB     3       /* Parallel IO Controller B */
+#define AT91SAM9263_ID_PIOCDE   4       /* Parallel IO Controller C, D and E */
+#define AT91SAM9263_ID_US0      7       /* USART 0 */
+#define AT91SAM9263_ID_US1      8       /* USART 1 */
+#define AT91SAM9263_ID_US2      9       /* USART 2 */
+#define AT91SAM9263_ID_MCI0     10      /* Multimedia Card Interface 0 */
+#define AT91SAM9263_ID_MCI1     11      /* Multimedia Card Interface 1 */
+#define AT91SAM9263_ID_CAN      12      /* CAN */
+#define AT91SAM9263_ID_TWI      13      /* Two-Wire Interface */
+#define AT91SAM9263_ID_SPI0     14      /* Serial Peripheral Interface 0 */
+#define AT91SAM9263_ID_SPI1     15      /* Serial Peripheral Interface 1 */
+#define AT91SAM9263_ID_SSC0     16      /* Serial Synchronous Controller 0 */
+#define AT91SAM9263_ID_SSC1     17      /* Serial Synchronous Controller 1 */
+#define AT91SAM9263_ID_AC97C    18      /* AC97 Controller */
+#define AT91SAM9263_ID_TCB      19      /* Timer Counter 0, 1 and 2 */
+#define AT91SAM9263_ID_PWMC     20      /* Pulse Width Modulation Controller */
+#define AT91SAM9263_ID_EMAC     21      /* Ethernet */
+#define AT91SAM9263_ID_2DGE     23      /* 2D Graphic Engine */
+#define AT91SAM9263_ID_UDP      24      /* USB Device Port */
+#define AT91SAM9263_ID_ISI      25      /* Image Sensor Interface */
+#define AT91SAM9263_ID_LCDC     26      /* LCD Controller */
+#define AT91SAM9263_ID_DMA      27      /* DMA Controller */
+#define AT91SAM9263_ID_UHP      29      /* USB Host port */
+#define AT91SAM9263_ID_IRQ0     30      /* Advanced Interrupt Controller (IRQ0) */
+#define AT91SAM9263_ID_IRQ1     31      /* Advanced Interrupt Controller (IRQ1) */
+
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT91SAM9263_BASE_UDP            0xfff78000
+#define AT91SAM9263_BASE_TCB0           0xfff7c000
+#define AT91SAM9263_BASE_TC0            0xfff7c000
+#define AT91SAM9263_BASE_TC1            0xfff7c040
+#define AT91SAM9263_BASE_TC2            0xfff7c080
+#define AT91SAM9263_BASE_MCI0           0xfff80000
+#define AT91SAM9263_BASE_MCI1           0xfff84000
+#define AT91SAM9263_BASE_TWI            0xfff88000
+#define AT91SAM9263_BASE_US0            0xfff8c000
+#define AT91SAM9263_BASE_US1            0xfff90000
+#define AT91SAM9263_BASE_US2            0xfff94000
+#define AT91SAM9263_BASE_SSC0           0xfff98000
+#define AT91SAM9263_BASE_SSC1           0xfff9c000
+#define AT91SAM9263_BASE_AC97C          0xfffa0000
+#define AT91SAM9263_BASE_SPI0           0xfffa4000
+#define AT91SAM9263_BASE_SPI1           0xfffa8000
+#define AT91SAM9263_BASE_CAN            0xfffac000
+#define AT91SAM9263_BASE_PWMC           0xfffb8000
+#define AT91SAM9263_BASE_EMAC           0xfffbc000
+#define AT91SAM9263_BASE_ISI            0xfffc4000
+#define AT91SAM9263_BASE_2DGE           0xfffc8000
+#define AT91_BASE_SYS                   0xffffe000
+
+/*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_ECC0       (0xffffe000 - AT91_BASE_SYS)
+#define AT91_SDRAMC0    (0xffffe200 - AT91_BASE_SYS)
+#define AT91_SMC0       (0xffffe400 - AT91_BASE_SYS)
+#define AT91_ECC1       (0xffffe600 - AT91_BASE_SYS)
+#define AT91_SDRAMC1    (0xffffe800 - AT91_BASE_SYS)
+#define AT91_SMC1       (0xffffea00 - AT91_BASE_SYS)
+#define AT91_MATRIX     (0xffffec00 - AT91_BASE_SYS)
+#define AT91_CCFG       (0xffffed10 - AT91_BASE_SYS)
+#define AT91_DBGU       (0xffffee00 - AT91_BASE_SYS)
+#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
+#define AT91_PIOA       (0xfffff200 - AT91_BASE_SYS)
+#define AT91_PIOB       (0xfffff400 - AT91_BASE_SYS)
+#define AT91_PIOC       (0xfffff600 - AT91_BASE_SYS)
+#define AT91_PIOD       (0xfffff800 - AT91_BASE_SYS)
+#define AT91_PIOE       (0xfffffa00 - AT91_BASE_SYS)
+#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
+#define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
+#define AT91_SHDWC      (0xfffffd10 - AT91_BASE_SYS)
+#define AT91_RTT0       (0xfffffd20 - AT91_BASE_SYS)
+#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
+#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_RTT1       (0xfffffd50 - AT91_BASE_SYS)
+#define AT91_GPBR       (0xfffffd60 - AT91_BASE_SYS)
+
+#define AT91_USART0     AT91SAM9263_BASE_US0
+#define AT91_USART1     AT91SAM9263_BASE_US1
+#define AT91_USART2     AT91SAM9263_BASE_US2
+
+#define AT91_SMC        AT91_SMC0
+
+/*
+ * Internal Memory.
+ */
+#define AT91SAM9263_SRAM0_BASE  0x00300000      /* Internal SRAM 0 base address */
+#define AT91SAM9263_SRAM0_SIZE  (80 * SZ_1K)    /* Internal SRAM 0 size (80Kb) */
+
+#define AT91SAM9263_ROM_BASE    0x00400000      /* Internal ROM base address */
+#define AT91SAM9263_ROM_SIZE    SZ_128K         /* Internal ROM size (128Kb) */
+
+#define AT91SAM9263_SRAM1_BASE  0x00500000      /* Internal SRAM 1 base address */
+#define AT91SAM9263_SRAM1_SIZE  SZ_16K          /* Internal SRAM 1 size (16Kb) */
+
+#define AT91SAM9263_LCDC_BASE   0x00700000      /* LCD Controller */
+#define AT91SAM9263_DMAC_BASE   0x00800000      /* DMA Controller */
+#define AT91SAM9263_UHP_BASE    0x00a00000      /* USB Host controller */
+
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
new file mode 100644
index 000000000000..9b3efd3eb2f3
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
@@ -0,0 +1,129 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
+ *
+ *  Copyright (C) 2006 Atmel Corporation.
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91SAM9263 datasheet revision B (Preliminary).
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9263_MATRIX_H
+#define AT91SAM9263_MATRIX_H
+
+#define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
+#define AT91_MATRIX_MCFG6       (AT91_MATRIX + 0x18)    /* Master Configuration Register 6 */
+#define AT91_MATRIX_MCFG7       (AT91_MATRIX + 0x1C)    /* Master Configuration Register 7 */
+#define AT91_MATRIX_MCFG8       (AT91_MATRIX + 0x20)    /* Master Configuration Register 8 */
+#define         AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
+#define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
+#define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
+#define                 AT91_MATRIX_ULBT_FOUR           (2 << 0)
+#define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
+#define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
+
+#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
+#define AT91_MATRIX_SCFG5       (AT91_MATRIX + 0x54)    /* Slave Configuration Register 5 */
+#define AT91_MATRIX_SCFG6       (AT91_MATRIX + 0x58)    /* Slave Configuration Register 6 */
+#define AT91_MATRIX_SCFG7       (AT91_MATRIX + 0x5C)    /* Slave Configuration Register 7 */
+#define         AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
+#define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
+#define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
+#define         AT91_MATRIX_FIXED_DEFMSTR       (0xf  << 18)    /* Fixed Index of Default Master */
+#define         AT91_MATRIX_ARBT                (3    << 24)    /* Arbitration Type */
+#define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
+#define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
+
+#define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRBS0       (AT91_MATRIX + 0x84)    /* Priority Register B for Slave 0 */
+#define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRBS1       (AT91_MATRIX + 0x8C)    /* Priority Register B for Slave 1 */
+#define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRBS2       (AT91_MATRIX + 0x94)    /* Priority Register B for Slave 2 */
+#define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRBS3       (AT91_MATRIX + 0x9C)    /* Priority Register B for Slave 3 */
+#define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
+#define AT91_MATRIX_PRBS4       (AT91_MATRIX + 0xA4)    /* Priority Register B for Slave 4 */
+#define AT91_MATRIX_PRAS5       (AT91_MATRIX + 0xA8)    /* Priority Register A for Slave 5 */
+#define AT91_MATRIX_PRBS5       (AT91_MATRIX + 0xAC)    /* Priority Register B for Slave 5 */
+#define AT91_MATRIX_PRAS6       (AT91_MATRIX + 0xB0)    /* Priority Register A for Slave 6 */
+#define AT91_MATRIX_PRBS6       (AT91_MATRIX + 0xB4)    /* Priority Register B for Slave 6 */
+#define AT91_MATRIX_PRAS7       (AT91_MATRIX + 0xB8)    /* Priority Register A for Slave 7 */
+#define AT91_MATRIX_PRBS7       (AT91_MATRIX + 0xBC)    /* Priority Register B for Slave 7 */
+#define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
+#define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
+#define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
+#define         AT91_MATRIX_M3PR                (3 << 12)       /* Master 3 Priority */
+#define         AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
+#define         AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
+#define         AT91_MATRIX_M6PR                (3 << 24)       /* Master 6 Priority */
+#define         AT91_MATRIX_M7PR                (3 << 28)       /* Master 7 Priority */
+#define         AT91_MATRIX_M8PR                (3 << 0)        /* Master 8 Priority (in Register B) */
+
+#define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
+#define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define         AT91_MATRIX_RCB2                (1 << 2)
+#define         AT91_MATRIX_RCB3                (1 << 3)
+#define         AT91_MATRIX_RCB4                (1 << 4)
+#define         AT91_MATRIX_RCB5                (1 << 5)
+#define         AT91_MATRIX_RCB6                (1 << 6)
+#define         AT91_MATRIX_RCB7                (1 << 7)
+#define         AT91_MATRIX_RCB8                (1 << 8)
+
+#define AT91_MATRIX_TCMR        (AT91_MATRIX + 0x114)   /* TCM Configuration Register */
+#define         AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
+#define                 AT91_MATRIX_ITCM_0              (0 << 0)
+#define                 AT91_MATRIX_ITCM_16             (5 << 0)
+#define                 AT91_MATRIX_ITCM_32             (6 << 0)
+#define         AT91_MATRIX_DTCM_SIZE           (0xf << 4)      /* Size of DTCM enabled memory block */
+#define                 AT91_MATRIX_DTCM_0              (0 << 4)
+#define                 AT91_MATRIX_DTCM_16             (5 << 4)
+#define                 AT91_MATRIX_DTCM_32             (6 << 4)
+
+#define AT91_MATRIX_EBI0CSA     (AT91_MATRIX + 0x120)   /* EBI0 Chip Select Assignment Register */
+#define         AT91_MATRIX_EBI0_CS1A           (1 << 1)        /* Chip Select 1 Assignment */
+#define                 AT91_MATRIX_EBI0_CS1A_SMC               (0 << 1)
+#define                 AT91_MATRIX_EBI0_CS1A_SDRAMC            (1 << 1)
+#define         AT91_MATRIX_EBI0_CS3A           (1 << 3)        /* Chip Select 3 Assignment */
+#define                 AT91_MATRIX_EBI0_CS3A_SMC               (0 << 3)
+#define                 AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA    (1 << 3)
+#define         AT91_MATRIX_EBI0_CS4A           (1 << 4)        /* Chip Select 4 Assignment */
+#define                 AT91_MATRIX_EBI0_CS4A_SMC               (0 << 4)
+#define                 AT91_MATRIX_EBI0_CS4A_SMC_CF1           (1 << 4)
+#define         AT91_MATRIX_EBI0_CS5A           (1 << 5)        /* Chip Select 5 Assignment */
+#define                 AT91_MATRIX_EBI0_CS5A_SMC               (0 << 5)
+#define                 AT91_MATRIX_EBI0_CS5A_SMC_CF2           (1 << 5)
+#define         AT91_MATRIX_EBI0_DBPUC          (1 << 8)        /* Data Bus Pull-up Configuration */
+#define         AT91_MATRIX_EBI0_VDDIOMSEL      (1 << 16)       /* Memory voltage selection */
+#define                 AT91_MATRIX_EBI0_VDDIOMSEL_1_8V         (0 << 16)
+#define                 AT91_MATRIX_EBI0_VDDIOMSEL_3_3V         (1 << 16)
+
+#define AT91_MATRIX_EBI1CSA     (AT91_MATRIX + 0x124)   /* EBI1 Chip Select Assignment Register */
+#define         AT91_MATRIX_EBI1_CS1A           (1 << 1)        /* Chip Select 1 Assignment */
+#define                 AT91_MATRIX_EBI1_CS1A_SMC               (0 << 1)
+#define                 AT91_MATRIX_EBI1_CS1A_SDRAMC            (1 << 1)
+#define         AT91_MATRIX_EBI1_CS2A           (1 << 3)        /* Chip Select 3 Assignment */
+#define                 AT91_MATRIX_EBI1_CS2A_SMC               (0 << 3)
+#define                 AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA    (1 << 3)
+#define         AT91_MATRIX_EBI1_DBPUC          (1 << 8)        /* Data Bus Pull-up Configuration */
+#define         AT91_MATRIX_EBI1_VDDIOMSEL      (1 << 16)       /* Memory voltage selection */
+#define                 AT91_MATRIX_EBI1_VDDIOMSEL_1_8V         (0 << 16)
+#define                 AT91_MATRIX_EBI1_VDDIOMSEL_3_3V         (1 << 16)
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
new file mode 100644
index 000000000000..1921181c63ca
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
@@ -0,0 +1,83 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
+ *
+ * SDRAM Controllers (SDRAMC) - System peripherals registers.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9_SDRAMC_H
+#define AT91SAM9_SDRAMC_H
+
+/* SDRAM Controller (SDRAMC) registers */
+#define AT91_SDRAMC_MR          (AT91_SDRAMC + 0x00)    /* SDRAM Controller Mode Register */
+#define         AT91_SDRAMC_MODE        (0xf << 0)              /* Command Mode */
+#define                 AT91_SDRAMC_MODE_NORMAL         0
+#define                 AT91_SDRAMC_MODE_NOP            1
+#define                 AT91_SDRAMC_MODE_PRECHARGE      2
+#define                 AT91_SDRAMC_MODE_LMR            3
+#define                 AT91_SDRAMC_MODE_REFRESH        4
+#define                 AT91_SDRAMC_MODE_EXT_LMR        5
+#define                 AT91_SDRAMC_MODE_DEEP           6
+
+#define AT91_SDRAMC_TR          (AT91_SDRAMC + 0x04)    /* SDRAM Controller Refresh Timer Register */
+#define         AT91_SDRAMC_COUNT       (0xfff << 0)            /* Refresh Timer Counter */
+
+#define AT91_SDRAMC_CR          (AT91_SDRAMC + 0x08)    /* SDRAM Controller Configuration Register */
+#define         AT91_SDRAMC_NC          (3 << 0)                /* Number of Column Bits */
+#define                 AT91_SDRAMC_NC_8        (0 << 0)
+#define                 AT91_SDRAMC_NC_9        (1 << 0)
+#define                 AT91_SDRAMC_NC_10       (2 << 0)
+#define                 AT91_SDRAMC_NC_11       (3 << 0)
+#define         AT91_SDRAMC_NR          (3 << 2)                /* Number of Row Bits */
+#define                 AT91_SDRAMC_NR_11       (0 << 2)
+#define                 AT91_SDRAMC_NR_12       (1 << 2)
+#define                 AT91_SDRAMC_NR_13       (2 << 2)
+#define         AT91_SDRAMC_NB          (1 << 4)                /* Number of Banks */
+#define                 AT91_SDRAMC_NB_2        (0 << 4)
+#define                 AT91_SDRAMC_NB_4        (1 << 4)
+#define         AT91_SDRAMC_CAS         (3 << 5)                /* CAS Latency */
+#define                 AT91_SDRAMC_CAS_1       (1 << 5)
+#define                 AT91_SDRAMC_CAS_2       (2 << 5)
+#define                 AT91_SDRAMC_CAS_3       (3 << 5)
+#define         AT91_SDRAMC_DBW         (1 << 7)                /* Data Bus Width */
+#define                 AT91_SDRAMC_DBW_32      (0 << 7)
+#define                 AT91_SDRAMC_DBW_16      (1 << 7)
+#define         AT91_SDRAMC_TWR         (0xf <<  8)             /* Write Recovery Delay */
+#define         AT91_SDRAMC_TRC         (0xf << 12)             /* Row Cycle Delay */
+#define         AT91_SDRAMC_TRP         (0xf << 16)             /* Row Precharge Delay */
+#define         AT91_SDRAMC_TRCD        (0xf << 20)             /* Row to Column Delay */
+#define         AT91_SDRAMC_TRAS        (0xf << 24)             /* Active to Precharge Delay */
+#define         AT91_SDRAMC_TXSR        (0xf << 28)             /* Exit Self Refresh to Active Delay */
+
+#define AT91_SDRAMC_LPR         (AT91_SDRAMC + 0x10)    /* SDRAM Controller Low Power Register */
+#define         AT91_SDRAMC_LPCB                (3 << 0)        /* Low-power Configurations */
+#define                 AT91_SDRAMC_LPCB_DISABLE                0
+#define                 AT91_SDRAMC_LPCB_SELF_REFRESH           1
+#define                 AT91_SDRAMC_LPCB_POWER_DOWN             2
+#define                 AT91_SDRAMC_LPCB_DEEP_POWER_DOWN        3
+#define         AT91_SDRAMC_PASR                (7 << 4)        /* Partial Array Self Refresh */
+#define         AT91_SDRAMC_TCSR                (3 << 8)        /* Temperature Compensated Self Refresh */
+#define         AT91_SDRAMC_DS                  (3 << 10)       /* Drive Strength */
+#define         AT91_SDRAMC_TIMEOUT             (3 << 12)       /* Time to define when Low Power Mode is enabled */
+#define                 AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES        (0 << 12)
+#define                 AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES       (1 << 12)
+#define                 AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES      (2 << 12)
+
+#define AT91_SDRAMC_IER         (AT91_SDRAMC + 0x14)    /* SDRAM Controller Interrupt Enable Register */
+#define AT91_SDRAMC_IDR         (AT91_SDRAMC + 0x18)    /* SDRAM Controller Interrupt Disable Register */
+#define AT91_SDRAMC_IMR         (AT91_SDRAMC + 0x1C)    /* SDRAM Controller Interrupt Mask Register */
+#define AT91_SDRAMC_ISR         (AT91_SDRAMC + 0x20)    /* SDRAM Controller Interrupt Status Register */
+#define         AT91_SDRAMC_RES         (1 << 0)                /* Refresh Error Status */
+
+#define AT91_SDRAMC_MDR         (AT91_SDRAMC + 0x24)    /* SDRAM Memory Device Register */
+#define         AT91_SDRAMC_MD          (3 << 0)                /* Memory Device Type */
+#define                 AT91_SDRAMC_MD_SDRAM            0
+#define                 AT91_SDRAMC_MD_LOW_POWER_SDRAM  1
+
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
new file mode 100644
index 000000000000..ec6ad1338b5a
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
@@ -0,0 +1,73 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91sam9_smc.h
+ *
+ * Static Memory Controllers (SMC) - System peripherals registers.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9_SMC_H
+#define AT91SAM9_SMC_H
+
+#define AT91_SMC_SETUP(n)       (AT91_SMC + 0x00 + ((n)*0x10))  /* Setup Register for CS n */
+#define         AT91_SMC_NWESETUP       (0x3f << 0)                     /* NWE Setup Length */
+#define                 AT91_SMC_NWESETUP_(x)   ((x) << 0)
+#define         AT91_SMC_NCS_WRSETUP    (0x3f << 8)                     /* NCS Setup Length in Write Access */
+#define                 AT91_SMC_NCS_WRSETUP_(x)        ((x) << 8)
+#define         AT91_SMC_NRDSETUP       (0x3f << 16)                    /* NRD Setup Length */
+#define                 AT91_SMC_NRDSETUP_(x)   ((x) << 16)
+#define         AT91_SMC_NCS_RDSETUP    (0x3f << 24)                    /* NCS Setup Length in Read Access */
+#define                 AT91_SMC_NCS_RDSETUP_(x)        ((x) << 24)
+
+#define AT91_SMC_PULSE(n)       (AT91_SMC + 0x04 + ((n)*0x10))  /* Pulse Register for CS n */
+#define         AT91_SMC_NWEPULSE       (0x7f <<  0)                    /* NWE Pulse Length */
+#define                 AT91_SMC_NWEPULSE_(x)   ((x) << 0)
+#define         AT91_SMC_NCS_WRPULSE    (0x7f <<  8)                    /* NCS Pulse Length in Write Access */
+#define                 AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
+#define         AT91_SMC_NRDPULSE       (0x7f << 16)                    /* NRD Pulse Length */
+#define                 AT91_SMC_NRDPULSE_(x)   ((x) << 16)
+#define         AT91_SMC_NCS_RDPULSE    (0x7f << 24)                    /* NCS Pulse Length in Read Access */
+#define                 AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
+
+#define AT91_SMC_CYCLE(n)       (AT91_SMC + 0x08 + ((n)*0x10))  /* Cycle Register for CS n */
+#define         AT91_SMC_NWECYCLE       (0x1ff << 0 )                   /* Total Write Cycle Length */
+#define                 AT91_SMC_NWECYCLE_(x)   ((x) << 0)
+#define         AT91_SMC_NRDCYCLE       (0x1ff << 16)                   /* Total Read Cycle Length */
+#define                 AT91_SMC_NRDCYCLE_(x)   ((x) << 16)
+
+#define AT91_SMC_MODE(n)        (AT91_SMC + 0x0c + ((n)*0x10))  /* Mode Register for CS n */
+#define         AT91_SMC_READMODE       (1 <<  0)                       /* Read Mode */
+#define         AT91_SMC_WRITEMODE      (1 <<  1)                       /* Write Mode */
+#define         AT91_SMC_EXNWMODE       (3 <<  4)                       /* NWAIT Mode */
+#define                 AT91_SMC_EXNWMODE_DISABLE       (0 << 4)
+#define                 AT91_SMC_EXNWMODE_FROZEN        (2 << 4)
+#define                 AT91_SMC_EXNWMODE_READY         (3 << 4)
+#define         AT91_SMC_BAT            (1 <<  8)                       /* Byte Access Type */
+#define                 AT91_SMC_BAT_SELECT             (0 << 8)
+#define                 AT91_SMC_BAT_WRITE              (1 << 8)
+#define         AT91_SMC_DBW            (3 << 12)                       /* Data Bus Width */
+#define                 AT91_SMC_DBW_8                  (0 << 12)
+#define                 AT91_SMC_DBW_16                 (1 << 12)
+#define                 AT91_SMC_DBW_32                 (2 << 12)
+#define         AT91_SMC_TDF            (0xf << 16)                     /* Data Float Time. */
+#define                 AT91_SMC_TDF_(x)                ((x) << 16)
+#define         AT91_SMC_TDFMODE        (1 << 20)                       /* TDF Optimization - Enabled */
+#define         AT91_SMC_PMEN           (1 << 24)                       /* Page Mode Enabled */
+#define         AT91_SMC_PS             (3 << 28)                       /* Page Size */
+#define                 AT91_SMC_PS_4                   (0 << 28)
+#define                 AT91_SMC_PS_8                   (1 << 28)
+#define                 AT91_SMC_PS_16                  (2 << 28)
+#define                 AT91_SMC_PS_32                  (3 << 28)
+
+#if defined(AT91_SMC1)          /* The AT91SAM9263 has 2 Static Memory contollers */
+#define AT91_SMC1_SETUP(n)      (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
+#define AT91_SMC1_PULSE(n)      (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
+#define AT91_SMC1_CYCLE(n)      (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
+#define AT91_SMC1_MODE(n)       (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
+#endif
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h
new file mode 100644
index 000000000000..fc2de6c09c86
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h
@@ -0,0 +1,115 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91sam9260.h
+ *
+ *  Copyright (C) 2007 Atmel Corporation
+ *
+ * Common definitions.
+ * Based on AT91SAM9RL datasheet revision A. (Preliminary)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+
+#ifndef AT91SAM9RL_H
+#define AT91SAM9RL_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS             1       /* System Controller */
+#define AT91SAM9RL_ID_PIOA      2       /* Parallel IO Controller A */
+#define AT91SAM9RL_ID_PIOB      3       /* Parallel IO Controller B */
+#define AT91SAM9RL_ID_PIOC      4       /* Parallel IO Controller C */
+#define AT91SAM9RL_ID_PIOD      5       /* Parallel IO Controller D */
+#define AT91SAM9RL_ID_US0       6       /* USART 0 */
+#define AT91SAM9RL_ID_US1       7       /* USART 1 */
+#define AT91SAM9RL_ID_US2       8       /* USART 2 */
+#define AT91SAM9RL_ID_US3       9       /* USART 3 */
+#define AT91SAM9RL_ID_MCI       10      /* Multimedia Card Interface */
+#define AT91SAM9RL_ID_TWI0      11      /* TWI 0 */
+#define AT91SAM9RL_ID_TWI1      12      /* TWI 1 */
+#define AT91SAM9RL_ID_SPI       13      /* Serial Peripheral Interface */
+#define AT91SAM9RL_ID_SSC0      14      /* Serial Synchronous Controller 0 */
+#define AT91SAM9RL_ID_SSC1      15      /* Serial Synchronous Controller 1 */
+#define AT91SAM9RL_ID_TC0       16      /* Timer Counter 0 */
+#define AT91SAM9RL_ID_TC1       17      /* Timer Counter 1 */
+#define AT91SAM9RL_ID_TC2       18      /* Timer Counter 2 */
+#define AT91SAM9RL_ID_PWMC      19      /* Pulse Width Modulation Controller */
+#define AT91SAM9RL_ID_TSC       20      /* Touch Screen Controller */
+#define AT91SAM9RL_ID_DMA       21      /* DMA Controller */
+#define AT91SAM9RL_ID_UDPHS     22      /* USB Device HS */
+#define AT91SAM9RL_ID_LCDC      23      /* LCD Controller */
+#define AT91SAM9RL_ID_AC97C     24      /* AC97 Controller */
+#define AT91SAM9RL_ID_IRQ0      31      /* Advanced Interrupt Controller (IRQ0) */
+
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT91SAM9RL_BASE_TCB0    0xfffa0000
+#define AT91SAM9RL_BASE_TC0     0xfffa0000
+#define AT91SAM9RL_BASE_TC1     0xfffa0040
+#define AT91SAM9RL_BASE_TC2     0xfffa0080
+#define AT91SAM9RL_BASE_MCI     0xfffa4000
+#define AT91SAM9RL_BASE_TWI0    0xfffa8000
+#define AT91SAM9RL_BASE_TWI1    0xfffac000
+#define AT91SAM9RL_BASE_US0     0xfffb0000
+#define AT91SAM9RL_BASE_US1     0xfffb4000
+#define AT91SAM9RL_BASE_US2     0xfffb8000
+#define AT91SAM9RL_BASE_US3     0xfffbc000
+#define AT91SAM9RL_BASE_SSC0    0xfffc0000
+#define AT91SAM9RL_BASE_SSC1    0xfffc4000
+#define AT91SAM9RL_BASE_PWMC    0xfffc8000
+#define AT91SAM9RL_BASE_SPI     0xfffcc000
+#define AT91SAM9RL_BASE_TSC     0xfffd0000
+#define AT91SAM9RL_BASE_UDPHS   0xfffd4000
+#define AT91SAM9RL_BASE_AC97C   0xfffd8000
+#define AT91_BASE_SYS           0xffffc000
+
+
+/*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_DMA        (0xffffe600 - AT91_BASE_SYS)
+#define AT91_ECC        (0xffffe800 - AT91_BASE_SYS)
+#define AT91_SDRAMC     (0xffffea00 - AT91_BASE_SYS)
+#define AT91_SMC        (0xffffec00 - AT91_BASE_SYS)
+#define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
+#define AT91_CCFG       (0xffffef10 - AT91_BASE_SYS)
+#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
+#define AT91_DBGU       (0xfffff200 - AT91_BASE_SYS)
+#define AT91_PIOA       (0xfffff400 - AT91_BASE_SYS)
+#define AT91_PIOB       (0xfffff600 - AT91_BASE_SYS)
+#define AT91_PIOC       (0xfffff800 - AT91_BASE_SYS)
+#define AT91_PIOD       (0xfffffa00 - AT91_BASE_SYS)
+#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
+#define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
+#define AT91_SHDWC      (0xfffffd10 - AT91_BASE_SYS)
+#define AT91_RTT        (0xfffffd20 - AT91_BASE_SYS)
+#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
+#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_SCKCR      (0xfffffd50 - AT91_BASE_SYS)
+#define AT91_GPBR       (0xfffffd60 - AT91_BASE_SYS)
+#define AT91_RTC        (0xfffffe00 - AT91_BASE_SYS)
+
+#define AT91_USART0     AT91SAM9RL_BASE_US0
+#define AT91_USART1     AT91SAM9RL_BASE_US1
+#define AT91_USART2     AT91SAM9RL_BASE_US2
+#define AT91_USART3     AT91SAM9RL_BASE_US3
+
+
+/*
+ * Internal Memory.
+ */
+#define AT91SAM9RL_SRAM_BASE    0x00300000      /* Internal SRAM base address */
+#define AT91SAM9RL_SRAM_SIZE    SZ_16K          /* Internal SRAM size (16Kb) */
+
+#define AT91SAM9RL_ROM_BASE     0x00400000      /* Internal ROM base address */
+#define AT91SAM9RL_ROM_SIZE     (2 * SZ_16K)    /* Internal ROM size (32Kb) */
+
+#define AT91SAM9RL_LCDC_BASE    0x00500000      /* LCD Controller */
+#define AT91SAM9RL_UDPHS_FIFO   0x00600000      /* USB Device HS controller */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
new file mode 100644
index 000000000000..5f9149071fe5
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
@@ -0,0 +1,96 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
+ *
+ *  Copyright (C) 2007 Atmel Corporation
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91SAM9RL datasheet revision A. (Preliminary)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+
+#ifndef AT91SAM9RL_MATRIX_H
+#define AT91SAM9RL_MATRIX_H
+
+#define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
+#define         AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
+#define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
+#define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
+#define                 AT91_MATRIX_ULBT_FOUR           (2 << 0)
+#define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
+#define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
+
+#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
+#define AT91_MATRIX_SCFG5       (AT91_MATRIX + 0x54)    /* Slave Configuration Register 5 */
+#define         AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
+#define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
+#define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
+#define         AT91_MATRIX_FIXED_DEFMSTR       (0xf  << 18)    /* Fixed Index of Default Master */
+#define         AT91_MATRIX_ARBT                (3    << 24)    /* Arbitration Type */
+#define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
+#define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
+
+#define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
+#define AT91_MATRIX_PRAS5       (AT91_MATRIX + 0xA8)    /* Priority Register A for Slave 5 */
+#define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
+#define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
+#define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
+#define         AT91_MATRIX_M3PR                (3 << 12)       /* Master 3 Priority */
+#define         AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
+#define         AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
+
+#define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
+#define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define         AT91_MATRIX_RCB2                (1 << 2)
+#define         AT91_MATRIX_RCB3                (1 << 3)
+#define         AT91_MATRIX_RCB4                (1 << 4)
+#define         AT91_MATRIX_RCB5                (1 << 5)
+
+#define AT91_MATRIX_TCMR        (AT91_MATRIX + 0x114)   /* TCM Configuration Register */
+#define         AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
+#define                 AT91_MATRIX_ITCM_0              (0 << 0)
+#define                 AT91_MATRIX_ITCM_16             (5 << 0)
+#define                 AT91_MATRIX_ITCM_32             (6 << 0)
+#define         AT91_MATRIX_DTCM_SIZE           (0xf << 4)      /* Size of DTCM enabled memory block */
+#define                 AT91_MATRIX_DTCM_0              (0 << 4)
+#define                 AT91_MATRIX_DTCM_16             (5 << 4)
+#define                 AT91_MATRIX_DTCM_32             (6 << 4)
+
+#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x120)   /* EBI0 Chip Select Assignment Register */
+#define         AT91_MATRIX_CS1A                (1 << 1)        /* Chip Select 1 Assignment */
+#define                 AT91_MATRIX_CS1A_SMC            (0 << 1)
+#define                 AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
+#define         AT91_MATRIX_CS3A                (1 << 3)        /* Chip Select 3 Assignment */
+#define                 AT91_MATRIX_CS3A_SMC            (0 << 3)
+#define                 AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define         AT91_MATRIX_CS4A                (1 << 4)        /* Chip Select 4 Assignment */
+#define                 AT91_MATRIX_CS4A_SMC            (0 << 4)
+#define                 AT91_MATRIX_CS4A_SMC_CF1        (1 << 4)
+#define         AT91_MATRIX_CS5A                (1 << 5)        /* Chip Select 5 Assignment */
+#define                 AT91_MATRIX_CS5A_SMC            (0 << 5)
+#define                 AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
+#define         AT91_MATRIX_DBPUC               (1 << 8)        /* Data Bus Pull-up Configuration */
+#define         AT91_MATRIX_VDDIOMSEL           (1 << 16)       /* Memory voltage selection */
+#define                 AT91_MATRIX_VDDIOMSEL_1_8V      (0 << 16)
+#define                 AT91_MATRIX_VDDIOMSEL_3_3V      (1 << 16)
+
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91x40.h b/arch/arm/mach-at91/include/mach/at91x40.h
new file mode 100644
index 000000000000..d34cdb8abdca
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91x40.h
@@ -0,0 +1,55 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91x40.h
+ *
+ * (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91X40_H
+#define AT91X40_H
+
+/*
+ *      IRQ list.
+ */
+#define AT91_ID_FIQ             0       /* FIQ */
+#define AT91_ID_SYS             1       /* System Peripheral */
+#define AT91X40_ID_USART0       2       /* USART port 0 */
+#define AT91X40_ID_USART1       3       /* USART port 1 */
+#define AT91X40_ID_TC0          4       /* Timer/Counter 0 */
+#define AT91X40_ID_TC1          5       /* Timer/Counter 1*/
+#define AT91X40_ID_TC2          6       /* Timer/Counter 2*/
+#define AT91X40_ID_WD           7       /* Watchdog? */
+#define AT91X40_ID_PIOA         8       /* Parallel IO Controller A */
+
+#define AT91X40_ID_IRQ0         16      /* External IRQ 0 */
+#define AT91X40_ID_IRQ1         17      /* External IRQ 1 */
+#define AT91X40_ID_IRQ2         18      /* External IRQ 2 */
+
+/*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_BASE_SYS   0xffc00000
+
+#define AT91_EBI        (0xffe00000 - AT91_BASE_SYS)    /* External Bus Interface */
+#define AT91_SF         (0xfff00000 - AT91_BASE_SYS)    /* Special Function */
+#define AT91_USART1     (0xfffcc000 - AT91_BASE_SYS)    /* USART 1 */
+#define AT91_USART0     (0xfffd0000 - AT91_BASE_SYS)    /* USART 0 */
+#define AT91_TC         (0xfffe0000 - AT91_BASE_SYS)    /* Timer Counter */
+#define AT91_PIOA       (0xffff0000 - AT91_BASE_SYS)    /* PIO Controller A */
+#define AT91_PS         (0xffff4000 - AT91_BASE_SYS)    /* Power Save */
+#define AT91_WD         (0xffff8000 - AT91_BASE_SYS)    /* Watchdog Timer */
+#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)    /* Advanced Interrupt Controller */
+
+/*
+ * The AT91x40 series doesn't have a debug unit like the other AT91 parts.
+ * But it does have a chip identify register and extension ID, so define at
+ * least these here.
+ */
+#define AT91_DBGU_CIDR  (AT91_SF + 0)   /* CIDR in PS segment */
+#define AT91_DBGU_EXID  (AT91_SF + 4)   /* EXID in PS segment */
+
+#endif /* AT91X40_H */
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
new file mode 100644
index 000000000000..acd60f2a0724
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -0,0 +1,172 @@
+/*
+ * arch/arm/mach-at91/include/mach/board.h
+ *
+ *  Copyright (C) 2005 HP Labs
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/*
+ * These are data structures found in platform_device.dev.platform_data,
+ * and describing board-specific data needed by drivers.  For example,
+ * which pin is used for a given GPIO role.
+ *
+ * In 2.6, drivers should strongly avoid board-specific knowledge so
+ * that supporting new boards normally won't require driver patches.
+ * Most board-specific knowledge should be in arch/.../board-*.c files.
+ */
+
+#ifndef __ASM_ARCH_BOARD_H
+#define __ASM_ARCH_BOARD_H
+
+#include <linux/mtd/partitions.h>
+#include <linux/device.h>
+#include <linux/i2c.h>
+#include <linux/leds.h>
+#include <linux/spi/spi.h>
+#include <linux/usb/atmel_usba_udc.h>
+
+ /* USB Device */
+struct at91_udc_data {
+        u8      vbus_pin;               /* high == host powering us */
+        u8      pullup_pin;             /* active == D+ pulled up */
+        u8      pullup_active_low;      /* true == pullup_pin is active low */
+};
+extern void __init at91_add_device_udc(struct at91_udc_data *data);
+
+ /* USB High Speed Device */
+extern void __init at91_add_device_usba(struct usba_platform_data *data);
+
+ /* Compact Flash */
+struct at91_cf_data {
+        u8      irq_pin;                /* I/O IRQ */
+        u8      det_pin;                /* Card detect */
+        u8      vcc_pin;                /* power switching */
+        u8      rst_pin;                /* card reset */
+        u8      chipselect;             /* EBI Chip Select number */
+};
+extern void __init at91_add_device_cf(struct at91_cf_data *data);
+
+ /* MMC / SD */
+struct at91_mmc_data {
+        u8              det_pin;        /* card detect IRQ */
+        unsigned        slot_b:1;       /* uses Slot B */
+        unsigned        wire4:1;        /* (SD) supports DAT0..DAT3 */
+        u8              wp_pin;         /* (SD) writeprotect detect */
+        u8              vcc_pin;        /* power switching (high == on) */
+};
+extern void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data);
+
+ /* Ethernet (EMAC & MACB) */
+struct at91_eth_data {
+        u32             phy_mask;
+        u8              phy_irq_pin;    /* PHY IRQ */
+        u8              is_rmii;        /* using RMII interface? */
+};
+extern void __init at91_add_device_eth(struct at91_eth_data *data);
+
+#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9)
+#define eth_platform_data       at91_eth_data
+#endif
+
+ /* USB Host */
+struct at91_usbh_data {
+        u8              ports;          /* number of ports on root hub */
+        u8              vbus_pin[];     /* port power-control pin */
+};
+extern void __init at91_add_device_usbh(struct at91_usbh_data *data);
+
+ /* NAND / SmartMedia */
+struct atmel_nand_data {
+        u8              enable_pin;     /* chip enable */
+        u8              det_pin;        /* card detect */
+        u8              rdy_pin;        /* ready/busy */
+        u8              ale;            /* address line number connected to ALE */
+        u8              cle;            /* address line number connected to CLE */
+        u8              bus_width_16;   /* buswidth is 16 bit */
+        struct mtd_partition* (*partition_info)(int, int*);
+};
+extern void __init at91_add_device_nand(struct atmel_nand_data *data);
+
+ /* I2C*/
+extern void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices);
+
+ /* SPI */
+extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices);
+
+ /* Serial */
+#define ATMEL_UART_CTS  0x01
+#define ATMEL_UART_RTS  0x02
+#define ATMEL_UART_DSR  0x04
+#define ATMEL_UART_DTR  0x08
+#define ATMEL_UART_DCD  0x10
+#define ATMEL_UART_RI   0x20
+
+extern void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins);
+extern void __init at91_set_serial_console(unsigned portnr);
+
+struct at91_uart_config {
+        unsigned short  console_tty;    /* tty number of serial console */
+        unsigned short  nr_tty;         /* number of serial tty's */
+        short           tty_map[];      /* map UART to tty number */
+};
+extern struct platform_device *atmel_default_console_device;
+extern void __init __deprecated at91_init_serial(struct at91_uart_config *config);
+
+struct atmel_uart_data {
+        short           use_dma_tx;     /* use transmit DMA? */
+        short           use_dma_rx;     /* use receive DMA? */
+        void __iomem    *regs;          /* virtual base address, if any */
+};
+extern void __init at91_add_device_serial(void);
+
+/*
+ * SSC -- accessed through ssc_request(id).  Drivers don't bind to SSC
+ * platform devices.  Their SSC ID is part of their configuration data,
+ * along with information about which SSC signals they should use.
+ */
+#define ATMEL_SSC_TK    0x01
+#define ATMEL_SSC_TF    0x02
+#define ATMEL_SSC_TD    0x04
+#define ATMEL_SSC_TX    (ATMEL_SSC_TK | ATMEL_SSC_TF | ATMEL_SSC_TD)
+
+#define ATMEL_SSC_RK    0x10
+#define ATMEL_SSC_RF    0x20
+#define ATMEL_SSC_RD    0x40
+#define ATMEL_SSC_RX    (ATMEL_SSC_RK | ATMEL_SSC_RF | ATMEL_SSC_RD)
+
+extern void __init at91_add_device_ssc(unsigned id, unsigned pins);
+
+ /* LCD Controller */
+struct atmel_lcdfb_info;
+extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data);
+
+ /* AC97 */
+struct atmel_ac97_data {
+        u8              reset_pin;      /* reset */
+};
+extern void __init at91_add_device_ac97(struct atmel_ac97_data *data);
+
+ /* ISI */
+extern void __init at91_add_device_isi(void);
+
+ /* LEDs */
+extern void __init at91_init_leds(u8 cpu_led, u8 timer_led);
+extern void __init at91_gpio_leds(struct gpio_led *leds, int nr);
+
+/* FIXME: this needs a better location, but gets stuff building again */
+extern int at91_suspend_entering_slow_clock(void);
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
new file mode 100644
index 000000000000..dbfd9f73f80b
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -0,0 +1,103 @@
+/*
+ * arch/arm/mach-at91/include/mach/cpu.h
+ *
+ *  Copyright (C) 2006 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_CPU_H
+#define __ASM_ARCH_CPU_H
+
+#include <mach/hardware.h>
+#include <mach/at91_dbgu.h>
+
+
+#define ARCH_ID_AT91RM9200      0x09290780
+#define ARCH_ID_AT91SAM9260     0x019803a0
+#define ARCH_ID_AT91SAM9261     0x019703a0
+#define ARCH_ID_AT91SAM9263     0x019607a0
+#define ARCH_ID_AT91SAM9G20     0x019905a0
+#define ARCH_ID_AT91SAM9RL64    0x019b03a0
+#define ARCH_ID_AT91CAP9        0x039A03A0
+
+#define ARCH_ID_AT91SAM9XE128   0x329973a0
+#define ARCH_ID_AT91SAM9XE256   0x329a93a0
+#define ARCH_ID_AT91SAM9XE512   0x329aa3a0
+
+#define ARCH_ID_AT91M40800      0x14080044
+#define ARCH_ID_AT91R40807      0x44080746
+#define ARCH_ID_AT91M40807      0x14080745
+#define ARCH_ID_AT91R40008      0x44000840
+
+static inline unsigned long at91_cpu_identify(void)
+{
+        return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION);
+}
+
+
+#define ARCH_FAMILY_AT91X92     0x09200000
+#define ARCH_FAMILY_AT91SAM9    0x01900000
+#define ARCH_FAMILY_AT91SAM9XE  0x02900000
+
+static inline unsigned long at91_arch_identify(void)
+{
+        return (at91_sys_read(AT91_DBGU_CIDR) & AT91_CIDR_ARCH);
+}
+
+
+#ifdef CONFIG_ARCH_AT91RM9200
+#define cpu_is_at91rm9200()     (at91_cpu_identify() == ARCH_ID_AT91RM9200)
+#else
+#define cpu_is_at91rm9200()     (0)
+#endif
+
+#ifdef CONFIG_ARCH_AT91SAM9260
+#define cpu_is_at91sam9xe()     (at91_arch_identify() == ARCH_FAMILY_AT91SAM9XE)
+#define cpu_is_at91sam9260()    ((at91_cpu_identify() == ARCH_ID_AT91SAM9260) || cpu_is_at91sam9xe())
+#else
+#define cpu_is_at91sam9xe()     (0)
+#define cpu_is_at91sam9260()    (0)
+#endif
+
+#ifdef CONFIG_ARCH_AT91SAM9G20
+#define cpu_is_at91sam9g20()    (at91_cpu_identify() == ARCH_ID_AT91SAM9G20)
+#else
+#define cpu_is_at91sam9g20()    (0)
+#endif
+
+#ifdef CONFIG_ARCH_AT91SAM9261
+#define cpu_is_at91sam9261()    (at91_cpu_identify() == ARCH_ID_AT91SAM9261)
+#else
+#define cpu_is_at91sam9261()    (0)
+#endif
+
+#ifdef CONFIG_ARCH_AT91SAM9263
+#define cpu_is_at91sam9263()    (at91_cpu_identify() == ARCH_ID_AT91SAM9263)
+#else
+#define cpu_is_at91sam9263()    (0)
+#endif
+
+#ifdef CONFIG_ARCH_AT91SAM9RL
+#define cpu_is_at91sam9rl()     (at91_cpu_identify() == ARCH_ID_AT91SAM9RL64)
+#else
+#define cpu_is_at91sam9rl()     (0)
+#endif
+
+#ifdef CONFIG_ARCH_AT91CAP9
+#define cpu_is_at91cap9()       (at91_cpu_identify() == ARCH_ID_AT91CAP9)
+#else
+#define cpu_is_at91cap9()       (0)
+#endif
+
+/*
+ * Since this is ARM, we will never run on any AVR32 CPU. But these
+ * definitions may reduce clutter in common drivers.
+ */
+#define cpu_is_at32ap7000()     (0)
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/debug-macro.S b/arch/arm/mach-at91/include/mach/debug-macro.S
new file mode 100644
index 000000000000..29052ba66ada
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/debug-macro.S
@@ -0,0 +1,39 @@
+/*
+ * arch/arm/mach-at91/include/mach/debug-macro.S
+ *
+ *  Copyright (C) 2003-2005 SAN People
+ *
+ * Debugging macro include header
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <mach/hardware.h>
+#include <mach/at91_dbgu.h>
+
+        .macro  addruart,rx
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1                                         @ MMU enabled?
+        ldreq   \rx, =(AT91_BASE_SYS + AT91_DBGU)               @ System peripherals (phys address)
+        ldrne   \rx, =(AT91_VA_BASE_SYS + AT91_DBGU)            @ System peripherals (virt address)
+        .endm
+
+        .macro  senduart,rd,rx
+        strb    \rd, [\rx, #(AT91_DBGU_THR - AT91_DBGU)]        @ Write to Transmitter Holding Register
+        .endm
+
+        .macro  waituart,rd,rx
+1001:   ldr     \rd, [\rx, #(AT91_DBGU_SR - AT91_DBGU)]         @ Read Status Register
+        tst     \rd, #AT91_DBGU_TXRDY                           @ DBGU_TXRDY = 1 when ready to transmit
+        beq     1001b
+        .endm
+
+        .macro  busyuart,rd,rx
+1001:   ldr     \rd, [\rx, #(AT91_DBGU_SR - AT91_DBGU)]         @ Read Status Register
+        tst     \rd, #AT91_DBGU_TXEMPTY                         @ DBGU_TXEMPTY = 1 when transmission complete
+        beq     1001b
+        .endm
+
diff --git a/arch/arm/mach-at91/include/mach/dma.h b/arch/arm/mach-at91/include/mach/dma.h
new file mode 100644
index 000000000000..e4f90c177616
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/dma.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-at91/include/mach/dma.h
+ *
+ *  Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
diff --git a/arch/arm/mach-at91/include/mach/entry-macro.S b/arch/arm/mach-at91/include/mach/entry-macro.S
new file mode 100644
index 000000000000..7ab68f972227
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/entry-macro.S
@@ -0,0 +1,32 @@
+/*
+ * arch/arm/mach-at91/include/mach/entry-macro.S
+ *
+ *  Copyright (C) 2003-2005 SAN People
+ *
+ * Low-level IRQ helper macros for AT91RM9200 platforms
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <mach/hardware.h>
+#include <mach/at91_aic.h>
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =(AT91_VA_BASE_SYS + AT91_AIC)           @ base virtual address of AIC peripheral
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        ldr     \irqnr, [\base, #(AT91_AIC_IVR - AT91_AIC)]     @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
+        ldr     \irqstat, [\base, #(AT91_AIC_ISR - AT91_AIC)]   @ read interrupt source number
+        teq     \irqstat, #0                                    @ ISR is 0 when no current interrupt, or spurious interrupt
+        streq   \tmp, [\base, #(AT91_AIC_EOICR - AT91_AIC)]     @ not going to be handled further, then ACK it now.
+        .endm
+
diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h
new file mode 100644
index 000000000000..76d76e2fa69e
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/gpio.h
@@ -0,0 +1,252 @@
+/*
+ * arch/arm/mach-at91/include/mach/gpio.h
+ *
+ *  Copyright (C) 2005 HP Labs
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_AT91RM9200_GPIO_H
+#define __ASM_ARCH_AT91RM9200_GPIO_H
+
+#include <asm/irq.h>
+
+#define PIN_BASE                NR_AIC_IRQS
+
+#define MAX_GPIO_BANKS          5
+
+/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
+
+#define AT91_PIN_PA0    (PIN_BASE + 0x00 + 0)
+#define AT91_PIN_PA1    (PIN_BASE + 0x00 + 1)
+#define AT91_PIN_PA2    (PIN_BASE + 0x00 + 2)
+#define AT91_PIN_PA3    (PIN_BASE + 0x00 + 3)
+#define AT91_PIN_PA4    (PIN_BASE + 0x00 + 4)
+#define AT91_PIN_PA5    (PIN_BASE + 0x00 + 5)
+#define AT91_PIN_PA6    (PIN_BASE + 0x00 + 6)
+#define AT91_PIN_PA7    (PIN_BASE + 0x00 + 7)
+#define AT91_PIN_PA8    (PIN_BASE + 0x00 + 8)
+#define AT91_PIN_PA9    (PIN_BASE + 0x00 + 9)
+#define AT91_PIN_PA10   (PIN_BASE + 0x00 + 10)
+#define AT91_PIN_PA11   (PIN_BASE + 0x00 + 11)
+#define AT91_PIN_PA12   (PIN_BASE + 0x00 + 12)
+#define AT91_PIN_PA13   (PIN_BASE + 0x00 + 13)
+#define AT91_PIN_PA14   (PIN_BASE + 0x00 + 14)
+#define AT91_PIN_PA15   (PIN_BASE + 0x00 + 15)
+#define AT91_PIN_PA16   (PIN_BASE + 0x00 + 16)
+#define AT91_PIN_PA17   (PIN_BASE + 0x00 + 17)
+#define AT91_PIN_PA18   (PIN_BASE + 0x00 + 18)
+#define AT91_PIN_PA19   (PIN_BASE + 0x00 + 19)
+#define AT91_PIN_PA20   (PIN_BASE + 0x00 + 20)
+#define AT91_PIN_PA21   (PIN_BASE + 0x00 + 21)
+#define AT91_PIN_PA22   (PIN_BASE + 0x00 + 22)
+#define AT91_PIN_PA23   (PIN_BASE + 0x00 + 23)
+#define AT91_PIN_PA24   (PIN_BASE + 0x00 + 24)
+#define AT91_PIN_PA25   (PIN_BASE + 0x00 + 25)
+#define AT91_PIN_PA26   (PIN_BASE + 0x00 + 26)
+#define AT91_PIN_PA27   (PIN_BASE + 0x00 + 27)
+#define AT91_PIN_PA28   (PIN_BASE + 0x00 + 28)
+#define AT91_PIN_PA29   (PIN_BASE + 0x00 + 29)
+#define AT91_PIN_PA30   (PIN_BASE + 0x00 + 30)
+#define AT91_PIN_PA31   (PIN_BASE + 0x00 + 31)
+
+#define AT91_PIN_PB0    (PIN_BASE + 0x20 + 0)
+#define AT91_PIN_PB1    (PIN_BASE + 0x20 + 1)
+#define AT91_PIN_PB2    (PIN_BASE + 0x20 + 2)
+#define AT91_PIN_PB3    (PIN_BASE + 0x20 + 3)
+#define AT91_PIN_PB4    (PIN_BASE + 0x20 + 4)
+#define AT91_PIN_PB5    (PIN_BASE + 0x20 + 5)
+#define AT91_PIN_PB6    (PIN_BASE + 0x20 + 6)
+#define AT91_PIN_PB7    (PIN_BASE + 0x20 + 7)
+#define AT91_PIN_PB8    (PIN_BASE + 0x20 + 8)
+#define AT91_PIN_PB9    (PIN_BASE + 0x20 + 9)
+#define AT91_PIN_PB10   (PIN_BASE + 0x20 + 10)
+#define AT91_PIN_PB11   (PIN_BASE + 0x20 + 11)
+#define AT91_PIN_PB12   (PIN_BASE + 0x20 + 12)
+#define AT91_PIN_PB13   (PIN_BASE + 0x20 + 13)
+#define AT91_PIN_PB14   (PIN_BASE + 0x20 + 14)
+#define AT91_PIN_PB15   (PIN_BASE + 0x20 + 15)
+#define AT91_PIN_PB16   (PIN_BASE + 0x20 + 16)
+#define AT91_PIN_PB17   (PIN_BASE + 0x20 + 17)
+#define AT91_PIN_PB18   (PIN_BASE + 0x20 + 18)
+#define AT91_PIN_PB19   (PIN_BASE + 0x20 + 19)
+#define AT91_PIN_PB20   (PIN_BASE + 0x20 + 20)
+#define AT91_PIN_PB21   (PIN_BASE + 0x20 + 21)
+#define AT91_PIN_PB22   (PIN_BASE + 0x20 + 22)
+#define AT91_PIN_PB23   (PIN_BASE + 0x20 + 23)
+#define AT91_PIN_PB24   (PIN_BASE + 0x20 + 24)
+#define AT91_PIN_PB25   (PIN_BASE + 0x20 + 25)
+#define AT91_PIN_PB26   (PIN_BASE + 0x20 + 26)
+#define AT91_PIN_PB27   (PIN_BASE + 0x20 + 27)
+#define AT91_PIN_PB28   (PIN_BASE + 0x20 + 28)
+#define AT91_PIN_PB29   (PIN_BASE + 0x20 + 29)
+#define AT91_PIN_PB30   (PIN_BASE + 0x20 + 30)
+#define AT91_PIN_PB31   (PIN_BASE + 0x20 + 31)
+
+#define AT91_PIN_PC0    (PIN_BASE + 0x40 + 0)
+#define AT91_PIN_PC1    (PIN_BASE + 0x40 + 1)
+#define AT91_PIN_PC2    (PIN_BASE + 0x40 + 2)
+#define AT91_PIN_PC3    (PIN_BASE + 0x40 + 3)
+#define AT91_PIN_PC4    (PIN_BASE + 0x40 + 4)
+#define AT91_PIN_PC5    (PIN_BASE + 0x40 + 5)
+#define AT91_PIN_PC6    (PIN_BASE + 0x40 + 6)
+#define AT91_PIN_PC7    (PIN_BASE + 0x40 + 7)
+#define AT91_PIN_PC8    (PIN_BASE + 0x40 + 8)
+#define AT91_PIN_PC9    (PIN_BASE + 0x40 + 9)
+#define AT91_PIN_PC10   (PIN_BASE + 0x40 + 10)
+#define AT91_PIN_PC11   (PIN_BASE + 0x40 + 11)
+#define AT91_PIN_PC12   (PIN_BASE + 0x40 + 12)
+#define AT91_PIN_PC13   (PIN_BASE + 0x40 + 13)
+#define AT91_PIN_PC14   (PIN_BASE + 0x40 + 14)
+#define AT91_PIN_PC15   (PIN_BASE + 0x40 + 15)
+#define AT91_PIN_PC16   (PIN_BASE + 0x40 + 16)
+#define AT91_PIN_PC17   (PIN_BASE + 0x40 + 17)
+#define AT91_PIN_PC18   (PIN_BASE + 0x40 + 18)
+#define AT91_PIN_PC19   (PIN_BASE + 0x40 + 19)
+#define AT91_PIN_PC20   (PIN_BASE + 0x40 + 20)
+#define AT91_PIN_PC21   (PIN_BASE + 0x40 + 21)
+#define AT91_PIN_PC22   (PIN_BASE + 0x40 + 22)
+#define AT91_PIN_PC23   (PIN_BASE + 0x40 + 23)
+#define AT91_PIN_PC24   (PIN_BASE + 0x40 + 24)
+#define AT91_PIN_PC25   (PIN_BASE + 0x40 + 25)
+#define AT91_PIN_PC26   (PIN_BASE + 0x40 + 26)
+#define AT91_PIN_PC27   (PIN_BASE + 0x40 + 27)
+#define AT91_PIN_PC28   (PIN_BASE + 0x40 + 28)
+#define AT91_PIN_PC29   (PIN_BASE + 0x40 + 29)
+#define AT91_PIN_PC30   (PIN_BASE + 0x40 + 30)
+#define AT91_PIN_PC31   (PIN_BASE + 0x40 + 31)
+
+#define AT91_PIN_PD0    (PIN_BASE + 0x60 + 0)
+#define AT91_PIN_PD1    (PIN_BASE + 0x60 + 1)
+#define AT91_PIN_PD2    (PIN_BASE + 0x60 + 2)
+#define AT91_PIN_PD3    (PIN_BASE + 0x60 + 3)
+#define AT91_PIN_PD4    (PIN_BASE + 0x60 + 4)
+#define AT91_PIN_PD5    (PIN_BASE + 0x60 + 5)
+#define AT91_PIN_PD6    (PIN_BASE + 0x60 + 6)
+#define AT91_PIN_PD7    (PIN_BASE + 0x60 + 7)
+#define AT91_PIN_PD8    (PIN_BASE + 0x60 + 8)
+#define AT91_PIN_PD9    (PIN_BASE + 0x60 + 9)
+#define AT91_PIN_PD10   (PIN_BASE + 0x60 + 10)
+#define AT91_PIN_PD11   (PIN_BASE + 0x60 + 11)
+#define AT91_PIN_PD12   (PIN_BASE + 0x60 + 12)
+#define AT91_PIN_PD13   (PIN_BASE + 0x60 + 13)
+#define AT91_PIN_PD14   (PIN_BASE + 0x60 + 14)
+#define AT91_PIN_PD15   (PIN_BASE + 0x60 + 15)
+#define AT91_PIN_PD16   (PIN_BASE + 0x60 + 16)
+#define AT91_PIN_PD17   (PIN_BASE + 0x60 + 17)
+#define AT91_PIN_PD18   (PIN_BASE + 0x60 + 18)
+#define AT91_PIN_PD19   (PIN_BASE + 0x60 + 19)
+#define AT91_PIN_PD20   (PIN_BASE + 0x60 + 20)
+#define AT91_PIN_PD21   (PIN_BASE + 0x60 + 21)
+#define AT91_PIN_PD22   (PIN_BASE + 0x60 + 22)
+#define AT91_PIN_PD23   (PIN_BASE + 0x60 + 23)
+#define AT91_PIN_PD24   (PIN_BASE + 0x60 + 24)
+#define AT91_PIN_PD25   (PIN_BASE + 0x60 + 25)
+#define AT91_PIN_PD26   (PIN_BASE + 0x60 + 26)
+#define AT91_PIN_PD27   (PIN_BASE + 0x60 + 27)
+#define AT91_PIN_PD28   (PIN_BASE + 0x60 + 28)
+#define AT91_PIN_PD29   (PIN_BASE + 0x60 + 29)
+#define AT91_PIN_PD30   (PIN_BASE + 0x60 + 30)
+#define AT91_PIN_PD31   (PIN_BASE + 0x60 + 31)
+
+#define AT91_PIN_PE0    (PIN_BASE + 0x80 + 0)
+#define AT91_PIN_PE1    (PIN_BASE + 0x80 + 1)
+#define AT91_PIN_PE2    (PIN_BASE + 0x80 + 2)
+#define AT91_PIN_PE3    (PIN_BASE + 0x80 + 3)
+#define AT91_PIN_PE4    (PIN_BASE + 0x80 + 4)
+#define AT91_PIN_PE5    (PIN_BASE + 0x80 + 5)
+#define AT91_PIN_PE6    (PIN_BASE + 0x80 + 6)
+#define AT91_PIN_PE7    (PIN_BASE + 0x80 + 7)
+#define AT91_PIN_PE8    (PIN_BASE + 0x80 + 8)
+#define AT91_PIN_PE9    (PIN_BASE + 0x80 + 9)
+#define AT91_PIN_PE10   (PIN_BASE + 0x80 + 10)
+#define AT91_PIN_PE11   (PIN_BASE + 0x80 + 11)
+#define AT91_PIN_PE12   (PIN_BASE + 0x80 + 12)
+#define AT91_PIN_PE13   (PIN_BASE + 0x80 + 13)
+#define AT91_PIN_PE14   (PIN_BASE + 0x80 + 14)
+#define AT91_PIN_PE15   (PIN_BASE + 0x80 + 15)
+#define AT91_PIN_PE16   (PIN_BASE + 0x80 + 16)
+#define AT91_PIN_PE17   (PIN_BASE + 0x80 + 17)
+#define AT91_PIN_PE18   (PIN_BASE + 0x80 + 18)
+#define AT91_PIN_PE19   (PIN_BASE + 0x80 + 19)
+#define AT91_PIN_PE20   (PIN_BASE + 0x80 + 20)
+#define AT91_PIN_PE21   (PIN_BASE + 0x80 + 21)
+#define AT91_PIN_PE22   (PIN_BASE + 0x80 + 22)
+#define AT91_PIN_PE23   (PIN_BASE + 0x80 + 23)
+#define AT91_PIN_PE24   (PIN_BASE + 0x80 + 24)
+#define AT91_PIN_PE25   (PIN_BASE + 0x80 + 25)
+#define AT91_PIN_PE26   (PIN_BASE + 0x80 + 26)
+#define AT91_PIN_PE27   (PIN_BASE + 0x80 + 27)
+#define AT91_PIN_PE28   (PIN_BASE + 0x80 + 28)
+#define AT91_PIN_PE29   (PIN_BASE + 0x80 + 29)
+#define AT91_PIN_PE30   (PIN_BASE + 0x80 + 30)
+#define AT91_PIN_PE31   (PIN_BASE + 0x80 + 31)
+
+#ifndef __ASSEMBLY__
+/* setup setup routines, called from board init or driver probe() */
+extern int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup);
+extern int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup);
+extern int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup);
+extern int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup);
+extern int __init_or_module at91_set_gpio_output(unsigned pin, int value);
+extern int __init_or_module at91_set_deglitch(unsigned pin, int is_on);
+extern int __init_or_module at91_set_multi_drive(unsigned pin, int is_on);
+
+/* callable at any time */
+extern int at91_set_gpio_value(unsigned pin, int value);
+extern int at91_get_gpio_value(unsigned pin);
+
+/* callable only from core power-management code */
+extern void at91_gpio_suspend(void);
+extern void at91_gpio_resume(void);
+
+/*-------------------------------------------------------------------------*/
+
+/* wrappers for "new style" GPIO calls. the old AT91-specfic ones should
+ * eventually be removed (along with this errno.h inclusion), and the
+ * gpio request/free calls should probably be implemented.
+ */
+
+#include <asm/errno.h>
+
+static inline int gpio_request(unsigned gpio, const char *label)
+{
+        return 0;
+}
+
+static inline void gpio_free(unsigned gpio)
+{
+}
+
+extern int gpio_direction_input(unsigned gpio);
+extern int gpio_direction_output(unsigned gpio, int value);
+
+static inline int gpio_get_value(unsigned gpio)
+{
+        return at91_get_gpio_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+        at91_set_gpio_value(gpio, value);
+}
+
+#include <asm-generic/gpio.h>           /* cansleep wrappers */
+
+static inline int gpio_to_irq(unsigned gpio)
+{
+        return gpio;
+}
+
+static inline int irq_to_gpio(unsigned irq)
+{
+        return irq;
+}
+
+#endif  /* __ASSEMBLY__ */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
new file mode 100644
index 000000000000..da0b681c652c
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -0,0 +1,92 @@
+/*
+ * arch/arm/mach-at91/include/mach/hardware.h
+ *
+ *  Copyright (C) 2003 SAN People
+ *  Copyright (C) 2003 ATMEL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/sizes.h>
+
+#if defined(CONFIG_ARCH_AT91RM9200)
+#include <mach/at91rm9200.h>
+#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)
+#include <mach/at91sam9260.h>
+#elif defined(CONFIG_ARCH_AT91SAM9261)
+#include <mach/at91sam9261.h>
+#elif defined(CONFIG_ARCH_AT91SAM9263)
+#include <mach/at91sam9263.h>
+#elif defined(CONFIG_ARCH_AT91SAM9RL)
+#include <mach/at91sam9rl.h>
+#elif defined(CONFIG_ARCH_AT91CAP9)
+#include <mach/at91cap9.h>
+#elif defined(CONFIG_ARCH_AT91X40)
+#include <mach/at91x40.h>
+#else
+#error "Unsupported AT91 processor"
+#endif
+
+
+#ifdef CONFIG_MMU
+/*
+ * Remap the peripherals from address 0xFFF78000 .. 0xFFFFFFFF
+ * to 0xFEF78000 .. 0xFF000000.  (544Kb)
+ */
+#define AT91_IO_PHYS_BASE       0xFFF78000
+#define AT91_IO_VIRT_BASE       (0xFF000000 - AT91_IO_SIZE)
+#else
+/*
+ * Identity mapping for the non MMU case.
+ */
+#define AT91_IO_PHYS_BASE       AT91_BASE_SYS
+#define AT91_IO_VIRT_BASE       AT91_IO_PHYS_BASE
+#endif
+
+#define AT91_IO_SIZE            (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1)
+
+ /* Convert a physical IO address to virtual IO address */
+#define AT91_IO_P2V(x)          ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE)
+
+/*
+ * Virtual to Physical Address mapping for IO devices.
+ */
+#define AT91_VA_BASE_SYS        AT91_IO_P2V(AT91_BASE_SYS)
+#define AT91_VA_BASE_EMAC       AT91_IO_P2V(AT91RM9200_BASE_EMAC)
+
+ /* Internal SRAM is mapped below the IO devices */
+#define AT91_SRAM_MAX           SZ_1M
+#define AT91_VIRT_BASE          (AT91_IO_VIRT_BASE - AT91_SRAM_MAX)
+
+/* Serial ports */
+#define ATMEL_MAX_UART          7               /* 6 USART3's and one DBGU port (SAM9260) */
+
+/* External Memory Map */
+#define AT91_CHIPSELECT_0       0x10000000
+#define AT91_CHIPSELECT_1       0x20000000
+#define AT91_CHIPSELECT_2       0x30000000
+#define AT91_CHIPSELECT_3       0x40000000
+#define AT91_CHIPSELECT_4       0x50000000
+#define AT91_CHIPSELECT_5       0x60000000
+#define AT91_CHIPSELECT_6       0x70000000
+#define AT91_CHIPSELECT_7       0x80000000
+
+/* SDRAM */
+#ifdef CONFIG_DRAM_BASE
+#define AT91_SDRAM_BASE         CONFIG_DRAM_BASE
+#else
+#define AT91_SDRAM_BASE         AT91_CHIPSELECT_1
+#endif
+
+/* Clocks */
+#define AT91_SLOW_CLOCK         32768           /* slow clock */
+
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/io.h b/arch/arm/mach-at91/include/mach/io.h
new file mode 100644
index 000000000000..1611bd03f528
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/io.h
@@ -0,0 +1,48 @@
+/*
+ * arch/arm/mach-at91/include/mach/io.h
+ *
+ *  Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT          0xFFFFFFFF
+
+#define __io(a)                 ((void __iomem *)(a))
+#define __mem_pci(a)            (a)
+
+
+#ifndef __ASSEMBLY__
+
+static inline unsigned int at91_sys_read(unsigned int reg_offset)
+{
+        void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
+
+        return __raw_readl(addr + reg_offset);
+}
+
+static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
+{
+        void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
+
+        __raw_writel(value, addr + reg_offset);
+}
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/irqs.h b/arch/arm/mach-at91/include/mach/irqs.h
new file mode 100644
index 000000000000..bda29ccbcd94
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/irqs.h
@@ -0,0 +1,48 @@
+/*
+ * arch/arm/mach-at91/include/mach/irqs.h
+ *
+ *  Copyright (C) 2004 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#include <asm/io.h>
+#include <mach/at91_aic.h>
+
+#define NR_AIC_IRQS 32
+
+
+/*
+ * Acknowledge interrupt with AIC after interrupt has been handled.
+ *   (by kernel/irq.c)
+ */
+#define irq_finish(irq) do { at91_sys_write(AT91_AIC_EOICR, 0); } while (0)
+
+
+/*
+ * IRQ interrupt symbols are the AT91xxx_ID_* symbols
+ * for IRQs handled directly through the AIC, or else the AT91_PIN_*
+ * symbols in gpio.h for ones handled indirectly as GPIOs.
+ * We make provision for 5 banks of GPIO.
+ */
+#define NR_IRQS         (NR_AIC_IRQS + (5 * 32))
+
+/* FIQ is AIC source 0. */
+#define FIQ_START AT91_ID_FIQ
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/memory.h b/arch/arm/mach-at91/include/mach/memory.h
new file mode 100644
index 000000000000..9dd1b8c79b08
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/memory.h
@@ -0,0 +1,39 @@
+/*
+ * arch/arm/mach-at91/include/mach/memory.h
+ *
+ *  Copyright (C) 2004 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#include <mach/hardware.h>
+
+#define PHYS_OFFSET     (AT91_SDRAM_BASE)
+
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+#define __virt_to_bus(x) __virt_to_phys(x)
+#define __bus_to_virt(x) __phys_to_virt(x)
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/system.h b/arch/arm/mach-at91/include/mach/system.h
new file mode 100644
index 000000000000..e712658d966c
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/system.h
@@ -0,0 +1,53 @@
+/*
+ * arch/arm/mach-at91/include/mach/system.h
+ *
+ *  Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <mach/hardware.h>
+#include <mach/at91_st.h>
+#include <mach/at91_dbgu.h>
+
+static inline void arch_idle(void)
+{
+        /*
+         * Disable the processor clock.  The processor will be automatically
+         * re-enabled by an interrupt or by a reset.
+         */
+//      at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
+
+        /*
+         * Set the processor (CP15) into 'Wait for Interrupt' mode.
+         * Unlike disabling the processor clock via the PMC (above)
+         *  this allows the processor to be woken via JTAG.
+         */
+        cpu_do_idle();
+}
+
+void (*at91_arch_reset)(void);
+
+static inline void arch_reset(char mode)
+{
+        /* call the CPU-specific reset function */
+        if (at91_arch_reset)
+                (at91_arch_reset)();
+}
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/timex.h b/arch/arm/mach-at91/include/mach/timex.h
new file mode 100644
index 000000000000..d84c9948becf
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/timex.h
@@ -0,0 +1,77 @@
+/*
+ * arch/arm/mach-at91/include/mach/timex.h
+ *
+ *  Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+
+#include <mach/hardware.h>
+
+#if defined(CONFIG_ARCH_AT91RM9200)
+
+#define CLOCK_TICK_RATE         (AT91_SLOW_CLOCK)
+
+#elif defined(CONFIG_ARCH_AT91SAM9260)
+
+#if defined(CONFIG_MACH_USB_A9260) || defined(CONFIG_MACH_QIL_A9260)
+#define AT91SAM9_MASTER_CLOCK   90000000
+#else
+#define AT91SAM9_MASTER_CLOCK   99300000
+#endif
+
+#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
+
+#elif defined(CONFIG_ARCH_AT91SAM9261)
+
+#define AT91SAM9_MASTER_CLOCK   99300000
+#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
+
+#elif defined(CONFIG_ARCH_AT91SAM9263)
+
+#if defined(CONFIG_MACH_USB_A9263)
+#define AT91SAM9_MASTER_CLOCK   90000000
+#else
+#define AT91SAM9_MASTER_CLOCK   99959500
+#endif
+
+#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
+
+#elif defined(CONFIG_ARCH_AT91SAM9RL)
+
+#define AT91SAM9_MASTER_CLOCK   100000000
+#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
+
+#elif defined(CONFIG_ARCH_AT91SAM9G20)
+
+#define AT91SAM9_MASTER_CLOCK   132096000
+#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
+
+#elif defined(CONFIG_ARCH_AT91CAP9)
+
+#define AT91CAP9_MASTER_CLOCK   100000000
+#define CLOCK_TICK_RATE         (AT91CAP9_MASTER_CLOCK/16)
+
+#elif defined(CONFIG_ARCH_AT91X40)
+
+#define AT91X40_MASTER_CLOCK    40000000
+#define CLOCK_TICK_RATE         (AT91X40_MASTER_CLOCK)
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h
new file mode 100644
index 000000000000..0410d548e9b1
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/uncompress.h
@@ -0,0 +1,76 @@
+/*
+ * arch/arm/mach-at91/include/mach/uncompress.h
+ *
+ *  Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+
+#include <asm/io.h>
+#include <linux/atmel_serial.h>
+
+#if defined(CONFIG_AT91_EARLY_DBGU)
+#define UART_OFFSET (AT91_DBGU + AT91_BASE_SYS)
+#elif defined(CONFIG_AT91_EARLY_USART0)
+#define UART_OFFSET AT91_USART0
+#elif defined(CONFIG_AT91_EARLY_USART1)
+#define UART_OFFSET AT91_USART1
+#elif defined(CONFIG_AT91_EARLY_USART2)
+#define UART_OFFSET AT91_USART2
+#elif defined(CONFIG_AT91_EARLY_USART3)
+#define UART_OFFSET AT91_USART3
+#elif defined(CONFIG_AT91_EARLY_USART4)
+#define UART_OFFSET AT91_USART4
+#elif defined(CONFIG_AT91_EARLY_USART5)
+#define UART_OFFSET AT91_USART5
+#endif
+
+/*
+ * The following code assumes the serial port has already been
+ * initialized by the bootloader.  If you didn't setup a port in
+ * your bootloader then nothing will appear (which might be desired).
+ *
+ * This does not append a newline
+ */
+static void putc(int c)
+{
+#ifdef UART_OFFSET
+        void __iomem *sys = (void __iomem *) UART_OFFSET;       /* physical address */
+
+        while (!(__raw_readl(sys + ATMEL_US_CSR) & ATMEL_US_TXRDY))
+                barrier();
+        __raw_writel(c, sys + ATMEL_US_THR);
+#endif
+}
+
+static inline void flush(void)
+{
+#ifdef UART_OFFSET
+        void __iomem *sys = (void __iomem *) UART_OFFSET;       /* physical address */
+
+        /* wait for transmission to complete */
+        while (!(__raw_readl(sys + ATMEL_US_CSR) & ATMEL_US_TXEMPTY))
+                barrier();
+#endif
+}
+
+#define arch_decomp_setup()
+
+#define arch_decomp_wdog()
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/vmalloc.h b/arch/arm/mach-at91/include/mach/vmalloc.h
new file mode 100644
index 000000000000..8eb459f3f5b7
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/vmalloc.h
@@ -0,0 +1,26 @@
+/*
+ * arch/arm/mach-at91/include/mach/vmalloc.h
+ *
+ *  Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_VMALLOC_H
+#define __ASM_ARCH_VMALLOC_H
+
+#define VMALLOC_END             (AT91_VIRT_BASE & PGDIR_MASK)
+
+#endif
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
index a1bfc12a0c23..da3494a53423 100644
--- a/arch/arm/mach-at91/irq.c
+++ b/arch/arm/mach-at91/irq.c
@@ -25,7 +25,7 @@
 #include <linux/mm.h>
 #include <linux/types.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/setup.h>
 
diff --git a/arch/arm/mach-at91/leds.c b/arch/arm/mach-at91/leds.c
index f064b7acb011..fec03c59ff94 100644
--- a/arch/arm/mach-at91/leds.c
+++ b/arch/arm/mach-at91/leds.c
@@ -13,8 +13,8 @@
 #include <linux/module.h>
 #include <linux/init.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/gpio.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
 
 
 /* ------------------------------------------------------------------------- */
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index a5cfe866c9dd..ec2fe4ca1e27 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -24,14 +24,14 @@
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/cpu.h>
+#include <mach/at91_pmc.h>
+#include <mach/gpio.h>
+#include <mach/cpu.h>
 
 #include "generic.h"
 
 #ifdef CONFIG_ARCH_AT91RM9200
-#include <asm/arch/at91rm9200_mc.h>
+#include <mach/at91rm9200_mc.h>
 
 /*
  * The AT91RM9200 goes into self-refresh mode with this command, and will
@@ -41,7 +41,7 @@
 #define sdram_selfrefresh_disable()     do {} while (0)
 
 #elif defined(CONFIG_ARCH_AT91CAP9)
-#include <asm/arch/at91cap9_ddrsdr.h>
+#include <mach/at91cap9_ddrsdr.h>
 
 static u32 saved_lpr;
 
@@ -58,7 +58,7 @@ static inline void sdram_selfrefresh_enable(void)
 #define sdram_selfrefresh_disable()     at91_sys_write(AT91_DDRSDRC_LPR, saved_lpr)
 
 #else
-#include <asm/arch/at91sam9_sdramc.h>
+#include <mach/at91sam9_sdramc.h>
 
 #ifdef CONFIG_ARCH_AT91SAM9263
 /*
@@ -91,8 +91,8 @@ static inline void sdram_selfrefresh_enable(void)
  */
 #if defined(AT91_SHDWC)
 
-#include <asm/arch/at91_rstc.h>
-#include <asm/arch/at91_shdwc.h>
+#include <mach/at91_rstc.h>
+#include <mach/at91_shdwc.h>
 
 static void __init show_reset_status(void)
 {
diff --git a/arch/arm/mach-clps711x/autcpu12.c b/arch/arm/mach-clps711x/autcpu12.c
index 25d18b738bd8..474616dcd7a6 100644
--- a/arch/arm/mach-clps711x/autcpu12.c
+++ b/arch/arm/mach-clps711x/autcpu12.c
@@ -23,7 +23,7 @@
 #include <linux/string.h>
 #include <linux/mm.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/sizes.h>
 #include <asm/io.h>
 #include <asm/setup.h>
@@ -33,7 +33,7 @@
 #include <asm/page.h>
 
 #include <asm/mach/map.h>
-#include <asm/arch/autcpu12.h>
+#include <mach/autcpu12.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-clps711x/cdb89712.c b/arch/arm/mach-clps711x/cdb89712.c
index 8520cb0fdab7..aa02aa5a01f4 100644
--- a/arch/arm/mach-clps711x/cdb89712.c
+++ b/arch/arm/mach-clps711x/cdb89712.c
@@ -23,7 +23,7 @@
 #include <linux/string.h>
 #include <linux/mm.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
diff --git a/arch/arm/mach-clps711x/ceiva.c b/arch/arm/mach-clps711x/ceiva.c
index 9444ab1ffaa5..8ada20184978 100644
--- a/arch/arm/mach-clps711x/ceiva.c
+++ b/arch/arm/mach-clps711x/ceiva.c
@@ -27,7 +27,7 @@
 
 #include <linux/kernel.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/sizes.h>
diff --git a/arch/arm/mach-clps711x/edb7211-mm.c b/arch/arm/mach-clps711x/edb7211-mm.c
index 06f64ec57ae4..c58e32ec4c5d 100644
--- a/arch/arm/mach-clps711x/edb7211-mm.c
+++ b/arch/arm/mach-clps711x/edb7211-mm.c
@@ -22,7 +22,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/sizes.h>
diff --git a/arch/arm/mach-clps711x/fortunet.c b/arch/arm/mach-clps711x/fortunet.c
index c457a35de4ec..7122b3d21043 100644
--- a/arch/arm/mach-clps711x/fortunet.c
+++ b/arch/arm/mach-clps711x/fortunet.c
@@ -23,7 +23,7 @@
 #include <linux/init.h>
 #include <linux/initrd.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
diff --git a/include/asm-arm/arch-clps711x/autcpu12.h b/arch/arm/mach-clps711x/include/mach/autcpu12.h
index 1588a365f610..1588a365f610 100644
--- a/include/asm-arm/arch-clps711x/autcpu12.h
+++ b/arch/arm/mach-clps711x/include/mach/autcpu12.h
diff --git a/arch/arm/mach-clps711x/include/mach/debug-macro.S b/arch/arm/mach-clps711x/include/mach/debug-macro.S
new file mode 100644
index 000000000000..64baf9f87408
--- /dev/null
+++ b/arch/arm/mach-clps711x/include/mach/debug-macro.S
@@ -0,0 +1,46 @@
+/* arch/arm/mach-clps711x/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <asm/hardware/clps7111.h>
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx, #CLPS7111_PHYS_BASE
+                movne   \rx, #CLPS7111_VIRT_BASE
+#ifndef CONFIG_DEBUG_CLPS711X_UART2
+                add     \rx, \rx, #0x0000       @ UART1
+#else
+                add     \rx, \rx, #0x1000       @ UART2
+#endif
+                .endm
+
+                .macro  senduart,rd,rx
+                str     \rd, [\rx, #0x0480]     @ UARTDR
+                .endm
+
+                .macro  waituart,rd,rx
+1001:           ldr     \rd, [\rx, #0x0140]     @ SYSFLGx
+                tst     \rd, #1 << 11           @ UBUSYx
+                bne     1001b
+                .endm
+
+                .macro  busyuart,rd,rx
+                tst     \rx, #0x1000            @ UART2 does not have CTS here
+                bne     1002f
+1001:           ldr     \rd, [\rx, #0x0140]     @ SYSFLGx
+                tst     \rd, #1 << 8            @ CTS
+                bne     1001b
+1002:
+                .endm
+
diff --git a/arch/arm/mach-clps711x/include/mach/dma.h b/arch/arm/mach-clps711x/include/mach/dma.h
new file mode 100644
index 000000000000..0d620e869536
--- /dev/null
+++ b/arch/arm/mach-clps711x/include/mach/dma.h
@@ -0,0 +1,19 @@
+/*
+ *  arch/arm/mach-clps711x/include/mach/dma.h
+ *
+ *  Copyright (C) 1997,1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
diff --git a/arch/arm/mach-clps711x/include/mach/entry-macro.S b/arch/arm/mach-clps711x/include/mach/entry-macro.S
new file mode 100644
index 000000000000..90fa2f70489f
--- /dev/null
+++ b/arch/arm/mach-clps711x/include/mach/entry-macro.S
@@ -0,0 +1,58 @@
+/*
+ * arch/arm/mach-clps711x/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for CLPS711X-based platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <mach/hardware.h>
+#include <asm/hardware/clps7111.h>
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_preamble, base, tmp
+                .endm
+
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
+
+#if (INTSR2 - INTSR1) != (INTMR2 - INTMR1)
+#error INTSR stride != INTMR stride
+#endif
+
+                .macro  get_irqnr_and_base, irqnr, stat, base, mask
+                mov     \base, #CLPS7111_BASE
+                ldr     \stat, [\base, #INTSR1]
+                ldr     \mask, [\base, #INTMR1]
+                mov     \irqnr, #4
+                mov     \mask, \mask, lsl #16
+                and     \stat, \stat, \mask, lsr #16
+                movs    \stat, \stat, lsr #4
+                bne     1001f
+
+                add     \base, \base, #INTSR2 - INTSR1
+                ldr     \stat, [\base, #INTSR1]
+                ldr     \mask, [\base, #INTMR1]
+                mov     \irqnr, #16
+                mov     \mask, \mask, lsl #16
+                and     \stat, \stat, \mask, lsr #16
+
+1001:           tst     \stat, #255
+                addeq   \irqnr, \irqnr, #8
+                moveq   \stat, \stat, lsr #8
+                tst     \stat, #15
+                addeq   \irqnr, \irqnr, #4
+                moveq   \stat, \stat, lsr #4
+                tst     \stat, #3
+                addeq   \irqnr, \irqnr, #2
+                moveq   \stat, \stat, lsr #2
+                tst     \stat, #1
+                addeq   \irqnr, \irqnr, #1
+                moveq   \stat, \stat, lsr #1
+                tst     \stat, #1                       @ bit 0 should be set
+                .endm
+
+
diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h
new file mode 100644
index 000000000000..4c3e101b96c9
--- /dev/null
+++ b/arch/arm/mach-clps711x/include/mach/hardware.h
@@ -0,0 +1,237 @@
+/*
+ *  arch/arm/mach-clps711x/include/mach/hardware.h
+ *
+ *  This file contains the hardware definitions of the Prospector P720T.
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+
+#define CLPS7111_VIRT_BASE      0xff000000
+#define CLPS7111_BASE           CLPS7111_VIRT_BASE
+
+/*
+ * The physical addresses that the external chip select signals map to is
+ * dependent on the setting of the nMEDCHG signal on EP7211 and EP7212
+ * processors.  CONFIG_EP72XX_BOOT_ROM is only available if these
+ * processors are in use.
+ */
+#ifndef CONFIG_EP72XX_ROM_BOOT
+#define CS0_PHYS_BASE           (0x00000000)
+#define CS1_PHYS_BASE           (0x10000000)
+#define CS2_PHYS_BASE           (0x20000000)
+#define CS3_PHYS_BASE           (0x30000000)
+#define CS4_PHYS_BASE           (0x40000000)
+#define CS5_PHYS_BASE           (0x50000000)
+#define CS6_PHYS_BASE           (0x60000000)
+#define CS7_PHYS_BASE           (0x70000000)
+#else
+#define CS0_PHYS_BASE           (0x70000000)
+#define CS1_PHYS_BASE           (0x60000000)
+#define CS2_PHYS_BASE           (0x50000000)
+#define CS3_PHYS_BASE           (0x40000000)
+#define CS4_PHYS_BASE           (0x30000000)
+#define CS5_PHYS_BASE           (0x20000000)
+#define CS6_PHYS_BASE           (0x10000000)
+#define CS7_PHYS_BASE           (0x00000000)
+#endif
+
+#if defined (CONFIG_ARCH_EP7211)
+
+#define EP7211_VIRT_BASE        CLPS7111_VIRT_BASE
+#define EP7211_BASE             CLPS7111_VIRT_BASE
+#include <asm/hardware/ep7211.h>
+
+#elif defined (CONFIG_ARCH_EP7212)
+
+#define EP7212_VIRT_BASE        CLPS7111_VIRT_BASE
+#define EP7212_BASE             CLPS7111_VIRT_BASE
+#include <asm/hardware/ep7212.h>
+
+#endif
+
+#define SYSPLD_VIRT_BASE        0xfe000000
+#define SYSPLD_BASE             SYSPLD_VIRT_BASE
+
+#ifndef __ASSEMBLER__
+
+#define PCIO_BASE               IO_BASE
+
+#endif
+
+
+#if  defined (CONFIG_ARCH_AUTCPU12)
+
+#define  CS89712_VIRT_BASE      CLPS7111_VIRT_BASE
+#define  CS89712_BASE           CLPS7111_VIRT_BASE
+
+#include <asm/hardware/clps7111.h>
+#include <asm/hardware/ep7212.h>
+#include <asm/hardware/cs89712.h>
+
+#endif
+
+
+#if defined (CONFIG_ARCH_CDB89712)
+
+#include <asm/hardware/clps7111.h>
+#include <asm/hardware/ep7212.h>
+#include <asm/hardware/cs89712.h>
+
+/* dynamic ioremap() areas */
+#define FLASH_START      0x00000000
+#define FLASH_SIZE       0x800000
+#define FLASH_WIDTH      4
+
+#define SRAM_START       0x60000000
+#define SRAM_SIZE        0xc000
+#define SRAM_WIDTH       4
+
+#define BOOTROM_START    0x70000000
+#define BOOTROM_SIZE     0x80
+#define BOOTROM_WIDTH    4
+
+
+/* static cdb89712_map_io() areas */
+#define REGISTER_START   0x80000000
+#define REGISTER_SIZE    0x4000
+#define REGISTER_BASE    0xff000000
+
+#define ETHER_START      0x20000000
+#define ETHER_SIZE       0x1000
+#define ETHER_BASE       0xfe000000
+
+#endif
+
+
+#if defined (CONFIG_ARCH_EDB7211)
+
+/*
+ * The extra 8 lines of the keyboard matrix are wired to chip select 3 (nCS3) 
+ * and repeat across it. This is the mapping for it.
+ *
+ * In jumpered boot mode, nCS3 is mapped to 0x4000000, not 0x3000000. This 
+ * was cause for much consternation and headscratching. This should probably
+ * be made a compile/run time kernel option.
+ */
+#define EP7211_PHYS_EXTKBD              CS3_PHYS_BASE   /* physical */
+
+#define EP7211_VIRT_EXTKBD              (0xfd000000)    /* virtual */
+
+
+/*
+ * The CS8900A ethernet chip has its I/O registers wired to chip select 2 
+ * (nCS2). This is the mapping for it.
+ *
+ * In jumpered boot mode, nCS2 is mapped to 0x5000000, not 0x2000000. This 
+ * was cause for much consternation and headscratching. This should probably
+ * be made a compile/run time kernel option.
+ */
+#define EP7211_PHYS_CS8900A             CS2_PHYS_BASE   /* physical */
+
+#define EP7211_VIRT_CS8900A             (0xfc000000)    /* virtual */
+
+
+/*
+ * The two flash banks are wired to chip selects 0 and 1. This is the mapping
+ * for them.
+ *
+ * nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running
+ * in jumpered boot mode.
+ */
+#define EP7211_PHYS_FLASH1              CS0_PHYS_BASE   /* physical */
+#define EP7211_PHYS_FLASH2              CS1_PHYS_BASE   /* physical */
+
+#define EP7211_VIRT_FLASH1              (0xfa000000)    /* virtual */
+#define EP7211_VIRT_FLASH2              (0xfb000000)    /* virtual */
+
+#endif /* CONFIG_ARCH_EDB7211 */
+
+
+/*
+ * Relevant bits in port D, which controls power to the various parts of
+ * the LCD on the EDB7211.
+ */
+#define EDB_PD1_LCD_DC_DC_EN    (1<<1)
+#define EDB_PD2_LCDEN           (1<<2)
+#define EDB_PD3_LCDBL           (1<<3)
+
+
+#if defined (CONFIG_ARCH_CEIVA)
+
+#define  CEIVA_VIRT_BASE        CLPS7111_VIRT_BASE
+#define  CEIVA_BASE             CLPS7111_VIRT_BASE
+
+#include <asm/hardware/clps7111.h>
+#include <asm/hardware/ep7212.h>
+
+
+/*
+ * The two flash banks are wired to chip selects 0 and 1. This is the mapping
+ * for them.
+ *
+ * nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running
+ * in jumpered boot mode.
+ */
+#define CEIVA_PHYS_FLASH1       CS0_PHYS_BASE   /* physical */
+#define CEIVA_PHYS_FLASH2       CS1_PHYS_BASE   /* physical */
+
+#define CEIVA_VIRT_FLASH1       (0xfa000000)    /* virtual */
+#define CEIVA_VIRT_FLASH2       (0xfb000000)    /* virtual */
+
+#define CEIVA_FLASH_SIZE        0x100000
+#define CEIVA_FLASH_WIDTH       2
+
+#define SRAM_START       0x60000000
+#define SRAM_SIZE        0xc000
+#define SRAM_WIDTH       4
+
+#define BOOTROM_START    0x70000000
+#define BOOTROM_SIZE     0x80
+#define BOOTROM_WIDTH    4
+
+/*
+ * SED1355 LCD controller
+ */
+#define CEIVA_PHYS_SED1355      CS2_PHYS_BASE
+#define CEIVA_VIRT_SED1355      (0xfc000000)
+
+/*
+ * Relevant bits in port D, which controls power to the various parts of
+ * the LCD on the Ceiva Photo Max, and reset to the LCD controller.
+ */
+
+// Reset line to SED1355 (must be high to operate)
+#define CEIVA_PD1_LCDRST        (1<<1)
+// LCD panel enable (set to one, to enable LCD)
+#define CEIVA_PD4_LCDEN         (1<<4)
+// Backlight (set to one, to turn on backlight
+#define CEIVA_PD5_LCDBL         (1<<5)
+
+/*
+ * Relevant bits in port B, which report the status of the buttons.
+ */
+
+// White button
+#define CEIVA_PB4_WHT_BTN       (1<<4)
+// Black button
+#define CEIVA_PB0_BLK_BTN       (1<<0)
+#endif // #if defined (CONFIG_ARCH_CEIVA)
+
+#endif
diff --git a/arch/arm/mach-clps711x/include/mach/io.h b/arch/arm/mach-clps711x/include/mach/io.h
new file mode 100644
index 000000000000..4c8440087679
--- /dev/null
+++ b/arch/arm/mach-clps711x/include/mach/io.h
@@ -0,0 +1,38 @@
+/*
+ *  arch/arm/mach-clps711x/include/mach/io.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#include <mach/hardware.h>
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+#define __io(a)                 ((void __iomem *)(a))
+#define __mem_pci(a)            (a)
+
+/*
+ * We don't support ins[lb]/outs[lb].  Make them fault.
+ */
+#define __raw_readsb(p,d,l)     do { *(int *)0 = 0; } while (0)
+#define __raw_readsl(p,d,l)     do { *(int *)0 = 0; } while (0)
+#define __raw_writesb(p,d,l)    do { *(int *)0 = 0; } while (0)
+#define __raw_writesl(p,d,l)    do { *(int *)0 = 0; } while (0)
+
+#endif
diff --git a/arch/arm/mach-clps711x/include/mach/irqs.h b/arch/arm/mach-clps711x/include/mach/irqs.h
new file mode 100644
index 000000000000..30b7e97285a4
--- /dev/null
+++ b/arch/arm/mach-clps711x/include/mach/irqs.h
@@ -0,0 +1,53 @@
+/*
+ *  arch/arm/mach-clps711x/include/mach/irqs.h
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/*
+ * Interrupts from INTSR1
+ */
+#define IRQ_CSINT                       4
+#define IRQ_EINT1                       5
+#define IRQ_EINT2                       6
+#define IRQ_EINT3                       7
+#define IRQ_TC1OI                       8
+#define IRQ_TC2OI                       9
+#define IRQ_RTCMI                       10
+#define IRQ_TINT                        11
+#define IRQ_UTXINT1                     12
+#define IRQ_URXINT1                     13
+#define IRQ_UMSINT                      14
+#define IRQ_SSEOTI                      15
+
+#define INT1_IRQS                       (0x0000fff0)
+#define INT1_ACK_IRQS                   (0x00004f10)
+
+/*
+ * Interrupts from INTSR2
+ */
+#define IRQ_KBDINT                      (16+0)  /* bit 0 */
+#define IRQ_SS2RX                       (16+1)  /* bit 1 */
+#define IRQ_SS2TX                       (16+2)  /* bit 2 */
+#define IRQ_UTXINT2                     (16+12) /* bit 12 */
+#define IRQ_URXINT2                     (16+13) /* bit 13 */
+
+#define INT2_IRQS                       (0x30070000)
+#define INT2_ACK_IRQS                   (0x00010000)
+
+#define NR_IRQS                         30
+
diff --git a/arch/arm/mach-clps711x/include/mach/memory.h b/arch/arm/mach-clps711x/include/mach/memory.h
new file mode 100644
index 000000000000..71c2fa70c8e8
--- /dev/null
+++ b/arch/arm/mach-clps711x/include/mach/memory.h
@@ -0,0 +1,94 @@
+/*
+ *  arch/arm/mach-clps711x/include/mach/memory.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     UL(0xc0000000)
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+
+#if defined(CONFIG_ARCH_CDB89712)
+
+#define __virt_to_bus(x)        (x)
+#define __bus_to_virt(x)        (x)
+
+#elif defined (CONFIG_ARCH_AUTCPU12)
+
+#define __virt_to_bus(x)        (x)
+#define __bus_to_virt(x)        (x)
+
+#else
+
+#define __virt_to_bus(x)        ((x) - PAGE_OFFSET)
+#define __bus_to_virt(x)        ((x) + PAGE_OFFSET)
+
+#endif
+
+
+/*
+ * Like the SA1100, the EDB7211 has a large gap between physical RAM
+ * banks.  In 2.2, the Psion (CL-PS7110) port added custom support for
+ * discontiguous physical memory.  In 2.4, we can use the standard
+ * Linux NUMA support.
+ *
+ * This is not necessary for EP7211 implementations with only one used
+ * memory bank.  For those systems, simply undefine CONFIG_DISCONTIGMEM.
+ */
+
+/*
+ * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211
+ * uses only one of the two banks (bank #1).  However, even within
+ * bank #1, memory is discontiguous.
+ *
+ * The EDB7211 has two 8MB DRAM areas with 8MB of empty space between
+ * them, so we use 24 for the node max shift to get 16MB node sizes.
+ */
+
+/*
+ * Because of the wide memory address space between physical RAM banks on the 
+ * SA1100, it's much more convenient to use Linux's NUMA support to implement
+ * our memory map representation.  Assuming all memory nodes have equal access 
+ * characteristics, we then have generic discontiguous memory support.
+ *
+ * Of course, all this isn't mandatory for SA1100 implementations with only
+ * one used memory bank.  For those, simply undefine CONFIG_DISCONTIGMEM.
+ *
+ * The nodes are matched with the physical memory bank addresses which are 
+ * incidentally the same as virtual addresses.
+ * 
+ *      node 0:  0xc0000000 - 0xc7ffffff
+ *      node 1:  0xc8000000 - 0xcfffffff
+ *      node 2:  0xd0000000 - 0xd7ffffff
+ *      node 3:  0xd8000000 - 0xdfffffff
+ */
+#define NODE_MEM_SIZE_BITS      24
+
+#endif
+
diff --git a/arch/arm/mach-clps711x/include/mach/syspld.h b/arch/arm/mach-clps711x/include/mach/syspld.h
new file mode 100644
index 000000000000..f7f4c1201898
--- /dev/null
+++ b/arch/arm/mach-clps711x/include/mach/syspld.h
@@ -0,0 +1,121 @@
+/*
+ *  arch/arm/mach-clps711x/include/mach/syspld.h
+ *
+ *  System Control PLD register definitions.
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_SYSPLD_H
+#define __ASM_ARCH_SYSPLD_H
+
+#define SYSPLD_PHYS_BASE        (0x10000000)
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+
+#define SYSPLD_REG(type,off)    (*(volatile type *)(SYSPLD_BASE + off))
+#else
+#define SYSPLD_REG(type,off)    (off)
+#endif
+
+#define PLD_INT         SYSPLD_REG(u32, 0x000000)
+#define PLD_INT_PENIRQ          (1 << 5)
+#define PLD_INT_UCB_IRQ         (1 << 1)
+#define PLD_INT_KBD_ATN         (1 << 0)        /* EINT1 */
+
+#define PLD_PWR         SYSPLD_REG(u32, 0x000004)
+#define PLD_PWR_EXT             (1 << 5)
+#define PLD_PWR_MODE            (1 << 4)        /* 1 = PWM, 0 = PFM */
+#define PLD_S4_ON               (1 << 3)        /* LCD bias voltage enable */
+#define PLD_S3_ON               (1 << 2)        /* LCD backlight enable */
+#define PLD_S2_ON               (1 << 1)        /* LCD 3V3 supply enable */
+#define PLD_S1_ON               (1 << 0)        /* LCD 3V supply enable */
+
+#define PLD_KBD         SYSPLD_REG(u32, 0x000008)
+#define PLD_KBD_WAKE            (1 << 1)
+#define PLD_KBD_EN              (1 << 0)
+
+#define PLD_SPI         SYSPLD_REG(u32, 0x00000c)
+#define PLD_SPI_EN              (1 << 0)
+
+#define PLD_IO          SYSPLD_REG(u32, 0x000010)
+#define PLD_IO_BOOTSEL          (1 << 6)        /* boot sel switch */
+#define PLD_IO_USER             (1 << 5)        /* user defined switch */
+#define PLD_IO_LED3             (1 << 4)
+#define PLD_IO_LED2             (1 << 3)
+#define PLD_IO_LED1             (1 << 2)
+#define PLD_IO_LED0             (1 << 1)
+#define PLD_IO_LEDEN            (1 << 0)
+
+#define PLD_IRDA        SYSPLD_REG(u32, 0x000014)
+#define PLD_IRDA_EN             (1 << 0)
+
+#define PLD_COM2        SYSPLD_REG(u32, 0x000018)
+#define PLD_COM2_EN             (1 << 0)
+
+#define PLD_COM1        SYSPLD_REG(u32, 0x00001c)
+#define PLD_COM1_EN             (1 << 0)
+
+#define PLD_AUD         SYSPLD_REG(u32, 0x000020)
+#define PLD_AUD_DIV1            (1 << 6)
+#define PLD_AUD_DIV0            (1 << 5)
+#define PLD_AUD_CLK_SEL1        (1 << 4)
+#define PLD_AUD_CLK_SEL0        (1 << 3)
+#define PLD_AUD_MIC_PWR         (1 << 2)
+#define PLD_AUD_MIC_GAIN        (1 << 1)
+#define PLD_AUD_CODEC_EN        (1 << 0)
+
+#define PLD_CF          SYSPLD_REG(u32, 0x000024)
+#define PLD_CF2_SLEEP           (1 << 5)
+#define PLD_CF1_SLEEP           (1 << 4)
+#define PLD_CF2_nPDREQ          (1 << 3)
+#define PLD_CF1_nPDREQ          (1 << 2)
+#define PLD_CF2_nIRQ            (1 << 1)
+#define PLD_CF1_nIRQ            (1 << 0)
+
+#define PLD_SDC         SYSPLD_REG(u32, 0x000028)
+#define PLD_SDC_INT_EN          (1 << 2)
+#define PLD_SDC_WP              (1 << 1)
+#define PLD_SDC_CD              (1 << 0)
+
+#define PLD_FPGA        SYSPLD_REG(u32, 0x00002c)
+
+#define PLD_CODEC       SYSPLD_REG(u32, 0x400000)
+#define PLD_CODEC_IRQ3          (1 << 4)
+#define PLD_CODEC_IRQ2          (1 << 3)
+#define PLD_CODEC_IRQ1          (1 << 2)
+#define PLD_CODEC_EN            (1 << 0)
+
+#define PLD_BRITE       SYSPLD_REG(u32, 0x400004)
+#define PLD_BRITE_UP            (1 << 1)
+#define PLD_BRITE_DN            (1 << 0)
+
+#define PLD_LCDEN       SYSPLD_REG(u32, 0x400008)
+#define PLD_LCDEN_EN            (1 << 0)
+
+#define PLD_ID          SYSPLD_REG(u32, 0x40000c)
+
+#define PLD_TCH         SYSPLD_REG(u32, 0x400010)
+#define PLD_TCH_PENIRQ          (1 << 1)
+#define PLD_TCH_EN              (1 << 0)
+
+#define PLD_GPIO        SYSPLD_REG(u32, 0x400014)
+#define PLD_GPIO2               (1 << 2)
+#define PLD_GPIO1               (1 << 1)
+#define PLD_GPIO0               (1 << 0)
+
+#endif
diff --git a/arch/arm/mach-clps711x/include/mach/system.h b/arch/arm/mach-clps711x/include/mach/system.h
new file mode 100644
index 000000000000..a8eade40317f
--- /dev/null
+++ b/arch/arm/mach-clps711x/include/mach/system.h
@@ -0,0 +1,40 @@
+/*
+ *  arch/arm/mach-clps711x/include/mach/system.h
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <mach/hardware.h>
+#include <asm/hardware/clps7111.h>
+#include <asm/io.h>
+
+static inline void arch_idle(void)
+{
+        clps_writel(1, HALT);
+        __asm__ __volatile__(
+        "mov    r0, r0\n\
+        mov     r0, r0");
+}
+
+static inline void arch_reset(char mode)
+{
+        cpu_reset(0);
+}
+
+#endif
diff --git a/arch/arm/mach-clps711x/include/mach/time.h b/arch/arm/mach-clps711x/include/mach/time.h
new file mode 100644
index 000000000000..8fe283ccd1f3
--- /dev/null
+++ b/arch/arm/mach-clps711x/include/mach/time.h
@@ -0,0 +1,49 @@
+/*
+ *  arch/arm/mach-clps711x/include/mach/time.h
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <asm/leds.h>
+#include <asm/hardware/clps7111.h>
+
+extern void clps711x_setup_timer(void);
+
+/*
+ * IRQ handler for the timer
+ */
+static irqreturn_t
+p720t_timer_interrupt(int irq, void *dev_id)
+{
+        struct pt_regs *regs = get_irq_regs();
+        do_leds();
+        do_timer(1);
+#ifndef CONFIG_SMP
+        update_process_times(user_mode(regs));
+#endif
+        do_profile(regs);
+        return IRQ_HANDLED;
+}
+
+/*
+ * Set up timer interrupt, and return the current time in seconds.
+ */
+void __init time_init(void)
+{
+        clps711x_setup_timer();
+        timer_irq.handler = p720t_timer_interrupt;
+        setup_irq(IRQ_TC2OI, &timer_irq);
+}
diff --git a/arch/arm/mach-clps711x/include/mach/timex.h b/arch/arm/mach-clps711x/include/mach/timex.h
new file mode 100644
index 000000000000..ac8823ccff93
--- /dev/null
+++ b/arch/arm/mach-clps711x/include/mach/timex.h
@@ -0,0 +1,23 @@
+/*
+ *  arch/arm/mach-clps711x/include/mach/timex.h
+ *
+ *  Prospector 720T architecture timex specifications
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#define CLOCK_TICK_RATE 512000
diff --git a/arch/arm/mach-clps711x/include/mach/uncompress.h b/arch/arm/mach-clps711x/include/mach/uncompress.h
new file mode 100644
index 000000000000..7164310dea7c
--- /dev/null
+++ b/arch/arm/mach-clps711x/include/mach/uncompress.h
@@ -0,0 +1,59 @@
+/*
+ *  arch/arm/mach-clps711x/include/mach/uncompress.h
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <mach/io.h>
+#include <mach/hardware.h>
+#include <asm/hardware/clps7111.h>
+
+#undef CLPS7111_BASE
+#define CLPS7111_BASE CLPS7111_PHYS_BASE
+
+#define __raw_readl(p)          (*(unsigned long *)(p))
+#define __raw_writel(v,p)       (*(unsigned long *)(p) = (v))
+
+#ifdef CONFIG_DEBUG_CLPS711X_UART2
+#define SYSFLGx SYSFLG2
+#define UARTDRx UARTDR2
+#else
+#define SYSFLGx SYSFLG1
+#define UARTDRx UARTDR1
+#endif
+
+/*
+ * This does not append a newline
+ */
+static inline void putc(int c)
+{
+        while (clps_readl(SYSFLGx) & SYSFLG_UTXFF)
+                barrier();
+        clps_writel(c, UARTDRx);
+}
+
+static inline void flush(void)
+{
+        while (clps_readl(SYSFLGx) & SYSFLG_UBUSY)
+                barrier();
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-clps711x/include/mach/vmalloc.h b/arch/arm/mach-clps711x/include/mach/vmalloc.h
new file mode 100644
index 000000000000..ea6cc7beff28
--- /dev/null
+++ b/arch/arm/mach-clps711x/include/mach/vmalloc.h
@@ -0,0 +1,20 @@
+/*
+ *  arch/arm/mach-clps711x/include/mach/vmalloc.h
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
diff --git a/arch/arm/mach-clps711x/irq.c b/arch/arm/mach-clps711x/irq.c
index 6954a7a49156..38623cfcac5a 100644
--- a/arch/arm/mach-clps711x/irq.c
+++ b/arch/arm/mach-clps711x/irq.c
@@ -21,7 +21,7 @@
 #include <linux/list.h>
 
 #include <asm/mach/irq.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 
diff --git a/arch/arm/mach-clps711x/mm.c b/arch/arm/mach-clps711x/mm.c
index 43c2fa8f4817..a7b4591205a3 100644
--- a/arch/arm/mach-clps711x/mm.c
+++ b/arch/arm/mach-clps711x/mm.c
@@ -25,7 +25,7 @@
 #include <linux/bootmem.h>
 
 #include <asm/sizes.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-clps711x/p720t-leds.c b/arch/arm/mach-clps711x/p720t-leds.c
index a9b9c5b847e2..262c3c361453 100644
--- a/arch/arm/mach-clps711x/p720t-leds.c
+++ b/arch/arm/mach-clps711x/p720t-leds.c
@@ -22,7 +22,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/leds.h>
 #include <asm/system.h>
diff --git a/arch/arm/mach-clps711x/p720t.c b/arch/arm/mach-clps711x/p720t.c
index 80d8fd28b2f1..f51f97d4f212 100644
--- a/arch/arm/mach-clps711x/p720t.c
+++ b/arch/arm/mach-clps711x/p720t.c
@@ -23,7 +23,7 @@
 #include <linux/string.h>
 #include <linux/mm.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
@@ -32,7 +32,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <asm/arch/syspld.h>
+#include <mach/syspld.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-clps711x/time.c b/arch/arm/mach-clps711x/time.c
index d922a891b1ad..ef1fcd17189e 100644
--- a/arch/arm/mach-clps711x/time.c
+++ b/arch/arm/mach-clps711x/time.c
@@ -22,7 +22,7 @@
 #include <linux/irq.h>
 #include <linux/sched.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/leds.h>
 #include <asm/io.h>
diff --git a/arch/arm/mach-clps7500/core.c b/arch/arm/mach-clps7500/core.c
index cfd8aca9f7da..cc1b82179e83 100644
--- a/arch/arm/mach-clps7500/core.c
+++ b/arch/arm/mach-clps7500/core.c
@@ -21,7 +21,7 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/hardware/iomd.h>
 #include <asm/io.h>
 #include <asm/irq.h>
diff --git a/include/asm-arm/arch-cl7500/acornfb.h b/arch/arm/mach-clps7500/include/mach/acornfb.h
index aea6330c9745..aea6330c9745 100644
--- a/include/asm-arm/arch-cl7500/acornfb.h
+++ b/arch/arm/mach-clps7500/include/mach/acornfb.h
diff --git a/arch/arm/mach-clps7500/include/mach/debug-macro.S b/arch/arm/mach-clps7500/include/mach/debug-macro.S
new file mode 100644
index 000000000000..af4104e7e84a
--- /dev/null
+++ b/arch/arm/mach-clps7500/include/mach/debug-macro.S
@@ -0,0 +1,21 @@
+/* arch/arm/mach-clps7500/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+                .macro  addruart,rx
+                mov     \rx, #0xe0000000
+                orr     \rx, \rx, #0x00010000
+                orr     \rx, \rx, #0x00000be0
+                .endm
+
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-clps7500/include/mach/dma.h b/arch/arm/mach-clps7500/include/mach/dma.h
new file mode 100644
index 000000000000..63fcde505498
--- /dev/null
+++ b/arch/arm/mach-clps7500/include/mach/dma.h
@@ -0,0 +1,21 @@
+/*
+ * arch/arm/mach-clps7500/include/mach/dma.h
+ *
+ * Copyright (C) 1999 Nexus Electronics Ltd.
+ */
+
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+/* DMA is not yet implemented! It should be the same as acorn, copy over.. */
+
+/*
+ * This is the maximum DMA address that can be DMAd to.
+ * There should not be more than (0xd0000000 - 0xc0000000)
+ * bytes of RAM.
+ */
+#define MAX_DMA_ADDRESS         0xd0000000
+
+#define DMA_S0                  0
+
+#endif /* _ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-clps7500/include/mach/entry-macro.S b/arch/arm/mach-clps7500/include/mach/entry-macro.S
new file mode 100644
index 000000000000..4e7e54144093
--- /dev/null
+++ b/arch/arm/mach-clps7500/include/mach/entry-macro.S
@@ -0,0 +1,16 @@
+#include <mach/hardware.h>
+#include <asm/hardware/entry-macro-iomd.S>
+
+        .equ    ioc_base_high, IOC_BASE & 0xff000000
+        .equ    ioc_base_low, IOC_BASE & 0x00ff0000
+
+        .macro  get_irqnr_preamble, base, tmp
+        mov     \base, #ioc_base_high           @ point at IOC
+        .if     ioc_base_low
+        orr     \base, \base, #ioc_base_low
+        .endif
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
diff --git a/arch/arm/mach-clps7500/include/mach/hardware.h b/arch/arm/mach-clps7500/include/mach/hardware.h
new file mode 100644
index 000000000000..d66578a3371c
--- /dev/null
+++ b/arch/arm/mach-clps7500/include/mach/hardware.h
@@ -0,0 +1,67 @@
+/*
+ * arch/arm/mach-clps7500/include/mach/hardware.h
+ *
+ * Copyright (C) 1996-1999 Russell King.
+ * Copyright (C) 1999 Nexus Electronics Ltd.
+ *
+ * This file contains the hardware definitions of the 
+ * CL7500 evaluation board.
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <mach/memory.h>
+#include <asm/hardware/iomd.h>
+
+#ifdef __ASSEMBLY__
+#define IOMEM(x) x
+#else
+#define IOMEM(x) ((void __iomem *)(x))
+#endif
+
+/*
+ * What hardware must be present
+ */
+#define HAS_IOMD
+#define HAS_VIDC20
+
+/* Hardware addresses of major areas.
+ *  *_START is the physical address
+ *  *_SIZE  is the size of the region
+ *  *_BASE  is the virtual address
+ */
+
+#define IO_START                0x03000000      /* I/O */
+#define IO_SIZE                 0x01000000
+#define IO_BASE                 IOMEM(0xe0000000)
+
+#define ISA_START               0x0c000000      /* ISA */
+#define ISA_SIZE                0x00010000
+#define ISA_BASE                0xe1000000
+
+#define FLASH_START             0x01000000      /* XXX */
+#define FLASH_SIZE              0x01000000
+#define FLASH_BASE              0xe2000000
+
+#define LED_START               0x0302B000
+#define LED_SIZE                0x00001000
+#define LED_BASE                0xe3000000
+#define LED_ADDRESS             (LED_BASE + 0xa00)
+
+/* Let's define SCREEN_START for CL7500, even though it's a lie. */
+#define SCREEN_START            0x02000000      /* VRAM */
+#define SCREEN_END              0xdfc00000
+#define SCREEN_BASE             0xdf800000
+
+#define VIDC_BASE               (void __iomem *)0xe0400000
+#define IOMD_BASE               IOMEM(0xe0200000)
+#define IOC_BASE                IOMEM(0xe0200000)
+#define FLOPPYDMA_BASE          IOMEM(0xe002a000)
+#define PCIO_BASE               IOMEM(0xe0010000)
+
+#define vidc_writel(val)        __raw_writel(val, VIDC_BASE)
+
+/* in/out bias for the ISA slot region */
+#define ISASLOT_IO              0x80400000
+
+#endif
diff --git a/arch/arm/mach-clps7500/include/mach/io.h b/arch/arm/mach-clps7500/include/mach/io.h
new file mode 100644
index 000000000000..2ff2860889ed
--- /dev/null
+++ b/arch/arm/mach-clps7500/include/mach/io.h
@@ -0,0 +1,255 @@
+/*
+ * arch/arm/mach-clps7500/include/mach/io.h
+ *  from arch/arm/mach-rpc/include/mach/io.h
+ *
+ * Copyright (C) 1997 Russell King
+ *
+ * Modifications:
+ *  06-Dec-1997 RMK     Created.
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#include <mach/hardware.h>
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * GCC is totally crap at loading/storing data.  We try to persuade it
+ * to do the right thing by using these whereever possible instead of
+ * the above.
+ */
+#define __arch_base_getb(b,o)                   \
+ ({                                             \
+        unsigned int v, r = (b);                \
+        __asm__ __volatile__(                   \
+                "ldrb   %0, [%1, %2]"           \
+                : "=r" (v)                      \
+                : "r" (r), "Ir" (o));           \
+        v;                                      \
+ })
+
+#define __arch_base_getl(b,o)                   \
+ ({                                             \
+        unsigned int v, r = (b);                \
+        __asm__ __volatile__(                   \
+                "ldr    %0, [%1, %2]"           \
+                : "=r" (v)                      \
+                : "r" (r), "Ir" (o));           \
+        v;                                      \
+ })
+
+#define __arch_base_putb(v,b,o)                 \
+ ({                                             \
+        unsigned int r = (b);                   \
+        __asm__ __volatile__(                   \
+                "strb   %0, [%1, %2]"           \
+                :                               \
+                : "r" (v), "r" (r), "Ir" (o));  \
+ })
+
+#define __arch_base_putl(v,b,o)                 \
+ ({                                             \
+        unsigned int r = (b);                   \
+        __asm__ __volatile__(                   \
+                "str    %0, [%1, %2]"           \
+                :                               \
+                : "r" (v), "r" (r), "Ir" (o));  \
+ })
+
+/*
+ * We use two different types of addressing - PC style addresses, and ARM
+ * addresses.  PC style accesses the PC hardware with the normal PC IO
+ * addresses, eg 0x3f8 for serial#1.  ARM addresses are 0x80000000+
+ * and are translated to the start of IO.  Note that all addresses are
+ * shifted left!
+ */
+#define __PORT_PCIO(x)  (!((x) & 0x80000000))
+
+/*
+ * Dynamic IO functions - let the compiler
+ * optimize the expressions
+ */
+static inline void __outb (unsigned int value, unsigned int port)
+{
+        unsigned long temp;
+        __asm__ __volatile__(
+        "tst    %2, #0x80000000\n\t"
+        "mov    %0, %4\n\t"
+        "addeq  %0, %0, %3\n\t"
+        "strb   %1, [%0, %2, lsl #2]    @ outb"
+        : "=&r" (temp)
+        : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
+        : "cc");
+}
+
+static inline void __outw (unsigned int value, unsigned int port)
+{
+        unsigned long temp;
+        __asm__ __volatile__(
+        "tst    %2, #0x80000000\n\t"
+        "mov    %0, %4\n\t"
+        "addeq  %0, %0, %3\n\t"
+        "str    %1, [%0, %2, lsl #2]    @ outw"
+        : "=&r" (temp)
+        : "r" (value|value<<16), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
+        : "cc");
+}
+
+static inline void __outl (unsigned int value, unsigned int port)
+{
+        unsigned long temp;
+        __asm__ __volatile__(
+        "tst    %2, #0x80000000\n\t"
+        "mov    %0, %4\n\t"
+        "addeq  %0, %0, %3\n\t"
+        "str    %1, [%0, %2, lsl #2]    @ outl"
+        : "=&r" (temp)
+        : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
+        : "cc");
+}
+
+#define DECLARE_DYN_IN(sz,fnsuffix,instr)                                       \
+static inline unsigned sz __in##fnsuffix (unsigned int port)            \
+{                                                                               \
+        unsigned long temp, value;                                              \
+        __asm__ __volatile__(                                                   \
+        "tst    %2, #0x80000000\n\t"                                            \
+        "mov    %0, %4\n\t"                                                     \
+        "addeq  %0, %0, %3\n\t"                                                 \
+        "ldr" instr "   %1, [%0, %2, lsl #2]    @ in" #fnsuffix                 \
+        : "=&r" (temp), "=r" (value)                                            \
+        : "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)                \
+        : "cc");                                                                \
+        return (unsigned sz)value;                                              \
+}
+
+static inline unsigned int __ioaddr (unsigned int port)                 \
+{                                                                               \
+        if (__PORT_PCIO(port))                                                  \
+                return (unsigned int)(PCIO_BASE + (port << 2));                 \
+        else                                                                    \
+                return (unsigned int)(IO_BASE + (port << 2));                   \
+}
+
+#define DECLARE_IO(sz,fnsuffix,instr)   \
+        DECLARE_DYN_IN(sz,fnsuffix,instr)
+
+DECLARE_IO(char,b,"b")
+DECLARE_IO(short,w,"")
+DECLARE_IO(int,l,"")
+
+#undef DECLARE_IO
+#undef DECLARE_DYN_IN
+
+/*
+ * Constant address IO functions
+ *
+ * These have to be macros for the 'J' constraint to work -
+ * +/-4096 immediate operand.
+ */
+#define __outbc(value,port)                                                     \
+({                                                                              \
+        if (__PORT_PCIO((port)))                                                \
+                __asm__ __volatile__(                                           \
+                "strb   %0, [%1, %2]    @ outbc"                                \
+                : : "r" (value), "r" (PCIO_BASE), "Jr" ((port) << 2));          \
+        else                                                                    \
+                __asm__ __volatile__(                                           \
+                "strb   %0, [%1, %2]    @ outbc"                                \
+                : : "r" (value), "r" (IO_BASE), "r" ((port) << 2));             \
+})
+
+#define __inbc(port)                                                            \
+({                                                                              \
+        unsigned char result;                                                   \
+        if (__PORT_PCIO((port)))                                                \
+                __asm__ __volatile__(                                           \
+                "ldrb   %0, [%1, %2]    @ inbc"                                 \
+                : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2));         \
+        else                                                                    \
+                __asm__ __volatile__(                                           \
+                "ldrb   %0, [%1, %2]    @ inbc"                                 \
+                : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2));            \
+        result;                                                                 \
+})
+
+#define __outwc(value,port)                                                     \
+({                                                                              \
+        unsigned long v = value;                                                \
+        if (__PORT_PCIO((port)))                                                \
+                __asm__ __volatile__(                                           \
+                "str    %0, [%1, %2]    @ outwc"                                \
+                : : "r" (v|v<<16), "r" (PCIO_BASE), "Jr" ((port) << 2));        \
+        else                                                                    \
+                __asm__ __volatile__(                                           \
+                "str    %0, [%1, %2]    @ outwc"                                \
+                : : "r" (v|v<<16), "r" (IO_BASE), "r" ((port) << 2));           \
+})
+
+#define __inwc(port)                                                            \
+({                                                                              \
+        unsigned short result;                                                  \
+        if (__PORT_PCIO((port)))                                                \
+                __asm__ __volatile__(                                           \
+                "ldr    %0, [%1, %2]    @ inwc"                                 \
+                : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2));         \
+        else                                                                    \
+                __asm__ __volatile__(                                           \
+                "ldr    %0, [%1, %2]    @ inwc"                                 \
+                : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2));            \
+        result & 0xffff;                                                        \
+})
+
+#define __outlc(value,port)                                                     \
+({                                                                              \
+        unsigned long v = value;                                                \
+        if (__PORT_PCIO((port)))                                                \
+                __asm__ __volatile__(                                           \
+                "str    %0, [%1, %2]    @ outlc"                                \
+                : : "r" (v), "r" (PCIO_BASE), "Jr" ((port) << 2));              \
+        else                                                                    \
+                __asm__ __volatile__(                                           \
+                "str    %0, [%1, %2]    @ outlc"                                \
+                : : "r" (v), "r" (IO_BASE), "r" ((port) << 2));                 \
+})
+
+#define __inlc(port)                                                            \
+({                                                                              \
+        unsigned long result;                                                   \
+        if (__PORT_PCIO((port)))                                                \
+                __asm__ __volatile__(                                           \
+                "ldr    %0, [%1, %2]    @ inlc"                                 \
+                : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2));         \
+        else                                                                    \
+                __asm__ __volatile__(                                           \
+                "ldr    %0, [%1, %2]    @ inlc"                                 \
+                : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2));            \
+        result;                                                                 \
+})
+
+#define __ioaddrc(port)                                                         \
+        (__PORT_PCIO((port)) ? PCIO_BASE + ((port) << 2) : IO_BASE + ((port) << 2))
+
+#define inb(p)          (__builtin_constant_p((p)) ? __inbc(p)    : __inb(p))
+#define inw(p)          (__builtin_constant_p((p)) ? __inwc(p)    : __inw(p))
+#define inl(p)          (__builtin_constant_p((p)) ? __inlc(p)    : __inl(p))
+#define outb(v,p)       (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p))
+#define outw(v,p)       (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p))
+#define outl(v,p)       (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p))
+#define __ioaddr(p)     (__builtin_constant_p((p)) ? __ioaddr(p)  : __ioaddrc(p))
+/* the following macro is deprecated */
+#define ioaddr(port)                    __ioaddr((port))
+
+#define insb(p,d,l)     __raw_readsb(__ioaddr(p),d,l)
+#define insw(p,d,l)     __raw_readsw(__ioaddr(p),d,l)
+
+#define outsb(p,d,l)    __raw_writesb(__ioaddr(p),d,l)
+#define outsw(p,d,l)    __raw_writesw(__ioaddr(p),d,l)
+
+/*
+ * 1:1 mapping for ioremapped regions.
+ */
+#define __mem_pci(x)    (x)
+
+#endif
diff --git a/arch/arm/mach-clps7500/include/mach/irq.h b/arch/arm/mach-clps7500/include/mach/irq.h
new file mode 100644
index 000000000000..e8da3c58df76
--- /dev/null
+++ b/arch/arm/mach-clps7500/include/mach/irq.h
@@ -0,0 +1,32 @@
+/*
+ * arch/arm/mach-clps7500/include/mach/irq.h
+ *
+ * Copyright (C) 1996 Russell King
+ * Copyright (C) 1999, 2001 Nexus Electronics Ltd.
+ *
+ * Changelog:
+ *   10-10-1996 RMK     Brought up to date with arch-sa110eval
+ *   22-08-1998 RMK     Restructured IRQ routines
+ *   11-08-1999 PJB     Created ARM7500 version, derived from RiscPC code
+ */
+
+#include <asm/hardware/iomd.h>
+#include <asm/io.h>
+
+static inline int fixup_irq(unsigned int irq)
+{
+        if (irq == IRQ_ISA) {
+                int isabits = *((volatile unsigned int *)0xe002b700);
+                if (isabits == 0) {
+                        printk("Spurious ISA IRQ!\n");
+                        return irq;
+                }
+                irq = IRQ_ISA_BASE;
+                while (!(isabits & 1)) {
+                        irq++;
+                        isabits >>= 1;
+                }
+        }
+
+        return irq;
+}
diff --git a/arch/arm/mach-clps7500/include/mach/irqs.h b/arch/arm/mach-clps7500/include/mach/irqs.h
new file mode 100644
index 000000000000..bee66b487f59
--- /dev/null
+++ b/arch/arm/mach-clps7500/include/mach/irqs.h
@@ -0,0 +1,66 @@
+/*
+ * arch/arm/mach-clps7500/include/mach/irqs.h
+ *
+ * Copyright (C) 1999 Nexus Electronics Ltd
+ */
+
+#define IRQ_INT2                0
+#define IRQ_INT1                2
+#define IRQ_VSYNCPULSE          3
+#define IRQ_POWERON             4
+#define IRQ_TIMER0              5
+#define IRQ_TIMER1              6
+#define IRQ_FORCE               7
+#define IRQ_INT8                8
+#define IRQ_ISA                 9
+#define IRQ_INT6                10
+#define IRQ_INT5                11
+#define IRQ_INT4                12
+#define IRQ_INT3                13
+#define IRQ_KEYBOARDTX          14
+#define IRQ_KEYBOARDRX          15
+
+#define IRQ_DMA0                16
+#define IRQ_DMA1                17
+#define IRQ_DMA2                18
+#define IRQ_DMA3                19
+#define IRQ_DMAS0               20
+#define IRQ_DMAS1               21
+
+#define IRQ_IOP0                24
+#define IRQ_IOP1                25
+#define IRQ_IOP2                26
+#define IRQ_IOP3                27
+#define IRQ_IOP4                28
+#define IRQ_IOP5                29
+#define IRQ_IOP6                30
+#define IRQ_IOP7                31
+
+#define IRQ_MOUSERX             40
+#define IRQ_MOUSETX             41
+#define IRQ_ADC                 42
+#define IRQ_EVENT1              43
+#define IRQ_EVENT2              44
+
+#define IRQ_ISA_BASE            48
+#define IRQ_ISA_3               48
+#define IRQ_ISA_4               49
+#define IRQ_ISA_5               50
+#define IRQ_ISA_7               51
+#define IRQ_ISA_9               52
+#define IRQ_ISA_10              53
+#define IRQ_ISA_11              54
+#define IRQ_ISA_14              55      
+
+#define FIQ_INT9                0
+#define FIQ_INT5                1
+#define FIQ_INT6                4
+#define FIQ_INT8                6
+#define FIQ_FORCE               7
+
+/*
+ * This is the offset of the FIQ "IRQ" numbers
+ */
+#define FIQ_START               64
+
+#define IRQ_TIMER               IRQ_TIMER0
diff --git a/arch/arm/mach-clps7500/include/mach/memory.h b/arch/arm/mach-clps7500/include/mach/memory.h
new file mode 100644
index 000000000000..3326aa99d3ec
--- /dev/null
+++ b/arch/arm/mach-clps7500/include/mach/memory.h
@@ -0,0 +1,35 @@
+/*
+ * arch/arm/mach-clps7500/include/mach/memory.h
+ *
+ * Copyright (c) 1996,1997,1998 Russell King.
+ *
+ * Changelog:
+ *  20-Oct-1996 RMK     Created
+ *  31-Dec-1997 RMK     Fixed definitions to reduce warnings
+ *  11-Jan-1998 RMK     Uninlined to reduce hits on cache
+ *  08-Feb-1998 RMK     Added __virt_to_bus and __bus_to_virt
+ *  21-Mar-1999 RMK     Renamed to memory.h
+ *              RMK     Added TASK_SIZE and PAGE_OFFSET
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     UL(0x10000000)
+
+/*
+ * These are exactly the same on the RiscPC as the
+ * physical memory view.
+ */
+#define __virt_to_bus(x) __virt_to_phys(x)
+#define __bus_to_virt(x) __phys_to_virt(x)
+
+/*
+ * Cache flushing area - ROM
+ */
+#define FLUSH_BASE_PHYS         0x00000000
+#define FLUSH_BASE              0xdf000000
+
+#endif
diff --git a/arch/arm/mach-clps7500/include/mach/system.h b/arch/arm/mach-clps7500/include/mach/system.h
new file mode 100644
index 000000000000..624fc2830ae0
--- /dev/null
+++ b/arch/arm/mach-clps7500/include/mach/system.h
@@ -0,0 +1,23 @@
+/*
+ * arch/arm/mach-clps7500/include/mach/system.h
+ *
+ * Copyright (c) 1999 Nexus Electronics Ltd.
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <asm/hardware/iomd.h>
+#include <asm/io.h>
+
+static inline void arch_idle(void)
+{
+        iomd_writeb(0, IOMD_SUSMODE);
+}
+
+#define arch_reset(mode)                        \
+        do {                                    \
+                iomd_writeb(0, IOMD_ROMCR0);    \
+                cpu_reset(0);                   \
+        } while (0)
+
+#endif
diff --git a/arch/arm/mach-clps7500/include/mach/timex.h b/arch/arm/mach-clps7500/include/mach/timex.h
new file mode 100644
index 000000000000..dfaa9b425757
--- /dev/null
+++ b/arch/arm/mach-clps7500/include/mach/timex.h
@@ -0,0 +1,13 @@
+/*
+ * arch/arm/mach-clps7500/include/mach/timex.h
+ *
+ * CL7500 architecture timex specifications
+ *
+ * Copyright (C) 1999 Nexus Electronics Ltd
+ */
+
+/*
+ * On the ARM7500, the clock ticks at 2MHz.
+ */
+#define CLOCK_TICK_RATE         2000000
+
diff --git a/arch/arm/mach-clps7500/include/mach/uncompress.h b/arch/arm/mach-clps7500/include/mach/uncompress.h
new file mode 100644
index 000000000000..d7d0af4b49fc
--- /dev/null
+++ b/arch/arm/mach-clps7500/include/mach/uncompress.h
@@ -0,0 +1,35 @@
+/*
+ * arch/arm/mach-clps7500/include/mach/uncompress.h
+ *
+ * Copyright (C) 1999, 2000 Nexus Electronics Ltd.
+ */
+#define BASE 0x03010000
+#define SERBASE (BASE + (0x2f8 << 2))
+
+static inline void putc(char c)
+{
+        while (!(*((volatile unsigned int *)(SERBASE + 0x14)) & 0x20))
+                barrier();
+
+        *((volatile unsigned int *)(SERBASE)) = c;
+}
+
+static inline void flush(void)
+{
+}
+
+static __inline__ void arch_decomp_setup(void)
+{
+        int baud = 3686400 / (9600 * 32);
+
+        *((volatile unsigned int *)(SERBASE + 0xC)) = 0x80;
+        *((volatile unsigned int *)(SERBASE + 0x0)) = baud & 0xff;
+        *((volatile unsigned int *)(SERBASE + 0x4)) = (baud & 0xff00) >> 8;
+        *((volatile unsigned int *)(SERBASE + 0xC)) = 3; /* 8 bits */
+        *((volatile unsigned int *)(SERBASE + 0x10)) = 3; /* DTR, RTS */
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-clps7500/include/mach/vmalloc.h b/arch/arm/mach-clps7500/include/mach/vmalloc.h
new file mode 100644
index 000000000000..8fc5406d1b6d
--- /dev/null
+++ b/arch/arm/mach-clps7500/include/mach/vmalloc.h
@@ -0,0 +1,4 @@
+/*
+ * arch/arm/mach-clps7500/include/mach/vmalloc.h
+ */
+#define VMALLOC_END       (PAGE_OFFSET + 0x1c000000)
diff --git a/arch/arm/mach-davinci/board-evm.c b/arch/arm/mach-davinci/board-evm.c
index 7497619e4a8a..134355787814 100644
--- a/arch/arm/mach-davinci/board-evm.c
+++ b/arch/arm/mach-davinci/board-evm.c
@@ -20,13 +20,13 @@
 #include <asm/setup.h>
 #include <asm/io.h>
 #include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 
-#include <asm/arch/common.h>
+#include <mach/common.h>
 
 /* other misc. init functions */
 void __init davinci_psc_init(void);
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 0014fb1c6eba..d46c69b55aaa 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -17,10 +17,10 @@
 #include <linux/mutex.h>
 #include <linux/platform_device.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 
-#include <asm/arch/psc.h>
+#include <mach/psc.h>
 #include "clock.h"
 
 /* PLL/Reset register offsets */
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index 9c67886e7189..c9cb4f09b18f 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -20,9 +20,9 @@
 #include <linux/irq.h>
 #include <linux/bitops.h>
 
-#include <asm/arch/irqs.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/gpio.h>
+#include <mach/irqs.h>
+#include <mach/hardware.h>
+#include <mach/gpio.h>
 
 #include <asm/mach/irq.h>
 
diff --git a/arch/arm/mach-davinci/include/mach/clock.h b/arch/arm/mach-davinci/include/mach/clock.h
new file mode 100644
index 000000000000..38bdd49bc181
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/clock.h
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/mach-davinci/include/mach/clock.h
+ *
+ * Clock control driver for DaVinci - header file
+ *
+ * Authors: Vladimir Barinov <source@mvista.com>
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASM_ARCH_DAVINCI_CLOCK_H
+#define __ASM_ARCH_DAVINCI_CLOCK_H
+
+struct clk;
+
+extern int clk_register(struct clk *clk);
+extern void clk_unregister(struct clk *clk);
+extern int davinci_clk_init(void);
+
+#endif
diff --git a/include/asm-arm/arch-davinci/common.h b/arch/arm/mach-davinci/include/mach/common.h
index a97dfbb15e57..a97dfbb15e57 100644
--- a/include/asm-arm/arch-davinci/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
diff --git a/include/asm-arm/arch-davinci/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S
index e6c0f0d5d062..e6c0f0d5d062 100644
--- a/include/asm-arm/arch-davinci/debug-macro.S
+++ b/arch/arm/mach-davinci/include/mach/debug-macro.S
diff --git a/include/asm-arm/arch-davinci/dma.h b/arch/arm/mach-davinci/include/mach/dma.h
index 8e2f2d0ba667..8e2f2d0ba667 100644
--- a/include/asm-arm/arch-davinci/dma.h
+++ b/arch/arm/mach-davinci/include/mach/dma.h
diff --git a/arch/arm/mach-davinci/include/mach/entry-macro.S b/arch/arm/mach-davinci/include/mach/entry-macro.S
new file mode 100644
index 000000000000..039b84f933b3
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/entry-macro.S
@@ -0,0 +1,32 @@
+/*
+ * Low-level IRQ helper macros for TI DaVinci-based platforms
+ *
+ * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#include <mach/io.h>
+#include <mach/irqs.h>
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_preamble, base, tmp
+                ldr \base, =IO_ADDRESS(DAVINCI_ARM_INTC_BASE)
+                .endm
+
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                ldr \tmp, [\base, #0x14]
+                mov \tmp, \tmp, lsr #2
+                sub \irqnr, \tmp, #1
+                cmp \tmp, #0
+                .endm
+
+                .macro  irq_prio_table
+                .endm
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
new file mode 100644
index 000000000000..ec151ccf1e8f
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -0,0 +1,159 @@
+/*
+ * TI DaVinci GPIO Support
+ *
+ * Copyright (c) 2006 David Brownell
+ * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DAVINCI_GPIO_H
+#define __DAVINCI_GPIO_H
+
+#include <linux/io.h>
+#include <mach/hardware.h>
+
+/*
+ * basic gpio routines
+ *
+ * board-specific init should be done by arch/.../.../board-XXX.c (maybe
+ * initializing banks together) rather than boot loaders; kexec() won't
+ * go through boot loaders.
+ *
+ * the gpio clock will be turned on when gpios are used, and you may also
+ * need to pay attention to PINMUX0 and PINMUX1 to be sure those pins are
+ * used as gpios, not with other peripherals.
+ *
+ * GPIOs are numbered 0..(DAVINCI_N_GPIO-1).  For documentation, and maybe
+ * for later updates, code should write GPIO(N) or:
+ *  - GPIOV18(N) for 1.8V pins, N in 0..53; same as GPIO(0)..GPIO(53)
+ *  - GPIOV33(N) for 3.3V pins, N in 0..17; same as GPIO(54)..GPIO(70)
+ *
+ * For GPIO IRQs use gpio_to_irq(GPIO(N)) or gpio_to_irq(GPIOV33(N)) etc
+ * for now, that's != GPIO(N)
+ */
+#define GPIO(X)         (X)             /* 0 <= X <= 70 */
+#define GPIOV18(X)      (X)             /* 1.8V i/o; 0 <= X <= 53 */
+#define GPIOV33(X)      ((X)+54)        /* 3.3V i/o; 0 <= X <= 17 */
+
+struct gpio_controller {
+        u32     dir;
+        u32     out_data;
+        u32     set_data;
+        u32     clr_data;
+        u32     in_data;
+        u32     set_rising;
+        u32     clr_rising;
+        u32     set_falling;
+        u32     clr_falling;
+        u32     intstat;
+};
+
+/* The __gpio_to_controller() and __gpio_mask() functions inline to constants
+ * with constant parameters; or in outlined code they execute at runtime.
+ *
+ * You'd access the controller directly when reading or writing more than
+ * one gpio value at a time, and to support wired logic where the value
+ * being driven by the cpu need not match the value read back.
+ *
+ * These are NOT part of the cross-platform GPIO interface
+ */
+static inline struct gpio_controller *__iomem
+__gpio_to_controller(unsigned gpio)
+{
+        void *__iomem ptr;
+
+        if (gpio < 32)
+                ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10);
+        else if (gpio < 64)
+                ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38);
+        else if (gpio < DAVINCI_N_GPIO)
+                ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60);
+        else
+                ptr = NULL;
+        return ptr;
+}
+
+static inline u32 __gpio_mask(unsigned gpio)
+{
+        return 1 << (gpio % 32);
+}
+
+/* The get/set/clear functions will inline when called with constant
+ * parameters, for low-overhead bitbanging.  Illegal constant parameters
+ * cause link-time errors.
+ *
+ * Otherwise, calls with variable parameters use outlined functions.
+ */
+extern int __error_inval_gpio(void);
+
+extern void __gpio_set(unsigned gpio, int value);
+extern int __gpio_get(unsigned gpio);
+
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+        if (__builtin_constant_p(value)) {
+                struct gpio_controller  *__iomem g;
+                u32                     mask;
+
+                if (gpio >= DAVINCI_N_GPIO)
+                        __error_inval_gpio();
+
+                g = __gpio_to_controller(gpio);
+                mask = __gpio_mask(gpio);
+                if (value)
+                        __raw_writel(mask, &g->set_data);
+                else
+                        __raw_writel(mask, &g->clr_data);
+                return;
+        }
+
+        __gpio_set(gpio, value);
+}
+
+/* Returns zero or nonzero; works for gpios configured as inputs OR
+ * as outputs.
+ *
+ * NOTE: changes in reported values are synchronized to the GPIO clock.
+ * This is most easily seen after calling gpio_set_value() and then immediatly
+ * gpio_get_value(), where the gpio_get_value() would return the old value
+ * until the GPIO clock ticks and the new value gets latched.
+ */
+
+static inline int gpio_get_value(unsigned gpio)
+{
+        struct gpio_controller *__iomem g;
+
+        if (!__builtin_constant_p(gpio))
+                return __gpio_get(gpio);
+
+        if (gpio >= DAVINCI_N_GPIO)
+                return __error_inval_gpio();
+
+        g = __gpio_to_controller(gpio);
+        return !!(__gpio_mask(gpio) & __raw_readl(&g->in_data));
+}
+
+/* powerup default direction is IN */
+extern int gpio_direction_input(unsigned gpio);
+extern int gpio_direction_output(unsigned gpio, int value);
+
+#include <asm-generic/gpio.h>   /* cansleep wrappers */
+
+extern int gpio_request(unsigned gpio, const char *tag);
+extern void gpio_free(unsigned gpio);
+
+static inline int gpio_to_irq(unsigned gpio)
+{
+        return DAVINCI_N_AINTC_IRQ + gpio;
+}
+
+static inline int irq_to_gpio(unsigned irq)
+{
+        return irq - DAVINCI_N_AINTC_IRQ;
+}
+
+#endif                          /* __DAVINCI_GPIO_H */
diff --git a/include/asm-arm/arch-davinci/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h
index a2e8969afaca..a2e8969afaca 100644
--- a/include/asm-arm/arch-davinci/hardware.h
+++ b/arch/arm/mach-davinci/include/mach/hardware.h
diff --git a/include/asm-arm/arch-davinci/i2c.h b/arch/arm/mach-davinci/include/mach/i2c.h
index e2f54168abd1..e2f54168abd1 100644
--- a/include/asm-arm/arch-davinci/i2c.h
+++ b/arch/arm/mach-davinci/include/mach/i2c.h
diff --git a/include/asm-arm/arch-davinci/io.h b/arch/arm/mach-davinci/include/mach/io.h
index e7accb910864..e7accb910864 100644
--- a/include/asm-arm/arch-davinci/io.h
+++ b/arch/arm/mach-davinci/include/mach/io.h
diff --git a/include/asm-arm/arch-davinci/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h
index f4c5ca6da9f4..f4c5ca6da9f4 100644
--- a/include/asm-arm/arch-davinci/irqs.h
+++ b/arch/arm/mach-davinci/include/mach/irqs.h
diff --git a/include/asm-arm/arch-davinci/memory.h b/arch/arm/mach-davinci/include/mach/memory.h
index dd1625c23cf4..dd1625c23cf4 100644
--- a/include/asm-arm/arch-davinci/memory.h
+++ b/arch/arm/mach-davinci/include/mach/memory.h
diff --git a/include/asm-arm/arch-davinci/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index c24b6782804d..c24b6782804d 100644
--- a/include/asm-arm/arch-davinci/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
diff --git a/include/asm-arm/arch-davinci/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 4977aa071e1e..4977aa071e1e 100644
--- a/include/asm-arm/arch-davinci/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
new file mode 100644
index 000000000000..fb8cb229bfd2
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -0,0 +1,20 @@
+/*
+ * DaVinci serial device definitions
+ *
+ * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASM_ARCH_SERIAL_H
+#define __ASM_ARCH_SERIAL_H
+
+#include <mach/io.h>
+
+#define DAVINCI_UART0_BASE   (IO_PHYS + 0x20000)
+#define DAVINCI_UART1_BASE   (IO_PHYS + 0x20400)
+#define DAVINCI_UART2_BASE   (IO_PHYS + 0x20800)
+
+#endif /* __ASM_ARCH_SERIAL_H */
diff --git a/arch/arm/mach-davinci/include/mach/system.h b/arch/arm/mach-davinci/include/mach/system.h
new file mode 100644
index 000000000000..84ff77aeb738
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/system.h
@@ -0,0 +1,29 @@
+/*
+ * DaVinci system defines
+ *
+ * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <asm/io.h>
+#include <mach/hardware.h>
+
+extern void davinci_watchdog_reset(void);
+
+static void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static void arch_reset(char mode)
+{
+        davinci_watchdog_reset();
+}
+
+#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/include/asm-arm/arch-davinci/timex.h b/arch/arm/mach-davinci/include/mach/timex.h
index 52827567841d..52827567841d 100644
--- a/include/asm-arm/arch-davinci/timex.h
+++ b/arch/arm/mach-davinci/include/mach/timex.h
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
new file mode 100644
index 000000000000..8c165def37b6
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -0,0 +1,35 @@
+/*
+ * Serial port stubs for kernel decompress status messages
+ *
+ *  Author:     Anant Gole
+ * (C) Copyright (C) 2006, Texas Instruments, Inc
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/types.h>
+#include <linux/serial_reg.h>
+#include <mach/serial.h>
+
+/* PORT_16C550A, in polled non-fifo mode */
+
+static void putc(char c)
+{
+        volatile u32 *uart = (volatile void *) DAVINCI_UART0_BASE;
+
+        while (!(uart[UART_LSR] & UART_LSR_THRE))
+                barrier();
+        uart[UART_TX] = c;
+}
+
+static inline void flush(void)
+{
+        volatile u32 *uart = (volatile void *) DAVINCI_UART0_BASE;
+        while (!(uart[UART_LSR] & UART_LSR_THRE))
+                barrier();
+}
+
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-davinci/include/mach/vmalloc.h b/arch/arm/mach-davinci/include/mach/vmalloc.h
new file mode 100644
index 000000000000..b98bd9e92fd6
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/vmalloc.h
@@ -0,0 +1,15 @@
+/*
+ * DaVinci vmalloc definitions
+ *
+ * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#include <asm/memory.h>
+#include <mach/io.h>
+
+/* Allow vmalloc range until the IO virtual range minus a 2M "hole" */
+#define VMALLOC_END       (IO_VIRT - (2<<20))
diff --git a/arch/arm/mach-davinci/io.c b/arch/arm/mach-davinci/io.c
index 47787ff84a6a..5bb66b61c1a3 100644
--- a/arch/arm/mach-davinci/io.c
+++ b/arch/arm/mach-davinci/io.c
@@ -17,7 +17,7 @@
 #include <asm/memory.h>
 
 #include <asm/mach/map.h>
-#include <asm/arch/clock.h>
+#include <mach/clock.h>
 
 extern void davinci_check_revision(void);
 
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c
index 090580ed88ef..12ca9f29f847 100644
--- a/arch/arm/mach-davinci/irq.c
+++ b/arch/arm/mach-davinci/irq.c
@@ -23,7 +23,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/mach/irq.h>
 
diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c
index 439bf94bdc4e..8ff9d8aca60b 100644
--- a/arch/arm/mach-davinci/mux.c
+++ b/arch/arm/mach-davinci/mux.c
@@ -11,9 +11,9 @@
 #include <linux/io.h>
 #include <linux/spinlock.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
-#include <asm/arch/mux.h>
+#include <mach/mux.h>
 
 /* System control register offsets */
 #define PINMUX0         0x00
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c
index 753f0ba81a44..720c48b9ee04 100644
--- a/arch/arm/mach-davinci/psc.c
+++ b/arch/arm/mach-davinci/psc.c
@@ -23,9 +23,9 @@
 #include <linux/init.h>
 
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/psc.h>
-#include <asm/arch/mux.h>
+#include <mach/hardware.h>
+#include <mach/psc.h>
+#include <mach/mux.h>
 
 /* PSC register offsets */
 #define EPCPR           0x070
diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
index c2b812f3391c..caf101e2cc62 100644
--- a/arch/arm/mach-davinci/serial.c
+++ b/arch/arm/mach-davinci/serial.c
@@ -29,9 +29,9 @@
 
 #include <asm/io.h>
 #include <asm/irq.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/serial.h>
-#include <asm/arch/irqs.h>
+#include <mach/hardware.h>
+#include <mach/serial.h>
+#include <mach/irqs.h>
 
 #define UART_DAVINCI_PWREMU 0x0c
 
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 50c3b54c4ccd..206e80d41717 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -17,13 +17,13 @@
 #include <linux/spinlock.h>
 
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/system.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
 #include <asm/errno.h>
-#include <asm/arch/io.h>
+#include <mach/io.h>
 
 static struct clock_event_device clockevent_davinci;
 
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index 31f4f213cce3..65cc7c271917 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -15,7 +15,7 @@
 #include <linux/serial_8250.h>
 #include <linux/init.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/io.h>
 #include <asm/setup.h>
diff --git a/arch/arm/mach-ebsa110/include/mach/debug-macro.S b/arch/arm/mach-ebsa110/include/mach/debug-macro.S
new file mode 100644
index 000000000000..1dde8227f3a2
--- /dev/null
+++ b/arch/arm/mach-ebsa110/include/mach/debug-macro.S
@@ -0,0 +1,21 @@
+/* arch/arm/mach-ebsa110/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+**/
+
+                .macro  addruart,rx
+                mov     \rx, #0xf0000000
+                orr     \rx, \rx, #0x00000be0
+                .endm
+
+#define UART_SHIFT      2
+#define FLOW_CONTROL
+#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-ebsa110/include/mach/dma.h b/arch/arm/mach-ebsa110/include/mach/dma.h
new file mode 100644
index 000000000000..780a04c8bbe9
--- /dev/null
+++ b/arch/arm/mach-ebsa110/include/mach/dma.h
@@ -0,0 +1,11 @@
+/*
+ *  arch/arm/mach-ebsa110/include/mach/dma.h
+ *
+ *  Copyright (C) 1997,1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  EBSA110 DMA definitions
+ */
diff --git a/arch/arm/mach-ebsa110/include/mach/entry-macro.S b/arch/arm/mach-ebsa110/include/mach/entry-macro.S
new file mode 100644
index 000000000000..cc3e5992f6b3
--- /dev/null
+++ b/arch/arm/mach-ebsa110/include/mach/entry-macro.S
@@ -0,0 +1,39 @@
+/*
+ * arch/arm/mach-ebsa110/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for ebsa110 platform.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+
+
+#define IRQ_STAT                0xff000000      /* read */
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        mov     \base, #IRQ_STAT
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, stat, base, tmp
+        ldrb    \stat, [\base]                  @ get interrupts
+        mov     \irqnr, #0
+        tst     \stat, #15
+        addeq   \irqnr, \irqnr, #4
+        moveq   \stat, \stat, lsr #4
+        tst     \stat, #3
+        addeq   \irqnr, \irqnr, #2
+        moveq   \stat, \stat, lsr #2
+        tst     \stat, #1
+        addeq   \irqnr, \irqnr, #1
+        moveq   \stat, \stat, lsr #1
+        tst     \stat, #1                       @ bit 0 should be set
+        .endm
+
diff --git a/arch/arm/mach-ebsa110/include/mach/hardware.h b/arch/arm/mach-ebsa110/include/mach/hardware.h
new file mode 100644
index 000000000000..4b2fb7743909
--- /dev/null
+++ b/arch/arm/mach-ebsa110/include/mach/hardware.h
@@ -0,0 +1,63 @@
+/*
+ *  arch/arm/mach-ebsa110/include/mach/hardware.h
+ *
+ *  Copyright (C) 1996-2000 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file contains the hardware definitions of the EBSA-110.
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+/*
+ * The EBSA110 has a weird "ISA IO" region:
+ *
+ * Region 0 (addr = 0xf0000000 + io << 2)
+ * --------------------------------------------------------
+ * Physical region      IO region
+ * f0000fe0 - f0000ffc  3f8 - 3ff  ttyS0
+ * f0000e60 - f0000e64  398 - 399
+ * f0000de0 - f0000dfc  378 - 37f  lp0
+ * f0000be0 - f0000bfc  2f8 - 2ff  ttyS1
+ *
+ * Region 1 (addr = 0xf0000000 + (io & ~1) << 1 + (io & 1))
+ * --------------------------------------------------------
+ * Physical region      IO region
+ * f00014f1             a79        pnp write data
+ * f00007c0 - f00007c1  3e0 - 3e1  pcmcia
+ * f00004f1             279        pnp address
+ * f0000440 - f000046c  220 - 236  eth0
+ * f0000405             203        pnp read data
+ */
+
+#define ISAMEM_PHYS             0xe0000000
+#define ISAMEM_SIZE             0x10000000
+
+#define ISAIO_PHYS              0xf0000000
+#define ISAIO_SIZE              PGDIR_SIZE
+
+#define TRICK0_PHYS             0xf2000000
+#define TRICK1_PHYS             0xf2400000
+#define TRICK2_PHYS             0xf2800000
+#define TRICK3_PHYS             0xf2c00000
+#define TRICK4_PHYS             0xf3000000
+#define TRICK5_PHYS             0xf3400000
+#define TRICK6_PHYS             0xf3800000
+#define TRICK7_PHYS             0xf3c00000
+
+#define ISAMEM_BASE             0xe0000000
+#define ISAIO_BASE              0xf0000000
+
+#define PIT_BASE                0xfc000000
+#define SOFT_BASE               0xfd000000
+
+/*
+ * RAM definitions
+ */
+#define UNCACHEABLE_ADDR        0xff000000      /* IRQ_STAT */
+
+#endif
+
diff --git a/arch/arm/mach-ebsa110/include/mach/io.h b/arch/arm/mach-ebsa110/include/mach/io.h
new file mode 100644
index 000000000000..f68daa632af0
--- /dev/null
+++ b/arch/arm/mach-ebsa110/include/mach/io.h
@@ -0,0 +1,92 @@
+/*
+ *  arch/arm/mach-ebsa110/include/mach/io.h
+ *
+ *  Copyright (C) 1997,1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ *  06-Dec-1997 RMK     Created.
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffff
+
+u8 __inb8(unsigned int port);
+void __outb8(u8  val, unsigned int port);
+
+u8 __inb16(unsigned int port);
+void __outb16(u8  val, unsigned int port);
+
+u16 __inw(unsigned int port);
+void __outw(u16 val, unsigned int port);
+
+u32 __inl(unsigned int port);
+void __outl(u32 val, unsigned int port);
+
+u8  __readb(const volatile void __iomem *addr);
+u16 __readw(const volatile void __iomem *addr);
+u32 __readl(const volatile void __iomem *addr);
+
+void __writeb(u8  val, void __iomem *addr);
+void __writew(u16 val, void __iomem *addr);
+void __writel(u32 val, void __iomem *addr);
+
+/*
+ * Argh, someone forgot the IOCS16 line.  We therefore have to handle
+ * the byte stearing by selecting the correct byte IO functions here.
+ */
+#ifdef ISA_SIXTEEN_BIT_PERIPHERAL
+#define inb(p)                  __inb16(p)
+#define outb(v,p)               __outb16(v,p)
+#else
+#define inb(p)                  __inb8(p)
+#define outb(v,p)               __outb8(v,p)
+#endif
+
+#define inw(p)                  __inw(p)
+#define outw(v,p)               __outw(v,p)
+
+#define inl(p)                  __inl(p)
+#define outl(v,p)               __outl(v,p)
+
+#define readb(b)                __readb(b)
+#define readw(b)                __readw(b)
+#define readl(b)                __readl(b)
+#define readb_relaxed(addr)     readb(addr)
+#define readw_relaxed(addr)     readw(addr)
+#define readl_relaxed(addr)     readl(addr)
+
+#define writeb(v,b)             __writeb(v,b)
+#define writew(v,b)             __writew(v,b)
+#define writel(v,b)             __writel(v,b)
+
+static inline void __iomem *__arch_ioremap(unsigned long cookie, size_t size,
+                                           unsigned int flags)
+{
+        return (void __iomem *)cookie;
+}
+
+#define __arch_ioremap          __arch_ioremap
+#define __arch_iounmap(cookie)  do { } while (0)
+
+extern void insb(unsigned int port, void *buf, int sz);
+extern void insw(unsigned int port, void *buf, int sz);
+extern void insl(unsigned int port, void *buf, int sz);
+
+extern void outsb(unsigned int port, const void *buf, int sz);
+extern void outsw(unsigned int port, const void *buf, int sz);
+extern void outsl(unsigned int port, const void *buf, int sz);
+
+/* can't support writesb atm */
+extern void writesw(void __iomem *addr, const void *data, int wordlen);
+extern void writesl(void __iomem *addr, const void *data, int longlen);
+
+/* can't support readsb atm */
+extern void readsw(const void __iomem *addr, void *data, int wordlen);
+extern void readsl(const void __iomem *addr, void *data, int longlen);
+
+#endif
diff --git a/arch/arm/mach-ebsa110/include/mach/irqs.h b/arch/arm/mach-ebsa110/include/mach/irqs.h
new file mode 100644
index 000000000000..a8f3771bc060
--- /dev/null
+++ b/arch/arm/mach-ebsa110/include/mach/irqs.h
@@ -0,0 +1,20 @@
+/*
+ *  arch/arm/mach-ebsa110/include/mach/irqs.h
+ *
+ *  Copyright (C) 1996 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define NR_IRQS                 8
+
+#define IRQ_EBSA110_PRINTER     0
+#define IRQ_EBSA110_COM1        1
+#define IRQ_EBSA110_COM2        2
+#define IRQ_EBSA110_ETHERNET    3
+#define IRQ_EBSA110_TIMER0      4
+#define IRQ_EBSA110_TIMER1      5
+#define IRQ_EBSA110_PCMCIA      6
+#define IRQ_EBSA110_IMMEDIATE   7
diff --git a/arch/arm/mach-ebsa110/include/mach/memory.h b/arch/arm/mach-ebsa110/include/mach/memory.h
new file mode 100644
index 000000000000..eea4b75b657b
--- /dev/null
+++ b/arch/arm/mach-ebsa110/include/mach/memory.h
@@ -0,0 +1,37 @@
+/*
+ *  arch/arm/mach-ebsa110/include/mach/memory.h
+ *
+ *  Copyright (C) 1996-1999 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   20-Oct-1996 RMK    Created
+ *   31-Dec-1997 RMK    Fixed definitions to reduce warnings
+ *   21-Mar-1999 RMK    Renamed to memory.h
+ *               RMK    Moved TASK_SIZE and PAGE_OFFSET here
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     UL(0x00000000)
+
+/*
+ * We keep this 1:1 so that we don't interfere
+ * with the PCMCIA memory regions
+ */
+#define __virt_to_bus(x)        (x)
+#define __bus_to_virt(x)        (x)
+
+/*
+ * Cache flushing area - SRAM
+ */
+#define FLUSH_BASE_PHYS         0x40000000
+#define FLUSH_BASE              0xdf000000
+
+#endif
diff --git a/arch/arm/mach-ebsa110/include/mach/system.h b/arch/arm/mach-ebsa110/include/mach/system.h
new file mode 100644
index 000000000000..350a028997ef
--- /dev/null
+++ b/arch/arm/mach-ebsa110/include/mach/system.h
@@ -0,0 +1,39 @@
+/*
+ *  arch/arm/mach-ebsa110/include/mach/system.h
+ *
+ *  Copyright (C) 1996-2000 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+/*
+ * EBSA110 idling methodology:
+ *
+ * We can not execute the "wait for interrupt" instruction since that
+ * will stop our MCLK signal (which provides the clock for the glue
+ * logic, and therefore the timer interrupt).
+ *
+ * Instead, we spin, polling the IRQ_STAT register for the occurrence
+ * of any interrupt with core clock down to the memory clock.
+ */
+static inline void arch_idle(void)
+{
+        const char *irq_stat = (char *)0xff000000;
+
+        /* disable clock switching */
+        asm volatile ("mcr p15, 0, ip, c15, c2, 2" : : : "cc");
+
+        /* wait for an interrupt to occur */
+        while (!*irq_stat);
+
+        /* enable clock switching */
+        asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc");
+}
+
+#define arch_reset(mode)        cpu_reset(0x80000000)
+
+#endif
diff --git a/arch/arm/mach-ebsa110/include/mach/timex.h b/arch/arm/mach-ebsa110/include/mach/timex.h
new file mode 100644
index 000000000000..4fb43b22a102
--- /dev/null
+++ b/arch/arm/mach-ebsa110/include/mach/timex.h
@@ -0,0 +1,19 @@
+/*
+ *  arch/arm/mach-ebsa110/include/mach/timex.h
+ *
+ *  Copyright (C) 1997, 1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  EBSA110 architecture timex specifications
+ */
+
+/*
+ * On the EBSA, the clock ticks at weird rates.
+ * This is therefore not used to calculate the
+ * divisor.
+ */
+#define CLOCK_TICK_RATE         47894000
+
diff --git a/arch/arm/mach-ebsa110/include/mach/uncompress.h b/arch/arm/mach-ebsa110/include/mach/uncompress.h
new file mode 100644
index 000000000000..32041509fbf8
--- /dev/null
+++ b/arch/arm/mach-ebsa110/include/mach/uncompress.h
@@ -0,0 +1,45 @@
+/*
+ *  arch/arm/mach-ebsa110/include/mach/uncompress.h
+ *
+ *  Copyright (C) 1996,1997,1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/serial_reg.h>
+
+#define SERIAL_BASE     ((unsigned char *)0xf0000be0)
+
+/*
+ * This does not append a newline
+ */
+static inline void putc(int c)
+{
+        unsigned char v, *base = SERIAL_BASE;
+
+        do {
+                v = base[UART_LSR << 2];
+                barrier();
+        } while (!(v & UART_LSR_THRE));
+
+        base[UART_TX << 2] = c;
+}
+
+static inline void flush(void)
+{
+        unsigned char v, *base = SERIAL_BASE;
+
+        do {
+                v = base[UART_LSR << 2];
+                barrier();
+        } while ((v & (UART_LSR_TEMT|UART_LSR_THRE)) !=
+                 (UART_LSR_TEMT|UART_LSR_THRE));
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-ebsa110/include/mach/vmalloc.h b/arch/arm/mach-ebsa110/include/mach/vmalloc.h
new file mode 100644
index 000000000000..9b44c19e95ec
--- /dev/null
+++ b/arch/arm/mach-ebsa110/include/mach/vmalloc.h
@@ -0,0 +1,10 @@
+/*
+ *  arch/arm/mach-ebsa110/include/mach/vmalloc.h
+ *
+ *  Copyright (C) 1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#define VMALLOC_END       (PAGE_OFFSET + 0x1f000000)
diff --git a/arch/arm/mach-ebsa110/io.c b/arch/arm/mach-ebsa110/io.c
index a2027adeefcb..53748f5462e9 100644
--- a/arch/arm/mach-ebsa110/io.c
+++ b/arch/arm/mach-ebsa110/io.c
@@ -24,7 +24,7 @@
 #include <linux/kernel.h>
 #include <linux/types.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/page.h>
 
diff --git a/arch/arm/mach-ebsa110/leds.c b/arch/arm/mach-ebsa110/leds.c
index b16d01679772..6a6ea57c2a4e 100644
--- a/arch/arm/mach-ebsa110/leds.c
+++ b/arch/arm/mach-ebsa110/leds.c
@@ -15,7 +15,7 @@
 #include <linux/spinlock.h>
 #include <linux/init.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/system.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c
index 8f87f8a41483..aa1fb352fb8f 100644
--- a/arch/arm/mach-ep93xx/adssphere.c
+++ b/arch/arm/mach-ep93xx/adssphere.c
@@ -19,7 +19,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index 4642c70f21e0..6062e47f2043 100644
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -16,7 +16,7 @@
 #include <linux/module.h>
 #include <linux/string.h>
 #include <asm/div64.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 
 struct clk {
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index b49da117af9b..f99f43669392 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -36,7 +36,7 @@
 #include <asm/types.h>
 #include <asm/setup.h>
 #include <asm/memory.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/system.h>
 #include <asm/tlbflush.h>
@@ -46,7 +46,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
-#include <asm/arch/gpio.h>
+#include <mach/gpio.h>
 
 #include <asm/hardware/vic.h>
 
diff --git a/arch/arm/mach-ep93xx/edb9302.c b/arch/arm/mach-ep93xx/edb9302.c
index 1650ec724228..97550c0ad7b0 100644
--- a/arch/arm/mach-ep93xx/edb9302.c
+++ b/arch/arm/mach-ep93xx/edb9302.c
@@ -19,7 +19,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
diff --git a/arch/arm/mach-ep93xx/edb9302a.c b/arch/arm/mach-ep93xx/edb9302a.c
index 00208ce6e620..99b01d44bf1c 100644
--- a/arch/arm/mach-ep93xx/edb9302a.c
+++ b/arch/arm/mach-ep93xx/edb9302a.c
@@ -19,7 +19,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
diff --git a/arch/arm/mach-ep93xx/edb9307.c b/arch/arm/mach-ep93xx/edb9307.c
index 78d04aeca463..9fb72d01a36c 100644
--- a/arch/arm/mach-ep93xx/edb9307.c
+++ b/arch/arm/mach-ep93xx/edb9307.c
@@ -19,7 +19,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
diff --git a/arch/arm/mach-ep93xx/edb9312.c b/arch/arm/mach-ep93xx/edb9312.c
index d658fb2f574b..87267a574f5e 100644
--- a/arch/arm/mach-ep93xx/edb9312.c
+++ b/arch/arm/mach-ep93xx/edb9312.c
@@ -20,7 +20,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
diff --git a/arch/arm/mach-ep93xx/edb9315.c b/arch/arm/mach-ep93xx/edb9315.c
index 4fd1cd671521..7e373950be4d 100644
--- a/arch/arm/mach-ep93xx/edb9315.c
+++ b/arch/arm/mach-ep93xx/edb9315.c
@@ -19,7 +19,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
diff --git a/arch/arm/mach-ep93xx/edb9315a.c b/arch/arm/mach-ep93xx/edb9315a.c
index 44dacbac8635..08a7c9bfb689 100644
--- a/arch/arm/mach-ep93xx/edb9315a.c
+++ b/arch/arm/mach-ep93xx/edb9315a.c
@@ -19,7 +19,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c
index cc80031b4ef8..9b41ec1f089e 100644
--- a/arch/arm/mach-ep93xx/gesbc9312.c
+++ b/arch/arm/mach-ep93xx/gesbc9312.c
@@ -19,7 +19,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c
index dc2e4c00d989..0f3fb87ca4be 100644
--- a/arch/arm/mach-ep93xx/gpio.c
+++ b/arch/arm/mach-ep93xx/gpio.c
@@ -17,7 +17,7 @@
 #include <linux/module.h>
 #include <linux/seq_file.h>
 
-#include <asm/arch/ep93xx-regs.h>
+#include <mach/ep93xx-regs.h>
 #include <asm/io.h>
 #include <asm/gpio.h>
 
diff --git a/arch/arm/mach-ep93xx/include/mach/debug-macro.S b/arch/arm/mach-ep93xx/include/mach/debug-macro.S
new file mode 100644
index 000000000000..802858bc8095
--- /dev/null
+++ b/arch/arm/mach-ep93xx/include/mach/debug-macro.S
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/mach-ep93xx/include/mach/debug-macro.S
+ * Debugging macro include header
+ *
+ * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ */
+#include <mach/ep93xx-regs.h>
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                         @ MMU enabled?
+                ldreq   \rx, =EP93XX_APB_PHYS_BASE      @ Physical base
+                ldrne   \rx, =EP93XX_APB_VIRT_BASE      @ virtual base
+                orr     \rx, \rx, #0x000c0000
+                .endm
+
+#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-ep93xx/include/mach/dma.h b/arch/arm/mach-ep93xx/include/mach/dma.h
new file mode 100644
index 000000000000..d0fa9656e92f
--- /dev/null
+++ b/arch/arm/mach-ep93xx/include/mach/dma.h
@@ -0,0 +1,3 @@
+/*
+ * arch/arm/mach-ep93xx/include/mach/dma.h
+ */
diff --git a/arch/arm/mach-ep93xx/include/mach/entry-macro.S b/arch/arm/mach-ep93xx/include/mach/entry-macro.S
new file mode 100644
index 000000000000..96b85e2c2c0b
--- /dev/null
+++ b/arch/arm/mach-ep93xx/include/mach/entry-macro.S
@@ -0,0 +1,59 @@
+/*
+ * arch/arm/mach-ep93xx/include/mach/entry-macro.S
+ * IRQ demultiplexing for EP93xx
+ *
+ * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ */
+#include <mach/ep93xx-regs.h>
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_preamble, base, tmp
+                .endm
+
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                ldr     \base, =(EP93XX_AHB_VIRT_BASE)
+                orr     \base, \base, #0x000b0000
+                mov     \irqnr, #0
+                ldr     \irqstat, [\base]               @ lower 32 interrupts
+                cmp     \irqstat, #0
+                bne     1001f
+
+                eor     \base, \base, #0x00070000
+                ldr     \irqstat, [\base]               @ upper 32 interrupts
+                cmp     \irqstat, #0
+                beq     1002f
+                mov     \irqnr, #0x20
+
+1001:
+                movs    \tmp, \irqstat, lsl #16
+                movne   \irqstat, \tmp
+                addeq   \irqnr, \irqnr, #16
+
+                movs    \tmp, \irqstat, lsl #8
+                movne   \irqstat, \tmp
+                addeq   \irqnr, \irqnr, #8
+
+                movs    \tmp, \irqstat, lsl #4
+                movne   \irqstat, \tmp
+                addeq   \irqnr, \irqnr, #4
+
+                movs    \tmp, \irqstat, lsl #2
+                movne   \irqstat, \tmp
+                addeq   \irqnr, \irqnr, #2
+
+                movs    \tmp, \irqstat, lsl #1
+                addeq   \irqnr, \irqnr, #1
+                orrs    \base, \base, #1
+
+1002:
+                .endm
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
new file mode 100644
index 000000000000..9f4458c8e070
--- /dev/null
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
@@ -0,0 +1,133 @@
+/*
+ * arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+ */
+
+#ifndef __ASM_ARCH_EP93XX_REGS_H
+#define __ASM_ARCH_EP93XX_REGS_H
+
+/*
+ * EP93xx linux memory map:
+ *
+ * virt         phys            size
+ * fe800000                     5M              per-platform mappings
+ * fed00000     80800000        2M              APB
+ * fef00000     80000000        1M              AHB
+ */
+
+#define EP93XX_AHB_PHYS_BASE            0x80000000
+#define EP93XX_AHB_VIRT_BASE            0xfef00000
+#define EP93XX_AHB_SIZE                 0x00100000
+
+#define EP93XX_APB_PHYS_BASE            0x80800000
+#define EP93XX_APB_VIRT_BASE            0xfed00000
+#define EP93XX_APB_SIZE                 0x00200000
+
+
+/* AHB peripherals */
+#define EP93XX_DMA_BASE                 (EP93XX_AHB_VIRT_BASE + 0x00000000)
+
+#define EP93XX_ETHERNET_BASE            (EP93XX_AHB_VIRT_BASE + 0x00010000)
+#define EP93XX_ETHERNET_PHYS_BASE       (EP93XX_AHB_PHYS_BASE + 0x00010000)
+
+#define EP93XX_USB_BASE                 (EP93XX_AHB_VIRT_BASE + 0x00020000)
+#define EP93XX_USB_PHYS_BASE            (EP93XX_AHB_PHYS_BASE + 0x00020000)
+
+#define EP93XX_RASTER_BASE              (EP93XX_AHB_VIRT_BASE + 0x00030000)
+
+#define EP93XX_GRAPHICS_ACCEL_BASE      (EP93XX_AHB_VIRT_BASE + 0x00040000)
+
+#define EP93XX_SDRAM_CONTROLLER_BASE    (EP93XX_AHB_VIRT_BASE + 0x00060000)
+
+#define EP93XX_PCMCIA_CONTROLLER_BASE   (EP93XX_AHB_VIRT_BASE + 0x00080000)
+
+#define EP93XX_BOOT_ROM_BASE            (EP93XX_AHB_VIRT_BASE + 0x00090000)
+
+#define EP93XX_IDE_BASE                 (EP93XX_AHB_VIRT_BASE + 0x000a0000)
+
+#define EP93XX_VIC1_BASE                (EP93XX_AHB_VIRT_BASE + 0x000b0000)
+
+#define EP93XX_VIC2_BASE                (EP93XX_AHB_VIRT_BASE + 0x000c0000)
+
+
+/* APB peripherals */
+#define EP93XX_TIMER_BASE               (EP93XX_APB_VIRT_BASE + 0x00010000)
+#define EP93XX_TIMER_REG(x)             (EP93XX_TIMER_BASE + (x))
+#define EP93XX_TIMER1_LOAD              EP93XX_TIMER_REG(0x00)
+#define EP93XX_TIMER1_VALUE             EP93XX_TIMER_REG(0x04)
+#define EP93XX_TIMER1_CONTROL           EP93XX_TIMER_REG(0x08)
+#define EP93XX_TIMER1_CLEAR             EP93XX_TIMER_REG(0x0c)
+#define EP93XX_TIMER2_LOAD              EP93XX_TIMER_REG(0x20)
+#define EP93XX_TIMER2_VALUE             EP93XX_TIMER_REG(0x24)
+#define EP93XX_TIMER2_CONTROL           EP93XX_TIMER_REG(0x28)
+#define EP93XX_TIMER2_CLEAR             EP93XX_TIMER_REG(0x2c)
+#define EP93XX_TIMER4_VALUE_LOW         EP93XX_TIMER_REG(0x60)
+#define EP93XX_TIMER4_VALUE_HIGH        EP93XX_TIMER_REG(0x64)
+#define EP93XX_TIMER3_LOAD              EP93XX_TIMER_REG(0x80)
+#define EP93XX_TIMER3_VALUE             EP93XX_TIMER_REG(0x84)
+#define EP93XX_TIMER3_CONTROL           EP93XX_TIMER_REG(0x88)
+#define EP93XX_TIMER3_CLEAR             EP93XX_TIMER_REG(0x8c)
+
+#define EP93XX_I2S_BASE                 (EP93XX_APB_VIRT_BASE + 0x00020000)
+
+#define EP93XX_SECURITY_BASE            (EP93XX_APB_VIRT_BASE + 0x00030000)
+
+#define EP93XX_GPIO_BASE                (EP93XX_APB_VIRT_BASE + 0x00040000)
+#define EP93XX_GPIO_REG(x)              (EP93XX_GPIO_BASE + (x))
+#define EP93XX_GPIO_F_INT_TYPE1         EP93XX_GPIO_REG(0x4c)
+#define EP93XX_GPIO_F_INT_TYPE2         EP93XX_GPIO_REG(0x50)
+#define EP93XX_GPIO_F_INT_ACK           EP93XX_GPIO_REG(0x54)
+#define EP93XX_GPIO_F_INT_ENABLE        EP93XX_GPIO_REG(0x58)
+#define EP93XX_GPIO_F_INT_STATUS        EP93XX_GPIO_REG(0x5c)
+#define EP93XX_GPIO_A_INT_TYPE1         EP93XX_GPIO_REG(0x90)
+#define EP93XX_GPIO_A_INT_TYPE2         EP93XX_GPIO_REG(0x94)
+#define EP93XX_GPIO_A_INT_ACK           EP93XX_GPIO_REG(0x98)
+#define EP93XX_GPIO_A_INT_ENABLE        EP93XX_GPIO_REG(0x9c)
+#define EP93XX_GPIO_A_INT_STATUS        EP93XX_GPIO_REG(0xa0)
+#define EP93XX_GPIO_B_INT_TYPE1         EP93XX_GPIO_REG(0xac)
+#define EP93XX_GPIO_B_INT_TYPE2         EP93XX_GPIO_REG(0xb0)
+#define EP93XX_GPIO_B_INT_ACK           EP93XX_GPIO_REG(0xb4)
+#define EP93XX_GPIO_B_INT_ENABLE        EP93XX_GPIO_REG(0xb8)
+#define EP93XX_GPIO_B_INT_STATUS        EP93XX_GPIO_REG(0xbc)
+
+#define EP93XX_AAC_BASE                 (EP93XX_APB_VIRT_BASE + 0x00080000)
+
+#define EP93XX_SPI_BASE                 (EP93XX_APB_VIRT_BASE + 0x000a0000)
+
+#define EP93XX_IRDA_BASE                (EP93XX_APB_VIRT_BASE + 0x000b0000)
+
+#define EP93XX_UART1_BASE               (EP93XX_APB_VIRT_BASE + 0x000c0000)
+#define EP93XX_UART1_PHYS_BASE          (EP93XX_APB_PHYS_BASE + 0x000c0000)
+
+#define EP93XX_UART2_BASE               (EP93XX_APB_VIRT_BASE + 0x000d0000)
+#define EP93XX_UART2_PHYS_BASE          (EP93XX_APB_PHYS_BASE + 0x000d0000)
+
+#define EP93XX_UART3_BASE               (EP93XX_APB_VIRT_BASE + 0x000e0000)
+#define EP93XX_UART3_PHYS_BASE          (EP93XX_APB_PHYS_BASE + 0x000e0000)
+
+#define EP93XX_KEY_MATRIX_BASE          (EP93XX_APB_VIRT_BASE + 0x000f0000)
+
+#define EP93XX_ADC_BASE                 (EP93XX_APB_VIRT_BASE + 0x00100000)
+#define EP93XX_TOUCHSCREEN_BASE         (EP93XX_APB_VIRT_BASE + 0x00100000)
+
+#define EP93XX_PWM_BASE                 (EP93XX_APB_VIRT_BASE + 0x00110000)
+
+#define EP93XX_RTC_BASE                 (EP93XX_APB_VIRT_BASE + 0x00120000)
+
+#define EP93XX_SYSCON_BASE              (EP93XX_APB_VIRT_BASE + 0x00130000)
+#define EP93XX_SYSCON_REG(x)            (EP93XX_SYSCON_BASE + (x))
+#define EP93XX_SYSCON_POWER_STATE       EP93XX_SYSCON_REG(0x00)
+#define EP93XX_SYSCON_CLOCK_CONTROL     EP93XX_SYSCON_REG(0x04)
+#define EP93XX_SYSCON_CLOCK_UARTBAUD    0x20000000
+#define EP93XX_SYSCON_CLOCK_USH_EN      0x10000000
+#define EP93XX_SYSCON_HALT              EP93XX_SYSCON_REG(0x08)
+#define EP93XX_SYSCON_STANDBY           EP93XX_SYSCON_REG(0x0c)
+#define EP93XX_SYSCON_CLOCK_SET1        EP93XX_SYSCON_REG(0x20)
+#define EP93XX_SYSCON_CLOCK_SET2        EP93XX_SYSCON_REG(0x24)
+#define EP93XX_SYSCON_DEVICE_CONFIG     EP93XX_SYSCON_REG(0x80)
+#define EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE       0x00800000
+#define EP93XX_SYSCON_SWLOCK            EP93XX_SYSCON_REG(0xc0)
+
+#define EP93XX_WATCHDOG_BASE            (EP93XX_APB_VIRT_BASE + 0x00140000)
+
+
+#endif
diff --git a/arch/arm/mach-ep93xx/include/mach/gesbc9312.h b/arch/arm/mach-ep93xx/include/mach/gesbc9312.h
new file mode 100644
index 000000000000..21fe2b922aa5
--- /dev/null
+++ b/arch/arm/mach-ep93xx/include/mach/gesbc9312.h
@@ -0,0 +1,3 @@
+/*
+ * arch/arm/mach-ep93xx/include/mach/gesbc9312.h
+ */
diff --git a/arch/arm/mach-ep93xx/include/mach/gpio.h b/arch/arm/mach-ep93xx/include/mach/gpio.h
new file mode 100644
index 000000000000..f7020414c5df
--- /dev/null
+++ b/arch/arm/mach-ep93xx/include/mach/gpio.h
@@ -0,0 +1,128 @@
+/*
+ * arch/arm/mach-ep93xx/include/mach/gpio.h
+ */
+
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H
+
+/* GPIO port A.  */
+#define EP93XX_GPIO_LINE_A(x)           ((x) + 0)
+#define EP93XX_GPIO_LINE_EGPIO0         EP93XX_GPIO_LINE_A(0)
+#define EP93XX_GPIO_LINE_EGPIO1         EP93XX_GPIO_LINE_A(1)
+#define EP93XX_GPIO_LINE_EGPIO2         EP93XX_GPIO_LINE_A(2)
+#define EP93XX_GPIO_LINE_EGPIO3         EP93XX_GPIO_LINE_A(3)
+#define EP93XX_GPIO_LINE_EGPIO4         EP93XX_GPIO_LINE_A(4)
+#define EP93XX_GPIO_LINE_EGPIO5         EP93XX_GPIO_LINE_A(5)
+#define EP93XX_GPIO_LINE_EGPIO6         EP93XX_GPIO_LINE_A(6)
+#define EP93XX_GPIO_LINE_EGPIO7         EP93XX_GPIO_LINE_A(7)
+
+/* GPIO port B.  */
+#define EP93XX_GPIO_LINE_B(x)           ((x) + 8)
+#define EP93XX_GPIO_LINE_EGPIO8         EP93XX_GPIO_LINE_B(0)
+#define EP93XX_GPIO_LINE_EGPIO9         EP93XX_GPIO_LINE_B(1)
+#define EP93XX_GPIO_LINE_EGPIO10        EP93XX_GPIO_LINE_B(2)
+#define EP93XX_GPIO_LINE_EGPIO11        EP93XX_GPIO_LINE_B(3)
+#define EP93XX_GPIO_LINE_EGPIO12        EP93XX_GPIO_LINE_B(4)
+#define EP93XX_GPIO_LINE_EGPIO13        EP93XX_GPIO_LINE_B(5)
+#define EP93XX_GPIO_LINE_EGPIO14        EP93XX_GPIO_LINE_B(6)
+#define EP93XX_GPIO_LINE_EGPIO15        EP93XX_GPIO_LINE_B(7)
+
+/* GPIO port C.  */
+#define EP93XX_GPIO_LINE_C(x)           ((x) + 40)
+#define EP93XX_GPIO_LINE_ROW0           EP93XX_GPIO_LINE_C(0)
+#define EP93XX_GPIO_LINE_ROW1           EP93XX_GPIO_LINE_C(1)
+#define EP93XX_GPIO_LINE_ROW2           EP93XX_GPIO_LINE_C(2)
+#define EP93XX_GPIO_LINE_ROW3           EP93XX_GPIO_LINE_C(3)
+#define EP93XX_GPIO_LINE_ROW4           EP93XX_GPIO_LINE_C(4)
+#define EP93XX_GPIO_LINE_ROW5           EP93XX_GPIO_LINE_C(5)
+#define EP93XX_GPIO_LINE_ROW6           EP93XX_GPIO_LINE_C(6)
+#define EP93XX_GPIO_LINE_ROW7           EP93XX_GPIO_LINE_C(7)
+
+/* GPIO port D.  */
+#define EP93XX_GPIO_LINE_D(x)           ((x) + 24)
+#define EP93XX_GPIO_LINE_COL0           EP93XX_GPIO_LINE_D(0)
+#define EP93XX_GPIO_LINE_COL1           EP93XX_GPIO_LINE_D(1)
+#define EP93XX_GPIO_LINE_COL2           EP93XX_GPIO_LINE_D(2)
+#define EP93XX_GPIO_LINE_COL3           EP93XX_GPIO_LINE_D(3)
+#define EP93XX_GPIO_LINE_COL4           EP93XX_GPIO_LINE_D(4)
+#define EP93XX_GPIO_LINE_COL5           EP93XX_GPIO_LINE_D(5)
+#define EP93XX_GPIO_LINE_COL6           EP93XX_GPIO_LINE_D(6)
+#define EP93XX_GPIO_LINE_COL7           EP93XX_GPIO_LINE_D(7)
+
+/* GPIO port E.  */
+#define EP93XX_GPIO_LINE_E(x)           ((x) + 32)
+#define EP93XX_GPIO_LINE_GRLED          EP93XX_GPIO_LINE_E(0)
+#define EP93XX_GPIO_LINE_RDLED          EP93XX_GPIO_LINE_E(1)
+#define EP93XX_GPIO_LINE_DIORn          EP93XX_GPIO_LINE_E(2)
+#define EP93XX_GPIO_LINE_IDECS1n        EP93XX_GPIO_LINE_E(3)
+#define EP93XX_GPIO_LINE_IDECS2n        EP93XX_GPIO_LINE_E(4)
+#define EP93XX_GPIO_LINE_IDEDA0         EP93XX_GPIO_LINE_E(5)
+#define EP93XX_GPIO_LINE_IDEDA1         EP93XX_GPIO_LINE_E(6)
+#define EP93XX_GPIO_LINE_IDEDA2         EP93XX_GPIO_LINE_E(7)
+
+/* GPIO port F.  */
+#define EP93XX_GPIO_LINE_F(x)           ((x) + 16)
+#define EP93XX_GPIO_LINE_WP             EP93XX_GPIO_LINE_F(0)
+#define EP93XX_GPIO_LINE_MCCD1          EP93XX_GPIO_LINE_F(1)
+#define EP93XX_GPIO_LINE_MCCD2          EP93XX_GPIO_LINE_F(2)
+#define EP93XX_GPIO_LINE_MCBVD1         EP93XX_GPIO_LINE_F(3)
+#define EP93XX_GPIO_LINE_MCBVD2         EP93XX_GPIO_LINE_F(4)
+#define EP93XX_GPIO_LINE_VS1            EP93XX_GPIO_LINE_F(5)
+#define EP93XX_GPIO_LINE_READY          EP93XX_GPIO_LINE_F(6)
+#define EP93XX_GPIO_LINE_VS2            EP93XX_GPIO_LINE_F(7)
+
+/* GPIO port G.  */
+#define EP93XX_GPIO_LINE_G(x)           ((x) + 48)
+#define EP93XX_GPIO_LINE_EECLK          EP93XX_GPIO_LINE_G(0)
+#define EP93XX_GPIO_LINE_EEDAT          EP93XX_GPIO_LINE_G(1)
+#define EP93XX_GPIO_LINE_SLA0           EP93XX_GPIO_LINE_G(2)
+#define EP93XX_GPIO_LINE_SLA1           EP93XX_GPIO_LINE_G(3)
+#define EP93XX_GPIO_LINE_DD12           EP93XX_GPIO_LINE_G(4)
+#define EP93XX_GPIO_LINE_DD13           EP93XX_GPIO_LINE_G(5)
+#define EP93XX_GPIO_LINE_DD14           EP93XX_GPIO_LINE_G(6)
+#define EP93XX_GPIO_LINE_DD15           EP93XX_GPIO_LINE_G(7)
+
+/* GPIO port H.  */
+#define EP93XX_GPIO_LINE_H(x)           ((x) + 56)
+#define EP93XX_GPIO_LINE_DD0            EP93XX_GPIO_LINE_H(0)
+#define EP93XX_GPIO_LINE_DD1            EP93XX_GPIO_LINE_H(1)
+#define EP93XX_GPIO_LINE_DD2            EP93XX_GPIO_LINE_H(2)
+#define EP93XX_GPIO_LINE_DD3            EP93XX_GPIO_LINE_H(3)
+#define EP93XX_GPIO_LINE_DD4            EP93XX_GPIO_LINE_H(4)
+#define EP93XX_GPIO_LINE_DD5            EP93XX_GPIO_LINE_H(5)
+#define EP93XX_GPIO_LINE_DD6            EP93XX_GPIO_LINE_H(6)
+#define EP93XX_GPIO_LINE_DD7            EP93XX_GPIO_LINE_H(7)
+
+/* maximum value for gpio line identifiers */
+#define EP93XX_GPIO_LINE_MAX            EP93XX_GPIO_LINE_H(7)
+
+/* maximum value for irq capable line identifiers */
+#define EP93XX_GPIO_LINE_MAX_IRQ        EP93XX_GPIO_LINE_F(7)
+
+/* new generic GPIO API - see Documentation/gpio.txt */
+
+#include <asm-generic/gpio.h>
+
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
+
+/*
+ * Map GPIO A0..A7  (0..7)  to irq 64..71,
+ *          B0..B7  (7..15) to irq 72..79, and
+ *          F0..F7 (16..24) to irq 80..87.
+ */
+static inline int gpio_to_irq(unsigned gpio)
+{
+        if (gpio <= EP93XX_GPIO_LINE_MAX_IRQ)
+                return 64 + gpio;
+
+        return -EINVAL;
+}
+
+static inline int irq_to_gpio(unsigned irq)
+{
+        return irq - gpio_to_irq(0);
+}
+
+#endif
diff --git a/arch/arm/mach-ep93xx/include/mach/hardware.h b/arch/arm/mach-ep93xx/include/mach/hardware.h
new file mode 100644
index 000000000000..529807d182bf
--- /dev/null
+++ b/arch/arm/mach-ep93xx/include/mach/hardware.h
@@ -0,0 +1,16 @@
+/*
+ * arch/arm/mach-ep93xx/include/mach/hardware.h
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include "ep93xx-regs.h"
+
+#define pcibios_assign_all_busses()     0
+
+#include "platform.h"
+
+#include "gesbc9312.h"
+#include "ts72xx.h"
+
+#endif
diff --git a/arch/arm/mach-ep93xx/include/mach/io.h b/arch/arm/mach-ep93xx/include/mach/io.h
new file mode 100644
index 000000000000..1ab9a90ad339
--- /dev/null
+++ b/arch/arm/mach-ep93xx/include/mach/io.h
@@ -0,0 +1,8 @@
+/*
+ * arch/arm/mach-ep93xx/include/mach/io.h
+ */
+
+#define IO_SPACE_LIMIT          0xffffffff
+
+#define __io(p)                 ((void __iomem *)(p))
+#define __mem_pci(p)            (p)
diff --git a/arch/arm/mach-ep93xx/include/mach/irqs.h b/arch/arm/mach-ep93xx/include/mach/irqs.h
new file mode 100644
index 000000000000..ff98390bbf0f
--- /dev/null
+++ b/arch/arm/mach-ep93xx/include/mach/irqs.h
@@ -0,0 +1,78 @@
+/*
+ * arch/arm/mach-ep93xx/include/mach/irqs.h
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#define IRQ_EP93XX_COMMRX               2
+#define IRQ_EP93XX_COMMTX               3
+#define IRQ_EP93XX_TIMER1               4
+#define IRQ_EP93XX_TIMER2               5
+#define IRQ_EP93XX_AACINTR              6
+#define IRQ_EP93XX_DMAM2P0              7
+#define IRQ_EP93XX_DMAM2P1              8
+#define IRQ_EP93XX_DMAM2P2              9
+#define IRQ_EP93XX_DMAM2P3              10
+#define IRQ_EP93XX_DMAM2P4              11
+#define IRQ_EP93XX_DMAM2P5              12
+#define IRQ_EP93XX_DMAM2P6              13
+#define IRQ_EP93XX_DMAM2P7              14
+#define IRQ_EP93XX_DMAM2P8              15
+#define IRQ_EP93XX_DMAM2P9              16
+#define IRQ_EP93XX_DMAM2M0              17
+#define IRQ_EP93XX_DMAM2M1              18
+#define IRQ_EP93XX_GPIO0MUX             19
+#define IRQ_EP93XX_GPIO1MUX             20
+#define IRQ_EP93XX_GPIO2MUX             21
+#define IRQ_EP93XX_GPIO3MUX             22
+#define IRQ_EP93XX_UART1RX              23
+#define IRQ_EP93XX_UART1TX              24
+#define IRQ_EP93XX_UART2RX              25
+#define IRQ_EP93XX_UART2TX              26
+#define IRQ_EP93XX_UART3RX              27
+#define IRQ_EP93XX_UART3TX              28
+#define IRQ_EP93XX_KEY                  29
+#define IRQ_EP93XX_TOUCH                30
+#define EP93XX_VIC1_VALID_IRQ_MASK      0x7ffffffc
+
+#define IRQ_EP93XX_EXT0                 32
+#define IRQ_EP93XX_EXT1                 33
+#define IRQ_EP93XX_EXT2                 34
+#define IRQ_EP93XX_64HZ                 35
+#define IRQ_EP93XX_WATCHDOG             36
+#define IRQ_EP93XX_RTC                  37
+#define IRQ_EP93XX_IRDA                 38
+#define IRQ_EP93XX_ETHERNET             39
+#define IRQ_EP93XX_EXT3                 40
+#define IRQ_EP93XX_PROG                 41
+#define IRQ_EP93XX_1HZ                  42
+#define IRQ_EP93XX_VSYNC                43
+#define IRQ_EP93XX_VIDEO_FIFO           44
+#define IRQ_EP93XX_SSP1RX               45
+#define IRQ_EP93XX_SSP1TX               46
+#define IRQ_EP93XX_GPIO4MUX             47
+#define IRQ_EP93XX_GPIO5MUX             48
+#define IRQ_EP93XX_GPIO6MUX             49
+#define IRQ_EP93XX_GPIO7MUX             50
+#define IRQ_EP93XX_TIMER3               51
+#define IRQ_EP93XX_UART1                52
+#define IRQ_EP93XX_SSP                  53
+#define IRQ_EP93XX_UART2                54
+#define IRQ_EP93XX_UART3                55
+#define IRQ_EP93XX_USB                  56
+#define IRQ_EP93XX_ETHERNET_PME         57
+#define IRQ_EP93XX_DSP                  58
+#define IRQ_EP93XX_GPIO_AB              59
+#define IRQ_EP93XX_SAI                  60
+#define EP93XX_VIC2_VALID_IRQ_MASK      0x1fffffff
+
+#define NR_EP93XX_IRQS                  (64 + 24)
+
+#define EP93XX_BOARD_IRQ(x)             (NR_EP93XX_IRQS + (x))
+#define EP93XX_BOARD_IRQS               32
+
+#define NR_IRQS                         (NR_EP93XX_IRQS + EP93XX_BOARD_IRQS)
+
+
+#endif
diff --git a/arch/arm/mach-ep93xx/include/mach/memory.h b/arch/arm/mach-ep93xx/include/mach/memory.h
new file mode 100644
index 000000000000..f1b633590752
--- /dev/null
+++ b/arch/arm/mach-ep93xx/include/mach/memory.h
@@ -0,0 +1,14 @@
+/*
+ * arch/arm/mach-ep93xx/include/mach/memory.h
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#define PHYS_OFFSET             UL(0x00000000)
+
+#define __bus_to_virt(x)        __phys_to_virt(x)
+#define __virt_to_bus(x)        __virt_to_phys(x)
+
+
+#endif
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
new file mode 100644
index 000000000000..b5c182473f5d
--- /dev/null
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/mach-ep93xx/include/mach/platform.h
+ */
+
+#ifndef __ASSEMBLY__
+
+void ep93xx_map_io(void);
+void ep93xx_init_irq(void);
+void ep93xx_init_time(unsigned long);
+void ep93xx_init_devices(void);
+extern struct sys_timer ep93xx_timer;
+
+struct ep93xx_eth_data
+{
+        unsigned char   dev_addr[6];
+        unsigned char   phy_id;
+};
+
+
+#endif
diff --git a/arch/arm/mach-ep93xx/include/mach/system.h b/arch/arm/mach-ep93xx/include/mach/system.h
new file mode 100644
index 000000000000..67789d0f329e
--- /dev/null
+++ b/arch/arm/mach-ep93xx/include/mach/system.h
@@ -0,0 +1,26 @@
+/*
+ * arch/arm/mach-ep93xx/include/mach/system.h
+ */
+
+#include <mach/hardware.h>
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        u32 devicecfg;
+
+        local_irq_disable();
+
+        devicecfg = __raw_readl(EP93XX_SYSCON_DEVICE_CONFIG);
+        __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
+        __raw_writel(devicecfg | 0x80000000, EP93XX_SYSCON_DEVICE_CONFIG);
+        __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
+        __raw_writel(devicecfg & ~0x80000000, EP93XX_SYSCON_DEVICE_CONFIG);
+
+        while (1)
+                ;
+}
diff --git a/arch/arm/mach-ep93xx/include/mach/timex.h b/arch/arm/mach-ep93xx/include/mach/timex.h
new file mode 100644
index 000000000000..6b3503b01fa6
--- /dev/null
+++ b/arch/arm/mach-ep93xx/include/mach/timex.h
@@ -0,0 +1,5 @@
+/*
+ * arch/arm/mach-ep93xx/include/mach/timex.h
+ */
+
+#define CLOCK_TICK_RATE         983040
diff --git a/arch/arm/mach-ep93xx/include/mach/ts72xx.h b/arch/arm/mach-ep93xx/include/mach/ts72xx.h
new file mode 100644
index 000000000000..30b318aa1a1f
--- /dev/null
+++ b/arch/arm/mach-ep93xx/include/mach/ts72xx.h
@@ -0,0 +1,101 @@
+/*
+ * arch/arm/mach-ep93xx/include/mach/ts72xx.h
+ */
+
+/*
+ * TS72xx memory map:
+ *
+ * virt         phys            size
+ * febff000     22000000        4K      model number register
+ * febfe000     22400000        4K      options register
+ * febfd000     22800000        4K      options register #2
+ * febfc000     [67]0000000     4K      NAND data register
+ * febfb000     [67]0400000     4K      NAND control register
+ * febfa000     [67]0800000     4K      NAND busy register
+ * febf9000     10800000        4K      TS-5620 RTC index register
+ * febf8000     11700000        4K      TS-5620 RTC data register
+ */
+
+#define TS72XX_MODEL_PHYS_BASE          0x22000000
+#define TS72XX_MODEL_VIRT_BASE          0xfebff000
+#define TS72XX_MODEL_SIZE               0x00001000
+
+#define TS72XX_MODEL_TS7200             0x00
+#define TS72XX_MODEL_TS7250             0x01
+#define TS72XX_MODEL_TS7260             0x02
+
+
+#define TS72XX_OPTIONS_PHYS_BASE        0x22400000
+#define TS72XX_OPTIONS_VIRT_BASE        0xfebfe000
+#define TS72XX_OPTIONS_SIZE             0x00001000
+
+#define TS72XX_OPTIONS_COM2_RS485       0x02
+#define TS72XX_OPTIONS_MAX197           0x01
+
+
+#define TS72XX_OPTIONS2_PHYS_BASE       0x22800000
+#define TS72XX_OPTIONS2_VIRT_BASE       0xfebfd000
+#define TS72XX_OPTIONS2_SIZE            0x00001000
+
+#define TS72XX_OPTIONS2_TS9420          0x04
+#define TS72XX_OPTIONS2_TS9420_BOOT     0x02
+
+
+#define TS72XX_NOR_PHYS_BASE            0x60000000
+#define TS72XX_NOR2_PHYS_BASE           0x62000000
+
+#define TS72XX_NAND1_DATA_PHYS_BASE     0x60000000
+#define TS72XX_NAND2_DATA_PHYS_BASE     0x70000000
+#define TS72XX_NAND_DATA_VIRT_BASE      0xfebfc000
+#define TS72XX_NAND_DATA_SIZE           0x00001000
+
+#define TS72XX_NAND1_CONTROL_PHYS_BASE  0x60400000
+#define TS72XX_NAND2_CONTROL_PHYS_BASE  0x70400000
+#define TS72XX_NAND_CONTROL_VIRT_BASE   0xfebfb000
+#define TS72XX_NAND_CONTROL_SIZE        0x00001000
+
+#define TS72XX_NAND1_BUSY_PHYS_BASE     0x60800000
+#define TS72XX_NAND2_BUSY_PHYS_BASE     0x70800000
+#define TS72XX_NAND_BUSY_VIRT_BASE      0xfebfa000
+#define TS72XX_NAND_BUSY_SIZE           0x00001000
+
+
+#define TS72XX_RTC_INDEX_VIRT_BASE      0xfebf9000
+#define TS72XX_RTC_INDEX_PHYS_BASE      0x10800000
+#define TS72XX_RTC_INDEX_SIZE           0x00001000
+
+#define TS72XX_RTC_DATA_VIRT_BASE       0xfebf8000
+#define TS72XX_RTC_DATA_PHYS_BASE       0x11700000
+#define TS72XX_RTC_DATA_SIZE            0x00001000
+
+
+#ifndef __ASSEMBLY__
+#include <asm/io.h>
+
+static inline int board_is_ts7200(void)
+{
+        return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7200;
+}
+
+static inline int board_is_ts7250(void)
+{
+        return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7250;
+}
+
+static inline int board_is_ts7260(void)
+{
+        return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7260;
+}
+
+static inline int is_max197_installed(void)
+{
+        return !!(__raw_readb(TS72XX_OPTIONS_VIRT_BASE) &
+                                        TS72XX_OPTIONS_MAX197);
+}
+
+static inline int is_ts9420_installed(void)
+{
+        return !!(__raw_readb(TS72XX_OPTIONS2_VIRT_BASE) &
+                                        TS72XX_OPTIONS2_TS9420);
+}
+#endif
diff --git a/arch/arm/mach-ep93xx/include/mach/uncompress.h b/arch/arm/mach-ep93xx/include/mach/uncompress.h
new file mode 100644
index 000000000000..1fd2f17de325
--- /dev/null
+++ b/arch/arm/mach-ep93xx/include/mach/uncompress.h
@@ -0,0 +1,85 @@
+/*
+ * arch/arm/mach-ep93xx/include/mach/uncompress.h
+ *
+ * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ */
+
+#include <mach/ep93xx-regs.h>
+
+static unsigned char __raw_readb(unsigned int ptr)
+{
+        return *((volatile unsigned char *)ptr);
+}
+
+static unsigned int __raw_readl(unsigned int ptr)
+{
+        return *((volatile unsigned int *)ptr);
+}
+
+static void __raw_writeb(unsigned char value, unsigned int ptr)
+{
+        *((volatile unsigned char *)ptr) = value;
+}
+
+static void __raw_writel(unsigned int value, unsigned int ptr)
+{
+        *((volatile unsigned int *)ptr) = value;
+}
+
+
+#define PHYS_UART1_DATA         0x808c0000
+#define PHYS_UART1_FLAG         0x808c0018
+#define UART1_FLAG_TXFF         0x20
+
+static inline void putc(int c)
+{
+        int i;
+
+        for (i = 0; i < 1000; i++) {
+                /* Transmit fifo not full?  */
+                if (!(__raw_readb(PHYS_UART1_FLAG) & UART1_FLAG_TXFF))
+                        break;
+        }
+
+        __raw_writeb(c, PHYS_UART1_DATA);
+}
+
+static inline void flush(void)
+{
+}
+
+
+/*
+ * Some bootloaders don't turn off DMA from the ethernet MAC before
+ * jumping to linux, which means that we might end up with bits of RX
+ * status and packet data scribbled over the uncompressed kernel image.
+ * Work around this by resetting the ethernet MAC before we uncompress.
+ */
+#define PHYS_ETH_SELF_CTL               0x80010020
+#define ETH_SELF_CTL_RESET              0x00000001
+
+static void ethernet_reset(void)
+{
+        unsigned int v;
+
+        /* Reset the ethernet MAC.  */
+        v = __raw_readl(PHYS_ETH_SELF_CTL);
+        __raw_writel(v | ETH_SELF_CTL_RESET, PHYS_ETH_SELF_CTL);
+
+        /* Wait for reset to finish.  */
+        while (__raw_readl(PHYS_ETH_SELF_CTL) & ETH_SELF_CTL_RESET)
+                ;
+}
+
+
+static void arch_decomp_setup(void)
+{
+        ethernet_reset();
+}
+
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-ep93xx/include/mach/vmalloc.h b/arch/arm/mach-ep93xx/include/mach/vmalloc.h
new file mode 100644
index 000000000000..aed21cd3fe2d
--- /dev/null
+++ b/arch/arm/mach-ep93xx/include/mach/vmalloc.h
@@ -0,0 +1,5 @@
+/*
+ * arch/arm/mach-ep93xx/include/mach/vmalloc.h
+ */
+
+#define VMALLOC_END     0xfe800000
diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c
index 4d831ba799d5..de047a5c8112 100644
--- a/arch/arm/mach-ep93xx/micro9.c
+++ b/arch/arm/mach-ep93xx/micro9.c
@@ -20,7 +20,7 @@
 #include <linux/mtd/physmap.h>
 
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index c0bc642a5c18..c3cbff126d0c 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -20,7 +20,7 @@
 #include <linux/platform_device.h>
 #include <linux/m48t86.h>
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-footbridge/ebsa285-leds.c b/arch/arm/mach-footbridge/ebsa285-leds.c
index c04c46c404f7..4e10090cd87f 100644
--- a/arch/arm/mach-footbridge/ebsa285-leds.c
+++ b/arch/arm/mach-footbridge/ebsa285-leds.c
@@ -21,7 +21,7 @@
 #include <linux/init.h>
 #include <linux/spinlock.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/system.h>
diff --git a/arch/arm/mach-footbridge/include/mach/debug-macro.S b/arch/arm/mach-footbridge/include/mach/debug-macro.S
new file mode 100644
index 000000000000..4329b8123570
--- /dev/null
+++ b/arch/arm/mach-footbridge/include/mach/debug-macro.S
@@ -0,0 +1,57 @@
+/* arch/arm/mach-footbridge/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <asm/hardware/dec21285.h>
+
+#ifndef CONFIG_DEBUG_DC21285_PORT
+        /* For NetWinder debugging */
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx, #0x7c000000        @ physical
+                movne   \rx, #0xff000000        @ virtual
+                orr     \rx, \rx, #0x000003f8
+                .endm
+
+#define UART_SHIFT      0
+#define FLOW_CONTROL
+#include <asm/hardware/debug-8250.S>
+
+#else
+        /* For EBSA285 debugging */
+                .equ    dc21285_high, ARMCSR_BASE & 0xff000000
+                .equ    dc21285_low,  ARMCSR_BASE & 0x00ffffff
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx, #0x42000000
+                movne   \rx, #dc21285_high
+                .if     dc21285_low
+                orrne   \rx, \rx, #dc21285_low
+                .endif
+                .endm
+
+                .macro  senduart,rd,rx
+                str     \rd, [\rx, #0x160]      @ UARTDR
+                .endm
+
+                .macro  busyuart,rd,rx
+1001:           ldr     \rd, [\rx, #0x178]      @ UARTFLG
+                tst     \rd, #1 << 3
+                bne     1001b
+                .endm
+
+                .macro  waituart,rd,rx
+                .endm
+#endif
diff --git a/arch/arm/mach-footbridge/include/mach/dma.h b/arch/arm/mach-footbridge/include/mach/dma.h
new file mode 100644
index 000000000000..62afd213effb
--- /dev/null
+++ b/arch/arm/mach-footbridge/include/mach/dma.h
@@ -0,0 +1,25 @@
+/*
+ *  arch/arm/mach-footbridge/include/mach/dma.h
+ *
+ *  Architecture DMA routines
+ *
+ *  Copyright (C) 1998,1999 Russell King
+ *  Copyright (C) 1998,1999 Philip Blundell
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+/*
+ * The 21285 has two internal DMA channels; we call these 8 and 9.
+ * On CATS hardware we have an additional eight ISA dma channels
+ * numbered 0..7.
+ */
+#define _ISA_DMA(x)             (0+(x))
+#define _DC21285_DMA(x)         (8+(x))
+
+#define MAX_DMA_CHANNELS        10
+
+#define DMA_FLOPPY              _ISA_DMA(2)
+#define DMA_ISA_CASCADE         _ISA_DMA(4)
+
+#endif /* _ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-footbridge/include/mach/entry-macro.S b/arch/arm/mach-footbridge/include/mach/entry-macro.S
new file mode 100644
index 000000000000..d3847be0c667
--- /dev/null
+++ b/arch/arm/mach-footbridge/include/mach/entry-macro.S
@@ -0,0 +1,113 @@
+/*
+ * arch/arm/mach-footbridge/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for footbridge-based platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+#include <asm/hardware/dec21285.h>
+
+                .equ    dc21285_high, ARMCSR_BASE & 0xff000000
+                .equ    dc21285_low, ARMCSR_BASE & 0x00ffffff
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_preamble, base, tmp
+                mov     \base, #dc21285_high
+                .if     dc21285_low
+                orr     \base, \base, #dc21285_low
+                .endif
+                .endm
+
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                ldr     \irqstat, [\base, #0x180]       @ get interrupts
+
+                mov     \irqnr, #IRQ_SDRAMPARITY
+                tst     \irqstat, #IRQ_MASK_SDRAMPARITY
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_UART_RX
+                movne   \irqnr, #IRQ_CONRX
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_DMA1
+                movne   \irqnr, #IRQ_DMA1
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_DMA2
+                movne   \irqnr, #IRQ_DMA2
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_IN0
+                movne   \irqnr, #IRQ_IN0
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_IN1
+                movne   \irqnr, #IRQ_IN1
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_IN2
+                movne   \irqnr, #IRQ_IN2
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_IN3
+                movne   \irqnr, #IRQ_IN3
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_PCI
+                movne   \irqnr, #IRQ_PCI
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_DOORBELLHOST
+                movne   \irqnr, #IRQ_DOORBELLHOST
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_I2OINPOST
+                movne   \irqnr, #IRQ_I2OINPOST
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_TIMER1
+                movne   \irqnr, #IRQ_TIMER1
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_TIMER2
+                movne   \irqnr, #IRQ_TIMER2
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_TIMER3
+                movne   \irqnr, #IRQ_TIMER3
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_UART_TX
+                movne   \irqnr, #IRQ_CONTX
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_PCI_ABORT
+                movne   \irqnr, #IRQ_PCI_ABORT
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_PCI_SERR
+                movne   \irqnr, #IRQ_PCI_SERR
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_DISCARD_TIMER
+                movne   \irqnr, #IRQ_DISCARD_TIMER
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_PCI_DPERR
+                movne   \irqnr, #IRQ_PCI_DPERR
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_PCI_PERR
+                movne   \irqnr, #IRQ_PCI_PERR
+1001:
+                .endm
+
diff --git a/arch/arm/mach-footbridge/include/mach/hardware.h b/arch/arm/mach-footbridge/include/mach/hardware.h
new file mode 100644
index 000000000000..ffaea90486f9
--- /dev/null
+++ b/arch/arm/mach-footbridge/include/mach/hardware.h
@@ -0,0 +1,105 @@
+/*
+ *  arch/arm/mach-footbridge/include/mach/hardware.h
+ *
+ *  Copyright (C) 1998-1999 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  This file contains the hardware definitions of the EBSA-285.
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <mach/memory.h>
+
+/*   Virtual      Physical      Size
+ * 0xff800000   0x40000000      1MB     X-Bus
+ * 0xff000000   0x7c000000      1MB     PCI I/O space
+ * 0xfe000000   0x42000000      1MB     CSR
+ * 0xfd000000   0x78000000      1MB     Outbound write flush (not supported)
+ * 0xfc000000   0x79000000      1MB     PCI IACK/special space
+ * 0xfb000000   0x7a000000      16MB    PCI Config type 1
+ * 0xfa000000   0x7b000000      16MB    PCI Config type 0
+ * 0xf9000000   0x50000000      1MB     Cache flush
+ * 0xf0000000   0x80000000      16MB    ISA memory
+ */
+#define XBUS_SIZE               0x00100000
+#define XBUS_BASE               0xff800000
+
+#define PCIO_SIZE               0x00100000
+#define PCIO_BASE               0xff000000
+
+#define ARMCSR_SIZE             0x00100000
+#define ARMCSR_BASE             0xfe000000
+
+#define WFLUSH_SIZE             0x00100000
+#define WFLUSH_BASE             0xfd000000
+
+#define PCIIACK_SIZE            0x00100000
+#define PCIIACK_BASE            0xfc000000
+
+#define PCICFG1_SIZE            0x01000000
+#define PCICFG1_BASE            0xfb000000
+
+#define PCICFG0_SIZE            0x01000000
+#define PCICFG0_BASE            0xfa000000
+
+#define PCIMEM_SIZE             0x01000000
+#define PCIMEM_BASE             0xf0000000
+
+#define XBUS_LEDS               ((volatile unsigned char *)(XBUS_BASE + 0x12000))
+#define XBUS_LED_AMBER          (1 << 0)
+#define XBUS_LED_GREEN          (1 << 1)
+#define XBUS_LED_RED            (1 << 2)
+#define XBUS_LED_TOGGLE         (1 << 8)
+
+#define XBUS_SWITCH             ((volatile unsigned char *)(XBUS_BASE + 0x12000))
+#define XBUS_SWITCH_SWITCH      ((*XBUS_SWITCH) & 15)
+#define XBUS_SWITCH_J17_13      ((*XBUS_SWITCH) & (1 << 4))
+#define XBUS_SWITCH_J17_11      ((*XBUS_SWITCH) & (1 << 5))
+#define XBUS_SWITCH_J17_9       ((*XBUS_SWITCH) & (1 << 6))
+
+#define UNCACHEABLE_ADDR        (ARMCSR_BASE + 0x108)
+
+
+/* PIC irq control */
+#define PIC_LO                  0x20
+#define PIC_MASK_LO             0x21
+#define PIC_HI                  0xA0
+#define PIC_MASK_HI             0xA1
+
+/* GPIO pins */
+#define GPIO_CCLK               0x800
+#define GPIO_DSCLK              0x400
+#define GPIO_E2CLK              0x200
+#define GPIO_IOLOAD             0x100
+#define GPIO_RED_LED            0x080
+#define GPIO_WDTIMER            0x040
+#define GPIO_DATA               0x020
+#define GPIO_IOCLK              0x010
+#define GPIO_DONE               0x008
+#define GPIO_FAN                0x004
+#define GPIO_GREEN_LED          0x002
+#define GPIO_RESET              0x001
+
+/* CPLD pins */
+#define CPLD_DS_ENABLE          8
+#define CPLD_7111_DISABLE       4
+#define CPLD_UNMUTE             2
+#define CPLD_FLASH_WR_ENABLE    1
+
+#ifndef __ASSEMBLY__
+extern void gpio_modify_op(int mask, int set);
+extern void gpio_modify_io(int mask, int in);
+extern int  gpio_read(void);
+extern void cpld_modify(int mask, int set);
+#endif
+
+#define pcibios_assign_all_busses()     1
+
+#define PCIBIOS_MIN_IO          0x1000
+#define PCIBIOS_MIN_MEM         0x81000000
+
+#endif
diff --git a/arch/arm/mach-footbridge/include/mach/io.h b/arch/arm/mach-footbridge/include/mach/io.h
new file mode 100644
index 000000000000..a7b066239996
--- /dev/null
+++ b/arch/arm/mach-footbridge/include/mach/io.h
@@ -0,0 +1,39 @@
+/*
+ *  arch/arm/mach-footbridge/include/mach/io.h
+ *
+ *  Copyright (C) 1997-1999 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Modifications:
+ *   06-12-1997 RMK     Created.
+ *   07-04-1999 RMK     Major cleanup
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#include <mach/hardware.h>
+
+#define IO_SPACE_LIMIT 0xffff
+
+/*
+ * Translation of various region addresses to virtual addresses
+ */
+#define __io(a)                 ((void __iomem *)(PCIO_BASE + (a)))
+#if 1
+#define __mem_pci(a)            (a)
+#else
+
+static inline void __iomem *___mem_pci(void __iomem *p)
+{
+        unsigned long a = (unsigned long)p;
+        BUG_ON(a <= 0xc0000000 || a >= 0xe0000000);
+        return p;
+}
+
+#define __mem_pci(a)            ___mem_pci(a)
+#endif
+
+#endif
diff --git a/arch/arm/mach-footbridge/include/mach/irqs.h b/arch/arm/mach-footbridge/include/mach/irqs.h
new file mode 100644
index 000000000000..400551e43e4e
--- /dev/null
+++ b/arch/arm/mach-footbridge/include/mach/irqs.h
@@ -0,0 +1,98 @@
+/*
+ * arch/arm/mach-footbridge/include/mach/irqs.h
+ *
+ * Copyright (C) 1998 Russell King
+ * Copyright (C) 1998 Phil Blundell
+ *
+ * Changelog:
+ *  20-Jan-1998 RMK     Started merge of EBSA286, CATS and NetWinder
+ *  01-Feb-1999 PJB     ISA IRQs start at 0 not 16
+ */
+#include <asm/mach-types.h>
+
+#define NR_IRQS                 36
+#define NR_DC21285_IRQS         16
+
+#define _ISA_IRQ(x)             (0 + (x))
+#define _ISA_INR(x)             ((x) - 0)
+#define _DC21285_IRQ(x)         (16 + (x))
+#define _DC21285_INR(x)         ((x) - 16)
+
+/*
+ * This is a list of all interrupts that the 21285
+ * can generate and we handle.
+ */
+#define IRQ_CONRX               _DC21285_IRQ(0)
+#define IRQ_CONTX               _DC21285_IRQ(1)
+#define IRQ_TIMER1              _DC21285_IRQ(2)
+#define IRQ_TIMER2              _DC21285_IRQ(3)
+#define IRQ_TIMER3              _DC21285_IRQ(4)
+#define IRQ_IN0                 _DC21285_IRQ(5)
+#define IRQ_IN1                 _DC21285_IRQ(6)
+#define IRQ_IN2                 _DC21285_IRQ(7)
+#define IRQ_IN3                 _DC21285_IRQ(8)
+#define IRQ_DOORBELLHOST        _DC21285_IRQ(9)
+#define IRQ_DMA1                _DC21285_IRQ(10)
+#define IRQ_DMA2                _DC21285_IRQ(11)
+#define IRQ_PCI                 _DC21285_IRQ(12)
+#define IRQ_SDRAMPARITY         _DC21285_IRQ(13)
+#define IRQ_I2OINPOST           _DC21285_IRQ(14)
+#define IRQ_PCI_ABORT           _DC21285_IRQ(15)
+#define IRQ_PCI_SERR            _DC21285_IRQ(16)
+#define IRQ_DISCARD_TIMER       _DC21285_IRQ(17)
+#define IRQ_PCI_DPERR           _DC21285_IRQ(18)
+#define IRQ_PCI_PERR            _DC21285_IRQ(19)
+
+#define IRQ_ISA_TIMER           _ISA_IRQ(0)
+#define IRQ_ISA_KEYBOARD        _ISA_IRQ(1)
+#define IRQ_ISA_CASCADE         _ISA_IRQ(2)
+#define IRQ_ISA_UART2           _ISA_IRQ(3)
+#define IRQ_ISA_UART            _ISA_IRQ(4)
+#define IRQ_ISA_FLOPPY          _ISA_IRQ(6)
+#define IRQ_ISA_PRINTER         _ISA_IRQ(7)
+#define IRQ_ISA_RTC_ALARM       _ISA_IRQ(8)
+#define IRQ_ISA_2               _ISA_IRQ(9)
+#define IRQ_ISA_PS2MOUSE        _ISA_IRQ(12)
+#define IRQ_ISA_HARDDISK1       _ISA_IRQ(14)
+#define IRQ_ISA_HARDDISK2       _ISA_IRQ(15)
+
+#define IRQ_MASK_UART_RX        (1 << 2)
+#define IRQ_MASK_UART_TX        (1 << 3)
+#define IRQ_MASK_TIMER1         (1 << 4)
+#define IRQ_MASK_TIMER2         (1 << 5)
+#define IRQ_MASK_TIMER3         (1 << 6)
+#define IRQ_MASK_IN0            (1 << 8)
+#define IRQ_MASK_IN1            (1 << 9)
+#define IRQ_MASK_IN2            (1 << 10)
+#define IRQ_MASK_IN3            (1 << 11)
+#define IRQ_MASK_DOORBELLHOST   (1 << 15)
+#define IRQ_MASK_DMA1           (1 << 16)
+#define IRQ_MASK_DMA2           (1 << 17)
+#define IRQ_MASK_PCI            (1 << 18)
+#define IRQ_MASK_SDRAMPARITY    (1 << 24)
+#define IRQ_MASK_I2OINPOST      (1 << 25)
+#define IRQ_MASK_PCI_ABORT      ((1 << 29) | (1 << 30))
+#define IRQ_MASK_PCI_SERR       (1 << 23)
+#define IRQ_MASK_DISCARD_TIMER  (1 << 27)
+#define IRQ_MASK_PCI_DPERR      (1 << 28)
+#define IRQ_MASK_PCI_PERR       (1 << 31)
+
+/*
+ * Netwinder interrupt allocations
+ */
+#define IRQ_NETWINDER_ETHER10   IRQ_IN0
+#define IRQ_NETWINDER_ETHER100  IRQ_IN1
+#define IRQ_NETWINDER_VIDCOMP   IRQ_IN2
+#define IRQ_NETWINDER_PS2MOUSE  _ISA_IRQ(5)
+#define IRQ_NETWINDER_IR        _ISA_IRQ(6)
+#define IRQ_NETWINDER_BUTTON    _ISA_IRQ(10)
+#define IRQ_NETWINDER_VGA       _ISA_IRQ(11)
+#define IRQ_NETWINDER_SOUND     _ISA_IRQ(12)
+
+#undef RTC_IRQ
+#define RTC_IRQ         IRQ_ISA_RTC_ALARM
+#define I8042_KBD_IRQ   IRQ_ISA_KEYBOARD
+#define I8042_AUX_IRQ   (machine_is_netwinder() ? IRQ_NETWINDER_PS2MOUSE : IRQ_ISA_PS2MOUSE)
+#define IRQ_FLOPPYDISK  IRQ_ISA_FLOPPY
+
+#define irq_canonicalize(_i)    (((_i) == IRQ_ISA_CASCADE) ? IRQ_ISA_2 : _i)
diff --git a/arch/arm/mach-footbridge/include/mach/memory.h b/arch/arm/mach-footbridge/include/mach/memory.h
new file mode 100644
index 000000000000..e9cae99dd1f9
--- /dev/null
+++ b/arch/arm/mach-footbridge/include/mach/memory.h
@@ -0,0 +1,67 @@
+/*
+ *  arch/arm/mach-footbridge/include/mach/memory.h
+ *
+ *  Copyright (C) 1996-1999 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   20-Oct-1996 RMK    Created
+ *   31-Dec-1997 RMK    Fixed definitions to reduce warnings.
+ *   17-May-1998 DAG    Added __virt_to_bus and __bus_to_virt functions.
+ *   21-Nov-1998 RMK    Changed __virt_to_bus and __bus_to_virt to macros.
+ *   21-Mar-1999 RMK    Added PAGE_OFFSET for co285 architecture.
+ *                      Renamed to memory.h
+ *                      Moved PAGE_OFFSET and TASK_SIZE here
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+
+#if defined(CONFIG_FOOTBRIDGE_ADDIN)
+/*
+ * If we may be using add-in footbridge mode, then we must
+ * use the out-of-line translation that makes use of the
+ * PCI BAR
+ */
+#ifndef __ASSEMBLY__
+extern unsigned long __virt_to_bus(unsigned long);
+extern unsigned long __bus_to_virt(unsigned long);
+#endif
+
+#elif defined(CONFIG_FOOTBRIDGE_HOST)
+
+#define __virt_to_bus(x)        ((x) - 0xe0000000)
+#define __bus_to_virt(x)        ((x) + 0xe0000000)
+
+#else
+
+#error "Undefined footbridge mode"
+
+#endif
+
+/* Task size and page offset at 3GB */
+#define TASK_SIZE               UL(0xbf000000)
+#define PAGE_OFFSET             UL(0xc0000000)
+
+/*
+ * Cache flushing area.
+ */
+#define FLUSH_BASE              0xf9000000
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET             UL(0x00000000)
+
+/*
+ * This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE ((TASK_SIZE + 0x01000000) / 3)
+
+#define FLUSH_BASE_PHYS         0x50000000
+
+#endif
diff --git a/arch/arm/mach-footbridge/include/mach/system.h b/arch/arm/mach-footbridge/include/mach/system.h
new file mode 100644
index 000000000000..01c9f407f498
--- /dev/null
+++ b/arch/arm/mach-footbridge/include/mach/system.h
@@ -0,0 +1,69 @@
+/*
+ *  arch/arm/mach-footbridge/include/mach/system.h
+ *
+ *  Copyright (C) 1996-1999 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <asm/hardware/dec21285.h>
+#include <asm/io.h>
+#include <mach/hardware.h>
+#include <asm/leds.h>
+#include <asm/mach-types.h>
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        if (mode == 's') {
+                /*
+                 * Jump into the ROM
+                 */
+                cpu_reset(0x41000000);
+        } else {
+                if (machine_is_netwinder()) {
+                        /* open up the SuperIO chip
+                         */
+                        outb(0x87, 0x370);
+                        outb(0x87, 0x370);
+
+                        /* aux function group 1 (logical device 7)
+                         */
+                        outb(0x07, 0x370);
+                        outb(0x07, 0x371);
+
+                        /* set GP16 for WD-TIMER output
+                         */
+                        outb(0xe6, 0x370);
+                        outb(0x00, 0x371);
+
+                        /* set a RED LED and toggle WD_TIMER for rebooting
+                         */
+                        outb(0xc4, 0x338);
+                } else {
+                        /* 
+                         * Force the watchdog to do a CPU reset.
+                         *
+                         * After making sure that the watchdog is disabled
+                         * (so we can change the timer registers) we first
+                         * enable the timer to autoreload itself.  Next, the
+                         * timer interval is set really short and any
+                         * current interrupt request is cleared (so we can
+                         * see an edge transition).  Finally, TIMER4 is
+                         * enabled as the watchdog.
+                         */
+                        *CSR_SA110_CNTL &= ~(1 << 13);
+                        *CSR_TIMER4_CNTL = TIMER_CNTL_ENABLE |
+                                           TIMER_CNTL_AUTORELOAD |
+                                           TIMER_CNTL_DIV16;
+                        *CSR_TIMER4_LOAD = 0x2;
+                        *CSR_TIMER4_CLR  = 0;
+                        *CSR_SA110_CNTL |= (1 << 13);
+                }
+        }
+}
diff --git a/arch/arm/mach-footbridge/include/mach/timex.h b/arch/arm/mach-footbridge/include/mach/timex.h
new file mode 100644
index 000000000000..d0fea9d6d4ab
--- /dev/null
+++ b/arch/arm/mach-footbridge/include/mach/timex.h
@@ -0,0 +1,18 @@
+/*
+ *  arch/arm/mach-footbridge/include/mach/timex.h
+ *
+ *  Copyright (C) 1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  EBSA285 architecture timex specifications
+ */
+
+/*
+ * We assume a constant here; this satisfies the maths in linux/timex.h
+ * and linux/time.h.  CLOCK_TICK_RATE is actually system dependent, but
+ * this must be a constant.
+ */
+#define CLOCK_TICK_RATE         (50000000/16)
diff --git a/arch/arm/mach-footbridge/include/mach/uncompress.h b/arch/arm/mach-footbridge/include/mach/uncompress.h
new file mode 100644
index 000000000000..5dfa44287346
--- /dev/null
+++ b/arch/arm/mach-footbridge/include/mach/uncompress.h
@@ -0,0 +1,38 @@
+/*
+ *  arch/arm/mach-footbridge/include/mach/uncompress.h
+ *
+ *  Copyright (C) 1996-1999 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <asm/mach-types.h>
+
+/*
+ * Note! This could cause problems on the NetWinder
+ */
+#define DC21285_BASE ((volatile unsigned int *)0x42000160)
+#define SER0_BASE    ((volatile unsigned char *)0x7c0003f8)
+
+static inline void putc(char c)
+{
+        if (machine_is_netwinder()) {
+                while ((SER0_BASE[5] & 0x60) != 0x60)
+                        barrier();
+                SER0_BASE[0] = c;
+        } else {
+                while (DC21285_BASE[6] & 8);
+                DC21285_BASE[0] = c;
+        }
+}
+
+static inline void flush(void)
+{
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-footbridge/include/mach/vmalloc.h b/arch/arm/mach-footbridge/include/mach/vmalloc.h
new file mode 100644
index 000000000000..d0958d860a3c
--- /dev/null
+++ b/arch/arm/mach-footbridge/include/mach/vmalloc.h
@@ -0,0 +1,10 @@
+/*
+ *  arch/arm/mach-footbridge/include/mach/vmalloc.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+
+#define VMALLOC_END       (PAGE_OFFSET + 0x30000000)
diff --git a/arch/arm/mach-footbridge/isa-irq.c b/arch/arm/mach-footbridge/isa-irq.c
index b8e53d68c093..7132e522c366 100644
--- a/arch/arm/mach-footbridge/isa-irq.c
+++ b/arch/arm/mach-footbridge/isa-irq.c
@@ -21,7 +21,7 @@
 
 #include <asm/mach/irq.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/hardware/dec21285.h>
 #include <asm/irq.h>
 #include <asm/io.h>
diff --git a/arch/arm/mach-footbridge/netwinder-leds.c b/arch/arm/mach-footbridge/netwinder-leds.c
index 2a2fbff75851..d91a4f4a32dc 100644
--- a/arch/arm/mach-footbridge/netwinder-leds.c
+++ b/arch/arm/mach-footbridge/netwinder-leds.c
@@ -21,7 +21,7 @@
 #include <linux/init.h>
 #include <linux/spinlock.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/system.h>
diff --git a/arch/arm/mach-footbridge/time.c b/arch/arm/mach-footbridge/time.c
index bffba25dd262..fd9a7c11d62d 100644
--- a/arch/arm/mach-footbridge/time.c
+++ b/arch/arm/mach-footbridge/time.c
@@ -1,5 +1,5 @@
 /*
- *  linux/include/asm-arm/arch-ebsa285/time.h
+ *  arch/arm/mach-footbridge/include/mach/time.h
  *
  *  Copyright (C) 1998 Russell King.
  *  Copyright (C) 1998 Phil Blundell
@@ -23,7 +23,7 @@
 #include <linux/mc146818rtc.h>
 #include <linux/bcd.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 
 #include <asm/mach/time.h>
diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c
index 26aefae7f9ac..b5f9741ae13c 100644
--- a/arch/arm/mach-h720x/common.c
+++ b/arch/arm/mach-h720x/common.c
@@ -23,11 +23,11 @@
 #include <asm/pgtable.h>
 #include <asm/dma.h>
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
-#include <asm/arch/irqs.h>
+#include <mach/irqs.h>
 
 #include <asm/mach/dma.h>
 
diff --git a/arch/arm/mach-h720x/cpu-h7201.c b/arch/arm/mach-h720x/cpu-h7201.c
index cd51520b1e31..24df2a349a98 100644
--- a/arch/arm/mach-h720x/cpu-h7201.c
+++ b/arch/arm/mach-h720x/cpu-h7201.c
@@ -17,9 +17,9 @@
 #include <linux/interrupt.h>
 #include <linux/module.h>
 #include <asm/types.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/arch/irqs.h>
+#include <mach/irqs.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
 #include "common.h"
diff --git a/arch/arm/mach-h720x/cpu-h7202.c b/arch/arm/mach-h720x/cpu-h7202.c
index 22573fcf9e13..53e1f62f2e79 100644
--- a/arch/arm/mach-h720x/cpu-h7202.c
+++ b/arch/arm/mach-h720x/cpu-h7202.c
@@ -17,9 +17,9 @@
 #include <linux/interrupt.h>
 #include <linux/module.h>
 #include <asm/types.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/arch/irqs.h>
+#include <mach/irqs.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
 #include <linux/device.h>
diff --git a/arch/arm/mach-h720x/h7201-eval.c b/arch/arm/mach-h720x/h7201-eval.c
index 899f9350cc65..78be457dc324 100644
--- a/arch/arm/mach-h720x/h7201-eval.c
+++ b/arch/arm/mach-h720x/h7201-eval.c
@@ -25,7 +25,7 @@
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/mach/arch.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include "common.h"
 
 MACHINE_START(H7201, "Hynix GMS30C7201")
diff --git a/arch/arm/mach-h720x/h7202-eval.c b/arch/arm/mach-h720x/h7202-eval.c
index eb725bd8e837..56161d55cf47 100644
--- a/arch/arm/mach-h720x/h7202-eval.c
+++ b/arch/arm/mach-h720x/h7202-eval.c
@@ -25,7 +25,7 @@
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/mach/arch.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include "common.h"
 
 static struct resource cirrus_resources[] = {
diff --git a/arch/arm/mach-h720x/include/mach/boards.h b/arch/arm/mach-h720x/include/mach/boards.h
new file mode 100644
index 000000000000..079b279e1242
--- /dev/null
+++ b/arch/arm/mach-h720x/include/mach/boards.h
@@ -0,0 +1,53 @@
+/*
+ * arch/arm/mach-h720x/include/mach/boards.h
+ *
+ * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
+ *           (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
+ *
+ * This file contains the board specific defines for various devices
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_INCMACH_H
+#error Do not include this file directly. Include asm/hardware.h instead !
+#endif
+
+/* Hynix H7202 developer board specific device defines */
+#ifdef CONFIG_ARCH_H7202
+
+/* FLASH */
+#define FLASH_VIRT              0xd0000000
+#define FLASH_PHYS              0x00000000
+#define FLASH_SIZE              0x02000000
+
+/* onboard LAN controller */
+# define ETH0_PHYS              0x08000000
+
+/* Touch screen defines */
+/* GPIO Port */
+#define PEN_GPIO                GPIO_B_VIRT
+/* Bitmask for pen down interrupt */
+#define PEN_INT_BIT             (1<<7)
+/* Bitmask for pen up interrupt */
+#define PEN_ENA_BIT             (1<<6)
+/* pen up interrupt */
+#define IRQ_PEN                 IRQ_MUX_GPIOB(7)
+
+#endif
+
+/* Hynix H7201 developer board specific device defines */
+#if defined (CONFIG_ARCH_H7201)
+/* ROM DISK SPACE */
+#define ROM_DISK_BASE           0xc1800000
+#define ROM_DISK_START          0x41800000
+#define ROM_DISK_SIZE           0x00700000
+
+/* SRAM DISK SPACE */
+#define SRAM_DISK_BASE          0xf1000000
+#define SRAM_DISK_START         0x04000000
+#define SRAM_DISK_SIZE          0x00400000
+#endif
+
diff --git a/arch/arm/mach-h720x/include/mach/debug-macro.S b/arch/arm/mach-h720x/include/mach/debug-macro.S
new file mode 100644
index 000000000000..6294a1344dda
--- /dev/null
+++ b/arch/arm/mach-h720x/include/mach/debug-macro.S
@@ -0,0 +1,40 @@
+/* arch/arm/mach-h720x/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+                .equ    io_virt, IO_BASE
+                .equ    io_phys, IO_START
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                @ MMU enabled?
+                moveq   \rx, #io_phys          @ physical base address
+                movne   \rx, #io_virt          @ virtual address
+                add     \rx, \rx, #0x00020000   @ UART1
+                .endm
+
+                .macro  senduart,rd,rx
+                str     \rd, [\rx, #0x0]        @ UARTDR
+
+                .endm
+
+                .macro  waituart,rd,rx
+1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
+                tst     \rd, #1 << 5           @ UARTFLGUTXFF - 1 when full
+                bne     1001b
+                .endm
+
+                .macro  busyuart,rd,rx
+1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
+                tst     \rd, #1 << 3           @ UARTFLGUBUSY - 1 when busy
+                bne     1001b
+                .endm
diff --git a/arch/arm/mach-h720x/include/mach/dma.h b/arch/arm/mach-h720x/include/mach/dma.h
new file mode 100644
index 000000000000..0a9d86ee84fe
--- /dev/null
+++ b/arch/arm/mach-h720x/include/mach/dma.h
@@ -0,0 +1,26 @@
+/*
+ * arch/arm/mach-h720x/include/mach/dma.h
+ *
+ * Architecture DMA routes
+ *
+ * Copyright (C) 1997.1998 Russell King
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+/*
+ * This is the maximum DMA address that can be DMAd to.
+ * There should not be more than (0xd0000000 - 0xc0000000)
+ * bytes of RAM.
+ */
+#define MAX_DMA_ADDRESS         0xd0000000
+
+#if defined (CONFIG_CPU_H7201)
+#define MAX_DMA_CHANNELS        3
+#elif defined (CONFIG_CPU_H7202)
+#define MAX_DMA_CHANNELS        4
+#else
+#error processor definition missmatch
+#endif
+
+#endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-h720x/include/mach/entry-macro.S b/arch/arm/mach-h720x/include/mach/entry-macro.S
new file mode 100644
index 000000000000..6d3b917c4a18
--- /dev/null
+++ b/arch/arm/mach-h720x/include/mach/entry-macro.S
@@ -0,0 +1,66 @@
+/*
+ * arch/arm/mach-h720x/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for Hynix HMS720x based platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_preamble, base, tmp
+                .endm
+
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+#if defined (CONFIG_CPU_H7201) || defined (CONFIG_CPU_H7202)
+                @ we could use the id register on H7202, but this is not
+                @ properly updated when we come back from asm_do_irq
+                @ without a previous return from interrupt
+                @ (see loops below in irq_svc, irq_usr)
+                @ We see unmasked pending ints only, as the masked pending ints
+                @ are not visible here
+
+                mov     \base, #0xf0000000             @ base register
+                orr     \base, \base, #0x24000         @ irqbase
+                ldr     \irqstat, [\base, #0x04]        @ get interrupt status
+#if defined (CONFIG_CPU_H7201)
+                ldr     \tmp, =0x001fffff
+#else
+                mvn     \tmp, #0xc0000000
+#endif
+                and     \irqstat, \irqstat, \tmp        @ mask out unused ints
+                mov     \irqnr, #0
+
+                mov     \tmp, #0xff00
+                orr     \tmp, \tmp, #0xff
+                tst     \irqstat, \tmp
+                addeq   \irqnr, \irqnr, #16
+                moveq   \irqstat, \irqstat, lsr #16
+                tst     \irqstat, #255
+                addeq   \irqnr, \irqnr, #8
+                moveq   \irqstat, \irqstat, lsr #8
+                tst     \irqstat, #15
+                addeq   \irqnr, \irqnr, #4
+                moveq   \irqstat, \irqstat, lsr #4
+                tst     \irqstat, #3
+                addeq   \irqnr, \irqnr, #2
+                moveq   \irqstat, \irqstat, lsr #2
+                tst     \irqstat, #1
+                addeq   \irqnr, \irqnr, #1
+                moveq   \irqstat, \irqstat, lsr #1
+                tst     \irqstat, #1                   @ bit 0 should be set
+                .endm
+
+                .macro  irq_prio_table
+                .endm
+
+#else
+#error hynix processor selection missmatch
+#endif
+
diff --git a/arch/arm/mach-h720x/include/mach/h7201-regs.h b/arch/arm/mach-h720x/include/mach/h7201-regs.h
new file mode 100644
index 000000000000..611b4947ccfc
--- /dev/null
+++ b/arch/arm/mach-h720x/include/mach/h7201-regs.h
@@ -0,0 +1,67 @@
+/*
+ * arch/arm/mach-h720x/include/mach/h7201-regs.h
+ *
+ * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
+ *           (C) 2003 Thomas Gleixner <tglx@linutronix.de>
+ *           (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
+ *           (C) 2004 Sascha Hauer    <s.hauer@pengutronix.de>
+ *
+ * This file contains the hardware definitions of the h720x processors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Do not add implementations specific defines here. This files contains
+ * only defines of the onchip peripherals. Add those defines to boards.h,
+ * which is included by this file.
+ */
+
+#define SERIAL2_VIRT            (IO_VIRT + 0x50100)
+#define SERIAL3_VIRT            (IO_VIRT + 0x50200)
+
+/*
+ * PCMCIA
+ */
+#define PCMCIA0_ATT_BASE        0xe5000000
+#define PCMCIA0_ATT_SIZE        0x00200000
+#define PCMCIA0_ATT_START       0x20000000
+#define PCMCIA0_MEM_BASE        0xe5200000
+#define PCMCIA0_MEM_SIZE        0x00200000
+#define PCMCIA0_MEM_START       0x24000000
+#define PCMCIA0_IO_BASE         0xe5400000
+#define PCMCIA0_IO_SIZE         0x00200000
+#define PCMCIA0_IO_START        0x28000000
+
+#define PCMCIA1_ATT_BASE        0xe5600000
+#define PCMCIA1_ATT_SIZE        0x00200000
+#define PCMCIA1_ATT_START       0x30000000
+#define PCMCIA1_MEM_BASE        0xe5800000
+#define PCMCIA1_MEM_SIZE        0x00200000
+#define PCMCIA1_MEM_START       0x34000000
+#define PCMCIA1_IO_BASE         0xe5a00000
+#define PCMCIA1_IO_SIZE         0x00200000
+#define PCMCIA1_IO_START        0x38000000
+
+#define PRIME3C_BASE            0xf0050000
+#define PRIME3C_SIZE            0x00001000
+#define PRIME3C_START           0x10000000
+
+/* VGA Controller */
+#define VGA_RAMBASE             0x50
+#define VGA_TIMING0             0x60
+#define VGA_TIMING1             0x64
+#define VGA_TIMING2             0x68
+#define VGA_TIMING3             0x6c
+
+#define LCD_CTRL_VGA_ENABLE     0x00000100
+#define LCD_CTRL_VGA_BPP_MASK   0x00000600
+#define LCD_CTRL_VGA_4BPP       0x00000000
+#define LCD_CTRL_VGA_8BPP       0x00000200
+#define LCD_CTRL_VGA_16BPP      0x00000300
+#define LCD_CTRL_SHARE_DMA      0x00000800
+#define LCD_CTRL_VDE            0x00100000
+#define LCD_CTRL_LPE            0x00400000      /* LCD Power enable */
+#define LCD_CTRL_BLE            0x00800000      /* LCD backlight enable */
+
+#define VGA_PALETTE_BASE        (IO_VIRT + 0x10800)
diff --git a/arch/arm/mach-h720x/include/mach/h7202-regs.h b/arch/arm/mach-h720x/include/mach/h7202-regs.h
new file mode 100644
index 000000000000..17c12eb34995
--- /dev/null
+++ b/arch/arm/mach-h720x/include/mach/h7202-regs.h
@@ -0,0 +1,155 @@
+/*
+ * arch/arm/mach-h720x/include/mach/h7202-regs.h
+ *
+ * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
+ *           (C) 2003 Thomas Gleixner <tglx@linutronix.de>
+ *           (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
+ *           (C) 2004 Sascha Hauer    <s.hauer@pengutronix.de>
+ *
+ * This file contains the hardware definitions of the h720x processors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Do not add implementations specific defines here. This files contains
+ * only defines of the onchip peripherals. Add those defines to boards.h,
+ * which is included by this file.
+ */
+
+#define SERIAL2_OFS             0x2d000
+#define SERIAL2_BASE            (IO_PHYS + SERIAL2_OFS)
+#define SERIAL2_VIRT            (IO_VIRT + SERIAL2_OFS)
+#define SERIAL3_OFS             0x2e000
+#define SERIAL3_BASE            (IO_PHYS + SERIAL3_OFS)
+#define SERIAL3_VIRT            (IO_VIRT + SERIAL3_OFS)
+
+/* Matrix Keyboard Controller */
+#define KBD_VIRT                (IO_VIRT + 0x22000)
+#define KBD_KBCR                0x00
+#define KBD_KBSC                0x04
+#define KBD_KBTR                0x08
+#define KBD_KBVR0               0x0C
+#define KBD_KBVR1               0x10
+#define KBD_KBSR                0x18
+
+#define KBD_KBCR_SCANENABLE     (1 << 7)
+#define KBD_KBCR_NPOWERDOWN     (1 << 2)
+#define KBD_KBCR_CLKSEL_MASK    (3)
+#define KBD_KBCR_CLKSEL_PCLK2   0x0
+#define KBD_KBCR_CLKSEL_PCLK128 0x1
+#define KBD_KBCR_CLKSEL_PCLK256 0x2
+#define KBD_KBCR_CLKSEL_PCLK512 0x3
+
+#define KBD_KBSR_INTR           (1 << 0)
+#define KBD_KBSR_WAKEUP         (1 << 1)
+
+/* USB device controller */
+
+#define USBD_BASE               (IO_VIRT + 0x12000)
+#define USBD_LENGTH             0x3C
+
+#define USBD_GCTRL              0x00
+#define USBD_EPCTRL             0x04
+#define USBD_INTMASK            0x08
+#define USBD_INTSTAT            0x0C
+#define USBD_PWR                0x10
+#define USBD_DMARXTX            0x14
+#define USBD_DEVID              0x18
+#define USBD_DEVCLASS           0x1C
+#define USBD_INTCLASS           0x20
+#define USBD_SETUP0             0x24
+#define USBD_SETUP1             0x28
+#define USBD_ENDP0RD            0x2C
+#define USBD_ENDP0WT            0x30
+#define USBD_ENDP1RD            0x34
+#define USBD_ENDP2WT            0x38
+
+/* PS/2 port */
+#define PSDATA 0x00
+#define PSSTAT 0x04
+#define PSSTAT_TXEMPTY (1<<0)
+#define PSSTAT_TXBUSY (1<<1)
+#define PSSTAT_RXFULL (1<<2)
+#define PSSTAT_RXBUSY (1<<3)
+#define PSSTAT_CLKIN (1<<4)
+#define PSSTAT_DATAIN (1<<5)
+#define PSSTAT_PARITY (1<<6)
+
+#define PSCONF 0x08
+#define PSCONF_ENABLE (1<<0)
+#define PSCONF_TXINTEN (1<<2)
+#define PSCONF_RXINTEN (1<<3)
+#define PSCONF_FORCECLKLOW (1<<4)
+#define PSCONF_FORCEDATLOW (1<<5)
+#define PSCONF_LCE (1<<6)
+
+#define PSINTR 0x0C
+#define PSINTR_TXINT (1<<0)
+#define PSINTR_RXINT (1<<1)
+#define PSINTR_PAR (1<<2)
+#define PSINTR_RXTO (1<<3)
+#define PSINTR_TXTO (1<<4)
+
+#define PSTDLO 0x10 /* clk low before start transmission */
+#define PSTPRI 0x14 /* PRI clock */
+#define PSTXMT 0x18 /* maximum transmission time */
+#define PSTREC 0x20 /* maximum receive time */
+#define PSPWDN 0x3c
+
+/* ADC converter */
+#define ADC_BASE                (IO_VIRT + 0x29000)
+#define ADC_CR                  0x00
+#define ADC_TSCTRL              0x04
+#define ADC_BT_CTRL             0x08
+#define ADC_MC_CTRL             0x0C
+#define ADC_STATUS              0x10
+
+/* ADC control register bits */
+#define ADC_CR_PW_CTRL          0x80
+#define ADC_CR_DIRECTC          0x04
+#define ADC_CR_CONTIME_NO       0x00
+#define ADC_CR_CONTIME_2        0x04
+#define ADC_CR_CONTIME_4        0x08
+#define ADC_CR_CONTIME_ADE      0x0c
+#define ADC_CR_LONGCALTIME      0x01
+
+/* ADC touch panel register bits */
+#define ADC_TSCTRL_ENABLE       0x80
+#define ADC_TSCTRL_INTR         0x40
+#define ADC_TSCTRL_SWBYPSS      0x20
+#define ADC_TSCTRL_SWINVT       0x10
+#define ADC_TSCTRL_S400         0x03
+#define ADC_TSCTRL_S200         0x02
+#define ADC_TSCTRL_S100         0x01
+#define ADC_TSCTRL_S50          0x00
+
+/* ADC Interrupt Status Register bits */
+#define ADC_STATUS_TS_BIT       0x80
+#define ADC_STATUS_MBT_BIT      0x40
+#define ADC_STATUS_BBT_BIT      0x20
+#define ADC_STATUS_MIC_BIT      0x10
+
+/* Touch data registers */
+#define ADC_TS_X0X1             0x30
+#define ADC_TS_X2X3             0x34
+#define ADC_TS_Y0Y1             0x38
+#define ADC_TS_Y2Y3             0x3c
+#define ADC_TS_X4X5             0x40
+#define ADC_TS_X6X7             0x44
+#define ADC_TS_Y4Y5             0x48
+#define ADC_TS_Y6Y7             0x50
+
+/* battery data */
+#define ADC_MB_DATA             0x54
+#define ADC_BB_DATA             0x58
+
+/* Sound data register */
+#define ADC_SD_DAT0             0x60
+#define ADC_SD_DAT1             0x64
+#define ADC_SD_DAT2             0x68
+#define ADC_SD_DAT3             0x6c
+#define ADC_SD_DAT4             0x70
+#define ADC_SD_DAT5             0x74
+#define ADC_SD_DAT6             0x78
+#define ADC_SD_DAT7             0x7c
diff --git a/arch/arm/mach-h720x/include/mach/hardware.h b/arch/arm/mach-h720x/include/mach/hardware.h
new file mode 100644
index 000000000000..6c19156e2a42
--- /dev/null
+++ b/arch/arm/mach-h720x/include/mach/hardware.h
@@ -0,0 +1,192 @@
+/*
+ * arch/arm/mach-h720x/include/mach/hardware.h
+ *
+ * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
+ *           (C) 2003 Thomas Gleixner <tglx@linutronix.de>
+ *           (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
+ *
+ * This file contains the hardware definitions of the h720x processors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Do not add implementations specific defines here. This files contains
+ * only defines of the onchip peripherals. Add those defines to boards.h,
+ * which is included by this file.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#define IOCLK (3686400L)
+
+/* Onchip peripherals */
+
+#define IO_VIRT                 0xf0000000      /* IO peripherals */
+#define IO_PHYS                 0x80000000
+#define IO_SIZE                 0x00050000
+
+#ifdef CONFIG_CPU_H7202
+#include "h7202-regs.h"
+#elif defined CONFIG_CPU_H7201
+#include "h7201-regs.h"
+#else
+#error machine definition mismatch
+#endif
+
+/* Macro to access the CPU IO */
+#define CPU_IO(x) (*(volatile u32*)(x))
+
+/* Macro to access general purpose regs (base, offset) */
+#define CPU_REG(x,y) CPU_IO(x+y)
+
+/* Macro to access irq related regs */
+#define IRQ_REG(x) CPU_REG(IRQC_VIRT,x)
+
+/* CPU registers */
+/* general purpose I/O */
+#define GPIO_VIRT(x)            (IO_VIRT + 0x23000 + ((x)<<5))
+#define GPIO_A_VIRT             (GPIO_VIRT(0))
+#define GPIO_B_VIRT             (GPIO_VIRT(1))
+#define GPIO_C_VIRT             (GPIO_VIRT(2))
+#define GPIO_D_VIRT             (GPIO_VIRT(3))
+#define GPIO_E_VIRT             (GPIO_VIRT(4))
+#define GPIO_AMULSEL            (GPIO_VIRT(0) + 0xA4)
+
+#define AMULSEL_USIN2   (1<<5)
+#define AMULSEL_USOUT2  (1<<6)
+#define AMULSEL_USIN3   (1<<13)
+#define AMULSEL_USOUT3  (1<<14)
+#define AMULSEL_IRDIN   (1<<15)
+#define AMULSEL_IRDOUT  (1<<7)
+
+/* Register offsets general purpose I/O */
+#define GPIO_DATA               0x00
+#define GPIO_DIR                0x04
+#define GPIO_MASK               0x08
+#define GPIO_STAT               0x0C
+#define GPIO_EDGE               0x10
+#define GPIO_CLR                0x14
+#define GPIO_POL                0x18
+#define GPIO_EN                 0x1C
+
+/*interrupt controller */
+#define IRQC_VIRT               (IO_VIRT + 0x24000)
+/* register offset interrupt controller */
+#define IRQC_IER                0x00
+#define IRQC_ISR                0x04
+
+/* timer unit */
+#define TIMER_VIRT              (IO_VIRT + 0x25000)
+/* Register offsets timer unit */
+#define TM0_PERIOD              0x00
+#define TM0_COUNT               0x08
+#define TM0_CTRL                0x10
+#define TM1_PERIOD              0x20
+#define TM1_COUNT               0x28
+#define TM1_CTRL                0x30
+#define TM2_PERIOD              0x40
+#define TM2_COUNT               0x48
+#define TM2_CTRL                0x50
+#define TIMER_TOPCTRL           0x60
+#define TIMER_TOPSTAT           0x64
+#define T64_COUNTL              0x80
+#define T64_COUNTH              0x84
+#define T64_CTRL                0x88
+#define T64_BASEL               0x94
+#define T64_BASEH               0x98
+/* Bitmaks timer unit TOPSTAT reg */
+#define TSTAT_T0INT             0x1
+#define TSTAT_T1INT             0x2
+#define TSTAT_T2INT             0x4
+#define TSTAT_T3INT             0x8
+/* Bit description of TMx_CTRL register */
+#define TM_START                0x1
+#define TM_REPEAT               0x2
+#define TM_RESET                0x4
+/* Bit description of TIMER_CTRL register */
+#define ENABLE_TM0_INTR         0x1
+#define ENABLE_TM1_INTR         0x2
+#define ENABLE_TM2_INTR         0x4
+#define TIMER_ENABLE_BIT        0x8
+#define ENABLE_TIMER64          0x10
+#define ENABLE_TIMER64_INT      0x20
+
+/* PMU & PLL */
+#define PMU_BASE                (IO_VIRT + 0x1000)
+#define PMU_MODE                0x00
+#define PMU_STAT                0x20
+#define PMU_PLL_CTRL            0x28
+
+/* PMU Mode bits */
+#define PMU_MODE_SLOW           0x00
+#define PMU_MODE_RUN            0x01
+#define PMU_MODE_IDLE           0x02
+#define PMU_MODE_SLEEP          0x03
+#define PMU_MODE_INIT           0x04
+#define PMU_MODE_DEEPSLEEP      0x07
+#define PMU_MODE_WAKEUP         0x08
+
+/* PMU ... */
+#define PLL_2_EN                0x8000
+#define PLL_1_EN                0x4000
+#define PLL_3_MUTE              0x0080
+
+/* Control bits for PMU/ PLL */
+#define PMU_WARMRESET           0x00010000
+#define PLL_CTRL_MASK23         0x000080ff
+
+/* LCD Controller */
+#define LCD_BASE                (IO_VIRT + 0x10000)
+#define LCD_CTRL                0x00
+#define LCD_STATUS              0x04
+#define LCD_STATUS_M            0x08
+#define LCD_INTERRUPT           0x0C
+#define LCD_DBAR                0x10
+#define LCD_DCAR                0x14
+#define LCD_TIMING0             0x20
+#define LCD_TIMING1             0x24
+#define LCD_TIMING2             0x28
+#define LCD_TEST                0x40
+
+/* LCD Control Bits */
+#define LCD_CTRL_LCD_ENABLE     0x00000001
+/* Bits per pixel */
+#define LCD_CTRL_LCD_BPP_MASK   0x00000006
+#define LCD_CTRL_LCD_4BPP       0x00000000
+#define LCD_CTRL_LCD_8BPP       0x00000002
+#define LCD_CTRL_LCD_16BPP      0x00000004
+#define LCD_CTRL_LCD_BW         0x00000008
+#define LCD_CTRL_LCD_TFT        0x00000010
+#define LCD_CTRL_BGR            0x00001000
+#define LCD_CTRL_LCD_VCOMP      0x00080000
+#define LCD_CTRL_LCD_MONO8      0x00200000
+#define LCD_CTRL_LCD_PWR        0x00400000
+#define LCD_CTRL_LCD_BLE        0x00800000
+#define LCD_CTRL_LDBUSEN        0x01000000
+
+/* Palette */
+#define LCD_PALETTE_BASE        (IO_VIRT + 0x10400)
+
+/* Serial ports */
+#define SERIAL0_OFS             0x20000
+#define SERIAL0_VIRT            (IO_VIRT + SERIAL0_OFS)
+#define SERIAL0_BASE            (IO_PHYS + SERIAL0_OFS)
+
+#define SERIAL1_OFS             0x21000
+#define SERIAL1_VIRT            (IO_VIRT + SERIAL1_OFS)
+#define SERIAL1_BASE            (IO_PHYS + SERIAL1_OFS)
+
+#define SERIAL_ENABLE           0x30
+#define SERIAL_ENABLE_EN        (1<<0)
+
+/* General defines to pacify gcc */
+#define PCIO_BASE               (0)     /* for inb, outb and friends */
+#define PCIO_VIRT               PCIO_BASE
+
+#define __ASM_ARCH_HARDWARE_INCMACH_H
+#include "boards.h"
+#undef __ASM_ARCH_HARDWARE_INCMACH_H
+
+#endif                          /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-h720x/include/mach/io.h b/arch/arm/mach-h720x/include/mach/io.h
new file mode 100644
index 000000000000..1dab74ce88c6
--- /dev/null
+++ b/arch/arm/mach-h720x/include/mach/io.h
@@ -0,0 +1,24 @@
+/*
+ * arch/arm/mach-h720x/include/mach/io.h
+ *
+ * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
+ *
+ * Changelog:
+ *
+ *  09-19-2001  JJKIM
+ *              Created from arch/arm/mach-l7200/include/mach/io.h
+ *
+ *  03-27-2003  Robert Schwebel <r.schwebel@pengutronix.de>:
+ *              re-unified header files for h720x
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#include <mach/hardware.h>
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+#define __io(a)         ((void __iomem *)(a))
+#define __mem_pci(a)    (a)
+
+#endif
diff --git a/arch/arm/mach-h720x/include/mach/irqs.h b/arch/arm/mach-h720x/include/mach/irqs.h
new file mode 100644
index 000000000000..430a92b492f1
--- /dev/null
+++ b/arch/arm/mach-h720x/include/mach/irqs.h
@@ -0,0 +1,116 @@
+/*
+ * arch/arm/mach-h720x/include/mach/irqs.h
+ *
+ * Copyright (C) 2000 Jungjun Kim
+ *           (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
+ *           (C) 2003 Thomas Gleixner <tglx@linutronix.de>
+ *
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#if defined (CONFIG_CPU_H7201)
+
+#define IRQ_PMU         0               /* 0x000001 */
+#define IRQ_DMA         1               /* 0x000002 */
+#define IRQ_LCD         2               /* 0x000004 */
+#define IRQ_VGA         3               /* 0x000008 */
+#define IRQ_PCMCIA1     4               /* 0x000010 */
+#define IRQ_PCMCIA2     5               /* 0x000020 */
+#define IRQ_AFE         6               /* 0x000040 */
+#define IRQ_AIC         7               /* 0x000080 */
+#define IRQ_KEYBOARD    8               /* 0x000100 */
+#define IRQ_TIMER0      9               /* 0x000200 */
+#define IRQ_RTC         10              /* 0x000400 */
+#define IRQ_SOUND       11              /* 0x000800 */
+#define IRQ_USB         12              /* 0x001000 */
+#define IRQ_IrDA        13              /* 0x002000 */
+#define IRQ_UART0       14              /* 0x004000 */
+#define IRQ_UART1       15              /* 0x008000 */
+#define IRQ_SPI         16              /* 0x010000 */
+#define IRQ_GPIOA       17              /* 0x020000 */
+#define IRQ_GPIOB       18              /* 0x040000 */
+#define IRQ_GPIOC       19              /* 0x080000 */
+#define IRQ_GPIOD       20              /* 0x100000 */
+#define IRQ_CommRX      21              /* 0x200000 */
+#define IRQ_CommTX      22              /* 0x400000 */
+#define IRQ_Soft        23              /* 0x800000 */
+
+#define NR_GLBL_IRQS    24
+
+#define IRQ_CHAINED_GPIOA(x)  (NR_GLBL_IRQS + x)
+#define IRQ_CHAINED_GPIOB(x)  (IRQ_CHAINED_GPIOA(32) + x)
+#define IRQ_CHAINED_GPIOC(x)  (IRQ_CHAINED_GPIOB(32) + x)
+#define IRQ_CHAINED_GPIOD(x)  (IRQ_CHAINED_GPIOC(32) + x)
+#define NR_IRQS               IRQ_CHAINED_GPIOD(32)
+
+/* Enable mask for multiplexed interrupts */
+#define IRQ_ENA_MUX     (1<<IRQ_GPIOA) | (1<<IRQ_GPIOB) \
+                        | (1<<IRQ_GPIOC) | (1<<IRQ_GPIOD)
+
+
+#elif defined (CONFIG_CPU_H7202)
+
+#define IRQ_PMU         0               /* 0x00000001 */
+#define IRQ_DMA         1               /* 0x00000002 */
+#define IRQ_LCD         2               /* 0x00000004 */
+#define IRQ_SOUND       3               /* 0x00000008 */
+#define IRQ_I2S         4               /* 0x00000010 */
+#define IRQ_USB         5               /* 0x00000020 */
+#define IRQ_MMC         6               /* 0x00000040 */
+#define IRQ_RTC         7               /* 0x00000080 */
+#define IRQ_UART0       8               /* 0x00000100 */
+#define IRQ_UART1       9               /* 0x00000200 */
+#define IRQ_UART2       10              /* 0x00000400 */
+#define IRQ_UART3       11              /* 0x00000800 */
+#define IRQ_KBD         12              /* 0x00001000 */
+#define IRQ_PS2         13              /* 0x00002000 */
+#define IRQ_AIC         14              /* 0x00004000 */
+#define IRQ_TIMER0      15              /* 0x00008000 */
+#define IRQ_TIMERX      16              /* 0x00010000 */
+#define IRQ_WDT         17              /* 0x00020000 */
+#define IRQ_CAN0        18              /* 0x00040000 */
+#define IRQ_CAN1        19              /* 0x00080000 */
+#define IRQ_EXT0        20              /* 0x00100000 */
+#define IRQ_EXT1        21              /* 0x00200000 */
+#define IRQ_GPIOA       22              /* 0x00400000 */
+#define IRQ_GPIOB       23              /* 0x00800000 */
+#define IRQ_GPIOC       24              /* 0x01000000 */
+#define IRQ_GPIOD       25              /* 0x02000000 */
+#define IRQ_GPIOE       26              /* 0x04000000 */
+#define IRQ_COMMRX      27              /* 0x08000000 */
+#define IRQ_COMMTX      28              /* 0x10000000 */
+#define IRQ_SMC         29              /* 0x20000000 */
+#define IRQ_Soft        30              /* 0x40000000 */
+#define IRQ_RESERVED1   31              /* 0x80000000 */
+#define NR_GLBL_IRQS    32
+
+#define NR_TIMERX_IRQS  3
+
+#define IRQ_CHAINED_GPIOA(x)  (NR_GLBL_IRQS + x)
+#define IRQ_CHAINED_GPIOB(x)  (IRQ_CHAINED_GPIOA(32) + x)
+#define IRQ_CHAINED_GPIOC(x)  (IRQ_CHAINED_GPIOB(32) + x)
+#define IRQ_CHAINED_GPIOD(x)  (IRQ_CHAINED_GPIOC(32) + x)
+#define IRQ_CHAINED_GPIOE(x)  (IRQ_CHAINED_GPIOD(32) + x)
+#define IRQ_CHAINED_TIMERX(x) (IRQ_CHAINED_GPIOE(32) + x)
+#define IRQ_TIMER1            (IRQ_CHAINED_TIMERX(0))
+#define IRQ_TIMER2            (IRQ_CHAINED_TIMERX(1))
+#define IRQ_TIMER64B          (IRQ_CHAINED_TIMERX(2))
+
+#define NR_IRQS         (IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS))
+
+/* Enable mask for multiplexed interrupts */
+#define IRQ_ENA_MUX     (1<<IRQ_TIMERX) | (1<<IRQ_GPIOA) | (1<<IRQ_GPIOB) | \
+                        (1<<IRQ_GPIOC)  | (1<<IRQ_GPIOD) | (1<<IRQ_GPIOE) | \
+                        (1<<IRQ_TIMERX)
+
+#else
+#error cpu definition mismatch
+#endif
+
+/* decode irq number to register number */
+#define IRQ_TO_REGNO(irq) ((irq - NR_GLBL_IRQS) >> 5)
+#define IRQ_TO_BIT(irq) (1 << ((irq - NR_GLBL_IRQS) % 32))
+
+#endif
diff --git a/arch/arm/mach-h720x/include/mach/memory.h b/arch/arm/mach-h720x/include/mach/memory.h
new file mode 100644
index 000000000000..cb26f49cc4e1
--- /dev/null
+++ b/arch/arm/mach-h720x/include/mach/memory.h
@@ -0,0 +1,29 @@
+/*
+ * arch/arm/mach-h720x/include/mach/memory.h
+ *
+ * Copyright (c) 2000 Jungjun Kim
+ *
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Page offset:
+ *    ( 0xc0000000UL )
+ */
+#define PHYS_OFFSET     UL(0x40000000)
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ *
+ * There is something to do here later !, Mar 2000, Jungjun Kim
+ */
+
+#define __virt_to_bus(x)        __virt_to_phys(x)
+#define __bus_to_virt(x)        __phys_to_virt(x)
+
+#endif
diff --git a/arch/arm/mach-h720x/include/mach/system.h b/arch/arm/mach-h720x/include/mach/system.h
new file mode 100644
index 000000000000..e4a7c760d52a
--- /dev/null
+++ b/arch/arm/mach-h720x/include/mach/system.h
@@ -0,0 +1,33 @@
+/*
+ * arch/arm/mach-h720x/include/mach/system.h
+ *
+ * Copyright (C) 2001-2002 Jungjun Kim, Hynix Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * arch/arm/mach-h720x/include/mach/system.h
+ *
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+#include <mach/hardware.h>
+
+static void arch_idle(void)
+{
+        CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_IDLE;
+        nop();
+        nop();
+        CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_RUN;
+        nop();
+        nop();
+}
+
+
+static __inline__ void arch_reset(char mode)
+{
+        CPU_REG (PMU_BASE, PMU_STAT) |= PMU_WARMRESET;
+}
+
+#endif
diff --git a/arch/arm/mach-h720x/include/mach/timex.h b/arch/arm/mach-h720x/include/mach/timex.h
new file mode 100644
index 000000000000..3f2f447ff36b
--- /dev/null
+++ b/arch/arm/mach-h720x/include/mach/timex.h
@@ -0,0 +1,15 @@
+/*
+ * arch/arm/mach-h720x/include/mach/timex.h
+ * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_TIMEX
+#define __ASM_ARCH_TIMEX
+
+#define CLOCK_TICK_RATE         3686400
+
+#endif
diff --git a/arch/arm/mach-h720x/include/mach/uncompress.h b/arch/arm/mach-h720x/include/mach/uncompress.h
new file mode 100644
index 000000000000..d6623234f61e
--- /dev/null
+++ b/arch/arm/mach-h720x/include/mach/uncompress.h
@@ -0,0 +1,37 @@
+/*
+ * arch/arm/mach-h720x/include/mach/uncompress.h
+ *
+ * Copyright (C) 2001-2002 Jungjun Kim
+ */
+
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+
+#include <mach/hardware.h>
+
+#define LSR     0x14
+#define TEMPTY  0x40
+
+static inline void putc(int c)
+{
+        volatile unsigned char *p = (volatile unsigned char *)(IO_PHYS+0x20000);
+
+        /* wait until transmit buffer is empty */
+        while((p[LSR] & TEMPTY) == 0x0)
+                barrier();
+
+        /* write next character */
+        *p = c;
+}
+
+static inline void flush(void)
+{
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
+
+#endif
diff --git a/arch/arm/mach-h720x/include/mach/vmalloc.h b/arch/arm/mach-h720x/include/mach/vmalloc.h
new file mode 100644
index 000000000000..ff1460d6841b
--- /dev/null
+++ b/arch/arm/mach-h720x/include/mach/vmalloc.h
@@ -0,0 +1,10 @@
+/*
+ * arch/arm/mach-h720x/include/mach/vmalloc.h
+ */
+
+#ifndef __ARCH_ARM_VMALLOC_H
+#define __ARCH_ARM_VMALLOC_H
+
+#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+
+#endif
diff --git a/arch/arm/mach-imx/clock.c b/arch/arm/mach-imx/clock.c
index 8915a5fc63cd..4b4230db3765 100644
--- a/arch/arm/mach-imx/clock.c
+++ b/arch/arm/mach-imx/clock.c
@@ -23,7 +23,7 @@
 #include <linux/err.h>
 
 #include <asm/io.h>
-#include <asm/arch/imx-regs.h>
+#include <mach/imx-regs.h>
 
 /*
  * Very simple approach: We can't disable clocks, so we do
diff --git a/arch/arm/mach-imx/cpufreq.c b/arch/arm/mach-imx/cpufreq.c
index 3fee1ac6fd8c..434b4ca0af67 100644
--- a/arch/arm/mach-imx/cpufreq.c
+++ b/arch/arm/mach-imx/cpufreq.c
@@ -36,7 +36,7 @@
 #include <linux/err.h>
 #include <asm/system.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-imx/dma.c b/arch/arm/mach-imx/dma.c
index 17a43ba1696b..c10810c936b3 100644
--- a/arch/arm/mach-imx/dma.c
+++ b/arch/arm/mach-imx/dma.c
@@ -30,9 +30,9 @@
 
 #include <asm/system.h>
 #include <asm/irq.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/dma.h>
-#include <asm/arch/imx-dma.h>
+#include <mach/imx-dma.h>
 
 struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS];
 
diff --git a/arch/arm/mach-imx/generic.c b/arch/arm/mach-imx/generic.c
index df77665fadce..fa72174dd95c 100644
--- a/arch/arm/mach-imx/generic.c
+++ b/arch/arm/mach-imx/generic.c
@@ -29,13 +29,13 @@
 #include <linux/string.h>
 
 #include <asm/errno.h>
-#include <asm/arch/imxfb.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/imx-regs.h>
+#include <mach/imxfb.h>
+#include <mach/hardware.h>
+#include <mach/imx-regs.h>
 
 #include <asm/mach/map.h>
-#include <asm/arch/mmc.h>
-#include <asm/arch/gpio.h>
+#include <mach/mmc.h>
+#include <mach/gpio.h>
 
 unsigned long imx_gpio_alloc_map[(GPIO_PORT_MAX + 1) * 32 / BITS_PER_LONG];
 
diff --git a/arch/arm/mach-imx/include/mach/debug-macro.S b/arch/arm/mach-imx/include/mach/debug-macro.S
new file mode 100644
index 000000000000..87802bbfe633
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/debug-macro.S
@@ -0,0 +1,34 @@
+/* arch/arm/mach-imx/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx, #0x00000000        @ physical
+                movne   \rx, #0xe0000000        @ virtual
+                orreq   \rx, \rx, #0x00200000   @ physical
+                orr     \rx, \rx, #0x00006000   @ UART1 offset
+                .endm
+
+                .macro  senduart,rd,rx
+                str     \rd, [\rx, #0x40]       @ TXDATA
+                .endm
+
+                .macro  waituart,rd,rx
+                .endm
+
+                .macro  busyuart,rd,rx
+1002:           ldr     \rd, [\rx, #0x98]       @ SR2
+                tst     \rd, #1 << 3            @ TXDC
+                beq     1002b                   @ wait until transmit done
+                .endm
diff --git a/include/asm-arm/arch-imx/dma.h b/arch/arm/mach-imx/include/mach/dma.h
index 621ff2c730f2..621ff2c730f2 100644
--- a/include/asm-arm/arch-imx/dma.h
+++ b/arch/arm/mach-imx/include/mach/dma.h
diff --git a/arch/arm/mach-imx/include/mach/entry-macro.S b/arch/arm/mach-imx/include/mach/entry-macro.S
new file mode 100644
index 000000000000..e4db679f7766
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/entry-macro.S
@@ -0,0 +1,32 @@
+/*
+ * arch/arm/mach-imx/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for iMX-based platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <mach/hardware.h>
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_preamble, base, tmp
+                .endm
+
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
+
+#define AITC_NIVECSR   0x40
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                ldr     \base, =IO_ADDRESS(IMX_AITC_BASE)
+                @ Load offset & priority of the highest priority
+                @ interrupt pending.
+                ldr     \irqstat, [\base, #AITC_NIVECSR]
+                @ Shift off the priority leaving the offset or
+                @ "interrupt number", use arithmetic shift to
+                @ transform illegal source (0xffff) as -1
+                mov     \irqnr, \irqstat, asr #16
+                adds    \tmp, \irqnr, #1
+                .endm
diff --git a/arch/arm/mach-imx/include/mach/gpio.h b/arch/arm/mach-imx/include/mach/gpio.h
new file mode 100644
index 000000000000..6e3d795f2264
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/gpio.h
@@ -0,0 +1,102 @@
+#ifndef _IMX_GPIO_H
+
+#include <mach/imx-regs.h>
+
+#define IMX_GPIO_ALLOC_MODE_NORMAL      0
+#define IMX_GPIO_ALLOC_MODE_NO_ALLOC    1
+#define IMX_GPIO_ALLOC_MODE_TRY_ALLOC   2
+#define IMX_GPIO_ALLOC_MODE_ALLOC_ONLY  4
+#define IMX_GPIO_ALLOC_MODE_RELEASE     8
+
+extern int imx_gpio_request(unsigned gpio, const char *label);
+
+extern void imx_gpio_free(unsigned gpio);
+
+extern int imx_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
+                                        int alloc_mode, const char *label);
+
+extern int imx_gpio_direction_input(unsigned gpio);
+
+extern int imx_gpio_direction_output(unsigned gpio, int value);
+
+extern void __imx_gpio_set_value(unsigned gpio, int value);
+
+static inline int imx_gpio_get_value(unsigned gpio)
+{
+        return SSR(gpio >> GPIO_PORT_SHIFT) & (1 << (gpio & GPIO_PIN_MASK));
+}
+
+static inline void imx_gpio_set_value_inline(unsigned gpio, int value)
+{
+        unsigned long flags;
+
+        raw_local_irq_save(flags);
+        if(value)
+                DR(gpio >> GPIO_PORT_SHIFT) |= (1 << (gpio & GPIO_PIN_MASK));
+        else
+                DR(gpio >> GPIO_PORT_SHIFT) &= ~(1 << (gpio & GPIO_PIN_MASK));
+        raw_local_irq_restore(flags);
+}
+
+static inline void imx_gpio_set_value(unsigned gpio, int value)
+{
+        if(__builtin_constant_p(gpio))
+                imx_gpio_set_value_inline(gpio, value);
+        else
+                __imx_gpio_set_value(gpio, value);
+}
+
+extern int imx_gpio_to_irq(unsigned gpio);
+
+extern int imx_irq_to_gpio(unsigned irq);
+
+/*-------------------------------------------------------------------------*/
+
+/* Wrappers for "new style" GPIO calls. These calls i.MX specific versions
+ * to allow future extension of GPIO logic.
+ */
+
+static inline int gpio_request(unsigned gpio, const char *label)
+{
+        return imx_gpio_request(gpio, label);
+}
+
+static inline void gpio_free(unsigned gpio)
+{
+        imx_gpio_free(gpio);
+}
+
+static inline  int gpio_direction_input(unsigned gpio)
+{
+        return imx_gpio_direction_input(gpio);
+}
+
+static inline int gpio_direction_output(unsigned gpio, int value)
+{
+        return imx_gpio_direction_output(gpio, value);
+}
+
+static inline int gpio_get_value(unsigned gpio)
+{
+        return imx_gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+        imx_gpio_set_value(gpio, value);
+}
+
+#include <asm-generic/gpio.h>           /* cansleep wrappers */
+
+static inline int gpio_to_irq(unsigned gpio)
+{
+        return imx_gpio_to_irq(gpio);
+}
+
+static inline int irq_to_gpio(unsigned irq)
+{
+        return imx_irq_to_gpio(irq);
+}
+
+
+#endif
diff --git a/arch/arm/mach-imx/include/mach/hardware.h b/arch/arm/mach-imx/include/mach/hardware.h
new file mode 100644
index 000000000000..c73e9e724c75
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/hardware.h
@@ -0,0 +1,91 @@
+/*
+ *  arch/arm/mach-imx/include/mach/hardware.h
+ *
+ *  Copyright (C) 1999 ARM Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/sizes.h>
+#include "imx-regs.h"
+
+#ifndef __ASSEMBLY__
+# define __REG(x)       (*((volatile u32 *)IO_ADDRESS(x)))
+
+# define __REG2(x,y)        (*(volatile u32 *)((u32)&__REG(x) + (y)))
+#endif
+
+/*
+ * Memory map
+ */
+
+#define IMX_IO_PHYS             0x00200000
+#define IMX_IO_SIZE             0x00100000
+#define IMX_IO_BASE             0xe0000000
+
+#define IMX_CS0_PHYS            0x10000000
+#define IMX_CS0_SIZE            0x02000000
+#define IMX_CS0_VIRT            0xe8000000
+
+#define IMX_CS1_PHYS            0x12000000
+#define IMX_CS1_SIZE            0x01000000
+#define IMX_CS1_VIRT            0xea000000
+
+#define IMX_CS2_PHYS            0x13000000
+#define IMX_CS2_SIZE            0x01000000
+#define IMX_CS2_VIRT            0xeb000000
+
+#define IMX_CS3_PHYS            0x14000000
+#define IMX_CS3_SIZE            0x01000000
+#define IMX_CS3_VIRT            0xec000000
+
+#define IMX_CS4_PHYS            0x15000000
+#define IMX_CS4_SIZE            0x01000000
+#define IMX_CS4_VIRT            0xed000000
+
+#define IMX_CS5_PHYS            0x16000000
+#define IMX_CS5_SIZE            0x01000000
+#define IMX_CS5_VIRT            0xee000000
+
+#define IMX_FB_VIRT             0xF1000000
+#define IMX_FB_SIZE             (256*1024)
+
+/* macro to get at IO space when running virtually */
+#define IO_ADDRESS(x) ((x) | IMX_IO_BASE)
+
+#ifndef __ASSEMBLY__
+/*
+ * Handy routine to set GPIO functions
+ */
+extern void imx_gpio_mode( int gpio_mode );
+
+#endif
+
+#define MAXIRQNUM                       62
+#define MAXFIQNUM                       62
+#define MAXSWINUM                       62
+
+/*
+ * Use SDRAM for memory
+ */
+#define MEM_SIZE                0x01000000
+
+#ifdef CONFIG_ARCH_MX1ADS
+#include "mx1ads.h"
+#endif
+
+#endif
diff --git a/include/asm-arm/arch-imx/imx-dma.h b/arch/arm/mach-imx/include/mach/imx-dma.h
index 44d89c35539a..44d89c35539a 100644
--- a/include/asm-arm/arch-imx/imx-dma.h
+++ b/arch/arm/mach-imx/include/mach/imx-dma.h
diff --git a/include/asm-arm/arch-imx/imx-regs.h b/arch/arm/mach-imx/include/mach/imx-regs.h
index fb9de2733879..fb9de2733879 100644
--- a/include/asm-arm/arch-imx/imx-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx-regs.h
diff --git a/include/asm-arm/arch-imx/imx-uart.h b/arch/arm/mach-imx/include/mach/imx-uart.h
index d54eb1d48026..d54eb1d48026 100644
--- a/include/asm-arm/arch-imx/imx-uart.h
+++ b/arch/arm/mach-imx/include/mach/imx-uart.h
diff --git a/include/asm-arm/arch-imx/imxfb.h b/arch/arm/mach-imx/include/mach/imxfb.h
index 3ed9ec8b9f00..3ed9ec8b9f00 100644
--- a/include/asm-arm/arch-imx/imxfb.h
+++ b/arch/arm/mach-imx/include/mach/imxfb.h
diff --git a/arch/arm/mach-imx/include/mach/io.h b/arch/arm/mach-imx/include/mach/io.h
new file mode 100644
index 000000000000..c50c5fa6fb81
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/io.h
@@ -0,0 +1,30 @@
+/*
+ *  arch/arm/mach-imxads/include/mach/io.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#include <mach/hardware.h>
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+#define __io(a)         ((void __iomem *)(a))
+#define __mem_pci(a)    (a)
+
+#endif
diff --git a/arch/arm/mach-imx/include/mach/irqs.h b/arch/arm/mach-imx/include/mach/irqs.h
new file mode 100644
index 000000000000..eb8d5bd05d56
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/irqs.h
@@ -0,0 +1,116 @@
+/*
+ *  arch/arm/mach-imxads/include/mach/irqs.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ARM_IRQS_H__
+#define __ARM_IRQS_H__
+
+/* Use the imx definitions */
+#include <mach/hardware.h>
+
+/*
+ *  IMX Interrupt numbers
+ *
+ */
+#define INT_SOFTINT                 0
+#define CSI_INT                     6
+#define DSPA_MAC_INT                7
+#define DSPA_INT                    8
+#define COMP_INT                    9
+#define MSHC_XINT                   10
+#define GPIO_INT_PORTA              11
+#define GPIO_INT_PORTB              12
+#define GPIO_INT_PORTC              13
+#define LCDC_INT                    14
+#define SIM_INT                     15
+#define SIM_DATA_INT                16
+#define RTC_INT                     17
+#define RTC_SAMINT                  18
+#define UART2_MINT_PFERR            19
+#define UART2_MINT_RTS              20
+#define UART2_MINT_DTR              21
+#define UART2_MINT_UARTC            22
+#define UART2_MINT_TX               23
+#define UART2_MINT_RX               24
+#define UART1_MINT_PFERR            25
+#define UART1_MINT_RTS              26
+#define UART1_MINT_DTR              27
+#define UART1_MINT_UARTC            28
+#define UART1_MINT_TX               29
+#define UART1_MINT_RX               30
+#define VOICE_DAC_INT               31
+#define VOICE_ADC_INT               32
+#define PEN_DATA_INT                33
+#define PWM_INT                     34
+#define SDHC_INT                    35
+#define I2C_INT                     39
+#define CSPI_INT                    41
+#define SSI_TX_INT                  42
+#define SSI_TX_ERR_INT              43
+#define SSI_RX_INT                  44
+#define SSI_RX_ERR_INT              45
+#define TOUCH_INT                   46
+#define USBD_INT0                   47
+#define USBD_INT1                   48
+#define USBD_INT2                   49
+#define USBD_INT3                   50
+#define USBD_INT4                   51
+#define USBD_INT5                   52
+#define USBD_INT6                   53
+#define BTSYS_INT                   55
+#define BTTIM_INT                   56
+#define BTWUI_INT                   57
+#define TIM2_INT                    58
+#define TIM1_INT                    59
+#define DMA_ERR                     60
+#define DMA_INT                     61
+#define GPIO_INT_PORTD              62
+
+#define IMX_IRQS                         (64)
+
+/* note: the IMX has four gpio ports (A-D), but only
+ *       the following pins are connected to the outside
+ *       world:
+ *
+ * PORT A: bits 0-31
+ * PORT B: bits 8-31
+ * PORT C: bits 3-17
+ * PORT D: bits 6-31
+ *
+ * We map these interrupts straight on. As a result we have
+ * several holes in the interrupt mapping. We do this for two
+ * reasons:
+ *   - mapping the interrupts without holes would get
+ *     far more complicated
+ *   - Motorola could well decide to bring some processor
+ *     with more pins connected
+ */
+
+#define IRQ_GPIOA(x)  (IMX_IRQS + x)
+#define IRQ_GPIOB(x)  (IRQ_GPIOA(32) + x)
+#define IRQ_GPIOC(x)  (IRQ_GPIOB(32) + x)
+#define IRQ_GPIOD(x)  (IRQ_GPIOC(32) + x)
+
+/* decode irq number to use with IMR(x), ISR(x) and friends */
+#define IRQ_TO_REG(irq) ((irq - IMX_IRQS) >> 5)
+
+#define NR_IRQS (IRQ_GPIOD(32) + 1)
+#define IRQ_GPIO(x)
+#endif
diff --git a/arch/arm/mach-imx/include/mach/memory.h b/arch/arm/mach-imx/include/mach/memory.h
new file mode 100644
index 000000000000..5c453063c0ed
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/memory.h
@@ -0,0 +1,36 @@
+/*
+ *  arch/arm/mach-imx/include/mach/memory.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_MMU_H
+#define __ASM_ARCH_MMU_H
+
+#define PHYS_OFFSET     UL(0x08000000)
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+#define __virt_to_bus(x)        (x - PAGE_OFFSET + PHYS_OFFSET)
+#define __bus_to_virt(x)        (x - PHYS_OFFSET + PAGE_OFFSET)
+
+#endif
diff --git a/include/asm-arm/arch-imx/mmc.h b/arch/arm/mach-imx/include/mach/mmc.h
index 4712f354dcca..4712f354dcca 100644
--- a/include/asm-arm/arch-imx/mmc.h
+++ b/arch/arm/mach-imx/include/mach/mmc.h
diff --git a/arch/arm/mach-imx/include/mach/mx1ads.h b/arch/arm/mach-imx/include/mach/mx1ads.h
new file mode 100644
index 000000000000..def05d510eb3
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/mx1ads.h
@@ -0,0 +1,36 @@
+/*
+ * arch/arm/mach-imx/include/mach/mx1ads.h
+ *
+ * Copyright (C) 2004 Robert Schwebel, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __ASM_ARCH_MX1ADS_H
+#define __ASM_ARCH_MX1ADS_H
+
+/* ------------------------------------------------------------------------ */
+/* Memory Map for the M9328MX1ADS (MX1ADS) Board                            */
+/* ------------------------------------------------------------------------ */
+
+#define MX1ADS_FLASH_PHYS               0x10000000
+#define MX1ADS_FLASH_SIZE               (16*1024*1024)
+
+#define IMX_FB_PHYS                     (0x0C000000 - 0x40000)
+
+#define CLK32 32000
+
+#endif /* __ASM_ARCH_MX1ADS_H */
diff --git a/arch/arm/mach-imx/include/mach/spi_imx.h b/arch/arm/mach-imx/include/mach/spi_imx.h
new file mode 100644
index 000000000000..4186430feecf
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/spi_imx.h
@@ -0,0 +1,72 @@
+/*
+ * arch/arm/mach-imx/include/mach/spi_imx.h
+ *
+ * Copyright (C) 2006 SWAPP
+ *      Andrea Paterniani <a.paterniani@swapp-eng.it>
+ *
+ * Initial version inspired by:
+ *      linux-2.6.17-rc3-mm1/arch/arm/mach-pxa/include/mach/pxa2xx_spi.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef SPI_IMX_H_
+#define SPI_IMX_H_
+
+
+/*-------------------------------------------------------------------------*/
+/**
+ * struct spi_imx_master - device.platform_data for SPI controller devices.
+ * @num_chipselect: chipselects are used to distinguish individual
+ *      SPI slaves, and are numbered from zero to num_chipselects - 1.
+ *      each slave has a chipselect signal, but it's common that not
+ *      every chipselect is connected to a slave.
+ * @enable_dma: if true enables DMA driven transfers.
+*/
+struct spi_imx_master {
+        u8 num_chipselect;
+        u8 enable_dma:1;
+};
+/*-------------------------------------------------------------------------*/
+
+
+/*-------------------------------------------------------------------------*/
+/**
+ * struct spi_imx_chip - spi_board_info.controller_data for SPI
+ * slave devices, copied to spi_device.controller_data.
+ * @enable_loopback : used for test purpouse to internally connect RX and TX
+ *      sections.
+ * @enable_dma : enables dma transfer (provided that controller driver has
+ *      dma enabled too).
+ * @ins_ss_pulse : enable /SS pulse insertion between SPI burst.
+ * @bclk_wait : number of bclk waits between each bits_per_word SPI burst.
+ * @cs_control : function pointer to board-specific function to assert/deassert
+ *      I/O port to control HW generation of devices chip-select.
+*/
+struct spi_imx_chip {
+        u8      enable_loopback:1;
+        u8      enable_dma:1;
+        u8      ins_ss_pulse:1;
+        u16     bclk_wait:15;
+        void (*cs_control)(u32 control);
+};
+
+/* Chip-select state */
+#define SPI_CS_ASSERT                   (1 << 0)
+#define SPI_CS_DEASSERT                 (1 << 1)
+/*-------------------------------------------------------------------------*/
+
+
+#endif /* SPI_IMX_H_*/
diff --git a/arch/arm/mach-imx/include/mach/system.h b/arch/arm/mach-imx/include/mach/system.h
new file mode 100644
index 000000000000..adee7e51bab2
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/system.h
@@ -0,0 +1,40 @@
+/*
+ *  arch/arm/mach-imxads/include/mach/system.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+static void
+arch_idle(void)
+{
+        /*
+         * This should do all the clock switching
+         * and wait for interrupt tricks
+         */
+        cpu_do_idle();
+}
+
+static inline void
+arch_reset(char mode)
+{
+        cpu_reset(0);
+}
+
+#endif
diff --git a/include/asm-arm/arch-imx/timex.h b/arch/arm/mach-imx/include/mach/timex.h
index e22ba789546c..e22ba789546c 100644
--- a/include/asm-arm/arch-imx/timex.h
+++ b/arch/arm/mach-imx/include/mach/timex.h
diff --git a/arch/arm/mach-imx/include/mach/uncompress.h b/arch/arm/mach-imx/include/mach/uncompress.h
new file mode 100644
index 000000000000..70523e67a8f6
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/uncompress.h
@@ -0,0 +1,71 @@
+/*
+ *  arch/arm/mach-imxads/include/mach/uncompress.h
+ *
+ *
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) Shane Nay (shane@minirl.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#define UART(x) (*(volatile unsigned long *)(serial_port + (x)))
+
+#define UART1_BASE 0x206000
+#define UART2_BASE 0x207000
+#define USR2 0x98
+#define USR2_TXFE (1<<14)
+#define TXR  0x40
+#define UCR1 0x80
+#define UCR1_UARTEN 1
+
+/*
+ * The following code assumes the serial port has already been
+ * initialized by the bootloader.  We search for the first enabled
+ * port in the most probable order.  If you didn't setup a port in
+ * your bootloader then nothing will appear (which might be desired).
+ *
+ * This does not append a newline
+ */
+static void putc(int c)
+{
+        unsigned long serial_port;
+
+        do {
+                serial_port = UART1_BASE;
+                if ( UART(UCR1) & UCR1_UARTEN )
+                        break;
+                serial_port = UART2_BASE;
+                if ( UART(UCR1) & UCR1_UARTEN )
+                        break;
+                return;
+        } while(0);
+
+        while (!(UART(USR2) & USR2_TXFE))
+                barrier();
+
+        UART(TXR) = c;
+}
+
+static inline void flush(void)
+{
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-imx/include/mach/vmalloc.h b/arch/arm/mach-imx/include/mach/vmalloc.h
new file mode 100644
index 000000000000..7d7cb0bde3e8
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/vmalloc.h
@@ -0,0 +1,20 @@
+/*
+ *  arch/arm/mach-imx/include/mach/vmalloc.h
+ *
+ *  Copyright (C) 2000 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
diff --git a/arch/arm/mach-imx/irq.c b/arch/arm/mach-imx/irq.c
index 167b7fcbed2f..798f221eb3b7 100644
--- a/arch/arm/mach-imx/irq.c
+++ b/arch/arm/mach-imx/irq.c
@@ -27,7 +27,7 @@
 #include <linux/list.h>
 #include <linux/timer.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/io.h>
 
diff --git a/arch/arm/mach-imx/leds-mx1ads.c b/arch/arm/mach-imx/leds-mx1ads.c
index 8757d37354f2..af81621f689b 100644
--- a/arch/arm/mach-imx/leds-mx1ads.c
+++ b/arch/arm/mach-imx/leds-mx1ads.c
@@ -13,7 +13,7 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/system.h>
 #include <asm/io.h>
 #include <asm/leds.h>
diff --git a/arch/arm/mach-imx/mx1ads.c b/arch/arm/mach-imx/mx1ads.c
index baf5e2f711ee..87fa1ff43b0b 100644
--- a/arch/arm/mach-imx/mx1ads.c
+++ b/arch/arm/mach-imx/mx1ads.c
@@ -16,7 +16,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <asm/system.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
@@ -25,8 +25,8 @@
 #include <asm/mach-types.h>
 
 #include <asm/mach/arch.h>
-#include <asm/arch/mmc.h>
-#include <asm/arch/imx-uart.h>
+#include <mach/mmc.h>
+#include <mach/imx-uart.h>
 #include <linux/interrupt.h>
 #include "generic.h"
 
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
index 7fc6d2cdfd99..08be3875c59e 100644
--- a/arch/arm/mach-imx/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -19,7 +19,7 @@
 #include <linux/clockchips.h>
 #include <linux/clk.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/leds.h>
 #include <asm/irq.h>
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index f439bf12be5e..8bacf6d4d097 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -20,11 +20,11 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/serial.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/io.h>
 #include <asm/hardware/arm_timer.h>
-#include <asm/arch/cm.h>
+#include <mach/cm.h>
 #include <asm/system.h>
 #include <asm/leds.h>
 #include <asm/mach/time.h>
diff --git a/arch/arm/mach-integrator/cpu.c b/arch/arm/mach-integrator/cpu.c
index afa0f21ea96e..ce5ea7c26675 100644
--- a/arch/arm/mach-integrator/cpu.c
+++ b/arch/arm/mach-integrator/cpu.c
@@ -20,7 +20,7 @@
 #include <linux/smp.h>
 #include <linux/init.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/mach-types.h>
 #include <asm/hardware/icst525.h>
diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c
index 5a1588cf8242..0a7b3267c8d8 100644
--- a/arch/arm/mach-integrator/impd1.c
+++ b/arch/arm/mach-integrator/impd1.c
@@ -23,8 +23,8 @@
 
 #include <asm/io.h>
 #include <asm/hardware/icst525.h>
-#include <asm/arch/lm.h>
-#include <asm/arch/impd1.h>
+#include <mach/lm.h>
+#include <mach/impd1.h>
 #include <asm/sizes.h>
 
 #include "clock.h"
diff --git a/include/asm-arm/arch-integrator/bits.h b/arch/arm/mach-integrator/include/mach/bits.h
index 09b024e0496a..09b024e0496a 100644
--- a/include/asm-arm/arch-integrator/bits.h
+++ b/arch/arm/mach-integrator/include/mach/bits.h
diff --git a/include/asm-arm/arch-integrator/cm.h b/arch/arm/mach-integrator/include/mach/cm.h
index 1ab353e23595..1ab353e23595 100644
--- a/include/asm-arm/arch-integrator/cm.h
+++ b/arch/arm/mach-integrator/include/mach/cm.h
diff --git a/arch/arm/mach-integrator/include/mach/debug-macro.S b/arch/arm/mach-integrator/include/mach/debug-macro.S
new file mode 100644
index 000000000000..d347d659ea30
--- /dev/null
+++ b/arch/arm/mach-integrator/include/mach/debug-macro.S
@@ -0,0 +1,22 @@
+/* arch/arm/mach-integrator/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx, #0x16000000        @ physical base address
+                movne   \rx, #0xf0000000        @ virtual base
+                addne   \rx, \rx, #0x16000000 >> 4
+                .endm
+
+#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-integrator/include/mach/dma.h b/arch/arm/mach-integrator/include/mach/dma.h
new file mode 100644
index 000000000000..fbebe85a2db7
--- /dev/null
+++ b/arch/arm/mach-integrator/include/mach/dma.h
@@ -0,0 +1,19 @@
+/*
+ *  arch/arm/mach-integrator/include/mach/dma.h
+ *
+ *  Copyright (C) 1997,1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
diff --git a/arch/arm/mach-integrator/include/mach/entry-macro.S b/arch/arm/mach-integrator/include/mach/entry-macro.S
new file mode 100644
index 000000000000..7649c57acb53
--- /dev/null
+++ b/arch/arm/mach-integrator/include/mach/entry-macro.S
@@ -0,0 +1,44 @@
+/*
+ * arch/arm/mach-integrator/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for Integrator platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_preamble, base, tmp
+                .endm
+
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+/* FIXME: should not be using soo many LDRs here */
+                ldr     \base, =IO_ADDRESS(INTEGRATOR_IC_BASE)
+                mov     \irqnr, #IRQ_PIC_START
+                ldr     \irqstat, [\base, #IRQ_STATUS]          @ get masked status
+                ldr     \base, =IO_ADDRESS(INTEGRATOR_HDR_BASE)
+                teq     \irqstat, #0
+                ldreq   \irqstat, [\base, #(INTEGRATOR_HDR_IC_OFFSET+IRQ_STATUS)]
+                moveq   \irqnr, #IRQ_CIC_START
+
+1001:           tst     \irqstat, #15
+                bne     1002f
+                add     \irqnr, \irqnr, #4
+                movs    \irqstat, \irqstat, lsr #4
+                bne     1001b
+1002:           tst     \irqstat, #1
+                bne     1003f
+                add     \irqnr, \irqnr, #1
+                movs    \irqstat, \irqstat, lsr #1
+                bne     1002b
+1003:           /* EQ will be set if no irqs pending */
+                .endm
+
diff --git a/arch/arm/mach-integrator/include/mach/hardware.h b/arch/arm/mach-integrator/include/mach/hardware.h
new file mode 100644
index 000000000000..1251319ef9ae
--- /dev/null
+++ b/arch/arm/mach-integrator/include/mach/hardware.h
@@ -0,0 +1,48 @@
+/*
+ *  arch/arm/mach-integrator/include/mach/hardware.h
+ *
+ *  This file contains the hardware definitions of the Integrator.
+ *
+ *  Copyright (C) 1999 ARM Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/sizes.h>
+#include <mach/platform.h>
+
+/*
+ * Where in virtual memory the IO devices (timers, system controllers
+ * and so on)
+ */
+#define IO_BASE                 0xF0000000                 // VA of IO 
+#define IO_SIZE                 0x0B000000                 // How much?
+#define IO_START                INTEGRATOR_HDR_BASE        // PA of IO
+
+#define PCIO_BASE               PCI_IO_VADDR
+#define PCIMEM_BASE             PCI_MEMORY_VADDR
+
+/* macro to get at IO space when running virtually */
+#define IO_ADDRESS(x) (((x) >> 4) + IO_BASE) 
+
+#define pcibios_assign_all_busses()     1
+
+#define PCIBIOS_MIN_IO          0x6000
+#define PCIBIOS_MIN_MEM         0x00100000
+
+#endif
+
diff --git a/include/asm-arm/arch-integrator/impd1.h b/arch/arm/mach-integrator/include/mach/impd1.h
index d75de4b14237..d75de4b14237 100644
--- a/include/asm-arm/arch-integrator/impd1.h
+++ b/arch/arm/mach-integrator/include/mach/impd1.h
diff --git a/arch/arm/mach-integrator/include/mach/io.h b/arch/arm/mach-integrator/include/mach/io.h
new file mode 100644
index 000000000000..f21bb5493dd9
--- /dev/null
+++ b/arch/arm/mach-integrator/include/mach/io.h
@@ -0,0 +1,36 @@
+/*
+ *  arch/arm/mach-integrator/include/mach/io.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffff
+
+/*
+ * WARNING: this has to mirror definitions in platform.h
+ */
+#define PCI_MEMORY_VADDR        0xe8000000
+#define PCI_CONFIG_VADDR        0xec000000
+#define PCI_V3_VADDR            0xed000000
+#define PCI_IO_VADDR            0xee000000
+
+#define __io(a)                 ((void __iomem *)(PCI_IO_VADDR + (a)))
+#define __mem_pci(a)            (a)
+
+#endif
diff --git a/arch/arm/mach-integrator/include/mach/irqs.h b/arch/arm/mach-integrator/include/mach/irqs.h
new file mode 100644
index 000000000000..1fbe6d190222
--- /dev/null
+++ b/arch/arm/mach-integrator/include/mach/irqs.h
@@ -0,0 +1,82 @@
+/*
+ *  arch/arm/mach-integrator/include/mach/irqs.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/* 
+ *  Interrupt numbers
+ */
+#define IRQ_PIC_START                   0
+#define IRQ_SOFTINT                     0
+#define IRQ_UARTINT0                    1
+#define IRQ_UARTINT1                    2
+#define IRQ_KMIINT0                     3
+#define IRQ_KMIINT1                     4
+#define IRQ_TIMERINT0                   5
+#define IRQ_TIMERINT1                   6
+#define IRQ_TIMERINT2                   7
+#define IRQ_RTCINT                      8
+#define IRQ_AP_EXPINT0                  9
+#define IRQ_AP_EXPINT1                  10
+#define IRQ_AP_EXPINT2                  11
+#define IRQ_AP_EXPINT3                  12
+#define IRQ_AP_PCIINT0                  13
+#define IRQ_AP_PCIINT1                  14
+#define IRQ_AP_PCIINT2                  15
+#define IRQ_AP_PCIINT3                  16
+#define IRQ_AP_V3INT                    17
+#define IRQ_AP_CPINT0                   18
+#define IRQ_AP_CPINT1                   19
+#define IRQ_AP_LBUSTIMEOUT              20
+#define IRQ_AP_APCINT                   21
+#define IRQ_CP_CLCDCINT                 22
+#define IRQ_CP_MMCIINT0                 23
+#define IRQ_CP_MMCIINT1                 24
+#define IRQ_CP_AACIINT                  25
+#define IRQ_CP_CPPLDINT                 26
+#define IRQ_CP_ETHINT                   27
+#define IRQ_CP_TSPENINT                 28
+#define IRQ_PIC_END                     31
+
+#define IRQ_CIC_START                   32
+#define IRQ_CM_SOFTINT                  32
+#define IRQ_CM_COMMRX                   33
+#define IRQ_CM_COMMTX                   34
+#define IRQ_CIC_END                     34
+
+/*
+ * IntegratorCP only
+ */
+#define IRQ_SIC_START                   35
+#define IRQ_SIC_CP_SOFTINT              35
+#define IRQ_SIC_CP_RI0                  36
+#define IRQ_SIC_CP_RI1                  37
+#define IRQ_SIC_CP_CARDIN               38
+#define IRQ_SIC_CP_LMINT0               39
+#define IRQ_SIC_CP_LMINT1               40
+#define IRQ_SIC_CP_LMINT2               41
+#define IRQ_SIC_CP_LMINT3               42
+#define IRQ_SIC_CP_LMINT4               43
+#define IRQ_SIC_CP_LMINT5               44
+#define IRQ_SIC_CP_LMINT6               45
+#define IRQ_SIC_CP_LMINT7               46
+#define IRQ_SIC_END                     46
+
+#define NR_IRQS                         47
+
diff --git a/include/asm-arm/arch-integrator/lm.h b/arch/arm/mach-integrator/include/mach/lm.h
index 28186b6f2c09..28186b6f2c09 100644
--- a/include/asm-arm/arch-integrator/lm.h
+++ b/arch/arm/mach-integrator/include/mach/lm.h
diff --git a/arch/arm/mach-integrator/include/mach/memory.h b/arch/arm/mach-integrator/include/mach/memory.h
new file mode 100644
index 000000000000..be7e63c21d25
--- /dev/null
+++ b/arch/arm/mach-integrator/include/mach/memory.h
@@ -0,0 +1,39 @@
+/*
+ *  arch/arm/mach-integrator/include/mach/memory.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     UL(0x00000000)
+#define BUS_OFFSET      UL(0x80000000)
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+#define __virt_to_bus(x)        (x - PAGE_OFFSET + BUS_OFFSET)
+#define __bus_to_virt(x)        (x - BUS_OFFSET + PAGE_OFFSET)
+
+#endif
diff --git a/include/asm-arm/arch-integrator/platform.h b/arch/arm/mach-integrator/include/mach/platform.h
index 83c4c1ceb411..83c4c1ceb411 100644
--- a/include/asm-arm/arch-integrator/platform.h
+++ b/arch/arm/mach-integrator/include/mach/platform.h
diff --git a/arch/arm/mach-integrator/include/mach/system.h b/arch/arm/mach-integrator/include/mach/system.h
new file mode 100644
index 000000000000..c485345c8c77
--- /dev/null
+++ b/arch/arm/mach-integrator/include/mach/system.h
@@ -0,0 +1,44 @@
+/*
+ *  arch/arm/mach-integrator/include/mach/system.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <mach/cm.h>
+
+static inline void arch_idle(void)
+{
+        /*
+         * This should do all the clock switching
+         * and wait for interrupt tricks
+         */
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        /*
+         * To reset, we hit the on-board reset register
+         * in the system FPGA
+         */
+        cm_control(CM_CTRL_RESET, CM_CTRL_RESET);
+}
+
+#endif
diff --git a/arch/arm/mach-integrator/include/mach/timex.h b/arch/arm/mach-integrator/include/mach/timex.h
new file mode 100644
index 000000000000..1dcb42028c82
--- /dev/null
+++ b/arch/arm/mach-integrator/include/mach/timex.h
@@ -0,0 +1,26 @@
+/*
+ *  arch/arm/mach-integrator/include/mach/timex.h
+ *
+ *  Integrator architecture timex specifications
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/*
+ * ??
+ */
+#define CLOCK_TICK_RATE         (50000000 / 16)
diff --git a/arch/arm/mach-integrator/include/mach/uncompress.h b/arch/arm/mach-integrator/include/mach/uncompress.h
new file mode 100644
index 000000000000..30452f00a164
--- /dev/null
+++ b/arch/arm/mach-integrator/include/mach/uncompress.h
@@ -0,0 +1,50 @@
+/*
+ *  arch/arm/mach-integrator/include/mach/uncompress.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#define AMBA_UART_DR    (*(volatile unsigned char *)0x16000000)
+#define AMBA_UART_LCRH  (*(volatile unsigned char *)0x16000008)
+#define AMBA_UART_LCRM  (*(volatile unsigned char *)0x1600000c)
+#define AMBA_UART_LCRL  (*(volatile unsigned char *)0x16000010)
+#define AMBA_UART_CR    (*(volatile unsigned char *)0x16000014)
+#define AMBA_UART_FR    (*(volatile unsigned char *)0x16000018)
+
+/*
+ * This does not append a newline
+ */
+static void putc(int c)
+{
+        while (AMBA_UART_FR & (1 << 5))
+                barrier();
+
+        AMBA_UART_DR = c;
+}
+
+static inline void flush(void)
+{
+        while (AMBA_UART_FR & (1 << 3))
+                barrier();
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-integrator/include/mach/vmalloc.h b/arch/arm/mach-integrator/include/mach/vmalloc.h
new file mode 100644
index 000000000000..e87ab0b37bdd
--- /dev/null
+++ b/arch/arm/mach-integrator/include/mach/vmalloc.h
@@ -0,0 +1,20 @@
+/*
+ *  arch/arm/mach-integrator/include/mach/vmalloc.h
+ *
+ *  Copyright (C) 2000 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 3996ddc2a4b1..6e472b5f8f26 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -28,14 +28,14 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/kmi.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/setup.h>
 #include <asm/param.h>          /* HZ */
 #include <asm/mach-types.h>
 
-#include <asm/arch/lm.h>
+#include <mach/lm.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 28d330101e6f..6b99e9c258bd 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -20,15 +20,15 @@
 #include <linux/amba/kmi.h>
 #include <linux/amba/clcd.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/hardware/icst525.h>
 
-#include <asm/arch/cm.h>
-#include <asm/arch/lm.h>
+#include <mach/cm.h>
+#include <mach/lm.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
diff --git a/arch/arm/mach-integrator/leds.c b/arch/arm/mach-integrator/leds.c
index 6062180b108b..7bc6881434ec 100644
--- a/arch/arm/mach-integrator/leds.c
+++ b/arch/arm/mach-integrator/leds.c
@@ -25,12 +25,12 @@
 #include <linux/smp.h>
 #include <linux/spinlock.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/leds.h>
 #include <asm/system.h>
 #include <asm/mach-types.h>
-#include <asm/arch/cm.h>
+#include <mach/cm.h>
 
 static int saved_leds;
 
diff --git a/arch/arm/mach-integrator/lm.c b/arch/arm/mach-integrator/lm.c
index f939c5091405..f52c7af31eaa 100644
--- a/arch/arm/mach-integrator/lm.c
+++ b/arch/arm/mach-integrator/lm.c
@@ -12,7 +12,7 @@
 #include <linux/device.h>
 #include <linux/slab.h>
 
-#include <asm/arch/lm.h>
+#include <mach/lm.h>
 
 #define to_lm_device(d) container_of(d, struct lm_device, dev)
 #define to_lm_driver(d) container_of(d, struct lm_driver, drv)
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index b8685d919fee..9f2b1ea8fb20 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -28,7 +28,7 @@
 #include <linux/spinlock.h>
 #include <linux/init.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/system.h>
diff --git a/arch/arm/mach-iop13xx/include/mach/adma.h b/arch/arm/mach-iop13xx/include/mach/adma.h
new file mode 100644
index 000000000000..60019c8e6465
--- /dev/null
+++ b/arch/arm/mach-iop13xx/include/mach/adma.h
@@ -0,0 +1,537 @@
+/*
+ * Copyright(c) 2006, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+#ifndef _ADMA_H
+#define _ADMA_H
+#include <linux/types.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <asm/hardware/iop_adma.h>
+
+#define ADMA_ACCR(chan) (chan->mmr_base + 0x0)
+#define ADMA_ACSR(chan) (chan->mmr_base + 0x4)
+#define ADMA_ADAR(chan) (chan->mmr_base + 0x8)
+#define ADMA_IIPCR(chan)        (chan->mmr_base + 0x18)
+#define ADMA_IIPAR(chan)        (chan->mmr_base + 0x1c)
+#define ADMA_IIPUAR(chan)       (chan->mmr_base + 0x20)
+#define ADMA_ANDAR(chan)        (chan->mmr_base + 0x24)
+#define ADMA_ADCR(chan) (chan->mmr_base + 0x28)
+#define ADMA_CARMD(chan)        (chan->mmr_base + 0x2c)
+#define ADMA_ABCR(chan) (chan->mmr_base + 0x30)
+#define ADMA_DLADR(chan)        (chan->mmr_base + 0x34)
+#define ADMA_DUADR(chan)        (chan->mmr_base + 0x38)
+#define ADMA_SLAR(src, chan)    (chan->mmr_base + (0x3c + (src << 3)))
+#define ADMA_SUAR(src, chan)    (chan->mmr_base + (0x40 + (src << 3)))
+
+struct iop13xx_adma_src {
+        u32 src_addr;
+        union {
+                u32 upper_src_addr;
+                struct {
+                        unsigned int pq_upper_src_addr:24;
+                        unsigned int pq_dmlt:8;
+                };
+        };
+};
+
+struct iop13xx_adma_desc_ctrl {
+        unsigned int int_en:1;
+        unsigned int xfer_dir:2;
+        unsigned int src_select:4;
+        unsigned int zero_result:1;
+        unsigned int block_fill_en:1;
+        unsigned int crc_gen_en:1;
+        unsigned int crc_xfer_dis:1;
+        unsigned int crc_seed_fetch_dis:1;
+        unsigned int status_write_back_en:1;
+        unsigned int endian_swap_en:1;
+        unsigned int reserved0:2;
+        unsigned int pq_update_xfer_en:1;
+        unsigned int dual_xor_en:1;
+        unsigned int pq_xfer_en:1;
+        unsigned int p_xfer_dis:1;
+        unsigned int reserved1:10;
+        unsigned int relax_order_en:1;
+        unsigned int no_snoop_en:1;
+};
+
+struct iop13xx_adma_byte_count {
+        unsigned int byte_count:24;
+        unsigned int host_if:3;
+        unsigned int reserved:2;
+        unsigned int zero_result_err_q:1;
+        unsigned int zero_result_err:1;
+        unsigned int tx_complete:1;
+};
+
+struct iop13xx_adma_desc_hw {
+        u32 next_desc;
+        union {
+                u32 desc_ctrl;
+                struct iop13xx_adma_desc_ctrl desc_ctrl_field;
+        };
+        union {
+                u32 crc_addr;
+                u32 block_fill_data;
+                u32 q_dest_addr;
+        };
+        union {
+                u32 byte_count;
+                struct iop13xx_adma_byte_count byte_count_field;
+        };
+        union {
+                u32 dest_addr;
+                u32 p_dest_addr;
+        };
+        union {
+                u32 upper_dest_addr;
+                u32 pq_upper_dest_addr;
+        };
+        struct iop13xx_adma_src src[1];
+};
+
+struct iop13xx_adma_desc_dual_xor {
+        u32 next_desc;
+        u32 desc_ctrl;
+        u32 reserved;
+        u32 byte_count;
+        u32 h_dest_addr;
+        u32 h_upper_dest_addr;
+        u32 src0_addr;
+        u32 upper_src0_addr;
+        u32 src1_addr;
+        u32 upper_src1_addr;
+        u32 h_src_addr;
+        u32 h_upper_src_addr;
+        u32 d_src_addr;
+        u32 d_upper_src_addr;
+        u32 d_dest_addr;
+        u32 d_upper_dest_addr;
+};
+
+struct iop13xx_adma_desc_pq_update {
+        u32 next_desc;
+        u32 desc_ctrl;
+        u32 reserved;
+        u32 byte_count;
+        u32 p_dest_addr;
+        u32 p_upper_dest_addr;
+        u32 src0_addr;
+        u32 upper_src0_addr;
+        u32 src1_addr;
+        u32 upper_src1_addr;
+        u32 p_src_addr;
+        u32 p_upper_src_addr;
+        u32 q_src_addr;
+        struct {
+                unsigned int q_upper_src_addr:24;
+                unsigned int q_dmlt:8;
+        };
+        u32 q_dest_addr;
+        u32 q_upper_dest_addr;
+};
+
+static inline int iop_adma_get_max_xor(void)
+{
+        return 16;
+}
+
+static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan)
+{
+        return __raw_readl(ADMA_ADAR(chan));
+}
+
+static inline void iop_chan_set_next_descriptor(struct iop_adma_chan *chan,
+                                                u32 next_desc_addr)
+{
+        __raw_writel(next_desc_addr, ADMA_ANDAR(chan));
+}
+
+#define ADMA_STATUS_BUSY (1 << 13)
+
+static inline char iop_chan_is_busy(struct iop_adma_chan *chan)
+{
+        if (__raw_readl(ADMA_ACSR(chan)) &
+                ADMA_STATUS_BUSY)
+                return 1;
+        else
+                return 0;
+}
+
+static inline int
+iop_chan_get_desc_align(struct iop_adma_chan *chan, int num_slots)
+{
+        return 1;
+}
+#define iop_desc_is_aligned(x, y) 1
+
+static inline int
+iop_chan_memcpy_slot_count(size_t len, int *slots_per_op)
+{
+        *slots_per_op = 1;
+        return 1;
+}
+
+#define iop_chan_interrupt_slot_count(s, c) iop_chan_memcpy_slot_count(0, s)
+
+static inline int
+iop_chan_memset_slot_count(size_t len, int *slots_per_op)
+{
+        *slots_per_op = 1;
+        return 1;
+}
+
+static inline int
+iop_chan_xor_slot_count(size_t len, int src_cnt, int *slots_per_op)
+{
+        static const char slot_count_table[] = { 1, 2, 2, 2,
+                                                 2, 3, 3, 3,
+                                                 3, 4, 4, 4,
+                                                 4, 5, 5, 5,
+                                                };
+        *slots_per_op = slot_count_table[src_cnt - 1];
+        return *slots_per_op;
+}
+
+#define ADMA_MAX_BYTE_COUNT     (16 * 1024 * 1024)
+#define IOP_ADMA_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
+#define IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
+#define IOP_ADMA_XOR_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
+#define iop_chan_zero_sum_slot_count(l, s, o) iop_chan_xor_slot_count(l, s, o)
+
+static inline u32 iop_desc_get_dest_addr(struct iop_adma_desc_slot *desc,
+                                        struct iop_adma_chan *chan)
+{
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
+        return hw_desc->dest_addr;
+}
+
+static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc,
+                                        struct iop_adma_chan *chan)
+{
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
+        return hw_desc->byte_count_field.byte_count;
+}
+
+static inline u32 iop_desc_get_src_addr(struct iop_adma_desc_slot *desc,
+                                        struct iop_adma_chan *chan,
+                                        int src_idx)
+{
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
+        return hw_desc->src[src_idx].src_addr;
+}
+
+static inline u32 iop_desc_get_src_count(struct iop_adma_desc_slot *desc,
+                                        struct iop_adma_chan *chan)
+{
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
+        return hw_desc->desc_ctrl_field.src_select + 1;
+}
+
+static inline void
+iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, unsigned long flags)
+{
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
+        union {
+                u32 value;
+                struct iop13xx_adma_desc_ctrl field;
+        } u_desc_ctrl;
+
+        u_desc_ctrl.value = 0;
+        u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
+        u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
+        hw_desc->desc_ctrl = u_desc_ctrl.value;
+        hw_desc->crc_addr = 0;
+}
+
+static inline void
+iop_desc_init_memset(struct iop_adma_desc_slot *desc, unsigned long flags)
+{
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
+        union {
+                u32 value;
+                struct iop13xx_adma_desc_ctrl field;
+        } u_desc_ctrl;
+
+        u_desc_ctrl.value = 0;
+        u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
+        u_desc_ctrl.field.block_fill_en = 1;
+        u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
+        hw_desc->desc_ctrl = u_desc_ctrl.value;
+        hw_desc->crc_addr = 0;
+}
+
+/* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */
+static inline void
+iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt,
+                  unsigned long flags)
+{
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
+        union {
+                u32 value;
+                struct iop13xx_adma_desc_ctrl field;
+        } u_desc_ctrl;
+
+        u_desc_ctrl.value = 0;
+        u_desc_ctrl.field.src_select = src_cnt - 1;
+        u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
+        u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
+        hw_desc->desc_ctrl = u_desc_ctrl.value;
+        hw_desc->crc_addr = 0;
+
+}
+#define iop_desc_init_null_xor(d, s, i) iop_desc_init_xor(d, s, i)
+
+/* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */
+static inline int
+iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt,
+                       unsigned long flags)
+{
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
+        union {
+                u32 value;
+                struct iop13xx_adma_desc_ctrl field;
+        } u_desc_ctrl;
+
+        u_desc_ctrl.value = 0;
+        u_desc_ctrl.field.src_select = src_cnt - 1;
+        u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
+        u_desc_ctrl.field.zero_result = 1;
+        u_desc_ctrl.field.status_write_back_en = 1;
+        u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
+        hw_desc->desc_ctrl = u_desc_ctrl.value;
+        hw_desc->crc_addr = 0;
+
+        return 1;
+}
+
+static inline void iop_desc_set_byte_count(struct iop_adma_desc_slot *desc,
+                                        struct iop_adma_chan *chan,
+                                        u32 byte_count)
+{
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
+        hw_desc->byte_count = byte_count;
+}
+
+static inline void
+iop_desc_set_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len)
+{
+        int slots_per_op = desc->slots_per_op;
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter;
+        int i = 0;
+
+        if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) {
+                hw_desc->byte_count = len;
+        } else {
+                do {
+                        iter = iop_hw_desc_slot_idx(hw_desc, i);
+                        iter->byte_count = IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
+                        len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
+                        i += slots_per_op;
+                } while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT);
+
+                if (len) {
+                        iter = iop_hw_desc_slot_idx(hw_desc, i);
+                        iter->byte_count = len;
+                }
+        }
+}
+
+
+static inline void iop_desc_set_dest_addr(struct iop_adma_desc_slot *desc,
+                                        struct iop_adma_chan *chan,
+                                        dma_addr_t addr)
+{
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
+        hw_desc->dest_addr = addr;
+        hw_desc->upper_dest_addr = 0;
+}
+
+static inline void iop_desc_set_memcpy_src_addr(struct iop_adma_desc_slot *desc,
+                                        dma_addr_t addr)
+{
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
+        hw_desc->src[0].src_addr = addr;
+        hw_desc->src[0].upper_src_addr = 0;
+}
+
+static inline void iop_desc_set_xor_src_addr(struct iop_adma_desc_slot *desc,
+                                        int src_idx, dma_addr_t addr)
+{
+        int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op;
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter;
+        int i = 0;
+
+        do {
+                iter = iop_hw_desc_slot_idx(hw_desc, i);
+                iter->src[src_idx].src_addr = addr;
+                iter->src[src_idx].upper_src_addr = 0;
+                slot_cnt -= slots_per_op;
+                if (slot_cnt) {
+                        i += slots_per_op;
+                        addr += IOP_ADMA_XOR_MAX_BYTE_COUNT;
+                }
+        } while (slot_cnt);
+}
+
+static inline void
+iop_desc_init_interrupt(struct iop_adma_desc_slot *desc,
+        struct iop_adma_chan *chan)
+{
+        iop_desc_init_memcpy(desc, 1);
+        iop_desc_set_byte_count(desc, chan, 0);
+        iop_desc_set_dest_addr(desc, chan, 0);
+        iop_desc_set_memcpy_src_addr(desc, 0);
+}
+
+#define iop_desc_set_zero_sum_src_addr iop_desc_set_xor_src_addr
+
+static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc,
+                                        u32 next_desc_addr)
+{
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
+        BUG_ON(hw_desc->next_desc);
+        hw_desc->next_desc = next_desc_addr;
+}
+
+static inline u32 iop_desc_get_next_desc(struct iop_adma_desc_slot *desc)
+{
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
+        return hw_desc->next_desc;
+}
+
+static inline void iop_desc_clear_next_desc(struct iop_adma_desc_slot *desc)
+{
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
+        hw_desc->next_desc = 0;
+}
+
+static inline void iop_desc_set_block_fill_val(struct iop_adma_desc_slot *desc,
+                                                u32 val)
+{
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
+        hw_desc->block_fill_data = val;
+}
+
+static inline int iop_desc_get_zero_result(struct iop_adma_desc_slot *desc)
+{
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
+        struct iop13xx_adma_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field;
+        struct iop13xx_adma_byte_count byte_count = hw_desc->byte_count_field;
+
+        BUG_ON(!(byte_count.tx_complete && desc_ctrl.zero_result));
+
+        if (desc_ctrl.pq_xfer_en)
+                return byte_count.zero_result_err_q;
+        else
+                return byte_count.zero_result_err;
+}
+
+static inline void iop_chan_append(struct iop_adma_chan *chan)
+{
+        u32 adma_accr;
+
+        adma_accr = __raw_readl(ADMA_ACCR(chan));
+        adma_accr |= 0x2;
+        __raw_writel(adma_accr, ADMA_ACCR(chan));
+}
+
+static inline u32 iop_chan_get_status(struct iop_adma_chan *chan)
+{
+        return __raw_readl(ADMA_ACSR(chan));
+}
+
+static inline void iop_chan_disable(struct iop_adma_chan *chan)
+{
+        u32 adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan));
+        adma_chan_ctrl &= ~0x1;
+        __raw_writel(adma_chan_ctrl, ADMA_ACCR(chan));
+}
+
+static inline void iop_chan_enable(struct iop_adma_chan *chan)
+{
+        u32 adma_chan_ctrl;
+
+        adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan));
+        adma_chan_ctrl |= 0x1;
+        __raw_writel(adma_chan_ctrl, ADMA_ACCR(chan));
+}
+
+static inline void iop_adma_device_clear_eot_status(struct iop_adma_chan *chan)
+{
+        u32 status = __raw_readl(ADMA_ACSR(chan));
+        status &= (1 << 12);
+        __raw_writel(status, ADMA_ACSR(chan));
+}
+
+static inline void iop_adma_device_clear_eoc_status(struct iop_adma_chan *chan)
+{
+        u32 status = __raw_readl(ADMA_ACSR(chan));
+        status &= (1 << 11);
+        __raw_writel(status, ADMA_ACSR(chan));
+}
+
+static inline void iop_adma_device_clear_err_status(struct iop_adma_chan *chan)
+{
+        u32 status = __raw_readl(ADMA_ACSR(chan));
+        status &= (1 << 9) | (1 << 5) | (1 << 4) | (1 << 3);
+        __raw_writel(status, ADMA_ACSR(chan));
+}
+
+static inline int
+iop_is_err_int_parity(unsigned long status, struct iop_adma_chan *chan)
+{
+        return test_bit(9, &status);
+}
+
+static inline int
+iop_is_err_mcu_abort(unsigned long status, struct iop_adma_chan *chan)
+{
+        return test_bit(5, &status);
+}
+
+static inline int
+iop_is_err_int_tabort(unsigned long status, struct iop_adma_chan *chan)
+{
+        return test_bit(4, &status);
+}
+
+static inline int
+iop_is_err_int_mabort(unsigned long status, struct iop_adma_chan *chan)
+{
+        return test_bit(3, &status);
+}
+
+static inline int
+iop_is_err_pci_tabort(unsigned long status, struct iop_adma_chan *chan)
+{
+        return 0;
+}
+
+static inline int
+iop_is_err_pci_mabort(unsigned long status, struct iop_adma_chan *chan)
+{
+        return 0;
+}
+
+static inline int
+iop_is_err_split_tx(unsigned long status, struct iop_adma_chan *chan)
+{
+        return 0;
+}
+
+#endif /* _ADMA_H */
diff --git a/arch/arm/mach-iop13xx/include/mach/debug-macro.S b/arch/arm/mach-iop13xx/include/mach/debug-macro.S
new file mode 100644
index 000000000000..9037d2e8557c
--- /dev/null
+++ b/arch/arm/mach-iop13xx/include/mach/debug-macro.S
@@ -0,0 +1,26 @@
+/*
+ * arch/arm/mach-iop13xx/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ * Copyright (C) 1994-1999 Russell King
+ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+        .macro  addruart, rx
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1                 @ mmu enabled?
+        moveq   \rx, #0xff000000        @ physical
+        orreq   \rx, \rx, #0x00d80000
+        movne   \rx, #0xfe000000        @ virtual
+        orrne   \rx, \rx, #0x00e80000
+        orr     \rx, \rx, #0x00002300
+        orr     \rx, \rx, #0x00000040
+        .endm
+
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-iop13xx/dma.h b/arch/arm/mach-iop13xx/include/mach/dma.h
index d79846fbb394..d79846fbb394 100644
--- a/include/asm-arm/arch-iop13xx/dma.h
+++ b/arch/arm/mach-iop13xx/include/mach/dma.h
diff --git a/include/asm-arm/arch-iop13xx/entry-macro.S b/arch/arm/mach-iop13xx/include/mach/entry-macro.S
index a624a7870c64..a624a7870c64 100644
--- a/include/asm-arm/arch-iop13xx/entry-macro.S
+++ b/arch/arm/mach-iop13xx/include/mach/entry-macro.S
diff --git a/include/asm-arm/arch-iop13xx/hardware.h b/arch/arm/mach-iop13xx/include/mach/hardware.h
index 8e1d56289846..8e1d56289846 100644
--- a/include/asm-arm/arch-iop13xx/hardware.h
+++ b/arch/arm/mach-iop13xx/include/mach/hardware.h
diff --git a/include/asm-arm/arch-iop13xx/io.h b/arch/arm/mach-iop13xx/include/mach/io.h
index a6e0f9e6ddcf..a6e0f9e6ddcf 100644
--- a/include/asm-arm/arch-iop13xx/io.h
+++ b/arch/arm/mach-iop13xx/include/mach/io.h
diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
index 52b7fab7ef60..52b7fab7ef60 100644
--- a/include/asm-arm/arch-iop13xx/iop13xx.h
+++ b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
diff --git a/include/asm-arm/arch-iop13xx/iq81340.h b/arch/arm/mach-iop13xx/include/mach/iq81340.h
index ba2cf931e9ce..ba2cf931e9ce 100644
--- a/include/asm-arm/arch-iop13xx/iq81340.h
+++ b/arch/arm/mach-iop13xx/include/mach/iq81340.h
diff --git a/include/asm-arm/arch-iop13xx/irqs.h b/arch/arm/mach-iop13xx/include/mach/irqs.h
index 054e7acb5bfa..054e7acb5bfa 100644
--- a/include/asm-arm/arch-iop13xx/irqs.h
+++ b/arch/arm/mach-iop13xx/include/mach/irqs.h
diff --git a/arch/arm/mach-iop13xx/include/mach/memory.h b/arch/arm/mach-iop13xx/include/mach/memory.h
new file mode 100644
index 000000000000..e8b59d8f1bb9
--- /dev/null
+++ b/arch/arm/mach-iop13xx/include/mach/memory.h
@@ -0,0 +1,64 @@
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#include <mach/hardware.h>
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     UL(0x00000000)
+#define TASK_SIZE       UL(0x3f000000)
+#define PAGE_OFFSET     UL(0x40000000)
+#define TASK_UNMAPPED_BASE ((TASK_SIZE + 0x01000000) / 3)
+
+#ifndef __ASSEMBLY__
+
+#if defined(CONFIG_ARCH_IOP13XX)
+#define IOP13XX_PMMR_V_START (IOP13XX_PMMR_VIRT_MEM_BASE)
+#define IOP13XX_PMMR_V_END   (IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_SIZE)
+#define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE)
+#define IOP13XX_PMMR_P_END   (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE)
+
+/*
+ * Virtual view <-> PCI DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+
+/* RAM has 1:1 mapping on the PCIe/x Busses */
+#define __virt_to_bus(x)        (__virt_to_phys(x))
+#define __bus_to_virt(x)    (__phys_to_virt(x))
+
+#define virt_to_lbus(x)                                            \
+(( ((void*)(x) >= (void*)IOP13XX_PMMR_V_START) &&                  \
+((void*)(x) < (void*)IOP13XX_PMMR_V_END) ) ?                       \
+((x) - IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_PHYS_MEM_BASE) : \
+((x) - PAGE_OFFSET + PHYS_OFFSET))
+
+#define lbus_to_virt(x)                                            \
+(( ((x) >= IOP13XX_PMMR_P_START) && ((x) < IOP13XX_PMMR_P_END) ) ? \
+((x) - IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_VIRT_MEM_BASE ) : \
+((x) - PHYS_OFFSET + PAGE_OFFSET))
+
+/* Device is an lbus device if it is on the platform bus of the IOP13XX */
+#define is_lbus_device(dev) (dev &&\
+                             (strncmp(dev->bus->name, "platform", 8) == 0))
+
+#define __arch_page_to_dma(dev, page)                                   \
+({is_lbus_device(dev) ? (dma_addr_t)virt_to_lbus(page_address(page)) : \
+(dma_addr_t)__virt_to_bus(page_address(page));})
+
+#define __arch_dma_to_virt(dev, addr) \
+({is_lbus_device(dev) ? lbus_to_virt(addr) : __bus_to_virt(addr);})
+
+#define __arch_virt_to_dma(dev, addr) \
+({is_lbus_device(dev) ? virt_to_lbus(addr) : __virt_to_bus(addr);})
+
+#endif /* CONFIG_ARCH_IOP13XX */
+#endif /* !ASSEMBLY */
+
+#define PFN_TO_NID(addr)        (0)
+
+#endif
diff --git a/include/asm-arm/arch-iop13xx/msi.h b/arch/arm/mach-iop13xx/include/mach/msi.h
index b80c5ae17e99..b80c5ae17e99 100644
--- a/include/asm-arm/arch-iop13xx/msi.h
+++ b/arch/arm/mach-iop13xx/include/mach/msi.h
diff --git a/arch/arm/mach-iop13xx/include/mach/pci.h b/arch/arm/mach-iop13xx/include/mach/pci.h
new file mode 100644
index 000000000000..17b5515af8b1
--- /dev/null
+++ b/arch/arm/mach-iop13xx/include/mach/pci.h
@@ -0,0 +1,57 @@
+#ifndef _IOP13XX_PCI_H_
+#define _IOP13XX_PCI_H_
+#include <mach/irqs.h>
+#include <asm/io.h>
+
+struct pci_sys_data;
+struct hw_pci;
+int iop13xx_pci_setup(int nr, struct pci_sys_data *sys);
+struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *);
+void iop13xx_atu_select(struct hw_pci *plat_pci);
+void iop13xx_pci_init(void);
+void iop13xx_map_pci_memory(void);
+
+#define IOP_PCI_STATUS_ERROR (PCI_STATUS_PARITY |            \
+                               PCI_STATUS_SIG_TARGET_ABORT | \
+                               PCI_STATUS_REC_TARGET_ABORT | \
+                               PCI_STATUS_REC_TARGET_ABORT | \
+                               PCI_STATUS_REC_MASTER_ABORT | \
+                               PCI_STATUS_SIG_SYSTEM_ERROR | \
+                               PCI_STATUS_DETECTED_PARITY)
+
+#define IOP13XX_ATUE_ATUISR_ERROR (IOP13XX_ATUE_STAT_HALT_ON_ERROR |  \
+                                    IOP13XX_ATUE_STAT_ROOT_SYS_ERR |   \
+                                    IOP13XX_ATUE_STAT_PCI_IFACE_ERR |  \
+                                    IOP13XX_ATUE_STAT_ERR_COR |        \
+                                    IOP13XX_ATUE_STAT_ERR_UNCOR |      \
+                                    IOP13XX_ATUE_STAT_CRS |            \
+                                    IOP13XX_ATUE_STAT_DET_PAR_ERR |    \
+                                    IOP13XX_ATUE_STAT_EXT_REC_MABORT | \
+                                    IOP13XX_ATUE_STAT_SIG_TABORT |     \
+                                    IOP13XX_ATUE_STAT_EXT_REC_TABORT | \
+                                    IOP13XX_ATUE_STAT_MASTER_DATA_PAR)
+
+#define IOP13XX_ATUX_ATUISR_ERROR (IOP13XX_ATUX_STAT_TX_SCEM |        \
+                                    IOP13XX_ATUX_STAT_REC_SCEM |       \
+                                    IOP13XX_ATUX_STAT_TX_SERR |        \
+                                    IOP13XX_ATUX_STAT_DET_PAR_ERR |    \
+                                    IOP13XX_ATUX_STAT_INT_REC_MABORT | \
+                                    IOP13XX_ATUX_STAT_REC_SERR |       \
+                                    IOP13XX_ATUX_STAT_EXT_REC_MABORT | \
+                                    IOP13XX_ATUX_STAT_EXT_REC_TABORT | \
+                                    IOP13XX_ATUX_STAT_EXT_SIG_TABORT | \
+                                    IOP13XX_ATUX_STAT_MASTER_DATA_PAR)
+
+/* PCI interrupts
+ */
+#define ATUX_INTA IRQ_IOP13XX_XINT0
+#define ATUX_INTB IRQ_IOP13XX_XINT1
+#define ATUX_INTC IRQ_IOP13XX_XINT2
+#define ATUX_INTD IRQ_IOP13XX_XINT3
+
+#define ATUE_INTA IRQ_IOP13XX_ATUE_IMA
+#define ATUE_INTB IRQ_IOP13XX_ATUE_IMB
+#define ATUE_INTC IRQ_IOP13XX_ATUE_IMC
+#define ATUE_INTD IRQ_IOP13XX_ATUE_IMD
+
+#endif /* _IOP13XX_PCI_H_ */
diff --git a/arch/arm/mach-iop13xx/include/mach/system.h b/arch/arm/mach-iop13xx/include/mach/system.h
new file mode 100644
index 000000000000..c7127f416e1f
--- /dev/null
+++ b/arch/arm/mach-iop13xx/include/mach/system.h
@@ -0,0 +1,27 @@
+/*
+ * arch/arm/mach-iop13xx/include/mach/system.h
+ *
+ *  Copyright (C) 2004 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <mach/iop13xx.h>
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        /*
+         * Reset the internal bus (warning both cores are reset)
+         */
+        write_wdtcr(IOP_WDTCR_EN_ARM);
+        write_wdtcr(IOP_WDTCR_EN);
+        write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
+        write_wdtcr(0x1000);
+
+        for(;;);
+}
diff --git a/include/asm-arm/arch-iop13xx/time.h b/arch/arm/mach-iop13xx/include/mach/time.h
index 49213d9d7cad..49213d9d7cad 100644
--- a/include/asm-arm/arch-iop13xx/time.h
+++ b/arch/arm/mach-iop13xx/include/mach/time.h
diff --git a/arch/arm/mach-iop13xx/include/mach/timex.h b/arch/arm/mach-iop13xx/include/mach/timex.h
new file mode 100644
index 000000000000..5b1f1c8a8270
--- /dev/null
+++ b/arch/arm/mach-iop13xx/include/mach/timex.h
@@ -0,0 +1,3 @@
+#include <mach/hardware.h>
+
+#define CLOCK_TICK_RATE (100 * HZ)
diff --git a/arch/arm/mach-iop13xx/include/mach/uncompress.h b/arch/arm/mach-iop13xx/include/mach/uncompress.h
new file mode 100644
index 000000000000..fa4f80522fad
--- /dev/null
+++ b/arch/arm/mach-iop13xx/include/mach/uncompress.h
@@ -0,0 +1,23 @@
+#include <asm/types.h>
+#include <linux/serial_reg.h>
+#include <mach/hardware.h>
+
+#define UART_BASE ((volatile u32 *)IOP13XX_UART1_PHYS)
+#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
+
+static inline void putc(char c)
+{
+        while ((UART_BASE[UART_LSR] & TX_DONE) != TX_DONE)
+                barrier();
+        UART_BASE[UART_TX] = c;
+}
+
+static inline void flush(void)
+{
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-iop13xx/vmalloc.h b/arch/arm/mach-iop13xx/include/mach/vmalloc.h
index c53456740345..c53456740345 100644
--- a/include/asm-arm/arch-iop13xx/vmalloc.h
+++ b/arch/arm/mach-iop13xx/include/mach/vmalloc.h
diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c
index 44b8c8c14105..26cfa318142c 100644
--- a/arch/arm/mach-iop13xx/io.c
+++ b/arch/arm/mach-iop13xx/io.c
@@ -18,7 +18,7 @@
  */
 #include <linux/kernel.h>
 #include <linux/module.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 
 void * __iomem __iop13xx_io(unsigned long io_addr)
diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c
index e17457e8e919..5051c03d437c 100644
--- a/arch/arm/mach-iop13xx/iq81340mc.c
+++ b/arch/arm/mach-iop13xx/iq81340mc.c
@@ -18,14 +18,14 @@
  */
 #include <linux/pci.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach/pci.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/arch/pci.h>
+#include <mach/pci.h>
 #include <asm/mach/time.h>
-#include <asm/arch/time.h>
+#include <mach/time.h>
 
 extern int init_atu; /* Flag to select which ATU(s) to initialize / disable */
 
diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c
index 19204d8f8109..bc443073a8e3 100644
--- a/arch/arm/mach-iop13xx/iq81340sc.c
+++ b/arch/arm/mach-iop13xx/iq81340sc.c
@@ -18,14 +18,14 @@
  */
 #include <linux/pci.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach/pci.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/arch/pci.h>
+#include <mach/pci.h>
 #include <asm/mach/time.h>
-#include <asm/arch/time.h>
+#include <mach/time.h>
 
 extern int init_atu;
 
diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c
index e860a6d22dee..0d099ca87bdf 100644
--- a/arch/arm/mach-iop13xx/irq.c
+++ b/arch/arm/mach-iop13xx/irq.c
@@ -23,9 +23,9 @@
 #include <asm/uaccess.h>
 #include <asm/mach/irq.h>
 #include <asm/irq.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/irqs.h>
-#include <asm/arch/msi.h>
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+#include <mach/msi.h>
 
 /* INTCTL0 CP6 R0 Page 4
  */
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index a0e0147f24f8..673b0db22034 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -21,11 +21,11 @@
 #include <linux/delay.h>
 #include <linux/jiffies.h>
 #include <asm/irq.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/sizes.h>
 #include <asm/signal.h>
 #include <asm/mach/pci.h>
-#include <asm/arch/pci.h>
+#include <mach/pci.h>
 
 #define IOP13XX_PCI_DEBUG 0
 #define PRINTK(x...) ((void)(IOP13XX_PCI_DEBUG && printk(x)))
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c
index d3fee8a11b62..b17ccc8cb471 100644
--- a/arch/arm/mach-iop13xx/setup.c
+++ b/arch/arm/mach-iop13xx/setup.c
@@ -22,7 +22,7 @@
 #include <linux/mtd/physmap.h>
 #endif
 #include <asm/mach/map.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/io.h>
 #include <asm/hardware/iop_adma.h>
diff --git a/arch/arm/mach-iop32x/em7210.c b/arch/arm/mach-iop32x/em7210.c
index 9941395a5d00..3ad4696ade42 100644
--- a/arch/arm/mach-iop32x/em7210.c
+++ b/arch/arm/mach-iop32x/em7210.c
@@ -23,7 +23,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
 #include <linux/i2c.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <asm/mach/arch.h>
@@ -31,7 +31,7 @@
 #include <asm/mach/pci.h>
 #include <asm/mach/time.h>
 #include <asm/mach-types.h>
-#include <asm/arch/time.h>
+#include <mach/time.h>
 
 static void __init em7210_timer_init(void)
 {
diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c
index 8761445ed040..45d61276d233 100644
--- a/arch/arm/mach-iop32x/glantank.c
+++ b/arch/arm/mach-iop32x/glantank.c
@@ -25,7 +25,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/i2c.h>
 #include <linux/platform_device.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
@@ -34,7 +34,7 @@
 #include <asm/mach/time.h>
 #include <asm/mach-types.h>
 #include <asm/page.h>
-#include <asm/arch/time.h>
+#include <mach/time.h>
 
 /*
  * GLAN Tank timer tick configuration.
diff --git a/include/asm-arm/arch-iop32x/adma.h b/arch/arm/mach-iop32x/include/mach/adma.h
index 5ed92037dd10..5ed92037dd10 100644
--- a/include/asm-arm/arch-iop32x/adma.h
+++ b/arch/arm/mach-iop32x/include/mach/adma.h
diff --git a/arch/arm/mach-iop32x/include/mach/debug-macro.S b/arch/arm/mach-iop32x/include/mach/debug-macro.S
new file mode 100644
index 000000000000..58b01664ffba
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/debug-macro.S
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/mach-iop32x/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ * Copyright (C) 1994-1999 Russell King
+ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+                .macro  addruart, rx
+                mov     \rx, #0xfe000000        @ physical as well as virtual
+                orr     \rx, \rx, #0x00800000   @ location of the UART
+                .endm
+
+#define UART_SHIFT      0
+#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-iop32x/include/mach/dma.h b/arch/arm/mach-iop32x/include/mach/dma.h
new file mode 100644
index 000000000000..f8bd817f205d
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/dma.h
@@ -0,0 +1,9 @@
+/*
+ * arch/arm/mach-iop32x/include/mach/dma.h
+ *
+ * Copyright (C) 2004 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
diff --git a/arch/arm/mach-iop32x/include/mach/entry-macro.S b/arch/arm/mach-iop32x/include/mach/entry-macro.S
new file mode 100644
index 000000000000..b02fb56bafcc
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/entry-macro.S
@@ -0,0 +1,36 @@
+/*
+ * arch/arm/mach-iop32x/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for IOP32x-based platforms
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <mach/iop32x.h>
+
+        .macro  disable_fiq
+        .endm
+
+        .macro get_irqnr_preamble, base, tmp
+        mrc     p15, 0, \tmp, c15, c1, 0
+        orr     \tmp, \tmp, #(1 << 6)
+        mcr     p15, 0, \tmp, c15, c1, 0        @ Enable cp6 access
+        mrc     p15, 0, \tmp, c15, c1, 0
+        mov     \tmp, \tmp
+        sub     pc, pc, #4                      @ cp_wait
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        mrc     p6, 0, \irqstat, c8, c0, 0      @ Read IINTSRC
+        cmp     \irqstat, #0
+        clzne   \irqnr, \irqstat
+        rsbne   \irqnr, \irqnr, #31
+        .endm
+
+        .macro arch_ret_to_user, tmp1, tmp2
+        mrc     p15, 0, \tmp1, c15, c1, 0
+        ands    \tmp2, \tmp1, #(1 << 6)
+        bicne   \tmp1, \tmp1, #(1 << 6)
+        mcrne   p15, 0, \tmp1, c15, c1, 0       @ Disable cp6 access
+        .endm
diff --git a/arch/arm/mach-iop32x/include/mach/glantank.h b/arch/arm/mach-iop32x/include/mach/glantank.h
new file mode 100644
index 000000000000..958eb91c0913
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/glantank.h
@@ -0,0 +1,13 @@
+/*
+ * arch/arm/mach-iop32x/include/mach/glantank.h
+ *
+ * IO-Data GLAN Tank board registers
+ */
+
+#ifndef __GLANTANK_H
+#define __GLANTANK_H
+
+#define GLANTANK_UART           0xfe800000      /* UART */
+
+
+#endif
diff --git a/include/asm-arm/arch-iop32x/gpio.h b/arch/arm/mach-iop32x/include/mach/gpio.h
index 708f4ec9db1d..708f4ec9db1d 100644
--- a/include/asm-arm/arch-iop32x/gpio.h
+++ b/arch/arm/mach-iop32x/include/mach/gpio.h
diff --git a/arch/arm/mach-iop32x/include/mach/hardware.h b/arch/arm/mach-iop32x/include/mach/hardware.h
new file mode 100644
index 000000000000..d559c4e6095a
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/hardware.h
@@ -0,0 +1,44 @@
+/*
+ * arch/arm/mach-iop32x/include/mach/hardware.h
+ */
+
+#ifndef __HARDWARE_H
+#define __HARDWARE_H
+
+#include <asm/types.h>
+
+/*
+ * Note about PCI IO space mappings
+ *
+ * To make IO space accesses efficient, we store virtual addresses in
+ * the IO resources.
+ *
+ * The PCI IO space is located at virtual 0xfe000000 from physical
+ * 0x90000000. The PCI BARs must be programmed with physical addresses,
+ * but when we read them, we convert them to virtual addresses. See
+ * arch/arm/plat-iop/pci.c.
+ */
+#define pcibios_assign_all_busses() 1
+#define PCIBIOS_MIN_IO          0x00000000
+#define PCIBIOS_MIN_MEM         0x00000000
+
+#ifndef __ASSEMBLY__
+void iop32x_init_irq(void);
+#endif
+
+
+/*
+ * Generic chipset bits
+ */
+#include "iop32x.h"
+
+/*
+ * Board specific bits
+ */
+#include "glantank.h"
+#include "iq80321.h"
+#include "iq31244.h"
+#include "n2100.h"
+
+
+#endif
diff --git a/arch/arm/mach-iop32x/include/mach/io.h b/arch/arm/mach-iop32x/include/mach/io.h
new file mode 100644
index 000000000000..ce54705ba3d4
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/io.h
@@ -0,0 +1,27 @@
+/*
+ * arch/arm/mach-iop32x/include/mach/io.h
+ *
+ * Copyright (C) 2001 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __IO_H
+#define __IO_H
+
+#include <mach/hardware.h>
+
+extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size,
+        unsigned int mtype);
+extern void __iop3xx_iounmap(void __iomem *addr);
+
+#define IO_SPACE_LIMIT          0xffffffff
+#define __io(p)         ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
+#define __mem_pci(a)            (a)
+
+#define __arch_ioremap(a, s, f) __iop3xx_ioremap(a, s, f)
+#define __arch_iounmap(a)        __iop3xx_iounmap(a)
+
+#endif
diff --git a/arch/arm/mach-iop32x/include/mach/iop32x.h b/arch/arm/mach-iop32x/include/mach/iop32x.h
new file mode 100644
index 000000000000..abd9eb49f103
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/iop32x.h
@@ -0,0 +1,37 @@
+/*
+ * arch/arm/mach-iop32x/include/mach/iop32x.h
+ *
+ * Intel IOP32X Chip definitions
+ *
+ * Author: Rory Bolt <rorybolt@pacbell.net>
+ * Copyright (C) 2002 Rory Bolt
+ * Copyright (C) 2004 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __IOP32X_H
+#define __IOP32X_H
+
+/*
+ * Peripherals that are shared between the iop32x and iop33x but
+ * located at different addresses.
+ */
+#define IOP3XX_GPIO_REG(reg)    (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07c4 + (reg))
+#define IOP3XX_TIMER_REG(reg)   (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg))
+
+#include <asm/hardware/iop3xx.h>
+
+/* ATU Parameters
+ * set up a 1:1 bus to physical ram relationship
+ * w/ physical ram on top of pci in the memory map
+ */
+#define IOP32X_MAX_RAM_SIZE            0x40000000UL
+#define IOP3XX_MAX_RAM_SIZE            IOP32X_MAX_RAM_SIZE
+#define IOP3XX_PCI_LOWER_MEM_BA        0x80000000
+#define IOP32X_PCI_MEM_WINDOW_SIZE     0x04000000
+#define IOP3XX_PCI_MEM_WINDOW_SIZE     IOP32X_PCI_MEM_WINDOW_SIZE
+
+#endif
diff --git a/arch/arm/mach-iop32x/include/mach/iq31244.h b/arch/arm/mach-iop32x/include/mach/iq31244.h
new file mode 100644
index 000000000000..6b6b369e781c
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/iq31244.h
@@ -0,0 +1,17 @@
+/*
+ * arch/arm/mach-iop32x/include/mach/iq31244.h
+ *
+ * Intel IQ31244 evaluation board registers
+ */
+
+#ifndef __IQ31244_H
+#define __IQ31244_H
+
+#define IQ31244_UART            0xfe800000      /* UART #1 */
+#define IQ31244_7SEG_1          0xfe840000      /* 7-Segment MSB */
+#define IQ31244_7SEG_0          0xfe850000      /* 7-Segment LSB (WO) */
+#define IQ31244_ROTARY_SW       0xfe8d0000      /* Rotary Switch */
+#define IQ31244_BATT_STAT       0xfe8f0000      /* Battery Status */
+
+
+#endif
diff --git a/arch/arm/mach-iop32x/include/mach/iq80321.h b/arch/arm/mach-iop32x/include/mach/iq80321.h
new file mode 100644
index 000000000000..498819b737e7
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/iq80321.h
@@ -0,0 +1,17 @@
+/*
+ * arch/arm/mach-iop32x/include/mach/iq80321.h
+ *
+ * Intel IQ80321 evaluation board registers
+ */
+
+#ifndef __IQ80321_H
+#define __IQ80321_H
+
+#define IQ80321_UART            0xfe800000      /* UART #1 */
+#define IQ80321_7SEG_1          0xfe840000      /* 7-Segment MSB */
+#define IQ80321_7SEG_0          0xfe850000      /* 7-Segment LSB (WO) */
+#define IQ80321_ROTARY_SW       0xfe8d0000      /* Rotary Switch */
+#define IQ80321_BATT_STAT       0xfe8f0000      /* Battery Status */
+
+
+#endif
diff --git a/arch/arm/mach-iop32x/include/mach/irqs.h b/arch/arm/mach-iop32x/include/mach/irqs.h
new file mode 100644
index 000000000000..33573e09914c
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/irqs.h
@@ -0,0 +1,50 @@
+/*
+ * arch/arm/mach-iop32x/include/mach/irqs.h
+ *
+ * Author:      Rory Bolt <rorybolt@pacbell.net>
+ * Copyright:   (C) 2002 Rory Bolt
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __IRQS_H
+#define __IRQS_H
+
+/*
+ * IOP80321 chipset interrupts
+ */
+#define IRQ_IOP32X_DMA0_EOT     0
+#define IRQ_IOP32X_DMA0_EOC     1
+#define IRQ_IOP32X_DMA1_EOT     2
+#define IRQ_IOP32X_DMA1_EOC     3
+#define IRQ_IOP32X_AA_EOT       6
+#define IRQ_IOP32X_AA_EOC       7
+#define IRQ_IOP32X_CORE_PMON    8
+#define IRQ_IOP32X_TIMER0       9
+#define IRQ_IOP32X_TIMER1       10
+#define IRQ_IOP32X_I2C_0        11
+#define IRQ_IOP32X_I2C_1        12
+#define IRQ_IOP32X_MESSAGING    13
+#define IRQ_IOP32X_ATU_BIST     14
+#define IRQ_IOP32X_PERFMON      15
+#define IRQ_IOP32X_CORE_PMU     16
+#define IRQ_IOP32X_BIU_ERR      17
+#define IRQ_IOP32X_ATU_ERR      18
+#define IRQ_IOP32X_MCU_ERR      19
+#define IRQ_IOP32X_DMA0_ERR     20
+#define IRQ_IOP32X_DMA1_ERR     21
+#define IRQ_IOP32X_AA_ERR       23
+#define IRQ_IOP32X_MSG_ERR      24
+#define IRQ_IOP32X_SSP          25
+#define IRQ_IOP32X_XINT0        27
+#define IRQ_IOP32X_XINT1        28
+#define IRQ_IOP32X_XINT2        29
+#define IRQ_IOP32X_XINT3        30
+#define IRQ_IOP32X_HPI          31
+
+#define NR_IRQS                 32
+
+
+#endif
diff --git a/arch/arm/mach-iop32x/include/mach/memory.h b/arch/arm/mach-iop32x/include/mach/memory.h
new file mode 100644
index 000000000000..42cd4bf3148c
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/memory.h
@@ -0,0 +1,26 @@
+/*
+ * arch/arm/mach-iop32x/include/mach/memory.h
+ */
+
+#ifndef __MEMORY_H
+#define __MEMORY_H
+
+#include <mach/hardware.h>
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     UL(0xa0000000)
+
+/*
+ * Virtual view <-> PCI DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+#define __virt_to_bus(x)        (__virt_to_phys(x))
+#define __bus_to_virt(x)        (__phys_to_virt(x))
+
+
+#endif
diff --git a/arch/arm/mach-iop32x/include/mach/n2100.h b/arch/arm/mach-iop32x/include/mach/n2100.h
new file mode 100644
index 000000000000..40b8a532b064
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/n2100.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-iop32x/include/mach/n2100.h
+ *
+ * Thecus N2100 board registers
+ */
+
+#ifndef __N2100_H
+#define __N2100_H
+
+#define N2100_UART              0xfe800000      /* UART */
+
+#define N2100_COPY_BUTTON       IOP3XX_GPIO_LINE(0)
+#define N2100_PCA9532_RESET     IOP3XX_GPIO_LINE(2)
+#define N2100_RESET_BUTTON      IOP3XX_GPIO_LINE(3)
+#define N2100_HARDWARE_RESET    IOP3XX_GPIO_LINE(4)
+#define N2100_POWER_BUTTON      IOP3XX_GPIO_LINE(5)
+
+
+#endif
diff --git a/arch/arm/mach-iop32x/include/mach/system.h b/arch/arm/mach-iop32x/include/mach/system.h
new file mode 100644
index 000000000000..20f923e54f46
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/system.h
@@ -0,0 +1,33 @@
+/*
+ * arch/arm/mach-iop32x/include/mach/system.h
+ *
+ * Copyright (C) 2001 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <asm/mach-types.h>
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        local_irq_disable();
+
+        if (machine_is_n2100()) {
+                gpio_line_set(N2100_HARDWARE_RESET, GPIO_LOW);
+                gpio_line_config(N2100_HARDWARE_RESET, GPIO_OUT);
+                while (1)
+                        ;
+        }
+
+        *IOP3XX_PCSR = 0x30;
+
+        /* Jump into ROM at address 0 */
+        cpu_reset(0);
+}
diff --git a/include/asm-arm/arch-iop32x/time.h b/arch/arm/mach-iop32x/include/mach/time.h
index 0f28c9949623..0f28c9949623 100644
--- a/include/asm-arm/arch-iop32x/time.h
+++ b/arch/arm/mach-iop32x/include/mach/time.h
diff --git a/arch/arm/mach-iop32x/include/mach/timex.h b/arch/arm/mach-iop32x/include/mach/timex.h
new file mode 100644
index 000000000000..a541afced3cb
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/timex.h
@@ -0,0 +1,9 @@
+/*
+ * arch/arm/mach-iop32x/include/mach/timex.h
+ *
+ * IOP32x architecture timex specifications
+ */
+
+#include <mach/hardware.h>
+
+#define CLOCK_TICK_RATE         (100 * HZ)
diff --git a/arch/arm/mach-iop32x/include/mach/uncompress.h b/arch/arm/mach-iop32x/include/mach/uncompress.h
new file mode 100644
index 000000000000..b247551b6f5a
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/uncompress.h
@@ -0,0 +1,39 @@
+/*
+ * arch/arm/mach-iop32x/include/mach/uncompress.h
+ */
+
+#include <asm/types.h>
+#include <asm/mach-types.h>
+#include <linux/serial_reg.h>
+#include <mach/hardware.h>
+
+static volatile u8 *uart_base;
+
+#define TX_DONE         (UART_LSR_TEMT | UART_LSR_THRE)
+
+static inline void putc(char c)
+{
+        while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
+                barrier();
+        uart_base[UART_TX] = c;
+}
+
+static inline void flush(void)
+{
+}
+
+static __inline__ void __arch_decomp_setup(unsigned long arch_id)
+{
+        if (machine_is_iq80321())
+                uart_base = (volatile u8 *)IQ80321_UART;
+        else if (machine_is_iq31244() || machine_is_em7210())
+                uart_base = (volatile u8 *)IQ31244_UART;
+        else
+                uart_base = (volatile u8 *)0xfe800000;
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()     __arch_decomp_setup(arch_id)
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-iop32x/include/mach/vmalloc.h b/arch/arm/mach-iop32x/include/mach/vmalloc.h
new file mode 100644
index 000000000000..85ceb09d85f0
--- /dev/null
+++ b/arch/arm/mach-iop32x/include/mach/vmalloc.h
@@ -0,0 +1,5 @@
+/*
+ * arch/arm/mach-iop32x/include/mach/vmalloc.h
+ */
+
+#define VMALLOC_END     0xfe000000
diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c
index 5a4e951cad9e..082818aaa205 100644
--- a/arch/arm/mach-iop32x/iq31244.c
+++ b/arch/arm/mach-iop32x/iq31244.c
@@ -26,7 +26,7 @@
 #include <linux/serial_8250.h>
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
@@ -36,7 +36,7 @@
 #include <asm/mach-types.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
-#include <asm/arch/time.h>
+#include <mach/time.h>
 
 /*
  * Until March of 2007 iq31244 platforms and ep80219 platforms shared the
diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c
index 1c098c507c66..d735539808b4 100644
--- a/arch/arm/mach-iop32x/iq80321.c
+++ b/arch/arm/mach-iop32x/iq80321.c
@@ -23,7 +23,7 @@
 #include <linux/serial_8250.h>
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
@@ -33,7 +33,7 @@
 #include <asm/mach-types.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
-#include <asm/arch/time.h>
+#include <mach/time.h>
 
 /*
  * IQ80321 timer tick configuration.
diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c
index 2ea1e716296f..ba59b2d17db1 100644
--- a/arch/arm/mach-iop32x/irq.c
+++ b/arch/arm/mach-iop32x/irq.c
@@ -16,7 +16,7 @@
 #include <linux/list.h>
 #include <asm/mach/irq.h>
 #include <asm/irq.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 
 static u32 iop32x_mask;
diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c
index f38dc19bbcc9..3173f9c5835d 100644
--- a/arch/arm/mach-iop32x/n2100.c
+++ b/arch/arm/mach-iop32x/n2100.c
@@ -30,7 +30,7 @@
 #include <linux/i2c.h>
 #include <linux/platform_device.h>
 #include <linux/reboot.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
@@ -40,7 +40,7 @@
 #include <asm/mach-types.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
-#include <asm/arch/time.h>
+#include <mach/time.h>
 
 /*
  * N2100 timer tick configuration.
diff --git a/include/asm-arm/arch-iop33x/adma.h b/arch/arm/mach-iop33x/include/mach/adma.h
index 4b92f795f90e..4b92f795f90e 100644
--- a/include/asm-arm/arch-iop33x/adma.h
+++ b/arch/arm/mach-iop33x/include/mach/adma.h
diff --git a/arch/arm/mach-iop33x/include/mach/debug-macro.S b/arch/arm/mach-iop33x/include/mach/debug-macro.S
new file mode 100644
index 000000000000..a60c9ef05cc3
--- /dev/null
+++ b/arch/arm/mach-iop33x/include/mach/debug-macro.S
@@ -0,0 +1,24 @@
+/*
+ * arch/arm/mach-iop33x/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ * Copyright (C) 1994-1999 Russell King
+ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+                .macro  addruart, rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ mmu enabled?
+                moveq   \rx, #0xff000000        @ physical
+                movne   \rx, #0xfe000000        @ virtual
+                orr     \rx, \rx, #0x00ff0000
+                orr     \rx, \rx, #0x0000f700
+                .endm
+
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-iop33x/include/mach/dma.h b/arch/arm/mach-iop33x/include/mach/dma.h
new file mode 100644
index 000000000000..d8b42232931d
--- /dev/null
+++ b/arch/arm/mach-iop33x/include/mach/dma.h
@@ -0,0 +1,9 @@
+/*
+ * arch/arm/mach-iop33x/include/mach/dma.h
+ *
+ * Copyright (C) 2004 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
diff --git a/arch/arm/mach-iop33x/include/mach/entry-macro.S b/arch/arm/mach-iop33x/include/mach/entry-macro.S
new file mode 100644
index 000000000000..4e1f7282b354
--- /dev/null
+++ b/arch/arm/mach-iop33x/include/mach/entry-macro.S
@@ -0,0 +1,37 @@
+/*
+ * arch/arm/mach-iop33x/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for IOP33x-based platforms
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <mach/iop33x.h>
+
+        .macro  disable_fiq
+        .endm
+
+        .macro get_irqnr_preamble, base, tmp
+        mrc     p15, 0, \tmp, c15, c1, 0
+        orr     \tmp, \tmp, #(1 << 6)
+        mcr     p15, 0, \tmp, c15, c1, 0        @ Enable cp6 access
+        mrc     p15, 0, \tmp, c15, c1, 0
+        mov     \tmp, \tmp
+        sub     pc, pc, #4                      @ cp_wait
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        mrc     p6, 0, \irqstat, c14, c0, 0     @ Read IINTVEC
+        cmp     \irqstat, #0
+        mrceq   p6, 0, \irqstat, c14, c0, 0     @ erratum 63 workaround
+        adds    \irqnr, \irqstat, #1
+        movne   \irqnr, \irqstat, lsr #2
+        .endm
+
+        .macro arch_ret_to_user, tmp1, tmp2
+        mrc     p15, 0, \tmp1, c15, c1, 0
+        ands    \tmp2, \tmp1, #(1 << 6)
+        bicne   \tmp1, \tmp1, #(1 << 6)
+        mcrne   p15, 0, \tmp1, c15, c1, 0       @ Disable cp6 access
+        .endm
diff --git a/include/asm-arm/arch-iop33x/gpio.h b/arch/arm/mach-iop33x/include/mach/gpio.h
index ddd55bba9bb9..ddd55bba9bb9 100644
--- a/include/asm-arm/arch-iop33x/gpio.h
+++ b/arch/arm/mach-iop33x/include/mach/gpio.h
diff --git a/arch/arm/mach-iop33x/include/mach/hardware.h b/arch/arm/mach-iop33x/include/mach/hardware.h
new file mode 100644
index 000000000000..8c10e430655e
--- /dev/null
+++ b/arch/arm/mach-iop33x/include/mach/hardware.h
@@ -0,0 +1,46 @@
+/*
+ * arch/arm/mach-iop33x/include/mach/hardware.h
+ */
+
+#ifndef __HARDWARE_H
+#define __HARDWARE_H
+
+#include <asm/types.h>
+
+/*
+ * Note about PCI IO space mappings
+ *
+ * To make IO space accesses efficient, we store virtual addresses in
+ * the IO resources.
+ *
+ * The PCI IO space is located at virtual 0xfe000000 from physical
+ * 0x90000000.  The PCI BARs must be programmed with physical addresses,
+ * but when we read them, we convert them to virtual addresses.  See
+ * arch/arm/mach-iop3xx/iop3xx-pci.c
+ */
+#define pcibios_assign_all_busses()     1
+#define PCIBIOS_MIN_IO          0x00000000
+#define PCIBIOS_MIN_MEM         0x00000000
+
+#ifndef __ASSEMBLY__
+void iop33x_init_irq(void);
+
+extern struct platform_device iop33x_uart0_device;
+extern struct platform_device iop33x_uart1_device;
+#endif
+
+
+/*
+ * Generic chipset bits
+ *
+ */
+#include "iop33x.h"
+
+/*
+ * Board specific bits
+ */
+#include "iq80331.h"
+#include "iq80332.h"
+
+
+#endif
diff --git a/arch/arm/mach-iop33x/include/mach/io.h b/arch/arm/mach-iop33x/include/mach/io.h
new file mode 100644
index 000000000000..158874631217
--- /dev/null
+++ b/arch/arm/mach-iop33x/include/mach/io.h
@@ -0,0 +1,27 @@
+/*
+ * arch/arm/mach-iop33x/include/mach/io.h
+ *
+ * Copyright (C) 2001  MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __IO_H
+#define __IO_H
+
+#include <mach/hardware.h>
+
+extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size,
+        unsigned int mtype);
+extern void __iop3xx_iounmap(void __iomem *addr);
+
+#define IO_SPACE_LIMIT          0xffffffff
+#define __io(p)         ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
+#define __mem_pci(a)            (a)
+
+#define __arch_ioremap(a, s, f) __iop3xx_ioremap(a, s, f)
+#define __arch_iounmap(a)        __iop3xx_iounmap(a)
+
+#endif
diff --git a/arch/arm/mach-iop33x/include/mach/iop33x.h b/arch/arm/mach-iop33x/include/mach/iop33x.h
new file mode 100644
index 000000000000..24567316ec88
--- /dev/null
+++ b/arch/arm/mach-iop33x/include/mach/iop33x.h
@@ -0,0 +1,43 @@
+/*
+ * arch/arm/mach-iop33x/include/mach/iop33x.h
+ *
+ * Intel IOP33X Chip definitions
+ *
+ * Author: Dave Jiang (dave.jiang@intel.com)
+ * Copyright (C) 2003, 2004 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __IOP33X_H
+#define __IOP33X_H
+
+/*
+ * Peripherals that are shared between the iop32x and iop33x but
+ * located at different addresses.
+ */
+#define IOP3XX_GPIO_REG(reg)    (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1780 + (reg))
+#define IOP3XX_TIMER_REG(reg)   (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07d0 + (reg))
+
+#include <asm/hardware/iop3xx.h>
+
+/* UARTs  */
+#define IOP33X_UART0_PHYS       (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1700)
+#define IOP33X_UART0_VIRT       (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1700)
+#define IOP33X_UART1_PHYS       (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1740)
+#define IOP33X_UART1_VIRT       (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1740)
+
+/* ATU Parameters
+ * set up a 1:1 bus to physical ram relationship
+ * w/ pci on top of physical ram in memory map
+ */
+#define IOP33X_MAX_RAM_SIZE             0x80000000UL
+#define IOP3XX_MAX_RAM_SIZE             IOP33X_MAX_RAM_SIZE
+#define IOP3XX_PCI_LOWER_MEM_BA (PHYS_OFFSET + IOP33X_MAX_RAM_SIZE)
+#define IOP33X_PCI_MEM_WINDOW_SIZE      0x08000000
+#define IOP3XX_PCI_MEM_WINDOW_SIZE      IOP33X_PCI_MEM_WINDOW_SIZE
+
+
+#endif
diff --git a/arch/arm/mach-iop33x/include/mach/iq80331.h b/arch/arm/mach-iop33x/include/mach/iq80331.h
new file mode 100644
index 000000000000..fe406b0127f7
--- /dev/null
+++ b/arch/arm/mach-iop33x/include/mach/iq80331.h
@@ -0,0 +1,16 @@
+/*
+ * arch/arm/mach-iop33x/include/mach/iq80331.h
+ *
+ * Intel IQ80331 evaluation board registers
+ */
+
+#ifndef __IQ80331_H
+#define __IQ80331_H
+
+#define IQ80331_7SEG_1          0xce840000      /* 7-Segment MSB */
+#define IQ80331_7SEG_0          0xce850000      /* 7-Segment LSB (WO) */
+#define IQ80331_ROTARY_SW       0xce8d0000      /* Rotary Switch */
+#define IQ80331_BATT_STAT       0xce8f0000      /* Battery Status */
+
+
+#endif
diff --git a/arch/arm/mach-iop33x/include/mach/iq80332.h b/arch/arm/mach-iop33x/include/mach/iq80332.h
new file mode 100644
index 000000000000..8325d71f2ed5
--- /dev/null
+++ b/arch/arm/mach-iop33x/include/mach/iq80332.h
@@ -0,0 +1,16 @@
+/*
+ * arch/arm/mach-iop33x/include/mach/iq80332.h
+ *
+ * Intel IQ80332 evaluation board registers
+ */
+
+#ifndef __IQ80332_H
+#define __IQ80332_H
+
+#define IQ80332_7SEG_1          0xce840000      /* 7-Segment MSB */
+#define IQ80332_7SEG_0          0xce850000      /* 7-Segment LSB (WO) */
+#define IQ80332_ROTARY_SW       0xce8d0000      /* Rotary Switch */
+#define IQ80332_BATT_STAT       0xce8f0000      /* Battery Status */
+
+
+#endif
diff --git a/arch/arm/mach-iop33x/include/mach/irqs.h b/arch/arm/mach-iop33x/include/mach/irqs.h
new file mode 100644
index 000000000000..707628a600ac
--- /dev/null
+++ b/arch/arm/mach-iop33x/include/mach/irqs.h
@@ -0,0 +1,60 @@
+/*
+ * arch/arm/mach-iop33x/include/mach/irqs.h
+ *
+ * Author:      Dave Jiang (dave.jiang@intel.com)
+ * Copyright:   (C) 2003 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __IRQS_H
+#define __IRQS_H
+
+/*
+ * IOP80331 chipset interrupts
+ */
+#define IRQ_IOP33X_DMA0_EOT     0
+#define IRQ_IOP33X_DMA0_EOC     1
+#define IRQ_IOP33X_DMA1_EOT     2
+#define IRQ_IOP33X_DMA1_EOC     3
+#define IRQ_IOP33X_AA_EOT       6
+#define IRQ_IOP33X_AA_EOC       7
+#define IRQ_IOP33X_TIMER0       8
+#define IRQ_IOP33X_TIMER1       9
+#define IRQ_IOP33X_I2C_0        10
+#define IRQ_IOP33X_I2C_1        11
+#define IRQ_IOP33X_MSG          12
+#define IRQ_IOP33X_MSGIBQ       13
+#define IRQ_IOP33X_ATU_BIST     14
+#define IRQ_IOP33X_PERFMON      15
+#define IRQ_IOP33X_CORE_PMU     16
+#define IRQ_IOP33X_XINT0        24
+#define IRQ_IOP33X_XINT1        25
+#define IRQ_IOP33X_XINT2        26
+#define IRQ_IOP33X_XINT3        27
+#define IRQ_IOP33X_XINT8        32
+#define IRQ_IOP33X_XINT9        33
+#define IRQ_IOP33X_XINT10       34
+#define IRQ_IOP33X_XINT11       35
+#define IRQ_IOP33X_XINT12       36
+#define IRQ_IOP33X_XINT13       37
+#define IRQ_IOP33X_XINT14       38
+#define IRQ_IOP33X_XINT15       39
+#define IRQ_IOP33X_UART0        51
+#define IRQ_IOP33X_UART1        52
+#define IRQ_IOP33X_PBIE         53
+#define IRQ_IOP33X_ATU_CRW      54
+#define IRQ_IOP33X_ATU_ERR      55
+#define IRQ_IOP33X_MCU_ERR      56
+#define IRQ_IOP33X_DMA0_ERR     57
+#define IRQ_IOP33X_DMA1_ERR     58
+#define IRQ_IOP33X_AA_ERR       60
+#define IRQ_IOP33X_MSG_ERR      62
+#define IRQ_IOP33X_HPI          63
+
+#define NR_IRQS                 64
+
+
+#endif
diff --git a/arch/arm/mach-iop33x/include/mach/memory.h b/arch/arm/mach-iop33x/include/mach/memory.h
new file mode 100644
index 000000000000..2cef0bbb354f
--- /dev/null
+++ b/arch/arm/mach-iop33x/include/mach/memory.h
@@ -0,0 +1,26 @@
+/*
+ * arch/arm/mach-iop33x/include/mach/memory.h
+ */
+
+#ifndef __MEMORY_H
+#define __MEMORY_H
+
+#include <mach/hardware.h>
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     UL(0x00000000)
+
+/*
+ * Virtual view <-> PCI DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+#define __virt_to_bus(x)        (__virt_to_phys(x))
+#define __bus_to_virt(x)        (__phys_to_virt(x))
+
+
+#endif
diff --git a/arch/arm/mach-iop33x/include/mach/system.h b/arch/arm/mach-iop33x/include/mach/system.h
new file mode 100644
index 000000000000..7bf3bfb49446
--- /dev/null
+++ b/arch/arm/mach-iop33x/include/mach/system.h
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/mach-iop33x/include/mach/system.h
+ *
+ * Copyright (C) 2001 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        *IOP3XX_PCSR = 0x30;
+
+        /* Jump into ROM at address 0 */
+        cpu_reset(0);
+}
diff --git a/include/asm-arm/arch-iop33x/time.h b/arch/arm/mach-iop33x/include/mach/time.h
index 4ac4d7664f85..4ac4d7664f85 100644
--- a/include/asm-arm/arch-iop33x/time.h
+++ b/arch/arm/mach-iop33x/include/mach/time.h
diff --git a/arch/arm/mach-iop33x/include/mach/timex.h b/arch/arm/mach-iop33x/include/mach/timex.h
new file mode 100644
index 000000000000..c75760844d49
--- /dev/null
+++ b/arch/arm/mach-iop33x/include/mach/timex.h
@@ -0,0 +1,9 @@
+/*
+ * arch/arm/mach-iop33x/include/mach/timex.h
+ *
+ * IOP3xx architecture timex specifications
+ */
+
+#include <mach/hardware.h>
+
+#define CLOCK_TICK_RATE         (100 * HZ)
diff --git a/arch/arm/mach-iop33x/include/mach/uncompress.h b/arch/arm/mach-iop33x/include/mach/uncompress.h
new file mode 100644
index 000000000000..b42423f63302
--- /dev/null
+++ b/arch/arm/mach-iop33x/include/mach/uncompress.h
@@ -0,0 +1,37 @@
+/*
+ * arch/arm/mach-iop33x/include/mach/uncompress.h
+ */
+
+#include <asm/types.h>
+#include <asm/mach-types.h>
+#include <linux/serial_reg.h>
+#include <mach/hardware.h>
+
+static volatile u32 *uart_base;
+
+#define TX_DONE         (UART_LSR_TEMT | UART_LSR_THRE)
+
+static inline void putc(char c)
+{
+        while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
+                barrier();
+        uart_base[UART_TX] = c;
+}
+
+static inline void flush(void)
+{
+}
+
+static __inline__ void __arch_decomp_setup(unsigned long arch_id)
+{
+        if (machine_is_iq80331() || machine_is_iq80332())
+                uart_base = (volatile u32 *)IOP33X_UART0_PHYS;
+        else
+                uart_base = (volatile u32 *)0xfe800000;
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()     __arch_decomp_setup(arch_id)
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-iop33x/include/mach/vmalloc.h b/arch/arm/mach-iop33x/include/mach/vmalloc.h
new file mode 100644
index 000000000000..f9f99dea9bc4
--- /dev/null
+++ b/arch/arm/mach-iop33x/include/mach/vmalloc.h
@@ -0,0 +1,5 @@
+/*
+ * arch/arm/mach-iop33x/include/mach/vmalloc.h
+ */
+
+#define VMALLOC_END     0xfe000000
diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c
index e736c50ed3dc..c7d99f9fafed 100644
--- a/arch/arm/mach-iop33x/iq80331.c
+++ b/arch/arm/mach-iop33x/iq80331.c
@@ -22,7 +22,7 @@
 #include <linux/serial_8250.h>
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
@@ -32,7 +32,7 @@
 #include <asm/mach-types.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
-#include <asm/arch/time.h>
+#include <mach/time.h>
 
 /*
  * IQ80331 timer tick configuration.
diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c
index 75347a23ceb1..af616c5f4fb2 100644
--- a/arch/arm/mach-iop33x/iq80332.c
+++ b/arch/arm/mach-iop33x/iq80332.c
@@ -22,7 +22,7 @@
 #include <linux/serial_8250.h>
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
@@ -32,7 +32,7 @@
 #include <asm/mach-types.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
-#include <asm/arch/time.h>
+#include <mach/time.h>
 
 /*
  * IQ80332 timer tick configuration.
diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c
index 6ae1fac6c61a..abb4ea2ed4fd 100644
--- a/arch/arm/mach-iop33x/irq.c
+++ b/arch/arm/mach-iop33x/irq.c
@@ -16,7 +16,7 @@
 #include <linux/list.h>
 #include <asm/mach/irq.h>
 #include <asm/irq.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 
 static u32 iop33x_mask0;
diff --git a/arch/arm/mach-iop33x/uart.c b/arch/arm/mach-iop33x/uart.c
index f11b86fc86c1..8c21870fa808 100644
--- a/arch/arm/mach-iop33x/uart.c
+++ b/arch/arm/mach-iop33x/uart.c
@@ -24,7 +24,7 @@
 #include <asm/setup.h>
 #include <asm/system.h>
 #include <asm/memory.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/hardware/iop3xx.h>
 #include <asm/mach/arch.h>
 
diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c
index 7e810b3fa552..a6a4f93085fd 100644
--- a/arch/arm/mach-ixp2000/core.c
+++ b/arch/arm/mach-ixp2000/core.c
@@ -29,7 +29,7 @@
 #include <asm/types.h>
 #include <asm/setup.h>
 #include <asm/memory.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/system.h>
 #include <asm/tlbflush.h>
@@ -39,7 +39,7 @@
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/gpio.h>
+#include <mach/gpio.h>
 
 static DEFINE_SPINLOCK(ixp2000_slowport_lock);
 static unsigned long ixp2000_slowport_irq_flags;
diff --git a/arch/arm/mach-ixp2000/enp2611.c b/arch/arm/mach-ixp2000/enp2611.c
index 17af9f7bd066..c62ed655c1a7 100644
--- a/arch/arm/mach-ixp2000/enp2611.c
+++ b/arch/arm/mach-ixp2000/enp2611.c
@@ -38,7 +38,7 @@
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/system.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 
 #include <asm/mach/pci.h>
diff --git a/arch/arm/mach-ixp2000/include/mach/debug-macro.S b/arch/arm/mach-ixp2000/include/mach/debug-macro.S
new file mode 100644
index 000000000000..904ff56d2246
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/debug-macro.S
@@ -0,0 +1,27 @@
+/* arch/arm/mach-ixp2000/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx, #0xc0000000        @ Physical base
+                movne   \rx, #0xfe000000        @ virtual base
+                orrne   \rx, \rx, #0x00f00000
+                orr     \rx, \rx, #0x00030000
+#ifdef  __ARMEB__
+                orr     \rx, \rx, #0x00000003
+#endif
+                .endm
+
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-ixp2000/include/mach/dma.h b/arch/arm/mach-ixp2000/include/mach/dma.h
new file mode 100644
index 000000000000..26063d60f622
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/dma.h
@@ -0,0 +1,9 @@
+/*
+ * arch/arm/mach-ixp2000/include/mach/dma.h
+ *
+ * Copyright (C) 2002 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
diff --git a/arch/arm/mach-ixp2000/include/mach/enp2611.h b/arch/arm/mach-ixp2000/include/mach/enp2611.h
new file mode 100644
index 000000000000..9ce3690061d5
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/enp2611.h
@@ -0,0 +1,46 @@
+/*
+ * arch/arm/mach-ixp2000/include/mach/enp2611.h
+ *
+ * Register and other defines for Radisys ENP-2611
+ *
+ * Created 2004 by Lennert Buytenhek from the ixdp2x01 code.  The
+ * original version carries the following notices:
+ *
+ * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright (C) 2002 Intel Corp.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#ifndef __ENP2611_H
+#define __ENP2611_H
+
+#define ENP2611_CALEB_PHYS_BASE         0xc5000000
+#define ENP2611_CALEB_VIRT_BASE         0xfe000000
+#define ENP2611_CALEB_SIZE              0x00100000
+
+#define ENP2611_PM3386_0_PHYS_BASE      0xc6000000
+#define ENP2611_PM3386_0_VIRT_BASE      0xfe100000
+#define ENP2611_PM3386_0_SIZE           0x00100000
+
+#define ENP2611_PM3386_1_PHYS_BASE      0xc6400000
+#define ENP2611_PM3386_1_VIRT_BASE      0xfe200000
+#define ENP2611_PM3386_1_SIZE           0x00100000
+
+#define ENP2611_GPIO_SCL                7
+#define ENP2611_GPIO_SDA                6
+
+#define IRQ_ENP2611_THERMAL             IRQ_IXP2000_GPIO4
+#define IRQ_ENP2611_OPTION_BOARD        IRQ_IXP2000_GPIO3
+#define IRQ_ENP2611_CALEB               IRQ_IXP2000_GPIO2
+#define IRQ_ENP2611_PM3386_1            IRQ_IXP2000_GPIO1
+#define IRQ_ENP2611_PM3386_0            IRQ_IXP2000_GPIO0
+
+
+#endif
diff --git a/arch/arm/mach-ixp2000/include/mach/entry-macro.S b/arch/arm/mach-ixp2000/include/mach/entry-macro.S
new file mode 100644
index 000000000000..5850ffc8c751
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/entry-macro.S
@@ -0,0 +1,60 @@
+/*
+ * arch/arm/mach-ixp2000/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for IXP2000-based platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <mach/irqs.h>
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_preamble, base, tmp
+                .endm
+
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+                mov     \irqnr, #0x0              @clear out irqnr as default
+                mov     \base, #0xfe000000
+                orr     \base, \base, #0x00e00000
+                orr     \base, \base, #0x08
+                ldr     \irqstat, [\base]         @ get interrupts
+
+                cmp     \irqstat, #0
+                beq     1001f
+
+                clz     \irqnr, \irqstat
+                mov     \base, #31
+                subs    \irqnr, \base, \irqnr
+
+                /*
+                 * We handle PCIA and PCIB here so we don't have an
+                 * extra layer of code just to check these two bits.
+                 */
+                cmp     \irqnr, #IRQ_IXP2000_PCI
+                bne     1001f
+
+                mov     \base, #0xfe000000
+                orr     \base, \base, #0x00c00000
+                orr     \base, \base, #0x00000100
+                orr     \base, \base, #0x00000058
+                ldr     \irqstat, [\base]
+
+                mov     \tmp, #(1<<26)
+                tst     \irqstat, \tmp
+                movne   \irqnr, #IRQ_IXP2000_PCIA
+                bne     1001f
+
+                mov     \tmp, #(1<<27)
+                tst     \irqstat, \tmp
+                movne   \irqnr, #IRQ_IXP2000_PCIB
+
+1001:
+                .endm
+
diff --git a/arch/arm/mach-ixp2000/include/mach/gpio.h b/arch/arm/mach-ixp2000/include/mach/gpio.h
new file mode 100644
index 000000000000..4a88d2c33dac
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/gpio.h
@@ -0,0 +1,48 @@
+/*
+ * arch/arm/mach-ixp2000/include/mach/gpio.h
+ *
+ * Copyright (C) 2002 Intel Corporation.
+ *
+ * This program is free software, you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * IXP2000 GPIO in/out, edge/level detection for IRQs:
+ * IRQs are generated on Falling-edge, Rising-Edge, Level-low, Level-High
+ * or both Falling-edge and Rising-edge.  
+ * This must be called *before* the corresponding IRQ is registerd.
+ * Use this instead of directly setting the GPIO registers.
+ * GPIOs may also be used as GPIOs (e.g. for emulating i2c/smb)
+ */
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H
+
+#ifndef __ASSEMBLY__
+
+#define GPIO_IN                         0
+#define GPIO_OUT                        1
+
+#define IXP2000_GPIO_LOW                0
+#define IXP2000_GPIO_HIGH               1
+
+extern void gpio_line_config(int line, int direction);
+
+static inline int gpio_line_get(int line)
+{
+        return (((*IXP2000_GPIO_PLR) >> line) & 1);
+}
+
+static inline void gpio_line_set(int line, int value)
+{
+        if (value == IXP2000_GPIO_HIGH) {
+                ixp2000_reg_write(IXP2000_GPIO_POSR, 1 << line);
+        } else if (value == IXP2000_GPIO_LOW) {
+                ixp2000_reg_write(IXP2000_GPIO_POCR, 1 << line);
+        }
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* ASM_ARCH_IXP2000_GPIO_H_ */
diff --git a/arch/arm/mach-ixp2000/include/mach/hardware.h b/arch/arm/mach-ixp2000/include/mach/hardware.h
new file mode 100644
index 000000000000..f033de4e7493
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/hardware.h
@@ -0,0 +1,44 @@
+/*
+ * arch/arm/mach-ixp2000/include/mach/hardware.h
+ *
+ * Hardware definitions for IXP2400/2800 based systems
+ *
+ * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
+ *
+ * Maintainer: Deepak Saxena <dsaxena@mvista.com>
+ *
+ * Copyright (C) 2001-2002 Intel Corp.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H__
+#define __ASM_ARCH_HARDWARE_H__
+
+/*
+ * This needs to be platform-specific?
+ */
+#define PCIBIOS_MIN_IO          0x00000000
+#define PCIBIOS_MIN_MEM         0x00000000
+
+#include "ixp2000-regs.h"       /* Chipset Registers */
+
+#define pcibios_assign_all_busses() 0
+
+/*
+ * Platform helper functions
+ */
+#include "platform.h"
+
+/*
+ * Platform-specific bits
+ */
+#include "enp2611.h"            /* ENP-2611 */
+#include "ixdp2x00.h"           /* IXDP2400/2800 */
+#include "ixdp2x01.h"           /* IXDP2401/2801 */
+
+#endif  /* _ASM_ARCH_HARDWARE_H__ */
diff --git a/arch/arm/mach-ixp2000/include/mach/io.h b/arch/arm/mach-ixp2000/include/mach/io.h
new file mode 100644
index 000000000000..859e584914d9
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/io.h
@@ -0,0 +1,134 @@
+/*
+ * arch/arm/mach-ixp2000/include/mach/io.h
+ *
+ * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright (C) 2002  Intel Corp.
+ * Copyrgiht (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#include <mach/hardware.h>
+
+#define IO_SPACE_LIMIT          0xffffffff
+#define __mem_pci(a)            (a)
+
+/*
+ * The A? revisions of the IXP2000s assert byte lanes for PCI I/O
+ * transactions the other way round (MEM transactions don't have this
+ * issue), so if we want to support those models, we need to override
+ * the standard I/O functions.
+ *
+ * B0 and later have a bit that can be set to 1 to get the proper
+ * behavior for I/O transactions, which then allows us to use the
+ * standard I/O functions.  This is what we do if the user does not
+ * explicitly ask for support for pre-B0.
+ */
+#ifdef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO
+#define ___io(p)                ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
+
+#define alignb(addr)            (void __iomem *)((unsigned long)(addr) ^ 3)
+#define alignw(addr)            (void __iomem *)((unsigned long)(addr) ^ 2)
+
+#define outb(v,p)               __raw_writeb((v),alignb(___io(p)))
+#define outw(v,p)               __raw_writew((v),alignw(___io(p)))
+#define outl(v,p)               __raw_writel((v),___io(p))
+
+#define inb(p)          ({ unsigned int __v = __raw_readb(alignb(___io(p))); __v; })
+#define inw(p)          \
+        ({ unsigned int __v = (__raw_readw(alignw(___io(p)))); __v; })
+#define inl(p)          \
+        ({ unsigned int __v = (__raw_readl(___io(p))); __v; })
+
+#define outsb(p,d,l)            __raw_writesb(alignb(___io(p)),d,l)
+#define outsw(p,d,l)            __raw_writesw(alignw(___io(p)),d,l)
+#define outsl(p,d,l)            __raw_writesl(___io(p),d,l)
+
+#define insb(p,d,l)             __raw_readsb(alignb(___io(p)),d,l)
+#define insw(p,d,l)             __raw_readsw(alignw(___io(p)),d,l)
+#define insl(p,d,l)             __raw_readsl(___io(p),d,l)
+
+#define __is_io_address(p)      ((((unsigned long)(p)) & ~(IXP2000_PCI_IO_SIZE - 1)) == IXP2000_PCI_IO_VIRT_BASE)
+
+#define ioread8(p)                                              \
+        ({                                                      \
+                unsigned int __v;                               \
+                                                                \
+                if (__is_io_address(p)) {                       \
+                        __v = __raw_readb(alignb(p));           \
+                } else {                                        \
+                        __v = __raw_readb(p);                   \
+                }                                               \
+                                                                \
+                __v;                                            \
+        })                                                      \
+
+#define ioread16(p)                                             \
+        ({                                                      \
+                unsigned int __v;                               \
+                                                                \
+                if (__is_io_address(p)) {                       \
+                        __v = __raw_readw(alignw(p));           \
+                } else {                                        \
+                        __v = le16_to_cpu(__raw_readw(p));      \
+                }                                               \
+                                                                \
+                __v;                                            \
+        })
+
+#define ioread32(p)                                             \
+        ({                                                      \
+                unsigned int __v;                               \
+                                                                \
+                if (__is_io_address(p)) {                       \
+                        __v = __raw_readl(p);                   \
+                } else {                                        \
+                        __v = le32_to_cpu(__raw_readl(p));      \
+                }                                               \
+                                                                \
+                 __v;                                           \
+        })
+
+#define iowrite8(v,p)                                           \
+        ({                                                      \
+                if (__is_io_address(p)) {                       \
+                        __raw_writeb((v), alignb(p));           \
+                } else {                                        \
+                        __raw_writeb((v), p);                   \
+                }                                               \
+        })
+
+#define iowrite16(v,p)                                          \
+        ({                                                      \
+                if (__is_io_address(p)) {                       \
+                        __raw_writew((v), alignw(p));           \
+                } else {                                        \
+                        __raw_writew(cpu_to_le16(v), p);        \
+                }                                               \
+        })
+
+#define iowrite32(v,p)                                          \
+        ({                                                      \
+                if (__is_io_address(p)) {                       \
+                        __raw_writel((v), p);                   \
+                } else {                                        \
+                        __raw_writel(cpu_to_le32(v), p);        \
+                }                                               \
+        })
+
+#define ioport_map(port, nr)    ___io(port)
+
+#define ioport_unmap(addr)
+#else
+#define __io(p)                 ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
+#endif
+
+
+#endif
diff --git a/arch/arm/mach-ixp2000/include/mach/irqs.h b/arch/arm/mach-ixp2000/include/mach/irqs.h
new file mode 100644
index 000000000000..bee96bcafdca
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/irqs.h
@@ -0,0 +1,207 @@
+/*
+ * arch/arm/mach-ixp2000/include/mach/irqs.h
+ *
+ * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright (C) 2002 Intel Corp.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _IRQS_H
+#define _IRQS_H
+
+/*
+ * Do NOT add #ifdef MACHINE_FOO in here.
+ * Simpy add your machine IRQs here and increase NR_IRQS if needed to
+ * hold your machine's IRQ table.
+ */
+
+/*
+ * Some interrupt numbers go unused b/c the IRQ mask/ummask/status
+ * register has those bit reserved. We just mark those interrupts
+ * as invalid and this allows us to do mask/unmask with a single
+ * shift operation instead of having to map the IRQ number to
+ * a HW IRQ number.
+ */
+#define IRQ_IXP2000_SOFT_INT            0 /* soft interrupt */
+#define IRQ_IXP2000_ERRSUM              1 /* OR of all bits in ErrorStatus reg*/
+#define IRQ_IXP2000_UART                2
+#define IRQ_IXP2000_GPIO                3
+#define IRQ_IXP2000_TIMER1              4
+#define IRQ_IXP2000_TIMER2              5
+#define IRQ_IXP2000_TIMER3              6
+#define IRQ_IXP2000_TIMER4              7
+#define IRQ_IXP2000_PMU                 8               
+#define IRQ_IXP2000_SPF                 9  /* Slow port framer IRQ */
+#define IRQ_IXP2000_DMA1                10
+#define IRQ_IXP2000_DMA2                11
+#define IRQ_IXP2000_DMA3                12
+#define IRQ_IXP2000_PCI_DOORBELL        13
+#define IRQ_IXP2000_ME_ATTN             14 
+#define IRQ_IXP2000_PCI                 15 /* PCI INTA or INTB */
+#define IRQ_IXP2000_THDA0               16 /* thread 0-31A */
+#define IRQ_IXP2000_THDA1               17 /* thread 32-63A, IXP2800 only */
+#define IRQ_IXP2000_THDA2               18 /* thread 64-95A */
+#define IRQ_IXP2000_THDA3               19 /* thread 96-127A, IXP2800 only */
+#define IRQ_IXP2000_THDB0               24 /* thread 0-31B */
+#define IRQ_IXP2000_THDB1               25 /* thread 32-63B, IXP2800 only */
+#define IRQ_IXP2000_THDB2               26 /* thread 64-95B */
+#define IRQ_IXP2000_THDB3               27 /* thread 96-127B, IXP2800 only */
+
+/* define generic GPIOs */
+#define IRQ_IXP2000_GPIO0               32
+#define IRQ_IXP2000_GPIO1               33
+#define IRQ_IXP2000_GPIO2               34
+#define IRQ_IXP2000_GPIO3               35
+#define IRQ_IXP2000_GPIO4               36
+#define IRQ_IXP2000_GPIO5               37
+#define IRQ_IXP2000_GPIO6               38
+#define IRQ_IXP2000_GPIO7               39
+
+/* split off the 2 PCI sources */
+#define IRQ_IXP2000_PCIA                40
+#define IRQ_IXP2000_PCIB                41
+
+/* Int sources from IRQ_ERROR_STATUS */
+#define IRQ_IXP2000_DRAM0_MIN_ERR       42
+#define IRQ_IXP2000_DRAM0_MAJ_ERR       43
+#define IRQ_IXP2000_DRAM1_MIN_ERR       44
+#define IRQ_IXP2000_DRAM1_MAJ_ERR       45
+#define IRQ_IXP2000_DRAM2_MIN_ERR       46
+#define IRQ_IXP2000_DRAM2_MAJ_ERR       47
+/* 48-57 reserved */
+#define IRQ_IXP2000_SRAM0_ERR           58
+#define IRQ_IXP2000_SRAM1_ERR           59
+#define IRQ_IXP2000_SRAM2_ERR           60
+#define IRQ_IXP2000_SRAM3_ERR           61
+/* 62-65 reserved */
+#define IRQ_IXP2000_MEDIA_ERR           66
+#define IRQ_IXP2000_PCI_ERR                     67
+#define IRQ_IXP2000_SP_INT                      68
+
+#define NR_IXP2000_IRQS                         69
+
+#define IXP2000_BOARD_IRQ(x)            (NR_IXP2000_IRQS + (x))
+
+#define IXP2000_BOARD_IRQ_MASK(irq)     (1 << (irq - NR_IXP2000_IRQS))  
+
+#define IXP2000_ERR_IRQ_MASK(irq) ( 1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR))
+#define IXP2000_VALID_ERR_IRQ_MASK (\
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MIN_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MAJ_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MIN_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MAJ_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MIN_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MAJ_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM0_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM1_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM2_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM3_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_MEDIA_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_PCI_ERR) | \
+                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SP_INT)        )
+
+/*
+ * This allows for all the on-chip sources plus up to 32 CPLD based
+ * IRQs. Should be more than enough.
+ */
+#define IXP2000_BOARD_IRQS              32
+#define NR_IRQS                         (NR_IXP2000_IRQS + IXP2000_BOARD_IRQS)
+
+
+/* 
+ * IXDP2400 specific IRQs
+ */
+#define IRQ_IXDP2400_INGRESS_NPU        IXP2000_BOARD_IRQ(0) 
+#define IRQ_IXDP2400_ENET               IXP2000_BOARD_IRQ(1) 
+#define IRQ_IXDP2400_MEDIA_PCI          IXP2000_BOARD_IRQ(2) 
+#define IRQ_IXDP2400_MEDIA_SP           IXP2000_BOARD_IRQ(3) 
+#define IRQ_IXDP2400_SF_PCI             IXP2000_BOARD_IRQ(4) 
+#define IRQ_IXDP2400_SF_SP              IXP2000_BOARD_IRQ(5) 
+#define IRQ_IXDP2400_PMC                IXP2000_BOARD_IRQ(6) 
+#define IRQ_IXDP2400_TVM                IXP2000_BOARD_IRQ(7) 
+
+#define NR_IXDP2400_IRQS                ((IRQ_IXDP2400_TVM)+1)  
+#define IXDP2400_NR_IRQS                NR_IXDP2400_IRQS - NR_IXP2000_IRQS
+
+/* IXDP2800 specific IRQs */
+#define IRQ_IXDP2800_EGRESS_ENET        IXP2000_BOARD_IRQ(0)
+#define IRQ_IXDP2800_INGRESS_NPU        IXP2000_BOARD_IRQ(1)
+#define IRQ_IXDP2800_PMC                IXP2000_BOARD_IRQ(2)
+#define IRQ_IXDP2800_FABRIC_PCI         IXP2000_BOARD_IRQ(3)
+#define IRQ_IXDP2800_FABRIC             IXP2000_BOARD_IRQ(4)
+#define IRQ_IXDP2800_MEDIA              IXP2000_BOARD_IRQ(5)
+
+#define NR_IXDP2800_IRQS                ((IRQ_IXDP2800_MEDIA)+1)
+#define IXDP2800_NR_IRQS                NR_IXDP2800_IRQS - NR_IXP2000_IRQS
+
+/* 
+ * IRQs on both IXDP2x01 boards
+ */
+#define IRQ_IXDP2X01_SPCI_DB_0          IXP2000_BOARD_IRQ(2)
+#define IRQ_IXDP2X01_SPCI_DB_1          IXP2000_BOARD_IRQ(3)
+#define IRQ_IXDP2X01_SPCI_PMC_INTA      IXP2000_BOARD_IRQ(4)
+#define IRQ_IXDP2X01_SPCI_PMC_INTB      IXP2000_BOARD_IRQ(5)
+#define IRQ_IXDP2X01_SPCI_PMC_INTC      IXP2000_BOARD_IRQ(6)
+#define IRQ_IXDP2X01_SPCI_PMC_INTD      IXP2000_BOARD_IRQ(7)
+#define IRQ_IXDP2X01_SPCI_FIC_INT       IXP2000_BOARD_IRQ(8)
+#define IRQ_IXDP2X01_IPMI_FROM          IXP2000_BOARD_IRQ(16)
+#define IRQ_IXDP2X01_125US              IXP2000_BOARD_IRQ(17)
+#define IRQ_IXDP2X01_DB_0_ADD           IXP2000_BOARD_IRQ(18)
+#define IRQ_IXDP2X01_DB_1_ADD           IXP2000_BOARD_IRQ(19)
+#define IRQ_IXDP2X01_UART1              IXP2000_BOARD_IRQ(21)
+#define IRQ_IXDP2X01_UART2              IXP2000_BOARD_IRQ(22)
+#define IRQ_IXDP2X01_FIC_ADD_INT        IXP2000_BOARD_IRQ(24)
+#define IRQ_IXDP2X01_CS8900             IXP2000_BOARD_IRQ(25)
+#define IRQ_IXDP2X01_BBSRAM             IXP2000_BOARD_IRQ(26)
+
+#define IXDP2X01_VALID_IRQ_MASK ( \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_0) | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_1) | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTA) | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTB) | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTC) | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTD) | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_FIC_INT) | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_IPMI_FROM) | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_125US) | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_0_ADD) | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_1_ADD) | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART1) | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART2) | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_FIC_ADD_INT) | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_CS8900) | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_BBSRAM) )
+
+/* 
+ * IXDP2401 specific IRQs
+ */
+#define IRQ_IXDP2401_INTA_82546         IXP2000_BOARD_IRQ(0)
+#define IRQ_IXDP2401_INTB_82546         IXP2000_BOARD_IRQ(1)
+
+#define IXDP2401_VALID_IRQ_MASK ( \
+                IXDP2X01_VALID_IRQ_MASK | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTA_82546) |\
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTB_82546))
+
+/*
+ * IXDP2801-specific IRQs
+ */
+#define IRQ_IXDP2801_RIV                IXP2000_BOARD_IRQ(0)
+#define IRQ_IXDP2801_CNFG_MEDIA         IXP2000_BOARD_IRQ(27)
+#define IRQ_IXDP2801_CLOCK_REF          IXP2000_BOARD_IRQ(28)
+
+#define IXDP2801_VALID_IRQ_MASK ( \
+                IXDP2X01_VALID_IRQ_MASK | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_RIV) |\
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CNFG_MEDIA) |\
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CLOCK_REF))
+
+#define NR_IXDP2X01_IRQS                ((IRQ_IXDP2801_CLOCK_REF) + 1)
+
+#endif /*_IRQS_H*/
diff --git a/arch/arm/mach-ixp2000/include/mach/ixdp2x00.h b/arch/arm/mach-ixp2000/include/mach/ixdp2x00.h
new file mode 100644
index 000000000000..5df8479d9481
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/ixdp2x00.h
@@ -0,0 +1,92 @@
+/*
+ * arch/arm/mach-ixp2000/include/mach/ixdp2x00.h
+ *
+ * Register and other defines for IXDP2[48]00 platforms
+ *
+ * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright (C) 2002 Intel Corp.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+#ifndef _IXDP2X00_H_
+#define _IXDP2X00_H_
+
+/*
+ * On board CPLD memory map
+ */
+#define IXDP2X00_PHYS_CPLD_BASE         0xc7000000
+#define IXDP2X00_VIRT_CPLD_BASE         0xfe000000
+#define IXDP2X00_CPLD_SIZE              0x00100000
+
+
+#define IXDP2X00_CPLD_REG(x)    \
+        (volatile unsigned long *)(IXDP2X00_VIRT_CPLD_BASE | x)
+
+/*
+ * IXDP2400 CPLD registers
+ */
+#define IXDP2400_CPLD_SYSLED            IXDP2X00_CPLD_REG(0x0)  
+#define IXDP2400_CPLD_DISP_DATA         IXDP2X00_CPLD_REG(0x4)
+#define IXDP2400_CPLD_CLOCK_SPEED       IXDP2X00_CPLD_REG(0x8)
+#define IXDP2400_CPLD_INT_STAT          IXDP2X00_CPLD_REG(0xc)
+#define IXDP2400_CPLD_REV               IXDP2X00_CPLD_REG(0x10)
+#define IXDP2400_CPLD_SYS_CLK_M         IXDP2X00_CPLD_REG(0x14)
+#define IXDP2400_CPLD_SYS_CLK_N         IXDP2X00_CPLD_REG(0x18)
+#define IXDP2400_CPLD_INT_MASK          IXDP2X00_CPLD_REG(0x48)
+
+/*
+ * IXDP2800 CPLD registers
+ */
+#define IXDP2800_CPLD_INT_STAT          IXDP2X00_CPLD_REG(0x0)
+#define IXDP2800_CPLD_INT_MASK          IXDP2X00_CPLD_REG(0x140)
+
+
+#define IXDP2X00_GPIO_I2C_ENABLE        0x02
+#define IXDP2X00_GPIO_SCL               0x07
+#define IXDP2X00_GPIO_SDA               0x06
+
+/*
+ * PCI devfns for on-board devices. We need these to be able to
+ * properly translate IRQs and for device removal.
+ */
+#define IXDP2400_SLAVE_ENET_DEVFN       0x18    /* Bus 1 */
+#define IXDP2400_MASTER_ENET_DEVFN      0x20    /* Bus 1 */
+#define IXDP2400_MEDIA_DEVFN            0x28    /* Bus 1 */
+#define IXDP2400_SWITCH_FABRIC_DEVFN    0x30    /* Bus 1 */
+
+#define IXDP2800_SLAVE_ENET_DEVFN       0x20    /* Bus 1 */
+#define IXDP2800_MASTER_ENET_DEVFN      0x18    /* Bus 1 */
+#define IXDP2800_SWITCH_FABRIC_DEVFN    0x30    /* Bus 1 */
+
+#define IXDP2X00_P2P_DEVFN              0x20    /* Bus 0 */
+#define IXDP2X00_21555_DEVFN            0x30    /* Bus 0 */
+#define IXDP2X00_SLAVE_NPU_DEVFN        0x28    /* Bus 1 */
+#define IXDP2X00_PMC_DEVFN              0x38    /* Bus 1 */
+#define IXDP2X00_MASTER_NPU_DEVFN       0x38    /* Bus 1 */
+
+#ifndef __ASSEMBLY__
+/*
+ * The master NPU is always PCI master.
+ */
+static inline unsigned int ixdp2x00_master_npu(void)
+{
+        return !!ixp2000_is_pcimaster();
+}
+
+/*
+ * Helper functions used by ixdp2400 and ixdp2800 specific code
+ */
+void ixdp2x00_init_irq(volatile unsigned long*, volatile unsigned long *, unsigned long);
+void ixdp2x00_slave_pci_postinit(void);
+void ixdp2x00_init_machine(void);
+void ixdp2x00_map_io(void);
+
+#endif
+
+#endif /*_IXDP2X00_H_ */
diff --git a/arch/arm/mach-ixp2000/include/mach/ixdp2x01.h b/arch/arm/mach-ixp2000/include/mach/ixdp2x01.h
new file mode 100644
index 000000000000..4c1f04083e54
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/ixdp2x01.h
@@ -0,0 +1,57 @@
+/*
+ * arch/arm/mach-ixp2000/include/mach/ixdp2x01.h
+ *
+ * Platform definitions for IXDP2X01 && IXDP2801 systems
+ *
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright 2004 (c) MontaVista Software, Inc. 
+ *
+ * Based on original code Copyright (c) 2002-2003 Intel Corporation
+ * 
+ * This file is licensed under  the terms of the GNU General Public 
+ * License version 2. This program is licensed "as is" without any 
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __IXDP2X01_H__
+#define __IXDP2X01_H__
+
+#define IXDP2X01_PHYS_CPLD_BASE         0xc6024000
+#define IXDP2X01_VIRT_CPLD_BASE         0xfe000000
+#define IXDP2X01_CPLD_REGION_SIZE       0x00100000
+
+#define IXDP2X01_CPLD_VIRT_REG(reg) (volatile unsigned long*)(IXDP2X01_VIRT_CPLD_BASE | reg)
+#define IXDP2X01_CPLD_PHYS_REG(reg) (IXDP2X01_PHYS_CPLD_BASE | reg)
+
+#define IXDP2X01_UART1_VIRT_BASE        IXDP2X01_CPLD_VIRT_REG(0x40)
+#define IXDP2X01_UART1_PHYS_BASE        IXDP2X01_CPLD_PHYS_REG(0x40)
+
+#define IXDP2X01_UART2_VIRT_BASE        IXDP2X01_CPLD_VIRT_REG(0x60)
+#define IXDP2X01_UART2_PHYS_BASE        IXDP2X01_CPLD_PHYS_REG(0x60)
+
+#define IXDP2X01_CS8900_VIRT_BASE       IXDP2X01_CPLD_VIRT_REG(0x80)
+#define IXDP2X01_CS8900_VIRT_END        (IXDP2X01_CS8900_VIRT_BASE + 16)
+
+#define IXDP2X01_CPLD_RESET_REG         IXDP2X01_CPLD_VIRT_REG(0x00)
+#define IXDP2X01_INT_MASK_SET_REG       IXDP2X01_CPLD_VIRT_REG(0x08)
+#define IXDP2X01_INT_STAT_REG           IXDP2X01_CPLD_VIRT_REG(0x0C)
+#define IXDP2X01_INT_RAW_REG            IXDP2X01_CPLD_VIRT_REG(0x10) 
+#define IXDP2X01_INT_MASK_CLR_REG       IXDP2X01_INT_RAW_REG
+#define IXDP2X01_INT_SIM_REG            IXDP2X01_CPLD_VIRT_REG(0x14)
+
+#define IXDP2X01_CPLD_FLASH_REG         IXDP2X01_CPLD_VIRT_REG(0x20)
+
+#define IXDP2X01_CPLD_FLASH_INTERN      0x8000
+#define IXDP2X01_CPLD_FLASH_BANK_MASK   0xF
+#define IXDP2X01_FLASH_WINDOW_BITS      25
+#define IXDP2X01_FLASH_WINDOW_SIZE      (1 << IXDP2X01_FLASH_WINDOW_BITS)
+#define IXDP2X01_FLASH_WINDOW_MASK      (IXDP2X01_FLASH_WINDOW_SIZE - 1)
+
+#define IXDP2X01_UART_CLK               1843200
+
+#define IXDP2X01_GPIO_I2C_ENABLE        0x02
+#define IXDP2X01_GPIO_SCL               0x07
+#define IXDP2X01_GPIO_SDA               0x06
+
+#endif /* __IXDP2x01_H__ */
diff --git a/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h b/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h
new file mode 100644
index 000000000000..19d80379a3e3
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h
@@ -0,0 +1,457 @@
+/*
+ * arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h
+ *
+ * Chipset register definitions for IXP2400/2800 based systems.
+ *
+ * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
+ *
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright (C) 2002 Intel Corp.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+#ifndef _IXP2000_REGS_H_
+#define _IXP2000_REGS_H_
+
+/*
+ * IXP2000 linux memory map:
+ *
+ * virt         phys            size
+ * fb000000     db000000        16M             PCI CFG1
+ * fc000000     da000000        16M             PCI CFG0
+ * fd000000     d8000000        16M             PCI I/O
+ * fe[0-7]00000                 8M              per-platform mappings
+ * fe900000     80000000        1M              SRAM #0 (first MB)
+ * fea00000     cb400000        1M              SCRATCH ring get/put
+ * feb00000     c8000000        1M              MSF
+ * fec00000     df000000        1M              PCI CSRs
+ * fed00000     de000000        1M              PCI CREG
+ * fee00000     d6000000        1M              INTCTL
+ * fef00000     c0000000        1M              CAP
+ */
+
+/* 
+ * Static I/O regions.
+ *
+ * Most of the registers are clumped in 4K regions spread throughout
+ * the 0xc0000000 -> 0xc0100000 address range, but we just map in
+ * the whole range using a single 1 MB section instead of small
+ * 4K pages.  This has two advantages for us:
+ *
+ * 1) We use only one TLB entry for large number of on-chip I/O devices.
+ *
+ * 2) We can easily set the Section attributes to XCB=101 on the IXP2400
+ *    as required per erratum #66.  We accomplish this by using a
+ *    new MT_IXP2000_DEVICE memory type with the bits set as required.
+ *
+ * CAP stands for CSR Access Proxy.
+ *
+ * If you change the virtual address of this mapping, please propagate
+ * the change to arch/arm/kernel/debug.S, which hardcodes the virtual
+ * address of the UART located in this region.
+ */
+
+#define IXP2000_CAP_PHYS_BASE           0xc0000000
+#define IXP2000_CAP_VIRT_BASE           0xfef00000
+#define IXP2000_CAP_SIZE                0x00100000
+
+/*
+ * Addresses for specific on-chip peripherals.
+ */
+#define IXP2000_SLOWPORT_CSR_VIRT_BASE  0xfef80000
+#define IXP2000_GLOBAL_REG_VIRT_BASE    0xfef04000
+#define IXP2000_UART_PHYS_BASE          0xc0030000
+#define IXP2000_UART_VIRT_BASE          0xfef30000
+#define IXP2000_TIMER_VIRT_BASE         0xfef20000
+#define IXP2000_UENGINE_CSR_VIRT_BASE   0xfef18000
+#define IXP2000_GPIO_VIRT_BASE          0xfef10000
+
+/*
+ * Devices outside of the 0xc0000000 -> 0xc0100000 range.  The virtual
+ * addresses of the INTCTL and PCI_CSR mappings are hardcoded in
+ * entry-macro.S, so if you ever change these please propagate
+ * the change.
+ */
+#define IXP2000_INTCTL_PHYS_BASE        0xd6000000
+#define IXP2000_INTCTL_VIRT_BASE        0xfee00000
+#define IXP2000_INTCTL_SIZE             0x00100000
+
+#define IXP2000_PCI_CREG_PHYS_BASE      0xde000000
+#define IXP2000_PCI_CREG_VIRT_BASE      0xfed00000
+#define IXP2000_PCI_CREG_SIZE           0x00100000
+
+#define IXP2000_PCI_CSR_PHYS_BASE       0xdf000000
+#define IXP2000_PCI_CSR_VIRT_BASE       0xfec00000
+#define IXP2000_PCI_CSR_SIZE            0x00100000
+
+#define IXP2000_MSF_PHYS_BASE           0xc8000000
+#define IXP2000_MSF_VIRT_BASE           0xfeb00000
+#define IXP2000_MSF_SIZE                0x00100000
+
+#define IXP2000_SCRATCH_RING_PHYS_BASE  0xcb400000
+#define IXP2000_SCRATCH_RING_VIRT_BASE  0xfea00000
+#define IXP2000_SCRATCH_RING_SIZE       0x00100000
+
+#define IXP2000_SRAM0_PHYS_BASE         0x80000000
+#define IXP2000_SRAM0_VIRT_BASE         0xfe900000
+#define IXP2000_SRAM0_SIZE              0x00100000
+
+#define IXP2000_PCI_IO_PHYS_BASE        0xd8000000
+#define IXP2000_PCI_IO_VIRT_BASE        0xfd000000
+#define IXP2000_PCI_IO_SIZE             0x01000000
+
+#define IXP2000_PCI_CFG0_PHYS_BASE      0xda000000
+#define IXP2000_PCI_CFG0_VIRT_BASE      0xfc000000
+#define IXP2000_PCI_CFG0_SIZE           0x01000000
+
+#define IXP2000_PCI_CFG1_PHYS_BASE      0xdb000000
+#define IXP2000_PCI_CFG1_VIRT_BASE      0xfb000000
+#define IXP2000_PCI_CFG1_SIZE           0x01000000
+
+/* 
+ * Timers
+ */
+#define IXP2000_TIMER_REG(x)            ((volatile unsigned long*)(IXP2000_TIMER_VIRT_BASE | (x)))
+/* Timer control */
+#define IXP2000_T1_CTL                  IXP2000_TIMER_REG(0x00)
+#define IXP2000_T2_CTL                  IXP2000_TIMER_REG(0x04)
+#define IXP2000_T3_CTL                  IXP2000_TIMER_REG(0x08)
+#define IXP2000_T4_CTL                  IXP2000_TIMER_REG(0x0c)
+/* Store initial value */
+#define IXP2000_T1_CLD                  IXP2000_TIMER_REG(0x10)
+#define IXP2000_T2_CLD                  IXP2000_TIMER_REG(0x14)
+#define IXP2000_T3_CLD                  IXP2000_TIMER_REG(0x18)
+#define IXP2000_T4_CLD                  IXP2000_TIMER_REG(0x1c)
+/* Read current value */
+#define IXP2000_T1_CSR                  IXP2000_TIMER_REG(0x20)
+#define IXP2000_T2_CSR                  IXP2000_TIMER_REG(0x24)
+#define IXP2000_T3_CSR                  IXP2000_TIMER_REG(0x28)
+#define IXP2000_T4_CSR                  IXP2000_TIMER_REG(0x2c)
+/* Clear associated timer interrupt */
+#define IXP2000_T1_CLR                  IXP2000_TIMER_REG(0x30)
+#define IXP2000_T2_CLR                  IXP2000_TIMER_REG(0x34)
+#define IXP2000_T3_CLR                  IXP2000_TIMER_REG(0x38)
+#define IXP2000_T4_CLR                  IXP2000_TIMER_REG(0x3c)
+/* Timer watchdog enable for T4 */
+#define IXP2000_TWDE                    IXP2000_TIMER_REG(0x40)
+
+#define WDT_ENABLE                      0x00000001
+#define TIMER_DIVIDER_256               0x00000008
+#define TIMER_ENABLE                    0x00000080
+#define IRQ_MASK_TIMER1                 (1 << 4)
+
+/*
+ * Interrupt controller registers
+ */
+#define IXP2000_INTCTL_REG(x)           (volatile unsigned long*)(IXP2000_INTCTL_VIRT_BASE | (x))
+#define IXP2000_IRQ_STATUS              IXP2000_INTCTL_REG(0x08)
+#define IXP2000_IRQ_ENABLE              IXP2000_INTCTL_REG(0x10)
+#define IXP2000_IRQ_ENABLE_SET          IXP2000_INTCTL_REG(0x10)
+#define IXP2000_IRQ_ENABLE_CLR          IXP2000_INTCTL_REG(0x18)
+#define IXP2000_FIQ_ENABLE_CLR          IXP2000_INTCTL_REG(0x14)
+#define IXP2000_IRQ_ERR_STATUS          IXP2000_INTCTL_REG(0x24)
+#define IXP2000_IRQ_ERR_ENABLE_SET      IXP2000_INTCTL_REG(0x2c)
+#define IXP2000_FIQ_ERR_ENABLE_CLR      IXP2000_INTCTL_REG(0x30)
+#define IXP2000_IRQ_ERR_ENABLE_CLR      IXP2000_INTCTL_REG(0x34)
+#define IXP2000_IRQ_THD_RAW_STATUS_A_0  IXP2000_INTCTL_REG(0x60)
+#define IXP2000_IRQ_THD_RAW_STATUS_A_1  IXP2000_INTCTL_REG(0x64)
+#define IXP2000_IRQ_THD_RAW_STATUS_A_2  IXP2000_INTCTL_REG(0x68)
+#define IXP2000_IRQ_THD_RAW_STATUS_A_3  IXP2000_INTCTL_REG(0x6c)
+#define IXP2000_IRQ_THD_RAW_STATUS_B_0  IXP2000_INTCTL_REG(0x80)
+#define IXP2000_IRQ_THD_RAW_STATUS_B_1  IXP2000_INTCTL_REG(0x84)
+#define IXP2000_IRQ_THD_RAW_STATUS_B_2  IXP2000_INTCTL_REG(0x88)
+#define IXP2000_IRQ_THD_RAW_STATUS_B_3  IXP2000_INTCTL_REG(0x8c)
+#define IXP2000_IRQ_THD_STATUS_A_0      IXP2000_INTCTL_REG(0xe0)
+#define IXP2000_IRQ_THD_STATUS_A_1      IXP2000_INTCTL_REG(0xe4)
+#define IXP2000_IRQ_THD_STATUS_A_2      IXP2000_INTCTL_REG(0xe8)
+#define IXP2000_IRQ_THD_STATUS_A_3      IXP2000_INTCTL_REG(0xec)
+#define IXP2000_IRQ_THD_STATUS_B_0      IXP2000_INTCTL_REG(0x100)
+#define IXP2000_IRQ_THD_STATUS_B_1      IXP2000_INTCTL_REG(0x104)
+#define IXP2000_IRQ_THD_STATUS_B_2      IXP2000_INTCTL_REG(0x108)
+#define IXP2000_IRQ_THD_STATUS_B_3      IXP2000_INTCTL_REG(0x10c)
+#define IXP2000_IRQ_THD_ENABLE_SET_A_0  IXP2000_INTCTL_REG(0x160)
+#define IXP2000_IRQ_THD_ENABLE_SET_A_1  IXP2000_INTCTL_REG(0x164)
+#define IXP2000_IRQ_THD_ENABLE_SET_A_2  IXP2000_INTCTL_REG(0x168)
+#define IXP2000_IRQ_THD_ENABLE_SET_A_3  IXP2000_INTCTL_REG(0x16c)
+#define IXP2000_IRQ_THD_ENABLE_SET_B_0  IXP2000_INTCTL_REG(0x180)
+#define IXP2000_IRQ_THD_ENABLE_SET_B_1  IXP2000_INTCTL_REG(0x184)
+#define IXP2000_IRQ_THD_ENABLE_SET_B_2  IXP2000_INTCTL_REG(0x188)
+#define IXP2000_IRQ_THD_ENABLE_SET_B_3  IXP2000_INTCTL_REG(0x18c)
+#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_0        IXP2000_INTCTL_REG(0x1e0)
+#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_1        IXP2000_INTCTL_REG(0x1e4)
+#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_2        IXP2000_INTCTL_REG(0x1e8)
+#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_3        IXP2000_INTCTL_REG(0x1ec)
+#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_0        IXP2000_INTCTL_REG(0x200)
+#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_1        IXP2000_INTCTL_REG(0x204)
+#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_2        IXP2000_INTCTL_REG(0x208)
+#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_3        IXP2000_INTCTL_REG(0x20c)
+
+/*
+ * Mask of valid IRQs in the 32-bit IRQ register. We use
+ * this to mark certain IRQs as being invalid.
+ */
+#define IXP2000_VALID_IRQ_MASK  0x0f0fffff
+
+/*
+ * PCI config register access from core
+ */
+#define IXP2000_PCI_CREG(x)             (volatile unsigned long*)(IXP2000_PCI_CREG_VIRT_BASE | (x))
+#define IXP2000_PCI_CMDSTAT             IXP2000_PCI_CREG(0x04)
+#define IXP2000_PCI_CSR_BAR             IXP2000_PCI_CREG(0x10)
+#define IXP2000_PCI_SRAM_BAR            IXP2000_PCI_CREG(0x14)
+#define IXP2000_PCI_SDRAM_BAR           IXP2000_PCI_CREG(0x18)
+
+/*
+ * PCI CSRs
+ */
+#define IXP2000_PCI_CSR(x)              (volatile unsigned long*)(IXP2000_PCI_CSR_VIRT_BASE | (x))
+
+/*
+ * PCI outbound interrupts
+ */
+#define IXP2000_PCI_OUT_INT_STATUS      IXP2000_PCI_CSR(0x30)
+#define IXP2000_PCI_OUT_INT_MASK        IXP2000_PCI_CSR(0x34)
+/*
+ * PCI communications
+ */
+#define IXP2000_PCI_MAILBOX0            IXP2000_PCI_CSR(0x50)
+#define IXP2000_PCI_MAILBOX1            IXP2000_PCI_CSR(0x54)
+#define IXP2000_PCI_MAILBOX2            IXP2000_PCI_CSR(0x58)
+#define IXP2000_PCI_MAILBOX3            IXP2000_PCI_CSR(0x5C)
+#define IXP2000_XSCALE_DOORBELL         IXP2000_PCI_CSR(0x60)
+#define IXP2000_XSCALE_DOORBELL_SETUP   IXP2000_PCI_CSR(0x64)
+#define IXP2000_PCI_DOORBELL            IXP2000_PCI_CSR(0x70)
+#define IXP2000_PCI_DOORBELL_SETUP      IXP2000_PCI_CSR(0x74)
+
+/*
+ * DMA engines
+ */
+#define IXP2000_PCI_CH1_BYTE_CNT        IXP2000_PCI_CSR(0x80)
+#define IXP2000_PCI_CH1_ADDR            IXP2000_PCI_CSR(0x84)
+#define IXP2000_PCI_CH1_DRAM_ADDR       IXP2000_PCI_CSR(0x88)
+#define IXP2000_PCI_CH1_DESC_PTR        IXP2000_PCI_CSR(0x8C)
+#define IXP2000_PCI_CH1_CNTRL           IXP2000_PCI_CSR(0x90)
+#define IXP2000_PCI_CH1_ME_PARAM        IXP2000_PCI_CSR(0x94)
+#define IXP2000_PCI_CH2_BYTE_CNT        IXP2000_PCI_CSR(0xA0)
+#define IXP2000_PCI_CH2_ADDR            IXP2000_PCI_CSR(0xA4)
+#define IXP2000_PCI_CH2_DRAM_ADDR       IXP2000_PCI_CSR(0xA8)
+#define IXP2000_PCI_CH2_DESC_PTR        IXP2000_PCI_CSR(0xAC)
+#define IXP2000_PCI_CH2_CNTRL           IXP2000_PCI_CSR(0xB0)
+#define IXP2000_PCI_CH2_ME_PARAM        IXP2000_PCI_CSR(0xB4)
+#define IXP2000_PCI_CH3_BYTE_CNT        IXP2000_PCI_CSR(0xC0)
+#define IXP2000_PCI_CH3_ADDR            IXP2000_PCI_CSR(0xC4)
+#define IXP2000_PCI_CH3_DRAM_ADDR       IXP2000_PCI_CSR(0xC8)
+#define IXP2000_PCI_CH3_DESC_PTR        IXP2000_PCI_CSR(0xCC)
+#define IXP2000_PCI_CH3_CNTRL           IXP2000_PCI_CSR(0xD0)
+#define IXP2000_PCI_CH3_ME_PARAM        IXP2000_PCI_CSR(0xD4)
+#define IXP2000_DMA_INF_MODE            IXP2000_PCI_CSR(0xE0)
+/*
+ * Size masks for BARs
+ */
+#define IXP2000_PCI_SRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0xFC)
+#define IXP2000_PCI_DRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0x100)
+/*
+ * Control and uEngine related
+ */
+#define IXP2000_PCI_CONTROL             IXP2000_PCI_CSR(0x13C)
+#define IXP2000_PCI_ADDR_EXT            IXP2000_PCI_CSR(0x140)
+#define IXP2000_PCI_ME_PUSH_STATUS      IXP2000_PCI_CSR(0x148)
+#define IXP2000_PCI_ME_PUSH_EN          IXP2000_PCI_CSR(0x14C)
+#define IXP2000_PCI_ERR_STATUS          IXP2000_PCI_CSR(0x150)
+#define IXP2000_PCI_ERR_ENABLE          IXP2000_PCI_CSR(0x154)
+/*
+ * Inbound PCI interrupt control
+ */
+#define IXP2000_PCI_XSCALE_INT_STATUS   IXP2000_PCI_CSR(0x158)
+#define IXP2000_PCI_XSCALE_INT_ENABLE   IXP2000_PCI_CSR(0x15C)
+
+#define IXP2000_PCICNTL_PNR             (1<<17) /* PCI not Reset bit of PCI_CONTROL */
+#define IXP2000_PCICNTL_PCF             (1<<28) /* PCI Central function bit */
+#define IXP2000_XSCALE_INT              (1<<1)  /* Interrupt from XScale to PCI */
+
+/* These are from the IRQ register in the PCI ISR register */
+#define PCI_CONTROL_BE_DEO              (1 << 22)       /* Big Endian Data Enable Out */
+#define PCI_CONTROL_BE_DEI              (1 << 21)       /* Big Endian Data Enable In  */
+#define PCI_CONTROL_BE_BEO              (1 << 20)       /* Big Endian Byte Enable Out */
+#define PCI_CONTROL_BE_BEI              (1 << 19)       /* Big Endian Byte Enable In  */
+#define PCI_CONTROL_IEE                 (1 << 17)       /* I/O cycle Endian swap Enable */
+
+#define IXP2000_PCI_RST_REL             (1 << 2)
+#define CFG_RST_DIR                     (*IXP2000_PCI_CONTROL & IXP2000_PCICNTL_PCF)
+#define CFG_PCI_BOOT_HOST               (1 << 2)
+#define CFG_BOOT_PROM                   (1 << 1)
+
+/*
+ * SlowPort CSRs
+ *
+ * The slowport is used to access things like flash, SONET framer control
+ * ports, slave microprocessors, CPLDs, and others of chip memory mapped
+ * peripherals.
+ */
+#define SLOWPORT_CSR(x)         (volatile unsigned long*)(IXP2000_SLOWPORT_CSR_VIRT_BASE | (x))
+
+#define IXP2000_SLOWPORT_CCR            SLOWPORT_CSR(0x00)
+#define IXP2000_SLOWPORT_WTC1           SLOWPORT_CSR(0x04)
+#define IXP2000_SLOWPORT_WTC2           SLOWPORT_CSR(0x08)
+#define IXP2000_SLOWPORT_RTC1           SLOWPORT_CSR(0x0c)
+#define IXP2000_SLOWPORT_RTC2           SLOWPORT_CSR(0x10)
+#define IXP2000_SLOWPORT_FSR            SLOWPORT_CSR(0x14)
+#define IXP2000_SLOWPORT_PCR            SLOWPORT_CSR(0x18)
+#define IXP2000_SLOWPORT_ADC            SLOWPORT_CSR(0x1C)
+#define IXP2000_SLOWPORT_FAC            SLOWPORT_CSR(0x20)
+#define IXP2000_SLOWPORT_FRM            SLOWPORT_CSR(0x24)
+#define IXP2000_SLOWPORT_FIN            SLOWPORT_CSR(0x28)
+
+/*
+ * CCR values.  
+ * The CCR configures the clock division for the slowport interface.
+ */
+#define SLOWPORT_CCR_DIV_1              0x00
+#define SLOWPORT_CCR_DIV_2              0x01
+#define SLOWPORT_CCR_DIV_4              0x02
+#define SLOWPORT_CCR_DIV_6              0x03
+#define SLOWPORT_CCR_DIV_8              0x04
+#define SLOWPORT_CCR_DIV_10             0x05
+#define SLOWPORT_CCR_DIV_12             0x06
+#define SLOWPORT_CCR_DIV_14             0x07
+#define SLOWPORT_CCR_DIV_16             0x08
+#define SLOWPORT_CCR_DIV_18             0x09
+#define SLOWPORT_CCR_DIV_20             0x0a
+#define SLOWPORT_CCR_DIV_22             0x0b
+#define SLOWPORT_CCR_DIV_24             0x0c
+#define SLOWPORT_CCR_DIV_26             0x0d
+#define SLOWPORT_CCR_DIV_28             0x0e
+#define SLOWPORT_CCR_DIV_30             0x0f
+
+/*
+ * PCR values.  PCR configure the mode of the interface.
+ */
+#define SLOWPORT_MODE_FLASH             0x00
+#define SLOWPORT_MODE_LUCENT            0x01
+#define SLOWPORT_MODE_PMC_SIERRA        0x02
+#define SLOWPORT_MODE_INTEL_UP          0x03
+#define SLOWPORT_MODE_MOTOROLA_UP       0x04
+
+/*
+ * ADC values.  Defines data and address bus widths.
+ */
+#define SLOWPORT_ADDR_WIDTH_8           0x00
+#define SLOWPORT_ADDR_WIDTH_16          0x01
+#define SLOWPORT_ADDR_WIDTH_24          0x02
+#define SLOWPORT_ADDR_WIDTH_32          0x03
+#define SLOWPORT_DATA_WIDTH_8           0x00
+#define SLOWPORT_DATA_WIDTH_16          0x10
+#define SLOWPORT_DATA_WIDTH_24          0x20
+#define SLOWPORT_DATA_WIDTH_32          0x30
+
+/*
+ * Masks and shifts for various fields in the WTC and RTC registers.
+ */
+#define SLOWPORT_WRTC_MASK_HD           0x0003
+#define SLOWPORT_WRTC_MASK_PW           0x003c
+#define SLOWPORT_WRTC_MASK_SU           0x03c0
+
+#define SLOWPORT_WRTC_SHIFT_HD          0x00
+#define SLOWPORT_WRTC_SHIFT_SU          0x02
+#define SLOWPORT_WRTC_SHFIT_PW          0x06
+
+
+/*
+ * GPIO registers & GPIO interface.
+ */
+#define IXP2000_GPIO_REG(x)             ((volatile unsigned long*)(IXP2000_GPIO_VIRT_BASE+(x)))
+#define IXP2000_GPIO_PLR                IXP2000_GPIO_REG(0x00)
+#define IXP2000_GPIO_PDPR               IXP2000_GPIO_REG(0x04)
+#define IXP2000_GPIO_PDSR               IXP2000_GPIO_REG(0x08)
+#define IXP2000_GPIO_PDCR               IXP2000_GPIO_REG(0x0c)
+#define IXP2000_GPIO_POPR               IXP2000_GPIO_REG(0x10)
+#define IXP2000_GPIO_POSR               IXP2000_GPIO_REG(0x14)
+#define IXP2000_GPIO_POCR               IXP2000_GPIO_REG(0x18)
+#define IXP2000_GPIO_REDR               IXP2000_GPIO_REG(0x1c)
+#define IXP2000_GPIO_FEDR               IXP2000_GPIO_REG(0x20)
+#define IXP2000_GPIO_EDSR               IXP2000_GPIO_REG(0x24)
+#define IXP2000_GPIO_LSHR               IXP2000_GPIO_REG(0x28)
+#define IXP2000_GPIO_LSLR               IXP2000_GPIO_REG(0x2c)
+#define IXP2000_GPIO_LDSR               IXP2000_GPIO_REG(0x30)
+#define IXP2000_GPIO_INER               IXP2000_GPIO_REG(0x34)
+#define IXP2000_GPIO_INSR               IXP2000_GPIO_REG(0x38)
+#define IXP2000_GPIO_INCR               IXP2000_GPIO_REG(0x3c)
+#define IXP2000_GPIO_INST               IXP2000_GPIO_REG(0x40)
+
+/*
+ * "Global" registers...whatever that's supposed to mean.
+ */
+#define GLOBAL_REG_BASE                 (IXP2000_GLOBAL_REG_VIRT_BASE + 0x0a00)
+#define GLOBAL_REG(x)                   (volatile unsigned long*)(GLOBAL_REG_BASE | (x))
+
+#define IXP2000_MAJ_PROD_TYPE_MASK      0x001F0000
+#define IXP2000_MAJ_PROD_TYPE_IXP2000   0x00000000
+#define IXP2000_MIN_PROD_TYPE_MASK      0x0000FF00
+#define IXP2000_MIN_PROD_TYPE_IXP2400   0x00000200
+#define IXP2000_MIN_PROD_TYPE_IXP2850   0x00000100
+#define IXP2000_MIN_PROD_TYPE_IXP2800   0x00000000
+#define IXP2000_MAJ_REV_MASK            0x000000F0
+#define IXP2000_MIN_REV_MASK            0x0000000F
+#define IXP2000_PROD_ID_MASK            0xFFFFFFFF
+
+#define IXP2000_PRODUCT_ID              GLOBAL_REG(0x00)
+#define IXP2000_MISC_CONTROL            GLOBAL_REG(0x04)
+#define IXP2000_MSF_CLK_CNTRL           GLOBAL_REG(0x08)
+#define IXP2000_RESET0                  GLOBAL_REG(0x0c)
+#define IXP2000_RESET1                  GLOBAL_REG(0x10)
+#define IXP2000_CCR                     GLOBAL_REG(0x14)
+#define IXP2000_STRAP_OPTIONS           GLOBAL_REG(0x18)
+
+#define RSTALL                          (1 << 16)
+#define WDT_RESET_ENABLE                0x01000000
+
+
+/*
+ * MSF registers.  The IXP2400 and IXP2800 have somewhat different MSF
+ * units, but the registers that differ between the two don't overlap,
+ * so we can have one register list for both.
+ */
+#define IXP2000_MSF_REG(x)                      ((volatile unsigned long*)(IXP2000_MSF_VIRT_BASE + (x)))
+#define IXP2000_MSF_RX_CONTROL                  IXP2000_MSF_REG(0x0000)
+#define IXP2000_MSF_TX_CONTROL                  IXP2000_MSF_REG(0x0004)
+#define IXP2000_MSF_INTERRUPT_STATUS            IXP2000_MSF_REG(0x0008)
+#define IXP2000_MSF_INTERRUPT_ENABLE            IXP2000_MSF_REG(0x000c)
+#define IXP2000_MSF_CSIX_TYPE_MAP               IXP2000_MSF_REG(0x0010)
+#define IXP2000_MSF_FC_EGRESS_STATUS            IXP2000_MSF_REG(0x0014)
+#define IXP2000_MSF_FC_INGRESS_STATUS           IXP2000_MSF_REG(0x0018)
+#define IXP2000_MSF_HWM_CONTROL                 IXP2000_MSF_REG(0x0024)
+#define IXP2000_MSF_FC_STATUS_OVERRIDE          IXP2000_MSF_REG(0x0028)
+#define IXP2000_MSF_CLOCK_CONTROL               IXP2000_MSF_REG(0x002c)
+#define IXP2000_MSF_RX_PORT_MAP                 IXP2000_MSF_REG(0x0040)
+#define IXP2000_MSF_RBUF_ELEMENT_DONE           IXP2000_MSF_REG(0x0044)
+#define IXP2000_MSF_RX_MPHY_POLL_LIMIT          IXP2000_MSF_REG(0x0048)
+#define IXP2000_MSF_RX_CALENDAR_LENGTH          IXP2000_MSF_REG(0x0048)
+#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_0        IXP2000_MSF_REG(0x0050)
+#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_1        IXP2000_MSF_REG(0x0054)
+#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_2        IXP2000_MSF_REG(0x0058)
+#define IXP2000_MSF_TX_SEQUENCE_0               IXP2000_MSF_REG(0x0060)
+#define IXP2000_MSF_TX_SEQUENCE_1               IXP2000_MSF_REG(0x0064)
+#define IXP2000_MSF_TX_SEQUENCE_2               IXP2000_MSF_REG(0x0068)
+#define IXP2000_MSF_TX_MPHY_POLL_LIMIT          IXP2000_MSF_REG(0x0070)
+#define IXP2000_MSF_TX_CALENDAR_LENGTH          IXP2000_MSF_REG(0x0070)
+#define IXP2000_MSF_RX_UP_CONTROL_0             IXP2000_MSF_REG(0x0080)
+#define IXP2000_MSF_RX_UP_CONTROL_1             IXP2000_MSF_REG(0x0084)
+#define IXP2000_MSF_RX_UP_CONTROL_2             IXP2000_MSF_REG(0x0088)
+#define IXP2000_MSF_RX_UP_CONTROL_3             IXP2000_MSF_REG(0x008c)
+#define IXP2000_MSF_TX_UP_CONTROL_0             IXP2000_MSF_REG(0x0090)
+#define IXP2000_MSF_TX_UP_CONTROL_1             IXP2000_MSF_REG(0x0094)
+#define IXP2000_MSF_TX_UP_CONTROL_2             IXP2000_MSF_REG(0x0098)
+#define IXP2000_MSF_TX_UP_CONTROL_3             IXP2000_MSF_REG(0x009c)
+#define IXP2000_MSF_TRAIN_DATA                  IXP2000_MSF_REG(0x00a0)
+#define IXP2000_MSF_TRAIN_CALENDAR              IXP2000_MSF_REG(0x00a4)
+#define IXP2000_MSF_TRAIN_FLOW_CONTROL          IXP2000_MSF_REG(0x00a8)
+#define IXP2000_MSF_TX_CALENDAR_0               IXP2000_MSF_REG(0x1000)
+#define IXP2000_MSF_RX_PORT_CALENDAR_STATUS     IXP2000_MSF_REG(0x1400)
+
+
+#endif                          /* _IXP2000_H_ */
diff --git a/arch/arm/mach-ixp2000/include/mach/memory.h b/arch/arm/mach-ixp2000/include/mach/memory.h
new file mode 100644
index 000000000000..241529a7c52d
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/memory.h
@@ -0,0 +1,34 @@
+/*
+ * arch/arm/mach-ixp2000/include/mach/memory.h
+ *
+ * Copyright (c) 2002 Intel Corp.
+ * Copyright (c) 2003-2004 MontaVista Software, Inc.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#define PHYS_OFFSET     UL(0x00000000)
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+#include <mach/ixp2000-regs.h>
+
+#define __virt_to_bus(v) \
+        (((__virt_to_phys(v) - 0x0) + (*IXP2000_PCI_SDRAM_BAR & 0xfffffff0)))
+
+#define __bus_to_virt(b) \
+        __phys_to_virt((((b - (*IXP2000_PCI_SDRAM_BAR & 0xfffffff0)) + 0x0)))
+
+#endif
+
diff --git a/arch/arm/mach-ixp2000/include/mach/platform.h b/arch/arm/mach-ixp2000/include/mach/platform.h
new file mode 100644
index 000000000000..42182c79ed90
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/platform.h
@@ -0,0 +1,152 @@
+/*
+ * arch/arm/mach-ixp2000/include/mach/platform.h
+ *
+ * Various bits of code used by platform-level code.
+ *
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright 2004 (c) MontaVista Software, Inc. 
+ * 
+ * This file is licensed under  the terms of the GNU General Public 
+ * License version 2. This program is licensed "as is" without any 
+ * warranty of any kind, whether express or implied.
+ */
+
+
+#ifndef __ASSEMBLY__
+
+static inline unsigned long ixp2000_reg_read(volatile void *reg)
+{
+        return *((volatile unsigned long *)reg);
+}
+
+static inline void ixp2000_reg_write(volatile void *reg, unsigned long val)
+{
+        *((volatile unsigned long *)reg) = val;
+}
+
+/*
+ * On the IXP2400, we can't use XCB=000 due to chip bugs.  We use
+ * XCB=101 instead, but that makes all I/O accesses bufferable.  This
+ * is not a problem in general, but we do have to be slightly more
+ * careful because I/O writes are no longer automatically flushed out
+ * of the write buffer.
+ *
+ * In cases where we want to make sure that a write has been flushed
+ * out of the write buffer before we proceed, for example when masking
+ * a device interrupt before re-enabling IRQs in CPSR, we can use this
+ * function, ixp2000_reg_wrb, which performs a write, a readback, and
+ * issues a dummy instruction dependent on the value of the readback
+ * (mov rX, rX) to make sure that the readback has completed before we
+ * continue.
+ */
+static inline void ixp2000_reg_wrb(volatile void *reg, unsigned long val)
+{
+        unsigned long dummy;
+
+        *((volatile unsigned long *)reg) = val;
+
+        dummy = *((volatile unsigned long *)reg);
+        __asm__ __volatile__("mov %0, %0" : "+r" (dummy));
+}
+
+/*
+ * Boards may multiplex different devices on the 2nd channel of 
+ * the slowport interface that each need different configuration 
+ * settings.  For example, the IXDP2400 uses channel 2 on the interface 
+ * to access the CPLD, the switch fabric card, and the media card.  Each
+ * one needs a different mode so drivers must save/restore the mode 
+ * before and after each operation.  
+ *
+ * acquire_slowport(&your_config);
+ * ...
+ * do slowport operations
+ * ...
+ * release_slowport();
+ *
+ * Note that while you have the slowport, you are holding a spinlock,
+ * so your code should be written as if you explicitly acquired a lock.
+ *
+ * The configuration only affects device 2 on the slowport, so the
+ * MTD map driver does not acquire/release the slowport.  
+ */
+struct slowport_cfg {
+        unsigned long CCR;      /* Clock divide */
+        unsigned long WTC;      /* Write Timing Control */
+        unsigned long RTC;      /* Read Timing Control */
+        unsigned long PCR;      /* Protocol Control Register */
+        unsigned long ADC;      /* Address/Data Width Control */
+};
+
+
+void ixp2000_acquire_slowport(struct slowport_cfg *, struct slowport_cfg *);
+void ixp2000_release_slowport(struct slowport_cfg *);
+
+/*
+ * IXP2400 A0/A1 and  IXP2800 A0/A1/A2 have broken slowport that requires
+ * tweaking of addresses in the MTD driver.
+ */
+static inline unsigned ixp2000_has_broken_slowport(void)
+{
+        unsigned long id = *IXP2000_PRODUCT_ID;
+        unsigned long id_prod = id & (IXP2000_MAJ_PROD_TYPE_MASK |
+                                      IXP2000_MIN_PROD_TYPE_MASK);
+        return (((id_prod ==
+                  /* fixed in IXP2400-B0 */
+                  (IXP2000_MAJ_PROD_TYPE_IXP2000 |
+                   IXP2000_MIN_PROD_TYPE_IXP2400)) &&
+                 ((id & IXP2000_MAJ_REV_MASK) == 0)) ||
+                ((id_prod ==
+                  /* fixed in IXP2800-B0 */
+                  (IXP2000_MAJ_PROD_TYPE_IXP2000 |
+                   IXP2000_MIN_PROD_TYPE_IXP2800)) &&
+                 ((id & IXP2000_MAJ_REV_MASK) == 0)) ||
+                ((id_prod ==
+                  /* fixed in IXP2850-B0 */
+                  (IXP2000_MAJ_PROD_TYPE_IXP2000 |
+                   IXP2000_MIN_PROD_TYPE_IXP2850)) &&
+                 ((id & IXP2000_MAJ_REV_MASK) == 0)));
+}
+
+static inline unsigned int ixp2000_has_flash(void)
+{
+        return ((*IXP2000_STRAP_OPTIONS) & (CFG_BOOT_PROM));
+}
+
+static inline unsigned int ixp2000_is_pcimaster(void)
+{
+        return ((*IXP2000_STRAP_OPTIONS) & (CFG_PCI_BOOT_HOST));
+}
+
+void ixp2000_map_io(void);
+void ixp2000_uart_init(void);
+void ixp2000_init_irq(void);
+void ixp2000_init_time(unsigned long);
+unsigned long ixp2000_gettimeoffset(void);
+
+struct pci_sys_data;
+
+u32 *ixp2000_pci_config_addr(unsigned int bus, unsigned int devfn, int where);
+void ixp2000_pci_preinit(void);
+int ixp2000_pci_setup(int, struct pci_sys_data*);
+struct pci_bus* ixp2000_pci_scan_bus(int, struct pci_sys_data*);
+int ixp2000_pci_read_config(struct pci_bus*, unsigned int, int, int, u32 *);
+int ixp2000_pci_write_config(struct pci_bus*, unsigned int, int, int, u32);
+
+/*
+ * Several of the IXP2000 systems have banked flash so we need to extend the
+ * flash_platform_data structure with some private pointers
+ */
+struct ixp2000_flash_data {
+        struct flash_platform_data *platform_data;
+        int nr_banks;
+        unsigned long (*bank_setup)(unsigned long);
+};
+
+struct ixp2000_i2c_pins {
+        unsigned long sda_pin;
+        unsigned long scl_pin;
+};
+
+
+#endif /*  !__ASSEMBLY__ */
diff --git a/arch/arm/mach-ixp2000/include/mach/system.h b/arch/arm/mach-ixp2000/include/mach/system.h
new file mode 100644
index 000000000000..2e9c68f95a24
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/system.h
@@ -0,0 +1,49 @@
+/*
+ * arch/arm/mach-ixp2000/include/mach/system.h
+ *
+ * Copyright (C) 2002 Intel Corp.
+ * Copyricht (C) 2003-2005 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        local_irq_disable();
+
+        /*
+         * Reset flash banking register so that we are pointing at
+         * RedBoot bank.
+         */
+        if (machine_is_ixdp2401()) {
+                ixp2000_reg_write(IXDP2X01_CPLD_FLASH_REG,
+                                        ((0 >> IXDP2X01_FLASH_WINDOW_BITS)
+                                                | IXDP2X01_CPLD_FLASH_INTERN));
+                ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0xffffffff);
+        }
+
+        /*
+         * On IXDP2801 we need to write this magic sequence to the CPLD
+         * to cause a complete reset of the CPU and all external devices
+         * and move the flash bank register back to 0.
+         */
+        if (machine_is_ixdp2801() || machine_is_ixdp28x5()) {
+                unsigned long reset_reg = *IXDP2X01_CPLD_RESET_REG;
+
+                reset_reg = 0x55AA0000 | (reset_reg & 0x0000FFFF);
+                ixp2000_reg_write(IXDP2X01_CPLD_RESET_REG, reset_reg);
+                ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0x80000000);
+        }
+
+        ixp2000_reg_wrb(IXP2000_RESET0, RSTALL);
+}
diff --git a/arch/arm/mach-ixp2000/include/mach/timex.h b/arch/arm/mach-ixp2000/include/mach/timex.h
new file mode 100644
index 000000000000..835e659f93d4
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/timex.h
@@ -0,0 +1,13 @@
+/*
+ * arch/arm/mach-ixp2000/include/mach/timex.h
+ *
+ * IXP2000 architecture timex specifications
+ */
+
+
+/*
+ * Default clock is 50MHz APB, but platform code can override this
+ */
+#define CLOCK_TICK_RATE 50000000
+
+
diff --git a/arch/arm/mach-ixp2000/include/mach/uncompress.h b/arch/arm/mach-ixp2000/include/mach/uncompress.h
new file mode 100644
index 000000000000..ce363087df78
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/uncompress.h
@@ -0,0 +1,47 @@
+/*
+ * arch/arm/mach-ixp2000/include/mach/uncompress.h
+ *
+ *
+ * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright 2002 Intel Corp.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/serial_reg.h>
+
+#define UART_BASE       0xc0030000
+
+#define PHYS(x)          ((volatile unsigned long *)(UART_BASE + x))
+
+#define UARTDR          PHYS(0x00)      /* Transmit reg dlab=0 */
+#define UARTDLL         PHYS(0x00)      /* Divisor Latch reg dlab=1*/
+#define UARTDLM         PHYS(0x04)      /* Divisor Latch reg dlab=1*/
+#define UARTIER         PHYS(0x04)      /* Interrupt enable reg */
+#define UARTFCR         PHYS(0x08)      /* FIFO control reg dlab =0*/
+#define UARTLCR         PHYS(0x0c)      /* Control reg */
+#define UARTSR          PHYS(0x14)      /* Status reg */
+
+
+static inline void putc(int c)
+{
+        int j = 0x1000;
+
+        while (--j && !(*UARTSR & UART_LSR_THRE))
+                barrier();
+
+        *UARTDR = c;
+}
+
+static inline void flush(void)
+{
+}
+
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-ixp2000/include/mach/vmalloc.h b/arch/arm/mach-ixp2000/include/mach/vmalloc.h
new file mode 100644
index 000000000000..d195e35aed3b
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/vmalloc.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/mach-ixp2000/include/mach/vmalloc.h
+ *
+ * Author: Naeem Afzal <naeem.m.afzal@intel.com>
+ *
+ * Copyright 2002 Intel Corp.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_END         0xfb000000
diff --git a/arch/arm/mach-ixp2000/ixdp2400.c b/arch/arm/mach-ixp2000/ixdp2400.c
index 5f1068762979..c673b9ef9f69 100644
--- a/arch/arm/mach-ixp2000/ixdp2400.c
+++ b/arch/arm/mach-ixp2000/ixdp2400.c
@@ -31,7 +31,7 @@
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/system.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 
 #include <asm/mach/pci.h>
diff --git a/arch/arm/mach-ixp2000/ixdp2800.c b/arch/arm/mach-ixp2000/ixdp2800.c
index 4c0f0ee63407..6715b50829a6 100644
--- a/arch/arm/mach-ixp2000/ixdp2800.c
+++ b/arch/arm/mach-ixp2000/ixdp2800.c
@@ -31,7 +31,7 @@
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/system.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 
 #include <asm/mach/pci.h>
diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c
index f378baed267f..5a781fd9757a 100644
--- a/arch/arm/mach-ixp2000/ixdp2x00.c
+++ b/arch/arm/mach-ixp2000/ixdp2x00.c
@@ -31,7 +31,7 @@
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/system.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 
 #include <asm/mach/pci.h>
@@ -41,7 +41,7 @@
 #include <asm/mach/flash.h>
 #include <asm/mach/arch.h>
 
-#include <asm/arch/gpio.h>
+#include <mach/gpio.h>
 
 
 /*************************************************************************
diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c
index 739a9e0965c6..78a2341dee2c 100644
--- a/arch/arm/mach-ixp2000/ixdp2x01.c
+++ b/arch/arm/mach-ixp2000/ixdp2x01.c
@@ -36,7 +36,7 @@
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/system.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 
 #include <asm/mach/pci.h>
diff --git a/arch/arm/mach-ixp2000/pci.c b/arch/arm/mach-ixp2000/pci.c
index dd0eee2c4ccf..03d916fbe531 100644
--- a/arch/arm/mach-ixp2000/pci.c
+++ b/arch/arm/mach-ixp2000/pci.c
@@ -28,7 +28,7 @@
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/system.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 #include <asm/mach/pci.h>
 
diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c
index bc40cd49462d..68b4ac5b2481 100644
--- a/arch/arm/mach-ixp23xx/core.c
+++ b/arch/arm/mach-ixp23xx/core.c
@@ -32,7 +32,7 @@
 #include <asm/types.h>
 #include <asm/setup.h>
 #include <asm/memory.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/system.h>
 #include <asm/tlbflush.h>
diff --git a/arch/arm/mach-ixp23xx/espresso.c b/arch/arm/mach-ixp23xx/espresso.c
index b6cbefce7c18..1c06bfc5a7ef 100644
--- a/arch/arm/mach-ixp23xx/espresso.c
+++ b/arch/arm/mach-ixp23xx/espresso.c
@@ -29,7 +29,7 @@
 #include <asm/types.h>
 #include <asm/setup.h>
 #include <asm/memory.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
 #include <asm/system.h>
diff --git a/arch/arm/mach-ixp23xx/include/mach/debug-macro.S b/arch/arm/mach-ixp23xx/include/mach/debug-macro.S
new file mode 100644
index 000000000000..905db3188724
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/include/mach/debug-macro.S
@@ -0,0 +1,26 @@
+/*
+ * arch/arm/mach-ixp23xx/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ * Copyright (C) 1994-1999 Russell King
+ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <mach/ixp23xx.h>
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                         @ mmu enabled?
+                ldreq   \rx, =IXP23XX_PERIPHERAL_PHYS   @ physical
+                ldrne   \rx, =IXP23XX_PERIPHERAL_VIRT   @ virtual
+#ifdef __ARMEB__
+                orr     \rx, \rx, #0x00000003
+#endif
+                .endm
+
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-ixp23xx/include/mach/dma.h b/arch/arm/mach-ixp23xx/include/mach/dma.h
new file mode 100644
index 000000000000..8886544b93f7
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/include/mach/dma.h
@@ -0,0 +1,3 @@
+/*
+ * arch/arm/mach-ixp23xx/include/mach/dma.h
+ */
diff --git a/arch/arm/mach-ixp23xx/include/mach/entry-macro.S b/arch/arm/mach-ixp23xx/include/mach/entry-macro.S
new file mode 100644
index 000000000000..3f5338a7bbdd
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/include/mach/entry-macro.S
@@ -0,0 +1,37 @@
+/*
+ * arch/arm/mach-ixp23xx/include/mach/entry-macro.S
+ */
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_preamble, base, tmp
+                .endm
+
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                ldr     \irqnr, =(IXP23XX_INTC_VIRT + IXP23XX_INTR_IRQ_ENC_ST_OFFSET)
+                ldr     \irqnr, [\irqnr]        @ get interrupt number
+                cmp     \irqnr, #0x0            @ spurious interrupt ?
+                movne   \irqnr, \irqnr, lsr #2  @ skip unwanted low order bits
+                subne   \irqnr, \irqnr, #1      @ convert to 0 based
+
+#if 0
+                cmp     \irqnr, #IRQ_IXP23XX_PCI_INT_RPH
+                bne     1001f
+                mov     \irqnr, #IRQ_IXP23XX_INTA
+
+                ldr     \irqnr, =0xf5000030
+
+                mov     \tmp, #(1<<26)
+                tst     \irqnr, \tmp
+                movne   \irqnr, #IRQ_IXP23XX_INTB
+
+                mov     \tmp, #(1<<27)
+                tst     \irqnr, \tmp
+                movne   \irqnr, #IRQ_IXP23XX_INTA
+1001:
+#endif
+                .endm
diff --git a/arch/arm/mach-ixp23xx/include/mach/hardware.h b/arch/arm/mach-ixp23xx/include/mach/hardware.h
new file mode 100644
index 000000000000..c3192009a886
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/include/mach/hardware.h
@@ -0,0 +1,37 @@
+/*
+ * arch/arm/mach-ixp23xx/include/mach/hardware.h
+ *
+ * Copyright (C) 2002-2004 Intel Corporation.
+ * Copyricht (C) 2005 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Hardware definitions for IXP23XX based systems
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+/* PCI IO info */
+#define PCIO_BASE               IXP23XX_PCI_IO_VIRT
+#define PCIBIOS_MIN_IO          0x00000000
+#define PCIBIOS_MIN_MEM         0xe0000000
+
+#include "ixp23xx.h"
+
+#define pcibios_assign_all_busses()     0
+
+/*
+ * Platform helper functions
+ */
+#include "platform.h"
+
+/*
+ * Platform-specific headers
+ */
+#include "ixdp2351.h"
+
+
+#endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/io.h b/arch/arm/mach-ixp23xx/include/mach/io.h
new file mode 100644
index 000000000000..305ea1808c71
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/include/mach/io.h
@@ -0,0 +1,54 @@
+/*
+ * arch/arm/mach-ixp23xx/include/mach/io.h
+ *
+ * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright (C) 2003-2005 Intel Corp.
+ * Copyright (C) 2005 MontaVista Software, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+#define __io(p)         ((void __iomem*)((p) + IXP23XX_PCI_IO_VIRT))
+#define __mem_pci(a)    (a)
+
+#include <linux/kernel.h>       /* For BUG */
+
+static inline void __iomem *
+ixp23xx_ioremap(unsigned long addr, unsigned long size, unsigned int mtype)
+{
+        if (addr >= IXP23XX_PCI_MEM_START &&
+                addr <= IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE) {
+                if (addr + size > IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE)
+                        return NULL;
+
+                return (void __iomem *)
+                        ((addr - IXP23XX_PCI_MEM_START) + IXP23XX_PCI_MEM_VIRT);
+        }
+
+        return __arm_ioremap(addr, size, mtype);
+}
+
+static inline void
+ixp23xx_iounmap(void __iomem *addr)
+{
+        if ((((u32)addr) >= IXP23XX_PCI_MEM_VIRT) &&
+            (((u32)addr) < IXP23XX_PCI_MEM_VIRT + IXP23XX_PCI_MEM_SIZE))
+                return;
+
+        __iounmap(addr);
+}
+
+#define __arch_ioremap(a,s,f)   ixp23xx_ioremap(a,s,f)
+#define __arch_iounmap(a)       ixp23xx_iounmap(a)
+
+
+#endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/irqs.h b/arch/arm/mach-ixp23xx/include/mach/irqs.h
new file mode 100644
index 000000000000..3af33a04b8a2
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/include/mach/irqs.h
@@ -0,0 +1,223 @@
+/*
+ * arch/arm/mach-ixp23xx/include/mach/irqs.h
+ *
+ * IRQ definitions for IXP23XX based systems
+ *
+ * Author: Naeem Afzal <naeem.m.afzal@intel.com>
+ *
+ * Copyright (C) 2003-2004 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#define NR_IXP23XX_IRQS                 IRQ_IXP23XX_INTB+1
+#define IRQ_IXP23XX_EXTIRQS             NR_IXP23XX_IRQS
+
+
+#define IRQ_IXP23XX_DBG0                0       /* Debug/Execution/MBox */
+#define IRQ_IXP23XX_DBG1                1       /* Debug/Execution/MBox */
+#define IRQ_IXP23XX_NPE_TRG             2       /* npe_trigger */
+#define IRQ_IXP23XX_TIMER1              3       /* Timer[0] */
+#define IRQ_IXP23XX_TIMER2              4       /* Timer[1] */
+#define IRQ_IXP23XX_TIMESTAMP           5       /* Timer[2], Time-stamp */
+#define IRQ_IXP23XX_WDOG                6       /* Time[3], Watchdog Timer */
+#define IRQ_IXP23XX_PCI_DBELL           7       /* PCI Doorbell */
+#define IRQ_IXP23XX_PCI_DMA1            8       /* PCI DMA Channel 1 */
+#define IRQ_IXP23XX_PCI_DMA2            9       /* PCI DMA Channel 2 */
+#define IRQ_IXP23XX_PCI_DMA3            10      /* PCI DMA Channel 3 */
+#define IRQ_IXP23XX_PCI_INT_RPH         11      /* pcxg_pci_int_rph */
+#define IRQ_IXP23XX_CPP_PMU             12      /* xpxg_pm_int_rpl */
+#define IRQ_IXP23XX_SWINT0              13      /* S/W Interrupt0 */
+#define IRQ_IXP23XX_SWINT1              14      /* S/W Interrupt1 */
+#define IRQ_IXP23XX_UART2               15      /* UART1 Interrupt */
+#define IRQ_IXP23XX_UART1               16      /* UART0 Interrupt */
+#define IRQ_IXP23XX_XSI_PMU_ROLLOVER    17      /* AHB Performance M. Unit counter rollover */
+#define IRQ_IXP23XX_XSI_AHB_PM0         18      /* intr_pm_o */
+#define IRQ_IXP23XX_XSI_AHB_ECE0        19      /* intr_ece_o */
+#define IRQ_IXP23XX_XSI_AHB_GASKET      20      /* gas_intr_o */
+#define IRQ_IXP23XX_XSI_CPP             21      /* xsi2cpp_int */
+#define IRQ_IXP23XX_CPP_XSI             22      /* cpp2xsi_int */
+#define IRQ_IXP23XX_ME_ATTN0            23      /* ME_ATTN */
+#define IRQ_IXP23XX_ME_ATTN1            24      /* ME_ATTN */
+#define IRQ_IXP23XX_ME_ATTN2            25      /* ME_ATTN */
+#define IRQ_IXP23XX_ME_ATTN3            26      /* ME_ATTN */
+#define IRQ_IXP23XX_PCI_ERR_RPH         27      /* PCXG_PCI_ERR_RPH */
+#define IRQ_IXP23XX_D0XG_ECC_CORR       28      /* D0XG_DRAM_ECC_CORR */
+#define IRQ_IXP23XX_D0XG_ECC_UNCORR     29      /* D0XG_DRAM_ECC_UNCORR */
+#define IRQ_IXP23XX_SRAM_ERR1           30      /* SRAM1_ERR */
+#define IRQ_IXP23XX_SRAM_ERR0           31      /* SRAM0_ERR */
+#define IRQ_IXP23XX_MEDIA_ERR           32      /* MEDIA_ERR */
+#define IRQ_IXP23XX_STH_DRAM_ECC_MAJ    33      /* STH_DRAM0_ECC_MAJ */
+#define IRQ_IXP23XX_GPIO6               34      /* GPIO0 interrupts */
+#define IRQ_IXP23XX_GPIO7               35      /* GPIO1 interrupts */
+#define IRQ_IXP23XX_GPIO8               36      /* GPIO2 interrupts */
+#define IRQ_IXP23XX_GPIO9               37      /* GPIO3 interrupts */
+#define IRQ_IXP23XX_GPIO10              38      /* GPIO4 interrupts */
+#define IRQ_IXP23XX_GPIO11              39      /* GPIO5 interrupts */
+#define IRQ_IXP23XX_GPIO12              40      /* GPIO6 interrupts */
+#define IRQ_IXP23XX_GPIO13              41      /* GPIO7 interrupts */
+#define IRQ_IXP23XX_GPIO14              42      /* GPIO8 interrupts */
+#define IRQ_IXP23XX_GPIO15              43      /* GPIO9 interrupts */
+#define IRQ_IXP23XX_SHAC_RING0          44      /* SHAC Ring Full */
+#define IRQ_IXP23XX_SHAC_RING1          45      /* SHAC Ring Full */
+#define IRQ_IXP23XX_SHAC_RING2          46      /* SHAC Ring Full */
+#define IRQ_IXP23XX_SHAC_RING3          47      /* SHAC Ring Full */
+#define IRQ_IXP23XX_SHAC_RING4          48      /* SHAC Ring Full */
+#define IRQ_IXP23XX_SHAC_RING5          49      /* SHAC Ring Full */
+#define IRQ_IXP23XX_SHAC_RING6          50      /* SHAC RING Full */
+#define IRQ_IXP23XX_SHAC_RING7          51      /* SHAC Ring Full */
+#define IRQ_IXP23XX_SHAC_RING8          52      /* SHAC Ring Full */
+#define IRQ_IXP23XX_SHAC_RING9          53      /* SHAC Ring Full */
+#define IRQ_IXP23XX_SHAC_RING10         54      /* SHAC Ring Full */
+#define IRQ_IXP23XX_SHAC_RING11         55      /* SHAC Ring Full */
+#define IRQ_IXP23XX_ME_THREAD_A0_ME0    56      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A1_ME0    57      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A2_ME0    58      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A3_ME0    59      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A4_ME0    60      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A5_ME0    61      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A6_ME0    62      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A7_ME0    63      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A8_ME1    64      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A9_ME1    65      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A10_ME1   66      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A11_ME1   67      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A12_ME1   68      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A13_ME1   69      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A14_ME1   70      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A15_ME1   71      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A16_ME2   72      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A17_ME2   73      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A18_ME2   74      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A19_ME2   75      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A20_ME2   76      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A21_ME2   77      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A22_ME2   78      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A23_ME2   79      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A24_ME3   80      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A25_ME3   81      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A26_ME3   82      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A27_ME3   83      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A28_ME3   84      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A29_ME3   85      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A30_ME3   86      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_A31_ME3   87      /* ME_THREAD_A */
+#define IRQ_IXP23XX_ME_THREAD_B0_ME0    88      /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B1_ME0    89      /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B2_ME0    90      /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B3_ME0    91      /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B4_ME0    92      /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B5_ME0    93      /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B6_ME0    94      /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B7_ME0    95      /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B8_ME1    96      /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B9_ME1    97      /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B10_ME1   98      /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B11_ME1   99      /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B12_ME1   100     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B13_ME1   101     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B14_ME1   102     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B15_ME1   103     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B16_ME2   104     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B17_ME2   105     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B18_ME2   106     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B19_ME2   107     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B20_ME2   108     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B21_ME2   109     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B22_ME2   110     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B23_ME2   111     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B24_ME3   112     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B25_ME3   113     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B26_ME3   114     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B27_ME3   115     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B28_ME3   116     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B29_ME3   117     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B30_ME3   118     /* ME_THREAD_B */
+#define IRQ_IXP23XX_ME_THREAD_B31_ME3   119     /* ME_THREAD_B */
+
+#define NUM_IXP23XX_RAW_IRQS            120
+
+#define IRQ_IXP23XX_INTA                120     /* Indirect pcxg_pci_int_rph */
+#define IRQ_IXP23XX_INTB                121     /* Indirect pcxg_pci_int_rph */
+
+#define NR_IXP23XX_IRQ                  (IRQ_IXP23XX_INTB + 1)
+
+/*
+ * We default to 32 per-board IRQs. Increase this number if you need
+ * more, but keep it realistic.
+ */
+#define NR_IXP23XX_MACH_IRQS            32
+
+#define NR_IRQS                         (NR_IXP23XX_IRQS + NR_IXP23XX_MACH_IRQS)
+
+#define IXP23XX_MACH_IRQ(irq)           (NR_IXP23XX_IRQ + (irq))
+
+
+/*
+ * IXDP2351-specific interrupts
+ */
+
+/*
+ * External PCI interrupts signaled through INTB
+ *
+ */
+#define IXDP2351_INTB_IRQ_BASE          0
+#define IRQ_IXDP2351_INTA_82546         IXP23XX_MACH_IRQ(0)
+#define IRQ_IXDP2351_INTB_82546         IXP23XX_MACH_IRQ(1)
+#define IRQ_IXDP2351_SPCI_DB_0          IXP23XX_MACH_IRQ(2)
+#define IRQ_IXDP2351_SPCI_DB_1          IXP23XX_MACH_IRQ(3)
+#define IRQ_IXDP2351_SPCI_PMC_INTA      IXP23XX_MACH_IRQ(4)
+#define IRQ_IXDP2351_SPCI_PMC_INTB      IXP23XX_MACH_IRQ(5)
+#define IRQ_IXDP2351_SPCI_PMC_INTC      IXP23XX_MACH_IRQ(6)
+#define IRQ_IXDP2351_SPCI_PMC_INTD      IXP23XX_MACH_IRQ(7)
+#define IRQ_IXDP2351_SPCI_FIC           IXP23XX_MACH_IRQ(8)
+
+#define IXDP2351_INTB_IRQ_BIT(irq)      (irq - IXP23XX_MACH_IRQ(0))
+#define IXDP2351_INTB_IRQ_MASK(irq)     (1 << IXDP2351_INTB_IRQ_BIT(irq))
+#define IXDP2351_INTB_IRQ_VALID         0x01FF
+#define IXDP2351_INTB_IRQ_NUM           16
+
+/*
+ * Other external interrupts signaled through INTA
+ */
+#define IXDP2351_INTA_IRQ_BASE          16
+#define IRQ_IXDP2351_IPMI_FROM          IXP23XX_MACH_IRQ(16)
+#define IRQ_IXDP2351_125US              IXP23XX_MACH_IRQ(17)
+#define IRQ_IXDP2351_DB_0_ADD           IXP23XX_MACH_IRQ(18)
+#define IRQ_IXDP2351_DB_1_ADD           IXP23XX_MACH_IRQ(19)
+#define IRQ_IXDP2351_DEBUG1             IXP23XX_MACH_IRQ(20)
+#define IRQ_IXDP2351_ADD_UART           IXP23XX_MACH_IRQ(21)
+#define IRQ_IXDP2351_FIC_ADD            IXP23XX_MACH_IRQ(24)
+#define IRQ_IXDP2351_CS8900             IXP23XX_MACH_IRQ(25)
+#define IRQ_IXDP2351_BBSRAM             IXP23XX_MACH_IRQ(26)
+#define IRQ_IXDP2351_CONFIG_MEDIA       IXP23XX_MACH_IRQ(27)
+#define IRQ_IXDP2351_CLOCK_REF          IXP23XX_MACH_IRQ(28)
+#define IRQ_IXDP2351_A10_NP             IXP23XX_MACH_IRQ(29)
+#define IRQ_IXDP2351_A11_NP             IXP23XX_MACH_IRQ(30)
+#define IRQ_IXDP2351_DEBUG_NP           IXP23XX_MACH_IRQ(31)
+
+#define IXDP2351_INTA_IRQ_BIT(irq)      (irq - IXP23XX_MACH_IRQ(16))
+#define IXDP2351_INTA_IRQ_MASK(irq)     (1 << IXDP2351_INTA_IRQ_BIT(irq))
+#define IXDP2351_INTA_IRQ_VALID         0xFF3F
+#define IXDP2351_INTA_IRQ_NUM           16
+
+
+/*
+ * ADI RoadRunner IRQs
+ */
+#define IRQ_ROADRUNNER_PCI_INTA         IRQ_IXP23XX_INTA
+#define IRQ_ROADRUNNER_PCI_INTB         IRQ_IXP23XX_INTB
+#define IRQ_ROADRUNNER_PCI_INTC         IRQ_IXP23XX_GPIO11
+#define IRQ_ROADRUNNER_PCI_INTD         IRQ_IXP23XX_GPIO12
+
+/*
+ * Put new board definitions here
+ */
+
+
+#endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/ixdp2351.h b/arch/arm/mach-ixp23xx/include/mach/ixdp2351.h
new file mode 100644
index 000000000000..663951027de5
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/include/mach/ixdp2351.h
@@ -0,0 +1,89 @@
+/*
+ * arch/arm/mach-ixp23xx/include/mach/ixdp2351.h
+ *
+ * Register and other defines for IXDP2351
+ *
+ * Copyright (c) 2002-2004 Intel Corp.
+ * Copytight (c) 2005 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_ARCH_IXDP2351_H
+#define __ASM_ARCH_IXDP2351_H
+
+/*
+ * NP module memory map
+ */
+#define IXDP2351_NP_PHYS_BASE           (IXP23XX_EXP_BUS_CS4_BASE)
+#define IXDP2351_NP_PHYS_SIZE           0x00100000
+#define IXDP2351_NP_VIRT_BASE           0xeff00000
+
+#define IXDP2351_VIRT_CS8900_BASE       (IXDP2351_NP_VIRT_BASE)
+#define IXDP2351_VIRT_CS8900_END        (IXDP2351_VIRT_CS8900_BASE + 16)
+
+#define IXDP2351_VIRT_NP_CPLD_BASE      (IXP23XX_EXP_BUS_CS4_BASE_VIRT + 0x00010000)
+
+#define IXDP2351_NP_CPLD_REG(reg) ((volatile u16 *)(IXDP2351_VIRT_NP_CPLD_BASE + reg))
+
+#define IXDP2351_NP_CPLD_RESET1_REG     IXDP2351_NP_CPLD_REG(0x00)
+#define IXDP2351_NP_CPLD_LED_REG        IXDP2351_NP_CPLD_REG(0x02)
+#define IXDP2351_NP_CPLD_VERSION_REG    IXDP2351_NP_CPLD_REG(0x04)
+
+/*
+ * Base board module memory map
+ */
+
+#define IXDP2351_BB_BASE_PHYS           (IXP23XX_EXP_BUS_CS5_BASE)
+#define IXDP2351_BB_SIZE                0x01000000
+#define IXDP2351_BB_BASE_VIRT           (0xee000000)
+
+#define IXDP2351_BB_AREA_BASE(offset)   (IXDP2351_BB_BASE_VIRT + offset)
+
+#define IXDP2351_VIRT_NVRAM_BASE        IXDP2351_BB_AREA_BASE(0x0)
+#define IXDP2351_NVRAM_SIZE             (0x20000)
+
+#define IXDP2351_VIRT_MB_IXF1104_BASE   IXDP2351_BB_AREA_BASE(0x00020000)
+#define IXDP2351_VIRT_ADD_UART_BASE     IXDP2351_BB_AREA_BASE(0x000240C0)
+#define IXDP2351_VIRT_FIC_BASE          IXDP2351_BB_AREA_BASE(0x00200000)
+#define IXDP2351_VIRT_DB0_BASE          IXDP2351_BB_AREA_BASE(0x00400000)
+#define IXDP2351_VIRT_DB1_BASE          IXDP2351_BB_AREA_BASE(0x00600000)
+#define IXDP2351_VIRT_CPLD_BASE         IXDP2351_BB_AREA_BASE(0x00024000)
+
+/*
+ * On board CPLD registers
+ */
+#define IXDP2351_CPLD_BB_REG(reg) ((volatile u16 *)(IXDP2351_VIRT_CPLD_BASE + reg))
+
+#define IXDP2351_CPLD_RESET0_REG        IXDP2351_CPLD_BB_REG(0x00)
+#define IXDP2351_CPLD_RESET1_REG        IXDP2351_CPLD_BB_REG(0x04)
+
+#define IXDP2351_CPLD_RESET1_MAGIC      0x55AA
+#define IXDP2351_CPLD_RESET1_ENABLE     0x8000
+
+#define IXDP2351_CPLD_FPGA_CONFIG_REG   IXDP2351_CPLD_BB_REG(0x08)
+#define IXDP2351_CPLD_INTB_MASK_SET_REG IXDP2351_CPLD_BB_REG(0x10)
+#define IXDP2351_CPLD_INTA_MASK_SET_REG IXDP2351_CPLD_BB_REG(0x14)
+#define IXDP2351_CPLD_INTB_STAT_REG     IXDP2351_CPLD_BB_REG(0x18)
+#define IXDP2351_CPLD_INTA_STAT_REG     IXDP2351_CPLD_BB_REG(0x1C)
+#define IXDP2351_CPLD_INTB_RAW_REG      IXDP2351_CPLD_BB_REG(0x20)      /* read */
+#define IXDP2351_CPLD_INTA_RAW_REG      IXDP2351_CPLD_BB_REG(0x24)      /* read */
+#define IXDP2351_CPLD_INTB_MASK_CLR_REG IXDP2351_CPLD_INTB_RAW_REG      /* write */
+#define IXDP2351_CPLD_INTA_MASK_CLR_REG IXDP2351_CPLD_INTA_RAW_REG      /* write */
+#define IXDP2351_CPLD_INTB_SIM_REG      IXDP2351_CPLD_BB_REG(0x28)
+#define IXDP2351_CPLD_INTA_SIM_REG      IXDP2351_CPLD_BB_REG(0x2C)
+        /* Interrupt bits are defined in irqs.h */
+#define IXDP2351_CPLD_BB_GBE0_REG       IXDP2351_CPLD_BB_REG(0x30)
+#define IXDP2351_CPLD_BB_GBE1_REG       IXDP2351_CPLD_BB_REG(0x34)
+
+/* #define IXDP2351_CPLD_BB_MISC_REG    IXDP2351_CPLD_REG(0x1C) */
+/* #define IXDP2351_CPLD_BB_MISC_REV_MASK       0xFF            */
+/* #define IXDP2351_CPLD_BB_GDXCS0_REG  IXDP2351_CPLD_REG(0x24) */
+/* #define IXDP2351_CPLD_BB_GDXCS1_REG  IXDP2351_CPLD_REG(0x28) */
+/* #define IXDP2351_CPLD_BB_CLOCK_REG   IXDP2351_CPLD_REG(0x04) */
+
+
+#endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/ixp23xx.h b/arch/arm/mach-ixp23xx/include/mach/ixp23xx.h
new file mode 100644
index 000000000000..6d02481b1d6d
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/include/mach/ixp23xx.h
@@ -0,0 +1,298 @@
+/*
+ * arch/arm/mach-ixp23xx/include/mach/ixp23xx.h
+ *
+ * Register definitions for IXP23XX
+ *
+ * Copyright (C) 2003-2005 Intel Corporation.
+ * Copyright (C) 2005 MontaVista Software, Inc.
+ *
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_IXP23XX_H
+#define __ASM_ARCH_IXP23XX_H
+
+/*
+ * IXP2300 linux memory map:
+ *
+ * virt         phys            size
+ * fffd0000     a0000000        64K             XSI2CPP_CSR
+ * fffc0000     c4000000        4K              EXP_CFG
+ * fff00000     c8000000        64K             PERIPHERAL
+ * fe000000     1c0000000       16M             CAP_CSR
+ * fd000000     1c8000000       16M             MSF_CSR
+ * fb000000                     16M             ---
+ * fa000000     1d8000000       32M             PCI_IO
+ * f8000000     1da000000       32M             PCI_CFG
+ * f6000000     1de000000       32M             PCI_CREG
+ * f4000000                     32M             ---
+ * f0000000     1e0000000       64M             PCI_MEM
+ * e[c-f]000000                                 per-platform mappings
+ */
+
+
+/****************************************************************************
+ * Static mappings.
+ ****************************************************************************/
+#define IXP23XX_XSI2CPP_CSR_PHYS        0xa0000000
+#define IXP23XX_XSI2CPP_CSR_VIRT        0xfffd0000
+#define IXP23XX_XSI2CPP_CSR_SIZE        0x00010000
+
+#define IXP23XX_EXP_CFG_PHYS            0xc4000000
+#define IXP23XX_EXP_CFG_VIRT            0xfffc0000
+#define IXP23XX_EXP_CFG_SIZE            0x00001000
+
+#define IXP23XX_PERIPHERAL_PHYS         0xc8000000
+#define IXP23XX_PERIPHERAL_VIRT         0xfff00000
+#define IXP23XX_PERIPHERAL_SIZE         0x00010000
+
+#define IXP23XX_CAP_CSR_PHYS            0x1c0000000ULL
+#define IXP23XX_CAP_CSR_VIRT            0xfe000000
+#define IXP23XX_CAP_CSR_SIZE            0x01000000
+
+#define IXP23XX_MSF_CSR_PHYS            0x1c8000000ULL
+#define IXP23XX_MSF_CSR_VIRT            0xfd000000
+#define IXP23XX_MSF_CSR_SIZE            0x01000000
+
+#define IXP23XX_PCI_IO_PHYS             0x1d8000000ULL
+#define IXP23XX_PCI_IO_VIRT             0xfa000000
+#define IXP23XX_PCI_IO_SIZE             0x02000000
+
+#define IXP23XX_PCI_CFG_PHYS            0x1da000000ULL
+#define IXP23XX_PCI_CFG_VIRT            0xf8000000
+#define IXP23XX_PCI_CFG_SIZE            0x02000000
+#define IXP23XX_PCI_CFG0_VIRT           IXP23XX_PCI_CFG_VIRT
+#define IXP23XX_PCI_CFG1_VIRT           (IXP23XX_PCI_CFG_VIRT + 0x01000000)
+
+#define IXP23XX_PCI_CREG_PHYS           0x1de000000ULL
+#define IXP23XX_PCI_CREG_VIRT           0xf6000000
+#define IXP23XX_PCI_CREG_SIZE           0x02000000
+#define IXP23XX_PCI_CSR_VIRT            (IXP23XX_PCI_CREG_VIRT + 0x01000000)
+
+#define IXP23XX_PCI_MEM_START           0xe0000000
+#define IXP23XX_PCI_MEM_PHYS            0x1e0000000ULL
+#define IXP23XX_PCI_MEM_VIRT            0xf0000000
+#define IXP23XX_PCI_MEM_SIZE            0x04000000
+
+
+/****************************************************************************
+ * XSI2CPP CSRs.
+ ****************************************************************************/
+#define IXP23XX_XSI2CPP_REG(x)          ((volatile unsigned long *)(IXP23XX_XSI2CPP_CSR_VIRT + (x)))
+#define IXP23XX_CPP2XSI_CURR_XFER_REG3  IXP23XX_XSI2CPP_REG(0xf8)
+#define IXP23XX_CPP2XSI_ADDR_31         (1 << 19)
+#define IXP23XX_CPP2XSI_PSH_OFF         (1 << 20)
+#define IXP23XX_CPP2XSI_COH_OFF         (1 << 21)
+
+
+/****************************************************************************
+ * Expansion Bus Config.
+ ****************************************************************************/
+#define IXP23XX_EXP_CFG_REG(x)          ((volatile unsigned long *)(IXP23XX_EXP_CFG_VIRT + (x)))
+#define IXP23XX_EXP_CS0                 IXP23XX_EXP_CFG_REG(0x00)
+#define IXP23XX_EXP_CS1                 IXP23XX_EXP_CFG_REG(0x04)
+#define IXP23XX_EXP_CS2                 IXP23XX_EXP_CFG_REG(0x08)
+#define IXP23XX_EXP_CS3                 IXP23XX_EXP_CFG_REG(0x0c)
+#define IXP23XX_EXP_CS4                 IXP23XX_EXP_CFG_REG(0x10)
+#define IXP23XX_EXP_CS5                 IXP23XX_EXP_CFG_REG(0x14)
+#define IXP23XX_EXP_CS6                 IXP23XX_EXP_CFG_REG(0x18)
+#define IXP23XX_EXP_CS7                 IXP23XX_EXP_CFG_REG(0x1c)
+#define IXP23XX_FLASH_WRITABLE          (0x2)
+#define IXP23XX_FLASH_BUS8              (0x1)
+
+#define IXP23XX_EXP_CFG0                IXP23XX_EXP_CFG_REG(0x20)
+#define IXP23XX_EXP_CFG1                IXP23XX_EXP_CFG_REG(0x24)
+#define IXP23XX_EXP_CFG0_MEM_MAP                (1 << 31)
+#define IXP23XX_EXP_CFG0_XSCALE_SPEED_SEL       (3 << 22)
+#define IXP23XX_EXP_CFG0_XSCALE_SPEED_EN        (1 << 21)
+#define IXP23XX_EXP_CFG0_CPP_SPEED_SEL          (3 << 19)
+#define IXP23XX_EXP_CFG0_CPP_SPEED_EN           (1 << 18)
+#define IXP23XX_EXP_CFG0_PCI_SWIN               (3 << 16)
+#define IXP23XX_EXP_CFG0_PCI_DWIN               (3 << 14)
+#define IXP23XX_EXP_CFG0_PCI33_MODE             (1 << 13)
+#define IXP23XX_EXP_CFG0_QDR_SPEED_SEL          (1 << 12)
+#define IXP23XX_EXP_CFG0_CPP_DIV_SEL            (1 << 5)
+#define IXP23XX_EXP_CFG0_XSI_NOT_PRES           (1 << 4)
+#define IXP23XX_EXP_CFG0_PROM_BOOT              (1 << 3)
+#define IXP23XX_EXP_CFG0_PCI_ARB                (1 << 2)
+#define IXP23XX_EXP_CFG0_PCI_HOST               (1 << 1)
+#define IXP23XX_EXP_CFG0_FLASH_WIDTH            (1 << 0)
+
+#define IXP23XX_EXP_UNIT_FUSE           IXP23XX_EXP_CFG_REG(0x28)
+#define IXP23XX_EXP_MSF_MUX             IXP23XX_EXP_CFG_REG(0x30)
+#define IXP23XX_EXP_CFG_FUSE            IXP23XX_EXP_CFG_REG(0x34)
+
+#define IXP23XX_EXP_BUS_PHYS            0x90000000
+#define IXP23XX_EXP_BUS_WINDOW_SIZE     0x01000000
+
+#define IXP23XX_EXP_BUS_CS0_BASE        (IXP23XX_EXP_BUS_PHYS + 0x00000000)
+#define IXP23XX_EXP_BUS_CS1_BASE        (IXP23XX_EXP_BUS_PHYS + 0x01000000)
+#define IXP23XX_EXP_BUS_CS2_BASE        (IXP23XX_EXP_BUS_PHYS + 0x02000000)
+#define IXP23XX_EXP_BUS_CS3_BASE        (IXP23XX_EXP_BUS_PHYS + 0x03000000)
+#define IXP23XX_EXP_BUS_CS4_BASE        (IXP23XX_EXP_BUS_PHYS + 0x04000000)
+#define IXP23XX_EXP_BUS_CS5_BASE        (IXP23XX_EXP_BUS_PHYS + 0x05000000)
+#define IXP23XX_EXP_BUS_CS6_BASE        (IXP23XX_EXP_BUS_PHYS + 0x06000000)
+#define IXP23XX_EXP_BUS_CS7_BASE        (IXP23XX_EXP_BUS_PHYS + 0x07000000)
+
+
+/****************************************************************************
+ * Peripherals.
+ ****************************************************************************/
+#define IXP23XX_UART1_VIRT              (IXP23XX_PERIPHERAL_VIRT + 0x0000)
+#define IXP23XX_UART2_VIRT              (IXP23XX_PERIPHERAL_VIRT + 0x1000)
+#define IXP23XX_PMU_VIRT                (IXP23XX_PERIPHERAL_VIRT + 0x2000)
+#define IXP23XX_INTC_VIRT               (IXP23XX_PERIPHERAL_VIRT + 0x3000)
+#define IXP23XX_GPIO_VIRT               (IXP23XX_PERIPHERAL_VIRT + 0x4000)
+#define IXP23XX_TIMER_VIRT              (IXP23XX_PERIPHERAL_VIRT + 0x5000)
+#define IXP23XX_NPE0_VIRT               (IXP23XX_PERIPHERAL_VIRT + 0x6000)
+#define IXP23XX_DSR_VIRT                (IXP23XX_PERIPHERAL_VIRT + 0x7000)
+#define IXP23XX_NPE1_VIRT               (IXP23XX_PERIPHERAL_VIRT + 0x8000)
+#define IXP23XX_ETH0_VIRT               (IXP23XX_PERIPHERAL_VIRT + 0x9000)
+#define IXP23XX_ETH1_VIRT               (IXP23XX_PERIPHERAL_VIRT + 0xA000)
+#define IXP23XX_GIG0_VIRT               (IXP23XX_PERIPHERAL_VIRT + 0xB000)
+#define IXP23XX_GIG1_VIRT               (IXP23XX_PERIPHERAL_VIRT + 0xC000)
+#define IXP23XX_DDRS_VIRT               (IXP23XX_PERIPHERAL_VIRT + 0xD000)
+
+#define IXP23XX_UART1_PHYS              (IXP23XX_PERIPHERAL_PHYS + 0x0000)
+#define IXP23XX_UART2_PHYS              (IXP23XX_PERIPHERAL_PHYS + 0x1000)
+#define IXP23XX_PMU_PHYS                (IXP23XX_PERIPHERAL_PHYS + 0x2000)
+#define IXP23XX_INTC_PHYS               (IXP23XX_PERIPHERAL_PHYS + 0x3000)
+#define IXP23XX_GPIO_PHYS               (IXP23XX_PERIPHERAL_PHYS + 0x4000)
+#define IXP23XX_TIMER_PHYS              (IXP23XX_PERIPHERAL_PHYS + 0x5000)
+#define IXP23XX_NPE0_PHYS               (IXP23XX_PERIPHERAL_PHYS + 0x6000)
+#define IXP23XX_DSR_PHYS                (IXP23XX_PERIPHERAL_PHYS + 0x7000)
+#define IXP23XX_NPE1_PHYS               (IXP23XX_PERIPHERAL_PHYS + 0x8000)
+#define IXP23XX_ETH0_PHYS               (IXP23XX_PERIPHERAL_PHYS + 0x9000)
+#define IXP23XX_ETH1_PHYS               (IXP23XX_PERIPHERAL_PHYS + 0xA000)
+#define IXP23XX_GIG0_PHYS               (IXP23XX_PERIPHERAL_PHYS + 0xB000)
+#define IXP23XX_GIG1_PHYS               (IXP23XX_PERIPHERAL_PHYS + 0xC000)
+#define IXP23XX_DDRS_PHYS               (IXP23XX_PERIPHERAL_PHYS + 0xD000)
+
+
+/****************************************************************************
+ * Interrupt controller.
+ ****************************************************************************/
+#define IXP23XX_INTC_REG(x)              ((volatile unsigned long *)(IXP23XX_INTC_VIRT + (x)))
+#define IXP23XX_INTR_ST1                IXP23XX_INTC_REG(0x00)
+#define IXP23XX_INTR_ST2                IXP23XX_INTC_REG(0x04)
+#define IXP23XX_INTR_ST3                IXP23XX_INTC_REG(0x08)
+#define IXP23XX_INTR_ST4                IXP23XX_INTC_REG(0x0c)
+#define IXP23XX_INTR_EN1                IXP23XX_INTC_REG(0x10)
+#define IXP23XX_INTR_EN2                IXP23XX_INTC_REG(0x14)
+#define IXP23XX_INTR_EN3                IXP23XX_INTC_REG(0x18)
+#define IXP23XX_INTR_EN4                IXP23XX_INTC_REG(0x1c)
+#define IXP23XX_INTR_SEL1               IXP23XX_INTC_REG(0x20)
+#define IXP23XX_INTR_SEL2               IXP23XX_INTC_REG(0x24)
+#define IXP23XX_INTR_SEL3               IXP23XX_INTC_REG(0x28)
+#define IXP23XX_INTR_SEL4               IXP23XX_INTC_REG(0x2c)
+#define IXP23XX_INTR_IRQ_ST1            IXP23XX_INTC_REG(0x30)
+#define IXP23XX_INTR_IRQ_ST2            IXP23XX_INTC_REG(0x34)
+#define IXP23XX_INTR_IRQ_ST3            IXP23XX_INTC_REG(0x38)
+#define IXP23XX_INTR_IRQ_ST4            IXP23XX_INTC_REG(0x3c)
+#define IXP23XX_INTR_IRQ_ENC_ST_OFFSET  0x54
+
+
+/****************************************************************************
+ * GPIO.
+ ****************************************************************************/
+#define IXP23XX_GPIO_REG(x)             ((volatile unsigned long *)(IXP23XX_GPIO_VIRT + (x)))
+#define IXP23XX_GPIO_GPOUTR             IXP23XX_GPIO_REG(0x00)
+#define IXP23XX_GPIO_GPOER              IXP23XX_GPIO_REG(0x04)
+#define IXP23XX_GPIO_GPINR              IXP23XX_GPIO_REG(0x08)
+#define IXP23XX_GPIO_GPISR              IXP23XX_GPIO_REG(0x0c)
+#define IXP23XX_GPIO_GPIT1R             IXP23XX_GPIO_REG(0x10)
+#define IXP23XX_GPIO_GPIT2R             IXP23XX_GPIO_REG(0x14)
+#define IXP23XX_GPIO_GPCLKR             IXP23XX_GPIO_REG(0x18)
+#define IXP23XX_GPIO_GPDBSELR           IXP23XX_GPIO_REG(0x1c)
+
+#define IXP23XX_GPIO_STYLE_MASK         0x7
+#define IXP23XX_GPIO_STYLE_ACTIVE_HIGH  0x0
+#define IXP23XX_GPIO_STYLE_ACTIVE_LOW   0x1
+#define IXP23XX_GPIO_STYLE_RISING_EDGE  0x2
+#define IXP23XX_GPIO_STYLE_FALLING_EDGE 0x3
+#define IXP23XX_GPIO_STYLE_TRANSITIONAL 0x4
+
+#define IXP23XX_GPIO_STYLE_SIZE         3
+
+
+/****************************************************************************
+ * Timer.
+ ****************************************************************************/
+#define IXP23XX_TIMER_REG(x)            ((volatile unsigned long *)(IXP23XX_TIMER_VIRT + (x)))
+#define IXP23XX_TIMER_CONT              IXP23XX_TIMER_REG(0x00)
+#define IXP23XX_TIMER1_TIMESTAMP        IXP23XX_TIMER_REG(0x04)
+#define IXP23XX_TIMER1_RELOAD           IXP23XX_TIMER_REG(0x08)
+#define IXP23XX_TIMER2_TIMESTAMP        IXP23XX_TIMER_REG(0x0c)
+#define IXP23XX_TIMER2_RELOAD           IXP23XX_TIMER_REG(0x10)
+#define IXP23XX_TIMER_WDOG              IXP23XX_TIMER_REG(0x14)
+#define IXP23XX_TIMER_WDOG_EN           IXP23XX_TIMER_REG(0x18)
+#define IXP23XX_TIMER_WDOG_KEY          IXP23XX_TIMER_REG(0x1c)
+#define IXP23XX_TIMER_WDOG_KEY_MAGIC    0x482e
+#define IXP23XX_TIMER_STATUS            IXP23XX_TIMER_REG(0x20)
+#define IXP23XX_TIMER_SOFT_RESET        IXP23XX_TIMER_REG(0x24)
+#define IXP23XX_TIMER_SOFT_RESET_EN     IXP23XX_TIMER_REG(0x28)
+
+#define IXP23XX_TIMER_ENABLE            (1 << 0)
+#define IXP23XX_TIMER_ONE_SHOT          (1 << 1)
+/* Low order bits of reload value ignored */
+#define IXP23XX_TIMER_RELOAD_MASK       (0x3)
+#define IXP23XX_TIMER_DISABLED          (0x0)
+#define IXP23XX_TIMER1_INT_PEND         (1 << 0)
+#define IXP23XX_TIMER2_INT_PEND         (1 << 1)
+#define IXP23XX_TIMER_STATUS_TS_PEND    (1 << 2)
+#define IXP23XX_TIMER_STATUS_WDOG_PEND  (1 << 3)
+#define IXP23XX_TIMER_STATUS_WARM_RESET (1 << 4)
+
+
+/****************************************************************************
+ * CAP CSRs.
+ ****************************************************************************/
+#define IXP23XX_GLOBAL_REG(x)           ((volatile unsigned long *)(IXP23XX_CAP_CSR_VIRT + 0x4a00 + (x)))
+#define IXP23XX_PRODUCT_ID              IXP23XX_GLOBAL_REG(0x00)
+#define IXP23XX_MISC_CONTROL            IXP23XX_GLOBAL_REG(0x04)
+#define IXP23XX_MSF_CLK_CNTRL           IXP23XX_GLOBAL_REG(0x08)
+#define IXP23XX_RESET0                  IXP23XX_GLOBAL_REG(0x0c)
+#define IXP23XX_RESET1                  IXP23XX_GLOBAL_REG(0x10)
+#define IXP23XX_STRAP_OPTIONS           IXP23XX_GLOBAL_REG(0x18)
+
+#define IXP23XX_ENABLE_WATCHDOG         (1 << 24)
+#define IXP23XX_SHPC_INIT_COMP          (1 << 21)
+#define IXP23XX_RST_ALL                 (1 << 16)
+#define IXP23XX_RESET_PCI               (1 << 2)
+#define IXP23XX_PCI_UNIT_RESET          (1 << 1)
+#define IXP23XX_XSCALE_RESET            (1 << 0)
+
+#define IXP23XX_UENGINE_CSR_VIRT_BASE   (IXP23XX_CAP_CSR_VIRT + 0x18000)
+
+
+/****************************************************************************
+ * PCI CSRs.
+ ****************************************************************************/
+#define IXP23XX_PCI_CREG(x)             ((volatile unsigned long *)(IXP23XX_PCI_CREG_VIRT + (x)))
+#define IXP23XX_PCI_CMDSTAT             IXP23XX_PCI_CREG(0x04)
+#define IXP23XX_PCI_SRAM_BAR            IXP23XX_PCI_CREG(0x14)
+#define IXP23XX_PCI_SDRAM_BAR           IXP23XX_PCI_CREG(0x18)
+
+
+#define IXP23XX_PCI_CSR(x)              ((volatile unsigned long *)(IXP23XX_PCI_CREG_VIRT + 0x01000000 + (x)))
+#define IXP23XX_PCI_OUT_INT_STATUS      IXP23XX_PCI_CSR(0x0030)
+#define IXP23XX_PCI_OUT_INT_MASK        IXP23XX_PCI_CSR(0x0034)
+#define IXP23XX_PCI_SRAM_BASE_ADDR_MASK IXP23XX_PCI_CSR(0x00fc)
+#define IXP23XX_PCI_DRAM_BASE_ADDR_MASK IXP23XX_PCI_CSR(0x0100)
+#define IXP23XX_PCI_CONTROL             IXP23XX_PCI_CSR(0x013c)
+#define IXP23XX_PCI_ADDR_EXT            IXP23XX_PCI_CSR(0x0140)
+#define IXP23XX_PCI_ME_PUSH_STATUS      IXP23XX_PCI_CSR(0x0148)
+#define IXP23XX_PCI_ME_PUSH_EN          IXP23XX_PCI_CSR(0x014c)
+#define IXP23XX_PCI_ERR_STATUS          IXP23XX_PCI_CSR(0x0150)
+#define IXP23XX_PCI_ERROR_STATUS        IXP23XX_PCI_CSR(0x0150)
+#define IXP23XX_PCI_ERR_ENABLE          IXP23XX_PCI_CSR(0x0154)
+#define IXP23XX_PCI_XSCALE_INT_STATUS   IXP23XX_PCI_CSR(0x0158)
+#define IXP23XX_PCI_XSCALE_INT_ENABLE   IXP23XX_PCI_CSR(0x015c)
+#define IXP23XX_PCI_CPP_ADDR_BITS       IXP23XX_PCI_CSR(0x0160)
+
+
+#endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/memory.h b/arch/arm/mach-ixp23xx/include/mach/memory.h
new file mode 100644
index 000000000000..9d40115f7ebe
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/include/mach/memory.h
@@ -0,0 +1,48 @@
+/*
+ * arch/arm/mach-ixp23xx/include/mach/memory.h
+ *
+ * Copyright (c) 2003-2004 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#include <mach/hardware.h>
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET             (0x00000000)
+
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+#ifndef __ASSEMBLY__
+
+#define __virt_to_bus(v)                                                \
+        ({ unsigned int ret;                                            \
+        ret = ((__virt_to_phys(v) - 0x00000000) +                       \
+         (*((volatile int *)IXP23XX_PCI_SDRAM_BAR) & 0xfffffff0));      \
+        ret; })
+
+#define __bus_to_virt(b)                                                \
+        ({ unsigned int data;                                           \
+        data = *((volatile int *)IXP23XX_PCI_SDRAM_BAR);                \
+         __phys_to_virt((((b - (data & 0xfffffff0)) + 0x00000000))); })
+
+#define arch_is_coherent()      1
+
+#endif
+
+
+#endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/platform.h b/arch/arm/mach-ixp23xx/include/mach/platform.h
new file mode 100644
index 000000000000..db9d9416e5e4
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/include/mach/platform.h
@@ -0,0 +1,57 @@
+/*
+ * arch/arm/mach-ixp23xx/include/mach/platform.h
+ *
+ * Various bits of code used by platform-level code.
+ *
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright 2005 (c) MontaVista Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASSEMBLY__
+
+static inline unsigned long ixp2000_reg_read(volatile void *reg)
+{
+        return *((volatile unsigned long *)reg);
+}
+
+static inline void ixp2000_reg_write(volatile void *reg, unsigned long val)
+{
+        *((volatile unsigned long *)reg) = val;
+}
+
+static inline void ixp2000_reg_wrb(volatile void *reg, unsigned long val)
+{
+        *((volatile unsigned long *)reg) = val;
+}
+
+struct pci_sys_data;
+
+void ixp23xx_map_io(void);
+void ixp23xx_init_irq(void);
+void ixp23xx_sys_init(void);
+int ixp23xx_pci_setup(int, struct pci_sys_data *);
+void ixp23xx_pci_preinit(void);
+struct pci_bus *ixp23xx_pci_scan_bus(int, struct pci_sys_data*);
+void ixp23xx_pci_slave_init(void);
+
+extern struct sys_timer ixp23xx_timer;
+
+#define IXP23XX_UART_XTAL               14745600
+
+#ifndef __ASSEMBLY__
+/*
+ * Is system memory on the XSI or CPP bus?
+ */
+static inline unsigned ixp23xx_cpp_boot(void)
+{
+        return (*IXP23XX_EXP_CFG0 & IXP23XX_EXP_CFG0_XSI_NOT_PRES);
+}
+#endif
+
+
+#endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/system.h b/arch/arm/mach-ixp23xx/include/mach/system.h
new file mode 100644
index 000000000000..d57c3fc10f1f
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/include/mach/system.h
@@ -0,0 +1,33 @@
+/*
+ * arch/arm/mach-ixp23xx/include/mach/system.h
+ *
+ * Copyright (C) 2003 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+
+static inline void arch_idle(void)
+{
+#if 0
+        if (!hlt_counter)
+                cpu_do_idle();
+#endif
+}
+
+static inline void arch_reset(char mode)
+{
+        /* First try machine specific support */
+        if (machine_is_ixdp2351()) {
+                *IXDP2351_CPLD_RESET1_REG = IXDP2351_CPLD_RESET1_MAGIC;
+                (void) *IXDP2351_CPLD_RESET1_REG;
+                *IXDP2351_CPLD_RESET1_REG = IXDP2351_CPLD_RESET1_ENABLE;
+        }
+
+        /* Use on-chip reset capability */
+        *IXP23XX_RESET0 |= IXP23XX_RST_ALL;
+}
diff --git a/arch/arm/mach-ixp23xx/include/mach/time.h b/arch/arm/mach-ixp23xx/include/mach/time.h
new file mode 100644
index 000000000000..b61dafc884ac
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/include/mach/time.h
@@ -0,0 +1,3 @@
+/*
+ * arch/arm/mach-ixp23xx/include/mach/time.h
+ */
diff --git a/arch/arm/mach-ixp23xx/include/mach/timex.h b/arch/arm/mach-ixp23xx/include/mach/timex.h
new file mode 100644
index 000000000000..e341e9cf9c37
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/include/mach/timex.h
@@ -0,0 +1,7 @@
+/*
+ * arch/arm/mach-ixp23xx/include/mach/timex.h
+ *
+ * XScale architecture timex specifications
+ */
+
+#define CLOCK_TICK_RATE 75000000
diff --git a/arch/arm/mach-ixp23xx/include/mach/uncompress.h b/arch/arm/mach-ixp23xx/include/mach/uncompress.h
new file mode 100644
index 000000000000..8b4c358d2c04
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/include/mach/uncompress.h
@@ -0,0 +1,40 @@
+/*
+ * arch/arm/mach-ixp23xx/include/mach/uncompress.h
+ *
+ * Copyright (C) 2002-2004 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+
+#include <mach/ixp23xx.h>
+#include <linux/serial_reg.h>
+
+#define UART_BASE       ((volatile u32 *)IXP23XX_UART1_PHYS)
+
+static inline void putc(char c)
+{
+        int j;
+
+        for (j = 0; j < 0x1000; j++) {
+                if (UART_BASE[UART_LSR] & UART_LSR_THRE)
+                        break;
+                barrier();
+        }
+
+        UART_BASE[UART_TX] = c;
+}
+
+static inline void flush(void)
+{
+}
+
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
+
+
+#endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/vmalloc.h b/arch/arm/mach-ixp23xx/include/mach/vmalloc.h
new file mode 100644
index 000000000000..dd519f678d10
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/include/mach/vmalloc.h
@@ -0,0 +1,10 @@
+/*
+ * arch/arm/mach-ixp23xx/include/mach/vmalloc.h
+ *
+ * Copyright (c) 2005 MontaVista Software, Inc.
+ *
+ * NPU mappings end at 0xf0000000 and we allocate 64MB for board
+ * specific static I/O.
+ */
+
+#define VMALLOC_END     (0xec000000)
diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c
index d510160d4722..b6e0bfa44df9 100644
--- a/arch/arm/mach-ixp23xx/ixdp2351.c
+++ b/arch/arm/mach-ixp23xx/ixdp2351.c
@@ -34,7 +34,7 @@
 #include <asm/types.h>
 #include <asm/setup.h>
 #include <asm/memory.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/system.h>
 #include <asm/tlbflush.h>
diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c
index c84cc6b140ac..701d60aa0efd 100644
--- a/arch/arm/mach-ixp23xx/pci.c
+++ b/arch/arm/mach-ixp23xx/pci.c
@@ -31,7 +31,7 @@
 #include <asm/sizes.h>
 #include <asm/system.h>
 #include <asm/mach/pci.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 extern int (*external_fault) (unsigned long, struct pt_regs *);
 
diff --git a/arch/arm/mach-ixp23xx/roadrunner.c b/arch/arm/mach-ixp23xx/roadrunner.c
index c461520d79c6..6d38d769761c 100644
--- a/arch/arm/mach-ixp23xx/roadrunner.c
+++ b/arch/arm/mach-ixp23xx/roadrunner.c
@@ -33,7 +33,7 @@
 #include <asm/types.h>
 #include <asm/setup.h>
 #include <asm/memory.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
 #include <asm/system.h>
diff --git a/arch/arm/mach-ixp4xx/avila-pci.c b/arch/arm/mach-ixp4xx/avila-pci.c
index 8d549daba1e9..08d65dcdb5fe 100644
--- a/arch/arm/mach-ixp4xx/avila-pci.c
+++ b/arch/arm/mach-ixp4xx/avila-pci.c
@@ -25,7 +25,7 @@
 
 #include <asm/mach/pci.h>
 #include <asm/irq.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 
 void __init avila_pci_preinit(void)
diff --git a/arch/arm/mach-ixp4xx/avila-setup.c b/arch/arm/mach-ixp4xx/avila-setup.c
index 87e38ca18a27..797995ce18b9 100644
--- a/arch/arm/mach-ixp4xx/avila-setup.c
+++ b/arch/arm/mach-ixp4xx/avila-setup.c
@@ -23,7 +23,7 @@
 #include <asm/types.h>
 #include <asm/setup.h>
 #include <asm/memory.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index 3b32f7014bf6..192538a04575 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -32,7 +32,7 @@
 #include <asm/sizes.h>
 #include <asm/system.h>
 #include <asm/mach/pci.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 
 /*
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 00cede2b7a42..58bd2842a6f1 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -29,8 +29,8 @@
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
 
-#include <asm/arch/udc.h>
-#include <asm/arch/hardware.h>
+#include <mach/udc.h>
+#include <mach/hardware.h>
 #include <asm/uaccess.h>
 #include <asm/io.h>
 #include <asm/pgtable.h>
diff --git a/arch/arm/mach-ixp4xx/coyote-pci.c b/arch/arm/mach-ixp4xx/coyote-pci.c
index 6dd400f55e44..efddf01ed17b 100644
--- a/arch/arm/mach-ixp4xx/coyote-pci.c
+++ b/arch/arm/mach-ixp4xx/coyote-pci.c
@@ -20,7 +20,7 @@
 #include <linux/irq.h>
 
 #include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 
 #include <asm/mach/pci.h>
diff --git a/arch/arm/mach-ixp4xx/coyote-setup.c b/arch/arm/mach-ixp4xx/coyote-setup.c
index 66acd55346cb..aab1954e2747 100644
--- a/arch/arm/mach-ixp4xx/coyote-setup.c
+++ b/arch/arm/mach-ixp4xx/coyote-setup.c
@@ -19,7 +19,7 @@
 #include <asm/types.h>
 #include <asm/setup.h>
 #include <asm/memory.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-ixp4xx/gateway7001-pci.c b/arch/arm/mach-ixp4xx/gateway7001-pci.c
index 07ee00c05edd..7e93a0975c4d 100644
--- a/arch/arm/mach-ixp4xx/gateway7001-pci.c
+++ b/arch/arm/mach-ixp4xx/gateway7001-pci.c
@@ -23,7 +23,7 @@
 #include <linux/irq.h>
 
 #include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 #include <asm/mach/pci.h>
 
diff --git a/arch/arm/mach-ixp4xx/gateway7001-setup.c b/arch/arm/mach-ixp4xx/gateway7001-setup.c
index 80044e8b90b2..59b73a0ddfa9 100644
--- a/arch/arm/mach-ixp4xx/gateway7001-setup.c
+++ b/arch/arm/mach-ixp4xx/gateway7001-setup.c
@@ -22,7 +22,7 @@
 #include <asm/types.h>
 #include <asm/setup.h>
 #include <asm/memory.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-pci.c b/arch/arm/mach-ixp4xx/gtwx5715-pci.c
index 241bb5f2f424..7b8a2c323840 100644
--- a/arch/arm/mach-ixp4xx/gtwx5715-pci.c
+++ b/arch/arm/mach-ixp4xx/gtwx5715-pci.c
@@ -28,8 +28,8 @@
 #include <linux/irq.h>
 
 #include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/gtwx5715.h>
+#include <mach/hardware.h>
+#include <mach/gtwx5715.h>
 #include <asm/mach/pci.h>
 
 /*
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-setup.c b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
index ef21bfb3359a..25c21d6665ec 100644
--- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c
+++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
@@ -32,12 +32,12 @@
 #include <asm/types.h>
 #include <asm/setup.h>
 #include <asm/memory.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
-#include <asm/arch/gtwx5715.h>
+#include <mach/gtwx5715.h>
 
 /*
  * Xscale UART registers are 32 bits wide with only the least
diff --git a/arch/arm/mach-ixp4xx/include/mach/avila.h b/arch/arm/mach-ixp4xx/include/mach/avila.h
new file mode 100644
index 000000000000..1640cb61972b
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/avila.h
@@ -0,0 +1,39 @@
+/*
+ * arch/arm/mach-ixp4xx/include/mach/avila.h
+ *
+ * Gateworks Avila platform specific definitions
+ *
+ * Author: Michael-Luke Jones <mlj28@cam.ac.uk>
+ *
+ * Based on ixdp425.h
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright 2004 (c) MontaVista, Software, Inc.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H__
+#error "Do not include this directly, instead #include <mach/hardware.h>"
+#endif
+
+#define AVILA_SDA_PIN           7
+#define AVILA_SCL_PIN           6
+
+/*
+ * AVILA PCI IRQs
+ */
+#define AVILA_PCI_MAX_DEV       4
+#define LOFT_PCI_MAX_DEV    6
+#define AVILA_PCI_IRQ_LINES     4
+
+
+/* PCI controller GPIO to IRQ pin mappings */
+#define AVILA_PCI_INTA_PIN      11
+#define AVILA_PCI_INTB_PIN      10
+#define AVILA_PCI_INTC_PIN      9
+#define AVILA_PCI_INTD_PIN      8
+
+
diff --git a/arch/arm/mach-ixp4xx/include/mach/coyote.h b/arch/arm/mach-ixp4xx/include/mach/coyote.h
new file mode 100644
index 000000000000..717ac6d16f55
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/coyote.h
@@ -0,0 +1,33 @@
+/*
+ * arch/arm/mach-ixp4xx/include/mach/coyote.h
+ *
+ * ADI Engineering platform specific definitions
+ *
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright 2004 (c) MontaVista, Software, Inc. 
+ * 
+ * This file is licensed under  the terms of the GNU General Public 
+ * License version 2. This program is licensed "as is" without any 
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H__
+#error "Do not include this directly, instead #include <mach/hardware.h>"
+#endif
+
+/* PCI controller GPIO to IRQ pin mappings */
+#define COYOTE_PCI_SLOT0_PIN    6
+#define COYOTE_PCI_SLOT1_PIN    11
+
+#define COYOTE_PCI_SLOT0_DEVID  14
+#define COYOTE_PCI_SLOT1_DEVID  15
+
+#define COYOTE_IDE_BASE_PHYS    IXP4XX_EXP_BUS_BASE(3)
+#define COYOTE_IDE_BASE_VIRT    0xFFFE1000
+#define COYOTE_IDE_REGION_SIZE  0x1000
+
+#define COYOTE_IDE_DATA_PORT    0xFFFE10E0
+#define COYOTE_IDE_CTRL_PORT    0xFFFE10FC
+#define COYOTE_IDE_ERROR_PORT   0xFFFE10E2
+
diff --git a/arch/arm/mach-ixp4xx/include/mach/cpu.h b/arch/arm/mach-ixp4xx/include/mach/cpu.h
new file mode 100644
index 000000000000..ff8aa2393bf9
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/cpu.h
@@ -0,0 +1,46 @@
+/*
+ * arch/arm/mach-ixp4xx/include/mach/cpu.h
+ *
+ * IXP4XX cpu type detection
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_CPU_H__
+#define __ASM_ARCH_CPU_H__
+
+extern unsigned int processor_id;
+/* Processor id value in CP15 Register 0 */
+#define IXP425_PROCESSOR_ID_VALUE       0x690541c0
+#define IXP435_PROCESSOR_ID_VALUE       0x69054040
+#define IXP465_PROCESSOR_ID_VALUE       0x69054200
+#define IXP4XX_PROCESSOR_ID_MASK        0xfffffff0
+
+#define cpu_is_ixp42x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \
+                          IXP425_PROCESSOR_ID_VALUE)
+#define cpu_is_ixp43x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \
+                          IXP435_PROCESSOR_ID_VALUE)
+#define cpu_is_ixp46x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \
+                          IXP465_PROCESSOR_ID_VALUE)
+
+static inline u32 ixp4xx_read_feature_bits(void)
+{
+        unsigned int val = ~*IXP4XX_EXP_CFG2;
+        val &= ~IXP4XX_FEATURE_RESERVED;
+        if (!cpu_is_ixp46x())
+                val &= ~IXP4XX_FEATURE_IXP46X_ONLY;
+
+        return val;
+}
+
+static inline void ixp4xx_write_feature_bits(u32 value)
+{
+        *IXP4XX_EXP_CFG2 = ~value;
+}
+
+#endif  /* _ASM_ARCH_CPU_H */
diff --git a/arch/arm/mach-ixp4xx/include/mach/debug-macro.S b/arch/arm/mach-ixp4xx/include/mach/debug-macro.S
new file mode 100644
index 000000000000..7c6a6912acde
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/debug-macro.S
@@ -0,0 +1,24 @@
+/* arch/arm/mach-ixp4xx/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx, #0xc8000000
+                movne   \rx, #0xff000000
+                orrne   \rx, \rx, #0x00b00000
+                add     \rx,\rx,#3              @ Uart regs are at off set of 3 if
+                                                @ byte writes used - Big Endian.
+                .endm
+
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-ixp4xx/include/mach/dma.h b/arch/arm/mach-ixp4xx/include/mach/dma.h
new file mode 100644
index 000000000000..00c5070c0201
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/dma.h
@@ -0,0 +1,21 @@
+/*
+ * arch/arm/mach-ixp4xx/include/mach/dma.h
+ *
+ * Copyright (C) 2001-2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+#include <linux/device.h>
+#include <asm/page.h>
+#include <asm/sizes.h>
+#include <mach/hardware.h>
+
+#define MAX_DMA_ADDRESS         (PAGE_OFFSET + SZ_64M)
+
+#endif /* _ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-ixp4xx/include/mach/dsmg600.h b/arch/arm/mach-ixp4xx/include/mach/dsmg600.h
new file mode 100644
index 000000000000..dc087a34a268
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/dsmg600.h
@@ -0,0 +1,52 @@
+/*
+ * DSM-G600 platform specific definitions
+ *
+ * Copyright (C) 2006 Tower Technologies
+ * Author: Alessandro Zummo <a.zummo@towertech.it>
+ *
+ * based on ixdp425.h:
+ *      Copyright 2004 (C) MontaVista, Software, Inc.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H__
+#error "Do not include this directly, instead #include <mach/hardware.h>"
+#endif
+
+#define DSMG600_SDA_PIN         5
+#define DSMG600_SCL_PIN         4
+
+/*
+ * DSMG600 PCI IRQs
+ */
+#define DSMG600_PCI_MAX_DEV     4
+#define DSMG600_PCI_IRQ_LINES   3
+
+
+/* PCI controller GPIO to IRQ pin mappings */
+#define DSMG600_PCI_INTA_PIN    11
+#define DSMG600_PCI_INTB_PIN    10
+#define DSMG600_PCI_INTC_PIN    9
+#define DSMG600_PCI_INTD_PIN    8
+#define DSMG600_PCI_INTE_PIN    7
+#define DSMG600_PCI_INTF_PIN    6
+
+/* DSM-G600 Timer Setting */
+#define DSMG600_FREQ 66000000
+
+/* Buttons */
+
+#define DSMG600_PB_GPIO         15      /* power button */
+#define DSMG600_RB_GPIO         3       /* reset button */
+
+/* Power control */
+
+#define DSMG600_PO_GPIO         2       /* power off */
+
+/* LEDs */
+
+#define DSMG600_LED_PWR_GPIO    0
+#define DSMG600_LED_WLAN_GPIO   14
diff --git a/arch/arm/mach-ixp4xx/include/mach/entry-macro.S b/arch/arm/mach-ixp4xx/include/mach/entry-macro.S
new file mode 100644
index 000000000000..f2e14e94ed15
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/entry-macro.S
@@ -0,0 +1,47 @@
+/*
+ * arch/arm/mach-ixp4xx/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for IXP4xx-based platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <mach/hardware.h>
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_preamble, base, tmp
+                .endm
+
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                ldr     \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP_OFFSET)
+                ldr     \irqstat, [\irqstat]            @ get interrupts
+                cmp     \irqstat, #0
+                beq     1001f                           @ upper IRQ?
+                clz     \irqnr, \irqstat
+                mov     \base, #31
+                sub     \irqnr, \base, \irqnr
+                b       1002f                           @ lower IRQ being
+                                                        @ handled
+
+1001:
+                /*
+                 * IXP465/IXP435 has an upper IRQ status register
+                 */
+#if defined(CONFIG_CPU_IXP46X) || defined(CONFIG_CPU_IXP43X)
+                ldr     \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP2_OFFSET)
+                ldr     \irqstat, [\irqstat]            @ get upper interrupts
+                mov     \irqnr, #63
+                clz     \irqstat, \irqstat
+                cmp     \irqstat, #32
+                subne   \irqnr, \irqnr, \irqstat
+#endif
+1002:
+                .endm
+
+
diff --git a/arch/arm/mach-ixp4xx/include/mach/fsg.h b/arch/arm/mach-ixp4xx/include/mach/fsg.h
new file mode 100644
index 000000000000..1f02b7e22a13
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/fsg.h
@@ -0,0 +1,50 @@
+/*
+ * arch/arm/mach-ixp4xx/include/mach/fsg.h
+ *
+ * Freecom FSG-3 platform specific definitions
+ *
+ * Author: Rod Whitby <rod@whitby.id.au>
+ * Author: Tomasz Chmielewski <mangoo@wpkg.org>
+ * Maintainers: http://www.nslu2-linux.org
+ *
+ * Based on coyote.h by
+ * Copyright 2004 (c) MontaVista, Software, Inc.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H__
+#error "Do not include this directly, instead #include <mach/hardware.h>"
+#endif
+
+#define FSG_SDA_PIN             12
+#define FSG_SCL_PIN             13
+
+/*
+ * FSG PCI IRQs
+ */
+#define FSG_PCI_MAX_DEV         3
+#define FSG_PCI_IRQ_LINES       3
+
+
+/* PCI controller GPIO to IRQ pin mappings */
+#define FSG_PCI_INTA_PIN        6
+#define FSG_PCI_INTB_PIN        7
+#define FSG_PCI_INTC_PIN        5
+
+/* Buttons */
+
+#define FSG_SB_GPIO             4       /* sync button */
+#define FSG_RB_GPIO             9       /* reset button */
+#define FSG_UB_GPIO             10      /* usb button */
+
+/* LEDs */
+
+#define FSG_LED_WLAN_BIT        0
+#define FSG_LED_WAN_BIT         1
+#define FSG_LED_SATA_BIT        2
+#define FSG_LED_USB_BIT         4
+#define FSG_LED_RING_BIT        5
+#define FSG_LED_SYNC_BIT        7
diff --git a/arch/arm/mach-ixp4xx/include/mach/gpio.h b/arch/arm/mach-ixp4xx/include/mach/gpio.h
new file mode 100644
index 000000000000..9fbde177920f
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/gpio.h
@@ -0,0 +1,73 @@
+/*
+ * arch/arm/mach-ixp4xx/include/mach/gpio.h
+ *
+ * IXP4XX GPIO wrappers for arch-neutral GPIO calls
+ *
+ * Written by Milan Svoboda <msvoboda@ra.rockwell.com>
+ * Based on PXA implementation by Philipp Zabel <philipp.zabel@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARCH_IXP4XX_GPIO_H
+#define __ASM_ARCH_IXP4XX_GPIO_H
+
+#include <mach/hardware.h>
+
+static inline int gpio_request(unsigned gpio, const char *label)
+{
+        return 0;
+}
+
+static inline void gpio_free(unsigned gpio)
+{
+        return;
+}
+
+static inline int gpio_direction_input(unsigned gpio)
+{
+        gpio_line_config(gpio, IXP4XX_GPIO_IN);
+        return 0;
+}
+
+static inline int gpio_direction_output(unsigned gpio, int level)
+{
+        gpio_line_set(gpio, level);
+        gpio_line_config(gpio, IXP4XX_GPIO_OUT);
+        return 0;
+}
+
+static inline int gpio_get_value(unsigned gpio)
+{
+        int value;
+
+        gpio_line_get(gpio, &value);
+
+        return value;
+}
+
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+        gpio_line_set(gpio, value);
+}
+
+#include <asm-generic/gpio.h>                   /* cansleep wrappers */
+
+extern int gpio_to_irq(int gpio);
+extern int irq_to_gpio(int gpio);
+
+#endif
+
diff --git a/arch/arm/mach-ixp4xx/include/mach/gtwx5715.h b/arch/arm/mach-ixp4xx/include/mach/gtwx5715.h
new file mode 100644
index 000000000000..5d5e201cac7e
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/gtwx5715.h
@@ -0,0 +1,116 @@
+/*
+ * arch/arm/mach-ixp4xx/include/mach/gtwx5715.h
+ *
+ * Gemtek GTWX5715 Gateway (Linksys WRV54G)
+ *
+ * Copyright 2004 (c) George T. Joseph
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H__
+#error "Do not include this directly, instead #include <mach/hardware.h>"
+#endif
+#include "irqs.h"
+
+#define GTWX5715_GPIO0  0
+#define GTWX5715_GPIO1  1
+#define GTWX5715_GPIO2  2
+#define GTWX5715_GPIO3  3
+#define GTWX5715_GPIO4  4
+#define GTWX5715_GPIO5  5
+#define GTWX5715_GPIO6  6
+#define GTWX5715_GPIO7  7
+#define GTWX5715_GPIO8  8
+#define GTWX5715_GPIO9  9
+#define GTWX5715_GPIO10 10
+#define GTWX5715_GPIO11 11
+#define GTWX5715_GPIO12 12
+#define GTWX5715_GPIO13 13
+#define GTWX5715_GPIO14 14
+
+#define GTWX5715_GPIO0_IRQ                      IRQ_IXP4XX_GPIO0
+#define GTWX5715_GPIO1_IRQ                      IRQ_IXP4XX_GPIO1
+#define GTWX5715_GPIO2_IRQ                      IRQ_IXP4XX_GPIO2
+#define GTWX5715_GPIO3_IRQ                      IRQ_IXP4XX_GPIO3
+#define GTWX5715_GPIO4_IRQ                      IRQ_IXP4XX_GPIO4
+#define GTWX5715_GPIO5_IRQ                      IRQ_IXP4XX_GPIO5
+#define GTWX5715_GPIO6_IRQ                      IRQ_IXP4XX_GPIO6
+#define GTWX5715_GPIO7_IRQ                      IRQ_IXP4XX_GPIO7
+#define GTWX5715_GPIO8_IRQ                      IRQ_IXP4XX_GPIO8
+#define GTWX5715_GPIO9_IRQ                      IRQ_IXP4XX_GPIO9
+#define GTWX5715_GPIO10_IRQ             IRQ_IXP4XX_GPIO10
+#define GTWX5715_GPIO11_IRQ             IRQ_IXP4XX_GPIO11
+#define GTWX5715_GPIO12_IRQ             IRQ_IXP4XX_GPIO12
+#define GTWX5715_GPIO13_IRQ             IRQ_IXP4XX_SW_INT1
+#define GTWX5715_GPIO14_IRQ             IRQ_IXP4XX_SW_INT2
+
+/* PCI controller GPIO to IRQ pin mappings
+
+                        INTA    INTB
+SLOT 0  10              11
+SLOT 1  11              10
+
+*/
+
+#define GTWX5715_PCI_SLOT0_DEVID        0
+#define GTWX5715_PCI_SLOT0_INTA_GPIO    GTWX5715_GPIO10
+#define GTWX5715_PCI_SLOT0_INTB_GPIO    GTWX5715_GPIO11
+#define GTWX5715_PCI_SLOT0_INTA_IRQ     GTWX5715_GPIO10_IRQ
+#define GTWX5715_PCI_SLOT0_INTB_IRQ     GTWX5715_GPIO11_IRQ
+
+#define GTWX5715_PCI_SLOT1_DEVID        1
+#define GTWX5715_PCI_SLOT1_INTA_GPIO    GTWX5715_GPIO11
+#define GTWX5715_PCI_SLOT1_INTB_GPIO    GTWX5715_GPIO10
+#define GTWX5715_PCI_SLOT1_INTA_IRQ     GTWX5715_GPIO11_IRQ
+#define GTWX5715_PCI_SLOT1_INTB_IRQ     GTWX5715_GPIO10_IRQ
+
+#define GTWX5715_PCI_SLOT_COUNT                 2
+#define GTWX5715_PCI_INT_PIN_COUNT              2
+
+/*
+ * GPIO 5,6,7 and12 are hard wired to the Kendin KS8995M Switch
+ * and operate as an SPI type interface.  The details of the interface
+ * are available on Kendin/Micrel's web site.
+ */
+
+#define GTWX5715_KSSPI_SELECT   GTWX5715_GPIO5
+#define GTWX5715_KSSPI_TXD              GTWX5715_GPIO6
+#define GTWX5715_KSSPI_CLOCK    GTWX5715_GPIO7
+#define GTWX5715_KSSPI_RXD              GTWX5715_GPIO12
+
+/*
+ * The "reset" button is wired to GPIO 3.
+ * The GPIO is brought "low" when the button is pushed.
+ */
+
+#define GTWX5715_BUTTON_GPIO    GTWX5715_GPIO3
+#define GTWX5715_BUTTON_IRQ     GTWX5715_GPIO3_IRQ
+
+/*
+ *  Board Label      Front Label
+ *  LED1             Power
+ *  LED2             Wireless-G
+ *  LED3             not populated but could be
+ *  LED4             Internet
+ *  LED5 - LED8      Controlled by KS8995M Switch
+ *  LED9             DMZ
+ */
+
+#define GTWX5715_LED1_GPIO              GTWX5715_GPIO2
+#define GTWX5715_LED2_GPIO              GTWX5715_GPIO9
+#define GTWX5715_LED3_GPIO              GTWX5715_GPIO8
+#define GTWX5715_LED4_GPIO              GTWX5715_GPIO1
+#define GTWX5715_LED9_GPIO              GTWX5715_GPIO4
diff --git a/arch/arm/mach-ixp4xx/include/mach/hardware.h b/arch/arm/mach-ixp4xx/include/mach/hardware.h
new file mode 100644
index 000000000000..f58a43a23966
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/hardware.h
@@ -0,0 +1,50 @@
+/*
+ * arch/arm/mach-ixp4xx/include/mach/hardware.h 
+ *
+ * Copyright (C) 2002 Intel Corporation.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+/*
+ * Hardware definitions for IXP4xx based systems
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H__
+#define __ASM_ARCH_HARDWARE_H__
+
+#define PCIBIOS_MIN_IO          0x00001000
+#define PCIBIOS_MIN_MEM         (cpu_is_ixp43x() ? 0x40000000 : 0x48000000)
+
+/*
+ * We override the standard dma-mask routines for bouncing.
+ */
+#define HAVE_ARCH_PCI_SET_DMA_MASK
+
+#define pcibios_assign_all_busses()     1
+
+/* Register locations and bits */
+#include "ixp4xx-regs.h"
+
+#ifndef __ASSEMBLER__
+#include <mach/cpu.h>
+#endif
+
+/* Platform helper functions and definitions */
+#include "platform.h"
+
+/* Platform specific details */
+#include "ixdp425.h"
+#include "avila.h"
+#include "coyote.h"
+#include "prpmc1100.h"
+#include "nslu2.h"
+#include "nas100d.h"
+#include "dsmg600.h"
+#include "fsg.h"
+
+#endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h
new file mode 100644
index 000000000000..319948e31bec
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/io.h
@@ -0,0 +1,569 @@
+/*
+ * arch/arm/mach-ixp4xx/include/mach/io.h
+ *
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright (C) 2002-2005  MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#include <linux/bitops.h>
+
+#include <mach/hardware.h>
+
+#define IO_SPACE_LIMIT 0xffff0000
+
+extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
+extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
+
+
+/*
+ * IXP4xx provides two methods of accessing PCI memory space:
+ *
+ * 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB).
+ *    To access PCI via this space, we simply ioremap() the BAR
+ *    into the kernel and we can use the standard read[bwl]/write[bwl]
+ *    macros. This is the preffered method due to speed but it
+ *    limits the system to just 64MB of PCI memory. This can be 
+ *    problamatic if using video cards and other memory-heavy
+ *    targets.
+ *
+ * 2) If > 64MB of memory space is required, the IXP4xx can be configured
+ *    to use indirect registers to access PCI (as we do below for I/O
+ *    transactions). This allows for up to 128MB (0x48000000 to 0x4fffffff)
+ *    of memory on the bus. The disadvantage of this is that every 
+ *    PCI access requires three local register accesses plus a spinlock,
+ *    but in some cases the performance hit is acceptable. In addition,
+ *    you cannot mmap() PCI devices in this case.
+ *
+ */
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+
+#define __mem_pci(a)            (a)
+
+#else
+
+#include <linux/mm.h>
+
+/*
+ * In the case of using indirect PCI, we simply return the actual PCI
+ * address and our read/write implementation use that to drive the 
+ * access registers. If something outside of PCI is ioremap'd, we
+ * fallback to the default.
+ */
+static inline void __iomem *
+__ixp4xx_ioremap(unsigned long addr, size_t size, unsigned int mtype)
+{
+        if((addr < PCIBIOS_MIN_MEM) || (addr > 0x4fffffff))
+                return __arm_ioremap(addr, size, mtype);
+
+        return (void __iomem *)addr;
+}
+
+static inline void
+__ixp4xx_iounmap(void __iomem *addr)
+{
+        if ((__force u32)addr >= VMALLOC_START)
+                __iounmap(addr);
+}
+
+#define __arch_ioremap(a, s, f)         __ixp4xx_ioremap(a, s, f)
+#define __arch_iounmap(a)               __ixp4xx_iounmap(a)
+
+#define writeb(v, p)                    __ixp4xx_writeb(v, p)
+#define writew(v, p)                    __ixp4xx_writew(v, p)
+#define writel(v, p)                    __ixp4xx_writel(v, p)
+
+#define writesb(p, v, l)                __ixp4xx_writesb(p, v, l)
+#define writesw(p, v, l)                __ixp4xx_writesw(p, v, l)
+#define writesl(p, v, l)                __ixp4xx_writesl(p, v, l)
+        
+#define readb(p)                        __ixp4xx_readb(p)
+#define readw(p)                        __ixp4xx_readw(p)
+#define readl(p)                        __ixp4xx_readl(p)
+        
+#define readsb(p, v, l)                 __ixp4xx_readsb(p, v, l)
+#define readsw(p, v, l)                 __ixp4xx_readsw(p, v, l)
+#define readsl(p, v, l)                 __ixp4xx_readsl(p, v, l)
+
+static inline void 
+__ixp4xx_writeb(u8 value, volatile void __iomem *p)
+{
+        u32 addr = (u32)p;
+        u32 n, byte_enables, data;
+
+        if (addr >= VMALLOC_START) {
+                __raw_writeb(value, addr);
+                return;
+        }
+
+        n = addr % 4;
+        byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
+        data = value << (8*n);
+        ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
+}
+
+static inline void
+__ixp4xx_writesb(volatile void __iomem *bus_addr, const u8 *vaddr, int count)
+{
+        while (count--)
+                writeb(*vaddr++, bus_addr);
+}
+
+static inline void 
+__ixp4xx_writew(u16 value, volatile void __iomem *p)
+{
+        u32 addr = (u32)p;
+        u32 n, byte_enables, data;
+
+        if (addr >= VMALLOC_START) {
+                __raw_writew(value, addr);
+                return;
+        }
+
+        n = addr % 4;
+        byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
+        data = value << (8*n);
+        ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
+}
+
+static inline void
+__ixp4xx_writesw(volatile void __iomem *bus_addr, const u16 *vaddr, int count)
+{
+        while (count--)
+                writew(*vaddr++, bus_addr);
+}
+
+static inline void 
+__ixp4xx_writel(u32 value, volatile void __iomem *p)
+{
+        u32 addr = (__force u32)p;
+        if (addr >= VMALLOC_START) {
+                __raw_writel(value, p);
+                return;
+        }
+
+        ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value);
+}
+
+static inline void
+__ixp4xx_writesl(volatile void __iomem *bus_addr, const u32 *vaddr, int count)
+{
+        while (count--)
+                writel(*vaddr++, bus_addr);
+}
+
+static inline unsigned char 
+__ixp4xx_readb(const volatile void __iomem *p)
+{
+        u32 addr = (u32)p;
+        u32 n, byte_enables, data;
+
+        if (addr >= VMALLOC_START)
+                return __raw_readb(addr);
+
+        n = addr % 4;
+        byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
+        if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data))
+                return 0xff;
+
+        return data >> (8*n);
+}
+
+static inline void
+__ixp4xx_readsb(const volatile void __iomem *bus_addr, u8 *vaddr, u32 count)
+{
+        while (count--)
+                *vaddr++ = readb(bus_addr);
+}
+
+static inline unsigned short 
+__ixp4xx_readw(const volatile void __iomem *p)
+{
+        u32 addr = (u32)p;
+        u32 n, byte_enables, data;
+
+        if (addr >= VMALLOC_START)
+                return __raw_readw(addr);
+
+        n = addr % 4;
+        byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
+        if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data))
+                return 0xffff;
+
+        return data>>(8*n);
+}
+
+static inline void 
+__ixp4xx_readsw(const volatile void __iomem *bus_addr, u16 *vaddr, u32 count)
+{
+        while (count--)
+                *vaddr++ = readw(bus_addr);
+}
+
+static inline unsigned long 
+__ixp4xx_readl(const volatile void __iomem *p)
+{
+        u32 addr = (__force u32)p;
+        u32 data;
+
+        if (addr >= VMALLOC_START)
+                return __raw_readl(p);
+
+        if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data))
+                return 0xffffffff;
+
+        return data;
+}
+
+static inline void 
+__ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count)
+{
+        while (count--)
+                *vaddr++ = readl(bus_addr);
+}
+
+
+/*
+ * We can use the built-in functions b/c they end up calling writeb/readb
+ */
+#define memset_io(c,v,l)                _memset_io((c),(v),(l))
+#define memcpy_fromio(a,c,l)            _memcpy_fromio((a),(c),(l))
+#define memcpy_toio(c,a,l)              _memcpy_toio((c),(a),(l))
+
+#endif
+
+#ifndef CONFIG_PCI
+
+#define __io(v)         v
+
+#else
+
+/*
+ * IXP4xx does not have a transparent cpu -> PCI I/O translation
+ * window.  Instead, it has a set of registers that must be tweaked
+ * with the proper byte lanes, command types, and address for the
+ * transaction.  This means that we need to override the default
+ * I/O functions.
+ */
+#define outb(p, v)                      __ixp4xx_outb(p, v)
+#define outw(p, v)                      __ixp4xx_outw(p, v)
+#define outl(p, v)                      __ixp4xx_outl(p, v)
+        
+#define outsb(p, v, l)                  __ixp4xx_outsb(p, v, l)
+#define outsw(p, v, l)                  __ixp4xx_outsw(p, v, l)
+#define outsl(p, v, l)                  __ixp4xx_outsl(p, v, l)
+
+#define inb(p)                          __ixp4xx_inb(p)
+#define inw(p)                          __ixp4xx_inw(p)
+#define inl(p)                          __ixp4xx_inl(p)
+
+#define insb(p, v, l)                   __ixp4xx_insb(p, v, l)
+#define insw(p, v, l)                   __ixp4xx_insw(p, v, l)
+#define insl(p, v, l)                   __ixp4xx_insl(p, v, l)
+
+
+static inline void 
+__ixp4xx_outb(u8 value, u32 addr)
+{
+        u32 n, byte_enables, data;
+        n = addr % 4;
+        byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
+        data = value << (8*n);
+        ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
+}
+
+static inline void 
+__ixp4xx_outsb(u32 io_addr, const u8 *vaddr, u32 count)
+{
+        while (count--)
+                outb(*vaddr++, io_addr);
+}
+
+static inline void 
+__ixp4xx_outw(u16 value, u32 addr)
+{
+        u32 n, byte_enables, data;
+        n = addr % 4;
+        byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
+        data = value << (8*n);
+        ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
+}
+
+static inline void 
+__ixp4xx_outsw(u32 io_addr, const u16 *vaddr, u32 count)
+{
+        while (count--)
+                outw(cpu_to_le16(*vaddr++), io_addr);
+}
+
+static inline void 
+__ixp4xx_outl(u32 value, u32 addr)
+{
+        ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value);
+}
+
+static inline void 
+__ixp4xx_outsl(u32 io_addr, const u32 *vaddr, u32 count)
+{
+        while (count--)
+                outl(*vaddr++, io_addr);
+}
+
+static inline u8 
+__ixp4xx_inb(u32 addr)
+{
+        u32 n, byte_enables, data;
+        n = addr % 4;
+        byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
+        if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data))
+                return 0xff;
+
+        return data >> (8*n);
+}
+
+static inline void 
+__ixp4xx_insb(u32 io_addr, u8 *vaddr, u32 count)
+{
+        while (count--)
+                *vaddr++ = inb(io_addr);
+}
+
+static inline u16 
+__ixp4xx_inw(u32 addr)
+{
+        u32 n, byte_enables, data;
+        n = addr % 4;
+        byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
+        if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data))
+                return 0xffff;
+
+        return data>>(8*n);
+}
+
+static inline void 
+__ixp4xx_insw(u32 io_addr, u16 *vaddr, u32 count)
+{
+        while (count--)
+                *vaddr++ = le16_to_cpu(inw(io_addr));
+}
+
+static inline u32 
+__ixp4xx_inl(u32 addr)
+{
+        u32 data;
+        if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data))
+                return 0xffffffff;
+
+        return data;
+}
+
+static inline void 
+__ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count)
+{
+        while (count--)
+                *vaddr++ = inl(io_addr);
+}
+
+#define PIO_OFFSET      0x10000UL
+#define PIO_MASK        0x0ffffUL
+
+#define __is_io_address(p)      (((unsigned long)p >= PIO_OFFSET) && \
+                                        ((unsigned long)p <= (PIO_MASK + PIO_OFFSET)))
+static inline unsigned int
+__ixp4xx_ioread8(const void __iomem *addr)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                return  (unsigned int)__ixp4xx_inb(port & PIO_MASK);
+        else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                return (unsigned int)__raw_readb(port);
+#else
+                return (unsigned int)__ixp4xx_readb(addr);
+#endif
+}
+
+static inline void
+__ixp4xx_ioread8_rep(const void __iomem *addr, void *vaddr, u32 count)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                __ixp4xx_insb(port & PIO_MASK, vaddr, count);
+        else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                __raw_readsb(addr, vaddr, count);
+#else
+                __ixp4xx_readsb(addr, vaddr, count);
+#endif
+}
+
+static inline unsigned int
+__ixp4xx_ioread16(const void __iomem *addr)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                return  (unsigned int)__ixp4xx_inw(port & PIO_MASK);
+        else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                return le16_to_cpu(__raw_readw((u32)port));
+#else
+                return (unsigned int)__ixp4xx_readw(addr);
+#endif
+}
+
+static inline void
+__ixp4xx_ioread16_rep(const void __iomem *addr, void *vaddr, u32 count)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                __ixp4xx_insw(port & PIO_MASK, vaddr, count);
+        else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                __raw_readsw(addr, vaddr, count);
+#else
+                __ixp4xx_readsw(addr, vaddr, count);
+#endif
+}
+
+static inline unsigned int
+__ixp4xx_ioread32(const void __iomem *addr)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                return  (unsigned int)__ixp4xx_inl(port & PIO_MASK);
+        else {
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                return le32_to_cpu((__force __le32)__raw_readl(addr));
+#else
+                return (unsigned int)__ixp4xx_readl(addr);
+#endif
+        }
+}
+
+static inline void
+__ixp4xx_ioread32_rep(const void __iomem *addr, void *vaddr, u32 count)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                __ixp4xx_insl(port & PIO_MASK, vaddr, count);
+        else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                __raw_readsl(addr, vaddr, count);
+#else
+                __ixp4xx_readsl(addr, vaddr, count);
+#endif
+}
+
+static inline void
+__ixp4xx_iowrite8(u8 value, void __iomem *addr)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                __ixp4xx_outb(value, port & PIO_MASK);
+        else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                __raw_writeb(value, port);
+#else
+                __ixp4xx_writeb(value, addr);
+#endif
+}
+
+static inline void
+__ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                __ixp4xx_outsb(port & PIO_MASK, vaddr, count);
+        else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                __raw_writesb(addr, vaddr, count);
+#else
+                __ixp4xx_writesb(addr, vaddr, count);
+#endif
+}
+
+static inline void
+__ixp4xx_iowrite16(u16 value, void __iomem *addr)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                __ixp4xx_outw(value, port & PIO_MASK);
+        else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                __raw_writew(cpu_to_le16(value), addr);
+#else
+                __ixp4xx_writew(value, addr);
+#endif
+}
+
+static inline void
+__ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                __ixp4xx_outsw(port & PIO_MASK, vaddr, count);
+        else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                __raw_writesw(addr, vaddr, count);
+#else
+                __ixp4xx_writesw(addr, vaddr, count);
+#endif
+}
+
+static inline void
+__ixp4xx_iowrite32(u32 value, void __iomem *addr)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                __ixp4xx_outl(value, port & PIO_MASK);
+        else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                __raw_writel((u32 __force)cpu_to_le32(value), addr);
+#else
+                __ixp4xx_writel(value, addr);
+#endif
+}
+
+static inline void
+__ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count)
+{
+        unsigned long port = (unsigned long __force)addr;
+        if (__is_io_address(port))
+                __ixp4xx_outsl(port & PIO_MASK, vaddr, count);
+        else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+                __raw_writesl(addr, vaddr, count);
+#else
+                __ixp4xx_writesl(addr, vaddr, count);
+#endif
+}
+
+#define ioread8(p)                      __ixp4xx_ioread8(p)
+#define ioread16(p)                     __ixp4xx_ioread16(p)
+#define ioread32(p)                     __ixp4xx_ioread32(p)
+
+#define ioread8_rep(p, v, c)            __ixp4xx_ioread8_rep(p, v, c)
+#define ioread16_rep(p, v, c)           __ixp4xx_ioread16_rep(p, v, c)
+#define ioread32_rep(p, v, c)           __ixp4xx_ioread32_rep(p, v, c)
+
+#define iowrite8(v,p)                   __ixp4xx_iowrite8(v,p)
+#define iowrite16(v,p)                  __ixp4xx_iowrite16(v,p)
+#define iowrite32(v,p)                  __ixp4xx_iowrite32(v,p)
+
+#define iowrite8_rep(p, v, c)           __ixp4xx_iowrite8_rep(p, v, c)
+#define iowrite16_rep(p, v, c)          __ixp4xx_iowrite16_rep(p, v, c)
+#define iowrite32_rep(p, v, c)          __ixp4xx_iowrite32_rep(p, v, c)
+
+#define ioport_map(port, nr)            ((void __iomem*)(port + PIO_OFFSET))
+#define ioport_unmap(addr)
+#endif  // !CONFIG_PCI
+
+#endif  //  __ASM_ARM_ARCH_IO_H
+
diff --git a/arch/arm/mach-ixp4xx/include/mach/irqs.h b/arch/arm/mach-ixp4xx/include/mach/irqs.h
new file mode 100644
index 000000000000..f4d74de1566a
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/irqs.h
@@ -0,0 +1,138 @@
+/*
+ * arch/arm/mach-ixp4xx/include/mach/irqs.h 
+ *
+ * IRQ definitions for IXP4XX based systems
+ *
+ * Copyright (C) 2002 Intel Corporation.
+ * Copyright (C) 2003 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _ARCH_IXP4XX_IRQS_H_
+#define _ARCH_IXP4XX_IRQS_H_
+
+
+#define IRQ_IXP4XX_NPEA         0
+#define IRQ_IXP4XX_NPEB         1
+#define IRQ_IXP4XX_NPEC         2
+#define IRQ_IXP4XX_QM1          3
+#define IRQ_IXP4XX_QM2          4
+#define IRQ_IXP4XX_TIMER1       5
+#define IRQ_IXP4XX_GPIO0        6
+#define IRQ_IXP4XX_GPIO1        7
+#define IRQ_IXP4XX_PCI_INT      8
+#define IRQ_IXP4XX_PCI_DMA1     9
+#define IRQ_IXP4XX_PCI_DMA2     10
+#define IRQ_IXP4XX_TIMER2       11
+#define IRQ_IXP4XX_USB          12
+#define IRQ_IXP4XX_UART2        13
+#define IRQ_IXP4XX_TIMESTAMP    14
+#define IRQ_IXP4XX_UART1        15
+#define IRQ_IXP4XX_WDOG         16
+#define IRQ_IXP4XX_AHB_PMU      17
+#define IRQ_IXP4XX_XSCALE_PMU   18
+#define IRQ_IXP4XX_GPIO2        19
+#define IRQ_IXP4XX_GPIO3        20
+#define IRQ_IXP4XX_GPIO4        21
+#define IRQ_IXP4XX_GPIO5        22
+#define IRQ_IXP4XX_GPIO6        23
+#define IRQ_IXP4XX_GPIO7        24
+#define IRQ_IXP4XX_GPIO8        25
+#define IRQ_IXP4XX_GPIO9        26
+#define IRQ_IXP4XX_GPIO10       27
+#define IRQ_IXP4XX_GPIO11       28
+#define IRQ_IXP4XX_GPIO12       29
+#define IRQ_IXP4XX_SW_INT1      30
+#define IRQ_IXP4XX_SW_INT2      31
+#define IRQ_IXP4XX_USB_HOST     32
+#define IRQ_IXP4XX_I2C          33
+#define IRQ_IXP4XX_SSP          34
+#define IRQ_IXP4XX_TSYNC        35
+#define IRQ_IXP4XX_EAU_DONE     36
+#define IRQ_IXP4XX_SHA_DONE     37
+#define IRQ_IXP4XX_SWCP_PE      58
+#define IRQ_IXP4XX_QM_PE        60
+#define IRQ_IXP4XX_MCU_ECC      61
+#define IRQ_IXP4XX_EXP_PE       62
+
+/*
+ * Only first 32 sources are valid if running on IXP42x systems
+ */
+#if defined(CONFIG_CPU_IXP46X) || defined(CONFIG_CPU_IXP43X)
+#define NR_IRQS                 64
+#else
+#define NR_IRQS                 32
+#endif
+
+#define XSCALE_PMU_IRQ          (IRQ_IXP4XX_XSCALE_PMU)
+
+/*
+ * IXDP425 board IRQs
+ */
+#define IRQ_IXDP425_PCI_INTA    IRQ_IXP4XX_GPIO11
+#define IRQ_IXDP425_PCI_INTB    IRQ_IXP4XX_GPIO10
+#define IRQ_IXDP425_PCI_INTC    IRQ_IXP4XX_GPIO9
+#define IRQ_IXDP425_PCI_INTD    IRQ_IXP4XX_GPIO8
+
+/*
+ * Gateworks Avila board IRQs
+ */
+#define IRQ_AVILA_PCI_INTA      IRQ_IXP4XX_GPIO11
+#define IRQ_AVILA_PCI_INTB      IRQ_IXP4XX_GPIO10
+#define IRQ_AVILA_PCI_INTC      IRQ_IXP4XX_GPIO9
+#define IRQ_AVILA_PCI_INTD      IRQ_IXP4XX_GPIO8
+
+
+/*
+ * PrPMC1100 Board IRQs
+ */
+#define IRQ_PRPMC1100_PCI_INTA  IRQ_IXP4XX_GPIO11
+#define IRQ_PRPMC1100_PCI_INTB  IRQ_IXP4XX_GPIO10
+#define IRQ_PRPMC1100_PCI_INTC  IRQ_IXP4XX_GPIO9
+#define IRQ_PRPMC1100_PCI_INTD  IRQ_IXP4XX_GPIO8
+
+/*
+ * ADI Coyote Board IRQs
+ */
+#define IRQ_COYOTE_PCI_SLOT0    IRQ_IXP4XX_GPIO6
+#define IRQ_COYOTE_PCI_SLOT1    IRQ_IXP4XX_GPIO11
+#define IRQ_COYOTE_IDE          IRQ_IXP4XX_GPIO5
+
+/*
+ * NSLU2 board IRQs
+ */
+#define        IRQ_NSLU2_PCI_INTA      IRQ_IXP4XX_GPIO11
+#define        IRQ_NSLU2_PCI_INTB      IRQ_IXP4XX_GPIO10
+#define        IRQ_NSLU2_PCI_INTC      IRQ_IXP4XX_GPIO9
+
+/*
+ * NAS100D board IRQs
+ */
+#define        IRQ_NAS100D_PCI_INTA    IRQ_IXP4XX_GPIO11
+#define        IRQ_NAS100D_PCI_INTB    IRQ_IXP4XX_GPIO10
+#define        IRQ_NAS100D_PCI_INTC    IRQ_IXP4XX_GPIO9
+#define        IRQ_NAS100D_PCI_INTD    IRQ_IXP4XX_GPIO8
+#define        IRQ_NAS100D_PCI_INTE    IRQ_IXP4XX_GPIO7
+
+/*
+ * D-Link DSM-G600 RevA board IRQs
+ */
+#define        IRQ_DSMG600_PCI_INTA    IRQ_IXP4XX_GPIO11
+#define        IRQ_DSMG600_PCI_INTB    IRQ_IXP4XX_GPIO10
+#define        IRQ_DSMG600_PCI_INTC    IRQ_IXP4XX_GPIO9
+#define        IRQ_DSMG600_PCI_INTD    IRQ_IXP4XX_GPIO8
+#define        IRQ_DSMG600_PCI_INTE    IRQ_IXP4XX_GPIO7
+#define        IRQ_DSMG600_PCI_INTF    IRQ_IXP4XX_GPIO6
+
+/*
+ * Freecom FSG-3 Board IRQs
+ */
+#define        IRQ_FSG_PCI_INTA        IRQ_IXP4XX_GPIO6
+#define        IRQ_FSG_PCI_INTB        IRQ_IXP4XX_GPIO7
+#define        IRQ_FSG_PCI_INTC        IRQ_IXP4XX_GPIO5
+
+#endif
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixdp425.h b/arch/arm/mach-ixp4xx/include/mach/ixdp425.h
new file mode 100644
index 000000000000..2cafe65ebfee
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/ixdp425.h
@@ -0,0 +1,39 @@
+/*
+ * arch/arm/mach-ixp4xx/include/mach/ixdp425.h
+ *
+ * IXDP425 platform specific definitions
+ *
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright 2004 (c) MontaVista, Software, Inc. 
+ * 
+ * This file is licensed under  the terms of the GNU General Public 
+ * License version 2. This program is licensed "as is" without any 
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H__
+#error "Do not include this directly, instead #include <mach/hardware.h>"
+#endif
+
+#define IXDP425_SDA_PIN         7
+#define IXDP425_SCL_PIN         6
+
+/*
+ * IXDP425 PCI IRQs
+ */
+#define IXDP425_PCI_MAX_DEV     4
+#define IXDP425_PCI_IRQ_LINES   4
+
+
+/* PCI controller GPIO to IRQ pin mappings */
+#define IXDP425_PCI_INTA_PIN    11
+#define IXDP425_PCI_INTB_PIN    10
+#define IXDP425_PCI_INTC_PIN    9
+#define IXDP425_PCI_INTD_PIN    8
+
+/* NAND Flash pins */
+#define IXDP425_NAND_NCE_PIN    12
+
+#define IXDP425_NAND_CMD_BYTE   0x01
+#define IXDP425_NAND_ADDR_BYTE  0x02
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
new file mode 100644
index 000000000000..ad9c888dd850
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
@@ -0,0 +1,638 @@
+/*
+ * arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
+ *
+ * Register definitions for IXP4xx chipset. This file contains 
+ * register location and bit definitions only. Platform specific 
+ * definitions and helper function declarations are in platform.h 
+ * and machine-name.h.
+ *
+ * Copyright (C) 2002 Intel Corporation.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _ASM_ARM_IXP4XX_H_
+#define _ASM_ARM_IXP4XX_H_
+
+/*
+ * IXP4xx Linux Memory Map:
+ *
+ * Phy          Size            Virt            Description
+ * =========================================================================
+ *
+ * 0x00000000   0x10000000(max) PAGE_OFFSET     System RAM
+ *
+ * 0x48000000   0x04000000      ioremap'd       PCI Memory Space
+ *
+ * 0x50000000   0x10000000      ioremap'd       EXP BUS
+ *
+ * 0x6000000    0x00004000      ioremap'd       QMgr
+ *
+ * 0xC0000000   0x00001000      0xffbff000      PCI CFG
+ *
+ * 0xC4000000   0x00001000      0xffbfe000      EXP CFG
+ *
+ * 0xC8000000   0x00013000      0xffbeb000      On-Chip Peripherals
+ */
+
+/*
+ * Queue Manager
+ */
+#define IXP4XX_QMGR_BASE_PHYS           (0x60000000)
+#define IXP4XX_QMGR_REGION_SIZE         (0x00004000)
+
+/*
+ * Expansion BUS Configuration registers
+ */
+#define IXP4XX_EXP_CFG_BASE_PHYS        (0xC4000000)
+#define IXP4XX_EXP_CFG_BASE_VIRT        (0xFFBFE000)
+#define IXP4XX_EXP_CFG_REGION_SIZE      (0x00001000)
+
+/*
+ * PCI Config registers
+ */
+#define IXP4XX_PCI_CFG_BASE_PHYS        (0xC0000000)
+#define IXP4XX_PCI_CFG_BASE_VIRT        (0xFFBFF000)
+#define IXP4XX_PCI_CFG_REGION_SIZE      (0x00001000)
+
+/*
+ * Peripheral space
+ */
+#define IXP4XX_PERIPHERAL_BASE_PHYS     (0xC8000000)
+#define IXP4XX_PERIPHERAL_BASE_VIRT     (0xFFBEB000)
+#define IXP4XX_PERIPHERAL_REGION_SIZE   (0x00013000)
+
+/*
+ * Debug UART
+ *
+ * This is basically a remap of UART1 into a region that is section
+ * aligned so that it * can be used with the low-level debug code.
+ */
+#define IXP4XX_DEBUG_UART_BASE_PHYS     (0xC8000000)
+#define IXP4XX_DEBUG_UART_BASE_VIRT     (0xffb00000)
+#define IXP4XX_DEBUG_UART_REGION_SIZE   (0x00001000)
+
+#define IXP4XX_EXP_CS0_OFFSET   0x00
+#define IXP4XX_EXP_CS1_OFFSET   0x04
+#define IXP4XX_EXP_CS2_OFFSET   0x08
+#define IXP4XX_EXP_CS3_OFFSET   0x0C
+#define IXP4XX_EXP_CS4_OFFSET   0x10
+#define IXP4XX_EXP_CS5_OFFSET   0x14
+#define IXP4XX_EXP_CS6_OFFSET   0x18
+#define IXP4XX_EXP_CS7_OFFSET   0x1C
+#define IXP4XX_EXP_CFG0_OFFSET  0x20
+#define IXP4XX_EXP_CFG1_OFFSET  0x24
+#define IXP4XX_EXP_CFG2_OFFSET  0x28
+#define IXP4XX_EXP_CFG3_OFFSET  0x2C
+
+/*
+ * Expansion Bus Controller registers.
+ */
+#define IXP4XX_EXP_REG(x) ((volatile u32 *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))
+
+#define IXP4XX_EXP_CS0      IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET)
+#define IXP4XX_EXP_CS1      IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET)
+#define IXP4XX_EXP_CS2      IXP4XX_EXP_REG(IXP4XX_EXP_CS2_OFFSET) 
+#define IXP4XX_EXP_CS3      IXP4XX_EXP_REG(IXP4XX_EXP_CS3_OFFSET)
+#define IXP4XX_EXP_CS4      IXP4XX_EXP_REG(IXP4XX_EXP_CS4_OFFSET)
+#define IXP4XX_EXP_CS5      IXP4XX_EXP_REG(IXP4XX_EXP_CS5_OFFSET)
+#define IXP4XX_EXP_CS6      IXP4XX_EXP_REG(IXP4XX_EXP_CS6_OFFSET)     
+#define IXP4XX_EXP_CS7      IXP4XX_EXP_REG(IXP4XX_EXP_CS7_OFFSET)
+
+#define IXP4XX_EXP_CFG0     IXP4XX_EXP_REG(IXP4XX_EXP_CFG0_OFFSET) 
+#define IXP4XX_EXP_CFG1     IXP4XX_EXP_REG(IXP4XX_EXP_CFG1_OFFSET) 
+#define IXP4XX_EXP_CFG2     IXP4XX_EXP_REG(IXP4XX_EXP_CFG2_OFFSET) 
+#define IXP4XX_EXP_CFG3     IXP4XX_EXP_REG(IXP4XX_EXP_CFG3_OFFSET)
+
+
+/*
+ * Peripheral Space Register Region Base Addresses
+ */
+#define IXP4XX_UART1_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000)
+#define IXP4XX_UART2_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000)
+#define IXP4XX_PMU_BASE_PHYS            (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000)
+#define IXP4XX_INTC_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000)
+#define IXP4XX_GPIO_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000)
+#define IXP4XX_TIMER_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)
+#define IXP4XX_NPEA_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000)
+#define IXP4XX_NPEB_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000)
+#define IXP4XX_NPEC_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000)
+#define IXP4XX_EthB_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)
+#define IXP4XX_EthC_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)
+#define IXP4XX_USB_BASE_PHYS            (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000)
+/* ixp46X only */
+#define IXP4XX_EthA_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0xC000)
+#define IXP4XX_EthB1_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0xD000)
+#define IXP4XX_EthB2_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0xE000)
+#define IXP4XX_EthB3_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0xF000)
+#define IXP4XX_TIMESYNC_BASE_PHYS       (IXP4XX_PERIPHERAL_BASE_PHYS + 0x10000)
+#define IXP4XX_I2C_BASE_PHYS            (IXP4XX_PERIPHERAL_BASE_PHYS + 0x11000)
+#define IXP4XX_SSP_BASE_PHYS            (IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000)
+
+
+#define IXP4XX_UART1_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)
+#define IXP4XX_UART2_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)
+#define IXP4XX_PMU_BASE_VIRT            (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)
+#define IXP4XX_INTC_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)
+#define IXP4XX_GPIO_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)
+#define IXP4XX_TIMER_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
+#define IXP4XX_NPEA_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0x6000)
+#define IXP4XX_NPEB_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0x7000)
+#define IXP4XX_NPEC_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0x8000)
+#define IXP4XX_EthB_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000)
+#define IXP4XX_EthC_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000)
+#define IXP4XX_USB_BASE_VIRT            (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000)
+/* ixp46X only */
+#define IXP4XX_EthA_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0xC000)
+#define IXP4XX_EthB1_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0xD000)
+#define IXP4XX_EthB2_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0xE000)
+#define IXP4XX_EthB3_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0xF000)
+#define IXP4XX_TIMESYNC_BASE_VIRT       (IXP4XX_PERIPHERAL_BASE_VIRT + 0x10000)
+#define IXP4XX_I2C_BASE_VIRT            (IXP4XX_PERIPHERAL_BASE_VIRT + 0x11000)
+#define IXP4XX_SSP_BASE_VIRT            (IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000)
+
+/*
+ * Constants to make it easy to access  Interrupt Controller registers
+ */
+#define IXP4XX_ICPR_OFFSET      0x00 /* Interrupt Status */
+#define IXP4XX_ICMR_OFFSET      0x04 /* Interrupt Enable */
+#define IXP4XX_ICLR_OFFSET      0x08 /* Interrupt IRQ/FIQ Select */
+#define IXP4XX_ICIP_OFFSET      0x0C /* IRQ Status */
+#define IXP4XX_ICFP_OFFSET      0x10 /* FIQ Status */
+#define IXP4XX_ICHR_OFFSET      0x14 /* Interrupt Priority */
+#define IXP4XX_ICIH_OFFSET      0x18 /* IRQ Highest Pri Int */
+#define IXP4XX_ICFH_OFFSET      0x1C /* FIQ Highest Pri Int */
+
+/*
+ * IXP465-only
+ */
+#define IXP4XX_ICPR2_OFFSET     0x20 /* Interrupt Status 2 */
+#define IXP4XX_ICMR2_OFFSET     0x24 /* Interrupt Enable 2 */
+#define IXP4XX_ICLR2_OFFSET     0x28 /* Interrupt IRQ/FIQ Select 2 */
+#define IXP4XX_ICIP2_OFFSET     0x2C /* IRQ Status */
+#define IXP4XX_ICFP2_OFFSET     0x30 /* FIQ Status */
+#define IXP4XX_ICEEN_OFFSET     0x34 /* Error High Pri Enable */
+
+
+/*
+ * Interrupt Controller Register Definitions.
+ */
+
+#define IXP4XX_INTC_REG(x) ((volatile u32 *)(IXP4XX_INTC_BASE_VIRT+(x)))
+
+#define IXP4XX_ICPR     IXP4XX_INTC_REG(IXP4XX_ICPR_OFFSET)
+#define IXP4XX_ICMR     IXP4XX_INTC_REG(IXP4XX_ICMR_OFFSET)
+#define IXP4XX_ICLR     IXP4XX_INTC_REG(IXP4XX_ICLR_OFFSET)
+#define IXP4XX_ICIP     IXP4XX_INTC_REG(IXP4XX_ICIP_OFFSET)
+#define IXP4XX_ICFP     IXP4XX_INTC_REG(IXP4XX_ICFP_OFFSET)
+#define IXP4XX_ICHR     IXP4XX_INTC_REG(IXP4XX_ICHR_OFFSET)
+#define IXP4XX_ICIH     IXP4XX_INTC_REG(IXP4XX_ICIH_OFFSET) 
+#define IXP4XX_ICFH     IXP4XX_INTC_REG(IXP4XX_ICFH_OFFSET)
+#define IXP4XX_ICPR2    IXP4XX_INTC_REG(IXP4XX_ICPR2_OFFSET)
+#define IXP4XX_ICMR2    IXP4XX_INTC_REG(IXP4XX_ICMR2_OFFSET)
+#define IXP4XX_ICLR2    IXP4XX_INTC_REG(IXP4XX_ICLR2_OFFSET)
+#define IXP4XX_ICIP2    IXP4XX_INTC_REG(IXP4XX_ICIP2_OFFSET)
+#define IXP4XX_ICFP2    IXP4XX_INTC_REG(IXP4XX_ICFP2_OFFSET)
+#define IXP4XX_ICEEN    IXP4XX_INTC_REG(IXP4XX_ICEEN_OFFSET)
+                                                                                
+/*
+ * Constants to make it easy to access GPIO registers
+ */
+#define IXP4XX_GPIO_GPOUTR_OFFSET       0x00
+#define IXP4XX_GPIO_GPOER_OFFSET        0x04
+#define IXP4XX_GPIO_GPINR_OFFSET        0x08
+#define IXP4XX_GPIO_GPISR_OFFSET        0x0C
+#define IXP4XX_GPIO_GPIT1R_OFFSET       0x10
+#define IXP4XX_GPIO_GPIT2R_OFFSET       0x14
+#define IXP4XX_GPIO_GPCLKR_OFFSET       0x18
+#define IXP4XX_GPIO_GPDBSELR_OFFSET     0x1C
+
+/* 
+ * GPIO Register Definitions.
+ * [Only perform 32bit reads/writes]
+ */
+#define IXP4XX_GPIO_REG(x) ((volatile u32 *)(IXP4XX_GPIO_BASE_VIRT+(x)))
+
+#define IXP4XX_GPIO_GPOUTR      IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOUTR_OFFSET)
+#define IXP4XX_GPIO_GPOER       IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOER_OFFSET)
+#define IXP4XX_GPIO_GPINR       IXP4XX_GPIO_REG(IXP4XX_GPIO_GPINR_OFFSET)
+#define IXP4XX_GPIO_GPISR       IXP4XX_GPIO_REG(IXP4XX_GPIO_GPISR_OFFSET)
+#define IXP4XX_GPIO_GPIT1R      IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT1R_OFFSET)
+#define IXP4XX_GPIO_GPIT2R      IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT2R_OFFSET)
+#define IXP4XX_GPIO_GPCLKR      IXP4XX_GPIO_REG(IXP4XX_GPIO_GPCLKR_OFFSET)
+#define IXP4XX_GPIO_GPDBSELR    IXP4XX_GPIO_REG(IXP4XX_GPIO_GPDBSELR_OFFSET)
+
+/*
+ * GPIO register bit definitions
+ */
+
+/* Interrupt styles
+ */
+#define IXP4XX_GPIO_STYLE_ACTIVE_HIGH   0x0
+#define IXP4XX_GPIO_STYLE_ACTIVE_LOW    0x1
+#define IXP4XX_GPIO_STYLE_RISING_EDGE   0x2
+#define IXP4XX_GPIO_STYLE_FALLING_EDGE  0x3
+#define IXP4XX_GPIO_STYLE_TRANSITIONAL  0x4
+
+/* 
+ * Mask used to clear interrupt styles 
+ */
+#define IXP4XX_GPIO_STYLE_CLEAR         0x7
+#define IXP4XX_GPIO_STYLE_SIZE          3
+
+/*
+ * Constants to make it easy to access Timer Control/Status registers
+ */
+#define IXP4XX_OSTS_OFFSET      0x00  /* Continious TimeStamp */
+#define IXP4XX_OST1_OFFSET      0x04  /* Timer 1 Timestamp */
+#define IXP4XX_OSRT1_OFFSET     0x08  /* Timer 1 Reload */
+#define IXP4XX_OST2_OFFSET      0x0C  /* Timer 2 Timestamp */
+#define IXP4XX_OSRT2_OFFSET     0x10  /* Timer 2 Reload */
+#define IXP4XX_OSWT_OFFSET      0x14  /* Watchdog Timer */
+#define IXP4XX_OSWE_OFFSET      0x18  /* Watchdog Enable */
+#define IXP4XX_OSWK_OFFSET      0x1C  /* Watchdog Key */
+#define IXP4XX_OSST_OFFSET      0x20  /* Timer Status */
+
+/*
+ * Operating System Timer Register Definitions.
+ */
+
+#define IXP4XX_TIMER_REG(x) ((volatile u32 *)(IXP4XX_TIMER_BASE_VIRT+(x)))
+
+#define IXP4XX_OSTS     IXP4XX_TIMER_REG(IXP4XX_OSTS_OFFSET)
+#define IXP4XX_OST1     IXP4XX_TIMER_REG(IXP4XX_OST1_OFFSET)
+#define IXP4XX_OSRT1    IXP4XX_TIMER_REG(IXP4XX_OSRT1_OFFSET)
+#define IXP4XX_OST2     IXP4XX_TIMER_REG(IXP4XX_OST2_OFFSET)
+#define IXP4XX_OSRT2    IXP4XX_TIMER_REG(IXP4XX_OSRT2_OFFSET)
+#define IXP4XX_OSWT     IXP4XX_TIMER_REG(IXP4XX_OSWT_OFFSET)
+#define IXP4XX_OSWE     IXP4XX_TIMER_REG(IXP4XX_OSWE_OFFSET)
+#define IXP4XX_OSWK     IXP4XX_TIMER_REG(IXP4XX_OSWK_OFFSET)
+#define IXP4XX_OSST     IXP4XX_TIMER_REG(IXP4XX_OSST_OFFSET)
+
+/*
+ * Timer register values and bit definitions 
+ */
+#define IXP4XX_OST_ENABLE               0x00000001
+#define IXP4XX_OST_ONE_SHOT             0x00000002
+/* Low order bits of reload value ignored */
+#define IXP4XX_OST_RELOAD_MASK          0x00000003
+#define IXP4XX_OST_DISABLED             0x00000000
+#define IXP4XX_OSST_TIMER_1_PEND        0x00000001
+#define IXP4XX_OSST_TIMER_2_PEND        0x00000002
+#define IXP4XX_OSST_TIMER_TS_PEND       0x00000004
+#define IXP4XX_OSST_TIMER_WDOG_PEND     0x00000008
+#define IXP4XX_OSST_TIMER_WARM_RESET    0x00000010
+
+#define IXP4XX_WDT_KEY                  0x0000482E
+
+#define IXP4XX_WDT_RESET_ENABLE         0x00000001
+#define IXP4XX_WDT_IRQ_ENABLE           0x00000002
+#define IXP4XX_WDT_COUNT_ENABLE         0x00000004
+
+
+/*
+ * Constants to make it easy to access PCI Control/Status registers
+ */
+#define PCI_NP_AD_OFFSET            0x00
+#define PCI_NP_CBE_OFFSET           0x04
+#define PCI_NP_WDATA_OFFSET         0x08
+#define PCI_NP_RDATA_OFFSET         0x0c
+#define PCI_CRP_AD_CBE_OFFSET       0x10
+#define PCI_CRP_WDATA_OFFSET        0x14
+#define PCI_CRP_RDATA_OFFSET        0x18
+#define PCI_CSR_OFFSET              0x1c
+#define PCI_ISR_OFFSET              0x20
+#define PCI_INTEN_OFFSET            0x24
+#define PCI_DMACTRL_OFFSET          0x28
+#define PCI_AHBMEMBASE_OFFSET       0x2c
+#define PCI_AHBIOBASE_OFFSET        0x30
+#define PCI_PCIMEMBASE_OFFSET       0x34
+#define PCI_AHBDOORBELL_OFFSET      0x38
+#define PCI_PCIDOORBELL_OFFSET      0x3C
+#define PCI_ATPDMA0_AHBADDR_OFFSET  0x40
+#define PCI_ATPDMA0_PCIADDR_OFFSET  0x44
+#define PCI_ATPDMA0_LENADDR_OFFSET  0x48
+#define PCI_ATPDMA1_AHBADDR_OFFSET  0x4C
+#define PCI_ATPDMA1_PCIADDR_OFFSET  0x50
+#define PCI_ATPDMA1_LENADDR_OFFSET      0x54
+
+/*
+ * PCI Control/Status Registers
+ */
+#define IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x)))
+
+#define PCI_NP_AD               IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET)
+#define PCI_NP_CBE              IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET)
+#define PCI_NP_WDATA            IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET)
+#define PCI_NP_RDATA            IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET)
+#define PCI_CRP_AD_CBE          IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)
+#define PCI_CRP_WDATA           IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET)
+#define PCI_CRP_RDATA           IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET)
+#define PCI_CSR                 IXP4XX_PCI_CSR(PCI_CSR_OFFSET) 
+#define PCI_ISR                 IXP4XX_PCI_CSR(PCI_ISR_OFFSET)
+#define PCI_INTEN               IXP4XX_PCI_CSR(PCI_INTEN_OFFSET)
+#define PCI_DMACTRL             IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET)
+#define PCI_AHBMEMBASE          IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET)
+#define PCI_AHBIOBASE           IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET)
+#define PCI_PCIMEMBASE          IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET)
+#define PCI_AHBDOORBELL         IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET)
+#define PCI_PCIDOORBELL         IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET)
+#define PCI_ATPDMA0_AHBADDR     IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)
+#define PCI_ATPDMA0_PCIADDR     IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)
+#define PCI_ATPDMA0_LENADDR     IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)
+#define PCI_ATPDMA1_AHBADDR     IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)
+#define PCI_ATPDMA1_PCIADDR     IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)
+#define PCI_ATPDMA1_LENADDR     IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)
+
+/*
+ * PCI register values and bit definitions 
+ */
+
+/* CSR bit definitions */
+#define PCI_CSR_HOST            0x00000001
+#define PCI_CSR_ARBEN           0x00000002
+#define PCI_CSR_ADS             0x00000004
+#define PCI_CSR_PDS             0x00000008
+#define PCI_CSR_ABE             0x00000010
+#define PCI_CSR_DBT             0x00000020
+#define PCI_CSR_ASE             0x00000100
+#define PCI_CSR_IC              0x00008000
+
+/* ISR (Interrupt status) Register bit definitions */
+#define PCI_ISR_PSE             0x00000001
+#define PCI_ISR_PFE             0x00000002
+#define PCI_ISR_PPE             0x00000004
+#define PCI_ISR_AHBE            0x00000008
+#define PCI_ISR_APDC            0x00000010
+#define PCI_ISR_PADC            0x00000020
+#define PCI_ISR_ADB             0x00000040
+#define PCI_ISR_PDB             0x00000080
+
+/* INTEN (Interrupt Enable) Register bit definitions */
+#define PCI_INTEN_PSE           0x00000001
+#define PCI_INTEN_PFE           0x00000002
+#define PCI_INTEN_PPE           0x00000004
+#define PCI_INTEN_AHBE          0x00000008
+#define PCI_INTEN_APDC          0x00000010
+#define PCI_INTEN_PADC          0x00000020
+#define PCI_INTEN_ADB           0x00000040
+#define PCI_INTEN_PDB           0x00000080
+
+/*
+ * Shift value for byte enable on NP cmd/byte enable register
+ */
+#define IXP4XX_PCI_NP_CBE_BESL          4
+
+/*
+ * PCI commands supported by NP access unit
+ */
+#define NP_CMD_IOREAD                   0x2
+#define NP_CMD_IOWRITE                  0x3
+#define NP_CMD_CONFIGREAD               0xa
+#define NP_CMD_CONFIGWRITE              0xb
+#define NP_CMD_MEMREAD                  0x6
+#define NP_CMD_MEMWRITE                 0x7
+
+/*
+ * Constants for CRP access into local config space
+ */
+#define CRP_AD_CBE_BESL         20
+#define CRP_AD_CBE_WRITE        0x00010000
+
+
+/*
+ * USB Device Controller
+ *
+ * These are used by the USB gadget driver, so they don't follow the
+ * IXP4XX_ naming convetions.
+ *
+ */
+# define IXP4XX_USB_REG(x)       (*((volatile u32 *)(x)))
+
+/* UDC Undocumented - Reserved1 */
+#define UDC_RES1        IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0004)  
+/* UDC Undocumented - Reserved2 */
+#define UDC_RES2        IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0008)  
+/* UDC Undocumented - Reserved3 */
+#define UDC_RES3        IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x000C)  
+/* UDC Control Register */
+#define UDCCR           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0000)  
+/* UDC Endpoint 0 Control/Status Register */
+#define UDCCS0          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0010)  
+/* UDC Endpoint 1 (IN) Control/Status Register */
+#define UDCCS1          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0014)  
+/* UDC Endpoint 2 (OUT) Control/Status Register */
+#define UDCCS2          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0018)  
+/* UDC Endpoint 3 (IN) Control/Status Register */
+#define UDCCS3          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x001C)  
+/* UDC Endpoint 4 (OUT) Control/Status Register */
+#define UDCCS4          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0020)  
+/* UDC Endpoint 5 (Interrupt) Control/Status Register */
+#define UDCCS5          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0024)  
+/* UDC Endpoint 6 (IN) Control/Status Register */
+#define UDCCS6          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0028)  
+/* UDC Endpoint 7 (OUT) Control/Status Register */
+#define UDCCS7          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x002C)  
+/* UDC Endpoint 8 (IN) Control/Status Register */
+#define UDCCS8          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0030)  
+/* UDC Endpoint 9 (OUT) Control/Status Register */
+#define UDCCS9          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0034)  
+/* UDC Endpoint 10 (Interrupt) Control/Status Register */
+#define UDCCS10         IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0038)  
+/* UDC Endpoint 11 (IN) Control/Status Register */
+#define UDCCS11         IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x003C)  
+/* UDC Endpoint 12 (OUT) Control/Status Register */
+#define UDCCS12         IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0040)  
+/* UDC Endpoint 13 (IN) Control/Status Register */
+#define UDCCS13         IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0044)  
+/* UDC Endpoint 14 (OUT) Control/Status Register */
+#define UDCCS14         IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0048)  
+/* UDC Endpoint 15 (Interrupt) Control/Status Register */
+#define UDCCS15         IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x004C)  
+/* UDC Frame Number Register High */
+#define UFNRH           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0060)  
+/* UDC Frame Number Register Low */
+#define UFNRL           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0064)  
+/* UDC Byte Count Reg 2 */
+#define UBCR2           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0068)  
+/* UDC Byte Count Reg 4 */
+#define UBCR4           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x006c)  
+/* UDC Byte Count Reg 7 */
+#define UBCR7           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0070)  
+/* UDC Byte Count Reg 9 */
+#define UBCR9           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0074)  
+/* UDC Byte Count Reg 12 */
+#define UBCR12          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0078)  
+/* UDC Byte Count Reg 14 */
+#define UBCR14          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x007c)  
+/* UDC Endpoint 0 Data Register */
+#define UDDR0           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0080)  
+/* UDC Endpoint 1 Data Register */
+#define UDDR1           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0100)  
+/* UDC Endpoint 2 Data Register */
+#define UDDR2           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0180)  
+/* UDC Endpoint 3 Data Register */
+#define UDDR3           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0200)  
+/* UDC Endpoint 4 Data Register */
+#define UDDR4           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0400)  
+/* UDC Endpoint 5 Data Register */
+#define UDDR5           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00A0)  
+/* UDC Endpoint 6 Data Register */
+#define UDDR6           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0600)  
+/* UDC Endpoint 7 Data Register */
+#define UDDR7           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0680)  
+/* UDC Endpoint 8 Data Register */
+#define UDDR8           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0700)  
+/* UDC Endpoint 9 Data Register */
+#define UDDR9           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0900)  
+/* UDC Endpoint 10 Data Register */
+#define UDDR10          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00C0)  
+/* UDC Endpoint 11 Data Register */
+#define UDDR11          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B00)  
+/* UDC Endpoint 12 Data Register */
+#define UDDR12          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B80)  
+/* UDC Endpoint 13 Data Register */
+#define UDDR13          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0C00)  
+/* UDC Endpoint 14 Data Register */
+#define UDDR14          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0E00)  
+/* UDC Endpoint 15 Data Register */
+#define UDDR15          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00E0)  
+/* UDC Interrupt Control Register 0 */
+#define UICR0           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0050)  
+/* UDC Interrupt Control Register 1 */
+#define UICR1           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0054)  
+/* UDC Status Interrupt Register 0 */
+#define USIR0           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0058)  
+/* UDC Status Interrupt Register 1 */
+#define USIR1           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x005C)  
+
+#define UDCCR_UDE       (1 << 0)        /* UDC enable */
+#define UDCCR_UDA       (1 << 1)        /* UDC active */
+#define UDCCR_RSM       (1 << 2)        /* Device resume */
+#define UDCCR_RESIR     (1 << 3)        /* Resume interrupt request */
+#define UDCCR_SUSIR     (1 << 4)        /* Suspend interrupt request */
+#define UDCCR_SRM       (1 << 5)        /* Suspend/resume interrupt mask */
+#define UDCCR_RSTIR     (1 << 6)        /* Reset interrupt request */
+#define UDCCR_REM       (1 << 7)        /* Reset interrupt mask */
+
+#define UDCCS0_OPR      (1 << 0)        /* OUT packet ready */
+#define UDCCS0_IPR      (1 << 1)        /* IN packet ready */
+#define UDCCS0_FTF      (1 << 2)        /* Flush Tx FIFO */
+#define UDCCS0_DRWF     (1 << 3)        /* Device remote wakeup feature */
+#define UDCCS0_SST      (1 << 4)        /* Sent stall */
+#define UDCCS0_FST      (1 << 5)        /* Force stall */
+#define UDCCS0_RNE      (1 << 6)        /* Receive FIFO no empty */
+#define UDCCS0_SA       (1 << 7)        /* Setup active */
+
+#define UDCCS_BI_TFS    (1 << 0)        /* Transmit FIFO service */
+#define UDCCS_BI_TPC    (1 << 1)        /* Transmit packet complete */
+#define UDCCS_BI_FTF    (1 << 2)        /* Flush Tx FIFO */
+#define UDCCS_BI_TUR    (1 << 3)        /* Transmit FIFO underrun */
+#define UDCCS_BI_SST    (1 << 4)        /* Sent stall */
+#define UDCCS_BI_FST    (1 << 5)        /* Force stall */
+#define UDCCS_BI_TSP    (1 << 7)        /* Transmit short packet */
+
+#define UDCCS_BO_RFS    (1 << 0)        /* Receive FIFO service */
+#define UDCCS_BO_RPC    (1 << 1)        /* Receive packet complete */
+#define UDCCS_BO_DME    (1 << 3)        /* DMA enable */
+#define UDCCS_BO_SST    (1 << 4)        /* Sent stall */
+#define UDCCS_BO_FST    (1 << 5)        /* Force stall */
+#define UDCCS_BO_RNE    (1 << 6)        /* Receive FIFO not empty */
+#define UDCCS_BO_RSP    (1 << 7)        /* Receive short packet */
+
+#define UDCCS_II_TFS    (1 << 0)        /* Transmit FIFO service */
+#define UDCCS_II_TPC    (1 << 1)        /* Transmit packet complete */
+#define UDCCS_II_FTF    (1 << 2)        /* Flush Tx FIFO */
+#define UDCCS_II_TUR    (1 << 3)        /* Transmit FIFO underrun */
+#define UDCCS_II_TSP    (1 << 7)        /* Transmit short packet */
+
+#define UDCCS_IO_RFS    (1 << 0)        /* Receive FIFO service */
+#define UDCCS_IO_RPC    (1 << 1)        /* Receive packet complete */
+#define UDCCS_IO_ROF    (1 << 3)        /* Receive overflow */
+#define UDCCS_IO_DME    (1 << 3)        /* DMA enable */
+#define UDCCS_IO_RNE    (1 << 6)        /* Receive FIFO not empty */
+#define UDCCS_IO_RSP    (1 << 7)        /* Receive short packet */
+
+#define UDCCS_INT_TFS   (1 << 0)        /* Transmit FIFO service */
+#define UDCCS_INT_TPC   (1 << 1)        /* Transmit packet complete */
+#define UDCCS_INT_FTF   (1 << 2)        /* Flush Tx FIFO */
+#define UDCCS_INT_TUR   (1 << 3)        /* Transmit FIFO underrun */
+#define UDCCS_INT_SST   (1 << 4)        /* Sent stall */
+#define UDCCS_INT_FST   (1 << 5)        /* Force stall */
+#define UDCCS_INT_TSP   (1 << 7)        /* Transmit short packet */
+
+#define UICR0_IM0       (1 << 0)        /* Interrupt mask ep 0 */
+#define UICR0_IM1       (1 << 1)        /* Interrupt mask ep 1 */
+#define UICR0_IM2       (1 << 2)        /* Interrupt mask ep 2 */
+#define UICR0_IM3       (1 << 3)        /* Interrupt mask ep 3 */
+#define UICR0_IM4       (1 << 4)        /* Interrupt mask ep 4 */
+#define UICR0_IM5       (1 << 5)        /* Interrupt mask ep 5 */
+#define UICR0_IM6       (1 << 6)        /* Interrupt mask ep 6 */
+#define UICR0_IM7       (1 << 7)        /* Interrupt mask ep 7 */
+
+#define UICR1_IM8       (1 << 0)        /* Interrupt mask ep 8 */
+#define UICR1_IM9       (1 << 1)        /* Interrupt mask ep 9 */
+#define UICR1_IM10      (1 << 2)        /* Interrupt mask ep 10 */
+#define UICR1_IM11      (1 << 3)        /* Interrupt mask ep 11 */
+#define UICR1_IM12      (1 << 4)        /* Interrupt mask ep 12 */
+#define UICR1_IM13      (1 << 5)        /* Interrupt mask ep 13 */
+#define UICR1_IM14      (1 << 6)        /* Interrupt mask ep 14 */
+#define UICR1_IM15      (1 << 7)        /* Interrupt mask ep 15 */
+
+#define USIR0_IR0       (1 << 0)        /* Interrupt request ep 0 */
+#define USIR0_IR1       (1 << 1)        /* Interrupt request ep 1 */
+#define USIR0_IR2       (1 << 2)        /* Interrupt request ep 2 */
+#define USIR0_IR3       (1 << 3)        /* Interrupt request ep 3 */
+#define USIR0_IR4       (1 << 4)        /* Interrupt request ep 4 */
+#define USIR0_IR5       (1 << 5)        /* Interrupt request ep 5 */
+#define USIR0_IR6       (1 << 6)        /* Interrupt request ep 6 */
+#define USIR0_IR7       (1 << 7)        /* Interrupt request ep 7 */
+
+#define USIR1_IR8       (1 << 0)        /* Interrupt request ep 8 */
+#define USIR1_IR9       (1 << 1)        /* Interrupt request ep 9 */
+#define USIR1_IR10      (1 << 2)        /* Interrupt request ep 10 */
+#define USIR1_IR11      (1 << 3)        /* Interrupt request ep 11 */
+#define USIR1_IR12      (1 << 4)        /* Interrupt request ep 12 */
+#define USIR1_IR13      (1 << 5)        /* Interrupt request ep 13 */
+#define USIR1_IR14      (1 << 6)        /* Interrupt request ep 14 */
+#define USIR1_IR15      (1 << 7)        /* Interrupt request ep 15 */
+
+#define DCMD_LENGTH     0x01fff         /* length mask (max = 8K - 1) */
+
+/* "fuse" bits of IXP_EXP_CFG2 */
+#define IXP4XX_FEATURE_RCOMP            (1 << 0)
+#define IXP4XX_FEATURE_USB_DEVICE       (1 << 1)
+#define IXP4XX_FEATURE_HASH             (1 << 2)
+#define IXP4XX_FEATURE_AES              (1 << 3)
+#define IXP4XX_FEATURE_DES              (1 << 4)
+#define IXP4XX_FEATURE_HDLC             (1 << 5)
+#define IXP4XX_FEATURE_AAL              (1 << 6)
+#define IXP4XX_FEATURE_HSS              (1 << 7)
+#define IXP4XX_FEATURE_UTOPIA           (1 << 8)
+#define IXP4XX_FEATURE_NPEB_ETH0        (1 << 9)
+#define IXP4XX_FEATURE_NPEC_ETH         (1 << 10)
+#define IXP4XX_FEATURE_RESET_NPEA       (1 << 11)
+#define IXP4XX_FEATURE_RESET_NPEB       (1 << 12)
+#define IXP4XX_FEATURE_RESET_NPEC       (1 << 13)
+#define IXP4XX_FEATURE_PCI              (1 << 14)
+#define IXP4XX_FEATURE_ECC_TIMESYNC     (1 << 15)
+#define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16)
+#define IXP4XX_FEATURE_USB_HOST         (1 << 18)
+#define IXP4XX_FEATURE_NPEA_ETH         (1 << 19)
+#define IXP4XX_FEATURE_NPEB_ETH_1_TO_3  (1 << 20)
+#define IXP4XX_FEATURE_RSA              (1 << 21)
+#define IXP4XX_FEATURE_XSCALE_MAX_FREQ  (3 << 22)
+#define IXP4XX_FEATURE_RESERVED         (0xFF << 24)
+
+#define IXP4XX_FEATURE_IXP46X_ONLY (IXP4XX_FEATURE_ECC_TIMESYNC |       \
+                                    IXP4XX_FEATURE_USB_HOST |           \
+                                    IXP4XX_FEATURE_NPEA_ETH |           \
+                                    IXP4XX_FEATURE_NPEB_ETH_1_TO_3 |    \
+                                    IXP4XX_FEATURE_RSA |                \
+                                    IXP4XX_FEATURE_XSCALE_MAX_FREQ)
+
+#endif
diff --git a/arch/arm/mach-ixp4xx/include/mach/memory.h b/arch/arm/mach-ixp4xx/include/mach/memory.h
new file mode 100644
index 000000000000..c4d2830ac987
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/memory.h
@@ -0,0 +1,40 @@
+/*
+ * arch/arm/mach-ixp4xx/include/mach/memory.h
+ *
+ * Copyright (c) 2001-2004 MontaVista Software, Inc.
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#include <asm/sizes.h>
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     UL(0x00000000)
+
+#if !defined(__ASSEMBLY__) && defined(CONFIG_PCI)
+
+void ixp4xx_adjust_zones(int node, unsigned long *size, unsigned long *holes);
+
+#define arch_adjust_zones(node, size, holes) \
+        ixp4xx_adjust_zones(node, size, holes)
+
+#define ISA_DMA_THRESHOLD (SZ_64M - 1)
+
+#endif
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ *
+ * These are dummies for now.
+ */
+#define __virt_to_bus(x)         __virt_to_phys(x)
+#define __bus_to_virt(x)         __phys_to_virt(x)
+
+#endif
diff --git a/arch/arm/mach-ixp4xx/include/mach/nas100d.h b/arch/arm/mach-ixp4xx/include/mach/nas100d.h
new file mode 100644
index 000000000000..3771d62a9748
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/nas100d.h
@@ -0,0 +1,52 @@
+/*
+ * arch/arm/mach-ixp4xx/include/mach/nas100d.h
+ *
+ * NAS100D platform specific definitions
+ *
+ * Copyright (c) 2005 Tower Technologies
+ *
+ * Author: Alessandro Zummo <a.zummo@towertech.it>
+ *
+ * based on ixdp425.h:
+ *      Copyright 2004 (c) MontaVista, Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H__
+#error "Do not include this directly, instead #include <mach/hardware.h>"
+#endif
+
+#define NAS100D_SDA_PIN         5
+#define NAS100D_SCL_PIN         6
+
+/*
+ * NAS100D PCI IRQs
+ */
+#define NAS100D_PCI_MAX_DEV     3
+#define NAS100D_PCI_IRQ_LINES   3
+
+
+/* PCI controller GPIO to IRQ pin mappings */
+#define NAS100D_PCI_INTA_PIN    11
+#define NAS100D_PCI_INTB_PIN    10
+#define NAS100D_PCI_INTC_PIN    9
+#define NAS100D_PCI_INTD_PIN    8
+#define NAS100D_PCI_INTE_PIN    7
+
+/* Buttons */
+
+#define NAS100D_PB_GPIO         14   /* power button */
+#define NAS100D_RB_GPIO         4    /* reset button */
+
+/* Power control */
+
+#define NAS100D_PO_GPIO         12   /* power off */
+
+/* LEDs */
+
+#define NAS100D_LED_WLAN_GPIO   0
+#define NAS100D_LED_DISK_GPIO   3
+#define NAS100D_LED_PWR_GPIO    15
diff --git a/include/asm-arm/arch-ixp4xx/npe.h b/arch/arm/mach-ixp4xx/include/mach/npe.h
index 37d0511689dc..37d0511689dc 100644
--- a/include/asm-arm/arch-ixp4xx/npe.h
+++ b/arch/arm/mach-ixp4xx/include/mach/npe.h
diff --git a/arch/arm/mach-ixp4xx/include/mach/nslu2.h b/arch/arm/mach-ixp4xx/include/mach/nslu2.h
new file mode 100644
index 000000000000..85d00adbfb92
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/nslu2.h
@@ -0,0 +1,55 @@
+/*
+ * arch/arm/mach-ixp4xx/include/mach/nslu2.h
+ *
+ * NSLU2 platform specific definitions
+ *
+ * Author: Mark Rakes <mrakes AT mac.com>
+ * Maintainers: http://www.nslu2-linux.org
+ *
+ * based on ixdp425.h:
+ *      Copyright 2004 (c) MontaVista, Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H__
+#error "Do not include this directly, instead #include <mach/hardware.h>"
+#endif
+
+#define NSLU2_SDA_PIN           7
+#define NSLU2_SCL_PIN           6
+
+/*
+ * NSLU2 PCI IRQs
+ */
+#define NSLU2_PCI_MAX_DEV       3
+#define NSLU2_PCI_IRQ_LINES     3
+
+
+/* PCI controller GPIO to IRQ pin mappings */
+#define NSLU2_PCI_INTA_PIN      11
+#define NSLU2_PCI_INTB_PIN      10
+#define NSLU2_PCI_INTC_PIN      9
+#define NSLU2_PCI_INTD_PIN      8
+
+/* NSLU2 Timer */
+#define NSLU2_FREQ 66000000
+
+/* Buttons */
+
+#define NSLU2_PB_GPIO           5       /* power button */
+#define NSLU2_PO_GPIO           8       /* power off */
+#define NSLU2_RB_GPIO           12      /* reset button */
+
+/* Buzzer */
+
+#define NSLU2_GPIO_BUZZ         4
+
+/* LEDs */
+
+#define NSLU2_LED_RED_GPIO      0
+#define NSLU2_LED_GRN_GPIO      1
+#define NSLU2_LED_DISK1_GPIO    3
+#define NSLU2_LED_DISK2_GPIO    2
diff --git a/arch/arm/mach-ixp4xx/include/mach/platform.h b/arch/arm/mach-ixp4xx/include/mach/platform.h
new file mode 100644
index 000000000000..e824c02c825a
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/platform.h
@@ -0,0 +1,173 @@
+/*
+ * arch/arm/mach-ixp4xx/include/mach/platform.h
+ *
+ * Constants and functions that are useful to IXP4xx platform-specific code
+ * and device drivers.
+ *
+ * Copyright (C) 2004 MontaVista Software, Inc.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H__
+#error "Do not include this directly, instead #include <mach/hardware.h>"
+#endif
+
+#ifndef __ASSEMBLY__
+
+#include <asm/types.h>
+
+#ifndef __ARMEB__
+#define REG_OFFSET      0
+#else
+#define REG_OFFSET      3
+#endif
+
+/*
+ * Expansion bus memory regions
+ */
+#define IXP4XX_EXP_BUS_BASE_PHYS        (0x50000000)
+
+/*
+ * The expansion bus on the IXP4xx can be configured for either 16 or
+ * 32MB windows and the CS offset for each region changes based on the
+ * current configuration. This means that we cannot simply hardcode
+ * each offset. ixp4xx_sys_init() looks at the expansion bus configuration
+ * as setup by the bootloader to determine our window size.
+ */
+extern unsigned long ixp4xx_exp_bus_size;
+
+#define IXP4XX_EXP_BUS_BASE(region)\
+                (IXP4XX_EXP_BUS_BASE_PHYS + ((region) * ixp4xx_exp_bus_size))
+
+#define IXP4XX_EXP_BUS_END(region)\
+                (IXP4XX_EXP_BUS_BASE(region) + ixp4xx_exp_bus_size - 1)
+
+/* Those macros can be used to adjust timing and configure
+ * other features for each region.
+ */
+
+#define IXP4XX_EXP_BUS_RECOVERY_T(x)    (((x) & 0x0f) << 16)
+#define IXP4XX_EXP_BUS_HOLD_T(x)        (((x) & 0x03) << 20)
+#define IXP4XX_EXP_BUS_STROBE_T(x)      (((x) & 0x0f) << 22)
+#define IXP4XX_EXP_BUS_SETUP_T(x)       (((x) & 0x03) << 26)
+#define IXP4XX_EXP_BUS_ADDR_T(x)        (((x) & 0x03) << 28)
+#define IXP4XX_EXP_BUS_SIZE(x)          (((x) & 0x0f) << 10)
+#define IXP4XX_EXP_BUS_CYCLES(x)        (((x) & 0x03) << 14)
+
+#define IXP4XX_EXP_BUS_CS_EN            (1L << 31)
+#define IXP4XX_EXP_BUS_BYTE_RD16        (1L << 6)
+#define IXP4XX_EXP_BUS_HRDY_POL         (1L << 5)
+#define IXP4XX_EXP_BUS_MUX_EN           (1L << 4)
+#define IXP4XX_EXP_BUS_SPLT_EN          (1L << 3)
+#define IXP4XX_EXP_BUS_WR_EN            (1L << 1)
+#define IXP4XX_EXP_BUS_BYTE_EN          (1L << 0)
+
+#define IXP4XX_EXP_BUS_CYCLES_INTEL     0x00
+#define IXP4XX_EXP_BUS_CYCLES_MOTOROLA  0x01
+#define IXP4XX_EXP_BUS_CYCLES_HPI       0x02
+
+#define IXP4XX_FLASH_WRITABLE   (0x2)
+#define IXP4XX_FLASH_DEFAULT    (0xbcd23c40)
+#define IXP4XX_FLASH_WRITE      (0xbcd23c42)
+
+/*
+ * Clock Speed Definitions.
+ */
+#define IXP4XX_PERIPHERAL_BUS_CLOCK     (66) /* 66Mhzi APB BUS   */ 
+#define IXP4XX_UART_XTAL                14745600
+
+/*
+ * This structure provide a means for the board setup code
+ * to give information to th pata_ixp4xx driver. It is
+ * passed as platform_data.
+ */
+struct ixp4xx_pata_data {
+        volatile u32    *cs0_cfg;
+        volatile u32    *cs1_cfg;
+        unsigned long   cs0_bits;
+        unsigned long   cs1_bits;
+        void __iomem    *cs0;
+        void __iomem    *cs1;
+};
+
+struct sys_timer;
+
+#define IXP4XX_ETH_NPEA         0x00
+#define IXP4XX_ETH_NPEB         0x10
+#define IXP4XX_ETH_NPEC         0x20
+
+/* Information about built-in Ethernet MAC interfaces */
+struct eth_plat_info {
+        u8 phy;         /* MII PHY ID, 0 - 31 */
+        u8 rxq;         /* configurable, currently 0 - 31 only */
+        u8 txreadyq;
+        u8 hwaddr[6];
+};
+
+/* Information about built-in HSS (synchronous serial) interfaces */
+struct hss_plat_info {
+        int (*set_clock)(int port, unsigned int clock_type);
+        int (*open)(int port, void *pdev,
+                    void (*set_carrier_cb)(void *pdev, int carrier));
+        void (*close)(int port, void *pdev);
+        u8 txreadyq;
+};
+
+/*
+ * Frequency of clock used for primary clocksource
+ */
+extern unsigned long ixp4xx_timer_freq;
+
+/*
+ * Functions used by platform-level setup code
+ */
+extern void ixp4xx_map_io(void);
+extern void ixp4xx_init_irq(void);
+extern void ixp4xx_sys_init(void);
+extern void ixp4xx_timer_init(void);
+extern struct sys_timer ixp4xx_timer;
+extern void ixp4xx_pci_preinit(void);
+struct pci_sys_data;
+extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
+extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
+
+/*
+ * GPIO-functions
+ */
+/*
+ * The following converted to the real HW bits the gpio_line_config
+ */
+/* GPIO pin types */
+#define IXP4XX_GPIO_OUT                 0x1
+#define IXP4XX_GPIO_IN                  0x2
+
+/* GPIO signal types */
+#define IXP4XX_GPIO_LOW                 0
+#define IXP4XX_GPIO_HIGH                1
+
+/* GPIO Clocks */
+#define IXP4XX_GPIO_CLK_0               14
+#define IXP4XX_GPIO_CLK_1               15
+
+static inline void gpio_line_config(u8 line, u32 direction)
+{
+        if (direction == IXP4XX_GPIO_IN)
+                *IXP4XX_GPIO_GPOER |= (1 << line);
+        else
+                *IXP4XX_GPIO_GPOER &= ~(1 << line);
+}
+
+static inline void gpio_line_get(u8 line, int *value)
+{
+        *value = (*IXP4XX_GPIO_GPINR >> line) & 0x1;
+}
+
+static inline void gpio_line_set(u8 line, int value)
+{
+        if (value == IXP4XX_GPIO_HIGH)
+            *IXP4XX_GPIO_GPOUTR |= (1 << line);
+        else if (value == IXP4XX_GPIO_LOW)
+            *IXP4XX_GPIO_GPOUTR &= ~(1 << line);
+}
+
+#endif // __ASSEMBLY__
+
diff --git a/arch/arm/mach-ixp4xx/include/mach/prpmc1100.h b/arch/arm/mach-ixp4xx/include/mach/prpmc1100.h
new file mode 100644
index 000000000000..17274a2e3dec
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/prpmc1100.h
@@ -0,0 +1,33 @@
+/*
+ * arch/arm/mach-ixp4xx/include/mach/prpmc1100.h
+ *
+ * Motorolla PrPMC1100 platform specific definitions
+ *
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright 2004 (c) MontaVista, Software, Inc. 
+ * 
+ * This file is licensed under  the terms of the GNU General Public 
+ * License version 2. This program is licensed "as is" without any 
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H__
+#error "Do not include this directly, instead #include <mach/hardware.h>"
+#endif
+
+#define PRPMC1100_FLASH_BASE    IXP4XX_EXP_BUS_CS0_BASE_PHYS
+#define PRPMC1100_FLASH_SIZE    IXP4XX_EXP_BUS_CSX_REGION_SIZE
+
+#define PRPMC1100_PCI_MIN_DEVID 10
+#define PRPMC1100_PCI_MAX_DEVID 16
+#define PRPMC1100_PCI_IRQ_LINES 4
+
+
+/* PCI controller GPIO to IRQ pin mappings */
+#define PRPMC1100_PCI_INTA_PIN  11
+#define PRPMC1100_PCI_INTB_PIN  10
+#define PRPMC1100_PCI_INTC_PIN  9
+#define PRPMC1100_PCI_INTD_PIN  8
+
+
diff --git a/include/asm-arm/arch-ixp4xx/qmgr.h b/arch/arm/mach-ixp4xx/include/mach/qmgr.h
index 1e52b95cede5..1e52b95cede5 100644
--- a/include/asm-arm/arch-ixp4xx/qmgr.h
+++ b/arch/arm/mach-ixp4xx/include/mach/qmgr.h
diff --git a/arch/arm/mach-ixp4xx/include/mach/system.h b/arch/arm/mach-ixp4xx/include/mach/system.h
new file mode 100644
index 000000000000..92a7e8ddf69a
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/system.h
@@ -0,0 +1,42 @@
+/*
+ * arch/arm/mach-ixp4xx/include/mach/system.h
+ *
+ * Copyright (C) 2002 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <mach/hardware.h>
+
+static inline void arch_idle(void)
+{
+#if 0
+        if (!hlt_counter)
+                cpu_do_idle(0);
+#endif
+}
+
+
+static inline void arch_reset(char mode)
+{
+        if ( 1 && mode == 's') {
+                /* Jump into ROM at address 0 */
+                cpu_reset(0);
+        } else {
+                /* Use on-chip reset capability */
+
+                /* set the "key" register to enable access to
+                 * "timer" and "enable" registers
+                 */
+                *IXP4XX_OSWK = IXP4XX_WDT_KEY;
+
+                /* write 0 to the timer register for an immediate reset */
+                *IXP4XX_OSWT = 0;
+
+                *IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;
+        }
+}
+
diff --git a/arch/arm/mach-ixp4xx/include/mach/timex.h b/arch/arm/mach-ixp4xx/include/mach/timex.h
new file mode 100644
index 000000000000..89ce3ee84698
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/timex.h
@@ -0,0 +1,15 @@
+/*
+ * arch/arm/mach-ixp4xx/include/mach/timex.h
+ * 
+ */
+
+#include <mach/hardware.h>
+
+/*
+ * We use IXP425 General purpose timer for our timer needs, it runs at 
+ * 66.66... MHz. We do a convulted calculation of CLOCK_TICK_RATE b/c the
+ * timer register ignores the bottom 2 bits of the LATCH value.
+ */
+#define FREQ 66666666
+#define CLOCK_TICK_RATE (((FREQ / HZ & ~IXP4XX_OST_RELOAD_MASK) + 1) * HZ)
+
diff --git a/arch/arm/mach-ixp4xx/include/mach/udc.h b/arch/arm/mach-ixp4xx/include/mach/udc.h
new file mode 100644
index 000000000000..80d6da2eafac
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/udc.h
@@ -0,0 +1,8 @@
+/*
+ * arch/arm/mach-ixp4xx/include/mach/udc.h
+ *
+ */
+#include <asm/mach/udc_pxa2xx.h>
+
+extern void ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info);
+
diff --git a/arch/arm/mach-ixp4xx/include/mach/uncompress.h b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
new file mode 100644
index 000000000000..2db0078a8cf2
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
@@ -0,0 +1,57 @@
+/*
+ * arch/arm/mach-ixp4xx/include/mach/uncompress.h 
+ *
+ * Copyright (C) 2002 Intel Corporation.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _ARCH_UNCOMPRESS_H_
+#define _ARCH_UNCOMPRESS_H_
+
+#include "ixp4xx-regs.h"
+#include <asm/mach-types.h>
+#include <linux/serial_reg.h>
+
+#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE)
+
+static volatile u32* uart_base;
+
+static inline void putc(int c)
+{
+        /* Check THRE and TEMT bits before we transmit the character.
+         */
+        while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
+                barrier();
+
+        *uart_base = c;
+}
+
+static void flush(void)
+{
+}
+
+static __inline__ void __arch_decomp_setup(unsigned long arch_id)
+{
+        /*
+         * Some boards are using UART2 as console
+         */
+        if (machine_is_adi_coyote() || machine_is_gtwx5715() ||
+                         machine_is_gateway7001() || machine_is_wg302v2())
+                uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
+        else
+                uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;
+}
+
+/*
+ * arch_id is a variable in decompress_kernel()
+ */
+#define arch_decomp_setup()     __arch_decomp_setup(arch_id)
+
+#define arch_decomp_wdog()
+
+#endif
diff --git a/arch/arm/mach-ixp4xx/include/mach/vmalloc.h b/arch/arm/mach-ixp4xx/include/mach/vmalloc.h
new file mode 100644
index 000000000000..7b3580b53adf
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/vmalloc.h
@@ -0,0 +1,5 @@
+/*
+ * arch/arm/mach-ixp4xx/include/mach/vmalloc.h
+ */
+#define VMALLOC_END       (0xFF000000)
+
diff --git a/arch/arm/mach-ixp4xx/ixdp425-pci.c b/arch/arm/mach-ixp4xx/ixdp425-pci.c
index 9ec957196c70..64c29aacaac9 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-pci.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c
@@ -22,7 +22,7 @@
 
 #include <asm/mach/pci.h>
 #include <asm/irq.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 
 void __init ixdp425_pci_preinit(void)
diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c
index 8666a428f9be..9b2d2ec14c80 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
@@ -24,7 +24,7 @@
 #include <asm/types.h>
 #include <asm/setup.h>
 #include <asm/memory.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-ixp4xx/ixdpg425-pci.c b/arch/arm/mach-ixp4xx/ixdpg425-pci.c
index fac9e5cdab20..4ed7ac614920 100644
--- a/arch/arm/mach-ixp4xx/ixdpg425-pci.c
+++ b/arch/arm/mach-ixp4xx/ixdpg425-pci.c
@@ -19,7 +19,7 @@
 #include <linux/irq.h>
 
 #include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 #include <asm/mach/pci.h>
 
diff --git a/arch/arm/mach-ixp4xx/ixp4xx_npe.c b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
index 63a23fa4aab4..c73a94d0ca2b 100644
--- a/arch/arm/mach-ixp4xx/ixp4xx_npe.c
+++ b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
@@ -21,7 +21,7 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/slab.h>
-#include <asm/arch/npe.h>
+#include <mach/npe.h>
 
 #define DEBUG_MSG                       0
 #define DEBUG_FW                        0
diff --git a/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
index fab94eaecee7..c6cb069a5a83 100644
--- a/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
+++ b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
@@ -12,7 +12,7 @@
 #include <linux/interrupt.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
-#include <asm/arch/qmgr.h>
+#include <mach/qmgr.h>
 
 #define DEBUG           0
 
diff --git a/arch/arm/mach-ixp4xx/wg302v2-pci.c b/arch/arm/mach-ixp4xx/wg302v2-pci.c
index 0fd513af9a45..9b59ed03b151 100644
--- a/arch/arm/mach-ixp4xx/wg302v2-pci.c
+++ b/arch/arm/mach-ixp4xx/wg302v2-pci.c
@@ -23,7 +23,7 @@
 #include <linux/irq.h>
 
 #include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 #include <asm/mach/pci.h>
 
diff --git a/arch/arm/mach-ixp4xx/wg302v2-setup.c b/arch/arm/mach-ixp4xx/wg302v2-setup.c
index c426dcb5b9b3..7ea782021d1f 100644
--- a/arch/arm/mach-ixp4xx/wg302v2-setup.c
+++ b/arch/arm/mach-ixp4xx/wg302v2-setup.c
@@ -23,7 +23,7 @@
 #include <asm/types.h>
 #include <asm/setup.h>
 #include <asm/memory.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
index 8a7ebe9ad7f1..c79f492072f9 100644
--- a/arch/arm/mach-kirkwood/addr-map.c
+++ b/arch/arm/mach-kirkwood/addr-map.c
@@ -12,7 +12,7 @@
 #include <linux/init.h>
 #include <linux/mbus.h>
 #include <linux/io.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include "common.h"
 
 /*
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 5938a3b33cdc..0e509b8ad56e 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -19,7 +19,7 @@
 #include <asm/timex.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <asm/arch/kirkwood.h>
+#include <mach/kirkwood.h>
 #include <asm/plat-orion/cache-feroceon-l2.h>
 #include <asm/plat-orion/ehci-orion.h>
 #include <asm/plat-orion/orion_nand.h>
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index d5c482c628e3..610fb24d8ae2 100644
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -21,7 +21,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
-#include <asm/arch/kirkwood.h>
+#include <mach/kirkwood.h>
 #include "common.h"
 
 static struct mv643xx_eth_platform_data db88f6281_ge00_data = {
diff --git a/arch/arm/mach-kirkwood/include/mach/debug-macro.S b/arch/arm/mach-kirkwood/include/mach/debug-macro.S
new file mode 100644
index 000000000000..c0cc5b5c82ac
--- /dev/null
+++ b/arch/arm/mach-kirkwood/include/mach/debug-macro.S
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/mach-kirkwood/include/mach/debug-macro.S
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <mach/kirkwood.h>
+
+        .macro  addruart,rx
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1                                 @ MMU enabled?
+        ldreq   \rx, =KIRKWOOD_REGS_PHYS_BASE
+        ldrne   \rx, =KIRKWOOD_REGS_VIRT_BASE
+        orr     \rx, \rx, #0x00012000
+        .endm
+
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-kirkwood/dma.h b/arch/arm/mach-kirkwood/include/mach/dma.h
index 40a8c178f10d..40a8c178f10d 100644
--- a/include/asm-arm/arch-kirkwood/dma.h
+++ b/arch/arm/mach-kirkwood/include/mach/dma.h
diff --git a/arch/arm/mach-kirkwood/include/mach/entry-macro.S b/arch/arm/mach-kirkwood/include/mach/entry-macro.S
new file mode 100644
index 000000000000..83e0cba77b36
--- /dev/null
+++ b/arch/arm/mach-kirkwood/include/mach/entry-macro.S
@@ -0,0 +1,40 @@
+/*
+ * arch/arm/mach-kirkwood/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for Marvell Kirkwood platforms
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <mach/kirkwood.h>
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =IRQ_VIRT_BASE
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        @ check low interrupts
+        ldr     \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
+        ldr     \tmp, [\base, #IRQ_MASK_LOW_OFF]
+        mov     \irqnr, #31
+        ands    \irqstat, \irqstat, \tmp
+        bne     1001f
+
+        @ if no low interrupts set, check high interrupts
+        ldr     \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
+        ldr     \tmp, [\base, #IRQ_MASK_HIGH_OFF]
+        mov     \irqnr, #63
+        ands    \irqstat, \irqstat, \tmp
+
+        @ find first active interrupt source
+1001:   clzne   \irqstat, \irqstat
+        subne   \irqnr, \irqnr, \irqstat
+        .endm
diff --git a/arch/arm/mach-kirkwood/include/mach/hardware.h b/arch/arm/mach-kirkwood/include/mach/hardware.h
new file mode 100644
index 000000000000..cde85283f7d3
--- /dev/null
+++ b/arch/arm/mach-kirkwood/include/mach/hardware.h
@@ -0,0 +1,21 @@
+/*
+ * arch/arm/mach-kirkwood/include/mach/hardware.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include "kirkwood.h"
+
+#define pcibios_assign_all_busses()     1
+
+#define PCIBIOS_MIN_IO                  0x00001000
+#define PCIBIOS_MIN_MEM                 0x01000000
+#define PCIMEM_BASE                     KIRKWOOD_PCIE_MEM_PHYS_BASE /* mem base for VGA */
+
+
+#endif
diff --git a/arch/arm/mach-kirkwood/include/mach/io.h b/arch/arm/mach-kirkwood/include/mach/io.h
new file mode 100644
index 000000000000..be07be0ef522
--- /dev/null
+++ b/arch/arm/mach-kirkwood/include/mach/io.h
@@ -0,0 +1,26 @@
+/*
+ * arch/arm/mach-kirkwood/include/mach/io.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#include "kirkwood.h"
+
+#define IO_SPACE_LIMIT          0xffffffff
+
+static inline void __iomem *__io(unsigned long addr)
+{
+        return (void __iomem *)((addr - KIRKWOOD_PCIE_IO_PHYS_BASE)
+                                        + KIRKWOOD_PCIE_IO_VIRT_BASE);
+}
+
+#define __io(a)                 __io(a)
+#define __mem_pci(a)            (a)
+
+
+#endif
diff --git a/arch/arm/mach-kirkwood/include/mach/irqs.h b/arch/arm/mach-kirkwood/include/mach/irqs.h
new file mode 100644
index 000000000000..6fd05838c72d
--- /dev/null
+++ b/arch/arm/mach-kirkwood/include/mach/irqs.h
@@ -0,0 +1,63 @@
+/*
+ * arch/arm/mach-kirkwood/include/mach/irqs.h
+ *
+ * IRQ definitions for Marvell Kirkwood SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#include "kirkwood.h"   /* need GPIO_MAX */
+
+/*
+ * Low Interrupt Controller
+ */
+#define IRQ_KIRKWOOD_HIGH_SUM   0
+#define IRQ_KIRKWOOD_BRIDGE     1
+#define IRQ_KIRKWOOD_HOST2CPU   2
+#define IRQ_KIRKWOOD_CPU2HOST   3
+#define IRQ_KIRKWOOD_XOR_00     5
+#define IRQ_KIRKWOOD_XOR_01     6
+#define IRQ_KIRKWOOD_XOR_10     7
+#define IRQ_KIRKWOOD_XOR_11     8
+#define IRQ_KIRKWOOD_PCIE       9
+#define IRQ_KIRKWOOD_GE00_SUM   11
+#define IRQ_KIRKWOOD_GE01_SUM   15
+#define IRQ_KIRKWOOD_USB        19
+#define IRQ_KIRKWOOD_SATA       21
+#define IRQ_KIRKWOOD_CRYPTO     22
+#define IRQ_KIRKWOOD_SPI        23
+#define IRQ_KIRKWOOD_I2S        24
+#define IRQ_KIRKWOOD_TS_0       26
+#define IRQ_KIRKWOOD_SDIO       28
+#define IRQ_KIRKWOOD_TWSI       29
+#define IRQ_KIRKWOOD_AVB        30
+#define IRQ_KIRKWOOD_TDMI       31
+
+/*
+ * High Interrupt Controller
+ */
+#define IRQ_KIRKWOOD_UART_0     33
+#define IRQ_KIRKWOOD_UART_1     34
+#define IRQ_KIRKWOOD_GPIO_LOW_0_7       35
+#define IRQ_KIRKWOOD_GPIO_LOW_8_15      36
+#define IRQ_KIRKWOOD_GPIO_LOW_16_23     37
+#define IRQ_KIRKWOOD_GPIO_LOW_24_31     38
+#define IRQ_KIRKWOOD_GPIO_HIGH_0_7      39
+#define IRQ_KIRKWOOD_GPIO_HIGH_8_15     40
+#define IRQ_KIRKWOOD_GPIO_HIGH_16_23    41
+
+/*
+ * KIRKWOOD General Purpose Pins
+ */
+#define IRQ_KIRKWOOD_GPIO_START 64
+#define NR_GPIO_IRQS            GPIO_MAX
+
+#define NR_IRQS                 (IRQ_KIRKWOOD_GPIO_START + NR_GPIO_IRQS)
+
+
+#endif
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
new file mode 100644
index 000000000000..d1336b41f0fb
--- /dev/null
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -0,0 +1,100 @@
+/*
+ * arch/arm/mach-kirkwood/include/mach/kirkwood.h
+ *
+ * Generic definitions for Marvell Kirkwood SoC flavors:
+ *  88F6180, 88F6192 and 88F6281.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_KIRKWOOD_H
+#define __ASM_ARCH_KIRKWOOD_H
+
+/*
+ * Marvell Kirkwood address maps.
+ *
+ * phys
+ * e0000000     PCIe Memory space
+ * f1000000     on-chip peripheral registers
+ * f2000000     PCIe I/O space
+ * f3000000     NAND controller address window
+ *
+ * virt         phys            size
+ * fee00000     f1000000        1M      on-chip peripheral registers
+ * fef00000     f2000000        1M      PCIe I/O space
+ */
+
+#define KIRKWOOD_NAND_MEM_PHYS_BASE     0xf3000000
+#define KIRKWOOD_NAND_MEM_SIZE          SZ_64K /* 1K is sufficient, but 64K
+                                                * is the minimal window size
+                                                */
+
+#define KIRKWOOD_PCIE_IO_PHYS_BASE      0xf2000000
+#define KIRKWOOD_PCIE_IO_VIRT_BASE      0xfef00000
+#define KIRKWOOD_PCIE_IO_BUS_BASE       0x00000000
+#define KIRKWOOD_PCIE_IO_SIZE           SZ_1M
+
+#define KIRKWOOD_REGS_PHYS_BASE         0xf1000000
+#define KIRKWOOD_REGS_VIRT_BASE         0xfee00000
+#define KIRKWOOD_REGS_SIZE              SZ_1M
+
+#define KIRKWOOD_PCIE_MEM_PHYS_BASE     0xe0000000
+#define KIRKWOOD_PCIE_MEM_SIZE          SZ_128M
+
+/*
+ * MBUS bridge registers.
+ */
+#define BRIDGE_VIRT_BASE        (KIRKWOOD_REGS_VIRT_BASE | 0x20000)
+#define  CPU_CONTROL            (BRIDGE_VIRT_BASE | 0x0104)
+#define   CPU_RESET             0x00000002
+#define  RSTOUTn_MASK           (BRIDGE_VIRT_BASE | 0x0108)
+#define   SOFT_RESET_OUT_EN     0x00000004
+#define  SYSTEM_SOFT_RESET      (BRIDGE_VIRT_BASE | 0x010c)
+#define   SOFT_RESET            0x00000001
+#define  BRIDGE_CAUSE           (BRIDGE_VIRT_BASE | 0x0110)
+#define  BRIDGE_MASK            (BRIDGE_VIRT_BASE | 0x0114)
+#define   BRIDGE_INT_TIMER0     0x0002
+#define   BRIDGE_INT_TIMER1     0x0004
+#define   BRIDGE_INT_TIMER1_CLR (~0x0004)
+#define  IRQ_VIRT_BASE          (BRIDGE_VIRT_BASE | 0x0200)
+#define   IRQ_CAUSE_LOW_OFF     0x0000
+#define   IRQ_MASK_LOW_OFF      0x0004
+#define   IRQ_CAUSE_HIGH_OFF    0x0010
+#define   IRQ_MASK_HIGH_OFF     0x0014
+#define  TIMER_VIRT_BASE        (BRIDGE_VIRT_BASE | 0x0300)
+#define  L2_CONFIG_REG          (BRIDGE_VIRT_BASE | 0x0128)
+#define   L2_WRITETHROUGH       0x00000010
+
+/*
+ * Register Map
+ */
+#define DDR_VIRT_BASE           (KIRKWOOD_REGS_VIRT_BASE | 0x00000)
+#define  DDR_WINDOW_CPU_BASE    (DDR_VIRT_BASE | 0x1500)
+
+#define DEV_BUS_PHYS_BASE       (KIRKWOOD_REGS_PHYS_BASE | 0x10000)
+#define DEV_BUS_VIRT_BASE       (KIRKWOOD_REGS_VIRT_BASE | 0x10000)
+#define  SAMPLE_AT_RESET        (DEV_BUS_VIRT_BASE | 0x0030)
+#define  DEVICE_ID              (DEV_BUS_VIRT_BASE | 0x0034)
+#define  RTC_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x0300)
+#define  SPI_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x0600)
+#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2000)
+#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2000)
+#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2100)
+#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2100)
+
+#define PCIE_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
+
+#define USB_PHYS_BASE           (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
+
+#define GE00_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x70000)
+#define GE01_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x74000)
+
+#define SATA_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x80000)
+
+
+#define GPIO_MAX                50
+
+
+#endif
diff --git a/arch/arm/mach-kirkwood/include/mach/memory.h b/arch/arm/mach-kirkwood/include/mach/memory.h
new file mode 100644
index 000000000000..b5fb34bdccd5
--- /dev/null
+++ b/arch/arm/mach-kirkwood/include/mach/memory.h
@@ -0,0 +1,14 @@
+/*
+ * arch/arm/mach-kirkwood/include/mach/memory.h
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#define PHYS_OFFSET             UL(0x00000000)
+
+#define __virt_to_bus(x)        __virt_to_phys(x)
+#define __bus_to_virt(x)        __phys_to_virt(x)
+
+
+#endif
diff --git a/arch/arm/mach-kirkwood/include/mach/system.h b/arch/arm/mach-kirkwood/include/mach/system.h
new file mode 100644
index 000000000000..8510f6cfdabf
--- /dev/null
+++ b/arch/arm/mach-kirkwood/include/mach/system.h
@@ -0,0 +1,37 @@
+/*
+ * arch/arm/mach-kirkwood/include/mach/system.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <mach/hardware.h>
+#include <mach/kirkwood.h>
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        /*
+         * Enable soft reset to assert RSTOUTn.
+         */
+        writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
+
+        /*
+         * Assert soft reset.
+         */
+        writel(SOFT_RESET, SYSTEM_SOFT_RESET);
+
+        while (1)
+                ;
+}
+
+
+#endif
diff --git a/arch/arm/mach-kirkwood/include/mach/timex.h b/arch/arm/mach-kirkwood/include/mach/timex.h
new file mode 100644
index 000000000000..f77ef4a32c5f
--- /dev/null
+++ b/arch/arm/mach-kirkwood/include/mach/timex.h
@@ -0,0 +1,11 @@
+/*
+ * arch/arm/mach-kirkwood/include/mach/timex.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#define CLOCK_TICK_RATE         (100 * HZ)
+
+#define KIRKWOOD_TCLK           166666667
diff --git a/arch/arm/mach-kirkwood/include/mach/uncompress.h b/arch/arm/mach-kirkwood/include/mach/uncompress.h
new file mode 100644
index 000000000000..75d5497df3a8
--- /dev/null
+++ b/arch/arm/mach-kirkwood/include/mach/uncompress.h
@@ -0,0 +1,47 @@
+/*
+ * arch/arm/mach-kirkwood/include/mach/uncompress.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/serial_reg.h>
+#include <mach/kirkwood.h>
+
+#define SERIAL_BASE     ((unsigned char *)UART0_PHYS_BASE)
+
+static void putc(const char c)
+{
+        unsigned char *base = SERIAL_BASE;
+        int i;
+
+        for (i = 0; i < 0x1000; i++) {
+                if (base[UART_LSR << 2] & UART_LSR_THRE)
+                        break;
+                barrier();
+        }
+
+        base[UART_TX << 2] = c;
+}
+
+static void flush(void)
+{
+        unsigned char *base = SERIAL_BASE;
+        unsigned char mask;
+        int i;
+
+        mask = UART_LSR_TEMT | UART_LSR_THRE;
+
+        for (i = 0; i < 0x1000; i++) {
+                if ((base[UART_LSR << 2] & mask) == mask)
+                        break;
+                barrier();
+        }
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-kirkwood/include/mach/vmalloc.h b/arch/arm/mach-kirkwood/include/mach/vmalloc.h
new file mode 100644
index 000000000000..8f48260dcdad
--- /dev/null
+++ b/arch/arm/mach-kirkwood/include/mach/vmalloc.h
@@ -0,0 +1,5 @@
+/*
+ * arch/arm/mach-kirkwood/include/mach/vmalloc.h
+ */
+
+#define VMALLOC_END     0xfe800000
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
index 6cf642c504d3..182230a5d198 100644
--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -21,7 +21,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
-#include <asm/arch/kirkwood.h>
+#include <mach/kirkwood.h>
 #include "common.h"
 
 #define RD88F6192_GPIO_USB_VBUS         10
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index b6437f47a77f..d8a43018c7d3 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -22,7 +22,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
-#include <asm/arch/kirkwood.h>
+#include <mach/kirkwood.h>
 #include <asm/plat-orion/orion_nand.h>
 #include "common.h"
 
diff --git a/arch/arm/mach-ks8695/board-micrel.c b/arch/arm/mach-ks8695/board-micrel.c
index 05ac2bd04020..0468e93b7d3b 100644
--- a/arch/arm/mach-ks8695/board-micrel.c
+++ b/arch/arm/mach-ks8695/board-micrel.c
@@ -18,7 +18,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/devices.h>
+#include <mach/devices.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-ks8695/cpu.c b/arch/arm/mach-ks8695/cpu.c
index 97ab618fc358..c6c08e800233 100644
--- a/arch/arm/mach-ks8695/cpu.c
+++ b/arch/arm/mach-ks8695/cpu.c
@@ -25,13 +25,13 @@
 #include <linux/module.h>
 #include <linux/init.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <asm/arch/regs-sys.h>
-#include <asm/arch/regs-misc.h>
+#include <mach/regs-sys.h>
+#include <mach/regs-misc.h>
 
 
 static struct __initdata map_desc ks8695_io_desc[] = {
diff --git a/arch/arm/mach-ks8695/devices.c b/arch/arm/mach-ks8695/devices.c
index 3db2ec61d06f..4bd251482c8f 100644
--- a/arch/arm/mach-ks8695/devices.c
+++ b/arch/arm/mach-ks8695/devices.c
@@ -22,9 +22,9 @@
 
 #include <linux/platform_device.h>
 
-#include <asm/arch/regs-wan.h>
-#include <asm/arch/regs-lan.h>
-#include <asm/arch/regs-hpna.h>
+#include <mach/regs-wan.h>
+#include <mach/regs-lan.h>
+#include <mach/regs-hpna.h>
 
 
 /* --------------------------------------------------------------------
diff --git a/arch/arm/mach-ks8695/gpio.c b/arch/arm/mach-ks8695/gpio.c
index a1e46436a940..3624e65cd89b 100644
--- a/arch/arm/mach-ks8695/gpio.c
+++ b/arch/arm/mach-ks8695/gpio.c
@@ -25,11 +25,11 @@
 #include <linux/module.h>
 
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/gpio.h>
+#include <mach/regs-gpio.h>
+#include <mach/gpio.h>
 
 /*
  * Configure a GPIO line for either GPIO function, or its internal
diff --git a/arch/arm/mach-ks8695/include/mach/debug-macro.S b/arch/arm/mach-ks8695/include/mach/debug-macro.S
new file mode 100644
index 000000000000..3782c3559497
--- /dev/null
+++ b/arch/arm/mach-ks8695/include/mach/debug-macro.S
@@ -0,0 +1,38 @@
+/*
+ * arch/arm/mach-ks8695/include/mach/debug-macro.S
+ *
+ * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
+ * Copyright (C) 2006 Simtec Electronics
+ *
+ * KS8695 - Debug macros
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <mach/hardware.h>
+#include <mach/regs-uart.h>
+
+        .macro  addruart, rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                         @ MMU enabled?
+                ldreq   \rx, =KS8695_UART_PA            @ physical base address
+                ldrne   \rx, =KS8695_UART_VA            @ virtual base address
+        .endm
+
+        .macro  senduart, rd, rx
+                str     \rd, [\rx, #KS8695_URTH]        @ Write to Transmit Holding Register
+        .endm
+
+        .macro  busyuart, rd, rx
+1001:           ldr     \rd, [\rx, #KS8695_URLS]        @ Read Line Status Register
+                tst     \rd, #URLS_URTE                 @ Holding & Shift registers empty?
+                beq     1001b
+        .endm
+
+        .macro  waituart, rd, rx
+1001:           ldr     \rd, [\rx, #KS8695_URLS]        @ Read Line Status Register
+                tst     \rd, #URLS_URTHRE               @ Holding Register empty?
+                beq     1001b
+        .endm
diff --git a/arch/arm/mach-ks8695/include/mach/devices.h b/arch/arm/mach-ks8695/include/mach/devices.h
new file mode 100644
index 000000000000..2744fecb429c
--- /dev/null
+++ b/arch/arm/mach-ks8695/include/mach/devices.h
@@ -0,0 +1,37 @@
+/*
+ * arch/arm/mach-ks8695/include/mach/devices.h
+ *
+ * Copyright (C) 2006 Andrew Victor
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_DEVICES_H
+#define __ASM_ARCH_DEVICES_H
+
+#include <linux/pci.h>
+
+ /* Ethernet */
+extern void __init ks8695_add_device_wan(void);
+extern void __init ks8695_add_device_lan(void);
+extern void __init ks8695_add_device_hpna(void);
+
+ /* LEDs */
+extern short ks8695_leds_cpu;
+extern short ks8695_leds_timer;
+extern void __init ks8695_init_leds(u8 cpu_led, u8 timer_led);
+
+ /* PCI */
+#define KS8695_MODE_PCI         0
+#define KS8695_MODE_MINIPCI     1
+#define KS8695_MODE_CARDBUS     2
+
+struct ks8695_pci_cfg {
+        short mode;
+        int (*map_irq)(struct pci_dev *, u8, u8);
+};
+extern __init void ks8695_init_pci(struct ks8695_pci_cfg *);
+
+#endif
diff --git a/arch/arm/mach-ks8695/include/mach/dma.h b/arch/arm/mach-ks8695/include/mach/dma.h
new file mode 100644
index 000000000000..561206280089
--- /dev/null
+++ b/arch/arm/mach-ks8695/include/mach/dma.h
@@ -0,0 +1,17 @@
+/*
+ * arch/arm/mach-ks8695/include/mach/dma.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
diff --git a/arch/arm/mach-ks8695/include/mach/entry-macro.S b/arch/arm/mach-ks8695/include/mach/entry-macro.S
new file mode 100644
index 000000000000..b4fe0c11c6ce
--- /dev/null
+++ b/arch/arm/mach-ks8695/include/mach/entry-macro.S
@@ -0,0 +1,53 @@
+/*
+ * arch/arm/mach-ks8695/include/mach/entry-macro.S
+ *
+ * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
+ * Copyright (C) 2006 Simtec Electronics
+ *
+ * Low-level IRQ helper macros for KS8695
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+*/
+
+#include <mach/hardware.h>
+#include <mach/regs-irq.h>
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+                ldr     \base, =KS8695_IRQ_VA                   @ Base address of interrupt controller
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                ldr     \irqstat, [\base, #KS8695_INTMS]        @ Mask Status register
+
+                teq     \irqstat, #0
+                beq     1001f
+
+                mov     \irqnr, #0
+
+                tst     \irqstat, #0xff
+                moveq   \irqstat, \irqstat, lsr #8
+                addeq   \irqnr, \irqnr, #8
+                tsteq   \irqstat, #0xff
+                moveq   \irqstat, \irqstat, lsr #8
+                addeq   \irqnr, \irqnr, #8
+                tsteq   \irqstat, #0xff
+                moveq   \irqstat, \irqstat, lsr #8
+                addeq   \irqnr, \irqnr, #8
+                tst     \irqstat, #0x0f
+                moveq   \irqstat, \irqstat, lsr #4
+                addeq   \irqnr, \irqnr, #4
+                tst     \irqstat, #0x03
+                moveq   \irqstat, \irqstat, lsr #2
+                addeq   \irqnr, \irqnr, #2
+                tst     \irqstat, #0x01
+                addeqs  \irqnr, \irqnr, #1
+1001:
+        .endm
diff --git a/arch/arm/mach-ks8695/include/mach/gpio.h b/arch/arm/mach-ks8695/include/mach/gpio.h
new file mode 100644
index 000000000000..73c84168761c
--- /dev/null
+++ b/arch/arm/mach-ks8695/include/mach/gpio.h
@@ -0,0 +1,79 @@
+/*
+ * arch/arm/mach-ks8695/include/mach/gpio.h
+ *
+ * Copyright (C) 2006 Andrew Victor
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_GPIO_H_
+#define __ASM_ARCH_GPIO_H_
+
+#define KS8695_GPIO_0           0
+#define KS8695_GPIO_1           1
+#define KS8695_GPIO_2           2
+#define KS8695_GPIO_3           3
+#define KS8695_GPIO_4           4
+#define KS8695_GPIO_5           5
+#define KS8695_GPIO_6           6
+#define KS8695_GPIO_7           7
+#define KS8695_GPIO_8           8
+#define KS8695_GPIO_9           9
+#define KS8695_GPIO_10          10
+#define KS8695_GPIO_11          11
+#define KS8695_GPIO_12          12
+#define KS8695_GPIO_13          13
+#define KS8695_GPIO_14          14
+#define KS8695_GPIO_15          15
+
+
+/*
+ * Configure GPIO pin as external interrupt source.
+ */
+int __init_or_module ks8695_gpio_interrupt(unsigned int pin, unsigned int type);
+
+/*
+ * Configure the GPIO line as an input.
+ */
+int __init_or_module gpio_direction_input(unsigned int pin);
+
+/*
+ * Configure the GPIO line as an output, with default state.
+ */
+int __init_or_module gpio_direction_output(unsigned int pin, unsigned int state);
+
+/*
+ * Set the state of an output GPIO line.
+ */
+void gpio_set_value(unsigned int pin, unsigned int state);
+
+/*
+ * Read the state of a GPIO line.
+ */
+int gpio_get_value(unsigned int pin);
+
+/*
+ * Map GPIO line to IRQ number.
+ */
+int gpio_to_irq(unsigned int pin);
+
+/*
+ * Map IRQ number to GPIO line.
+ */
+int irq_to_gpio(unsigned int irq);
+
+
+#include <asm-generic/gpio.h>
+
+static inline int gpio_request(unsigned int pin, const char *label)
+{
+        return 0;
+}
+
+static inline void gpio_free(unsigned int pin)
+{
+}
+
+#endif
diff --git a/arch/arm/mach-ks8695/include/mach/hardware.h b/arch/arm/mach-ks8695/include/mach/hardware.h
new file mode 100644
index 000000000000..1d640d075b7e
--- /dev/null
+++ b/arch/arm/mach-ks8695/include/mach/hardware.h
@@ -0,0 +1,49 @@
+/*
+ * arch/arm/mach-ks8695/include/mach/hardware.h
+ *
+ * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
+ * Copyright (C) 2006 Simtec Electronics
+ *
+ * KS8695 - Memory Map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/sizes.h>
+
+/*
+ * Physical RAM address.
+ */
+#define KS8695_SDRAM_PA         0x00000000
+
+
+/*
+ * We map an entire MiB with the System Configuration Registers in even
+ * though only 64KiB is needed. This makes it easier for use with the
+ * head debug code as the initial MMU setup only deals in L1 sections.
+ */
+#define KS8695_IO_PA            0x03F00000
+#define KS8695_IO_VA            0xF0000000
+#define KS8695_IO_SIZE          SZ_1M
+
+#define KS8695_PCIMEM_PA        0x60000000
+#define KS8695_PCIMEM_SIZE      SZ_512M
+
+#define KS8695_PCIIO_PA         0x80000000
+#define KS8695_PCIIO_SIZE       SZ_64K
+
+
+/*
+ * PCI support
+ */
+#define pcibios_assign_all_busses()     1
+
+#define PCIBIOS_MIN_IO          0
+#define PCIBIOS_MIN_MEM         0
+
+#endif
diff --git a/arch/arm/mach-ks8695/include/mach/io.h b/arch/arm/mach-ks8695/include/mach/io.h
new file mode 100644
index 000000000000..f364f24ffe1e
--- /dev/null
+++ b/arch/arm/mach-ks8695/include/mach/io.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-ks8695/include/mach/io.h
+ *
+ * Copyright (C) 2006 Andrew Victor
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT          0xffffffff
+
+#define __io(a)                 ((void __iomem *)(a))
+#define __mem_pci(a)            (a)
+
+#endif
diff --git a/arch/arm/mach-ks8695/include/mach/irqs.h b/arch/arm/mach-ks8695/include/mach/irqs.h
new file mode 100644
index 000000000000..86fc9e6ce404
--- /dev/null
+++ b/arch/arm/mach-ks8695/include/mach/irqs.h
@@ -0,0 +1,54 @@
+/*
+ * arch/arm/mach-ks8695/include/mach/irqs.h
+ *
+ * Copyright (C) 2006 Simtec Electronics
+ *   Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+
+#define NR_IRQS                         32
+
+/*
+ * IRQ definitions
+ */
+#define KS8695_IRQ_COMM_RX              0
+#define KS8695_IRQ_COMM_TX              1
+#define KS8695_IRQ_EXTERN0              2
+#define KS8695_IRQ_EXTERN1              3
+#define KS8695_IRQ_EXTERN2              4
+#define KS8695_IRQ_EXTERN3              5
+#define KS8695_IRQ_TIMER0               6
+#define KS8695_IRQ_TIMER1               7
+#define KS8695_IRQ_UART_TX              8
+#define KS8695_IRQ_UART_RX              9
+#define KS8695_IRQ_UART_LINE_STATUS     10
+#define KS8695_IRQ_UART_MODEM_STATUS    11
+#define KS8695_IRQ_LAN_RX_STOP          12
+#define KS8695_IRQ_LAN_TX_STOP          13
+#define KS8695_IRQ_LAN_RX_BUF           14
+#define KS8695_IRQ_LAN_TX_BUF           15
+#define KS8695_IRQ_LAN_RX_STATUS        16
+#define KS8695_IRQ_LAN_TX_STATUS        17
+#define KS8695_IRQ_HPNA_RX_STOP         18
+#define KS8695_IRQ_HPNA_TX_STOP         19
+#define KS8695_IRQ_HPNA_RX_BUF          20
+#define KS8695_IRQ_HPNA_TX_BUF          21
+#define KS8695_IRQ_HPNA_RX_STATUS       22
+#define KS8695_IRQ_HPNA_TX_STATUS       23
+#define KS8695_IRQ_BUS_ERROR            24
+#define KS8695_IRQ_WAN_RX_STOP          25
+#define KS8695_IRQ_WAN_TX_STOP          26
+#define KS8695_IRQ_WAN_RX_BUF           27
+#define KS8695_IRQ_WAN_TX_BUF           28
+#define KS8695_IRQ_WAN_RX_STATUS        29
+#define KS8695_IRQ_WAN_TX_STATUS        30
+#define KS8695_IRQ_WAN_LINK             31
+
+#endif
diff --git a/arch/arm/mach-ks8695/include/mach/memory.h b/arch/arm/mach-ks8695/include/mach/memory.h
new file mode 100644
index 000000000000..dadbe66cb75c
--- /dev/null
+++ b/arch/arm/mach-ks8695/include/mach/memory.h
@@ -0,0 +1,49 @@
+/*
+ * arch/arm/mach-ks8695/include/mach/memory.h
+ *
+ * Copyright (C) 2006 Andrew Victor
+ *
+ * KS8695 Memory definitions
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#include <mach/hardware.h>
+
+/*
+ * Physical SRAM offset.
+ */
+#define PHYS_OFFSET             KS8695_SDRAM_PA
+
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_PCI
+
+/* PCI mappings */
+#define __virt_to_bus(x)        ((x) - PAGE_OFFSET + KS8695_PCIMEM_PA)
+#define __bus_to_virt(x)        ((x) - KS8695_PCIMEM_PA + PAGE_OFFSET)
+
+/* Platform-bus mapping */
+extern struct bus_type platform_bus_type;
+#define is_lbus_device(dev)             (dev && dev->bus == &platform_bus_type)
+#define __arch_dma_to_virt(dev, x)      ({ is_lbus_device(dev) ? \
+                                        __phys_to_virt(x) : __bus_to_virt(x); })
+#define __arch_virt_to_dma(dev, x)      ({ is_lbus_device(dev) ? \
+                                        (dma_addr_t)__virt_to_phys(x) : (dma_addr_t)__virt_to_bus(x); })
+#define __arch_page_to_dma(dev, x)      __arch_virt_to_dma(dev, page_address(x))
+
+#else
+
+#define __virt_to_bus(x)        __virt_to_phys(x)
+#define __bus_to_virt(x)        __phys_to_virt(x)
+
+#endif
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-ks8695/include/mach/regs-gpio.h b/arch/arm/mach-ks8695/include/mach/regs-gpio.h
new file mode 100644
index 000000000000..0df6fe61d1ce
--- /dev/null
+++ b/arch/arm/mach-ks8695/include/mach/regs-gpio.h
@@ -0,0 +1,55 @@
+/*
+ * arch/arm/mach-ks8695/include/mach/regs-gpio.h
+ *
+ * Copyright (C) 2007 Andrew Victor
+ *
+ * KS8695 - GPIO control registers and bit definitions.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef KS8695_GPIO_H
+#define KS8695_GPIO_H
+
+#define KS8695_GPIO_OFFSET      (0xF0000 + 0xE600)
+#define KS8695_GPIO_VA          (KS8695_IO_VA + KS8695_GPIO_OFFSET)
+#define KS8695_GPIO_PA          (KS8695_IO_PA + KS8695_GPIO_OFFSET)
+
+
+#define KS8695_IOPM             (0x00)          /* I/O Port Mode Register */
+#define KS8695_IOPC             (0x04)          /* I/O Port Control Register */
+#define KS8695_IOPD             (0x08)          /* I/O Port Data Register */
+
+
+/* Port Mode Register */
+#define IOPM_(x)                (1 << (x))      /* Mode for GPIO Pin x */
+
+/* Port Control Register */
+#define IOPC_IOTIM1EN           (1 << 17)       /* GPIO Pin for Timer1 Enable */
+#define IOPC_IOTIM0EN           (1 << 16)       /* GPIO Pin for Timer0 Enable */
+#define IOPC_IOEINT3EN          (1 << 15)       /* GPIO Pin for External/Soft Interrupt 3 Enable */
+#define IOPC_IOEINT3TM          (7 << 12)       /* GPIO Pin for External/Soft Interrupt 3 Trigger Mode */
+#define IOPC_IOEINT3_MODE(x)    ((x) << 12)
+#define IOPC_IOEINT2EN          (1 << 11)       /* GPIO Pin for External/Soft Interrupt 2 Enable */
+#define IOPC_IOEINT2TM          (7 << 8)        /* GPIO Pin for External/Soft Interrupt 2 Trigger Mode */
+#define IOPC_IOEINT2_MODE(x)    ((x) << 8)
+#define IOPC_IOEINT1EN          (1 << 7)        /* GPIO Pin for External/Soft Interrupt 1 Enable */
+#define IOPC_IOEINT1TM          (7 << 4)        /* GPIO Pin for External/Soft Interrupt 1 Trigger Mode */
+#define IOPC_IOEINT1_MODE(x)    ((x) << 4)
+#define IOPC_IOEINT0EN          (1 << 3)        /* GPIO Pin for External/Soft Interrupt 0 Enable */
+#define IOPC_IOEINT0TM          (7 << 0)        /* GPIO Pin for External/Soft Interrupt 0 Trigger Mode */
+#define IOPC_IOEINT0_MODE(x)    ((x) << 0)
+
+ /* Trigger Modes */
+#define IOPC_TM_LOW             (0)             /* Level Detection (Active Low) */
+#define IOPC_TM_HIGH            (1)             /* Level Detection (Active High) */
+#define IOPC_TM_RISING          (2)             /* Rising Edge Detection */
+#define IOPC_TM_FALLING         (4)             /* Falling Edge Detection */
+#define IOPC_TM_EDGE            (6)             /* Both Edge Detection */
+
+/* Port Data Register */
+#define IOPD_(x)                (1 << (x))      /* Signal Level of GPIO Pin x */
+
+#endif
diff --git a/arch/arm/mach-ks8695/include/mach/regs-hpna.h b/arch/arm/mach-ks8695/include/mach/regs-hpna.h
new file mode 100644
index 000000000000..815ce5c2e3b9
--- /dev/null
+++ b/arch/arm/mach-ks8695/include/mach/regs-hpna.h
@@ -0,0 +1,25 @@
+/*
+ * arch/arm/mach-ks8695/include/mach/regs-wan.h
+ *
+ * Copyright (C) 2006 Andrew Victor
+ *
+ * KS8695 - HPNA Registers and bit definitions.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef KS8695_HPNA_H
+#define KS8695_HPNA_H
+
+#define KS8695_HPNA_OFFSET      (0xF0000 + 0xA000)
+#define KS8695_HPNA_VA          (KS8695_IO_VA + KS8695_HPNA_OFFSET)
+#define KS8695_HPNA_PA          (KS8695_IO_PA + KS8695_HPNA_OFFSET)
+
+
+/*
+ * HPNA registers
+ */
+
+#endif
diff --git a/arch/arm/mach-ks8695/include/mach/regs-irq.h b/arch/arm/mach-ks8695/include/mach/regs-irq.h
new file mode 100644
index 000000000000..352b7e8704d5
--- /dev/null
+++ b/arch/arm/mach-ks8695/include/mach/regs-irq.h
@@ -0,0 +1,41 @@
+/*
+ * arch/arm/mach-ks8695/include/mach/regs-irq.h
+ *
+ * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
+ * Copyright (C) 2006 Simtec Electronics
+ *
+ * KS8695 - IRQ registers and bit definitions
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef KS8695_IRQ_H
+#define KS8695_IRQ_H
+
+#define KS8695_IRQ_OFFSET       (0xF0000 + 0xE200)
+#define KS8695_IRQ_VA           (KS8695_IO_VA + KS8695_IRQ_OFFSET)
+#define KS8695_IRQ_PA           (KS8695_IO_PA + KS8695_IRQ_OFFSET)
+
+
+/*
+ * Interrupt Controller registers
+ */
+#define KS8695_INTMC            (0x00)          /* Mode Control Register */
+#define KS8695_INTEN            (0x04)          /* Interrupt Enable Register */
+#define KS8695_INTST            (0x08)          /* Interrupt Status Register */
+#define KS8695_INTPW            (0x0c)          /* Interrupt Priority (WAN MAC) */
+#define KS8695_INTPH            (0x10)          /* Interrupt Priority (HPNA) [KS8695 only] */
+#define KS8695_INTPL            (0x14)          /* Interrupt Priority (LAN MAC) */
+#define KS8695_INTPT            (0x18)          /* Interrupt Priority (Timer) */
+#define KS8695_INTPU            (0x1c)          /* Interrupt Priority (UART) */
+#define KS8695_INTPE            (0x20)          /* Interrupt Priority (External Interrupt) */
+#define KS8695_INTPC            (0x24)          /* Interrupt Priority (Communications Channel) */
+#define KS8695_INTPBE           (0x28)          /* Interrupt Priority (Bus Error Response) */
+#define KS8695_INTMS            (0x2c)          /* Interrupt Mask Status Register */
+#define KS8695_INTHPF           (0x30)          /* Interrupt Pending Highest Priority (FIQ) */
+#define KS8695_INTHPI           (0x34)          /* Interrupt Pending Highest Priority (IRQ) */
+
+
+#endif
diff --git a/arch/arm/mach-ks8695/include/mach/regs-lan.h b/arch/arm/mach-ks8695/include/mach/regs-lan.h
new file mode 100644
index 000000000000..9ef409901e76
--- /dev/null
+++ b/arch/arm/mach-ks8695/include/mach/regs-lan.h
@@ -0,0 +1,65 @@
+/*
+ * arch/arm/mach-ks8695/include/mach/regs-lan.h
+ *
+ * Copyright (C) 2006 Andrew Victor
+ *
+ * KS8695 - LAN Registers and bit definitions.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef KS8695_LAN_H
+#define KS8695_LAN_H
+
+#define KS8695_LAN_OFFSET       (0xF0000 + 0x8000)
+#define KS8695_LAN_VA           (KS8695_IO_VA + KS8695_LAN_OFFSET)
+#define KS8695_LAN_PA           (KS8695_IO_PA + KS8695_LAN_OFFSET)
+
+
+/*
+ * LAN registers
+ */
+#define KS8695_LMDTXC           (0x00)          /* DMA Transmit Control */
+#define KS8695_LMDRXC           (0x04)          /* DMA Receive Control */
+#define KS8695_LMDTSC           (0x08)          /* DMA Transmit Start Command */
+#define KS8695_LMDRSC           (0x0c)          /* DMA Receive Start Command */
+#define KS8695_LTDLB            (0x10)          /* Transmit Descriptor List Base Address */
+#define KS8695_LRDLB            (0x14)          /* Receive Descriptor List Base Address */
+#define KS8695_LMAL             (0x18)          /* MAC Station Address Low */
+#define KS8695_LMAH             (0x1c)          /* MAC Station Address High */
+#define KS8695_LMAAL_(n)        (0x80 + ((n)*8))        /* MAC Additional Station Address (0..15) Low */
+#define KS8695_LMAAH_(n)        (0x84 + ((n)*8))        /* MAC Additional Station Address (0..15) High */
+
+
+/* DMA Transmit Control Register */
+#define LMDTXC_LMTRST           (1    << 31)    /* Soft Reset */
+#define LMDTXC_LMTBS            (0x3f << 24)    /* Transmit Burst Size */
+#define LMDTXC_LMTUCG           (1    << 18)    /* Transmit UDP Checksum Generate */
+#define LMDTXC_LMTTCG           (1    << 17)    /* Transmit TCP Checksum Generate */
+#define LMDTXC_LMTICG           (1    << 16)    /* Transmit IP Checksum Generate */
+#define LMDTXC_LMTFCE           (1    <<  9)    /* Transmit Flow Control Enable */
+#define LMDTXC_LMTLB            (1    <<  8)    /* Loopback mode */
+#define LMDTXC_LMTEP            (1    <<  2)    /* Transmit Enable Padding */
+#define LMDTXC_LMTAC            (1    <<  1)    /* Transmit Add CRC */
+#define LMDTXC_LMTE             (1    <<  0)    /* TX Enable */
+
+/* DMA Receive Control Register */
+#define LMDRXC_LMRBS            (0x3f << 24)    /* Receive Burst Size */
+#define LMDRXC_LMRUCC           (1    << 18)    /* Receive UDP Checksum check */
+#define LMDRXC_LMRTCG           (1    << 17)    /* Receive TCP Checksum check */
+#define LMDRXC_LMRICG           (1    << 16)    /* Receive IP Checksum check */
+#define LMDRXC_LMRFCE           (1    <<  9)    /* Receive Flow Control Enable */
+#define LMDRXC_LMRB             (1    <<  6)    /* Receive Broadcast */
+#define LMDRXC_LMRM             (1    <<  5)    /* Receive Multicast */
+#define LMDRXC_LMRU             (1    <<  4)    /* Receive Unicast */
+#define LMDRXC_LMRERR           (1    <<  3)    /* Receive Error Frame */
+#define LMDRXC_LMRA             (1    <<  2)    /* Receive All */
+#define LMDRXC_LMRE             (1    <<  1)    /* RX Enable */
+
+/* Additional Station Address High */
+#define LMAAH_E                 (1    << 31)    /* Address Enabled */
+
+
+#endif
diff --git a/arch/arm/mach-ks8695/include/mach/regs-mem.h b/arch/arm/mach-ks8695/include/mach/regs-mem.h
new file mode 100644
index 000000000000..55806bc68ce3
--- /dev/null
+++ b/arch/arm/mach-ks8695/include/mach/regs-mem.h
@@ -0,0 +1,89 @@
+/*
+ * arch/arm/mach-ks8695/include/mach/regs-mem.h
+ *
+ * Copyright (C) 2006 Andrew Victor
+ *
+ * KS8695 - Memory Controller registers and bit definitions
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef KS8695_MEM_H
+#define KS8695_MEM_H
+
+#define KS8695_MEM_OFFSET       (0xF0000 + 0x4000)
+#define KS8695_MEM_VA           (KS8695_IO_VA + KS8695_MEM_OFFSET)
+#define KS8695_MEM_PA           (KS8695_IO_PA + KS8695_MEM_OFFSET)
+
+
+/*
+ * Memory Controller Registers
+ */
+#define KS8695_EXTACON0         (0x00)          /* External I/O 0 Access Control */
+#define KS8695_EXTACON1         (0x04)          /* External I/O 1 Access Control */
+#define KS8695_EXTACON2         (0x08)          /* External I/O 2 Access Control */
+#define KS8695_ROMCON0          (0x10)          /* ROM/SRAM/Flash 1 Control Register */
+#define KS8695_ROMCON1          (0x14)          /* ROM/SRAM/Flash 2 Control Register */
+#define KS8695_ERGCON           (0x20)          /* External I/O and ROM/SRAM/Flash General Register */
+#define KS8695_SDCON0           (0x30)          /* SDRAM Control Register 0 */
+#define KS8695_SDCON1           (0x34)          /* SDRAM Control Register 1 */
+#define KS8695_SDGCON           (0x38)          /* SDRAM General Control */
+#define KS8695_SDBCON           (0x3c)          /* SDRAM Buffer Control */
+#define KS8695_REFTIM           (0x40)          /* SDRAM Refresh Timer */
+
+
+/* External I/O Access Control Registers */
+#define EXTACON_EBNPTR          (0x3ff << 22)           /* Last Address Pointer */
+#define EXTACON_EBBPTR          (0x3ff << 12)           /* Base Pointer */
+#define EXTACON_EBTACT          (7     <<  9)           /* Write Enable/Output Enable Active Time */
+#define EXTACON_EBTCOH          (7     <<  6)           /* Chip Select Hold Time */
+#define EXTACON_EBTACS          (7     <<  3)           /* Address Setup Time before ECSN */
+#define EXTACON_EBTCOS          (7     <<  0)           /* Chip Select Time before OEN */
+
+/* ROM/SRAM/Flash Control Register */
+#define ROMCON_RBNPTR           (0x3ff << 22)           /* Next Pointer */
+#define ROMCON_RBBPTR           (0x3ff << 12)           /* Base Pointer */
+#define ROMCON_RBTACC           (7     <<  4)           /* Access Cycle Time */
+#define ROMCON_RBTPA            (3     <<  2)           /* Page Address Access Time */
+#define ROMCON_PMC              (3     <<  0)           /* Page Mode Configuration */
+#define         PMC_NORMAL              (0 << 0)
+#define         PMC_4WORD               (1 << 0)
+#define         PMC_8WORD               (2 << 0)
+#define         PMC_16WORD              (3 << 0)
+
+/* External I/O and ROM/SRAM/Flash General Register */
+#define ERGCON_TMULT            (3 << 28)               /* Time Multiplier */
+#define ERGCON_DSX2             (3 << 20)               /* Data Width (External I/O Bank 2) */
+#define ERGCON_DSX1             (3 << 18)               /* Data Width (External I/O Bank 1) */
+#define ERGCON_DSX0             (3 << 16)               /* Data Width (External I/O Bank 0) */
+#define ERGCON_DSR1             (3 <<  2)               /* Data Width (ROM/SRAM/Flash Bank 1) */
+#define ERGCON_DSR0             (3 <<  0)               /* Data Width (ROM/SRAM/Flash Bank 0) */
+
+/* SDRAM Control Register */
+#define SDCON_DBNPTR            (0x3ff << 22)           /* Last Address Pointer */
+#define SDCON_DBBPTR            (0x3ff << 12)           /* Base Pointer */
+#define SDCON_DBCAB             (3     <<  8)           /* Column Address Bits */
+#define SDCON_DBBNUM            (1     <<  3)           /* Number of Banks */
+#define SDCON_DBDBW             (3     <<  1)           /* Data Bus Width */
+
+/* SDRAM General Control Register */
+#define SDGCON_SDTRC            (3 << 2)                /* RAS to CAS latency */
+#define SDGCON_SDCAS            (3 << 0)                /* CAS latency */
+
+/* SDRAM Buffer Control Register */
+#define SDBCON_SDESTA           (1 << 31)               /* SDRAM Engine Status */
+#define SDBCON_RBUFBDIS         (1 << 24)               /* Read Buffer Burst Enable */
+#define SDBCON_WFIFOEN          (1 << 23)               /* Write FIFO Enable */
+#define SDBCON_RBUFEN           (1 << 22)               /* Read Buffer Enable */
+#define SDBCON_FLUSHWFIFO       (1 << 21)               /* Flush Write FIFO */
+#define SDBCON_RBUFINV          (1 << 20)               /* Read Buffer Invalidate */
+#define SDBCON_SDINI            (3 << 16)               /* SDRAM Initialization Control */
+#define SDBCON_SDMODE           (0x3fff << 0)           /* SDRAM Mode Register Value Program */
+
+/* SDRAM Refresh Timer Register */
+#define REFTIM_REFTIM           (0xffff << 0)           /* Refresh Timer Value */
+
+
+#endif
diff --git a/arch/arm/mach-ks8695/include/mach/regs-misc.h b/arch/arm/mach-ks8695/include/mach/regs-misc.h
new file mode 100644
index 000000000000..2740c52494a0
--- /dev/null
+++ b/arch/arm/mach-ks8695/include/mach/regs-misc.h
@@ -0,0 +1,97 @@
+/*
+ * arch/arm/mach-ks8695/include/mach/regs-misc.h
+ *
+ * Copyright (C) 2006 Andrew Victor
+ *
+ * KS8695 - Miscellaneous Registers
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef KS8695_MISC_H
+#define KS8695_MISC_H
+
+#define KS8695_MISC_OFFSET      (0xF0000 + 0xEA00)
+#define KS8695_MISC_VA          (KS8695_IO_VA + KS8695_MISC_OFFSET)
+#define KS8695_MISC_PA          (KS8695_IO_PA + KS8695_MISC_OFFSET)
+
+
+/*
+ * Miscellaneous registers
+ */
+#define KS8695_DID              (0x00)          /* Device ID */
+#define KS8695_RID              (0x04)          /* Revision ID */
+#define KS8695_HMC              (0x08)          /* HPNA Miscellaneous Control [KS8695 only] */
+#define KS8695_WMC              (0x0c)          /* WAN Miscellaneous Control */
+#define KS8695_WPPM             (0x10)          /* WAN PHY Power Management */
+#define KS8695_PPS              (0x1c)          /* PHY PowerSave */
+
+/* Device ID Register */
+#define DID_ID                  (0xffff << 0)   /* Device ID */
+
+/* Revision ID Register */
+#define RID_SUBID               (0xf << 4)      /* Sub-Device ID */
+#define RID_REVISION            (0xf << 0)      /* Revision ID */
+
+/* HPNA Miscellaneous Control Register */
+#define HMC_HSS                 (1 << 1)        /* Speed */
+#define HMC_HDS                 (1 << 0)        /* Duplex */
+
+/* WAN Miscellaneous Control Register */
+#define WMC_WANC                (1 << 30)       /* Auto-negotiation complete */
+#define WMC_WANR                (1 << 29)       /* Auto-negotiation restart */
+#define WMC_WANAP               (1 << 28)       /* Advertise Pause */
+#define WMC_WANA100F            (1 << 27)       /* Advertise 100 FDX */
+#define WMC_WANA100H            (1 << 26)       /* Advertise 100 HDX */
+#define WMC_WANA10F             (1 << 25)       /* Advertise 10 FDX */
+#define WMC_WANA10H             (1 << 24)       /* Advertise 10 HDX */
+#define WMC_WLS                 (1 << 23)       /* Link status */
+#define WMC_WDS                 (1 << 22)       /* Duplex status */
+#define WMC_WSS                 (1 << 21)       /* Speed status */
+#define WMC_WLPP                (1 << 20)       /* Link Partner Pause */
+#define WMC_WLP100F             (1 << 19)       /* Link Partner 100 FDX */
+#define WMC_WLP100H             (1 << 18)       /* Link Partner 100 HDX */
+#define WMC_WLP10F              (1 << 17)       /* Link Partner 10 FDX */
+#define WMC_WLP10H              (1 << 16)       /* Link Partner 10 HDX */
+#define WMC_WAND                (1 << 15)       /* Auto-negotiation disable */
+#define WMC_WANF100             (1 << 14)       /* Force 100 */
+#define WMC_WANFF               (1 << 13)       /* Force FDX */
+#define WMC_WLED1S              (7 <<  4)       /* LED1 Select */
+#define         WLED1S_SPEED            (0 << 4)
+#define         WLED1S_LINK             (1 << 4)
+#define         WLED1S_DUPLEX           (2 << 4)
+#define         WLED1S_COLLISION        (3 << 4)
+#define         WLED1S_ACTIVITY         (4 << 4)
+#define         WLED1S_FDX_COLLISION    (5 << 4)
+#define         WLED1S_LINK_ACTIVITY    (6 << 4)
+#define WMC_WLED0S              (7 << 0)        /* LED0 Select */
+#define         WLED0S_SPEED            (0 << 0)
+#define         WLED0S_LINK             (1 << 0)
+#define         WLED0S_DUPLEX           (2 << 0)
+#define         WLED0S_COLLISION        (3 << 0)
+#define         WLED0S_ACTIVITY         (4 << 0)
+#define         WLED0S_FDX_COLLISION    (5 << 0)
+#define         WLED0S_LINK_ACTIVITY    (6 << 0)
+
+/* WAN PHY Power Management Register */
+#define WPPM_WLPBK              (1 << 14)       /* Local Loopback */
+#define WPPM_WRLPKB             (1 << 13)       /* Remove Loopback */
+#define WPPM_WPI                (1 << 12)       /* PHY isolate */
+#define WPPM_WFL                (1 << 10)       /* Force link */
+#define WPPM_MDIXS              (1 << 9)        /* MDIX Status */
+#define WPPM_FEF                (1 << 8)        /* Far End Fault */
+#define WPPM_AMDIXP             (1 << 7)        /* Auto MDIX Parameter */
+#define WPPM_TXDIS              (1 << 6)        /* Disable transmitter */
+#define WPPM_DFEF               (1 << 5)        /* Disable Far End Fault */
+#define WPPM_PD                 (1 << 4)        /* Power Down */
+#define WPPM_DMDX               (1 << 3)        /* Disable Auto MDI/MDIX */
+#define WPPM_FMDX               (1 << 2)        /* Force MDIX */
+#define WPPM_LPBK               (1 << 1)        /* MAX Loopback */
+
+/* PHY Power Save Register */
+#define PPS_PPSM                (1 << 0)        /* PHY Power Save Mode */
+
+
+#endif
diff --git a/arch/arm/mach-ks8695/include/mach/regs-pci.h b/arch/arm/mach-ks8695/include/mach/regs-pci.h
new file mode 100644
index 000000000000..75a9db6edbd9
--- /dev/null
+++ b/arch/arm/mach-ks8695/include/mach/regs-pci.h
@@ -0,0 +1,53 @@
+/*
+ * arch/arm/mach-ks8695/include/mach/regs-pci.h
+ *
+ * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
+ * Copyright (C) 2006 Simtec Electronics
+ *
+ * KS8695 - PCI bridge registers and bit definitions.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#define KS8695_PCI_OFFSET       (0xF0000 + 0x2000)
+#define KS8695_PCI_VA           (KS8695_IO_VA + KS8695_PCI_OFFSET)
+#define KS8695_PCI_PA           (KS8695_IO_PA + KS8695_PCI_OFFSET)
+
+
+#define KS8695_CRCFID           (0x000)         /* Configuration: Identification */
+#define KS8695_CRCFCS           (0x004)         /* Configuration: Command and Status */
+#define KS8695_CRCFRV           (0x008)         /* Configuration: Revision */
+#define KS8695_CRCFLT           (0x00C)         /* Configuration: Latency Timer */
+#define KS8695_CRCBMA           (0x010)         /* Configuration: Base Memory Address */
+#define KS8695_CRCSID           (0x02C)         /* Configuration: Subsystem ID */
+#define KS8695_CRCFIT           (0x03C)         /* Configuration: Interrupt */
+#define KS8695_PBCA             (0x100)         /* Bridge Configuration Address */
+#define KS8695_PBCD             (0x104)         /* Bridge Configuration Data */
+#define KS8695_PBM              (0x200)         /* Bridge Mode */
+#define KS8695_PBCS             (0x204)         /* Bridge Control and Status */
+#define KS8695_PMBA             (0x208)         /* Bridge Memory Base Address */
+#define KS8695_PMBAC            (0x20C)         /* Bridge Memory Base Address Control */
+#define KS8695_PMBAM            (0x210)         /* Bridge Memory Base Address Mask */
+#define KS8695_PMBAT            (0x214)         /* Bridge Memory Base Address Translation */
+#define KS8695_PIOBA            (0x218)         /* Bridge I/O Base Address */
+#define KS8695_PIOBAC           (0x21C)         /* Bridge I/O Base Address Control */
+#define KS8695_PIOBAM           (0x220)         /* Bridge I/O Base Address Mask */
+#define KS8695_PIOBAT           (0x224)         /* Bridge I/O Base Address Translation */
+
+
+/* Configuration: Identification */
+
+/* Configuration: Command and Status */
+
+/* Configuration: Revision */
+
+
+
+#define CFRV_GUEST              (1 << 23)
+
+#define PBCA_TYPE1              (1)
+#define PBCA_ENABLE             (1 << 31)
+
+
diff --git a/arch/arm/mach-ks8695/include/mach/regs-switch.h b/arch/arm/mach-ks8695/include/mach/regs-switch.h
new file mode 100644
index 000000000000..56d12e8de895
--- /dev/null
+++ b/arch/arm/mach-ks8695/include/mach/regs-switch.h
@@ -0,0 +1,66 @@
+/*
+ * arch/arm/mach-ks8695/include/mach/regs-switch.h
+ *
+ * Copyright (C) 2006 Andrew Victor
+ *
+ * KS8695 - Switch Registers and bit definitions.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef KS8695_SWITCH_H
+#define KS8695_SWITCH_H
+
+#define KS8695_SWITCH_OFFSET    (0xF0000 + 0xe800)
+#define KS8695_SWITCH_VA        (KS8695_IO_VA + KS8695_SWITCH_OFFSET)
+#define KS8695_SWITCH_PA        (KS8695_IO_PA + KS8695_SWITCH_OFFSET)
+
+
+/*
+ * Switch registers
+ */
+#define KS8695_SEC0             (0x00)          /* Switch Engine Control 0 */
+#define KS8695_SEC1             (0x04)          /* Switch Engine Control 1 */
+#define KS8695_SEC2             (0x08)          /* Switch Engine Control 2 */
+
+#define KS8695_P(x)_C(z)        (0xc0 + (((x)-1)*3 + ((z)-1))*4)        /* Port Configuration Registers */
+
+#define KS8695_SEP12AN          (0x48)          /* Port 1 & 2 Auto-Negotiation */
+#define KS8695_SEP34AN          (0x4c)          /* Port 3 & 4 Auto-Negotiation */
+#define KS8695_SEIAC            (0x50)          /* Indirect Access Control */
+#define KS8695_SEIADH2          (0x54)          /* Indirect Access Data High 2 */
+#define KS8695_SEIADH1          (0x58)          /* Indirect Access Data High 1 */
+#define KS8695_SEIADL           (0x5c)          /* Indirect Access Data Low */
+#define KS8695_SEAFC            (0x60)          /* Advance Feature Control */
+#define KS8695_SEDSCPH          (0x64)          /* TOS Priority High */
+#define KS8695_SEDSCPL          (0x68)          /* TOS Priority Low */
+#define KS8695_SEMAH            (0x6c)          /* Switch Engine MAC Address High */
+#define KS8695_SEMAL            (0x70)          /* Switch Engine MAC Address Low */
+#define KS8695_LPPM12           (0x74)          /* Port 1 & 2 PHY Power Management */
+#define KS8695_LPPM34           (0x78)          /* Port 3 & 4 PHY Power Management */
+
+
+/* Switch Engine Control 0 */
+#define SEC0_LLED1S             (7 << 25)       /* LED1 Select */
+#define         LLED1S_SPEED            (0 << 25)
+#define         LLED1S_LINK             (1 << 25)
+#define         LLED1S_DUPLEX           (2 << 25)
+#define         LLED1S_COLLISION        (3 << 25)
+#define         LLED1S_ACTIVITY         (4 << 25)
+#define         LLED1S_FDX_COLLISION    (5 << 25)
+#define         LLED1S_LINK_ACTIVITY    (6 << 25)
+#define SEC0_LLED0S             (7 << 22)       /* LED0 Select */
+#define         LLED0S_SPEED            (0 << 22)
+#define         LLED0S_LINK             (1 << 22)
+#define         LLED0S_DUPLEX           (2 << 22)
+#define         LLED0S_COLLISION        (3 << 22)
+#define         LLED0S_ACTIVITY         (4 << 22)
+#define         LLED0S_FDX_COLLISION    (5 << 22)
+#define         LLED0S_LINK_ACTIVITY    (6 << 22)
+#define SEC0_ENABLE             (1 << 0)        /* Enable Switch */
+
+
+
+#endif
diff --git a/arch/arm/mach-ks8695/include/mach/regs-sys.h b/arch/arm/mach-ks8695/include/mach/regs-sys.h
new file mode 100644
index 000000000000..57c20be0c129
--- /dev/null
+++ b/arch/arm/mach-ks8695/include/mach/regs-sys.h
@@ -0,0 +1,34 @@
+/*
+ * arch/arm/mach-ks8695/include/mach/regs-sys.h
+ *
+ * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
+ * Copyright (C) 2006 Simtec Electronics
+ *
+ * KS8695 - System control registers and bit definitions
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef KS8695_SYS_H
+#define KS8695_SYS_H
+
+#define KS8695_SYS_OFFSET       (0xF0000 + 0x0000)
+#define KS8695_SYS_VA           (KS8695_IO_VA + KS8695_SYS_OFFSET)
+#define KS8695_SYS_PA           (KS8695_IO_PA + KS8695_SYS_OFFSET)
+
+
+#define KS8695_SYSCFG           (0x00)          /* System Configuration Register */
+#define KS8695_CLKCON           (0x04)          /* System Clock and Bus Control Register */
+
+
+/* System Configuration Register */
+#define SYSCFG_SPRBP            (0x3ff << 16)   /* Register Bank Base Pointer */
+
+/* System Clock and Bus Control Register */
+#define CLKCON_SFMODE           (1 << 8)        /* System Fast Mode for Simulation */
+#define CLKCON_SCDC             (7 << 0)        /* System Clock Divider Select */
+
+
+#endif
diff --git a/arch/arm/mach-ks8695/include/mach/regs-timer.h b/arch/arm/mach-ks8695/include/mach/regs-timer.h
new file mode 100644
index 000000000000..e620cda99d2d
--- /dev/null
+++ b/arch/arm/mach-ks8695/include/mach/regs-timer.h
@@ -0,0 +1,40 @@
+/*
+ * arch/arm/mach-ks8695/include/mach/regs-timer.h
+ *
+ * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
+ * Copyright (C) 2006 Simtec Electronics
+ *
+ * KS8695 - Timer registers and bit definitions.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef KS8695_TIMER_H
+#define KS8695_TIMER_H
+
+#define KS8695_TMR_OFFSET       (0xF0000 + 0xE400)
+#define KS8695_TMR_VA           (KS8695_IO_VA + KS8695_TMR_OFFSET)
+#define KS8695_TMR_PA           (KS8695_IO_PA + KS8695_TMR_OFFSET)
+
+
+/*
+ * Timer registers
+ */
+#define KS8695_TMCON            (0x00)          /* Timer Control Register */
+#define KS8695_T1TC             (0x04)          /* Timer 1 Timeout Count Register */
+#define KS8695_T0TC             (0x08)          /* Timer 0 Timeout Count Register */
+#define KS8695_T1PD             (0x0C)          /* Timer 1 Pulse Count Register */
+#define KS8695_T0PD             (0x10)          /* Timer 0 Pulse Count Register */
+
+
+/* Timer Control Register */
+#define TMCON_T1EN              (1 << 1)        /* Timer 1 Enable */
+#define TMCON_T0EN              (1 << 0)        /* Timer 0 Enable */
+
+/* Timer0 Timeout Counter Register */
+#define T0TC_WATCHDOG           (0xff)          /* Enable watchdog mode */
+
+
+#endif
diff --git a/arch/arm/mach-ks8695/include/mach/regs-uart.h b/arch/arm/mach-ks8695/include/mach/regs-uart.h
new file mode 100644
index 000000000000..8581fbc6245f
--- /dev/null
+++ b/arch/arm/mach-ks8695/include/mach/regs-uart.h
@@ -0,0 +1,92 @@
+/*
+ * arch/arm/mach-ks8695/include/mach/regs-uart.h
+ *
+ * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
+ * Copyright (C) 2006 Simtec Electronics
+ *
+ * KS8695 - UART register and bit definitions.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef KS8695_UART_H
+#define KS8695_UART_H
+
+#define KS8695_UART_OFFSET      (0xF0000 + 0xE000)
+#define KS8695_UART_VA          (KS8695_IO_VA + KS8695_UART_OFFSET)
+#define KS8695_UART_PA          (KS8695_IO_PA + KS8695_UART_OFFSET)
+
+
+/*
+ * UART registers
+ */
+#define KS8695_URRB     (0x00)          /* Receive Buffer Register */
+#define KS8695_URTH     (0x04)          /* Transmit Holding Register */
+#define KS8695_URFC     (0x08)          /* FIFO Control Register */
+#define KS8695_URLC     (0x0C)          /* Line Control Register */
+#define KS8695_URMC     (0x10)          /* Modem Control Register */
+#define KS8695_URLS     (0x14)          /* Line Status Register */
+#define KS8695_URMS     (0x18)          /* Modem Status Register */
+#define KS8695_URBD     (0x1C)          /* Baud Rate Divisor Register */
+#define KS8695_USR      (0x20)          /* Status Register */
+
+
+/* FIFO Control Register */
+#define URFC_URFRT      (3 << 6)        /* Receive FIFO Trigger Level */
+#define         URFC_URFRT_1    (0 << 6)
+#define         URFC_URFRT_4    (1 << 6)
+#define         URFC_URFRT_8    (2 << 6)
+#define         URFC_URFRT_14   (3 << 6)
+#define URFC_URTFR      (1 << 2)        /* Transmit FIFO Reset */
+#define URFC_URRFR      (1 << 1)        /* Receive FIFO Reset */
+#define URFC_URFE       (1 << 0)        /* FIFO Enable */
+
+/* Line Control Register */
+#define URLC_URSBC      (1 << 6)        /* Set Break Condition */
+#define URLC_PARITY     (7 << 3)        /* Parity */
+#define         URPE_NONE       (0 << 3)
+#define         URPE_ODD        (1 << 3)
+#define         URPE_EVEN       (3 << 3)
+#define         URPE_MARK       (5 << 3)
+#define         URPE_SPACE      (7 << 3)
+#define URLC_URSB       (1 << 2)        /* Stop Bits */
+#define URLC_URCL       (3 << 0)        /* Character Length */
+#define         URCL_5          (0 << 0)
+#define         URCL_6          (1 << 0)
+#define         URCL_7          (2 << 0)
+#define         URCL_8          (3 << 0)
+
+/* Modem Control Register */
+#define URMC_URLB       (1 << 4)        /* Loop-back mode */
+#define URMC_UROUT2     (1 << 3)        /* OUT2 signal */
+#define URMC_UROUT1     (1 << 2)        /* OUT1 signal */
+#define URMC_URRTS      (1 << 1)        /* Request to Send */
+#define URMC_URDTR      (1 << 0)        /* Data Terminal Ready */
+
+/* Line Status Register */
+#define URLS_URRFE      (1 << 7)        /* Receive FIFO Error */
+#define URLS_URTE       (1 << 6)        /* Transmit Empty */
+#define URLS_URTHRE     (1 << 5)        /* Transmit Holding Register Empty */
+#define URLS_URBI       (1 << 4)        /* Break Interrupt */
+#define URLS_URFE       (1 << 3)        /* Framing Error */
+#define URLS_URPE       (1 << 2)        /* Parity Error */
+#define URLS_URROE      (1 << 1)        /* Receive Overrun Error */
+#define URLS_URDR       (1 << 0)        /* Receive Data Ready */
+
+/* Modem Status Register */
+#define URMS_URDCD      (1 << 7)        /* Data Carrier Detect */
+#define URMS_URRI       (1 << 6)        /* Ring Indicator */
+#define URMS_URDSR      (1 << 5)        /* Data Set Ready */
+#define URMS_URCTS      (1 << 4)        /* Clear to Send */
+#define URMS_URDDCD     (1 << 3)        /* Delta Data Carrier Detect */
+#define URMS_URTERI     (1 << 2)        /* Trailing Edge Ring Indicator */
+#define URMS_URDDST     (1 << 1)        /* Delta Data Set Ready */
+#define URMS_URDCTS     (1 << 0)        /* Delta Clear to Send */
+
+/* Status Register */
+#define USR_UTI         (1 << 0)        /* Timeout Indication */
+
+
+#endif
diff --git a/arch/arm/mach-ks8695/include/mach/regs-wan.h b/arch/arm/mach-ks8695/include/mach/regs-wan.h
new file mode 100644
index 000000000000..eb494ec6e956
--- /dev/null
+++ b/arch/arm/mach-ks8695/include/mach/regs-wan.h
@@ -0,0 +1,65 @@
+/*
+ * arch/arm/mach-ks8695/include/mach/regs-wan.h
+ *
+ * Copyright (C) 2006 Andrew Victor
+ *
+ * KS8695 - WAN Registers and bit definitions.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef KS8695_WAN_H
+#define KS8695_WAN_H
+
+#define KS8695_WAN_OFFSET       (0xF0000 + 0x6000)
+#define KS8695_WAN_VA           (KS8695_IO_VA + KS8695_WAN_OFFSET)
+#define KS8695_WAN_PA           (KS8695_IO_PA + KS8695_WAN_OFFSET)
+
+
+/*
+ * WAN registers
+ */
+#define KS8695_WMDTXC           (0x00)          /* DMA Transmit Control */
+#define KS8695_WMDRXC           (0x04)          /* DMA Receive Control */
+#define KS8695_WMDTSC           (0x08)          /* DMA Transmit Start Command */
+#define KS8695_WMDRSC           (0x0c)          /* DMA Receive Start Command */
+#define KS8695_WTDLB            (0x10)          /* Transmit Descriptor List Base Address */
+#define KS8695_WRDLB            (0x14)          /* Receive Descriptor List Base Address */
+#define KS8695_WMAL             (0x18)          /* MAC Station Address Low */
+#define KS8695_WMAH             (0x1c)          /* MAC Station Address High */
+#define KS8695_WMAAL_(n)        (0x80 + ((n)*8))        /* MAC Additional Station Address (0..15) Low */
+#define KS8695_WMAAH_(n)        (0x84 + ((n)*8))        /* MAC Additional Station Address (0..15) High */
+
+
+/* DMA Transmit Control Register */
+#define WMDTXC_WMTRST           (1    << 31)    /* Soft Reset */
+#define WMDTXC_WMTBS            (0x3f << 24)    /* Transmit Burst Size */
+#define WMDTXC_WMTUCG           (1    << 18)    /* Transmit UDP Checksum Generate */
+#define WMDTXC_WMTTCG           (1    << 17)    /* Transmit TCP Checksum Generate */
+#define WMDTXC_WMTICG           (1    << 16)    /* Transmit IP Checksum Generate */
+#define WMDTXC_WMTFCE           (1    <<  9)    /* Transmit Flow Control Enable */
+#define WMDTXC_WMTLB            (1    <<  8)    /* Loopback mode */
+#define WMDTXC_WMTEP            (1    <<  2)    /* Transmit Enable Padding */
+#define WMDTXC_WMTAC            (1    <<  1)    /* Transmit Add CRC */
+#define WMDTXC_WMTE             (1    <<  0)    /* TX Enable */
+
+/* DMA Receive Control Register */
+#define WMDRXC_WMRBS            (0x3f << 24)    /* Receive Burst Size */
+#define WMDRXC_WMRUCC           (1    << 18)    /* Receive UDP Checksum check */
+#define WMDRXC_WMRTCG           (1    << 17)    /* Receive TCP Checksum check */
+#define WMDRXC_WMRICG           (1    << 16)    /* Receive IP Checksum check */
+#define WMDRXC_WMRFCE           (1    <<  9)    /* Receive Flow Control Enable */
+#define WMDRXC_WMRB             (1    <<  6)    /* Receive Broadcast */
+#define WMDRXC_WMRM             (1    <<  5)    /* Receive Multicast */
+#define WMDRXC_WMRU             (1    <<  4)    /* Receive Unicast */
+#define WMDRXC_WMRERR           (1    <<  3)    /* Receive Error Frame */
+#define WMDRXC_WMRA             (1    <<  2)    /* Receive All */
+#define WMDRXC_WMRE             (1    <<  0)    /* RX Enable */
+
+/* Additional Station Address High */
+#define WMAAH_E                 (1    << 31)    /* Address Enabled */
+
+
+#endif
diff --git a/arch/arm/mach-ks8695/include/mach/system.h b/arch/arm/mach-ks8695/include/mach/system.h
new file mode 100644
index 000000000000..2a6f91869056
--- /dev/null
+++ b/arch/arm/mach-ks8695/include/mach/system.h
@@ -0,0 +1,48 @@
+/*
+ * arch/arm/mach-s3c2410/include/mach/system.h
+ *
+ * Copyright (C) 2006 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * KS8695 - System function defines and includes
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <asm/io.h>
+#include <mach/regs-timer.h>
+
+static void arch_idle(void)
+{
+        /*
+         * This should do all the clock switching
+         * and wait for interrupt tricks,
+         */
+        cpu_do_idle();
+
+}
+
+static void arch_reset(char mode)
+{
+        unsigned int reg;
+
+        if (mode == 's')
+                cpu_reset(0);
+
+        /* disable timer0 */
+        reg = __raw_readl(KS8695_TMR_VA + KS8695_TMCON);
+        __raw_writel(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
+
+        /* enable watchdog mode */
+        __raw_writel((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC);
+
+        /* re-enable timer0 */
+        __raw_writel(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
+}
+
+#endif
diff --git a/arch/arm/mach-ks8695/include/mach/timex.h b/arch/arm/mach-ks8695/include/mach/timex.h
new file mode 100644
index 000000000000..4682e350369b
--- /dev/null
+++ b/arch/arm/mach-ks8695/include/mach/timex.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/mach-ks8695/include/mach/timex.h
+ *
+ * Copyright (C) 2006 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * KS8695 - Time Parameters
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+
+/* timers are derived from MCLK, which is 25MHz */
+#define CLOCK_TICK_RATE 25000000
+
+#endif
diff --git a/arch/arm/mach-ks8695/include/mach/uncompress.h b/arch/arm/mach-ks8695/include/mach/uncompress.h
new file mode 100644
index 000000000000..0eee37a69075
--- /dev/null
+++ b/arch/arm/mach-ks8695/include/mach/uncompress.h
@@ -0,0 +1,37 @@
+/*
+ * arch/arm/mach-ks8695/include/mach/uncompress.h
+ *
+ * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
+ * Copyright (C) 2006 Simtec Electronics
+ *
+ * KS8695 - Kernel uncompressor
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+
+#include <asm/io.h>
+#include <mach/regs-uart.h>
+
+static void putc(char c)
+{
+        while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTHRE))
+                barrier();
+
+        __raw_writel(c, KS8695_UART_PA + KS8695_URTH);
+}
+
+static inline void flush(void)
+{
+        while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTE))
+                barrier();
+}
+
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
+
+#endif
diff --git a/arch/arm/mach-ks8695/include/mach/vmalloc.h b/arch/arm/mach-ks8695/include/mach/vmalloc.h
new file mode 100644
index 000000000000..744ac66be3a2
--- /dev/null
+++ b/arch/arm/mach-ks8695/include/mach/vmalloc.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-ks8695/include/mach/vmalloc.h
+ *
+ * Copyright (C) 2006 Ben Dooks
+ * Copyright (C) 2006 Simtec Electronics <linux@simtec.co.uk>
+ *
+ * KS8695 vmalloc definition
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_VMALLOC_H
+#define __ASM_ARCH_VMALLOC_H
+
+#define VMALLOC_END       (KS8695_IO_VA & PGDIR_MASK)
+
+#endif
diff --git a/arch/arm/mach-ks8695/irq.c b/arch/arm/mach-ks8695/irq.c
index 0773ae79572e..e5e71f4dbb84 100644
--- a/arch/arm/mach-ks8695/irq.c
+++ b/arch/arm/mach-ks8695/irq.c
@@ -25,14 +25,14 @@
 #include <linux/ioport.h>
 #include <linux/sysdev.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/io.h>
 
 #include <asm/mach/irq.h>
 
-#include <asm/arch/regs-irq.h>
-#include <asm/arch/regs-gpio.h>
+#include <mach/regs-irq.h>
+#include <mach/regs-gpio.h>
 
 static void ks8695_irq_mask(unsigned int irqno)
 {
diff --git a/arch/arm/mach-ks8695/leds.c b/arch/arm/mach-ks8695/leds.c
index 17c5ef13b0d1..184ef74e4bee 100644
--- a/arch/arm/mach-ks8695/leds.c
+++ b/arch/arm/mach-ks8695/leds.c
@@ -13,8 +13,8 @@
 #include <linux/init.h>
 
 #include <asm/leds.h>
-#include <asm/arch/devices.h>
-#include <asm/arch/gpio.h>
+#include <mach/devices.h>
+#include <mach/gpio.h>
 
 
 static inline void ks8695_led_on(unsigned int led)
diff --git a/arch/arm/mach-ks8695/pci.c b/arch/arm/mach-ks8695/pci.c
index c0c2d5901590..1746c67af176 100644
--- a/arch/arm/mach-ks8695/pci.c
+++ b/arch/arm/mach-ks8695/pci.c
@@ -31,10 +31,10 @@
 #include <asm/io.h>
 #include <asm/signal.h>
 #include <asm/mach/pci.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
-#include <asm/arch/devices.h>
-#include <asm/arch/regs-pci.h>
+#include <mach/devices.h>
+#include <mach/regs-pci.h>
 
 
 static int pci_dbg;
diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c
index 02f766b3121d..940888dffc16 100644
--- a/arch/arm/mach-ks8695/time.c
+++ b/arch/arm/mach-ks8695/time.c
@@ -28,8 +28,8 @@
 #include <asm/io.h>
 #include <asm/mach/time.h>
 
-#include <asm/arch/regs-timer.h>
-#include <asm/arch/regs-irq.h>
+#include <mach/regs-timer.h>
+#include <mach/regs-irq.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-l7200/core.c b/arch/arm/mach-l7200/core.c
index 8cec912fd030..50d23246d4f0 100644
--- a/arch/arm/mach-l7200/core.c
+++ b/arch/arm/mach-l7200/core.c
@@ -13,7 +13,7 @@
 #include <asm/types.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/page.h>
 
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-l7200/include/mach/aux_reg.h b/arch/arm/mach-l7200/include/mach/aux_reg.h
new file mode 100644
index 000000000000..4671558cdd51
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/aux_reg.h
@@ -0,0 +1,28 @@
+/*
+ * arch/arm/mach-l7200/include/mach/aux_reg.h
+ *
+ * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
+ *
+ * Changelog:
+ *   08-02-2000 SJH     Created file
+ */
+#ifndef _ASM_ARCH_AUXREG_H
+#define _ASM_ARCH_AUXREG_H
+
+#include <mach/hardware.h>
+
+#define l7200aux_reg    *((volatile unsigned int *) (AUX_BASE))
+
+/*
+ * Auxillary register values
+ */
+#define AUX_CLEAR               0x00000000
+#define AUX_DIAG_LED_ON         0x00000002
+#define AUX_RTS_UART1           0x00000004
+#define AUX_DTR_UART1           0x00000008
+#define AUX_KBD_COLUMN_12_HIGH  0x00000010
+#define AUX_KBD_COLUMN_12_OFF   0x00000020
+#define AUX_KBD_COLUMN_13_HIGH  0x00000040
+#define AUX_KBD_COLUMN_13_OFF   0x00000080
+
+#endif
diff --git a/arch/arm/mach-l7200/include/mach/debug-macro.S b/arch/arm/mach-l7200/include/mach/debug-macro.S
new file mode 100644
index 000000000000..34eed2a63e69
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/debug-macro.S
@@ -0,0 +1,40 @@
+/* arch/arm/mach-l7200/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+                .equ    io_virt, IO_BASE
+                .equ    io_phys, IO_START
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx, #io_phys           @ physical base address
+                movne   \rx, #io_virt           @ virtual address
+                add     \rx, \rx, #0x00044000   @ UART1
+@               add     \rx, \rx, #0x00045000   @ UART2
+                .endm
+
+                .macro  senduart,rd,rx
+                str     \rd, [\rx, #0x0]        @ UARTDR
+                .endm
+
+                .macro  waituart,rd,rx
+1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
+                tst     \rd, #1 << 5            @ UARTFLGUTXFF - 1 when full
+                bne     1001b
+                .endm
+
+                .macro  busyuart,rd,rx
+1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
+                tst     \rd, #1 << 3            @ UARTFLGUBUSY - 1 when busy
+                bne     1001b
+                .endm
diff --git a/arch/arm/mach-l7200/include/mach/dma.h b/arch/arm/mach-l7200/include/mach/dma.h
new file mode 100644
index 000000000000..c7e48bd4590c
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/dma.h
@@ -0,0 +1,23 @@
+/*
+ * arch/arm/mach-l7200/include/mach/dma.h
+ *
+ * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
+ *
+ * Changelog:
+ *  08-29-2000  SJH     Created
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+/* DMA is not yet implemented! It should be the same as acorn, copy over.. */
+
+/*
+ * This is the maximum DMA address that can be DMAd to.
+ * There should not be more than (0xd0000000 - 0xc0000000)
+ * bytes of RAM.
+ */
+#define MAX_DMA_ADDRESS         0xd0000000
+
+#define DMA_S0                  0
+
+#endif /* _ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-l7200/include/mach/entry-macro.S b/arch/arm/mach-l7200/include/mach/entry-macro.S
new file mode 100644
index 000000000000..1726d91fc1d3
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/entry-macro.S
@@ -0,0 +1,35 @@
+/*
+ * arch/arm/mach-l7200/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for L7200-based platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <mach/hardware.h>
+
+                .equ    irq_base_addr,  IO_BASE_2
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_preamble, base, tmp
+                .endm
+
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                mov     \irqstat, #irq_base_addr                @ Virt addr IRQ regs
+                add     \irqstat, \irqstat, #0x00001000         @ Status reg
+                ldr     \irqstat, [\irqstat, #0]                @ get interrupts
+                mov     \irqnr, #0
+1001:           tst     \irqstat, #1
+                addeq   \irqnr, \irqnr, #1
+                moveq   \irqstat, \irqstat, lsr #1
+                tsteq   \irqnr, #32
+                beq     1001b
+                teq     \irqnr, #32
+                .endm
+
diff --git a/arch/arm/mach-l7200/include/mach/gp_timers.h b/arch/arm/mach-l7200/include/mach/gp_timers.h
new file mode 100644
index 000000000000..2b7086a26b81
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/gp_timers.h
@@ -0,0 +1,42 @@
+/*
+ * arch/arm/mach-l7200/include/mach/gp_timers.h
+ *
+ * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
+ *
+ * Changelog:
+ *   07-28-2000 SJH     Created file
+ *   08-02-2000 SJH     Used structure for registers
+ */
+#ifndef _ASM_ARCH_GPTIMERS_H
+#define _ASM_ARCH_GPTIMERS_H
+
+#include <mach/hardware.h>
+
+/*
+ * Layout of L7200 general purpose timer registers
+ */
+struct GPT_Regs {
+        unsigned int TIMERLOAD;
+        unsigned int TIMERVALUE;
+        unsigned int TIMERCONTROL;
+        unsigned int TIMERCLEAR;
+};
+
+#define GPT_BASE                (IO_BASE_2 + 0x3000)
+#define l7200_timer1_regs       ((volatile struct GPT_Regs *) (GPT_BASE))
+#define l7200_timer2_regs       ((volatile struct GPT_Regs *) (GPT_BASE + 0x20))
+
+/*
+ * General register values
+ */
+#define GPT_PRESCALE_1          0x00000000
+#define GPT_PRESCALE_16         0x00000004
+#define GPT_PRESCALE_256        0x00000008
+#define GPT_MODE_FREERUN        0x00000000
+#define GPT_MODE_PERIODIC       0x00000040
+#define GPT_ENABLE              0x00000080
+#define GPT_BZTOG               0x00000100
+#define GPT_BZMOD               0x00000200
+#define GPT_LOAD_MASK           0x0000ffff
+
+#endif
diff --git a/arch/arm/mach-l7200/include/mach/gpio.h b/arch/arm/mach-l7200/include/mach/gpio.h
new file mode 100644
index 000000000000..c7b0a5d7b8bb
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/gpio.h
@@ -0,0 +1,105 @@
+/****************************************************************************/
+/*
+ *      arch/arm/mach-l7200/include/mach/gpio.h
+ *
+ *      Registers and  helper functions for the L7200 Link-Up Systems
+ *      GPIO.
+ *
+ *      (C) Copyright 2000, S A McConnell  (samcconn@cotw.com)
+ *
+ *  This file is subject to the terms and conditions of the GNU General Public
+ *  License. See the file COPYING in the main directory of this archive for
+ *  more details.
+ */
+
+/****************************************************************************/
+
+#define GPIO_OFF   0x00005000  /* Offset from IO_START to the GPIO reg's. */
+
+/* IO_START and IO_BASE are defined in hardware.h */
+
+#define GPIO_START (IO_START_2 + GPIO_OFF) /* Physical addr of the GPIO reg. */
+#define GPIO_BASE  (IO_BASE_2  + GPIO_OFF) /* Virtual addr of the GPIO reg. */
+
+/* Offsets from the start of the GPIO for all the registers. */
+#define PADR_OFF     0x000
+#define PADDR_OFF    0x004
+#define PASBSR_OFF   0x008
+#define PAEENR_OFF   0x00c
+#define PAESNR_OFF   0x010
+#define PAESTR_OFF   0x014
+#define PAIMR_OFF    0x018
+#define PAINT_OFF    0x01c
+
+#define PBDR_OFF     0x020
+#define PBDDR_OFF    0x024
+#define PBSBSR_OFF   0x028
+#define PBIMR_OFF    0x038
+#define PBINT_OFF    0x03c
+
+#define PCDR_OFF     0x040
+#define PCDDR_OFF    0x044
+#define PCSBSR_OFF   0x048
+#define PCIMR_OFF    0x058
+#define PCINT_OFF    0x05c
+
+#define PDDR_OFF     0x060
+#define PDDDR_OFF    0x064
+#define PDSBSR_OFF   0x068
+#define PDEENR_OFF   0x06c
+#define PDESNR_OFF   0x070
+#define PDESTR_OFF   0x074
+#define PDIMR_OFF    0x078
+#define PDINT_OFF    0x07c
+
+#define PEDR_OFF     0x080
+#define PEDDR_OFF    0x084
+#define PESBSR_OFF   0x088
+#define PEEENR_OFF   0x08c
+#define PEESNR_OFF   0x090
+#define PEESTR_OFF   0x094
+#define PEIMR_OFF    0x098
+#define PEINT_OFF    0x09c
+
+/* Define the GPIO registers for use by device drivers and the kernel. */
+#define PADR   (*(volatile unsigned long *)(GPIO_BASE+PADR_OFF))
+#define PADDR  (*(volatile unsigned long *)(GPIO_BASE+PADDR_OFF))
+#define PASBSR (*(volatile unsigned long *)(GPIO_BASE+PASBSR_OFF))
+#define PAEENR (*(volatile unsigned long *)(GPIO_BASE+PAEENR_OFF))
+#define PAESNR (*(volatile unsigned long *)(GPIO_BASE+PAESNR_OFF))
+#define PAESTR (*(volatile unsigned long *)(GPIO_BASE+PAESTR_OFF))
+#define PAIMR  (*(volatile unsigned long *)(GPIO_BASE+PAIMR_OFF))
+#define PAINT  (*(volatile unsigned long *)(GPIO_BASE+PAINT_OFF))
+
+#define PBDR   (*(volatile unsigned long *)(GPIO_BASE+PBDR_OFF))
+#define PBDDR  (*(volatile unsigned long *)(GPIO_BASE+PBDDR_OFF))
+#define PBSBSR (*(volatile unsigned long *)(GPIO_BASE+PBSBSR_OFF))
+#define PBIMR  (*(volatile unsigned long *)(GPIO_BASE+PBIMR_OFF))
+#define PBINT  (*(volatile unsigned long *)(GPIO_BASE+PBINT_OFF))
+
+#define PCDR   (*(volatile unsigned long *)(GPIO_BASE+PCDR_OFF))
+#define PCDDR  (*(volatile unsigned long *)(GPIO_BASE+PCDDR_OFF))
+#define PCSBSR (*(volatile unsigned long *)(GPIO_BASE+PCSBSR_OFF))
+#define PCIMR  (*(volatile unsigned long *)(GPIO_BASE+PCIMR_OFF))
+#define PCINT  (*(volatile unsigned long *)(GPIO_BASE+PCINT_OFF))
+
+#define PDDR   (*(volatile unsigned long *)(GPIO_BASE+PDDR_OFF))
+#define PDDDR  (*(volatile unsigned long *)(GPIO_BASE+PDDDR_OFF))
+#define PDSBSR (*(volatile unsigned long *)(GPIO_BASE+PDSBSR_OFF))
+#define PDEENR (*(volatile unsigned long *)(GPIO_BASE+PDEENR_OFF))
+#define PDESNR (*(volatile unsigned long *)(GPIO_BASE+PDESNR_OFF))
+#define PDESTR (*(volatile unsigned long *)(GPIO_BASE+PDESTR_OFF))
+#define PDIMR  (*(volatile unsigned long *)(GPIO_BASE+PDIMR_OFF))
+#define PDINT  (*(volatile unsigned long *)(GPIO_BASE+PDINT_OFF))
+
+#define PEDR   (*(volatile unsigned long *)(GPIO_BASE+PEDR_OFF))
+#define PEDDR  (*(volatile unsigned long *)(GPIO_BASE+PEDDR_OFF))
+#define PESBSR (*(volatile unsigned long *)(GPIO_BASE+PESBSR_OFF))
+#define PEEENR (*(volatile unsigned long *)(GPIO_BASE+PEEENR_OFF))
+#define PEESNR (*(volatile unsigned long *)(GPIO_BASE+PEESNR_OFF))
+#define PEESTR (*(volatile unsigned long *)(GPIO_BASE+PEESTR_OFF))
+#define PEIMR  (*(volatile unsigned long *)(GPIO_BASE+PEIMR_OFF))
+#define PEINT  (*(volatile unsigned long *)(GPIO_BASE+PEINT_OFF))
+
+#define VEE_EN         0x02
+#define BACKLIGHT_EN   0x04
diff --git a/arch/arm/mach-l7200/include/mach/hardware.h b/arch/arm/mach-l7200/include/mach/hardware.h
new file mode 100644
index 000000000000..c31909cfc254
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/hardware.h
@@ -0,0 +1,57 @@
+/*
+ * arch/arm/mach-l7200/include/mach/hardware.h
+ *
+ * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
+ *                    Steve Hill (sjhill@cotw.com)
+ *
+ * This file contains the hardware definitions for the 
+ * LinkUp Systems L7200 SOC development board.
+ *
+ * Changelog:
+ *   02-01-2000  RS     Created L7200 version, derived from rpc code
+ *   03-21-2000 SJH     Cleaned up file
+ *   04-21-2000  RS     Changed mapping of I/O in virtual space
+ *   04-25-2000 SJH     Removed unused symbols and such
+ *   05-05-2000 SJH     Complete rewrite
+ *   07-31-2000 SJH     Added undocumented debug auxillary port to
+ *                      get at last two columns for keyboard driver
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+/* Hardware addresses of major areas.
+ *  *_START is the physical address
+ *  *_SIZE  is the size of the region
+ *  *_BASE  is the virtual address
+ */
+#define RAM_START               0xf0000000
+#define RAM_SIZE                0x02000000
+#define RAM_BASE                0xc0000000
+
+#define IO_START                0x80000000      /* I/O */
+#define IO_SIZE                 0x01000000
+#define IO_BASE                 0xd0000000
+
+#define IO_START_2              0x90000000      /* I/O */
+#define IO_SIZE_2               0x01000000
+#define IO_BASE_2               0xd1000000
+
+#define AUX_START               0x1a000000      /* AUX PORT */
+#define AUX_SIZE                0x01000000
+#define AUX_BASE                0xd2000000
+
+#define FLASH1_START            0x00000000      /* FLASH BANK 1 */
+#define FLASH1_SIZE             0x01000000
+#define FLASH1_BASE             0xd3000000
+
+#define FLASH2_START            0x10000000      /* FLASH BANK 2 */
+#define FLASH2_SIZE             0x01000000
+#define FLASH2_BASE             0xd4000000
+
+#define ISA_START               0x20000000      /* ISA */
+#define ISA_SIZE                0x20000000
+#define ISA_BASE                0xe0000000
+
+#define PCIO_BASE               IO_BASE
+
+#endif
diff --git a/arch/arm/mach-l7200/include/mach/io.h b/arch/arm/mach-l7200/include/mach/io.h
new file mode 100644
index 000000000000..d432ba9e5dff
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/io.h
@@ -0,0 +1,27 @@
+/*
+ * arch/arm/mach-l7200/include/mach/io.h
+ *
+ * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
+ *
+ * Changelog:
+ *  03-21-2000  SJH     Created from arch/arm/mach-nexuspci/include/mach/io.h
+ *  08-31-2000  SJH     Added in IO functions necessary for new drivers
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#include <mach/hardware.h>
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * There are not real ISA nor PCI buses, so we fake it.
+ */
+static inline void __iomem *__io(unsigned long addr)
+{
+        return (void __iomem *)addr;
+}
+#define __io(a) __io(a)
+#define __mem_pci(a)            (a)
+
+#endif
diff --git a/arch/arm/mach-l7200/include/mach/irqs.h b/arch/arm/mach-l7200/include/mach/irqs.h
new file mode 100644
index 000000000000..7edffd713c5b
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/irqs.h
@@ -0,0 +1,56 @@
+/*
+ * arch/arm/mach-l7200/include/mach/irqs.h
+ *
+ * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
+ *                    Steve Hill (sjhill@cotw.com)
+ *
+ * Changelog:
+ *   01-02-2000 RS      Create l7200 version
+ *   03-28-2000 SJH     Removed unused interrupt
+ *   07-28-2000 SJH     Added pseudo-keyboard interrupt
+ */
+
+/*
+ * NOTE: The second timer (Timer 2) is used as the keyboard
+ *       interrupt when the keyboard driver is enabled.
+ */
+
+#define NR_IRQS          32
+
+#define IRQ_STWDOG        0   /* Watchdog timer */
+#define IRQ_PROG          1   /* Programmable interrupt */
+#define IRQ_DEBUG_RX      2   /* Comm Rx debug */
+#define IRQ_DEBUG_TX      3   /* Comm Tx debug */
+#define IRQ_GCTC1         4   /* Timer 1 */
+#define IRQ_GCTC2         5   /* Timer 2 / Keyboard */
+#define IRQ_DMA           6   /* DMA controller */
+#define IRQ_CLCD          7   /* Color LCD controller */
+#define IRQ_SM_RX         8   /* Smart card */
+#define IRQ_SM_TX         9   /* Smart cart */
+#define IRQ_SM_RST       10   /* Smart card */
+#define IRQ_SIB          11   /* Serial Interface Bus */
+#define IRQ_MMC          12   /* MultiMediaCard */
+#define IRQ_SSP1         13   /* Synchronous Serial Port 1 */
+#define IRQ_SSP2         14   /* Synchronous Serial Port 1 */
+#define IRQ_SPI          15   /* SPI slave */
+#define IRQ_UART_1       16   /* UART 1 */
+#define IRQ_UART_2       17   /* UART 2 */
+#define IRQ_IRDA         18   /* IRDA */
+#define IRQ_RTC_TICK     19   /* Real Time Clock tick */
+#define IRQ_RTC_ALARM    20   /* Real Time Clock alarm */
+#define IRQ_GPIO         21   /* General Purpose IO */
+#define IRQ_GPIO_DMA     22   /* General Purpose IO, DMA */
+#define IRQ_M2M          23   /* Memory to memory DMA  */
+#define IRQ_RESERVED     24   /* RESERVED, don't use */
+#define IRQ_INTF         25   /* External active low interrupt */
+#define IRQ_INT0         26   /* External active low interrupt */
+#define IRQ_INT1         27   /* External active low interrupt */
+#define IRQ_INT2         28   /* External active low interrupt */
+#define IRQ_UCB1200      29   /* Interrupt generated by UCB1200*/
+#define IRQ_BAT_LO       30   /* Low batery or external power */
+#define IRQ_MEDIA_CHG    31   /* Media change interrupt */
+
+/*
+ * This is the offset of the FIQ "IRQ" numbers
+ */
+#define FIQ_START       64
diff --git a/arch/arm/mach-l7200/include/mach/memory.h b/arch/arm/mach-l7200/include/mach/memory.h
new file mode 100644
index 000000000000..f338cf3ffd93
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/memory.h
@@ -0,0 +1,29 @@
+/*
+ * arch/arm/mach-l7200/include/mach/memory.h
+ *
+ * Copyright (c) 2000 Steve Hill (sjhill@cotw.com)
+ * Copyright (c) 2000 Rob Scott (rscott@mtrob.fdns.net)
+ *
+ * Changelog:
+ *  03-13-2000  SJH     Created
+ *  04-13-2000  RS      Changed bus macros for new addr
+ *  05-03-2000  SJH     Removed bus macros and fixed virt_to_phys macro
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset on the L7200 SDB.
+ */
+#define PHYS_OFFSET     UL(0xf0000000)
+
+#define __virt_to_bus(x) __virt_to_phys(x)
+#define __bus_to_virt(x) __phys_to_virt(x)
+
+/*
+ * Cache flushing area - ROM
+ */
+#define FLUSH_BASE_PHYS         0x40000000
+#define FLUSH_BASE              0xdf000000
+
+#endif
diff --git a/arch/arm/mach-l7200/include/mach/pmpcon.h b/arch/arm/mach-l7200/include/mach/pmpcon.h
new file mode 100644
index 000000000000..3959871e8361
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/pmpcon.h
@@ -0,0 +1,46 @@
+/****************************************************************************/
+/*
+ *  arch/arm/mach-l7200/include/mach/pmpcon.h
+ *
+ *   Registers and  helper functions for the L7200 Link-Up Systems
+ *   DC/DC converter register.
+ *
+ *   (C) Copyright 2000, S A McConnell  (samcconn@cotw.com)
+ *
+ *  This file is subject to the terms and conditions of the GNU General Public
+ *  License. See the file COPYING in the main directory of this archive for
+ *  more details.
+ */
+
+/****************************************************************************/
+
+#define PMPCON_OFF 0x00006000  /* Offset from IO_START_2. */
+
+/* IO_START_2 and IO_BASE_2 are defined in hardware.h */
+
+#define PMPCON_START (IO_START_2 + PMPCON_OFF)  /* Physical address of reg. */
+#define PMPCON_BASE  (IO_BASE_2  + PMPCON_OFF)  /* Virtual address of reg. */
+
+
+#define PMPCON (*(volatile unsigned int *)(PMPCON_BASE))
+
+#define PWM2_50CYCLE 0x800
+#define CONTRAST     0x9
+
+#define PWM1H (CONTRAST)
+#define PWM1L (CONTRAST << 4)
+
+#define PMPCON_VALUE  (PWM2_50CYCLE | PWM1L | PWM1H) 
+        
+/* PMPCON = 0x811;   // too light and fuzzy
+ * PMPCON = 0x844;   
+ * PMPCON = 0x866;   // better color poor depth
+ * PMPCON = 0x888;   // Darker but better depth 
+ * PMPCON = 0x899;   // Darker even better depth
+ * PMPCON = 0x8aa;   // too dark even better depth
+ * PMPCON = 0X8cc;   // Way too dark
+ */
+
+/* As CONTRAST value increases the greater the depth perception and
+ * the darker the colors.
+ */
diff --git a/arch/arm/mach-l7200/include/mach/pmu.h b/arch/arm/mach-l7200/include/mach/pmu.h
new file mode 100644
index 000000000000..a2da7aedf208
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/pmu.h
@@ -0,0 +1,125 @@
+/****************************************************************************/
+/*
+ *  arch/arm/mach-l7200/include/mach/pmu.h
+ *
+ *   Registers and  helper functions for the L7200 Link-Up Systems
+ *   Power Management Unit (PMU).
+ *
+ *   (C) Copyright 2000, S A McConnell  (samcconn@cotw.com)
+ *
+ *  This file is subject to the terms and conditions of the GNU General Public
+ *  License. See the file COPYING in the main directory of this archive for
+ *  more details.
+ */
+
+/****************************************************************************/
+
+#define PMU_OFF   0x00050000  /* Offset from IO_START to the PMU registers. */
+
+/* IO_START and IO_BASE are defined in hardware.h */
+
+#define PMU_START (IO_START + PMU_OFF)  /* Physical addr. of the PMU reg. */
+#define PMU_BASE  (IO_BASE  + PMU_OFF)  /* Virtual addr. of the PMU reg. */
+
+
+/* Define the PMU registers for use by device drivers and the kernel. */
+
+typedef struct {
+     unsigned int CURRENT;  /* Current configuration register */
+     unsigned int NEXT;     /* Next configuration register */
+     unsigned int reserved;
+     unsigned int RUN;      /* Run configuration register */
+     unsigned int COMM;     /* Configuration command register */
+     unsigned int SDRAM;    /* SDRAM configuration bypass register */
+} pmu_interface;
+
+#define PMU ((volatile pmu_interface *)(PMU_BASE))
+
+
+/* Macro's for reading the common register fields. */
+
+#define GET_TRANSOP(reg)  ((reg >> 25) & 0x03) /* Bits 26-25 */
+#define GET_OSCEN(reg)    ((reg >> 16) & 0x01)
+#define GET_OSCMUX(reg)   ((reg >> 15) & 0x01)
+#define GET_PLLMUL(reg)   ((reg >>  9) & 0x3f) /* Bits 14-9 */
+#define GET_PLLEN(reg)    ((reg >>  8) & 0x01)
+#define GET_PLLMUX(reg)   ((reg >>  7) & 0x01)
+#define GET_BCLK_DIV(reg) ((reg >>  3) & 0x03) /* Bits 4-3 */
+#define GET_SDRB_SEL(reg) ((reg >>  2) & 0x01)
+#define GET_SDRF_SEL(reg) ((reg >>  1) & 0x01)
+#define GET_FASTBUS(reg)  (reg & 0x1)
+
+/* CFG_NEXT register */
+
+#define CFG_NEXT_CLOCKRECOVERY ((PMU->NEXT >> 18) & 0x7f)   /* Bits 24-18 */
+#define CFG_NEXT_INTRET        ((PMU->NEXT >> 17) & 0x01)
+#define CFG_NEXT_SDR_STOP      ((PMU->NEXT >>  6) & 0x01)
+#define CFG_NEXT_SYSCLKEN      ((PMU->NEXT >>  5) & 0x01)
+
+/* Useful field values that can be used to construct the
+ * CFG_NEXT and CFG_RUN registers.
+ */
+
+#define TRANSOP_NOP      0<<25  /* NOCHANGE_NOSTALL */
+#define NOCHANGE_STALL   1<<25
+#define CHANGE_NOSTALL   2<<25
+#define CHANGE_STALL     3<<25
+
+#define INTRET           1<<17
+#define OSCEN            1<<16
+#define OSCMUX           1<<15
+
+/* PLL frequencies */
+
+#define PLLMUL_0         0<<9         /*  3.6864 MHz */
+#define PLLMUL_1         1<<9         /*  ?????? MHz */
+#define PLLMUL_5         5<<9         /*  18.432 MHz */
+#define PLLMUL_10       10<<9         /*  36.864 MHz */
+#define PLLMUL_18       18<<9         /*  ?????? MHz */
+#define PLLMUL_20       20<<9         /*  73.728 MHz */
+#define PLLMUL_32       32<<9         /*  ?????? MHz */
+#define PLLMUL_35       35<<9         /* 129.024 MHz */
+#define PLLMUL_36       36<<9         /*  ?????? MHz */
+#define PLLMUL_39       39<<9         /*  ?????? MHz */
+#define PLLMUL_40       40<<9         /* 147.456 MHz */
+
+/* Clock recovery times */
+
+#define CRCLOCK_1        1<<18
+#define CRCLOCK_2        2<<18
+#define CRCLOCK_4        4<<18
+#define CRCLOCK_8        8<<18
+#define CRCLOCK_16      16<<18
+#define CRCLOCK_32      32<<18
+#define CRCLOCK_63      63<<18
+#define CRCLOCK_127    127<<18
+
+#define PLLEN            1<<8
+#define PLLMUX           1<<7
+#define SDR_STOP         1<<6
+#define SYSCLKEN         1<<5
+
+#define BCLK_DIV_4       2<<3
+#define BCLK_DIV_2       1<<3
+#define BCLK_DIV_1       0<<3
+
+#define SDRB_SEL         1<<2
+#define SDRF_SEL         1<<1
+#define FASTBUS          1<<0
+
+
+/* CFG_SDRAM */
+
+#define SDRREFFQ         1<<0  /* Only if SDRSTOPRQ is not set. */
+#define SDRREFACK        1<<1  /* Read-only */
+#define SDRSTOPRQ        1<<2  /* Only if SDRREFFQ is not set. */
+#define SDRSTOPACK       1<<3  /* Read-only */
+#define PICEN            1<<4  /* Enable Co-procesor */
+#define PICTEST          1<<5
+
+#define GET_SDRREFFQ    ((PMU->SDRAM >> 0) & 0x01)
+#define GET_SDRREFACK   ((PMU->SDRAM >> 1) & 0x01) /* Read-only */
+#define GET_SDRSTOPRQ   ((PMU->SDRAM >> 2) & 0x01)
+#define GET_SDRSTOPACK  ((PMU->SDRAM >> 3) & 0x01) /* Read-only */
+#define GET_PICEN       ((PMU->SDRAM >> 4) & 0x01)
+#define GET_PICTEST     ((PMU->SDRAM >> 5) & 0x01)
diff --git a/arch/arm/mach-l7200/include/mach/serial.h b/arch/arm/mach-l7200/include/mach/serial.h
new file mode 100644
index 000000000000..adc05e5f8378
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/serial.h
@@ -0,0 +1,37 @@
+/*
+ * arch/arm/mach-l7200/include/mach/serial.h
+ *
+ * Copyright (c) 2000 Rob Scott (rscott@mtrob.fdns.net)
+ *                    Steve Hill (sjhill@cotw.com)
+ *
+ * Changelog:
+ *  03-20-2000  SJH     Created
+ *  03-26-2000  SJH     Added flags for serial ports
+ *  03-27-2000  SJH     Corrected BASE_BAUD value
+ *  04-14-2000  RS      Made register addr dependent on IO_BASE
+ *  05-03-2000  SJH     Complete rewrite
+ *  05-09-2000  SJH     Stripped out architecture specific serial stuff
+ *                      and placed it in a separate file
+ *  07-28-2000  SJH     Moved base baud rate variable
+ */
+#ifndef __ASM_ARCH_SERIAL_H
+#define __ASM_ARCH_SERIAL_H
+
+/*
+ * This assumes you have a 3.6864 MHz clock for your UART.
+ */
+#define BASE_BAUD       3686400
+
+/*
+ * Standard COM flags
+ */
+#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
+
+#define STD_SERIAL_PORT_DEFNS           \
+        /* MAGIC UART CLK   PORT       IRQ     FLAGS */                 \
+        { 0, BASE_BAUD, UART1_BASE, IRQ_UART_1, STD_COM_FLAGS },  /* ttyLU0 */ \
+        { 0, BASE_BAUD, UART2_BASE, IRQ_UART_2, STD_COM_FLAGS },  /* ttyLU1 */ \
+
+#define EXTRA_SERIAL_PORT_DEFNS
+
+#endif
diff --git a/arch/arm/mach-l7200/include/mach/serial_l7200.h b/arch/arm/mach-l7200/include/mach/serial_l7200.h
new file mode 100644
index 000000000000..645f1c5e568d
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/serial_l7200.h
@@ -0,0 +1,101 @@
+/*
+ * arch/arm/mach-l7200/include/mach/serial_l7200.h
+ *
+ * Copyright (c) 2000 Steven Hill (sjhill@cotw.com)
+ *
+ * Changelog:
+ *  05-09-2000  SJH     Created
+ */
+#ifndef __ASM_ARCH_SERIAL_L7200_H
+#define __ASM_ARCH_SERIAL_L7200_H
+
+#include <mach/memory.h>
+
+/*
+ * This assumes you have a 3.6864 MHz clock for your UART.
+ */
+#define BASE_BAUD 3686400
+
+/*
+ * UART base register addresses
+ */
+#define UART1_BASE      (IO_BASE + 0x00044000)
+#define UART2_BASE      (IO_BASE + 0x00045000)
+
+/*
+ * UART register offsets
+ */
+#define UARTDR                  0x00    /* Tx/Rx data */
+#define RXSTAT                  0x04    /* Rx status */
+#define H_UBRLCR                0x08    /* mode register high */
+#define M_UBRLCR                0x0C    /* mode reg mid (MSB of baud)*/
+#define L_UBRLCR                0x10    /* mode reg low (LSB of baud)*/
+#define UARTCON                 0x14    /* control register */
+#define UARTFLG                 0x18    /* flag register */
+#define UARTINTSTAT             0x1C    /* FIFO IRQ status register */
+#define UARTINTMASK             0x20    /* FIFO IRQ mask register */
+
+/*
+ * UART baud rate register values
+ */
+#define BR_110                  0x827
+#define BR_1200                 0x06e
+#define BR_2400                 0x05f
+#define BR_4800                 0x02f
+#define BR_9600                 0x017
+#define BR_14400                0x00f
+#define BR_19200                0x00b
+#define BR_38400                0x005
+#define BR_57600                0x003
+#define BR_76800                0x002
+#define BR_115200               0x001
+
+/*
+ * Receiver status register (RXSTAT) mask values
+ */
+#define RXSTAT_NO_ERR           0x00    /* No error */
+#define RXSTAT_FRM_ERR          0x01    /* Framing error */
+#define RXSTAT_PAR_ERR          0x02    /* Parity error */
+#define RXSTAT_OVR_ERR          0x04    /* Overrun error */
+
+/*
+ * High byte of UART bit rate and line control register (H_UBRLCR) values
+ */
+#define UBRLCR_BRK              0x01    /* generate break on tx */
+#define UBRLCR_PEN              0x02    /* enable parity */
+#define UBRLCR_PDIS             0x00    /* disable parity */
+#define UBRLCR_EVEN             0x04    /* 1= even parity,0 = odd parity */
+#define UBRLCR_STP2             0x08    /* transmit 2 stop bits */
+#define UBRLCR_FIFO             0x10    /* enable FIFO */
+#define UBRLCR_LEN5             0x60    /* word length5 */
+#define UBRLCR_LEN6             0x40    /* word length6 */
+#define UBRLCR_LEN7             0x20    /* word length7 */
+#define UBRLCR_LEN8             0x00    /* word length8 */
+
+/*
+ * UART control register (UARTCON) values
+ */
+#define UARTCON_UARTEN          0x01    /* Enable UART */
+#define UARTCON_DMAONERR        0x08    /* Mask RxDmaRq when errors occur */
+
+/*
+ * UART flag register (UARTFLG) mask values
+ */
+#define UARTFLG_UTXFF           0x20    /* Transmit FIFO full */
+#define UARTFLG_URXFE           0x10    /* Receiver FIFO empty */
+#define UARTFLG_UBUSY           0x08    /* Transmitter busy */
+#define UARTFLG_DCD             0x04    /* Data carrier detect */
+#define UARTFLG_DSR             0x02    /* Data set ready */
+#define UARTFLG_CTS             0x01    /* Clear to send */
+
+/*
+ * UART interrupt status/clear registers (UARTINTSTAT/CLR) values
+ */
+#define UART_TXINT              0x01    /* TX interrupt */
+#define UART_RXINT              0x02    /* RX interrupt */
+#define UART_RXERRINT           0x04    /* RX error interrupt */
+#define UART_MSINT              0x08    /* Modem Status interrupt */
+#define UART_UDINT              0x10    /* UART Disabled interrupt */
+#define UART_ALLIRQS            0x1f    /* All interrupts */
+
+#endif
diff --git a/arch/arm/mach-l7200/include/mach/sib.h b/arch/arm/mach-l7200/include/mach/sib.h
new file mode 100644
index 000000000000..965728712cf3
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/sib.h
@@ -0,0 +1,119 @@
+/****************************************************************************/
+/*
+ *  arch/arm/mach-l7200/include/mach/sib.h
+ *
+ *  Registers and helper functions for the Serial Interface Bus.
+ *
+ *  (C) Copyright 2000, S A McConnell  (samcconn@cotw.com)
+ *
+ *  This file is subject to the terms and conditions of the GNU General Public
+ *  License. See the file COPYING in the main directory of this archive for
+ *  more details.
+ */
+
+/****************************************************************************/
+
+#define SIB_OFF   0x00040000  /* Offset from IO_START to the SIB reg's. */
+
+/* IO_START and IO_BASE are defined in hardware.h */
+
+#define SIB_START (IO_START + SIB_OFF) /* Physical addr of the SIB reg. */
+#define SIB_BASE  (IO_BASE  + SIB_OFF) /* Virtual addr of the SIB reg.  */
+
+/* Offsets from the start of the SIB for all the registers. */
+
+/* Define the SIB registers for use by device drivers and the kernel. */
+
+typedef struct
+{
+     unsigned int MCCR;    /* SIB Control Register           Offset: 0x00 */
+     unsigned int RES1;    /* Reserved                       Offset: 0x04 */
+     unsigned int MCDR0;   /* SIB Data Register 0            Offset: 0x08 */
+     unsigned int MCDR1;   /* SIB Data Register 1            Offset: 0x0c */
+     unsigned int MCDR2;   /* SIB Data Register 2 (UCB1x00)  Offset: 0x10 */
+     unsigned int RES2;    /* Reserved                       Offset: 0x14 */
+     unsigned int MCSR;    /* SIB Status Register            Offset: 0x18 */
+} SIB_Interface;
+
+#define SIB ((volatile SIB_Interface *) (SIB_BASE))
+
+/* MCCR */
+
+#define INTERNAL_FREQ   9216000  /* Hertz */
+#define AUDIO_FREQ         5000  /* Hertz */
+#define TELECOM_FREQ       5000  /* Hertz */
+
+#define AUDIO_DIVIDE    (INTERNAL_FREQ / (32 * AUDIO_FREQ))
+#define TELECOM_DIVIDE  (INTERNAL_FREQ / (32 * TELECOM_FREQ))
+
+#define MCCR_ASD57      AUDIO_DIVIDE
+#define MCCR_TSD57      (TELECOM_DIVIDE << 8)
+#define MCCR_MCE        (1 << 16)             /* SIB enable */
+#define MCCR_ECS        (1 << 17)             /* External Clock Select */
+#define MCCR_ADM        (1 << 18)             /* A/D Data Sampling */
+#define MCCR_PMC        (1 << 26)             /* PIN Multiplexer Control */
+
+
+#define GET_ASD ((SIB->MCCR >>  0) & 0x3f) /* Audio Sample Rate Div. */
+#define GET_TSD ((SIB->MCCR >>  8) & 0x3f) /* Telcom Sample Rate Div. */
+#define GET_MCE ((SIB->MCCR >> 16) & 0x01) /* SIB Enable */
+#define GET_ECS ((SIB->MCCR >> 17) & 0x01) /* External Clock Select */
+#define GET_ADM ((SIB->MCCR >> 18) & 0x01) /* A/D Data Sampling Mode */
+#define GET_TTM ((SIB->MCCR >> 19) & 0x01) /* Telco Trans. FIFO I mask */ 
+#define GET_TRM ((SIB->MCCR >> 20) & 0x01) /* Telco Recv. FIFO I mask */
+#define GET_ATM ((SIB->MCCR >> 21) & 0x01) /* Audio Trans. FIFO I mask */ 
+#define GET_ARM ((SIB->MCCR >> 22) & 0x01) /* Audio Recv. FIFO I mask */
+#define GET_LBM ((SIB->MCCR >> 23) & 0x01) /* Loop Back Mode */
+#define GET_ECP ((SIB->MCCR >> 24) & 0x03) /* Extern. Clck Prescale sel */
+#define GET_PMC ((SIB->MCCR >> 26) & 0x01) /* PIN Multiplexer Control */
+#define GET_ERI ((SIB->MCCR >> 27) & 0x01) /* External Read Interrupt */
+#define GET_EWI ((SIB->MCCR >> 28) & 0x01) /* External Write Interrupt */
+
+/* MCDR0 */
+
+#define AUDIO_RECV     ((SIB->MCDR0 >> 4) & 0xfff)
+#define AUDIO_WRITE(v) ((SIB->MCDR0 = (v & 0xfff) << 4))
+
+/* MCDR1 */
+
+#define TELECOM_RECV     ((SIB->MCDR1 >> 2) & 032fff)
+#define TELECOM_WRITE(v) ((SIB->MCDR1 = (v & 0x3fff) << 2))
+
+
+/* MCSR */
+
+#define MCSR_ATU (1 << 4)  /* Audio Transmit FIFO Underrun */
+#define MCSR_ARO (1 << 5)  /* Audio Receive  FIFO Underrun */
+#define MCSR_TTU (1 << 6)  /* TELECOM Transmit FIFO Underrun */
+#define MCSR_TRO (1 << 7)  /* TELECOM Receive  FIFO Underrun */
+
+#define MCSR_CLEAR_UNDERUN_BITS (MCSR_ATU | MCSR_ARO | MCSR_TTU | MCSR_TRO)
+
+
+#define GET_ATS ((SIB->MCSR >>  0) & 0x01) /* Audio Transmit FIFO Service Req*/
+#define GET_ARS ((SIB->MCSR >>  1) & 0x01) /* Audio Recv FIFO Service Request*/
+#define GET_TTS ((SIB->MCSR >>  2) & 0x01) /* TELECOM Transmit FIFO  Flag */
+#define GET_TRS ((SIB->MCSR >>  3) & 0x01) /* TELECOM Recv FIFO Service Req. */
+#define GET_ATU ((SIB->MCSR >>  4) & 0x01) /* Audio Transmit FIFO Underrun */
+#define GET_ARO ((SIB->MCSR >>  5) & 0x01) /* Audio Receive  FIFO Underrun */
+#define GET_TTU ((SIB->MCSR >>  6) & 0x01) /* TELECOM Transmit FIFO Underrun */
+#define GET_TRO ((SIB->MCSR >>  7) & 0x01) /* TELECOM Receive  FIFO Underrun */
+#define GET_ANF ((SIB->MCSR >>  8) & 0x01) /* Audio Transmit FIFO not full */
+#define GET_ANE ((SIB->MCSR >>  9) & 0x01) /* Audio Receive FIFO not empty */
+#define GET_TNF ((SIB->MCSR >> 10) & 0x01) /* Telecom Transmit FIFO not full */
+#define GET_TNE ((SIB->MCSR >> 11) & 0x01) /* Telecom Receive FIFO not empty */
+#define GET_CWC ((SIB->MCSR >> 12) & 0x01) /* Codec Write Complete */
+#define GET_CRC ((SIB->MCSR >> 13) & 0x01) /* Codec Read Complete */
+#define GET_ACE ((SIB->MCSR >> 14) & 0x01) /* Audio Codec Enabled */
+#define GET_TCE ((SIB->MCSR >> 15) & 0x01) /* Telecom Codec Enabled */
+
+/* MCDR2 */
+
+#define MCDR2_rW               (1 << 16)
+
+#define WRITE_MCDR2(reg, data) (SIB->MCDR2 =((reg<<17)|MCDR2_rW|(data&0xffff)))
+#define MCDR2_WRITE_COMPLETE   GET_CWC
+
+#define INITIATE_MCDR2_READ(reg) (SIB->MCDR2 = (reg << 17))
+#define MCDR2_READ_COMPLETE      GET_CRC
+#define MCDR2_READ               (SIB->MCDR2 & 0xffff)
diff --git a/arch/arm/mach-l7200/include/mach/sys-clock.h b/arch/arm/mach-l7200/include/mach/sys-clock.h
new file mode 100644
index 000000000000..2d7722be60ea
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/sys-clock.h
@@ -0,0 +1,67 @@
+/****************************************************************************/
+/*
+ *  arch/arm/mach-l7200/include/mach/sys-clock.h
+ *
+ *   Registers and  helper functions for the L7200 Link-Up Systems
+ *   System clocks.
+ *
+ *   (C) Copyright 2000, S A McConnell  (samcconn@cotw.com)
+ *
+ *  This file is subject to the terms and conditions of the GNU General Public
+ *  License. See the file COPYING in the main directory of this archive for
+ *  more details.
+ */
+
+/****************************************************************************/
+
+#define SYS_CLOCK_OFF   0x00050030  /* Offset from IO_START. */
+
+/* IO_START and IO_BASE are defined in hardware.h */
+
+#define SYS_CLOCK_START (IO_START + SYS_CLCOK_OFF)  /* Physical address */
+#define SYS_CLOCK_BASE  (IO_BASE  + SYS_CLOCK_OFF)  /* Virtual address  */
+
+/* Define the interface to the SYS_CLOCK */
+
+typedef struct
+{
+     unsigned int ENABLE;
+     unsigned int ESYNC;
+     unsigned int SELECT;
+} sys_clock_interface;
+
+#define SYS_CLOCK   ((volatile sys_clock_interface *)(SYS_CLOCK_BASE))
+
+//#define CLOCK_EN    (*(volatile unsigned long *)(PMU_BASE+CLOCK_EN_OFF))
+//#define CLOCK_ESYNC (*(volatile unsigned long *)(PMU_BASE+CLOCK_ESYNC_OFF))
+//#define CLOCK_SEL   (*(volatile unsigned long *)(PMU_BASE+CLOCK_SEL_OFF))
+
+/* SYS_CLOCK -> ENABLE */
+
+#define SYN_EN          1<<0
+#define B18M_EN         1<<1
+#define CLK3M6_EN       1<<2
+#define BUART_EN        1<<3
+#define CLK18MU_EN      1<<4
+#define FIR_EN          1<<5
+#define MIRN_EN         1<<6
+#define UARTM_EN        1<<7
+#define SIBADC_EN       1<<8
+#define ALTD_EN         1<<9
+#define CLCLK_EN        1<<10
+
+/* SYS_CLOCK -> SELECT */
+
+#define CLK18M_DIV      1<<0
+#define MIR_SEL         1<<1
+#define SSP_SEL         1<<4
+#define MM_DIV          1<<5
+#define MM_SEL          1<<6
+#define ADC_SEL_2       0<<7
+#define ADC_SEL_4       1<<7
+#define ADC_SEL_8       3<<7
+#define ADC_SEL_16      7<<7
+#define ADC_SEL_32      0x0f<<7
+#define ADC_SEL_64      0x1f<<7
+#define ADC_SEL_128     0x3f<<7
+#define ALTD_SEL        1<<13
diff --git a/arch/arm/mach-l7200/include/mach/system.h b/arch/arm/mach-l7200/include/mach/system.h
new file mode 100644
index 000000000000..5272abee0d0e
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/system.h
@@ -0,0 +1,29 @@
+/*
+ * arch/arm/mach-l7200/include/mach/system.h
+ *
+ * Copyright (c) 2000 Steve Hill (sjhill@cotw.com)
+ *
+ * Changelog
+ *  03-21-2000  SJH     Created
+ *  04-26-2000  SJH     Fixed functions
+ *  05-03-2000  SJH     Removed usage of obsolete 'iomd.h'
+ *  05-31-2000  SJH     Properly implemented 'arch_idle'
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <mach/hardware.h>
+
+static inline void arch_idle(void)
+{
+        *(unsigned long *)(IO_BASE + 0x50004) = 1;      /* idle mode */
+}
+
+static inline void arch_reset(char mode)
+{
+        if (mode == 's') {
+                cpu_reset(0);
+        }
+}
+
+#endif
diff --git a/arch/arm/mach-l7200/include/mach/time.h b/arch/arm/mach-l7200/include/mach/time.h
new file mode 100644
index 000000000000..061771c2c2bd
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/time.h
@@ -0,0 +1,73 @@
+/*
+ * arch/arm/mach-l7200/include/mach/time.h
+ *
+ * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
+ *                    Steve Hill (sjhill@cotw.com)
+ *
+ * Changelog:
+ *   01-02-2000 RS      Created l7200 version, derived from rpc code
+ *   05-03-2000 SJH     Complete rewrite
+ */
+#ifndef _ASM_ARCH_TIME_H
+#define _ASM_ARCH_TIME_H
+
+#include <mach/irqs.h>
+
+/*
+ * RTC base register address
+ */
+#define RTC_BASE        (IO_BASE_2 + 0x2000)
+
+/*
+ * RTC registers
+ */
+#define RTC_RTCDR       (*(volatile unsigned char *) (RTC_BASE + 0x000))
+#define RTC_RTCMR       (*(volatile unsigned char *) (RTC_BASE + 0x004))
+#define RTC_RTCS        (*(volatile unsigned char *) (RTC_BASE + 0x008))
+#define RTC_RTCC        (*(volatile unsigned char *) (RTC_BASE + 0x008))
+#define RTC_RTCDV       (*(volatile unsigned char *) (RTC_BASE + 0x00c))
+#define RTC_RTCCR       (*(volatile unsigned char *) (RTC_BASE + 0x010))
+
+/*
+ * RTCCR register values
+ */
+#define RTC_RATE_32     0x00      /* 32 Hz tick */
+#define RTC_RATE_64     0x10      /* 64 Hz tick */
+#define RTC_RATE_128    0x20      /* 128 Hz tick */
+#define RTC_RATE_256    0x30      /* 256 Hz tick */
+#define RTC_EN_ALARM    0x01      /* Enable alarm */
+#define RTC_EN_TIC      0x04      /* Enable counter */
+#define RTC_EN_STWDOG   0x08      /* Enable watchdog */
+
+/*
+ * Handler for RTC timer interrupt
+ */
+static irqreturn_t
+timer_interrupt(int irq, void *dev_id)
+{
+        struct pt_regs *regs = get_irq_regs();
+        do_timer(1);
+#ifndef CONFIG_SMP
+        update_process_times(user_mode(regs));
+#endif
+        do_profile(regs);
+        RTC_RTCC = 0;                           /* Clear interrupt */
+
+        return IRQ_HANDLED;
+}
+
+/*
+ * Set up RTC timer interrupt, and return the current time in seconds.
+ */
+void __init time_init(void)
+{
+        RTC_RTCC = 0;                           /* Clear interrupt */
+
+        timer_irq.handler = timer_interrupt;
+
+        setup_irq(IRQ_RTC_TICK, &timer_irq);
+
+        RTC_RTCCR = RTC_RATE_128 | RTC_EN_TIC;  /* Set rate and enable timer */
+}
+
+#endif
diff --git a/arch/arm/mach-l7200/include/mach/timex.h b/arch/arm/mach-l7200/include/mach/timex.h
new file mode 100644
index 000000000000..ffc96a63b5a2
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/timex.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/mach-l7200/include/mach/timex.h
+ *
+ * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
+ *                    Steve Hill (sjhill@cotw.com)
+ *
+ * 04-21-2000  RS Created file
+ * 05-03-2000 SJH Tick rate was wrong
+ *
+ */
+
+/*
+ * On the ARM720T, clock ticks are set to 128 Hz.
+ *
+ * NOTE: The actual RTC value is set in 'time.h' which
+ *       must be changed when choosing a different tick
+ *       rate. The value of HZ in 'param.h' must also
+ *       be changed to match below.
+ */
+#define CLOCK_TICK_RATE         128
diff --git a/arch/arm/mach-l7200/include/mach/uncompress.h b/arch/arm/mach-l7200/include/mach/uncompress.h
new file mode 100644
index 000000000000..591c962bb315
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/uncompress.h
@@ -0,0 +1,39 @@
+/*
+ * arch/arm/mach-l7200/include/mach/uncompress.h
+ *
+ * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
+ *
+ * Changelog:
+ *  05-01-2000  SJH     Created
+ *  05-13-2000  SJH     Filled in function bodies
+ *  07-26-2000  SJH     Removed hard coded baud rate
+ */
+
+#include <mach/hardware.h>
+
+#define IO_UART  IO_START + 0x00044000
+
+#define __raw_writeb(v,p)       (*(volatile unsigned char *)(p) = (v))
+#define __raw_readb(p)          (*(volatile unsigned char *)(p))
+
+static inline void putc(int c)
+{
+        while(__raw_readb(IO_UART + 0x18) & 0x20 ||
+              __raw_readb(IO_UART + 0x18) & 0x08)
+                barrier();
+
+        __raw_writeb(c, IO_UART + 0x00);
+}
+
+static inline void flush(void)
+{
+}
+
+static __inline__ void arch_decomp_setup(void)
+{
+        __raw_writeb(0x00, IO_UART + 0x08);     /* Set HSB */
+        __raw_writeb(0x00, IO_UART + 0x20);     /* Disable IRQs */
+        __raw_writeb(0x01, IO_UART + 0x14);     /* Enable UART */
+}
+
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-l7200/include/mach/vmalloc.h b/arch/arm/mach-l7200/include/mach/vmalloc.h
new file mode 100644
index 000000000000..85f0abbf15f1
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/vmalloc.h
@@ -0,0 +1,4 @@
+/*
+ * arch/arm/mach-l7200/include/mach/vmalloc.h
+ */
+#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
diff --git a/arch/arm/mach-lh7a40x/arch-kev7a400.c b/arch/arm/mach-lh7a40x/arch-kev7a400.c
index c794ca7a5f20..551b97261826 100644
--- a/arch/arm/mach-lh7a40x/arch-kev7a400.c
+++ b/arch/arm/mach-lh7a40x/arch-kev7a400.c
@@ -13,7 +13,7 @@
 #include <linux/device.h>
 #include <linux/interrupt.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
index ff3109a00c2b..e373fb8e2699 100644
--- a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
+++ b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
@@ -14,7 +14,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-lh7a40x/clcd.c b/arch/arm/mach-lh7a40x/clcd.c
index 395ad9b83c40..a2a543258fc3 100644
--- a/arch/arm/mach-lh7a40x/clcd.c
+++ b/arch/arm/mach-lh7a40x/clcd.c
@@ -23,7 +23,7 @@
 #include <asm/mach/irq.h>
 
 #include <asm/system.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
 
diff --git a/arch/arm/mach-lh7a40x/clocks.c b/arch/arm/mach-lh7a40x/clocks.c
index 9fe7f3a48949..4fb23ac6b5ac 100644
--- a/arch/arm/mach-lh7a40x/clocks.c
+++ b/arch/arm/mach-lh7a40x/clocks.c
@@ -9,8 +9,8 @@
  */
 
 #include <linux/cpufreq.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/clocks.h>
+#include <mach/hardware.h>
+#include <mach/clocks.h>
 #include <linux/err.h>
 
 struct module;
diff --git a/arch/arm/mach-lh7a40x/include/mach/clocks.h b/arch/arm/mach-lh7a40x/include/mach/clocks.h
new file mode 100644
index 000000000000..fe2e0255c084
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/include/mach/clocks.h
@@ -0,0 +1,18 @@
+/* arch/arm/mach-lh7a40x/include/mach/clocks.h
+ *
+ *  Copyright (C) 2004 Marc Singer
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_CLOCKS_H
+#define __ASM_ARCH_CLOCKS_H
+
+unsigned int fclkfreq_get (void);
+unsigned int hclkfreq_get (void);
+unsigned int pclkfreq_get (void);
+
+#endif  /* _ASM_ARCH_CLOCKS_H */
diff --git a/arch/arm/mach-lh7a40x/include/mach/constants.h b/arch/arm/mach-lh7a40x/include/mach/constants.h
new file mode 100644
index 000000000000..55c6edbc2dfd
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/include/mach/constants.h
@@ -0,0 +1,91 @@
+/* arch/arm/mach-lh7a40x/include/mach/constants.h
+ *
+ *  Copyright (C) 2004 Coastal Environmental Systems
+ *  Copyright (C) 2004 Logic Product Development
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_CONSTANTS_H
+#define __ASM_ARCH_CONSTANTS_H
+
+
+/* Addressing constants */
+
+        /* SoC CPU IO addressing */
+#define IO_PHYS                 (0x80000000)
+#define IO_VIRT                 (0xf8000000)
+#define IO_SIZE                 (0x0000B000)
+
+#ifdef CONFIG_MACH_KEV7A400
+# define CPLD_PHYS              (0x20000000)
+# define CPLD_VIRT              (0xf2000000)
+# define CPLD_SIZE              PAGE_SIZE
+#endif
+
+#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
+
+# define IOBARRIER_PHYS         0x10000000 /* Second bank, fastest timing */
+# define IOBARRIER_VIRT         0xf0000000
+# define IOBARRIER_SIZE         PAGE_SIZE
+
+# define CF_PHYS                0x60200000
+# define CF_VIRT                0xf6020000
+# define CF_SIZE                (8*1024)
+
+        /* The IO mappings for the LPD CPLD are, unfortunately, sparse.  */
+# define CPLDX_PHYS(x)          (0x70000000 | ((x) << 20))
+# define CPLDX_VIRT(x)          (0xf7000000 | ((x) << 16))
+# define CPLD00_PHYS            CPLDX_PHYS (0x00) /* Wired LAN */
+# define CPLD00_VIRT            CPLDX_VIRT (0x00)
+# define CPLD00_SIZE            PAGE_SIZE
+# define CPLD02_PHYS            CPLDX_PHYS (0x02)
+# define CPLD02_VIRT            CPLDX_VIRT (0x02)
+# define CPLD02_SIZE            PAGE_SIZE
+# define CPLD06_PHYS            CPLDX_PHYS (0x06)
+# define CPLD06_VIRT            CPLDX_VIRT (0x06)
+# define CPLD06_SIZE            PAGE_SIZE
+# define CPLD08_PHYS            CPLDX_PHYS (0x08)
+# define CPLD08_VIRT            CPLDX_VIRT (0x08)
+# define CPLD08_SIZE            PAGE_SIZE
+# define CPLD0A_PHYS            CPLDX_PHYS (0x0a)
+# define CPLD0A_VIRT            CPLDX_VIRT (0x0a)
+# define CPLD0A_SIZE            PAGE_SIZE
+# define CPLD0C_PHYS            CPLDX_PHYS (0x0c)
+# define CPLD0C_VIRT            CPLDX_VIRT (0x0c)
+# define CPLD0C_SIZE            PAGE_SIZE
+# define CPLD0E_PHYS            CPLDX_PHYS (0x0e)
+# define CPLD0E_VIRT            CPLDX_VIRT (0x0e)
+# define CPLD0E_SIZE            PAGE_SIZE
+# define CPLD10_PHYS            CPLDX_PHYS (0x10)
+# define CPLD10_VIRT            CPLDX_VIRT (0x10)
+# define CPLD10_SIZE            PAGE_SIZE
+# define CPLD12_PHYS            CPLDX_PHYS (0x12)
+# define CPLD12_VIRT            CPLDX_VIRT (0x12)
+# define CPLD12_SIZE            PAGE_SIZE
+# define CPLD14_PHYS            CPLDX_PHYS (0x14)
+# define CPLD14_VIRT            CPLDX_VIRT (0x14)
+# define CPLD14_SIZE            PAGE_SIZE
+# define CPLD16_PHYS            CPLDX_PHYS (0x16)
+# define CPLD16_VIRT            CPLDX_VIRT (0x16)
+# define CPLD16_SIZE            PAGE_SIZE
+# define CPLD18_PHYS            CPLDX_PHYS (0x18)
+# define CPLD18_VIRT            CPLDX_VIRT (0x18)
+# define CPLD18_SIZE            PAGE_SIZE
+# define CPLD1A_PHYS            CPLDX_PHYS (0x1a)
+# define CPLD1A_VIRT            CPLDX_VIRT (0x1a)
+# define CPLD1A_SIZE            PAGE_SIZE
+#endif
+
+        /* Timing constants */
+
+#define XTAL_IN                 14745600        /* 14.7456 MHz crystal */
+#define PLL_CLOCK               (XTAL_IN * 21)  /* 309 MHz PLL clock */
+#define MAX_HCLK_KHZ            100000          /* HCLK max limit ~100MHz */
+#define HCLK                    (99993600)
+//#define HCLK                  (119808000)
+
+#endif /* __ASM_ARCH_CONSTANTS_H */
diff --git a/arch/arm/mach-lh7a40x/include/mach/debug-macro.S b/arch/arm/mach-lh7a40x/include/mach/debug-macro.S
new file mode 100644
index 000000000000..85141ed5383d
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/include/mach/debug-macro.S
@@ -0,0 +1,39 @@
+/* arch/arm/mach-lh7a40x/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+        @ It is not known if this will be appropriate for every 40x
+        @ board.
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                mov     \rx, #0x00000700        @ offset from base
+                orreq   \rx, \rx, #0x80000000   @ physical base
+                orrne   \rx, \rx, #0xf8000000   @ virtual base
+                .endm
+
+                .macro  senduart,rd,rx
+                strb    \rd, [\rx]              @ DATA
+                .endm
+
+                .macro  busyuart,rd,rx          @ spin while busy
+1001:           ldr     \rd, [\rx, #0x10]       @ STATUS
+                tst     \rd, #1 << 3            @ BUSY (TX FIFO not empty)
+                bne     1001b                   @ yes, spin
+                .endm
+
+                .macro  waituart,rd,rx          @ wait for Tx FIFO room
+1001:           ldrb    \rd, [\rx, #0x10]       @ STATUS
+                tst     \rd, #1 << 5            @ TXFF (TX FIFO full)
+                bne     1001b                   @ yes, spin
+                .endm
diff --git a/arch/arm/mach-lh7a40x/include/mach/dma.h b/arch/arm/mach-lh7a40x/include/mach/dma.h
new file mode 100644
index 000000000000..baa3f8dbd04b
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/include/mach/dma.h
@@ -0,0 +1,86 @@
+/* arch/arm/mach-lh7a40x/include/mach/dma.h
+ *
+ *  Copyright (C) 2005 Marc Singer
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  version 2 as published by the Free Software Foundation.
+ *
+ */
+
+typedef enum {
+        DMA_M2M0        = 0,
+        DMA_M2M1        = 1,
+        DMA_M2P0        = 2,    /* Tx */
+        DMA_M2P1        = 3,    /* Rx */
+        DMA_M2P2        = 4,    /* Tx */
+        DMA_M2P3        = 5,    /* Rx */
+        DMA_M2P4        = 6,    /* Tx - AC97 */
+        DMA_M2P5        = 7,    /* Rx - AC97 */
+        DMA_M2P6        = 8,    /* Tx */
+        DMA_M2P7        = 9,    /* Rx */
+} dma_device_t;
+
+#define DMA_LENGTH_MAX          ((64*1024) - 4) /* bytes */
+
+#define DMAC_GCA                __REG(DMAC_PHYS + 0x2b80)
+#define DMAC_GIR                __REG(DMAC_PHYS + 0x2bc0)
+
+#define DMAC_GIR_MMI1           (1<<11)
+#define DMAC_GIR_MMI0           (1<<10)
+#define DMAC_GIR_MPI8           (1<<9)
+#define DMAC_GIR_MPI9           (1<<8)
+#define DMAC_GIR_MPI6           (1<<7)
+#define DMAC_GIR_MPI7           (1<<6)
+#define DMAC_GIR_MPI4           (1<<5)
+#define DMAC_GIR_MPI5           (1<<4)
+#define DMAC_GIR_MPI2           (1<<3)
+#define DMAC_GIR_MPI3           (1<<2)
+#define DMAC_GIR_MPI0           (1<<1)
+#define DMAC_GIR_MPI1           (1<<0)
+
+#define DMAC_M2P0               0x0000
+#define DMAC_M2P1               0x0040
+#define DMAC_M2P2               0x0080
+#define DMAC_M2P3               0x00c0
+#define DMAC_M2P4               0x0240
+#define DMAC_M2P5               0x0200
+#define DMAC_M2P6               0x02c0
+#define DMAC_M2P7               0x0280
+#define DMAC_M2P8               0x0340
+#define DMAC_M2P9               0x0300
+#define DMAC_M2M0               0x0100
+#define DMAC_M2M1               0x0140
+
+#define DMAC_P_PCONTROL(c)      __REG(DMAC_PHYS + (c) + 0x00)
+#define DMAC_P_PINTERRUPT(c)    __REG(DMAC_PHYS + (c) + 0x04)
+#define DMAC_P_PPALLOC(c)       __REG(DMAC_PHYS + (c) + 0x08)
+#define DMAC_P_PSTATUS(c)       __REG(DMAC_PHYS + (c) + 0x0c)
+#define DMAC_P_REMAIN(c)        __REG(DMAC_PHYS + (c) + 0x14)
+#define DMAC_P_MAXCNT0(c)       __REG(DMAC_PHYS + (c) + 0x20)
+#define DMAC_P_BASE0(c)         __REG(DMAC_PHYS + (c) + 0x24)
+#define DMAC_P_CURRENT0(c)      __REG(DMAC_PHYS + (c) + 0x28)
+#define DMAC_P_MAXCNT1(c)       __REG(DMAC_PHYS + (c) + 0x30)
+#define DMAC_P_BASE1(c)         __REG(DMAC_PHYS + (c) + 0x34)
+#define DMAC_P_CURRENT1(c)      __REG(DMAC_PHYS + (c) + 0x38)
+
+#define DMAC_PCONTROL_ENABLE    (1<<4)
+
+#define DMAC_PORT_USB           0
+#define DMAC_PORT_SDMMC         1
+#define DMAC_PORT_AC97_1        2
+#define DMAC_PORT_AC97_2        3
+#define DMAC_PORT_AC97_3        4
+#define DMAC_PORT_UART1         6
+#define DMAC_PORT_UART2         7
+#define DMAC_PORT_UART3         8
+
+#define DMAC_PSTATUS_CURRSTATE_SHIFT    4
+#define DMAC_PSTATUS_CURRSTATE_MASK     0x3
+
+#define DMAC_PSTATUS_NEXTBUF     (1<<6)
+#define DMAC_PSTATUS_STALLRINT   (1<<0)
+
+#define DMAC_INT_CHE             (1<<3)
+#define DMAC_INT_NFB             (1<<1)
+#define DMAC_INT_STALL           (1<<0)
diff --git a/arch/arm/mach-lh7a40x/include/mach/entry-macro.S b/arch/arm/mach-lh7a40x/include/mach/entry-macro.S
new file mode 100644
index 000000000000..069bb4cefff7
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/include/mach/entry-macro.S
@@ -0,0 +1,149 @@
+/*
+ * arch/arm/mach-lh7a40x/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for LH7A40x platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+
+/* In order to allow there to be support for both of the processor
+   classes at the same time, we make a hack here that isn't very
+   pretty.  At startup, the link pointed to with the
+   branch_irq_lh7a400 symbol is replaced with a NOP when the CPU is
+   detected as a lh7a404.
+
+   *** FIXME: we should clean this up so that there is only one
+              implementation for each CPU's design.
+
+*/
+
+#if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_preamble, base, tmp
+                .endm
+
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+branch_irq_lh7a400: b 1000f
+
+@ Implementation of the LH7A404 get_irqnr_and_base.
+
+                mov     \irqnr, #0                      @ VIC1 irq base
+                mov     \base, #io_p2v(0x80000000)      @ APB registers
+                add     \base, \base, #0x8000
+                ldr     \tmp, [\base, #0x0030]          @ VIC1_VECTADDR
+                tst     \tmp, #VA_VECTORED              @ Direct vectored
+                bne     1002f
+                tst     \tmp, #VA_VIC1DEFAULT           @ Default vectored VIC1
+                ldrne   \irqstat, [\base, #0]           @ VIC1_IRQSTATUS
+                bne     1001f
+                add     \base, \base, #(0xa000 - 0x8000)
+                ldr     \tmp, [\base, #0x0030]          @ VIC2_VECTADDR
+                tst     \tmp, #VA_VECTORED              @ Direct vectored
+                bne     1002f
+                ldr     \irqstat, [\base, #0]           @ VIC2_IRQSTATUS
+                mov     \irqnr, #32                     @ VIC2 irq base
+
+1001:           movs    \irqstat, \irqstat, lsr #1      @ Shift into carry
+                bcs     1008f                           @ Bit set; irq found
+                add     \irqnr, \irqnr, #1
+                bne     1001b                           @ Until no bits
+                b       1009f                           @ Nothing?  Hmm.
+1002:           and     \irqnr, \tmp, #0x3f             @ Mask for valid bits
+1008:           movs    \irqstat, #1                    @ Force !Z
+                str     \tmp, [\base, #0x0030]          @ Clear vector
+                b       1009f
+
+@ Implementation of the LH7A400 get_irqnr_and_base.
+
+1000:           mov     \irqnr, #0
+                mov     \base, #io_p2v(0x80000000)      @ APB registers
+                ldr     \irqstat, [\base, #0x500]       @ PIC INTSR
+
+1001:           movs    \irqstat, \irqstat, lsr #1      @ Shift into carry
+                bcs     1008f                           @ Bit set; irq found
+                add     \irqnr, \irqnr, #1
+                bne     1001b                           @ Until no bits
+                b       1009f                           @ Nothing?  Hmm.
+1008:           movs    \irqstat, #1                    @ Force !Z
+
+1009:
+               .endm
+
+
+
+#elif defined (CONFIG_ARCH_LH7A400)
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_preamble, base, tmp
+                .endm
+
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                mov     \irqnr, #0
+                mov     \base, #io_p2v(0x80000000)      @ APB registers
+                ldr     \irqstat, [\base, #0x500]       @ PIC INTSR
+
+1001:           movs    \irqstat, \irqstat, lsr #1      @ Shift into carry
+                bcs     1008f                           @ Bit set; irq found
+                add     \irqnr, \irqnr, #1
+                bne     1001b                           @ Until no bits
+                b       1009f                           @ Nothing?  Hmm.
+1008:           movs    \irqstat, #1                    @ Force !Z
+1009:
+               .endm
+
+#elif defined(CONFIG_ARCH_LH7A404)
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_preamble, base, tmp
+                .endm
+
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                mov     \irqnr, #0                      @ VIC1 irq base
+                mov     \base, #io_p2v(0x80000000)      @ APB registers
+                add     \base, \base, #0x8000
+                ldr     \tmp, [\base, #0x0030]          @ VIC1_VECTADDR
+                tst     \tmp, #VA_VECTORED              @ Direct vectored
+                bne     1002f
+                tst     \tmp, #VA_VIC1DEFAULT           @ Default vectored VIC1
+                ldrne   \irqstat, [\base, #0]           @ VIC1_IRQSTATUS
+                bne     1001f
+                add     \base, \base, #(0xa000 - 0x8000)
+                ldr     \tmp, [\base, #0x0030]          @ VIC2_VECTADDR
+                tst     \tmp, #VA_VECTORED              @ Direct vectored
+                bne     1002f
+                ldr     \irqstat, [\base, #0]           @ VIC2_IRQSTATUS
+                mov     \irqnr, #32                     @ VIC2 irq base
+
+1001:           movs    \irqstat, \irqstat, lsr #1      @ Shift into carry
+                bcs     1008f                           @ Bit set; irq found
+                add     \irqnr, \irqnr, #1
+                bne     1001b                           @ Until no bits
+                b       1009f                           @ Nothing?  Hmm.
+1002:           and     \irqnr, \tmp, #0x3f             @ Mask for valid bits
+1008:           movs    \irqstat, #1                    @ Force !Z
+                str     \tmp, [\base, #0x0030]          @ Clear vector
+1009:
+               .endm
+#endif
+
+
diff --git a/arch/arm/mach-lh7a40x/include/mach/hardware.h b/arch/arm/mach-lh7a40x/include/mach/hardware.h
new file mode 100644
index 000000000000..48e827d2fa56
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/include/mach/hardware.h
@@ -0,0 +1,62 @@
+/* arch/arm/mach-lh7a40x/include/mach/hardware.h
+ *
+ *  Copyright (C) 2004 Coastal Environmental Systems
+ *
+ *  [ Substantially cribbed from arch/arm/mach-pxa/include/mach/hardware.h ]
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/sizes.h>          /* Added for the sake of amba-clcd driver */
+
+#define io_p2v(x) (0xf0000000 | (((x) & 0xfff00000) >> 4) | ((x) & 0x0000ffff))
+#define io_v2p(x) (             (((x) & 0x0fff0000) << 4) | ((x) & 0x0000ffff))
+
+#ifdef __ASSEMBLY__
+
+# define __REG(x)       io_p2v(x)
+# define __PREG(x)      io_v2p(x)
+
+#else
+
+# if 0
+#  define __REG(x)      (*((volatile u32 *)io_p2v(x)))
+# else
+/*
+ * This __REG() version gives the same results as the one above,  except
+ * that we are fooling gcc somehow so it generates far better and smaller
+ * assembly code for access to contigous registers.  It's a shame that gcc
+ * doesn't guess this by itself.
+ */
+#include <asm/types.h>
+typedef struct { volatile u32 offset[4096]; } __regbase;
+# define __REGP(x)      ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
+# define __REG(x)       __REGP(io_p2v(x))
+typedef struct { volatile u16 offset[4096]; } __regbase16;
+# define __REGP16(x)    ((__regbase16 *)((x)&~4095))->offset[((x)&4095)>>1]
+# define __REG16(x)     __REGP16(io_p2v(x))
+typedef struct { volatile u8 offset[4096]; } __regbase8;
+# define __REGP8(x)     ((__regbase8 *)((x)&~4095))->offset[(x)&4095]
+# define __REG8(x)      __REGP8(io_p2v(x))
+#endif
+
+/* Let's kick gcc's ass again... */
+# define __REG2(x,y)    \
+        ( __builtin_constant_p(y) ? (__REG((x) + (y))) \
+                                  : (*(volatile u32 *)((u32)&__REG(x) + (y))) )
+
+# define __PREG(x)      (io_v2p((u32)&(x)))
+
+#endif
+
+#define MASK_AND_SET(v,m,s)     (v) = ((v)&~(m))|(s)
+
+#include "registers.h"
+
+#endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-lh7a40x/include/mach/io.h b/arch/arm/mach-lh7a40x/include/mach/io.h
new file mode 100644
index 000000000000..031d26f9163c
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/include/mach/io.h
@@ -0,0 +1,22 @@
+/* arch/arm/mach-lh7a40x/include/mach/io.h
+ *
+ *  Copyright (C) 2004 Coastal Environmental Systems
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#include <mach/hardware.h>
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/* No ISA or PCI bus on this machine. */
+#define __io(a)                 ((void __iomem *)(a))
+#define __mem_pci(a)            (a)
+
+#endif /* __ASM_ARCH_IO_H */
diff --git a/arch/arm/mach-lh7a40x/include/mach/irqs.h b/arch/arm/mach-lh7a40x/include/mach/irqs.h
new file mode 100644
index 000000000000..0f9b83675935
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/include/mach/irqs.h
@@ -0,0 +1,200 @@
+/* arch/arm/mach-lh7a40x/include/mach/irqs.h
+ *
+ *  Copyright (C) 2004 Coastal Environmental Systems
+ *  Copyright (C) 2004 Logic Product Development
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  version 2 as published by the Free Software Foundation.
+ *
+ */
+
+/* It is to be seen whether or not we can build a kernel for more than
+ * one board.  For the time being, these macros assume that we cannot.
+ * Thus, it is OK to ifdef machine/board specific IRQ assignments.
+ */
+
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+
+#define FIQ_START       80
+
+#if defined (CONFIG_ARCH_LH7A400)
+
+  /* FIQs */
+
+# define IRQ_GPIO0FIQ   0       /* GPIO External FIQ Interrupt on F0 */
+# define IRQ_BLINT      1       /* Battery Low */
+# define IRQ_WEINT      2       /* Watchdog Timer, WDT overflow */
+# define IRQ_MCINT      3       /* Media Change, MEDCHG pin rising */
+
+  /* IRQs */
+
+# define IRQ_CSINT      4       /* Audio Codec (ACI) */
+# define IRQ_GPIO1INTR  5       /* GPIO External IRQ Interrupt on F1 */
+# define IRQ_GPIO2INTR  6       /* GPIO External IRQ Interrupt on F2 */
+# define IRQ_GPIO3INTR  7       /* GPIO External IRQ Interrupt on F3 */
+# define IRQ_T1UI       8       /* Timer 1 underflow */
+# define IRQ_T2UI       9       /* Timer 2 underflow */
+# define IRQ_RTCMI      10
+# define IRQ_TINTR      11      /* Clock State Controller 64 Hz tick (CSC) */
+# define IRQ_UART1INTR  12
+# define IRQ_UART2INTR  13
+# define IRQ_LCDINTR    14
+# define IRQ_SSIEOT     15      /* Synchronous Serial Interface (SSI) */
+# define IRQ_UART3INTR  16
+# define IRQ_SCIINTR    17      /* Smart Card Interface (SCI) */
+# define IRQ_AACINTR    18      /* Advanced Audio Codec (AAC) */
+# define IRQ_MMCINTR    19      /* Multimedia Card (MMC) */
+# define IRQ_USBINTR    20
+# define IRQ_DMAINTR    21
+# define IRQ_T3UI       22      /* Timer 3 underflow */
+# define IRQ_GPIO4INTR  23      /* GPIO External IRQ Interrupt on F4 */
+# define IRQ_GPIO5INTR  24      /* GPIO External IRQ Interrupt on F5 */
+# define IRQ_GPIO6INTR  25      /* GPIO External IRQ Interrupt on F6 */
+# define IRQ_GPIO7INTR  26      /* GPIO External IRQ Interrupt on F7 */
+# define IRQ_BMIINTR    27      /* Battery Monitor Interface (BMI) */
+
+# define NR_IRQ_CPU     28      /* IRQs directly recognized by CPU */
+
+        /* Given IRQ, return GPIO interrupt number 0-7 */
+# define IRQ_TO_GPIO(i)  ((i) \
+        - (((i) > IRQ_GPIO3INTR) ? IRQ_GPIO4INTR - IRQ_GPIO3INTR - 1 : 0)\
+        - (((i) > IRQ_GPIO0INTR) ? IRQ_GPIO1INTR - IRQ_GPIO0INTR - 1 : 0))
+
+#endif
+
+#if defined (CONFIG_ARCH_LH7A404)
+
+# define IRQ_BROWN      0       /* Brownout */
+# define IRQ_WDTINTR    1       /* Watchdog Timer */
+# define IRQ_COMMRX     2       /* ARM Comm Rx for Debug */
+# define IRQ_COMMTX     3       /* ARM Comm Tx for Debug */
+# define IRQ_T1UI       4       /* Timer 1 underflow */
+# define IRQ_T2UI       5       /* Timer 2 underflow */
+# define IRQ_CSINT      6       /* Codec Interrupt (shared by AAC on 404) */
+# define IRQ_DMAM2P0    7       /* -- DMA Memory to Peripheral */
+# define IRQ_DMAM2P1    8
+# define IRQ_DMAM2P2    9
+# define IRQ_DMAM2P3    10
+# define IRQ_DMAM2P4    11
+# define IRQ_DMAM2P5    12
+# define IRQ_DMAM2P6    13
+# define IRQ_DMAM2P7    14
+# define IRQ_DMAM2P8    15
+# define IRQ_DMAM2P9    16
+# define IRQ_DMAM2M0    17      /* -- DMA Memory to Memory */
+# define IRQ_DMAM2M1    18
+# define IRQ_GPIO0INTR  19      /* -- GPIOF Interrupt */
+# define IRQ_GPIO1INTR  20
+# define IRQ_GPIO2INTR  21
+# define IRQ_GPIO3INTR  22
+# define IRQ_SOFT_V1_23 23      /* -- Unassigned */
+# define IRQ_SOFT_V1_24 24
+# define IRQ_SOFT_V1_25 25
+# define IRQ_SOFT_V1_26 26
+# define IRQ_SOFT_V1_27 27
+# define IRQ_SOFT_V1_28 28
+# define IRQ_SOFT_V1_29 29
+# define IRQ_SOFT_V1_30 30
+# define IRQ_SOFT_V1_31 31
+
+# define IRQ_BLINT      32      /* Battery Low */
+# define IRQ_BMIINTR    33      /* Battery Monitor */
+# define IRQ_MCINTR     34      /* Media Change */
+# define IRQ_TINTR      35      /* 64Hz Tick */
+# define IRQ_WEINT      36      /* Watchdog Expired */
+# define IRQ_RTCMI      37      /* Real-time Clock Match */
+# define IRQ_UART1INTR  38      /* UART1 Interrupt (including error) */
+# define IRQ_UART1ERR   39      /* UART1 Error */
+# define IRQ_UART2INTR  40      /* UART2 Interrupt (including error) */
+# define IRQ_UART2ERR   41      /* UART2 Error */
+# define IRQ_UART3INTR  42      /* UART3 Interrupt (including error) */
+# define IRQ_UART3ERR   43      /* UART3 Error */
+# define IRQ_SCIINTR    44      /* Smart Card */
+# define IRQ_TSCINTR    45      /* Touchscreen */
+# define IRQ_KMIINTR    46      /* Keyboard/Mouse (PS/2) */
+# define IRQ_GPIO4INTR  47      /* -- GPIOF Interrupt */
+# define IRQ_GPIO5INTR  48
+# define IRQ_GPIO6INTR  49
+# define IRQ_GPIO7INTR  50
+# define IRQ_T3UI       51      /* Timer 3 underflow */
+# define IRQ_LCDINTR    52      /* LCD Controller */
+# define IRQ_SSPINTR    53      /* Synchronous Serial Port */
+# define IRQ_SDINTR     54      /* Secure Digital Port (MMC) */
+# define IRQ_USBINTR    55      /* USB Device Port */
+# define IRQ_USHINTR    56      /* USB Host Port */
+# define IRQ_SOFT_V2_25 57      /* -- Unassigned */
+# define IRQ_SOFT_V2_26 58
+# define IRQ_SOFT_V2_27 59
+# define IRQ_SOFT_V2_28 60
+# define IRQ_SOFT_V2_29 61
+# define IRQ_SOFT_V2_30 62
+# define IRQ_SOFT_V2_31 63
+
+# define NR_IRQ_CPU     64      /* IRQs directly recognized by CPU */
+
+        /* Given IRQ, return GPIO interrupt number 0-7 */
+# define IRQ_TO_GPIO(i)  ((i) \
+        - (((i) > IRQ_GPIO3INTR) ? IRQ_GPIO4INTR - IRQ_GPIO3INTR - 1 : 0)\
+        - IRQ_GPIO0INTR)
+
+                        /* Vector Address constants */
+# define VA_VECTORED    0x100   /* Set for vectored interrupt */
+# define VA_VIC1DEFAULT 0x200   /* Set as default VECTADDR for VIC1 */
+# define VA_VIC2DEFAULT 0x400   /* Set as default VECTADDR for VIC2 */
+
+#endif
+
+  /* IRQ aliases */
+
+#if !defined (IRQ_GPIO0INTR)
+# define IRQ_GPIO0INTR  IRQ_GPIO0FIQ
+#endif
+#define IRQ_TICK        IRQ_TINTR
+#define IRQ_PCC1_RDY    IRQ_GPIO6INTR   /* PCCard 1 ready */
+#define IRQ_PCC2_RDY    IRQ_GPIO7INTR   /* PCCard 2 ready */
+#define IRQ_USB         IRQ_USBINTR     /* USB device */
+
+#ifdef CONFIG_MACH_KEV7A400
+# define IRQ_TS         IRQ_GPIOFIQ     /* Touchscreen */
+# define IRQ_CPLD       IRQ_GPIO1INTR   /* CPLD cascade */
+# define IRQ_PCC1_CD    IRQ_GPIO_F2     /* PCCard 1 card detect */
+# define IRQ_PCC2_CD    IRQ_GPIO_F3     /* PCCard 2 card detect */
+#endif
+
+#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
+# define IRQ_CPLD_V28   IRQ_GPIO7INTR   /* CPLD cascade through GPIO_PF7 */
+# define IRQ_CPLD_V34   IRQ_GPIO3INTR   /* CPLD cascade through GPIO_PF3 */
+#endif
+
+  /* System specific IRQs */
+
+#define IRQ_BOARD_START NR_IRQ_CPU
+
+#ifdef CONFIG_MACH_KEV7A400
+# define IRQ_KEV7A400_CPLD      IRQ_BOARD_START
+# define NR_IRQ_BOARD           5
+# define IRQ_KEV7A400_MMC_CD    IRQ_KEV7A400_CPLD + 0   /* MMC Card Detect */
+# define IRQ_KEV7A400_RI2       IRQ_KEV7A400_CPLD + 1   /* Ring Indicator 2 */
+# define IRQ_KEV7A400_IDE_CF    IRQ_KEV7A400_CPLD + 2   /* Compact Flash (?) */
+# define IRQ_KEV7A400_ETH_INT   IRQ_KEV7A400_CPLD + 3   /* Ethernet chip */
+# define IRQ_KEV7A400_INT       IRQ_KEV7A400_CPLD + 4
+#endif
+
+#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
+# define IRQ_LPD7A40X_CPLD      IRQ_BOARD_START
+# define NR_IRQ_BOARD           2
+# define IRQ_LPD7A40X_ETH_INT   IRQ_LPD7A40X_CPLD + 0   /* Ethernet chip */
+# define IRQ_LPD7A400_TS        IRQ_LPD7A40X_CPLD + 1   /* Touch screen */
+#endif
+
+#if defined (CONFIG_MACH_LPD7A400)
+# define IRQ_TOUCH              IRQ_LPD7A400_TS
+#endif
+
+#define NR_IRQS         (NR_IRQ_CPU + NR_IRQ_BOARD)
+
+#endif
diff --git a/arch/arm/mach-lh7a40x/include/mach/memory.h b/arch/arm/mach-lh7a40x/include/mach/memory.h
new file mode 100644
index 000000000000..f7107b4c197a
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/include/mach/memory.h
@@ -0,0 +1,76 @@
+/* arch/arm/mach-lh7a40x/include/mach/memory.h
+ *
+ *  Copyright (C) 2004 Coastal Environmental Systems
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  version 2 as published by the Free Software Foundation.
+ *
+ *
+ *  Refer to <file:Documentation/arm/Sharp-LH/SDRAM> for more information.
+ *
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     UL(0xc0000000)
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+#define __virt_to_bus(x)         __virt_to_phys(x)
+#define __bus_to_virt(x)         __phys_to_virt(x)
+
+#ifdef CONFIG_DISCONTIGMEM
+
+/*
+ * Given a kernel address, find the home node of the underlying memory.
+ */
+
+# ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE
+#  define KVADDR_TO_NID(addr) \
+  (  ((((unsigned long) (addr) - PAGE_OFFSET) >> 24) &  1)\
+   | ((((unsigned long) (addr) - PAGE_OFFSET) >> 25) & ~1))
+# else  /* 2 banks per node */
+#  define KVADDR_TO_NID(addr) \
+      (((unsigned long) (addr) - PAGE_OFFSET) >> 26)
+# endif
+
+/*
+ * Given a page frame number, convert it to a node id.
+ */
+
+# ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE
+#  define PFN_TO_NID(pfn) \
+  (((((pfn) - PHYS_PFN_OFFSET) >> (24 - PAGE_SHIFT)) &  1)\
+ | ((((pfn) - PHYS_PFN_OFFSET) >> (25 - PAGE_SHIFT)) & ~1))
+# else  /* 2 banks per node */
+#  define PFN_TO_NID(pfn) \
+    (((pfn) - PHYS_PFN_OFFSET) >> (26 - PAGE_SHIFT))
+#endif
+
+/*
+ * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
+ * and returns the index corresponding to the appropriate page in the
+ * node's mem_map.
+ */
+
+# ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE
+#  define LOCAL_MAP_NR(addr) \
+       (((unsigned long)(addr) & 0x003fffff) >> PAGE_SHIFT)
+# else  /* 2 banks per node */
+#  define LOCAL_MAP_NR(addr) \
+       (((unsigned long)(addr) & 0x01ffffff) >> PAGE_SHIFT)
+# endif
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-lh7a40x/include/mach/registers.h b/arch/arm/mach-lh7a40x/include/mach/registers.h
new file mode 100644
index 000000000000..ea44396383a7
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/include/mach/registers.h
@@ -0,0 +1,224 @@
+/* arch/arm/mach-lh7a40x/include/mach/registers.h
+ *
+ *  Copyright (C) 2004 Coastal Environmental Systems
+ *  Copyright (C) 2004 Logic Product Development
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#include <mach/constants.h>
+
+#ifndef __ASM_ARCH_REGISTERS_H
+#define __ASM_ARCH_REGISTERS_H
+
+
+        /* Physical register base addresses */
+
+#define AC97C_PHYS      (0x80000000)    /* AC97 Controller */
+#define MMC_PHYS        (0x80000100)    /* Multimedia Card Controller */
+#define USB_PHYS        (0x80000200)    /* USB Client */
+#define SCI_PHYS        (0x80000300)    /* Secure Card Interface */
+#define CSC_PHYS        (0x80000400)    /* Clock/State Controller  */
+#define INTC_PHYS       (0x80000500)    /* Interrupt Controller */
+#define UART1_PHYS      (0x80000600)    /* UART1 Controller */
+#define SIR_PHYS        (0x80000600)    /* IR Controller, same are UART1 */
+#define UART2_PHYS      (0x80000700)    /* UART2 Controller */
+#define UART3_PHYS      (0x80000800)    /* UART3 Controller */
+#define DCDC_PHYS       (0x80000900)    /* DC to DC Controller */
+#define ACI_PHYS        (0x80000a00)    /* Audio Codec Interface */
+#define SSP_PHYS        (0x80000b00)    /* Synchronous ... */
+#define TIMER_PHYS      (0x80000c00)    /* Timer Controller */
+#define RTC_PHYS        (0x80000d00)    /* Real-time Clock */
+#define GPIO_PHYS       (0x80000e00)    /* General Purpose IO */
+#define BMI_PHYS        (0x80000f00)    /* Battery Monitor Interface */
+#define HRTFTC_PHYS     (0x80001000)    /* High-res TFT Controller (LH7A400) */
+#define ALI_PHYS        (0x80001000)    /* Advanced LCD Interface (LH7A404) */
+#define WDT_PHYS        (0x80001400)    /* Watchdog Timer */
+#define SMC_PHYS        (0x80002000)    /* Static Memory Controller */
+#define SDRC_PHYS       (0x80002400)    /* SDRAM Controller */
+#define DMAC_PHYS       (0x80002800)    /* DMA Controller */
+#define CLCDC_PHYS      (0x80003000)    /* Color LCD Controller */
+
+        /* Physical registers of the LH7A404 */
+
+#define ADC_PHYS        (0x80001300)    /* A/D & Touchscreen Controller */
+#define VIC1_PHYS       (0x80008000)    /* Vectored Interrupt Controller 1 */
+#define USBH_PHYS       (0x80009000)    /* USB OHCI host controller */
+#define VIC2_PHYS       (0x8000a000)    /* Vectored Interrupt Controller 2 */
+
+/*#define KBD_PHYS      (0x80000e00) */
+/*#define LCDICP_PHYS   (0x80001000) */
+
+
+        /* Clock/State Controller register */
+
+#define CSC_PWRSR       __REG(CSC_PHYS + 0x00) /* Reset register & ID */
+#define CSC_PWRCNT      __REG(CSC_PHYS + 0x04) /* Power control */
+#define CSC_CLKSET      __REG(CSC_PHYS + 0x20) /* Clock speed control */
+#define CSC_USBDRESET   __REG(CSC_PHYS + 0x4c) /* USB Device resets */
+
+#define CSC_PWRCNT_USBH_EN      (1<<28) /* USB Host power enable */
+#define CSC_PWRCNT_DMAC_M2M1_EN (1<<27)
+#define CSC_PWRCNT_DMAC_M2M0_EN (1<<26)
+#define CSC_PWRCNT_DMAC_M2P8_EN (1<<25)
+#define CSC_PWRCNT_DMAC_M2P9_EN (1<<24)
+#define CSC_PWRCNT_DMAC_M2P6_EN (1<<23)
+#define CSC_PWRCNT_DMAC_M2P7_EN (1<<22)
+#define CSC_PWRCNT_DMAC_M2P4_EN (1<<21)
+#define CSC_PWRCNT_DMAC_M2P5_EN (1<<20)
+#define CSC_PWRCNT_DMAC_M2P2_EN (1<<19)
+#define CSC_PWRCNT_DMAC_M2P3_EN (1<<18)
+#define CSC_PWRCNT_DMAC_M2P0_EN (1<<17)
+#define CSC_PWRCNT_DMAC_M2P1_EN (1<<16)
+
+#define CSC_PWRSR_CHIPMAN_SHIFT (24)
+#define CSC_PWRSR_CHIPMAN_MASK  (0xff)
+#define CSC_PWRSR_CHIPID_SHIFT  (16)
+#define CSC_PWRSR_CHIPID_MASK   (0xff)
+
+#define CSC_USBDRESET_APBRESETREG       (1<<1)
+#define CSC_USBDRESET_IORESETREG        (1<<0)
+
+        /* Interrupt Controller registers */
+
+#define INTC_INTSR      __REG(INTC_PHYS + 0x00) /* Status */
+#define INTC_INTRSR     __REG(INTC_PHYS + 0x04) /* Raw Status */
+#define INTC_INTENS     __REG(INTC_PHYS + 0x08) /* Enable Set */
+#define INTC_INTENC     __REG(INTC_PHYS + 0x0c) /* Enable Clear */
+
+
+        /* Vectored Interrupted Controller registers */
+
+#define VIC1_IRQSTATUS  __REG(VIC1_PHYS + 0x00)
+#define VIC1_FIQSTATUS  __REG(VIC1_PHYS + 0x04)
+#define VIC1_RAWINTR    __REG(VIC1_PHYS + 0x08)
+#define VIC1_INTSEL     __REG(VIC1_PHYS + 0x0c)
+#define VIC1_INTEN      __REG(VIC1_PHYS + 0x10)
+#define VIC1_INTENCLR   __REG(VIC1_PHYS + 0x14)
+#define VIC1_SOFTINT    __REG(VIC1_PHYS + 0x18)
+#define VIC1_SOFTINTCLR __REG(VIC1_PHYS + 0x1c)
+#define VIC1_PROTECT    __REG(VIC1_PHYS + 0x20)
+#define VIC1_VECTADDR   __REG(VIC1_PHYS + 0x30)
+#define VIC1_NVADDR     __REG(VIC1_PHYS + 0x34)
+#define VIC1_VAD0       __REG(VIC1_PHYS + 0x100)
+#define VIC1_VECTCNTL0  __REG(VIC1_PHYS + 0x200)
+#define VIC2_IRQSTATUS  __REG(VIC2_PHYS + 0x00)
+#define VIC2_FIQSTATUS  __REG(VIC2_PHYS + 0x04)
+#define VIC2_RAWINTR    __REG(VIC2_PHYS + 0x08)
+#define VIC2_INTSEL     __REG(VIC2_PHYS + 0x0c)
+#define VIC2_INTEN      __REG(VIC2_PHYS + 0x10)
+#define VIC2_INTENCLR   __REG(VIC2_PHYS + 0x14)
+#define VIC2_SOFTINT    __REG(VIC2_PHYS + 0x18)
+#define VIC2_SOFTINTCLR __REG(VIC2_PHYS + 0x1c)
+#define VIC2_PROTECT    __REG(VIC2_PHYS + 0x20)
+#define VIC2_VECTADDR   __REG(VIC2_PHYS + 0x30)
+#define VIC2_NVADDR     __REG(VIC2_PHYS + 0x34)
+#define VIC2_VAD0       __REG(VIC2_PHYS + 0x100)
+#define VIC2_VECTCNTL0  __REG(VIC2_PHYS + 0x200)
+
+#define VIC_CNTL_ENABLE (0x20)
+
+        /* USB Host registers (Open HCI compatible) */
+
+#define USBH_CMDSTATUS  __REG(USBH_PHYS + 0x08)
+
+
+        /* GPIO registers */
+
+#define GPIO_INTTYPE1   __REG(GPIO_PHYS + 0x4c) /* Interrupt Type 1 (Edge) */
+#define GPIO_INTTYPE2   __REG(GPIO_PHYS + 0x50) /* Interrupt Type 2 */
+#define GPIO_GPIOFEOI   __REG(GPIO_PHYS + 0x54) /* GPIO End-of-Interrupt */
+#define GPIO_GPIOINTEN  __REG(GPIO_PHYS + 0x58) /* GPIO Interrupt Enable */
+#define GPIO_INTSTATUS  __REG(GPIO_PHYS + 0x5c) /* GPIO Interrupt Status */
+#define GPIO_PINMUX     __REG(GPIO_PHYS + 0x2c)
+#define GPIO_PADD       __REG(GPIO_PHYS + 0x10)
+#define GPIO_PAD        __REG(GPIO_PHYS + 0x00)
+#define GPIO_PCD        __REG(GPIO_PHYS + 0x08)
+#define GPIO_PCDD       __REG(GPIO_PHYS + 0x18)
+#define GPIO_PEDD       __REG(GPIO_PHYS + 0x24)
+#define GPIO_PED        __REG(GPIO_PHYS + 0x20)
+
+
+        /* Static Memory Controller registers */
+
+#define SMC_BCR0        __REG(SMC_PHYS + 0x00)  /* Bank 0 Configuration */
+#define SMC_BCR1        __REG(SMC_PHYS + 0x04)  /* Bank 1 Configuration */
+#define SMC_BCR2        __REG(SMC_PHYS + 0x08)  /* Bank 2 Configuration */
+#define SMC_BCR3        __REG(SMC_PHYS + 0x0C)  /* Bank 3 Configuration */
+#define SMC_BCR6        __REG(SMC_PHYS + 0x18)  /* Bank 6 Configuration */
+#define SMC_BCR7        __REG(SMC_PHYS + 0x1c)  /* Bank 7 Configuration */
+
+
+#ifdef CONFIG_MACH_KEV7A400
+# define CPLD_RD_OPT_DIP_SW     __REG16(CPLD_PHYS + 0x00) /* Read Option SW */
+# define CPLD_WR_IO_BRD_CTL     __REG16(CPLD_PHYS + 0x00) /* Write Control */
+# define CPLD_RD_PB_KEYS        __REG16(CPLD_PHYS + 0x02) /* Read Btn Keys */
+# define CPLD_LATCHED_INTS      __REG16(CPLD_PHYS + 0x04) /* Read INTR stat. */
+# define CPLD_CL_INT            __REG16(CPLD_PHYS + 0x04) /* Clear INTR stat */
+# define CPLD_BOOT_MMC_STATUS   __REG16(CPLD_PHYS + 0x06) /* R/O */
+# define CPLD_RD_KPD_ROW_SENSE  __REG16(CPLD_PHYS + 0x08)
+# define CPLD_WR_PB_INT_MASK    __REG16(CPLD_PHYS + 0x08)
+# define CPLD_RD_BRD_DISP_SW    __REG16(CPLD_PHYS + 0x0a)
+# define CPLD_WR_EXT_INT_MASK   __REG16(CPLD_PHYS + 0x0a)
+# define CPLD_LCD_PWR_CNTL      __REG16(CPLD_PHYS + 0x0c)
+# define CPLD_SEVEN_SEG         __REG16(CPLD_PHYS + 0x0e) /* 7 seg. LED mask */
+
+#endif
+
+#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
+
+# define CPLD_CONTROL           __REG16(CPLD02_PHYS)
+# define CPLD_SPI_DATA          __REG16(CPLD06_PHYS)
+# define CPLD_SPI_CONTROL       __REG16(CPLD08_PHYS)
+# define CPLD_SPI_EEPROM        __REG16(CPLD0A_PHYS)
+# define CPLD_INTERRUPTS        __REG16(CPLD0C_PHYS) /* IRQ mask/status */
+# define CPLD_BOOT_MODE         __REG16(CPLD0E_PHYS)
+# define CPLD_FLASH             __REG16(CPLD10_PHYS)
+# define CPLD_POWER_MGMT        __REG16(CPLD12_PHYS)
+# define CPLD_REVISION          __REG16(CPLD14_PHYS)
+# define CPLD_GPIO_EXT          __REG16(CPLD16_PHYS)
+# define CPLD_GPIO_DATA         __REG16(CPLD18_PHYS)
+# define CPLD_GPIO_DIR          __REG16(CPLD1A_PHYS)
+
+#endif
+
+        /* Timer registers */
+
+#define TIMER_LOAD1     __REG(TIMER_PHYS + 0x00) /* Timer 1 initial value */
+#define TIMER_VALUE1    __REG(TIMER_PHYS + 0x04) /* Timer 1 current value */
+#define TIMER_CONTROL1  __REG(TIMER_PHYS + 0x08) /* Timer 1 control word */
+#define TIMER_EOI1      __REG(TIMER_PHYS + 0x0c) /* Timer 1 interrupt clear */
+
+#define TIMER_LOAD2     __REG(TIMER_PHYS + 0x20) /* Timer 2 initial value */
+#define TIMER_VALUE2    __REG(TIMER_PHYS + 0x24) /* Timer 2 current value */
+#define TIMER_CONTROL2  __REG(TIMER_PHYS + 0x28) /* Timer 2 control word */
+#define TIMER_EOI2      __REG(TIMER_PHYS + 0x2c) /* Timer 2 interrupt clear */
+
+#define TIMER_BUZZCON   __REG(TIMER_PHYS + 0x40) /* Buzzer configuration */
+
+#define TIMER_LOAD3     __REG(TIMER_PHYS + 0x80) /* Timer 3 initial value */
+#define TIMER_VALUE3    __REG(TIMER_PHYS + 0x84) /* Timer 3 current value */
+#define TIMER_CONTROL3  __REG(TIMER_PHYS + 0x88) /* Timer 3 control word */
+#define TIMER_EOI3      __REG(TIMER_PHYS + 0x8c) /* Timer 3 interrupt clear */
+
+#define TIMER_C_ENABLE          (1<<7)
+#define TIMER_C_PERIODIC        (1<<6)
+#define TIMER_C_FREERUNNING     (0)
+#define TIMER_C_2KHZ            (0x00)          /* 1.986 kHz */
+#define TIMER_C_508KHZ          (0x08)
+
+        /* GPIO registers */
+
+#define GPIO_PFDD               __REG(GPIO_PHYS + 0x34) /* PF direction */
+#define GPIO_INTTYPE1           __REG(GPIO_PHYS + 0x4c) /* IRQ edge or lvl  */
+#define GPIO_INTTYPE2           __REG(GPIO_PHYS + 0x50) /* IRQ activ hi/lo */
+#define GPIO_GPIOFEOI           __REG(GPIO_PHYS + 0x54) /* GPIOF end of IRQ */
+#define GPIO_GPIOFINTEN         __REG(GPIO_PHYS + 0x58) /* GPIOF IRQ enable */
+#define GPIO_INTSTATUS          __REG(GPIO_PHYS + 0x5c) /* GPIOF IRQ latch */
+#define GPIO_RAWINTSTATUS       __REG(GPIO_PHYS + 0x60) /* GPIOF IRQ raw */
+
+
+#endif  /* _ASM_ARCH_REGISTERS_H */
diff --git a/include/asm-arm/arch-lh7a40x/ssp.h b/arch/arm/mach-lh7a40x/include/mach/ssp.h
index 132b1c4d5ce6..132b1c4d5ce6 100644
--- a/include/asm-arm/arch-lh7a40x/ssp.h
+++ b/arch/arm/mach-lh7a40x/include/mach/ssp.h
diff --git a/arch/arm/mach-lh7a40x/include/mach/system.h b/arch/arm/mach-lh7a40x/include/mach/system.h
new file mode 100644
index 000000000000..fa46bb1ef07b
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/include/mach/system.h
@@ -0,0 +1,19 @@
+/* arch/arm/mach-lh7a40x/include/mach/system.h
+ *
+ *  Copyright (C) 2004 Coastal Environmental Systems
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  version 2 as published by the Free Software Foundation.
+ *
+ */
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle ();
+}
+
+static inline void arch_reset(char mode)
+{
+        cpu_reset (0);
+}
diff --git a/arch/arm/mach-lh7a40x/include/mach/timex.h b/arch/arm/mach-lh7a40x/include/mach/timex.h
new file mode 100644
index 000000000000..08028cef1b3b
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/include/mach/timex.h
@@ -0,0 +1,17 @@
+/* arch/arm/mach-lh7a40x/include/mach/timex.h
+ *
+ *  Copyright (C) 2004 Coastal Environmental Systems
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#include <mach/constants.h>
+
+#define CLOCK_TICK_RATE         (PLL_CLOCK/6/16)
+
+/*
+#define CLOCK_TICK_RATE         3686400
+*/
diff --git a/arch/arm/mach-lh7a40x/include/mach/uncompress.h b/arch/arm/mach-lh7a40x/include/mach/uncompress.h
new file mode 100644
index 000000000000..55b80d479eb4
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/include/mach/uncompress.h
@@ -0,0 +1,38 @@
+/* arch/arm/mach-lh7a40x/include/mach/uncompress.h
+ *
+ *  Copyright (C) 2004 Coastal Environmental Systems
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#include <mach/registers.h>
+
+#ifndef UART_R_DATA
+# define UART_R_DATA    (0x00)
+#endif
+#ifndef UART_R_STATUS
+# define UART_R_STATUS  (0x10)
+#endif
+#define nTxRdy          (0x20)  /* Not TxReady (literally Tx FIFO full) */
+
+        /* Access UART with physical addresses before MMU is setup */
+#define UART_STATUS (*(volatile unsigned long*) (UART2_PHYS + UART_R_STATUS))
+#define UART_DATA   (*(volatile unsigned long*) (UART2_PHYS + UART_R_DATA))
+
+static inline void putc(int ch)
+{
+        while (UART_STATUS & nTxRdy)
+                barrier();
+        UART_DATA = ch;
+}
+
+static inline void flush(void)
+{
+}
+
+        /* NULL functions; we don't presently need them */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-lh7a40x/include/mach/vmalloc.h b/arch/arm/mach-lh7a40x/include/mach/vmalloc.h
new file mode 100644
index 000000000000..3fbd49490bb9
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/include/mach/vmalloc.h
@@ -0,0 +1,10 @@
+/* arch/arm/mach-lh7a40x/include/mach/vmalloc.h
+ *
+ *  Copyright (C) 2004 Coastal Environmental Systems
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  version 2 as published by the Free Software Foundation.
+ *
+ */
+#define VMALLOC_END       (0xe8000000)
diff --git a/arch/arm/mach-lh7a40x/irq-lh7a400.c b/arch/arm/mach-lh7a40x/irq-lh7a400.c
index 0e5a805036db..1ad3afcf6b3d 100644
--- a/arch/arm/mach-lh7a40x/irq-lh7a400.c
+++ b/arch/arm/mach-lh7a40x/irq-lh7a400.c
@@ -12,10 +12,10 @@
 #include <linux/module.h>
 #include <linux/interrupt.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
-#include <asm/arch/irqs.h>
+#include <mach/irqs.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-lh7a40x/irq-lh7a404.c b/arch/arm/mach-lh7a40x/irq-lh7a404.c
index f3293bfac8c6..12b045b688c6 100644
--- a/arch/arm/mach-lh7a40x/irq-lh7a404.c
+++ b/arch/arm/mach-lh7a40x/irq-lh7a404.c
@@ -12,10 +12,10 @@
 #include <linux/module.h>
 #include <linux/interrupt.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
-#include <asm/arch/irqs.h>
+#include <mach/irqs.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-lh7a40x/irq-lpd7a40x.c b/arch/arm/mach-lh7a40x/irq-lpd7a40x.c
index 41bf9f817b91..0d5063ebda10 100644
--- a/arch/arm/mach-lh7a40x/irq-lpd7a40x.c
+++ b/arch/arm/mach-lh7a40x/irq-lpd7a40x.c
@@ -13,10 +13,10 @@
 #include <linux/module.h>
 #include <linux/interrupt.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
-#include <asm/arch/irqs.h>
+#include <mach/irqs.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-lh7a40x/ssp-cpld.c b/arch/arm/mach-lh7a40x/ssp-cpld.c
index 4cd31bb8a8b8..51fbef9601b9 100644
--- a/arch/arm/mach-lh7a40x/ssp-cpld.c
+++ b/arch/arm/mach-lh7a40x/ssp-cpld.c
@@ -46,9 +46,9 @@
 
 #include <asm/io.h>
 #include <asm/irq.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
-#include <asm/arch/ssp.h>
+#include <mach/ssp.h>
 
 //#define TALK
 
diff --git a/arch/arm/mach-lh7a40x/time.c b/arch/arm/mach-lh7a40x/time.c
index 1c7e469e3528..7fe9e06cf662 100644
--- a/arch/arm/mach-lh7a40x/time.c
+++ b/arch/arm/mach-lh7a40x/time.c
@@ -14,7 +14,7 @@
 #include <linux/irq.h>
 #include <linux/time.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/leds.h>
diff --git a/arch/arm/mach-loki/addr-map.c b/arch/arm/mach-loki/addr-map.c
index 3b6319d4c1ce..70ca56bb6f33 100644
--- a/arch/arm/mach-loki/addr-map.c
+++ b/arch/arm/mach-loki/addr-map.c
@@ -11,7 +11,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/mbus.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include "common.h"
 
diff --git a/arch/arm/mach-loki/common.c b/arch/arm/mach-loki/common.c
index 410f50399dd3..e20cdbca1ebe 100644
--- a/arch/arm/mach-loki/common.c
+++ b/arch/arm/mach-loki/common.c
@@ -18,7 +18,7 @@
 #include <asm/timex.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <asm/arch/loki.h>
+#include <mach/loki.h>
 #include <asm/plat-orion/orion_nand.h>
 #include <asm/plat-orion/time.h>
 #include "common.h"
diff --git a/arch/arm/mach-loki/include/mach/debug-macro.S b/arch/arm/mach-loki/include/mach/debug-macro.S
new file mode 100644
index 000000000000..a8c20bd2f951
--- /dev/null
+++ b/arch/arm/mach-loki/include/mach/debug-macro.S
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/mach-loki/include/mach/debug-macro.S
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <mach/loki.h>
+
+        .macro  addruart,rx
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1                                 @ MMU enabled?
+        ldreq   \rx, =LOKI_REGS_PHYS_BASE
+        ldrne   \rx, =LOKI_REGS_VIRT_BASE
+        orr     \rx, \rx, #0x00012000
+        .endm
+
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-loki/dma.h b/arch/arm/mach-loki/include/mach/dma.h
index 40a8c178f10d..40a8c178f10d 100644
--- a/include/asm-arm/arch-loki/dma.h
+++ b/arch/arm/mach-loki/include/mach/dma.h
diff --git a/arch/arm/mach-loki/include/mach/entry-macro.S b/arch/arm/mach-loki/include/mach/entry-macro.S
new file mode 100644
index 000000000000..332af38ec13c
--- /dev/null
+++ b/arch/arm/mach-loki/include/mach/entry-macro.S
@@ -0,0 +1,30 @@
+/*
+ * arch/arm/mach-loki/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for Marvell Loki (88RC8480) platforms
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <mach/loki.h>
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =IRQ_VIRT_BASE
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        ldr     \irqstat, [\base, #IRQ_CAUSE_OFF]
+        ldr     \tmp, [\base, #IRQ_MASK_OFF]
+        mov     \irqnr, #0
+        ands    \irqstat, \irqstat, \tmp
+        clzne   \irqnr, \irqstat
+        rsbne   \irqnr, \irqnr, #31
+        .endm
diff --git a/arch/arm/mach-loki/include/mach/hardware.h b/arch/arm/mach-loki/include/mach/hardware.h
new file mode 100644
index 000000000000..d7bfc8f17729
--- /dev/null
+++ b/arch/arm/mach-loki/include/mach/hardware.h
@@ -0,0 +1,15 @@
+/*
+ * arch/arm/mach-loki/include/mach/hardware.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include "loki.h"
+
+
+#endif
diff --git a/arch/arm/mach-loki/include/mach/io.h b/arch/arm/mach-loki/include/mach/io.h
new file mode 100644
index 000000000000..a373cd582c84
--- /dev/null
+++ b/arch/arm/mach-loki/include/mach/io.h
@@ -0,0 +1,26 @@
+/*
+ * arch/arm/mach-loki/include/mach/io.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#include "loki.h"
+
+#define IO_SPACE_LIMIT          0xffffffff
+
+static inline void __iomem *__io(unsigned long addr)
+{
+        return (void __iomem *)((addr - LOKI_PCIE0_IO_PHYS_BASE)
+                                        + LOKI_PCIE0_IO_VIRT_BASE);
+}
+
+#define __io(a)                 __io(a)
+#define __mem_pci(a)            (a)
+
+
+#endif
diff --git a/arch/arm/mach-loki/include/mach/irqs.h b/arch/arm/mach-loki/include/mach/irqs.h
new file mode 100644
index 000000000000..9fbd3326867b
--- /dev/null
+++ b/arch/arm/mach-loki/include/mach/irqs.h
@@ -0,0 +1,58 @@
+/*
+ * arch/arm/mach-loki/include/mach/irqs.h
+ *
+ * IRQ definitions for Marvell Loki (88RC8480) SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#include "loki.h"       /* need GPIO_MAX */
+
+/*
+ * Interrupt Controller
+ */
+#define IRQ_LOKI_PCIE_A_CPU_DRBL        0
+#define IRQ_LOKI_CPU_PCIE_A_DRBL        1
+#define IRQ_LOKI_PCIE_B_CPU_DRBL        2
+#define IRQ_LOKI_CPU_PCIE_B_DRBL        3
+#define IRQ_LOKI_COM_A_ERR              6
+#define IRQ_LOKI_COM_A_IN               7
+#define IRQ_LOKI_COM_A_OUT              8
+#define IRQ_LOKI_COM_B_ERR              9
+#define IRQ_LOKI_COM_B_IN               10
+#define IRQ_LOKI_COM_B_OUT              11
+#define IRQ_LOKI_DMA_A                  12
+#define IRQ_LOKI_DMA_B                  13
+#define IRQ_LOKI_SAS_A                  14
+#define IRQ_LOKI_SAS_B                  15
+#define IRQ_LOKI_DDR                    16
+#define IRQ_LOKI_XOR                    17
+#define IRQ_LOKI_BRIDGE                 18
+#define IRQ_LOKI_PCIE_A_ERR             20
+#define IRQ_LOKI_PCIE_A_INT             21
+#define IRQ_LOKI_PCIE_B_ERR             22
+#define IRQ_LOKI_PCIE_B_INT             23
+#define IRQ_LOKI_GBE_A_INT              24
+#define IRQ_LOKI_GBE_B_INT              25
+#define IRQ_LOKI_DEV_ERR                26
+#define IRQ_LOKI_UART0                  27
+#define IRQ_LOKI_UART1                  28
+#define IRQ_LOKI_TWSI                   29
+#define IRQ_LOKI_GPIO_23_0              30
+#define IRQ_LOKI_GPIO_25_24             31
+
+/*
+ * Loki General Purpose Pins
+ */
+#define IRQ_LOKI_GPIO_START     32
+#define NR_GPIO_IRQS            GPIO_MAX
+
+#define NR_IRQS                 (IRQ_LOKI_GPIO_START + NR_GPIO_IRQS)
+
+
+#endif
diff --git a/arch/arm/mach-loki/include/mach/loki.h b/arch/arm/mach-loki/include/mach/loki.h
new file mode 100644
index 000000000000..c00af6ba5578
--- /dev/null
+++ b/arch/arm/mach-loki/include/mach/loki.h
@@ -0,0 +1,97 @@
+/*
+ * arch/arm/mach-loki/include/mach/loki.h
+ *
+ * Generic definitions for Marvell Loki (88RC8480) SoC flavors
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_LOKI_H
+#define __ASM_ARCH_LOKI_H
+
+/*
+ * Marvell Loki (88RC8480) address maps.
+ *
+ * phys
+ * d0000000     on-chip peripheral registers
+ * e0000000     PCIe 0 Memory space
+ * e8000000     PCIe 1 Memory space
+ * f0000000     PCIe 0 I/O space
+ * f0100000     PCIe 1 I/O space
+ *
+ * virt         phys            size
+ * fed00000     d0000000        1M      on-chip peripheral registers
+ * fee00000     f0000000        64K     PCIe 0 I/O space
+ * fef00000     f0100000        64K     PCIe 1 I/O space
+ */
+
+#define LOKI_REGS_PHYS_BASE             0xd0000000
+#define LOKI_REGS_VIRT_BASE             0xfed00000
+#define LOKI_REGS_SIZE                  SZ_1M
+
+#define LOKI_PCIE0_IO_PHYS_BASE         0xf0000000
+#define LOKI_PCIE0_IO_VIRT_BASE         0xfee00000
+#define LOKI_PCIE0_IO_BUS_BASE          0x00000000
+#define LOKI_PCIE0_IO_SIZE              SZ_64K
+
+#define LOKI_PCIE1_IO_PHYS_BASE         0xf0100000
+#define LOKI_PCIE1_IO_VIRT_BASE         0xfef00000
+#define LOKI_PCIE1_IO_BUS_BASE          0x00000000
+#define LOKI_PCIE1_IO_SIZE              SZ_64K
+
+#define LOKI_PCIE0_MEM_PHYS_BASE        0xe0000000
+#define LOKI_PCIE0_MEM_SIZE             SZ_128M
+
+#define LOKI_PCIE1_MEM_PHYS_BASE        0xe8000000
+#define LOKI_PCIE1_MEM_SIZE             SZ_128M
+
+/*
+ * Register Map
+ */
+#define DEV_BUS_PHYS_BASE       (LOKI_REGS_PHYS_BASE | 0x10000)
+#define DEV_BUS_VIRT_BASE       (LOKI_REGS_VIRT_BASE | 0x10000)
+#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2000)
+#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2000)
+#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2100)
+#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2100)
+
+#define BRIDGE_VIRT_BASE        (LOKI_REGS_VIRT_BASE | 0x20000)
+#define  BRIDGE_REG(x)          (BRIDGE_VIRT_BASE | (x))
+#define  RSTOUTn_MASK           (BRIDGE_VIRT_BASE | 0x0108)
+#define   SOFT_RESET_OUT_EN     0x00000004
+#define  SYSTEM_SOFT_RESET      (BRIDGE_VIRT_BASE | 0x010c)
+#define   SOFT_RESET            0x00000001
+#define  BRIDGE_CAUSE           (BRIDGE_VIRT_BASE | 0x0110)
+#define  BRIDGE_MASK            (BRIDGE_VIRT_BASE | 0x0114)
+#define   BRIDGE_INT_TIMER0     0x0002
+#define   BRIDGE_INT_TIMER1     0x0004
+#define   BRIDGE_INT_TIMER1_CLR 0x0004
+#define  IRQ_VIRT_BASE          (BRIDGE_VIRT_BASE | 0x0200)
+#define   IRQ_CAUSE_OFF         0x0000
+#define   IRQ_MASK_OFF          0x0004
+#define  TIMER_VIRT_BASE        (BRIDGE_VIRT_BASE | 0x0300)
+
+#define PCIE0_VIRT_BASE         (LOKI_REGS_VIRT_BASE | 0x30000)
+
+#define PCIE1_VIRT_BASE         (LOKI_REGS_VIRT_BASE | 0x40000)
+
+#define SAS0_PHYS_BASE          (LOKI_REGS_PHYS_BASE | 0x80000)
+
+#define SAS1_PHYS_BASE          (LOKI_REGS_PHYS_BASE | 0x90000)
+
+#define GE0_PHYS_BASE           (LOKI_REGS_PHYS_BASE | 0xa0000)
+#define GE0_VIRT_BASE           (LOKI_REGS_VIRT_BASE | 0xa0000)
+
+#define GE1_PHYS_BASE           (LOKI_REGS_PHYS_BASE | 0xb0000)
+#define GE1_VIRT_BASE           (LOKI_REGS_VIRT_BASE | 0xb0000)
+
+#define DDR_VIRT_BASE           (LOKI_REGS_VIRT_BASE | 0xf0000)
+#define DDR_REG(x)              (DDR_VIRT_BASE | (x))
+
+
+#define GPIO_MAX                8
+
+
+#endif
diff --git a/arch/arm/mach-loki/include/mach/memory.h b/arch/arm/mach-loki/include/mach/memory.h
new file mode 100644
index 000000000000..a39533ab489d
--- /dev/null
+++ b/arch/arm/mach-loki/include/mach/memory.h
@@ -0,0 +1,14 @@
+/*
+ * arch/arm/mach-loki/include/mach/memory.h
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#define PHYS_OFFSET             UL(0x00000000)
+
+#define __virt_to_bus(x)        __virt_to_phys(x)
+#define __bus_to_virt(x)        __phys_to_virt(x)
+
+
+#endif
diff --git a/arch/arm/mach-loki/include/mach/system.h b/arch/arm/mach-loki/include/mach/system.h
new file mode 100644
index 000000000000..8db1147d4ec5
--- /dev/null
+++ b/arch/arm/mach-loki/include/mach/system.h
@@ -0,0 +1,37 @@
+/*
+ * arch/arm/mach-loki/include/mach/system.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <mach/hardware.h>
+#include <mach/loki.h>
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        /*
+         * Enable soft reset to assert RSTOUTn.
+         */
+        writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
+
+        /*
+         * Assert soft reset.
+         */
+        writel(SOFT_RESET, SYSTEM_SOFT_RESET);
+
+        while (1)
+                ;
+}
+
+
+#endif
diff --git a/arch/arm/mach-loki/include/mach/timex.h b/arch/arm/mach-loki/include/mach/timex.h
new file mode 100644
index 000000000000..9df210915297
--- /dev/null
+++ b/arch/arm/mach-loki/include/mach/timex.h
@@ -0,0 +1,11 @@
+/*
+ * arch/arm/mach-loki/include/mach/timex.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#define CLOCK_TICK_RATE         (100 * HZ)
+
+#define LOKI_TCLK               180000000
diff --git a/arch/arm/mach-loki/include/mach/uncompress.h b/arch/arm/mach-loki/include/mach/uncompress.h
new file mode 100644
index 000000000000..90b2a7e65da3
--- /dev/null
+++ b/arch/arm/mach-loki/include/mach/uncompress.h
@@ -0,0 +1,47 @@
+/*
+ * arch/arm/mach-loki/include/mach/uncompress.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/serial_reg.h>
+#include <mach/loki.h>
+
+#define SERIAL_BASE     ((unsigned char *)UART0_PHYS_BASE)
+
+static void putc(const char c)
+{
+        unsigned char *base = SERIAL_BASE;
+        int i;
+
+        for (i = 0; i < 0x1000; i++) {
+                if (base[UART_LSR << 2] & UART_LSR_THRE)
+                        break;
+                barrier();
+        }
+
+        base[UART_TX << 2] = c;
+}
+
+static void flush(void)
+{
+        unsigned char *base = SERIAL_BASE;
+        unsigned char mask;
+        int i;
+
+        mask = UART_LSR_TEMT | UART_LSR_THRE;
+
+        for (i = 0; i < 0x1000; i++) {
+                if ((base[UART_LSR << 2] & mask) == mask)
+                        break;
+                barrier();
+        }
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-loki/include/mach/vmalloc.h b/arch/arm/mach-loki/include/mach/vmalloc.h
new file mode 100644
index 000000000000..8dc3bfcbf9f0
--- /dev/null
+++ b/arch/arm/mach-loki/include/mach/vmalloc.h
@@ -0,0 +1,5 @@
+/*
+ * arch/arm/mach-loki/include/mach/vmalloc.h
+ */
+
+#define VMALLOC_END     0xfe800000
diff --git a/arch/arm/mach-loki/lb88rc8480-setup.c b/arch/arm/mach-loki/lb88rc8480-setup.c
index d1b9e6e6253a..2cc9ac9b488f 100644
--- a/arch/arm/mach-loki/lb88rc8480-setup.c
+++ b/arch/arm/mach-loki/lb88rc8480-setup.c
@@ -19,7 +19,7 @@
 #include <linux/mv643xx_eth.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/arch/loki.h>
+#include <mach/loki.h>
 #include "common.h"
 
 #define LB88RC8480_FLASH_BOOT_CS_BASE   0xf8000000
diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c
index 46460218a208..995afc4ade4b 100644
--- a/arch/arm/mach-msm/board-halibut.c
+++ b/arch/arm/mach-msm/board-halibut.c
@@ -19,14 +19,14 @@
 #include <linux/platform_device.h>
 #include <linux/input.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/msm_iomap.h>
+#include <mach/board.h>
+#include <mach/msm_iomap.h>
 
 #include <asm/io.h>
 #include <asm/delay.h>
diff --git a/arch/arm/mach-msm/common.c b/arch/arm/mach-msm/common.c
index 3f5d3362f887..3a511368a5d8 100644
--- a/arch/arm/mach-msm/common.c
+++ b/arch/arm/mach-msm/common.c
@@ -28,9 +28,9 @@
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 
-#include <asm/arch/msm_iomap.h>
+#include <mach/msm_iomap.h>
 
-#include <asm/arch/board.h>
+#include <mach/board.h>
 
 struct flash_platform_data msm_nand_data = {
         .parts          = 0,
diff --git a/arch/arm/mach-msm/dma.c b/arch/arm/mach-msm/dma.c
index 8b0f339b3274..9de08265d974 100644
--- a/arch/arm/mach-msm/dma.c
+++ b/arch/arm/mach-msm/dma.c
@@ -15,7 +15,7 @@
 
 #include <asm/io.h>
 #include <linux/interrupt.h>
-#include <asm/arch/dma.h>
+#include <mach/dma.h>
 
 #define MSM_DMOV_CHANNEL_COUNT 16
 
diff --git a/arch/arm/mach-msm/idle.S b/arch/arm/mach-msm/idle.S
index 2b1cb7f16943..6a94f0527137 100644
--- a/arch/arm/mach-msm/idle.S
+++ b/arch/arm/mach-msm/idle.S
@@ -1,4 +1,4 @@
-/* linux/include/asm-arm/arch-msm/idle.S
+/* arch/arm/mach-msm/include/mach/idle.S
  *
  * Idle processing for MSM7K - work around bugs with SWFI.
  *
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h
new file mode 100644
index 000000000000..a7639493c095
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/board.h
@@ -0,0 +1,37 @@
+/* arch/arm/mach-msm/include/mach/board.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_BOARD_H
+#define __ASM_ARCH_MSM_BOARD_H
+
+#include <linux/types.h>
+
+/* platform device data structures */
+
+struct msm_mddi_platform_data
+{
+        void (*panel_power)(int on);
+        unsigned has_vsync_irq:1;
+};
+
+/* common init routines for use by arch/arm/mach-msm/board-*.c */
+
+void __init msm_add_devices(void);
+void __init msm_map_common_io(void);
+void __init msm_init_irq(void);
+void __init msm_init_gpio(void);
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/debug-macro.S b/arch/arm/mach-msm/include/mach/debug-macro.S
new file mode 100644
index 000000000000..528eef4b605c
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/debug-macro.S
@@ -0,0 +1,40 @@
+/* arch/arm/mach-msm7200/include/mach/debug-macro.S
+ *
+ * Copyright (C) 2007 Google, Inc.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <mach/hardware.h>
+#include <mach/msm_iomap.h>
+
+        .macro  addruart,rx
+        @ see if the MMU is enabled and select appropriate base address
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1
+        ldreq   \rx, =MSM_UART1_PHYS
+        ldrne   \rx, =MSM_UART1_BASE
+        .endm
+
+        .macro  senduart,rd,rx
+        str     \rd, [\rx, #0x0C]
+        .endm
+
+        .macro  waituart,rd,rx
+        @ wait for TX_READY
+1:      ldr     \rd, [\rx, #0x08]
+        tst     \rd, #0x04
+        beq     1b
+        .endm
+
+        .macro  busyuart,rd,rx
+        .endm
diff --git a/arch/arm/mach-msm/include/mach/dma.h b/arch/arm/mach-msm/include/mach/dma.h
new file mode 100644
index 000000000000..ad1c87f86d10
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/dma.h
@@ -0,0 +1,151 @@
+/* arch/arm/mach-msm/include/mach/dma.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_DMA_H
+
+#include <linux/list.h>
+#include <mach/msm_iomap.h>
+
+struct msm_dmov_cmd {
+        struct list_head list;
+        unsigned int cmdptr;
+        void (*complete_func)(struct msm_dmov_cmd *cmd, unsigned int result);
+/*      void (*user_result_func)(struct msm_dmov_cmd *cmd); */
+};
+
+void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd);
+void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd);
+int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr);
+/* int msm_dmov_exec_cmd_etc(unsigned id, unsigned int cmdptr, int timeout, int interruptible); */
+
+
+
+#define DMOV_SD0(off, ch) (MSM_DMOV_BASE + 0x0000 + (off) + ((ch) << 2))
+#define DMOV_SD1(off, ch) (MSM_DMOV_BASE + 0x0400 + (off) + ((ch) << 2))
+#define DMOV_SD2(off, ch) (MSM_DMOV_BASE + 0x0800 + (off) + ((ch) << 2))
+#define DMOV_SD3(off, ch) (MSM_DMOV_BASE + 0x0C00 + (off) + ((ch) << 2))
+
+/* only security domain 3 is available to the ARM11
+ * SD0 -> mARM trusted, SD1 -> mARM nontrusted, SD2 -> aDSP, SD3 -> aARM
+ */
+
+#define DMOV_CMD_PTR(ch)      DMOV_SD3(0x000, ch)
+#define DMOV_CMD_LIST         (0 << 29) /* does not work */
+#define DMOV_CMD_PTR_LIST     (1 << 29) /* works */
+#define DMOV_CMD_INPUT_CFG    (2 << 29) /* untested */
+#define DMOV_CMD_OUTPUT_CFG   (3 << 29) /* untested */
+#define DMOV_CMD_ADDR(addr)   ((addr) >> 3)
+
+#define DMOV_RSLT(ch)         DMOV_SD3(0x040, ch)
+#define DMOV_RSLT_VALID       (1 << 31) /* 0 == host has empties result fifo */
+#define DMOV_RSLT_ERROR       (1 << 3)
+#define DMOV_RSLT_FLUSH       (1 << 2)
+#define DMOV_RSLT_DONE        (1 << 1)  /* top pointer done */
+#define DMOV_RSLT_USER        (1 << 0)  /* command with FR force result */
+
+#define DMOV_FLUSH0(ch)       DMOV_SD3(0x080, ch)
+#define DMOV_FLUSH1(ch)       DMOV_SD3(0x0C0, ch)
+#define DMOV_FLUSH2(ch)       DMOV_SD3(0x100, ch)
+#define DMOV_FLUSH3(ch)       DMOV_SD3(0x140, ch)
+#define DMOV_FLUSH4(ch)       DMOV_SD3(0x180, ch)
+#define DMOV_FLUSH5(ch)       DMOV_SD3(0x1C0, ch)
+
+#define DMOV_STATUS(ch)       DMOV_SD3(0x200, ch)
+#define DMOV_STATUS_RSLT_COUNT(n)    (((n) >> 29))
+#define DMOV_STATUS_CMD_COUNT(n)     (((n) >> 27) & 3)
+#define DMOV_STATUS_RSLT_VALID       (1 << 1)
+#define DMOV_STATUS_CMD_PTR_RDY      (1 << 0)
+
+#define DMOV_ISR              DMOV_SD3(0x380, 0)
+
+#define DMOV_CONFIG(ch)       DMOV_SD3(0x300, ch)
+#define DMOV_CONFIG_FORCE_TOP_PTR_RSLT (1 << 2)
+#define DMOV_CONFIG_FORCE_FLUSH_RSLT   (1 << 1)
+#define DMOV_CONFIG_IRQ_EN             (1 << 0)
+
+/* channel assignments */
+
+#define DMOV_NAND_CHAN        7
+#define DMOV_NAND_CRCI_CMD    5
+#define DMOV_NAND_CRCI_DATA   4
+
+#define DMOV_SDC1_CHAN        8
+#define DMOV_SDC1_CRCI        6
+
+#define DMOV_SDC2_CHAN        8
+#define DMOV_SDC2_CRCI        7
+
+#define DMOV_TSIF_CHAN        10
+#define DMOV_TSIF_CRCI        10
+
+#define DMOV_USB_CHAN         11
+
+/* no client rate control ifc (eg, ram) */
+#define DMOV_NONE_CRCI        0
+
+
+/* If the CMD_PTR register has CMD_PTR_LIST selected, the data mover
+ * is going to walk a list of 32bit pointers as described below.  Each
+ * pointer points to a *array* of dmov_s, etc structs.  The last pointer
+ * in the list is marked with CMD_PTR_LP.  The last struct in each array
+ * is marked with CMD_LC (see below).
+ */
+#define CMD_PTR_ADDR(addr)  ((addr) >> 3)
+#define CMD_PTR_LP          (1 << 31) /* last pointer */
+#define CMD_PTR_PT          (3 << 29) /* ? */
+
+/* Single Item Mode */
+typedef struct {
+        unsigned cmd;
+        unsigned src;
+        unsigned dst;
+        unsigned len;
+} dmov_s;
+
+/* Scatter/Gather Mode */
+typedef struct {
+        unsigned cmd;
+        unsigned src_dscr;
+        unsigned dst_dscr;
+        unsigned _reserved;
+} dmov_sg;
+
+/* bits for the cmd field of the above structures */
+
+#define CMD_LC      (1 << 31)  /* last command */
+#define CMD_FR      (1 << 22)  /* force result -- does not work? */
+#define CMD_OCU     (1 << 21)  /* other channel unblock */
+#define CMD_OCB     (1 << 20)  /* other channel block */
+#define CMD_TCB     (1 << 19)  /* ? */
+#define CMD_DAH     (1 << 18)  /* destination address hold -- does not work?*/
+#define CMD_SAH     (1 << 17)  /* source address hold -- does not work? */
+
+#define CMD_MODE_SINGLE     (0 << 0) /* dmov_s structure used */
+#define CMD_MODE_SG         (1 << 0) /* untested */
+#define CMD_MODE_IND_SG     (2 << 0) /* untested */
+#define CMD_MODE_BOX        (3 << 0) /* untested */
+
+#define CMD_DST_SWAP_BYTES  (1 << 14) /* exchange each byte n with byte n+1 */
+#define CMD_DST_SWAP_SHORTS (1 << 15) /* exchange each short n with short n+1 */
+#define CMD_DST_SWAP_WORDS  (1 << 16) /* exchange each word n with word n+1 */
+
+#define CMD_SRC_SWAP_BYTES  (1 << 11) /* exchange each byte n with byte n+1 */
+#define CMD_SRC_SWAP_SHORTS (1 << 12) /* exchange each short n with short n+1 */
+#define CMD_SRC_SWAP_WORDS  (1 << 13) /* exchange each word n with word n+1 */
+
+#define CMD_DST_CRCI(n)     (((n) & 15) << 7)
+#define CMD_SRC_CRCI(n)     (((n) & 15) << 3)
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/entry-macro.S b/arch/arm/mach-msm/include/mach/entry-macro.S
new file mode 100644
index 000000000000..d2259486bcb1
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/entry-macro.S
@@ -0,0 +1,38 @@
+/* arch/arm/mach-msm7200/include/mach/entry-macro.S
+ *
+ * Copyright (C) 2007 Google, Inc.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <mach/msm_iomap.h>
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        @ enable imprecise aborts
+        cpsie   a
+        mov     \base, #MSM_VIC_BASE
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        @ 0xD0 has irq# or old irq# if the irq has been handled
+        @ 0xD4 has irq# or -1 if none pending *but* if you just
+        @ read 0xD4 you never get the first irq for some reason
+        ldr     \irqnr, [\base, #0xD0]
+        ldr     \irqnr, [\base, #0xD4]
+        cmp     \irqnr, #0xffffffff
+        .endm
diff --git a/arch/arm/mach-msm/include/mach/hardware.h b/arch/arm/mach-msm/include/mach/hardware.h
new file mode 100644
index 000000000000..2d126091ae41
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/hardware.h
@@ -0,0 +1,18 @@
+/* arch/arm/mach-msm/include/mach/hardware.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_HARDWARE_H
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/io.h b/arch/arm/mach-msm/include/mach/io.h
new file mode 100644
index 000000000000..c6a2feb268b0
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/io.h
@@ -0,0 +1,33 @@
+/* arch/arm/mach-msm/include/mach/io.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+#define __arch_ioremap __msm_ioremap
+#define __arch_iounmap __iounmap
+
+void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype);
+
+static inline void __iomem *__io(unsigned long addr)
+{
+        return (void __iomem *)addr;
+}
+#define __io(a)         __io(a)
+#define __mem_pci(a)    (a)
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs.h b/arch/arm/mach-msm/include/mach/irqs.h
new file mode 100644
index 000000000000..9dd4cf8a2693
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/irqs.h
@@ -0,0 +1,90 @@
+/* arch/arm/mach-msm/include/mach/irqs.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_IRQS_H
+#define __ASM_ARCH_MSM_IRQS_H
+
+/* MSM ARM11 Interrupt Numbers */
+/* See 80-VE113-1 A, pp219-221     */
+
+#define INT_A9_M2A_0         0
+#define INT_A9_M2A_1         1
+#define INT_A9_M2A_2         2
+#define INT_A9_M2A_3         3
+#define INT_A9_M2A_4         4
+#define INT_A9_M2A_5         5
+#define INT_A9_M2A_6         6
+#define INT_GP_TIMER_EXP     7
+#define INT_DEBUG_TIMER_EXP  8
+#define INT_UART1            9
+#define INT_UART2            10
+#define INT_UART3            11
+#define INT_UART1_RX         12
+#define INT_UART2_RX         13
+#define INT_UART3_RX         14
+#define INT_USB_OTG          15
+#define INT_MDDI_PRI         16
+#define INT_MDDI_EXT         17
+#define INT_MDDI_CLIENT      18
+#define INT_MDP              19
+#define INT_GRAPHICS         20
+#define INT_ADM_AARM         21
+#define INT_ADSP_A11         22
+#define INT_ADSP_A9_A11      23
+#define INT_SDC1_0           24
+#define INT_SDC1_1           25
+#define INT_SDC2_0           26
+#define INT_SDC2_1           27
+#define INT_KEYSENSE         28
+#define INT_TCHSCRN_SSBI     29
+#define INT_TCHSCRN1         30
+#define INT_TCHSCRN2         31
+
+#define INT_GPIO_GROUP1      (32 + 0)
+#define INT_GPIO_GROUP2      (32 + 1)
+#define INT_PWB_I2C          (32 + 2)
+#define INT_SOFTRESET        (32 + 3)
+#define INT_NAND_WR_ER_DONE  (32 + 4)
+#define INT_NAND_OP_DONE     (32 + 5)
+#define INT_PBUS_ARM11       (32 + 6)
+#define INT_AXI_MPU_SMI      (32 + 7)
+#define INT_AXI_MPU_EBI1     (32 + 8)
+#define INT_AD_HSSD          (32 + 9)
+#define INT_ARM11_PMU        (32 + 10)
+#define INT_ARM11_DMA        (32 + 11)
+#define INT_TSIF_IRQ         (32 + 12)
+#define INT_UART1DM_IRQ      (32 + 13)
+#define INT_UART1DM_RX       (32 + 14)
+#define INT_USB_HS           (32 + 15)
+#define INT_SDC3_0           (32 + 16)
+#define INT_SDC3_1           (32 + 17)
+#define INT_SDC4_0           (32 + 18)
+#define INT_SDC4_1           (32 + 19)
+#define INT_UART2DM_RX       (32 + 20)
+#define INT_UART2DM_IRQ      (32 + 21)
+
+/* 22-31 are reserved */
+
+#define MSM_IRQ_BIT(irq)     (1 << ((irq) & 31))
+
+#define NR_MSM_IRQS 64
+#define NR_GPIO_IRQS 122
+#define NR_BOARD_IRQS 64
+#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS)
+
+#define MSM_GPIO_TO_INT(n) (NR_MSM_IRQS + (n))
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h
new file mode 100644
index 000000000000..63fd47f2e62e
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/memory.h
@@ -0,0 +1,27 @@
+/* arch/arm/mach-msm/include/mach/memory.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/* physical offset of RAM */
+#define PHYS_OFFSET             UL(0x10000000)
+
+/* bus address and physical addresses are identical */
+#define __virt_to_bus(x)        __virt_to_phys(x)
+#define __bus_to_virt(x)        __phys_to_virt(x)
+
+#endif
+
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
new file mode 100644
index 000000000000..e221f58ceea3
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -0,0 +1,104 @@
+/* arch/arm/mach-msm/include/mach/msm_iomap.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *
+ * The MSM peripherals are spread all over across 768MB of physical
+ * space, which makes just having a simple IO_ADDRESS macro to slide
+ * them into the right virtual location rough.  Instead, we will
+ * provide a master phys->virt mapping for peripherals here.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_IOMAP_H
+#define __ASM_ARCH_MSM_IOMAP_H
+
+#include <asm/sizes.h>
+
+/* Physical base address and size of peripherals.
+ * Ordered by the virtual base addresses they will be mapped at.
+ *
+ * MSM_VIC_BASE must be an value that can be loaded via a "mov"
+ * instruction, otherwise entry-macro.S will not compile.
+ *
+ * If you add or remove entries here, you'll want to edit the
+ * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
+ * changes.
+ *
+ */
+
+#define MSM_VIC_BASE          0xE0000000
+#define MSM_VIC_PHYS          0xC0000000
+#define MSM_VIC_SIZE          SZ_4K
+
+#define MSM_CSR_BASE          0xE0001000
+#define MSM_CSR_PHYS          0xC0100000
+#define MSM_CSR_SIZE          SZ_4K
+
+#define MSM_GPT_PHYS          MSM_CSR_PHYS
+#define MSM_GPT_BASE          MSM_CSR_BASE
+#define MSM_GPT_SIZE          SZ_4K
+
+#define MSM_DMOV_BASE         0xE0002000
+#define MSM_DMOV_PHYS         0xA9700000
+#define MSM_DMOV_SIZE         SZ_4K
+
+#define MSM_UART1_BASE        0xE0003000
+#define MSM_UART1_PHYS        0xA9A00000
+#define MSM_UART1_SIZE        SZ_4K
+
+#define MSM_UART2_BASE        0xE0004000
+#define MSM_UART2_PHYS        0xA9B00000
+#define MSM_UART2_SIZE        SZ_4K
+
+#define MSM_UART3_BASE        0xE0005000
+#define MSM_UART3_PHYS        0xA9C00000
+#define MSM_UART3_SIZE        SZ_4K
+
+#define MSM_I2C_BASE          0xE0006000
+#define MSM_I2C_PHYS          0xA9900000
+#define MSM_I2C_SIZE          SZ_4K
+
+#define MSM_GPIO1_BASE        0xE0007000
+#define MSM_GPIO1_PHYS        0xA9200000
+#define MSM_GPIO1_SIZE        SZ_4K
+
+#define MSM_GPIO2_BASE        0xE0008000
+#define MSM_GPIO2_PHYS        0xA9300000
+#define MSM_GPIO2_SIZE        SZ_4K
+
+#define MSM_HSUSB_BASE        0xE0009000
+#define MSM_HSUSB_PHYS        0xA0800000
+#define MSM_HSUSB_SIZE        SZ_4K
+
+#define MSM_CLK_CTL_BASE      0xE000A000
+#define MSM_CLK_CTL_PHYS      0xA8600000
+#define MSM_CLK_CTL_SIZE      SZ_4K
+
+#define MSM_PMDH_BASE         0xE000B000
+#define MSM_PMDH_PHYS         0xAA600000
+#define MSM_PMDH_SIZE         SZ_4K
+
+#define MSM_EMDH_BASE         0xE000C000
+#define MSM_EMDH_PHYS         0xAA700000
+#define MSM_EMDH_SIZE         SZ_4K
+
+#define MSM_MDP_BASE          0xE0010000
+#define MSM_MDP_PHYS          0xAA200000
+#define MSM_MDP_SIZE          0x000F0000
+
+#define MSM_SHARED_RAM_BASE   0xE0100000
+#define MSM_SHARED_RAM_PHYS   0x01F00000
+#define MSM_SHARED_RAM_SIZE   SZ_1M
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/system.h b/arch/arm/mach-msm/include/mach/system.h
new file mode 100644
index 000000000000..f05ad2e0f235
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/system.h
@@ -0,0 +1,23 @@
+/* arch/arm/mach-msm/include/mach/system.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <mach/hardware.h>
+
+void arch_idle(void);
+
+static inline void arch_reset(char mode)
+{
+        for (;;) ;  /* depends on IPC w/ other core */
+}
diff --git a/arch/arm/mach-msm/include/mach/timex.h b/arch/arm/mach-msm/include/mach/timex.h
new file mode 100644
index 000000000000..a62e6b215aec
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/timex.h
@@ -0,0 +1,21 @@
+/* arch/arm/mach-msm/include/mach/timex.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_TIMEX_H
+#define __ASM_ARCH_MSM_TIMEX_H
+
+#define CLOCK_TICK_RATE         1000000
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/uncompress.h b/arch/arm/mach-msm/include/mach/uncompress.h
new file mode 100644
index 000000000000..026e8955ace9
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/uncompress.h
@@ -0,0 +1,36 @@
+/* arch/arm/mach-msm/include/mach/uncompress.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_UNCOMPRESS_H
+
+#include "hardware.h"
+
+static void putc(int c)
+{
+}
+
+static inline void flush(void)
+{
+}
+
+static inline void arch_decomp_setup(void)
+{
+}
+
+static inline void arch_decomp_wdog(void)
+{
+}
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/vmalloc.h b/arch/arm/mach-msm/include/mach/vmalloc.h
new file mode 100644
index 000000000000..05f81fd8623c
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/vmalloc.h
@@ -0,0 +1,22 @@
+/* arch/arm/mach-msm/include/mach/vmalloc.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_VMALLOC_H
+#define __ASM_ARCH_MSM_VMALLOC_H
+
+#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+
+#endif
+
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index eca4283bbcb2..5976200de99b 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -19,13 +19,13 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/page.h>
-#include <asm/arch/msm_iomap.h>
+#include <mach/msm_iomap.h>
 #include <asm/mach/map.h>
 
-#include <asm/arch/board.h>
+#include <mach/board.h>
 
 #define MSM_DEVICE(name) { \
                 .virtual = MSM_##name##_BASE, \
diff --git a/arch/arm/mach-msm/irq.c b/arch/arm/mach-msm/irq.c
index 0535b39261f0..66901baf8c8e 100644
--- a/arch/arm/mach-msm/irq.c
+++ b/arch/arm/mach-msm/irq.c
@@ -21,11 +21,11 @@
 #include <linux/timer.h>
 
 #include <linux/irq.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 #include <asm/io.h>
 
-#include <asm/arch/msm_iomap.h>
+#include <mach/msm_iomap.h>
 
 #define VIC_REG(off) (MSM_VIC_BASE + (off))
 
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index bd4732d1ab3e..9f02d7dca985 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -22,7 +22,7 @@
 #include <linux/delay.h>
 
 #include <asm/mach/time.h>
-#include <asm/arch/msm_iomap.h>
+#include <mach/msm_iomap.h>
 
 #include <asm/io.h>
 
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index d27b83b7bf62..e633f9cb239f 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -17,7 +17,7 @@
 #include <linux/ata_platform.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <asm/arch/mv78xx0.h>
+#include <mach/mv78xx0.h>
 #include <asm/plat-orion/cache-feroceon-l2.h>
 #include <asm/plat-orion/ehci-orion.h>
 #include <asm/plat-orion/orion_nand.h>
diff --git a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
index 0c93d19193df..a2d0c9783604 100644
--- a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
+++ b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
@@ -13,7 +13,7 @@
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
-#include <asm/arch/mv78xx0.h>
+#include <mach/mv78xx0.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include "common.h"
diff --git a/arch/arm/mach-mv78xx0/include/mach/debug-macro.S b/arch/arm/mach-mv78xx0/include/mach/debug-macro.S
new file mode 100644
index 000000000000..a06442fbd341
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/include/mach/debug-macro.S
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/mach-mv78xx0/include/mach/debug-macro.S
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <mach/mv78xx0.h>
+
+        .macro  addruart,rx
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1                                 @ MMU enabled?
+        ldreq   \rx, =MV78XX0_REGS_PHYS_BASE
+        ldrne   \rx, =MV78XX0_REGS_VIRT_BASE
+        orr     \rx, \rx, #0x00012000
+        .endm
+
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-mv78xx0/dma.h b/arch/arm/mach-mv78xx0/include/mach/dma.h
index 40a8c178f10d..40a8c178f10d 100644
--- a/include/asm-arm/arch-mv78xx0/dma.h
+++ b/arch/arm/mach-mv78xx0/include/mach/dma.h
diff --git a/arch/arm/mach-mv78xx0/include/mach/entry-macro.S b/arch/arm/mach-mv78xx0/include/mach/entry-macro.S
new file mode 100644
index 000000000000..ed4a46bcd3b0
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/include/mach/entry-macro.S
@@ -0,0 +1,39 @@
+/*
+ * arch/arm/mach-mv78xx0/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for Marvell MV78xx0 platforms
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <mach/mv78xx0.h>
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =IRQ_VIRT_BASE
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        @ check low interrupts
+        ldr     \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
+        ldr     \tmp, [\base, #IRQ_MASK_LOW_OFF]
+        mov     \irqnr, #31
+        ands    \irqstat, \irqstat, \tmp
+
+        @ if no low interrupts set, check high interrupts
+        ldreq   \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
+        ldreq   \tmp, [\base, #IRQ_MASK_HIGH_OFF]
+        moveq   \irqnr, #63
+        andeqs  \irqstat, \irqstat, \tmp
+
+        @ find first active interrupt source
+        clzne   \irqstat, \irqstat
+        subne   \irqnr, \irqnr, \irqstat
+        .endm
diff --git a/arch/arm/mach-mv78xx0/include/mach/hardware.h b/arch/arm/mach-mv78xx0/include/mach/hardware.h
new file mode 100644
index 000000000000..5d887557e123
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/include/mach/hardware.h
@@ -0,0 +1,21 @@
+/*
+ * arch/arm/mach-mv78xx0/include/mach/hardware.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include "mv78xx0.h"
+
+#define pcibios_assign_all_busses()     1
+
+#define PCIBIOS_MIN_IO                  0x00001000
+#define PCIBIOS_MIN_MEM                 0x01000000
+#define PCIMEM_BASE                     MV78XX0_PCIE_MEM_PHYS_BASE /* mem base for VGA */
+
+
+#endif
diff --git a/arch/arm/mach-mv78xx0/include/mach/io.h b/arch/arm/mach-mv78xx0/include/mach/io.h
new file mode 100644
index 000000000000..450e0e1ad092
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/include/mach/io.h
@@ -0,0 +1,26 @@
+/*
+ * arch/arm/mach-mv78xx0/include/mach/io.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#include "mv78xx0.h"
+
+#define IO_SPACE_LIMIT          0xffffffff
+
+static inline void __iomem *__io(unsigned long addr)
+{
+        return (void __iomem *)((addr - MV78XX0_PCIE_IO_PHYS_BASE(0))
+                                        + MV78XX0_PCIE_IO_VIRT_BASE(0));
+}
+
+#define __io(a)                 __io(a)
+#define __mem_pci(a)            (a)
+
+
+#endif
diff --git a/arch/arm/mach-mv78xx0/include/mach/irqs.h b/arch/arm/mach-mv78xx0/include/mach/irqs.h
new file mode 100644
index 000000000000..995d7fb8d06f
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/include/mach/irqs.h
@@ -0,0 +1,91 @@
+/*
+ * arch/arm/mach-mv78xx0/include/mach/irqs.h
+ *
+ * IRQ definitions for Marvell MV78xx0 SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#include "mv78xx0.h"    /* need GPIO_MAX */
+
+/*
+ * MV78xx0 Low Interrupt Controller
+ */
+#define IRQ_MV78XX0_ERR         0
+#define IRQ_MV78XX0_SPI         1
+#define IRQ_MV78XX0_I2C_0       2
+#define IRQ_MV78XX0_I2C_1       3
+#define IRQ_MV78XX0_IDMA_0      4
+#define IRQ_MV78XX0_IDMA_1      5
+#define IRQ_MV78XX0_IDMA_2      6
+#define IRQ_MV78XX0_IDMA_3      7
+#define IRQ_MV78XX0_TIMER_0     8
+#define IRQ_MV78XX0_TIMER_1     9
+#define IRQ_MV78XX0_TIMER_2     10
+#define IRQ_MV78XX0_TIMER_3     11
+#define IRQ_MV78XX0_UART_0      12
+#define IRQ_MV78XX0_UART_1      13
+#define IRQ_MV78XX0_UART_2      14
+#define IRQ_MV78XX0_UART_3      15
+#define IRQ_MV78XX0_USB_0       16
+#define IRQ_MV78XX0_USB_1       17
+#define IRQ_MV78XX0_USB_2       18
+#define IRQ_MV78XX0_CRYPTO      19
+#define IRQ_MV78XX0_SDIO_0      20
+#define IRQ_MV78XX0_SDIO_1      21
+#define IRQ_MV78XX0_XOR_0       22
+#define IRQ_MV78XX0_XOR_1       23
+#define IRQ_MV78XX0_I2S_0       24
+#define IRQ_MV78XX0_I2S_1       25
+#define IRQ_MV78XX0_SATA        26
+#define IRQ_MV78XX0_TDMI        27
+
+/*
+ * MV78xx0 High Interrupt Controller
+ */
+#define IRQ_MV78XX0_PCIE_00     32
+#define IRQ_MV78XX0_PCIE_01     33
+#define IRQ_MV78XX0_PCIE_02     34
+#define IRQ_MV78XX0_PCIE_03     35
+#define IRQ_MV78XX0_PCIE_10     36
+#define IRQ_MV78XX0_PCIE_11     37
+#define IRQ_MV78XX0_PCIE_12     38
+#define IRQ_MV78XX0_PCIE_13     39
+#define IRQ_MV78XX0_GE00_SUM    40
+#define IRQ_MV78XX0_GE00_RX     41
+#define IRQ_MV78XX0_GE00_TX     42
+#define IRQ_MV78XX0_GE00_MISC   43
+#define IRQ_MV78XX0_GE01_SUM    44
+#define IRQ_MV78XX0_GE01_RX     45
+#define IRQ_MV78XX0_GE01_TX     46
+#define IRQ_MV78XX0_GE01_MISC   47
+#define IRQ_MV78XX0_GE10_SUM    48
+#define IRQ_MV78XX0_GE10_RX     49
+#define IRQ_MV78XX0_GE10_TX     50
+#define IRQ_MV78XX0_GE10_MISC   51
+#define IRQ_MV78XX0_GE11_SUM    52
+#define IRQ_MV78XX0_GE11_RX     53
+#define IRQ_MV78XX0_GE11_TX     54
+#define IRQ_MV78XX0_GE11_MISC   55
+#define IRQ_MV78XX0_GPIO_0_7    56
+#define IRQ_MV78XX0_GPIO_8_15   57
+#define IRQ_MV78XX0_GPIO_16_23  58
+#define IRQ_MV78XX0_GPIO_24_31  59
+#define IRQ_MV78XX0_DB_IN       60
+#define IRQ_MV78XX0_DB_OUT      61
+
+/*
+ * MV78XX0 General Purpose Pins
+ */
+#define IRQ_MV78XX0_GPIO_START  64
+#define NR_GPIO_IRQS            GPIO_MAX
+
+#define NR_IRQS                 (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS)
+
+
+#endif
diff --git a/arch/arm/mach-mv78xx0/include/mach/memory.h b/arch/arm/mach-mv78xx0/include/mach/memory.h
new file mode 100644
index 000000000000..9e47a140ff7a
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/include/mach/memory.h
@@ -0,0 +1,14 @@
+/*
+ * arch/arm/mach-mv78xx0/include/mach/memory.h
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#define PHYS_OFFSET             UL(0x00000000)
+
+#define __virt_to_bus(x)        __virt_to_phys(x)
+#define __bus_to_virt(x)        __phys_to_virt(x)
+
+
+#endif
diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
new file mode 100644
index 000000000000..ad664178d6e1
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
@@ -0,0 +1,126 @@
+/*
+ * arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
+ *
+ * Generic definitions for Marvell MV78xx0 SoC flavors:
+ *  MV781x0 and MV782x0.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_MV78XX0_H
+#define __ASM_ARCH_MV78XX0_H
+
+/*
+ * Marvell MV78xx0 address maps.
+ *
+ * phys
+ * c0000000     PCIe Memory space
+ * f0800000     PCIe #0 I/O space
+ * f0900000     PCIe #1 I/O space
+ * f0a00000     PCIe #2 I/O space
+ * f0b00000     PCIe #3 I/O space
+ * f0c00000     PCIe #4 I/O space
+ * f0d00000     PCIe #5 I/O space
+ * f0e00000     PCIe #6 I/O space
+ * f0f00000     PCIe #7 I/O space
+ * f1000000     on-chip peripheral registers
+ *
+ * virt         phys            size
+ * fe400000     f102x000        16K     core-specific peripheral registers
+ * fe700000     f0800000        1M      PCIe #0 I/O space
+ * fe800000     f0900000        1M      PCIe #1 I/O space
+ * fe900000     f0a00000        1M      PCIe #2 I/O space
+ * fea00000     f0b00000        1M      PCIe #3 I/O space
+ * feb00000     f0c00000        1M      PCIe #4 I/O space
+ * fec00000     f0d00000        1M      PCIe #5 I/O space
+ * fed00000     f0e00000        1M      PCIe #6 I/O space
+ * fee00000     f0f00000        1M      PCIe #7 I/O space
+ * fef00000     f1000000        1M      on-chip peripheral registers
+ */
+#define MV78XX0_CORE0_REGS_PHYS_BASE    0xf1020000
+#define MV78XX0_CORE1_REGS_PHYS_BASE    0xf1024000
+#define MV78XX0_CORE_REGS_VIRT_BASE     0xfe400000
+#define MV78XX0_CORE_REGS_SIZE          SZ_16K
+
+#define MV78XX0_PCIE_IO_PHYS_BASE(i)    (0xf0800000 + ((i) << 20))
+#define MV78XX0_PCIE_IO_VIRT_BASE(i)    (0xfe700000 + ((i) << 20))
+#define MV78XX0_PCIE_IO_SIZE            SZ_1M
+
+#define MV78XX0_REGS_PHYS_BASE          0xf1000000
+#define MV78XX0_REGS_VIRT_BASE          0xfef00000
+#define MV78XX0_REGS_SIZE               SZ_1M
+
+#define MV78XX0_PCIE_MEM_PHYS_BASE      0xc0000000
+#define MV78XX0_PCIE_MEM_SIZE           0x30000000
+
+/*
+ * Core-specific peripheral registers.
+ */
+#define BRIDGE_VIRT_BASE        (MV78XX0_CORE_REGS_VIRT_BASE)
+#define  CPU_CONTROL            (BRIDGE_VIRT_BASE | 0x0104)
+#define   L2_WRITETHROUGH       0x00020000
+#define  RSTOUTn_MASK           (BRIDGE_VIRT_BASE | 0x0108)
+#define   SOFT_RESET_OUT_EN     0x00000004
+#define  SYSTEM_SOFT_RESET      (BRIDGE_VIRT_BASE | 0x010c)
+#define   SOFT_RESET            0x00000001
+#define  BRIDGE_CAUSE           (BRIDGE_VIRT_BASE | 0x0110)
+#define  BRIDGE_MASK            (BRIDGE_VIRT_BASE | 0x0114)
+#define   BRIDGE_INT_TIMER0     0x0002
+#define   BRIDGE_INT_TIMER1     0x0004
+#define   BRIDGE_INT_TIMER1_CLR (~0x0004)
+#define  IRQ_VIRT_BASE          (BRIDGE_VIRT_BASE | 0x0200)
+#define   IRQ_CAUSE_LOW_OFF     0x0004
+#define   IRQ_CAUSE_HIGH_OFF    0x0008
+#define   IRQ_MASK_LOW_OFF      0x0010
+#define   IRQ_MASK_HIGH_OFF     0x0014
+#define  TIMER_VIRT_BASE        (BRIDGE_VIRT_BASE | 0x0300)
+
+/*
+ * Register Map
+ */
+#define DDR_VIRT_BASE           (MV78XX0_REGS_VIRT_BASE | 0x00000)
+#define  DDR_WINDOW_CPU0_BASE   (DDR_VIRT_BASE | 0x1500)
+#define  DDR_WINDOW_CPU1_BASE   (DDR_VIRT_BASE | 0x1700)
+
+#define DEV_BUS_PHYS_BASE       (MV78XX0_REGS_PHYS_BASE | 0x10000)
+#define DEV_BUS_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE | 0x10000)
+#define  SAMPLE_AT_RESET_LOW    (DEV_BUS_VIRT_BASE | 0x0030)
+#define  SAMPLE_AT_RESET_HIGH   (DEV_BUS_VIRT_BASE | 0x0034)
+#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2000)
+#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2000)
+#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2100)
+#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2100)
+#define  UART2_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2200)
+#define  UART2_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2200)
+#define  UART3_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2300)
+#define  UART3_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2300)
+
+#define GE10_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x30000)
+#define GE11_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x34000)
+
+#define PCIE00_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x40000)
+#define PCIE01_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x44000)
+#define PCIE02_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x48000)
+#define PCIE03_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x4c000)
+
+#define USB0_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x50000)
+#define USB1_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x51000)
+#define USB2_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x52000)
+
+#define GE00_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x70000)
+#define GE01_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x74000)
+
+#define PCIE10_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x80000)
+#define PCIE11_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x84000)
+#define PCIE12_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x88000)
+#define PCIE13_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x8c000)
+
+#define SATA_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0xa0000)
+
+
+#define GPIO_MAX                32
+
+
+#endif
diff --git a/arch/arm/mach-mv78xx0/include/mach/system.h b/arch/arm/mach-mv78xx0/include/mach/system.h
new file mode 100644
index 000000000000..7d5179408832
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/include/mach/system.h
@@ -0,0 +1,37 @@
+/*
+ * arch/arm/mach-mv78xx0/include/mach/system.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <mach/hardware.h>
+#include <mach/mv78xx0.h>
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        /*
+         * Enable soft reset to assert RSTOUTn.
+         */
+        writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
+
+        /*
+         * Assert soft reset.
+         */
+        writel(SOFT_RESET, SYSTEM_SOFT_RESET);
+
+        while (1)
+                ;
+}
+
+
+#endif
diff --git a/arch/arm/mach-mv78xx0/include/mach/timex.h b/arch/arm/mach-mv78xx0/include/mach/timex.h
new file mode 100644
index 000000000000..0e8c443c723a
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/include/mach/timex.h
@@ -0,0 +1,9 @@
+/*
+ * arch/arm/mach-mv78xx0/include/mach/timex.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#define CLOCK_TICK_RATE         (100 * HZ)
diff --git a/arch/arm/mach-mv78xx0/include/mach/uncompress.h b/arch/arm/mach-mv78xx0/include/mach/uncompress.h
new file mode 100644
index 000000000000..365264298e79
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/include/mach/uncompress.h
@@ -0,0 +1,47 @@
+/*
+ * arch/arm/mach-mv78xx0/include/mach/uncompress.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/serial_reg.h>
+#include <mach/mv78xx0.h>
+
+#define SERIAL_BASE     ((unsigned char *)UART0_PHYS_BASE)
+
+static void putc(const char c)
+{
+        unsigned char *base = SERIAL_BASE;
+        int i;
+
+        for (i = 0; i < 0x1000; i++) {
+                if (base[UART_LSR << 2] & UART_LSR_THRE)
+                        break;
+                barrier();
+        }
+
+        base[UART_TX << 2] = c;
+}
+
+static void flush(void)
+{
+        unsigned char *base = SERIAL_BASE;
+        unsigned char mask;
+        int i;
+
+        mask = UART_LSR_TEMT | UART_LSR_THRE;
+
+        for (i = 0; i < 0x1000; i++) {
+                if ((base[UART_LSR << 2] & mask) == mask)
+                        break;
+                barrier();
+        }
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-mv78xx0/include/mach/vmalloc.h b/arch/arm/mach-mv78xx0/include/mach/vmalloc.h
new file mode 100644
index 000000000000..1c4954386a84
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/include/mach/vmalloc.h
@@ -0,0 +1,5 @@
+/*
+ * arch/arm/mach-mv78xx0/include/mach/vmalloc.h
+ */
+
+#define VMALLOC_END     0xfe000000
diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c
index 60f4ee4d4532..3198abf54c90 100644
--- a/arch/arm/mach-mv78xx0/irq.c
+++ b/arch/arm/mach-mv78xx0/irq.c
@@ -11,7 +11,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/pci.h>
-#include <asm/arch/mv78xx0.h>
+#include <mach/mv78xx0.h>
 #include <asm/plat-orion/irq.h>
 #include "common.h"
 
diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-mx2/clock_imx27.c
index 4af6f4f06e82..c69896d011a1 100644
--- a/arch/arm/mach-mx2/clock_imx27.c
+++ b/arch/arm/mach-mx2/clock_imx27.c
@@ -22,8 +22,8 @@
 #include <linux/module.h>
 #include <linux/spinlock.h>
 
-#include <asm/arch/clock.h>
-#include <asm/arch/common.h>
+#include <mach/clock.h>
+#include <mach/common.h>
 #include <asm/div64.h>
 
 #include "crm_regs.h"
diff --git a/arch/arm/mach-mx2/cpu_imx27.c b/arch/arm/mach-mx2/cpu_imx27.c
index 33f81f2b0860..239308fe6652 100644
--- a/arch/arm/mach-mx2/cpu_imx27.c
+++ b/arch/arm/mach-mx2/cpu_imx27.c
@@ -24,7 +24,7 @@
 #include <linux/io.h>
 #include <linux/module.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 #include "crm_regs.h"
 
diff --git a/arch/arm/mach-mx2/crm_regs.h b/arch/arm/mach-mx2/crm_regs.h
index a40a9b950ce9..94644cd0a0fc 100644
--- a/arch/arm/mach-mx2/crm_regs.h
+++ b/arch/arm/mach-mx2/crm_regs.h
@@ -20,7 +20,7 @@
 #ifndef __ARCH_ARM_MACH_MX2_CRM_REGS_H__
 #define __ARCH_ARM_MACH_MX2_CRM_REGS_H__
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 /* Register offsets */
 #define CCM_CSCR                (IO_ADDRESS(CCM_BASE_ADDR) + 0x0)
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c
index b5d2b63ea0df..bd0559d5933e 100644
--- a/arch/arm/mach-mx2/devices.c
+++ b/arch/arm/mach-mx2/devices.c
@@ -32,7 +32,7 @@
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 /*
  * Resource definition for the MXC IrDA
diff --git a/arch/arm/mach-mx2/generic.c b/arch/arm/mach-mx2/generic.c
index 4de97e18778e..dea6521d4d5c 100644
--- a/arch/arm/mach-mx2/generic.c
+++ b/arch/arm/mach-mx2/generic.c
@@ -20,7 +20,7 @@
 
 #include <linux/mm.h>
 #include <linux/init.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
 
diff --git a/arch/arm/mach-mx2/mx27ads.c b/arch/arm/mach-mx2/mx27ads.c
index 64c7bf67c400..4ce56ef4d8d3 100644
--- a/arch/arm/mach-mx2/mx27ads.c
+++ b/arch/arm/mach-mx2/mx27ads.c
@@ -23,16 +23,16 @@
 #include <linux/mtd/map.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
-#include <asm/arch/common.h>
-#include <asm/arch/hardware.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/imx-uart.h>
-#include <asm/arch/iomux-mx1-mx2.h>
-#include <asm/arch/board-mx27ads.h>
+#include <mach/gpio.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx1-mx2.h>
+#include <mach/board-mx27ads.h>
 
 /* ADS's NOR flash */
 static struct physmap_flash_data mx27ads_flash_data = {
diff --git a/arch/arm/mach-mx2/pcm038.c b/arch/arm/mach-mx2/pcm038.c
index ebe972605760..1028f453cfc8 100644
--- a/arch/arm/mach-mx2/pcm038.c
+++ b/arch/arm/mach-mx2/pcm038.c
@@ -21,12 +21,12 @@
 #include <linux/mtd/physmap.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
-#include <asm/arch/common.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/iomux-mx1-mx2.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx1-mx2.h>
 #include <asm/mach/time.h>
-#include <asm/arch/imx-uart.h>
-#include <asm/arch/board-pcm038.h>
+#include <mach/imx-uart.h>
+#include <mach/board-pcm038.h>
 
 /*
  * Phytec's phyCORE-i.MX27 comes with 32MiB flash,
diff --git a/arch/arm/mach-mx2/pcm970-baseboard.c b/arch/arm/mach-mx2/pcm970-baseboard.c
index 165d54acebed..a560cd6ad23d 100644
--- a/arch/arm/mach-mx2/pcm970-baseboard.c
+++ b/arch/arm/mach-mx2/pcm970-baseboard.c
@@ -17,7 +17,7 @@
  */
 
 #include <linux/platform_device.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach/arch.h>
 
 /*
diff --git a/arch/arm/mach-mx2/serial.c b/arch/arm/mach-mx2/serial.c
index 58dda232bb62..e31fd44f7941 100644
--- a/arch/arm/mach-mx2/serial.c
+++ b/arch/arm/mach-mx2/serial.c
@@ -20,8 +20,8 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/serial.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/imx-uart.h>
+#include <mach/hardware.h>
+#include <mach/imx-uart.h>
 
 static struct resource uart0[] = {
         {
diff --git a/arch/arm/mach-mx2/system.c b/arch/arm/mach-mx2/system.c
index 99304645299d..7b8269719d11 100644
--- a/arch/arm/mach-mx2/system.c
+++ b/arch/arm/mach-mx2/system.c
@@ -23,7 +23,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/proc-fns.h>
 #include <asm/system.h>
 
diff --git a/arch/arm/mach-mx3/clock.c b/arch/arm/mach-mx3/clock.c
index 2f3635943e70..9f14a871ee7c 100644
--- a/arch/arm/mach-mx3/clock.c
+++ b/arch/arm/mach-mx3/clock.c
@@ -23,7 +23,7 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/io.h>
-#include <asm/arch/clock.h>
+#include <mach/clock.h>
 #include <asm/div64.h>
 
 #include "crm_regs.h"
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index cdd0ff95e88d..e08c6a8ac56b 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -21,8 +21,8 @@
 #include <linux/platform_device.h>
 #include <linux/serial.h>
 #include <linux/gpio.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/imx-uart.h>
+#include <mach/hardware.h>
+#include <mach/imx-uart.h>
 
 static struct resource uart0[] = {
         {
diff --git a/arch/arm/mach-mx3/iomux.c b/arch/arm/mach-mx3/iomux.c
index e189a5f9aba3..3dda1fe23cbf 100644
--- a/arch/arm/mach-mx3/iomux.c
+++ b/arch/arm/mach-mx3/iomux.c
@@ -21,9 +21,9 @@
 #include <linux/spinlock.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/iomux-mx3.h>
+#include <mach/hardware.h>
+#include <mach/gpio.h>
+#include <mach/iomux-mx3.h>
 
 /*
  * IOMUX register (base) addresses
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
index 881b3569af5f..30d842bd4d64 100644
--- a/arch/arm/mach-mx3/mm.c
+++ b/arch/arm/mach-mx3/mm.c
@@ -22,10 +22,10 @@
 
 #include <linux/mm.h>
 #include <linux/init.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
-#include <asm/arch/common.h>
+#include <mach/common.h>
 
 /*!
  * @file mm.c
diff --git a/arch/arm/mach-mx3/mx31ads.c b/arch/arm/mach-mx3/mx31ads.c
index 63df8b0c480d..60fb4e0d5acd 100644
--- a/arch/arm/mach-mx3/mx31ads.c
+++ b/arch/arm/mach-mx3/mx31ads.c
@@ -23,14 +23,14 @@
 #include <linux/clk.h>
 #include <linux/serial_8250.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/memory.h>
 #include <asm/mach/map.h>
-#include <asm/arch/common.h>
-#include <asm/arch/board-mx31ads.h>
+#include <mach/common.h>
+#include <mach/board-mx31ads.h>
 
 /*!
  * @file mx31ads.c
diff --git a/arch/arm/mach-mx3/mx31lite.c b/arch/arm/mach-mx3/mx31lite.c
index 03384a73f57b..d363a6e79f80 100644
--- a/arch/arm/mach-mx3/mx31lite.c
+++ b/arch/arm/mach-mx3/mx31lite.c
@@ -23,15 +23,15 @@
 #include <linux/kernel.h>
 #include <linux/memory.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <asm/arch/common.h>
+#include <mach/common.h>
 #include <asm/page.h>
 #include <asm/setup.h>
-#include <asm/arch/board-mx31lite.h>
+#include <mach/board-mx31lite.h>
 
 /*
  * This file contains the board-specific initialization routines.
diff --git a/arch/arm/mach-mx3/pcm037.c b/arch/arm/mach-mx3/pcm037.c
index 1bb4eadf1ec5..0a152ed15a85 100644
--- a/arch/arm/mach-mx3/pcm037.c
+++ b/arch/arm/mach-mx3/pcm037.c
@@ -23,15 +23,15 @@
 #include <linux/mtd/physmap.h>
 #include <linux/memory.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <asm/arch/common.h>
-#include <asm/arch/imx-uart.h>
-#include <asm/arch/iomux-mx3.h>
-#include <asm/arch/board-pcm037.h>
+#include <mach/common.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx3.h>
+#include <mach/board-pcm037.h>
 
 static struct physmap_flash_data pcm037_flash_data = {
         .width  = 2,
diff --git a/arch/arm/mach-netx/fb.c b/arch/arm/mach-netx/fb.c
index e169b683e4de..24c79650f9f3 100644
--- a/arch/arm/mach-netx/fb.c
+++ b/arch/arm/mach-netx/fb.c
@@ -23,8 +23,8 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
 
-#include <asm/arch/netx-regs.h>
-#include <asm/arch/hardware.h>
+#include <mach/netx-regs.h>
+#include <mach/hardware.h>
 
 struct clk {};
 
diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c
index 798ac6e120ff..1b40483ea753 100644
--- a/arch/arm/mach-netx/generic.c
+++ b/arch/arm/mach-netx/generic.c
@@ -22,11 +22,11 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach/map.h>
 #include <asm/hardware/vic.h>
 #include <asm/io.h>
-#include <asm/arch/netx-regs.h>
+#include <mach/netx-regs.h>
 #include <asm/mach/irq.h>
 
 static struct map_desc netx_io_desc[] __initdata = {
diff --git a/arch/arm/mach-netx/include/mach/debug-macro.S b/arch/arm/mach-netx/include/mach/debug-macro.S
new file mode 100644
index 000000000000..11b9d5b46390
--- /dev/null
+++ b/arch/arm/mach-netx/include/mach/debug-macro.S
@@ -0,0 +1,38 @@
+/* arch/arm/mach-netx/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include "hardware.h"
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx, #0x00100000                @ physical
+                movne   \rx, #io_p2v(0x00100000)        @ virtual
+                orr     \rx, \rx, #0x00000a00
+                .endm
+
+                .macro  senduart,rd,rx
+                str     \rd, [\rx, #0]
+                .endm
+
+                .macro  busyuart,rd,rx
+1002:           ldr     \rd, [\rx, #0x18]
+                tst     \rd, #(1 << 3)
+                bne     1002b
+                .endm
+
+                .macro  waituart,rd,rx
+1001:           ldr     \rd, [\rx, #0x18]
+                tst     \rd, #(1 << 3)
+                bne     1001b
+                .endm
diff --git a/arch/arm/mach-netx/include/mach/dma.h b/arch/arm/mach-netx/include/mach/dma.h
new file mode 100644
index 000000000000..690b3ebc43ac
--- /dev/null
+++ b/arch/arm/mach-netx/include/mach/dma.h
@@ -0,0 +1,21 @@
+/*
+ *  arch/arm/mach-netx/include/mach/dma.h
+ *
+ * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#define MAX_DMA_CHANNELS 0
+#define MAX_DMA_ADDRESS ~0
diff --git a/arch/arm/mach-netx/include/mach/entry-macro.S b/arch/arm/mach-netx/include/mach/entry-macro.S
new file mode 100644
index 000000000000..a1952a0feda6
--- /dev/null
+++ b/arch/arm/mach-netx/include/mach/entry-macro.S
@@ -0,0 +1,41 @@
+/*
+ * arch/arm/mach-netx/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for Hilscher netX based platforms
+ *
+ * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <mach/hardware.h>
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_preamble, base, tmp
+                .endm
+
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                mov     \base, #io_p2v(0x00100000)
+                add     \base, \base, #0x000ff000
+
+                ldr     \irqstat, [\base, #0]
+                clz     \irqnr, \irqstat
+                rsb     \irqnr, \irqnr, #31
+                cmp     \irqstat, #0
+                .endm
+
diff --git a/arch/arm/mach-netx/include/mach/eth.h b/arch/arm/mach-netx/include/mach/eth.h
new file mode 100644
index 000000000000..88af1ac28ead
--- /dev/null
+++ b/arch/arm/mach-netx/include/mach/eth.h
@@ -0,0 +1,27 @@
+/*
+ * arch/arm/mach-netx/include/mach/eth.h
+ *
+ * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef ASMARM_ARCH_ETH_H
+#define ASMARM_ARCH_ETH_H
+
+struct netxeth_platform_data {
+        unsigned int xcno;      /* number of xmac/xpec engine this eth uses */
+};
+
+#endif
diff --git a/arch/arm/mach-netx/include/mach/hardware.h b/arch/arm/mach-netx/include/mach/hardware.h
new file mode 100644
index 000000000000..517a2bd37842
--- /dev/null
+++ b/arch/arm/mach-netx/include/mach/hardware.h
@@ -0,0 +1,39 @@
+/*
+ * arch/arm/mach-netx/include/mach/hardware.h
+ *
+ * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#define NETX_IO_PHYS    0x00100000
+#define NETX_IO_VIRT    0xe0000000
+#define NETX_IO_SIZE    0x00100000
+
+#define SRAM_INTERNAL_PHYS_0 0x00000
+#define SRAM_INTERNAL_PHYS_1 0x08000
+#define SRAM_INTERNAL_PHYS_2 0x10000
+#define SRAM_INTERNAL_PHYS_3 0x18000
+#define SRAM_INTERNAL_PHYS(no) ((no) * 0x8000)
+
+#define XPEC_MEM_SIZE 0x4000
+#define XMAC_MEM_SIZE 0x1000
+#define SRAM_MEM_SIZE 0x8000
+
+#define io_p2v(x) ((x) - NETX_IO_PHYS + NETX_IO_VIRT)
+#define io_v2p(x) ((x) - NETX_IO_VIRT + NETX_IO_PHYS)
+
+#endif
diff --git a/arch/arm/mach-netx/include/mach/io.h b/arch/arm/mach-netx/include/mach/io.h
new file mode 100644
index 000000000000..468b92a82585
--- /dev/null
+++ b/arch/arm/mach-netx/include/mach/io.h
@@ -0,0 +1,28 @@
+/*
+ *  arch/arm/mach-netx/include/mach/io.h
+ *
+ * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+#define __io(a)         ((void __iomem *)(a))
+#define __mem_pci(a)            (a)
+
+#endif
diff --git a/arch/arm/mach-netx/include/mach/irqs.h b/arch/arm/mach-netx/include/mach/irqs.h
new file mode 100644
index 000000000000..6ce914d54a30
--- /dev/null
+++ b/arch/arm/mach-netx/include/mach/irqs.h
@@ -0,0 +1,70 @@
+/*
+ * arch/arm/mach-netx/include/mach/irqs.h
+ *
+ * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#define NETX_IRQ_VIC_START   0
+#define NETX_IRQ_SOFTINT     0
+#define NETX_IRQ_TIMER0      1
+#define NETX_IRQ_TIMER1      2
+#define NETX_IRQ_TIMER2      3
+#define NETX_IRQ_SYSTIME_NS  4
+#define NETX_IRQ_SYSTIME_S   5
+#define NETX_IRQ_GPIO_15     6
+#define NETX_IRQ_WATCHDOG    7
+#define NETX_IRQ_UART0       8
+#define NETX_IRQ_UART1       9
+#define NETX_IRQ_UART2      10
+#define NETX_IRQ_USB        11
+#define NETX_IRQ_SPI        12
+#define NETX_IRQ_I2C        13
+#define NETX_IRQ_LCD        14
+#define NETX_IRQ_HIF        15
+#define NETX_IRQ_GPIO_0_14  16
+#define NETX_IRQ_XPEC0      17
+#define NETX_IRQ_XPEC1      18
+#define NETX_IRQ_XPEC2      19
+#define NETX_IRQ_XPEC3      20
+#define NETX_IRQ_XPEC(no)   (17 + (no))
+#define NETX_IRQ_MSYNC0     21
+#define NETX_IRQ_MSYNC1     22
+#define NETX_IRQ_MSYNC2     23
+#define NETX_IRQ_MSYNC3     24
+#define NETX_IRQ_IRQ_PHY    25
+#define NETX_IRQ_ISO_AREA   26
+/* int 27 is reserved */
+/* int 28 is reserved */
+#define NETX_IRQ_TIMER3     29
+#define NETX_IRQ_TIMER4     30
+/* int 31 is reserved */
+
+#define NETX_IRQS 32
+
+/* for multiplexed irqs on gpio 0..14 */
+#define NETX_IRQ_GPIO(x) (NETX_IRQS + (x))
+#define NETX_IRQ_GPIO_LAST NETX_IRQ_GPIO(14)
+
+/* Host interface interrupts */
+#define NETX_IRQ_HIF_CHAINED(x)    (NETX_IRQ_GPIO_LAST + 1 + (x))
+#define NETX_IRQ_HIF_PIO35         NETX_IRQ_HIF_CHAINED(0)
+#define NETX_IRQ_HIF_PIO36         NETX_IRQ_HIF_CHAINED(1)
+#define NETX_IRQ_HIF_PIO40         NETX_IRQ_HIF_CHAINED(2)
+#define NETX_IRQ_HIF_PIO47         NETX_IRQ_HIF_CHAINED(3)
+#define NETX_IRQ_HIF_PIO72         NETX_IRQ_HIF_CHAINED(4)
+#define NETX_IRQ_HIF_LAST          NETX_IRQ_HIF_CHAINED(4)
+
+#define NR_IRQS (NETX_IRQ_HIF_LAST + 1)
diff --git a/arch/arm/mach-netx/include/mach/memory.h b/arch/arm/mach-netx/include/mach/memory.h
new file mode 100644
index 000000000000..53745a1378de
--- /dev/null
+++ b/arch/arm/mach-netx/include/mach/memory.h
@@ -0,0 +1,36 @@
+/*
+ *  arch/arm/mach-netx/include/mach/memory.h
+ *
+ * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#define PHYS_OFFSET UL(0x80000000)
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+#define __virt_to_bus(x)         __virt_to_phys(x)
+#define __bus_to_virt(x)         __phys_to_virt(x)
+
+#endif
+
diff --git a/arch/arm/mach-netx/include/mach/netx-regs.h b/arch/arm/mach-netx/include/mach/netx-regs.h
new file mode 100644
index 000000000000..5104a00d40f4
--- /dev/null
+++ b/arch/arm/mach-netx/include/mach/netx-regs.h
@@ -0,0 +1,410 @@
+/*
+ * arch/arm/mach-netx/include/mach/netx-regs.h
+ *
+ * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_NETX_REGS_H
+#define __ASM_ARCH_NETX_REGS_H
+
+/* offsets relative to the beginning of the io space */
+#define NETX_OFS_SYSTEM  0x00000
+#define NETX_OFS_MEMCR   0x00100
+#define NETX_OFS_DPMAS   0x03000
+#define NETX_OFS_GPIO    0x00800
+#define NETX_OFS_PIO     0x00900
+#define NETX_OFS_UART0   0x00a00
+#define NETX_OFS_UART1   0x00a40
+#define NETX_OFS_UART2   0x00a80
+#define NETX_OF_MIIMU    0x00b00
+#define NETX_OFS_SPI     0x00c00
+#define NETX_OFS_I2C     0x00d00
+#define NETX_OFS_SYSTIME 0x01100
+#define NETX_OFS_RTC     0x01200
+#define NETX_OFS_EXTBUS  0x03600
+#define NETX_OFS_LCD     0x04000
+#define NETX_OFS_USB     0x20000
+#define NETX_OFS_XMAC0   0x60000
+#define NETX_OFS_XMAC1   0x61000
+#define NETX_OFS_XMAC2   0x62000
+#define NETX_OFS_XMAC3   0x63000
+#define NETX_OFS_XMAC(no) (0x60000 + (no) * 0x1000)
+#define NETX_OFS_PFIFO   0x64000
+#define NETX_OFS_XPEC0   0x70000
+#define NETX_OFS_XPEC1   0x74000
+#define NETX_OFS_XPEC2   0x78000
+#define NETX_OFS_XPEC3   0x7c000
+#define NETX_OFS_XPEC(no) (0x70000 + (no) * 0x4000)
+#define NETX_OFS_VIC     0xff000
+
+/* physical addresses */
+#define NETX_PA_SYSTEM   (NETX_IO_PHYS + NETX_OFS_SYSTEM)
+#define NETX_PA_MEMCR    (NETX_IO_PHYS + NETX_OFS_MEMCR)
+#define NETX_PA_DPMAS    (NETX_IO_PHYS + NETX_OFS_DPMAS)
+#define NETX_PA_GPIO     (NETX_IO_PHYS + NETX_OFS_GPIO)
+#define NETX_PA_PIO      (NETX_IO_PHYS + NETX_OFS_PIO)
+#define NETX_PA_UART0    (NETX_IO_PHYS + NETX_OFS_UART0)
+#define NETX_PA_UART1    (NETX_IO_PHYS + NETX_OFS_UART1)
+#define NETX_PA_UART2    (NETX_IO_PHYS + NETX_OFS_UART2)
+#define NETX_PA_MIIMU    (NETX_IO_PHYS + NETX_OF_MIIMU)
+#define NETX_PA_SPI      (NETX_IO_PHYS + NETX_OFS_SPI)
+#define NETX_PA_I2C      (NETX_IO_PHYS + NETX_OFS_I2C)
+#define NETX_PA_SYSTIME  (NETX_IO_PHYS + NETX_OFS_SYSTIME)
+#define NETX_PA_RTC      (NETX_IO_PHYS + NETX_OFS_RTC)
+#define NETX_PA_EXTBUS   (NETX_IO_PHYS + NETX_OFS_EXTBUS)
+#define NETX_PA_LCD      (NETX_IO_PHYS + NETX_OFS_LCD)
+#define NETX_PA_USB      (NETX_IO_PHYS + NETX_OFS_USB)
+#define NETX_PA_XMAC0    (NETX_IO_PHYS + NETX_OFS_XMAC0)
+#define NETX_PA_XMAC1    (NETX_IO_PHYS + NETX_OFS_XMAC1)
+#define NETX_PA_XMAC2    (NETX_IO_PHYS + NETX_OFS_XMAC2)
+#define NETX_PA_XMAC3    (NETX_IO_PHYS + NETX_OFS_XMAC3)
+#define NETX_PA_XMAC(no) (NETX_IO_PHYS + NETX_OFS_XMAC(no))
+#define NETX_PA_PFIFO    (NETX_IO_PHYS + NETX_OFS_PFIFO)
+#define NETX_PA_XPEC0    (NETX_IO_PHYS + NETX_OFS_XPEC0)
+#define NETX_PA_XPEC1    (NETX_IO_PHYS + NETX_OFS_XPEC1)
+#define NETX_PA_XPEC2    (NETX_IO_PHYS + NETX_OFS_XPEC2)
+#define NETX_PA_XPEC3    (NETX_IO_PHYS + NETX_OFS_XPEC3)
+#define NETX_PA_XPEC(no) (NETX_IO_PHYS + NETX_OFS_XPEC(no))
+#define NETX_PA_VIC      (NETX_IO_PHYS + NETX_OFS_VIC)
+
+/* virual addresses */
+#define NETX_VA_SYSTEM   (NETX_IO_VIRT + NETX_OFS_SYSTEM)
+#define NETX_VA_MEMCR    (NETX_IO_VIRT + NETX_OFS_MEMCR)
+#define NETX_VA_DPMAS    (NETX_IO_VIRT + NETX_OFS_DPMAS)
+#define NETX_VA_GPIO     (NETX_IO_VIRT + NETX_OFS_GPIO)
+#define NETX_VA_PIO      (NETX_IO_VIRT + NETX_OFS_PIO)
+#define NETX_VA_UART0    (NETX_IO_VIRT + NETX_OFS_UART0)
+#define NETX_VA_UART1    (NETX_IO_VIRT + NETX_OFS_UART1)
+#define NETX_VA_UART2    (NETX_IO_VIRT + NETX_OFS_UART2)
+#define NETX_VA_MIIMU    (NETX_IO_VIRT + NETX_OF_MIIMU)
+#define NETX_VA_SPI      (NETX_IO_VIRT + NETX_OFS_SPI)
+#define NETX_VA_I2C      (NETX_IO_VIRT + NETX_OFS_I2C)
+#define NETX_VA_SYSTIME  (NETX_IO_VIRT + NETX_OFS_SYSTIME)
+#define NETX_VA_RTC      (NETX_IO_VIRT + NETX_OFS_RTC)
+#define NETX_VA_EXTBUS   (NETX_IO_VIRT + NETX_OFS_EXTBUS)
+#define NETX_VA_LCD      (NETX_IO_VIRT + NETX_OFS_LCD)
+#define NETX_VA_USB      (NETX_IO_VIRT + NETX_OFS_USB)
+#define NETX_VA_XMAC0    (NETX_IO_VIRT + NETX_OFS_XMAC0)
+#define NETX_VA_XMAC1    (NETX_IO_VIRT + NETX_OFS_XMAC1)
+#define NETX_VA_XMAC2    (NETX_IO_VIRT + NETX_OFS_XMAC2)
+#define NETX_VA_XMAC3    (NETX_IO_VIRT + NETX_OFS_XMAC3)
+#define NETX_VA_XMAC(no) (NETX_IO_VIRT + NETX_OFS_XMAC(no))
+#define NETX_VA_PFIFO    (NETX_IO_VIRT + NETX_OFS_PFIFO)
+#define NETX_VA_XPEC0    (NETX_IO_VIRT + NETX_OFS_XPEC0)
+#define NETX_VA_XPEC1    (NETX_IO_VIRT + NETX_OFS_XPEC1)
+#define NETX_VA_XPEC2    (NETX_IO_VIRT + NETX_OFS_XPEC2)
+#define NETX_VA_XPEC3    (NETX_IO_VIRT + NETX_OFS_XPEC3)
+#define NETX_VA_XPEC(no) (NETX_IO_VIRT + NETX_OFS_XPEC(no))
+#define NETX_VA_VIC      (NETX_IO_VIRT + NETX_OFS_VIC)
+
+/*********************************
+ * System functions              *
+ *********************************/
+
+/* Registers */
+#define NETX_SYSTEM_REG(ofs)            __io(NETX_VA_SYSTEM + (ofs))
+#define NETX_SYSTEM_BOO_SR          NETX_SYSTEM_REG(0x00)
+#define NETX_SYSTEM_IOC_CR          NETX_SYSTEM_REG(0x04)
+#define NETX_SYSTEM_IOC_MR          NETX_SYSTEM_REG(0x08)
+
+/* FIXME: Docs are not consistent */
+/* #define NETX_SYSTEM_RES_CR          NETX_SYSTEM_REG(0x08) */
+#define NETX_SYSTEM_RES_CR          NETX_SYSTEM_REG(0x0c)
+
+#define NETX_SYSTEM_PHY_CONTROL     NETX_SYSTEM_REG(0x10)
+#define NETX_SYSTEM_REV             NETX_SYSTEM_REG(0x34)
+#define NETX_SYSTEM_IOC_ACCESS_KEY  NETX_SYSTEM_REG(0x70)
+#define NETX_SYSTEM_WDG_TR          NETX_SYSTEM_REG(0x200)
+#define NETX_SYSTEM_WDG_CTR         NETX_SYSTEM_REG(0x204)
+#define NETX_SYSTEM_WDG_IRQ_TIMEOUT NETX_SYSTEM_REG(0x208)
+#define NETX_SYSTEM_WDG_RES_TIMEOUT NETX_SYSTEM_REG(0x20c)
+
+/* Bits */
+#define NETX_SYSTEM_RES_CR_RSTIN         (1<<0)
+#define NETX_SYSTEM_RES_CR_WDG_RES       (1<<1)
+#define NETX_SYSTEM_RES_CR_HOST_RES      (1<<2)
+#define NETX_SYSTEM_RES_CR_FIRMW_RES     (1<<3)
+#define NETX_SYSTEM_RES_CR_XPEC0_RES     (1<<4)
+#define NETX_SYSTEM_RES_CR_XPEC1_RES     (1<<5)
+#define NETX_SYSTEM_RES_CR_XPEC2_RES     (1<<6)
+#define NETX_SYSTEM_RES_CR_XPEC3_RES     (1<<7)
+#define NETX_SYSTEM_RES_CR_DIS_XPEC0_RES (1<<16)
+#define NETX_SYSTEM_RES_CR_DIS_XPEC1_RES (1<<17)
+#define NETX_SYSTEM_RES_CR_DIS_XPEC2_RES (1<<18)
+#define NETX_SYSTEM_RES_CR_DIS_XPEC3_RES (1<<19)
+#define NETX_SYSTEM_RES_CR_FIRMW_FLG0    (1<<20)
+#define NETX_SYSTEM_RES_CR_FIRMW_FLG1    (1<<21)
+#define NETX_SYSTEM_RES_CR_FIRMW_FLG2    (1<<22)
+#define NETX_SYSTEM_RES_CR_FIRMW_FLG3    (1<<23)
+#define NETX_SYSTEM_RES_CR_FIRMW_RES_EN  (1<<24)
+#define NETX_SYSTEM_RES_CR_RSTOUT        (1<<25)
+#define NETX_SYSTEM_RES_CR_EN_RSTOUT     (1<<26)
+
+#define PHY_CONTROL_RESET            (1<<31)
+#define PHY_CONTROL_SIM_BYP          (1<<30)
+#define PHY_CONTROL_CLK_XLATIN       (1<<29)
+#define PHY_CONTROL_PHY1_EN          (1<<21)
+#define PHY_CONTROL_PHY1_NP_MSG_CODE
+#define PHY_CONTROL_PHY1_AUTOMDIX    (1<<17)
+#define PHY_CONTROL_PHY1_FIXMODE     (1<<16)
+#define PHY_CONTROL_PHY1_MODE(mode)  (((mode) & 0x7) << 13)
+#define PHY_CONTROL_PHY0_EN          (1<<12)
+#define PHY_CONTROL_PHY0_NP_MSG_CODE
+#define PHY_CONTROL_PHY0_AUTOMDIX    (1<<8)
+#define PHY_CONTROL_PHY0_FIXMODE     (1<<7)
+#define PHY_CONTROL_PHY0_MODE(mode)  (((mode) & 0x7) << 4)
+#define PHY_CONTROL_PHY_ADDRESS(adr) ((adr) & 0xf)
+
+#define PHY_MODE_10BASE_T_HALF      0
+#define PHY_MODE_10BASE_T_FULL      1
+#define PHY_MODE_100BASE_TX_FX_FULL 2
+#define PHY_MODE_100BASE_TX_FX_HALF 3
+#define PHY_MODE_100BASE_TX_HALF    4
+#define PHY_MODE_REPEATER           5
+#define PHY_MODE_POWER_DOWN         6
+#define PHY_MODE_ALL                7
+
+/* Bits */
+#define VECT_CNTL_ENABLE               (1 << 5)
+
+/*******************************
+ * GPIO and timer module       *
+ *******************************/
+
+/* Registers */
+#define NETX_GPIO_REG(ofs)                     __io(NETX_VA_GPIO + (ofs))
+#define NETX_GPIO_CFG(gpio)                NETX_GPIO_REG(0x0  + ((gpio)<<2))
+#define NETX_GPIO_THRESHOLD_CAPTURE(gpio)  NETX_GPIO_REG(0x40 + ((gpio)<<2))
+#define NETX_GPIO_COUNTER_CTRL(counter)    NETX_GPIO_REG(0x80 + ((counter)<<2))
+#define NETX_GPIO_COUNTER_MAX(counter)     NETX_GPIO_REG(0x94 + ((counter)<<2))
+#define NETX_GPIO_COUNTER_CURRENT(counter) NETX_GPIO_REG(0xa8 + ((counter)<<2))
+#define NETX_GPIO_IRQ_ENABLE               NETX_GPIO_REG(0xbc)
+#define NETX_GPIO_IRQ_DISABLE              NETX_GPIO_REG(0xc0)
+#define NETX_GPIO_SYSTIME_NS_CMP           NETX_GPIO_REG(0xc4)
+#define NETX_GPIO_LINE                     NETX_GPIO_REG(0xc8)
+#define NETX_GPIO_IRQ                      NETX_GPIO_REG(0xd0)
+
+/* Bits */
+#define NETX_GPIO_CFG_IOCFG_GP_INPUT                 (0x0)
+#define NETX_GPIO_CFG_IOCFG_GP_OUTPUT                (0x1)
+#define NETX_GPIO_CFG_IOCFG_GP_UART                  (0x2)
+#define NETX_GPIO_CFG_INV                            (1<<2)
+#define NETX_GPIO_CFG_MODE_INPUT_READ                (0<<3)
+#define NETX_GPIO_CFG_MODE_INPUT_CAPTURE_CONT_RISING (1<<3)
+#define NETX_GPIO_CFG_MODE_INPUT_CAPTURE_ONCE_RISING (2<<3)
+#define NETX_GPIO_CFG_MODE_INPUT_CAPTURE_HIGH_LEVEL  (3<<3)
+#define NETX_GPIO_CFG_COUNT_REF_COUNTER0             (0<<5)
+#define NETX_GPIO_CFG_COUNT_REF_COUNTER1             (1<<5)
+#define NETX_GPIO_CFG_COUNT_REF_COUNTER2             (2<<5)
+#define NETX_GPIO_CFG_COUNT_REF_COUNTER3             (3<<5)
+#define NETX_GPIO_CFG_COUNT_REF_COUNTER4             (4<<5)
+#define NETX_GPIO_CFG_COUNT_REF_SYSTIME              (7<<5)
+
+#define NETX_GPIO_COUNTER_CTRL_RUN                   (1<<0)
+#define NETX_GPIO_COUNTER_CTRL_SYM                   (1<<1)
+#define NETX_GPIO_COUNTER_CTRL_ONCE                  (1<<2)
+#define NETX_GPIO_COUNTER_CTRL_IRQ_EN                (1<<3)
+#define NETX_GPIO_COUNTER_CTRL_CNT_EVENT             (1<<4)
+#define NETX_GPIO_COUNTER_CTRL_RST_EN                (1<<5)
+#define NETX_GPIO_COUNTER_CTRL_SEL_EVENT             (1<<6)
+#define NETX_GPIO_COUNTER_CTRL_GPIO_REF /* FIXME */
+
+#define GPIO_BIT(gpio)                     (1<<(gpio))
+#define COUNTER_BIT(counter)               ((1<<16)<<(counter))
+
+/*******************************
+ * PIO                         *
+ *******************************/
+
+/* Registers */
+#define NETX_PIO_REG(ofs)        __io(NETX_VA_PIO + (ofs))
+#define NETX_PIO_INPIO       NETX_PIO_REG(0x0)
+#define NETX_PIO_OUTPIO      NETX_PIO_REG(0x4)
+#define NETX_PIO_OEPIO       NETX_PIO_REG(0x8)
+
+/*******************************
+ * MII Unit                    *
+ *******************************/
+
+/* Registers */
+#define NETX_MIIMU           __io(NETX_VA_MIIMU)
+
+/* Bits */
+#define MIIMU_SNRDY        (1<<0)
+#define MIIMU_PREAMBLE     (1<<1)
+#define MIIMU_OPMODE_WRITE (1<<2)
+#define MIIMU_MDC_PERIOD   (1<<3)
+#define MIIMU_PHY_NRES     (1<<4)
+#define MIIMU_RTA          (1<<5)
+#define MIIMU_REGADDR(adr) (((adr) & 0x1f) << 6)
+#define MIIMU_PHYADDR(adr) (((adr) & 0x1f) << 11)
+#define MIIMU_DATA(data)   (((data) & 0xffff) << 16)
+
+/*******************************
+ * xmac / xpec                 *
+ *******************************/
+
+/* XPEC register offsets relative to NETX_VA_XPEC(no) */
+#define NETX_XPEC_R0_OFS           0x00
+#define NETX_XPEC_R1_OFS           0x04
+#define NETX_XPEC_R2_OFS           0x08
+#define NETX_XPEC_R3_OFS           0x0c
+#define NETX_XPEC_R4_OFS           0x10
+#define NETX_XPEC_R5_OFS           0x14
+#define NETX_XPEC_R6_OFS           0x18
+#define NETX_XPEC_R7_OFS           0x1c
+#define NETX_XPEC_RANGE01_OFS      0x20
+#define NETX_XPEC_RANGE23_OFS      0x24
+#define NETX_XPEC_RANGE45_OFS      0x28
+#define NETX_XPEC_RANGE67_OFS      0x2c
+#define NETX_XPEC_PC_OFS           0x48
+#define NETX_XPEC_TIMER_OFS(timer) (0x30 + ((timer)<<2))
+#define NETX_XPEC_IRQ_OFS          0x8c
+#define NETX_XPEC_SYSTIME_NS_OFS   0x90
+#define NETX_XPEC_FIFO_DATA_OFS    0x94
+#define NETX_XPEC_SYSTIME_S_OFS    0x98
+#define NETX_XPEC_ADC_OFS          0x9c
+#define NETX_XPEC_URX_COUNT_OFS    0x40
+#define NETX_XPEC_UTX_COUNT_OFS    0x44
+#define NETX_XPEC_PC_OFS           0x48
+#define NETX_XPEC_ZERO_OFS         0x4c
+#define NETX_XPEC_STATCFG_OFS      0x50
+#define NETX_XPEC_EC_MASKA_OFS     0x54
+#define NETX_XPEC_EC_MASKB_OFS     0x58
+#define NETX_XPEC_EC_MASK0_OFS     0x5c
+#define NETX_XPEC_EC_MASK8_OFS     0x7c
+#define NETX_XPEC_EC_MASK9_OFS     0x80
+#define NETX_XPEC_XPU_HOLD_PC_OFS  0x100
+#define NETX_XPEC_RAM_START_OFS    0x2000
+
+/* Bits */
+#define XPU_HOLD_PC (1<<0)
+
+/* XMAC register offsets relative to NETX_VA_XMAC(no) */
+#define NETX_XMAC_RPU_PROGRAM_START_OFS       0x000
+#define NETX_XMAC_RPU_PROGRAM_END_OFS         0x3ff
+#define NETX_XMAC_TPU_PROGRAM_START_OFS       0x400
+#define NETX_XMAC_TPU_PROGRAM_END_OFS         0x7ff
+#define NETX_XMAC_RPU_HOLD_PC_OFS             0xa00
+#define NETX_XMAC_TPU_HOLD_PC_OFS             0xa04
+#define NETX_XMAC_STATUS_SHARED0_OFS          0x840
+#define NETX_XMAC_CONFIG_SHARED0_OFS          0x844
+#define NETX_XMAC_STATUS_SHARED1_OFS          0x848
+#define NETX_XMAC_CONFIG_SHARED1_OFS          0x84c
+#define NETX_XMAC_STATUS_SHARED2_OFS          0x850
+#define NETX_XMAC_CONFIG_SHARED2_OFS          0x854
+#define NETX_XMAC_STATUS_SHARED3_OFS          0x858
+#define NETX_XMAC_CONFIG_SHARED3_OFS          0x85c
+
+#define RPU_HOLD_PC            (1<<15)
+#define TPU_HOLD_PC            (1<<15)
+
+/*******************************
+ * Pointer FIFO                *
+ *******************************/
+
+/* Registers */
+#define NETX_PFIFO_REG(ofs)               __io(NETX_VA_PFIFO + (ofs))
+#define NETX_PFIFO_BASE(pfifo)        NETX_PFIFO_REG(0x00 + ((pfifo)<<2))
+#define NETX_PFIFO_BORDER_BASE(pfifo) NETX_PFIFO_REG(0x80 + ((pfifo)<<2))
+#define NETX_PFIFO_RESET              NETX_PFIFO_REG(0x100)
+#define NETX_PFIFO_FULL               NETX_PFIFO_REG(0x104)
+#define NETX_PFIFO_EMPTY              NETX_PFIFO_REG(0x108)
+#define NETX_PFIFO_OVEFLOW            NETX_PFIFO_REG(0x10c)
+#define NETX_PFIFO_UNDERRUN           NETX_PFIFO_REG(0x110)
+#define NETX_PFIFO_FILL_LEVEL(pfifo)  NETX_PFIFO_REG(0x180 + ((pfifo)<<2))
+#define NETX_PFIFO_XPEC_ISR(xpec)     NETX_PFIFO_REG(0x400 + ((xpec) << 2))
+
+/*******************************
+ * Dual Port Memory            *
+ *******************************/
+
+/* Registers */
+#define NETX_DPMAS_REG(ofs)               __io(NETX_VA_DPMAS + (ofs))
+#define NETX_DPMAS_SYS_STAT           NETX_DPMAS_REG(0x4d8)
+#define NETX_DPMAS_INT_STAT           NETX_DPMAS_REG(0x4e0)
+#define NETX_DPMAS_INT_EN             NETX_DPMAS_REG(0x4f0)
+#define NETX_DPMAS_IF_CONF0           NETX_DPMAS_REG(0x608)
+#define NETX_DPMAS_IF_CONF1           NETX_DPMAS_REG(0x60c)
+#define NETX_DPMAS_EXT_CONFIG(cs)     NETX_DPMAS_REG(0x610 + 4 * (cs))
+#define NETX_DPMAS_IO_MODE0           NETX_DPMAS_REG(0x620) /* I/O 32..63 */
+#define NETX_DPMAS_DRV_EN0            NETX_DPMAS_REG(0x624)
+#define NETX_DPMAS_DATA0              NETX_DPMAS_REG(0x628)
+#define NETX_DPMAS_IO_MODE1           NETX_DPMAS_REG(0x630) /* I/O 64..84 */
+#define NETX_DPMAS_DRV_EN1            NETX_DPMAS_REG(0x634)
+#define NETX_DPMAS_DATA1              NETX_DPMAS_REG(0x638)
+
+/* Bits */
+#define NETX_DPMAS_INT_EN_GLB_EN         (1<<31)
+#define NETX_DPMAS_INT_EN_MEM_LCK        (1<<30)
+#define NETX_DPMAS_INT_EN_WDG            (1<<29)
+#define NETX_DPMAS_INT_EN_PIO72          (1<<28)
+#define NETX_DPMAS_INT_EN_PIO47          (1<<27)
+#define NETX_DPMAS_INT_EN_PIO40          (1<<26)
+#define NETX_DPMAS_INT_EN_PIO36          (1<<25)
+#define NETX_DPMAS_INT_EN_PIO35          (1<<24)
+
+#define NETX_DPMAS_IF_CONF0_HIF_DISABLED (0<<28)
+#define NETX_DPMAS_IF_CONF0_HIF_EXT_BUS  (1<<28)
+#define NETX_DPMAS_IF_CONF0_HIF_UP_8BIT  (2<<28)
+#define NETX_DPMAS_IF_CONF0_HIF_UP_16BIT (3<<28)
+#define NETX_DPMAS_IF_CONF0_HIF_IO       (4<<28)
+#define NETX_DPMAS_IF_CONF0_WAIT_DRV_PP  (1<<14)
+#define NETX_DPMAS_IF_CONF0_WAIT_DRV_OD  (2<<14)
+#define NETX_DPMAS_IF_CONF0_WAIT_DRV_TRI (3<<14)
+
+#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO35 (1<<26)
+#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO36 (1<<27)
+#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO40 (1<<28)
+#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO47 (1<<29)
+#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO72 (1<<30)
+
+#define NETX_EXT_CONFIG_TALEWIDTH(x) (((x) & 0x7) << 29)
+#define NETX_EXT_CONFIG_TADRHOLD(x)  (((x) & 0x7) << 26)
+#define NETX_EXT_CONFIG_TCSON(x)     (((x) & 0x7) << 23)
+#define NETX_EXT_CONFIG_TRDON(x)     (((x) & 0x7) << 20)
+#define NETX_EXT_CONFIG_TWRON(x)     (((x) & 0x7)  << 17)
+#define NETX_EXT_CONFIG_TWROFF(x)    (((x) & 0x1f) << 12)
+#define NETX_EXT_CONFIG_TRDWRCYC(x)  (((x) & 0x1f) << 7)
+#define NETX_EXT_CONFIG_WAIT_POL     (1<<6)
+#define NETX_EXT_CONFIG_WAIT_EN      (1<<5)
+#define NETX_EXT_CONFIG_NRD_MODE     (1<<4)
+#define NETX_EXT_CONFIG_DS_MODE      (1<<3)
+#define NETX_EXT_CONFIG_NWR_MODE     (1<<2)
+#define NETX_EXT_CONFIG_16BIT        (1<<1)
+#define NETX_EXT_CONFIG_CS_ENABLE    (1<<0)
+
+#define NETX_DPMAS_IO_MODE0_WRL   (1<<13)
+#define NETX_DPMAS_IO_MODE0_WAIT  (1<<14)
+#define NETX_DPMAS_IO_MODE0_READY (1<<15)
+#define NETX_DPMAS_IO_MODE0_CS0   (1<<19)
+#define NETX_DPMAS_IO_MODE0_EXTRD (1<<20)
+
+#define NETX_DPMAS_IO_MODE1_CS2           (1<<15)
+#define NETX_DPMAS_IO_MODE1_CS1           (1<<16)
+#define NETX_DPMAS_IO_MODE1_SAMPLE_NPOR   (0<<30)
+#define NETX_DPMAS_IO_MODE1_SAMPLE_100MHZ (1<<30)
+#define NETX_DPMAS_IO_MODE1_SAMPLE_NPIO36 (2<<30)
+#define NETX_DPMAS_IO_MODE1_SAMPLE_PIO36  (3<<30)
+
+/*******************************
+ * I2C                         *
+ *******************************/
+#define NETX_I2C_REG(ofs)       __io(NETX_VA_I2C, (ofs))
+#define NETX_I2C_CTRL   NETX_I2C_REG(0x0)
+#define NETX_I2C_DATA   NETX_I2C_REG(0x4)
+
+#endif /* __ASM_ARCH_NETX_REGS_H */
diff --git a/arch/arm/mach-netx/include/mach/param.h b/arch/arm/mach-netx/include/mach/param.h
new file mode 100644
index 000000000000..a771459206aa
--- /dev/null
+++ b/arch/arm/mach-netx/include/mach/param.h
@@ -0,0 +1,18 @@
+/*
+ *  arch/arm/mach-netx/include/mach/param.h
+ *
+ * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
diff --git a/arch/arm/mach-netx/include/mach/pfifo.h b/arch/arm/mach-netx/include/mach/pfifo.h
new file mode 100644
index 000000000000..42c59068f8d8
--- /dev/null
+++ b/arch/arm/mach-netx/include/mach/pfifo.h
@@ -0,0 +1,54 @@
+/*
+ * arch/arm/mach-netx/include/mach/pfifo.h
+ *
+ * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+
+#ifndef ASM_ARCH_PFIFO_H
+#define ASM_ARCH_PFIFO_H
+
+static inline int pfifo_push(int no, unsigned int pointer)
+{
+        writel(pointer, NETX_PFIFO_BASE(no));
+        return 0;
+}
+
+static inline unsigned int pfifo_pop(int no)
+{
+        return readl(NETX_PFIFO_BASE(no));
+}
+
+static inline int pfifo_fill_level(int no)
+{
+
+        return readl(NETX_PFIFO_FILL_LEVEL(no));
+}
+
+static inline int pfifo_full(int no)
+{
+        return readl(NETX_PFIFO_FULL) & (1<<no) ? 1 : 0;
+}
+
+static inline int pfifo_empty(int no)
+{
+        return readl(NETX_PFIFO_EMPTY) & (1<<no) ? 1 : 0;
+}
+
+int pfifo_request(unsigned int pfifo_mask);
+void pfifo_free(unsigned int pfifo_mask);
+
+#endif /* ASM_ARCH_PFIFO_H */
diff --git a/arch/arm/mach-netx/include/mach/system.h b/arch/arm/mach-netx/include/mach/system.h
new file mode 100644
index 000000000000..27d8ef8e8e29
--- /dev/null
+++ b/arch/arm/mach-netx/include/mach/system.h
@@ -0,0 +1,38 @@
+/*
+ * arch/arm/mach-netx/include/mach/system.h
+ *
+ * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <asm/io.h>
+#include <mach/hardware.h>
+#include "netx-regs.h"
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        writel(NETX_SYSTEM_RES_CR_FIRMW_RES_EN | NETX_SYSTEM_RES_CR_FIRMW_RES,
+               NETX_SYSTEM_RES_CR);
+}
+
+#endif
+
diff --git a/arch/arm/mach-netx/include/mach/timex.h b/arch/arm/mach-netx/include/mach/timex.h
new file mode 100644
index 000000000000..1120dd0ba393
--- /dev/null
+++ b/arch/arm/mach-netx/include/mach/timex.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/mach-netx/include/mach/timex.h
+ *
+ * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#define CLOCK_TICK_RATE 100000000
diff --git a/arch/arm/mach-netx/include/mach/uncompress.h b/arch/arm/mach-netx/include/mach/uncompress.h
new file mode 100644
index 000000000000..84f91284f612
--- /dev/null
+++ b/arch/arm/mach-netx/include/mach/uncompress.h
@@ -0,0 +1,76 @@
+/*
+ * arch/arm/mach-netx/include/mach/uncompress.h
+ *
+ * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/*
+ * The following code assumes the serial port has already been
+ * initialized by the bootloader.  We search for the first enabled
+ * port in the most probable order.  If you didn't setup a port in
+ * your bootloader then nothing will appear (which might be desired).
+ *
+ * This does not append a newline
+ */
+
+#define REG(x) (*(volatile unsigned long *)(x))
+
+#define UART1_BASE 0x100a00
+#define UART2_BASE 0x100a80
+
+#define UART_DR 0x0
+
+#define UART_CR 0x14
+#define CR_UART_EN (1<<0)
+
+#define UART_FR 0x18
+#define FR_BUSY (1<<3)
+#define FR_TXFF (1<<5)
+
+static void putc(char c)
+{
+        unsigned long base;
+
+        if (REG(UART1_BASE + UART_CR) & CR_UART_EN)
+                base = UART1_BASE;
+        else if (REG(UART2_BASE + UART_CR) & CR_UART_EN)
+                base = UART2_BASE;
+        else
+                return;
+
+        while (REG(base + UART_FR) & FR_TXFF);
+        REG(base + UART_DR) = c;
+}
+
+static inline void flush(void)
+{
+        unsigned long base;
+
+        if (REG(UART1_BASE + UART_CR) & CR_UART_EN)
+                base = UART1_BASE;
+        else if (REG(UART2_BASE + UART_CR) & CR_UART_EN)
+                base = UART2_BASE;
+        else
+                return;
+
+        while (REG(base + UART_FR) & FR_BUSY);
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-netx/include/mach/vmalloc.h b/arch/arm/mach-netx/include/mach/vmalloc.h
new file mode 100644
index 000000000000..25d5cc676e0f
--- /dev/null
+++ b/arch/arm/mach-netx/include/mach/vmalloc.h
@@ -0,0 +1,19 @@
+/*
+ *  arch/arm/mach-netx/include/mach/vmalloc.h
+ *
+ * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
diff --git a/arch/arm/mach-netx/include/mach/xc.h b/arch/arm/mach-netx/include/mach/xc.h
new file mode 100644
index 000000000000..0c0011d4fc2d
--- /dev/null
+++ b/arch/arm/mach-netx/include/mach/xc.h
@@ -0,0 +1,42 @@
+/*
+ *  arch/arm/mach-netx/include/mach/xc.h
+ *
+ * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_XC_H
+#define __ASM_ARCH_XC_H
+
+struct xc {
+        int no;
+        unsigned int type;
+        unsigned int version;
+        void __iomem *xpec_base;
+        void __iomem *xmac_base;
+        void __iomem *sram_base;
+        int irq;
+        struct device *dev;
+};
+
+int xc_reset(struct xc *x);
+int xc_stop(struct xc* x);
+int xc_start(struct xc *x);
+int xc_running(struct xc *x);
+int xc_request_firmware(struct xc* x);
+struct xc* request_xc(int xcno, struct device *dev);
+void free_xc(struct xc *x);
+
+#endif /* __ASM_ARCH_XC_H */
diff --git a/arch/arm/mach-netx/nxdb500.c b/arch/arm/mach-netx/nxdb500.c
index 0cb19450499b..c9b174bc8ccf 100644
--- a/arch/arm/mach-netx/nxdb500.c
+++ b/arch/arm/mach-netx/nxdb500.c
@@ -25,11 +25,11 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/arch/netx-regs.h>
-#include <asm/arch/eth.h>
+#include <mach/netx-regs.h>
+#include <mach/eth.h>
 
 #include "generic.h"
 #include "fb.h"
diff --git a/arch/arm/mach-netx/nxdkn.c b/arch/arm/mach-netx/nxdkn.c
index 848b2f172dd8..15b54c62d60f 100644
--- a/arch/arm/mach-netx/nxdkn.c
+++ b/arch/arm/mach-netx/nxdkn.c
@@ -25,11 +25,11 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/arch/netx-regs.h>
-#include <asm/arch/eth.h>
+#include <mach/netx-regs.h>
+#include <mach/eth.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-netx/nxeb500hmi.c b/arch/arm/mach-netx/nxeb500hmi.c
index cb361eadba5b..1061c01ff679 100644
--- a/arch/arm/mach-netx/nxeb500hmi.c
+++ b/arch/arm/mach-netx/nxeb500hmi.c
@@ -25,11 +25,11 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/arch/netx-regs.h>
-#include <asm/arch/eth.h>
+#include <mach/netx-regs.h>
+#include <mach/eth.h>
 
 #include "generic.h"
 #include "fb.h"
diff --git a/arch/arm/mach-netx/pfifo.c b/arch/arm/mach-netx/pfifo.c
index d0e6b43ff3a0..19ae0a72bea3 100644
--- a/arch/arm/mach-netx/pfifo.c
+++ b/arch/arm/mach-netx/pfifo.c
@@ -22,9 +22,9 @@
 #include <linux/mutex.h>
 
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/netx-regs.h>
-#include <asm/arch/pfifo.h>
+#include <mach/hardware.h>
+#include <mach/netx-regs.h>
+#include <mach/pfifo.h>
 
 static DEFINE_MUTEX(pfifo_lock);
 
diff --git a/arch/arm/mach-netx/time.c b/arch/arm/mach-netx/time.c
index 2c93fd3d03e5..ac8e5bfed691 100644
--- a/arch/arm/mach-netx/time.c
+++ b/arch/arm/mach-netx/time.c
@@ -22,10 +22,10 @@
 #include <linux/irq.h>
 #include <linux/clocksource.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/mach/time.h>
-#include <asm/arch/netx-regs.h>
+#include <mach/netx-regs.h>
 
 /*
  * IRQ handler for the timer
diff --git a/arch/arm/mach-netx/xc.c b/arch/arm/mach-netx/xc.c
index 0ea4d3baf7b1..04c34e82fe6d 100644
--- a/arch/arm/mach-netx/xc.c
+++ b/arch/arm/mach-netx/xc.c
@@ -23,10 +23,10 @@
 #include <linux/mutex.h>
 
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/netx-regs.h>
+#include <mach/hardware.h>
+#include <mach/netx-regs.h>
 
-#include <asm/arch/xc.h>
+#include <mach/xc.h>
 
 static DEFINE_MUTEX(xc_lock);
 
diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.c b/arch/arm/mach-ns9xxx/board-a9m9750dev.c
index 46b4f5a2e7f4..a22a608a7aba 100644
--- a/arch/arm/mach-ns9xxx/board-a9m9750dev.c
+++ b/arch/arm/mach-ns9xxx/board-a9m9750dev.c
@@ -13,12 +13,12 @@
 #include <asm/mach/map.h>
 #include <asm/gpio.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/processor-ns9360.h>
-#include <asm/arch/regs-sys-ns9360.h>
-#include <asm/arch/regs-mem.h>
-#include <asm/arch/regs-bbu.h>
-#include <asm/arch/regs-board-a9m9750dev.h>
+#include <mach/board.h>
+#include <mach/processor-ns9360.h>
+#include <mach/regs-sys-ns9360.h>
+#include <mach/regs-mem.h>
+#include <mach/regs-bbu.h>
+#include <mach/regs-board-a9m9750dev.h>
 
 #include "board-a9m9750dev.h"
 
diff --git a/arch/arm/mach-ns9xxx/gpio-ns9360.c b/arch/arm/mach-ns9xxx/gpio-ns9360.c
index 7bc05a4b45b8..377330c1b250 100644
--- a/arch/arm/mach-ns9xxx/gpio-ns9360.c
+++ b/arch/arm/mach-ns9xxx/gpio-ns9360.c
@@ -14,8 +14,8 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 
-#include <asm/arch/regs-bbu.h>
-#include <asm/arch/processor-ns9360.h>
+#include <mach/regs-bbu.h>
+#include <mach/processor-ns9360.h>
 
 #include "gpio-ns9360.h"
 
diff --git a/arch/arm/mach-ns9xxx/gpio.c b/arch/arm/mach-ns9xxx/gpio.c
index ed4c83389d4a..804c30075960 100644
--- a/arch/arm/mach-ns9xxx/gpio.c
+++ b/arch/arm/mach-ns9xxx/gpio.c
@@ -13,9 +13,9 @@
 #include <linux/spinlock.h>
 #include <linux/module.h>
 
-#include <asm/arch/gpio.h>
-#include <asm/arch/processor.h>
-#include <asm/arch/processor-ns9360.h>
+#include <mach/gpio.h>
+#include <mach/processor.h>
+#include <mach/processor-ns9360.h>
 #include <asm/bug.h>
 #include <asm/types.h>
 #include <asm/bitops.h>
diff --git a/arch/arm/mach-ns9xxx/include/mach/board.h b/arch/arm/mach-ns9xxx/include/mach/board.h
new file mode 100644
index 000000000000..f7e9196eb9ab
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/board.h
@@ -0,0 +1,42 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/board.h
+ *
+ * Copyright (C) 2006,2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_BOARD_H
+#define __ASM_ARCH_BOARD_H
+
+#include <asm/mach-types.h>
+
+#define board_is_a9m9750dev()   (0                      \
+                || machine_is_cc9p9360dev()             \
+                || machine_is_cc9p9750dev()             \
+                )
+
+#define board_is_a9mvali()      (0                      \
+                || machine_is_cc9p9360val()             \
+                || machine_is_cc9p9750val()             \
+                )
+
+#define board_is_jscc9p9210()   (0                      \
+                || machine_is_cc9p9210js()              \
+                )
+
+#define board_is_jscc9p9215()   (0                      \
+                || machine_is_cc9p9215js()              \
+                )
+
+#define board_is_jscc9p9360()   (0                      \
+                || machine_is_cc9p9360js()              \
+                )
+
+#define board_is_uncbas()       (0                      \
+                || machine_is_cc7ucamry()               \
+                )
+
+#endif /* ifndef __ASM_ARCH_BOARD_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/debug-macro.S b/arch/arm/mach-ns9xxx/include/mach/debug-macro.S
new file mode 100644
index 000000000000..c9530fba00aa
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/debug-macro.S
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/debug-macro.S
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#include <mach/hardware.h>
+
+#include <mach/regs-board-a9m9750dev.h>
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1
+                ldreq   \rx, =NS9XXX_CSxSTAT_PHYS(0)
+                ldrne   \rx, =io_p2v(NS9XXX_CSxSTAT_PHYS(0))
+                .endm
+
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-ns9xxx/include/mach/dma.h b/arch/arm/mach-ns9xxx/include/mach/dma.h
new file mode 100644
index 000000000000..3f50d8c9e5c7
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/dma.h
@@ -0,0 +1,14 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/dma.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+#endif /* ifndef __ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/entry-macro.S b/arch/arm/mach-ns9xxx/include/mach/entry-macro.S
new file mode 100644
index 000000000000..71ca0319b547
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/entry-macro.S
@@ -0,0 +1,28 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/entry-macro.S
+ *
+ * Copyright (C) 2006,2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#include <mach/hardware.h>
+#include <mach/regs-sys-common.h>
+
+                .macro  get_irqnr_preamble, base, tmp
+                ldr     \base, =SYS_ISRADDR
+                .endm
+
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                ldr     \irqstat, [\base, #(SYS_ISA - SYS_ISRADDR)]
+                cmp     \irqstat, #0
+                ldrne   \irqnr, [\base]
+                .endm
+
+                .macro  disable_fiq
+                .endm
diff --git a/arch/arm/mach-ns9xxx/include/mach/gpio.h b/arch/arm/mach-ns9xxx/include/mach/gpio.h
new file mode 100644
index 000000000000..5eb349032579
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/gpio.h
@@ -0,0 +1,47 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/gpio.h
+ *
+ * Copyright (C) 2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+*/
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H
+
+#include <asm/errno.h>
+
+int gpio_request(unsigned gpio, const char *label);
+
+void gpio_free(unsigned gpio);
+
+int ns9xxx_gpio_configure(unsigned gpio, int inv, int func);
+
+int gpio_direction_input(unsigned gpio);
+
+int gpio_direction_output(unsigned gpio, int value);
+
+int gpio_get_value(unsigned gpio);
+
+void gpio_set_value(unsigned gpio, int value);
+
+/*
+ * ns9xxx can use gpio pins to trigger an irq, but it's not generic
+ * enough to be supported by the gpio_to_irq/irq_to_gpio interface
+ */
+static inline int gpio_to_irq(unsigned gpio)
+{
+        return -EINVAL;
+}
+
+static inline int irq_to_gpio(unsigned irq)
+{
+        return -EINVAL;
+}
+
+/* get the cansleep() stubs */
+#include <asm-generic/gpio.h>
+
+#endif /* ifndef __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/hardware.h b/arch/arm/mach-ns9xxx/include/mach/hardware.h
new file mode 100644
index 000000000000..6dbb2030f563
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/hardware.h
@@ -0,0 +1,79 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/hardware.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/memory.h>
+
+/*
+ * NetSilicon NS9xxx internal mapping:
+ *
+ * physical                <--> virtual
+ * 0x90000000 - 0x906fffff <--> 0xf9000000 - 0xf96fffff
+ * 0xa0100000 - 0xa0afffff <--> 0xfa100000 - 0xfaafffff
+ */
+#define io_p2v(x)       (0xf0000000 \
+                         + (((x) & 0xf0000000) >> 4) \
+                         + ((x) & 0x00ffffff))
+
+#define io_v2p(x)       ((((x) & 0x0f000000) << 4) \
+                         + ((x) & 0x00ffffff))
+
+#define __REGSHIFT(mask)        ((mask) & (-(mask)))
+
+#define __REGBIT(bit)           ((u32)1 << (bit))
+#define __REGBITS(hbit, lbit)   ((((u32)1 << ((hbit) - (lbit) + 1)) - 1) << (lbit))
+#define __REGVAL(mask, value)   (((value) * __REGSHIFT(mask)) & (mask))
+
+#ifndef __ASSEMBLY__
+
+#  define __REG(x)      ((void __iomem __force *)io_p2v((x)))
+#  define __REG2(x, y)  ((void __iomem __force *)(io_p2v((x)) + 4 * (y)))
+
+#  define __REGSET(var, field, value)                                   \
+        ((var) = (((var) & ~((field) & ~(value))) | (value)))
+
+#  define REGSET(var, reg, field, value)                                \
+        __REGSET(var, reg ## _ ## field, reg ## _ ## field ## _ ## value)
+
+#  define REGSET_IDX(var, reg, field, idx, value)                       \
+        __REGSET(var, reg ## _ ## field((idx)), reg ## _ ## field ## _ ## value((idx)))
+
+#  define REGSETIM(var, reg, field, value)                              \
+        __REGSET(var, reg ## _ ## field, __REGVAL(reg ## _ ## field, (value)))
+
+#  define REGSETIM_IDX(var, reg, field, idx, value)                     \
+        __REGSET(var, reg ## _ ## field((idx)), __REGVAL(reg ## _ ## field((idx)), (value)))
+
+#  define __REGGET(var, field)                                          \
+        (((var) & (field)))
+
+#  define REGGET(var, reg, field)                                       \
+         __REGGET(var, reg ## _ ## field)
+
+#  define REGGET_IDX(var, reg, field, idx)                              \
+         __REGGET(var, reg ## _ ## field((idx)))
+
+#  define REGGETIM(var, reg, field)                                     \
+         __REGGET(var, reg ## _ ## field) / __REGSHIFT(reg ## _ ## field)
+
+#  define REGGETIM_IDX(var, reg, field, idx)                            \
+         __REGGET(var, reg ## _ ## field((idx))) /                      \
+         __REGSHIFT(reg ## _ ## field((idx)))
+
+#else
+
+#  define __REG(x)      io_p2v(x)
+#  define __REG2(x, y)  io_p2v((x) + 4 * (y))
+
+#endif
+
+#endif /* ifndef __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/io.h b/arch/arm/mach-ns9xxx/include/mach/io.h
new file mode 100644
index 000000000000..027bf649645a
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/io.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/io.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT  0xffffffff /* XXX */
+
+#define __io(a)         ((void __iomem *)(a))
+#define __mem_pci(a)    (a)
+#define __mem_isa(a)    (IO_BASE + (a))
+
+#endif /* ifndef __ASM_ARCH_IO_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/irqs.h b/arch/arm/mach-ns9xxx/include/mach/irqs.h
new file mode 100644
index 000000000000..13483949e210
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/irqs.h
@@ -0,0 +1,86 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/irqs.h
+ *
+ * Copyright (C) 2006,2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+/* NetSilicon 9360 */
+#define IRQ_NS9XXX_WATCHDOG     0
+#define IRQ_NS9XXX_AHBBUSERR    1
+#define IRQ_NS9360_BBUSAGG      2
+/* irq 3 is reserved for NS9360 */
+#define IRQ_NS9XXX_ETHRX        4
+#define IRQ_NS9XXX_ETHTX        5
+#define IRQ_NS9XXX_ETHPHY       6
+#define IRQ_NS9360_LCD          7
+#define IRQ_NS9360_SERBRX       8
+#define IRQ_NS9360_SERBTX       9
+#define IRQ_NS9360_SERARX       10
+#define IRQ_NS9360_SERATX       11
+#define IRQ_NS9360_SERCRX       12
+#define IRQ_NS9360_SERCTX       13
+#define IRQ_NS9360_I2C          14
+#define IRQ_NS9360_BBUSDMA      15
+#define IRQ_NS9360_TIMER0       16
+#define IRQ_NS9360_TIMER1       17
+#define IRQ_NS9360_TIMER2       18
+#define IRQ_NS9360_TIMER3       19
+#define IRQ_NS9360_TIMER4       20
+#define IRQ_NS9360_TIMER5       21
+#define IRQ_NS9360_TIMER6       22
+#define IRQ_NS9360_TIMER7       23
+#define IRQ_NS9360_RTC          24
+#define IRQ_NS9360_USBHOST      25
+#define IRQ_NS9360_USBDEVICE    26
+#define IRQ_NS9360_IEEE1284     27
+#define IRQ_NS9XXX_EXT0         28
+#define IRQ_NS9XXX_EXT1         29
+#define IRQ_NS9XXX_EXT2         30
+#define IRQ_NS9XXX_EXT3         31
+
+#define BBUS_IRQ(irq)   (32 + irq)
+
+#define IRQ_BBUS_DMA            BBUS_IRQ(0)
+#define IRQ_BBUS_SERBRX         BBUS_IRQ(2)
+#define IRQ_BBUS_SERBTX         BBUS_IRQ(3)
+#define IRQ_BBUS_SERARX         BBUS_IRQ(4)
+#define IRQ_BBUS_SERATX         BBUS_IRQ(5)
+#define IRQ_BBUS_SERCRX         BBUS_IRQ(6)
+#define IRQ_BBUS_SERCTX         BBUS_IRQ(7)
+#define IRQ_BBUS_SERDRX         BBUS_IRQ(8)
+#define IRQ_BBUS_SERDTX         BBUS_IRQ(9)
+#define IRQ_BBUS_I2C            BBUS_IRQ(10)
+#define IRQ_BBUS_1284           BBUS_IRQ(11)
+#define IRQ_BBUS_UTIL           BBUS_IRQ(12)
+#define IRQ_BBUS_RTC            BBUS_IRQ(13)
+#define IRQ_BBUS_USBHST         BBUS_IRQ(14)
+#define IRQ_BBUS_USBDEV         BBUS_IRQ(15)
+#define IRQ_BBUS_AHBDMA1        BBUS_IRQ(24)
+#define IRQ_BBUS_AHBDMA2        BBUS_IRQ(25)
+
+/*
+ * these Interrupts are specific for the a9m9750dev board.
+ * They are generated by an FPGA that interrupts the CPU on
+ * IRQ_NS9360_EXT2
+ */
+#define FPGA_IRQ(irq)   (64 + irq)
+
+#define IRQ_FPGA_UARTA          FPGA_IRQ(0)
+#define IRQ_FPGA_UARTB          FPGA_IRQ(1)
+#define IRQ_FPGA_UARTC          FPGA_IRQ(2)
+#define IRQ_FPGA_UARTD          FPGA_IRQ(3)
+#define IRQ_FPGA_TOUCH          FPGA_IRQ(4)
+#define IRQ_FPGA_CF             FPGA_IRQ(5)
+#define IRQ_FPGA_CAN0           FPGA_IRQ(6)
+#define IRQ_FPGA_CAN1           FPGA_IRQ(7)
+
+#define NR_IRQS 72
+
+#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/memory.h b/arch/arm/mach-ns9xxx/include/mach/memory.h
new file mode 100644
index 000000000000..649ee6235b94
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/memory.h
@@ -0,0 +1,27 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/memory.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+*/
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/* x in [0..3] */
+#define NS9XXX_CSxSTAT_PHYS(x)  UL(((x) + 4) << 28)
+
+#define NS9XXX_CS0STAT_LENGTH   UL(0x1000)
+#define NS9XXX_CS1STAT_LENGTH   UL(0x1000)
+#define NS9XXX_CS2STAT_LENGTH   UL(0x1000)
+#define NS9XXX_CS3STAT_LENGTH   UL(0x1000)
+
+#define PHYS_OFFSET     UL(0x00000000)
+
+#define __virt_to_bus(x) __virt_to_phys(x)
+#define __bus_to_virt(x) __phys_to_virt(x)
+
+#endif
diff --git a/arch/arm/mach-ns9xxx/include/mach/module.h b/arch/arm/mach-ns9xxx/include/mach/module.h
new file mode 100644
index 000000000000..f851a6b7da6c
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/module.h
@@ -0,0 +1,60 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/module.h
+ *
+ * Copyright (C) 2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_MODULE_H
+#define __ASM_ARCH_MODULE_H
+
+#include <asm/mach-types.h>
+
+#define module_is_cc7ucamry()   (0                      \
+                || machine_is_cc7ucamry()               \
+                )
+
+#define module_is_cc9c()        (0                      \
+                || machine_is_cc9c()                    \
+                )
+
+#define module_is_cc9p9210()    (0                      \
+                || machine_is_cc9p9210()                \
+                || machine_is_cc9p9210js()              \
+                )
+
+#define module_is_cc9p9215()    (0                      \
+                || machine_is_cc9p9215()                \
+                || machine_is_cc9p9215js()              \
+                )
+
+#define module_is_cc9p9360()    (0                      \
+                || machine_is_a9m9360()                 \
+                || machine_is_cc9p9360dev()             \
+                || machine_is_cc9p9360js()              \
+                || machine_is_cc9p9360val()             \
+                )
+
+#define module_is_cc9p9750()    (0                      \
+                || machine_is_a9m9750()                 \
+                || machine_is_cc9p9750dev()             \
+                || machine_is_cc9p9750js()              \
+                || machine_is_cc9p9750val()             \
+                )
+
+#define module_is_ccw9c()       (0                      \
+                || machine_is_ccw9c()                   \
+                )
+
+#define module_is_inc20otter()  (0                      \
+                || machine_is_inc20otter()              \
+                )
+
+#define module_is_otter()       (0                      \
+                || machine_is_otter()                   \
+                )
+
+#endif /* ifndef __ASM_ARCH_MODULE_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/processor-ns9360.h b/arch/arm/mach-ns9xxx/include/mach/processor-ns9360.h
new file mode 100644
index 000000000000..f41deda5129e
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/processor-ns9360.h
@@ -0,0 +1,32 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/processor-ns9360.h
+ *
+ * Copyright (C) 2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_PROCESSORNS9360_H
+#define __ASM_ARCH_PROCESSORNS9360_H
+
+#include <linux/init.h>
+
+void ns9360_reset(char mode);
+
+unsigned long ns9360_systemclock(void) __attribute__((const));
+
+static inline unsigned long ns9360_cpuclock(void) __attribute__((const));
+static inline unsigned long ns9360_cpuclock(void)
+{
+        return ns9360_systemclock() / 2;
+}
+
+void __init ns9360_map_io(void);
+
+extern struct sys_timer ns9360_timer;
+
+int ns9360_gpio_configure(unsigned gpio, int inv, int func);
+
+#endif /* ifndef __ASM_ARCH_PROCESSORNS9360_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/processor.h b/arch/arm/mach-ns9xxx/include/mach/processor.h
new file mode 100644
index 000000000000..9f77f746a386
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/processor.h
@@ -0,0 +1,42 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/processor.h
+ *
+ * Copyright (C) 2006,2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_PROCESSOR_H
+#define __ASM_ARCH_PROCESSOR_H
+
+#include <mach/module.h>
+
+#define processor_is_ns9210()   (0                      \
+                || module_is_cc7ucamry()                \
+                || module_is_cc9p9210()                 \
+                || module_is_inc20otter()               \
+                || module_is_otter()                    \
+                )
+
+#define processor_is_ns9215()   (0                      \
+                || module_is_cc9p9215()                 \
+                )
+
+#define processor_is_ns9360()   (0                      \
+                || module_is_cc9p9360()                 \
+                || module_is_cc9c()                     \
+                || module_is_ccw9c()                    \
+                )
+
+#define processor_is_ns9750()   (0                      \
+                || module_is_cc9p9750()                 \
+                )
+
+#define processor_is_ns921x()   (0                      \
+                || processor_is_ns9210()                \
+                || processor_is_ns9215()                \
+                )
+
+#endif /* ifndef __ASM_ARCH_PROCESSOR_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-bbu.h b/arch/arm/mach-ns9xxx/include/mach/regs-bbu.h
new file mode 100644
index 000000000000..af227c058fb9
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/regs-bbu.h
@@ -0,0 +1,45 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/regs-bbu.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_REGSBBU_H
+#define __ASM_ARCH_REGSBBU_H
+
+#include <mach/hardware.h>
+
+/* BBus Utility */
+
+/* GPIO Configuration Registers block 1 */
+/* NOTE: the HRM starts counting at 1 for the GPIO registers, here the start is
+ * at 0 for each block.  That is, BBU_GCONFb1(0) is GPIO Configuration Register
+ * #1, BBU_GCONFb2(0) is GPIO Configuration Register #8. */
+#define BBU_GCONFb1(x)  __REG2(0x90600010, (x))
+#define BBU_GCONFb2(x)  __REG2(0x90600100, (x))
+
+#define BBU_GCONFx_DIR(m)       __REGBIT(3 + (((m) & 7) << 2))
+#define BBU_GCONFx_DIR_INPUT(m) __REGVAL(BBU_GCONFx_DIR(m), 0)
+#define BBU_GCONFx_DIR_OUTPUT(m)        __REGVAL(BBU_GCONFx_DIR(m), 1)
+#define BBU_GCONFx_INV(m)       __REGBIT(2 + (((m) & 7) << 2))
+#define BBU_GCONFx_INV_NO(m)            __REGVAL(BBU_GCONFx_INV(m), 0)
+#define BBU_GCONFx_INV_YES(m)           __REGVAL(BBU_GCONFx_INV(m), 1)
+#define BBU_GCONFx_FUNC(m)      __REGBITS(1 + (((m) & 7) << 2), ((m) & 7) << 2)
+#define BBU_GCONFx_FUNC_0(m)            __REGVAL(BBU_GCONFx_FUNC(m), 0)
+#define BBU_GCONFx_FUNC_1(m)            __REGVAL(BBU_GCONFx_FUNC(m), 1)
+#define BBU_GCONFx_FUNC_2(m)            __REGVAL(BBU_GCONFx_FUNC(m), 2)
+#define BBU_GCONFx_FUNC_3(m)            __REGVAL(BBU_GCONFx_FUNC(m), 3)
+
+#define BBU_GCTRL1      __REG(0x90600030)
+#define BBU_GCTRL2      __REG(0x90600034)
+#define BBU_GCTRL3      __REG(0x90600120)
+
+#define BBU_GSTAT1      __REG(0x90600040)
+#define BBU_GSTAT2      __REG(0x90600044)
+#define BBU_GSTAT3      __REG(0x90600130)
+
+#endif /* ifndef __ASM_ARCH_REGSBBU_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-board-a9m9750dev.h b/arch/arm/mach-ns9xxx/include/mach/regs-board-a9m9750dev.h
new file mode 100644
index 000000000000..cd1593693f56
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/regs-board-a9m9750dev.h
@@ -0,0 +1,24 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/regs-board-a9m9750dev.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_REGSBOARDA9M9750_H
+#define __ASM_ARCH_REGSBOARDA9M9750_H
+
+#include <mach/hardware.h>
+
+#define FPGA_UARTA_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0))
+#define FPGA_UARTB_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x08)
+#define FPGA_UARTC_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x10)
+#define FPGA_UARTD_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x18)
+
+#define FPGA_IER        __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x50)
+#define FPGA_ISR        __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x60)
+
+#endif /* ifndef __ASM_ARCH_REGSBOARDA9M9750_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-mem.h b/arch/arm/mach-ns9xxx/include/mach/regs-mem.h
new file mode 100644
index 000000000000..f1625bf8cdce
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/regs-mem.h
@@ -0,0 +1,135 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/regs-mem.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_REGSMEM_H
+#define __ASM_ARCH_REGSMEM_H
+
+#include <mach/hardware.h>
+
+/* Memory Module */
+
+/* Control register */
+#define MEM_CTRL        __REG(0xa0700000)
+
+/* Status register */
+#define MEM_STAT        __REG(0xa0700004)
+
+/* Configuration register */
+#define MEM_CONF        __REG(0xa0700008)
+
+/* Dynamic Memory Control register */
+#define MEM_DMCTRL      __REG(0xa0700020)
+
+/* Dynamic Memory Refresh Timer */
+#define MEM_DMRT        __REG(0xa0700024)
+
+/* Dynamic Memory Read Configuration register */
+#define MEM_DMRC        __REG(0xa0700028)
+
+/* Dynamic Memory Precharge Command Period (tRP) */
+#define MEM_DMPCP       __REG(0xa0700030)
+
+/* Dynamic Memory Active to Precharge Command Period (tRAS) */
+#define MEM_DMAPCP      __REG(0xa0700034)
+
+/* Dynamic Memory Self-Refresh Exit Time (tSREX) */
+#define MEM_DMSRET      __REG(0xa0700038)
+
+/* Dynamic Memory Last Data Out to Active Time (tAPR) */
+#define MEM_DMLDOAT     __REG(0xa070003c)
+
+/* Dynamic Memory Data-in to Active Command Time (tDAL or TAPW) */
+#define MEM_DMDIACT     __REG(0xa0700040)
+
+/* Dynamic Memory Write Recovery Time (tWR, tDPL, tRWL, tRDL) */
+#define MEM_DMWRT       __REG(0xa0700044)
+
+/* Dynamic Memory Active to Active Command Period (tRC) */
+#define MEM_DMAACP      __REG(0xa0700048)
+
+/* Dynamic Memory Auto Refresh Period, and Auto Refresh to Active Command Period (tRFC) */
+#define MEM_DMARP       __REG(0xa070004c)
+
+/* Dynamic Memory Exit Self-Refresh to Active Command (tXSR) */
+#define MEM_DMESRAC     __REG(0xa0700050)
+
+/* Dynamic Memory Active Bank A to Active B Time (tRRD) */
+#define MEM_DMABAABT    __REG(0xa0700054)
+
+/* Dynamic Memory Load Mode register to Active Command Time (tMRD) */
+#define MEM_DMLMACT     __REG(0xa0700058)
+
+/* Static Memory Extended Wait */
+#define MEM_SMEW        __REG(0xa0700080)
+
+/* Dynamic Memory Configuration Register x */
+#define MEM_DMCONF(x)   __REG2(0xa0700100, (x) << 3)
+
+/* Dynamic Memory RAS and CAS Delay x */
+#define MEM_DMRCD(x)    __REG2(0xa0700104, (x) << 3)
+
+/* Static Memory Configuration Register x */
+#define MEM_SMC(x)      __REG2(0xa0700200, (x) << 3)
+
+/* Static Memory Configuration Register x: Write protect */
+#define MEM_SMC_PSMC            __REGBIT(20)
+#define MEM_SMC_PSMC_OFF                __REGVAL(MEM_SMC_PSMC, 0)
+#define MEM_SMC_PSMC_ON                 __REGVAL(MEM_SMC_PSMC, 1)
+
+/* Static Memory Configuration Register x: Buffer enable */
+#define MEM_SMC_BSMC            __REGBIT(19)
+#define MEM_SMC_BSMC_OFF                __REGVAL(MEM_SMC_BSMC, 0)
+#define MEM_SMC_BSMC_ON                 __REGVAL(MEM_SMC_BSMC, 1)
+
+/* Static Memory Configuration Register x: Extended Wait */
+#define MEM_SMC_EW              __REGBIT(8)
+#define MEM_SMC_EW_OFF                  __REGVAL(MEM_SMC_EW, 0)
+#define MEM_SMC_EW_ON                   __REGVAL(MEM_SMC_EW, 1)
+
+/* Static Memory Configuration Register x: Byte lane state */
+#define MEM_SMC_PB              __REGBIT(7)
+#define MEM_SMC_PB_0                    __REGVAL(MEM_SMC_PB, 0)
+#define MEM_SMC_PB_1                    __REGVAL(MEM_SMC_PB, 1)
+
+/* Static Memory Configuration Register x: Chip select polarity */
+#define MEM_SMC_PC              __REGBIT(6)
+#define MEM_SMC_PC_AL                   __REGVAL(MEM_SMC_PC, 0)
+#define MEM_SMC_PC_AH                   __REGVAL(MEM_SMC_PC, 1)
+
+/* static memory configuration register x: page mode*/
+#define MEM_SMC_PM              __REGBIT(3)
+#define MEM_SMC_PM_DIS                  __REGVAL(MEM_SMC_PM, 0)
+#define MEM_SMC_PM_ASYNC                __REGVAL(MEM_SMC_PM, 1)
+
+/* static memory configuration register x: Memory width */
+#define MEM_SMC_MW              __REGBITS(1, 0)
+#define MEM_SMC_MW_8                    __REGVAL(MEM_SMC_MW, 0)
+#define MEM_SMC_MW_16                   __REGVAL(MEM_SMC_MW, 1)
+#define MEM_SMC_MW_32                   __REGVAL(MEM_SMC_MW, 2)
+
+/* Static Memory Write Enable Delay x */
+#define MEM_SMWED(x)    __REG2(0xa0700204, (x) << 3)
+
+/* Static Memory Output Enable Delay x */
+#define MEM_SMOED(x)    __REG2(0xa0700208, (x) << 3)
+
+/* Static Memory Read Delay x */
+#define MEM_SMRD(x)     __REG2(0xa070020c, (x) << 3)
+
+/* Static Memory Page Mode Read Delay 0 */
+#define MEM_SMPMRD(x)   __REG2(0xa0700210, (x) << 3)
+
+/* Static Memory Write Delay */
+#define MEM_SMWD(x)     __REG2(0xa0700214, (x) << 3)
+
+/* Static Memory Turn Round Delay x */
+#define MEM_SWT(x)      __REG2(0xa0700218, (x) << 3)
+
+#endif /* ifndef __ASM_ARCH_REGSMEM_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h b/arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h
new file mode 100644
index 000000000000..14f91dfd5736
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h
@@ -0,0 +1,31 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h
+ *
+ * Copyright (C) 2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_REGSSYSCOMMON_H
+#define __ASM_ARCH_REGSSYSCOMMON_H
+#include <mach/hardware.h>
+
+/* Interrupt Vector Address Register Level x */
+#define SYS_IVA(x)      __REG2(0xa09000c4, (x))
+
+/* Interrupt Configuration registers */
+#define SYS_IC(x)       __REG2(0xa0900144, (x))
+
+/* ISRADDR */
+#define SYS_ISRADDR     __REG(0xa0900164)
+
+/* Interrupt Status Active */
+#define SYS_ISA         __REG(0xa0900168)
+
+/* Interrupt Status Raw */
+#define SYS_ISR         __REG(0xa090016c)
+
+#endif /* ifndef __ASM_ARCH_REGSSYSCOMMON_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h b/arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h
new file mode 100644
index 000000000000..8ff254d9901c
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h
@@ -0,0 +1,148 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h
+ *
+ * Copyright (C) 2006,2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_REGSSYSNS9360_H
+#define __ASM_ARCH_REGSSYSNS9360_H
+
+#include <mach/hardware.h>
+
+/* System Control Module */
+
+/* AHB Arbiter Gen Configuration */
+#define SYS_AHBAGENCONF __REG(0xa0900000)
+
+/* BRC */
+#define SYS_BRC(x)      __REG2(0xa0900004, (x))
+
+/* Timer x Reload Count register */
+#define SYS_TRC(x)      __REG2(0xa0900044, (x))
+
+/* Timer x Read register */
+#define SYS_TR(x)       __REG2(0xa0900084, (x))
+
+/* Timer Interrupt Status register */
+#define SYS_TIS         __REG(0xa0900170)
+
+/* PLL Configuration register */
+#define SYS_PLL         __REG(0xa0900188)
+
+/* PLL FS status */
+#define SYS_PLL_FS              __REGBITS(24, 23)
+
+/* PLL ND status */
+#define SYS_PLL_ND              __REGBITS(20, 16)
+
+/* PLL Configuration register: PLL SW change */
+#define SYS_PLL_SWC             __REGBIT(15)
+#define SYS_PLL_SWC_NO                  __REGVAL(SYS_PLL_SWC, 0)
+#define SYS_PLL_SWC_YES                 __REGVAL(SYS_PLL_SWC, 1)
+
+/* Timer x Control register */
+#define SYS_TC(x)       __REG2(0xa0900190, (x))
+
+/* Timer x Control register: Timer enable */
+#define SYS_TCx_TEN             __REGBIT(15)
+#define SYS_TCx_TEN_DIS                 __REGVAL(SYS_TCx_TEN, 0)
+#define SYS_TCx_TEN_EN                  __REGVAL(SYS_TCx_TEN, 1)
+
+/* Timer x Control register: CPU debug mode */
+#define SYS_TCx_TDBG            __REGBIT(10)
+#define SYS_TCx_TDBG_CONT               __REGVAL(SYS_TCx_TDBG, 0)
+#define SYS_TCx_TDBG_STOP               __REGVAL(SYS_TCx_TDBG, 1)
+
+/* Timer x Control register: Interrupt clear */
+#define SYS_TCx_INTC            __REGBIT(9)
+#define SYS_TCx_INTC_UNSET              __REGVAL(SYS_TCx_INTC, 0)
+#define SYS_TCx_INTC_SET                __REGVAL(SYS_TCx_INTC, 1)
+
+/* Timer x Control register: Timer clock select */
+#define SYS_TCx_TLCS            __REGBITS(8, 6)
+#define SYS_TCx_TLCS_CPU                __REGVAL(SYS_TCx_TLCS, 0)       /* CPU clock */
+#define SYS_TCx_TLCS_DIV2               __REGVAL(SYS_TCx_TLCS, 1)       /* CPU clock / 2 */
+#define SYS_TCx_TLCS_DIV4               __REGVAL(SYS_TCx_TLCS, 2)       /* CPU clock / 4 */
+#define SYS_TCx_TLCS_DIV8               __REGVAL(SYS_TCx_TLCS, 3)       /* CPU clock / 8 */
+#define SYS_TCx_TLCS_DIV16              __REGVAL(SYS_TCx_TLCS, 4)       /* CPU clock / 16 */
+#define SYS_TCx_TLCS_DIV32              __REGVAL(SYS_TCx_TLCS, 5)       /* CPU clock / 32 */
+#define SYS_TCx_TLCS_DIV64              __REGVAL(SYS_TCx_TLCS, 6)       /* CPU clock / 64 */
+#define SYS_TCx_TLCS_EXT                __REGVAL(SYS_TCx_TLCS, 7)
+
+/* Timer x Control register: Timer mode */
+#define SYS_TCx_TM              __REGBITS(5, 4)
+#define SYS_TCx_TM_IEE                  __REGVAL(SYS_TCx_TM, 0)         /* Internal timer or external event */
+#define SYS_TCx_TM_ELL                  __REGVAL(SYS_TCx_TM, 1)         /* External low-level, gated timer */
+#define SYS_TCx_TM_EHL                  __REGVAL(SYS_TCx_TM, 2)         /* External high-level, gated timer */
+#define SYS_TCx_TM_CONCAT               __REGVAL(SYS_TCx_TM, 3)         /* Concatenate the lower timer. */
+
+/* Timer x Control register: Interrupt select */
+#define SYS_TCx_INTS            __REGBIT(3)
+#define SYS_TCx_INTS_DIS                __REGVAL(SYS_TCx_INTS, 0)
+#define SYS_TCx_INTS_EN                 __REGVAL(SYS_TCx_INTS, 1)
+
+/* Timer x Control register: Up/down select */
+#define SYS_TCx_UDS             __REGBIT(2)
+#define SYS_TCx_UDS_UP                  __REGVAL(SYS_TCx_UDS, 0)
+#define SYS_TCx_UDS_DOWN                __REGVAL(SYS_TCx_UDS, 1)
+
+/* Timer x Control register: 32- or 16-bit timer */
+#define SYS_TCx_TSZ             __REGBIT(1)
+#define SYS_TCx_TSZ_16                  __REGVAL(SYS_TCx_TSZ, 0)
+#define SYS_TCx_TSZ_32                  __REGVAL(SYS_TCx_TSZ, 1)
+
+/* Timer x Control register: Reload enable */
+#define SYS_TCx_REN             __REGBIT(0)
+#define SYS_TCx_REN_DIS                 __REGVAL(SYS_TCx_REN, 0)
+#define SYS_TCx_REN_EN                  __REGVAL(SYS_TCx_REN, 1)
+
+/* System Memory Chip Select x Dynamic Memory Base */
+#define SYS_SMCSDMB(x)  __REG2(0xa09001d0, (x) << 1)
+
+/* System Memory Chip Select x Dynamic Memory Mask */
+#define SYS_SMCSDMM(x)  __REG2(0xa09001d4, (x) << 1)
+
+/* System Memory Chip Select x Static Memory Base */
+#define SYS_SMCSSMB(x)  __REG2(0xa09001f0, (x) << 1)
+
+/* System Memory Chip Select x Static Memory Base: Chip select x base */
+#define SYS_SMCSSMB_CSxB        __REGBITS(31, 12)
+
+/* System Memory Chip Select x Static Memory Mask */
+#define SYS_SMCSSMM(x)  __REG2(0xa09001f4, (x) << 1)
+
+/* System Memory Chip Select x Static Memory Mask: Chip select x mask */
+#define SYS_SMCSSMM_CSxM        __REGBITS(31, 12)
+
+/* System Memory Chip Select x Static Memory Mask: Chip select x enable */
+#define SYS_SMCSSMM_CSEx        __REGBIT(0)
+#define SYS_SMCSSMM_CSEx_DIS            __REGVAL(SYS_SMCSSMM_CSEx, 0)
+#define SYS_SMCSSMM_CSEx_EN             __REGVAL(SYS_SMCSSMM_CSEx, 1)
+
+/* General purpose, user-defined ID register */
+#define SYS_GENID       __REG(0xa0900210)
+
+/* External Interrupt x Control register */
+#define SYS_EIC(x)      __REG2(0xa0900214, (x))
+
+/* External Interrupt x Control register: Status */
+#define SYS_EIC_STS             __REGBIT(3)
+
+/* External Interrupt x Control register: Clear */
+#define SYS_EIC_CLR             __REGBIT(2)
+
+/* External Interrupt x Control register: Polarity */
+#define SYS_EIC_PLTY            __REGBIT(1)
+#define SYS_EIC_PLTY_AH                 __REGVAL(SYS_EIC_PLTY, 0)
+#define SYS_EIC_PLTY_AL                 __REGVAL(SYS_EIC_PLTY, 1)
+
+/* External Interrupt x Control register: Level edge */
+#define SYS_EIC_LVEDG           __REGBIT(0)
+#define SYS_EIC_LVEDG_LEVEL             __REGVAL(SYS_EIC_LVEDG, 0)
+#define SYS_EIC_LVEDG_EDGE              __REGVAL(SYS_EIC_LVEDG, 1)
+
+#endif /* ifndef __ASM_ARCH_REGSSYSNS9360_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/system.h b/arch/arm/mach-ns9xxx/include/mach/system.h
new file mode 100644
index 000000000000..e2068c57415f
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/system.h
@@ -0,0 +1,35 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/system.h
+ *
+ * Copyright (C) 2006,2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <asm/proc-fns.h>
+#include <mach/processor.h>
+#include <mach/processor-ns9360.h>
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+#ifdef CONFIG_PROCESSOR_NS9360
+        if (processor_is_ns9360())
+                ns9360_reset(mode);
+        else
+#endif
+                BUG();
+
+        BUG();
+}
+
+#endif /* ifndef __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/timex.h b/arch/arm/mach-ns9xxx/include/mach/timex.h
new file mode 100644
index 000000000000..734a8d8bd578
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/timex.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/timex.h
+ *
+ * Copyright (C) 2005-2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+
+/*
+ * value for CLOCK_TICK_RATE stolen from arch/arm/mach-s3c2410/include/mach/timex.h.
+ * See there for an explanation.
+ */
+#define CLOCK_TICK_RATE         12000000
+
+#endif /* ifndef __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/uncompress.h b/arch/arm/mach-ns9xxx/include/mach/uncompress.h
new file mode 100644
index 000000000000..5dbc3c5167c8
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/uncompress.h
@@ -0,0 +1,164 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/uncompress.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+
+#include <asm/io.h>
+
+#define __REG(x)        ((void __iomem __force *)(x))
+
+static void putc_dummy(char c, void __iomem *base)
+{
+        /* nothing */
+}
+
+static void putc_ns9360(char c, void __iomem *base)
+{
+        static int t = 0x10000;
+        do {
+                if (t)
+                        --t;
+
+                if (__raw_readl(base + 8) & (1 << 3)) {
+                        __raw_writeb(c, base + 16);
+                        t = 0x10000;
+                        break;
+                }
+        } while (t);
+}
+
+static void putc_a9m9750dev(char c, void __iomem *base)
+{
+        static int t = 0x10000;
+        do {
+                if (t)
+                        --t;
+
+                if (__raw_readb(base + 5) & (1 << 5)) {
+                        __raw_writeb(c, base);
+                        t = 0x10000;
+                        break;
+                }
+        } while (t);
+
+}
+
+static void putc_ns921x(char c, void __iomem *base)
+{
+        static int t = 0x10000;
+        do {
+                if (t)
+                        --t;
+
+                if (!(__raw_readl(base) & (1 << 11))) {
+                        __raw_writeb(c, base + 0x0028);
+                        t = 0x10000;
+                        break;
+                }
+        } while (t);
+}
+
+#define MSCS __REG(0xA0900184)
+
+#define NS9360_UARTA    __REG(0x90200040)
+#define NS9360_UARTB    __REG(0x90200000)
+#define NS9360_UARTC    __REG(0x90300000)
+#define NS9360_UARTD    __REG(0x90300040)
+
+#define NS9360_UART_ENABLED(base)                                       \
+                (__raw_readl(NS9360_UARTA) & (1 << 31))
+
+#define A9M9750DEV_UARTA        __REG(0x40000000)
+
+#define NS921XSYS_CLOCK __REG(0xa090017c)
+#define NS921X_UARTA    __REG(0x90010000)
+#define NS921X_UARTB    __REG(0x90018000)
+#define NS921X_UARTC    __REG(0x90020000)
+#define NS921X_UARTD    __REG(0x90028000)
+
+#define NS921X_UART_ENABLED(base)                                       \
+                (__raw_readl((base) + 0x1000) & (1 << 29))
+
+static void autodetect(void (**putc)(char, void __iomem *), void __iomem **base)
+{
+        if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x00) {
+                /* ns9360 or ns9750 */
+                if (NS9360_UART_ENABLED(NS9360_UARTA)) {
+                        *putc = putc_ns9360;
+                        *base = NS9360_UARTA;
+                        return;
+                } else if (NS9360_UART_ENABLED(NS9360_UARTB)) {
+                        *putc = putc_ns9360;
+                        *base = NS9360_UARTB;
+                        return;
+                } else if (NS9360_UART_ENABLED(NS9360_UARTC)) {
+                        *putc = putc_ns9360;
+                        *base = NS9360_UARTC;
+                        return;
+                } else if (NS9360_UART_ENABLED(NS9360_UARTD)) {
+                        *putc = putc_ns9360;
+                        *base = NS9360_UARTD;
+                        return;
+                } else if (__raw_readl(__REG(0xa09001f4)) == 0xfffff001) {
+                        *putc = putc_a9m9750dev;
+                        *base = A9M9750DEV_UARTA;
+                        return;
+                }
+        } else if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x02) {
+                /* ns921x */
+                u32 clock = __raw_readl(NS921XSYS_CLOCK);
+
+                if ((clock & (1 << 1)) &&
+                                NS921X_UART_ENABLED(NS921X_UARTA)) {
+                        *putc = putc_ns921x;
+                        *base = NS921X_UARTA;
+                        return;
+                } else if ((clock & (1 << 2)) &&
+                                NS921X_UART_ENABLED(NS921X_UARTB)) {
+                        *putc = putc_ns921x;
+                        *base = NS921X_UARTB;
+                        return;
+                } else if ((clock & (1 << 3)) &&
+                                NS921X_UART_ENABLED(NS921X_UARTC)) {
+                        *putc = putc_ns921x;
+                        *base = NS921X_UARTC;
+                        return;
+                } else if ((clock & (1 << 4)) &&
+                                NS921X_UART_ENABLED(NS921X_UARTD)) {
+                        *putc = putc_ns921x;
+                        *base = NS921X_UARTD;
+                        return;
+                }
+        }
+
+        *putc = putc_dummy;
+}
+
+void (*myputc)(char, void __iomem *);
+void __iomem *base;
+
+static void putc(char c)
+{
+        myputc(c, base);
+}
+
+static void arch_decomp_setup(void)
+{
+        autodetect(&myputc, &base);
+}
+#define arch_decomp_wdog()
+
+static void flush(void)
+{
+        /* nothing */
+}
+
+#endif /* ifndef __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/vmalloc.h b/arch/arm/mach-ns9xxx/include/mach/vmalloc.h
new file mode 100644
index 000000000000..fe964d3bcc47
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/vmalloc.h
@@ -0,0 +1,16 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/vmalloc.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_VMALLOC_H
+#define __ASM_ARCH_VMALLOC_H
+
+#define VMALLOC_END     (0xf0000000)
+
+#endif /* ifndef __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-ns9xxx/irq.c b/arch/arm/mach-ns9xxx/irq.c
index 96de8ebed41d..38260d5f849b 100644
--- a/arch/arm/mach-ns9xxx/irq.c
+++ b/arch/arm/mach-ns9xxx/irq.c
@@ -12,9 +12,9 @@
 #include <linux/kernel_stat.h>
 #include <asm/io.h>
 #include <asm/mach/irq.h>
-#include <asm/arch/regs-sys-common.h>
-#include <asm/arch/irqs.h>
-#include <asm/arch/board.h>
+#include <mach/regs-sys-common.h>
+#include <mach/irqs.h>
+#include <mach/board.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c b/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c
index 7714233fb004..2858417d8d8a 100644
--- a/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c
+++ b/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c
@@ -11,7 +11,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/processor-ns9360.h>
+#include <mach/processor-ns9360.h>
 
 #include "board-a9m9750dev.h"
 #include "generic.h"
diff --git a/arch/arm/mach-ns9xxx/mach-cc9p9360js.c b/arch/arm/mach-ns9xxx/mach-cc9p9360js.c
index bdbd0bb1a0b3..729f68da4293 100644
--- a/arch/arm/mach-ns9xxx/mach-cc9p9360js.c
+++ b/arch/arm/mach-ns9xxx/mach-cc9p9360js.c
@@ -11,7 +11,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/processor-ns9360.h>
+#include <mach/processor-ns9360.h>
 
 #include "board-jscc9p9360.h"
 #include "generic.h"
diff --git a/arch/arm/mach-ns9xxx/plat-serial8250.c b/arch/arm/mach-ns9xxx/plat-serial8250.c
index c9cce9b4e6c9..795b15e8982a 100644
--- a/arch/arm/mach-ns9xxx/plat-serial8250.c
+++ b/arch/arm/mach-ns9xxx/plat-serial8250.c
@@ -11,8 +11,8 @@
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
 
-#include <asm/arch/regs-board-a9m9750dev.h>
-#include <asm/arch/board.h>
+#include <mach/regs-board-a9m9750dev.h>
+#include <mach/board.h>
 
 #define DRIVER_NAME "serial8250"
 
diff --git a/arch/arm/mach-ns9xxx/processor-ns9360.c b/arch/arm/mach-ns9xxx/processor-ns9360.c
index 8ee81b59b35d..abee8338735d 100644
--- a/arch/arm/mach-ns9xxx/processor-ns9360.c
+++ b/arch/arm/mach-ns9xxx/processor-ns9360.c
@@ -14,8 +14,8 @@
 
 #include <asm/page.h>
 #include <asm/mach/map.h>
-#include <asm/arch/processor-ns9360.h>
-#include <asm/arch/regs-sys-ns9360.h>
+#include <mach/processor-ns9360.h>
+#include <mach/regs-sys-ns9360.h>
 
 void ns9360_reset(char mode)
 {
diff --git a/arch/arm/mach-ns9xxx/time-ns9360.c b/arch/arm/mach-ns9xxx/time-ns9360.c
index 66bd58262974..a63424d083d9 100644
--- a/arch/arm/mach-ns9xxx/time-ns9360.c
+++ b/arch/arm/mach-ns9xxx/time-ns9360.c
@@ -15,10 +15,10 @@
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
 
-#include <asm/arch/processor-ns9360.h>
-#include <asm/arch/regs-sys-ns9360.h>
-#include <asm/arch/irqs.h>
-#include <asm/arch/system.h>
+#include <mach/processor-ns9360.h>
+#include <mach/regs-sys-ns9360.h>
+#include <mach/irqs.h>
+#include <mach/system.h>
 #include "generic.h"
 
 #define TIMER_CLOCKSOURCE 0
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index 46488c276654..2e618391cc51 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -17,18 +17,18 @@
 #include <linux/input.h>
 #include <linux/platform_device.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <asm/arch/board-ams-delta.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/keypad.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/usb.h>
-#include <asm/arch/board.h>
-#include <asm/arch/common.h>
+#include <mach/board-ams-delta.h>
+#include <mach/gpio.h>
+#include <mach/keypad.h>
+#include <mach/mux.h>
+#include <mach/usb.h>
+#include <mach/board.h>
+#include <mach/common.h>
 
 static u8 ams_delta_latch1_reg;
 static u16 ams_delta_latch2_reg;
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 8583e80a3ca9..db789461fca4 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -20,21 +20,21 @@
 #include <linux/mtd/partitions.h>
 #include <linux/input.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 #include <asm/mach/map.h>
 
-#include <asm/arch/tc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/fpga.h>
-#include <asm/arch/nand.h>
-#include <asm/arch/keypad.h>
-#include <asm/arch/common.h>
-#include <asm/arch/board.h>
-#include <asm/arch/board-fsample.h>
+#include <mach/tc.h>
+#include <mach/gpio.h>
+#include <mach/mux.h>
+#include <mach/fpga.h>
+#include <mach/nand.h>
+#include <mach/keypad.h>
+#include <mach/common.h>
+#include <mach/board.h>
+#include <mach/board-fsample.h>
 
 static int fsample_keymap[] = {
         KEY(0,0,KEY_UP),
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
index d90266243134..7d2670205373 100644
--- a/arch/arm/mach-omap1/board-generic.c
+++ b/arch/arm/mach-omap1/board-generic.c
@@ -17,16 +17,16 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <asm/arch/gpio.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/usb.h>
-#include <asm/arch/board.h>
-#include <asm/arch/common.h>
+#include <mach/gpio.h>
+#include <mach/mux.h>
+#include <mach/usb.h>
+#include <mach/board.h>
+#include <mach/common.h>
 
 static void __init omap_generic_init_irq(void)
 {
diff --git a/arch/arm/mach-omap1/board-h2-mmc.c b/arch/arm/mach-omap1/board-h2-mmc.c
index 6fdc78406b21..ab9ee5820c48 100644
--- a/arch/arm/mach-omap1/board-h2-mmc.c
+++ b/arch/arm/mach-omap1/board-h2-mmc.c
@@ -12,8 +12,8 @@
  * published by the Free Software Foundation.
  */
 
-#include <asm/arch/mmc.h>
-#include <asm/arch/gpio.h>
+#include <mach/mmc.h>
+#include <mach/gpio.h>
 
 #ifdef CONFIG_MMC_OMAP
 static int slot_cover_open;
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index f69e3b5ad546..3b65914b9141 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -29,7 +29,7 @@
 #include <linux/input.h>
 #include <linux/i2c/tps65010.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/gpio.h>
 
 #include <asm/mach-types.h>
@@ -37,16 +37,16 @@
 #include <asm/mach/flash.h>
 #include <asm/mach/map.h>
 
-#include <asm/arch/gpio-switch.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/tc.h>
-#include <asm/arch/nand.h>
-#include <asm/arch/irda.h>
-#include <asm/arch/usb.h>
-#include <asm/arch/keypad.h>
-#include <asm/arch/common.h>
-#include <asm/arch/mcbsp.h>
-#include <asm/arch/omap-alsa.h>
+#include <mach/gpio-switch.h>
+#include <mach/mux.h>
+#include <mach/tc.h>
+#include <mach/nand.h>
+#include <mach/irda.h>
+#include <mach/usb.h>
+#include <mach/keypad.h>
+#include <mach/common.h>
+#include <mach/mcbsp.h>
+#include <mach/omap-alsa.h>
 
 static int h2_keymap[] = {
         KEY(0, 0, KEY_LEFT),
diff --git a/arch/arm/mach-omap1/board-h3-mmc.c b/arch/arm/mach-omap1/board-h3-mmc.c
index 66ecc437928f..36085819098c 100644
--- a/arch/arm/mach-omap1/board-h3-mmc.c
+++ b/arch/arm/mach-omap1/board-h3-mmc.c
@@ -12,8 +12,8 @@
  * published by the Free Software Foundation.
  */
 
-#include <asm/arch/mmc.h>
-#include <asm/arch/gpio.h>
+#include <mach/mmc.h>
+#include <mach/gpio.h>
 
 #ifdef CONFIG_MMC_OMAP
 static int slot_cover_open;
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index 1ae3826e27c1..2ced6d9984d2 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -31,7 +31,7 @@
 
 #include <asm/setup.h>
 #include <asm/page.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/gpio.h>
 
 #include <asm/mach-types.h>
@@ -39,18 +39,18 @@
 #include <asm/mach/flash.h>
 #include <asm/mach/map.h>
 
-#include <asm/arch/gpioexpander.h>
-#include <asm/arch/irqs.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/tc.h>
-#include <asm/arch/nand.h>
-#include <asm/arch/irda.h>
-#include <asm/arch/usb.h>
-#include <asm/arch/keypad.h>
-#include <asm/arch/dma.h>
-#include <asm/arch/common.h>
-#include <asm/arch/mcbsp.h>
-#include <asm/arch/omap-alsa.h>
+#include <mach/gpioexpander.h>
+#include <mach/irqs.h>
+#include <mach/mux.h>
+#include <mach/tc.h>
+#include <mach/nand.h>
+#include <mach/irda.h>
+#include <mach/usb.h>
+#include <mach/keypad.h>
+#include <mach/dma.h>
+#include <mach/common.h>
+#include <mach/mcbsp.h>
+#include <mach/omap-alsa.h>
 
 #define H3_TS_GPIO      48
 
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index 667c7204f823..cbc11be5cd2a 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -24,21 +24,21 @@
 #include <linux/mtd/partitions.h>
 #include <linux/input.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 #include <asm/mach/map.h>
 
-#include <asm/arch/mux.h>
-#include <asm/arch/fpga.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/tc.h>
-#include <asm/arch/usb.h>
-#include <asm/arch/keypad.h>
-#include <asm/arch/common.h>
-#include <asm/arch/mcbsp.h>
-#include <asm/arch/omap-alsa.h>
+#include <mach/mux.h>
+#include <mach/fpga.h>
+#include <mach/gpio.h>
+#include <mach/tc.h>
+#include <mach/usb.h>
+#include <mach/keypad.h>
+#include <mach/common.h>
+#include <mach/mcbsp.h>
+#include <mach/omap-alsa.h>
 
 static int innovator_keymap[] = {
         KEY(0, 0, KEY_F1),
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index 2826214d3517..38d9783ac6d6 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -20,21 +20,21 @@
 #include <linux/workqueue.h>
 #include <linux/delay.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <asm/arch/gpio.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/usb.h>
-#include <asm/arch/board.h>
-#include <asm/arch/keypad.h>
-#include <asm/arch/common.h>
-#include <asm/arch/dsp_common.h>
-#include <asm/arch/aic23.h>
-#include <asm/arch/omapfb.h>
-#include <asm/arch/lcd_mipid.h>
+#include <mach/gpio.h>
+#include <mach/mux.h>
+#include <mach/usb.h>
+#include <mach/board.h>
+#include <mach/keypad.h>
+#include <mach/common.h>
+#include <mach/dsp_common.h>
+#include <mach/aic23.h>
+#include <mach/omapfb.h>
+#include <mach/lcd_mipid.h>
 
 #define ADS7846_PENDOWN_GPIO    15
 
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 4d8cd9fcb690..3e766e49f7cc 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -39,7 +39,7 @@
 
 #include <linux/i2c/tps65010.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/gpio.h>
 
 #include <asm/mach-types.h>
@@ -47,12 +47,12 @@
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 
-#include <asm/arch/usb.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/tc.h>
-#include <asm/arch/common.h>
-#include <asm/arch/mcbsp.h>
-#include <asm/arch/omap-alsa.h>
+#include <mach/usb.h>
+#include <mach/mux.h>
+#include <mach/tc.h>
+#include <mach/common.h>
+#include <mach/mcbsp.h>
+#include <mach/omap-alsa.h>
 
 static struct mtd_partition osk_partitions[] = {
         /* bootloader (U-Boot, etc) in first sector */
@@ -340,7 +340,7 @@ static struct omap_board_config_kernel osk_config[] __initdata = {
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
 
-#include <asm/arch/keypad.h>
+#include <mach/keypad.h>
 
 static const int osk_keymap[] = {
         /* KEY(col, row, code) */
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 6855255f5c64..b58043644a6f 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -27,23 +27,23 @@
 #include <linux/interrupt.h>
 #include <linux/apm-emulation.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 
-#include <asm/arch/gpio.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/usb.h>
-#include <asm/arch/tc.h>
-#include <asm/arch/dma.h>
-#include <asm/arch/board.h>
-#include <asm/arch/irda.h>
-#include <asm/arch/keypad.h>
-#include <asm/arch/common.h>
-#include <asm/arch/mcbsp.h>
-#include <asm/arch/omap-alsa.h>
+#include <mach/gpio.h>
+#include <mach/mux.h>
+#include <mach/usb.h>
+#include <mach/tc.h>
+#include <mach/dma.h>
+#include <mach/board.h>
+#include <mach/irda.h>
+#include <mach/keypad.h>
+#include <mach/common.h>
+#include <mach/mcbsp.h>
+#include <mach/omap-alsa.h>
 
 static void __init omap_palmte_init_irq(void)
 {
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index 96896f83b5f4..40f9860a09df 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -23,24 +23,24 @@
 #include <linux/mtd/partitions.h>
 #include <linux/leds.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 
-#include <asm/arch/led.h>
-#include <asm/arch/mcbsp.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/usb.h>
-#include <asm/arch/dma.h>
-#include <asm/arch/tc.h>
-#include <asm/arch/board.h>
-#include <asm/arch/irda.h>
-#include <asm/arch/keypad.h>
-#include <asm/arch/common.h>
-#include <asm/arch/omap-alsa.h>
+#include <mach/led.h>
+#include <mach/mcbsp.h>
+#include <mach/gpio.h>
+#include <mach/mux.h>
+#include <mach/usb.h>
+#include <mach/dma.h>
+#include <mach/tc.h>
+#include <mach/board.h>
+#include <mach/irda.h>
+#include <mach/keypad.h>
+#include <mach/common.h>
+#include <mach/omap-alsa.h>
 
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index b8ccdb205002..e719294250b1 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -26,23 +26,23 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 
-#include <asm/arch/mcbsp.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/usb.h>
-#include <asm/arch/dma.h>
-#include <asm/arch/tc.h>
-#include <asm/arch/board.h>
-#include <asm/arch/irda.h>
-#include <asm/arch/keypad.h>
-#include <asm/arch/common.h>
-#include <asm/arch/omap-alsa.h>
+#include <mach/mcbsp.h>
+#include <mach/gpio.h>
+#include <mach/mux.h>
+#include <mach/usb.h>
+#include <mach/dma.h>
+#include <mach/tc.h>
+#include <mach/board.h>
+#include <mach/irda.h>
+#include <mach/keypad.h>
+#include <mach/common.h>
+#include <mach/omap-alsa.h>
 
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index 9857fc9e1563..b715917bfdaf 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -20,20 +20,20 @@
 #include <linux/mtd/partitions.h>
 #include <linux/input.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 #include <asm/mach/map.h>
 
-#include <asm/arch/tc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/fpga.h>
-#include <asm/arch/nand.h>
-#include <asm/arch/keypad.h>
-#include <asm/arch/common.h>
-#include <asm/arch/board.h>
+#include <mach/tc.h>
+#include <mach/gpio.h>
+#include <mach/mux.h>
+#include <mach/fpga.h>
+#include <mach/nand.h>
+#include <mach/keypad.h>
+#include <mach/common.h>
+#include <mach/board.h>
 
 static int p2_keymap[] = {
         KEY(0,0,KEY_UP),
diff --git a/arch/arm/mach-omap1/board-sx1-mmc.c b/arch/arm/mach-omap1/board-sx1-mmc.c
index 8c93d47719e8..0be4ebaa2842 100644
--- a/arch/arm/mach-omap1/board-sx1-mmc.c
+++ b/arch/arm/mach-omap1/board-sx1-mmc.c
@@ -12,9 +12,9 @@
  * published by the Free Software Foundation.
  */
 
-#include <asm/arch/hardware.h>
-#include <asm/arch/mmc.h>
-#include <asm/arch/gpio.h>
+#include <mach/hardware.h>
+#include <mach/mmc.h>
+#include <mach/gpio.h>
 
 #ifdef CONFIG_MMC_OMAP
 static int slot_cover_open;
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 0c2c42b2ec6d..130bcc6fd082 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -26,22 +26,22 @@
 #include <linux/i2c.h>
 #include <linux/errno.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 #include <asm/mach/map.h>
 
-#include <asm/arch/gpio.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/irda.h>
-#include <asm/arch/usb.h>
-#include <asm/arch/tc.h>
-#include <asm/arch/board.h>
-#include <asm/arch/common.h>
-#include <asm/arch/mcbsp.h>
-#include <asm/arch/omap-alsa.h>
-#include <asm/arch/keypad.h>
+#include <mach/gpio.h>
+#include <mach/mux.h>
+#include <mach/irda.h>
+#include <mach/usb.h>
+#include <mach/tc.h>
+#include <mach/board.h>
+#include <mach/common.h>
+#include <mach/mcbsp.h>
+#include <mach/omap-alsa.h>
+#include <mach/keypad.h>
 
 /* Write to I2C device */
 int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value)
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 902b12ed8c13..213b48787102 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -22,17 +22,17 @@
 #include <linux/serial_8250.h>
 #include <linux/serial_reg.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 #include <asm/mach/map.h>
 
-#include <asm/arch/common.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/tc.h>
-#include <asm/arch/usb.h>
+#include <mach/common.h>
+#include <mach/gpio.h>
+#include <mach/mux.h>
+#include <mach/tc.h>
+#include <mach/usb.h>
 
 static struct plat_serial8250_port voiceblue_ports[] = {
         {
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 4ea2933f887d..5965cf09f8c4 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -21,10 +21,10 @@
 #include <asm/io.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/cpu.h>
-#include <asm/arch/usb.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sram.h>
+#include <mach/cpu.h>
+#include <mach/usb.h>
+#include <mach/clock.h>
+#include <mach/sram.h>
 
 #include "clock.h"
 
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index 9ad8f927ef13..ab708d4c597e 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -14,14 +14,14 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/mach/map.h>
 
-#include <asm/arch/tc.h>
-#include <asm/arch/board.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/gpio.h>
+#include <mach/tc.h>
+#include <mach/board.h>
+#include <mach/mux.h>
+#include <mach/gpio.h>
 
 /*-------------------------------------------------------------------------*/
 
diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c
index b9649c75836d..4449d86095f6 100644
--- a/arch/arm/mach-omap1/fpga.c
+++ b/arch/arm/mach-omap1/fpga.c
@@ -22,13 +22,13 @@
 #include <linux/device.h>
 #include <linux/errno.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/fpga.h>
-#include <asm/arch/gpio.h>
+#include <mach/fpga.h>
+#include <mach/gpio.h>
 
 static void fpga_mask_irq(unsigned int irq)
 {
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
index 81c4e738506c..2b9750b200ce 100644
--- a/arch/arm/mach-omap1/io.c
+++ b/arch/arm/mach-omap1/io.c
@@ -15,8 +15,8 @@
 #include <asm/tlb.h>
 #include <asm/mach/map.h>
 #include <asm/io.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/tc.h>
+#include <mach/mux.h>
+#include <mach/tc.h>
 
 extern int omap1_clk_init(void);
 extern void omap_check_revision(void);
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index 061f073265f7..0ec6c1ec4250 100644
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -41,11 +41,11 @@
 #include <linux/sched.h>
 #include <linux/interrupt.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/cpu.h>
+#include <mach/gpio.h>
+#include <mach/cpu.h>
 
 #include <asm/io.h>
 
diff --git a/arch/arm/mach-omap1/leds-h2p2-debug.c b/arch/arm/mach-omap1/leds-h2p2-debug.c
index c9e894a66e26..610f51f18741 100644
--- a/arch/arm/mach-omap1/leds-h2p2-debug.c
+++ b/arch/arm/mach-omap1/leds-h2p2-debug.c
@@ -14,13 +14,13 @@
 #include <linux/sched.h>
 
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/system.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/fpga.h>
-#include <asm/arch/gpio.h>
+#include <mach/fpga.h>
+#include <mach/gpio.h>
 
 #include "leds.h"
 
diff --git a/arch/arm/mach-omap1/leds-innovator.c b/arch/arm/mach-omap1/leds-innovator.c
index 82eacb005e2f..9b99c2894623 100644
--- a/arch/arm/mach-omap1/leds-innovator.c
+++ b/arch/arm/mach-omap1/leds-innovator.c
@@ -3,7 +3,7 @@
  */
 #include <linux/init.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/system.h>
 
diff --git a/arch/arm/mach-omap1/leds-osk.c b/arch/arm/mach-omap1/leds-osk.c
index 1cd94e0c9b3d..98e789622dfd 100644
--- a/arch/arm/mach-omap1/leds-osk.c
+++ b/arch/arm/mach-omap1/leds-osk.c
@@ -5,11 +5,11 @@
  */
 #include <linux/init.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/system.h>
 
-#include <asm/arch/gpio.h>
+#include <mach/gpio.h>
 
 #include "leds.h"
 
diff --git a/arch/arm/mach-omap1/leds.c b/arch/arm/mach-omap1/leds.c
index 3f9dcac4fd41..6cdad93c4a00 100644
--- a/arch/arm/mach-omap1/leds.c
+++ b/arch/arm/mach-omap1/leds.c
@@ -9,8 +9,8 @@
 #include <asm/leds.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/gpio.h>
-#include <asm/arch/mux.h>
+#include <mach/gpio.h>
+#include <mach/mux.h>
 
 #include "leds.h"
 
diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c
index bad1e7152d8e..af44eab1ed24 100644
--- a/arch/arm/mach-omap1/mailbox.c
+++ b/arch/arm/mach-omap1/mailbox.c
@@ -13,8 +13,8 @@
 #include <linux/resource.h>
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
-#include <asm/arch/mailbox.h>
-#include <asm/arch/irqs.h>
+#include <mach/mailbox.h>
+#include <mach/irqs.h>
 #include <asm/io.h>
 
 #define MAILBOX_ARM2DSP1                0x00
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index 2d2c2522b048..826010d5d014 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -17,11 +17,11 @@
 #include <linux/io.h>
 #include <linux/platform_device.h>
 
-#include <asm/arch/dma.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/mcbsp.h>
-#include <asm/arch/dsp_common.h>
+#include <mach/dma.h>
+#include <mach/mux.h>
+#include <mach/cpu.h>
+#include <mach/mcbsp.h>
+#include <mach/dsp_common.h>
 
 #define DPS_RSTCT2_PER_EN       (1 << 0)
 #define DSP_RSTCT2_WD_PER_EN    (1 << 1)
diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c
index e207bf7cb853..898516e362e7 100644
--- a/arch/arm/mach-omap1/mux.c
+++ b/arch/arm/mach-omap1/mux.c
@@ -28,7 +28,7 @@
 #include <asm/io.h>
 #include <linux/spinlock.h>
 
-#include <asm/arch/mux.h>
+#include <mach/mux.h>
 
 #ifdef CONFIG_OMAP_MUX
 
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index bb06de92daee..63c4ea18b1ca 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -48,15 +48,15 @@
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/cpu.h>
-#include <asm/arch/irqs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sram.h>
-#include <asm/arch/tc.h>
-#include <asm/arch/pm.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/dma.h>
-#include <asm/arch/dmtimer.h>
+#include <mach/cpu.h>
+#include <mach/irqs.h>
+#include <mach/clock.h>
+#include <mach/sram.h>
+#include <mach/tc.h>
+#include <mach/pm.h>
+#include <mach/mux.h>
+#include <mach/dma.h>
+#include <mach/dmtimer.h>
 
 static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
 static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c
index 10a4fe88b2fd..0e25a996bb4c 100644
--- a/arch/arm/mach-omap1/serial.c
+++ b/arch/arm/mach-omap1/serial.c
@@ -22,12 +22,12 @@
 #include <asm/io.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/fpga.h>
+#include <mach/board.h>
+#include <mach/mux.h>
+#include <mach/gpio.h>
+#include <mach/fpga.h>
 #ifdef CONFIG_PM
-#include <asm/arch/pm.h>
+#include <mach/pm.h>
 #endif
 
 static struct clk * uart1_ck;
diff --git a/arch/arm/mach-omap1/sleep.S b/arch/arm/mach-omap1/sleep.S
index 68f5b39030b6..f3eac932092d 100644
--- a/arch/arm/mach-omap1/sleep.S
+++ b/arch/arm/mach-omap1/sleep.S
@@ -34,8 +34,8 @@
 
 #include <linux/linkage.h>
 #include <asm/assembler.h>
-#include <asm/arch/io.h>
-#include <asm/arch/pm.h>
+#include <mach/io.h>
+#include <mach/pm.h>
 
                 .text
 
diff --git a/arch/arm/mach-omap1/sram.S b/arch/arm/mach-omap1/sram.S
index 776c89c7c5a4..261cdc48228b 100644
--- a/arch/arm/mach-omap1/sram.S
+++ b/arch/arm/mach-omap1/sram.S
@@ -10,8 +10,8 @@
 
 #include <linux/linkage.h>
 #include <asm/assembler.h>
-#include <asm/arch/io.h>
-#include <asm/arch/hardware.h>
+#include <mach/io.h>
+#include <mach/hardware.h>
 
         .text
 
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index ae8910381e3b..e54708595ecf 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -45,7 +45,7 @@
 #include <linux/clockchips.h>
 
 #include <asm/system.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/leds.h>
 #include <asm/irq.h>
diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c
index f358fe9548f3..e67760189d14 100644
--- a/arch/arm/mach-omap1/timer32k.c
+++ b/arch/arm/mach-omap1/timer32k.c
@@ -46,13 +46,13 @@
 #include <linux/clockchips.h>
 
 #include <asm/system.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/leds.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
-#include <asm/arch/dmtimer.h>
+#include <mach/dmtimer.h>
 
 struct sys_timer omap_timer;
 
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 8911f8e675c4..d4d6385cad7c 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -22,17 +22,17 @@
 #include <linux/err.h>
 #include <linux/clk.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 
-#include <asm/arch/gpio.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/board.h>
-#include <asm/arch/common.h>
-#include <asm/arch/gpmc.h>
+#include <mach/gpio.h>
+#include <mach/mux.h>
+#include <mach/board.h>
+#include <mach/common.h>
+#include <mach/gpmc.h>
 
 #include <asm/io.h>
 
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 170c9681d093..989ad152d7f8 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -29,19 +29,19 @@
 #include <linux/err.h>
 #include <linux/clk.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 
-#include <asm/arch/gpio.h>
-#include <asm/arch/led.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/usb.h>
-#include <asm/arch/board.h>
-#include <asm/arch/common.h>
-#include <asm/arch/gpmc.h>
-#include <asm/arch/control.h>
+#include <mach/gpio.h>
+#include <mach/led.h>
+#include <mach/mux.h>
+#include <mach/usb.h>
+#include <mach/board.h>
+#include <mach/common.h>
+#include <mach/gpmc.h>
+#include <mach/control.h>
 
 /* LED & Switch macros */
 #define LED0_GPIO13             13
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 68ec3a32387a..9ba097868e72 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -20,16 +20,16 @@
 #include <linux/init.h>
 #include <linux/device.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <asm/arch/gpio.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/usb.h>
-#include <asm/arch/board.h>
-#include <asm/arch/common.h>
+#include <mach/gpio.h>
+#include <mach/mux.h>
+#include <mach/usb.h>
+#include <mach/board.h>
+#include <mach/common.h>
 
 static void __init omap_generic_init_irq(void)
 {
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index a32b475dc09c..9e2624ca70a2 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -22,24 +22,24 @@
 #include <linux/err.h>
 #include <linux/clk.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 
-#include <asm/arch/control.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/gpioexpander.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/usb.h>
-#include <asm/arch/irda.h>
-#include <asm/arch/board.h>
-#include <asm/arch/common.h>
-#include <asm/arch/keypad.h>
-#include <asm/arch/menelaus.h>
-#include <asm/arch/dma.h>
-#include <asm/arch/gpmc.h>
+#include <mach/control.h>
+#include <mach/gpio.h>
+#include <mach/gpioexpander.h>
+#include <mach/mux.h>
+#include <mach/usb.h>
+#include <mach/irda.h>
+#include <mach/board.h>
+#include <mach/common.h>
+#include <mach/keypad.h>
+#include <mach/menelaus.h>
+#include <mach/dma.h>
+#include <mach/gpmc.h>
 
 #include <asm/io.h>
 
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 15675bce8012..1d891e4a6933 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -25,9 +25,9 @@
 
 #include <asm/io.h>
 
-#include <asm/arch/clock.h>
-#include <asm/arch/sram.h>
-#include <asm/arch/cpu.h>
+#include <mach/clock.h>
+#include <mach/sram.h>
+#include <mach/cpu.h>
 #include <asm/div64.h>
 
 #include "memory.h"
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 3cd37cb57c5a..626e5fa93b6a 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -16,7 +16,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
 
-#include <asm/arch/clock.h>
+#include <mach/clock.h>
 
 /* The maximum error between a target DPLL rate and the rounded rate in Hz */
 #define DEFAULT_DPLL_RATE_TOLERANCE     50000
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index aa567876651d..295e671e9cfd 100644
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -28,8 +28,8 @@
 #include <linux/io.h>
 #include <linux/cpufreq.h>
 
-#include <asm/arch/clock.h>
-#include <asm/arch/sram.h>
+#include <mach/clock.h>
+#include <mach/sram.h>
 #include <asm/div64.h>
 #include <asm/bitops.h>
 
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 4263099b1ad3..3ff74952f835 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -26,8 +26,8 @@
 #include <linux/io.h>
 #include <linux/limits.h>
 
-#include <asm/arch/clock.h>
-#include <asm/arch/sram.h>
+#include <mach/clock.h>
+#include <mach/sram.h>
 #include <asm/div64.h>
 #include <asm/bitops.h>
 
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 05757eb032bc..ec664457a11a 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -19,7 +19,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
 
-#include <asm/arch/control.h>
+#include <mach/control.h>
 
 #include "clock.h"
 #include "cm.h"
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 51f70300996f..5f3aad977842 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -15,8 +15,8 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 
-#include <asm/arch/common.h>
-#include <asm/arch/control.h>
+#include <mach/common.h>
+#include <mach/control.h>
 
 static void __iomem *omap2_ctrl_base;
 
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index a6acdcdbb63c..7a7f02559075 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -14,15 +14,15 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
 
-#include <asm/arch/tc.h>
-#include <asm/arch/board.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/gpio.h>
+#include <mach/tc.h>
+#include <mach/board.h>
+#include <mach/mux.h>
+#include <mach/gpio.h>
 
 #if     defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
 
@@ -142,7 +142,7 @@ static inline void omap_init_sti(void) {}
 
 #if defined(CONFIG_SPI_OMAP24XX)
 
-#include <asm/arch/mcspi.h>
+#include <mach/mcspi.h>
 
 #define OMAP2_MCSPI1_BASE               0x48098000
 #define OMAP2_MCSPI2_BASE               0x4809a000
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index dbf68dc50ae2..f51d69bc457d 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -18,7 +18,7 @@
 
 #include <asm/io.h>
 #include <asm/mach-types.h>
-#include <asm/arch/gpmc.h>
+#include <mach/gpmc.h>
 
 #undef DEBUG
 
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index dff4b16cead6..a5d4526ac4d6 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -17,8 +17,8 @@
 
 #include <asm/io.h>
 
-#include <asm/arch/control.h>
-#include <asm/arch/cpu.h>
+#include <mach/control.h>
+#include <mach/cpu.h>
 
 #if defined(CONFIG_ARCH_OMAP2420)
 #define TAP_BASE        io_p2v(0x48014000)
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 69c8174f3aac..987351f07d7b 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -21,8 +21,8 @@
 
 #include <asm/mach/map.h>
 
-#include <asm/arch/mux.h>
-#include <asm/arch/omapfb.h>
+#include <mach/mux.h>
+#include <mach/omapfb.h>
 
 extern void omap_sram_init(void);
 extern int omap2_clk_init(void);
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 6d4c4bf82ad5..9ef15b31d8fc 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -13,7 +13,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach/irq.h>
 #include <asm/irq.h>
 #include <asm/io.h>
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 4799561c5a9e..a480b96948e4 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -14,8 +14,8 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/platform_device.h>
-#include <asm/arch/mailbox.h>
-#include <asm/arch/irqs.h>
+#include <mach/mailbox.h>
+#include <mach/irqs.h>
 #include <asm/io.h>
 
 #define MAILBOX_REVISION                0x00
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 17cf199d1130..27eb6e3ca926 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -17,10 +17,10 @@
 #include <linux/io.h>
 #include <linux/platform_device.h>
 
-#include <asm/arch/dma.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/mcbsp.h>
+#include <mach/dma.h>
+#include <mach/mux.h>
+#include <mach/cpu.h>
+#include <mach/mcbsp.h>
 
 struct mcbsp_internal_clk {
         struct clk clk;
diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c
index 73cadb2c75cf..6b49cc9cbdcb 100644
--- a/arch/arm/mach-omap2/memory.c
+++ b/arch/arm/mach-omap2/memory.c
@@ -24,9 +24,9 @@
 
 #include <asm/io.h>
 
-#include <asm/arch/common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sram.h>
+#include <mach/common.h>
+#include <mach/clock.h>
+#include <mach/sram.h>
 
 #include "prm.h"
 
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 8f98b20f30a1..443d07fef7f3 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -29,8 +29,8 @@
 #include <asm/io.h>
 #include <linux/spinlock.h>
 
-#include <asm/arch/control.h>
-#include <asm/arch/mux.h>
+#include <mach/control.h>
+#include <mach/mux.h>
 
 #ifdef CONFIG_OMAP_MUX
 
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 5e6e595d8eff..8671e1079ab5 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -31,10 +31,10 @@
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/irqs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sram.h>
-#include <asm/arch/pm.h>
+#include <mach/irqs.h>
+#include <mach/clock.h>
+#include <mach/sram.h>
+#include <mach/pm.h>
 
 static struct clk *vclk;
 static void (*omap2_sram_idle)(void);
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index fd92a80f38f2..f945156d5585 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -18,8 +18,8 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <asm/arch/common.h>
-#include <asm/arch/prcm.h>
+#include <mach/common.h>
+#include <mach/prcm.h>
 
 #include "clock.h"
 #include "prm.h"
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h
index 1b1fe4f6e030..1a8bbd094066 100644
--- a/arch/arm/mach-omap2/sdrc.h
+++ b/arch/arm/mach-omap2/sdrc.h
@@ -15,7 +15,7 @@
  */
 #undef DEBUG
 
-#include <asm/arch/sdrc.h>
+#include <mach/sdrc.h>
 
 #ifndef __ASSEMBLER__
 extern void __iomem *omap2_sdrc_base;
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index e9c367fc9f61..adc8a26a8fb0 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -20,8 +20,8 @@
 
 #include <asm/io.h>
 
-#include <asm/arch/common.h>
-#include <asm/arch/board.h>
+#include <mach/common.h>
+#include <mach/board.h>
 
 static struct clk * uart1_ick = NULL;
 static struct clk * uart1_fck = NULL;
diff --git a/arch/arm/mach-omap2/sleep.S b/arch/arm/mach-omap2/sleep.S
index 46ccb9b8b583..87a706fd5f82 100644
--- a/arch/arm/mach-omap2/sleep.S
+++ b/arch/arm/mach-omap2/sleep.S
@@ -23,8 +23,8 @@
 
 #include <linux/linkage.h>
 #include <asm/assembler.h>
-#include <asm/arch/io.h>
-#include <asm/arch/pm.h>
+#include <mach/io.h>
+#include <mach/pm.h>
 
 #include "sdrc.h"
 
diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S
index 229a9284ed90..af4bd3490227 100644
--- a/arch/arm/mach-omap2/sram242x.S
+++ b/arch/arm/mach-omap2/sram242x.S
@@ -24,8 +24,8 @@
  */
 #include <linux/linkage.h>
 #include <asm/assembler.h>
-#include <asm/arch/io.h>
-#include <asm/arch/hardware.h>
+#include <mach/io.h>
+#include <mach/hardware.h>
 
 #include "prm.h"
 #include "cm.h"
diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S
index 1665ebb9d7ce..84363e269e8c 100644
--- a/arch/arm/mach-omap2/sram243x.S
+++ b/arch/arm/mach-omap2/sram243x.S
@@ -24,8 +24,8 @@
  */
 #include <linux/linkage.h>
 #include <asm/assembler.h>
-#include <asm/arch/io.h>
-#include <asm/arch/hardware.h>
+#include <mach/io.h>
+#include <mach/hardware.h>
 
 #include "prm.h"
 #include "cm.h"
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index 557603f99313..589393bedade 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -34,7 +34,7 @@
 #include <linux/clockchips.h>
 
 #include <asm/mach/time.h>
-#include <asm/arch/dmtimer.h>
+#include <mach/dmtimer.h>
 
 static struct omap_dm_timer *gptimer;
 static struct clock_event_device clockevent_gpt;
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index 80bb42eb5082..1607c941d95f 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -15,9 +15,9 @@
 
 #include <linux/usb/musb.h>
 
-#include <asm/arch/gpmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mux.h>
+#include <mach/gpmc.h>
+#include <mach/gpio.h>
+#include <mach/mux.h>
 
 
 static u8               async_cs, sync_cs;
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index 9a3cc0068362..bea37972120a 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -13,7 +13,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/mbus.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include "common.h"
 
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index faf4e3211918..168eeacaa4c0 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -24,8 +24,8 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/orion5x.h>
+#include <mach/hardware.h>
+#include <mach/orion5x.h>
 #include <asm/plat-orion/ehci-orion.h>
 #include <asm/plat-orion/orion_nand.h>
 #include <asm/plat-orion/time.h>
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index 40a0bee4fbb3..48ce6d0e0020 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -24,7 +24,7 @@
 #include <asm/gpio.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
-#include <asm/arch/orion5x.h>
+#include <mach/orion5x.h>
 #include <asm/plat-orion/orion_nand.h>
 #include "common.h"
 #include "mpp.h"
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 3791ca6f001a..1a1d84b80a65 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -25,7 +25,7 @@
 #include <asm/gpio.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
-#include <asm/arch/orion5x.h>
+#include <mach/orion5x.h>
 #include "common.h"
 #include "mpp.h"
 
diff --git a/arch/arm/mach-orion5x/gpio.c b/arch/arm/mach-orion5x/gpio.c
index d09797990f41..cd8a16f67d2b 100644
--- a/arch/arm/mach-orion5x/gpio.c
+++ b/arch/arm/mach-orion5x/gpio.c
@@ -17,7 +17,7 @@
 #include <linux/bitops.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
-#include <asm/arch/orion5x.h>
+#include <mach/orion5x.h>
 #include "common.h"
 
 static DEFINE_SPINLOCK(gpio_lock);
diff --git a/arch/arm/mach-orion5x/include/mach/debug-macro.S b/arch/arm/mach-orion5x/include/mach/debug-macro.S
new file mode 100644
index 000000000000..c7f808bfe272
--- /dev/null
+++ b/arch/arm/mach-orion5x/include/mach/debug-macro.S
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/mach-orion5x/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <mach/orion5x.h>
+
+        .macro  addruart,rx
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1                                 @ MMU enabled?
+        ldreq   \rx, =ORION5X_REGS_PHYS_BASE
+        ldrne   \rx, =ORION5X_REGS_VIRT_BASE
+        orr     \rx, \rx, #0x00012000
+        .endm
+
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-orion5x/dma.h b/arch/arm/mach-orion5x/include/mach/dma.h
index 40a8c178f10d..40a8c178f10d 100644
--- a/include/asm-arm/arch-orion5x/dma.h
+++ b/arch/arm/mach-orion5x/include/mach/dma.h
diff --git a/arch/arm/mach-orion5x/include/mach/entry-macro.S b/arch/arm/mach-orion5x/include/mach/entry-macro.S
new file mode 100644
index 000000000000..4351937035cd
--- /dev/null
+++ b/arch/arm/mach-orion5x/include/mach/entry-macro.S
@@ -0,0 +1,31 @@
+/*
+ * arch/arm/mach-orion5x/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for Orion platforms
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <mach/orion5x.h>
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =MAIN_IRQ_CAUSE
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        ldr     \irqstat, [\base, #0]           @ main cause
+        ldr     \tmp, [\base, #(MAIN_IRQ_MASK - MAIN_IRQ_CAUSE)] @ main mask
+        mov     \irqnr, #0                      @ default irqnr
+        @ find cause bits that are unmasked
+        ands    \irqstat, \irqstat, \tmp        @ clear Z flag if any
+        clzne   \irqnr, \irqstat                @ calc irqnr
+        rsbne   \irqnr, \irqnr, #31
+        .endm
diff --git a/arch/arm/mach-orion5x/include/mach/gpio.h b/arch/arm/mach-orion5x/include/mach/gpio.h
new file mode 100644
index 000000000000..65dc136a86f7
--- /dev/null
+++ b/arch/arm/mach-orion5x/include/mach/gpio.h
@@ -0,0 +1,28 @@
+/*
+ * arch/arm/mach-orion5x/include/mach/gpio.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+extern int gpio_request(unsigned pin, const char *label);
+extern void gpio_free(unsigned pin);
+extern int gpio_direction_input(unsigned pin);
+extern int gpio_direction_output(unsigned pin, int value);
+extern int gpio_get_value(unsigned pin);
+extern void gpio_set_value(unsigned pin, int value);
+extern void orion5x_gpio_set_blink(unsigned pin, int blink);
+extern void gpio_display(void);         /* debug */
+
+static inline int gpio_to_irq(int pin)
+{
+        return pin + IRQ_ORION5X_GPIO_START;
+}
+
+static inline int irq_to_gpio(int irq)
+{
+        return irq - IRQ_ORION5X_GPIO_START;
+}
+
+#include <asm-generic/gpio.h>           /* cansleep wrappers */
diff --git a/arch/arm/mach-orion5x/include/mach/hardware.h b/arch/arm/mach-orion5x/include/mach/hardware.h
new file mode 100644
index 000000000000..e51aaf4bf2b5
--- /dev/null
+++ b/arch/arm/mach-orion5x/include/mach/hardware.h
@@ -0,0 +1,21 @@
+/*
+ * arch/arm/mach-orion5x/include/mach/hardware.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include "orion5x.h"
+
+#define pcibios_assign_all_busses()     1
+
+#define PCIBIOS_MIN_IO          0x00001000
+#define PCIBIOS_MIN_MEM         0x01000000
+#define PCIMEM_BASE             ORION5X_PCIE_MEM_PHYS_BASE
+
+
+#endif
diff --git a/arch/arm/mach-orion5x/include/mach/io.h b/arch/arm/mach-orion5x/include/mach/io.h
new file mode 100644
index 000000000000..f24b2513f7f3
--- /dev/null
+++ b/arch/arm/mach-orion5x/include/mach/io.h
@@ -0,0 +1,63 @@
+/*
+ * arch/arm/mach-orion5x/include/mach/io.h
+ *
+ * Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#include "orion5x.h"
+
+#define IO_SPACE_LIMIT          0xffffffff
+
+static inline void __iomem *
+__arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype)
+{
+        void __iomem *retval;
+        unsigned long offs = paddr - ORION5X_REGS_PHYS_BASE;
+        if (mtype == MT_DEVICE && size && offs < ORION5X_REGS_SIZE &&
+            size <= ORION5X_REGS_SIZE && offs + size <= ORION5X_REGS_SIZE) {
+                retval = (void __iomem *)ORION5X_REGS_VIRT_BASE + offs;
+        } else {
+                retval = __arm_ioremap(paddr, size, mtype);
+        }
+
+        return retval;
+}
+
+static inline void
+__arch_iounmap(void __iomem *addr)
+{
+        if (addr < (void __iomem *)ORION5X_REGS_VIRT_BASE ||
+            addr >= (void __iomem *)(ORION5X_REGS_VIRT_BASE + ORION5X_REGS_SIZE))
+                __iounmap(addr);
+}
+
+static inline void __iomem *__io(unsigned long addr)
+{
+        return (void __iomem *)addr;
+}
+
+#define __arch_ioremap(p, s, m) __arch_ioremap(p, s, m)
+#define __arch_iounmap(a)       __arch_iounmap(a)
+#define __io(a)                 __io(a)
+#define __mem_pci(a)            (a)
+
+
+/*****************************************************************************
+ * Helpers to access Orion registers
+ ****************************************************************************/
+/*
+ * These are not preempt-safe.  Locks, if needed, must be taken
+ * care of by the caller.
+ */
+#define orion5x_setbits(r, mask)        writel(readl(r) | (mask), (r))
+#define orion5x_clrbits(r, mask)        writel(readl(r) & ~(mask), (r))
+
+
+#endif
diff --git a/arch/arm/mach-orion5x/include/mach/irqs.h b/arch/arm/mach-orion5x/include/mach/irqs.h
new file mode 100644
index 000000000000..d5b0fbf6b965
--- /dev/null
+++ b/arch/arm/mach-orion5x/include/mach/irqs.h
@@ -0,0 +1,62 @@
+/*
+ * arch/arm/mach-orion5x/include/mach/irqs.h
+ *
+ * IRQ definitions for Orion SoC
+ *
+ *  Maintainer: Tzachi Perelstein <tzachi@marvell.com>
+ *
+ *  This file is licensed under the terms of the GNU General Public
+ *  License version 2. This program is licensed "as is" without any
+ *  warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#include "orion5x.h"    /* need GPIO_MAX */
+
+/*
+ * Orion Main Interrupt Controller
+ */
+#define IRQ_ORION5X_BRIDGE              0
+#define IRQ_ORION5X_DOORBELL_H2C        1
+#define IRQ_ORION5X_DOORBELL_C2H        2
+#define IRQ_ORION5X_UART0               3
+#define IRQ_ORION5X_UART1               4
+#define IRQ_ORION5X_I2C                 5
+#define IRQ_ORION5X_GPIO_0_7            6
+#define IRQ_ORION5X_GPIO_8_15           7
+#define IRQ_ORION5X_GPIO_16_23          8
+#define IRQ_ORION5X_GPIO_24_31          9
+#define IRQ_ORION5X_PCIE0_ERR           10
+#define IRQ_ORION5X_PCIE0_INT           11
+#define IRQ_ORION5X_USB1_CTRL           12
+#define IRQ_ORION5X_DEV_BUS_ERR         14
+#define IRQ_ORION5X_PCI_ERR             15
+#define IRQ_ORION5X_USB_BR_ERR          16
+#define IRQ_ORION5X_USB0_CTRL           17
+#define IRQ_ORION5X_ETH_RX              18
+#define IRQ_ORION5X_ETH_TX              19
+#define IRQ_ORION5X_ETH_MISC            20
+#define IRQ_ORION5X_ETH_SUM             21
+#define IRQ_ORION5X_ETH_ERR             22
+#define IRQ_ORION5X_IDMA_ERR            23
+#define IRQ_ORION5X_IDMA_0              24
+#define IRQ_ORION5X_IDMA_1              25
+#define IRQ_ORION5X_IDMA_2              26
+#define IRQ_ORION5X_IDMA_3              27
+#define IRQ_ORION5X_CESA                28
+#define IRQ_ORION5X_SATA                29
+#define IRQ_ORION5X_XOR0                30
+#define IRQ_ORION5X_XOR1                31
+
+/*
+ * Orion General Purpose Pins
+ */
+#define IRQ_ORION5X_GPIO_START  32
+#define NR_GPIO_IRQS            GPIO_MAX
+
+#define NR_IRQS                 (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS)
+
+
+#endif
diff --git a/arch/arm/mach-orion5x/include/mach/memory.h b/arch/arm/mach-orion5x/include/mach/memory.h
new file mode 100644
index 000000000000..54dd76b013f2
--- /dev/null
+++ b/arch/arm/mach-orion5x/include/mach/memory.h
@@ -0,0 +1,16 @@
+/*
+ * arch/arm/mach-orion5x/include/mach/memory.h
+ *
+ * Marvell Orion memory definitions
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#define PHYS_OFFSET     UL(0x00000000)
+
+#define __virt_to_bus(x)        __virt_to_phys(x)
+#define __bus_to_virt(x)        __phys_to_virt(x)
+
+
+#endif
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h
new file mode 100644
index 000000000000..f52a7d65bec2
--- /dev/null
+++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
@@ -0,0 +1,162 @@
+/*
+ * arch/arm/mach-orion5x/include/mach/orion5x.h
+ *
+ * Generic definitions of Orion SoC flavors:
+ *  Orion-1, Orion-VoIP, Orion-NAS, and Orion-2.
+ *
+ * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_ORION5X_H
+#define __ASM_ARCH_ORION5X_H
+
+/*****************************************************************************
+ * Orion Address Maps
+ *
+ * phys
+ * e0000000     PCIe MEM space
+ * e8000000     PCI MEM space
+ * f0000000     PCIe WA space (Orion-1/Orion-NAS only)
+ * f1000000     on-chip peripheral registers
+ * f2000000     PCIe I/O space
+ * f2100000     PCI I/O space
+ * f4000000     device bus mappings (boot)
+ * fa000000     device bus mappings (cs0)
+ * fa800000     device bus mappings (cs2)
+ * fc000000     device bus mappings (cs0/cs1)
+ *
+ * virt         phys            size
+ * fdd00000     f1000000        1M      on-chip peripheral registers
+ * fde00000     f2000000        1M      PCIe I/O space
+ * fdf00000     f2100000        1M      PCI I/O space
+ * fe000000     f0000000        16M     PCIe WA space (Orion-1/Orion-NAS only)
+ ****************************************************************************/
+#define ORION5X_REGS_PHYS_BASE          0xf1000000
+#define ORION5X_REGS_VIRT_BASE          0xfdd00000
+#define ORION5X_REGS_SIZE               SZ_1M
+
+#define ORION5X_PCIE_IO_PHYS_BASE       0xf2000000
+#define ORION5X_PCIE_IO_VIRT_BASE       0xfde00000
+#define ORION5X_PCIE_IO_BUS_BASE        0x00000000
+#define ORION5X_PCIE_IO_SIZE            SZ_1M
+
+#define ORION5X_PCI_IO_PHYS_BASE        0xf2100000
+#define ORION5X_PCI_IO_VIRT_BASE        0xfdf00000
+#define ORION5X_PCI_IO_BUS_BASE         0x00100000
+#define ORION5X_PCI_IO_SIZE             SZ_1M
+
+/* Relevant only for Orion-1/Orion-NAS */
+#define ORION5X_PCIE_WA_PHYS_BASE       0xf0000000
+#define ORION5X_PCIE_WA_VIRT_BASE       0xfe000000
+#define ORION5X_PCIE_WA_SIZE            SZ_16M
+
+#define ORION5X_PCIE_MEM_PHYS_BASE      0xe0000000
+#define ORION5X_PCIE_MEM_SIZE           SZ_128M
+
+#define ORION5X_PCI_MEM_PHYS_BASE       0xe8000000
+#define ORION5X_PCI_MEM_SIZE            SZ_128M
+
+/*******************************************************************************
+ * Supported Devices & Revisions
+ ******************************************************************************/
+/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
+#define MV88F5181_DEV_ID        0x5181
+#define MV88F5181_REV_B1        3
+#define MV88F5181L_REV_A0       8
+#define MV88F5181L_REV_A1       9
+/* Orion-NAS (88F5182) */
+#define MV88F5182_DEV_ID        0x5182
+#define MV88F5182_REV_A2        2
+/* Orion-2 (88F5281) */
+#define MV88F5281_DEV_ID        0x5281
+#define MV88F5281_REV_D1        5
+#define MV88F5281_REV_D2        6
+
+/*******************************************************************************
+ * Orion Registers Map
+ ******************************************************************************/
+#define ORION5X_DDR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x00000)
+#define ORION5X_DDR_REG(x)              (ORION5X_DDR_VIRT_BASE | (x))
+
+#define ORION5X_DEV_BUS_PHYS_BASE       (ORION5X_REGS_PHYS_BASE | 0x10000)
+#define ORION5X_DEV_BUS_VIRT_BASE       (ORION5X_REGS_VIRT_BASE | 0x10000)
+#define ORION5X_DEV_BUS_REG(x)          (ORION5X_DEV_BUS_VIRT_BASE | (x))
+#define  I2C_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE | 0x1000)
+#define  UART0_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE | 0x2000)
+#define  UART0_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE | 0x2000)
+#define  UART1_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE | 0x2100)
+#define  UART1_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE | 0x2100)
+
+#define ORION5X_BRIDGE_VIRT_BASE        (ORION5X_REGS_VIRT_BASE | 0x20000)
+#define ORION5X_BRIDGE_REG(x)           (ORION5X_BRIDGE_VIRT_BASE | (x))
+#define  TIMER_VIRT_BASE                (ORION5X_BRIDGE_VIRT_BASE | 0x300)
+
+#define ORION5X_PCI_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x30000)
+#define ORION5X_PCI_REG(x)              (ORION5X_PCI_VIRT_BASE | (x))
+
+#define ORION5X_PCIE_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x40000)
+#define ORION5X_PCIE_REG(x)             (ORION5X_PCIE_VIRT_BASE | (x))
+
+#define ORION5X_USB0_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0x50000)
+#define ORION5X_USB0_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x50000)
+#define ORION5X_USB0_REG(x)             (ORION5X_USB0_VIRT_BASE | (x))
+
+#define ORION5X_ETH_PHYS_BASE           (ORION5X_REGS_PHYS_BASE | 0x70000)
+#define ORION5X_ETH_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x70000)
+#define ORION5X_ETH_REG(x)              (ORION5X_ETH_VIRT_BASE | (x))
+
+#define ORION5X_SATA_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0x80000)
+#define ORION5X_SATA_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x80000)
+#define ORION5X_SATA_REG(x)             (ORION5X_SATA_VIRT_BASE | (x))
+
+#define ORION5X_USB1_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0xa0000)
+#define ORION5X_USB1_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0xa0000)
+#define ORION5X_USB1_REG(x)             (ORION5X_USB1_VIRT_BASE | (x))
+
+/*******************************************************************************
+ * Device Bus Registers
+ ******************************************************************************/
+#define MPP_0_7_CTRL            ORION5X_DEV_BUS_REG(0x000)
+#define MPP_8_15_CTRL           ORION5X_DEV_BUS_REG(0x004)
+#define MPP_16_19_CTRL          ORION5X_DEV_BUS_REG(0x050)
+#define MPP_DEV_CTRL            ORION5X_DEV_BUS_REG(0x008)
+#define MPP_RESET_SAMPLE        ORION5X_DEV_BUS_REG(0x010)
+#define GPIO_OUT                ORION5X_DEV_BUS_REG(0x100)
+#define GPIO_IO_CONF            ORION5X_DEV_BUS_REG(0x104)
+#define GPIO_BLINK_EN           ORION5X_DEV_BUS_REG(0x108)
+#define GPIO_IN_POL             ORION5X_DEV_BUS_REG(0x10c)
+#define GPIO_DATA_IN            ORION5X_DEV_BUS_REG(0x110)
+#define GPIO_EDGE_CAUSE         ORION5X_DEV_BUS_REG(0x114)
+#define GPIO_EDGE_MASK          ORION5X_DEV_BUS_REG(0x118)
+#define GPIO_LEVEL_MASK         ORION5X_DEV_BUS_REG(0x11c)
+#define DEV_BANK_0_PARAM        ORION5X_DEV_BUS_REG(0x45c)
+#define DEV_BANK_1_PARAM        ORION5X_DEV_BUS_REG(0x460)
+#define DEV_BANK_2_PARAM        ORION5X_DEV_BUS_REG(0x464)
+#define DEV_BANK_BOOT_PARAM     ORION5X_DEV_BUS_REG(0x46c)
+#define DEV_BUS_CTRL            ORION5X_DEV_BUS_REG(0x4c0)
+#define DEV_BUS_INT_CAUSE       ORION5X_DEV_BUS_REG(0x4d0)
+#define DEV_BUS_INT_MASK        ORION5X_DEV_BUS_REG(0x4d4)
+#define GPIO_MAX                32
+
+/***************************************************************************
+ * Orion CPU Bridge Registers
+ **************************************************************************/
+#define CPU_CONF                ORION5X_BRIDGE_REG(0x100)
+#define CPU_CTRL                ORION5X_BRIDGE_REG(0x104)
+#define CPU_RESET_MASK          ORION5X_BRIDGE_REG(0x108)
+#define CPU_SOFT_RESET          ORION5X_BRIDGE_REG(0x10c)
+#define POWER_MNG_CTRL_REG      ORION5X_BRIDGE_REG(0x11C)
+#define BRIDGE_CAUSE            ORION5X_BRIDGE_REG(0x110)
+#define BRIDGE_MASK             ORION5X_BRIDGE_REG(0x114)
+#define  BRIDGE_INT_TIMER0      0x0002
+#define  BRIDGE_INT_TIMER1      0x0004
+#define  BRIDGE_INT_TIMER1_CLR  (~0x0004)
+#define MAIN_IRQ_CAUSE          ORION5X_BRIDGE_REG(0x200)
+#define MAIN_IRQ_MASK           ORION5X_BRIDGE_REG(0x204)
+
+
+#endif
diff --git a/arch/arm/mach-orion5x/include/mach/system.h b/arch/arm/mach-orion5x/include/mach/system.h
new file mode 100644
index 000000000000..08e430757890
--- /dev/null
+++ b/arch/arm/mach-orion5x/include/mach/system.h
@@ -0,0 +1,32 @@
+/*
+ * arch/arm/mach-orion5x/include/mach/system.h
+ *
+ * Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <mach/hardware.h>
+#include <mach/orion5x.h>
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        /*
+         * Enable and issue soft reset
+         */
+        orion5x_setbits(CPU_RESET_MASK, (1 << 2));
+        orion5x_setbits(CPU_SOFT_RESET, 1);
+}
+
+
+#endif
diff --git a/arch/arm/mach-orion5x/include/mach/timex.h b/arch/arm/mach-orion5x/include/mach/timex.h
new file mode 100644
index 000000000000..e82e44db7629
--- /dev/null
+++ b/arch/arm/mach-orion5x/include/mach/timex.h
@@ -0,0 +1,13 @@
+/*
+ * arch/arm/mach-orion5x/include/mach/timex.h
+ *
+ * Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#define CLOCK_TICK_RATE         (100 * HZ)
+
+#define ORION5X_TCLK            166666667
diff --git a/arch/arm/mach-orion5x/include/mach/uncompress.h b/arch/arm/mach-orion5x/include/mach/uncompress.h
new file mode 100644
index 000000000000..4322dba468a4
--- /dev/null
+++ b/arch/arm/mach-orion5x/include/mach/uncompress.h
@@ -0,0 +1,49 @@
+/*
+ * arch/arm/mach-orion5x/include/mach/uncompress.h
+ *
+ * Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/serial_reg.h>
+#include <mach/orion5x.h>
+
+#define SERIAL_BASE     ((unsigned char *)UART0_PHYS_BASE)
+
+static void putc(const char c)
+{
+        unsigned char *base = SERIAL_BASE;
+        int i;
+
+        for (i = 0; i < 0x1000; i++) {
+                if (base[UART_LSR << 2] & UART_LSR_THRE)
+                        break;
+                barrier();
+        }
+
+        base[UART_TX << 2] = c;
+}
+
+static void flush(void)
+{
+        unsigned char *base = SERIAL_BASE;
+        unsigned char mask;
+        int i;
+
+        mask = UART_LSR_TEMT | UART_LSR_THRE;
+
+        for (i = 0; i < 0x1000; i++) {
+                if ((base[UART_LSR << 2] & mask) == mask)
+                        break;
+                barrier();
+        }
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-orion5x/include/mach/vmalloc.h b/arch/arm/mach-orion5x/include/mach/vmalloc.h
new file mode 100644
index 000000000000..7147a297e97f
--- /dev/null
+++ b/arch/arm/mach-orion5x/include/mach/vmalloc.h
@@ -0,0 +1,5 @@
+/*
+ * arch/arm/mach-orion5x/include/mach/vmalloc.h
+ */
+
+#define VMALLOC_END       0xfd800000
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c
index 9ae3f6dc7839..cc2a017fd2a9 100644
--- a/arch/arm/mach-orion5x/irq.c
+++ b/arch/arm/mach-orion5x/irq.c
@@ -15,7 +15,7 @@
 #include <linux/irq.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
-#include <asm/arch/orion5x.h>
+#include <mach/orion5x.h>
 #include <asm/plat-orion/irq.h>
 #include "common.h"
 
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index 84feac4a1fe2..0caaaac74bc1 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -24,7 +24,7 @@
 #include <asm/gpio.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
-#include <asm/arch/orion5x.h>
+#include <mach/orion5x.h>
 #include <asm/plat-orion/orion_nand.h>
 #include "common.h"
 #include "mpp.h"
diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c
index 8eadc9b5b0a5..c04ab0e16ea1 100644
--- a/arch/arm/mach-orion5x/mpp.c
+++ b/arch/arm/mach-orion5x/mpp.c
@@ -11,7 +11,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/mbus.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include "common.h"
 #include "mpp.h"
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c
index 7ce9e407d9d1..4403cc963d66 100644
--- a/arch/arm/mach-orion5x/mss2-setup.c
+++ b/arch/arm/mach-orion5x/mss2-setup.c
@@ -25,7 +25,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
-#include <asm/arch/orion5x.h>
+#include <mach/orion5x.h>
 #include "common.h"
 #include "mpp.h"
 
diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c
index 55f3b0fdef8b..67b2c0df615f 100644
--- a/arch/arm/mach-orion5x/mv2120-setup.c
+++ b/arch/arm/mach-orion5x/mv2120-setup.c
@@ -22,7 +22,7 @@
 #include <asm/mach-types.h>
 #include <asm/gpio.h>
 #include <asm/mach/arch.h>
-#include <asm/arch/orion5x.h>
+#include <mach/orion5x.h>
 #include "common.h"
 #include "mpp.h"
 
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
index 73e9242da7ad..e72fe1e065e8 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -21,7 +21,7 @@
 #include <asm/leds.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
-#include <asm/arch/orion5x.h>
+#include <mach/orion5x.h>
 #include "common.h"
 #include "mpp.h"
 
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
index ac482019abbf..a1fe3257320d 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -22,7 +22,7 @@
 #include <asm/leds.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
-#include <asm/arch/orion5x.h>
+#include <mach/orion5x.h>
 #include "common.h"
 #include "mpp.h"
 
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index 2a46d27209c1..8771cb76f0dc 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -24,7 +24,7 @@
 #include <asm/leds.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
-#include <asm/arch/orion5x.h>
+#include <mach/orion5x.h>
 #include "common.h"
 #include "mpp.h"
 
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index f270ada2def9..809132de31d2 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -26,7 +26,7 @@
 #include <asm/gpio.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
-#include <asm/arch/orion5x.h>
+#include <mach/orion5x.h>
 #include "common.h"
 #include "mpp.h"
 #include "tsx09-common.h"
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
index 32f0ff073b7e..6053e76ac967 100644
--- a/arch/arm/mach-orion5x/ts409-setup.c
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -24,7 +24,7 @@
 #include <asm/gpio.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
-#include <asm/arch/orion5x.h>
+#include <mach/orion5x.h>
 #include "common.h"
 #include "mpp.h"
 #include "tsx09-common.h"
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index 77e9f351f07a..014916a28fdc 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -18,7 +18,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <asm/arch/orion5x.h>
+#include <mach/orion5x.h>
 #include "common.h"
 #include "mpp.h"
 
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
index 25568c2a3d29..b6bc43e07eed 100644
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -19,7 +19,7 @@
 #include <asm/gpio.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
-#include <asm/arch/orion5x.h>
+#include <mach/orion5x.h>
 #include "common.h"
 #include "mpp.h"
 
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
index 9b8ee8c48bf0..b10da17b3fbd 100644
--- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -19,7 +19,7 @@
 #include <asm/gpio.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
-#include <asm/arch/orion5x.h>
+#include <mach/orion5x.h>
 #include "common.h"
 #include "mpp.h"
 
diff --git a/arch/arm/mach-pnx4008/clock.c b/arch/arm/mach-pnx4008/clock.c
index 576e9a4d21e0..24d036a24a72 100644
--- a/arch/arm/mach-pnx4008/clock.c
+++ b/arch/arm/mach-pnx4008/clock.c
@@ -21,10 +21,10 @@
 #include <linux/err.h>
 #include <linux/delay.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 
-#include <asm/arch/clock.h>
+#include <mach/clock.h>
 #include "clock.h"
 
 /*forward declaration*/
diff --git a/arch/arm/mach-pnx4008/core.c b/arch/arm/mach-pnx4008/core.c
index 156d8faa3560..3ba46ede9bbd 100644
--- a/arch/arm/mach-pnx4008/core.c
+++ b/arch/arm/mach-pnx4008/core.c
@@ -26,7 +26,7 @@
 #include <linux/device.h>
 #include <linux/spi/spi.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -38,9 +38,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 
-#include <asm/arch/irq.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/dma.h>
+#include <mach/irq.h>
+#include <mach/clock.h>
+#include <mach/dma.h>
 
 struct resource spipnx_0_resources[] = {
         {
diff --git a/arch/arm/mach-pnx4008/dma.c b/arch/arm/mach-pnx4008/dma.c
index fee0d252854e..833c56be7344 100644
--- a/arch/arm/mach-pnx4008/dma.c
+++ b/arch/arm/mach-pnx4008/dma.c
@@ -23,12 +23,12 @@
 #include <linux/clk.h>
 
 #include <asm/system.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/dma.h>
 #include <asm/dma-mapping.h>
 #include <asm/io.h>
 #include <asm/mach/dma.h>
-#include <asm/arch/clock.h>
+#include <mach/clock.h>
 
 static struct dma_channel {
         char *name;
diff --git a/arch/arm/mach-pnx4008/gpio.c b/arch/arm/mach-pnx4008/gpio.c
index ef179cab80e2..fb51f7279e95 100644
--- a/arch/arm/mach-pnx4008/gpio.c
+++ b/arch/arm/mach-pnx4008/gpio.c
@@ -18,8 +18,8 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <asm/io.h>
-#include <asm/arch/platform.h>
-#include <asm/arch/gpio.h>
+#include <mach/platform.h>
+#include <mach/gpio.h>
 
 /* register definitions */
 #define PIO_VA_BASE     IO_ADDRESS(PNX4008_PIO_BASE)
diff --git a/arch/arm/mach-pnx4008/i2c.c b/arch/arm/mach-pnx4008/i2c.c
index 6f308827c4fe..87c093286ff9 100644
--- a/arch/arm/mach-pnx4008/i2c.c
+++ b/arch/arm/mach-pnx4008/i2c.c
@@ -14,8 +14,8 @@
 #include <linux/i2c-pnx.h>
 #include <linux/platform_device.h>
 #include <linux/err.h>
-#include <asm/arch/platform.h>
-#include <asm/arch/i2c.h>
+#include <mach/platform.h>
+#include <mach/i2c.h>
 
 static int set_clock_run(struct platform_device *pdev)
 {
diff --git a/arch/arm/mach-pnx4008/include/mach/clock.h b/arch/arm/mach-pnx4008/include/mach/clock.h
new file mode 100644
index 000000000000..8d2a5ef52c90
--- /dev/null
+++ b/arch/arm/mach-pnx4008/include/mach/clock.h
@@ -0,0 +1,62 @@
+/*
+ * arch/arm/mach-pnx4008/include/mach/clock.h
+ *
+ * Clock control driver for PNX4008 - header file
+ *
+ * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __PNX4008_CLOCK_H__
+#define __PNX4008_CLOCK_H__
+
+struct module;
+struct clk;
+
+#define PWRMAN_VA_BASE          IO_ADDRESS(PNX4008_PWRMAN_BASE)
+#define HCLKDIVCTRL_REG         (PWRMAN_VA_BASE + 0x40)
+#define PWRCTRL_REG             (PWRMAN_VA_BASE + 0x44)
+#define PLLCTRL_REG             (PWRMAN_VA_BASE + 0x48)
+#define OSC13CTRL_REG           (PWRMAN_VA_BASE + 0x4c)
+#define SYSCLKCTRL_REG          (PWRMAN_VA_BASE + 0x50)
+#define HCLKPLLCTRL_REG         (PWRMAN_VA_BASE + 0x58)
+#define USBCTRL_REG             (PWRMAN_VA_BASE + 0x64)
+#define SDRAMCLKCTRL_REG        (PWRMAN_VA_BASE + 0x68)
+#define MSCTRL_REG              (PWRMAN_VA_BASE + 0x80)
+#define BTCLKCTRL               (PWRMAN_VA_BASE + 0x84)
+#define DUMCLKCTRL_REG          (PWRMAN_VA_BASE + 0x90)
+#define I2CCLKCTRL_REG          (PWRMAN_VA_BASE + 0xac)
+#define KEYCLKCTRL_REG          (PWRMAN_VA_BASE + 0xb0)
+#define TSCLKCTRL_REG           (PWRMAN_VA_BASE + 0xb4)
+#define PWMCLKCTRL_REG          (PWRMAN_VA_BASE + 0xb8)
+#define TIMCLKCTRL_REG          (PWRMAN_VA_BASE + 0xbc)
+#define SPICTRL_REG             (PWRMAN_VA_BASE + 0xc4)
+#define FLASHCLKCTRL_REG        (PWRMAN_VA_BASE + 0xc8)
+#define UART3CLK_REG            (PWRMAN_VA_BASE + 0xd0)
+#define UARTCLKCTRL_REG         (PWRMAN_VA_BASE + 0xe4)
+#define DMACLKCTRL_REG          (PWRMAN_VA_BASE + 0xe8)
+#define AUTOCLK_CTRL            (PWRMAN_VA_BASE + 0xec)
+#define JPEGCLKCTRL_REG         (PWRMAN_VA_BASE + 0xfc)
+
+#define AUDIOCONFIG_VA_BASE     IO_ADDRESS(PNX4008_AUDIOCONFIG_BASE)
+#define DSPPLLCTRL_REG          (AUDIOCONFIG_VA_BASE + 0x60)
+#define DSPCLKCTRL_REG          (AUDIOCONFIG_VA_BASE + 0x64)
+#define AUDIOCLKCTRL_REG        (AUDIOCONFIG_VA_BASE + 0x68)
+#define AUDIOPLLCTRL_REG        (AUDIOCONFIG_VA_BASE + 0x6C)
+
+#define USB_OTG_CLKCTRL_REG     IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xff4)
+
+#define VFP9CLKCTRL_REG         IO_ADDRESS(PNX4008_DEBUG_BASE)
+
+#define CLK_RATE_13MHZ 13000
+#define CLK_RATE_1MHZ 1000
+#define CLK_RATE_208MHZ 208000
+#define CLK_RATE_48MHZ 48000
+#define CLK_RATE_32KHZ 32
+
+#define PNX4008_UART_CLK CLK_RATE_13MHZ * 1000 /* in MHz */
+
+#endif
diff --git a/arch/arm/mach-pnx4008/include/mach/debug-macro.S b/arch/arm/mach-pnx4008/include/mach/debug-macro.S
new file mode 100644
index 000000000000..6d1407f319f8
--- /dev/null
+++ b/arch/arm/mach-pnx4008/include/mach/debug-macro.S
@@ -0,0 +1,23 @@
+/* arch/arm/mach-pnx4008/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                mov     \rx, #0x00090000
+                addeq   \rx, \rx, #0x40000000
+                addne   \rx, \rx, #0xf4000000
+                .endm
+
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-pnx4008/include/mach/dma.h b/arch/arm/mach-pnx4008/include/mach/dma.h
new file mode 100644
index 000000000000..5442d04fc575
--- /dev/null
+++ b/arch/arm/mach-pnx4008/include/mach/dma.h
@@ -0,0 +1,162 @@
+/*
+ *  arch/arm/mach-pnx4008/include/mach/dma.h
+ *
+ *  PNX4008 DMA header file
+ *
+ *  Author:     Vitaly Wool
+ *  Copyright:  MontaVista Software Inc. (c) 2005
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+#include "platform.h"
+
+#define MAX_DMA_ADDRESS         0xffffffff
+
+#define MAX_DMA_CHANNELS        8
+
+#define DMAC_BASE               IO_ADDRESS(PNX4008_DMA_CONFIG_BASE)
+#define DMAC_INT_STAT           (DMAC_BASE + 0x0000)
+#define DMAC_INT_TC_STAT        (DMAC_BASE + 0x0004)
+#define DMAC_INT_TC_CLEAR       (DMAC_BASE + 0x0008)
+#define DMAC_INT_ERR_STAT       (DMAC_BASE + 0x000c)
+#define DMAC_INT_ERR_CLEAR      (DMAC_BASE + 0x0010)
+#define DMAC_SOFT_SREQ          (DMAC_BASE + 0x0024)
+#define DMAC_CONFIG             (DMAC_BASE + 0x0030)
+#define DMAC_Cx_SRC_ADDR(c)     (DMAC_BASE + 0x0100 + (c) * 0x20)
+#define DMAC_Cx_DEST_ADDR(c)    (DMAC_BASE + 0x0104 + (c) * 0x20)
+#define DMAC_Cx_LLI(c)          (DMAC_BASE + 0x0108 + (c) * 0x20)
+#define DMAC_Cx_CONTROL(c)      (DMAC_BASE + 0x010c + (c) * 0x20)
+#define DMAC_Cx_CONFIG(c)       (DMAC_BASE + 0x0110 + (c) * 0x20)
+
+enum {
+        WIDTH_BYTE = 0,
+        WIDTH_HWORD,
+        WIDTH_WORD
+};
+
+enum {
+        FC_MEM2MEM_DMA,
+        FC_MEM2PER_DMA,
+        FC_PER2MEM_DMA,
+        FC_PER2PER_DMA,
+        FC_PER2PER_DPER,
+        FC_MEM2PER_PER,
+        FC_PER2MEM_PER,
+        FC_PER2PER_SPER
+};
+
+enum {
+        DMA_INT_UNKNOWN = 0,
+        DMA_ERR_INT = 1,
+        DMA_TC_INT = 2,
+};
+
+enum {
+        DMA_BUFFER_ALLOCATED = 1,
+        DMA_HAS_LL = 2,
+};
+
+enum {
+        PER_CAM_DMA_1 = 0,
+        PER_NDF_FLASH = 1,
+        PER_MBX_SLAVE_FIFO = 2,
+        PER_SPI2_REC_XMIT = 3,
+        PER_MS_SD_RX_XMIT = 4,
+        PER_HS_UART_1_XMIT = 5,
+        PER_HS_UART_1_RX = 6,
+        PER_HS_UART_2_XMIT = 7,
+        PER_HS_UART_2_RX = 8,
+        PER_HS_UART_7_XMIT = 9,
+        PER_HS_UART_7_RX = 10,
+        PER_SPI1_REC_XMIT = 11,
+        PER_MLC_NDF_SREC = 12,
+        PER_CAM_DMA_2 = 13,
+        PER_PRNG_INFIFO = 14,
+        PER_PRNG_OUTFIFO = 15,
+};
+
+struct pnx4008_dma_ch_ctrl {
+        int tc_mask;
+        int cacheable;
+        int bufferable;
+        int priv_mode;
+        int di;
+        int si;
+        int dest_ahb1;
+        int src_ahb1;
+        int dwidth;
+        int swidth;
+        int dbsize;
+        int sbsize;
+        int tr_size;
+};
+
+struct pnx4008_dma_ch_config {
+        int halt;
+        int active;
+        int lock;
+        int itc;
+        int ie;
+        int flow_cntrl;
+        int dest_per;
+        int src_per;
+};
+
+struct pnx4008_dma_ll {
+        unsigned long src_addr;
+        unsigned long dest_addr;
+        u32 next_dma;
+        unsigned long ch_ctrl;
+        struct pnx4008_dma_ll *next;
+        int flags;
+        void *alloc_data;
+        int (*free) (void *);
+};
+
+struct pnx4008_dma_config {
+        int is_ll;
+        unsigned long src_addr;
+        unsigned long dest_addr;
+        unsigned long ch_ctrl;
+        unsigned long ch_cfg;
+        struct pnx4008_dma_ll *ll;
+        u32 ll_dma;
+        int flags;
+        void *alloc_data;
+        int (*free) (void *);
+};
+
+extern struct pnx4008_dma_ll *pnx4008_alloc_ll_entry(dma_addr_t *);
+extern void pnx4008_free_ll_entry(struct pnx4008_dma_ll *, dma_addr_t);
+extern void pnx4008_free_ll(u32 ll_dma, struct pnx4008_dma_ll *);
+
+extern int pnx4008_request_channel(char *, int,
+                                   void (*)(int, int, void *),
+                                   void *);
+extern void pnx4008_free_channel(int);
+extern int pnx4008_config_dma(int, int, int);
+extern int pnx4008_dma_pack_control(const struct pnx4008_dma_ch_ctrl *,
+                                    unsigned long *);
+extern int pnx4008_dma_parse_control(unsigned long,
+                                     struct pnx4008_dma_ch_ctrl *);
+extern int pnx4008_dma_pack_config(const struct pnx4008_dma_ch_config *,
+                                   unsigned long *);
+extern int pnx4008_dma_parse_config(unsigned long,
+                                    struct pnx4008_dma_ch_config *);
+extern int pnx4008_config_channel(int, struct pnx4008_dma_config *);
+extern int pnx4008_channel_get_config(int, struct pnx4008_dma_config *);
+extern int pnx4008_dma_ch_enable(int);
+extern int pnx4008_dma_ch_disable(int);
+extern int pnx4008_dma_ch_enabled(int);
+extern void pnx4008_dma_split_head_entry(struct pnx4008_dma_config *,
+                                         struct pnx4008_dma_ch_ctrl *);
+extern void pnx4008_dma_split_ll_entry(struct pnx4008_dma_ll *,
+                                       struct pnx4008_dma_ch_ctrl *);
+
+#endif                          /* _ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-pnx4008/include/mach/entry-macro.S b/arch/arm/mach-pnx4008/include/mach/entry-macro.S
new file mode 100644
index 000000000000..8003037578ed
--- /dev/null
+++ b/arch/arm/mach-pnx4008/include/mach/entry-macro.S
@@ -0,0 +1,127 @@
+/*
+ * arch/arm/mach-pnx4008/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for PNX4008-based platforms
+ *
+ * 2005-2006 (c) MontaVista Software, Inc.
+ * Author: Vitaly Wool <vwool@ru.mvista.com>
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include "platform.h"
+
+#define IO_BASE         0xF0000000
+#define IO_ADDRESS(x)  (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE)
+
+#define INTRC_MASK                      0x00
+#define INTRC_RAW_STAT                  0x04
+#define INTRC_STAT                      0x08
+#define INTRC_POLAR                     0x0C
+#define INTRC_ACT_TYPE                  0x10
+#define INTRC_TYPE                      0x14
+
+#define SIC1_BASE_INT   32
+#define SIC2_BASE_INT   64
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_preamble, base, tmp
+                .endm
+
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+/* decode the MIC interrupt numbers */
+                ldr     \base, =IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
+                ldr     \irqstat, [\base, #INTRC_STAT]
+
+                cmp     \irqstat,#1<<16
+                movhs   \irqnr,#16
+                movlo   \irqnr,#0
+                movhs   \irqstat,\irqstat,lsr#16
+                cmp     \irqstat,#1<<8
+                addhs   \irqnr,\irqnr,#8
+                movhs   \irqstat,\irqstat,lsr#8
+                cmp     \irqstat,#1<<4
+                addhs   \irqnr,\irqnr,#4
+                movhs   \irqstat,\irqstat,lsr#4
+                cmp     \irqstat,#1<<2
+                addhs   \irqnr,\irqnr,#2
+                movhs   \irqstat,\irqstat,lsr#2
+                cmp     \irqstat,#1<<1
+                addhs   \irqnr,\irqnr,#1
+
+/* was there an interrupt ? if not then drop out with EQ status */
+                teq     \irqstat,#0
+                beq     1003f
+
+/* and now check for extended IRQ reasons */
+                cmp     \irqnr,#1
+                bls     1003f
+                cmp     \irqnr,#30
+                blo     1002f
+
+/* IRQ 31,30  : High priority cascade IRQ handle */
+/* read the correct SIC */
+/* decoding status after compare : eq is 30 (SIC1) , ne is 31 (SIC2) */
+/* set the base IRQ number */
+                ldreq   \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
+                moveq  \irqnr,#SIC1_BASE_INT
+                ldrne   \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
+                movne   \irqnr,#SIC2_BASE_INT
+                ldr     \irqstat, [\base, #INTRC_STAT]
+                ldr     \tmp,     [\base, #INTRC_TYPE]
+/* and with inverted mask : low priority interrupts  */
+                and     \irqstat,\irqstat,\tmp
+                b       1004f
+
+1003:
+/* IRQ 1,0  : Low priority cascade IRQ handle */
+/* read the correct SIC */
+/* decoding status after compare : eq is 1 (SIC2) , ne is 0 (SIC1)*/
+/* read the correct SIC */
+/* set the base IRQ number  */
+                ldrne   \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
+                movne   \irqnr,#SIC1_BASE_INT
+                ldreq   \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
+                moveq   \irqnr,#SIC2_BASE_INT
+                ldr     \irqstat, [\base, #INTRC_STAT]
+                ldr     \tmp,     [\base, #INTRC_TYPE]
+/* and with inverted mask : low priority interrupts  */
+                bic     \irqstat,\irqstat,\tmp
+
+1004:
+
+                cmp     \irqstat,#1<<16
+                addhs   \irqnr,\irqnr,#16
+                movhs   \irqstat,\irqstat,lsr#16
+                cmp     \irqstat,#1<<8
+                addhs   \irqnr,\irqnr,#8
+                movhs   \irqstat,\irqstat,lsr#8
+                cmp     \irqstat,#1<<4
+                addhs   \irqnr,\irqnr,#4
+                movhs   \irqstat,\irqstat,lsr#4
+                cmp     \irqstat,#1<<2
+                addhs   \irqnr,\irqnr,#2
+                movhs   \irqstat,\irqstat,lsr#2
+                cmp     \irqstat,#1<<1
+                addhs   \irqnr,\irqnr,#1
+
+
+/* is irqstat not zero */
+
+1002:
+/* we assert that irqstat is not equal to zero and return ne status if true*/
+                teq     \irqstat,#0
+1003:
+                .endm
+
+
+                .macro  irq_prio_table
+                .endm
+
+
diff --git a/arch/arm/mach-pnx4008/include/mach/gpio.h b/arch/arm/mach-pnx4008/include/mach/gpio.h
new file mode 100644
index 000000000000..9591467eb9ec
--- /dev/null
+++ b/arch/arm/mach-pnx4008/include/mach/gpio.h
@@ -0,0 +1,241 @@
+/*
+ * arch/arm/mach-pnx4008/include/mach/gpio.h
+ *
+ * PNX4008 GPIO driver - header file
+ *
+ * Author: Dmitry Chigirev <source@mvista.com>
+ *
+ * Based on reference code by Iwo Mergler and Z.Tabaaloute from Philips:
+ * Copyright (c) 2005 Koninklijke Philips Electronics N.V.
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#ifndef _PNX4008_GPIO_H_
+#define _PNX4008_GPIO_H_
+
+
+/* Block numbers */
+#define GPIO_IN         (0)
+#define GPIO_OUT                (0x100)
+#define GPIO_BID                (0x200)
+#define GPIO_RAM                (0x300)
+#define GPIO_MUX                (0x400)
+
+#define GPIO_TYPE_MASK(K) ((K) & 0x700)
+
+/* INPUT GPIOs */
+/* GPI */
+#define GPI_00          (GPIO_IN | 0)
+#define GPI_01          (GPIO_IN | 1)
+#define GPI_02          (GPIO_IN | 2)
+#define GPI_03          (GPIO_IN | 3)
+#define GPI_04          (GPIO_IN | 4)
+#define GPI_05          (GPIO_IN | 5)
+#define GPI_06          (GPIO_IN | 6)
+#define GPI_07          (GPIO_IN | 7)
+#define GPI_08          (GPIO_IN | 8)
+#define GPI_09          (GPIO_IN | 9)
+#define U1_RX           (GPIO_IN | 15)
+#define U2_HTCS         (GPIO_IN | 16)
+#define U2_RX           (GPIO_IN | 17)
+#define U3_RX           (GPIO_IN | 18)
+#define U4_RX           (GPIO_IN | 19)
+#define U5_RX           (GPIO_IN | 20)
+#define U6_IRRX         (GPIO_IN | 21)
+#define U7_HCTS         (GPIO_IN | 22)
+#define U7_RX           (GPIO_IN | 23)
+/* MISC IN */
+#define SPI1_DATIN      (GPIO_IN | 25)
+#define DISP_SYNC       (GPIO_IN | 26)
+#define SPI2_DATIN      (GPIO_IN | 27)
+#define GPI_11          (GPIO_IN | 28)
+
+#define GPIO_IN_MASK   0x1eff83ff
+
+/* OUTPUT GPIOs */
+/* GPO */
+#define GPO_00          (GPIO_OUT | 0)
+#define GPO_01          (GPIO_OUT | 1)
+#define GPO_02          (GPIO_OUT | 2)
+#define GPO_03          (GPIO_OUT | 3)
+#define GPO_04          (GPIO_OUT | 4)
+#define GPO_05          (GPIO_OUT | 5)
+#define GPO_06          (GPIO_OUT | 6)
+#define GPO_07          (GPIO_OUT | 7)
+#define GPO_08          (GPIO_OUT | 8)
+#define GPO_09          (GPIO_OUT | 9)
+#define GPO_10          (GPIO_OUT | 10)
+#define GPO_11          (GPIO_OUT | 11)
+#define GPO_12          (GPIO_OUT | 12)
+#define GPO_13          (GPIO_OUT | 13)
+#define GPO_14          (GPIO_OUT | 14)
+#define GPO_15          (GPIO_OUT | 15)
+#define GPO_16          (GPIO_OUT | 16)
+#define GPO_17          (GPIO_OUT | 17)
+#define GPO_18          (GPIO_OUT | 18)
+#define GPO_19          (GPIO_OUT | 19)
+#define GPO_20          (GPIO_OUT | 20)
+#define GPO_21          (GPIO_OUT | 21)
+#define GPO_22          (GPIO_OUT | 22)
+#define GPO_23          (GPIO_OUT | 23)
+
+#define GPIO_OUT_MASK   0xffffff
+
+/* BIDIRECTIONAL GPIOs */
+/* RAM pins */
+#define RAM_D19         (GPIO_RAM | 0)
+#define RAM_D20         (GPIO_RAM | 1)
+#define RAM_D21         (GPIO_RAM | 2)
+#define RAM_D22         (GPIO_RAM | 3)
+#define RAM_D23         (GPIO_RAM | 4)
+#define RAM_D24         (GPIO_RAM | 5)
+#define RAM_D25         (GPIO_RAM | 6)
+#define RAM_D26         (GPIO_RAM | 7)
+#define RAM_D27         (GPIO_RAM | 8)
+#define RAM_D28         (GPIO_RAM | 9)
+#define RAM_D29         (GPIO_RAM | 10)
+#define RAM_D30         (GPIO_RAM | 11)
+#define RAM_D31         (GPIO_RAM | 12)
+
+#define GPIO_RAM_MASK   0x1fff
+
+/* I/O pins */
+#define GPIO_00         (GPIO_BID | 25)
+#define GPIO_01         (GPIO_BID | 26)
+#define GPIO_02         (GPIO_BID | 27)
+#define GPIO_03         (GPIO_BID | 28)
+#define GPIO_04         (GPIO_BID | 29)
+#define GPIO_05         (GPIO_BID | 30)
+
+#define GPIO_BID_MASK   0x7e000000
+
+/* Non-GPIO multiplexed PIOs. For multiplexing with GPIO, please use GPIO macros */
+#define GPIO_SDRAM_SEL  (GPIO_MUX | 3)
+
+#define GPIO_MUX_MASK   0x8
+
+/* Extraction/assembly macros */
+#define GPIO_BIT_MASK(K) ((K) & 0x1F)
+#define GPIO_BIT(K) (1 << GPIO_BIT_MASK(K))
+#define GPIO_ISMUX(K) ((GPIO_TYPE_MASK(K) == GPIO_MUX) && (GPIO_BIT(K) & GPIO_MUX_MASK))
+#define GPIO_ISRAM(K) ((GPIO_TYPE_MASK(K) == GPIO_RAM) && (GPIO_BIT(K) & GPIO_RAM_MASK))
+#define GPIO_ISBID(K) ((GPIO_TYPE_MASK(K) == GPIO_BID) && (GPIO_BIT(K) & GPIO_BID_MASK))
+#define GPIO_ISOUT(K) ((GPIO_TYPE_MASK(K) == GPIO_OUT) && (GPIO_BIT(K) & GPIO_OUT_MASK))
+#define GPIO_ISIN(K)  ((GPIO_TYPE_MASK(K) == GPIO_IN) && (GPIO_BIT(K) & GPIO_IN_MASK))
+
+/* Start Enable Pin Interrupts - table 58 page 66 */
+
+#define SE_PIN_BASE_INT   32
+
+#define SE_U7_RX_INT            63
+#define SE_U7_HCTS_INT          62
+#define SE_BT_CLKREQ_INT        61
+#define SE_U6_IRRX_INT          60
+/*59 unused*/
+#define SE_U5_RX_INT            58
+#define SE_GPI_11_INT           57
+#define SE_U3_RX_INT            56
+#define SE_U2_HCTS_INT          55
+#define SE_U2_RX_INT            54
+#define SE_U1_RX_INT            53
+#define SE_DISP_SYNC_INT        52
+/*51 unused*/
+#define SE_SDIO_INT_N           50
+#define SE_MSDIO_START_INT      49
+#define SE_GPI_06_INT           48
+#define SE_GPI_05_INT           47
+#define SE_GPI_04_INT           46
+#define SE_GPI_03_INT           45
+#define SE_GPI_02_INT           44
+#define SE_GPI_01_INT           43
+#define SE_GPI_00_INT           42
+#define SE_SYSCLKEN_PIN_INT     41
+#define SE_SPI1_DATAIN_INT      40
+#define SE_GPI_07_INT           39
+#define SE_SPI2_DATAIN_INT      38
+#define SE_GPI_10_INT           37
+#define SE_GPI_09_INT           36
+#define SE_GPI_08_INT           35
+/*34-32 unused*/
+
+/* Start Enable Internal Interrupts - table 57 page 65 */
+
+#define SE_INT_BASE_INT   0
+
+#define SE_TS_IRQ               31
+#define SE_TS_P_INT             30
+#define SE_TS_AUX_INT           29
+/*27-28 unused*/
+#define SE_USB_AHB_NEED_CLK_INT 26
+#define SE_MSTIMER_INT          25
+#define SE_RTC_INT              24
+#define SE_USB_NEED_CLK_INT     23
+#define SE_USB_INT              22
+#define SE_USB_I2C_INT          21
+#define SE_USB_OTG_TIMER_INT    20
+#define SE_USB_OTG_ATX_INT_N    19
+/*18 unused*/
+#define SE_DSP_GPIO4_INT        17
+#define SE_KEY_IRQ              16
+#define SE_DSP_SLAVEPORT_INT    15
+#define SE_DSP_GPIO1_INT        14
+#define SE_DSP_GPIO0_INT        13
+#define SE_DSP_AHB_INT          12
+/*11-6 unused*/
+#define SE_GPIO_05_INT          5
+#define SE_GPIO_04_INT          4
+#define SE_GPIO_03_INT          3
+#define SE_GPIO_02_INT          2
+#define SE_GPIO_01_INT          1
+#define SE_GPIO_00_INT          0
+
+#define START_INT_REG_BIT(irq) (1<<((irq)&0x1F))
+
+#define START_INT_ER_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1)))
+#define START_INT_RSR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1)))
+#define START_INT_SR_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1)))
+#define START_INT_APR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1)))
+
+extern int pnx4008_gpio_register_pin(unsigned short pin);
+extern int pnx4008_gpio_unregister_pin(unsigned short pin);
+extern unsigned long pnx4008_gpio_read_pin(unsigned short pin);
+extern int pnx4008_gpio_write_pin(unsigned short pin, int output);
+extern int pnx4008_gpio_set_pin_direction(unsigned short pin, int output);
+extern int pnx4008_gpio_read_pin_direction(unsigned short pin);
+extern int pnx4008_gpio_set_pin_mux(unsigned short pin, int output);
+extern int pnx4008_gpio_read_pin_mux(unsigned short pin);
+
+static inline void start_int_umask(u8 irq)
+{
+        __raw_writel(__raw_readl(START_INT_ER_REG(irq)) |
+                     START_INT_REG_BIT(irq), START_INT_ER_REG(irq));
+}
+
+static inline void start_int_mask(u8 irq)
+{
+        __raw_writel(__raw_readl(START_INT_ER_REG(irq)) &
+                     ~START_INT_REG_BIT(irq), START_INT_ER_REG(irq));
+}
+
+static inline void start_int_ack(u8 irq)
+{
+        __raw_writel(START_INT_REG_BIT(irq), START_INT_RSR_REG(irq));
+}
+
+static inline void start_int_set_falling_edge(u8 irq)
+{
+        __raw_writel(__raw_readl(START_INT_APR_REG(irq)) &
+                     ~START_INT_REG_BIT(irq), START_INT_APR_REG(irq));
+}
+
+static inline void start_int_set_rising_edge(u8 irq)
+{
+        __raw_writel(__raw_readl(START_INT_APR_REG(irq)) |
+                     START_INT_REG_BIT(irq), START_INT_APR_REG(irq));
+}
+
+#endif                          /* _PNX4008_GPIO_H_ */
diff --git a/arch/arm/mach-pnx4008/include/mach/hardware.h b/arch/arm/mach-pnx4008/include/mach/hardware.h
new file mode 100644
index 000000000000..7b98b828d368
--- /dev/null
+++ b/arch/arm/mach-pnx4008/include/mach/hardware.h
@@ -0,0 +1,32 @@
+/*
+ * arch/arm/mach-pnx4008/include/mach/hardware.h
+ *
+ * Copyright (c) 2005 MontaVista Software, Inc. <source@mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/sizes.h>
+#include <mach/platform.h>
+
+/* Start of virtual addresses for IO devices */
+#define IO_BASE         0xF0000000
+
+/* This macro relies on fact that for all HW i/o addresses bits 20-23 are 0 */
+#define IO_ADDRESS(x)  (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE)
+
+#endif
diff --git a/include/asm-arm/arch-pnx4008/i2c.h b/arch/arm/mach-pnx4008/include/mach/i2c.h
index 92e8d65006f7..92e8d65006f7 100644
--- a/include/asm-arm/arch-pnx4008/i2c.h
+++ b/arch/arm/mach-pnx4008/include/mach/i2c.h
diff --git a/arch/arm/mach-pnx4008/include/mach/io.h b/arch/arm/mach-pnx4008/include/mach/io.h
new file mode 100644
index 000000000000..c6206f25839d
--- /dev/null
+++ b/arch/arm/mach-pnx4008/include/mach/io.h
@@ -0,0 +1,21 @@
+
+/*
+ *  arch/arm/mach-pnx4008/include/mach/io.h
+ *
+ * Author: Dmitry Chigirev <chigirev@ru.mvista.com>
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+#define __io(a)                 ((void __iomem *)(a))
+#define __mem_pci(a)            (a)
+
+#endif
diff --git a/arch/arm/mach-pnx4008/include/mach/irq.h b/arch/arm/mach-pnx4008/include/mach/irq.h
new file mode 100644
index 000000000000..2a690ca33870
--- /dev/null
+++ b/arch/arm/mach-pnx4008/include/mach/irq.h
@@ -0,0 +1,42 @@
+/*
+ * arch/arm/mach-pnx4008/include/mach/irq.h
+ *
+ * PNX4008 IRQ controller driver - header file
+ * this one is used in entry-arnv.S as well so it cannot contain C code
+ *
+ * Copyright (c) 2005 Philips Semiconductors
+ * Copyright (c) 2005 MontaVista Software, Inc.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+#ifndef __PNX4008_IRQ_H__
+#define __PNX4008_IRQ_H__
+
+#define MIC_VA_BASE             IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
+#define SIC1_VA_BASE            IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
+#define SIC2_VA_BASE            IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
+
+/* Manual: Chapter 20, page 195 */
+
+#define INTC_BIT(irq) (1<< ((irq) & 0x1F))
+
+#define INTC_ER(irq)    IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x0 + (((irq)&(0x3<<5))<<9)))
+#define INTC_RSR(irq)   IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x4 + (((irq)&(0x3<<5))<<9)))
+#define INTC_SR(irq)    IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x8 + (((irq)&(0x3<<5))<<9)))
+#define INTC_APR(irq)   IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0xC + (((irq)&(0x3<<5))<<9)))
+#define INTC_ATR(irq)   IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x10 + (((irq)&(0x3<<5))<<9)))
+#define INTC_ITR(irq)   IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x14 + (((irq)&(0x3<<5))<<9)))
+
+#define START_INT_REG_BIT(irq) (1<<((irq)&0x1F))
+
+#define START_INT_ER_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1)))
+#define START_INT_RSR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1)))
+#define START_INT_SR_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1)))
+#define START_INT_APR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1)))
+
+extern void __init pnx4008_init_irq(void);
+
+#endif /* __PNX4008_IRQ_H__ */
diff --git a/arch/arm/mach-pnx4008/include/mach/irqs.h b/arch/arm/mach-pnx4008/include/mach/irqs.h
new file mode 100644
index 000000000000..f6b33cf23ae2
--- /dev/null
+++ b/arch/arm/mach-pnx4008/include/mach/irqs.h
@@ -0,0 +1,215 @@
+/*
+ * arch/arm/mach-pnx4008/include/mach/irqs.h
+ *
+ * PNX4008 IRQ controller driver - header file
+ *
+ * Author: Dmitry Chigirev <source@mvista.com>
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __PNX4008_IRQS_h__
+#define __PNX4008_IRQS_h__
+
+#define NR_IRQS         96
+
+/*Manual: table 259, page 199*/
+
+/*SUB2 Interrupt Routing (SIC2)*/
+
+#define SIC2_BASE_INT   64
+
+#define CLK_SWITCH_ARM_INT 95   /*manual: Clkswitch ARM  */
+#define CLK_SWITCH_DSP_INT 94   /*manual: ClkSwitch DSP  */
+#define CLK_SWITCH_AUD_INT 93   /*manual: Clkswitch AUD  */
+#define GPI_06_INT         92
+#define GPI_05_INT         91
+#define GPI_04_INT         90
+#define GPI_03_INT         89
+#define GPI_02_INT         88
+#define GPI_01_INT         87
+#define GPI_00_INT         86
+#define BT_CLKREQ_INT      85
+#define SPI1_DATIN_INT     84
+#define U5_RX_INT          83
+#define SDIO_INT_N         82
+#define CAM_HS_INT         81
+#define CAM_VS_INT         80
+#define GPI_07_INT         79
+#define DISP_SYNC_INT      78
+#define DSP_INT8           77
+#define U7_HCTS_INT        76
+#define GPI_10_INT         75
+#define GPI_09_INT         74
+#define GPI_08_INT         73
+#define DSP_INT7           72
+#define U2_HCTS_INT        71
+#define SPI2_DATIN_INT     70
+#define GPIO_05_INT        69
+#define GPIO_04_INT        68
+#define GPIO_03_INT        67
+#define GPIO_02_INT        66
+#define GPIO_01_INT        65
+#define GPIO_00_INT        64
+
+/*Manual: table 258, page 198*/
+
+/*SUB1 Interrupt Routing (SIC1)*/
+
+#define SIC1_BASE_INT   32
+
+#define USB_I2C_INT        63
+#define USB_DEV_HP_INT     62
+#define USB_DEV_LP_INT     61
+#define USB_DEV_DMA_INT    60
+#define USB_HOST_INT       59
+#define USB_OTG_ATX_INT_N  58
+#define USB_OTG_TIMER_INT  57
+#define SW_INT             56
+#define SPI1_INT           55
+#define KEY_IRQ            54
+#define DSP_M_INT          53
+#define RTC_INT            52
+#define I2C_1_INT          51
+#define I2C_2_INT          50
+#define PLL1_LOCK_INT      49
+#define PLL2_LOCK_INT      48
+#define PLL3_LOCK_INT      47
+#define PLL4_LOCK_INT      46
+#define PLL5_LOCK_INT      45
+#define SPI2_INT           44
+#define DSP_INT1           43
+#define DSP_INT2           42
+#define DSP_TDM_INT2       41
+#define TS_AUX_INT         40
+#define TS_IRQ             39
+#define TS_P_INT           38
+#define UOUT1_TO_PAD_INT   37
+#define GPI_11_INT         36
+#define DSP_INT4           35
+#define JTAG_COMM_RX_INT   34
+#define JTAG_COMM_TX_INT   33
+#define DSP_INT3           32
+
+/*Manual: table 257, page 197*/
+
+/*MAIN Interrupt Routing*/
+
+#define MAIN_BASE_INT   0
+
+#define SUB2_FIQ_N         31   /*active low */
+#define SUB1_FIQ_N         30   /*active low */
+#define JPEG_INT           29
+#define DMA_INT            28
+#define MSTIMER_INT        27
+#define IIR1_INT           26
+#define IIR2_INT           25
+#define IIR7_INT           24
+#define DSP_TDM_INT0       23
+#define DSP_TDM_INT1       22
+#define DSP_P_INT          21
+#define DSP_INT0           20
+#define DUM_INT            19
+#define UOUT0_TO_PAD_INT   18
+#define MP4_ENC_INT        17
+#define MP4_DEC_INT        16
+#define SD0_INT            15
+#define MBX_INT            14
+#define SD1_INT            13
+#define MS_INT_N           12
+#define FLASH_INT          11 /*NAND*/
+#define IIR6_INT           10
+#define IIR5_INT           9
+#define IIR4_INT           8
+#define IIR3_INT           7
+#define WATCH_INT          6
+#define HSTIMER_INT        5
+#define ARCH_TIMER_IRQ     HSTIMER_INT
+#define CAM_INT            4
+#define PRNG_INT           3
+#define CRYPTO_INT         2
+#define SUB2_IRQ_N         1    /*active low */
+#define SUB1_IRQ_N         0    /*active low */
+
+#define PNX4008_IRQ_TYPES \
+{                                           /*IRQ #'s: */         \
+IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, /*  0, 1, 2, 3 */     \
+IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /*  4, 5, 6, 7 */     \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /*  8, 9,10,11 */     \
+IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 12,13,14,15 */     \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 16,17,18,19 */     \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 20,21,22,23 */     \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 24,25,26,27 */     \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_LOW,  /* 28,29,30,31 */     \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 32,33,34,35 */     \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_FALLING, IRQ_TYPE_LEVEL_HIGH, /* 36,37,38,39 */  \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 40,41,42,43 */     \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 44,45,46,47 */     \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_LOW,  /* 48,49,50,51 */     \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 52,53,54,55 */     \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, /* 56,57,58,59 */     \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 60,61,62,63 */     \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 64,65,66,67 */     \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 68,69,70,71 */     \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 72,73,74,75 */     \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 76,77,78,79 */     \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 80,81,82,83 */     \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 84,85,86,87 */     \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 88,89,90,91 */     \
+IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 92,93,94,95 */     \
+}
+
+/* Start Enable Pin Interrupts - table 58 page 66 */
+
+#define SE_PIN_BASE_INT   32
+
+#define SE_U7_RX_INT            63
+#define SE_U7_HCTS_INT          62
+#define SE_BT_CLKREQ_INT        61
+#define SE_U6_IRRX_INT          60
+/*59 unused*/
+#define SE_U5_RX_INT            58
+#define SE_GPI_11_INT           57
+#define SE_U3_RX_INT            56
+#define SE_U2_HCTS_INT          55
+#define SE_U2_RX_INT            54
+#define SE_U1_RX_INT            53
+#define SE_DISP_SYNC_INT        52
+/*51 unused*/
+#define SE_SDIO_INT_N           50
+#define SE_MSDIO_START_INT      49
+#define SE_GPI_06_INT           48
+#define SE_GPI_05_INT           47
+#define SE_GPI_04_INT           46
+#define SE_GPI_03_INT           45
+#define SE_GPI_02_INT           44
+#define SE_GPI_01_INT           43
+#define SE_GPI_00_INT           42
+#define SE_SYSCLKEN_PIN_INT     41
+#define SE_SPI1_DATAIN_INT      40
+#define SE_GPI_07_INT           39
+#define SE_SPI2_DATAIN_INT      38
+#define SE_GPI_10_INT           37
+#define SE_GPI_09_INT           36
+#define SE_GPI_08_INT           35
+/*34-32 unused*/
+
+/* Start Enable Internal Interrupts - table 57 page 65 */
+
+#define SE_INT_BASE_INT   0
+
+#define SE_TS_IRQ               31
+#define SE_TS_P_INT             30
+#define SE_TS_AUX_INT           29
+/*27-28 unused*/
+#define SE_USB_AHB_NEED_CLK_INT 26
+#define SE_MSTIMER_INT          25
+#define SE_RTC_INT              24
+#define SE_USB_NEED_CLK_INT     23
+#define SE_USB_INT              22
+#define SE_USB_I2C_INT          21
+#define SE_USB_OTG_TIMER_INT    20
+
+#endif /* __PNX4008_IRQS_h__ */
diff --git a/arch/arm/mach-pnx4008/include/mach/memory.h b/arch/arm/mach-pnx4008/include/mach/memory.h
new file mode 100644
index 000000000000..5789a2d16f5a
--- /dev/null
+++ b/arch/arm/mach-pnx4008/include/mach/memory.h
@@ -0,0 +1,24 @@
+/*
+ * arch/arm/mach-pnx4008/include/mach/memory.h
+ *
+ * Copyright (c) 2005 Philips Semiconductors
+ * Copyright (c) 2005 MontaVista Software, Inc.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     (0x80000000)
+
+#define __virt_to_bus(x) ((x) - PAGE_OFFSET + PHYS_OFFSET)
+#define __bus_to_virt(x) ((x) + PAGE_OFFSET - PHYS_OFFSET)
+
+#endif
diff --git a/arch/arm/mach-pnx4008/include/mach/param.h b/arch/arm/mach-pnx4008/include/mach/param.h
new file mode 100644
index 000000000000..6ea02f2176b7
--- /dev/null
+++ b/arch/arm/mach-pnx4008/include/mach/param.h
@@ -0,0 +1,21 @@
+/*
+ *  arch/arm/mach-pnx4008/include/mach/param.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#define HZ 100
diff --git a/arch/arm/mach-pnx4008/include/mach/platform.h b/arch/arm/mach-pnx4008/include/mach/platform.h
new file mode 100644
index 000000000000..368c2c10a308
--- /dev/null
+++ b/arch/arm/mach-pnx4008/include/mach/platform.h
@@ -0,0 +1,69 @@
+/*
+ * arch/arm/mach-pnx4008/include/mach/platform.h
+ *
+ * PNX4008 Base addresses - header file
+ *
+ * Author: Dmitry Chigirev <source@mvista.com>
+ *
+ * Based on reference code received from Philips:
+ * Copyright (C) 2003 Philips Semiconductors
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+
+#ifndef __ASM_ARCH_PLATFORM_H__
+#define __ASM_ARCH_PLATFORM_H__
+
+#define PNX4008_IRAM_BASE               0x08000000
+#define PNX4008_IRAM_SIZE               0x00010000
+#define PNX4008_YUV_SLAVE_BASE          0x10000000
+#define PNX4008_DUM_SLAVE_BASE          0x18000000
+#define PNX4008_NDF_FLASH_BASE          0x20020000
+#define PNX4008_SPI1_BASE               0x20088000
+#define PNX4008_SPI2_BASE               0x20090000
+#define PNX4008_SD_CONFIG_BASE          0x20098000
+#define PNX4008_FLASH_DATA              0x200B0000
+#define PNX4008_MLC_FLASH_BASE          0x200B8000
+#define PNX4008_JPEG_CONFIG_BASE        0x300A0000
+#define PNX4008_DMA_CONFIG_BASE         0x31000000
+#define PNX4008_USB_CONFIG_BASE         0x31020000
+#define PNX4008_SDRAM_CFG_BASE          0x31080000
+#define PNX4008_AHB2FAB_BASE            0x40000000
+#define PNX4008_PWRMAN_BASE             0x40004000
+#define PNX4008_INTCTRLMIC_BASE         0x40008000
+#define PNX4008_INTCTRLSIC1_BASE        0x4000C000
+#define PNX4008_INTCTRLSIC2_BASE        0x40010000
+#define PNX4008_HSUART1_BASE            0x40014000
+#define PNX4008_HSUART2_BASE            0x40018000
+#define PNX4008_HSUART7_BASE            0x4001C000
+#define PNX4008_RTC_BASE                0x40024000
+#define PNX4008_PIO_BASE                0x40028000
+#define PNX4008_MSTIMER_BASE            0x40034000
+#define PNX4008_HSTIMER_BASE            0x40038000
+#define PNX4008_WDOG_BASE               0x4003C000
+#define PNX4008_DEBUG_BASE              0x40040000
+#define PNX4008_TOUCH1_BASE             0x40048000
+#define PNX4008_KEYSCAN_BASE            0x40050000
+#define PNX4008_UARTCTRL_BASE           0x40054000
+#define PNX4008_PWM_BASE                0x4005C000
+#define PNX4008_UART3_BASE              0x40080000
+#define PNX4008_UART4_BASE              0x40088000
+#define PNX4008_UART5_BASE              0x40090000
+#define PNX4008_UART6_BASE              0x40098000
+#define PNX4008_I2C1_BASE               0x400A0000
+#define PNX4008_I2C2_BASE               0x400A8000
+#define PNX4008_MAGICGATE_BASE          0x400B0000
+#define PNX4008_DUMCONF_BASE            0x400B8000
+#define PNX4008_DUM_MAINCFG_BASE        0x400BC000
+#define PNX4008_DSP_BASE                0x400C0000
+#define PNX4008_PROFCOUNTER_BASE        0x400C8000
+#define PNX4008_CRYPTO_BASE             0x400D0000
+#define PNX4008_CAMIFCONF_BASE          0x400D8000
+#define PNX4008_YUV2RGB_BASE            0x400E0000
+#define PNX4008_AUDIOCONFIG_BASE        0x400E8000
+
+#endif
diff --git a/arch/arm/mach-pnx4008/include/mach/pm.h b/arch/arm/mach-pnx4008/include/mach/pm.h
new file mode 100644
index 000000000000..2fa685bff858
--- /dev/null
+++ b/arch/arm/mach-pnx4008/include/mach/pm.h
@@ -0,0 +1,33 @@
+/*
+ * arch/arm/mach-pnx4008/include/mach/pm.h
+ *
+ * PNX4008 Power Management Routiness - header file
+ *
+ * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#ifndef __ASM_ARCH_PNX4008_PM_H
+#define __ASM_ARCH_PNX4008_PM_H
+
+#ifndef __ASSEMBLER__
+#include "irq.h"
+#include "irqs.h"
+#include "clock.h"
+
+extern void pnx4008_pm_idle(void);
+extern void pnx4008_pm_suspend(void);
+extern unsigned int pnx4008_cpu_suspend_sz;
+extern void pnx4008_cpu_suspend(void);
+extern unsigned int pnx4008_cpu_standby_sz;
+extern void pnx4008_cpu_standby(void);
+
+extern int pnx4008_startup_pll(struct clk *);
+extern int pnx4008_shutdown_pll(struct clk *);
+
+#endif                          /* ASSEMBLER */
+#endif                          /* __ASM_ARCH_PNX4008_PM_H */
diff --git a/arch/arm/mach-pnx4008/include/mach/system.h b/arch/arm/mach-pnx4008/include/mach/system.h
new file mode 100644
index 000000000000..8985a4622b8c
--- /dev/null
+++ b/arch/arm/mach-pnx4008/include/mach/system.h
@@ -0,0 +1,38 @@
+/*
+ * arch/arm/mach-pnx4008/include/mach/system.h
+ *
+ * Copyright (C) 2003 Philips Semiconductors
+ * Copyright (C) 2005 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <mach/hardware.h>
+#include <asm/io.h>
+#include <mach/platform.h>
+
+static void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        cpu_reset(0);
+}
+
+#endif
diff --git a/arch/arm/mach-pnx4008/include/mach/timex.h b/arch/arm/mach-pnx4008/include/mach/timex.h
new file mode 100644
index 000000000000..956fbd8e977c
--- /dev/null
+++ b/arch/arm/mach-pnx4008/include/mach/timex.h
@@ -0,0 +1,73 @@
+/*
+ * arch/arm/mach-pnx4008/include/mach/timex.h
+ *
+ * PNX4008 timers header file
+ *
+ * Author: Dmitry Chigirev <source@mvista.com>
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#ifndef __PNX4008_TIMEX_H
+#define __PNX4008_TIMEX_H
+
+#include <mach/hardware.h>
+#include <asm/io.h>
+
+#define CLOCK_TICK_RATE         1000000
+
+#define TICKS2USECS(x)  (x)
+
+/* MilliSecond Timer - Chapter 21 Page 202 */
+
+#define MSTIM_INT     IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x0))
+#define MSTIM_CTRL    IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x4))
+#define MSTIM_COUNTER IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x8))
+#define MSTIM_MCTRL   IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x14))
+#define MSTIM_MATCH0  IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x18))
+#define MSTIM_MATCH1  IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x1c))
+
+/* High Speed Timer - Chpater 22, Page 205 */
+
+#define HSTIM_INT     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x0))
+#define HSTIM_CTRL    IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x4))
+#define HSTIM_COUNTER IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x8))
+#define HSTIM_PMATCH  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0xC))
+#define HSTIM_PCOUNT  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x10))
+#define HSTIM_MCTRL   IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x14))
+#define HSTIM_MATCH0  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x18))
+#define HSTIM_MATCH1  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x1c))
+#define HSTIM_MATCH2  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x20))
+#define HSTIM_CCR     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x28))
+#define HSTIM_CR0     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x2C))
+#define HSTIM_CR1     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x30))
+
+/* IMPORTANT: both timers are UPCOUNTING */
+
+/* xSTIM_MCTRL bit definitions */
+#define MR0_INT        1
+#define RESET_COUNT0   (1<<1)
+#define STOP_COUNT0    (1<<2)
+#define MR1_INT        (1<<3)
+#define RESET_COUNT1   (1<<4)
+#define STOP_COUNT1    (1<<5)
+#define MR2_INT        (1<<6)
+#define RESET_COUNT2   (1<<7)
+#define STOP_COUNT2    (1<<8)
+
+/* xSTIM_CTRL bit definitions */
+#define COUNT_ENAB     1
+#define RESET_COUNT    (1<<1)
+#define DEBUG_EN       (1<<2)
+
+/* xSTIM_INT bit definitions */
+#define MATCH0_INT     1
+#define MATCH1_INT     (1<<1)
+#define MATCH2_INT     (1<<2)
+#define RTC_TICK0      (1<<4)
+#define RTC_TICK1      (1<<5)
+
+#endif
diff --git a/arch/arm/mach-pnx4008/include/mach/uncompress.h b/arch/arm/mach-pnx4008/include/mach/uncompress.h
new file mode 100644
index 000000000000..bb4751ee2539
--- /dev/null
+++ b/arch/arm/mach-pnx4008/include/mach/uncompress.h
@@ -0,0 +1,46 @@
+/*
+ *  arch/arm/mach-pnx4008/include/mach/uncompress.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) 2006 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#define UART5_BASE 0x40090000
+
+#define UART5_DR    (*(volatile unsigned char *) (UART5_BASE))
+#define UART5_FR    (*(volatile unsigned char *) (UART5_BASE + 18))
+
+static __inline__ void putc(char c)
+{
+        while (UART5_FR & (1 << 5))
+                barrier();
+
+        UART5_DR = c;
+}
+
+/*
+ * This does not append a newline
+ */
+static inline void flush(void)
+{
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-pnx4008/include/mach/vmalloc.h b/arch/arm/mach-pnx4008/include/mach/vmalloc.h
new file mode 100644
index 000000000000..2ad398378aed
--- /dev/null
+++ b/arch/arm/mach-pnx4008/include/mach/vmalloc.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/mach-pnx4008/include/mach/vmalloc.h
+ *
+ * Author: Vitaly Wool <source@mvista.com>
+ *
+ * 2006 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
diff --git a/arch/arm/mach-pnx4008/irq.c b/arch/arm/mach-pnx4008/irq.c
index 7eba2929a137..5c4f55af5d4b 100644
--- a/arch/arm/mach-pnx4008/irq.c
+++ b/arch/arm/mach-pnx4008/irq.c
@@ -23,7 +23,7 @@
 #include <linux/ioport.h>
 #include <linux/device.h>
 #include <linux/irq.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/setup.h>
 #include <asm/pgtable.h>
@@ -32,7 +32,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
-#include <asm/arch/irq.h>
+#include <mach/irq.h>
 
 static u8 pnx4008_irq_type[NR_IRQS] = PNX4008_IRQ_TYPES;
 
diff --git a/arch/arm/mach-pnx4008/pm.c b/arch/arm/mach-pnx4008/pm.c
index 52c51f91ed8a..f970906d8848 100644
--- a/arch/arm/mach-pnx4008/pm.c
+++ b/arch/arm/mach-pnx4008/pm.c
@@ -21,8 +21,8 @@
 
 #include <asm/io.h>
 #include <asm/cacheflush.h>
-#include <asm/arch/pm.h>
-#include <asm/arch/clock.h>
+#include <mach/pm.h>
+#include <mach/clock.h>
 
 #define SRAM_VA IO_ADDRESS(PNX4008_IRAM_BASE)
 
diff --git a/arch/arm/mach-pnx4008/serial.c b/arch/arm/mach-pnx4008/serial.c
index a95bd19e00cb..9be84bbb30e8 100644
--- a/arch/arm/mach-pnx4008/serial.c
+++ b/arch/arm/mach-pnx4008/serial.c
@@ -15,14 +15,14 @@
 
 #include <asm/io.h>
 
-#include <asm/arch/platform.h>
-#include <asm/arch/hardware.h>
+#include <mach/platform.h>
+#include <mach/hardware.h>
 
 #include <linux/serial_core.h>
 #include <linux/serial_reg.h>
-#include <asm/arch/gpio.h>
+#include <mach/gpio.h>
 
-#include <asm/arch/clock.h>
+#include <mach/clock.h>
 
 #define UART_3          0
 #define UART_4          1
diff --git a/arch/arm/mach-pnx4008/sleep.S b/arch/arm/mach-pnx4008/sleep.S
index fe6bdcdda4f3..f4eed495d295 100644
--- a/arch/arm/mach-pnx4008/sleep.S
+++ b/arch/arm/mach-pnx4008/sleep.S
@@ -13,7 +13,7 @@
 
 #include <linux/linkage.h>
 #include <asm/assembler.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 #define PWRMAN_VA_BASE IO_ADDRESS(PNX4008_PWRMAN_BASE)
 #define PWR_CTRL_REG_OFFS 0x44
diff --git a/arch/arm/mach-pnx4008/time.c b/arch/arm/mach-pnx4008/time.c
index 616cb3e96059..180975244f96 100644
--- a/arch/arm/mach-pnx4008/time.c
+++ b/arch/arm/mach-pnx4008/time.c
@@ -24,7 +24,7 @@
 #include <linux/irq.h>
 
 #include <asm/system.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/leds.h>
 #include <asm/mach/time.h>
diff --git a/arch/arm/mach-pxa/akita-ioexp.c b/arch/arm/mach-pxa/akita-ioexp.c
index 254892ac30cd..5c67b188a3ba 100644
--- a/arch/arm/mach-pxa/akita-ioexp.c
+++ b/arch/arm/mach-pxa/akita-ioexp.c
@@ -19,7 +19,7 @@
 #include <linux/i2c.h>
 #include <linux/slab.h>
 #include <linux/workqueue.h>
-#include <asm/arch/akita.h>
+#include <mach/akita.h>
 
 /* MAX7310 Regiser Map */
 #define MAX7310_INPUT    0x00
diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c
index d858f9864bfa..c01eea88f787 100644
--- a/arch/arm/mach-pxa/clock.c
+++ b/arch/arm/mach-pxa/clock.c
@@ -12,9 +12,9 @@
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 
-#include <asm/arch/pxa2xx-regs.h>
-#include <asm/arch/pxa2xx-gpio.h>
-#include <asm/arch/hardware.h>
+#include <mach/pxa2xx-regs.h>
+#include <mach/pxa2xx-gpio.h>
+#include <mach/hardware.h>
 
 #include "devices.h"
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/cm-x270-pci.c b/arch/arm/mach-pxa/cm-x270-pci.c
index 31f5bd411ced..2d5bcea1e520 100644
--- a/arch/arm/mach-pxa/cm-x270-pci.c
+++ b/arch/arm/mach-pxa/cm-x270-pci.c
@@ -22,7 +22,7 @@
 #include <linux/gpio.h>
 
 #include <asm/mach/pci.h>
-#include <asm/arch/pxa-regs.h>
+#include <mach/pxa-regs.h>
 #include <asm/mach-types.h>
 
 #include <asm/hardware/it8152.h>
diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c
index 402e807eae54..af003a269534 100644
--- a/arch/arm/mach-pxa/cm-x270.c
+++ b/arch/arm/mach-pxa/cm-x270.c
@@ -23,14 +23,14 @@
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
 
-#include <asm/arch/pxa2xx-regs.h>
-#include <asm/arch/mfp-pxa27x.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/audio.h>
-#include <asm/arch/pxafb.h>
-#include <asm/arch/ohci.h>
-#include <asm/arch/mmc.h>
-#include <asm/arch/bitfield.h>
+#include <mach/pxa2xx-regs.h>
+#include <mach/mfp-pxa27x.h>
+#include <mach/pxa-regs.h>
+#include <mach/audio.h>
+#include <mach/pxafb.h>
+#include <mach/ohci.h>
+#include <mach/mmc.h>
+#include <mach/bitfield.h>
 
 #include <asm/hardware/it8152.h>
 
diff --git a/arch/arm/mach-pxa/colibri.c b/arch/arm/mach-pxa/colibri.c
index c0c81b7a94f6..abce13c846c5 100644
--- a/arch/arm/mach-pxa/colibri.c
+++ b/arch/arm/mach-pxa/colibri.c
@@ -21,16 +21,16 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
 #include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/sizes.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/flash.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-gpio.h>
-#include <asm/arch/colibri.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-gpio.h>
+#include <mach/colibri.h>
 
 #include "generic.h"
 #include "devices.h"
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 8c43e2730026..123a950db466 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -26,7 +26,7 @@
 #include <asm/setup.h>
 #include <asm/memory.h>
 #include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/io.h>
 #include <asm/system.h>
@@ -35,14 +35,14 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-regs.h>
-#include <asm/arch/pxa2xx-gpio.h>
-#include <asm/arch/irda.h>
-#include <asm/arch/mmc.h>
-#include <asm/arch/udc.h>
-#include <asm/arch/corgi.h>
-#include <asm/arch/sharpsl.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-regs.h>
+#include <mach/pxa2xx-gpio.h>
+#include <mach/irda.h>
+#include <mach/mmc.h>
+#include <mach/udc.h>
+#include <mach/corgi.h>
+#include <mach/sharpsl.h>
 
 #include <asm/mach/sharpsl_param.h>
 #include <asm/hardware/scoop.h>
diff --git a/arch/arm/mach-pxa/corgi_lcd.c b/arch/arm/mach-pxa/corgi_lcd.c
index b08290bd5fa0..311baf149b07 100644
--- a/arch/arm/mach-pxa/corgi_lcd.c
+++ b/arch/arm/mach-pxa/corgi_lcd.c
@@ -20,12 +20,12 @@
 #include <linux/platform_device.h>
 #include <linux/module.h>
 #include <linux/string.h>
-#include <asm/arch/akita.h>
-#include <asm/arch/corgi.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/sharpsl.h>
-#include <asm/arch/spitz.h>
+#include <mach/akita.h>
+#include <mach/corgi.h>
+#include <mach/hardware.h>
+#include <mach/pxa-regs.h>
+#include <mach/sharpsl.h>
+#include <mach/spitz.h>
 #include <asm/hardware/scoop.h>
 #include <asm/mach/sharpsl_param.h>
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/corgi_pm.c b/arch/arm/mach-pxa/corgi_pm.c
index abd8b13e7316..35bbfccd2df3 100644
--- a/arch/arm/mach-pxa/corgi_pm.c
+++ b/arch/arm/mach-pxa/corgi_pm.c
@@ -20,14 +20,14 @@
 
 #include <asm/irq.h>
 #include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/hardware/scoop.h>
 
-#include <asm/arch/sharpsl.h>
-#include <asm/arch/corgi.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-regs.h>
-#include <asm/arch/pxa2xx-gpio.h>
+#include <mach/sharpsl.h>
+#include <mach/corgi.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-regs.h>
+#include <mach/pxa2xx-gpio.h>
 #include "sharpsl.h"
 
 #define SHARPSL_CHARGE_ON_VOLT         0x99  /* 2.9V */
diff --git a/arch/arm/mach-pxa/corgi_ssp.c b/arch/arm/mach-pxa/corgi_ssp.c
index 21e616f2bb41..8e2f2215c4ba 100644
--- a/arch/arm/mach-pxa/corgi_ssp.c
+++ b/arch/arm/mach-pxa/corgi_ssp.c
@@ -16,13 +16,13 @@
 #include <linux/slab.h>
 #include <linux/delay.h>
 #include <linux/platform_device.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/ssp.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-gpio.h>
-#include <asm/arch/regs-ssp.h>
+#include <mach/ssp.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-gpio.h>
+#include <mach/regs-ssp.h>
 #include "sharpsl.h"
 
 static DEFINE_SPINLOCK(corgi_ssp_lock);
diff --git a/arch/arm/mach-pxa/cpu-pxa.c b/arch/arm/mach-pxa/cpu-pxa.c
index 8f6075a29961..6f5569bac131 100644
--- a/arch/arm/mach-pxa/cpu-pxa.c
+++ b/arch/arm/mach-pxa/cpu-pxa.c
@@ -37,9 +37,9 @@
 #include <linux/init.h>
 #include <linux/cpufreq.h>
 
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-regs.h>
+#include <mach/hardware.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-regs.h>
 
 #ifdef DEBUG
 static unsigned int freq_debug;
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index 84489dc51d81..35736fc08634 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -4,19 +4,19 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 
-#include <asm/arch/gpio.h>
-#include <asm/arch/udc.h>
-#include <asm/arch/pxafb.h>
-#include <asm/arch/mmc.h>
-#include <asm/arch/irda.h>
-#include <asm/arch/i2c.h>
-#include <asm/arch/mfp-pxa27x.h>
-#include <asm/arch/ohci.h>
-#include <asm/arch/pxa27x_keypad.h>
-#include <asm/arch/pxa2xx_spi.h>
-#include <asm/arch/camera.h>
-#include <asm/arch/audio.h>
-#include <asm/arch/pxa3xx_nand.h>
+#include <mach/gpio.h>
+#include <mach/udc.h>
+#include <mach/pxafb.h>
+#include <mach/mmc.h>
+#include <mach/irda.h>
+#include <mach/i2c.h>
+#include <mach/mfp-pxa27x.h>
+#include <mach/ohci.h>
+#include <mach/pxa27x_keypad.h>
+#include <mach/pxa2xx_spi.h>
+#include <mach/camera.h>
+#include <mach/audio.h>
+#include <mach/pxa3xx_nand.h>
 
 #include "devices.h"
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/dma.c b/arch/arm/mach-pxa/dma.c
index 2532b6d66715..c0be17e0ab82 100644
--- a/arch/arm/mach-pxa/dma.c
+++ b/arch/arm/mach-pxa/dma.c
@@ -20,10 +20,10 @@
 
 #include <asm/system.h>
 #include <asm/irq.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/dma.h>
 
-#include <asm/arch/pxa-regs.h>
+#include <mach/pxa-regs.h>
 
 struct dma_channel {
         char *name;
diff --git a/arch/arm/mach-pxa/e400_lcd.c b/arch/arm/mach-pxa/e400_lcd.c
index 16c023630626..263884165f57 100644
--- a/arch/arm/mach-pxa/e400_lcd.c
+++ b/arch/arm/mach-pxa/e400_lcd.c
@@ -14,8 +14,8 @@
 #include <linux/module.h>
 
 #include <asm/mach-types.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxafb.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxafb.h>
 
 static struct pxafb_mode_info e400_pxafb_mode_info = {
         .pixclock       = 140703,
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index e5cc6ca63c75..7a0a681a5847 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -23,14 +23,14 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <asm/arch/mfp-pxa27x.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa27x-udc.h>
-#include <asm/arch/audio.h>
-#include <asm/arch/pxafb.h>
-#include <asm/arch/ohci.h>
-#include <asm/arch/mmc.h>
-#include <asm/arch/pxa27x_keypad.h>
+#include <mach/mfp-pxa27x.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa27x-udc.h>
+#include <mach/audio.h>
+#include <mach/pxafb.h>
+#include <mach/ohci.h>
+#include <mach/mmc.h>
+#include <mach/pxa27x_keypad.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index c29b7b21c11b..03942450885b 100644
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -14,7 +14,7 @@
 
 #include <asm/setup.h>
 #include <asm/mach/arch.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/eseries_udc.c b/arch/arm/mach-pxa/eseries_udc.c
index 362847a10998..d622c04c0d44 100644
--- a/arch/arm/mach-pxa/eseries_udc.c
+++ b/arch/arm/mach-pxa/eseries_udc.c
@@ -14,10 +14,10 @@
 #include <linux/init.h>
 #include <linux/device.h>
 
-#include <asm/arch/udc.h>
-#include <asm/arch/eseries-gpio.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa-regs.h>
+#include <mach/udc.h>
+#include <mach/eseries-gpio.h>
+#include <mach/hardware.h>
+#include <mach/pxa-regs.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c
index 0143eed65398..cc3d850cc0b6 100644
--- a/arch/arm/mach-pxa/ezx.c
+++ b/arch/arm/mach-pxa/ezx.c
@@ -18,13 +18,13 @@
 #include <linux/pwm_backlight.h>
 
 #include <asm/setup.h>
-#include <asm/arch/pxafb.h>
-#include <asm/arch/ohci.h>
-#include <asm/arch/i2c.h>
+#include <mach/pxafb.h>
+#include <mach/ohci.h>
+#include <mach/i2c.h>
 
-#include <asm/arch/mfp-pxa27x.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-regs.h>
+#include <mach/mfp-pxa27x.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-regs.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index 2106028636f4..2834b7fff78c 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -20,12 +20,12 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/system.h>
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
 
-#include <asm/arch/pxa-regs.h>
+#include <mach/pxa-regs.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-pxa/gpio.c b/arch/arm/mach-pxa/gpio.c
index 1f34f23e1773..07acc1b23857 100644
--- a/arch/arm/mach-pxa/gpio.c
+++ b/arch/arm/mach-pxa/gpio.c
@@ -18,10 +18,10 @@
 #include <linux/sysdev.h>
 
 #include <asm/gpio.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-gpio.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c
index 2bc063639401..c0092472fa58 100644
--- a/arch/arm/mach-pxa/gumstix.c
+++ b/arch/arm/mach-pxa/gumstix.c
@@ -26,7 +26,7 @@
 #include <asm/setup.h>
 #include <asm/memory.h>
 #include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/sizes.h>
 
@@ -34,13 +34,13 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/flash.h>
-#include <asm/arch/mmc.h>
-#include <asm/arch/udc.h>
-#include <asm/arch/gumstix.h>
+#include <mach/mmc.h>
+#include <mach/udc.h>
+#include <mach/gumstix.h>
 
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-regs.h>
-#include <asm/arch/pxa2xx-gpio.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-regs.h>
+#include <mach/pxa2xx-gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c
index a994292fba11..5aa0270d5605 100644
--- a/arch/arm/mach-pxa/idp.c
+++ b/arch/arm/mach-pxa/idp.c
@@ -25,18 +25,18 @@
 #include <asm/setup.h>
 #include <asm/memory.h>
 #include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-gpio.h>
-#include <asm/arch/idp.h>
-#include <asm/arch/pxafb.h>
-#include <asm/arch/bitfield.h>
-#include <asm/arch/mmc.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-gpio.h>
+#include <mach/idp.h>
+#include <mach/pxafb.h>
+#include <mach/bitfield.h>
+#include <mach/mmc.h>
 
 #include "generic.h"
 #include "devices.h"
diff --git a/include/asm-arm/arch-pxa/akita.h b/arch/arm/mach-pxa/include/mach/akita.h
index 5d8cc1d9cb10..5d8cc1d9cb10 100644
--- a/include/asm-arm/arch-pxa/akita.h
+++ b/arch/arm/mach-pxa/include/mach/akita.h
diff --git a/include/asm-arm/arch-pxa/audio.h b/arch/arm/mach-pxa/include/mach/audio.h
index f82f96dd1053..f82f96dd1053 100644
--- a/include/asm-arm/arch-pxa/audio.h
+++ b/arch/arm/mach-pxa/include/mach/audio.h
diff --git a/include/asm-arm/arch-pxa/bitfield.h b/arch/arm/mach-pxa/include/mach/bitfield.h
index f1f0e3387d9c..f1f0e3387d9c 100644
--- a/include/asm-arm/arch-pxa/bitfield.h
+++ b/arch/arm/mach-pxa/include/mach/bitfield.h
diff --git a/include/asm-arm/arch-pxa/camera.h b/arch/arm/mach-pxa/include/mach/camera.h
index 39516ced8b1f..39516ced8b1f 100644
--- a/include/asm-arm/arch-pxa/camera.h
+++ b/arch/arm/mach-pxa/include/mach/camera.h
diff --git a/include/asm-arm/arch-pxa/colibri.h b/arch/arm/mach-pxa/include/mach/colibri.h
index 2ae373fb5675..2ae373fb5675 100644
--- a/include/asm-arm/arch-pxa/colibri.h
+++ b/arch/arm/mach-pxa/include/mach/colibri.h
diff --git a/include/asm-arm/arch-pxa/corgi.h b/arch/arm/mach-pxa/include/mach/corgi.h
index bf856503baf6..bf856503baf6 100644
--- a/include/asm-arm/arch-pxa/corgi.h
+++ b/arch/arm/mach-pxa/include/mach/corgi.h
diff --git a/arch/arm/mach-pxa/include/mach/debug-macro.S b/arch/arm/mach-pxa/include/mach/debug-macro.S
new file mode 100644
index 000000000000..55d6a175ab19
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/debug-macro.S
@@ -0,0 +1,25 @@
+/* arch/arm/mach-pxa/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include "hardware.h"
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx, #0x40000000                @ physical
+                movne   \rx, #io_p2v(0x40000000)        @ virtual
+                orr     \rx, \rx, #0x00100000
+                .endm
+
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-pxa/include/mach/dma.h b/arch/arm/mach-pxa/include/mach/dma.h
new file mode 100644
index 000000000000..955bfe606067
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/dma.h
@@ -0,0 +1,50 @@
+/*
+ *  arch/arm/mach-pxa/include/mach/dma.h
+ *
+ *  Author:     Nicolas Pitre
+ *  Created:    Jun 15, 2001
+ *  Copyright:  MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+/*
+ * Descriptor structure for PXA's DMA engine
+ * Note: this structure must always be aligned to a 16-byte boundary.
+ */
+
+typedef struct pxa_dma_desc {
+        volatile u32 ddadr;     /* Points to the next descriptor + flags */
+        volatile u32 dsadr;     /* DSADR value for the current transfer */
+        volatile u32 dtadr;     /* DTADR value for the current transfer */
+        volatile u32 dcmd;      /* DCMD value for the current transfer */
+} pxa_dma_desc;
+
+typedef enum {
+        DMA_PRIO_HIGH = 0,
+        DMA_PRIO_MEDIUM = 1,
+        DMA_PRIO_LOW = 2
+} pxa_dma_prio;
+
+#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
+#define HAVE_ARCH_PCI_SET_DMA_MASK      1
+#endif
+
+/*
+ * DMA registration
+ */
+
+int __init pxa_init_dma(int num_ch);
+
+int pxa_request_dma (char *name,
+                         pxa_dma_prio prio,
+                         void (*irq_handler)(int, void *),
+                         void *data);
+
+void pxa_free_dma (int dma_ch);
+
+#endif /* _ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-pxa/include/mach/entry-macro.S b/arch/arm/mach-pxa/include/mach/entry-macro.S
new file mode 100644
index 000000000000..de16c12d5232
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/entry-macro.S
@@ -0,0 +1,57 @@
+/*
+ * arch/arm/mach-pxa/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for PXA-based platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_preamble, base, tmp
+                .endm
+
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                mrc     p15, 0, \tmp, c0, c0, 0         @ CPUID
+                mov     \tmp, \tmp, lsr #13
+                and     \tmp, \tmp, #0x7                @ Core G
+                cmp     \tmp, #1
+                bhi     1004f
+
+                mov     \base, #io_p2v(0x40000000)      @ IIR Ctl = 0x40d00000
+                add     \base, \base, #0x00d00000
+                ldr     \irqstat, [\base, #0]           @ ICIP
+                ldr     \irqnr, [\base, #4]             @ ICMR
+                b       1002f
+
+1004:
+                mrc     p6, 0, \irqstat, c6, c0, 0      @ ICIP2
+                mrc     p6, 0, \irqnr, c7, c0, 0        @ ICMR2
+                ands    \irqnr, \irqstat, \irqnr
+                beq     1003f
+                rsb     \irqstat, \irqnr, #0
+                and     \irqstat, \irqstat, \irqnr
+                clz     \irqnr, \irqstat
+                rsb     \irqnr, \irqnr, #31
+                add     \irqnr, \irqnr, #32
+                b       1001f
+1003:
+                mrc     p6, 0, \irqstat, c0, c0, 0      @ ICIP
+                mrc     p6, 0, \irqnr, c1, c0, 0        @ ICMR
+1002:
+                ands    \irqnr, \irqstat, \irqnr
+                beq     1001f
+                rsb     \irqstat, \irqnr, #0
+                and     \irqstat, \irqstat, \irqnr
+                clz     \irqnr, \irqstat
+                rsb     \irqnr, \irqnr, #31
+1001:
+                .endm
diff --git a/include/asm-arm/arch-pxa/eseries-gpio.h b/arch/arm/mach-pxa/include/mach/eseries-gpio.h
index 4c90b1310270..4c90b1310270 100644
--- a/include/asm-arm/arch-pxa/eseries-gpio.h
+++ b/arch/arm/mach-pxa/include/mach/eseries-gpio.h
diff --git a/include/asm-arm/arch-pxa/eseries-irq.h b/arch/arm/mach-pxa/include/mach/eseries-irq.h
index f2a93d5e31d3..f2a93d5e31d3 100644
--- a/include/asm-arm/arch-pxa/eseries-irq.h
+++ b/arch/arm/mach-pxa/include/mach/eseries-irq.h
diff --git a/arch/arm/mach-pxa/include/mach/gpio.h b/arch/arm/mach-pxa/include/mach/gpio.h
new file mode 100644
index 000000000000..2c538d8c362d
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/gpio.h
@@ -0,0 +1,65 @@
+/*
+ * arch/arm/mach-pxa/include/mach/gpio.h
+ *
+ * PXA GPIO wrappers for arch-neutral GPIO calls
+ *
+ * Written by Philipp Zabel <philipp.zabel@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARCH_PXA_GPIO_H
+#define __ASM_ARCH_PXA_GPIO_H
+
+#include <mach/pxa-regs.h>
+#include <asm/irq.h>
+#include <mach/hardware.h>
+
+#include <asm-generic/gpio.h>
+
+
+/* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85).
+ * Those cases currently cause holes in the GPIO number space.
+ */
+#define NR_BUILTIN_GPIO 128
+
+static inline int gpio_get_value(unsigned gpio)
+{
+        if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO))
+                return GPLR(gpio) & GPIO_bit(gpio);
+        else
+                return __gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+        if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) {
+                if (value)
+                        GPSR(gpio) = GPIO_bit(gpio);
+                else
+                        GPCR(gpio) = GPIO_bit(gpio);
+        } else {
+                __gpio_set_value(gpio, value);
+        }
+}
+
+#define gpio_cansleep __gpio_cansleep
+
+#define gpio_to_irq(gpio)       IRQ_GPIO(gpio)
+#define irq_to_gpio(irq)        IRQ_TO_GPIO(irq)
+
+
+#endif
diff --git a/arch/arm/mach-pxa/include/mach/gumstix.h b/arch/arm/mach-pxa/include/mach/gumstix.h
new file mode 100644
index 000000000000..42ee1956750e
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/gumstix.h
@@ -0,0 +1,96 @@
+/*
+ *  arch/arm/mach-pxa/include/mach/gumstix.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+
+/* BTRESET - Reset line to Bluetooth module, active low signal. */
+#define GPIO_GUMSTIX_BTRESET          7
+#define GPIO_GUMSTIX_BTRESET_MD         (GPIO_GUMSTIX_BTRESET | GPIO_OUT)
+
+
+/*
+GPIOn - Input from MAX823 (or equiv), normalizing USB +5V into a clean
+interrupt signal for determining cable presence. On the original gumstix,
+this is GPIO81, and GPIO83 needs to be defined as well. On the gumstix F,
+this moves to GPIO17 and GPIO37. */
+
+/* GPIOx - Connects to USB D+ and used as a pull-up after GPIOn
+has detected a cable insertion; driven low otherwise. */
+
+#ifdef CONFIG_ARCH_GUMSTIX_ORIG
+
+#define GPIO_GUMSTIX_USB_GPIOn          81
+#define GPIO_GUMSTIX_USB_GPIOx          83
+
+#else
+
+#define GPIO_GUMSTIX_USB_GPIOn          35
+#define GPIO_GUMSTIX_USB_GPIOx          41
+
+#endif
+
+/* usb state change */
+#define GUMSTIX_USB_INTR_IRQ            IRQ_GPIO(GPIO_GUMSTIX_USB_GPIOn)
+
+#define GPIO_GUMSTIX_USB_GPIOn_MD       (GPIO_GUMSTIX_USB_GPIOn | GPIO_IN)
+#define GPIO_GUMSTIX_USB_GPIOx_CON_MD   (GPIO_GUMSTIX_USB_GPIOx | GPIO_OUT)
+#define GPIO_GUMSTIX_USB_GPIOx_DIS_MD   (GPIO_GUMSTIX_USB_GPIOx | GPIO_IN)
+
+/*
+ * SD/MMC definitions
+ */
+#define GUMSTIX_GPIO_nSD_WP             22 /* SD Write Protect */
+#define GUMSTIX_GPIO_nSD_DETECT         11 /* MMC/SD Card Detect */
+#define GUMSTIX_IRQ_GPIO_nSD_DETECT     IRQ_GPIO(GUMSTIX_GPIO_nSD_DETECT)
+
+/*
+ * SMC Ethernet definitions
+ * ETH_RST provides a hardware reset line to the ethernet chip
+ * ETH is the IRQ line in from the ethernet chip to the PXA
+ */
+#define GPIO_GUMSTIX_ETH0_RST           80
+#define GPIO_GUMSTIX_ETH0_RST_MD        (GPIO_GUMSTIX_ETH0_RST | GPIO_OUT)
+#define GPIO_GUMSTIX_ETH1_RST           52
+#define GPIO_GUMSTIX_ETH1_RST_MD        (GPIO_GUMSTIX_ETH1_RST | GPIO_OUT)
+
+#define GPIO_GUMSTIX_ETH0               36
+#define GPIO_GUMSTIX_ETH0_MD            (GPIO_GUMSTIX_ETH0 | GPIO_IN)
+#define GUMSTIX_ETH0_IRQ                IRQ_GPIO(GPIO_GUMSTIX_ETH0)
+#define GPIO_GUMSTIX_ETH1               27
+#define GPIO_GUMSTIX_ETH1_MD            (GPIO_GUMSTIX_ETH1 | GPIO_IN)
+#define GUMSTIX_ETH1_IRQ                IRQ_GPIO(GPIO_GUMSTIX_ETH1)
+
+
+/* CF reset line */
+#define GPIO8_RESET                     8
+
+/* CF slot 0 */
+#define GPIO4_nBVD1                     4
+#define GPIO4_nSTSCHG                   GPIO4_nBVD1
+#define GPIO11_nCD                      11
+#define GPIO26_PRDY_nBSY                26
+#define GUMSTIX_S0_nSTSCHG_IRQ          IRQ_GPIO(GPIO4_nSTSCHG)
+#define GUMSTIX_S0_nCD_IRQ              IRQ_GPIO(GPIO11_nCD)
+#define GUMSTIX_S0_PRDY_nBSY_IRQ        IRQ_GPIO(GPIO26_PRDY_nBSY)
+
+/* CF slot 1 */
+#define GPIO18_nBVD1                    18
+#define GPIO18_nSTSCHG                  GPIO18_nBVD1
+#define GPIO36_nCD                      36
+#define GPIO27_PRDY_nBSY                27
+#define GUMSTIX_S1_nSTSCHG_IRQ          IRQ_GPIO(GPIO18_nSTSCHG)
+#define GUMSTIX_S1_nCD_IRQ              IRQ_GPIO(GPIO36_nCD)
+#define GUMSTIX_S1_PRDY_nBSY_IRQ        IRQ_GPIO(GPIO27_PRDY_nBSY)
+
+/* CF GPIO line modes */
+#define GPIO4_nSTSCHG_MD                (GPIO4_nSTSCHG | GPIO_IN)
+#define GPIO8_RESET_MD                  (GPIO8_RESET | GPIO_OUT)
+#define GPIO11_nCD_MD                   (GPIO11_nCD | GPIO_IN)
+#define GPIO18_nSTSCHG_MD               (GPIO18_nSTSCHG | GPIO_IN)
+#define GPIO26_PRDY_nBSY_MD             (GPIO26_PRDY_nBSY | GPIO_IN)
+#define GPIO27_PRDY_nBSY_MD             (GPIO27_PRDY_nBSY | GPIO_IN)
+#define GPIO36_nCD_MD                   (GPIO36_nCD | GPIO_IN)
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
new file mode 100644
index 000000000000..f8fb1e75997f
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/hardware.h
@@ -0,0 +1,240 @@
+/*
+ *  arch/arm/mach-pxa/include/mach/hardware.h
+ *
+ *  Author:     Nicolas Pitre
+ *  Created:    Jun 15, 2001
+ *  Copyright:  MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+/*
+ * We requires absolute addresses.
+ */
+#define PCIO_BASE               0
+
+/*
+ * Workarounds for at least 2 errata so far require this.
+ * The mapping is set in mach-pxa/generic.c.
+ */
+#define UNCACHED_PHYS_0         0xff000000
+#define UNCACHED_ADDR           UNCACHED_PHYS_0
+
+/*
+ * Intel PXA2xx internal register mapping:
+ *
+ * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
+ * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
+ * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
+ * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
+ * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
+ * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
+ * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
+ *
+ * Note that not all PXA2xx chips implement all those addresses, and the
+ * kernel only maps the minimum needed range of this mapping.
+ */
+#define io_p2v(x) (0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
+#define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
+
+#ifndef __ASSEMBLY__
+
+# define __REG(x)       (*((volatile u32 *)io_p2v(x)))
+
+/* With indexed regs we don't want to feed the index through io_p2v()
+   especially if it is a variable, otherwise horrible code will result. */
+# define __REG2(x,y)    \
+        (*(volatile u32 *)((u32)&__REG(x) + (y)))
+
+# define __PREG(x)      (io_v2p((u32)&(x)))
+
+#else
+
+# define __REG(x)       io_p2v(x)
+# define __PREG(x)      io_v2p(x)
+
+#endif
+
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_PXA25x
+#define __cpu_is_pxa21x(id)                             \
+        ({                                              \
+                unsigned int _id = (id) >> 4 & 0xf3f;   \
+                _id == 0x212;                           \
+        })
+
+#define __cpu_is_pxa255(id)                             \
+        ({                                              \
+                unsigned int _id = (id) >> 4 & 0xfff;   \
+                _id == 0x2d0;                           \
+         })
+
+#define __cpu_is_pxa25x(id)                             \
+        ({                                              \
+                unsigned int _id = (id) >> 4 & 0xfff;   \
+                _id == 0x2d0 || _id == 0x290;           \
+        })
+#else
+#define __cpu_is_pxa21x(id)     (0)
+#define __cpu_is_pxa255(id)     (0)
+#define __cpu_is_pxa25x(id)     (0)
+#endif
+
+#ifdef CONFIG_PXA27x
+#define __cpu_is_pxa27x(id)                             \
+        ({                                              \
+                unsigned int _id = (id) >> 4 & 0xfff;   \
+                _id == 0x411;                           \
+        })
+#else
+#define __cpu_is_pxa27x(id)     (0)
+#endif
+
+#ifdef CONFIG_CPU_PXA300
+#define __cpu_is_pxa300(id)                             \
+        ({                                              \
+                unsigned int _id = (id) >> 4 & 0xfff;   \
+                _id == 0x688;                           \
+         })
+#else
+#define __cpu_is_pxa300(id)     (0)
+#endif
+
+#ifdef CONFIG_CPU_PXA310
+#define __cpu_is_pxa310(id)                             \
+        ({                                              \
+                unsigned int _id = (id) >> 4 & 0xfff;   \
+                _id == 0x689;                           \
+         })
+#else
+#define __cpu_is_pxa310(id)     (0)
+#endif
+
+#ifdef CONFIG_CPU_PXA320
+#define __cpu_is_pxa320(id)                             \
+        ({                                              \
+                unsigned int _id = (id) >> 4 & 0xfff;   \
+                _id == 0x603 || _id == 0x682;           \
+         })
+#else
+#define __cpu_is_pxa320(id)     (0)
+#endif
+
+#ifdef CONFIG_CPU_PXA930
+#define __cpu_is_pxa930(id)                             \
+        ({                                              \
+                unsigned int _id = (id) >> 4 & 0xfff;   \
+                _id == 0x683;           \
+         })
+#else
+#define __cpu_is_pxa930(id)     (0)
+#endif
+
+#define cpu_is_pxa21x()                                 \
+        ({                                              \
+                __cpu_is_pxa21x(read_cpuid_id());       \
+        })
+
+#define cpu_is_pxa255()                                 \
+        ({                                              \
+                __cpu_is_pxa255(read_cpuid_id());       \
+        })
+
+#define cpu_is_pxa25x()                                 \
+        ({                                              \
+                __cpu_is_pxa25x(read_cpuid_id());       \
+        })
+
+#define cpu_is_pxa27x()                                 \
+        ({                                              \
+                __cpu_is_pxa27x(read_cpuid_id());       \
+        })
+
+#define cpu_is_pxa300()                                 \
+        ({                                              \
+                __cpu_is_pxa300(read_cpuid_id());       \
+         })
+
+#define cpu_is_pxa310()                                 \
+        ({                                              \
+                __cpu_is_pxa310(read_cpuid_id());       \
+         })
+
+#define cpu_is_pxa320()                                 \
+        ({                                              \
+                __cpu_is_pxa320(read_cpuid_id());       \
+         })
+
+#define cpu_is_pxa930()                                 \
+        ({                                              \
+                unsigned int id = read_cpuid(CPUID_ID); \
+                __cpu_is_pxa930(id);                    \
+         })
+
+/*
+ * CPUID Core Generation Bit
+ * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
+ * == 0x3 for pxa300/pxa310/pxa320
+ */
+#define __cpu_is_pxa2xx(id)                             \
+        ({                                              \
+                unsigned int _id = (id) >> 13 & 0x7;    \
+                _id <= 0x2;                             \
+         })
+
+#define __cpu_is_pxa3xx(id)                             \
+        ({                                              \
+                unsigned int _id = (id) >> 13 & 0x7;    \
+                _id == 0x3;                             \
+         })
+
+#define cpu_is_pxa2xx()                                 \
+        ({                                              \
+                __cpu_is_pxa2xx(read_cpuid_id());       \
+         })
+
+#define cpu_is_pxa3xx()                                 \
+        ({                                              \
+                __cpu_is_pxa3xx(read_cpuid_id());       \
+         })
+
+/*
+ * Handy routine to set GPIO alternate functions
+ */
+extern int pxa_gpio_mode( int gpio_mode );
+
+/*
+ * Return GPIO level, nonzero means high, zero is low
+ */
+extern int pxa_gpio_get_value(unsigned gpio);
+
+/*
+ * Set output GPIO level
+ */
+extern void pxa_gpio_set_value(unsigned gpio, int value);
+
+/*
+ * return current memory and LCD clock frequency in units of 10kHz
+ */
+extern unsigned int get_memclk_frequency_10khz(void);
+
+/*
+ * register GPIO as reset generator
+ */
+extern int init_gpio_reset(int gpio);
+
+#endif
+
+#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
+#define PCIBIOS_MIN_IO          0
+#define PCIBIOS_MIN_MEM         0
+#define pcibios_assign_all_busses()     1
+#endif
+
+#endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-pxa/i2c.h b/arch/arm/mach-pxa/include/mach/i2c.h
index 80596b013443..80596b013443 100644
--- a/include/asm-arm/arch-pxa/i2c.h
+++ b/arch/arm/mach-pxa/include/mach/i2c.h
diff --git a/arch/arm/mach-pxa/include/mach/idp.h b/arch/arm/mach-pxa/include/mach/idp.h
new file mode 100644
index 000000000000..5eff96fcc944
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/idp.h
@@ -0,0 +1,199 @@
+/*
+ *  arch/arm/mach-pxa/include/mach/idp.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Copyright (c) 2001 Cliff Brake, Accelent Systems Inc.
+ *
+ * 2001-09-13: Cliff Brake <cbrake@accelent.com>
+ *             Initial code
+ *
+ * 2005-02-15: Cliff Brake <cliff.brake@gmail.com>
+ *             <http://www.vibren.com> <http://bec-systems.com>
+ *             Changes for 2.6 kernel.
+ */
+
+
+/*
+ * Note: this file must be safe to include in assembly files
+ *
+ * Support for the Vibren PXA255 IDP requires rev04 or later
+ * IDP hardware.
+ */
+
+
+#define IDP_FLASH_PHYS          (PXA_CS0_PHYS)
+#define IDP_ALT_FLASH_PHYS      (PXA_CS1_PHYS)
+#define IDP_MEDIAQ_PHYS         (PXA_CS3_PHYS)
+#define IDP_IDE_PHYS            (PXA_CS5_PHYS + 0x03000000)
+#define IDP_ETH_PHYS            (PXA_CS5_PHYS + 0x03400000)
+#define IDP_COREVOLT_PHYS       (PXA_CS5_PHYS + 0x03800000)
+#define IDP_CPLD_PHYS           (PXA_CS5_PHYS + 0x03C00000)
+
+
+/*
+ * virtual memory map
+ */
+
+#define IDP_COREVOLT_VIRT       (0xf0000000)
+#define IDP_COREVOLT_SIZE       (1*1024*1024)
+
+#define IDP_CPLD_VIRT           (IDP_COREVOLT_VIRT + IDP_COREVOLT_SIZE)
+#define IDP_CPLD_SIZE           (1*1024*1024)
+
+#if (IDP_CPLD_VIRT + IDP_CPLD_SIZE) > 0xfc000000
+#error Your custom IO space is getting a bit large !!
+#endif
+
+#define CPLD_P2V(x)             ((x) - IDP_CPLD_PHYS + IDP_CPLD_VIRT)
+#define CPLD_V2P(x)             ((x) - IDP_CPLD_VIRT + IDP_CPLD_PHYS)
+
+#ifndef __ASSEMBLY__
+#  define __CPLD_REG(x)         (*((volatile unsigned long *)CPLD_P2V(x)))
+#else
+#  define __CPLD_REG(x)         CPLD_P2V(x)
+#endif
+
+/* board level registers in the CPLD: (offsets from CPLD_VIRT) */
+
+#define _IDP_CPLD_REV                   (IDP_CPLD_PHYS + 0x00)
+#define _IDP_CPLD_PERIPH_PWR            (IDP_CPLD_PHYS + 0x04)
+#define _IDP_CPLD_LED_CONTROL           (IDP_CPLD_PHYS + 0x08)
+#define _IDP_CPLD_KB_COL_HIGH           (IDP_CPLD_PHYS + 0x0C)
+#define _IDP_CPLD_KB_COL_LOW            (IDP_CPLD_PHYS + 0x10)
+#define _IDP_CPLD_PCCARD_EN             (IDP_CPLD_PHYS + 0x14)
+#define _IDP_CPLD_GPIOH_DIR             (IDP_CPLD_PHYS + 0x18)
+#define _IDP_CPLD_GPIOH_VALUE           (IDP_CPLD_PHYS + 0x1C)
+#define _IDP_CPLD_GPIOL_DIR             (IDP_CPLD_PHYS + 0x20)
+#define _IDP_CPLD_GPIOL_VALUE           (IDP_CPLD_PHYS + 0x24)
+#define _IDP_CPLD_PCCARD_PWR            (IDP_CPLD_PHYS + 0x28)
+#define _IDP_CPLD_MISC_CTRL             (IDP_CPLD_PHYS + 0x2C)
+#define _IDP_CPLD_LCD                   (IDP_CPLD_PHYS + 0x30)
+#define _IDP_CPLD_FLASH_WE              (IDP_CPLD_PHYS + 0x34)
+
+#define _IDP_CPLD_KB_ROW                (IDP_CPLD_PHYS + 0x50)
+#define _IDP_CPLD_PCCARD0_STATUS        (IDP_CPLD_PHYS + 0x54)
+#define _IDP_CPLD_PCCARD1_STATUS        (IDP_CPLD_PHYS + 0x58)
+#define _IDP_CPLD_MISC_STATUS           (IDP_CPLD_PHYS + 0x5C)
+
+/* FPGA register virtual addresses */
+
+#define IDP_CPLD_REV                    __CPLD_REG(_IDP_CPLD_REV)
+#define IDP_CPLD_PERIPH_PWR             __CPLD_REG(_IDP_CPLD_PERIPH_PWR)
+#define IDP_CPLD_LED_CONTROL            __CPLD_REG(_IDP_CPLD_LED_CONTROL)
+#define IDP_CPLD_KB_COL_HIGH            __CPLD_REG(_IDP_CPLD_KB_COL_HIGH)
+#define IDP_CPLD_KB_COL_LOW             __CPLD_REG(_IDP_CPLD_KB_COL_LOW)
+#define IDP_CPLD_PCCARD_EN              __CPLD_REG(_IDP_CPLD_PCCARD_EN)
+#define IDP_CPLD_GPIOH_DIR              __CPLD_REG(_IDP_CPLD_GPIOH_DIR)
+#define IDP_CPLD_GPIOH_VALUE            __CPLD_REG(_IDP_CPLD_GPIOH_VALUE)
+#define IDP_CPLD_GPIOL_DIR              __CPLD_REG(_IDP_CPLD_GPIOL_DIR)
+#define IDP_CPLD_GPIOL_VALUE            __CPLD_REG(_IDP_CPLD_GPIOL_VALUE)
+#define IDP_CPLD_PCCARD_PWR             __CPLD_REG(_IDP_CPLD_PCCARD_PWR)
+#define IDP_CPLD_MISC_CTRL              __CPLD_REG(_IDP_CPLD_MISC_CTRL)
+#define IDP_CPLD_LCD                    __CPLD_REG(_IDP_CPLD_LCD)
+#define IDP_CPLD_FLASH_WE               __CPLD_REG(_IDP_CPLD_FLASH_WE)
+
+#define IDP_CPLD_KB_ROW                 __CPLD_REG(_IDP_CPLD_KB_ROW)
+#define IDP_CPLD_PCCARD0_STATUS         __CPLD_REG(_IDP_CPLD_PCCARD0_STATUS)
+#define IDP_CPLD_PCCARD1_STATUS         __CPLD_REG(_IDP_CPLD_PCCARD1_STATUS)
+#define IDP_CPLD_MISC_STATUS            __CPLD_REG(_IDP_CPLD_MISC_STATUS)
+
+
+/*
+ * Bit masks for various registers
+ */
+
+// IDP_CPLD_PCCARD_PWR
+#define PCC0_PWR0       (1 << 0)
+#define PCC0_PWR1       (1 << 1)
+#define PCC0_PWR2       (1 << 2)
+#define PCC0_PWR3       (1 << 3)
+#define PCC1_PWR0       (1 << 4)
+#define PCC1_PWR1       (1 << 5)
+#define PCC1_PWR2       (1 << 6)
+#define PCC1_PWR3       (1 << 7)
+
+// IDP_CPLD_PCCARD_EN
+#define PCC0_RESET      (1 << 6)
+#define PCC1_RESET      (1 << 7)
+#define PCC0_ENABLE     (1 << 0)
+#define PCC1_ENABLE     (1 << 1)
+
+// IDP_CPLD_PCCARDx_STATUS
+#define _PCC_WRPROT     (1 << 7) // 7-4 read as low true
+#define _PCC_RESET      (1 << 6)
+#define _PCC_IRQ        (1 << 5)
+#define _PCC_INPACK     (1 << 4)
+#define PCC_BVD2        (1 << 3)
+#define PCC_BVD1        (1 << 2)
+#define PCC_VS2         (1 << 1)
+#define PCC_VS1         (1 << 0)
+
+#define PCC_DETECT(x)   (GPLR(7 + (x)) & GPIO_bit(7 + (x)))
+
+/* A listing of interrupts used by external hardware devices */
+
+#define TOUCH_PANEL_IRQ                 IRQ_GPIO(5)
+#define IDE_IRQ                         IRQ_GPIO(21)
+
+#define TOUCH_PANEL_IRQ_EDGE            IRQ_TYPE_EDGE_FALLING
+
+#define ETHERNET_IRQ                    IRQ_GPIO(4)
+#define ETHERNET_IRQ_EDGE               IRQ_TYPE_EDGE_RISING
+
+#define IDE_IRQ_EDGE                    IRQ_TYPE_EDGE_RISING
+
+#define PCMCIA_S0_CD_VALID              IRQ_GPIO(7)
+#define PCMCIA_S0_CD_VALID_EDGE         IRQ_TYPE_EDGE_BOTH
+
+#define PCMCIA_S1_CD_VALID              IRQ_GPIO(8)
+#define PCMCIA_S1_CD_VALID_EDGE         IRQ_TYPE_EDGE_BOTH
+
+#define PCMCIA_S0_RDYINT                IRQ_GPIO(19)
+#define PCMCIA_S1_RDYINT                IRQ_GPIO(22)
+
+
+/*
+ * Macros for LED Driver
+ */
+
+/* leds 0 = ON */
+#define IDP_HB_LED      (1<<5)
+#define IDP_BUSY_LED    (1<<6)
+
+#define IDP_LEDS_MASK   (IDP_HB_LED | IDP_BUSY_LED)
+
+/*
+ * macros for MTD driver
+ */
+
+#define FLASH_WRITE_PROTECT_DISABLE()   ((IDP_CPLD_FLASH_WE) &= ~(0x1))
+#define FLASH_WRITE_PROTECT_ENABLE()    ((IDP_CPLD_FLASH_WE) |= (0x1))
+
+/*
+ * macros for matrix keyboard driver
+ */
+
+#define KEYBD_MATRIX_NUMBER_INPUTS      7
+#define KEYBD_MATRIX_NUMBER_OUTPUTS     14
+
+#define KEYBD_MATRIX_INVERT_OUTPUT_LOGIC        FALSE
+#define KEYBD_MATRIX_INVERT_INPUT_LOGIC         FALSE
+
+#define KEYBD_MATRIX_SETTLING_TIME_US                   100
+#define KEYBD_MATRIX_KEYSTATE_DEBOUNCE_CONSTANT         2
+
+#define KEYBD_MATRIX_SET_OUTPUTS(outputs) \
+{\
+        IDP_CPLD_KB_COL_LOW = outputs;\
+        IDP_CPLD_KB_COL_HIGH = outputs >> 7;\
+}
+
+#define KEYBD_MATRIX_GET_INPUTS(inputs) \
+{\
+        inputs = (IDP_CPLD_KB_ROW & 0x7f);\
+}
+
+
diff --git a/arch/arm/mach-pxa/include/mach/io.h b/arch/arm/mach-pxa/include/mach/io.h
new file mode 100644
index 000000000000..600fd4f76603
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/io.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/mach-pxa/include/mach/io.h
+ *
+ * Copied from asm/arch/sa1100/io.h
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#include <mach/hardware.h>
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * We don't actually have real ISA nor PCI buses, but there is so many
+ * drivers out there that might just work if we fake them...
+ */
+#define __io(a)                 ((void __iomem *)(a))
+#define __mem_pci(a)            (a)
+
+#endif
diff --git a/include/asm-arm/arch-pxa/irda.h b/arch/arm/mach-pxa/include/mach/irda.h
index 0a50c3c763df..0a50c3c763df 100644
--- a/include/asm-arm/arch-pxa/irda.h
+++ b/arch/arm/mach-pxa/include/mach/irda.h
diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h
new file mode 100644
index 000000000000..32772bc6925c
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/irqs.h
@@ -0,0 +1,264 @@
+/*
+ *  arch/arm/mach-pxa/include/mach/irqs.h
+ *
+ *  Author:     Nicolas Pitre
+ *  Created:    Jun 15, 2001
+ *  Copyright:  MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+
+#define PXA_IRQ(x)      (x)
+
+#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
+#define IRQ_SSP3        PXA_IRQ(0)      /* SSP3 service request */
+#define IRQ_MSL         PXA_IRQ(1)      /* MSL Interface interrupt */
+#define IRQ_USBH2       PXA_IRQ(2)      /* USB Host interrupt 1 (OHCI) */
+#define IRQ_USBH1       PXA_IRQ(3)      /* USB Host interrupt 2 (non-OHCI) */
+#define IRQ_KEYPAD      PXA_IRQ(4)      /* Key pad controller */
+#define IRQ_MEMSTK      PXA_IRQ(5)      /* Memory Stick interrupt */
+#define IRQ_PWRI2C      PXA_IRQ(6)      /* Power I2C interrupt */
+#endif
+
+#define IRQ_HWUART      PXA_IRQ(7)      /* HWUART Transmit/Receive/Error (PXA26x) */
+#define IRQ_OST_4_11    PXA_IRQ(7)      /* OS timer 4-11 matches (PXA27x) */
+#define IRQ_GPIO0       PXA_IRQ(8)      /* GPIO0 Edge Detect */
+#define IRQ_GPIO1       PXA_IRQ(9)      /* GPIO1 Edge Detect */
+#define IRQ_GPIO_2_x    PXA_IRQ(10)     /* GPIO[2-x] Edge Detect */
+#define IRQ_USB         PXA_IRQ(11)     /* USB Service */
+#define IRQ_PMU         PXA_IRQ(12)     /* Performance Monitoring Unit */
+#define IRQ_I2S         PXA_IRQ(13)     /* I2S Interrupt */
+#define IRQ_AC97        PXA_IRQ(14)     /* AC97 Interrupt */
+#define IRQ_ASSP        PXA_IRQ(15)     /* Audio SSP Service Request (PXA25x) */
+#define IRQ_USIM        PXA_IRQ(15)     /* Smart Card interface interrupt (PXA27x) */
+#define IRQ_NSSP        PXA_IRQ(16)     /* Network SSP Service Request (PXA25x) */
+#define IRQ_SSP2        PXA_IRQ(16)     /* SSP2 interrupt (PXA27x) */
+#define IRQ_LCD         PXA_IRQ(17)     /* LCD Controller Service Request */
+#define IRQ_I2C         PXA_IRQ(18)     /* I2C Service Request */
+#define IRQ_ICP         PXA_IRQ(19)     /* ICP Transmit/Receive/Error */
+#define IRQ_STUART      PXA_IRQ(20)     /* STUART Transmit/Receive/Error */
+#define IRQ_BTUART      PXA_IRQ(21)     /* BTUART Transmit/Receive/Error */
+#define IRQ_FFUART      PXA_IRQ(22)     /* FFUART Transmit/Receive/Error*/
+#define IRQ_MMC         PXA_IRQ(23)     /* MMC Status/Error Detection */
+#define IRQ_SSP         PXA_IRQ(24)     /* SSP Service Request */
+#define IRQ_DMA         PXA_IRQ(25)     /* DMA Channel Service Request */
+#define IRQ_OST0        PXA_IRQ(26)     /* OS Timer match 0 */
+#define IRQ_OST1        PXA_IRQ(27)     /* OS Timer match 1 */
+#define IRQ_OST2        PXA_IRQ(28)     /* OS Timer match 2 */
+#define IRQ_OST3        PXA_IRQ(29)     /* OS Timer match 3 */
+#define IRQ_RTC1Hz      PXA_IRQ(30)     /* RTC HZ Clock Tick */
+#define IRQ_RTCAlrm     PXA_IRQ(31)     /* RTC Alarm */
+
+#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
+#define IRQ_TPM         PXA_IRQ(32)     /* TPM interrupt */
+#define IRQ_CAMERA      PXA_IRQ(33)     /* Camera Interface */
+#endif
+
+#ifdef CONFIG_PXA3xx
+#define IRQ_SSP4        PXA_IRQ(13)     /* SSP4 service request */
+#define IRQ_CIR         PXA_IRQ(34)     /* Consumer IR */
+#define IRQ_TSI         PXA_IRQ(36)     /* Touch Screen Interface (PXA320) */
+#define IRQ_USIM2       PXA_IRQ(38)     /* USIM2 Controller */
+#define IRQ_GRPHICS     PXA_IRQ(39)     /* Graphics Controller */
+#define IRQ_MMC2        PXA_IRQ(41)     /* MMC2 Controller */
+#define IRQ_1WIRE       PXA_IRQ(44)     /* 1-Wire Controller */
+#define IRQ_NAND        PXA_IRQ(45)     /* NAND Controller */
+#define IRQ_USB2        PXA_IRQ(46)     /* USB 2.0 Device Controller */
+#define IRQ_WAKEUP0     PXA_IRQ(49)     /* EXT_WAKEUP0 */
+#define IRQ_WAKEUP1     PXA_IRQ(50)     /* EXT_WAKEUP1 */
+#define IRQ_DMEMC       PXA_IRQ(51)     /* Dynamic Memory Controller */
+#define IRQ_MMC3        PXA_IRQ(55)     /* MMC3 Controller (PXA310) */
+#endif
+
+#define PXA_GPIO_IRQ_BASE       (64)
+#define PXA_GPIO_IRQ_NUM        (128)
+
+#define GPIO_2_x_TO_IRQ(x)      (PXA_GPIO_IRQ_BASE + (x))
+#define IRQ_GPIO(x)     (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x))
+
+#define IRQ_TO_GPIO_2_x(i)      ((i) - PXA_GPIO_IRQ_BASE)
+#define IRQ_TO_GPIO(i)  (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i))
+
+/*
+ * The next 16 interrupts are for board specific purposes.  Since
+ * the kernel can only run on one machine at a time, we can re-use
+ * these.  If you need more, increase IRQ_BOARD_END, but keep it
+ * within sensible limits.
+ */
+#define IRQ_BOARD_START         (PXA_GPIO_IRQ_BASE + PXA_GPIO_IRQ_NUM)
+#define IRQ_BOARD_END           (IRQ_BOARD_START + 16)
+
+#define IRQ_SA1111_START        (IRQ_BOARD_END)
+#define IRQ_GPAIN0              (IRQ_BOARD_END + 0)
+#define IRQ_GPAIN1              (IRQ_BOARD_END + 1)
+#define IRQ_GPAIN2              (IRQ_BOARD_END + 2)
+#define IRQ_GPAIN3              (IRQ_BOARD_END + 3)
+#define IRQ_GPBIN0              (IRQ_BOARD_END + 4)
+#define IRQ_GPBIN1              (IRQ_BOARD_END + 5)
+#define IRQ_GPBIN2              (IRQ_BOARD_END + 6)
+#define IRQ_GPBIN3              (IRQ_BOARD_END + 7)
+#define IRQ_GPBIN4              (IRQ_BOARD_END + 8)
+#define IRQ_GPBIN5              (IRQ_BOARD_END + 9)
+#define IRQ_GPCIN0              (IRQ_BOARD_END + 10)
+#define IRQ_GPCIN1              (IRQ_BOARD_END + 11)
+#define IRQ_GPCIN2              (IRQ_BOARD_END + 12)
+#define IRQ_GPCIN3              (IRQ_BOARD_END + 13)
+#define IRQ_GPCIN4              (IRQ_BOARD_END + 14)
+#define IRQ_GPCIN5              (IRQ_BOARD_END + 15)
+#define IRQ_GPCIN6              (IRQ_BOARD_END + 16)
+#define IRQ_GPCIN7              (IRQ_BOARD_END + 17)
+#define IRQ_MSTXINT             (IRQ_BOARD_END + 18)
+#define IRQ_MSRXINT             (IRQ_BOARD_END + 19)
+#define IRQ_MSSTOPERRINT        (IRQ_BOARD_END + 20)
+#define IRQ_TPTXINT             (IRQ_BOARD_END + 21)
+#define IRQ_TPRXINT             (IRQ_BOARD_END + 22)
+#define IRQ_TPSTOPERRINT        (IRQ_BOARD_END + 23)
+#define SSPXMTINT               (IRQ_BOARD_END + 24)
+#define SSPRCVINT               (IRQ_BOARD_END + 25)
+#define SSPROR                  (IRQ_BOARD_END + 26)
+#define AUDXMTDMADONEA          (IRQ_BOARD_END + 32)
+#define AUDRCVDMADONEA          (IRQ_BOARD_END + 33)
+#define AUDXMTDMADONEB          (IRQ_BOARD_END + 34)
+#define AUDRCVDMADONEB          (IRQ_BOARD_END + 35)
+#define AUDTFSR                 (IRQ_BOARD_END + 36)
+#define AUDRFSR                 (IRQ_BOARD_END + 37)
+#define AUDTUR                  (IRQ_BOARD_END + 38)
+#define AUDROR                  (IRQ_BOARD_END + 39)
+#define AUDDTS                  (IRQ_BOARD_END + 40)
+#define AUDRDD                  (IRQ_BOARD_END + 41)
+#define AUDSTO                  (IRQ_BOARD_END + 42)
+#define IRQ_USBPWR              (IRQ_BOARD_END + 43)
+#define IRQ_HCIM                (IRQ_BOARD_END + 44)
+#define IRQ_HCIBUFFACC          (IRQ_BOARD_END + 45)
+#define IRQ_HCIRMTWKP           (IRQ_BOARD_END + 46)
+#define IRQ_NHCIMFCIR           (IRQ_BOARD_END + 47)
+#define IRQ_USB_PORT_RESUME     (IRQ_BOARD_END + 48)
+#define IRQ_S0_READY_NINT       (IRQ_BOARD_END + 49)
+#define IRQ_S1_READY_NINT       (IRQ_BOARD_END + 50)
+#define IRQ_S0_CD_VALID         (IRQ_BOARD_END + 51)
+#define IRQ_S1_CD_VALID         (IRQ_BOARD_END + 52)
+#define IRQ_S0_BVD1_STSCHG      (IRQ_BOARD_END + 53)
+#define IRQ_S1_BVD1_STSCHG      (IRQ_BOARD_END + 54)
+
+#define IRQ_LOCOMO_START        (IRQ_BOARD_END)
+#define IRQ_LOCOMO_KEY          (IRQ_BOARD_END + 0)
+#define IRQ_LOCOMO_GPIO0        (IRQ_BOARD_END + 1)
+#define IRQ_LOCOMO_GPIO1        (IRQ_BOARD_END + 2)
+#define IRQ_LOCOMO_GPIO2        (IRQ_BOARD_END + 3)
+#define IRQ_LOCOMO_GPIO3        (IRQ_BOARD_END + 4)
+#define IRQ_LOCOMO_GPIO4        (IRQ_BOARD_END + 5)
+#define IRQ_LOCOMO_GPIO5        (IRQ_BOARD_END + 6)
+#define IRQ_LOCOMO_GPIO6        (IRQ_BOARD_END + 7)
+#define IRQ_LOCOMO_GPIO7        (IRQ_BOARD_END + 8)
+#define IRQ_LOCOMO_GPIO8        (IRQ_BOARD_END + 9)
+#define IRQ_LOCOMO_GPIO9        (IRQ_BOARD_END + 10)
+#define IRQ_LOCOMO_GPIO10       (IRQ_BOARD_END + 11)
+#define IRQ_LOCOMO_GPIO11       (IRQ_BOARD_END + 12)
+#define IRQ_LOCOMO_GPIO12       (IRQ_BOARD_END + 13)
+#define IRQ_LOCOMO_GPIO13       (IRQ_BOARD_END + 14)
+#define IRQ_LOCOMO_GPIO14       (IRQ_BOARD_END + 15)
+#define IRQ_LOCOMO_GPIO15       (IRQ_BOARD_END + 16)
+#define IRQ_LOCOMO_LT           (IRQ_BOARD_END + 17)
+#define IRQ_LOCOMO_SPI_RFR      (IRQ_BOARD_END + 18)
+#define IRQ_LOCOMO_SPI_RFW      (IRQ_BOARD_END + 19)
+#define IRQ_LOCOMO_SPI_OVRN     (IRQ_BOARD_END + 20)
+#define IRQ_LOCOMO_SPI_TEND     (IRQ_BOARD_END + 21)
+
+/*
+ * Figure out the MAX IRQ number.
+ *
+ * If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1.
+ * If we have an LoCoMo, the max IRQ is IRQ_LOCOMO_SPI_TEND+1
+ * Otherwise, we have the standard IRQs only.
+ */
+#ifdef CONFIG_SA1111
+#define NR_IRQS                 (IRQ_S1_BVD1_STSCHG + 1)
+#elif defined(CONFIG_SHARP_LOCOMO)
+#define NR_IRQS                 (IRQ_LOCOMO_SPI_TEND + 1)
+#elif defined(CONFIG_ARCH_LUBBOCK) || \
+      defined(CONFIG_MACH_LOGICPD_PXA270) || \
+      defined(CONFIG_MACH_TOSA) || \
+      defined(CONFIG_MACH_MAINSTONE) || \
+      defined(CONFIG_MACH_PCM027) || \
+      defined(CONFIG_MACH_MAGICIAN)
+#define NR_IRQS                 (IRQ_BOARD_END)
+#elif defined(CONFIG_MACH_ZYLONITE)
+#define NR_IRQS                 (IRQ_BOARD_START + 32)
+#else
+#define NR_IRQS                 (IRQ_BOARD_START)
+#endif
+
+/*
+ * Board specific IRQs.  Define them here.
+ * Do not surround them with ifdefs.
+ */
+#define LUBBOCK_IRQ(x)          (IRQ_BOARD_START + (x))
+#define LUBBOCK_SD_IRQ          LUBBOCK_IRQ(0)
+#define LUBBOCK_SA1111_IRQ      LUBBOCK_IRQ(1)
+#define LUBBOCK_USB_IRQ         LUBBOCK_IRQ(2)  /* usb connect */
+#define LUBBOCK_ETH_IRQ         LUBBOCK_IRQ(3)
+#define LUBBOCK_UCB1400_IRQ     LUBBOCK_IRQ(4)
+#define LUBBOCK_BB_IRQ          LUBBOCK_IRQ(5)
+#define LUBBOCK_USB_DISC_IRQ    LUBBOCK_IRQ(6)  /* usb disconnect */
+#define LUBBOCK_LAST_IRQ        LUBBOCK_IRQ(6)
+
+#define LPD270_IRQ(x)           (IRQ_BOARD_START + (x))
+#define LPD270_USBC_IRQ         LPD270_IRQ(2)
+#define LPD270_ETHERNET_IRQ     LPD270_IRQ(3)
+#define LPD270_AC97_IRQ         LPD270_IRQ(4)
+
+#define MAINSTONE_IRQ(x)        (IRQ_BOARD_START + (x))
+#define MAINSTONE_MMC_IRQ       MAINSTONE_IRQ(0)
+#define MAINSTONE_USIM_IRQ      MAINSTONE_IRQ(1)
+#define MAINSTONE_USBC_IRQ      MAINSTONE_IRQ(2)
+#define MAINSTONE_ETHERNET_IRQ  MAINSTONE_IRQ(3)
+#define MAINSTONE_AC97_IRQ      MAINSTONE_IRQ(4)
+#define MAINSTONE_PEN_IRQ       MAINSTONE_IRQ(5)
+#define MAINSTONE_MSINS_IRQ     MAINSTONE_IRQ(6)
+#define MAINSTONE_EXBRD_IRQ     MAINSTONE_IRQ(7)
+#define MAINSTONE_S0_CD_IRQ     MAINSTONE_IRQ(9)
+#define MAINSTONE_S0_STSCHG_IRQ MAINSTONE_IRQ(10)
+#define MAINSTONE_S0_IRQ        MAINSTONE_IRQ(11)
+#define MAINSTONE_S1_CD_IRQ     MAINSTONE_IRQ(13)
+#define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14)
+#define MAINSTONE_S1_IRQ        MAINSTONE_IRQ(15)
+
+/* LoCoMo Interrupts (CONFIG_SHARP_LOCOMO) */
+#define IRQ_LOCOMO_KEY_BASE     (IRQ_BOARD_START + 0)
+#define IRQ_LOCOMO_GPIO_BASE    (IRQ_BOARD_START + 1)
+#define IRQ_LOCOMO_LT_BASE      (IRQ_BOARD_START + 2)
+#define IRQ_LOCOMO_SPI_BASE     (IRQ_BOARD_START + 3)
+
+/* phyCORE-PXA270 (PCM027) Interrupts */
+#define PCM027_IRQ(x)          (IRQ_BOARD_START + (x))
+#define PCM027_BTDET_IRQ       PCM027_IRQ(0)
+#define PCM027_FF_RI_IRQ       PCM027_IRQ(1)
+#define PCM027_MMCDET_IRQ      PCM027_IRQ(2)
+#define PCM027_PM_5V_IRQ       PCM027_IRQ(3)
+
+/* ITE8152 irqs */
+/* add IT8152 IRQs beyond BOARD_END */
+#ifdef CONFIG_PCI_HOST_ITE8152
+#define IT8152_IRQ(x)   (IRQ_BOARD_END + (x))
+
+/* IRQ-sources in 3 groups - local devices, LPC (serial), and external PCI */
+#define IT8152_LD_IRQ_COUNT     9
+#define IT8152_LP_IRQ_COUNT     16
+#define IT8152_PD_IRQ_COUNT     15
+
+/* Priorities: */
+#define IT8152_PD_IRQ(i)        IT8152_IRQ(i)
+#define IT8152_LP_IRQ(i)        (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT)
+#define IT8152_LD_IRQ(i)        (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT + IT8152_LP_IRQ_COUNT)
+
+#define IT8152_LAST_IRQ         IT8152_LD_IRQ(IT8152_LD_IRQ_COUNT - 1)
+
+#if NR_IRQS < (IT8152_LAST_IRQ+1)
+#undef NR_IRQS
+#define NR_IRQS (IT8152_LAST_IRQ+1)
+#endif
+
+#endif /* CONFIG_PCI_HOST_ITE8152 */
diff --git a/include/asm-arm/arch-pxa/littleton.h b/arch/arm/mach-pxa/include/mach/littleton.h
index 79d209b826f4..79d209b826f4 100644
--- a/include/asm-arm/arch-pxa/littleton.h
+++ b/arch/arm/mach-pxa/include/mach/littleton.h
diff --git a/arch/arm/mach-pxa/include/mach/lpd270.h b/arch/arm/mach-pxa/include/mach/lpd270.h
new file mode 100644
index 000000000000..f89fb715266b
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/lpd270.h
@@ -0,0 +1,38 @@
+/*
+ * arch/arm/mach-pxa/include/mach/lpd270.h
+ *
+ * Author:      Lennert Buytenhek
+ * Created:     Feb 10, 2006
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_LPD270_H
+#define __ASM_ARCH_LPD270_H
+
+#define LPD270_CPLD_PHYS        PXA_CS2_PHYS
+#define LPD270_CPLD_VIRT        0xf0000000
+#define LPD270_CPLD_SIZE        0x00100000
+
+#define LPD270_ETH_PHYS         (PXA_CS2_PHYS + 0x01000000)
+
+/* CPLD registers  */
+#define LPD270_CPLD_REG(x)      ((unsigned long)(LPD270_CPLD_VIRT + (x)))
+#define LPD270_CONTROL          LPD270_CPLD_REG(0x00)
+#define LPD270_PERIPHERAL0      LPD270_CPLD_REG(0x04)
+#define LPD270_PERIPHERAL1      LPD270_CPLD_REG(0x08)
+#define LPD270_CPLD_REVISION    LPD270_CPLD_REG(0x14)
+#define LPD270_EEPROM_SPI_ITF   LPD270_CPLD_REG(0x20)
+#define LPD270_MODE_PINS        LPD270_CPLD_REG(0x24)
+#define LPD270_EGPIO            LPD270_CPLD_REG(0x30)
+#define LPD270_INT_MASK         LPD270_CPLD_REG(0x40)
+#define LPD270_INT_STATUS       LPD270_CPLD_REG(0x50)
+
+#define LPD270_INT_AC97         (1 << 4)  /* AC'97 CODEC IRQ */
+#define LPD270_INT_ETHERNET     (1 << 3)  /* Ethernet controller IRQ */
+#define LPD270_INT_USBC         (1 << 2)  /* USB client cable detection IRQ */
+
+
+#endif
diff --git a/arch/arm/mach-pxa/include/mach/lubbock.h b/arch/arm/mach-pxa/include/mach/lubbock.h
new file mode 100644
index 000000000000..4cb24154a5a8
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/lubbock.h
@@ -0,0 +1,40 @@
+/*
+ *  arch/arm/mach-pxa/include/mach/lubbock.h
+ *
+ *  Author:     Nicolas Pitre
+ *  Created:    Jun 15, 2001
+ *  Copyright:  MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define LUBBOCK_ETH_PHYS        PXA_CS3_PHYS
+
+#define LUBBOCK_FPGA_PHYS       PXA_CS2_PHYS
+#define LUBBOCK_FPGA_VIRT       (0xf0000000)
+#define LUB_P2V(x)              ((x) - LUBBOCK_FPGA_PHYS + LUBBOCK_FPGA_VIRT)
+#define LUB_V2P(x)              ((x) - LUBBOCK_FPGA_VIRT + LUBBOCK_FPGA_PHYS)
+
+#ifndef __ASSEMBLY__
+#  define __LUB_REG(x)          (*((volatile unsigned long *)LUB_P2V(x)))
+#else
+#  define __LUB_REG(x)          LUB_P2V(x)
+#endif
+
+/* FPGA register virtual addresses */
+#define LUB_WHOAMI              __LUB_REG(LUBBOCK_FPGA_PHYS + 0x000)
+#define LUB_HEXLED              __LUB_REG(LUBBOCK_FPGA_PHYS + 0x010)
+#define LUB_DISC_BLNK_LED       __LUB_REG(LUBBOCK_FPGA_PHYS + 0x040)
+#define LUB_CONF_SWITCHES       __LUB_REG(LUBBOCK_FPGA_PHYS + 0x050)
+#define LUB_USER_SWITCHES       __LUB_REG(LUBBOCK_FPGA_PHYS + 0x060)
+#define LUB_MISC_WR             __LUB_REG(LUBBOCK_FPGA_PHYS + 0x080)
+#define LUB_MISC_RD             __LUB_REG(LUBBOCK_FPGA_PHYS + 0x090)
+#define LUB_IRQ_MASK_EN         __LUB_REG(LUBBOCK_FPGA_PHYS + 0x0c0)
+#define LUB_IRQ_SET_CLR         __LUB_REG(LUBBOCK_FPGA_PHYS + 0x0d0)
+#define LUB_GP                  __LUB_REG(LUBBOCK_FPGA_PHYS + 0x100)
+
+#ifndef __ASSEMBLY__
+extern void lubbock_set_misc_wr(unsigned int mask, unsigned int set);
+#endif
diff --git a/arch/arm/mach-pxa/include/mach/magician.h b/arch/arm/mach-pxa/include/mach/magician.h
new file mode 100644
index 000000000000..38d68d99f585
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/magician.h
@@ -0,0 +1,117 @@
+/*
+ * GPIO and IRQ definitions for HTC Magician PDA phones
+ *
+ * Copyright (c) 2007 Philipp Zabel
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _MAGICIAN_H_
+#define _MAGICIAN_H_
+
+#include <mach/irqs.h>
+
+/*
+ * PXA GPIOs
+ */
+
+#define GPIO0_MAGICIAN_KEY_POWER                0
+#define GPIO9_MAGICIAN_UNKNOWN                  9
+#define GPIO10_MAGICIAN_GSM_IRQ                 10
+#define GPIO11_MAGICIAN_GSM_OUT1                11
+#define GPIO13_MAGICIAN_CPLD_IRQ                13
+#define GPIO18_MAGICIAN_UNKNOWN                 18
+#define GPIO22_MAGICIAN_VIBRA_EN                22
+#define GPIO26_MAGICIAN_GSM_POWER               26
+#define GPIO27_MAGICIAN_USBC_PUEN               27
+#define GPIO30_MAGICIAN_nCHARGE_EN              30
+#define GPIO37_MAGICIAN_KEY_HANGUP              37
+#define GPIO38_MAGICIAN_KEY_CONTACTS            38
+#define GPIO40_MAGICIAN_GSM_OUT2                40
+#define GPIO48_MAGICIAN_UNKNOWN                 48
+#define GPIO56_MAGICIAN_UNKNOWN                 56
+#define GPIO57_MAGICIAN_CAM_RESET               57
+#define GPIO75_MAGICIAN_SAMSUNG_POWER           75
+#define GPIO83_MAGICIAN_nIR_EN                  83
+#define GPIO86_MAGICIAN_GSM_RESET               86
+#define GPIO87_MAGICIAN_GSM_SELECT              87
+#define GPIO90_MAGICIAN_KEY_CALENDAR            90
+#define GPIO91_MAGICIAN_KEY_CAMERA              91
+#define GPIO93_MAGICIAN_KEY_UP                  93
+#define GPIO94_MAGICIAN_KEY_DOWN                94
+#define GPIO95_MAGICIAN_KEY_LEFT                95
+#define GPIO96_MAGICIAN_KEY_RIGHT               96
+#define GPIO97_MAGICIAN_KEY_ENTER               97
+#define GPIO98_MAGICIAN_KEY_RECORD              98
+#define GPIO99_MAGICIAN_HEADPHONE_IN            99
+#define GPIO100_MAGICIAN_KEY_VOL_UP             100
+#define GPIO101_MAGICIAN_KEY_VOL_DOWN           101
+#define GPIO102_MAGICIAN_KEY_PHONE              102
+#define GPIO103_MAGICIAN_LED_KP                 103
+#define GPIO104_MAGICIAN_LCD_POWER_1            104
+#define GPIO105_MAGICIAN_LCD_POWER_2            105
+#define GPIO106_MAGICIAN_LCD_POWER_3            106
+#define GPIO107_MAGICIAN_DS1WM_IRQ              107
+#define GPIO108_MAGICIAN_GSM_READY              108
+#define GPIO114_MAGICIAN_UNKNOWN                114
+#define GPIO115_MAGICIAN_nPEN_IRQ               115
+#define GPIO116_MAGICIAN_nCAM_EN                116
+#define GPIO119_MAGICIAN_UNKNOWN                119
+#define GPIO120_MAGICIAN_UNKNOWN                120
+
+/*
+ * CPLD IRQs
+ */
+
+#define IRQ_MAGICIAN_SD         (IRQ_BOARD_START + 0)
+#define IRQ_MAGICIAN_EP         (IRQ_BOARD_START + 1)
+#define IRQ_MAGICIAN_BT         (IRQ_BOARD_START + 2)
+#define IRQ_MAGICIAN_AC         (IRQ_BOARD_START + 3)
+
+/*
+ * CPLD EGPIOs
+ */
+
+#define MAGICIAN_EGPIO_BASE                     0x80 /* GPIO_BOARD_START */
+#define MAGICIAN_EGPIO(reg,bit) \
+        (MAGICIAN_EGPIO_BASE + 8*reg + bit)
+
+/* output */
+
+#define EGPIO_MAGICIAN_TOPPOLY_POWER            MAGICIAN_EGPIO(0, 2)
+#define EGPIO_MAGICIAN_LED_POWER                MAGICIAN_EGPIO(0, 5)
+#define EGPIO_MAGICIAN_GSM_RESET                MAGICIAN_EGPIO(0, 6)
+#define EGPIO_MAGICIAN_LCD_POWER                MAGICIAN_EGPIO(0, 7)
+#define EGPIO_MAGICIAN_SPK_POWER                MAGICIAN_EGPIO(1, 0)
+#define EGPIO_MAGICIAN_EP_POWER                 MAGICIAN_EGPIO(1, 1)
+#define EGPIO_MAGICIAN_IN_SEL0                  MAGICIAN_EGPIO(1, 2)
+#define EGPIO_MAGICIAN_IN_SEL1                  MAGICIAN_EGPIO(1, 3)
+#define EGPIO_MAGICIAN_MIC_POWER                MAGICIAN_EGPIO(1, 4)
+#define EGPIO_MAGICIAN_CODEC_RESET              MAGICIAN_EGPIO(1, 5)
+#define EGPIO_MAGICIAN_CODEC_POWER              MAGICIAN_EGPIO(1, 6)
+#define EGPIO_MAGICIAN_BL_POWER                 MAGICIAN_EGPIO(1, 7)
+#define EGPIO_MAGICIAN_SD_POWER                 MAGICIAN_EGPIO(2, 0)
+#define EGPIO_MAGICIAN_CARKIT_MIC               MAGICIAN_EGPIO(2, 1)
+#define EGPIO_MAGICIAN_UNKNOWN_WAVEDEV_DLL      MAGICIAN_EGPIO(2, 2)
+#define EGPIO_MAGICIAN_FLASH_VPP                MAGICIAN_EGPIO(2, 3)
+#define EGPIO_MAGICIAN_BL_POWER2                MAGICIAN_EGPIO(2, 4)
+#define EGPIO_MAGICIAN_CHARGE_EN                MAGICIAN_EGPIO(2, 5)
+#define EGPIO_MAGICIAN_GSM_POWER                MAGICIAN_EGPIO(2, 7)
+
+/* input */
+
+#define EGPIO_MAGICIAN_CABLE_STATE_AC           MAGICIAN_EGPIO(4, 0)
+#define EGPIO_MAGICIAN_CABLE_STATE_USB          MAGICIAN_EGPIO(4, 1)
+
+#define EGPIO_MAGICIAN_BOARD_ID0                MAGICIAN_EGPIO(5, 0)
+#define EGPIO_MAGICIAN_BOARD_ID1                MAGICIAN_EGPIO(5, 1)
+#define EGPIO_MAGICIAN_BOARD_ID2                MAGICIAN_EGPIO(5, 2)
+#define EGPIO_MAGICIAN_LCD_SELECT               MAGICIAN_EGPIO(5, 3)
+#define EGPIO_MAGICIAN_nSD_READONLY             MAGICIAN_EGPIO(5, 4)
+
+#define EGPIO_MAGICIAN_EP_INSERT                MAGICIAN_EGPIO(6, 1)
+
+#endif /* _MAGICIAN_H_ */
diff --git a/arch/arm/mach-pxa/include/mach/mainstone.h b/arch/arm/mach-pxa/include/mach/mainstone.h
new file mode 100644
index 000000000000..3461c4302ff4
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/mainstone.h
@@ -0,0 +1,120 @@
+/*
+ *  arch/arm/mach-pxa/include/mach/mainstone.h
+ *
+ *  Author:     Nicolas Pitre
+ *  Created:    Nov 14, 2002
+ *  Copyright:  MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef ASM_ARCH_MAINSTONE_H
+#define ASM_ARCH_MAINSTONE_H
+
+#define MST_ETH_PHYS            PXA_CS4_PHYS
+
+#define MST_FPGA_PHYS           PXA_CS2_PHYS
+#define MST_FPGA_VIRT           (0xf0000000)
+#define MST_P2V(x)              ((x) - MST_FPGA_PHYS + MST_FPGA_VIRT)
+#define MST_V2P(x)              ((x) - MST_FPGA_VIRT + MST_FPGA_PHYS)
+
+#ifndef __ASSEMBLY__
+# define __MST_REG(x)           (*((volatile unsigned long *)MST_P2V(x)))
+#else
+# define __MST_REG(x)           MST_P2V(x)
+#endif
+
+/* board level registers in the FPGA */
+
+#define MST_LEDDAT1             __MST_REG(0x08000010)
+#define MST_LEDDAT2             __MST_REG(0x08000014)
+#define MST_LEDCTRL             __MST_REG(0x08000040)
+#define MST_GPSWR               __MST_REG(0x08000060)
+#define MST_MSCWR1              __MST_REG(0x08000080)
+#define MST_MSCWR2              __MST_REG(0x08000084)
+#define MST_MSCWR3              __MST_REG(0x08000088)
+#define MST_MSCRD               __MST_REG(0x08000090)
+#define MST_INTMSKENA           __MST_REG(0x080000c0)
+#define MST_INTSETCLR           __MST_REG(0x080000d0)
+#define MST_PCMCIA0             __MST_REG(0x080000e0)
+#define MST_PCMCIA1             __MST_REG(0x080000e4)
+
+#define MST_MSCWR1_CAMERA_ON    (1 << 15)  /* Camera interface power control */
+#define MST_MSCWR1_CAMERA_SEL   (1 << 14)  /* Camera interface mux control */
+#define MST_MSCWR1_LCD_CTL      (1 << 13)  /* General-purpose LCD control */
+#define MST_MSCWR1_MS_ON        (1 << 12)  /* Memory Stick power control */
+#define MST_MSCWR1_MMC_ON       (1 << 11)  /* MultiMediaCard* power control */
+#define MST_MSCWR1_MS_SEL       (1 << 10)  /* SD/MS multiplexer control */
+#define MST_MSCWR1_BB_SEL       (1 << 9)   /* PCMCIA/Baseband multiplexer */
+#define MST_MSCWR1_BT_ON        (1 << 8)   /* Bluetooth UART transceiver */
+#define MST_MSCWR1_BTDTR        (1 << 7)   /* Bluetooth UART DTR */
+
+#define MST_MSCWR1_IRDA_MASK    (3 << 5)   /* IrDA transceiver mode */
+#define MST_MSCWR1_IRDA_FULL    (0 << 5)   /* full distance power */
+#define MST_MSCWR1_IRDA_OFF     (1 << 5)   /* shutdown */
+#define MST_MSCWR1_IRDA_MED     (2 << 5)   /* 2/3 distance power */
+#define MST_MSCWR1_IRDA_LOW     (3 << 5)   /* 1/3 distance power */
+
+#define MST_MSCWR1_IRDA_FIR     (1 << 4)   /* IrDA transceiver SIR/FIR */
+#define MST_MSCWR1_GREENLED     (1 << 3)   /* LED D1 control */
+#define MST_MSCWR1_PDC_CTL      (1 << 2)   /* reserved */
+#define MST_MSCWR1_MTR_ON       (1 << 1)   /* Silent alert motor */
+#define MST_MSCWR1_SYSRESET     (1 << 0)   /* System reset */
+
+#define MST_MSCWR2_USB_OTG_RST  (1 << 6)   /* USB On The Go reset */
+#define MST_MSCWR2_USB_OTG_SEL  (1 << 5)   /* USB On The Go control */
+#define MST_MSCWR2_nUSBC_SC     (1 << 4)   /* USB client soft connect control */
+#define MST_MSCWR2_I2S_SPKROFF  (1 << 3)   /* I2S CODEC amplifier control */
+#define MST_MSCWR2_AC97_SPKROFF (1 << 2)   /* AC97 CODEC amplifier control */
+#define MST_MSCWR2_RADIO_PWR    (1 << 1)   /* Radio module power control */
+#define MST_MSCWR2_RADIO_WAKE   (1 << 0)   /* Radio module wake-up signal */
+
+#define MST_MSCWR3_GPIO_RESET_EN        (1 << 2) /* Enable GPIO Reset */
+#define MST_MSCWR3_GPIO_RESET           (1 << 1) /* Initiate a GPIO Reset */
+#define MST_MSCWR3_COMMS_SW_RESET       (1 << 0) /* Communications Processor Reset Control */
+
+#define MST_MSCRD_nPENIRQ       (1 << 9)   /* ADI7873* nPENIRQ signal */
+#define MST_MSCRD_nMEMSTK_CD    (1 << 8)   /* Memory Stick detection signal */
+#define MST_MSCRD_nMMC_CD       (1 << 7)   /* SD/MMC card detection signal */
+#define MST_MSCRD_nUSIM_CD      (1 << 6)   /* USIM card detection signal */
+#define MST_MSCRD_USB_CBL       (1 << 5)   /* USB client cable status */
+#define MST_MSCRD_TS_BUSY       (1 << 4)   /* ADI7873 busy */
+#define MST_MSCRD_BTDSR         (1 << 3)   /* Bluetooth UART DSR */
+#define MST_MSCRD_BTRI          (1 << 2)   /* Bluetooth UART Ring Indicator */
+#define MST_MSCRD_BTDCD         (1 << 1)   /* Bluetooth UART DCD */
+#define MST_MSCRD_nMMC_WP       (1 << 0)   /* SD/MMC write-protect status */
+
+#define MST_INT_S1_IRQ          (1 << 15)  /* PCMCIA socket 1 IRQ */
+#define MST_INT_S1_STSCHG       (1 << 14)  /* PCMCIA socket 1 status changed */
+#define MST_INT_S1_CD           (1 << 13)  /* PCMCIA socket 1 card detection */
+#define MST_INT_S0_IRQ          (1 << 11)  /* PCMCIA socket 0 IRQ */
+#define MST_INT_S0_STSCHG       (1 << 10)  /* PCMCIA socket 0 status changed */
+#define MST_INT_S0_CD           (1 << 9)   /* PCMCIA socket 0 card detection */
+#define MST_INT_nEXBRD_INT      (1 << 7)   /* Expansion board IRQ */
+#define MST_INT_MSINS           (1 << 6)   /* Memory Stick* detection */
+#define MST_INT_PENIRQ          (1 << 5)   /* ADI7873* touch-screen IRQ */
+#define MST_INT_AC97            (1 << 4)   /* AC'97 CODEC IRQ */
+#define MST_INT_ETHERNET        (1 << 3)   /* Ethernet controller IRQ */
+#define MST_INT_USBC            (1 << 2)   /* USB client cable detection IRQ */
+#define MST_INT_USIM            (1 << 1)   /* USIM card detection IRQ */
+#define MST_INT_MMC             (1 << 0)   /* MMC/SD card detection IRQ */
+
+#define MST_PCMCIA_nIRQ         (1 << 10)  /* IRQ / ready signal */
+#define MST_PCMCIA_nSPKR_BVD2   (1 << 9)   /* VDD sense / digital speaker */
+#define MST_PCMCIA_nSTSCHG_BVD1 (1 << 8)   /* VDD sense / card status changed */
+#define MST_PCMCIA_nVS2         (1 << 7)   /* VSS voltage sense */
+#define MST_PCMCIA_nVS1         (1 << 6)   /* VSS voltage sense */
+#define MST_PCMCIA_nCD          (1 << 5)   /* Card detection signal */
+#define MST_PCMCIA_RESET        (1 << 4)   /* Card reset signal */
+#define MST_PCMCIA_PWR_MASK     (0x000f)   /* MAX1602 power-supply controls */
+
+#define MST_PCMCIA_PWR_VPP_0    0x0        /* voltage VPP = 0V */
+#define MST_PCMCIA_PWR_VPP_120  0x2        /* voltage VPP = 12V*/
+#define MST_PCMCIA_PWR_VPP_VCC  0x1        /* voltage VPP = VCC */
+#define MST_PCMCIA_PWR_VCC_0    0x0        /* voltage VCC = 0V */
+#define MST_PCMCIA_PWR_VCC_33   0x8        /* voltage VCC = 3.3V */
+#define MST_PCMCIA_PWR_VCC_50   0x4        /* voltage VCC = 5.0V */
+
+#endif
diff --git a/arch/arm/mach-pxa/include/mach/memory.h b/arch/arm/mach-pxa/include/mach/memory.h
new file mode 100644
index 000000000000..552eb7fa6579
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/memory.h
@@ -0,0 +1,52 @@
+/*
+ *  arch/arm/mach-pxa/include/mach/memory.h
+ *
+ * Author:      Nicolas Pitre
+ * Copyright:   (C) 2001 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     UL(0xa0000000)
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+#define __virt_to_bus(x)         __virt_to_phys(x)
+#define __bus_to_virt(x)         __phys_to_virt(x)
+
+/*
+ * The nodes are matched with the physical SDRAM banks as follows:
+ *
+ *      node 0:  0xa0000000-0xa3ffffff  -->  0xc0000000-0xc3ffffff
+ *      node 1:  0xa4000000-0xa7ffffff  -->  0xc4000000-0xc7ffffff
+ *      node 2:  0xa8000000-0xabffffff  -->  0xc8000000-0xcbffffff
+ *      node 3:  0xac000000-0xafffffff  -->  0xcc000000-0xcfffffff
+ *
+ * This needs a node mem size of 26 bits.
+ */
+#define NODE_MEM_SIZE_BITS      26
+
+#if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
+void cmx270_pci_adjust_zones(int node, unsigned long *size,
+                             unsigned long *holes);
+
+#define arch_adjust_zones(node, size, holes) \
+        cmx270_pci_adjust_zones(node, size, holes)
+
+#define ISA_DMA_THRESHOLD       (PHYS_OFFSET + SZ_64M - 1)
+#endif
+
+#endif
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
new file mode 100644
index 000000000000..6c8e72238bfd
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
@@ -0,0 +1,161 @@
+#ifndef __ASM_ARCH_MFP_PXA25X_H
+#define __ASM_ARCH_MFP_PXA25X_H
+
+#include <mach/mfp.h>
+#include <mach/mfp-pxa2xx.h>
+
+/* GPIO */
+#define GPIO2_GPIO              MFP_CFG_IN(GPIO2, AF0)
+#define GPIO3_GPIO              MFP_CFG_IN(GPIO3, AF0)
+#define GPIO4_GPIO              MFP_CFG_IN(GPIO4, AF0)
+#define GPIO5_GPIO              MFP_CFG_IN(GPIO5, AF0)
+#define GPIO6_GPIO              MFP_CFG_IN(GPIO6, AF0)
+#define GPIO7_GPIO              MFP_CFG_IN(GPIO7, AF0)
+#define GPIO8_GPIO              MFP_CFG_IN(GPIO8, AF0)
+
+#define GPIO1_RST               MFP_CFG_IN(GPIO1, AF1)
+
+/* Crystal and Clock Signals */
+#define GPIO10_RTCCLK           MFP_CFG_OUT(GPIO10, AF1, DRIVE_LOW)
+#define GPIO70_RTC_CLK          MFP_CFG_OUT(GPIO70, AF1, DRIVE_LOW)
+#define GPIO7_48MHz             MFP_CFG_OUT(GPIO7,  AF1, DRIVE_LOW)
+#define GPIO11_3_6MHz           MFP_CFG_OUT(GPIO11, AF1, DRIVE_LOW)
+#define GPIO71_3_6MHz           MFP_CFG_OUT(GPIO71, AF1, DRIVE_LOW)
+#define GPIO12_32KHz            MFP_CFG_OUT(GPIO12, AF1, DRIVE_LOW)
+#define GPIO72_32kHz            MFP_CFG_OUT(GPIO72, AF1, DRIVE_LOW)
+
+/* SDRAM and Static Memory I/O Signals */
+#define GPIO15_nCS_1            MFP_CFG_OUT(GPIO15, AF2, DRIVE_HIGH)
+#define GPIO78_nCS_2            MFP_CFG_OUT(GPIO78, AF2, DRIVE_HIGH)
+#define GPIO79_nCS_3            MFP_CFG_OUT(GPIO79, AF2, DRIVE_HIGH)
+#define GPIO80_nCS_4            MFP_CFG_OUT(GPIO80, AF2, DRIVE_HIGH)
+#define GPIO33_nCS_5            MFP_CFG_OUT(GPIO33, AF2, DRIVE_HIGH)
+
+/* Miscellaneous I/O and DMA Signals */
+#define GPIO18_RDY              MFP_CFG_IN(GPIO18, AF1)
+#define GPIO20_DREQ_0           MFP_CFG_IN(GPIO20, AF1)
+#define GPIO19_DREQ_1           MFP_CFG_IN(GPIO19, AF1)
+
+/* Alternate Bus Master Mode I/O Signals */
+#define GPIO13_MBGNT            MFP_CFG_OUT(GPIO13, AF2, DRIVE_LOW)
+#define GPIO73_MBGNT            MFP_CFG_OUT(GPIO73, AF1, DRIVE_LOW)
+#define GPIO14_MBREQ            MFP_CFG_IN(GPIO14, AF1)
+#define GPIO66_MBREQ            MFP_CFG_IN(GPIO66, AF1)
+
+/* PC CARD */
+#define GPIO52_nPCE_1           MFP_CFG_OUT(GPIO52, AF2, DRIVE_HIGH)
+#define GPIO53_nPCE_2           MFP_CFG_OUT(GPIO53, AF2, DRIVE_HIGH)
+#define GPIO55_nPREG            MFP_CFG_OUT(GPIO55, AF2, DRIVE_HIGH)
+#define GPIO50_nPIOR            MFP_CFG_OUT(GPIO50, AF2, DRIVE_HIGH)
+#define GPIO51_nPIOW            MFP_CFG_OUT(GPIO51, AF2, DRIVE_HIGH)
+#define GPIO49_nPWE             MFP_CFG_OUT(GPIO49, AF2, DRIVE_HIGH)
+#define GPIO48_nPOE             MFP_CFG_OUT(GPIO48, AF2, DRIVE_HIGH)
+#define GPIO57_nIOIS16          MFP_CFG_IN(GPIO57, AF1)
+#define GPIO56_nPWAIT           MFP_CFG_IN(GPIO56, AF1)
+#define GPIO54_nPSKTSEL         MFP_CFG_OUT(GPIO54, AF2, DRIVE_HIGH)
+
+/* FFUART */
+#define GPIO34_FFUART_RXD       MFP_CFG_IN(GPIO34, AF1)
+#define GPIO35_FFUART_CTS       MFP_CFG_IN(GPIO35, AF1)
+#define GPIO36_FFUART_DCD       MFP_CFG_IN(GPIO36, AF1)
+#define GPIO37_FFUART_DSR       MFP_CFG_IN(GPIO37, AF1)
+#define GPIO38_FFUART_RI        MFP_CFG_IN(GPIO38, AF1)
+#define GPIO39_FFUART_TXD       MFP_CFG_OUT(GPIO39, AF2, DRIVE_HIGH)
+#define GPIO40_FFUART_DTR       MFP_CFG_OUT(GPIO40, AF2, DRIVE_HIGH)
+#define GPIO41_FFUART_RTS       MFP_CFG_OUT(GPIO41, AF2, DRIVE_HIGH)
+
+/* BTUART */
+#define GPIO42_BTUART_RXD       MFP_CFG_IN(GPIO42, AF1)
+#define GPIO43_BTUART_TXD       MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH)
+#define GPIO44_BTUART_CTS       MFP_CFG_IN(GPIO44, AF1)
+#define GPIO45_BTUART_RTS       MFP_CFG_OUT(GPIO45, AF2, DRIVE_HIGH)
+
+/* STUART */
+#define GPIO46_STUART_RXD       MFP_CFG_IN(GPIO46, AF2)
+#define GPIO47_STUART_TXD       MFP_CFG_OUT(GPIO47, AF1, DRIVE_HIGH)
+
+/* HWUART */
+#define GPIO42_HWUART_RXD       MFP_CFG_IN(GPIO42, AF3)
+#define GPIO43_HWUART_TXD       MFP_CFG_OUT(GPIO43, AF3, DRIVE_HIGH)
+#define GPIO44_HWUART_CTS       MFP_CFG_IN(GPIO44, AF3)
+#define GPIO45_HWUART_RTS       MFP_CFG_OUT(GPIO45, AF3, DRIVE_HIGH)
+#define GPIO48_HWUART_TXD       MFP_CFG_OUT(GPIO48, AF1, DRIVE_HIGH)
+#define GPIO49_HWUART_RXD       MFP_CFG_IN(GPIO49, AF1)
+#define GPIO50_HWUART_CTS       MFP_CFG_IN(GPIO50, AF1)
+#define GPIO51_HWUART_RTS       MFP_CFG_OUT(GPIO51, AF1, DRIVE_HIGH)
+
+/* FICP */
+#define GPIO46_FICP_RXD         MFP_CFG_IN(GPIO46, AF1)
+#define GPIO47_FICP_TXD         MFP_CFG_OUT(GPIO47, AF2, DRIVE_HIGH)
+
+/* PWM 0/1 */
+#define GPIO16_PWM0_OUT         MFP_CFG_OUT(GPIO16, AF2, DRIVE_LOW)
+#define GPIO17_PWM1_OUT         MFP_CFG_OUT(GPIO17, AF2, DRIVE_LOW)
+
+/* AC97 */
+#define GPIO28_AC97_BITCLK      MFP_CFG_IN(GPIO28, AF1)
+#define GPIO29_AC97_SDATA_IN_0  MFP_CFG_IN(GPIO29, AF1)
+#define GPIO30_AC97_SDATA_OUT   MFP_CFG_OUT(GPIO30, AF2, DRIVE_LOW)
+#define GPIO31_AC97_SYNC        MFP_CFG_OUT(GPIO31, AF2, DRIVE_LOW)
+#define GPIO32_AC97_SDATA_IN_1  MFP_CFG_IN(GPIO32, AF1)
+
+/* I2S */
+#define GPIO28_I2S_BITCLK_IN    MFP_CFG_IN(GPIO28, AF2)
+#define GPIO28_I2S_BITCLK_OUT   MFP_CFG_OUT(GPIO28, AF1, DRIVE_LOW)
+#define GPIO29_I2S_SDATA_IN     MFP_CFG_IN(GPIO29, AF2)
+#define GPIO30_I2S_SDATA_OUT    MFP_CFG_OUT(GPIO30, AF1, DRIVE_LOW)
+#define GPIO31_I2S_SYNC         MFP_CFG_OUT(GPIO31, AF1, DRIVE_LOW)
+#define GPIO32_I2S_SYSCLK       MFP_CFG_OUT(GPIO32, AF1, DRIVE_LOW)
+
+/* SSP 1 */
+#define GPIO23_SSP1_SCLK        MFP_CFG_OUT(GPIO23, AF2, DRIVE_LOW)
+#define GPIO24_SSP1_SFRM        MFP_CFG_OUT(GPIO24, AF2, DRIVE_LOW)
+#define GPIO25_SSP1_TXD         MFP_CFG_OUT(GPIO25, AF2, DRIVE_LOW)
+#define GPIO26_SSP1_RXD         MFP_CFG_IN(GPIO26, AF1)
+#define GPIO27_SSP1_EXTCLK      MFP_CFG_IN(GPIO27, AF1)
+
+/* SSP 2 - NSSP */
+#define GPIO81_SSP2_CLK_OUT     MFP_CFG_OUT(GPIO81, AF1, DRIVE_LOW)
+#define GPIO81_SSP2_CLK_IN      MFP_CFG_IN(GPIO81, AF1)
+#define GPIO82_SSP2_FRM_OUT     MFP_CFG_OUT(GPIO82, AF1, DRIVE_LOW)
+#define GPIO82_SSP2_FRM_IN      MFP_CFG_IN(GPIO82, AF1)
+#define GPIO83_SSP2_TXD         MFP_CFG_OUT(GPIO83, AF1, DRIVE_LOW)
+#define GPIO83_SSP2_RXD         MFP_CFG_IN(GPIO83, AF2)
+#define GPIO84_SSP2_TXD         MFP_CFG_OUT(GPIO84, AF1, DRIVE_LOW)
+#define GPIO84_SSP2_RXD         MFP_CFG_IN(GPIO84, AF2)
+
+/* MMC */
+#define GPIO6_MMC_CLK           MFP_CFG_OUT(GPIO6, AF1, DRIVE_LOW)
+#define GPIO8_MMC_CS0           MFP_CFG_OUT(GPIO8, AF1, DRIVE_LOW)
+#define GPIO9_MMC_CS1           MFP_CFG_OUT(GPIO9, AF1, DRIVE_LOW)
+#define GPIO34_MMC_CS0          MFP_CFG_OUT(GPIO34, AF2, DRIVE_LOW)
+#define GPIO39_MMC_CS1          MFP_CFG_OUT(GPIO39, AF1, DRIVE_LOW)
+#define GPIO53_MMC_CLK          MFP_CFG_OUT(GPIO53, AF1, DRIVE_LOW)
+#define GPIO54_MMC_CLK          MFP_CFG_OUT(GPIO54, AF1, DRIVE_LOW)
+#define GPIO69_MMC_CLK          MFP_CFG_OUT(GPIO69, AF1, DRIVE_LOW)
+#define GPIO67_MMC_CS0          MFP_CFG_OUT(GPIO67, AF1, DRIVE_LOW)
+#define GPIO68_MMC_CS1          MFP_CFG_OUT(GPIO68, AF1, DRIVE_LOW)
+
+/* LCD */
+#define GPIO58_LCD_LDD_0        MFP_CFG_OUT(GPIO58, AF2, DRIVE_LOW)
+#define GPIO59_LCD_LDD_1        MFP_CFG_OUT(GPIO59, AF2, DRIVE_LOW)
+#define GPIO60_LCD_LDD_2        MFP_CFG_OUT(GPIO60, AF2, DRIVE_LOW)
+#define GPIO61_LCD_LDD_3        MFP_CFG_OUT(GPIO61, AF2, DRIVE_LOW)
+#define GPIO62_LCD_LDD_4        MFP_CFG_OUT(GPIO62, AF2, DRIVE_LOW)
+#define GPIO63_LCD_LDD_5        MFP_CFG_OUT(GPIO63, AF2, DRIVE_LOW)
+#define GPIO64_LCD_LDD_6        MFP_CFG_OUT(GPIO64, AF2, DRIVE_LOW)
+#define GPIO65_LCD_LDD_7        MFP_CFG_OUT(GPIO65, AF2, DRIVE_LOW)
+#define GPIO66_LCD_LDD_8        MFP_CFG_OUT(GPIO66, AF2, DRIVE_LOW)
+#define GPIO67_LCD_LDD_9        MFP_CFG_OUT(GPIO67, AF2, DRIVE_LOW)
+#define GPIO68_LCD_LDD_10       MFP_CFG_OUT(GPIO68, AF2, DRIVE_LOW)
+#define GPIO69_LCD_LDD_11       MFP_CFG_OUT(GPIO69, AF2, DRIVE_LOW)
+#define GPIO70_LCD_LDD_12       MFP_CFG_OUT(GPIO70, AF2, DRIVE_LOW)
+#define GPIO71_LCD_LDD_13       MFP_CFG_OUT(GPIO71, AF2, DRIVE_LOW)
+#define GPIO72_LCD_LDD_14       MFP_CFG_OUT(GPIO72, AF2, DRIVE_LOW)
+#define GPIO73_LCD_LDD_15       MFP_CFG_OUT(GPIO73, AF2, DRIVE_LOW)
+#define GPIO74_LCD_FCLK         MFP_CFG_OUT(GPIO74, AF2, DRIVE_LOW)
+#define GPIO75_LCD_LCLK         MFP_CFG_OUT(GPIO75, AF2, DRIVE_LOW)
+#define GPIO76_LCD_PCLK         MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW)
+#define GPIO77_LCD_ACBIAS       MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW)
+
+#endif /* __ASM_ARCH_MFP_PXA25X_H */
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
new file mode 100644
index 000000000000..122bdbd53182
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
@@ -0,0 +1,433 @@
+#ifndef __ASM_ARCH_MFP_PXA27X_H
+#define __ASM_ARCH_MFP_PXA27X_H
+
+/*
+ * NOTE:  for those special-function bidirectional GPIOs, as described
+ * in the "PXA27x Developer's Manual" Section 24.4.2.1, only its input
+ * alternative is preserved, the direction is actually selected by the
+ * specific controller, and this should work in most cases.
+ */
+
+#include <mach/mfp.h>
+#include <mach/mfp-pxa2xx.h>
+
+/* GPIO */
+#define GPIO85_GPIO             MFP_CFG_IN(GPIO85, AF0)
+#define GPIO86_GPIO             MFP_CFG_IN(GPIO86, AF0)
+#define GPIO87_GPIO             MFP_CFG_IN(GPIO87, AF0)
+#define GPIO88_GPIO             MFP_CFG_IN(GPIO88, AF0)
+#define GPIO89_GPIO             MFP_CFG_IN(GPIO89, AF0)
+#define GPIO90_GPIO             MFP_CFG_IN(GPIO90, AF0)
+#define GPIO91_GPIO             MFP_CFG_IN(GPIO91, AF0)
+#define GPIO92_GPIO             MFP_CFG_IN(GPIO92, AF0)
+#define GPIO93_GPIO             MFP_CFG_IN(GPIO93, AF0)
+#define GPIO94_GPIO             MFP_CFG_IN(GPIO94, AF0)
+#define GPIO95_GPIO             MFP_CFG_IN(GPIO95, AF0)
+#define GPIO96_GPIO             MFP_CFG_IN(GPIO96, AF0)
+#define GPIO97_GPIO             MFP_CFG_IN(GPIO97, AF0)
+#define GPIO98_GPIO             MFP_CFG_IN(GPIO98, AF0)
+#define GPIO99_GPIO             MFP_CFG_IN(GPIO99, AF0)
+#define GPIO100_GPIO            MFP_CFG_IN(GPIO100, AF0)
+#define GPIO101_GPIO            MFP_CFG_IN(GPIO101, AF0)
+#define GPIO102_GPIO            MFP_CFG_IN(GPIO102, AF0)
+#define GPIO103_GPIO            MFP_CFG_IN(GPIO103, AF0)
+#define GPIO104_GPIO            MFP_CFG_IN(GPIO104, AF0)
+#define GPIO105_GPIO            MFP_CFG_IN(GPIO105, AF0)
+#define GPIO106_GPIO            MFP_CFG_IN(GPIO106, AF0)
+#define GPIO107_GPIO            MFP_CFG_IN(GPIO107, AF0)
+#define GPIO108_GPIO            MFP_CFG_IN(GPIO108, AF0)
+#define GPIO109_GPIO            MFP_CFG_IN(GPIO109, AF0)
+#define GPIO110_GPIO            MFP_CFG_IN(GPIO110, AF0)
+#define GPIO111_GPIO            MFP_CFG_IN(GPIO111, AF0)
+#define GPIO112_GPIO            MFP_CFG_IN(GPIO112, AF0)
+#define GPIO113_GPIO            MFP_CFG_IN(GPIO113, AF0)
+#define GPIO114_GPIO            MFP_CFG_IN(GPIO114, AF0)
+#define GPIO115_GPIO            MFP_CFG_IN(GPIO115, AF0)
+#define GPIO116_GPIO            MFP_CFG_IN(GPIO116, AF0)
+#define GPIO117_GPIO            MFP_CFG_IN(GPIO117, AF0)
+#define GPIO118_GPIO            MFP_CFG_IN(GPIO118, AF0)
+#define GPIO119_GPIO            MFP_CFG_IN(GPIO119, AF0)
+#define GPIO120_GPIO            MFP_CFG_IN(GPIO120, AF0)
+
+/* Crystal and Clock Signals */
+#define GPIO9_HZ_CLK            MFP_CFG_OUT(GPIO9,  AF1, DRIVE_LOW)
+#define GPIO10_HZ_CLK           MFP_CFG_OUT(GPIO10, AF1, DRIVE_LOW)
+#define GPIO11_48_MHz           MFP_CFG_OUT(GPIO11, AF3, DRIVE_LOW)
+#define GPIO12_48_MHz           MFP_CFG_OUT(GPIO12, AF3, DRIVE_LOW)
+#define GPIO13_CLK_EXT          MFP_CFG_IN(GPIO13, AF1)
+
+/* OS Timer Signals */
+#define GPIO11_EXT_SYNC_0       MFP_CFG_IN(GPIO11, AF1)
+#define GPIO12_EXT_SYNC_1       MFP_CFG_IN(GPIO12, AF1)
+#define GPIO9_CHOUT_0           MFP_CFG_OUT(GPIO9,  AF3, DRIVE_LOW)
+#define GPIO10_CHOUT_1          MFP_CFG_OUT(GPIO10, AF3, DRIVE_LOW)
+#define GPIO11_CHOUT_0          MFP_CFG_OUT(GPIO11, AF1, DRIVE_LOW)
+#define GPIO12_CHOUT_1          MFP_CFG_OUT(GPIO12, AF1, DRIVE_LOW)
+
+/* SDRAM and Static Memory I/O Signals */
+#define GPIO20_nSDCS_2          MFP_CFG_OUT(GPIO20, AF1, DRIVE_HIGH)
+#define GPIO21_nSDCS_3          MFP_CFG_OUT(GPIO21, AF1, DRIVE_HIGH)
+#define GPIO15_nCS_1            MFP_CFG_OUT(GPIO15, AF2, DRIVE_HIGH)
+#define GPIO78_nCS_2            MFP_CFG_OUT(GPIO78, AF2, DRIVE_HIGH)
+#define GPIO79_nCS_3            MFP_CFG_OUT(GPIO79, AF2, DRIVE_HIGH)
+#define GPIO80_nCS_4            MFP_CFG_OUT(GPIO80, AF2, DRIVE_HIGH)
+#define GPIO33_nCS_5            MFP_CFG_OUT(GPIO33, AF2, DRIVE_HIGH)
+
+/* Miscellaneous I/O and DMA Signals */
+#define GPIO21_DVAL_0           MFP_CFG_OUT(GPIO21, AF2, DRIVE_HIGH)
+#define GPIO116_DVAL_0          MFP_CFG_OUT(GPIO116, AF1, DRIVE_HIGH)
+#define GPIO33_DVAL_1           MFP_CFG_OUT(GPIO33, AF1, DRIVE_HIGH)
+#define GPIO96_DVAL_1           MFP_CFG_OUT(GPIO96, AF2, DRIVE_HIGH)
+#define GPIO18_RDY              MFP_CFG_IN(GPIO18, AF1)
+#define GPIO20_DREQ_0           MFP_CFG_IN(GPIO20, AF1)
+#define GPIO115_DREQ_0          MFP_CFG_IN(GPIO115, AF1)
+#define GPIO80_DREQ_1           MFP_CFG_IN(GPIO80, AF1)
+#define GPIO97_DREQ_1           MFP_CFG_IN(GPIO97, AF2)
+#define GPIO85_DREQ_2           MFP_CFG_IN(GPIO85, AF2)
+#define GPIO100_DREQ_2          MFP_CFG_IN(GPIO100, AF2)
+
+/* Alternate Bus Master Mode I/O Signals */
+#define GPIO20_MBREQ            MFP_CFG_IN(GPIO20, AF2)
+#define GPIO80_MBREQ            MFP_CFG_IN(GPIO80, AF2)
+#define GPIO96_MBREQ            MFP_CFG_IN(GPIO96, AF2)
+#define GPIO115_MBREQ           MFP_CFG_IN(GPIO115, AF3)
+#define GPIO21_MBGNT            MFP_CFG_OUT(GPIO21, AF3, DRIVE_LOW)
+#define GPIO33_MBGNT            MFP_CFG_OUT(GPIO33, AF3, DRIVE_LOW)
+#define GPIO97_MBGNT            MFP_CFG_OUT(GPIO97, AF2, DRIVE_LOW)
+#define GPIO116_MBGNT           MFP_CFG_OUT(GPIO116, AF3, DRIVE_LOW)
+
+/* PC CARD */
+#define GPIO15_nPCE_1           MFP_CFG_OUT(GPIO15, AF1, DRIVE_HIGH)
+#define GPIO85_nPCE_1           MFP_CFG_OUT(GPIO85, AF1, DRIVE_HIGH)
+#define GPIO86_nPCE_1           MFP_CFG_OUT(GPIO86, AF1, DRIVE_HIGH)
+#define GPIO102_nPCE_1          MFP_CFG_OUT(GPIO102, AF1, DRIVE_HIGH)
+#define GPIO54_nPCE_2           MFP_CFG_OUT(GPIO54, AF2, DRIVE_HIGH)
+#define GPIO78_nPCE_2           MFP_CFG_OUT(GPIO78, AF1, DRIVE_HIGH)
+#define GPIO87_nPCE_2           MFP_CFG_IN(GPIO87, AF1)
+#define GPIO55_nPREG            MFP_CFG_OUT(GPIO55, AF2, DRIVE_HIGH)
+#define GPIO50_nPIOR            MFP_CFG_OUT(GPIO50, AF2, DRIVE_HIGH)
+#define GPIO51_nPIOW            MFP_CFG_OUT(GPIO51, AF2, DRIVE_HIGH)
+#define GPIO49_nPWE             MFP_CFG_OUT(GPIO49, AF2, DRIVE_HIGH)
+#define GPIO48_nPOE             MFP_CFG_OUT(GPIO48, AF2, DRIVE_HIGH)
+#define GPIO57_nIOIS16          MFP_CFG_IN(GPIO57, AF1)
+#define GPIO56_nPWAIT           MFP_CFG_IN(GPIO56, AF1)
+#define GPIO79_PSKTSEL          MFP_CFG_OUT(GPIO79, AF1, DRIVE_HIGH)
+#define GPIO104_PSKTSEL         MFP_CFG_OUT(GPIO104, AF1, DRIVE_HIGH)
+
+/* I2C */
+#define GPIO117_I2C_SCL         MFP_CFG_IN(GPIO117, AF1)
+#define GPIO118_I2C_SDA         MFP_CFG_IN(GPIO118, AF1)
+
+/* FFUART */
+#define GPIO9_FFUART_CTS        MFP_CFG_IN(GPIO9, AF3)
+#define GPIO26_FFUART_CTS       MFP_CFG_IN(GPIO26, AF3)
+#define GPIO35_FFUART_CTS       MFP_CFG_IN(GPIO35, AF1)
+#define GPIO100_FFUART_CTS      MFP_CFG_IN(GPIO100, AF3)
+#define GPIO10_FFUART_DCD       MFP_CFG_IN(GPIO10, AF1)
+#define GPIO36_FFUART_DCD       MFP_CFG_IN(GPIO36, AF1)
+#define GPIO33_FFUART_DSR       MFP_CFG_IN(GPIO33, AF2)
+#define GPIO37_FFUART_DSR       MFP_CFG_IN(GPIO37, AF1)
+#define GPIO38_FFUART_RI        MFP_CFG_IN(GPIO38, AF1)
+#define GPIO89_FFUART_RI        MFP_CFG_IN(GPIO89, AF3)
+#define GPIO19_FFUART_RXD       MFP_CFG_IN(GPIO19, AF3)
+#define GPIO33_FFUART_RXD       MFP_CFG_IN(GPIO33, AF1)
+#define GPIO34_FFUART_RXD       MFP_CFG_IN(GPIO34, AF1)
+#define GPIO41_FFUART_RXD       MFP_CFG_IN(GPIO41, AF1)
+#define GPIO53_FFUART_RXD       MFP_CFG_IN(GPIO53, AF1)
+#define GPIO85_FFUART_RXD       MFP_CFG_IN(GPIO85, AF1)
+#define GPIO96_FFUART_RXD       MFP_CFG_IN(GPIO96, AF3)
+#define GPIO102_FFUART_RXD      MFP_CFG_IN(GPIO102, AF3)
+#define GPIO16_FFUART_TXD       MFP_CFG_OUT(GPIO16, AF3, DRIVE_HIGH)
+#define GPIO37_FFUART_TXD       MFP_CFG_OUT(GPIO37, AF3, DRIVE_HIGH)
+#define GPIO39_FFUART_TXD       MFP_CFG_OUT(GPIO39, AF2, DRIVE_HIGH)
+#define GPIO83_FFUART_TXD       MFP_CFG_OUT(GPIO83, AF2, DRIVE_HIGH)
+#define GPIO99_FFUART_TXD       MFP_CFG_OUT(GPIO99, AF3, DRIVE_HIGH)
+#define GPIO27_FFUART_RTS       MFP_CFG_OUT(GPIO27, AF3, DRIVE_HIGH)
+#define GPIO41_FFUART_RTS       MFP_CFG_OUT(GPIO41, AF2, DRIVE_HIGH)
+#define GPIO83_FFUART_RTS       MFP_CFG_OUT(GPIO83, AF3, DRIVE_HIGH)
+#define GPIO98_FFUART_RTS       MFP_CFG_OUT(GPIO98, AF3, DRIVE_HIGH)
+#define GPIO40_FFUART_DTR       MFP_CFG_OUT(GPIO40, AF2, DRIVE_HIGH)
+#define GPIO82_FFUART_DTR       MFP_CFG_OUT(GPIO82, AF3, DRIVE_HIGH)
+
+/* BTUART */
+#define GPIO44_BTUART_CTS       MFP_CFG_IN(GPIO44, AF1)
+#define GPIO42_BTUART_RXD       MFP_CFG_IN(GPIO42, AF1)
+#define GPIO45_BTUART_RTS       MFP_CFG_OUT(GPIO45, AF2, DRIVE_HIGH)
+#define GPIO43_BTUART_TXD       MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH)
+
+/* STUART */
+#define GPIO46_STUART_RXD       MFP_CFG_IN(GPIO46, AF2)
+#define GPIO47_STUART_TXD       MFP_CFG_OUT(GPIO47, AF1, DRIVE_HIGH)
+
+/* FICP */
+#define GPIO42_FICP_RXD         MFP_CFG_IN(GPIO42, AF2)
+#define GPIO46_FICP_RXD         MFP_CFG_IN(GPIO46, AF1)
+#define GPIO43_FICP_TXD         MFP_CFG_OUT(GPIO43, AF1, DRIVE_HIGH)
+#define GPIO47_FICP_TXD         MFP_CFG_OUT(GPIO47, AF2, DRIVE_HIGH)
+
+/* PWM 0/1/2/3 */
+#define GPIO11_PWM2_OUT         MFP_CFG_OUT(GPIO11, AF2, DRIVE_LOW)
+#define GPIO12_PWM3_OUT         MFP_CFG_OUT(GPIO12, AF2, DRIVE_LOW)
+#define GPIO16_PWM0_OUT         MFP_CFG_OUT(GPIO16, AF2, DRIVE_LOW)
+#define GPIO17_PWM1_OUT         MFP_CFG_OUT(GPIO17, AF2, DRIVE_LOW)
+#define GPIO38_PWM1_OUT         MFP_CFG_OUT(GPIO38, AF3, DRIVE_LOW)
+#define GPIO46_PWM2_OUT         MFP_CFG_OUT(GPIO46, AF2, DRIVE_LOW)
+#define GPIO47_PWM3_OUT         MFP_CFG_OUT(GPIO47, AF3, DRIVE_LOW)
+#define GPIO79_PWM2_OUT         MFP_CFG_OUT(GPIO79, AF3, DRIVE_LOW)
+#define GPIO80_PWM3_OUT         MFP_CFG_OUT(GPIO80, AF3, DRIVE_LOW)
+#define GPIO115_PWM1_OUT        MFP_CFG_OUT(GPIO115, AF3, DRIVE_LOW)
+
+/* AC97 */
+#define GPIO31_AC97_SYNC        MFP_CFG_OUT(GPIO31, AF2, DRIVE_LOW)
+#define GPIO94_AC97_SYNC        MFP_CFG_OUT(GPIO94, AF1, DRIVE_LOW)
+#define GPIO30_AC97_SDATA_OUT   MFP_CFG_OUT(GPIO30, AF2, DRIVE_LOW)
+#define GPIO93_AC97_SDATA_OUT   MFP_CFG_OUT(GPIO93, AF1, DRIVE_LOW)
+#define GPIO45_AC97_SYSCLK      MFP_CFG_OUT(GPIO45, AF1, DRIVE_LOW)
+#define GPIO89_AC97_SYSCLK      MFP_CFG_OUT(GPIO89, AF1, DRIVE_LOW)
+#define GPIO98_AC97_SYSCLK      MFP_CFG_OUT(GPIO98, AF1, DRIVE_LOW)
+#define GPIO95_AC97_nRESET      MFP_CFG_OUT(GPIO95, AF1, DRIVE_LOW)
+#define GPIO113_AC97_nRESET     MFP_CFG_OUT(GPIO113, AF2, DRIVE_LOW)
+#define GPIO28_AC97_BITCLK      MFP_CFG_IN(GPIO28, AF1)
+#define GPIO29_AC97_SDATA_IN_0  MFP_CFG_IN(GPIO29, AF1)
+#define GPIO116_AC97_SDATA_IN_0 MFP_CFG_IN(GPIO116, AF2)
+#define GPIO99_AC97_SDATA_IN_1  MFP_CFG_IN(GPIO99, AF2)
+
+/* I2S */
+#define GPIO28_I2S_BITCLK_IN    MFP_CFG_IN(GPIO28, AF2)
+#define GPIO28_I2S_BITCLK_OUT   MFP_CFG_OUT(GPIO28, AF1, DRIVE_LOW)
+#define GPIO29_I2S_SDATA_IN     MFP_CFG_IN(GPIO29, AF2)
+#define GPIO30_I2S_SDATA_OUT    MFP_CFG_OUT(GPIO30, AF1, DRIVE_LOW)
+#define GPIO31_I2S_SYNC         MFP_CFG_OUT(GPIO31, AF1, DRIVE_LOW)
+#define GPIO113_I2S_SYSCLK      MFP_CFG_OUT(GPIO113, AF1, DRIVE_LOW)
+
+/* SSP 1 */
+#define GPIO23_SSP1_SCLK        MFP_CFG_OUT(GPIO23, AF2, DRIVE_LOW)
+#define GPIO29_SSP1_SCLK        MFP_CFG_IN(GPIO29, AF3)
+#define GPIO27_SSP1_SYSCLK      MFP_CFG_OUT(GPIO27, AF1, DRIVE_LOW)
+#define GPIO53_SSP1_SYSCLK      MFP_CFG_OUT(GPIO53, AF3, DRIVE_LOW)
+#define GPIO24_SSP1_SFRM        MFP_CFG_IN(GPIO24, AF2)
+#define GPIO28_SSP1_SFRM        MFP_CFG_IN(GPIO28, AF3)
+#define GPIO25_SSP1_TXD         MFP_CFG_OUT(GPIO25, AF2, DRIVE_LOW)
+#define GPIO57_SSP1_TXD         MFP_CFG_OUT(GPIO57, AF3, DRIVE_LOW)
+#define GPIO26_SSP1_RXD         MFP_CFG_IN(GPIO26, AF1)
+#define GPIO27_SSP1_SCLKEN      MFP_CFG_IN(GPIO27, AF2)
+
+/* SSP 2 */
+#define GPIO19_SSP2_SCLK        MFP_CFG_IN(GPIO19, AF1)
+#define GPIO22_SSP2_SCLK        MFP_CFG_IN(GPIO22, AF3)
+#define GPIO29_SSP2_SCLK        MFP_CFG_OUT(GPIO29, AF3, DRIVE_LOW)
+#define GPIO36_SSP2_SCLK        MFP_CFG_IN(GPIO36, AF2)
+#define GPIO50_SSP2_SCLK        MFP_CFG_IN(GPIO50, AF3)
+#define GPIO22_SSP2_SYSCLK      MFP_CFG_OUT(GPIO22, AF2, DRIVE_LOW)
+#define GPIO14_SSP2_SFRM        MFP_CFG_IN(GPIO14, AF2)
+#define GPIO37_SSP2_SFRM        MFP_CFG_IN(GPIO37, AF2)
+#define GPIO87_SSP2_SFRM        MFP_CFG_OUT(GPIO87, AF3, DRIVE_LOW)
+#define GPIO88_SSP2_SFRM        MFP_CFG_IN(GPIO88, AF3)
+#define GPIO13_SSP2_TXD         MFP_CFG_OUT(GPIO13, AF1, DRIVE_LOW)
+#define GPIO38_SSP2_TXD         MFP_CFG_OUT(GPIO38, AF2, DRIVE_LOW)
+#define GPIO87_SSP2_TXD         MFP_CFG_OUT(GPIO87, AF1, DRIVE_LOW)
+#define GPIO89_SSP2_TXD         MFP_CFG_OUT(GPIO89, AF3, DRIVE_LOW)
+#define GPIO11_SSP2_RXD         MFP_CFG_IN(GPIO11, AF2)
+#define GPIO29_SSP2_RXD         MFP_CFG_OUT(GPIO29, AF1, DRIVE_LOW)
+#define GPIO40_SSP2_RXD         MFP_CFG_IN(GPIO40, AF1)
+#define GPIO86_SSP2_RXD         MFP_CFG_IN(GPIO86, AF1)
+#define GPIO88_SSP2_RXD         MFP_CFG_IN(GPIO88, AF2)
+#define GPIO22_SSP2_EXTCLK      MFP_CFG_IN(GPIO22, AF1)
+#define GPIO27_SSP2_EXTCLK      MFP_CFG_IN(GPIO27, AF1)
+#define GPIO22_SSP2_SCLKEN      MFP_CFG_IN(GPIO22, AF2)
+#define GPIO23_SSP2_SCLKEN      MFP_CFG_IN(GPIO23, AF2)
+
+/* SSP 3 */
+#define GPIO34_SSP3_SCLK        MFP_CFG_IN(GPIO34, AF3)
+#define GPIO40_SSP3_SCLK        MFP_CFG_OUT(GPIO40, AF3, DRIVE_LOW)
+#define GPIO52_SSP3_SCLK        MFP_CFG_IN(GPIO52, AF2)
+#define GPIO84_SSP3_SCLK        MFP_CFG_IN(GPIO84, AF1)
+#define GPIO45_SSP3_SYSCLK      MFP_CFG_OUT(GPIO45, AF3, DRIVE_LOW)
+#define GPIO35_SSP3_SFRM        MFP_CFG_IN(GPIO35, AF3)
+#define GPIO39_SSP3_SFRM        MFP_CFG_IN(GPIO39, AF3)
+#define GPIO83_SSP3_SFRM        MFP_CFG_IN(GPIO83, AF1)
+#define GPIO35_SSP3_TXD         MFP_CFG_OUT(GPIO35, AF3, DRIVE_LOW)
+#define GPIO38_SSP3_TXD         MFP_CFG_OUT(GPIO38, AF1, DRIVE_LOW)
+#define GPIO81_SSP3_TXD         MFP_CFG_OUT(GPIO81, AF1, DRIVE_LOW)
+#define GPIO41_SSP3_RXD         MFP_CFG_IN(GPIO41, AF3)
+#define GPIO82_SSP3_RXD         MFP_CFG_IN(GPIO82, AF1)
+#define GPIO89_SSP3_RXD         MFP_CFG_IN(GPIO89, AF1)
+
+/* MMC */
+#define GPIO32_MMC_CLK          MFP_CFG_OUT(GPIO32, AF2, DRIVE_LOW)
+#define GPIO92_MMC_DAT_0        MFP_CFG_IN(GPIO92, AF1)
+#define GPIO109_MMC_DAT_1       MFP_CFG_IN(GPIO109, AF1)
+#define GPIO110_MMC_DAT_2       MFP_CFG_IN(GPIO110, AF1)
+#define GPIO111_MMC_DAT_3       MFP_CFG_IN(GPIO111, AF1)
+#define GPIO112_MMC_CMD         MFP_CFG_IN(GPIO112, AF1)
+
+/* LCD */
+#define GPIO58_LCD_LDD_0        MFP_CFG_OUT(GPIO58, AF2, DRIVE_LOW)
+#define GPIO59_LCD_LDD_1        MFP_CFG_OUT(GPIO59, AF2, DRIVE_LOW)
+#define GPIO60_LCD_LDD_2        MFP_CFG_OUT(GPIO60, AF2, DRIVE_LOW)
+#define GPIO61_LCD_LDD_3        MFP_CFG_OUT(GPIO61, AF2, DRIVE_LOW)
+#define GPIO62_LCD_LDD_4        MFP_CFG_OUT(GPIO62, AF2, DRIVE_LOW)
+#define GPIO63_LCD_LDD_5        MFP_CFG_OUT(GPIO63, AF2, DRIVE_LOW)
+#define GPIO64_LCD_LDD_6        MFP_CFG_OUT(GPIO64, AF2, DRIVE_LOW)
+#define GPIO65_LCD_LDD_7        MFP_CFG_OUT(GPIO65, AF2, DRIVE_LOW)
+#define GPIO66_LCD_LDD_8        MFP_CFG_OUT(GPIO66, AF2, DRIVE_LOW)
+#define GPIO67_LCD_LDD_9        MFP_CFG_OUT(GPIO67, AF2, DRIVE_LOW)
+#define GPIO68_LCD_LDD_10       MFP_CFG_OUT(GPIO68, AF2, DRIVE_LOW)
+#define GPIO69_LCD_LDD_11       MFP_CFG_OUT(GPIO69, AF2, DRIVE_LOW)
+#define GPIO70_LCD_LDD_12       MFP_CFG_OUT(GPIO70, AF2, DRIVE_LOW)
+#define GPIO71_LCD_LDD_13       MFP_CFG_OUT(GPIO71, AF2, DRIVE_LOW)
+#define GPIO72_LCD_LDD_14       MFP_CFG_OUT(GPIO72, AF2, DRIVE_LOW)
+#define GPIO73_LCD_LDD_15       MFP_CFG_OUT(GPIO73, AF2, DRIVE_LOW)
+#define GPIO86_LCD_LDD_16       MFP_CFG_OUT(GPIO86, AF2, DRIVE_LOW)
+#define GPIO87_LCD_LDD_17       MFP_CFG_OUT(GPIO87, AF2, DRIVE_LOW)
+#define GPIO74_LCD_FCLK         MFP_CFG_OUT(GPIO74, AF2, DRIVE_LOW)
+#define GPIO75_LCD_LCLK         MFP_CFG_OUT(GPIO75, AF2, DRIVE_LOW)
+#define GPIO76_LCD_PCLK         MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW)
+#define GPIO77_LCD_BIAS         MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW)
+#define GPIO14_LCD_VSYNC        MFP_CFG_IN(GPIO14, AF1)
+#define GPIO19_LCD_CS           MFP_CFG_OUT(GPIO19, AF2, DRIVE_LOW)
+
+/* Keypad */
+#define GPIO93_KP_DKIN_0        MFP_CFG_IN(GPIO93, AF1)
+#define GPIO94_KP_DKIN_1        MFP_CFG_IN(GPIO94, AF1)
+#define GPIO95_KP_DKIN_2        MFP_CFG_IN(GPIO95, AF1)
+#define GPIO96_KP_DKIN_3        MFP_CFG_IN(GPIO96, AF1)
+#define GPIO97_KP_DKIN_4        MFP_CFG_IN(GPIO97, AF1)
+#define GPIO98_KP_DKIN_5        MFP_CFG_IN(GPIO98, AF1)
+#define GPIO99_KP_DKIN_6        MFP_CFG_IN(GPIO99, AF1)
+#define GPIO13_KP_KDIN_7        MFP_CFG_IN(GPIO13, AF2)
+#define GPIO100_KP_MKIN_0       MFP_CFG_IN(GPIO100, AF1)
+#define GPIO101_KP_MKIN_1       MFP_CFG_IN(GPIO101, AF1)
+#define GPIO102_KP_MKIN_2       MFP_CFG_IN(GPIO102, AF1)
+#define GPIO34_KP_MKIN_3        MFP_CFG_IN(GPIO34, AF2)
+#define GPIO37_KP_MKIN_3        MFP_CFG_IN(GPIO37, AF3)
+#define GPIO97_KP_MKIN_3        MFP_CFG_IN(GPIO97, AF3)
+#define GPIO98_KP_MKIN_4        MFP_CFG_IN(GPIO98, AF3)
+#define GPIO38_KP_MKIN_4        MFP_CFG_IN(GPIO38, AF2)
+#define GPIO39_KP_MKIN_4        MFP_CFG_IN(GPIO39, AF1)
+#define GPIO16_KP_MKIN_5        MFP_CFG_IN(GPIO16, AF1)
+#define GPIO90_KP_MKIN_5        MFP_CFG_IN(GPIO90, AF1)
+#define GPIO99_KP_MKIN_5        MFP_CFG_IN(GPIO99, AF3)
+#define GPIO17_KP_MKIN_6        MFP_CFG_IN(GPIO17, AF1)
+#define GPIO91_KP_MKIN_6        MFP_CFG_IN(GPIO91, AF1)
+#define GPIO95_KP_MKIN_6        MFP_CFG_IN(GPIO95, AF3)
+#define GPIO13_KP_MKIN_7        MFP_CFG_IN(GPIO13, AF3)
+#define GPIO36_KP_MKIN_7        MFP_CFG_IN(GPIO36, AF3)
+#define GPIO103_KP_MKOUT_0      MFP_CFG_OUT(GPIO103, AF2, DRIVE_HIGH)
+#define GPIO104_KP_MKOUT_1      MFP_CFG_OUT(GPIO104, AF2, DRIVE_HIGH)
+#define GPIO105_KP_MKOUT_2      MFP_CFG_OUT(GPIO105, AF2, DRIVE_HIGH)
+#define GPIO106_KP_MKOUT_3      MFP_CFG_OUT(GPIO106, AF2, DRIVE_HIGH)
+#define GPIO107_KP_MKOUT_4      MFP_CFG_OUT(GPIO107, AF2, DRIVE_HIGH)
+#define GPIO108_KP_MKOUT_5      MFP_CFG_OUT(GPIO108, AF2, DRIVE_HIGH)
+#define GPIO35_KP_MKOUT_6       MFP_CFG_OUT(GPIO35, AF2, DRIVE_HIGH)
+#define GPIO22_KP_MKOUT_7       MFP_CFG_OUT(GPIO22, AF1, DRIVE_HIGH)
+#define GPIO40_KP_MKOUT_6       MFP_CFG_OUT(GPIO40, AF1, DRIVE_HIGH)
+#define GPIO41_KP_MKOUT_7       MFP_CFG_OUT(GPIO41, AF1, DRIVE_HIGH)
+#define GPIO96_KP_MKOUT_6       MFP_CFG_OUT(GPIO96, AF3, DRIVE_HIGH)
+
+/* USB P3 */
+#define GPIO10_USB_P3_5         MFP_CFG_IN(GPIO10, AF3)
+#define GPIO11_USB_P3_1         MFP_CFG_IN(GPIO11, AF3)
+#define GPIO30_USB_P3_2         MFP_CFG_OUT(GPIO30, AF3, DRIVE_LOW)
+#define GPIO31_USB_P3_6         MFP_CFG_OUT(GPIO31, AF3, DRIVE_LOW)
+#define GPIO56_USB_P3_4         MFP_CFG_OUT(GPIO56, AF1, DRIVE_LOW)
+#define GPIO86_USB_P3_5         MFP_CFG_IN(GPIO86, AF3)
+#define GPIO87_USB_P3_1         MFP_CFG_IN(GPIO87, AF3)
+#define GPIO90_USB_P3_5         MFP_CFG_IN(GPIO90, AF2)
+#define GPIO91_USB_P3_1         MFP_CFG_IN(GPIO91, AF2)
+#define GPIO113_USB_P3_3        MFP_CFG_IN(GPIO113, AF3)
+
+/* USB P2 */
+#define GPIO34_USB_P2_2         MFP_CFG_OUT(GPIO34, AF1, DRIVE_LOW)
+#define GPIO35_USB_P2_1         MFP_CFG_IN(GPIO35, AF2)
+#define GPIO36_USB_P2_4         MFP_CFG_OUT(GPIO36, AF1, DRIVE_LOW)
+#define GPIO37_USB_P2_8         MFP_CFG_OUT(GPIO37, AF1, DRIVE_LOW)
+#define GPIO38_USB_P2_3         MFP_CFG_IN(GPIO38, AF3)
+#define GPIO39_USB_P2_6         MFP_CFG_OUT(GPIO39, AF1, DRIVE_LOW)
+#define GPIO40_USB_P2_5         MFP_CFG_IN(GPIO40, AF3)
+#define GPIO41_USB_P2_7         MFP_CFG_IN(GPIO41, AF2)
+#define GPIO53_USB_P2_3         MFP_CFG_IN(GPIO53, AF2)
+
+/* USB Host Port 1/2 */
+#define GPIO88_USBH1_PWR        MFP_CFG_IN(GPIO88, AF1)
+#define GPIO89_USBH1_PEN        MFP_CFG_OUT(GPIO89, AF2, DRIVE_LOW)
+#define GPIO119_USBH2_PWR       MFP_CFG_IN(GPIO119, AF1)
+#define GPIO120_USBH2_PEN       MFP_CFG_OUT(GPIO120, AF2, DRIVE_LOW)
+
+/* QCI - default to Master Mode: CIF_FV/CIF_LV Direction In */
+#define GPIO115_CIF_DD_3        MFP_CFG_IN(GPIO115, AF2)
+#define GPIO116_CIF_DD_2        MFP_CFG_IN(GPIO116, AF1)
+#define GPIO12_CIF_DD_7         MFP_CFG_IN(GPIO12, AF2)
+#define GPIO17_CIF_DD_6         MFP_CFG_IN(GPIO17, AF2)
+#define GPIO23_CIF_MCLK         MFP_CFG_OUT(GPIO23, AF1, DRIVE_LOW)
+#define GPIO24_CIF_FV           MFP_CFG_IN(GPIO24, AF1)
+#define GPIO25_CIF_LV           MFP_CFG_IN(GPIO25, AF1)
+#define GPIO26_CIF_PCLK         MFP_CFG_IN(GPIO26, AF2)
+#define GPIO27_CIF_DD_0         MFP_CFG_IN(GPIO27, AF3)
+#define GPIO42_CIF_MCLK         MFP_CFG_OUT(GPIO42, AF3, DRIVE_LOW)
+#define GPIO43_CIF_FV           MFP_CFG_IN(GPIO43, AF3)
+#define GPIO44_CIF_LV           MFP_CFG_IN(GPIO44, AF3)
+#define GPIO45_CIF_PCLK         MFP_CFG_IN(GPIO45, AF3)
+#define GPIO47_CIF_DD_0         MFP_CFG_IN(GPIO47, AF1)
+#define GPIO48_CIF_DD_5         MFP_CFG_IN(GPIO48, AF1)
+#define GPIO50_CIF_DD_3         MFP_CFG_IN(GPIO50, AF1)
+#define GPIO51_CIF_DD_2         MFP_CFG_IN(GPIO51, AF1)
+#define GPIO52_CIF_DD_4         MFP_CFG_IN(GPIO52, AF1)
+#define GPIO53_CIF_MCLK         MFP_CFG_OUT(GPIO53, AF2, DRIVE_LOW)
+#define GPIO54_CIF_PCLK         MFP_CFG_IN(GPIO54, AF3)
+#define GPIO55_CIF_DD_1         MFP_CFG_IN(GPIO55, AF1)
+#define GPIO81_CIF_DD_0         MFP_CFG_IN(GPIO81, AF2)
+#define GPIO82_CIF_DD_5         MFP_CFG_IN(GPIO82, AF3)
+#define GPIO83_CIF_DD_4         MFP_CFG_IN(GPIO83, AF3)
+#define GPIO84_CIF_FV           MFP_CFG_IN(GPIO84, AF3)
+#define GPIO85_CIF_LV           MFP_CFG_IN(GPIO85, AF3)
+#define GPIO90_CIF_DD_4         MFP_CFG_IN(GPIO90, AF3)
+#define GPIO91_CIF_DD_5         MFP_CFG_IN(GPIO91, AF3)
+#define GPIO93_CIF_DD_6         MFP_CFG_IN(GPIO93, AF2)
+#define GPIO94_CIF_DD_5         MFP_CFG_IN(GPIO94, AF2)
+#define GPIO95_CIF_DD_4         MFP_CFG_IN(GPIO95, AF2)
+#define GPIO98_CIF_DD_0         MFP_CFG_IN(GPIO98, AF2)
+#define GPIO103_CIF_DD_3        MFP_CFG_IN(GPIO103, AF1)
+#define GPIO104_CIF_DD_2        MFP_CFG_IN(GPIO104, AF1)
+#define GPIO105_CIF_DD_1        MFP_CFG_IN(GPIO105, AF1)
+#define GPIO106_CIF_DD_9        MFP_CFG_IN(GPIO106, AF1)
+#define GPIO107_CIF_DD_8        MFP_CFG_IN(GPIO107, AF1)
+#define GPIO108_CIF_DD_7        MFP_CFG_IN(GPIO108, AF1)
+#define GPIO114_CIF_DD_1        MFP_CFG_IN(GPIO114, AF1)
+
+/* Universal Subscriber ID Interface */
+#define GPIO114_UVS0            MFP_CFG_OUT(GPIO114, AF2, DRIVE_LOW)
+#define GPIO115_nUVS1           MFP_CFG_OUT(GPIO115, AF2, DRIVE_LOW)
+#define GPIO116_nUVS2           MFP_CFG_OUT(GPIO116, AF2, DRIVE_LOW)
+#define GPIO14_UCLK             MFP_CFG_OUT(GPIO14, AF3, DRIVE_LOW)
+#define GPIO91_UCLK             MFP_CFG_OUT(GPIO91, AF2, DRIVE_LOW)
+#define GPIO19_nURST            MFP_CFG_OUT(GPIO19, AF3, DRIVE_LOW)
+#define GPIO90_nURST            MFP_CFG_OUT(GPIO90, AF2, DRIVE_LOW)
+#define GPIO116_UDET            MFP_CFG_IN(GPIO116, AF3)
+#define GPIO114_UEN             MFP_CFG_OUT(GPIO114, AF1, DRIVE_LOW)
+#define GPIO115_UEN             MFP_CFG_OUT(GPIO115, AF1, DRIVE_LOW)
+
+/* Mobile Scalable Link (MSL) Interface */
+#define GPIO81_BB_OB_DAT_0      MFP_CFG_OUT(GPIO81, AF2, DRIVE_LOW)
+#define GPIO48_BB_OB_DAT_1      MFP_CFG_OUT(GPIO48, AF1, DRIVE_LOW)
+#define GPIO50_BB_OB_DAT_2      MFP_CFG_OUT(GPIO50, AF1, DRIVE_LOW)
+#define GPIO51_BB_OB_DAT_3      MFP_CFG_OUT(GPIO51, AF1, DRIVE_LOW)
+#define GPIO52_BB_OB_CLK        MFP_CFG_OUT(GPIO52, AF1, DRIVE_LOW)
+#define GPIO53_BB_OB_STB        MFP_CFG_OUT(GPIO53, AF1, DRIVE_LOW)
+#define GPIO54_BB_OB_WAIT       MFP_CFG_IN(GPIO54, AF2)
+#define GPIO82_BB_IB_DAT_0      MFP_CFG_IN(GPIO82, AF2)
+#define GPIO55_BB_IB_DAT_1      MFP_CFG_IN(GPIO55, AF2)
+#define GPIO56_BB_IB_DAT_2      MFP_CFG_IN(GPIO56, AF2)
+#define GPIO57_BB_IB_DAT_3      MFP_CFG_IN(GPIO57, AF2)
+#define GPIO83_BB_IB_CLK        MFP_CFG_IN(GPIO83, AF2)
+#define GPIO84_BB_IB_STB        MFP_CFG_IN(GPIO84, AF2)
+#define GPIO85_BB_IB_WAIT       MFP_CFG_OUT(GPIO85, AF2, DRIVE_LOW)
+
+/* Memory Stick Host Controller */
+#define GPIO92_MSBS             MFP_CFG_OUT(GPIO92, AF2, DRIVE_LOW)
+#define GPIO109_MSSDIO          MFP_CFG_IN(GPIO109, AF2)
+#define GPIO112_nMSINS          MFP_CFG_IN(GPIO112, AF2)
+#define GPIO32_MSSCLK           MFP_CFG_OUT(GPIO32, AF1, DRIVE_LOW)
+
+extern int keypad_set_wake(unsigned int on);
+#endif /* __ASM_ARCH_MFP_PXA27X_H */
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
new file mode 100644
index 000000000000..3e9211591e20
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
@@ -0,0 +1,133 @@
+#ifndef __ASM_ARCH_MFP_PXA2XX_H
+#define __ASM_ARCH_MFP_PXA2XX_H
+
+#include <mach/mfp.h>
+
+/*
+ * the following MFP_xxx bit definitions in mfp.h are re-used for pxa2xx:
+ *
+ *  MFP_PIN(x)
+ *  MFP_AFx
+ *  MFP_LPM_DRIVE_{LOW, HIGH}
+ *  MFP_LPM_EDGE_x
+ *
+ * other MFP_x bit definitions will be ignored
+ *
+ * and adds the below two bits specifically for pxa2xx:
+ *
+ * bit     23 - Input/Output (PXA2xx specific)
+ * bit     24 - Wakeup Enable(PXA2xx specific)
+ */
+
+#define MFP_DIR_IN              (0x0 << 23)
+#define MFP_DIR_OUT             (0x1 << 23)
+#define MFP_DIR_MASK            (0x1 << 23)
+#define MFP_DIR(x)              (((x) >> 23) & 0x1)
+
+#define MFP_LPM_CAN_WAKEUP      (0x1 << 24)
+#define WAKEUP_ON_EDGE_RISE     (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE)
+#define WAKEUP_ON_EDGE_FALL     (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_FALL)
+#define WAKEUP_ON_EDGE_BOTH     (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_BOTH)
+
+/* specifically for enabling wakeup on keypad GPIOs */
+#define WAKEUP_ON_LEVEL_HIGH    (MFP_LPM_CAN_WAKEUP)
+
+#define MFP_CFG_IN(pin, af)             \
+        ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK)) |\
+         (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DIR_IN))
+
+/* NOTE:  pins configured as output _must_ provide a low power state,
+ * and this state should help to minimize the power dissipation.
+ */
+#define MFP_CFG_OUT(pin, af, state)     \
+        ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK | MFP_LPM_STATE_MASK)) |\
+         (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state))
+
+/* Common configurations for pxa25x and pxa27x
+ *
+ * Note: pins configured as GPIO are always initialized to input
+ * so not to cause any side effect
+ */
+#define GPIO0_GPIO      MFP_CFG_IN(GPIO0, AF0)
+#define GPIO1_GPIO      MFP_CFG_IN(GPIO1, AF0)
+#define GPIO9_GPIO      MFP_CFG_IN(GPIO9, AF0)
+#define GPIO10_GPIO     MFP_CFG_IN(GPIO10, AF0)
+#define GPIO11_GPIO     MFP_CFG_IN(GPIO11, AF0)
+#define GPIO12_GPIO     MFP_CFG_IN(GPIO12, AF0)
+#define GPIO13_GPIO     MFP_CFG_IN(GPIO13, AF0)
+#define GPIO14_GPIO     MFP_CFG_IN(GPIO14, AF0)
+#define GPIO15_GPIO     MFP_CFG_IN(GPIO15, AF0)
+#define GPIO16_GPIO     MFP_CFG_IN(GPIO16, AF0)
+#define GPIO17_GPIO     MFP_CFG_IN(GPIO17, AF0)
+#define GPIO18_GPIO     MFP_CFG_IN(GPIO18, AF0)
+#define GPIO19_GPIO     MFP_CFG_IN(GPIO19, AF0)
+#define GPIO20_GPIO     MFP_CFG_IN(GPIO20, AF0)
+#define GPIO21_GPIO     MFP_CFG_IN(GPIO21, AF0)
+#define GPIO22_GPIO     MFP_CFG_IN(GPIO22, AF0)
+#define GPIO23_GPIO     MFP_CFG_IN(GPIO23, AF0)
+#define GPIO24_GPIO     MFP_CFG_IN(GPIO24, AF0)
+#define GPIO25_GPIO     MFP_CFG_IN(GPIO25, AF0)
+#define GPIO26_GPIO     MFP_CFG_IN(GPIO26, AF0)
+#define GPIO27_GPIO     MFP_CFG_IN(GPIO27, AF0)
+#define GPIO28_GPIO     MFP_CFG_IN(GPIO28, AF0)
+#define GPIO29_GPIO     MFP_CFG_IN(GPIO29, AF0)
+#define GPIO30_GPIO     MFP_CFG_IN(GPIO30, AF0)
+#define GPIO31_GPIO     MFP_CFG_IN(GPIO31, AF0)
+#define GPIO32_GPIO     MFP_CFG_IN(GPIO32, AF0)
+#define GPIO33_GPIO     MFP_CFG_IN(GPIO33, AF0)
+#define GPIO34_GPIO     MFP_CFG_IN(GPIO34, AF0)
+#define GPIO35_GPIO     MFP_CFG_IN(GPIO35, AF0)
+#define GPIO36_GPIO     MFP_CFG_IN(GPIO36, AF0)
+#define GPIO37_GPIO     MFP_CFG_IN(GPIO37, AF0)
+#define GPIO38_GPIO     MFP_CFG_IN(GPIO38, AF0)
+#define GPIO39_GPIO     MFP_CFG_IN(GPIO39, AF0)
+#define GPIO40_GPIO     MFP_CFG_IN(GPIO40, AF0)
+#define GPIO41_GPIO     MFP_CFG_IN(GPIO41, AF0)
+#define GPIO42_GPIO     MFP_CFG_IN(GPIO42, AF0)
+#define GPIO43_GPIO     MFP_CFG_IN(GPIO43, AF0)
+#define GPIO44_GPIO     MFP_CFG_IN(GPIO44, AF0)
+#define GPIO45_GPIO     MFP_CFG_IN(GPIO45, AF0)
+#define GPIO46_GPIO     MFP_CFG_IN(GPIO46, AF0)
+#define GPIO47_GPIO     MFP_CFG_IN(GPIO47, AF0)
+#define GPIO48_GPIO     MFP_CFG_IN(GPIO48, AF0)
+#define GPIO49_GPIO     MFP_CFG_IN(GPIO49, AF0)
+#define GPIO50_GPIO     MFP_CFG_IN(GPIO50, AF0)
+#define GPIO51_GPIO     MFP_CFG_IN(GPIO51, AF0)
+#define GPIO52_GPIO     MFP_CFG_IN(GPIO52, AF0)
+#define GPIO53_GPIO     MFP_CFG_IN(GPIO53, AF0)
+#define GPIO54_GPIO     MFP_CFG_IN(GPIO54, AF0)
+#define GPIO55_GPIO     MFP_CFG_IN(GPIO55, AF0)
+#define GPIO56_GPIO     MFP_CFG_IN(GPIO56, AF0)
+#define GPIO57_GPIO     MFP_CFG_IN(GPIO57, AF0)
+#define GPIO58_GPIO     MFP_CFG_IN(GPIO58, AF0)
+#define GPIO59_GPIO     MFP_CFG_IN(GPIO59, AF0)
+#define GPIO60_GPIO     MFP_CFG_IN(GPIO60, AF0)
+#define GPIO61_GPIO     MFP_CFG_IN(GPIO61, AF0)
+#define GPIO62_GPIO     MFP_CFG_IN(GPIO62, AF0)
+#define GPIO63_GPIO     MFP_CFG_IN(GPIO63, AF0)
+#define GPIO64_GPIO     MFP_CFG_IN(GPIO64, AF0)
+#define GPIO65_GPIO     MFP_CFG_IN(GPIO65, AF0)
+#define GPIO66_GPIO     MFP_CFG_IN(GPIO66, AF0)
+#define GPIO67_GPIO     MFP_CFG_IN(GPIO67, AF0)
+#define GPIO68_GPIO     MFP_CFG_IN(GPIO68, AF0)
+#define GPIO69_GPIO     MFP_CFG_IN(GPIO69, AF0)
+#define GPIO70_GPIO     MFP_CFG_IN(GPIO70, AF0)
+#define GPIO71_GPIO     MFP_CFG_IN(GPIO71, AF0)
+#define GPIO72_GPIO     MFP_CFG_IN(GPIO72, AF0)
+#define GPIO73_GPIO     MFP_CFG_IN(GPIO73, AF0)
+#define GPIO74_GPIO     MFP_CFG_IN(GPIO74, AF0)
+#define GPIO75_GPIO     MFP_CFG_IN(GPIO75, AF0)
+#define GPIO76_GPIO     MFP_CFG_IN(GPIO76, AF0)
+#define GPIO77_GPIO     MFP_CFG_IN(GPIO77, AF0)
+#define GPIO78_GPIO     MFP_CFG_IN(GPIO78, AF0)
+#define GPIO79_GPIO     MFP_CFG_IN(GPIO79, AF0)
+#define GPIO80_GPIO     MFP_CFG_IN(GPIO80, AF0)
+#define GPIO81_GPIO     MFP_CFG_IN(GPIO81, AF0)
+#define GPIO82_GPIO     MFP_CFG_IN(GPIO82, AF0)
+#define GPIO83_GPIO     MFP_CFG_IN(GPIO83, AF0)
+#define GPIO84_GPIO     MFP_CFG_IN(GPIO84, AF0)
+
+extern void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num);
+extern void pxa2xx_mfp_set_lpm(int mfp, unsigned long lpm);
+extern int gpio_set_wake(unsigned int gpio, unsigned int on);
+#endif /* __ASM_ARCH_MFP_PXA2XX_H */
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa300.h b/arch/arm/mach-pxa/include/mach/mfp-pxa300.h
new file mode 100644
index 000000000000..bc1fb33a6e70
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa300.h
@@ -0,0 +1,575 @@
+/*
+ * arch/arm/mach-pxa/include/mach/mfp-pxa300.h
+ *
+ * PXA300/PXA310 specific MFP configuration definitions
+ *
+ * Copyright (C) 2007 Marvell International Ltd.
+ * 2007-08-21: eric miao <eric.miao@marvell.com>
+ *             initial version
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MFP_PXA300_H
+#define __ASM_ARCH_MFP_PXA300_H
+
+#include <mach/mfp.h>
+#include <mach/mfp-pxa3xx.h>
+
+/* GPIO */
+#define GPIO46_GPIO             MFP_CFG(GPIO46, AF1)
+#define GPIO49_GPIO             MFP_CFG(GPIO49, AF3)
+#define GPIO50_GPIO             MFP_CFG(GPIO50, AF2)
+#define GPIO51_GPIO             MFP_CFG(GPIO51, AF3)
+#define GPIO52_GPIO             MFP_CFG(GPIO52, AF3)
+#define GPIO56_GPIO             MFP_CFG(GPIO56, AF0)
+#define GPIO58_GPIO             MFP_CFG(GPIO58, AF0)
+#define GPIO59_GPIO             MFP_CFG(GPIO59, AF0)
+#define GPIO60_GPIO             MFP_CFG(GPIO60, AF0)
+#define GPIO61_GPIO             MFP_CFG(GPIO61, AF0)
+#define GPIO62_GPIO             MFP_CFG(GPIO62, AF0)
+
+#ifdef CONFIG_CPU_PXA310
+#define GPIO7_2_GPIO            MFP_CFG(GPIO7_2, AF0)
+#define GPIO8_2_GPIO            MFP_CFG(GPIO8_2, AF0)
+#define GPIO9_2_GPIO            MFP_CFG(GPIO9_2, AF0)
+#define GPIO10_2_GPIO           MFP_CFG(GPIO10_2, AF0)
+#define GPIO11_2_GPIO           MFP_CFG(GPIO11_2, AF0)
+#define GPIO12_2_GPIO           MFP_CFG(GPIO12_2, AF0)
+#endif
+
+/* Chip Select */
+#define GPIO2_nCS3              MFP_CFG(GPIO2,  AF1)
+
+/* AC97 */
+#define GPIO23_AC97_nACRESET    MFP_CFG(GPIO23, AF1)
+#define GPIO24_AC97_SYSCLK      MFP_CFG(GPIO24, AF1)
+#define GPIO29_AC97_BITCLK      MFP_CFG(GPIO29, AF1)
+#define GPIO25_AC97_SDATA_IN_0  MFP_CFG(GPIO25, AF1)
+#define GPIO26_AC97_SDATA_IN_1  MFP_CFG(GPIO26, AF1)
+#define GPIO17_AC97_SDATA_IN_2  MFP_CFG(GPIO17, AF3)
+#define GPIO21_AC97_SDATA_IN_2  MFP_CFG(GPIO21, AF2)
+#define GPIO18_AC97_SDATA_IN_3  MFP_CFG(GPIO18, AF3)
+#define GPIO22_AC97_SDATA_IN_3  MFP_CFG(GPIO22, AF2)
+#define GPIO27_AC97_SDATA_OUT   MFP_CFG(GPIO27, AF1)
+#define GPIO28_AC97_SYNC        MFP_CFG(GPIO28, AF1)
+
+/* I2C */
+#define GPIO21_I2C_SCL          MFP_CFG_LPM(GPIO21, AF1, PULL_HIGH)
+#define GPIO22_I2C_SDA          MFP_CFG_LPM(GPIO22, AF1, PULL_HIGH)
+
+/* QCI */
+#define GPIO39_CI_DD_0          MFP_CFG_DRV(GPIO39, AF1, DS04X)
+#define GPIO40_CI_DD_1          MFP_CFG_DRV(GPIO40, AF1, DS04X)
+#define GPIO41_CI_DD_2          MFP_CFG_DRV(GPIO41, AF1, DS04X)
+#define GPIO42_CI_DD_3          MFP_CFG_DRV(GPIO42, AF1, DS04X)
+#define GPIO43_CI_DD_4          MFP_CFG_DRV(GPIO43, AF1, DS04X)
+#define GPIO44_CI_DD_5          MFP_CFG_DRV(GPIO44, AF1, DS04X)
+#define GPIO45_CI_DD_6          MFP_CFG_DRV(GPIO45, AF1, DS04X)
+#define GPIO46_CI_DD_7          MFP_CFG_DRV(GPIO46, AF0, DS04X)
+#define GPIO47_CI_DD_8          MFP_CFG_DRV(GPIO47, AF1, DS04X)
+#define GPIO48_CI_DD_9          MFP_CFG_DRV(GPIO48, AF1, DS04X)
+#define GPIO52_CI_HSYNC         MFP_CFG_DRV(GPIO52, AF0, DS04X)
+#define GPIO51_CI_VSYNC         MFP_CFG_DRV(GPIO51, AF0, DS04X)
+#define GPIO49_CI_MCLK          MFP_CFG_DRV(GPIO49, AF0, DS04X)
+#define GPIO50_CI_PCLK          MFP_CFG_DRV(GPIO50, AF0, DS04X)
+
+/* KEYPAD */
+#define GPIO3_KP_DKIN_6         MFP_CFG_LPM(GPIO3,   AF2, FLOAT)
+#define GPIO4_KP_DKIN_7         MFP_CFG_LPM(GPIO4,   AF2, FLOAT)
+#define GPIO16_KP_DKIN_6        MFP_CFG_LPM(GPIO16,  AF6, FLOAT)
+#define GPIO83_KP_DKIN_2        MFP_CFG_LPM(GPIO83,  AF5, FLOAT)
+#define GPIO84_KP_DKIN_1        MFP_CFG_LPM(GPIO84,  AF5, FLOAT)
+#define GPIO85_KP_DKIN_0        MFP_CFG_LPM(GPIO85,  AF3, FLOAT)
+#define GPIO86_KP_DKIN_1        MFP_CFG_LPM(GPIO86,  AF3, FLOAT)
+#define GPIO87_KP_DKIN_2        MFP_CFG_LPM(GPIO87,  AF3, FLOAT)
+#define GPIO88_KP_DKIN_3        MFP_CFG_LPM(GPIO88,  AF3, FLOAT)
+#define GPIO89_KP_DKIN_3        MFP_CFG_LPM(GPIO89,  AF3, FLOAT)
+#define GPIO107_KP_DKIN_0       MFP_CFG_LPM(GPIO107, AF2, FLOAT)
+#define GPIO108_KP_DKIN_1       MFP_CFG_LPM(GPIO108, AF2, FLOAT)
+#define GPIO109_KP_DKIN_2       MFP_CFG_LPM(GPIO109, AF2, FLOAT)
+#define GPIO110_KP_DKIN_3       MFP_CFG_LPM(GPIO110, AF2, FLOAT)
+#define GPIO111_KP_DKIN_4       MFP_CFG_LPM(GPIO111, AF2, FLOAT)
+#define GPIO112_KP_DKIN_5       MFP_CFG_LPM(GPIO112, AF2, FLOAT)
+#define GPIO113_KP_DKIN_6       MFP_CFG_LPM(GPIO113, AF2, FLOAT)
+#define GPIO114_KP_DKIN_7       MFP_CFG_LPM(GPIO114, AF2, FLOAT)
+#define GPIO115_KP_DKIN_0       MFP_CFG_LPM(GPIO115, AF2, FLOAT)
+#define GPIO116_KP_DKIN_1       MFP_CFG_LPM(GPIO116, AF2, FLOAT)
+#define GPIO117_KP_DKIN_2       MFP_CFG_LPM(GPIO117, AF2, FLOAT)
+#define GPIO118_KP_DKIN_3       MFP_CFG_LPM(GPIO118, AF2, FLOAT)
+#define GPIO119_KP_DKIN_4       MFP_CFG_LPM(GPIO119, AF2, FLOAT)
+#define GPIO120_KP_DKIN_5       MFP_CFG_LPM(GPIO120, AF2, FLOAT)
+#define GPIO121_KP_DKIN_6       MFP_CFG_LPM(GPIO121, AF2, FLOAT)
+#define GPIO122_KP_DKIN_5       MFP_CFG_LPM(GPIO122, AF2, FLOAT)
+#define GPIO123_KP_DKIN_4       MFP_CFG_LPM(GPIO123, AF2, FLOAT)
+#define GPIO124_KP_DKIN_3       MFP_CFG_LPM(GPIO124, AF2, FLOAT)
+#define GPIO127_KP_DKIN_0       MFP_CFG_LPM(GPIO127, AF5, FLOAT)
+#define GPIO0_2_KP_DKIN_0       MFP_CFG_LPM(GPIO0_2, AF2, FLOAT)
+#define GPIO1_2_KP_DKIN_1       MFP_CFG_LPM(GPIO1_2, AF2, FLOAT)
+#define GPIO2_2_KP_DKIN_6       MFP_CFG_LPM(GPIO2_2, AF2, FLOAT)
+#define GPIO3_2_KP_DKIN_7       MFP_CFG_LPM(GPIO3_2, AF2, FLOAT)
+#define GPIO4_2_KP_DKIN_1       MFP_CFG_LPM(GPIO4_2, AF2, FLOAT)
+#define GPIO5_2_KP_DKIN_0       MFP_CFG_LPM(GPIO5_2, AF2, FLOAT)
+
+#define GPIO5_KP_MKIN_0         MFP_CFG_LPM(GPIO5,   AF2, FLOAT)
+#define GPIO6_KP_MKIN_1         MFP_CFG_LPM(GPIO6,   AF2, FLOAT)
+#define GPIO9_KP_MKIN_6         MFP_CFG_LPM(GPIO9,   AF3, FLOAT)
+#define GPIO10_KP_MKIN_7        MFP_CFG_LPM(GPIO10,  AF3, FLOAT)
+#define GPIO70_KP_MKIN_6        MFP_CFG_LPM(GPIO70,  AF3, FLOAT)
+#define GPIO71_KP_MKIN_7        MFP_CFG_LPM(GPIO71,  AF3, FLOAT)
+#define GPIO100_KP_MKIN_6       MFP_CFG_LPM(GPIO100, AF7, FLOAT)
+#define GPIO101_KP_MKIN_7       MFP_CFG_LPM(GPIO101, AF7, FLOAT)
+#define GPIO112_KP_MKIN_6       MFP_CFG_LPM(GPIO112, AF4, FLOAT)
+#define GPIO113_KP_MKIN_7       MFP_CFG_LPM(GPIO113, AF4, FLOAT)
+#define GPIO115_KP_MKIN_0       MFP_CFG_LPM(GPIO115, AF1, FLOAT)
+#define GPIO116_KP_MKIN_1       MFP_CFG_LPM(GPIO116, AF1, FLOAT)
+#define GPIO117_KP_MKIN_2       MFP_CFG_LPM(GPIO117, AF1, FLOAT)
+#define GPIO118_KP_MKIN_3       MFP_CFG_LPM(GPIO118, AF1, FLOAT)
+#define GPIO119_KP_MKIN_4       MFP_CFG_LPM(GPIO119, AF1, FLOAT)
+#define GPIO120_KP_MKIN_5       MFP_CFG_LPM(GPIO120, AF1, FLOAT)
+#define GPIO125_KP_MKIN_2       MFP_CFG_LPM(GPIO125, AF2, FLOAT)
+#define GPIO2_2_KP_MKIN_6       MFP_CFG_LPM(GPIO2_2, AF1, FLOAT)
+#define GPIO3_2_KP_MKIN_7       MFP_CFG_LPM(GPIO3_2, AF1, FLOAT)
+
+#define GPIO7_KP_MKOUT_5        MFP_CFG_LPM(GPIO7,   AF1, DRIVE_HIGH)
+#define GPIO11_KP_MKOUT_5       MFP_CFG_LPM(GPIO11,  AF3, DRIVE_HIGH)
+#define GPIO12_KP_MKOUT_6       MFP_CFG_LPM(GPIO12,  AF3, DRIVE_HIGH)
+#define GPIO13_KP_MKOUT_7       MFP_CFG_LPM(GPIO13,  AF3, DRIVE_HIGH)
+#define GPIO19_KP_MKOUT_4       MFP_CFG_LPM(GPIO19,  AF3, DRIVE_HIGH)
+#define GPIO20_KP_MKOUT_5       MFP_CFG_LPM(GPIO20,  AF3, DRIVE_HIGH)
+#define GPIO38_KP_MKOUT_5       MFP_CFG_LPM(GPIO38,  AF5, DRIVE_HIGH)
+#define GPIO53_KP_MKOUT_6       MFP_CFG_LPM(GPIO53,  AF5, DRIVE_HIGH)
+#define GPIO78_KP_MKOUT_7       MFP_CFG_LPM(GPIO78,  AF5, DRIVE_HIGH)
+#define GPIO85_KP_MKOUT_0       MFP_CFG_LPM(GPIO85,  AF2, DRIVE_HIGH)
+#define GPIO86_KP_MKOUT_1       MFP_CFG_LPM(GPIO86,  AF2, DRIVE_HIGH)
+#define GPIO87_KP_MKOUT_2       MFP_CFG_LPM(GPIO87,  AF2, DRIVE_HIGH)
+#define GPIO88_KP_MKOUT_3       MFP_CFG_LPM(GPIO88,  AF2, DRIVE_HIGH)
+#define GPIO104_KP_MKOUT_6      MFP_CFG_LPM(GPIO104, AF5, DRIVE_HIGH)
+#define GPIO105_KP_MKOUT_7      MFP_CFG_LPM(GPIO105, AF5, DRIVE_HIGH)
+#define GPIO121_KP_MKOUT_0      MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH)
+#define GPIO122_KP_MKOUT_1      MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH)
+#define GPIO123_KP_MKOUT_2      MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH)
+#define GPIO124_KP_MKOUT_3      MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH)
+#define GPIO125_KP_MKOUT_4      MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH)
+#define GPIO126_KP_MKOUT_7      MFP_CFG_LPM(GPIO126, AF4, DRIVE_HIGH)
+#define GPIO5_2_KP_MKOUT_6      MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH)
+#define GPIO4_2_KP_MKOUT_5      MFP_CFG_LPM(GPIO4_2, AF1, DRIVE_HIGH)
+#define GPIO6_2_KP_MKOUT_7      MFP_CFG_LPM(GPIO6_2, AF1, DRIVE_HIGH)
+
+/* LCD */
+#define GPIO54_LCD_LDD_0        MFP_CFG_DRV(GPIO54, AF1, DS01X)
+#define GPIO55_LCD_LDD_1        MFP_CFG_DRV(GPIO55, AF1, DS01X)
+#define GPIO56_LCD_LDD_2        MFP_CFG_DRV(GPIO56, AF1, DS01X)
+#define GPIO57_LCD_LDD_3        MFP_CFG_DRV(GPIO57, AF1, DS01X)
+#define GPIO58_LCD_LDD_4        MFP_CFG_DRV(GPIO58, AF1, DS01X)
+#define GPIO59_LCD_LDD_5        MFP_CFG_DRV(GPIO59, AF1, DS01X)
+#define GPIO60_LCD_LDD_6        MFP_CFG_DRV(GPIO60, AF1, DS01X)
+#define GPIO61_LCD_LDD_7        MFP_CFG_DRV(GPIO61, AF1, DS01X)
+#define GPIO62_LCD_LDD_8        MFP_CFG_DRV(GPIO62, AF1, DS01X)
+#define GPIO63_LCD_LDD_9        MFP_CFG_DRV(GPIO63, AF1, DS01X)
+#define GPIO64_LCD_LDD_10       MFP_CFG_DRV(GPIO64, AF1, DS01X)
+#define GPIO65_LCD_LDD_11       MFP_CFG_DRV(GPIO65, AF1, DS01X)
+#define GPIO66_LCD_LDD_12       MFP_CFG_DRV(GPIO66, AF1, DS01X)
+#define GPIO67_LCD_LDD_13       MFP_CFG_DRV(GPIO67, AF1, DS01X)
+#define GPIO68_LCD_LDD_14       MFP_CFG_DRV(GPIO68, AF1, DS01X)
+#define GPIO69_LCD_LDD_15       MFP_CFG_DRV(GPIO69, AF1, DS01X)
+#define GPIO70_LCD_LDD_16       MFP_CFG_DRV(GPIO70, AF1, DS01X)
+#define GPIO71_LCD_LDD_17       MFP_CFG_DRV(GPIO71, AF1, DS01X)
+#define GPIO62_LCD_CS_N         MFP_CFG_DRV(GPIO62, AF2, DS01X)
+#define GPIO72_LCD_FCLK         MFP_CFG_DRV(GPIO72, AF1, DS01X)
+#define GPIO73_LCD_LCLK         MFP_CFG_DRV(GPIO73, AF1, DS01X)
+#define GPIO74_LCD_PCLK         MFP_CFG_DRV(GPIO74, AF1, DS02X)
+#define GPIO75_LCD_BIAS         MFP_CFG_DRV(GPIO75, AF1, DS01X)
+#define GPIO76_LCD_VSYNC        MFP_CFG_DRV(GPIO76, AF2, DS01X)
+
+#define GPIO15_LCD_CS_N         MFP_CFG_DRV(GPIO15,  AF2, DS01X)
+#define GPIO127_LCD_CS_N        MFP_CFG_DRV(GPIO127, AF1, DS01X)
+#define GPIO63_LCD_VSYNC        MFP_CFG_DRV(GPIO63,  AF2, DS01X)
+
+/* Mini-LCD */
+#define GPIO72_MLCD_FCLK        MFP_CFG_DRV(GPIO72, AF7, DS08X)
+#define GPIO73_MLCD_LCLK        MFP_CFG_DRV(GPIO73, AF7, DS08X)
+#define GPIO54_MLCD_LDD_0       MFP_CFG_DRV(GPIO54, AF7, DS08X)
+#define GPIO55_MLCD_LDD_1       MFP_CFG_DRV(GPIO55, AF7, DS08X)
+#define GPIO56_MLCD_LDD_2       MFP_CFG_DRV(GPIO56, AF7, DS08X)
+#define GPIO57_MLCD_LDD_3       MFP_CFG_DRV(GPIO57, AF7, DS08X)
+#define GPIO58_MLCD_LDD_4       MFP_CFG_DRV(GPIO58, AF7, DS08X)
+#define GPIO59_MLCD_LDD_5       MFP_CFG_DRV(GPIO59, AF7, DS08X)
+#define GPIO60_MLCD_LDD_6       MFP_CFG_DRV(GPIO60, AF7, DS08X)
+#define GPIO61_MLCD_LDD_7       MFP_CFG_DRV(GPIO61, AF7, DS08X)
+#define GPIO62_MLCD_LDD_8       MFP_CFG_DRV(GPIO62, AF7, DS08X)
+#define GPIO63_MLCD_LDD_9       MFP_CFG_DRV(GPIO63, AF7, DS08X)
+#define GPIO64_MLCD_LDD_10      MFP_CFG_DRV(GPIO64, AF7, DS08X)
+#define GPIO65_MLCD_LDD_11      MFP_CFG_DRV(GPIO65, AF7, DS08X)
+#define GPIO66_MLCD_LDD_12      MFP_CFG_DRV(GPIO66, AF7, DS08X)
+#define GPIO67_MLCD_LDD_13      MFP_CFG_DRV(GPIO67, AF7, DS08X)
+#define GPIO68_MLCD_LDD_14      MFP_CFG_DRV(GPIO68, AF7, DS08X)
+#define GPIO69_MLCD_LDD_15      MFP_CFG_DRV(GPIO69, AF7, DS08X)
+#define GPIO74_MLCD_PCLK        MFP_CFG_DRV(GPIO74, AF7, DS08X)
+#define GPIO75_MLCD_BIAS        MFP_CFG_DRV(GPIO75, AF2, DS08X)
+
+/* MMC1 */
+#define GPIO7_MMC1_CLK          MFP_CFG_LPM(GPIO7,  AF4, DRIVE_HIGH)
+#define GPIO8_MMC1_CMD          MFP_CFG_LPM(GPIO8,  AF4, DRIVE_HIGH)
+#define GPIO14_MMC1_CMD         MFP_CFG_LPM(GPIO14, AF5, DRIVE_HIGH)
+#define GPIO15_MMC1_CMD         MFP_CFG_LPM(GPIO15, AF5, DRIVE_HIGH)
+#define GPIO3_MMC1_DAT0         MFP_CFG_LPM(GPIO3,  AF4, DRIVE_HIGH)
+#define GPIO4_MMC1_DAT1         MFP_CFG_LPM(GPIO4,  AF4, DRIVE_HIGH)
+#define GPIO5_MMC1_DAT2         MFP_CFG_LPM(GPIO5,  AF4, DRIVE_HIGH)
+#define GPIO6_MMC1_DAT3         MFP_CFG_LPM(GPIO6,  AF4, DRIVE_HIGH)
+
+/* MMC2 */
+#define GPIO9_MMC2_DAT0         MFP_CFG_LPM(GPIO9,  AF4, PULL_HIGH)
+#define GPIO10_MMC2_DAT1        MFP_CFG_LPM(GPIO10, AF4, PULL_HIGH)
+#define GPIO11_MMC2_DAT2        MFP_CFG_LPM(GPIO11, AF4, PULL_HIGH)
+#define GPIO12_MMC2_DAT3        MFP_CFG_LPM(GPIO12, AF4, PULL_HIGH)
+#define GPIO13_MMC2_CLK         MFP_CFG_LPM(GPIO13, AF4, PULL_HIGH)
+#define GPIO14_MMC2_CMD         MFP_CFG_LPM(GPIO14, AF4, PULL_HIGH)
+#define GPIO77_MMC2_DAT0        MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH)
+#define GPIO78_MMC2_DAT1        MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH)
+#define GPIO79_MMC2_DAT2        MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH)
+#define GPIO80_MMC2_DAT3        MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH)
+#define GPIO81_MMC2_CLK         MFP_CFG_LPM(GPIO81, AF4, PULL_HIGH)
+#define GPIO82_MMC2_CMD         MFP_CFG_LPM(GPIO82, AF4, PULL_HIGH)
+
+/* SSP1 */
+#define GPIO89_SSP1_EXTCLK      MFP_CFG(GPIO89, AF1)
+#define GPIO90_SSP1_SYSCLK      MFP_CFG(GPIO90, AF1)
+#define GPIO15_SSP1_SCLK        MFP_CFG(GPIO15, AF6)
+#define GPIO16_SSP1_FRM         MFP_CFG(GPIO16, AF2)
+#define GPIO33_SSP1_SCLK        MFP_CFG(GPIO33, AF5)
+#define GPIO34_SSP1_FRM         MFP_CFG(GPIO34, AF5)
+#define GPIO85_SSP1_SCLK        MFP_CFG(GPIO85, AF1)
+#define GPIO86_SSP1_FRM         MFP_CFG(GPIO86, AF1)
+#define GPIO18_SSP1_TXD         MFP_CFG(GPIO18, AF7)
+#define GPIO18_SSP1_RXD         MFP_CFG(GPIO18, AF2)
+#define GPIO20_SSP1_TXD         MFP_CFG(GPIO20, AF2)
+#define GPIO20_SSP1_RXD         MFP_CFG(GPIO20, AF7)
+#define GPIO35_SSP1_TXD         MFP_CFG(GPIO35, AF5)
+#define GPIO35_SSP1_RXD         MFP_CFG(GPIO35, AF4)
+#define GPIO36_SSP1_TXD         MFP_CFG(GPIO36, AF5)
+#define GPIO36_SSP1_RXD         MFP_CFG(GPIO36, AF6)
+#define GPIO87_SSP1_TXD         MFP_CFG(GPIO87, AF1)
+#define GPIO87_SSP1_RXD         MFP_CFG(GPIO87, AF6)
+#define GPIO88_SSP1_TXD         MFP_CFG(GPIO88, AF6)
+#define GPIO88_SSP1_RXD         MFP_CFG(GPIO88, AF1)
+
+/* SSP2 */
+#define GPIO29_SSP2_EXTCLK      MFP_CFG(GPIO29, AF2)
+#define GPIO23_SSP2_SCLK        MFP_CFG(GPIO23, AF2)
+#define GPIO17_SSP2_FRM         MFP_CFG(GPIO17, AF2)
+#define GPIO25_SSP2_SCLK        MFP_CFG(GPIO25, AF2)
+#define GPIO26_SSP2_FRM         MFP_CFG(GPIO26, AF2)
+#define GPIO33_SSP2_SCLK        MFP_CFG(GPIO33, AF6)
+#define GPIO34_SSP2_FRM         MFP_CFG(GPIO34, AF6)
+#define GPIO64_SSP2_SCLK        MFP_CFG(GPIO64, AF2)
+#define GPIO65_SSP2_FRM         MFP_CFG(GPIO65, AF2)
+#define GPIO19_SSP2_TXD         MFP_CFG(GPIO19, AF2)
+#define GPIO19_SSP2_RXD         MFP_CFG(GPIO19, AF7)
+#define GPIO24_SSP2_TXD         MFP_CFG(GPIO24, AF5)
+#define GPIO24_SSP2_RXD         MFP_CFG(GPIO24, AF4)
+#define GPIO27_SSP2_TXD         MFP_CFG(GPIO27, AF2)
+#define GPIO27_SSP2_RXD         MFP_CFG(GPIO27, AF5)
+#define GPIO28_SSP2_TXD         MFP_CFG(GPIO28, AF5)
+#define GPIO28_SSP2_RXD         MFP_CFG(GPIO28, AF2)
+#define GPIO35_SSP2_TXD         MFP_CFG(GPIO35, AF7)
+#define GPIO35_SSP2_RXD         MFP_CFG(GPIO35, AF6)
+#define GPIO66_SSP2_TXD         MFP_CFG(GPIO66, AF4)
+#define GPIO66_SSP2_RXD         MFP_CFG(GPIO66, AF2)
+#define GPIO67_SSP2_TXD         MFP_CFG(GPIO67, AF2)
+#define GPIO67_SSP2_RXD         MFP_CFG(GPIO67, AF4)
+#define GPIO36_SSP2_TXD         MFP_CFG(GPIO36, AF7)
+
+/* SSP3 */
+#define GPIO69_SSP3_FRM         MFP_CFG_X(GPIO69, AF2, DS08X, DRIVE_LOW)
+#define GPIO68_SSP3_SCLK        MFP_CFG_X(GPIO68, AF2, DS08X, FLOAT)
+#define GPIO92_SSP3_FRM         MFP_CFG_X(GPIO92, AF1, DS08X, DRIVE_LOW)
+#define GPIO91_SSP3_SCLK        MFP_CFG_X(GPIO91, AF1, DS08X, FLOAT)
+#define GPIO70_SSP3_TXD         MFP_CFG_X(GPIO70, AF2, DS08X, DRIVE_LOW)
+#define GPIO70_SSP3_RXD         MFP_CFG_X(GPIO70, AF5, DS08X, FLOAT)
+#define GPIO71_SSP3_TXD         MFP_CFG_X(GPIO71, AF5, DS08X, DRIVE_LOW)
+#define GPIO71_SSP3_RXD         MFP_CFG_X(GPIO71, AF2, DS08X, FLOAT)
+#define GPIO93_SSP3_TXD         MFP_CFG_X(GPIO93, AF1, DS08X, DRIVE_LOW)
+#define GPIO93_SSP3_RXD         MFP_CFG_X(GPIO93, AF5, DS08X, FLOAT)
+#define GPIO94_SSP3_TXD         MFP_CFG_X(GPIO94, AF5, DS08X, DRIVE_LOW)
+#define GPIO94_SSP3_RXD         MFP_CFG_X(GPIO94, AF1, DS08X, FLOAT)
+
+/* SSP4 */
+#define GPIO95_SSP4_SCLK        MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH)
+#define GPIO96_SSP4_FRM         MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH)
+#define GPIO97_SSP4_TXD         MFP_CFG_LPM(GPIO97, AF1, PULL_HIGH)
+#define GPIO97_SSP4_RXD         MFP_CFG_LPM(GPIO97, AF5, PULL_HIGH)
+#define GPIO98_SSP4_TXD         MFP_CFG_LPM(GPIO98, AF5, PULL_HIGH)
+#define GPIO98_SSP4_RXD         MFP_CFG_LPM(GPIO98, AF1, PULL_HIGH)
+
+/* UART1 */
+#define GPIO32_UART1_CTS        MFP_CFG_LPM(GPIO32,  AF2, FLOAT)
+#define GPIO37_UART1_CTS        MFP_CFG_LPM(GPIO37,  AF4, FLOAT)
+#define GPIO79_UART1_CTS        MFP_CFG_LPM(GPIO79,  AF1, FLOAT)
+#define GPIO84_UART1_CTS        MFP_CFG_LPM(GPIO84,  AF3, FLOAT)
+#define GPIO101_UART1_CTS       MFP_CFG_LPM(GPIO101, AF1, FLOAT)
+#define GPIO106_UART1_CTS       MFP_CFG_LPM(GPIO106, AF6, FLOAT)
+
+#define GPIO32_UART1_RTS        MFP_CFG_LPM(GPIO32,  AF4, FLOAT)
+#define GPIO37_UART1_RTS        MFP_CFG_LPM(GPIO37,  AF2, FLOAT)
+#define GPIO79_UART1_RTS        MFP_CFG_LPM(GPIO79,  AF3, FLOAT)
+#define GPIO84_UART1_RTS        MFP_CFG_LPM(GPIO84,  AF1, FLOAT)
+#define GPIO101_UART1_RTS       MFP_CFG_LPM(GPIO101, AF6, FLOAT)
+#define GPIO106_UART1_RTS       MFP_CFG_LPM(GPIO106, AF1, FLOAT)
+
+#define GPIO34_UART1_DSR        MFP_CFG_LPM(GPIO34,  AF2, FLOAT)
+#define GPIO36_UART1_DSR        MFP_CFG_LPM(GPIO36,  AF4, FLOAT)
+#define GPIO81_UART1_DSR        MFP_CFG_LPM(GPIO81,  AF1, FLOAT)
+#define GPIO83_UART1_DSR        MFP_CFG_LPM(GPIO83,  AF3, FLOAT)
+#define GPIO103_UART1_DSR       MFP_CFG_LPM(GPIO103, AF1, FLOAT)
+#define GPIO105_UART1_DSR       MFP_CFG_LPM(GPIO105, AF6, FLOAT)
+
+#define GPIO34_UART1_DTR        MFP_CFG_LPM(GPIO34,  AF4, FLOAT)
+#define GPIO36_UART1_DTR        MFP_CFG_LPM(GPIO36,  AF2, FLOAT)
+#define GPIO81_UART1_DTR        MFP_CFG_LPM(GPIO81,  AF3, FLOAT)
+#define GPIO83_UART1_DTR        MFP_CFG_LPM(GPIO83,  AF1, FLOAT)
+#define GPIO103_UART1_DTR       MFP_CFG_LPM(GPIO103, AF6, FLOAT)
+#define GPIO105_UART1_DTR       MFP_CFG_LPM(GPIO105, AF1, FLOAT)
+
+#define GPIO35_UART1_RI         MFP_CFG_LPM(GPIO35,  AF2, FLOAT)
+#define GPIO82_UART1_RI         MFP_CFG_LPM(GPIO82,  AF1, FLOAT)
+#define GPIO104_UART1_RI        MFP_CFG_LPM(GPIO104, AF1, FLOAT)
+
+#define GPIO33_UART1_DCD        MFP_CFG_LPM(GPIO33,  AF2, FLOAT)
+#define GPIO80_UART1_DCD        MFP_CFG_LPM(GPIO80,  AF1, FLOAT)
+#define GPIO102_UART1_DCD       MFP_CFG_LPM(GPIO102, AF1, FLOAT)
+
+#define GPIO30_UART1_RXD        MFP_CFG_LPM(GPIO30,  AF2, FLOAT)
+#define GPIO31_UART1_RXD        MFP_CFG_LPM(GPIO31,  AF4, FLOAT)
+#define GPIO77_UART1_RXD        MFP_CFG_LPM(GPIO77,  AF1, FLOAT)
+#define GPIO78_UART1_RXD        MFP_CFG_LPM(GPIO78,  AF3, FLOAT)
+#define GPIO99_UART1_RXD        MFP_CFG_LPM(GPIO99,  AF1, FLOAT)
+#define GPIO100_UART1_RXD       MFP_CFG_LPM(GPIO100, AF6, FLOAT)
+#define GPIO102_UART1_RXD       MFP_CFG_LPM(GPIO102, AF6, FLOAT)
+#define GPIO104_UART1_RXD       MFP_CFG_LPM(GPIO104, AF4, FLOAT)
+
+#define GPIO30_UART1_TXD        MFP_CFG_LPM(GPIO30,  AF4, FLOAT)
+#define GPIO31_UART1_TXD        MFP_CFG_LPM(GPIO31,  AF2, FLOAT)
+#define GPIO77_UART1_TXD        MFP_CFG_LPM(GPIO77,  AF3, FLOAT)
+#define GPIO78_UART1_TXD        MFP_CFG_LPM(GPIO78,  AF1, FLOAT)
+#define GPIO99_UART1_TXD        MFP_CFG_LPM(GPIO99,  AF6, FLOAT)
+#define GPIO100_UART1_TXD       MFP_CFG_LPM(GPIO100, AF1, FLOAT)
+#define GPIO102_UART1_TXD       MFP_CFG_LPM(GPIO102, AF4, FLOAT)
+
+/* UART2 */
+#define GPIO15_UART2_CTS        MFP_CFG_LPM(GPIO15,  AF3, FLOAT)
+#define GPIO16_UART2_CTS        MFP_CFG_LPM(GPIO16,  AF5, FLOAT)
+#define GPIO111_UART2_CTS       MFP_CFG_LPM(GPIO111, AF3, FLOAT)
+#define GPIO114_UART2_CTS       MFP_CFG_LPM(GPIO114, AF1, FLOAT)
+
+#define GPIO15_UART2_RTS        MFP_CFG_LPM(GPIO15,  AF4, FLOAT)
+#define GPIO16_UART2_RTS        MFP_CFG_LPM(GPIO16,  AF4, FLOAT)
+#define GPIO114_UART2_RTS       MFP_CFG_LPM(GPIO114, AF3, FLOAT)
+#define GPIO111_UART2_RTS       MFP_CFG_LPM(GPIO111, AF1, FLOAT)
+
+#define GPIO18_UART2_RXD        MFP_CFG_LPM(GPIO18,  AF5, FLOAT)
+#define GPIO19_UART2_RXD        MFP_CFG_LPM(GPIO19,  AF4, FLOAT)
+#define GPIO112_UART2_RXD       MFP_CFG_LPM(GPIO112, AF1, FLOAT)
+#define GPIO113_UART2_RXD       MFP_CFG_LPM(GPIO113, AF3, FLOAT)
+
+#define GPIO18_UART2_TXD        MFP_CFG_LPM(GPIO18,  AF4, FLOAT)
+#define GPIO19_UART2_TXD        MFP_CFG_LPM(GPIO19,  AF5, FLOAT)
+#define GPIO112_UART2_TXD       MFP_CFG_LPM(GPIO112, AF3, FLOAT)
+#define GPIO113_UART2_TXD       MFP_CFG_LPM(GPIO113, AF1, FLOAT)
+
+/* UART3 */
+#define GPIO91_UART3_CTS        MFP_CFG_LPM(GPIO91,  AF2, FLOAT)
+#define GPIO92_UART3_CTS        MFP_CFG_LPM(GPIO92,  AF4, FLOAT)
+#define GPIO107_UART3_CTS       MFP_CFG_LPM(GPIO107, AF1, FLOAT)
+#define GPIO108_UART3_CTS       MFP_CFG_LPM(GPIO108, AF3, FLOAT)
+
+#define GPIO91_UART3_RTS        MFP_CFG_LPM(GPIO91,  AF4, FLOAT)
+#define GPIO92_UART3_RTS        MFP_CFG_LPM(GPIO92,  AF2, FLOAT)
+#define GPIO107_UART3_RTS       MFP_CFG_LPM(GPIO107, AF3, FLOAT)
+#define GPIO108_UART3_RTS       MFP_CFG_LPM(GPIO108, AF1, FLOAT)
+
+#define GPIO7_UART3_RXD         MFP_CFG_LPM(GPIO7,   AF2, FLOAT)
+#define GPIO8_UART3_RXD         MFP_CFG_LPM(GPIO8,   AF6, FLOAT)
+#define GPIO93_UART3_RXD        MFP_CFG_LPM(GPIO93,  AF4, FLOAT)
+#define GPIO94_UART3_RXD        MFP_CFG_LPM(GPIO94,  AF2, FLOAT)
+#define GPIO109_UART3_RXD       MFP_CFG_LPM(GPIO109, AF3, FLOAT)
+#define GPIO110_UART3_RXD       MFP_CFG_LPM(GPIO110, AF1, FLOAT)
+
+#define GPIO7_UART3_TXD         MFP_CFG_LPM(GPIO7,   AF6, FLOAT)
+#define GPIO8_UART3_TXD         MFP_CFG_LPM(GPIO8,   AF2, FLOAT)
+#define GPIO93_UART3_TXD        MFP_CFG_LPM(GPIO93,  AF2, FLOAT)
+#define GPIO94_UART3_TXD        MFP_CFG_LPM(GPIO94,  AF4, FLOAT)
+#define GPIO109_UART3_TXD       MFP_CFG_LPM(GPIO109, AF1, FLOAT)
+#define GPIO110_UART3_TXD       MFP_CFG_LPM(GPIO110, AF3, FLOAT)
+
+/* USB Host */
+#define GPIO0_2_USBH_PEN        MFP_CFG(GPIO0_2, AF1)
+#define GPIO1_2_USBH_PWR        MFP_CFG(GPIO1_2, AF1)
+
+/* USB P3 */
+#define GPIO77_USB_P3_1         MFP_CFG(GPIO77,  AF2)
+#define GPIO78_USB_P3_2         MFP_CFG(GPIO78,  AF2)
+#define GPIO79_USB_P3_3         MFP_CFG(GPIO79,  AF2)
+#define GPIO80_USB_P3_4         MFP_CFG(GPIO80,  AF2)
+#define GPIO81_USB_P3_5         MFP_CFG(GPIO81,  AF2)
+#define GPIO82_USB_P3_6         MFP_CFG(GPIO82,  AF2)
+
+/* PWM */
+#define GPIO17_PWM0_OUT         MFP_CFG(GPIO17, AF1)
+#define GPIO18_PWM1_OUT         MFP_CFG(GPIO18, AF1)
+#define GPIO19_PWM2_OUT         MFP_CFG(GPIO19, AF1)
+#define GPIO20_PWM3_OUT         MFP_CFG(GPIO20, AF1)
+
+/* CIR */
+#define GPIO8_CIR_OUT           MFP_CFG(GPIO8, AF5)
+#define GPIO16_CIR_OUT          MFP_CFG(GPIO16, AF3)
+
+#define GPIO20_OW_DQ_IN         MFP_CFG(GPIO20, AF5)
+#define GPIO126_OW_DQ           MFP_CFG(GPIO126, AF2)
+
+#define GPIO0_DF_RDY            MFP_CFG(GPIO0, AF1)
+#define GPIO7_CLK_BYPASS_XSC    MFP_CFG(GPIO7, AF7)
+#define GPIO17_EXT_SYNC_MVT_0   MFP_CFG(GPIO17, AF6)
+#define GPIO18_EXT_SYNC_MVT_1   MFP_CFG(GPIO18, AF6)
+#define GPIO19_OST_CHOUT_MVT_0  MFP_CFG(GPIO19, AF6)
+#define GPIO20_OST_CHOUT_MVT_1  MFP_CFG(GPIO20, AF6)
+#define GPIO49_48M_CLK          MFP_CFG(GPIO49, AF2)
+#define GPIO126_EXT_CLK         MFP_CFG(GPIO126, AF3)
+#define GPIO127_CLK_BYPASS_GB   MFP_CFG(GPIO127, AF7)
+#define GPIO71_EXT_MATCH_MVT    MFP_CFG(GPIO71, AF6)
+
+#define GPIO3_uIO_IN            MFP_CFG(GPIO3, AF1)
+
+#define GPIO4_uSIM_CARD_STATE   MFP_CFG(GPIO4, AF1)
+#define GPIO5_uSIM_uCLK         MFP_CFG(GPIO5, AF1)
+#define GPIO6_uSIM_uRST         MFP_CFG(GPIO6, AF1)
+#define GPIO16_uSIM_UVS_0       MFP_CFG(GPIO16, AF1)
+
+#define GPIO9_SCIO              MFP_CFG(GPIO9, AF1)
+#define GPIO20_RTC_MVT          MFP_CFG(GPIO20, AF4)
+#define GPIO126_RTC_MVT         MFP_CFG(GPIO126, AF1)
+
+/*
+ * PXA300 specific MFP configurations
+ */
+#ifdef CONFIG_CPU_PXA300
+#define GPIO99_USB_P2_2         MFP_CFG(GPIO99, AF2)
+#define GPIO99_USB_P2_5         MFP_CFG(GPIO99, AF3)
+#define GPIO99_USB_P2_6         MFP_CFG(GPIO99, AF4)
+#define GPIO100_USB_P2_2        MFP_CFG(GPIO100, AF4)
+#define GPIO100_USB_P2_5        MFP_CFG(GPIO100, AF5)
+#define GPIO101_USB_P2_1        MFP_CFG(GPIO101, AF2)
+#define GPIO102_USB_P2_4        MFP_CFG(GPIO102, AF2)
+#define GPIO104_USB_P2_3        MFP_CFG(GPIO104, AF2)
+#define GPIO105_USB_P2_5        MFP_CFG(GPIO105, AF2)
+#define GPIO100_USB_P2_6        MFP_CFG(GPIO100, AF2)
+#define GPIO106_USB_P2_7        MFP_CFG(GPIO106, AF2)
+#define GPIO103_USB_P2_8        MFP_CFG(GPIO103, AF2)
+
+/* U2D UTMI */
+#define GPIO38_UTM_CLK          MFP_CFG(GPIO38,  AF1)
+#define GPIO26_U2D_RXERROR      MFP_CFG(GPIO26,  AF3)
+#define GPIO50_U2D_RXERROR      MFP_CFG(GPIO50,  AF1)
+#define GPIO89_U2D_RXERROR      MFP_CFG(GPIO89,  AF5)
+#define GPIO24_UTM_RXVALID      MFP_CFG(GPIO24,  AF3)
+#define GPIO48_UTM_RXVALID      MFP_CFG(GPIO48,  AF2)
+#define GPIO87_UTM_RXVALID      MFP_CFG(GPIO87,  AF5)
+#define GPIO25_UTM_RXACTIVE     MFP_CFG(GPIO25,  AF3)
+#define GPIO47_UTM_RXACTIVE     MFP_CFG(GPIO47,  AF2)
+#define GPIO49_UTM_RXACTIVE     MFP_CFG(GPIO49,  AF1)
+#define GPIO88_UTM_RXACTIVE     MFP_CFG(GPIO88,  AF5)
+#define GPIO53_UTM_TXREADY      MFP_CFG(GPIO53,  AF1)
+#define GPIO67_UTM_LINESTATE_0  MFP_CFG(GPIO67,  AF3)
+#define GPIO92_UTM_LINESTATE_0  MFP_CFG(GPIO92,  AF3)
+#define GPIO104_UTM_LINESTATE_0 MFP_CFG(GPIO104, AF3)
+#define GPIO109_UTM_LINESTATE_0 MFP_CFG(GPIO109, AF4)
+#define GPIO68_UTM_LINESTATE_1  MFP_CFG(GPIO68,  AF3)
+#define GPIO93_UTM_LINESTATE_1  MFP_CFG(GPIO93,  AF3)
+#define GPIO105_UTM_LINESTATE_1 MFP_CFG(GPIO105, AF3)
+#define GPIO27_U2D_OPMODE_0     MFP_CFG(GPIO27,  AF4)
+#define GPIO51_U2D_OPMODE_0     MFP_CFG(GPIO51,  AF2)
+#define GPIO90_U2D_OPMODE_0     MFP_CFG(GPIO90,  AF7)
+#define GPIO28_U2D_OPMODE_1     MFP_CFG(GPIO28,  AF4)
+#define GPIO52_U2D_OPMODE_1     MFP_CFG(GPIO52,  AF2)
+#define GPIO106_U2D_OPMODE_1    MFP_CFG(GPIO106, AF3)
+#define GPIO110_U2D_OPMODE_1    MFP_CFG(GPIO110, AF5)
+#define GPIO76_U2D_RESET        MFP_CFG(GPIO76,  AF1)
+#define GPIO95_U2D_RESET        MFP_CFG(GPIO95,  AF2)
+#define GPIO100_U2D_RESET       MFP_CFG(GPIO100, AF3)
+#define GPIO66_U2D_SUSPEND      MFP_CFG(GPIO66,  AF3)
+#define GPIO98_U2D_SUSPEND      MFP_CFG(GPIO98,  AF2)
+#define GPIO103_U2D_SUSPEND     MFP_CFG(GPIO103, AF3)
+#define GPIO65_U2D_TERM_SEL     MFP_CFG(GPIO65,  AF5)
+#define GPIO97_U2D_TERM_SEL     MFP_CFG(GPIO97,  AF3)
+#define GPIO102_U2D_TERM_SEL    MFP_CFG(GPIO102, AF5)
+#define GPIO29_U2D_TXVALID      MFP_CFG(GPIO29,  AF3)
+#define GPIO52_U2D_TXVALID      MFP_CFG(GPIO52,  AF4)
+#define GPIO69_U2D_TXVALID      MFP_CFG(GPIO69,  AF3)
+#define GPIO85_U2D_TXVALID      MFP_CFG(GPIO85,  AF7)
+#define GPIO64_U2D_XCVR_SEL     MFP_CFG(GPIO64,  AF5)
+#define GPIO96_U2D_XCVR_SEL     MFP_CFG(GPIO96,  AF3)
+#define GPIO101_U2D_XCVR_SEL    MFP_CFG(GPIO101, AF5)
+#define GPIO30_UTM_PHYDATA_0    MFP_CFG(GPIO30,  AF3)
+#define GPIO31_UTM_PHYDATA_1    MFP_CFG(GPIO31,  AF3)
+#define GPIO32_UTM_PHYDATA_2    MFP_CFG(GPIO32,  AF3)
+#define GPIO33_UTM_PHYDATA_3    MFP_CFG(GPIO33,  AF3)
+#define GPIO34_UTM_PHYDATA_4    MFP_CFG(GPIO34,  AF3)
+#define GPIO35_UTM_PHYDATA_5    MFP_CFG(GPIO35,  AF3)
+#define GPIO36_UTM_PHYDATA_6    MFP_CFG(GPIO36,  AF3)
+#define GPIO37_UTM_PHYDATA_7    MFP_CFG(GPIO37,  AF3)
+#define GPIO39_UTM_PHYDATA_0    MFP_CFG(GPIO39,  AF3)
+#define GPIO40_UTM_PHYDATA_1    MFP_CFG(GPIO40,  AF3)
+#define GPIO41_UTM_PHYDATA_2    MFP_CFG(GPIO41,  AF3)
+#define GPIO42_UTM_PHYDATA_3    MFP_CFG(GPIO42,  AF3)
+#define GPIO43_UTM_PHYDATA_4    MFP_CFG(GPIO43,  AF3)
+#define GPIO44_UTM_PHYDATA_5    MFP_CFG(GPIO44,  AF3)
+#define GPIO45_UTM_PHYDATA_6    MFP_CFG(GPIO45,  AF3)
+#define GPIO46_UTM_PHYDATA_7    MFP_CFG(GPIO46,  AF3)
+#endif /* CONFIG_CPU_PXA300 */
+
+/*
+ * PXA310 specific MFP configurations
+ */
+#ifdef CONFIG_CPU_PXA310
+/* USB P2 */
+#define GPIO36_USB_P2_1         MFP_CFG(GPIO36, AF1)
+#define GPIO30_USB_P2_2         MFP_CFG(GPIO30, AF1)
+#define GPIO35_USB_P2_3         MFP_CFG(GPIO35, AF1)
+#define GPIO32_USB_P2_4         MFP_CFG(GPIO32, AF1)
+#define GPIO34_USB_P2_5         MFP_CFG(GPIO34, AF1)
+#define GPIO31_USB_P2_6         MFP_CFG(GPIO31, AF1)
+
+/* MMC1 */
+#define GPIO24_MMC1_CMD         MFP_CFG(GPIO24, AF3)
+#define GPIO29_MMC1_DAT0        MFP_CFG(GPIO29, AF3)
+
+/* MMC3 */
+#define GPIO103_MMC3_CLK        MFP_CFG(GPIO103, AF2)
+#define GPIO105_MMC3_CMD        MFP_CFG(GPIO105, AF2)
+#define GPIO11_2_MMC3_CLK       MFP_CFG(GPIO11_2, AF1)
+#define GPIO12_2_MMC3_CMD       MFP_CFG(GPIO12_2, AF1)
+#define GPIO7_2_MMC3_DAT0       MFP_CFG(GPIO7_2, AF1)
+#define GPIO8_2_MMC3_DAT1       MFP_CFG(GPIO8_2, AF1)
+#define GPIO9_2_MMC3_DAT2       MFP_CFG(GPIO9_2, AF1)
+#define GPIO10_2_MMC3_DAT3      MFP_CFG(GPIO10_2, AF1)
+
+/* ULPI */
+#define GPIO38_ULPI_CLK         MFP_CFG(GPIO38, AF1)
+#define GPIO30_ULPI_DATA_OUT_0  MFP_CFG(GPIO30, AF3)
+#define GPIO31_ULPI_DATA_OUT_1  MFP_CFG(GPIO31, AF3)
+#define GPIO32_ULPI_DATA_OUT_2  MFP_CFG(GPIO32, AF3)
+#define GPIO33_ULPI_DATA_OUT_3  MFP_CFG(GPIO33, AF3)
+#define GPIO34_ULPI_DATA_OUT_4  MFP_CFG(GPIO34, AF3)
+#define GPIO35_ULPI_DATA_OUT_5  MFP_CFG(GPIO35, AF3)
+#define GPIO36_ULPI_DATA_OUT_6  MFP_CFG(GPIO36, AF3)
+#define GPIO37_ULPI_DATA_OUT_7  MFP_CFG(GPIO37, AF3)
+#define GPIO33_ULPI_OTG_INTR    MFP_CFG(GPIO33, AF1)
+
+#define ULPI_DIR        MFP_CFG_DRV(ULPI_DIR, MFP_AF0, MFP_DS01X)
+#define ULPI_NXT        MFP_CFG_DRV(ULPI_NXT, MFP_AF0, MFP_DS01X)
+#define ULPI_STP        MFP_CFG_DRV(ULPI_STP, MFP_AF0, MFP_DS01X)
+#endif /* CONFIG_CPU_PXA310 */
+
+#endif /* __ASM_ARCH_MFP_PXA300_H */
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa320.h b/arch/arm/mach-pxa/include/mach/mfp-pxa320.h
new file mode 100644
index 000000000000..74990510cf34
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa320.h
@@ -0,0 +1,447 @@
+/*
+ * arch/arm/mach-pxa/include/mach/mfp-pxa320.h
+ *
+ * PXA320 specific MFP configuration definitions
+ *
+ * Copyright (C) 2007 Marvell International Ltd.
+ * 2007-08-21: eric miao <eric.miao@marvell.com>
+ *             initial version
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MFP_PXA320_H
+#define __ASM_ARCH_MFP_PXA320_H
+
+#include <mach/mfp.h>
+#include <mach/mfp-pxa3xx.h>
+
+/* GPIO */
+#define GPIO46_GPIO             MFP_CFG(GPIO46, AF0)
+#define GPIO49_GPIO             MFP_CFG(GPIO49, AF0)
+#define GPIO50_GPIO             MFP_CFG(GPIO50, AF0)
+#define GPIO51_GPIO             MFP_CFG(GPIO51, AF0)
+#define GPIO52_GPIO             MFP_CFG(GPIO52, AF0)
+
+#define GPIO7_2_GPIO            MFP_CFG(GPIO7_2, AF0)
+#define GPIO8_2_GPIO            MFP_CFG(GPIO8_2, AF0)
+#define GPIO9_2_GPIO            MFP_CFG(GPIO9_2, AF0)
+#define GPIO10_2_GPIO           MFP_CFG(GPIO10_2, AF0)
+#define GPIO11_2_GPIO           MFP_CFG(GPIO11_2, AF0)
+#define GPIO12_2_GPIO           MFP_CFG(GPIO12_2, AF0)
+#define GPIO13_2_GPIO           MFP_CFG(GPIO13_2, AF0)
+#define GPIO14_2_GPIO           MFP_CFG(GPIO14_2, AF0)
+#define GPIO15_2_GPIO           MFP_CFG(GPIO15_2, AF0)
+#define GPIO16_2_GPIO           MFP_CFG(GPIO16_2, AF0)
+#define GPIO17_2_GPIO           MFP_CFG(GPIO17_2, AF0)
+
+/* Chip Select */
+#define GPIO4_nCS3              MFP_CFG(GPIO4, AF1)
+
+/* AC97 */
+#define GPIO34_AC97_SYSCLK      MFP_CFG(GPIO34, AF1)
+#define GPIO39_AC97_BITCLK      MFP_CFG(GPIO39, AF1)
+#define GPIO40_AC97_nACRESET    MFP_CFG(GPIO40, AF1)
+#define GPIO35_AC97_SDATA_IN_0  MFP_CFG(GPIO35, AF1)
+#define GPIO36_AC97_SDATA_IN_1  MFP_CFG(GPIO36, AF1)
+#define GPIO32_AC97_SDATA_IN_2  MFP_CFG(GPIO32, AF2)
+#define GPIO33_AC97_SDATA_IN_3  MFP_CFG(GPIO33, AF2)
+#define GPIO11_AC97_SDATA_IN_2  MFP_CFG(GPIO11, AF3)
+#define GPIO12_AC97_SDATA_IN_3  MFP_CFG(GPIO12, AF3)
+#define GPIO37_AC97_SDATA_OUT   MFP_CFG(GPIO37, AF1)
+#define GPIO38_AC97_SYNC        MFP_CFG(GPIO38, AF1)
+
+/* I2C */
+#define GPIO32_I2C_SCL          MFP_CFG_LPM(GPIO32, AF1, PULL_HIGH)
+#define GPIO33_I2C_SDA          MFP_CFG_LPM(GPIO33, AF1, PULL_HIGH)
+
+/* QCI */
+#define GPIO49_CI_DD_0          MFP_CFG_DRV(GPIO49, AF1, DS04X)
+#define GPIO50_CI_DD_1          MFP_CFG_DRV(GPIO50, AF1, DS04X)
+#define GPIO51_CI_DD_2          MFP_CFG_DRV(GPIO51, AF1, DS04X)
+#define GPIO52_CI_DD_3          MFP_CFG_DRV(GPIO52, AF1, DS04X)
+#define GPIO53_CI_DD_4          MFP_CFG_DRV(GPIO53, AF1, DS04X)
+#define GPIO54_CI_DD_5          MFP_CFG_DRV(GPIO54, AF1, DS04X)
+#define GPIO55_CI_DD_6          MFP_CFG_DRV(GPIO55, AF1, DS04X)
+#define GPIO56_CI_DD_7          MFP_CFG_DRV(GPIO56, AF0, DS04X)
+#define GPIO57_CI_DD_8          MFP_CFG_DRV(GPIO57, AF1, DS04X)
+#define GPIO58_CI_DD_9          MFP_CFG_DRV(GPIO58, AF1, DS04X)
+#define GPIO59_CI_MCLK          MFP_CFG_DRV(GPIO59, AF0, DS04X)
+#define GPIO60_CI_PCLK          MFP_CFG_DRV(GPIO60, AF0, DS04X)
+#define GPIO61_CI_HSYNC         MFP_CFG_DRV(GPIO61, AF0, DS04X)
+#define GPIO62_CI_VSYNC         MFP_CFG_DRV(GPIO62, AF0, DS04X)
+
+#define GPIO31_CIR_OUT          MFP_CFG(GPIO31, AF5)
+
+#define GPIO0_2_CLK_EXT         MFP_CFG(GPIO0_2, AF3)
+#define GPIO0_DRQ               MFP_CFG(GPIO0, AF2)
+#define GPIO11_EXT_SYNC0        MFP_CFG(GPIO11, AF5)
+#define GPIO12_EXT_SYNC1        MFP_CFG(GPIO12, AF6)
+#define GPIO0_2_HZ_CLK          MFP_CFG(GPIO0_2, AF1)
+#define GPIO14_HZ_CLK           MFP_CFG(GPIO14, AF4)
+#define GPIO30_ICP_RXD          MFP_CFG(GPIO30, AF1)
+#define GPIO31_ICP_TXD          MFP_CFG(GPIO31, AF1)
+
+#define GPIO83_KP_DKIN_0        MFP_CFG_LPM(GPIO83, AF3, FLOAT)
+#define GPIO84_KP_DKIN_1        MFP_CFG_LPM(GPIO84, AF3, FLOAT)
+#define GPIO85_KP_DKIN_2        MFP_CFG_LPM(GPIO85, AF3, FLOAT)
+#define GPIO86_KP_DKIN_3        MFP_CFG_LPM(GPIO86, AF3, FLOAT)
+
+#define GPIO105_KP_DKIN_0       MFP_CFG_LPM(GPIO105, AF2, FLOAT)
+#define GPIO106_KP_DKIN_1       MFP_CFG_LPM(GPIO106, AF2, FLOAT)
+#define GPIO107_KP_DKIN_2       MFP_CFG_LPM(GPIO107, AF2, FLOAT)
+#define GPIO108_KP_DKIN_3       MFP_CFG_LPM(GPIO108, AF2, FLOAT)
+#define GPIO109_KP_DKIN_4       MFP_CFG_LPM(GPIO109, AF2, FLOAT)
+#define GPIO110_KP_DKIN_5       MFP_CFG_LPM(GPIO110, AF2, FLOAT)
+#define GPIO111_KP_DKIN_6       MFP_CFG_LPM(GPIO111, AF2, FLOAT)
+#define GPIO112_KP_DKIN_7       MFP_CFG_LPM(GPIO112, AF2, FLOAT)
+
+#define GPIO113_KP_DKIN_0       MFP_CFG_LPM(GPIO113, AF2, FLOAT)
+#define GPIO114_KP_DKIN_1       MFP_CFG_LPM(GPIO114, AF2, FLOAT)
+#define GPIO115_KP_DKIN_2       MFP_CFG_LPM(GPIO115, AF2, FLOAT)
+#define GPIO116_KP_DKIN_3       MFP_CFG_LPM(GPIO116, AF2, FLOAT)
+#define GPIO117_KP_DKIN_4       MFP_CFG_LPM(GPIO117, AF2, FLOAT)
+#define GPIO118_KP_DKIN_5       MFP_CFG_LPM(GPIO118, AF2, FLOAT)
+#define GPIO119_KP_DKIN_6       MFP_CFG_LPM(GPIO119, AF2, FLOAT)
+#define GPIO120_KP_DKIN_7       MFP_CFG_LPM(GPIO120, AF2, FLOAT)
+
+#define GPIO127_KP_DKIN_0       MFP_CFG_LPM(GPIO127, AF2, FLOAT)
+#define GPIO126_KP_DKIN_1       MFP_CFG_LPM(GPIO126, AF2, FLOAT)
+
+#define GPIO2_2_KP_DKIN_0       MFP_CFG_LPM(GPIO2_2, AF2, FLOAT)
+#define GPIO3_2_KP_DKIN_1       MFP_CFG_LPM(GPIO3_2, AF2, FLOAT)
+#define GPIO125_KP_DKIN_2       MFP_CFG_LPM(GPIO125, AF2, FLOAT)
+#define GPIO124_KP_DKIN_3       MFP_CFG_LPM(GPIO124, AF2, FLOAT)
+#define GPIO123_KP_DKIN_4       MFP_CFG_LPM(GPIO123, AF2, FLOAT)
+#define GPIO122_KP_DKIN_5       MFP_CFG_LPM(GPIO122, AF2, FLOAT)
+#define GPIO121_KP_DKIN_6       MFP_CFG_LPM(GPIO121, AF2, FLOAT)
+#define GPIO4_2_KP_DKIN_7       MFP_CFG_LPM(GPIO4_2, AF2, FLOAT)
+
+#define GPIO113_KP_MKIN_0       MFP_CFG_LPM(GPIO113, AF1, FLOAT)
+#define GPIO114_KP_MKIN_1       MFP_CFG_LPM(GPIO114, AF1, FLOAT)
+#define GPIO115_KP_MKIN_2       MFP_CFG_LPM(GPIO115, AF1, FLOAT)
+#define GPIO116_KP_MKIN_3       MFP_CFG_LPM(GPIO116, AF1, FLOAT)
+#define GPIO117_KP_MKIN_4       MFP_CFG_LPM(GPIO117, AF1, FLOAT)
+#define GPIO118_KP_MKIN_5       MFP_CFG_LPM(GPIO118, AF1, FLOAT)
+#define GPIO119_KP_MKIN_6       MFP_CFG_LPM(GPIO119, AF1, FLOAT)
+#define GPIO120_KP_MKIN_7       MFP_CFG_LPM(GPIO120, AF1, FLOAT)
+
+#define GPIO83_KP_MKOUT_0       MFP_CFG_LPM(GPIO83, AF2, DRIVE_HIGH)
+#define GPIO84_KP_MKOUT_1       MFP_CFG_LPM(GPIO84, AF2, DRIVE_HIGH)
+#define GPIO85_KP_MKOUT_2       MFP_CFG_LPM(GPIO85, AF2, DRIVE_HIGH)
+#define GPIO86_KP_MKOUT_3       MFP_CFG_LPM(GPIO86, AF2, DRIVE_HIGH)
+#define GPIO13_KP_MKOUT_4       MFP_CFG_LPM(GPIO13, AF3, DRIVE_HIGH)
+#define GPIO14_KP_MKOUT_5       MFP_CFG_LPM(GPIO14, AF3, DRIVE_HIGH)
+
+#define GPIO121_KP_MKOUT_0      MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH)
+#define GPIO122_KP_MKOUT_1      MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH)
+#define GPIO123_KP_MKOUT_2      MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH)
+#define GPIO124_KP_MKOUT_3      MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH)
+#define GPIO125_KP_MKOUT_4      MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH)
+#define GPIO126_KP_MKOUT_5      MFP_CFG_LPM(GPIO126, AF1, DRIVE_HIGH)
+#define GPIO127_KP_MKOUT_6      MFP_CFG_LPM(GPIO127, AF1, DRIVE_HIGH)
+#define GPIO5_2_KP_MKOUT_7      MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH)
+
+/* LCD */
+#define GPIO6_2_LCD_LDD_0       MFP_CFG_DRV(GPIO6_2, AF1, DS01X)
+#define GPIO7_2_LCD_LDD_1       MFP_CFG_DRV(GPIO7_2, AF1, DS01X)
+#define GPIO8_2_LCD_LDD_2       MFP_CFG_DRV(GPIO8_2, AF1, DS01X)
+#define GPIO9_2_LCD_LDD_3       MFP_CFG_DRV(GPIO9_2, AF1, DS01X)
+#define GPIO10_2_LCD_LDD_4      MFP_CFG_DRV(GPIO10_2, AF1, DS01X)
+#define GPIO11_2_LCD_LDD_5      MFP_CFG_DRV(GPIO11_2, AF1, DS01X)
+#define GPIO12_2_LCD_LDD_6      MFP_CFG_DRV(GPIO12_2, AF1, DS01X)
+#define GPIO13_2_LCD_LDD_7      MFP_CFG_DRV(GPIO13_2, AF1, DS01X)
+#define GPIO63_LCD_LDD_8        MFP_CFG_DRV(GPIO63, AF1, DS01X)
+#define GPIO64_LCD_LDD_9        MFP_CFG_DRV(GPIO64, AF1, DS01X)
+#define GPIO65_LCD_LDD_10       MFP_CFG_DRV(GPIO65, AF1, DS01X)
+#define GPIO66_LCD_LDD_11       MFP_CFG_DRV(GPIO66, AF1, DS01X)
+#define GPIO67_LCD_LDD_12       MFP_CFG_DRV(GPIO67, AF1, DS01X)
+#define GPIO68_LCD_LDD_13       MFP_CFG_DRV(GPIO68, AF1, DS01X)
+#define GPIO69_LCD_LDD_14       MFP_CFG_DRV(GPIO69, AF1, DS01X)
+#define GPIO70_LCD_LDD_15       MFP_CFG_DRV(GPIO70, AF1, DS01X)
+#define GPIO71_LCD_LDD_16       MFP_CFG_DRV(GPIO71, AF1, DS01X)
+#define GPIO72_LCD_LDD_17       MFP_CFG_DRV(GPIO72, AF1, DS01X)
+#define GPIO73_LCD_CS_N         MFP_CFG_DRV(GPIO73, AF2, DS01X)
+#define GPIO74_LCD_VSYNC        MFP_CFG_DRV(GPIO74, AF2, DS01X)
+#define GPIO14_2_LCD_FCLK       MFP_CFG_DRV(GPIO14_2, AF1, DS01X)
+#define GPIO15_2_LCD_LCLK       MFP_CFG_DRV(GPIO15_2, AF1, DS01X)
+#define GPIO16_2_LCD_PCLK       MFP_CFG_DRV(GPIO16_2, AF1, DS01X)
+#define GPIO17_2_LCD_BIAS       MFP_CFG_DRV(GPIO17_2, AF1, DS01X)
+#define GPIO64_LCD_VSYNC        MFP_CFG_DRV(GPIO64, AF2, DS01X)
+#define GPIO63_LCD_CS_N         MFP_CFG_DRV(GPIO63, AF2, DS01X)
+
+#define GPIO6_2_MLCD_DD_0       MFP_CFG_DRV(GPIO6_2, AF7, DS08X)
+#define GPIO7_2_MLCD_DD_1       MFP_CFG_DRV(GPIO7_2, AF7, DS08X)
+#define GPIO8_2_MLCD_DD_2       MFP_CFG_DRV(GPIO8_2, AF7, DS08X)
+#define GPIO9_2_MLCD_DD_3       MFP_CFG_DRV(GPIO9_2, AF7, DS08X)
+#define GPIO10_2_MLCD_DD_4      MFP_CFG_DRV(GPIO10_2, AF7, DS08X)
+#define GPIO11_2_MLCD_DD_5      MFP_CFG_DRV(GPIO11_2, AF7, DS08X)
+#define GPIO12_2_MLCD_DD_6      MFP_CFG_DRV(GPIO12_2, AF7, DS08X)
+#define GPIO13_2_MLCD_DD_7      MFP_CFG_DRV(GPIO13_2, AF7, DS08X)
+#define GPIO63_MLCD_DD_8        MFP_CFG_DRV(GPIO63, AF7, DS08X)
+#define GPIO64_MLCD_DD_9        MFP_CFG_DRV(GPIO64, AF7, DS08X)
+#define GPIO65_MLCD_DD_10       MFP_CFG_DRV(GPIO65, AF7, DS08X)
+#define GPIO66_MLCD_DD_11       MFP_CFG_DRV(GPIO66, AF7, DS08X)
+#define GPIO67_MLCD_DD_12       MFP_CFG_DRV(GPIO67, AF7, DS08X)
+#define GPIO68_MLCD_DD_13       MFP_CFG_DRV(GPIO68, AF7, DS08X)
+#define GPIO69_MLCD_DD_14       MFP_CFG_DRV(GPIO69, AF7, DS08X)
+#define GPIO70_MLCD_DD_15       MFP_CFG_DRV(GPIO70, AF7, DS08X)
+#define GPIO71_MLCD_DD_16       MFP_CFG_DRV(GPIO71, AF7, DS08X)
+#define GPIO72_MLCD_DD_17       MFP_CFG_DRV(GPIO72, AF7, DS08X)
+#define GPIO73_MLCD_CS          MFP_CFG_DRV(GPIO73, AF7, DS08X)
+#define GPIO74_MLCD_VSYNC       MFP_CFG_DRV(GPIO74, AF7, DS08X)
+#define GPIO14_2_MLCD_FCLK      MFP_CFG_DRV(GPIO14_2, AF7, DS08X)
+#define GPIO15_2_MLCD_LCLK      MFP_CFG_DRV(GPIO15_2, AF7, DS08X)
+#define GPIO16_2_MLCD_PCLK      MFP_CFG_DRV(GPIO16_2, AF7, DS08X)
+#define GPIO17_2_MLCD_BIAS      MFP_CFG_DRV(GPIO17_2, AF7, DS08X)
+
+/* MMC1 */
+#define GPIO9_MMC1_CMD          MFP_CFG_LPM(GPIO9,  AF4, DRIVE_HIGH)
+#define GPIO22_MMC1_CLK         MFP_CFG_LPM(GPIO22, AF4, DRIVE_HIGH)
+#define GPIO23_MMC1_CMD         MFP_CFG_LPM(GPIO23, AF4, DRIVE_HIGH)
+#define GPIO30_MMC1_CLK         MFP_CFG_LPM(GPIO30, AF4, DRIVE_HIGH)
+#define GPIO31_MMC1_CMD         MFP_CFG_LPM(GPIO31, AF4, DRIVE_HIGH)
+#define GPIO5_MMC1_DAT0         MFP_CFG_LPM(GPIO5,  AF4, DRIVE_HIGH)
+#define GPIO6_MMC1_DAT1         MFP_CFG_LPM(GPIO6,  AF4, DRIVE_HIGH)
+#define GPIO7_MMC1_DAT2         MFP_CFG_LPM(GPIO7,  AF4, DRIVE_HIGH)
+#define GPIO8_MMC1_DAT3         MFP_CFG_LPM(GPIO8,  AF4, DRIVE_HIGH)
+#define GPIO18_MMC1_DAT0        MFP_CFG_LPM(GPIO18, AF4, DRIVE_HIGH)
+#define GPIO19_MMC1_DAT1        MFP_CFG_LPM(GPIO19, AF4, DRIVE_HIGH)
+#define GPIO20_MMC1_DAT2        MFP_CFG_LPM(GPIO20, AF4, DRIVE_HIGH)
+#define GPIO21_MMC1_DAT3        MFP_CFG_LPM(GPIO21, AF4, DRIVE_HIGH)
+
+#define GPIO28_MMC2_CLK         MFP_CFG_LPM(GPIO28, AF4, PULL_HIGH)
+#define GPIO29_MMC2_CMD         MFP_CFG_LPM(GPIO29, AF4, PULL_HIGH)
+#define GPIO30_MMC2_CLK         MFP_CFG_LPM(GPIO30, AF3, PULL_HIGH)
+#define GPIO31_MMC2_CMD         MFP_CFG_LPM(GPIO31, AF3, PULL_HIGH)
+#define GPIO79_MMC2_CLK         MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH)
+#define GPIO80_MMC2_CMD         MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH)
+
+#define GPIO5_MMC2_DAT0         MFP_CFG_LPM(GPIO5, AF2, PULL_HIGH)
+#define GPIO6_MMC2_DAT1         MFP_CFG_LPM(GPIO6, AF2, PULL_HIGH)
+#define GPIO7_MMC2_DAT2         MFP_CFG_LPM(GPIO7, AF2, PULL_HIGH)
+#define GPIO8_MMC2_DAT3         MFP_CFG_LPM(GPIO8, AF2, PULL_HIGH)
+#define GPIO24_MMC2_DAT0        MFP_CFG_LPM(GPIO24, AF4, PULL_HIGH)
+#define GPIO75_MMC2_DAT0        MFP_CFG_LPM(GPIO75, AF4, PULL_HIGH)
+#define GPIO25_MMC2_DAT1        MFP_CFG_LPM(GPIO25, AF4, PULL_HIGH)
+#define GPIO76_MMC2_DAT1        MFP_CFG_LPM(GPIO76, AF4, PULL_HIGH)
+#define GPIO26_MMC2_DAT2        MFP_CFG_LPM(GPIO26, AF4, PULL_HIGH)
+#define GPIO77_MMC2_DAT2        MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH)
+#define GPIO27_MMC2_DAT3        MFP_CFG_LPM(GPIO27, AF4, PULL_HIGH)
+#define GPIO78_MMC2_DAT3        MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH)
+
+/* 1-Wire */
+#define GPIO14_ONE_WIRE         MFP_CFG_LPM(GPIO14,  AF5, FLOAT)
+#define GPIO0_2_ONE_WIRE        MFP_CFG_LPM(GPIO0_2, AF2, FLOAT)
+
+/* SSP1 */
+#define GPIO87_SSP1_EXTCLK      MFP_CFG(GPIO87, AF1)
+#define GPIO88_SSP1_SYSCLK      MFP_CFG(GPIO88, AF1)
+#define GPIO83_SSP1_SCLK        MFP_CFG(GPIO83, AF1)
+#define GPIO84_SSP1_SFRM        MFP_CFG(GPIO84, AF1)
+#define GPIO85_SSP1_RXD         MFP_CFG(GPIO85, AF6)
+#define GPIO85_SSP1_TXD         MFP_CFG(GPIO85, AF1)
+#define GPIO86_SSP1_RXD         MFP_CFG(GPIO86, AF1)
+#define GPIO86_SSP1_TXD         MFP_CFG(GPIO86, AF6)
+
+/* SSP2 */
+#define GPIO39_SSP2_EXTCLK      MFP_CFG(GPIO39, AF2)
+#define GPIO40_SSP2_SYSCLK      MFP_CFG(GPIO40, AF2)
+#define GPIO12_SSP2_SCLK        MFP_CFG(GPIO12, AF2)
+#define GPIO35_SSP2_SCLK        MFP_CFG(GPIO35, AF2)
+#define GPIO36_SSP2_SFRM        MFP_CFG(GPIO36, AF2)
+#define GPIO37_SSP2_RXD         MFP_CFG(GPIO37, AF5)
+#define GPIO37_SSP2_TXD         MFP_CFG(GPIO37, AF2)
+#define GPIO38_SSP2_RXD         MFP_CFG(GPIO38, AF2)
+#define GPIO38_SSP2_TXD         MFP_CFG(GPIO38, AF5)
+
+#define GPIO69_SSP3_SCLK        MFP_CFG(GPIO69, AF2, DS08X, FLOAT)
+#define GPIO70_SSP3_FRM         MFP_CFG(GPIO70, AF2, DS08X, DRIVE_LOW)
+#define GPIO89_SSP3_SCLK        MFP_CFG(GPIO89, AF1, DS08X, FLOAT)
+#define GPIO90_SSP3_FRM         MFP_CFG(GPIO90, AF1, DS08X, DRIVE_LOW)
+#define GPIO71_SSP3_RXD         MFP_CFG_X(GPIO71, AF5, DS08X, FLOAT)
+#define GPIO71_SSP3_TXD         MFP_CFG_X(GPIO71, AF2, DS08X, DRIVE_LOW)
+#define GPIO72_SSP3_RXD         MFP_CFG_X(GPIO72, AF2, DS08X, FLOAT)
+#define GPIO72_SSP3_TXD         MFP_CFG_X(GPIO72, AF5, DS08X, DRIVE_LOW)
+#define GPIO91_SSP3_RXD         MFP_CFG_X(GPIO91, AF5, DS08X, FLOAT)
+#define GPIO91_SSP3_TXD         MFP_CFG_X(GPIO91, AF1, DS08X, DRIVE_LOW)
+#define GPIO92_SSP3_RXD         MFP_CFG_X(GPIO92, AF1, DS08X, FLOAT)
+#define GPIO92_SSP3_TXD         MFP_CFG_X(GPIO92, AF5, DS08X, DRIVE_LOW)
+
+#define GPIO93_SSP4_SCLK        MFP_CFG_LPM(GPIO93, AF1, PULL_HIGH)
+#define GPIO94_SSP4_FRM         MFP_CFG_LPM(GPIO94, AF1, PULL_HIGH)
+#define GPIO94_SSP4_RXD         MFP_CFG_LPM(GPIO94, AF5, PULL_HIGH)
+#define GPIO95_SSP4_RXD         MFP_CFG_LPM(GPIO95, AF5, PULL_HIGH)
+#define GPIO95_SSP4_TXD         MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH)
+#define GPIO96_SSP4_RXD         MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH)
+#define GPIO96_SSP4_TXD         MFP_CFG_LPM(GPIO96, AF5, PULL_HIGH)
+
+/* UART1 */
+#define GPIO41_UART1_RXD        MFP_CFG_LPM(GPIO41, AF2, FLOAT)
+#define GPIO41_UART1_TXD        MFP_CFG_LPM(GPIO41, AF4, FLOAT)
+#define GPIO42_UART1_RXD        MFP_CFG_LPM(GPIO42, AF4, FLOAT)
+#define GPIO42_UART1_TXD        MFP_CFG_LPM(GPIO42, AF2, FLOAT)
+#define GPIO97_UART1_RXD        MFP_CFG_LPM(GPIO97, AF1, FLOAT)
+#define GPIO97_UART1_TXD        MFP_CFG_LPM(GPIO97, AF6, FLOAT)
+#define GPIO98_UART1_RXD        MFP_CFG_LPM(GPIO98, AF6, FLOAT)
+#define GPIO98_UART1_TXD        MFP_CFG_LPM(GPIO98, AF1, FLOAT)
+#define GPIO43_UART1_CTS        MFP_CFG_LPM(GPIO43, AF2, FLOAT)
+#define GPIO43_UART1_RTS        MFP_CFG_LPM(GPIO43, AF4, FLOAT)
+#define GPIO48_UART1_CTS        MFP_CFG_LPM(GPIO48, AF4, FLOAT)
+#define GPIO48_UART1_RTS        MFP_CFG_LPM(GPIO48, AF2, FLOAT)
+#define GPIO99_UART1_CTS        MFP_CFG_LPM(GPIO99, AF1, FLOAT)
+#define GPIO99_UART1_RTS        MFP_CFG_LPM(GPIO99, AF6, FLOAT)
+#define GPIO104_UART1_CTS       MFP_CFG_LPM(GPIO104, AF6, FLOAT)
+#define GPIO104_UART1_RTS       MFP_CFG_LPM(GPIO104, AF1, FLOAT)
+#define GPIO45_UART1_DTR        MFP_CFG_LPM(GPIO45, AF4, FLOAT)
+#define GPIO45_UART1_DSR        MFP_CFG_LPM(GPIO45, AF2, FLOAT)
+#define GPIO47_UART1_DTR        MFP_CFG_LPM(GPIO47, AF2, FLOAT)
+#define GPIO47_UART1_DSR        MFP_CFG_LPM(GPIO47, AF4, FLOAT)
+#define GPIO101_UART1_DTR       MFP_CFG_LPM(GPIO101, AF6, FLOAT)
+#define GPIO101_UART1_DSR       MFP_CFG_LPM(GPIO101, AF1, FLOAT)
+#define GPIO103_UART1_DTR       MFP_CFG_LPM(GPIO103, AF1, FLOAT)
+#define GPIO103_UART1_DSR       MFP_CFG_LPM(GPIO103, AF6, FLOAT)
+#define GPIO44_UART1_DCD        MFP_CFG_LPM(GPIO44, AF2, FLOAT)
+#define GPIO100_UART1_DCD       MFP_CFG_LPM(GPIO100, AF1, FLOAT)
+#define GPIO46_UART1_RI         MFP_CFG_LPM(GPIO46, AF2, FLOAT)
+#define GPIO102_UART1_RI        MFP_CFG_LPM(GPIO102, AF1, FLOAT)
+
+/* UART2 */
+#define GPIO109_UART2_CTS       MFP_CFG_LPM(GPIO109, AF3, FLOAT)
+#define GPIO109_UART2_RTS       MFP_CFG_LPM(GPIO109, AF1, FLOAT)
+#define GPIO112_UART2_CTS       MFP_CFG_LPM(GPIO112, AF1, FLOAT)
+#define GPIO112_UART2_RTS       MFP_CFG_LPM(GPIO112, AF3, FLOAT)
+#define GPIO110_UART2_RXD       MFP_CFG_LPM(GPIO110, AF1, FLOAT)
+#define GPIO110_UART2_TXD       MFP_CFG_LPM(GPIO110, AF3, FLOAT)
+#define GPIO111_UART2_RXD       MFP_CFG_LPM(GPIO111, AF3, FLOAT)
+#define GPIO111_UART2_TXD       MFP_CFG_LPM(GPIO111, AF1, FLOAT)
+
+/* UART3 */
+#define GPIO89_UART3_CTS        MFP_CFG_LPM(GPIO89, AF2, FLOAT)
+#define GPIO89_UART3_RTS        MFP_CFG_LPM(GPIO89, AF4, FLOAT)
+#define GPIO90_UART3_CTS        MFP_CFG_LPM(GPIO90, AF4, FLOAT)
+#define GPIO90_UART3_RTS        MFP_CFG_LPM(GPIO90, AF2, FLOAT)
+#define GPIO105_UART3_CTS       MFP_CFG_LPM(GPIO105, AF1, FLOAT)
+#define GPIO105_UART3_RTS       MFP_CFG_LPM(GPIO105, AF3, FLOAT)
+#define GPIO106_UART3_CTS       MFP_CFG_LPM(GPIO106, AF3, FLOAT)
+#define GPIO106_UART3_RTS       MFP_CFG_LPM(GPIO106, AF1, FLOAT)
+#define GPIO30_UART3_RXD        MFP_CFG_LPM(GPIO30, AF2, FLOAT)
+#define GPIO30_UART3_TXD        MFP_CFG_LPM(GPIO30, AF6, FLOAT)
+#define GPIO31_UART3_RXD        MFP_CFG_LPM(GPIO31, AF6, FLOAT)
+#define GPIO31_UART3_TXD        MFP_CFG_LPM(GPIO31, AF2, FLOAT)
+#define GPIO91_UART3_RXD        MFP_CFG_LPM(GPIO91, AF4, FLOAT)
+#define GPIO91_UART3_TXD        MFP_CFG_LPM(GPIO91, AF2, FLOAT)
+#define GPIO92_UART3_RXD        MFP_CFG_LPM(GPIO92, AF2, FLOAT)
+#define GPIO92_UART3_TXD        MFP_CFG_LPM(GPIO92, AF4, FLOAT)
+#define GPIO107_UART3_RXD       MFP_CFG_LPM(GPIO107, AF3, FLOAT)
+#define GPIO107_UART3_TXD       MFP_CFG_LPM(GPIO107, AF1, FLOAT)
+#define GPIO108_UART3_RXD       MFP_CFG_LPM(GPIO108, AF1, FLOAT)
+#define GPIO108_UART3_TXD       MFP_CFG_LPM(GPIO108, AF3, FLOAT)
+
+
+/* USB 2.0 UTMI */
+#define GPIO10_UTM_CLK          MFP_CFG(GPIO10, AF1)
+#define GPIO36_U2D_RXERROR      MFP_CFG(GPIO36, AF3)
+#define GPIO60_U2D_RXERROR      MFP_CFG(GPIO60, AF1)
+#define GPIO87_U2D_RXERROR      MFP_CFG(GPIO87, AF5)
+#define GPIO34_UTM_RXVALID      MFP_CFG(GPIO34, AF3)
+#define GPIO58_UTM_RXVALID      MFP_CFG(GPIO58, AF2)
+#define GPIO85_UTM_RXVALID      MFP_CFG(GPIO85, AF5)
+#define GPIO35_UTM_RXACTIVE     MFP_CFG(GPIO35, AF3)
+#define GPIO59_UTM_RXACTIVE     MFP_CFG(GPIO59, AF1)
+#define GPIO86_UTM_RXACTIVE     MFP_CFG(GPIO86, AF5)
+#define GPIO73_UTM_TXREADY      MFP_CFG(GPIO73, AF1)
+#define GPIO68_UTM_LINESTATE_0  MFP_CFG(GPIO68, AF3)
+#define GPIO90_UTM_LINESTATE_0  MFP_CFG(GPIO90, AF3)
+#define GPIO102_UTM_LINESTATE_0 MFP_CFG(GPIO102, AF3)
+#define GPIO107_UTM_LINESTATE_0 MFP_CFG(GPIO107, AF4)
+#define GPIO69_UTM_LINESTATE_1  MFP_CFG(GPIO69, AF3)
+#define GPIO91_UTM_LINESTATE_1  MFP_CFG(GPIO91, AF3)
+#define GPIO103_UTM_LINESTATE_1 MFP_CFG(GPIO103, AF3)
+
+#define GPIO41_U2D_PHYDATA_0    MFP_CFG(GPIO41, AF3)
+#define GPIO42_U2D_PHYDATA_1    MFP_CFG(GPIO42, AF3)
+#define GPIO43_U2D_PHYDATA_2    MFP_CFG(GPIO43, AF3)
+#define GPIO44_U2D_PHYDATA_3    MFP_CFG(GPIO44, AF3)
+#define GPIO45_U2D_PHYDATA_4    MFP_CFG(GPIO45, AF3)
+#define GPIO46_U2D_PHYDATA_5    MFP_CFG(GPIO46, AF3)
+#define GPIO47_U2D_PHYDATA_6    MFP_CFG(GPIO47, AF3)
+#define GPIO48_U2D_PHYDATA_7    MFP_CFG(GPIO48, AF3)
+
+#define GPIO49_U2D_PHYDATA_0    MFP_CFG(GPIO49, AF3)
+#define GPIO50_U2D_PHYDATA_1    MFP_CFG(GPIO50, AF3)
+#define GPIO51_U2D_PHYDATA_2    MFP_CFG(GPIO51, AF3)
+#define GPIO52_U2D_PHYDATA_3    MFP_CFG(GPIO52, AF3)
+#define GPIO53_U2D_PHYDATA_4    MFP_CFG(GPIO53, AF3)
+#define GPIO54_U2D_PHYDATA_5    MFP_CFG(GPIO54, AF3)
+#define GPIO55_U2D_PHYDATA_6    MFP_CFG(GPIO55, AF3)
+#define GPIO56_U2D_PHYDATA_7    MFP_CFG(GPIO56, AF3)
+
+#define GPIO37_U2D_OPMODE0      MFP_CFG(GPIO37, AF4)
+#define GPIO61_U2D_OPMODE0      MFP_CFG(GPIO61, AF2)
+#define GPIO88_U2D_OPMODE0      MFP_CFG(GPIO88, AF7)
+
+#define GPIO38_U2D_OPMODE1      MFP_CFG(GPIO38, AF4)
+#define GPIO62_U2D_OPMODE1      MFP_CFG(GPIO62, AF2)
+#define GPIO104_U2D_OPMODE1     MFP_CFG(GPIO104, AF4)
+#define GPIO108_U2D_OPMODE1     MFP_CFG(GPIO108, AF5)
+
+#define GPIO74_U2D_RESET        MFP_CFG(GPIO74, AF1)
+#define GPIO93_U2D_RESET        MFP_CFG(GPIO93, AF2)
+#define GPIO98_U2D_RESET        MFP_CFG(GPIO98, AF3)
+
+#define GPIO67_U2D_SUSPEND      MFP_CFG(GPIO67, AF3)
+#define GPIO96_U2D_SUSPEND      MFP_CFG(GPIO96, AF2)
+#define GPIO101_U2D_SUSPEND     MFP_CFG(GPIO101, AF3)
+
+#define GPIO66_U2D_TERM_SEL     MFP_CFG(GPIO66, AF5)
+#define GPIO95_U2D_TERM_SEL     MFP_CFG(GPIO95, AF3)
+#define GPIO97_U2D_TERM_SEL     MFP_CFG(GPIO97, AF7)
+#define GPIO100_U2D_TERM_SEL    MFP_CFG(GPIO100, AF5)
+
+#define GPIO39_U2D_TXVALID      MFP_CFG(GPIO39, AF4)
+#define GPIO70_U2D_TXVALID      MFP_CFG(GPIO70, AF5)
+#define GPIO83_U2D_TXVALID      MFP_CFG(GPIO83, AF7)
+
+#define GPIO65_U2D_XCVR_SEL     MFP_CFG(GPIO65, AF5)
+#define GPIO94_U2D_XCVR_SEL     MFP_CFG(GPIO94, AF3)
+#define GPIO99_U2D_XCVR_SEL     MFP_CFG(GPIO99, AF5)
+
+/* USB Host 1.1 */
+#define GPIO2_2_USBH_PEN        MFP_CFG(GPIO2_2, AF1)
+#define GPIO3_2_USBH_PWR        MFP_CFG(GPIO3_2, AF1)
+
+/* USB P2 */
+#define GPIO97_USB_P2_2         MFP_CFG(GPIO97, AF2)
+#define GPIO97_USB_P2_6         MFP_CFG(GPIO97, AF4)
+#define GPIO98_USB_P2_2         MFP_CFG(GPIO98, AF4)
+#define GPIO98_USB_P2_6         MFP_CFG(GPIO98, AF2)
+#define GPIO99_USB_P2_1         MFP_CFG(GPIO99, AF2)
+#define GPIO100_USB_P2_4        MFP_CFG(GPIO100, AF2)
+#define GPIO101_USB_P2_8        MFP_CFG(GPIO101, AF2)
+#define GPIO102_USB_P2_3        MFP_CFG(GPIO102, AF2)
+#define GPIO103_USB_P2_5        MFP_CFG(GPIO103, AF2)
+#define GPIO104_USB_P2_7        MFP_CFG(GPIO104, AF2)
+
+/* USB P3 */
+#define GPIO75_USB_P3_1         MFP_CFG(GPIO75, AF2)
+#define GPIO76_USB_P3_2         MFP_CFG(GPIO76, AF2)
+#define GPIO77_USB_P3_3         MFP_CFG(GPIO77, AF2)
+#define GPIO78_USB_P3_4         MFP_CFG(GPIO78, AF2)
+#define GPIO79_USB_P3_5         MFP_CFG(GPIO79, AF2)
+#define GPIO80_USB_P3_6         MFP_CFG(GPIO80, AF2)
+
+#define GPIO13_CHOUT0           MFP_CFG(GPIO13, AF6)
+#define GPIO14_CHOUT1           MFP_CFG(GPIO14, AF6)
+
+#define GPIO2_RDY               MFP_CFG(GPIO2, AF1)
+#define GPIO5_NPIOR             MFP_CFG(GPIO5, AF3)
+
+#define GPIO11_PWM0_OUT         MFP_CFG(GPIO11, AF1)
+#define GPIO12_PWM1_OUT         MFP_CFG(GPIO12, AF1)
+#define GPIO13_PWM2_OUT         MFP_CFG(GPIO13, AF1)
+#define GPIO14_PWM3_OUT         MFP_CFG(GPIO14, AF1)
+
+#endif /* __ASM_ARCH_MFP_PXA320_H */
diff --git a/include/asm-arm/arch-pxa/mfp-pxa3xx.h b/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h
index 1f6b35c015d0..1f6b35c015d0 100644
--- a/include/asm-arm/arch-pxa/mfp-pxa3xx.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h
new file mode 100644
index 000000000000..fabd9b4df827
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h
@@ -0,0 +1,491 @@
+/*
+ * arch/arm/mach-pxa/include/mach/mfp-pxa930.h
+ *
+ * PXA930 specific MFP configuration definitions
+ *
+ * Copyright (C) 2007-2008 Marvell International Ltd.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MFP_PXA9xx_H
+#define __ASM_ARCH_MFP_PXA9xx_H
+
+#include <mach/mfp.h>
+#include <mach/mfp-pxa3xx.h>
+
+/* GPIO */
+#define GPIO46_GPIO             MFP_CFG(GPIO46, AF0)
+#define GPIO49_GPIO             MFP_CFG(GPIO49, AF0)
+#define GPIO50_GPIO             MFP_CFG(GPIO50, AF0)
+#define GPIO51_GPIO             MFP_CFG(GPIO51, AF0)
+#define GPIO52_GPIO             MFP_CFG(GPIO52, AF0)
+#define GPIO56_GPIO             MFP_CFG(GPIO56, AF0)
+#define GPIO58_GPIO             MFP_CFG(GPIO58, AF0)
+#define GPIO59_GPIO             MFP_CFG(GPIO59, AF0)
+#define GPIO60_GPIO             MFP_CFG(GPIO60, AF0)
+#define GPIO61_GPIO             MFP_CFG(GPIO61, AF0)
+#define GPIO62_GPIO             MFP_CFG(GPIO62, AF0)
+
+#define GSIM_UCLK_GPIO_79       MFP_CFG(GSIM_UCLK, AF0)
+#define GSIM_UIO_GPIO_80        MFP_CFG(GSIM_UIO, AF0)
+#define GSIM_nURST_GPIO_81      MFP_CFG(GSIM_nURST, AF0)
+#define GSIM_UDET_GPIO_82       MFP_CFG(GSIM_UDET, AF0)
+
+#define DF_IO15_GPIO_28         MFP_CFG(DF_IO15, AF0)
+#define DF_IO14_GPIO_29         MFP_CFG(DF_IO14, AF0)
+#define DF_IO13_GPIO_30         MFP_CFG(DF_IO13, AF0)
+#define DF_IO12_GPIO_31         MFP_CFG(DF_IO12, AF0)
+#define DF_IO11_GPIO_32         MFP_CFG(DF_IO11, AF0)
+#define DF_IO10_GPIO_33         MFP_CFG(DF_IO10, AF0)
+#define DF_IO9_GPIO_34          MFP_CFG(DF_IO9, AF0)
+#define DF_IO8_GPIO_35          MFP_CFG(DF_IO8, AF0)
+#define DF_IO7_GPIO_36          MFP_CFG(DF_IO7, AF0)
+#define DF_IO6_GPIO_37          MFP_CFG(DF_IO6, AF0)
+#define DF_IO5_GPIO_38          MFP_CFG(DF_IO5, AF0)
+#define DF_IO4_GPIO_39          MFP_CFG(DF_IO4, AF0)
+#define DF_IO3_GPIO_40          MFP_CFG(DF_IO3, AF0)
+#define DF_IO2_GPIO_41          MFP_CFG(DF_IO2, AF0)
+#define DF_IO1_GPIO_42          MFP_CFG(DF_IO1, AF0)
+#define DF_IO0_GPIO_43          MFP_CFG(DF_IO0, AF0)
+#define DF_nCS0_GPIO_44         MFP_CFG(DF_nCS0, AF0)
+#define DF_nCS1_GPIO_45         MFP_CFG(DF_nCS1, AF0)
+#define DF_nWE_GPIO_46          MFP_CFG(DF_nWE, AF0)
+#define DF_nRE_nOE_GPIO_47      MFP_CFG(DF_nRE_nOE, AF0)
+#define DF_CLE_nOE_GPIO_48      MFP_CFG(DF_CLE_nOE, AF0)
+#define DF_nADV1_ALE_GPIO_49    MFP_CFG(DF_nADV1_ALE, AF0)
+#define DF_nADV2_ALE_GPIO_50    MFP_CFG(DF_nADV2_ALE, AF0)
+#define DF_INT_RnB_GPIO_51      MFP_CFG(DF_INT_RnB, AF0)
+#define DF_SCLK_E_GPIO_52       MFP_CFG(DF_SCLK_E, AF0)
+
+#define DF_ADDR0_GPIO_53        MFP_CFG(DF_ADDR0, AF0)
+#define DF_ADDR1_GPIO_54        MFP_CFG(DF_ADDR1, AF0)
+#define DF_ADDR2_GPIO_55        MFP_CFG(DF_ADDR2, AF0)
+#define DF_ADDR3_GPIO_56        MFP_CFG(DF_ADDR3, AF0)
+#define nXCVREN_GPIO_57         MFP_CFG(nXCVREN, AF0)
+#define nLUA_GPIO_58            MFP_CFG(nLUA, AF0)
+#define nLLA_GPIO_59            MFP_CFG(nLLA, AF0)
+#define nBE0_GPIO_60            MFP_CFG(nBE0, AF0)
+#define nBE1_GPIO_61            MFP_CFG(nBE1, AF0)
+#define RDY_GPIO_62             MFP_CFG(RDY, AF0)
+
+/* Chip Select */
+#define DF_nCS0_nCS2            MFP_CFG_LPM(DF_nCS0, AF3, PULL_HIGH)
+#define DF_nCS1_nCS3            MFP_CFG_LPM(DF_nCS1, AF3, PULL_HIGH)
+
+/* AC97 */
+#define GPIO83_BAC97_SYSCLK     MFP_CFG(GPIO83, AF3)
+#define GPIO84_BAC97_SDATA_IN0  MFP_CFG(GPIO84, AF3)
+#define GPIO85_BAC97_BITCLK     MFP_CFG(GPIO85, AF3)
+#define GPIO86_BAC97_nRESET     MFP_CFG(GPIO86, AF3)
+#define GPIO87_BAC97_SYNC       MFP_CFG(GPIO87, AF3)
+#define GPIO88_BAC97_SDATA_OUT  MFP_CFG(GPIO88, AF3)
+
+/* I2C */
+#define GPIO39_CI2C_SCL         MFP_CFG_LPM(GPIO39, AF3, PULL_HIGH)
+#define GPIO40_CI2C_SDA         MFP_CFG_LPM(GPIO40, AF3, PULL_HIGH)
+
+#define GPIO51_CI2C_SCL         MFP_CFG_LPM(GPIO51, AF3, PULL_HIGH)
+#define GPIO52_CI2C_SDA         MFP_CFG_LPM(GPIO52, AF3, PULL_HIGH)
+
+#define GPIO63_CI2C_SCL         MFP_CFG_LPM(GPIO63, AF4, PULL_HIGH)
+#define GPIO64_CI2C_SDA         MFP_CFG_LPM(GPIO64, AF4, PULL_HIGH)
+
+#define GPIO77_CI2C_SCL         MFP_CFG_LPM(GPIO77, AF2, PULL_HIGH)
+#define GPIO78_CI2C_SDA         MFP_CFG_LPM(GPIO78, AF2, PULL_HIGH)
+
+#define GPIO89_CI2C_SCL         MFP_CFG_LPM(GPIO89, AF1, PULL_HIGH)
+#define GPIO90_CI2C_SDA         MFP_CFG_LPM(GPIO90, AF1, PULL_HIGH)
+
+#define GPIO95_CI2C_SCL         MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH)
+#define GPIO96_CI2C_SDA         MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH)
+
+#define GPIO97_CI2C_SCL         MFP_CFG_LPM(GPIO97, AF3, PULL_HIGH)
+#define GPIO98_CI2C_SDA         MFP_CFG_LPM(GPIO98, AF3, PULL_HIGH)
+
+/* QCI */
+#define GPIO63_CI_DD_9          MFP_CFG_LPM(GPIO63, AF1, PULL_LOW)
+#define GPIO64_CI_DD_8          MFP_CFG_LPM(GPIO64, AF1, PULL_LOW)
+#define GPIO65_CI_DD_7          MFP_CFG_LPM(GPIO65, AF1, PULL_LOW)
+#define GPIO66_CI_DD_6          MFP_CFG_LPM(GPIO66, AF1, PULL_LOW)
+#define GPIO67_CI_DD_5          MFP_CFG_LPM(GPIO67, AF1, PULL_LOW)
+#define GPIO68_CI_DD_4          MFP_CFG_LPM(GPIO68, AF1, PULL_LOW)
+#define GPIO69_CI_DD_3          MFP_CFG_LPM(GPIO69, AF1, PULL_LOW)
+#define GPIO70_CI_DD_2          MFP_CFG_LPM(GPIO70, AF1, PULL_LOW)
+#define GPIO71_CI_DD_1          MFP_CFG_LPM(GPIO71, AF1, PULL_LOW)
+#define GPIO72_CI_DD_0          MFP_CFG_LPM(GPIO72, AF1, PULL_LOW)
+#define GPIO73_CI_HSYNC         MFP_CFG_LPM(GPIO73, AF1, PULL_LOW)
+#define GPIO74_CI_VSYNC         MFP_CFG_LPM(GPIO74, AF1, PULL_LOW)
+#define GPIO75_CI_MCLK          MFP_CFG_LPM(GPIO75, AF1, PULL_LOW)
+#define GPIO76_CI_PCLK          MFP_CFG_LPM(GPIO76, AF1, PULL_LOW)
+
+/* KEYPAD */
+#define GPIO4_KP_DKIN_4         MFP_CFG_LPM(GPIO4, AF3, FLOAT)
+#define GPIO5_KP_DKIN_5         MFP_CFG_LPM(GPIO5, AF3, FLOAT)
+#define GPIO6_KP_DKIN_6         MFP_CFG_LPM(GPIO6, AF3, FLOAT)
+#define GPIO7_KP_DKIN_7         MFP_CFG_LPM(GPIO7, AF3, FLOAT)
+#define GPIO8_KP_DKIN_4         MFP_CFG_LPM(GPIO8, AF3, FLOAT)
+#define GPIO9_KP_DKIN_5         MFP_CFG_LPM(GPIO9, AF3, FLOAT)
+#define GPIO10_KP_DKIN_6        MFP_CFG_LPM(GPIO10, AF3, FLOAT)
+#define GPIO11_KP_DKIN_7        MFP_CFG_LPM(GPIO11, AF3, FLOAT)
+
+#define GPIO12_KP_DKIN_0        MFP_CFG_LPM(GPIO12, AF2, FLOAT)
+#define GPIO13_KP_DKIN_1        MFP_CFG_LPM(GPIO13, AF2, FLOAT)
+#define GPIO14_KP_DKIN_2        MFP_CFG_LPM(GPIO14, AF2, FLOAT)
+#define GPIO15_KP_DKIN_3        MFP_CFG_LPM(GPIO15, AF2, FLOAT)
+
+#define GPIO41_KP_DKIN_0        MFP_CFG_LPM(GPIO41, AF2, FLOAT)
+#define GPIO42_KP_DKIN_1        MFP_CFG_LPM(GPIO42, AF2, FLOAT)
+#define GPIO43_KP_DKIN_2        MFP_CFG_LPM(GPIO43, AF2, FLOAT)
+#define GPIO44_KP_DKIN_3        MFP_CFG_LPM(GPIO44, AF2, FLOAT)
+#define GPIO41_KP_DKIN_4        MFP_CFG_LPM(GPIO41, AF4, FLOAT)
+#define GPIO42_KP_DKIN_5        MFP_CFG_LPM(GPIO42, AF4, FLOAT)
+
+#define GPIO0_KP_MKIN_0         MFP_CFG_LPM(GPIO0, AF1, FLOAT)
+#define GPIO2_KP_MKIN_1         MFP_CFG_LPM(GPIO2, AF1, FLOAT)
+#define GPIO4_KP_MKIN_2         MFP_CFG_LPM(GPIO4, AF1, FLOAT)
+#define GPIO6_KP_MKIN_3         MFP_CFG_LPM(GPIO6, AF1, FLOAT)
+#define GPIO8_KP_MKIN_4         MFP_CFG_LPM(GPIO8, AF1, FLOAT)
+#define GPIO10_KP_MKIN_5        MFP_CFG_LPM(GPIO10, AF1, FLOAT)
+#define GPIO12_KP_MKIN_6        MFP_CFG_LPM(GPIO12, AF1, FLOAT)
+#define GPIO14_KP_MKIN_7        MFP_CFG(GPIO14, AF1)
+#define GPIO35_KP_MKIN_5        MFP_CFG(GPIO35, AF4)
+
+#define GPIO1_KP_MKOUT_0        MFP_CFG_LPM(GPIO1, AF1, DRIVE_HIGH)
+#define GPIO3_KP_MKOUT_1        MFP_CFG_LPM(GPIO3, AF1, DRIVE_HIGH)
+#define GPIO5_KP_MKOUT_2        MFP_CFG_LPM(GPIO5, AF1, DRIVE_HIGH)
+#define GPIO7_KP_MKOUT_3        MFP_CFG_LPM(GPIO7, AF1, DRIVE_HIGH)
+#define GPIO9_KP_MKOUT_4        MFP_CFG_LPM(GPIO9, AF1, DRIVE_HIGH)
+#define GPIO11_KP_MKOUT_5       MFP_CFG_LPM(GPIO11, AF1, DRIVE_HIGH)
+#define GPIO13_KP_MKOUT_6       MFP_CFG_LPM(GPIO13, AF1, DRIVE_HIGH)
+#define GPIO15_KP_MKOUT_7       MFP_CFG_LPM(GPIO15, AF1, DRIVE_HIGH)
+#define GPIO36_KP_MKOUT_5       MFP_CFG_LPM(GPIO36, AF4, DRIVE_HIGH)
+
+/* LCD */
+#define GPIO17_LCD_FCLK_RD      MFP_CFG(GPIO17, AF1)
+#define GPIO18_LCD_LCLK_A0      MFP_CFG(GPIO18, AF1)
+#define GPIO19_LCD_PCLK_WR      MFP_CFG(GPIO19, AF1)
+#define GPIO20_LCD_BIAS         MFP_CFG(GPIO20, AF1)
+#define GPIO21_LCD_CS           MFP_CFG(GPIO21, AF1)
+#define GPIO22_LCD_CS2          MFP_CFG(GPIO22, AF2)
+#define GPIO22_LCD_VSYNC        MFP_CFG(GPIO22, AF1)
+#define GPIO23_LCD_DD0          MFP_CFG(GPIO23, AF1)
+#define GPIO24_LCD_DD1          MFP_CFG(GPIO24, AF1)
+#define GPIO25_LCD_DD2          MFP_CFG(GPIO25, AF1)
+#define GPIO26_LCD_DD3          MFP_CFG(GPIO26, AF1)
+#define GPIO27_LCD_DD4          MFP_CFG(GPIO27, AF1)
+#define GPIO28_LCD_DD5          MFP_CFG(GPIO28, AF1)
+#define GPIO29_LCD_DD6          MFP_CFG(GPIO29, AF1)
+#define GPIO30_LCD_DD7          MFP_CFG(GPIO30, AF1)
+#define GPIO31_LCD_DD8          MFP_CFG(GPIO31, AF1)
+#define GPIO32_LCD_DD9          MFP_CFG(GPIO32, AF1)
+#define GPIO33_LCD_DD10         MFP_CFG(GPIO33, AF1)
+#define GPIO34_LCD_DD11         MFP_CFG(GPIO34, AF1)
+#define GPIO35_LCD_DD12         MFP_CFG(GPIO35, AF1)
+#define GPIO36_LCD_DD13         MFP_CFG(GPIO36, AF1)
+#define GPIO37_LCD_DD14         MFP_CFG(GPIO37, AF1)
+#define GPIO38_LCD_DD15         MFP_CFG(GPIO38, AF1)
+#define GPIO39_LCD_DD16         MFP_CFG(GPIO39, AF1)
+#define GPIO40_LCD_DD17         MFP_CFG(GPIO40, AF1)
+#define GPIO41_LCD_CS2          MFP_CFG(GPIO41, AF3)
+#define GPIO42_LCD_VSYNC2       MFP_CFG(GPIO42, AF3)
+#define GPIO44_LCD_DD7          MFP_CFG(GPIO44, AF1)
+
+/* Mini-LCD */
+#define GPIO17_MLCD_FCLK        MFP_CFG(GPIO17, AF3)
+#define GPIO18_MLCD_LCLK        MFP_CFG(GPIO18, AF3)
+#define GPIO19_MLCD_PCLK        MFP_CFG(GPIO19, AF3)
+#define GPIO20_MLCD_BIAS        MFP_CFG(GPIO20, AF3)
+#define GPIO23_MLCD_DD0         MFP_CFG(GPIO23, AF3)
+#define GPIO24_MLCD_DD1         MFP_CFG(GPIO24, AF3)
+#define GPIO25_MLCD_DD2         MFP_CFG(GPIO25, AF3)
+#define GPIO26_MLCD_DD3         MFP_CFG(GPIO26, AF3)
+#define GPIO27_MLCD_DD4         MFP_CFG(GPIO27, AF3)
+#define GPIO28_MLCD_DD5         MFP_CFG(GPIO28, AF3)
+#define GPIO29_MLCD_DD6         MFP_CFG(GPIO29, AF3)
+#define GPIO30_MLCD_DD7         MFP_CFG(GPIO30, AF3)
+#define GPIO31_MLCD_DD8         MFP_CFG(GPIO31, AF3)
+#define GPIO32_MLCD_DD9         MFP_CFG(GPIO32, AF3)
+#define GPIO33_MLCD_DD10        MFP_CFG(GPIO33, AF3)
+#define GPIO34_MLCD_DD11        MFP_CFG(GPIO34, AF3)
+#define GPIO35_MLCD_DD12        MFP_CFG(GPIO35, AF3)
+#define GPIO36_MLCD_DD13        MFP_CFG(GPIO36, AF3)
+#define GPIO37_MLCD_DD14        MFP_CFG(GPIO37, AF3)
+#define GPIO38_MLCD_DD15        MFP_CFG(GPIO38, AF3)
+#define GPIO44_MLCD_DD7         MFP_CFG(GPIO44, AF5)
+
+/* MMC1 */
+#define GPIO10_MMC1_DAT3        MFP_CFG(GPIO10, AF4)
+#define GPIO11_MMC1_DAT2        MFP_CFG(GPIO11, AF4)
+#define GPIO12_MMC1_DAT1        MFP_CFG(GPIO12, AF4)
+#define GPIO13_MMC1_DAT0        MFP_CFG(GPIO13, AF4)
+#define GPIO14_MMC1_CMD         MFP_CFG(GPIO14, AF4)
+#define GPIO15_MMC1_CLK         MFP_CFG(GPIO15, AF4)
+#define GPIO55_MMC1_CMD         MFP_CFG(GPIO55, AF3)
+#define GPIO56_MMC1_CLK         MFP_CFG(GPIO56, AF3)
+#define GPIO57_MMC1_DAT0        MFP_CFG(GPIO57, AF3)
+#define GPIO58_MMC1_DAT1        MFP_CFG(GPIO58, AF3)
+#define GPIO59_MMC1_DAT2        MFP_CFG(GPIO59, AF3)
+#define GPIO60_MMC1_DAT3        MFP_CFG(GPIO60, AF3)
+
+#define DF_ADDR0_MMC1_CLK       MFP_CFG(DF_ADDR0, AF2)
+#define DF_ADDR1_MMC1_CMD       MFP_CFG(DF_ADDR1, AF2)
+#define DF_ADDR2_MMC1_DAT0      MFP_CFG(DF_ADDR2, AF2)
+#define DF_ADDR3_MMC1_DAT1      MFP_CFG(DF_ADDR3, AF3)
+#define nXCVREN_MMC1_DAT2       MFP_CFG(nXCVREN, AF2)
+
+/* MMC2 */
+#define GPIO31_MMC2_CMD         MFP_CFG(GPIO31, AF7)
+#define GPIO32_MMC2_CLK         MFP_CFG(GPIO32, AF7)
+#define GPIO33_MMC2_DAT0        MFP_CFG(GPIO33, AF7)
+#define GPIO34_MMC2_DAT1        MFP_CFG(GPIO34, AF7)
+#define GPIO35_MMC2_DAT2        MFP_CFG(GPIO35, AF7)
+#define GPIO36_MMC2_DAT3        MFP_CFG(GPIO36, AF7)
+
+#define GPIO101_MMC2_DAT3       MFP_CFG(GPIO101, AF1)
+#define GPIO102_MMC2_DAT2       MFP_CFG(GPIO102, AF1)
+#define GPIO103_MMC2_DAT1       MFP_CFG(GPIO103, AF1)
+#define GPIO104_MMC2_DAT0       MFP_CFG(GPIO104, AF1)
+#define GPIO105_MMC2_CMD        MFP_CFG(GPIO105, AF1)
+#define GPIO106_MMC2_CLK        MFP_CFG(GPIO106, AF1)
+
+#define DF_IO10_MMC2_DAT3       MFP_CFG(DF_IO10, AF3)
+#define DF_IO11_MMC2_DAT2       MFP_CFG(DF_IO11, AF3)
+#define DF_IO12_MMC2_DAT1       MFP_CFG(DF_IO12, AF3)
+#define DF_IO13_MMC2_DAT0       MFP_CFG(DF_IO13, AF3)
+#define DF_IO14_MMC2_CLK        MFP_CFG(DF_IO14, AF3)
+#define DF_IO15_MMC2_CMD        MFP_CFG(DF_IO15, AF3)
+
+/* BSSP1 */
+#define GPIO12_BSSP1_CLK        MFP_CFG(GPIO12, AF3)
+#define GPIO13_BSSP1_FRM        MFP_CFG(GPIO13, AF3)
+#define GPIO14_BSSP1_RXD        MFP_CFG(GPIO14, AF3)
+#define GPIO15_BSSP1_TXD        MFP_CFG(GPIO15, AF3)
+#define GPIO97_BSSP1_CLK        MFP_CFG(GPIO97, AF5)
+#define GPIO98_BSSP1_FRM        MFP_CFG(GPIO98, AF5)
+
+/* BSSP2 */
+#define GPIO84_BSSP2_SDATA_IN   MFP_CFG(GPIO84, AF1)
+#define GPIO85_BSSP2_BITCLK     MFP_CFG(GPIO85, AF1)
+#define GPIO86_BSSP2_SYSCLK     MFP_CFG(GPIO86, AF1)
+#define GPIO87_BSSP2_SYNC       MFP_CFG(GPIO87, AF1)
+#define GPIO88_BSSP2_DATA_OUT   MFP_CFG(GPIO88, AF1)
+#define GPIO86_BSSP2_SDATA_IN   MFP_CFG(GPIO86, AF4)
+
+/* BSSP3 */
+#define GPIO79_BSSP3_CLK        MFP_CFG(GPIO79, AF1)
+#define GPIO80_BSSP3_FRM        MFP_CFG(GPIO80, AF1)
+#define GPIO81_BSSP3_TXD        MFP_CFG(GPIO81, AF1)
+#define GPIO82_BSSP3_RXD        MFP_CFG(GPIO82, AF1)
+#define GPIO83_BSSP3_SYSCLK     MFP_CFG(GPIO83, AF1)
+
+/* BSSP4 */
+#define GPIO43_BSSP4_CLK        MFP_CFG(GPIO43, AF4)
+#define GPIO44_BSSP4_FRM        MFP_CFG(GPIO44, AF4)
+#define GPIO45_BSSP4_TXD        MFP_CFG(GPIO45, AF4)
+#define GPIO46_BSSP4_RXD        MFP_CFG(GPIO46, AF4)
+
+#define GPIO51_BSSP4_CLK        MFP_CFG(GPIO51, AF4)
+#define GPIO52_BSSP4_FRM        MFP_CFG(GPIO52, AF4)
+#define GPIO53_BSSP4_TXD        MFP_CFG(GPIO53, AF4)
+#define GPIO54_BSSP4_RXD        MFP_CFG(GPIO54, AF4)
+
+/* GSSP1 */
+#define GPIO79_GSSP1_CLK        MFP_CFG(GPIO79, AF2)
+#define GPIO80_GSSP1_FRM        MFP_CFG(GPIO80, AF2)
+#define GPIO81_GSSP1_TXD        MFP_CFG(GPIO81, AF2)
+#define GPIO82_GSSP1_RXD        MFP_CFG(GPIO82, AF2)
+#define GPIO83_GSSP1_SYSCLK     MFP_CFG(GPIO83, AF2)
+
+#define GPIO93_GSSP1_CLK        MFP_CFG(GPIO93, AF4)
+#define GPIO94_GSSP1_FRM        MFP_CFG(GPIO94, AF4)
+#define GPIO95_GSSP1_TXD        MFP_CFG(GPIO95, AF4)
+#define GPIO96_GSSP1_RXD        MFP_CFG(GPIO96, AF4)
+
+/* GSSP2 */
+#define GPIO47_GSSP2_CLK        MFP_CFG(GPIO47, AF4)
+#define GPIO48_GSSP2_FRM        MFP_CFG(GPIO48, AF4)
+#define GPIO49_GSSP2_RXD        MFP_CFG(GPIO49, AF4)
+#define GPIO50_GSSP2_TXD        MFP_CFG(GPIO50, AF4)
+
+#define GPIO69_GSSP2_CLK        MFP_CFG(GPIO69, AF4)
+#define GPIO70_GSSP2_FRM        MFP_CFG(GPIO70, AF4)
+#define GPIO71_GSSP2_RXD        MFP_CFG(GPIO71, AF4)
+#define GPIO72_GSSP2_TXD        MFP_CFG(GPIO72, AF4)
+
+#define GPIO84_GSSP2_RXD        MFP_CFG(GPIO84, AF2)
+#define GPIO85_GSSP2_CLK        MFP_CFG(GPIO85, AF2)
+#define GPIO86_GSSP2_SYSCLK     MFP_CFG(GPIO86, AF2)
+#define GPIO87_GSSP2_FRM        MFP_CFG(GPIO87, AF2)
+#define GPIO88_GSSP2_TXD        MFP_CFG(GPIO88, AF2)
+#define GPIO86_GSSP2_RXD        MFP_CFG(GPIO86, AF5)
+
+#define GPIO103_GSSP2_CLK       MFP_CFG(GPIO103, AF2)
+#define GPIO104_GSSP2_FRM       MFP_CFG(GPIO104, AF2)
+#define GPIO105_GSSP2_RXD       MFP_CFG(GPIO105, AF2)
+#define GPIO106_GSSP2_TXD       MFP_CFG(GPIO106, AF2)
+
+/* UART1 - FFUART */
+#define GPIO47_UART1_DSR_N      MFP_CFG(GPIO47, AF1)
+#define GPIO48_UART1_DTR_N      MFP_CFG(GPIO48, AF1)
+#define GPIO49_UART1_RI         MFP_CFG(GPIO49, AF1)
+#define GPIO50_UART1_DCD        MFP_CFG(GPIO50, AF1)
+#define GPIO51_UART1_CTS        MFP_CFG(GPIO51, AF1)
+#define GPIO52_UART1_RTS        MFP_CFG(GPIO52, AF1)
+#define GPIO53_UART1_RXD        MFP_CFG(GPIO53, AF1)
+#define GPIO54_UART1_TXD        MFP_CFG(GPIO54, AF1)
+
+#define GPIO63_UART1_TXD        MFP_CFG(GPIO63, AF2)
+#define GPIO64_UART1_RXD        MFP_CFG(GPIO64, AF2)
+#define GPIO65_UART1_DSR        MFP_CFG(GPIO65, AF2)
+#define GPIO66_UART1_DTR        MFP_CFG(GPIO66, AF2)
+#define GPIO67_UART1_RI         MFP_CFG(GPIO67, AF2)
+#define GPIO68_UART1_DCD        MFP_CFG(GPIO68, AF2)
+#define GPIO69_UART1_CTS        MFP_CFG(GPIO69, AF2)
+#define GPIO70_UART1_RTS        MFP_CFG(GPIO70, AF2)
+
+/* UART2 - BTUART */
+#define GPIO91_UART2_RXD        MFP_CFG(GPIO91, AF1)
+#define GPIO92_UART2_TXD        MFP_CFG(GPIO92, AF1)
+#define GPIO93_UART2_CTS        MFP_CFG(GPIO93, AF1)
+#define GPIO94_UART2_RTS        MFP_CFG(GPIO94, AF1)
+
+/* UART3 - STUART */
+#define GPIO43_UART3_RTS        MFP_CFG(GPIO43, AF3)
+#define GPIO44_UART3_CTS        MFP_CFG(GPIO44, AF3)
+#define GPIO45_UART3_RXD        MFP_CFG(GPIO45, AF3)
+#define GPIO46_UART3_TXD        MFP_CFG(GPIO46, AF3)
+
+#define GPIO75_UART3_RTS        MFP_CFG(GPIO75, AF5)
+#define GPIO76_UART3_CTS        MFP_CFG(GPIO76, AF5)
+#define GPIO77_UART3_TXD        MFP_CFG(GPIO77, AF5)
+#define GPIO78_UART3_RXD        MFP_CFG(GPIO78, AF5)
+
+/* DFI */
+#define DF_IO0_DF_IO0           MFP_CFG(DF_IO0, AF2)
+#define DF_IO1_DF_IO1           MFP_CFG(DF_IO1, AF2)
+#define DF_IO2_DF_IO2           MFP_CFG(DF_IO2, AF2)
+#define DF_IO3_DF_IO3           MFP_CFG(DF_IO3, AF2)
+#define DF_IO4_DF_IO4           MFP_CFG(DF_IO4, AF2)
+#define DF_IO5_DF_IO5           MFP_CFG(DF_IO5, AF2)
+#define DF_IO6_DF_IO6           MFP_CFG(DF_IO6, AF2)
+#define DF_IO7_DF_IO7           MFP_CFG(DF_IO7, AF2)
+#define DF_IO8_DF_IO8           MFP_CFG(DF_IO8, AF2)
+#define DF_IO9_DF_IO9           MFP_CFG(DF_IO9, AF2)
+#define DF_IO10_DF_IO10         MFP_CFG(DF_IO10, AF2)
+#define DF_IO11_DF_IO11         MFP_CFG(DF_IO11, AF2)
+#define DF_IO12_DF_IO12         MFP_CFG(DF_IO12, AF2)
+#define DF_IO13_DF_IO13         MFP_CFG(DF_IO13, AF2)
+#define DF_IO14_DF_IO14         MFP_CFG(DF_IO14, AF2)
+#define DF_IO15_DF_IO15         MFP_CFG(DF_IO15, AF2)
+#define DF_nADV1_ALE_DF_nADV1   MFP_CFG(DF_nADV1_ALE, AF2)
+#define DF_nADV2_ALE_DF_nADV2   MFP_CFG(DF_nADV2_ALE, AF2)
+#define DF_nCS0_DF_nCS0         MFP_CFG(DF_nCS0, AF2)
+#define DF_nCS1_DF_nCS1         MFP_CFG(DF_nCS1, AF2)
+#define DF_nRE_nOE_DF_nOE       MFP_CFG(DF_nRE_nOE, AF2)
+#define DF_nWE_DF_nWE           MFP_CFG(DF_nWE, AF2)
+
+/* DFI - NAND */
+#define DF_CLE_nOE_ND_CLE       MFP_CFG_LPM(DF_CLE_nOE, AF1, PULL_HIGH)
+#define DF_INT_RnB_ND_INT_RnB   MFP_CFG_LPM(DF_INT_RnB, AF1, PULL_LOW)
+#define DF_IO0_ND_IO0           MFP_CFG_LPM(DF_IO0, AF1, PULL_LOW)
+#define DF_IO1_ND_IO1           MFP_CFG_LPM(DF_IO1, AF1, PULL_LOW)
+#define DF_IO2_ND_IO2           MFP_CFG_LPM(DF_IO2, AF1, PULL_LOW)
+#define DF_IO3_ND_IO3           MFP_CFG_LPM(DF_IO3, AF1, PULL_LOW)
+#define DF_IO4_ND_IO4           MFP_CFG_LPM(DF_IO4, AF1, PULL_LOW)
+#define DF_IO5_ND_IO5           MFP_CFG_LPM(DF_IO5, AF1, PULL_LOW)
+#define DF_IO6_ND_IO6           MFP_CFG_LPM(DF_IO6, AF1, PULL_LOW)
+#define DF_IO7_ND_IO7           MFP_CFG_LPM(DF_IO7, AF1, PULL_LOW)
+#define DF_IO8_ND_IO8           MFP_CFG_LPM(DF_IO8, AF1, PULL_LOW)
+#define DF_IO9_ND_IO9           MFP_CFG_LPM(DF_IO9, AF1, PULL_LOW)
+#define DF_IO10_ND_IO10         MFP_CFG_LPM(DF_IO10, AF1, PULL_LOW)
+#define DF_IO11_ND_IO11         MFP_CFG_LPM(DF_IO11, AF1, PULL_LOW)
+#define DF_IO12_ND_IO12         MFP_CFG_LPM(DF_IO12, AF1, PULL_LOW)
+#define DF_IO13_ND_IO13         MFP_CFG_LPM(DF_IO13, AF1, PULL_LOW)
+#define DF_IO14_ND_IO14         MFP_CFG_LPM(DF_IO14, AF1, PULL_LOW)
+#define DF_IO15_ND_IO15         MFP_CFG_LPM(DF_IO15, AF1, PULL_LOW)
+#define DF_nADV1_ALE_ND_ALE     MFP_CFG_LPM(DF_nADV1_ALE, AF1, PULL_HIGH)
+#define DF_nADV2_ALE_ND_ALE     MFP_CFG_LPM(DF_nADV2_ALE, AF1, PULL_HIGH)
+#define DF_nADV2_ALE_nCS3       MFP_CFG_LPM(DF_nADV2_ALE, AF3, PULL_HIGH)
+#define DF_nCS0_ND_nCS0         MFP_CFG_LPM(DF_nCS0, AF1, PULL_HIGH)
+#define DF_nCS1_ND_nCS1         MFP_CFG_LPM(DF_nCS1, AF1, PULL_HIGH)
+#define DF_nRE_nOE_ND_nRE       MFP_CFG_LPM(DF_nRE_nOE, AF1, PULL_HIGH)
+#define DF_nWE_ND_nWE           MFP_CFG_LPM(DF_nWE, AF1, PULL_HIGH)
+
+/* PWM */
+#define GPIO41_PWM0             MFP_CFG_LPM(GPIO41, AF1, PULL_LOW)
+#define GPIO42_PWM1             MFP_CFG_LPM(GPIO42, AF1, PULL_LOW)
+#define GPIO43_PWM3             MFP_CFG_LPM(GPIO43, AF1, PULL_LOW)
+#define GPIO20_PWM0             MFP_CFG_LPM(GPIO20, AF2, PULL_LOW)
+#define GPIO21_PWM2             MFP_CFG_LPM(GPIO21, AF3, PULL_LOW)
+#define GPIO22_PWM3             MFP_CFG_LPM(GPIO22, AF3, PULL_LOW)
+
+/* CIR */
+#define GPIO46_CIR_OUT          MFP_CFG(GPIO46, AF1)
+#define GPIO77_CIR_OUT          MFP_CFG(GPIO77, AF3)
+
+/* USB P2 */
+#define GPIO0_USB_P2_7          MFP_CFG(GPIO0, AF3)
+#define GPIO15_USB_P2_7         MFP_CFG(GPIO15, AF5)
+#define GPIO16_USB_P2_7         MFP_CFG(GPIO16, AF2)
+#define GPIO48_USB_P2_7         MFP_CFG(GPIO48, AF7)
+#define GPIO49_USB_P2_7         MFP_CFG(GPIO49, AF6)
+#define DF_IO9_USB_P2_7         MFP_CFG(DF_IO9, AF3)
+
+#define GPIO48_USB_P2_8         MFP_CFG(GPIO48, AF2)
+#define GPIO50_USB_P2_7         MFP_CFG_X(GPIO50, AF2, DS02X, FLOAT)
+#define GPIO51_USB_P2_5         MFP_CFG(GPIO51, AF2)
+#define GPIO47_USB_P2_4         MFP_CFG(GPIO47, AF2)
+#define GPIO53_USB_P2_3         MFP_CFG(GPIO53, AF2)
+#define GPIO54_USB_P2_6         MFP_CFG(GPIO54, AF2)
+#define GPIO49_USB_P2_2         MFP_CFG(GPIO49, AF2)
+#define GPIO52_USB_P2_1         MFP_CFG(GPIO52, AF2)
+
+#define GPIO63_USB_P2_8         MFP_CFG(GPIO63, AF3)
+#define GPIO64_USB_P2_7         MFP_CFG(GPIO64, AF3)
+#define GPIO65_USB_P2_6         MFP_CFG(GPIO65, AF3)
+#define GPIO66_USG_P2_5         MFP_CFG(GPIO66, AF3)
+#define GPIO67_USB_P2_4         MFP_CFG(GPIO67, AF3)
+#define GPIO68_USB_P2_3         MFP_CFG(GPIO68, AF3)
+#define GPIO69_USB_P2_2         MFP_CFG(GPIO69, AF3)
+#define GPIO70_USB_P2_1         MFP_CFG(GPIO70, AF3)
+
+/* ULPI */
+#define GPIO31_USB_ULPI_D0      MFP_CFG(GPIO31, AF4)
+#define GPIO30_USB_ULPI_D1      MFP_CFG(GPIO30, AF7)
+#define GPIO33_USB_ULPI_D2      MFP_CFG(GPIO33, AF5)
+#define GPIO34_USB_ULPI_D3      MFP_CFG(GPIO34, AF5)
+#define GPIO35_USB_ULPI_D4      MFP_CFG(GPIO35, AF5)
+#define GPIO36_USB_ULPI_D5      MFP_CFG(GPIO36, AF5)
+#define GPIO41_USB_ULPI_D6      MFP_CFG(GPIO41, AF5)
+#define GPIO42_USB_ULPI_D7      MFP_CFG(GPIO42, AF5)
+#define GPIO37_USB_ULPI_DIR     MFP_CFG(GPIO37, AF4)
+#define GPIO38_USB_ULPI_CLK     MFP_CFG(GPIO38, AF4)
+#define GPIO39_USB_ULPI_STP     MFP_CFG(GPIO39, AF4)
+#define GPIO40_USB_ULPI_NXT     MFP_CFG(GPIO40, AF4)
+
+#define GPIO3_CLK26MOUTDMD      MFP_CFG(GPIO3, AF3)
+#define GPIO40_CLK26MOUTDMD     MFP_CFG(GPIO40, AF7)
+#define GPIO94_CLK26MOUTDMD     MFP_CFG(GPIO94, AF5)
+#define GPIO104_CLK26MOUTDMD    MFP_CFG(GPIO104, AF4)
+#define DF_ADDR1_CLK26MOUTDMD   MFP_CFG(DF_ADDR2, AF3)
+#define DF_ADDR3_CLK26MOUTDMD   MFP_CFG(DF_ADDR3, AF3)
+
+#define GPIO14_CLK26MOUT        MFP_CFG(GPIO14, AF5)
+#define GPIO38_CLK26MOUT        MFP_CFG(GPIO38, AF7)
+#define GPIO92_CLK26MOUT        MFP_CFG(GPIO92, AF5)
+#define GPIO105_CLK26MOUT       MFP_CFG(GPIO105, AF4)
+
+#define GPIO2_CLK13MOUTDMD      MFP_CFG(GPIO2, AF3)
+#define GPIO39_CLK13MOUTDMD     MFP_CFG(GPIO39, AF7)
+#define GPIO50_CLK13MOUTDMD     MFP_CFG(GPIO50, AF3)
+#define GPIO93_CLK13MOUTDMD     MFP_CFG(GPIO93, AF5)
+#define GPIO103_CLK13MOUTDMD    MFP_CFG(GPIO103, AF4)
+#define DF_ADDR2_CLK13MOUTDMD   MFP_CFG(DF_ADDR2, AF3)
+
+/* 1 wire */
+#define GPIO95_OW_DQ_IN         MFP_CFG(GPIO95, AF5)
+
+#endif /* __ASM_ARCH_MFP_PXA9xx_H */
diff --git a/arch/arm/mach-pxa/include/mach/mfp.h b/arch/arm/mach-pxa/include/mach/mfp.h
new file mode 100644
index 000000000000..8769567b389b
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/mfp.h
@@ -0,0 +1,319 @@
+/*
+ * arch/arm/mach-pxa/include/mach/mfp.h
+ *
+ * Multi-Function Pin Definitions
+ *
+ * Copyright (C) 2007 Marvell International Ltd.
+ *
+ * 2007-8-21: eric miao <eric.miao@marvell.com>
+ *            initial version
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MFP_H
+#define __ASM_ARCH_MFP_H
+
+#define mfp_to_gpio(m)  ((m) % 128)
+
+/* list of all the configurable MFP pins */
+enum {
+        MFP_PIN_INVALID = -1,
+
+        MFP_PIN_GPIO0 = 0,
+        MFP_PIN_GPIO1,
+        MFP_PIN_GPIO2,
+        MFP_PIN_GPIO3,
+        MFP_PIN_GPIO4,
+        MFP_PIN_GPIO5,
+        MFP_PIN_GPIO6,
+        MFP_PIN_GPIO7,
+        MFP_PIN_GPIO8,
+        MFP_PIN_GPIO9,
+        MFP_PIN_GPIO10,
+        MFP_PIN_GPIO11,
+        MFP_PIN_GPIO12,
+        MFP_PIN_GPIO13,
+        MFP_PIN_GPIO14,
+        MFP_PIN_GPIO15,
+        MFP_PIN_GPIO16,
+        MFP_PIN_GPIO17,
+        MFP_PIN_GPIO18,
+        MFP_PIN_GPIO19,
+        MFP_PIN_GPIO20,
+        MFP_PIN_GPIO21,
+        MFP_PIN_GPIO22,
+        MFP_PIN_GPIO23,
+        MFP_PIN_GPIO24,
+        MFP_PIN_GPIO25,
+        MFP_PIN_GPIO26,
+        MFP_PIN_GPIO27,
+        MFP_PIN_GPIO28,
+        MFP_PIN_GPIO29,
+        MFP_PIN_GPIO30,
+        MFP_PIN_GPIO31,
+        MFP_PIN_GPIO32,
+        MFP_PIN_GPIO33,
+        MFP_PIN_GPIO34,
+        MFP_PIN_GPIO35,
+        MFP_PIN_GPIO36,
+        MFP_PIN_GPIO37,
+        MFP_PIN_GPIO38,
+        MFP_PIN_GPIO39,
+        MFP_PIN_GPIO40,
+        MFP_PIN_GPIO41,
+        MFP_PIN_GPIO42,
+        MFP_PIN_GPIO43,
+        MFP_PIN_GPIO44,
+        MFP_PIN_GPIO45,
+        MFP_PIN_GPIO46,
+        MFP_PIN_GPIO47,
+        MFP_PIN_GPIO48,
+        MFP_PIN_GPIO49,
+        MFP_PIN_GPIO50,
+        MFP_PIN_GPIO51,
+        MFP_PIN_GPIO52,
+        MFP_PIN_GPIO53,
+        MFP_PIN_GPIO54,
+        MFP_PIN_GPIO55,
+        MFP_PIN_GPIO56,
+        MFP_PIN_GPIO57,
+        MFP_PIN_GPIO58,
+        MFP_PIN_GPIO59,
+        MFP_PIN_GPIO60,
+        MFP_PIN_GPIO61,
+        MFP_PIN_GPIO62,
+        MFP_PIN_GPIO63,
+        MFP_PIN_GPIO64,
+        MFP_PIN_GPIO65,
+        MFP_PIN_GPIO66,
+        MFP_PIN_GPIO67,
+        MFP_PIN_GPIO68,
+        MFP_PIN_GPIO69,
+        MFP_PIN_GPIO70,
+        MFP_PIN_GPIO71,
+        MFP_PIN_GPIO72,
+        MFP_PIN_GPIO73,
+        MFP_PIN_GPIO74,
+        MFP_PIN_GPIO75,
+        MFP_PIN_GPIO76,
+        MFP_PIN_GPIO77,
+        MFP_PIN_GPIO78,
+        MFP_PIN_GPIO79,
+        MFP_PIN_GPIO80,
+        MFP_PIN_GPIO81,
+        MFP_PIN_GPIO82,
+        MFP_PIN_GPIO83,
+        MFP_PIN_GPIO84,
+        MFP_PIN_GPIO85,
+        MFP_PIN_GPIO86,
+        MFP_PIN_GPIO87,
+        MFP_PIN_GPIO88,
+        MFP_PIN_GPIO89,
+        MFP_PIN_GPIO90,
+        MFP_PIN_GPIO91,
+        MFP_PIN_GPIO92,
+        MFP_PIN_GPIO93,
+        MFP_PIN_GPIO94,
+        MFP_PIN_GPIO95,
+        MFP_PIN_GPIO96,
+        MFP_PIN_GPIO97,
+        MFP_PIN_GPIO98,
+        MFP_PIN_GPIO99,
+        MFP_PIN_GPIO100,
+        MFP_PIN_GPIO101,
+        MFP_PIN_GPIO102,
+        MFP_PIN_GPIO103,
+        MFP_PIN_GPIO104,
+        MFP_PIN_GPIO105,
+        MFP_PIN_GPIO106,
+        MFP_PIN_GPIO107,
+        MFP_PIN_GPIO108,
+        MFP_PIN_GPIO109,
+        MFP_PIN_GPIO110,
+        MFP_PIN_GPIO111,
+        MFP_PIN_GPIO112,
+        MFP_PIN_GPIO113,
+        MFP_PIN_GPIO114,
+        MFP_PIN_GPIO115,
+        MFP_PIN_GPIO116,
+        MFP_PIN_GPIO117,
+        MFP_PIN_GPIO118,
+        MFP_PIN_GPIO119,
+        MFP_PIN_GPIO120,
+        MFP_PIN_GPIO121,
+        MFP_PIN_GPIO122,
+        MFP_PIN_GPIO123,
+        MFP_PIN_GPIO124,
+        MFP_PIN_GPIO125,
+        MFP_PIN_GPIO126,
+        MFP_PIN_GPIO127,
+        MFP_PIN_GPIO0_2,
+        MFP_PIN_GPIO1_2,
+        MFP_PIN_GPIO2_2,
+        MFP_PIN_GPIO3_2,
+        MFP_PIN_GPIO4_2,
+        MFP_PIN_GPIO5_2,
+        MFP_PIN_GPIO6_2,
+        MFP_PIN_GPIO7_2,
+        MFP_PIN_GPIO8_2,
+        MFP_PIN_GPIO9_2,
+        MFP_PIN_GPIO10_2,
+        MFP_PIN_GPIO11_2,
+        MFP_PIN_GPIO12_2,
+        MFP_PIN_GPIO13_2,
+        MFP_PIN_GPIO14_2,
+        MFP_PIN_GPIO15_2,
+        MFP_PIN_GPIO16_2,
+        MFP_PIN_GPIO17_2,
+
+        MFP_PIN_ULPI_STP,
+        MFP_PIN_ULPI_NXT,
+        MFP_PIN_ULPI_DIR,
+
+        MFP_PIN_nXCVREN,
+        MFP_PIN_DF_CLE_nOE,
+        MFP_PIN_DF_nADV1_ALE,
+        MFP_PIN_DF_SCLK_E,
+        MFP_PIN_DF_SCLK_S,
+        MFP_PIN_nBE0,
+        MFP_PIN_nBE1,
+        MFP_PIN_DF_nADV2_ALE,
+        MFP_PIN_DF_INT_RnB,
+        MFP_PIN_DF_nCS0,
+        MFP_PIN_DF_nCS1,
+        MFP_PIN_nLUA,
+        MFP_PIN_nLLA,
+        MFP_PIN_DF_nWE,
+        MFP_PIN_DF_ALE_nWE,
+        MFP_PIN_DF_nRE_nOE,
+        MFP_PIN_DF_ADDR0,
+        MFP_PIN_DF_ADDR1,
+        MFP_PIN_DF_ADDR2,
+        MFP_PIN_DF_ADDR3,
+        MFP_PIN_DF_IO0,
+        MFP_PIN_DF_IO1,
+        MFP_PIN_DF_IO2,
+        MFP_PIN_DF_IO3,
+        MFP_PIN_DF_IO4,
+        MFP_PIN_DF_IO5,
+        MFP_PIN_DF_IO6,
+        MFP_PIN_DF_IO7,
+        MFP_PIN_DF_IO8,
+        MFP_PIN_DF_IO9,
+        MFP_PIN_DF_IO10,
+        MFP_PIN_DF_IO11,
+        MFP_PIN_DF_IO12,
+        MFP_PIN_DF_IO13,
+        MFP_PIN_DF_IO14,
+        MFP_PIN_DF_IO15,
+
+        /* additional pins on PXA930 */
+        MFP_PIN_GSIM_UIO,
+        MFP_PIN_GSIM_UCLK,
+        MFP_PIN_GSIM_UDET,
+        MFP_PIN_GSIM_nURST,
+        MFP_PIN_PMIC_INT,
+        MFP_PIN_RDY,
+
+        MFP_PIN_MAX,
+};
+
+/*
+ * a possible MFP configuration is represented by a 32-bit integer
+ *
+ * bit  0.. 9 - MFP Pin Number (1024 Pins Maximum)
+ * bit 10..12 - Alternate Function Selection
+ * bit 13..15 - Drive Strength
+ * bit 16..18 - Low Power Mode State
+ * bit 19..20 - Low Power Mode Edge Detection
+ * bit 21..22 - Run Mode Pull State
+ *
+ * to facilitate the definition, the following macros are provided
+ *
+ * MFP_CFG_DEFAULT - default MFP configuration value, with
+ *                alternate function = 0,
+ *                drive strength = fast 3mA (MFP_DS03X)
+ *                low power mode = default
+ *                edge detection = none
+ *
+ * MFP_CFG      - default MFPR value with alternate function
+ * MFP_CFG_DRV  - default MFPR value with alternate function and
+ *                pin drive strength
+ * MFP_CFG_LPM  - default MFPR value with alternate function and
+ *                low power mode
+ * MFP_CFG_X    - default MFPR value with alternate function,
+ *                pin drive strength and low power mode
+ */
+
+typedef unsigned long mfp_cfg_t;
+
+#define MFP_PIN(x)              ((x) & 0x3ff)
+
+#define MFP_AF0                 (0x0 << 10)
+#define MFP_AF1                 (0x1 << 10)
+#define MFP_AF2                 (0x2 << 10)
+#define MFP_AF3                 (0x3 << 10)
+#define MFP_AF4                 (0x4 << 10)
+#define MFP_AF5                 (0x5 << 10)
+#define MFP_AF6                 (0x6 << 10)
+#define MFP_AF7                 (0x7 << 10)
+#define MFP_AF_MASK             (0x7 << 10)
+#define MFP_AF(x)               (((x) >> 10) & 0x7)
+
+#define MFP_DS01X               (0x0 << 13)
+#define MFP_DS02X               (0x1 << 13)
+#define MFP_DS03X               (0x2 << 13)
+#define MFP_DS04X               (0x3 << 13)
+#define MFP_DS06X               (0x4 << 13)
+#define MFP_DS08X               (0x5 << 13)
+#define MFP_DS10X               (0x6 << 13)
+#define MFP_DS13X               (0x7 << 13)
+#define MFP_DS_MASK             (0x7 << 13)
+#define MFP_DS(x)               (((x) >> 13) & 0x7)
+
+#define MFP_LPM_INPUT           (0x0 << 16)
+#define MFP_LPM_DRIVE_LOW       (0x1 << 16)
+#define MFP_LPM_DRIVE_HIGH      (0x2 << 16)
+#define MFP_LPM_PULL_LOW        (0x3 << 16)
+#define MFP_LPM_PULL_HIGH       (0x4 << 16)
+#define MFP_LPM_FLOAT           (0x5 << 16)
+#define MFP_LPM_STATE_MASK      (0x7 << 16)
+#define MFP_LPM_STATE(x)        (((x) >> 16) & 0x7)
+
+#define MFP_LPM_EDGE_NONE       (0x0 << 19)
+#define MFP_LPM_EDGE_RISE       (0x1 << 19)
+#define MFP_LPM_EDGE_FALL       (0x2 << 19)
+#define MFP_LPM_EDGE_BOTH       (0x3 << 19)
+#define MFP_LPM_EDGE_MASK       (0x3 << 19)
+#define MFP_LPM_EDGE(x)         (((x) >> 19) & 0x3)
+
+#define MFP_PULL_NONE           (0x0 << 21)
+#define MFP_PULL_LOW            (0x1 << 21)
+#define MFP_PULL_HIGH           (0x2 << 21)
+#define MFP_PULL_BOTH           (0x3 << 21)
+#define MFP_PULL_MASK           (0x3 << 21)
+#define MFP_PULL(x)             (((x) >> 21) & 0x3)
+
+#define MFP_CFG_DEFAULT         (MFP_AF0 | MFP_DS03X | MFP_LPM_INPUT |\
+                                 MFP_LPM_EDGE_NONE | MFP_PULL_NONE)
+
+#define MFP_CFG(pin, af)                \
+        ((MFP_CFG_DEFAULT & ~MFP_AF_MASK) |\
+         (MFP_PIN(MFP_PIN_##pin) | MFP_##af))
+
+#define MFP_CFG_DRV(pin, af, drv)       \
+        ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK)) |\
+         (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv))
+
+#define MFP_CFG_LPM(pin, af, lpm)       \
+        ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_LPM_STATE_MASK)) |\
+         (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_LPM_##lpm))
+
+#define MFP_CFG_X(pin, af, drv, lpm)    \
+        ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\
+         (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm))
+
+#endif /* __ASM_ARCH_MFP_H */
diff --git a/include/asm-arm/arch-pxa/mmc.h b/arch/arm/mach-pxa/include/mach/mmc.h
index 6d1304c9270f..6d1304c9270f 100644
--- a/include/asm-arm/arch-pxa/mmc.h
+++ b/arch/arm/mach-pxa/include/mach/mmc.h
diff --git a/arch/arm/mach-pxa/include/mach/mtd-xip.h b/arch/arm/mach-pxa/include/mach/mtd-xip.h
new file mode 100644
index 000000000000..351f32f13ce4
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/mtd-xip.h
@@ -0,0 +1,37 @@
+/*
+ * MTD primitives for XIP support. Architecture specific functions
+ *
+ * Do not include this file directly. It's included from linux/mtd/xip.h
+ * 
+ * Author:      Nicolas Pitre
+ * Created:     Nov 2, 2004
+ * Copyright:   (C) 2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * $Id: xip.h,v 1.2 2004/12/01 15:49:10 nico Exp $
+ */
+
+#ifndef __ARCH_PXA_MTD_XIP_H__
+#define __ARCH_PXA_MTD_XIP_H__
+
+#include <mach/pxa-regs.h>
+
+#define xip_irqpending()        (ICIP & ICMR)
+
+/* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */
+#define xip_currtime()          (OSCR)
+#define xip_elapsed_since(x)    (signed)((OSCR - (x)) / 4)
+
+/*
+ * xip_cpu_idle() is used when waiting for a delay equal or larger than
+ * the system timer tick period.  This should put the CPU into idle mode
+ * to save power and to be woken up only when some interrupts are pending.
+ * As above, this should not rely upon standard kernel code.
+ */
+
+#define xip_cpu_idle()  asm volatile ("mcr p14, 0, %0, c7, c0, 0" :: "r" (1))
+
+#endif /* __ARCH_PXA_MTD_XIP_H__ */
diff --git a/include/asm-arm/arch-pxa/ohci.h b/arch/arm/mach-pxa/include/mach/ohci.h
index e848a47128cd..e848a47128cd 100644
--- a/include/asm-arm/arch-pxa/ohci.h
+++ b/arch/arm/mach-pxa/include/mach/ohci.h
diff --git a/include/asm-arm/arch-pxa/palmtx.h b/arch/arm/mach-pxa/include/mach/palmtx.h
index 1e8bccbda510..1e8bccbda510 100644
--- a/include/asm-arm/arch-pxa/palmtx.h
+++ b/arch/arm/mach-pxa/include/mach/palmtx.h
diff --git a/arch/arm/mach-pxa/include/mach/pcm027.h b/arch/arm/mach-pxa/include/mach/pcm027.h
new file mode 100644
index 000000000000..4dcd2e8baa61
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/pcm027.h
@@ -0,0 +1,75 @@
+/*
+ * arch/arm/mach-pxa/include/mach/pcm027.h
+ *
+ * (c) 2003 Phytec Messtechnik GmbH <armlinux@phytec.de>
+ * (c) 2007 Juergen Beisert <j.beisert@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/*
+ * Definitions of CPU card resources only
+ */
+
+/* I2C RTC */
+#define PCM027_RTC_IRQ_GPIO     0
+#define PCM027_RTC_IRQ          IRQ_GPIO(PCM027_RTC_IRQ_GPIO)
+#define PCM027_RTC_IRQ_EDGE     IRQ_TYPE_EDGE_FALLING
+#define ADR_PCM027_RTC          0x51    /* I2C address */
+
+/* I2C EEPROM */
+#define ADR_PCM027_EEPROM       0x54    /* I2C address */
+
+/* Ethernet chip (SMSC91C111) */
+#define PCM027_ETH_IRQ_GPIO     52
+#define PCM027_ETH_IRQ          IRQ_GPIO(PCM027_ETH_IRQ_GPIO)
+#define PCM027_ETH_IRQ_EDGE     IRQ_TYPE_EDGE_RISING
+#define PCM027_ETH_PHYS         PXA_CS5_PHYS
+#define PCM027_ETH_SIZE         (1*1024*1024)
+
+/* CAN controller SJA1000 (unsupported yet) */
+#define PCM027_CAN_IRQ_GPIO     114
+#define PCM027_CAN_IRQ          IRQ_GPIO(PCM027_CAN_IRQ_GPIO)
+#define PCM027_CAN_IRQ_EDGE     IRQ_TYPE_EDGE_FALLING
+#define PCM027_CAN_PHYS         0x22000000
+#define PCM027_CAN_SIZE         0x100
+
+/* SPI GPIO expander (unsupported yet) */
+#define PCM027_EGPIO_IRQ_GPIO   27
+#define PCM027_EGPIO_IRQ        IRQ_GPIO(PCM027_EGPIO_IRQ_GPIO)
+#define PCM027_EGPIO_IRQ_EDGE   IRQ_TYPE_EDGE_FALLING
+#define PCM027_EGPIO_CS         24
+/*
+ * TODO: Switch this pin from dedicated usage to GPIO if
+ * more than the MAX7301 device is connected to this SPI bus
+ */
+#define PCM027_EGPIO_CS_MODE    GPIO24_SFRM_MD
+
+/* Flash memory */
+#define PCM027_FLASH_PHYS       0x00000000
+#define PCM027_FLASH_SIZE       0x02000000
+
+/* onboard LEDs connected to GPIO */
+#define PCM027_LED_CPU          90
+#define PCM027_LED_HEARD_BEAT   91
+
+/*
+ * This CPU module needs a baseboard to work. After basic initializing
+ * its own devices, it calls baseboard's init function.
+ * TODO: Add your own basebaord init function and call it from
+ * inside pcm027_init(). This example here is for the developmen board.
+ * Refer pcm990-baseboard.c
+ */
+extern void pcm990_baseboard_init(void);
diff --git a/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h b/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h
new file mode 100644
index 000000000000..8a4383b776d7
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h
@@ -0,0 +1,275 @@
+/*
+ * arch/arm/mach-pxa/include/mach/pcm990_baseboard.h
+ *
+ * (c) 2003 Phytec Messtechnik GmbH <armlinux@phytec.de>
+ * (c) 2007 Juergen Beisert <j.beisert@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <mach/pcm027.h>
+
+/*
+ * definitions relevant only when the PCM-990
+ * development base board is in use
+ */
+
+/* CPLD's interrupt controller is connected to PCM-027 GPIO 9 */
+#define PCM990_CTRL_INT_IRQ_GPIO        9
+#define PCM990_CTRL_INT_IRQ             IRQ_GPIO(PCM990_CTRL_INT_IRQ_GPIO)
+#define PCM990_CTRL_INT_IRQ_EDGE        IRQ_TYPE_EDGE_RISING
+#define PCM990_CTRL_PHYS                PXA_CS1_PHYS    /* 16-Bit */
+#define PCM990_CTRL_BASE                0xea000000
+#define PCM990_CTRL_SIZE                (1*1024*1024)
+
+#define PCM990_CTRL_PWR_IRQ_GPIO        14
+#define PCM990_CTRL_PWR_IRQ             IRQ_GPIO(PCM990_CTRL_PWR_IRQ_GPIO)
+#define PCM990_CTRL_PWR_IRQ_EDGE        IRQ_TYPE_EDGE_RISING
+
+/* visible CPLD (U7) registers */
+#define PCM990_CTRL_REG0        0x0000  /* RESET REGISTER */
+#define PCM990_CTRL_SYSRES      0x0001  /* System RESET REGISTER */
+#define PCM990_CTRL_RESOUT      0x0002  /* RESETOUT Enable REGISTER */
+#define PCM990_CTRL_RESGPIO     0x0004  /* RESETGPIO Enable REGISTER */
+
+#define PCM990_CTRL_REG1        0x0002  /* Power REGISTER */
+#define PCM990_CTRL_5VOFF       0x0001  /* Disable  5V Regulators */
+#define PCM990_CTRL_CANPWR      0x0004  /* Enable CANPWR ADUM */
+#define PCM990_CTRL_PM_5V       0x0008  /* Read 5V OK */
+
+#define PCM990_CTRL_REG2        0x0004  /* LED REGISTER */
+#define PCM990_CTRL_LEDPWR      0x0001  /* POWER LED enable */
+#define PCM990_CTRL_LEDBAS      0x0002  /* BASIS LED enable */
+#define PCM990_CTRL_LEDUSR      0x0004  /* USER LED enable */
+
+#define PCM990_CTRL_REG3        0x0006  /* LCD CTRL REGISTER 3 */
+#define PCM990_CTRL_LCDPWR      0x0001  /* RW LCD Power on */
+#define PCM990_CTRL_LCDON       0x0002  /* RW LCD Latch on */
+#define PCM990_CTRL_LCDPOS1     0x0004  /* RW POS 1 */
+#define PCM990_CTRL_LCDPOS2     0x0008  /* RW POS 2 */
+
+#define PCM990_CTRL_REG4        0x0008  /* MMC1 CTRL REGISTER 4 */
+#define PCM990_CTRL_MMC1PWR     0x0001 /* RW MMC1 Power on */
+
+#define PCM990_CTRL_REG5        0x000A  /* MMC2 CTRL REGISTER 5 */
+#define PCM990_CTRL_MMC2PWR     0x0001  /* RW MMC2 Power on */
+#define PCM990_CTRL_MMC2LED     0x0002  /* RW MMC2 LED */
+#define PCM990_CTRL_MMC2DE      0x0004  /* R MMC2 Card detect */
+#define PCM990_CTRL_MMC2WP      0x0008  /* R MMC2 Card write protect */
+
+#define PCM990_CTRL_REG6        0x000C  /* Interrupt Clear REGISTER */
+#define PCM990_CTRL_INTC0       0x0001  /* Clear Reg BT Detect */
+#define PCM990_CTRL_INTC1       0x0002  /* Clear Reg FR RI */
+#define PCM990_CTRL_INTC2       0x0004  /* Clear Reg MMC1 Detect */
+#define PCM990_CTRL_INTC3       0x0008  /* Clear Reg PM_5V off */
+
+#define PCM990_CTRL_REG7        0x000E  /* Interrupt Enable REGISTER */
+#define PCM990_CTRL_ENAINT0     0x0001  /* Enable Int BT Detect */
+#define PCM990_CTRL_ENAINT1     0x0002  /* Enable Int FR RI */
+#define PCM990_CTRL_ENAINT2     0x0004  /* Enable Int MMC1 Detect */
+#define PCM990_CTRL_ENAINT3     0x0008  /* Enable Int PM_5V off */
+
+#define PCM990_CTRL_REG8        0x0014  /* Uart REGISTER */
+#define PCM990_CTRL_FFSD        0x0001  /* BT Uart Enable */
+#define PCM990_CTRL_BTSD        0x0002  /* FF Uart Enable */
+#define PCM990_CTRL_FFRI        0x0004  /* FF Uart RI detect */
+#define PCM990_CTRL_BTRX        0x0008  /* BT Uart Rx detect */
+
+#define PCM990_CTRL_REG9        0x0010  /* AC97 Flash REGISTER */
+#define PCM990_CTRL_FLWP        0x0001  /* pC Flash Write Protect */
+#define PCM990_CTRL_FLDIS       0x0002  /* pC Flash Disable */
+#define PCM990_CTRL_AC97ENA     0x0004  /* Enable AC97 Expansion */
+
+#define PCM990_CTRL_REG10       0x0012  /* GPS-REGISTER */
+#define PCM990_CTRL_GPSPWR      0x0004  /* GPS-Modul Power on */
+#define PCM990_CTRL_GPSENA      0x0008  /* GPS-Modul Enable */
+
+#define PCM990_CTRL_REG11       0x0014  /* Accu REGISTER */
+#define PCM990_CTRL_ACENA       0x0001  /* Charge Enable */
+#define PCM990_CTRL_ACSEL       0x0002  /* Charge Akku -> DC Enable */
+#define PCM990_CTRL_ACPRES      0x0004  /* DC Present */
+#define PCM990_CTRL_ACALARM     0x0008  /* Error Akku */
+
+#define PCM990_CTRL_P2V(x)      ((x) - PCM990_CTRL_PHYS + PCM990_CTRL_BASE)
+#define PCM990_CTRL_V2P(x)      ((x) - PCM990_CTRL_BASE + PCM990_CTRL_PHYS)
+
+#ifndef __ASSEMBLY__
+#  define __PCM990_CTRL_REG(x) \
+                (*((volatile unsigned char *)PCM990_CTRL_P2V(x)))
+#else
+#  define __PCM990_CTRL_REG(x)  PCM990_CTRL_P2V(x)
+#endif
+
+#define PCM990_INTMSKENA __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG7)
+#define PCM990_INTSETCLR __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG6)
+#define PCM990_CTRL0    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG0)
+#define PCM990_CTRL1    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG1)
+#define PCM990_CTRL2    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG2)
+#define PCM990_CTRL3    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG3)
+#define PCM990_CTRL4    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG4)
+#define PCM990_CTRL5    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG5)
+#define PCM990_CTRL6    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG6)
+#define PCM990_CTRL7    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG7)
+#define PCM990_CTRL8    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG8)
+#define PCM990_CTRL9    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG9)
+#define PCM990_CTRL10   __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG10)
+#define PCM990_CTRL11   __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG11)
+
+
+/*
+ * IDE
+ */
+#define PCM990_IDE_IRQ_GPIO     13
+#define PCM990_IDE_IRQ          IRQ_GPIO(PCM990_IDE_IRQ_GPIO)
+#define PCM990_IDE_IRQ_EDGE     IRQ_TYPE_EDGE_RISING
+#define PCM990_IDE_PLD_PHYS     0x20000000      /* 16 bit wide */
+#define PCM990_IDE_PLD_BASE     0xee000000
+#define PCM990_IDE_PLD_SIZE     (1*1024*1024)
+
+/* visible CPLD (U6) registers */
+#define PCM990_IDE_PLD_REG0     0x1000  /* OFFSET IDE REGISTER 0 */
+#define PCM990_IDE_PM5V         0x0004  /* R System VCC_5V */
+#define PCM990_IDE_STBY         0x0008  /* R System StandBy */
+
+#define PCM990_IDE_PLD_REG1     0x1002  /* OFFSET IDE REGISTER 1 */
+#define PCM990_IDE_IDEMODE      0x0001  /* R TrueIDE Mode */
+#define PCM990_IDE_DMAENA       0x0004  /* RW DMA Enable */
+#define PCM990_IDE_DMA1_0       0x0008  /* RW 1=DREQ1 0=DREQ0 */
+
+#define PCM990_IDE_PLD_REG2     0x1004  /* OFFSET IDE REGISTER 2 */
+#define PCM990_IDE_RESENA       0x0001  /* RW IDE Reset Bit enable */
+#define PCM990_IDE_RES          0x0002  /* RW IDE Reset Bit */
+#define PCM990_IDE_RDY          0x0008  /* RDY */
+
+#define PCM990_IDE_PLD_REG3     0x1006  /* OFFSET IDE REGISTER 3 */
+#define PCM990_IDE_IDEOE        0x0001  /* RW Latch on Databus */
+#define PCM990_IDE_IDEON        0x0002  /* RW Latch on Control Address */
+#define PCM990_IDE_IDEIN        0x0004  /* RW Latch on Interrupt usw. */
+
+#define PCM990_IDE_PLD_REG4     0x1008  /* OFFSET IDE REGISTER 4 */
+#define PCM990_IDE_PWRENA       0x0001  /* RW IDE Power enable */
+#define PCM990_IDE_5V           0x0002  /* R IDE Power 5V */
+#define PCM990_IDE_PWG          0x0008  /* R IDE Power is on */
+
+#define PCM990_IDE_PLD_P2V(x) ((x) - PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_BASE)
+#define PCM990_IDE_PLD_V2P(x) ((x) - PCM990_IDE_PLD_BASE + PCM990_IDE_PLD_PHYS)
+
+#ifndef __ASSEMBLY__
+# define  __PCM990_IDE_PLD_REG(x) \
+        (*((volatile unsigned char *)PCM990_IDE_PLD_P2V(x)))
+#else
+# define  __PCM990_IDE_PLD_REG(x)       PCM990_IDE_PLD_P2V(x)
+#endif
+
+#define PCM990_IDE0 \
+        __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG0)
+#define PCM990_IDE1 \
+        __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG1)
+#define PCM990_IDE2 \
+        __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG2)
+#define PCM990_IDE3 \
+        __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG3)
+#define PCM990_IDE4 \
+        __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG4)
+
+/*
+ * Compact Flash
+ */
+#define PCM990_CF_IRQ_GPIO      11
+#define PCM990_CF_IRQ           IRQ_GPIO(PCM990_CF_IRQ_GPIO)
+#define PCM990_CF_IRQ_EDGE      IRQ_TYPE_EDGE_RISING
+
+#define PCM990_CF_CD_GPIO       12
+#define PCM990_CF_CD            IRQ_GPIO(PCM990_CF_CD_GPIO)
+#define PCM990_CF_CD_EDGE       IRQ_TYPE_EDGE_RISING
+
+#define PCM990_CF_PLD_PHYS      0x30000000      /* 16 bit wide */
+#define PCM990_CF_PLD_BASE      0xef000000
+#define PCM990_CF_PLD_SIZE      (1*1024*1024)
+#define PCM990_CF_PLD_P2V(x)    ((x) - PCM990_CF_PLD_PHYS + PCM990_CF_PLD_BASE)
+#define PCM990_CF_PLD_V2P(x)    ((x) - PCM990_CF_PLD_BASE + PCM990_CF_PLD_PHYS)
+
+/* visible CPLD (U6) registers */
+#define PCM990_CF_PLD_REG0      0x1000  /* OFFSET CF REGISTER 0 */
+#define PCM990_CF_REG0_LED      0x0001  /* RW LED on */
+#define PCM990_CF_REG0_BLK      0x0002  /* RW LED flash when access */
+#define PCM990_CF_REG0_PM5V     0x0004  /* R System VCC_5V enable */
+#define PCM990_CF_REG0_STBY     0x0008  /* R System StandBy */
+
+#define PCM990_CF_PLD_REG1      0x1002  /* OFFSET CF REGISTER 1 */
+#define PCM990_CF_REG1_IDEMODE  0x0001  /* RW CF card run as TrueIDE */
+#define PCM990_CF_REG1_CF0      0x0002  /* RW CF card at ADDR 0x28000000 */
+
+#define PCM990_CF_PLD_REG2      0x1004  /* OFFSET CF REGISTER 2 */
+#define PCM990_CF_REG2_RES      0x0002  /* RW CF RESET BIT */
+#define PCM990_CF_REG2_RDYENA   0x0004  /* RW Enable CF_RDY */
+#define PCM990_CF_REG2_RDY      0x0008  /* R CF_RDY auf PWAIT */
+
+#define PCM990_CF_PLD_REG3      0x1006  /* OFFSET CF REGISTER 3 */
+#define PCM990_CF_REG3_CFOE     0x0001  /* RW Latch on Databus */
+#define PCM990_CF_REG3_CFON     0x0002  /* RW Latch on Control Address */
+#define PCM990_CF_REG3_CFIN     0x0004  /* RW Latch on Interrupt usw. */
+#define PCM990_CF_REG3_CFCD     0x0008  /* RW Latch on CD1/2 VS1/2 usw */
+
+#define PCM990_CF_PLD_REG4      0x1008  /* OFFSET CF REGISTER 4 */
+#define PCM990_CF_REG4_PWRENA   0x0001  /* RW CF Power on (CD1/2 = "00") */
+#define PCM990_CF_REG4_5_3V     0x0002  /* RW 1 = 5V CF_VCC 0 = 3 V CF_VCC */
+#define PCM990_CF_REG4_3B       0x0004  /* RW 3.0V Backup from VCC (5_3V=0) */
+#define PCM990_CF_REG4_PWG      0x0008  /* R CF-Power is on */
+
+#define PCM990_CF_PLD_REG5      0x100A  /* OFFSET CF REGISTER 5 */
+#define PCM990_CF_REG5_BVD1     0x0001  /* R CF /BVD1 */
+#define PCM990_CF_REG5_BVD2     0x0002  /* R CF /BVD2 */
+#define PCM990_CF_REG5_VS1      0x0004  /* R CF /VS1 */
+#define PCM990_CF_REG5_VS2      0x0008  /* R CF /VS2 */
+
+#define PCM990_CF_PLD_REG6      0x100C  /* OFFSET CF REGISTER 6 */
+#define PCM990_CF_REG6_CD1      0x0001  /* R CF Card_Detect1 */
+#define PCM990_CF_REG6_CD2      0x0002  /* R CF Card_Detect2 */
+
+#ifndef __ASSEMBLY__
+#  define  __PCM990_CF_PLD_REG(x) \
+        (*((volatile unsigned char *)PCM990_CF_PLD_P2V(x)))
+#else
+#  define  __PCM990_CF_PLD_REG(x)       PCM990_CF_PLD_P2V(x)
+#endif
+
+#define PCM990_CF0 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG0)
+#define PCM990_CF1 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG1)
+#define PCM990_CF2 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG2)
+#define PCM990_CF3 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG3)
+#define PCM990_CF4 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG4)
+#define PCM990_CF5 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG5)
+#define PCM990_CF6 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG6)
+
+/*
+ * Wolfson AC97 Touch
+ */
+#define PCM990_AC97_IRQ_GPIO    10
+#define PCM990_AC97_IRQ         IRQ_GPIO(PCM990_AC97_IRQ_GPIO)
+#define PCM990_AC97_IRQ_EDGE    IRQ_TYPE_EDGE_RISING
+
+/*
+ * MMC phyCORE
+ */
+#define PCM990_MMC0_IRQ_GPIO    9
+#define PCM990_MMC0_IRQ         IRQ_GPIO(PCM990_MMC0_IRQ_GPIO)
+#define PCM990_MMC0_IRQ_EDGE    IRQ_TYPE_EDGE_FALLING
+
+/*
+ * USB phyCore
+ */
+#define PCM990_USB_OVERCURRENT (88 | GPIO_ALT_FN_1_IN)
+#define PCM990_USB_PWR_EN (89 | GPIO_ALT_FN_2_OUT)
diff --git a/include/asm-arm/arch-pxa/pm.h b/arch/arm/mach-pxa/include/mach/pm.h
index 261e5bc958db..261e5bc958db 100644
--- a/include/asm-arm/arch-pxa/pm.h
+++ b/arch/arm/mach-pxa/include/mach/pm.h
diff --git a/arch/arm/mach-pxa/include/mach/poodle.h b/arch/arm/mach-pxa/include/mach/poodle.h
new file mode 100644
index 000000000000..8956afe8195e
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/poodle.h
@@ -0,0 +1,75 @@
+/*
+ * arch/arm/mach-pxa/include/mach/poodle.h
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License.  See linux/COPYING for more information.
+ *
+ * Based on:
+ *   arch/arm/mach-sa1100/include/mach/collie.h
+ *
+ * ChangeLog:
+ *   04-06-2001 Lineo Japan, Inc.
+ *   04-16-2001 SHARP Corporation
+ *   Update to 2.6 John Lenz
+ */
+#ifndef __ASM_ARCH_POODLE_H
+#define __ASM_ARCH_POODLE_H  1
+
+/*
+ * GPIOs
+ */
+/* PXA GPIOs */
+#define POODLE_GPIO_ON_KEY              (0)
+#define POODLE_GPIO_AC_IN               (1)
+#define POODLE_GPIO_CO                  16
+#define POODLE_GPIO_TP_INT              (5)
+#define POODLE_GPIO_WAKEUP              (11)    /* change battery */
+#define POODLE_GPIO_GA_INT              (10)
+#define POODLE_GPIO_IR_ON               (22)
+#define POODLE_GPIO_HP_IN               (4)
+#define POODLE_GPIO_CF_IRQ              (17)
+#define POODLE_GPIO_CF_CD               (14)
+#define POODLE_GPIO_CF_STSCHG           (14)
+#define POODLE_GPIO_SD_PWR              (33)
+#define POODLE_GPIO_SD_PWR1             (3)
+#define POODLE_GPIO_nSD_CLK             (6)
+#define POODLE_GPIO_nSD_WP              (7)
+#define POODLE_GPIO_nSD_INT             (8)
+#define POODLE_GPIO_nSD_DETECT          (9)
+#define POODLE_GPIO_MAIN_BAT_LOW        (13)
+#define POODLE_GPIO_BAT_COVER           (13)
+#define POODLE_GPIO_USB_PULLUP          (20)
+#define POODLE_GPIO_ADC_TEMP_ON         (21)
+#define POODLE_GPIO_BYPASS_ON           (36)
+#define POODLE_GPIO_CHRG_ON             (38)
+#define POODLE_GPIO_CHRG_FULL           (16)
+#define POODLE_GPIO_DISCHARGE_ON        (42) /* Enable battery discharge */
+
+/* PXA GPIOs */
+#define POODLE_IRQ_GPIO_ON_KEY          IRQ_GPIO(0)
+#define POODLE_IRQ_GPIO_AC_IN           IRQ_GPIO(1)
+#define POODLE_IRQ_GPIO_HP_IN           IRQ_GPIO(4)
+#define POODLE_IRQ_GPIO_CO              IRQ_GPIO(16)
+#define POODLE_IRQ_GPIO_TP_INT          IRQ_GPIO(5)
+#define POODLE_IRQ_GPIO_WAKEUP          IRQ_GPIO(11)
+#define POODLE_IRQ_GPIO_GA_INT          IRQ_GPIO(10)
+#define POODLE_IRQ_GPIO_CF_IRQ          IRQ_GPIO(17)
+#define POODLE_IRQ_GPIO_CF_CD           IRQ_GPIO(14)
+#define POODLE_IRQ_GPIO_nSD_INT         IRQ_GPIO(8)
+#define POODLE_IRQ_GPIO_nSD_DETECT      IRQ_GPIO(9)
+#define POODLE_IRQ_GPIO_MAIN_BAT_LOW    IRQ_GPIO(13)
+
+/* SCOOP GPIOs */
+#define POODLE_SCOOP_CHARGE_ON  SCOOP_GPCR_PA11
+#define POODLE_SCOOP_CP401      SCOOP_GPCR_PA13
+#define POODLE_SCOOP_VPEN       SCOOP_GPCR_PA18
+#define POODLE_SCOOP_L_PCLK     SCOOP_GPCR_PA20
+#define POODLE_SCOOP_L_LCLK     SCOOP_GPCR_PA21
+#define POODLE_SCOOP_HS_OUT     SCOOP_GPCR_PA22
+
+#define POODLE_SCOOP_IO_DIR     ( POODLE_SCOOP_VPEN | POODLE_SCOOP_HS_OUT )
+#define POODLE_SCOOP_IO_OUT     ( 0 )
+
+extern struct platform_device poodle_locomo_device;
+
+#endif /* __ASM_ARCH_POODLE_H  */
diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h
new file mode 100644
index 000000000000..12288ca3cbb2
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/pxa-regs.h
@@ -0,0 +1,1070 @@
+/*
+ *  arch/arm/mach-pxa/include/mach/pxa-regs.h
+ *
+ *  Author:     Nicolas Pitre
+ *  Created:    Jun 15, 2001
+ *  Copyright:  MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __PXA_REGS_H
+#define __PXA_REGS_H
+
+
+/*
+ * PXA Chip selects
+ */
+
+#define PXA_CS0_PHYS    0x00000000
+#define PXA_CS1_PHYS    0x04000000
+#define PXA_CS2_PHYS    0x08000000
+#define PXA_CS3_PHYS    0x0C000000
+#define PXA_CS4_PHYS    0x10000000
+#define PXA_CS5_PHYS    0x14000000
+
+
+/*
+ * Personal Computer Memory Card International Association (PCMCIA) sockets
+ */
+
+#define PCMCIAPrtSp     0x04000000      /* PCMCIA Partition Space [byte]   */
+#define PCMCIASp        (4*PCMCIAPrtSp) /* PCMCIA Space [byte]             */
+#define PCMCIAIOSp      PCMCIAPrtSp     /* PCMCIA I/O Space [byte]         */
+#define PCMCIAAttrSp    PCMCIAPrtSp     /* PCMCIA Attribute Space [byte]   */
+#define PCMCIAMemSp     PCMCIAPrtSp     /* PCMCIA Memory Space [byte]      */
+
+#define PCMCIA0Sp       PCMCIASp        /* PCMCIA 0 Space [byte]           */
+#define PCMCIA0IOSp     PCMCIAIOSp      /* PCMCIA 0 I/O Space [byte]       */
+#define PCMCIA0AttrSp   PCMCIAAttrSp    /* PCMCIA 0 Attribute Space [byte] */
+#define PCMCIA0MemSp    PCMCIAMemSp     /* PCMCIA 0 Memory Space [byte]    */
+
+#define PCMCIA1Sp       PCMCIASp        /* PCMCIA 1 Space [byte]           */
+#define PCMCIA1IOSp     PCMCIAIOSp      /* PCMCIA 1 I/O Space [byte]       */
+#define PCMCIA1AttrSp   PCMCIAAttrSp    /* PCMCIA 1 Attribute Space [byte] */
+#define PCMCIA1MemSp    PCMCIAMemSp     /* PCMCIA 1 Memory Space [byte]    */
+
+#define _PCMCIA(Nb)                     /* PCMCIA [0..1]                   */ \
+                        (0x20000000 + (Nb)*PCMCIASp)
+#define _PCMCIAIO(Nb)   _PCMCIA (Nb)    /* PCMCIA I/O [0..1]               */
+#define _PCMCIAAttr(Nb)                 /* PCMCIA Attribute [0..1]         */ \
+                        (_PCMCIA (Nb) + 2*PCMCIAPrtSp)
+#define _PCMCIAMem(Nb)                  /* PCMCIA Memory [0..1]            */ \
+                        (_PCMCIA (Nb) + 3*PCMCIAPrtSp)
+
+#define _PCMCIA0        _PCMCIA (0)     /* PCMCIA 0                        */
+#define _PCMCIA0IO      _PCMCIAIO (0)   /* PCMCIA 0 I/O                    */
+#define _PCMCIA0Attr    _PCMCIAAttr (0) /* PCMCIA 0 Attribute              */
+#define _PCMCIA0Mem     _PCMCIAMem (0)  /* PCMCIA 0 Memory                 */
+
+#define _PCMCIA1        _PCMCIA (1)     /* PCMCIA 1                        */
+#define _PCMCIA1IO      _PCMCIAIO (1)   /* PCMCIA 1 I/O                    */
+#define _PCMCIA1Attr    _PCMCIAAttr (1) /* PCMCIA 1 Attribute              */
+#define _PCMCIA1Mem     _PCMCIAMem (1)  /* PCMCIA 1 Memory                 */
+
+
+
+/*
+ * DMA Controller
+ */
+
+#define DCSR0           __REG(0x40000000)  /* DMA Control / Status Register for Channel 0 */
+#define DCSR1           __REG(0x40000004)  /* DMA Control / Status Register for Channel 1 */
+#define DCSR2           __REG(0x40000008)  /* DMA Control / Status Register for Channel 2 */
+#define DCSR3           __REG(0x4000000c)  /* DMA Control / Status Register for Channel 3 */
+#define DCSR4           __REG(0x40000010)  /* DMA Control / Status Register for Channel 4 */
+#define DCSR5           __REG(0x40000014)  /* DMA Control / Status Register for Channel 5 */
+#define DCSR6           __REG(0x40000018)  /* DMA Control / Status Register for Channel 6 */
+#define DCSR7           __REG(0x4000001c)  /* DMA Control / Status Register for Channel 7 */
+#define DCSR8           __REG(0x40000020)  /* DMA Control / Status Register for Channel 8 */
+#define DCSR9           __REG(0x40000024)  /* DMA Control / Status Register for Channel 9 */
+#define DCSR10          __REG(0x40000028)  /* DMA Control / Status Register for Channel 10 */
+#define DCSR11          __REG(0x4000002c)  /* DMA Control / Status Register for Channel 11 */
+#define DCSR12          __REG(0x40000030)  /* DMA Control / Status Register for Channel 12 */
+#define DCSR13          __REG(0x40000034)  /* DMA Control / Status Register for Channel 13 */
+#define DCSR14          __REG(0x40000038)  /* DMA Control / Status Register for Channel 14 */
+#define DCSR15          __REG(0x4000003c)  /* DMA Control / Status Register for Channel 15 */
+
+#define DCSR(x)         __REG2(0x40000000, (x) << 2)
+
+#define DCSR_RUN        (1 << 31)       /* Run Bit (read / write) */
+#define DCSR_NODESC     (1 << 30)       /* No-Descriptor Fetch (read / write) */
+#define DCSR_STOPIRQEN  (1 << 29)       /* Stop Interrupt Enable (read / write) */
+#ifdef CONFIG_PXA27x
+#define DCSR_EORIRQEN   (1 << 28)       /* End of Receive Interrupt Enable (R/W) */
+#define DCSR_EORJMPEN   (1 << 27)       /* Jump to next descriptor on EOR */
+#define DCSR_EORSTOPEN  (1 << 26)       /* STOP on an EOR */
+#define DCSR_SETCMPST   (1 << 25)       /* Set Descriptor Compare Status */
+#define DCSR_CLRCMPST   (1 << 24)       /* Clear Descriptor Compare Status */
+#define DCSR_CMPST      (1 << 10)       /* The Descriptor Compare Status */
+#define DCSR_EORINTR    (1 << 9)        /* The end of Receive */
+#endif
+#define DCSR_REQPEND    (1 << 8)        /* Request Pending (read-only) */
+#define DCSR_STOPSTATE  (1 << 3)        /* Stop State (read-only) */
+#define DCSR_ENDINTR    (1 << 2)        /* End Interrupt (read / write) */
+#define DCSR_STARTINTR  (1 << 1)        /* Start Interrupt (read / write) */
+#define DCSR_BUSERR     (1 << 0)        /* Bus Error Interrupt (read / write) */
+
+#define DALGN           __REG(0x400000a0)  /* DMA Alignment Register */
+#define DINT            __REG(0x400000f0)  /* DMA Interrupt Register */
+
+#define DRCMR(n)        (*(((n) < 64) ? \
+                        &__REG2(0x40000100, ((n) & 0x3f) << 2) : \
+                        &__REG2(0x40001100, ((n) & 0x3f) << 2)))
+
+#define DRCMR0          __REG(0x40000100)  /* Request to Channel Map Register for DREQ 0 */
+#define DRCMR1          __REG(0x40000104)  /* Request to Channel Map Register for DREQ 1 */
+#define DRCMR2          __REG(0x40000108)  /* Request to Channel Map Register for I2S receive Request */
+#define DRCMR3          __REG(0x4000010c)  /* Request to Channel Map Register for I2S transmit Request */
+#define DRCMR4          __REG(0x40000110)  /* Request to Channel Map Register for BTUART receive Request */
+#define DRCMR5          __REG(0x40000114)  /* Request to Channel Map Register for BTUART transmit Request. */
+#define DRCMR6          __REG(0x40000118)  /* Request to Channel Map Register for FFUART receive Request */
+#define DRCMR7          __REG(0x4000011c)  /* Request to Channel Map Register for FFUART transmit Request */
+#define DRCMR8          __REG(0x40000120)  /* Request to Channel Map Register for AC97 microphone Request */
+#define DRCMR9          __REG(0x40000124)  /* Request to Channel Map Register for AC97 modem receive Request */
+#define DRCMR10         __REG(0x40000128)  /* Request to Channel Map Register for AC97 modem transmit Request */
+#define DRCMR11         __REG(0x4000012c)  /* Request to Channel Map Register for AC97 audio receive Request */
+#define DRCMR12         __REG(0x40000130)  /* Request to Channel Map Register for AC97 audio transmit Request */
+#define DRCMR13         __REG(0x40000134)  /* Request to Channel Map Register for SSP receive Request */
+#define DRCMR14         __REG(0x40000138)  /* Request to Channel Map Register for SSP transmit Request */
+#define DRCMR15         __REG(0x4000013c)  /* Request to Channel Map Register for SSP2 receive Request */
+#define DRCMR16         __REG(0x40000140)  /* Request to Channel Map Register for SSP2 transmit Request */
+#define DRCMR17         __REG(0x40000144)  /* Request to Channel Map Register for ICP receive Request */
+#define DRCMR18         __REG(0x40000148)  /* Request to Channel Map Register for ICP transmit Request */
+#define DRCMR19         __REG(0x4000014c)  /* Request to Channel Map Register for STUART receive Request */
+#define DRCMR20         __REG(0x40000150)  /* Request to Channel Map Register for STUART transmit Request */
+#define DRCMR21         __REG(0x40000154)  /* Request to Channel Map Register for MMC receive Request */
+#define DRCMR22         __REG(0x40000158)  /* Request to Channel Map Register for MMC transmit Request */
+#define DRCMR23         __REG(0x4000015c)  /* Reserved */
+#define DRCMR24         __REG(0x40000160)  /* Reserved */
+#define DRCMR25         __REG(0x40000164)  /* Request to Channel Map Register for USB endpoint 1 Request */
+#define DRCMR26         __REG(0x40000168)  /* Request to Channel Map Register for USB endpoint 2 Request */
+#define DRCMR27         __REG(0x4000016C)  /* Request to Channel Map Register for USB endpoint 3 Request */
+#define DRCMR28         __REG(0x40000170)  /* Request to Channel Map Register for USB endpoint 4 Request */
+#define DRCMR29         __REG(0x40000174)  /* Reserved */
+#define DRCMR30         __REG(0x40000178)  /* Request to Channel Map Register for USB endpoint 6 Request */
+#define DRCMR31         __REG(0x4000017C)  /* Request to Channel Map Register for USB endpoint 7 Request */
+#define DRCMR32         __REG(0x40000180)  /* Request to Channel Map Register for USB endpoint 8 Request */
+#define DRCMR33         __REG(0x40000184)  /* Request to Channel Map Register for USB endpoint 9 Request */
+#define DRCMR34         __REG(0x40000188)  /* Reserved */
+#define DRCMR35         __REG(0x4000018C)  /* Request to Channel Map Register for USB endpoint 11 Request */
+#define DRCMR36         __REG(0x40000190)  /* Request to Channel Map Register for USB endpoint 12 Request */
+#define DRCMR37         __REG(0x40000194)  /* Request to Channel Map Register for USB endpoint 13 Request */
+#define DRCMR38         __REG(0x40000198)  /* Request to Channel Map Register for USB endpoint 14 Request */
+#define DRCMR39         __REG(0x4000019C)  /* Reserved */
+#define DRCMR66         __REG(0x40001108)  /* Request to Channel Map Register for SSP3 receive Request */
+#define DRCMR67         __REG(0x4000110C)  /* Request to Channel Map Register for SSP3 transmit Request */
+#define DRCMR68         __REG(0x40001110)  /* Request to Channel Map Register for Camera FIFO 0 Request */
+#define DRCMR69         __REG(0x40001114)  /* Request to Channel Map Register for Camera FIFO 1 Request */
+#define DRCMR70         __REG(0x40001118)  /* Request to Channel Map Register for Camera FIFO 2 Request */
+
+#define DRCMRRXSADR     DRCMR2
+#define DRCMRTXSADR     DRCMR3
+#define DRCMRRXBTRBR    DRCMR4
+#define DRCMRTXBTTHR    DRCMR5
+#define DRCMRRXFFRBR    DRCMR6
+#define DRCMRTXFFTHR    DRCMR7
+#define DRCMRRXMCDR     DRCMR8
+#define DRCMRRXMODR     DRCMR9
+#define DRCMRTXMODR     DRCMR10
+#define DRCMRRXPCDR     DRCMR11
+#define DRCMRTXPCDR     DRCMR12
+#define DRCMRRXSSDR     DRCMR13
+#define DRCMRTXSSDR     DRCMR14
+#define DRCMRRXSS2DR   DRCMR15
+#define DRCMRTXSS2DR   DRCMR16
+#define DRCMRRXICDR     DRCMR17
+#define DRCMRTXICDR     DRCMR18
+#define DRCMRRXSTRBR    DRCMR19
+#define DRCMRTXSTTHR    DRCMR20
+#define DRCMRRXMMC      DRCMR21
+#define DRCMRTXMMC      DRCMR22
+#define DRCMRRXSS3DR   DRCMR66
+#define DRCMRTXSS3DR   DRCMR67
+#define DRCMRUDC(x)     DRCMR((x) + 24)
+
+#define DRCMR_MAPVLD    (1 << 7)        /* Map Valid (read / write) */
+#define DRCMR_CHLNUM    0x1f            /* mask for Channel Number (read / write) */
+
+#define DDADR0          __REG(0x40000200)  /* DMA Descriptor Address Register Channel 0 */
+#define DSADR0          __REG(0x40000204)  /* DMA Source Address Register Channel 0 */
+#define DTADR0          __REG(0x40000208)  /* DMA Target Address Register Channel 0 */
+#define DCMD0           __REG(0x4000020c)  /* DMA Command Address Register Channel 0 */
+#define DDADR1          __REG(0x40000210)  /* DMA Descriptor Address Register Channel 1 */
+#define DSADR1          __REG(0x40000214)  /* DMA Source Address Register Channel 1 */
+#define DTADR1          __REG(0x40000218)  /* DMA Target Address Register Channel 1 */
+#define DCMD1           __REG(0x4000021c)  /* DMA Command Address Register Channel 1 */
+#define DDADR2          __REG(0x40000220)  /* DMA Descriptor Address Register Channel 2 */
+#define DSADR2          __REG(0x40000224)  /* DMA Source Address Register Channel 2 */
+#define DTADR2          __REG(0x40000228)  /* DMA Target Address Register Channel 2 */
+#define DCMD2           __REG(0x4000022c)  /* DMA Command Address Register Channel 2 */
+#define DDADR3          __REG(0x40000230)  /* DMA Descriptor Address Register Channel 3 */
+#define DSADR3          __REG(0x40000234)  /* DMA Source Address Register Channel 3 */
+#define DTADR3          __REG(0x40000238)  /* DMA Target Address Register Channel 3 */
+#define DCMD3           __REG(0x4000023c)  /* DMA Command Address Register Channel 3 */
+#define DDADR4          __REG(0x40000240)  /* DMA Descriptor Address Register Channel 4 */
+#define DSADR4          __REG(0x40000244)  /* DMA Source Address Register Channel 4 */
+#define DTADR4          __REG(0x40000248)  /* DMA Target Address Register Channel 4 */
+#define DCMD4           __REG(0x4000024c)  /* DMA Command Address Register Channel 4 */
+#define DDADR5          __REG(0x40000250)  /* DMA Descriptor Address Register Channel 5 */
+#define DSADR5          __REG(0x40000254)  /* DMA Source Address Register Channel 5 */
+#define DTADR5          __REG(0x40000258)  /* DMA Target Address Register Channel 5 */
+#define DCMD5           __REG(0x4000025c)  /* DMA Command Address Register Channel 5 */
+#define DDADR6          __REG(0x40000260)  /* DMA Descriptor Address Register Channel 6 */
+#define DSADR6          __REG(0x40000264)  /* DMA Source Address Register Channel 6 */
+#define DTADR6          __REG(0x40000268)  /* DMA Target Address Register Channel 6 */
+#define DCMD6           __REG(0x4000026c)  /* DMA Command Address Register Channel 6 */
+#define DDADR7          __REG(0x40000270)  /* DMA Descriptor Address Register Channel 7 */
+#define DSADR7          __REG(0x40000274)  /* DMA Source Address Register Channel 7 */
+#define DTADR7          __REG(0x40000278)  /* DMA Target Address Register Channel 7 */
+#define DCMD7           __REG(0x4000027c)  /* DMA Command Address Register Channel 7 */
+#define DDADR8          __REG(0x40000280)  /* DMA Descriptor Address Register Channel 8 */
+#define DSADR8          __REG(0x40000284)  /* DMA Source Address Register Channel 8 */
+#define DTADR8          __REG(0x40000288)  /* DMA Target Address Register Channel 8 */
+#define DCMD8           __REG(0x4000028c)  /* DMA Command Address Register Channel 8 */
+#define DDADR9          __REG(0x40000290)  /* DMA Descriptor Address Register Channel 9 */
+#define DSADR9          __REG(0x40000294)  /* DMA Source Address Register Channel 9 */
+#define DTADR9          __REG(0x40000298)  /* DMA Target Address Register Channel 9 */
+#define DCMD9           __REG(0x4000029c)  /* DMA Command Address Register Channel 9 */
+#define DDADR10         __REG(0x400002a0)  /* DMA Descriptor Address Register Channel 10 */
+#define DSADR10         __REG(0x400002a4)  /* DMA Source Address Register Channel 10 */
+#define DTADR10         __REG(0x400002a8)  /* DMA Target Address Register Channel 10 */
+#define DCMD10          __REG(0x400002ac)  /* DMA Command Address Register Channel 10 */
+#define DDADR11         __REG(0x400002b0)  /* DMA Descriptor Address Register Channel 11 */
+#define DSADR11         __REG(0x400002b4)  /* DMA Source Address Register Channel 11 */
+#define DTADR11         __REG(0x400002b8)  /* DMA Target Address Register Channel 11 */
+#define DCMD11          __REG(0x400002bc)  /* DMA Command Address Register Channel 11 */
+#define DDADR12         __REG(0x400002c0)  /* DMA Descriptor Address Register Channel 12 */
+#define DSADR12         __REG(0x400002c4)  /* DMA Source Address Register Channel 12 */
+#define DTADR12         __REG(0x400002c8)  /* DMA Target Address Register Channel 12 */
+#define DCMD12          __REG(0x400002cc)  /* DMA Command Address Register Channel 12 */
+#define DDADR13         __REG(0x400002d0)  /* DMA Descriptor Address Register Channel 13 */
+#define DSADR13         __REG(0x400002d4)  /* DMA Source Address Register Channel 13 */
+#define DTADR13         __REG(0x400002d8)  /* DMA Target Address Register Channel 13 */
+#define DCMD13          __REG(0x400002dc)  /* DMA Command Address Register Channel 13 */
+#define DDADR14         __REG(0x400002e0)  /* DMA Descriptor Address Register Channel 14 */
+#define DSADR14         __REG(0x400002e4)  /* DMA Source Address Register Channel 14 */
+#define DTADR14         __REG(0x400002e8)  /* DMA Target Address Register Channel 14 */
+#define DCMD14          __REG(0x400002ec)  /* DMA Command Address Register Channel 14 */
+#define DDADR15         __REG(0x400002f0)  /* DMA Descriptor Address Register Channel 15 */
+#define DSADR15         __REG(0x400002f4)  /* DMA Source Address Register Channel 15 */
+#define DTADR15         __REG(0x400002f8)  /* DMA Target Address Register Channel 15 */
+#define DCMD15          __REG(0x400002fc)  /* DMA Command Address Register Channel 15 */
+
+#define DDADR(x)        __REG2(0x40000200, (x) << 4)
+#define DSADR(x)        __REG2(0x40000204, (x) << 4)
+#define DTADR(x)        __REG2(0x40000208, (x) << 4)
+#define DCMD(x)         __REG2(0x4000020c, (x) << 4)
+
+#define DDADR_DESCADDR  0xfffffff0      /* Address of next descriptor (mask) */
+#define DDADR_STOP      (1 << 0)        /* Stop (read / write) */
+
+#define DCMD_INCSRCADDR (1 << 31)       /* Source Address Increment Setting. */
+#define DCMD_INCTRGADDR (1 << 30)       /* Target Address Increment Setting. */
+#define DCMD_FLOWSRC    (1 << 29)       /* Flow Control by the source. */
+#define DCMD_FLOWTRG    (1 << 28)       /* Flow Control by the target. */
+#define DCMD_STARTIRQEN (1 << 22)       /* Start Interrupt Enable */
+#define DCMD_ENDIRQEN   (1 << 21)       /* End Interrupt Enable */
+#define DCMD_ENDIAN     (1 << 18)       /* Device Endian-ness. */
+#define DCMD_BURST8     (1 << 16)       /* 8 byte burst */
+#define DCMD_BURST16    (2 << 16)       /* 16 byte burst */
+#define DCMD_BURST32    (3 << 16)       /* 32 byte burst */
+#define DCMD_WIDTH1     (1 << 14)       /* 1 byte width */
+#define DCMD_WIDTH2     (2 << 14)       /* 2 byte width (HalfWord) */
+#define DCMD_WIDTH4     (3 << 14)       /* 4 byte width (Word) */
+#define DCMD_LENGTH     0x01fff         /* length mask (max = 8K - 1) */
+
+
+/*
+ * UARTs
+ */
+
+/* Full Function UART (FFUART) */
+#define FFUART          FFRBR
+#define FFRBR           __REG(0x40100000)  /* Receive Buffer Register (read only) */
+#define FFTHR           __REG(0x40100000)  /* Transmit Holding Register (write only) */
+#define FFIER           __REG(0x40100004)  /* Interrupt Enable Register (read/write) */
+#define FFIIR           __REG(0x40100008)  /* Interrupt ID Register (read only) */
+#define FFFCR           __REG(0x40100008)  /* FIFO Control Register (write only) */
+#define FFLCR           __REG(0x4010000C)  /* Line Control Register (read/write) */
+#define FFMCR           __REG(0x40100010)  /* Modem Control Register (read/write) */
+#define FFLSR           __REG(0x40100014)  /* Line Status Register (read only) */
+#define FFMSR           __REG(0x40100018)  /* Modem Status Register (read only) */
+#define FFSPR           __REG(0x4010001C)  /* Scratch Pad Register (read/write) */
+#define FFISR           __REG(0x40100020)  /* Infrared Selection Register (read/write) */
+#define FFDLL           __REG(0x40100000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
+#define FFDLH           __REG(0x40100004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
+
+/* Bluetooth UART (BTUART) */
+#define BTUART          BTRBR
+#define BTRBR           __REG(0x40200000)  /* Receive Buffer Register (read only) */
+#define BTTHR           __REG(0x40200000)  /* Transmit Holding Register (write only) */
+#define BTIER           __REG(0x40200004)  /* Interrupt Enable Register (read/write) */
+#define BTIIR           __REG(0x40200008)  /* Interrupt ID Register (read only) */
+#define BTFCR           __REG(0x40200008)  /* FIFO Control Register (write only) */
+#define BTLCR           __REG(0x4020000C)  /* Line Control Register (read/write) */
+#define BTMCR           __REG(0x40200010)  /* Modem Control Register (read/write) */
+#define BTLSR           __REG(0x40200014)  /* Line Status Register (read only) */
+#define BTMSR           __REG(0x40200018)  /* Modem Status Register (read only) */
+#define BTSPR           __REG(0x4020001C)  /* Scratch Pad Register (read/write) */
+#define BTISR           __REG(0x40200020)  /* Infrared Selection Register (read/write) */
+#define BTDLL           __REG(0x40200000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
+#define BTDLH           __REG(0x40200004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
+
+/* Standard UART (STUART) */
+#define STUART          STRBR
+#define STRBR           __REG(0x40700000)  /* Receive Buffer Register (read only) */
+#define STTHR           __REG(0x40700000)  /* Transmit Holding Register (write only) */
+#define STIER           __REG(0x40700004)  /* Interrupt Enable Register (read/write) */
+#define STIIR           __REG(0x40700008)  /* Interrupt ID Register (read only) */
+#define STFCR           __REG(0x40700008)  /* FIFO Control Register (write only) */
+#define STLCR           __REG(0x4070000C)  /* Line Control Register (read/write) */
+#define STMCR           __REG(0x40700010)  /* Modem Control Register (read/write) */
+#define STLSR           __REG(0x40700014)  /* Line Status Register (read only) */
+#define STMSR           __REG(0x40700018)  /* Reserved */
+#define STSPR           __REG(0x4070001C)  /* Scratch Pad Register (read/write) */
+#define STISR           __REG(0x40700020)  /* Infrared Selection Register (read/write) */
+#define STDLL           __REG(0x40700000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
+#define STDLH           __REG(0x40700004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
+
+/* Hardware UART (HWUART) */
+#define HWUART          HWRBR
+#define HWRBR           __REG(0x41600000)  /* Receive Buffer Register (read only) */
+#define HWTHR           __REG(0x41600000)  /* Transmit Holding Register (write only) */
+#define HWIER           __REG(0x41600004)  /* Interrupt Enable Register (read/write) */
+#define HWIIR           __REG(0x41600008)  /* Interrupt ID Register (read only) */
+#define HWFCR           __REG(0x41600008)  /* FIFO Control Register (write only) */
+#define HWLCR           __REG(0x4160000C)  /* Line Control Register (read/write) */
+#define HWMCR           __REG(0x41600010)  /* Modem Control Register (read/write) */
+#define HWLSR           __REG(0x41600014)  /* Line Status Register (read only) */
+#define HWMSR           __REG(0x41600018)  /* Modem Status Register (read only) */
+#define HWSPR           __REG(0x4160001C)  /* Scratch Pad Register (read/write) */
+#define HWISR           __REG(0x41600020)  /* Infrared Selection Register (read/write) */
+#define HWFOR           __REG(0x41600024)  /* Receive FIFO Occupancy Register (read only) */
+#define HWABR           __REG(0x41600028)  /* Auto-Baud Control Register (read/write) */
+#define HWACR           __REG(0x4160002C)  /* Auto-Baud Count Register (read only) */
+#define HWDLL           __REG(0x41600000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
+#define HWDLH           __REG(0x41600004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
+
+#define IER_DMAE        (1 << 7)        /* DMA Requests Enable */
+#define IER_UUE         (1 << 6)        /* UART Unit Enable */
+#define IER_NRZE        (1 << 5)        /* NRZ coding Enable */
+#define IER_RTIOE       (1 << 4)        /* Receiver Time Out Interrupt Enable */
+#define IER_MIE         (1 << 3)        /* Modem Interrupt Enable */
+#define IER_RLSE        (1 << 2)        /* Receiver Line Status Interrupt Enable */
+#define IER_TIE         (1 << 1)        /* Transmit Data request Interrupt Enable */
+#define IER_RAVIE       (1 << 0)        /* Receiver Data Available Interrupt Enable */
+
+#define IIR_FIFOES1     (1 << 7)        /* FIFO Mode Enable Status */
+#define IIR_FIFOES0     (1 << 6)        /* FIFO Mode Enable Status */
+#define IIR_TOD         (1 << 3)        /* Time Out Detected */
+#define IIR_IID2        (1 << 2)        /* Interrupt Source Encoded */
+#define IIR_IID1        (1 << 1)        /* Interrupt Source Encoded */
+#define IIR_IP          (1 << 0)        /* Interrupt Pending (active low) */
+
+#define FCR_ITL2        (1 << 7)        /* Interrupt Trigger Level */
+#define FCR_ITL1        (1 << 6)        /* Interrupt Trigger Level */
+#define FCR_RESETTF     (1 << 2)        /* Reset Transmitter FIFO */
+#define FCR_RESETRF     (1 << 1)        /* Reset Receiver FIFO */
+#define FCR_TRFIFOE     (1 << 0)        /* Transmit and Receive FIFO Enable */
+#define FCR_ITL_1       (0)
+#define FCR_ITL_8       (FCR_ITL1)
+#define FCR_ITL_16      (FCR_ITL2)
+#define FCR_ITL_32      (FCR_ITL2|FCR_ITL1)
+
+#define LCR_DLAB        (1 << 7)        /* Divisor Latch Access Bit */
+#define LCR_SB          (1 << 6)        /* Set Break */
+#define LCR_STKYP       (1 << 5)        /* Sticky Parity */
+#define LCR_EPS         (1 << 4)        /* Even Parity Select */
+#define LCR_PEN         (1 << 3)        /* Parity Enable */
+#define LCR_STB         (1 << 2)        /* Stop Bit */
+#define LCR_WLS1        (1 << 1)        /* Word Length Select */
+#define LCR_WLS0        (1 << 0)        /* Word Length Select */
+
+#define LSR_FIFOE       (1 << 7)        /* FIFO Error Status */
+#define LSR_TEMT        (1 << 6)        /* Transmitter Empty */
+#define LSR_TDRQ        (1 << 5)        /* Transmit Data Request */
+#define LSR_BI          (1 << 4)        /* Break Interrupt */
+#define LSR_FE          (1 << 3)        /* Framing Error */
+#define LSR_PE          (1 << 2)        /* Parity Error */
+#define LSR_OE          (1 << 1)        /* Overrun Error */
+#define LSR_DR          (1 << 0)        /* Data Ready */
+
+#define MCR_LOOP        (1 << 4)
+#define MCR_OUT2        (1 << 3)        /* force MSR_DCD in loopback mode */
+#define MCR_OUT1        (1 << 2)        /* force MSR_RI in loopback mode */
+#define MCR_RTS         (1 << 1)        /* Request to Send */
+#define MCR_DTR         (1 << 0)        /* Data Terminal Ready */
+
+#define MSR_DCD         (1 << 7)        /* Data Carrier Detect */
+#define MSR_RI          (1 << 6)        /* Ring Indicator */
+#define MSR_DSR         (1 << 5)        /* Data Set Ready */
+#define MSR_CTS         (1 << 4)        /* Clear To Send */
+#define MSR_DDCD        (1 << 3)        /* Delta Data Carrier Detect */
+#define MSR_TERI        (1 << 2)        /* Trailing Edge Ring Indicator */
+#define MSR_DDSR        (1 << 1)        /* Delta Data Set Ready */
+#define MSR_DCTS        (1 << 0)        /* Delta Clear To Send */
+
+/*
+ * IrSR (Infrared Selection Register)
+ */
+#define STISR_RXPL      (1 << 4)        /* Receive Data Polarity */
+#define STISR_TXPL      (1 << 3)        /* Transmit Data Polarity */
+#define STISR_XMODE     (1 << 2)        /* Transmit Pulse Width Select */
+#define STISR_RCVEIR    (1 << 1)        /* Receiver SIR Enable */
+#define STISR_XMITIR    (1 << 0)        /* Transmitter SIR Enable */
+
+
+/*
+ * I2C registers
+ */
+
+#define IBMR            __REG(0x40301680)  /* I2C Bus Monitor Register - IBMR */
+#define IDBR            __REG(0x40301688)  /* I2C Data Buffer Register - IDBR */
+#define ICR             __REG(0x40301690)  /* I2C Control Register - ICR */
+#define ISR             __REG(0x40301698)  /* I2C Status Register - ISR */
+#define ISAR            __REG(0x403016A0)  /* I2C Slave Address Register - ISAR */
+
+#define PWRIBMR    __REG(0x40f00180)  /* Power I2C Bus Monitor Register-IBMR */
+#define PWRIDBR    __REG(0x40f00188)  /* Power I2C Data Buffer Register-IDBR */
+#define PWRICR __REG(0x40f00190)  /* Power I2C Control Register - ICR */
+#define PWRISR __REG(0x40f00198)  /* Power I2C Status Register - ISR */
+#define PWRISAR    __REG(0x40f001A0)  /*Power I2C Slave Address Register-ISAR */
+
+#define ICR_START       (1 << 0)           /* start bit */
+#define ICR_STOP        (1 << 1)           /* stop bit */
+#define ICR_ACKNAK      (1 << 2)           /* send ACK(0) or NAK(1) */
+#define ICR_TB          (1 << 3)           /* transfer byte bit */
+#define ICR_MA          (1 << 4)           /* master abort */
+#define ICR_SCLE        (1 << 5)           /* master clock enable */
+#define ICR_IUE         (1 << 6)           /* unit enable */
+#define ICR_GCD         (1 << 7)           /* general call disable */
+#define ICR_ITEIE       (1 << 8)           /* enable tx interrupts */
+#define ICR_IRFIE       (1 << 9)           /* enable rx interrupts */
+#define ICR_BEIE        (1 << 10)          /* enable bus error ints */
+#define ICR_SSDIE       (1 << 11)          /* slave STOP detected int enable */
+#define ICR_ALDIE       (1 << 12)          /* enable arbitration interrupt */
+#define ICR_SADIE       (1 << 13)          /* slave address detected int enable */
+#define ICR_UR          (1 << 14)          /* unit reset */
+
+#define ISR_RWM         (1 << 0)           /* read/write mode */
+#define ISR_ACKNAK      (1 << 1)           /* ack/nak status */
+#define ISR_UB          (1 << 2)           /* unit busy */
+#define ISR_IBB         (1 << 3)           /* bus busy */
+#define ISR_SSD         (1 << 4)           /* slave stop detected */
+#define ISR_ALD         (1 << 5)           /* arbitration loss detected */
+#define ISR_ITE         (1 << 6)           /* tx buffer empty */
+#define ISR_IRF         (1 << 7)           /* rx buffer full */
+#define ISR_GCAD        (1 << 8)           /* general call address detected */
+#define ISR_SAD         (1 << 9)           /* slave address detected */
+#define ISR_BED         (1 << 10)          /* bus error no ACK/NAK */
+
+
+/*
+ * Serial Audio Controller
+ */
+
+#define SACR0           __REG(0x40400000)  /* Global Control Register */
+#define SACR1           __REG(0x40400004)  /* Serial Audio I 2 S/MSB-Justified Control Register */
+#define SASR0           __REG(0x4040000C)  /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
+#define SAIMR           __REG(0x40400014)  /* Serial Audio Interrupt Mask Register */
+#define SAICR           __REG(0x40400018)  /* Serial Audio Interrupt Clear Register */
+#define SADIV           __REG(0x40400060)  /* Audio Clock Divider Register. */
+#define SADR            __REG(0x40400080)  /* Serial Audio Data Register (TX and RX FIFO access Register). */
+
+#define SACR0_RFTH(x)   ((x) << 12)     /* Rx FIFO Interrupt or DMA Trigger Threshold */
+#define SACR0_TFTH(x)   ((x) << 8)      /* Tx FIFO Interrupt or DMA Trigger Threshold */
+#define SACR0_STRF      (1 << 5)        /* FIFO Select for EFWR Special Function */
+#define SACR0_EFWR      (1 << 4)        /* Enable EFWR Function  */
+#define SACR0_RST       (1 << 3)        /* FIFO, i2s Register Reset */
+#define SACR0_BCKD      (1 << 2)        /* Bit Clock Direction */
+#define SACR0_ENB       (1 << 0)        /* Enable I2S Link */
+#define SACR1_ENLBF     (1 << 5)        /* Enable Loopback */
+#define SACR1_DRPL      (1 << 4)        /* Disable Replaying Function */
+#define SACR1_DREC      (1 << 3)        /* Disable Recording Function */
+#define SACR1_AMSL      (1 << 0)        /* Specify Alternate Mode */
+
+#define SASR0_I2SOFF    (1 << 7)        /* Controller Status */
+#define SASR0_ROR       (1 << 6)        /* Rx FIFO Overrun */
+#define SASR0_TUR       (1 << 5)        /* Tx FIFO Underrun */
+#define SASR0_RFS       (1 << 4)        /* Rx FIFO Service Request */
+#define SASR0_TFS       (1 << 3)        /* Tx FIFO Service Request */
+#define SASR0_BSY       (1 << 2)        /* I2S Busy */
+#define SASR0_RNE       (1 << 1)        /* Rx FIFO Not Empty */
+#define SASR0_TNF       (1 << 0)        /* Tx FIFO Not Empty */
+
+#define SAICR_ROR       (1 << 6)        /* Clear Rx FIFO Overrun Interrupt */
+#define SAICR_TUR       (1 << 5)        /* Clear Tx FIFO Underrun Interrupt */
+
+#define SAIMR_ROR       (1 << 6)        /* Enable Rx FIFO Overrun Condition Interrupt */
+#define SAIMR_TUR       (1 << 5)        /* Enable Tx FIFO Underrun Condition Interrupt */
+#define SAIMR_RFS       (1 << 4)        /* Enable Rx FIFO Service Interrupt */
+#define SAIMR_TFS       (1 << 3)        /* Enable Tx FIFO Service Interrupt */
+
+/*
+ * AC97 Controller registers
+ */
+
+#define POCR            __REG(0x40500000)  /* PCM Out Control Register */
+#define POCR_FEIE       (1 << 3)        /* FIFO Error Interrupt Enable */
+#define POCR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
+
+#define PICR            __REG(0x40500004)  /* PCM In Control Register */
+#define PICR_FEIE       (1 << 3)        /* FIFO Error Interrupt Enable */
+#define PICR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
+
+#define MCCR            __REG(0x40500008)  /* Mic In Control Register */
+#define MCCR_FEIE       (1 << 3)        /* FIFO Error Interrupt Enable */
+#define MCCR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
+
+#define GCR             __REG(0x4050000C)  /* Global Control Register */
+#ifdef CONFIG_PXA3xx
+#define GCR_CLKBPB      (1 << 31)       /* Internal clock enable */
+#endif
+#define GCR_nDMAEN      (1 << 24)       /* non DMA Enable */
+#define GCR_CDONE_IE    (1 << 19)       /* Command Done Interrupt Enable */
+#define GCR_SDONE_IE    (1 << 18)       /* Status Done Interrupt Enable */
+#define GCR_SECRDY_IEN  (1 << 9)        /* Secondary Ready Interrupt Enable */
+#define GCR_PRIRDY_IEN  (1 << 8)        /* Primary Ready Interrupt Enable */
+#define GCR_SECRES_IEN  (1 << 5)        /* Secondary Resume Interrupt Enable */
+#define GCR_PRIRES_IEN  (1 << 4)        /* Primary Resume Interrupt Enable */
+#define GCR_ACLINK_OFF  (1 << 3)        /* AC-link Shut Off */
+#define GCR_WARM_RST    (1 << 2)        /* AC97 Warm Reset */
+#define GCR_COLD_RST    (1 << 1)        /* AC'97 Cold Reset (0 = active) */
+#define GCR_GIE         (1 << 0)        /* Codec GPI Interrupt Enable */
+
+#define POSR            __REG(0x40500010)  /* PCM Out Status Register */
+#define POSR_FIFOE      (1 << 4)        /* FIFO error */
+#define POSR_FSR        (1 << 2)        /* FIFO Service Request */
+
+#define PISR            __REG(0x40500014)  /* PCM In Status Register */
+#define PISR_FIFOE      (1 << 4)        /* FIFO error */
+#define PISR_EOC        (1 << 3)        /* DMA End-of-Chain (exclusive clear) */
+#define PISR_FSR        (1 << 2)        /* FIFO Service Request */
+
+#define MCSR            __REG(0x40500018)  /* Mic In Status Register */
+#define MCSR_FIFOE      (1 << 4)        /* FIFO error */
+#define MCSR_EOC        (1 << 3)        /* DMA End-of-Chain (exclusive clear) */
+#define MCSR_FSR        (1 << 2)        /* FIFO Service Request */
+
+#define GSR             __REG(0x4050001C)  /* Global Status Register */
+#define GSR_CDONE       (1 << 19)       /* Command Done */
+#define GSR_SDONE       (1 << 18)       /* Status Done */
+#define GSR_RDCS        (1 << 15)       /* Read Completion Status */
+#define GSR_BIT3SLT12   (1 << 14)       /* Bit 3 of slot 12 */
+#define GSR_BIT2SLT12   (1 << 13)       /* Bit 2 of slot 12 */
+#define GSR_BIT1SLT12   (1 << 12)       /* Bit 1 of slot 12 */
+#define GSR_SECRES      (1 << 11)       /* Secondary Resume Interrupt */
+#define GSR_PRIRES      (1 << 10)       /* Primary Resume Interrupt */
+#define GSR_SCR         (1 << 9)        /* Secondary Codec Ready */
+#define GSR_PCR         (1 << 8)        /*  Primary Codec Ready */
+#define GSR_MCINT       (1 << 7)        /* Mic In Interrupt */
+#define GSR_POINT       (1 << 6)        /* PCM Out Interrupt */
+#define GSR_PIINT       (1 << 5)        /* PCM In Interrupt */
+#define GSR_ACOFFD      (1 << 3)        /* AC-link Shut Off Done */
+#define GSR_MOINT       (1 << 2)        /* Modem Out Interrupt */
+#define GSR_MIINT       (1 << 1)        /* Modem In Interrupt */
+#define GSR_GSCI        (1 << 0)        /* Codec GPI Status Change Interrupt */
+
+#define CAR             __REG(0x40500020)  /* CODEC Access Register */
+#define CAR_CAIP        (1 << 0)        /* Codec Access In Progress */
+
+#define PCDR            __REG(0x40500040)  /* PCM FIFO Data Register */
+#define MCDR            __REG(0x40500060)  /* Mic-in FIFO Data Register */
+
+#define MOCR            __REG(0x40500100)  /* Modem Out Control Register */
+#define MOCR_FEIE       (1 << 3)        /* FIFO Error */
+#define MOCR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
+
+#define MICR            __REG(0x40500108)  /* Modem In Control Register */
+#define MICR_FEIE       (1 << 3)        /* FIFO Error */
+#define MICR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
+
+#define MOSR            __REG(0x40500110)  /* Modem Out Status Register */
+#define MOSR_FIFOE      (1 << 4)        /* FIFO error */
+#define MOSR_FSR        (1 << 2)        /* FIFO Service Request */
+
+#define MISR            __REG(0x40500118)  /* Modem In Status Register */
+#define MISR_FIFOE      (1 << 4)        /* FIFO error */
+#define MISR_EOC        (1 << 3)        /* DMA End-of-Chain (exclusive clear) */
+#define MISR_FSR        (1 << 2)        /* FIFO Service Request */
+
+#define MODR            __REG(0x40500140)  /* Modem FIFO Data Register */
+
+#define PAC_REG_BASE    __REG(0x40500200)  /* Primary Audio Codec */
+#define SAC_REG_BASE    __REG(0x40500300)  /* Secondary Audio Codec */
+#define PMC_REG_BASE    __REG(0x40500400)  /* Primary Modem Codec */
+#define SMC_REG_BASE    __REG(0x40500500)  /* Secondary Modem Codec */
+
+
+/*
+ * Fast Infrared Communication Port
+ */
+
+#define FICP            __REG(0x40800000)  /* Start of FICP area */
+#define ICCR0           __REG(0x40800000)  /* ICP Control Register 0 */
+#define ICCR1           __REG(0x40800004)  /* ICP Control Register 1 */
+#define ICCR2           __REG(0x40800008)  /* ICP Control Register 2 */
+#define ICDR            __REG(0x4080000c)  /* ICP Data Register */
+#define ICSR0           __REG(0x40800014)  /* ICP Status Register 0 */
+#define ICSR1           __REG(0x40800018)  /* ICP Status Register 1 */
+
+#define ICCR0_AME       (1 << 7)        /* Address match enable */
+#define ICCR0_TIE       (1 << 6)        /* Transmit FIFO interrupt enable */
+#define ICCR0_RIE       (1 << 5)        /* Recieve FIFO interrupt enable */
+#define ICCR0_RXE       (1 << 4)        /* Receive enable */
+#define ICCR0_TXE       (1 << 3)        /* Transmit enable */
+#define ICCR0_TUS       (1 << 2)        /* Transmit FIFO underrun select */
+#define ICCR0_LBM       (1 << 1)        /* Loopback mode */
+#define ICCR0_ITR       (1 << 0)        /* IrDA transmission */
+
+#define ICCR2_RXP       (1 << 3)        /* Receive Pin Polarity select */
+#define ICCR2_TXP       (1 << 2)        /* Transmit Pin Polarity select */
+#define ICCR2_TRIG      (3 << 0)        /* Receive FIFO Trigger threshold */
+#define ICCR2_TRIG_8    (0 << 0)        /*      >= 8 bytes */
+#define ICCR2_TRIG_16   (1 << 0)        /*      >= 16 bytes */
+#define ICCR2_TRIG_32   (2 << 0)        /*      >= 32 bytes */
+
+#ifdef CONFIG_PXA27x
+#define ICSR0_EOC       (1 << 6)        /* DMA End of Descriptor Chain */
+#endif
+#define ICSR0_FRE       (1 << 5)        /* Framing error */
+#define ICSR0_RFS       (1 << 4)        /* Receive FIFO service request */
+#define ICSR0_TFS       (1 << 3)        /* Transnit FIFO service request */
+#define ICSR0_RAB       (1 << 2)        /* Receiver abort */
+#define ICSR0_TUR       (1 << 1)        /* Trunsmit FIFO underun */
+#define ICSR0_EIF       (1 << 0)        /* End/Error in FIFO */
+
+#define ICSR1_ROR       (1 << 6)        /* Receiver FIFO underrun  */
+#define ICSR1_CRE       (1 << 5)        /* CRC error */
+#define ICSR1_EOF       (1 << 4)        /* End of frame */
+#define ICSR1_TNF       (1 << 3)        /* Transmit FIFO not full */
+#define ICSR1_RNE       (1 << 2)        /* Receive FIFO not empty */
+#define ICSR1_TBY       (1 << 1)        /* Tramsmiter busy flag */
+#define ICSR1_RSY       (1 << 0)        /* Recevier synchronized flag */
+
+
+/*
+ * Real Time Clock
+ */
+
+#define RCNR            __REG(0x40900000)  /* RTC Count Register */
+#define RTAR            __REG(0x40900004)  /* RTC Alarm Register */
+#define RTSR            __REG(0x40900008)  /* RTC Status Register */
+#define RTTR            __REG(0x4090000C)  /* RTC Timer Trim Register */
+#define PIAR            __REG(0x40900038)  /* Periodic Interrupt Alarm Register */
+
+#define RTSR_PICE       (1 << 15)       /* Periodic interrupt count enable */
+#define RTSR_PIALE      (1 << 14)       /* Periodic interrupt Alarm enable */
+#define RTSR_HZE        (1 << 3)        /* HZ interrupt enable */
+#define RTSR_ALE        (1 << 2)        /* RTC alarm interrupt enable */
+#define RTSR_HZ         (1 << 1)        /* HZ rising-edge detected */
+#define RTSR_AL         (1 << 0)        /* RTC alarm detected */
+
+
+/*
+ * OS Timer & Match Registers
+ */
+
+#define OSMR0           __REG(0x40A00000)  /* */
+#define OSMR1           __REG(0x40A00004)  /* */
+#define OSMR2           __REG(0x40A00008)  /* */
+#define OSMR3           __REG(0x40A0000C)  /* */
+#define OSMR4           __REG(0x40A00080)  /* */
+#define OSCR            __REG(0x40A00010)  /* OS Timer Counter Register */
+#define OSCR4           __REG(0x40A00040)  /* OS Timer Counter Register */
+#define OMCR4           __REG(0x40A000C0)  /* */
+#define OSSR            __REG(0x40A00014)  /* OS Timer Status Register */
+#define OWER            __REG(0x40A00018)  /* OS Timer Watchdog Enable Register */
+#define OIER            __REG(0x40A0001C)  /* OS Timer Interrupt Enable Register */
+
+#define OSSR_M3         (1 << 3)        /* Match status channel 3 */
+#define OSSR_M2         (1 << 2)        /* Match status channel 2 */
+#define OSSR_M1         (1 << 1)        /* Match status channel 1 */
+#define OSSR_M0         (1 << 0)        /* Match status channel 0 */
+
+#define OWER_WME        (1 << 0)        /* Watchdog Match Enable */
+
+#define OIER_E3         (1 << 3)        /* Interrupt enable channel 3 */
+#define OIER_E2         (1 << 2)        /* Interrupt enable channel 2 */
+#define OIER_E1         (1 << 1)        /* Interrupt enable channel 1 */
+#define OIER_E0         (1 << 0)        /* Interrupt enable channel 0 */
+
+
+/*
+ * Pulse Width Modulator
+ */
+
+#define PWM_CTRL0       __REG(0x40B00000)  /* PWM 0 Control Register */
+#define PWM_PWDUTY0     __REG(0x40B00004)  /* PWM 0 Duty Cycle Register */
+#define PWM_PERVAL0     __REG(0x40B00008)  /* PWM 0 Period Control Register */
+
+#define PWM_CTRL1       __REG(0x40C00000)  /* PWM 1Control Register */
+#define PWM_PWDUTY1     __REG(0x40C00004)  /* PWM 1 Duty Cycle Register */
+#define PWM_PERVAL1     __REG(0x40C00008)  /* PWM 1 Period Control Register */
+
+
+/*
+ * Interrupt Controller
+ */
+
+#define ICIP            __REG(0x40D00000)  /* Interrupt Controller IRQ Pending Register */
+#define ICMR            __REG(0x40D00004)  /* Interrupt Controller Mask Register */
+#define ICLR            __REG(0x40D00008)  /* Interrupt Controller Level Register */
+#define ICFP            __REG(0x40D0000C)  /* Interrupt Controller FIQ Pending Register */
+#define ICPR            __REG(0x40D00010)  /* Interrupt Controller Pending Register */
+#define ICCR            __REG(0x40D00014)  /* Interrupt Controller Control Register */
+
+#define ICIP2           __REG(0x40D0009C)  /* Interrupt Controller IRQ Pending Register 2 */
+#define ICMR2           __REG(0x40D000A0)  /* Interrupt Controller Mask Register 2 */
+#define ICLR2           __REG(0x40D000A4)  /* Interrupt Controller Level Register 2 */
+#define ICFP2           __REG(0x40D000A8)  /* Interrupt Controller FIQ Pending Register 2 */
+#define ICPR2           __REG(0x40D000AC)  /* Interrupt Controller Pending Register 2 */
+
+/*
+ * General Purpose I/O
+ */
+
+#define GPIO0_BASE      ((void __iomem *)io_p2v(0x40E00000))
+#define GPIO1_BASE      ((void __iomem *)io_p2v(0x40E00004))
+#define GPIO2_BASE      ((void __iomem *)io_p2v(0x40E00008))
+#define GPIO3_BASE      ((void __iomem *)io_p2v(0x40E00100))
+
+#define GPLR_OFFSET     0x00
+#define GPDR_OFFSET     0x0C
+#define GPSR_OFFSET     0x18
+#define GPCR_OFFSET     0x24
+#define GRER_OFFSET     0x30
+#define GFER_OFFSET     0x3C
+#define GEDR_OFFSET     0x48
+
+#define GPLR0           __REG(0x40E00000)  /* GPIO Pin-Level Register GPIO<31:0> */
+#define GPLR1           __REG(0x40E00004)  /* GPIO Pin-Level Register GPIO<63:32> */
+#define GPLR2           __REG(0x40E00008)  /* GPIO Pin-Level Register GPIO<80:64> */
+
+#define GPDR0           __REG(0x40E0000C)  /* GPIO Pin Direction Register GPIO<31:0> */
+#define GPDR1           __REG(0x40E00010)  /* GPIO Pin Direction Register GPIO<63:32> */
+#define GPDR2           __REG(0x40E00014)  /* GPIO Pin Direction Register GPIO<80:64> */
+
+#define GPSR0           __REG(0x40E00018)  /* GPIO Pin Output Set Register GPIO<31:0> */
+#define GPSR1           __REG(0x40E0001C)  /* GPIO Pin Output Set Register GPIO<63:32> */
+#define GPSR2           __REG(0x40E00020)  /* GPIO Pin Output Set Register GPIO<80:64> */
+
+#define GPCR0           __REG(0x40E00024)  /* GPIO Pin Output Clear Register GPIO<31:0> */
+#define GPCR1           __REG(0x40E00028)  /* GPIO Pin Output Clear Register GPIO <63:32> */
+#define GPCR2           __REG(0x40E0002C)  /* GPIO Pin Output Clear Register GPIO <80:64> */
+
+#define GRER0           __REG(0x40E00030)  /* GPIO Rising-Edge Detect Register GPIO<31:0> */
+#define GRER1           __REG(0x40E00034)  /* GPIO Rising-Edge Detect Register GPIO<63:32> */
+#define GRER2           __REG(0x40E00038)  /* GPIO Rising-Edge Detect Register GPIO<80:64> */
+
+#define GFER0           __REG(0x40E0003C)  /* GPIO Falling-Edge Detect Register GPIO<31:0> */
+#define GFER1           __REG(0x40E00040)  /* GPIO Falling-Edge Detect Register GPIO<63:32> */
+#define GFER2           __REG(0x40E00044)  /* GPIO Falling-Edge Detect Register GPIO<80:64> */
+
+#define GEDR0           __REG(0x40E00048)  /* GPIO Edge Detect Status Register GPIO<31:0> */
+#define GEDR1           __REG(0x40E0004C)  /* GPIO Edge Detect Status Register GPIO<63:32> */
+#define GEDR2           __REG(0x40E00050)  /* GPIO Edge Detect Status Register GPIO<80:64> */
+
+#define GAFR0_L         __REG(0x40E00054)  /* GPIO Alternate Function Select Register GPIO<15:0> */
+#define GAFR0_U         __REG(0x40E00058)  /* GPIO Alternate Function Select Register GPIO<31:16> */
+#define GAFR1_L         __REG(0x40E0005C)  /* GPIO Alternate Function Select Register GPIO<47:32> */
+#define GAFR1_U         __REG(0x40E00060)  /* GPIO Alternate Function Select Register GPIO<63:48> */
+#define GAFR2_L         __REG(0x40E00064)  /* GPIO Alternate Function Select Register GPIO<79:64> */
+#define GAFR2_U         __REG(0x40E00068)  /* GPIO Alternate Function Select Register GPIO<95-80> */
+#define GAFR3_L         __REG(0x40E0006C)  /* GPIO Alternate Function Select Register GPIO<111:96> */
+#define GAFR3_U         __REG(0x40E00070)  /* GPIO Alternate Function Select Register GPIO<127:112> */
+
+#define GPLR3           __REG(0x40E00100)  /* GPIO Pin-Level Register GPIO<127:96> */
+#define GPDR3           __REG(0x40E0010C)  /* GPIO Pin Direction Register GPIO<127:96> */
+#define GPSR3           __REG(0x40E00118)  /* GPIO Pin Output Set Register GPIO<127:96> */
+#define GPCR3           __REG(0x40E00124)  /* GPIO Pin Output Clear Register GPIO<127:96> */
+#define GRER3           __REG(0x40E00130)  /* GPIO Rising-Edge Detect Register GPIO<127:96> */
+#define GFER3           __REG(0x40E0013C)  /* GPIO Falling-Edge Detect Register GPIO<127:96> */
+#define GEDR3           __REG(0x40E00148)  /* GPIO Edge Detect Status Register GPIO<127:96> */
+
+/* More handy macros.  The argument is a literal GPIO number. */
+
+#define GPIO_bit(x)     (1 << ((x) & 0x1f))
+
+#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
+
+/* Interrupt Controller */
+
+#define _GPLR(x)        __REG2(0x40E00000, ((x) & 0x60) >> 3)
+#define _GPDR(x)        __REG2(0x40E0000C, ((x) & 0x60) >> 3)
+#define _GPSR(x)        __REG2(0x40E00018, ((x) & 0x60) >> 3)
+#define _GPCR(x)        __REG2(0x40E00024, ((x) & 0x60) >> 3)
+#define _GRER(x)        __REG2(0x40E00030, ((x) & 0x60) >> 3)
+#define _GFER(x)        __REG2(0x40E0003C, ((x) & 0x60) >> 3)
+#define _GEDR(x)        __REG2(0x40E00048, ((x) & 0x60) >> 3)
+#define _GAFR(x)        __REG2(0x40E00054, ((x) & 0x70) >> 2)
+
+#define GPLR(x)         (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3))
+#define GPDR(x)         (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3))
+#define GPSR(x)         (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3))
+#define GPCR(x)         (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3))
+#define GRER(x)         (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3))
+#define GFER(x)         (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3))
+#define GEDR(x)         (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3))
+#define GAFR(x)         (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \
+                         ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U)))
+#else
+
+#define GPLR(x)         __REG2(0x40E00000, ((x) & 0x60) >> 3)
+#define GPDR(x)         __REG2(0x40E0000C, ((x) & 0x60) >> 3)
+#define GPSR(x)         __REG2(0x40E00018, ((x) & 0x60) >> 3)
+#define GPCR(x)         __REG2(0x40E00024, ((x) & 0x60) >> 3)
+#define GRER(x)         __REG2(0x40E00030, ((x) & 0x60) >> 3)
+#define GFER(x)         __REG2(0x40E0003C, ((x) & 0x60) >> 3)
+#define GEDR(x)         __REG2(0x40E00048, ((x) & 0x60) >> 3)
+#define GAFR(x)         __REG2(0x40E00054, ((x) & 0x70) >> 2)
+
+#endif
+
+/*
+ * Power Manager - see pxa2xx-regs.h
+ */
+
+/*
+ * SSP Serial Port Registers - see arch/arm/mach-pxa/include/mach/regs-ssp.h
+ */
+
+/*
+ * MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h
+ */
+
+/*
+ * Core Clock - see arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
+ */
+
+#ifdef CONFIG_PXA27x
+
+/* Camera Interface */
+#define CICR0           __REG(0x50000000)
+#define CICR1           __REG(0x50000004)
+#define CICR2           __REG(0x50000008)
+#define CICR3           __REG(0x5000000C)
+#define CICR4           __REG(0x50000010)
+#define CISR            __REG(0x50000014)
+#define CIFR            __REG(0x50000018)
+#define CITOR           __REG(0x5000001C)
+#define CIBR0           __REG(0x50000028)
+#define CIBR1           __REG(0x50000030)
+#define CIBR2           __REG(0x50000038)
+
+#define CICR0_DMAEN     (1 << 31)       /* DMA request enable */
+#define CICR0_PAR_EN    (1 << 30)       /* Parity enable */
+#define CICR0_SL_CAP_EN (1 << 29)       /* Capture enable for slave mode */
+#define CICR0_ENB       (1 << 28)       /* Camera interface enable */
+#define CICR0_DIS       (1 << 27)       /* Camera interface disable */
+#define CICR0_SIM       (0x7 << 24)     /* Sensor interface mode mask */
+#define CICR0_TOM       (1 << 9)        /* Time-out mask */
+#define CICR0_RDAVM     (1 << 8)        /* Receive-data-available mask */
+#define CICR0_FEM       (1 << 7)        /* FIFO-empty mask */
+#define CICR0_EOLM      (1 << 6)        /* End-of-line mask */
+#define CICR0_PERRM     (1 << 5)        /* Parity-error mask */
+#define CICR0_QDM       (1 << 4)        /* Quick-disable mask */
+#define CICR0_CDM       (1 << 3)        /* Disable-done mask */
+#define CICR0_SOFM      (1 << 2)        /* Start-of-frame mask */
+#define CICR0_EOFM      (1 << 1)        /* End-of-frame mask */
+#define CICR0_FOM       (1 << 0)        /* FIFO-overrun mask */
+
+#define CICR1_TBIT      (1 << 31)       /* Transparency bit */
+#define CICR1_RGBT_CONV (0x3 << 29)     /* RGBT conversion mask */
+#define CICR1_PPL       (0x7ff << 15)   /* Pixels per line mask */
+#define CICR1_RGB_CONV  (0x7 << 12)     /* RGB conversion mask */
+#define CICR1_RGB_F     (1 << 11)       /* RGB format */
+#define CICR1_YCBCR_F   (1 << 10)       /* YCbCr format */
+#define CICR1_RGB_BPP   (0x7 << 7)      /* RGB bis per pixel mask */
+#define CICR1_RAW_BPP   (0x3 << 5)      /* Raw bis per pixel mask */
+#define CICR1_COLOR_SP  (0x3 << 3)      /* Color space mask */
+#define CICR1_DW        (0x7 << 0)      /* Data width mask */
+
+#define CICR2_BLW       (0xff << 24)    /* Beginning-of-line pixel clock
+                                           wait count mask */
+#define CICR2_ELW       (0xff << 16)    /* End-of-line pixel clock
+                                           wait count mask */
+#define CICR2_HSW       (0x3f << 10)    /* Horizontal sync pulse width mask */
+#define CICR2_BFPW      (0x3f << 3)     /* Beginning-of-frame pixel clock
+                                           wait count mask */
+#define CICR2_FSW       (0x7 << 0)      /* Frame stabilization
+                                           wait count mask */
+
+#define CICR3_BFW       (0xff << 24)    /* Beginning-of-frame line clock
+                                           wait count mask */
+#define CICR3_EFW       (0xff << 16)    /* End-of-frame line clock
+                                           wait count mask */
+#define CICR3_VSW       (0x3f << 10)    /* Vertical sync pulse width mask */
+#define CICR3_BFPW      (0x3f << 3)     /* Beginning-of-frame pixel clock
+                                           wait count mask */
+#define CICR3_LPF       (0x7ff << 0)    /* Lines per frame mask */
+
+#define CICR4_MCLK_DLY  (0x3 << 24)     /* MCLK Data Capture Delay mask */
+#define CICR4_PCLK_EN   (1 << 23)       /* Pixel clock enable */
+#define CICR4_PCP       (1 << 22)       /* Pixel clock polarity */
+#define CICR4_HSP       (1 << 21)       /* Horizontal sync polarity */
+#define CICR4_VSP       (1 << 20)       /* Vertical sync polarity */
+#define CICR4_MCLK_EN   (1 << 19)       /* MCLK enable */
+#define CICR4_FR_RATE   (0x7 << 8)      /* Frame rate mask */
+#define CICR4_DIV       (0xff << 0)     /* Clock divisor mask */
+
+#define CISR_FTO        (1 << 15)       /* FIFO time-out */
+#define CISR_RDAV_2     (1 << 14)       /* Channel 2 receive data available */
+#define CISR_RDAV_1     (1 << 13)       /* Channel 1 receive data available */
+#define CISR_RDAV_0     (1 << 12)       /* Channel 0 receive data available */
+#define CISR_FEMPTY_2   (1 << 11)       /* Channel 2 FIFO empty */
+#define CISR_FEMPTY_1   (1 << 10)       /* Channel 1 FIFO empty */
+#define CISR_FEMPTY_0   (1 << 9)        /* Channel 0 FIFO empty */
+#define CISR_EOL        (1 << 8)        /* End of line */
+#define CISR_PAR_ERR    (1 << 7)        /* Parity error */
+#define CISR_CQD        (1 << 6)        /* Camera interface quick disable */
+#define CISR_CDD        (1 << 5)        /* Camera interface disable done */
+#define CISR_SOF        (1 << 4)        /* Start of frame */
+#define CISR_EOF        (1 << 3)        /* End of frame */
+#define CISR_IFO_2      (1 << 2)        /* FIFO overrun for Channel 2 */
+#define CISR_IFO_1      (1 << 1)        /* FIFO overrun for Channel 1 */
+#define CISR_IFO_0      (1 << 0)        /* FIFO overrun for Channel 0 */
+
+#define CIFR_FLVL2      (0x7f << 23)    /* FIFO 2 level mask */
+#define CIFR_FLVL1      (0x7f << 16)    /* FIFO 1 level mask */
+#define CIFR_FLVL0      (0xff << 8)     /* FIFO 0 level mask */
+#define CIFR_THL_0      (0x3 << 4)      /* Threshold Level for Channel 0 FIFO */
+#define CIFR_RESET_F    (1 << 3)        /* Reset input FIFOs */
+#define CIFR_FEN2       (1 << 2)        /* FIFO enable for channel 2 */
+#define CIFR_FEN1       (1 << 1)        /* FIFO enable for channel 1 */
+#define CIFR_FEN0       (1 << 0)        /* FIFO enable for channel 0 */
+
+#define SRAM_SIZE               0x40000 /* 4x64K  */
+
+#define SRAM_MEM_PHYS           0x5C000000
+
+#define IMPMCR          __REG(0x58000000) /* IM Power Management Control Reg */
+#define IMPMSR          __REG(0x58000008) /* IM Power Management Status Reg */
+
+#define IMPMCR_PC3              (0x3 << 22) /* Bank 3 Power Control */
+#define IMPMCR_PC3_RUN_MODE     (0x0 << 22) /*   Run mode */
+#define IMPMCR_PC3_STANDBY_MODE (0x1 << 22) /*   Standby mode */
+#define IMPMCR_PC3_AUTO_MODE    (0x3 << 22) /*   Automatically controlled */
+
+#define IMPMCR_PC2              (0x3 << 20) /* Bank 2 Power Control */
+#define IMPMCR_PC2_RUN_MODE     (0x0 << 20) /*   Run mode */
+#define IMPMCR_PC2_STANDBY_MODE (0x1 << 20) /*   Standby mode */
+#define IMPMCR_PC2_AUTO_MODE    (0x3 << 20) /*   Automatically controlled */
+
+#define IMPMCR_PC1              (0x3 << 18) /* Bank 1 Power Control */
+#define IMPMCR_PC1_RUN_MODE     (0x0 << 18) /*   Run mode */
+#define IMPMCR_PC1_STANDBY_MODE (0x1 << 18) /*   Standby mode */
+#define IMPMCR_PC1_AUTO_MODE    (0x3 << 18) /*   Automatically controlled */
+
+#define IMPMCR_PC0              (0x3 << 16) /* Bank 0 Power Control */
+#define IMPMCR_PC0_RUN_MODE     (0x0 << 16) /*   Run mode */
+#define IMPMCR_PC0_STANDBY_MODE (0x1 << 16) /*   Standby mode */
+#define IMPMCR_PC0_AUTO_MODE    (0x3 << 16) /*   Automatically controlled */
+
+#define IMPMCR_AW3              (1 << 11) /* Bank 3 Automatic Wake-up enable */
+#define IMPMCR_AW2              (1 << 10) /* Bank 2 Automatic Wake-up enable */
+#define IMPMCR_AW1              (1 << 9)  /* Bank 1 Automatic Wake-up enable */
+#define IMPMCR_AW0              (1 << 8)  /* Bank 0 Automatic Wake-up enable */
+
+#define IMPMCR_DST              (0xFF << 0) /* Delay Standby Time, ms */
+
+#define IMPMSR_PS3              (0x3 << 6) /* Bank 3 Power Status: */
+#define IMPMSR_PS3_RUN_MODE     (0x0 << 6) /*    Run mode */
+#define IMPMSR_PS3_STANDBY_MODE (0x1 << 6) /*    Standby mode */
+
+#define IMPMSR_PS2              (0x3 << 4) /* Bank 2 Power Status: */
+#define IMPMSR_PS2_RUN_MODE     (0x0 << 4) /*    Run mode */
+#define IMPMSR_PS2_STANDBY_MODE (0x1 << 4) /*    Standby mode */
+
+#define IMPMSR_PS1              (0x3 << 2) /* Bank 1 Power Status: */
+#define IMPMSR_PS1_RUN_MODE     (0x0 << 2) /*    Run mode */
+#define IMPMSR_PS1_STANDBY_MODE (0x1 << 2) /*    Standby mode */
+
+#define IMPMSR_PS0              (0x3 << 0) /* Bank 0 Power Status: */
+#define IMPMSR_PS0_RUN_MODE     (0x0 << 0) /*    Run mode */
+#define IMPMSR_PS0_STANDBY_MODE (0x1 << 0) /*    Standby mode */
+
+#endif
+
+#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
+/*
+ * UHC: USB Host Controller (OHCI-like) register definitions
+ */
+#define UHC_BASE_PHYS   (0x4C000000)
+#define UHCREV          __REG(0x4C000000) /* UHC HCI Spec Revision */
+#define UHCHCON         __REG(0x4C000004) /* UHC Host Control Register */
+#define UHCCOMS         __REG(0x4C000008) /* UHC Command Status Register */
+#define UHCINTS         __REG(0x4C00000C) /* UHC Interrupt Status Register */
+#define UHCINTE         __REG(0x4C000010) /* UHC Interrupt Enable */
+#define UHCINTD         __REG(0x4C000014) /* UHC Interrupt Disable */
+#define UHCHCCA         __REG(0x4C000018) /* UHC Host Controller Comm. Area */
+#define UHCPCED         __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
+#define UHCCHED         __REG(0x4C000020) /* UHC Control Head Endpt Descr */
+#define UHCCCED         __REG(0x4C000024) /* UHC Control Current Endpt Descr */
+#define UHCBHED         __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
+#define UHCBCED         __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
+#define UHCDHEAD        __REG(0x4C000030) /* UHC Done Head */
+#define UHCFMI          __REG(0x4C000034) /* UHC Frame Interval */
+#define UHCFMR          __REG(0x4C000038) /* UHC Frame Remaining */
+#define UHCFMN          __REG(0x4C00003C) /* UHC Frame Number */
+#define UHCPERS         __REG(0x4C000040) /* UHC Periodic Start */
+#define UHCLS           __REG(0x4C000044) /* UHC Low Speed Threshold */
+
+#define UHCRHDA         __REG(0x4C000048) /* UHC Root Hub Descriptor A */
+#define UHCRHDA_NOCP    (1 << 12)       /* No over current protection */
+
+#define UHCRHDB         __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
+#define UHCRHS          __REG(0x4C000050) /* UHC Root Hub Status */
+#define UHCRHPS1        __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
+#define UHCRHPS2        __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
+#define UHCRHPS3        __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
+
+#define UHCSTAT         __REG(0x4C000060) /* UHC Status Register */
+#define UHCSTAT_UPS3    (1 << 16)       /* USB Power Sense Port3 */
+#define UHCSTAT_SBMAI   (1 << 15)       /* System Bus Master Abort Interrupt*/
+#define UHCSTAT_SBTAI   (1 << 14)       /* System Bus Target Abort Interrupt*/
+#define UHCSTAT_UPRI    (1 << 13)       /* USB Port Resume Interrupt */
+#define UHCSTAT_UPS2    (1 << 12)       /* USB Power Sense Port 2 */
+#define UHCSTAT_UPS1    (1 << 11)       /* USB Power Sense Port 1 */
+#define UHCSTAT_HTA     (1 << 10)       /* HCI Target Abort */
+#define UHCSTAT_HBA     (1 << 8)        /* HCI Buffer Active */
+#define UHCSTAT_RWUE    (1 << 7)        /* HCI Remote Wake Up Event */
+
+#define UHCHR           __REG(0x4C000064) /* UHC Reset Register */
+#define UHCHR_SSEP3     (1 << 11)       /* Sleep Standby Enable for Port3 */
+#define UHCHR_SSEP2     (1 << 10)       /* Sleep Standby Enable for Port2 */
+#define UHCHR_SSEP1     (1 << 9)        /* Sleep Standby Enable for Port1 */
+#define UHCHR_PCPL      (1 << 7)        /* Power control polarity low */
+#define UHCHR_PSPL      (1 << 6)        /* Power sense polarity low */
+#define UHCHR_SSE       (1 << 5)        /* Sleep Standby Enable */
+#define UHCHR_UIT       (1 << 4)        /* USB Interrupt Test */
+#define UHCHR_SSDC      (1 << 3)        /* Simulation Scale Down Clock */
+#define UHCHR_CGR       (1 << 2)        /* Clock Generation Reset */
+#define UHCHR_FHR       (1 << 1)        /* Force Host Controller Reset */
+#define UHCHR_FSBIR     (1 << 0)        /* Force System Bus Iface Reset */
+
+#define UHCHIE          __REG(0x4C000068) /* UHC Interrupt Enable Register*/
+#define UHCHIE_UPS3IE   (1 << 14)       /* Power Sense Port3 IntEn */
+#define UHCHIE_UPRIE    (1 << 13)       /* Port Resume IntEn */
+#define UHCHIE_UPS2IE   (1 << 12)       /* Power Sense Port2 IntEn */
+#define UHCHIE_UPS1IE   (1 << 11)       /* Power Sense Port1 IntEn */
+#define UHCHIE_TAIE     (1 << 10)       /* HCI Interface Transfer Abort
+                                           Interrupt Enable*/
+#define UHCHIE_HBAIE    (1 << 8)        /* HCI Buffer Active IntEn */
+#define UHCHIE_RWIE     (1 << 7)        /* Remote Wake-up IntEn */
+
+#define UHCHIT          __REG(0x4C00006C) /* UHC Interrupt Test register */
+
+#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
+
+/* PWRMODE register M field values */
+
+#define PWRMODE_IDLE            0x1
+#define PWRMODE_STANDBY         0x2
+#define PWRMODE_SLEEP           0x3
+#define PWRMODE_DEEPSLEEP       0x7
+
+#endif
diff --git a/include/asm-arm/arch-pxa/pxa25x-udc.h b/arch/arm/mach-pxa/include/mach/pxa25x-udc.h
index 1b80a4805a60..1b80a4805a60 100644
--- a/include/asm-arm/arch-pxa/pxa25x-udc.h
+++ b/arch/arm/mach-pxa/include/mach/pxa25x-udc.h
diff --git a/include/asm-arm/arch-pxa/pxa27x-udc.h b/arch/arm/mach-pxa/include/mach/pxa27x-udc.h
index ab1443f8bd89..ab1443f8bd89 100644
--- a/include/asm-arm/arch-pxa/pxa27x-udc.h
+++ b/arch/arm/mach-pxa/include/mach/pxa27x-udc.h
diff --git a/include/asm-arm/arch-pxa/pxa27x_keypad.h b/arch/arm/mach-pxa/include/mach/pxa27x_keypad.h
index d5a48a96dea7..d5a48a96dea7 100644
--- a/include/asm-arm/arch-pxa/pxa27x_keypad.h
+++ b/arch/arm/mach-pxa/include/mach/pxa27x_keypad.h
diff --git a/include/asm-arm/arch-pxa/pxa2xx-gpio.h b/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h
index 6ef1dd09970b..6ef1dd09970b 100644
--- a/include/asm-arm/arch-pxa/pxa2xx-gpio.h
+++ b/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
new file mode 100644
index 000000000000..806ecfea44bf
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
@@ -0,0 +1,246 @@
+/*
+ *  arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
+ *
+ *  Taken from pxa-regs.h by Russell King
+ *
+ *  Author:     Nicolas Pitre
+ *  Copyright:  MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __PXA2XX_REGS_H
+#define __PXA2XX_REGS_H
+
+/*
+ * Memory controller
+ */
+
+#define MDCNFG          __REG(0x48000000)  /* SDRAM Configuration Register 0 */
+#define MDREFR          __REG(0x48000004)  /* SDRAM Refresh Control Register */
+#define MSC0            __REG(0x48000008)  /* Static Memory Control Register 0 */
+#define MSC1            __REG(0x4800000C)  /* Static Memory Control Register 1 */
+#define MSC2            __REG(0x48000010)  /* Static Memory Control Register 2 */
+#define MECR            __REG(0x48000014)  /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
+#define SXLCR           __REG(0x48000018)  /* LCR value to be written to SDRAM-Timing Synchronous Flash */
+#define SXCNFG          __REG(0x4800001C)  /* Synchronous Static Memory Control Register */
+#define SXMRS           __REG(0x48000024)  /* MRS value to be written to Synchronous Flash or SMROM */
+#define MCMEM0          __REG(0x48000028)  /* Card interface Common Memory Space Socket 0 Timing */
+#define MCMEM1          __REG(0x4800002C)  /* Card interface Common Memory Space Socket 1 Timing */
+#define MCATT0          __REG(0x48000030)  /* Card interface Attribute Space Socket 0 Timing Configuration */
+#define MCATT1          __REG(0x48000034)  /* Card interface Attribute Space Socket 1 Timing Configuration */
+#define MCIO0           __REG(0x48000038)  /* Card interface I/O Space Socket 0 Timing Configuration */
+#define MCIO1           __REG(0x4800003C)  /* Card interface I/O Space Socket 1 Timing Configuration */
+#define MDMRS           __REG(0x48000040)  /* MRS value to be written to SDRAM */
+#define BOOT_DEF        __REG(0x48000044)  /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
+
+/*
+ * More handy macros for PCMCIA
+ *
+ * Arg is socket number
+ */
+#define MCMEM(s)        __REG2(0x48000028, (s)<<2 )  /* Card interface Common Memory Space Socket s Timing */
+#define MCATT(s)        __REG2(0x48000030, (s)<<2 )  /* Card interface Attribute Space Socket s Timing Configuration */
+#define MCIO(s)         __REG2(0x48000038, (s)<<2 )  /* Card interface I/O Space Socket s Timing Configuration */
+
+/* MECR register defines */
+#define MECR_NOS        (1 << 0)        /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
+#define MECR_CIT        (1 << 1)        /* Card Is There: 0 -> no card, 1 -> card inserted */
+
+#define MDREFR_K0DB4    (1 << 29)       /* SDCLK0 Divide by 4 Control/Status */
+#define MDREFR_K2FREE   (1 << 25)       /* SDRAM Free-Running Control */
+#define MDREFR_K1FREE   (1 << 24)       /* SDRAM Free-Running Control */
+#define MDREFR_K0FREE   (1 << 23)       /* SDRAM Free-Running Control */
+#define MDREFR_SLFRSH   (1 << 22)       /* SDRAM Self-Refresh Control/Status */
+#define MDREFR_APD      (1 << 20)       /* SDRAM/SSRAM Auto-Power-Down Enable */
+#define MDREFR_K2DB2    (1 << 19)       /* SDCLK2 Divide by 2 Control/Status */
+#define MDREFR_K2RUN    (1 << 18)       /* SDCLK2 Run Control/Status */
+#define MDREFR_K1DB2    (1 << 17)       /* SDCLK1 Divide by 2 Control/Status */
+#define MDREFR_K1RUN    (1 << 16)       /* SDCLK1 Run Control/Status */
+#define MDREFR_E1PIN    (1 << 15)       /* SDCKE1 Level Control/Status */
+#define MDREFR_K0DB2    (1 << 14)       /* SDCLK0 Divide by 2 Control/Status */
+#define MDREFR_K0RUN    (1 << 13)       /* SDCLK0 Run Control/Status */
+#define MDREFR_E0PIN    (1 << 12)       /* SDCKE0 Level Control/Status */
+
+
+#ifdef CONFIG_PXA27x
+
+#define ARB_CNTRL       __REG(0x48000048)  /* Arbiter Control Register */
+
+#define ARB_DMA_SLV_PARK        (1<<31)    /* Be parked with DMA slave when idle */
+#define ARB_CI_PARK             (1<<30)    /* Be parked with Camera Interface when idle */
+#define ARB_EX_MEM_PARK         (1<<29)    /* Be parked with external MEMC when idle */
+#define ARB_INT_MEM_PARK        (1<<28)    /* Be parked with internal MEMC when idle */
+#define ARB_USB_PARK            (1<<27)    /* Be parked with USB when idle */
+#define ARB_LCD_PARK            (1<<26)    /* Be parked with LCD when idle */
+#define ARB_DMA_PARK            (1<<25)    /* Be parked with DMA when idle */
+#define ARB_CORE_PARK           (1<<24)    /* Be parked with core when idle */
+#define ARB_LOCK_FLAG           (1<<23)    /* Only Locking masters gain access to the bus */
+
+#endif
+
+
+/*
+ * Power Manager
+ */
+
+#define PMCR            __REG(0x40F00000)  /* Power Manager Control Register */
+#define PSSR            __REG(0x40F00004)  /* Power Manager Sleep Status Register */
+#define PSPR            __REG(0x40F00008)  /* Power Manager Scratch Pad Register */
+#define PWER            __REG(0x40F0000C)  /* Power Manager Wake-up Enable Register */
+#define PRER            __REG(0x40F00010)  /* Power Manager GPIO Rising-Edge Detect Enable Register */
+#define PFER            __REG(0x40F00014)  /* Power Manager GPIO Falling-Edge Detect Enable Register */
+#define PEDR            __REG(0x40F00018)  /* Power Manager GPIO Edge Detect Status Register */
+#define PCFR            __REG(0x40F0001C)  /* Power Manager General Configuration Register */
+#define PGSR0           __REG(0x40F00020)  /* Power Manager GPIO Sleep State Register for GP[31-0] */
+#define PGSR1           __REG(0x40F00024)  /* Power Manager GPIO Sleep State Register for GP[63-32] */
+#define PGSR2           __REG(0x40F00028)  /* Power Manager GPIO Sleep State Register for GP[84-64] */
+#define PGSR3           __REG(0x40F0002C)  /* Power Manager GPIO Sleep State Register for GP[118-96] */
+#define RCSR            __REG(0x40F00030)  /* Reset Controller Status Register */
+
+#define PSLR            __REG(0x40F00034)       /* Power Manager Sleep Config Register */
+#define PSTR            __REG(0x40F00038)       /* Power Manager Standby Config Register */
+#define PSNR            __REG(0x40F0003C)       /* Power Manager Sense Config Register */
+#define PVCR            __REG(0x40F00040)       /* Power Manager VoltageControl Register */
+#define PKWR            __REG(0x40F00050)       /* Power Manager KB Wake-up Enable Reg */
+#define PKSR            __REG(0x40F00054)       /* Power Manager KB Level-Detect Register */
+#define PCMD(x) __REG2(0x40F00080, (x)<<2)
+#define PCMD0   __REG(0x40F00080 + 0 * 4)
+#define PCMD1   __REG(0x40F00080 + 1 * 4)
+#define PCMD2   __REG(0x40F00080 + 2 * 4)
+#define PCMD3   __REG(0x40F00080 + 3 * 4)
+#define PCMD4   __REG(0x40F00080 + 4 * 4)
+#define PCMD5   __REG(0x40F00080 + 5 * 4)
+#define PCMD6   __REG(0x40F00080 + 6 * 4)
+#define PCMD7   __REG(0x40F00080 + 7 * 4)
+#define PCMD8   __REG(0x40F00080 + 8 * 4)
+#define PCMD9   __REG(0x40F00080 + 9 * 4)
+#define PCMD10  __REG(0x40F00080 + 10 * 4)
+#define PCMD11  __REG(0x40F00080 + 11 * 4)
+#define PCMD12  __REG(0x40F00080 + 12 * 4)
+#define PCMD13  __REG(0x40F00080 + 13 * 4)
+#define PCMD14  __REG(0x40F00080 + 14 * 4)
+#define PCMD15  __REG(0x40F00080 + 15 * 4)
+#define PCMD16  __REG(0x40F00080 + 16 * 4)
+#define PCMD17  __REG(0x40F00080 + 17 * 4)
+#define PCMD18  __REG(0x40F00080 + 18 * 4)
+#define PCMD19  __REG(0x40F00080 + 19 * 4)
+#define PCMD20  __REG(0x40F00080 + 20 * 4)
+#define PCMD21  __REG(0x40F00080 + 21 * 4)
+#define PCMD22  __REG(0x40F00080 + 22 * 4)
+#define PCMD23  __REG(0x40F00080 + 23 * 4)
+#define PCMD24  __REG(0x40F00080 + 24 * 4)
+#define PCMD25  __REG(0x40F00080 + 25 * 4)
+#define PCMD26  __REG(0x40F00080 + 26 * 4)
+#define PCMD27  __REG(0x40F00080 + 27 * 4)
+#define PCMD28  __REG(0x40F00080 + 28 * 4)
+#define PCMD29  __REG(0x40F00080 + 29 * 4)
+#define PCMD30  __REG(0x40F00080 + 30 * 4)
+#define PCMD31  __REG(0x40F00080 + 31 * 4)
+
+#define PCMD_MBC        (1<<12)
+#define PCMD_DCE        (1<<11)
+#define PCMD_LC (1<<10)
+/* FIXME:  PCMD_SQC need be checked.   */
+#define PCMD_SQC        (3<<8)  /* currently only bit 8 is changeable,
+                                   bit 9 should be 0 all day. */
+#define PVCR_VCSA       (0x1<<14)
+#define PVCR_CommandDelay (0xf80)
+#define PCFR_PI2C_EN    (0x1 << 6)
+
+#define PSSR_OTGPH      (1 << 6)        /* OTG Peripheral control Hold */
+#define PSSR_RDH        (1 << 5)        /* Read Disable Hold */
+#define PSSR_PH         (1 << 4)        /* Peripheral Control Hold */
+#define PSSR_STS        (1 << 3)        /* Standby Mode Status */
+#define PSSR_VFS        (1 << 2)        /* VDD Fault Status */
+#define PSSR_BFS        (1 << 1)        /* Battery Fault Status */
+#define PSSR_SSS        (1 << 0)        /* Software Sleep Status */
+
+#define PSLR_SL_ROD     (1 << 20)       /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
+
+#define PCFR_RO         (1 << 15)       /* RDH Override */
+#define PCFR_PO         (1 << 14)       /* PH Override */
+#define PCFR_GPROD      (1 << 12)       /* GPIO nRESET_OUT Disable */
+#define PCFR_L1_EN      (1 << 11)       /* Sleep Mode L1 converter Enable */
+#define PCFR_FVC        (1 << 10)       /* Frequency/Voltage Change */
+#define PCFR_DC_EN      (1 << 7)        /* Sleep/deep-sleep DC-DC Converter Enable */
+#define PCFR_PI2CEN     (1 << 6)        /* Enable PI2C controller */
+#define PCFR_GPR_EN     (1 << 4)        /* nRESET_GPIO Pin Enable */
+#define PCFR_DS         (1 << 3)        /* Deep Sleep Mode */
+#define PCFR_FS         (1 << 2)        /* Float Static Chip Selects */
+#define PCFR_FP         (1 << 1)        /* Float PCMCIA controls */
+#define PCFR_OPDE       (1 << 0)        /* 3.6864 MHz oscillator power-down enable */
+
+#define RCSR_GPR        (1 << 3)        /* GPIO Reset */
+#define RCSR_SMR        (1 << 2)        /* Sleep Mode */
+#define RCSR_WDR        (1 << 1)        /* Watchdog Reset */
+#define RCSR_HWR        (1 << 0)        /* Hardware Reset */
+
+#define PWER_GPIO(Nb)   (1 << Nb)       /* GPIO [0..15] wake-up enable     */
+#define PWER_GPIO0      PWER_GPIO (0)   /* GPIO  [0] wake-up enable        */
+#define PWER_GPIO1      PWER_GPIO (1)   /* GPIO  [1] wake-up enable        */
+#define PWER_GPIO2      PWER_GPIO (2)   /* GPIO  [2] wake-up enable        */
+#define PWER_GPIO3      PWER_GPIO (3)   /* GPIO  [3] wake-up enable        */
+#define PWER_GPIO4      PWER_GPIO (4)   /* GPIO  [4] wake-up enable        */
+#define PWER_GPIO5      PWER_GPIO (5)   /* GPIO  [5] wake-up enable        */
+#define PWER_GPIO6      PWER_GPIO (6)   /* GPIO  [6] wake-up enable        */
+#define PWER_GPIO7      PWER_GPIO (7)   /* GPIO  [7] wake-up enable        */
+#define PWER_GPIO8      PWER_GPIO (8)   /* GPIO  [8] wake-up enable        */
+#define PWER_GPIO9      PWER_GPIO (9)   /* GPIO  [9] wake-up enable        */
+#define PWER_GPIO10     PWER_GPIO (10)  /* GPIO [10] wake-up enable        */
+#define PWER_GPIO11     PWER_GPIO (11)  /* GPIO [11] wake-up enable        */
+#define PWER_GPIO12     PWER_GPIO (12)  /* GPIO [12] wake-up enable        */
+#define PWER_GPIO13     PWER_GPIO (13)  /* GPIO [13] wake-up enable        */
+#define PWER_GPIO14     PWER_GPIO (14)  /* GPIO [14] wake-up enable        */
+#define PWER_GPIO15     PWER_GPIO (15)  /* GPIO [15] wake-up enable        */
+#define PWER_RTC        0x80000000      /* RTC alarm wake-up enable        */
+
+/*
+ * PXA2xx specific Core clock definitions
+ */
+#define CCCR            __REG(0x41300000)  /* Core Clock Configuration Register */
+#define CCSR            __REG(0x4130000C)  /* Core Clock Status Register */
+#define CKEN            __REG(0x41300004)  /* Clock Enable Register */
+#define OSCC            __REG(0x41300008)  /* Oscillator Configuration Register */
+
+#define CCCR_N_MASK     0x0380  /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
+#define CCCR_M_MASK     0x0060  /* Memory Frequency to Run Mode Frequency Multiplier */
+#define CCCR_L_MASK     0x001f  /* Crystal Frequency to Memory Frequency Multiplier */
+
+#define CKEN_AC97CONF   (31)    /* AC97 Controller Configuration */
+#define CKEN_CAMERA     (24)    /* Camera Interface Clock Enable */
+#define CKEN_SSP1       (23)    /* SSP1 Unit Clock Enable */
+#define CKEN_MEMC       (22)    /* Memory Controller Clock Enable */
+#define CKEN_MEMSTK     (21)    /* Memory Stick Host Controller */
+#define CKEN_IM         (20)    /* Internal Memory Clock Enable */
+#define CKEN_KEYPAD     (19)    /* Keypad Interface Clock Enable */
+#define CKEN_USIM       (18)    /* USIM Unit Clock Enable */
+#define CKEN_MSL        (17)    /* MSL Unit Clock Enable */
+#define CKEN_LCD        (16)    /* LCD Unit Clock Enable */
+#define CKEN_PWRI2C     (15)    /* PWR I2C Unit Clock Enable */
+#define CKEN_I2C        (14)    /* I2C Unit Clock Enable */
+#define CKEN_FICP       (13)    /* FICP Unit Clock Enable */
+#define CKEN_MMC        (12)    /* MMC Unit Clock Enable */
+#define CKEN_USB        (11)    /* USB Unit Clock Enable */
+#define CKEN_ASSP       (10)    /* ASSP (SSP3) Clock Enable */
+#define CKEN_USBHOST    (10)    /* USB Host Unit Clock Enable */
+#define CKEN_OSTIMER    (9)     /* OS Timer Unit Clock Enable */
+#define CKEN_NSSP       (9)     /* NSSP (SSP2) Clock Enable */
+#define CKEN_I2S        (8)     /* I2S Unit Clock Enable */
+#define CKEN_BTUART     (7)     /* BTUART Unit Clock Enable */
+#define CKEN_FFUART     (6)     /* FFUART Unit Clock Enable */
+#define CKEN_STUART     (5)     /* STUART Unit Clock Enable */
+#define CKEN_HWUART     (4)     /* HWUART Unit Clock Enable */
+#define CKEN_SSP3       (4)     /* SSP3 Unit Clock Enable */
+#define CKEN_SSP        (3)     /* SSP Unit Clock Enable */
+#define CKEN_SSP2       (3)     /* SSP2 Unit Clock Enable */
+#define CKEN_AC97       (2)     /* AC97 Unit Clock Enable */
+#define CKEN_PWM1       (1)     /* PWM1 Clock Enable */
+#define CKEN_PWM0       (0)     /* PWM0 Clock Enable */
+
+#define OSCC_OON        (1 << 1)        /* 32.768kHz OON (write-once only bit) */
+#define OSCC_OOK        (1 << 0)        /* 32.768kHz OOK (read-only bit) */
+
+#endif
diff --git a/include/asm-arm/arch-pxa/pxa2xx_spi.h b/arch/arm/mach-pxa/include/mach/pxa2xx_spi.h
index 2206cb61a9f9..2206cb61a9f9 100644
--- a/include/asm-arm/arch-pxa/pxa2xx_spi.h
+++ b/arch/arm/mach-pxa/include/mach/pxa2xx_spi.h
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
new file mode 100644
index 000000000000..39eb68319e28
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
@@ -0,0 +1,183 @@
+/*
+ * arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
+ *
+ * PXA3xx specific register definitions
+ *
+ * Copyright (C) 2007 Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_PXA3XX_REGS_H
+#define __ASM_ARCH_PXA3XX_REGS_H
+
+/*
+ * Oscillator Configuration Register (OSCC)
+ */
+#define OSCC           __REG(0x41350000)  /* Oscillator Configuration Register */
+
+#define OSCC_PEN       (1 << 11)       /* 13MHz POUT */
+
+
+/*
+ * Service Power Management Unit (MPMU)
+ */
+#define PMCR            __REG(0x40F50000)       /* Power Manager Control Register */
+#define PSR             __REG(0x40F50004)       /* Power Manager S2 Status Register */
+#define PSPR            __REG(0x40F50008)       /* Power Manager Scratch Pad Register */
+#define PCFR            __REG(0x40F5000C)       /* Power Manager General Configuration Register */
+#define PWER            __REG(0x40F50010)       /* Power Manager Wake-up Enable Register */
+#define PWSR            __REG(0x40F50014)       /* Power Manager Wake-up Status Register */
+#define PECR            __REG(0x40F50018)       /* Power Manager EXT_WAKEUP[1:0] Control Register */
+#define DCDCSR          __REG(0x40F50080)       /* DC-DC Controller Status Register */
+#define PVCR            __REG(0x40F50100)       /* Power Manager Voltage Change Control Register */
+#define PCMD(x)         __REG(0x40F50110 + ((x) << 2))
+
+/*
+ * Slave Power Managment Unit
+ */
+#define ASCR            __REG(0x40f40000)       /* Application Subsystem Power Status/Configuration */
+#define ARSR            __REG(0x40f40004)       /* Application Subsystem Reset Status */
+#define AD3ER           __REG(0x40f40008)       /* Application Subsystem Wake-Up from D3 Enable */
+#define AD3SR           __REG(0x40f4000c)       /* Application Subsystem Wake-Up from D3 Status */
+#define AD2D0ER         __REG(0x40f40010)       /* Application Subsystem Wake-Up from D2 to D0 Enable */
+#define AD2D0SR         __REG(0x40f40014)       /* Application Subsystem Wake-Up from D2 to D0 Status */
+#define AD2D1ER         __REG(0x40f40018)       /* Application Subsystem Wake-Up from D2 to D1 Enable */
+#define AD2D1SR         __REG(0x40f4001c)       /* Application Subsystem Wake-Up from D2 to D1 Status */
+#define AD1D0ER         __REG(0x40f40020)       /* Application Subsystem Wake-Up from D1 to D0 Enable */
+#define AD1D0SR         __REG(0x40f40024)       /* Application Subsystem Wake-Up from D1 to D0 Status */
+#define AGENP           __REG(0x40f4002c)       /* Application Subsystem General Purpose */
+#define AD3R            __REG(0x40f40030)       /* Application Subsystem D3 Configuration */
+#define AD2R            __REG(0x40f40034)       /* Application Subsystem D2 Configuration */
+#define AD1R            __REG(0x40f40038)       /* Application Subsystem D1 Configuration */
+
+/*
+ * Application Subsystem Configuration bits.
+ */
+#define ASCR_RDH                (1 << 31)
+#define ASCR_D1S                (1 << 2)
+#define ASCR_D2S                (1 << 1)
+#define ASCR_D3S                (1 << 0)
+
+/*
+ * Application Reset Status bits.
+ */
+#define ARSR_GPR                (1 << 3)
+#define ARSR_LPMR               (1 << 2)
+#define ARSR_WDT                (1 << 1)
+#define ARSR_HWR                (1 << 0)
+
+/*
+ * Application Subsystem Wake-Up bits.
+ */
+#define ADXER_WRTC              (1 << 31)       /* RTC */
+#define ADXER_WOST              (1 << 30)       /* OS Timer */
+#define ADXER_WTSI              (1 << 29)       /* Touchscreen */
+#define ADXER_WUSBH             (1 << 28)       /* USB host */
+#define ADXER_WUSB2             (1 << 26)       /* USB client 2.0 */
+#define ADXER_WMSL0             (1 << 24)       /* MSL port 0*/
+#define ADXER_WDMUX3            (1 << 23)       /* USB EDMUX3 */
+#define ADXER_WDMUX2            (1 << 22)       /* USB EDMUX2 */
+#define ADXER_WKP               (1 << 21)       /* Keypad */
+#define ADXER_WUSIM1            (1 << 20)       /* USIM Port 1 */
+#define ADXER_WUSIM0            (1 << 19)       /* USIM Port 0 */
+#define ADXER_WOTG              (1 << 16)       /* USBOTG input */
+#define ADXER_MFP_WFLASH        (1 << 15)       /* MFP: Data flash busy */
+#define ADXER_MFP_GEN12         (1 << 14)       /* MFP: MMC3/GPIO/OST inputs */
+#define ADXER_MFP_WMMC2         (1 << 13)       /* MFP: MMC2 */
+#define ADXER_MFP_WMMC1         (1 << 12)       /* MFP: MMC1 */
+#define ADXER_MFP_WI2C          (1 << 11)       /* MFP: I2C */
+#define ADXER_MFP_WSSP4         (1 << 10)       /* MFP: SSP4 */
+#define ADXER_MFP_WSSP3         (1 << 9)        /* MFP: SSP3 */
+#define ADXER_MFP_WMAXTRIX      (1 << 8)        /* MFP: matrix keypad */
+#define ADXER_MFP_WUART3        (1 << 7)        /* MFP: UART3 */
+#define ADXER_MFP_WUART2        (1 << 6)        /* MFP: UART2 */
+#define ADXER_MFP_WUART1        (1 << 5)        /* MFP: UART1 */
+#define ADXER_MFP_WSSP2         (1 << 4)        /* MFP: SSP2 */
+#define ADXER_MFP_WSSP1         (1 << 3)        /* MFP: SSP1 */
+#define ADXER_MFP_WAC97         (1 << 2)        /* MFP: AC97 */
+#define ADXER_WEXTWAKE1         (1 << 1)        /* External Wake 1 */
+#define ADXER_WEXTWAKE0         (1 << 0)        /* External Wake 0 */
+
+/*
+ * AD3R/AD2R/AD1R bits.  R2-R5 are only defined for PXA320.
+ */
+#define ADXR_L2                 (1 << 8)
+#define ADXR_R5                 (1 << 5)
+#define ADXR_R4                 (1 << 4)
+#define ADXR_R3                 (1 << 3)
+#define ADXR_R2                 (1 << 2)
+#define ADXR_R1                 (1 << 1)
+#define ADXR_R0                 (1 << 0)
+
+/*
+ * Values for PWRMODE CP15 register
+ */
+#define PXA3xx_PM_S3D4C4        0x07    /* aka deep sleep */
+#define PXA3xx_PM_S2D3C4        0x06    /* aka sleep */
+#define PXA3xx_PM_S0D2C2        0x03    /* aka standby */
+#define PXA3xx_PM_S0D1C2        0x02    /* aka LCD refresh */
+#define PXA3xx_PM_S0D0C1        0x01
+
+/*
+ * Application Subsystem Clock
+ */
+#define ACCR            __REG(0x41340000)       /* Application Subsystem Clock Configuration Register */
+#define ACSR            __REG(0x41340004)       /* Application Subsystem Clock Status Register */
+#define AICSR           __REG(0x41340008)       /* Application Subsystem Interrupt Control/Status Register */
+#define CKENA           __REG(0x4134000C)       /* A Clock Enable Register */
+#define CKENB           __REG(0x41340010)       /* B Clock Enable Register */
+#define AC97_DIV        __REG(0x41340014)       /* AC97 clock divisor value register */
+
+/*
+ * Clock Enable Bit
+ */
+#define CKEN_LCD        1       /* < LCD Clock Enable */
+#define CKEN_USBH       2       /* < USB host clock enable */
+#define CKEN_CAMERA     3       /* < Camera interface clock enable */
+#define CKEN_NAND       4       /* < NAND Flash Controller Clock Enable */
+#define CKEN_USB2       6       /* < USB 2.0 client clock enable. */
+#define CKEN_DMC        8       /* < Dynamic Memory Controller clock enable */
+#define CKEN_SMC        9       /* < Static Memory Controller clock enable */
+#define CKEN_ISC        10      /* < Internal SRAM Controller clock enable */
+#define CKEN_BOOT       11      /* < Boot rom clock enable */
+#define CKEN_MMC1       12      /* < MMC1 Clock enable */
+#define CKEN_MMC2       13      /* < MMC2 clock enable */
+#define CKEN_KEYPAD     14      /* < Keypand Controller Clock Enable */
+#define CKEN_CIR        15      /* < Consumer IR Clock Enable */
+#define CKEN_USIM0      17      /* < USIM[0] Clock Enable */
+#define CKEN_USIM1      18      /* < USIM[1] Clock Enable */
+#define CKEN_TPM        19      /* < TPM clock enable */
+#define CKEN_UDC        20      /* < UDC clock enable */
+#define CKEN_BTUART     21      /* < BTUART clock enable */
+#define CKEN_FFUART     22      /* < FFUART clock enable */
+#define CKEN_STUART     23      /* < STUART clock enable */
+#define CKEN_AC97       24      /* < AC97 clock enable */
+#define CKEN_TOUCH      25      /* < Touch screen Interface Clock Enable */
+#define CKEN_SSP1       26      /* < SSP1 clock enable */
+#define CKEN_SSP2       27      /* < SSP2 clock enable */
+#define CKEN_SSP3       28      /* < SSP3 clock enable */
+#define CKEN_SSP4       29      /* < SSP4 clock enable */
+#define CKEN_MSL0       30      /* < MSL0 clock enable */
+#define CKEN_PWM0       32      /* < PWM[0] clock enable */
+#define CKEN_PWM1       33      /* < PWM[1] clock enable */
+#define CKEN_I2C        36      /* < I2C clock enable */
+#define CKEN_INTC       38      /* < Interrupt controller clock enable */
+#define CKEN_GPIO       39      /* < GPIO clock enable */
+#define CKEN_1WIRE      40      /* < 1-wire clock enable */
+#define CKEN_HSIO2      41      /* < HSIO2 clock enable */
+#define CKEN_MINI_IM    48      /* < Mini-IM */
+#define CKEN_MINI_LCD   49      /* < Mini LCD */
+
+#if defined(CONFIG_CPU_PXA310)
+#define CKEN_MMC3       5       /* < MMC3 Clock Enable */
+#define CKEN_MVED       43      /* < MVED clock enable */
+#endif
+
+/* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */
+#define PXA300_CKEN_GRAPHICS    42      /* Graphics controller clock enable */
+#define PXA320_CKEN_GRAPHICS    7       /* Graphics controller clock enable */
+
+#endif /* __ASM_ARCH_PXA3XX_REGS_H */
diff --git a/include/asm-arm/arch-pxa/pxa3xx_nand.h b/arch/arm/mach-pxa/include/mach/pxa3xx_nand.h
index eb4b190b6657..eb4b190b6657 100644
--- a/include/asm-arm/arch-pxa/pxa3xx_nand.h
+++ b/arch/arm/mach-pxa/include/mach/pxa3xx_nand.h
diff --git a/arch/arm/mach-pxa/include/mach/pxafb.h b/arch/arm/mach-pxa/include/mach/pxafb.h
new file mode 100644
index 000000000000..65447549616f
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/pxafb.h
@@ -0,0 +1,151 @@
+/*
+ *  arch/arm/mach-pxa/include/mach/pxafb.h
+ *
+ *  Support for the xscale frame buffer.
+ *
+ *  Author:     Jean-Frederic Clere
+ *  Created:    Sep 22, 2003
+ *  Copyright:  jfclere@sinix.net
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#include <linux/fb.h>
+#include <mach/regs-lcd.h>
+
+/*
+ * Supported LCD connections
+ *
+ * bits 0 - 3: for LCD panel type:
+ *
+ *   STN  - for passive matrix
+ *   DSTN - for dual scan passive matrix
+ *   TFT  - for active matrix
+ *
+ * bits 4 - 9 : for bus width
+ * bits 10-17 : for AC Bias Pin Frequency
+ * bit     18 : for output enable polarity
+ * bit     19 : for pixel clock edge
+ */
+#define LCD_CONN_TYPE(_x)       ((_x) & 0x0f)
+#define LCD_CONN_WIDTH(_x)      (((_x) >> 4) & 0x1f)
+
+#define LCD_TYPE_UNKNOWN        0
+#define LCD_TYPE_MONO_STN       1
+#define LCD_TYPE_MONO_DSTN      2
+#define LCD_TYPE_COLOR_STN      3
+#define LCD_TYPE_COLOR_DSTN     4
+#define LCD_TYPE_COLOR_TFT      5
+#define LCD_TYPE_SMART_PANEL    6
+#define LCD_TYPE_MAX            7
+
+#define LCD_MONO_STN_4BPP       ((4  << 4) | LCD_TYPE_MONO_STN)
+#define LCD_MONO_STN_8BPP       ((8  << 4) | LCD_TYPE_MONO_STN)
+#define LCD_MONO_DSTN_8BPP      ((8  << 4) | LCD_TYPE_MONO_DSTN)
+#define LCD_COLOR_STN_8BPP      ((8  << 4) | LCD_TYPE_COLOR_STN)
+#define LCD_COLOR_DSTN_16BPP    ((16 << 4) | LCD_TYPE_COLOR_DSTN)
+#define LCD_COLOR_TFT_16BPP     ((16 << 4) | LCD_TYPE_COLOR_TFT)
+#define LCD_COLOR_TFT_18BPP     ((18 << 4) | LCD_TYPE_COLOR_TFT)
+#define LCD_SMART_PANEL_8BPP    ((8  << 4) | LCD_TYPE_SMART_PANEL)
+#define LCD_SMART_PANEL_16BPP   ((16 << 4) | LCD_TYPE_SMART_PANEL)
+#define LCD_SMART_PANEL_18BPP   ((18 << 4) | LCD_TYPE_SMART_PANEL)
+
+#define LCD_AC_BIAS_FREQ(x)     (((x) & 0xff) << 10)
+#define LCD_BIAS_ACTIVE_HIGH    (0 << 17)
+#define LCD_BIAS_ACTIVE_LOW     (1 << 17)
+#define LCD_PCLK_EDGE_RISE      (0 << 18)
+#define LCD_PCLK_EDGE_FALL      (1 << 18)
+
+/*
+ * This structure describes the machine which we are running on.
+ * It is set in linux/arch/arm/mach-pxa/machine_name.c and used in the probe routine
+ * of linux/drivers/video/pxafb.c
+ */
+struct pxafb_mode_info {
+        u_long          pixclock;
+
+        u_short         xres;
+        u_short         yres;
+
+        u_char          bpp;
+        u_int           cmap_greyscale:1,
+                        depth:8,
+                        unused:23;
+
+        /* Parallel Mode Timing */
+        u_char          hsync_len;
+        u_char          left_margin;
+        u_char          right_margin;
+
+        u_char          vsync_len;
+        u_char          upper_margin;
+        u_char          lower_margin;
+        u_char          sync;
+
+        /* Smart Panel Mode Timing - see PXA27x DM 7.4.15.0.3 for details
+         * Note:
+         * 1. all parameters in nanosecond (ns)
+         * 2. a0cs{rd,wr}_set_hld are controlled by the same register bits
+         *    in pxa27x and pxa3xx, initialize them to the same value or
+         *    the larger one will be used
+         * 3. same to {rd,wr}_pulse_width
+         */
+        unsigned        a0csrd_set_hld; /* A0 and CS Setup/Hold Time before/after L_FCLK_RD */
+        unsigned        a0cswr_set_hld; /* A0 and CS Setup/Hold Time before/after L_PCLK_WR */
+        unsigned        wr_pulse_width; /* L_PCLK_WR pulse width */
+        unsigned        rd_pulse_width; /* L_FCLK_RD pulse width */
+        unsigned        cmd_inh_time;   /* Command Inhibit time between two writes */
+        unsigned        op_hold_time;   /* Output Hold time from L_FCLK_RD negation */
+};
+
+struct pxafb_mach_info {
+        struct pxafb_mode_info *modes;
+        unsigned int num_modes;
+
+        unsigned int    lcd_conn;
+
+        u_int           fixed_modes:1,
+                        cmap_inverse:1,
+                        cmap_static:1,
+                        unused:29;
+
+        /* The following should be defined in LCCR0
+         *      LCCR0_Act or LCCR0_Pas          Active or Passive
+         *      LCCR0_Sngl or LCCR0_Dual        Single/Dual panel
+         *      LCCR0_Mono or LCCR0_Color       Mono/Color
+         *      LCCR0_4PixMono or LCCR0_8PixMono (in mono single mode)
+         *      LCCR0_DMADel(Tcpu) (optional)   DMA request delay
+         *
+         * The following should not be defined in LCCR0:
+         *      LCCR0_OUM, LCCR0_BM, LCCR0_QDM, LCCR0_DIS, LCCR0_EFM
+         *      LCCR0_IUM, LCCR0_SFM, LCCR0_LDM, LCCR0_ENB
+         */
+        u_int           lccr0;
+        /* The following should be defined in LCCR3
+         *      LCCR3_OutEnH or LCCR3_OutEnL    Output enable polarity
+         *      LCCR3_PixRsEdg or LCCR3_PixFlEdg Pixel clock edge type
+         *      LCCR3_Acb(X)                    AB Bias pin frequency
+         *      LCCR3_DPC (optional)            Double Pixel Clock mode (untested)
+         *
+         * The following should not be defined in LCCR3
+         *      LCCR3_HSP, LCCR3_VSP, LCCR0_Pcd(x), LCCR3_Bpp
+         */
+        u_int           lccr3;
+        /* The following should be defined in LCCR4
+         *      LCCR4_PAL_FOR_0 or LCCR4_PAL_FOR_1 or LCCR4_PAL_FOR_2
+         *
+         * All other bits in LCCR4 should be left alone.
+         */
+        u_int           lccr4;
+        void (*pxafb_backlight_power)(int);
+        void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
+        void (*smart_update)(struct fb_info *);
+};
+void set_pxa_fb_info(struct pxafb_mach_info *hard_pxa_fb_info);
+void set_pxa_fb_parent(struct device *parent_dev);
+unsigned long pxafb_get_hsync_time(struct device *dev);
+
+extern int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int);
+extern int pxafb_smart_flush(struct fb_info *info);
diff --git a/arch/arm/mach-pxa/include/mach/regs-lcd.h b/arch/arm/mach-pxa/include/mach/regs-lcd.h
new file mode 100644
index 000000000000..c689c4ea769c
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/regs-lcd.h
@@ -0,0 +1,180 @@
+#ifndef __ASM_ARCH_REGS_LCD_H
+#define __ASM_ARCH_REGS_LCD_H
+
+#include <mach/bitfield.h>
+
+/*
+ * LCD Controller Registers and Bits Definitions
+ */
+#define LCCR0           (0x000) /* LCD Controller Control Register 0 */
+#define LCCR1           (0x004) /* LCD Controller Control Register 1 */
+#define LCCR2           (0x008) /* LCD Controller Control Register 2 */
+#define LCCR3           (0x00C) /* LCD Controller Control Register 3 */
+#define LCCR4           (0x010) /* LCD Controller Control Register 4 */
+#define LCCR5           (0x014) /* LCD Controller Control Register 5 */
+#define DFBR0           (0x020) /* DMA Channel 0 Frame Branch Register */
+#define DFBR1           (0x024) /* DMA Channel 1 Frame Branch Register */
+#define LCSR            (0x038) /* LCD Controller Status Register */
+#define LIIDR           (0x03C) /* LCD Controller Interrupt ID Register */
+#define TMEDRGBR        (0x040) /* TMED RGB Seed Register */
+#define TMEDCR          (0x044) /* TMED Control Register */
+
+#define CMDCR           (0x100) /* Command Control Register */
+#define PRSR            (0x104) /* Panel Read Status Register */
+
+#define LCCR3_1BPP      (0 << 24)
+#define LCCR3_2BPP      (1 << 24)
+#define LCCR3_4BPP      (2 << 24)
+#define LCCR3_8BPP      (3 << 24)
+#define LCCR3_16BPP     (4 << 24)
+#define LCCR3_18BPP     (5 << 24)
+#define LCCR3_18BPP_P   (6 << 24)
+#define LCCR3_19BPP     (7 << 24)
+#define LCCR3_19BPP_P   (1 << 29)
+#define LCCR3_24BPP     ((1 << 29) | (1 << 24))
+#define LCCR3_25BPP     ((1 << 29) | (2 << 24))
+
+#define LCCR3_PDFOR_0   (0 << 30)
+#define LCCR3_PDFOR_1   (1 << 30)
+#define LCCR3_PDFOR_2   (2 << 30)
+#define LCCR3_PDFOR_3   (3 << 30)
+
+#define LCCR4_PAL_FOR_0 (0 << 15)
+#define LCCR4_PAL_FOR_1 (1 << 15)
+#define LCCR4_PAL_FOR_2 (2 << 15)
+#define LCCR4_PAL_FOR_MASK      (3 << 15)
+
+#define FDADR0          (0x200) /* DMA Channel 0 Frame Descriptor Address Register */
+#define FSADR0          (0x204) /* DMA Channel 0 Frame Source Address Register */
+#define FIDR0           (0x208) /* DMA Channel 0 Frame ID Register */
+#define LDCMD0          (0x20C) /* DMA Channel 0 Command Register */
+#define FDADR1          (0x210) /* DMA Channel 1 Frame Descriptor Address Register */
+#define FSADR1          (0x214) /* DMA Channel 1 Frame Source Address Register */
+#define FIDR1           (0x218) /* DMA Channel 1 Frame ID Register */
+#define LDCMD1          (0x21C) /* DMA Channel 1 Command Register */
+#define FDADR6          (0x260) /* DMA Channel 6 Frame Descriptor Address Register */
+#define FSADR6          (0x264) /* DMA Channel 6 Frame Source Address Register */
+#define FIDR6           (0x268) /* DMA Channel 6 Frame ID Register */
+
+#define LCCR0_ENB       (1 << 0)        /* LCD Controller enable */
+#define LCCR0_CMS       (1 << 1)        /* Color/Monochrome Display Select */
+#define LCCR0_Color     (LCCR0_CMS*0)   /*  Color display */
+#define LCCR0_Mono      (LCCR0_CMS*1)   /*  Monochrome display */
+#define LCCR0_SDS       (1 << 2)        /* Single/Dual Panel Display Select */
+#define LCCR0_Sngl      (LCCR0_SDS*0)   /*  Single panel display */
+#define LCCR0_Dual      (LCCR0_SDS*1)   /*  Dual panel display */
+
+#define LCCR0_LDM       (1 << 3)        /* LCD Disable Done Mask */
+#define LCCR0_SFM       (1 << 4)        /* Start of frame mask */
+#define LCCR0_IUM       (1 << 5)        /* Input FIFO underrun mask */
+#define LCCR0_EFM       (1 << 6)        /* End of Frame mask */
+#define LCCR0_PAS       (1 << 7)        /* Passive/Active display Select */
+#define LCCR0_Pas       (LCCR0_PAS*0)   /*  Passive display (STN) */
+#define LCCR0_Act       (LCCR0_PAS*1)   /*  Active display (TFT) */
+#define LCCR0_DPD       (1 << 9)        /* Double Pixel Data (monochrome) */
+#define LCCR0_4PixMono  (LCCR0_DPD*0)   /*  4-Pixel/clock Monochrome display */
+#define LCCR0_8PixMono  (LCCR0_DPD*1)   /*  8-Pixel/clock Monochrome display */
+#define LCCR0_DIS       (1 << 10)       /* LCD Disable */
+#define LCCR0_QDM       (1 << 11)       /* LCD Quick Disable mask */
+#define LCCR0_PDD       (0xff << 12)    /* Palette DMA request delay */
+#define LCCR0_PDD_S     12
+#define LCCR0_BM        (1 << 20)       /* Branch mask */
+#define LCCR0_OUM       (1 << 21)       /* Output FIFO underrun mask */
+#define LCCR0_LCDT      (1 << 22)       /* LCD panel type */
+#define LCCR0_RDSTM     (1 << 23)       /* Read status interrupt mask */
+#define LCCR0_CMDIM     (1 << 24)       /* Command interrupt mask */
+#define LCCR0_OUC       (1 << 25)       /* Overlay Underlay control bit */
+#define LCCR0_LDDALT    (1 << 26)       /* LDD alternate mapping control */
+
+#define LCCR1_PPL       Fld (10, 0)     /* Pixels Per Line - 1 */
+#define LCCR1_DisWdth(Pixel)    (((Pixel) - 1) << FShft (LCCR1_PPL))
+
+#define LCCR1_HSW       Fld (6, 10)     /* Horizontal Synchronization */
+#define LCCR1_HorSnchWdth(Tpix) (((Tpix) - 1) << FShft (LCCR1_HSW))
+
+#define LCCR1_ELW       Fld (8, 16)     /* End-of-Line pixel clock Wait - 1 */
+#define LCCR1_EndLnDel(Tpix)    (((Tpix) - 1) << FShft (LCCR1_ELW))
+
+#define LCCR1_BLW       Fld (8, 24)     /* Beginning-of-Line pixel clock */
+#define LCCR1_BegLnDel(Tpix)    (((Tpix) - 1) << FShft (LCCR1_BLW))
+
+#define LCCR2_LPP       Fld (10, 0)     /* Line Per Panel - 1 */
+#define LCCR2_DisHght(Line)     (((Line) - 1) << FShft (LCCR2_LPP))
+
+#define LCCR2_VSW       Fld (6, 10)     /* Vertical Synchronization pulse - 1 */
+#define LCCR2_VrtSnchWdth(Tln)  (((Tln) - 1) << FShft (LCCR2_VSW))
+
+#define LCCR2_EFW       Fld (8, 16)     /* End-of-Frame line clock Wait */
+#define LCCR2_EndFrmDel(Tln)    ((Tln) << FShft (LCCR2_EFW))
+
+#define LCCR2_BFW       Fld (8, 24)     /* Beginning-of-Frame line clock */
+#define LCCR2_BegFrmDel(Tln)    ((Tln) << FShft (LCCR2_BFW))
+
+#define LCCR3_API       (0xf << 16)     /* AC Bias pin trasitions per interrupt */
+#define LCCR3_API_S     16
+#define LCCR3_VSP       (1 << 20)       /* vertical sync polarity */
+#define LCCR3_HSP       (1 << 21)       /* horizontal sync polarity */
+#define LCCR3_PCP       (1 << 22)       /* Pixel Clock Polarity (L_PCLK) */
+#define LCCR3_PixRsEdg  (LCCR3_PCP*0)   /*  Pixel clock Rising-Edge */
+#define LCCR3_PixFlEdg  (LCCR3_PCP*1)   /*  Pixel clock Falling-Edge */
+
+#define LCCR3_OEP       (1 << 23)       /* Output Enable Polarity */
+#define LCCR3_OutEnH    (LCCR3_OEP*0)   /*  Output Enable active High */
+#define LCCR3_OutEnL    (LCCR3_OEP*1)   /*  Output Enable active Low */
+
+#define LCCR3_DPC       (1 << 27)       /* double pixel clock mode */
+#define LCCR3_PCD       Fld (8, 0)      /* Pixel Clock Divisor */
+#define LCCR3_PixClkDiv(Div)    (((Div) << FShft (LCCR3_PCD)))
+
+#define LCCR3_BPP       Fld (3, 24)     /* Bit Per Pixel */
+#define LCCR3_Bpp(Bpp)  (((Bpp) << FShft (LCCR3_BPP)))
+
+#define LCCR3_ACB       Fld (8, 8)      /* AC Bias */
+#define LCCR3_Acb(Acb)  (((Acb) << FShft (LCCR3_ACB)))
+
+#define LCCR3_HorSnchH  (LCCR3_HSP*0)   /*  HSP Active High */
+#define LCCR3_HorSnchL  (LCCR3_HSP*1)   /*  HSP Active Low */
+
+#define LCCR3_VrtSnchH  (LCCR3_VSP*0)   /*  VSP Active High */
+#define LCCR3_VrtSnchL  (LCCR3_VSP*1)   /*  VSP Active Low */
+
+#define LCCR5_IUM(x)    (1 << ((x) + 23)) /* input underrun mask */
+#define LCCR5_BSM(x)    (1 << ((x) + 15)) /* branch mask */
+#define LCCR5_EOFM(x)   (1 << ((x) + 7))  /* end of frame mask */
+#define LCCR5_SOFM(x)   (1 << ((x) + 0))  /* start of frame mask */
+
+#define LCSR_LDD        (1 << 0)        /* LCD Disable Done */
+#define LCSR_SOF        (1 << 1)        /* Start of frame */
+#define LCSR_BER        (1 << 2)        /* Bus error */
+#define LCSR_ABC        (1 << 3)        /* AC Bias count */
+#define LCSR_IUL        (1 << 4)        /* input FIFO underrun Lower panel */
+#define LCSR_IUU        (1 << 5)        /* input FIFO underrun Upper panel */
+#define LCSR_OU         (1 << 6)        /* output FIFO underrun */
+#define LCSR_QD         (1 << 7)        /* quick disable */
+#define LCSR_EOF        (1 << 8)        /* end of frame */
+#define LCSR_BS         (1 << 9)        /* branch status */
+#define LCSR_SINT       (1 << 10)       /* subsequent interrupt */
+#define LCSR_RD_ST      (1 << 11)       /* read status */
+#define LCSR_CMD_INT    (1 << 12)       /* command interrupt */
+
+#define LDCMD_PAL       (1 << 26)       /* instructs DMA to load palette buffer */
+
+/* smartpanel related */
+#define PRSR_DATA(x)    ((x) & 0xff)    /* Panel Data */
+#define PRSR_A0         (1 << 8)        /* Read Data Source */
+#define PRSR_ST_OK      (1 << 9)        /* Status OK */
+#define PRSR_CON_NT     (1 << 10)       /* Continue to Next Command */
+
+#define SMART_CMD_A0                     (0x1 << 8)
+#define SMART_CMD_READ_STATUS_REG        (0x0 << 9)
+#define SMART_CMD_READ_FRAME_BUFFER     ((0x0 << 9) | SMART_CMD_A0)
+#define SMART_CMD_WRITE_COMMAND          (0x1 << 9)
+#define SMART_CMD_WRITE_DATA            ((0x1 << 9) | SMART_CMD_A0)
+#define SMART_CMD_WRITE_FRAME           ((0x2 << 9) | SMART_CMD_A0)
+#define SMART_CMD_WAIT_FOR_VSYNC         (0x3 << 9)
+#define SMART_CMD_NOOP                   (0x4 << 9)
+#define SMART_CMD_INTERRUPT              (0x5 << 9)
+
+#define SMART_CMD(x)    (SMART_CMD_WRITE_COMMAND | ((x) & 0xff))
+#define SMART_DAT(x)    (SMART_CMD_WRITE_DATA | ((x) & 0xff))
+#endif /* __ASM_ARCH_REGS_LCD_H */
diff --git a/include/asm-arm/arch-pxa/regs-ssp.h b/arch/arm/mach-pxa/include/mach/regs-ssp.h
index 3c04cde2cf1f..3c04cde2cf1f 100644
--- a/include/asm-arm/arch-pxa/regs-ssp.h
+++ b/arch/arm/mach-pxa/include/mach/regs-ssp.h
diff --git a/include/asm-arm/arch-pxa/sharpsl.h b/arch/arm/mach-pxa/include/mach/sharpsl.h
index 3b1d4a72d4d1..3b1d4a72d4d1 100644
--- a/include/asm-arm/arch-pxa/sharpsl.h
+++ b/arch/arm/mach-pxa/include/mach/sharpsl.h
diff --git a/include/asm-arm/arch-pxa/spitz.h b/arch/arm/mach-pxa/include/mach/spitz.h
index bd14365f7ed5..bd14365f7ed5 100644
--- a/include/asm-arm/arch-pxa/spitz.h
+++ b/arch/arm/mach-pxa/include/mach/spitz.h
diff --git a/include/asm-arm/arch-pxa/ssp.h b/arch/arm/mach-pxa/include/mach/ssp.h
index a012882c9ee6..a012882c9ee6 100644
--- a/include/asm-arm/arch-pxa/ssp.h
+++ b/arch/arm/mach-pxa/include/mach/ssp.h
diff --git a/arch/arm/mach-pxa/include/mach/system.h b/arch/arm/mach-pxa/include/mach/system.h
new file mode 100644
index 000000000000..0f381e692999
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/system.h
@@ -0,0 +1,24 @@
+/*
+ * arch/arm/mach-pxa/include/mach/system.h
+ *
+ * Author:      Nicolas Pitre
+ * Created:     Jun 15, 2001
+ * Copyright:   MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <asm/proc-fns.h>
+#include "hardware.h"
+#include "pxa2xx-regs.h"
+#include "pxa-regs.h"
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+
+void arch_reset(char mode);
diff --git a/arch/arm/mach-pxa/include/mach/timex.h b/arch/arm/mach-pxa/include/mach/timex.h
new file mode 100644
index 000000000000..b05fc6683c47
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/timex.h
@@ -0,0 +1,26 @@
+/*
+ * arch/arm/mach-pxa/include/mach/timex.h
+ *
+ * Author:      Nicolas Pitre
+ * Created:     Jun 15, 2001
+ * Copyright:   MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+
+#if defined(CONFIG_PXA25x)
+/* PXA250/210 timer base */
+#define CLOCK_TICK_RATE 3686400
+#elif defined(CONFIG_PXA27x)
+/* PXA27x timer base */
+#ifdef CONFIG_MACH_MAINSTONE
+#define CLOCK_TICK_RATE 3249600
+#else
+#define CLOCK_TICK_RATE 3250000
+#endif
+#else
+#define CLOCK_TICK_RATE 3250000
+#endif
diff --git a/include/asm-arm/arch-pxa/tosa.h b/arch/arm/mach-pxa/include/mach/tosa.h
index a72803f0461b..a72803f0461b 100644
--- a/include/asm-arm/arch-pxa/tosa.h
+++ b/arch/arm/mach-pxa/include/mach/tosa.h
diff --git a/include/asm-arm/arch-pxa/tosa_bt.h b/arch/arm/mach-pxa/include/mach/tosa_bt.h
index efc3c3d3b75d..efc3c3d3b75d 100644
--- a/include/asm-arm/arch-pxa/tosa_bt.h
+++ b/arch/arm/mach-pxa/include/mach/tosa_bt.h
diff --git a/include/asm-arm/arch-pxa/trizeps4.h b/arch/arm/mach-pxa/include/mach/trizeps4.h
index 641d0ec110bb..641d0ec110bb 100644
--- a/include/asm-arm/arch-pxa/trizeps4.h
+++ b/arch/arm/mach-pxa/include/mach/trizeps4.h
diff --git a/arch/arm/mach-pxa/include/mach/udc.h b/arch/arm/mach-pxa/include/mach/udc.h
new file mode 100644
index 000000000000..2f82332e81a0
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/udc.h
@@ -0,0 +1,8 @@
+/*
+ * arch/arm/mach-pxa/include/mach/udc.h
+ *
+ */
+#include <asm/mach/udc_pxa2xx.h>
+
+extern void pxa_set_udc_info(struct pxa2xx_udc_mach_info *info);
+
diff --git a/arch/arm/mach-pxa/include/mach/uncompress.h b/arch/arm/mach-pxa/include/mach/uncompress.h
new file mode 100644
index 000000000000..21e3e890af98
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/uncompress.h
@@ -0,0 +1,45 @@
+/*
+ * arch/arm/mach-pxa/include/mach/uncompress.h
+ *
+ * Author:      Nicolas Pitre
+ * Copyright:   (C) 2001 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/serial_reg.h>
+#include <mach/pxa-regs.h>
+#include <asm/mach-types.h>
+
+#define __REG(x)       ((volatile unsigned long *)x)
+
+static volatile unsigned long *UART = FFUART;
+
+static inline void putc(char c)
+{
+        if (!(UART[UART_IER] & IER_UUE))
+                return;
+        while (!(UART[UART_LSR] & LSR_TDRQ))
+                barrier();
+        UART[UART_TX] = c;
+}
+
+/*
+ * This does not append a newline
+ */
+static inline void flush(void)
+{
+}
+
+static inline void arch_decomp_setup(void)
+{
+        if (machine_is_littleton())
+                UART = STUART;
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-pxa/include/mach/vmalloc.h b/arch/arm/mach-pxa/include/mach/vmalloc.h
new file mode 100644
index 000000000000..e90c5eeb81dd
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/vmalloc.h
@@ -0,0 +1,11 @@
+/*
+ * arch/arm/mach-pxa/include/mach/vmalloc.h
+ *
+ * Author:      Nicolas Pitre
+ * Copyright:   (C) 2001 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#define VMALLOC_END       (0xe8000000)
diff --git a/include/asm-arm/arch-pxa/zylonite.h b/arch/arm/mach-pxa/include/mach/zylonite.h
index 0d35ca04731e..0d35ca04731e 100644
--- a/include/asm-arm/arch-pxa/zylonite.h
+++ b/arch/arm/mach-pxa/include/mach/zylonite.h
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 26a9d8b7d5f1..5e95c5372fec 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -17,10 +17,10 @@
 #include <linux/interrupt.h>
 #include <linux/sysdev.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
-#include <asm/arch/pxa-regs.h>
+#include <mach/pxa-regs.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-pxa/leds-idp.c b/arch/arm/mach-pxa/leds-idp.c
index c410e53bf9e9..18b20d469410 100644
--- a/arch/arm/mach-pxa/leds-idp.c
+++ b/arch/arm/mach-pxa/leds-idp.c
@@ -14,12 +14,12 @@
 
 #include <linux/init.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/system.h>
 
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/idp.h>
+#include <mach/pxa-regs.h>
+#include <mach/idp.h>
 
 #include "leds.h"
 
diff --git a/arch/arm/mach-pxa/leds-lubbock.c b/arch/arm/mach-pxa/leds-lubbock.c
index 7eafbb4d5079..1a258029c33c 100644
--- a/arch/arm/mach-pxa/leds-lubbock.c
+++ b/arch/arm/mach-pxa/leds-lubbock.c
@@ -13,11 +13,11 @@
 
 #include <linux/init.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/system.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/lubbock.h>
+#include <mach/pxa-regs.h>
+#include <mach/lubbock.h>
 
 #include "leds.h"
 
diff --git a/arch/arm/mach-pxa/leds-mainstone.c b/arch/arm/mach-pxa/leds-mainstone.c
index 32ca5acfa1c1..95e06b849634 100644
--- a/arch/arm/mach-pxa/leds-mainstone.c
+++ b/arch/arm/mach-pxa/leds-mainstone.c
@@ -12,12 +12,12 @@
 
 #include <linux/init.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/system.h>
 
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/mainstone.h>
+#include <mach/pxa-regs.h>
+#include <mach/mainstone.h>
 
 #include "leds.h"
 
diff --git a/arch/arm/mach-pxa/leds-trizeps4.c b/arch/arm/mach-pxa/leds-trizeps4.c
index c2fe1db22bf1..3bc29007df3a 100644
--- a/arch/arm/mach-pxa/leds-trizeps4.c
+++ b/arch/arm/mach-pxa/leds-trizeps4.c
@@ -12,14 +12,14 @@
 
 #include <linux/init.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/system.h>
 #include <asm/types.h>
 #include <asm/leds.h>
 
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-gpio.h>
-#include <asm/arch/trizeps4.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-gpio.h>
+#include <mach/trizeps4.h>
 
 #include "leds.h"
 
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index 101bd7ee8151..58f3402a0375 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -26,21 +26,21 @@
 #include <asm/setup.h>
 #include <asm/memory.h>
 #include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/mfp-pxa300.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/pxafb.h>
-#include <asm/arch/ssp.h>
-#include <asm/arch/pxa27x_keypad.h>
-#include <asm/arch/pxa3xx_nand.h>
-#include <asm/arch/littleton.h>
+#include <mach/pxa-regs.h>
+#include <mach/mfp-pxa300.h>
+#include <mach/gpio.h>
+#include <mach/pxafb.h>
+#include <mach/ssp.h>
+#include <mach/pxa27x_keypad.h>
+#include <mach/pxa3xx_nand.h>
+#include <mach/littleton.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index 34c69b10f1b5..b7038948d1d4 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -29,7 +29,7 @@
 #include <asm/setup.h>
 #include <asm/memory.h>
 #include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/sizes.h>
 
@@ -38,15 +38,15 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/flash.h>
 
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-regs.h>
-#include <asm/arch/pxa2xx-gpio.h>
-#include <asm/arch/lpd270.h>
-#include <asm/arch/audio.h>
-#include <asm/arch/pxafb.h>
-#include <asm/arch/mmc.h>
-#include <asm/arch/irda.h>
-#include <asm/arch/ohci.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-regs.h>
+#include <mach/pxa2xx-gpio.h>
+#include <mach/lpd270.h>
+#include <mach/audio.h>
+#include <mach/pxafb.h>
+#include <mach/mmc.h>
+#include <mach/irda.h>
+#include <mach/ohci.h>
 
 #include "generic.h"
 #include "devices.h"
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 66a3f334d6df..4ba8d3190721 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -25,12 +25,12 @@
 
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
-#include <asm/arch/pxa2xx_spi.h>
+#include <mach/pxa2xx_spi.h>
 
 #include <asm/setup.h>
 #include <asm/memory.h>
 #include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/sizes.h>
 
@@ -41,15 +41,15 @@
 
 #include <asm/hardware/sa1111.h>
 
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-regs.h>
-#include <asm/arch/mfp-pxa25x.h>
-#include <asm/arch/audio.h>
-#include <asm/arch/lubbock.h>
-#include <asm/arch/udc.h>
-#include <asm/arch/irda.h>
-#include <asm/arch/pxafb.h>
-#include <asm/arch/mmc.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-regs.h>
+#include <mach/mfp-pxa25x.h>
+#include <mach/audio.h>
+#include <mach/lubbock.h>
+#include <mach/udc.h>
+#include <mach/irda.h>
+#include <mach/pxafb.h>
+#include <mach/mmc.h>
 
 #include "generic.h"
 #include "devices.h"
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index e919f37be72b..143f28adaf95 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -26,18 +26,18 @@
 #include <linux/pda_power.h>
 #include <linux/pwm_backlight.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/arch/magician.h>
-#include <asm/arch/mfp-pxa27x.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-regs.h>
-#include <asm/arch/pxafb.h>
-#include <asm/arch/i2c.h>
-#include <asm/arch/mmc.h>
-#include <asm/arch/irda.h>
-#include <asm/arch/ohci.h>
+#include <mach/magician.h>
+#include <mach/mfp-pxa27x.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-regs.h>
+#include <mach/pxafb.h>
+#include <mach/i2c.h>
+#include <mach/mmc.h>
+#include <mach/irda.h>
+#include <mach/ohci.h>
 
 #include "devices.h"
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 425ba9666daa..d44af761564d 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -32,7 +32,7 @@
 #include <asm/setup.h>
 #include <asm/memory.h>
 #include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/sizes.h>
 
@@ -41,17 +41,17 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/flash.h>
 
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-regs.h>
-#include <asm/arch/mfp-pxa27x.h>
-#include <asm/arch/mainstone.h>
-#include <asm/arch/audio.h>
-#include <asm/arch/pxafb.h>
-#include <asm/arch/i2c.h>
-#include <asm/arch/mmc.h>
-#include <asm/arch/irda.h>
-#include <asm/arch/ohci.h>
-#include <asm/arch/pxa27x_keypad.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-regs.h>
+#include <mach/mfp-pxa27x.h>
+#include <mach/mainstone.h>
+#include <mach/audio.h>
+#include <mach/pxafb.h>
+#include <mach/i2c.h>
+#include <mach/mmc.h>
+#include <mach/irda.h>
+#include <mach/ohci.h>
+#include <mach/pxa27x_keypad.h>
 
 #include "generic.h"
 #include "devices.h"
diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c
index fd4545eab803..925575f10acf 100644
--- a/arch/arm/mach-pxa/mfp-pxa2xx.c
+++ b/arch/arm/mach-pxa/mfp-pxa2xx.c
@@ -18,10 +18,10 @@
 #include <linux/init.h>
 #include <linux/sysdev.h>
 
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-regs.h>
-#include <asm/arch/mfp-pxa2xx.h>
+#include <mach/hardware.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-regs.h>
+#include <mach/mfp-pxa2xx.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-pxa/mfp-pxa3xx.c b/arch/arm/mach-pxa/mfp-pxa3xx.c
index c15183174d7e..eb197a6e8e94 100644
--- a/arch/arm/mach-pxa/mfp-pxa3xx.c
+++ b/arch/arm/mach-pxa/mfp-pxa3xx.c
@@ -19,10 +19,10 @@
 #include <linux/io.h>
 #include <linux/sysdev.h>
 
-#include <asm/arch/hardware.h>
-#include <asm/arch/mfp.h>
-#include <asm/arch/mfp-pxa3xx.h>
-#include <asm/arch/pxa3xx-regs.h>
+#include <mach/hardware.h>
+#include <mach/mfp.h>
+#include <mach/mfp-pxa3xx.h>
+#include <mach/pxa3xx-regs.h>
 
 /* mfp_spin_lock is used to ensure that MFP register configuration
  * (most likely a read-modify-write operation) is atomic, and that
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c
index 408657a24f8c..fe924a23debe 100644
--- a/arch/arm/mach-pxa/palmtx.c
+++ b/arch/arm/mach-pxa/palmtx.c
@@ -30,15 +30,15 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <asm/arch/audio.h>
-#include <asm/arch/palmtx.h>
-#include <asm/arch/mmc.h>
-#include <asm/arch/pxafb.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/mfp-pxa27x.h>
-#include <asm/arch/irda.h>
-#include <asm/arch/pxa27x_keypad.h>
-#include <asm/arch/udc.h>
+#include <mach/audio.h>
+#include <mach/palmtx.h>
+#include <mach/mmc.h>
+#include <mach/pxafb.h>
+#include <mach/pxa-regs.h>
+#include <mach/mfp-pxa27x.h>
+#include <mach/irda.h>
+#include <mach/pxa27x_keypad.h>
+#include <mach/udc.h>
 
 #include "generic.h"
 #include "devices.h"
diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c
index 377f3be8ce57..730b9f6ede1d 100644
--- a/arch/arm/mach-pxa/pcm027.c
+++ b/arch/arm/mach-pxa/pcm027.c
@@ -29,12 +29,12 @@
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-gpio.h>
-#include <asm/arch/pxa2xx-regs.h>
-#include <asm/arch/pxa2xx_spi.h>
-#include <asm/arch/pcm027.h>
+#include <mach/hardware.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-gpio.h>
+#include <mach/pxa2xx-regs.h>
+#include <mach/pxa2xx_spi.h>
+#include <mach/pcm027.h>
 #include "generic.h"
 
 /*
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index 90056d56b210..420c9b3813f6 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -28,16 +28,16 @@
 #include <media/soc_camera.h>
 
 #include <asm/gpio.h>
-#include <asm/arch/i2c.h>
-#include <asm/arch/camera.h>
+#include <mach/i2c.h>
+#include <mach/camera.h>
 #include <asm/mach/map.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/audio.h>
-#include <asm/arch/mmc.h>
-#include <asm/arch/ohci.h>
-#include <asm/arch/pcm990_baseboard.h>
-#include <asm/arch/pxafb.h>
-#include <asm/arch/mfp-pxa27x.h>
+#include <mach/pxa-regs.h>
+#include <mach/audio.h>
+#include <mach/mmc.h>
+#include <mach/ohci.h>
+#include <mach/pcm990_baseboard.h>
+#include <mach/pxafb.h>
+#include <mach/mfp-pxa27x.h>
 
 #include "devices.h"
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/pm.c b/arch/arm/mach-pxa/pm.c
index 9445bf11e7ae..1b539e675579 100644
--- a/arch/arm/mach-pxa/pm.c
+++ b/arch/arm/mach-pxa/pm.c
@@ -16,12 +16,12 @@
 #include <linux/errno.h>
 #include <linux/time.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/memory.h>
 #include <asm/system.h>
-#include <asm/arch/pm.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/lubbock.h>
+#include <mach/pm.h>
+#include <mach/pxa-regs.h>
+#include <mach/lubbock.h>
 #include <asm/mach/time.h>
 
 struct pxa_cpu_pm_fns *pxa_cpu_pm_fns;
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index fef958fddf5c..055ec63d768c 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -21,7 +21,7 @@
 #include <linux/pm.h>
 #include <linux/delay.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
 #include <asm/setup.h>
@@ -31,16 +31,16 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-regs.h>
-#include <asm/arch/pxa2xx-gpio.h>
-#include <asm/arch/mmc.h>
-#include <asm/arch/udc.h>
-#include <asm/arch/irda.h>
-#include <asm/arch/poodle.h>
-#include <asm/arch/pxafb.h>
-#include <asm/arch/sharpsl.h>
-#include <asm/arch/ssp.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-regs.h>
+#include <mach/pxa2xx-gpio.h>
+#include <mach/mmc.h>
+#include <mach/udc.h>
+#include <mach/irda.h>
+#include <mach/poodle.h>
+#include <mach/pxafb.h>
+#include <mach/sharpsl.h>
+#include <mach/ssp.h>
 
 #include <asm/hardware/scoop.h>
 #include <asm/hardware/locomo.h>
diff --git a/arch/arm/mach-pxa/pwm.c b/arch/arm/mach-pxa/pwm.c
index ce28cd9fed16..316cd986da5c 100644
--- a/arch/arm/mach-pxa/pwm.c
+++ b/arch/arm/mach-pxa/pwm.c
@@ -20,7 +20,7 @@
 #include <linux/pwm.h>
 
 #include <asm/div64.h>
-#include <asm/arch/pxa-regs.h>
+#include <mach/pxa-regs.h>
 
 /* PWM registers and bits definitions */
 #define PWMCR           (0x00)
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index c8379e5309d7..3c2d22de9a13 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -23,13 +23,13 @@
 #include <linux/suspend.h>
 #include <linux/sysdev.h>
 
-#include <asm/arch/hardware.h>
-#include <asm/arch/irqs.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-regs.h>
-#include <asm/arch/mfp-pxa25x.h>
-#include <asm/arch/pm.h>
-#include <asm/arch/dma.h>
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-regs.h>
+#include <mach/mfp-pxa25x.h>
+#include <mach/pm.h>
+#include <mach/dma.h>
 
 #include "generic.h"
 #include "devices.h"
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 46720ed2a677..6bec43484ba7 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -18,16 +18,16 @@
 #include <linux/platform_device.h>
 #include <linux/sysdev.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/arch/irqs.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-regs.h>
-#include <asm/arch/mfp-pxa27x.h>
-#include <asm/arch/ohci.h>
-#include <asm/arch/pm.h>
-#include <asm/arch/dma.h>
-#include <asm/arch/i2c.h>
+#include <mach/irqs.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-regs.h>
+#include <mach/mfp-pxa27x.h>
+#include <mach/ohci.h>
+#include <mach/pm.h>
+#include <mach/dma.h>
+#include <mach/i2c.h>
 
 #include "generic.h"
 #include "devices.h"
diff --git a/arch/arm/mach-pxa/pxa2xx.c b/arch/arm/mach-pxa/pxa2xx.c
index d4f6415e8413..00b4de6d6bdd 100644
--- a/arch/arm/mach-pxa/pxa2xx.c
+++ b/arch/arm/mach-pxa/pxa2xx.c
@@ -14,9 +14,9 @@
 #include <linux/kernel.h>
 #include <linux/device.h>
 
-#include <asm/arch/mfp-pxa2xx.h>
-#include <asm/arch/mfp-pxa25x.h>
-#include <asm/arch/irda.h>
+#include <mach/mfp-pxa2xx.h>
+#include <mach/mfp-pxa25x.h>
+#include <mach/irda.h>
 
 static unsigned long pxa2xx_mfp_fir[] = {
         GPIO46_FICP_RXD,
diff --git a/arch/arm/mach-pxa/pxa300.c b/arch/arm/mach-pxa/pxa300.c
index b8482da3e4d5..494fc1f032db 100644
--- a/arch/arm/mach-pxa/pxa300.c
+++ b/arch/arm/mach-pxa/pxa300.c
@@ -17,9 +17,9 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa3xx-regs.h>
-#include <asm/arch/mfp-pxa300.h>
+#include <mach/hardware.h>
+#include <mach/pxa3xx-regs.h>
+#include <mach/mfp-pxa300.h>
 
 #include "generic.h"
 #include "devices.h"
diff --git a/arch/arm/mach-pxa/pxa320.c b/arch/arm/mach-pxa/pxa320.c
index 95d46d92621f..016eb18f01a3 100644
--- a/arch/arm/mach-pxa/pxa320.c
+++ b/arch/arm/mach-pxa/pxa320.c
@@ -17,10 +17,10 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 
-#include <asm/arch/hardware.h>
-#include <asm/arch/mfp.h>
-#include <asm/arch/pxa3xx-regs.h>
-#include <asm/arch/mfp-pxa320.h>
+#include <mach/hardware.h>
+#include <mach/mfp.h>
+#include <mach/pxa3xx-regs.h>
+#include <mach/mfp-pxa320.h>
 
 #include "generic.h"
 #include "devices.h"
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 4f5e6c7f6951..37b07212b5a5 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -22,12 +22,12 @@
 #include <linux/io.h>
 #include <linux/sysdev.h>
 
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa3xx-regs.h>
-#include <asm/arch/ohci.h>
-#include <asm/arch/pm.h>
-#include <asm/arch/dma.h>
-#include <asm/arch/ssp.h>
+#include <mach/hardware.h>
+#include <mach/pxa3xx-regs.h>
+#include <mach/ohci.h>
+#include <mach/pm.h>
+#include <mach/dma.h>
+#include <mach/ssp.h>
 
 #include "generic.h"
 #include "devices.h"
diff --git a/arch/arm/mach-pxa/pxa930.c b/arch/arm/mach-pxa/pxa930.c
index 028ee1d86548..13e6bfdfff60 100644
--- a/arch/arm/mach-pxa/pxa930.c
+++ b/arch/arm/mach-pxa/pxa930.c
@@ -16,8 +16,8 @@
 #include <linux/irq.h>
 #include <linux/dma-mapping.h>
 
-#include <asm/arch/hardware.h>
-#include <asm/arch/mfp-pxa930.h>
+#include <mach/hardware.h>
+#include <mach/mfp-pxa930.h>
 
 static struct pxa3xx_mfp_addr_map pxa930_mfp_addr_map[] __initdata = {
 
diff --git a/arch/arm/mach-pxa/reset.c b/arch/arm/mach-pxa/reset.c
index 9d39dea57ce2..fabead71d681 100644
--- a/arch/arm/mach-pxa/reset.c
+++ b/arch/arm/mach-pxa/reset.c
@@ -10,8 +10,8 @@
 #include <asm/io.h>
 #include <asm/proc-fns.h>
 
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-regs.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-regs.h>
 
 static void do_hw_reset(void);
 
diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c
index ee70dee5b4dc..e7ea91ce7f02 100644
--- a/arch/arm/mach-pxa/saar.c
+++ b/arch/arm/mach-pxa/saar.c
@@ -21,9 +21,9 @@
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa3xx-regs.h>
-#include <asm/arch/mfp-pxa930.h>
+#include <mach/hardware.h>
+#include <mach/pxa3xx-regs.h>
+#include <mach/mfp-pxa930.h>
 
 #include "devices.h"
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c
index 7b7d0bd32eb1..e804ae09370c 100644
--- a/arch/arm/mach-pxa/sharpsl_pm.c
+++ b/arch/arm/mach-pxa/sharpsl_pm.c
@@ -22,12 +22,12 @@
 #include <linux/platform_device.h>
 #include <linux/apm-emulation.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
-#include <asm/arch/pm.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-gpio.h>
-#include <asm/arch/sharpsl.h>
+#include <mach/pm.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-gpio.h>
+#include <mach/sharpsl.h>
 #include "sharpsl.h"
 
 struct battery_thresh spitz_battery_levels_acin[] = {
diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S
index 2a58f1e40e33..a62c8375eb53 100644
--- a/arch/arm/mach-pxa/sleep.S
+++ b/arch/arm/mach-pxa/sleep.S
@@ -13,10 +13,10 @@
 
 #include <linux/linkage.h>
 #include <asm/assembler.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-regs.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-regs.h>
 
 #define MDREFR_KDIV     0x200a4000      // all banks
 #define CCCR_SLEEP      0x00000107      // L=7 2N=2 A=0 PPDIS=0 CPDIS=0
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index a8774d458498..26b9fa56cffd 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -26,7 +26,7 @@
 #include <asm/setup.h>
 #include <asm/memory.h>
 #include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/io.h>
 #include <asm/system.h>
@@ -35,18 +35,18 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-regs.h>
-#include <asm/arch/pxa2xx-gpio.h>
-#include <asm/arch/pxa27x-udc.h>
-#include <asm/arch/irda.h>
-#include <asm/arch/mmc.h>
-#include <asm/arch/ohci.h>
-#include <asm/arch/udc.h>
-#include <asm/arch/pxafb.h>
-#include <asm/arch/akita.h>
-#include <asm/arch/spitz.h>
-#include <asm/arch/sharpsl.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-regs.h>
+#include <mach/pxa2xx-gpio.h>
+#include <mach/pxa27x-udc.h>
+#include <mach/irda.h>
+#include <mach/mmc.h>
+#include <mach/ohci.h>
+#include <mach/udc.h>
+#include <mach/pxafb.h>
+#include <mach/akita.h>
+#include <mach/spitz.h>
+#include <mach/sharpsl.h>
 
 #include <asm/mach/sharpsl_param.h>
 #include <asm/hardware/scoop.h>
diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c
index 8fb5651548de..8a40505dfd28 100644
--- a/arch/arm/mach-pxa/spitz_pm.c
+++ b/arch/arm/mach-pxa/spitz_pm.c
@@ -20,14 +20,14 @@
 
 #include <asm/irq.h>
 #include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/hardware/scoop.h>
 
-#include <asm/arch/sharpsl.h>
-#include <asm/arch/spitz.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-regs.h>
-#include <asm/arch/pxa2xx-gpio.h>
+#include <mach/sharpsl.h>
+#include <mach/spitz.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-regs.h>
+#include <mach/pxa2xx-gpio.h>
 #include "sharpsl.h"
 
 #define SHARPSL_CHARGE_ON_VOLT         0x99  /* 2.9V */
diff --git a/arch/arm/mach-pxa/ssp.c b/arch/arm/mach-pxa/ssp.c
index bca34e5c8c04..9bd93c5f28b2 100644
--- a/arch/arm/mach-pxa/ssp.c
+++ b/arch/arm/mach-pxa/ssp.c
@@ -31,10 +31,10 @@
 
 #include <asm/io.h>
 #include <asm/irq.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/ssp.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/regs-ssp.h>
+#include <mach/hardware.h>
+#include <mach/ssp.h>
+#include <mach/pxa-regs.h>
+#include <mach/regs-ssp.h>
 
 #define TIMEOUT 100000
 
diff --git a/arch/arm/mach-pxa/standby.S b/arch/arm/mach-pxa/standby.S
index 207fb6076624..f3821cfda72f 100644
--- a/arch/arm/mach-pxa/standby.S
+++ b/arch/arm/mach-pxa/standby.S
@@ -11,10 +11,10 @@
 
 #include <linux/linkage.h>
 #include <asm/assembler.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-regs.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-regs.h>
 
                 .text
 
diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c
index 9dcb349e6d90..589d32b4fc46 100644
--- a/arch/arm/mach-pxa/tavorevb.c
+++ b/arch/arm/mach-pxa/tavorevb.c
@@ -21,9 +21,9 @@
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa3xx-regs.h>
-#include <asm/arch/mfp-pxa930.h>
+#include <mach/hardware.h>
+#include <mach/pxa3xx-regs.h>
+#include <mach/mfp-pxa930.h>
 
 #include "devices.h"
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c
index 7b7c0179795b..67e18509d7bf 100644
--- a/arch/arm/mach-pxa/time.c
+++ b/arch/arm/mach-pxa/time.c
@@ -22,7 +22,7 @@
 #include <asm/cnt32_to_63.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
-#include <asm/arch/pxa-regs.h>
+#include <mach/pxa-regs.h>
 #include <asm/mach-types.h>
 
 /*
diff --git a/arch/arm/mach-pxa/tosa-bt.c b/arch/arm/mach-pxa/tosa-bt.c
index 7d8505466e54..fb0294bd4310 100644
--- a/arch/arm/mach-pxa/tosa-bt.c
+++ b/arch/arm/mach-pxa/tosa-bt.c
@@ -16,7 +16,7 @@
 #include <linux/delay.h>
 #include <linux/rfkill.h>
 
-#include <asm/arch/tosa_bt.h>
+#include <mach/tosa_bt.h>
 
 static void tosa_bt_on(struct tosa_bt_data *data)
 {
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index fea17ce6b55f..38bc59c44110 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -34,16 +34,16 @@
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
-#include <asm/arch/pxa2xx-regs.h>
-#include <asm/arch/mfp-pxa25x.h>
-#include <asm/arch/irda.h>
-#include <asm/arch/i2c.h>
-#include <asm/arch/mmc.h>
-#include <asm/arch/udc.h>
-#include <asm/arch/tosa_bt.h>
+#include <mach/pxa2xx-regs.h>
+#include <mach/mfp-pxa25x.h>
+#include <mach/irda.h>
+#include <mach/i2c.h>
+#include <mach/mmc.h>
+#include <mach/udc.h>
+#include <mach/tosa_bt.h>
 
 #include <asm/mach/arch.h>
-#include <asm/arch/tosa.h>
+#include <mach/tosa.h>
 
 #include <asm/hardware/scoop.h>
 #include <asm/mach/sharpsl_param.h>
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
index 6367ac21af84..3ed757e6bcc8 100644
--- a/arch/arm/mach-pxa/trizeps4.c
+++ b/arch/arm/mach-pxa/trizeps4.c
@@ -31,7 +31,7 @@
 #include <asm/setup.h>
 #include <asm/memory.h>
 #include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/sizes.h>
 
@@ -40,15 +40,15 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/flash.h>
 
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-regs.h>
-#include <asm/arch/pxa2xx-gpio.h>
-#include <asm/arch/trizeps4.h>
-#include <asm/arch/audio.h>
-#include <asm/arch/pxafb.h>
-#include <asm/arch/mmc.h>
-#include <asm/arch/irda.h>
-#include <asm/arch/ohci.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-regs.h>
+#include <mach/pxa2xx-gpio.h>
+#include <mach/trizeps4.h>
+#include <mach/audio.h>
+#include <mach/pxafb.h>
+#include <mach/mmc.h>
+#include <mach/irda.h>
+#include <mach/ohci.h>
 
 #include "generic.h"
 #include "devices.h"
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index f11ced1562b8..0cb65b5772fe 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -23,14 +23,14 @@
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/audio.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/pxafb.h>
-#include <asm/arch/zylonite.h>
-#include <asm/arch/mmc.h>
-#include <asm/arch/pxa27x_keypad.h>
-#include <asm/arch/pxa3xx_nand.h>
+#include <mach/hardware.h>
+#include <mach/audio.h>
+#include <mach/gpio.h>
+#include <mach/pxafb.h>
+#include <mach/zylonite.h>
+#include <mach/mmc.h>
+#include <mach/pxa27x_keypad.h>
+#include <mach/pxa3xx_nand.h>
 
 #include "devices.h"
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c
index b28d46e081d3..095f5c648236 100644
--- a/arch/arm/mach-pxa/zylonite_pxa300.c
+++ b/arch/arm/mach-pxa/zylonite_pxa300.c
@@ -20,9 +20,9 @@
 #include <linux/i2c/pca953x.h>
 
 #include <asm/gpio.h>
-#include <asm/arch/mfp-pxa300.h>
-#include <asm/arch/i2c.h>
-#include <asm/arch/zylonite.h>
+#include <mach/mfp-pxa300.h>
+#include <mach/i2c.h>
+#include <mach/zylonite.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-pxa/zylonite_pxa320.c b/arch/arm/mach-pxa/zylonite_pxa320.c
index 2b7fba7a2921..9879d7da2df5 100644
--- a/arch/arm/mach-pxa/zylonite_pxa320.c
+++ b/arch/arm/mach-pxa/zylonite_pxa320.c
@@ -17,9 +17,9 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 
-#include <asm/arch/gpio.h>
-#include <asm/arch/mfp-pxa320.h>
-#include <asm/arch/zylonite.h>
+#include <mach/gpio.h>
+#include <mach/mfp-pxa320.h>
+#include <mach/zylonite.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index b63fa88fb42b..4f9c84ab781c 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -29,7 +29,7 @@
 #include <linux/clockchips.h>
 
 #include <asm/system.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/leds.h>
diff --git a/arch/arm/mach-realview/include/mach/board-eb.h b/arch/arm/mach-realview/include/mach/board-eb.h
new file mode 100644
index 000000000000..8d699fd324d0
--- /dev/null
+++ b/arch/arm/mach-realview/include/mach/board-eb.h
@@ -0,0 +1,191 @@
+/*
+ * arch/arm/mach-realview/include/mach/board-eb.h
+ *
+ * Copyright (C) 2007 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_BOARD_EB_H
+#define __ASM_ARCH_BOARD_EB_H
+
+#include <mach/platform.h>
+
+/*
+ * RealView EB + ARM11MPCore peripheral addresses
+ */
+#define REALVIEW_EB_UART0_BASE          0x10009000      /* UART 0 */
+#define REALVIEW_EB_UART1_BASE          0x1000A000      /* UART 1 */
+#define REALVIEW_EB_UART2_BASE          0x1000B000      /* UART 2 */
+#define REALVIEW_EB_UART3_BASE          0x1000C000      /* UART 3 */
+#define REALVIEW_EB_SSP_BASE            0x1000D000      /* Synchronous Serial Port */
+#define REALVIEW_EB_WATCHDOG_BASE       0x10010000      /* watchdog interface */
+#define REALVIEW_EB_TIMER0_1_BASE       0x10011000      /* Timer 0 and 1 */
+#define REALVIEW_EB_TIMER2_3_BASE       0x10012000      /* Timer 2 and 3 */
+#define REALVIEW_EB_GPIO0_BASE          0x10013000      /* GPIO port 0 */
+#define REALVIEW_EB_RTC_BASE            0x10017000      /* Real Time Clock */
+#define REALVIEW_EB_CLCD_BASE           0x10020000      /* CLCD */
+#define REALVIEW_EB_GIC_CPU_BASE        0x10040000      /* Generic interrupt controller CPU interface */
+#define REALVIEW_EB_GIC_DIST_BASE       0x10041000      /* Generic interrupt controller distributor */
+#define REALVIEW_EB_SMC_BASE            0x10080000      /* Static memory controller */
+
+#define REALVIEW_EB_FLASH_BASE          0x40000000
+#define REALVIEW_EB_FLASH_SIZE          SZ_64M
+#define REALVIEW_EB_ETH_BASE            0x4E000000      /* Ethernet */
+#define REALVIEW_EB_USB_BASE            0x4F000000      /* USB */
+
+#ifdef CONFIG_REALVIEW_EB_ARM11MP_REVB
+#define REALVIEW_EB11MP_SCU_BASE        0x10100000      /* SCU registers */
+#define REALVIEW_EB11MP_GIC_CPU_BASE    0x10100100      /* Generic interrupt controller CPU interface */
+#define REALVIEW_EB11MP_TWD_BASE        0x10100700
+#define REALVIEW_EB11MP_TWD_SIZE        0x00000100
+#define REALVIEW_EB11MP_GIC_DIST_BASE   0x10101000      /* Generic interrupt controller distributor */
+#define REALVIEW_EB11MP_L220_BASE       0x10102000      /* L220 registers */
+#define REALVIEW_EB11MP_SYS_PLD_CTRL1   0xD8            /* Register offset for MPCore sysctl */
+#else
+#define REALVIEW_EB11MP_SCU_BASE        0x1F000000      /* SCU registers */
+#define REALVIEW_EB11MP_GIC_CPU_BASE    0x1F000100      /* Generic interrupt controller CPU interface */
+#define REALVIEW_EB11MP_TWD_BASE        0x1F000700
+#define REALVIEW_EB11MP_TWD_SIZE        0x00000100
+#define REALVIEW_EB11MP_GIC_DIST_BASE   0x1F001000      /* Generic interrupt controller distributor */
+#define REALVIEW_EB11MP_L220_BASE       0x1F002000      /* L220 registers */
+#define REALVIEW_EB11MP_SYS_PLD_CTRL1   0x74            /* Register offset for MPCore sysctl */
+#endif
+
+#define IRQ_EB_GIC_START        32
+
+/*
+ * RealView EB interrupt sources
+ */
+#define IRQ_EB_WDOG             (IRQ_EB_GIC_START + 0)          /* Watchdog timer */
+#define IRQ_EB_SOFT             (IRQ_EB_GIC_START + 1)          /* Software interrupt */
+#define IRQ_EB_COMMRx           (IRQ_EB_GIC_START + 2)          /* Debug Comm Rx interrupt */
+#define IRQ_EB_COMMTx           (IRQ_EB_GIC_START + 3)          /* Debug Comm Tx interrupt */
+#define IRQ_EB_TIMER0_1         (IRQ_EB_GIC_START + 4)          /* Timer 0 and 1 */
+#define IRQ_EB_TIMER2_3         (IRQ_EB_GIC_START + 5)          /* Timer 2 and 3 */
+#define IRQ_EB_GPIO0            (IRQ_EB_GIC_START + 6)          /* GPIO 0 */
+#define IRQ_EB_GPIO1            (IRQ_EB_GIC_START + 7)          /* GPIO 1 */
+#define IRQ_EB_GPIO2            (IRQ_EB_GIC_START + 8)          /* GPIO 2 */
+                                                                /* 9 reserved */
+#define IRQ_EB_RTC              (IRQ_EB_GIC_START + 10)         /* Real Time Clock */
+#define IRQ_EB_SSP              (IRQ_EB_GIC_START + 11)         /* Synchronous Serial Port */
+#define IRQ_EB_UART0            (IRQ_EB_GIC_START + 12)         /* UART 0 on development chip */
+#define IRQ_EB_UART1            (IRQ_EB_GIC_START + 13)         /* UART 1 on development chip */
+#define IRQ_EB_UART2            (IRQ_EB_GIC_START + 14)         /* UART 2 on development chip */
+#define IRQ_EB_UART3            (IRQ_EB_GIC_START + 15)         /* UART 3 on development chip */
+#define IRQ_EB_SCI              (IRQ_EB_GIC_START + 16)         /* Smart Card Interface */
+#define IRQ_EB_MMCI0A           (IRQ_EB_GIC_START + 17)         /* Multimedia Card 0A */
+#define IRQ_EB_MMCI0B           (IRQ_EB_GIC_START + 18)         /* Multimedia Card 0B */
+#define IRQ_EB_AACI             (IRQ_EB_GIC_START + 19)         /* Audio Codec */
+#define IRQ_EB_KMI0             (IRQ_EB_GIC_START + 20)         /* Keyboard/Mouse port 0 */
+#define IRQ_EB_KMI1             (IRQ_EB_GIC_START + 21)         /* Keyboard/Mouse port 1 */
+#define IRQ_EB_CHARLCD          (IRQ_EB_GIC_START + 22)         /* Character LCD */
+#define IRQ_EB_CLCD             (IRQ_EB_GIC_START + 23)         /* CLCD controller */
+#define IRQ_EB_DMA              (IRQ_EB_GIC_START + 24)         /* DMA controller */
+#define IRQ_EB_PWRFAIL          (IRQ_EB_GIC_START + 25)         /* Power failure */
+#define IRQ_EB_PISMO            (IRQ_EB_GIC_START + 26)         /* PISMO interface */
+#define IRQ_EB_DoC              (IRQ_EB_GIC_START + 27)         /* Disk on Chip memory controller */
+#define IRQ_EB_ETH              (IRQ_EB_GIC_START + 28)         /* Ethernet controller */
+#define IRQ_EB_USB              (IRQ_EB_GIC_START + 29)         /* USB controller */
+#define IRQ_EB_TSPEN            (IRQ_EB_GIC_START + 30)         /* Touchscreen pen */
+#define IRQ_EB_TSKPAD           (IRQ_EB_GIC_START + 31)         /* Touchscreen keypad */
+
+/*
+ * RealView EB + ARM11MPCore interrupt sources (primary GIC on the core tile)
+ */
+#define IRQ_EB11MP_AACI         (IRQ_EB_GIC_START + 0)
+#define IRQ_EB11MP_TIMER0_1     (IRQ_EB_GIC_START + 1)
+#define IRQ_EB11MP_TIMER2_3     (IRQ_EB_GIC_START + 2)
+#define IRQ_EB11MP_USB          (IRQ_EB_GIC_START + 3)
+#define IRQ_EB11MP_UART0        (IRQ_EB_GIC_START + 4)
+#define IRQ_EB11MP_UART1        (IRQ_EB_GIC_START + 5)
+#define IRQ_EB11MP_RTC          (IRQ_EB_GIC_START + 6)
+#define IRQ_EB11MP_KMI0         (IRQ_EB_GIC_START + 7)
+#define IRQ_EB11MP_KMI1         (IRQ_EB_GIC_START + 8)
+#define IRQ_EB11MP_ETH          (IRQ_EB_GIC_START + 9)
+#define IRQ_EB11MP_EB_IRQ1      (IRQ_EB_GIC_START + 10)         /* main GIC */
+#define IRQ_EB11MP_EB_IRQ2      (IRQ_EB_GIC_START + 11)         /* tile GIC */
+#define IRQ_EB11MP_EB_FIQ1      (IRQ_EB_GIC_START + 12)         /* main GIC */
+#define IRQ_EB11MP_EB_FIQ2      (IRQ_EB_GIC_START + 13)         /* tile GIC */
+#define IRQ_EB11MP_MMCI0A       (IRQ_EB_GIC_START + 14)
+#define IRQ_EB11MP_MMCI0B       (IRQ_EB_GIC_START + 15)
+
+#define IRQ_EB11MP_PMU_CPU0     (IRQ_EB_GIC_START + 17)
+#define IRQ_EB11MP_PMU_CPU1     (IRQ_EB_GIC_START + 18)
+#define IRQ_EB11MP_PMU_CPU2     (IRQ_EB_GIC_START + 19)
+#define IRQ_EB11MP_PMU_CPU3     (IRQ_EB_GIC_START + 20)
+#define IRQ_EB11MP_PMU_SCU0     (IRQ_EB_GIC_START + 21)
+#define IRQ_EB11MP_PMU_SCU1     (IRQ_EB_GIC_START + 22)
+#define IRQ_EB11MP_PMU_SCU2     (IRQ_EB_GIC_START + 23)
+#define IRQ_EB11MP_PMU_SCU3     (IRQ_EB_GIC_START + 24)
+#define IRQ_EB11MP_PMU_SCU4     (IRQ_EB_GIC_START + 25)
+#define IRQ_EB11MP_PMU_SCU5     (IRQ_EB_GIC_START + 26)
+#define IRQ_EB11MP_PMU_SCU6     (IRQ_EB_GIC_START + 27)
+#define IRQ_EB11MP_PMU_SCU7     (IRQ_EB_GIC_START + 28)
+
+#define IRQ_EB11MP_L220_EVENT   (IRQ_EB_GIC_START + 29)
+#define IRQ_EB11MP_L220_SLAVE   (IRQ_EB_GIC_START + 30)
+#define IRQ_EB11MP_L220_DECODE  (IRQ_EB_GIC_START + 31)
+
+#define IRQ_EB11MP_UART2        -1
+#define IRQ_EB11MP_UART3        -1
+#define IRQ_EB11MP_CLCD         -1
+#define IRQ_EB11MP_DMA          -1
+#define IRQ_EB11MP_WDOG         -1
+#define IRQ_EB11MP_GPIO0        -1
+#define IRQ_EB11MP_GPIO1        -1
+#define IRQ_EB11MP_GPIO2        -1
+#define IRQ_EB11MP_SCI          -1
+#define IRQ_EB11MP_SSP          -1
+
+#define NR_GIC_EB11MP           2
+
+/*
+ * Only define NR_IRQS if less than NR_IRQS_EB
+ */
+#define NR_IRQS_EB              (IRQ_EB_GIC_START + 96)
+
+#if defined(CONFIG_MACH_REALVIEW_EB) \
+        && (!defined(NR_IRQS) || (NR_IRQS < NR_IRQS_EB))
+#undef NR_IRQS
+#define NR_IRQS                 NR_IRQS_EB
+#endif
+
+#if defined(CONFIG_REALVIEW_EB_ARM11MP) \
+        && (!defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_EB11MP))
+#undef MAX_GIC_NR
+#define MAX_GIC_NR              NR_GIC_EB11MP
+#endif
+
+/*
+ * Core tile identification (REALVIEW_SYS_PROCID)
+ */
+#define REALVIEW_EB_PROC_MASK           0xFF000000
+#define REALVIEW_EB_PROC_ARM7TDMI       0x00000000
+#define REALVIEW_EB_PROC_ARM9           0x02000000
+#define REALVIEW_EB_PROC_ARM11          0x04000000
+#define REALVIEW_EB_PROC_ARM11MP        0x06000000
+
+#define check_eb_proc(proc_type)                                                \
+        ((readl(__io_address(REALVIEW_SYS_PROCID)) & REALVIEW_EB_PROC_MASK)     \
+         == proc_type)
+
+#ifdef CONFIG_REALVIEW_EB_ARM11MP
+#define core_tile_eb11mp()      check_eb_proc(REALVIEW_EB_PROC_ARM11MP)
+#else
+#define core_tile_eb11mp()      0
+#endif
+
+#endif  /* __ASM_ARCH_BOARD_EB_H */
diff --git a/arch/arm/mach-realview/include/mach/board-pb1176.h b/arch/arm/mach-realview/include/mach/board-pb1176.h
new file mode 100644
index 000000000000..858eea7b1adc
--- /dev/null
+++ b/arch/arm/mach-realview/include/mach/board-pb1176.h
@@ -0,0 +1,152 @@
+/*
+ * arch/arm/mach-realview/include/mach/board-pb1176.h
+ *
+ * Copyright (C) 2008 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_BOARD_PB1176_H
+#define __ASM_ARCH_BOARD_PB1176_H
+
+#include <mach/platform.h>
+
+/*
+ * Peripheral addresses
+ */
+#define REALVIEW_PB1176_SCTL_BASE               0x10100000 /* System controller */
+#define REALVIEW_PB1176_SMC_BASE                0x10111000 /* SMC */
+#define REALVIEW_PB1176_DMC_BASE                0x10109000 /* DMC configuration */
+#define REALVIEW_PB1176_SDRAM67_BASE            0x70000000 /* SDRAM banks 6 and 7 */
+#define REALVIEW_PB1176_FLASH_BASE              0x30000000
+#define REALVIEW_PB1176_FLASH_SIZE              SZ_64M
+
+#define REALVIEW_PB1176_TIMER0_1_BASE           0x10104000 /* Timer 0 and 1 */
+#define REALVIEW_PB1176_TIMER2_3_BASE           0x10105000 /* Timer 2 and 3 */
+#define REALVIEW_PB1176_TIMER4_5_BASE           0x10106000 /* Timer 4 and 5 */
+#define REALVIEW_PB1176_WATCHDOG_BASE           0x10107000 /* watchdog interface */
+#define REALVIEW_PB1176_RTC_BASE                0x10108000 /* Real Time Clock */
+#define REALVIEW_PB1176_GPIO0_BASE              0x1010A000 /* GPIO port 0 */
+#define REALVIEW_PB1176_SSP_BASE                0x1010B000 /* Synchronous Serial Port */
+#define REALVIEW_PB1176_UART0_BASE              0x1010C000 /* UART 0 */
+#define REALVIEW_PB1176_UART1_BASE              0x1010D000 /* UART 1 */
+#define REALVIEW_PB1176_UART2_BASE              0x1010E000 /* UART 2 */
+#define REALVIEW_PB1176_UART3_BASE              0x1010F000 /* UART 3 */
+#define REALVIEW_PB1176_CLCD_BASE               0x10112000 /* CLCD */
+#define REALVIEW_PB1176_ETH_BASE                0x3A000000 /* Ethernet */
+#define REALVIEW_PB1176_USB_BASE                0x3B000000 /* USB */
+
+/*
+ * PCI regions
+ */
+#define REALVIEW_PB1176_PCI_BASE                0x60000000 /* PCI self config */
+#define REALVIEW_PB1176_PCI_CFG_BASE            0x61000000 /* PCI config */
+#define REALVIEW_PB1176_PCI_IO_BASE0            0x62000000 /* PCI IO region */
+#define REALVIEW_PB1176_PCI_MEM_BASE0           0x63000000 /* Memory region 1 */
+#define REALVIEW_PB1176_PCI_MEM_BASE1           0x64000000 /* Memory region 2 */
+#define REALVIEW_PB1176_PCI_MEM_BASE2           0x68000000 /* Memory region 3 */
+
+#define REALVIEW_PB1176_PCI_BASE_SIZE           0x01000000 /* 16MB */
+#define REALVIEW_PB1176_PCI_CFG_BASE_SIZE       0x01000000 /* 16MB */
+#define REALVIEW_PB1176_PCI_IO_BASE0_SIZE       0x01000000 /* 16MB */
+#define REALVIEW_PB1176_PCI_MEM_BASE0_SIZE      0x01000000 /* 16MB */
+#define REALVIEW_PB1176_PCI_MEM_BASE1_SIZE      0x04000000 /* 64MB */
+#define REALVIEW_PB1176_PCI_MEM_BASE2_SIZE      0x08000000 /* 128MB */
+
+#define REALVIEW_DC1176_GIC_CPU_BASE            0x10120000 /* GIC CPU interface, on devchip */
+#define REALVIEW_DC1176_GIC_DIST_BASE           0x10121000 /* GIC distributor, on devchip */
+#define REALVIEW_PB1176_GIC_CPU_BASE            0x10040000 /* GIC CPU interface, on FPGA */
+#define REALVIEW_PB1176_GIC_DIST_BASE           0x10041000 /* GIC distributor, on FPGA */
+#define REALVIEW_PB1176_L220_BASE               0x10110000 /* L220 registers */
+
+/*
+ * Irqs
+ */
+#define IRQ_DC1176_GIC_START                    32
+#define IRQ_PB1176_GIC_START                    64
+
+/*
+ * ARM1176 DevChip interrupt sources (primary GIC)
+ */
+#define IRQ_DC1176_WATCHDOG     (IRQ_DC1176_GIC_START + 0)      /* Watchdog timer */
+#define IRQ_DC1176_SOFTINT      (IRQ_DC1176_GIC_START + 1)      /* Software interrupt */
+#define IRQ_DC1176_COMMRx       (IRQ_DC1176_GIC_START + 2)      /* Debug Comm Rx interrupt */
+#define IRQ_DC1176_COMMTx       (IRQ_DC1176_GIC_START + 3)      /* Debug Comm Tx interrupt */
+#define IRQ_DC1176_TIMER0       (IRQ_DC1176_GIC_START + 8)      /* Timer 0 */
+#define IRQ_DC1176_TIMER1       (IRQ_DC1176_GIC_START + 9)      /* Timer 1 */
+#define IRQ_DC1176_TIMER2       (IRQ_DC1176_GIC_START + 10)     /* Timer 2 */
+#define IRQ_DC1176_APC          (IRQ_DC1176_GIC_START + 11)
+#define IRQ_DC1176_IEC          (IRQ_DC1176_GIC_START + 12)
+#define IRQ_DC1176_L2CC         (IRQ_DC1176_GIC_START + 13)
+#define IRQ_DC1176_RTC          (IRQ_DC1176_GIC_START + 14)
+#define IRQ_DC1176_CLCD         (IRQ_DC1176_GIC_START + 15)     /* CLCD controller */
+#define IRQ_DC1176_UART0        (IRQ_DC1176_GIC_START + 18)     /* UART 0 on development chip */
+#define IRQ_DC1176_UART1        (IRQ_DC1176_GIC_START + 19)     /* UART 1 on development chip */
+#define IRQ_DC1176_UART2        (IRQ_DC1176_GIC_START + 20)     /* UART 2 on development chip */
+#define IRQ_DC1176_UART3        (IRQ_DC1176_GIC_START + 21)     /* UART 3 on development chip */
+
+#define IRQ_DC1176_PB_IRQ2      (IRQ_DC1176_GIC_START + 30)     /* tile GIC */
+#define IRQ_DC1176_PB_IRQ1      (IRQ_DC1176_GIC_START + 31)     /* main GIC */
+
+/*
+ * RealView PB1176 interrupt sources (secondary GIC)
+ */
+#define IRQ_PB1176_MMCI0A       (IRQ_PB1176_GIC_START + 1)      /* Multimedia Card 0A */
+#define IRQ_PB1176_MMCI0B       (IRQ_PB1176_GIC_START + 2)      /* Multimedia Card 0A */
+#define IRQ_PB1176_KMI0         (IRQ_PB1176_GIC_START + 3)      /* Keyboard/Mouse port 0 */
+#define IRQ_PB1176_KMI1         (IRQ_PB1176_GIC_START + 4)      /* Keyboard/Mouse port 1 */
+#define IRQ_PB1176_SCI          (IRQ_PB1176_GIC_START + 5)
+#define IRQ_PB1176_UART4        (IRQ_PB1176_GIC_START + 6)      /* UART 4 on baseboard */
+#define IRQ_PB1176_CHARLCD      (IRQ_PB1176_GIC_START + 7)      /* Character LCD */
+#define IRQ_PB1176_GPIO1        (IRQ_PB1176_GIC_START + 8)
+#define IRQ_PB1176_GPIO2        (IRQ_PB1176_GIC_START + 9)
+#define IRQ_PB1176_ETH          (IRQ_PB1176_GIC_START + 10)     /* Ethernet controller */
+#define IRQ_PB1176_USB          (IRQ_PB1176_GIC_START + 11)     /* USB controller */
+
+#define IRQ_PB1176_PISMO        (IRQ_PB1176_GIC_START + 16)
+
+#define IRQ_PB1176_AACI         (IRQ_PB1176_GIC_START + 19)     /* Audio Codec */
+
+#define IRQ_PB1176_TIMER0_1     (IRQ_PB1176_GIC_START + 22)
+#define IRQ_PB1176_TIMER2_3     (IRQ_PB1176_GIC_START + 23)
+#define IRQ_PB1176_DMAC         (IRQ_PB1176_GIC_START + 24)     /* DMA controller */
+#define IRQ_PB1176_RTC          (IRQ_PB1176_GIC_START + 25)     /* Real Time Clock */
+
+#define IRQ_PB1176_GPIO0        -1
+#define IRQ_PB1176_SSP          -1
+#define IRQ_PB1176_SCTL         -1
+
+#define NR_GIC_PB1176           2
+
+/*
+ * Only define NR_IRQS if less than NR_IRQS_PB1176
+ */
+#define NR_IRQS_PB1176          (IRQ_DC1176_GIC_START + 96)
+
+#if defined(CONFIG_MACH_REALVIEW_PB1176)
+
+#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PB1176)
+#undef NR_IRQS
+#define NR_IRQS                 NR_IRQS_PB1176
+#endif
+
+#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PB1176)
+#undef MAX_GIC_NR
+#define MAX_GIC_NR              NR_GIC_PB1176
+#endif
+
+#endif  /* CONFIG_MACH_REALVIEW_PB1176 */
+
+#endif  /* __ASM_ARCH_BOARD_PB1176_H */
diff --git a/arch/arm/mach-realview/include/mach/board-pb11mp.h b/arch/arm/mach-realview/include/mach/board-pb11mp.h
new file mode 100644
index 000000000000..ecd80e58631e
--- /dev/null
+++ b/arch/arm/mach-realview/include/mach/board-pb11mp.h
@@ -0,0 +1,186 @@
+/*
+ * arch/arm/mach-realview/include/mach/board-pb11mp.h
+ *
+ * Copyright (C) 2008 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_BOARD_PB11MP_H
+#define __ASM_ARCH_BOARD_PB11MP_H
+
+#include <mach/platform.h>
+
+/*
+ * Peripheral addresses
+ */
+#define REALVIEW_PB11MP_UART0_BASE              0x10009000      /* UART 0 */
+#define REALVIEW_PB11MP_UART1_BASE              0x1000A000      /* UART 1 */
+#define REALVIEW_PB11MP_UART2_BASE              0x1000B000      /* UART 2 */
+#define REALVIEW_PB11MP_UART3_BASE              0x1000C000      /* UART 3 */
+#define REALVIEW_PB11MP_SSP_BASE                0x1000D000      /* Synchronous Serial Port */
+#define REALVIEW_PB11MP_WATCHDOG0_BASE          0x1000F000      /* Watchdog 0 */
+#define REALVIEW_PB11MP_WATCHDOG_BASE           0x10010000      /* watchdog interface */
+#define REALVIEW_PB11MP_TIMER0_1_BASE           0x10011000      /* Timer 0 and 1 */
+#define REALVIEW_PB11MP_TIMER2_3_BASE           0x10012000      /* Timer 2 and 3 */
+#define REALVIEW_PB11MP_GPIO0_BASE              0x10013000      /* GPIO port 0 */
+#define REALVIEW_PB11MP_RTC_BASE                0x10017000      /* Real Time Clock */
+#define REALVIEW_PB11MP_TIMER4_5_BASE           0x10018000      /* Timer 4/5 */
+#define REALVIEW_PB11MP_TIMER6_7_BASE           0x10019000      /* Timer 6/7 */
+#define REALVIEW_PB11MP_SCTL_BASE               0x1001A000      /* System Controller */
+#define REALVIEW_PB11MP_CLCD_BASE               0x10020000      /* CLCD */
+#define REALVIEW_PB11MP_ONB_SRAM_BASE           0x10060000      /* On-board SRAM */
+#define REALVIEW_PB11MP_DMC_BASE                0x100E0000      /* DMC configuration */
+#define REALVIEW_PB11MP_SMC_BASE                0x100E1000      /* SMC configuration */
+#define REALVIEW_PB11MP_CAN_BASE                0x100E2000      /* CAN bus */
+#define REALVIEW_PB11MP_CF_BASE                 0x18000000      /* Compact flash */
+#define REALVIEW_PB11MP_CF_MEM_BASE             0x18003000      /* SMC for Compact flash */
+#define REALVIEW_PB11MP_GIC_CPU_BASE            0x1E000000      /* Generic interrupt controller CPU interface */
+#define REALVIEW_PB11MP_FLASH0_BASE             0x40000000
+#define REALVIEW_PB11MP_FLASH0_SIZE             SZ_64M
+#define REALVIEW_PB11MP_FLASH1_BASE             0x44000000
+#define REALVIEW_PB11MP_FLASH1_SIZE             SZ_64M
+#define REALVIEW_PB11MP_ETH_BASE                0x4E000000      /* Ethernet */
+#define REALVIEW_PB11MP_USB_BASE                0x4F000000      /* USB */
+#define REALVIEW_PB11MP_GIC_DIST_BASE           0x1E001000      /* Generic interrupt controller distributor */
+#define REALVIEW_PB11MP_LT_BASE                 0xC0000000      /* Logic Tile expansion */
+#define REALVIEW_PB11MP_SDRAM6_BASE             0x70000000      /* SDRAM bank 6 256MB */
+#define REALVIEW_PB11MP_SDRAM7_BASE             0x80000000      /* SDRAM bank 7 256MB */
+
+#define REALVIEW_PB11MP_SYS_PLD_CTRL1           0x74
+
+/*
+ * PB11MPCore PCI regions
+ */
+#define REALVIEW_PB11MP_PCI_BASE                0x90040000      /* PCI-X Unit base */
+#define REALVIEW_PB11MP_PCI_IO_BASE             0x90050000      /* IO Region on AHB */
+#define REALVIEW_PB11MP_PCI_MEM_BASE            0xA0000000      /* MEM Region on AHB */
+
+#define REALVIEW_PB11MP_PCI_BASE_SIZE           0x10000         /* 16 Kb */
+#define REALVIEW_PB11MP_PCI_IO_SIZE             0x1000          /* 4 Kb */
+#define REALVIEW_PB11MP_PCI_MEM_SIZE            0x20000000      /* 512 MB */
+
+/*
+ * Testchip peripheral and fpga gic regions
+ */
+#define REALVIEW_TC11MP_SCU_BASE                0x1F000000      /* IRQ, Test chip */
+#define REALVIEW_TC11MP_GIC_CPU_BASE            0x1F000100      /* Test chip interrupt controller CPU interface */
+#define REALVIEW_TC11MP_TWD_BASE                0x1F000700
+#define REALVIEW_TC11MP_TWD_SIZE                0x00000100
+#define REALVIEW_TC11MP_GIC_DIST_BASE           0x1F001000      /* Test chip interrupt controller distributor */
+#define REALVIEW_TC11MP_L220_BASE               0x1F002000      /* L220 registers */
+
+/*
+ * Irqs
+ */
+#define IRQ_TC11MP_GIC_START                    32
+#define IRQ_PB11MP_GIC_START                    64
+
+/*
+ * ARM11MPCore test chip interrupt sources (primary GIC on the test chip)
+ */
+#define IRQ_TC11MP_AACI         (IRQ_TC11MP_GIC_START + 0)
+#define IRQ_TC11MP_TIMER0_1     (IRQ_TC11MP_GIC_START + 1)
+#define IRQ_TC11MP_TIMER2_3     (IRQ_TC11MP_GIC_START + 2)
+#define IRQ_TC11MP_USB          (IRQ_TC11MP_GIC_START + 3)
+#define IRQ_TC11MP_UART0        (IRQ_TC11MP_GIC_START + 4)
+#define IRQ_TC11MP_UART1        (IRQ_TC11MP_GIC_START + 5)
+#define IRQ_TC11MP_RTC          (IRQ_TC11MP_GIC_START + 6)
+#define IRQ_TC11MP_KMI0         (IRQ_TC11MP_GIC_START + 7)
+#define IRQ_TC11MP_KMI1         (IRQ_TC11MP_GIC_START + 8)
+#define IRQ_TC11MP_ETH          (IRQ_TC11MP_GIC_START + 9)
+#define IRQ_TC11MP_PB_IRQ1      (IRQ_TC11MP_GIC_START + 10)             /* main GIC */
+#define IRQ_TC11MP_PB_IRQ2      (IRQ_TC11MP_GIC_START + 11)             /* tile GIC */
+#define IRQ_TC11MP_PB_FIQ1      (IRQ_TC11MP_GIC_START + 12)             /* main GIC */
+#define IRQ_TC11MP_PB_FIQ2      (IRQ_TC11MP_GIC_START + 13)             /* tile GIC */
+#define IRQ_TC11MP_MMCI0A       (IRQ_TC11MP_GIC_START + 14)
+#define IRQ_TC11MP_MMCI0B       (IRQ_TC11MP_GIC_START + 15)
+
+#define IRQ_TC11MP_PMU_CPU0     (IRQ_TC11MP_GIC_START + 17)
+#define IRQ_TC11MP_PMU_CPU1     (IRQ_TC11MP_GIC_START + 18)
+#define IRQ_TC11MP_PMU_CPU2     (IRQ_TC11MP_GIC_START + 19)
+#define IRQ_TC11MP_PMU_CPU3     (IRQ_TC11MP_GIC_START + 20)
+#define IRQ_TC11MP_PMU_SCU0     (IRQ_TC11MP_GIC_START + 21)
+#define IRQ_TC11MP_PMU_SCU1     (IRQ_TC11MP_GIC_START + 22)
+#define IRQ_TC11MP_PMU_SCU2     (IRQ_TC11MP_GIC_START + 23)
+#define IRQ_TC11MP_PMU_SCU3     (IRQ_TC11MP_GIC_START + 24)
+#define IRQ_TC11MP_PMU_SCU4     (IRQ_TC11MP_GIC_START + 25)
+#define IRQ_TC11MP_PMU_SCU5     (IRQ_TC11MP_GIC_START + 26)
+#define IRQ_TC11MP_PMU_SCU6     (IRQ_TC11MP_GIC_START + 27)
+#define IRQ_TC11MP_PMU_SCU7     (IRQ_TC11MP_GIC_START + 28)
+
+#define IRQ_TC11MP_L220_EVENT   (IRQ_TC11MP_GIC_START + 29)
+#define IRQ_TC11MP_L220_SLAVE   (IRQ_TC11MP_GIC_START + 30)
+#define IRQ_TC11MP_L220_DECODE  (IRQ_TC11MP_GIC_START + 31)
+
+/*
+ * RealView PB11MPCore GIC interrupt sources (secondary GIC on the board)
+ */
+#define IRQ_PB11MP_WATCHDOG     (IRQ_PB11MP_GIC_START + 0)      /* Watchdog timer */
+#define IRQ_PB11MP_SOFT         (IRQ_PB11MP_GIC_START + 1)      /* Software interrupt */
+#define IRQ_PB11MP_COMMRx       (IRQ_PB11MP_GIC_START + 2)      /* Debug Comm Rx interrupt */
+#define IRQ_PB11MP_COMMTx       (IRQ_PB11MP_GIC_START + 3)      /* Debug Comm Tx interrupt */
+#define IRQ_PB11MP_GPIO0        (IRQ_PB11MP_GIC_START + 6)      /* GPIO 0 */
+#define IRQ_PB11MP_GPIO1        (IRQ_PB11MP_GIC_START + 7)      /* GPIO 1 */
+#define IRQ_PB11MP_GPIO2        (IRQ_PB11MP_GIC_START + 8)      /* GPIO 2 */
+                                                                /* 9 reserved */
+#define IRQ_PB11MP_RTC_GIC1     (IRQ_PB11MP_GIC_START + 10)     /* Real Time Clock */
+#define IRQ_PB11MP_SSP          (IRQ_PB11MP_GIC_START + 11)     /* Synchronous Serial Port */
+#define IRQ_PB11MP_UART0_GIC1   (IRQ_PB11MP_GIC_START + 12)     /* UART 0 on development chip */
+#define IRQ_PB11MP_UART1_GIC1   (IRQ_PB11MP_GIC_START + 13)     /* UART 1 on development chip */
+#define IRQ_PB11MP_UART2        (IRQ_PB11MP_GIC_START + 14)     /* UART 2 on development chip */
+#define IRQ_PB11MP_UART3        (IRQ_PB11MP_GIC_START + 15)     /* UART 3 on development chip */
+#define IRQ_PB11MP_SCI          (IRQ_PB11MP_GIC_START + 16)     /* Smart Card Interface */
+#define IRQ_PB11MP_MMCI0A_GIC1  (IRQ_PB11MP_GIC_START + 17)     /* Multimedia Card 0A */
+#define IRQ_PB11MP_MMCI0B_GIC1  (IRQ_PB11MP_GIC_START + 18)     /* Multimedia Card 0B */
+#define IRQ_PB11MP_AACI_GIC1    (IRQ_PB11MP_GIC_START + 19)     /* Audio Codec */
+#define IRQ_PB11MP_KMI0_GIC1    (IRQ_PB11MP_GIC_START + 20)     /* Keyboard/Mouse port 0 */
+#define IRQ_PB11MP_KMI1_GIC1    (IRQ_PB11MP_GIC_START + 21)     /* Keyboard/Mouse port 1 */
+#define IRQ_PB11MP_CHARLCD      (IRQ_PB11MP_GIC_START + 22)     /* Character LCD */
+#define IRQ_PB11MP_CLCD         (IRQ_PB11MP_GIC_START + 23)     /* CLCD controller */
+#define IRQ_PB11MP_DMAC         (IRQ_PB11MP_GIC_START + 24)     /* DMA controller */
+#define IRQ_PB11MP_PWRFAIL      (IRQ_PB11MP_GIC_START + 25)     /* Power failure */
+#define IRQ_PB11MP_PISMO        (IRQ_PB11MP_GIC_START + 26)     /* PISMO interface */
+#define IRQ_PB11MP_DoC          (IRQ_PB11MP_GIC_START + 27)     /* Disk on Chip memory controller */
+#define IRQ_PB11MP_ETH_GIC1     (IRQ_PB11MP_GIC_START + 28)     /* Ethernet controller */
+#define IRQ_PB11MP_USB_GIC1     (IRQ_PB11MP_GIC_START + 29)     /* USB controller */
+#define IRQ_PB11MP_TSPEN        (IRQ_PB11MP_GIC_START + 30)     /* Touchscreen pen */
+#define IRQ_PB11MP_TSKPAD       (IRQ_PB11MP_GIC_START + 31)     /* Touchscreen keypad */
+
+#define IRQ_PB11MP_SMC          -1
+#define IRQ_PB11MP_SCTL         -1
+
+#define NR_GIC_PB11MP           2
+
+/*
+ * Only define NR_IRQS if less than NR_IRQS_PB11MP
+ */
+#define NR_IRQS_PB11MP          (IRQ_TC11MP_GIC_START + 96)
+
+#if defined(CONFIG_MACH_REALVIEW_PB11MP)
+
+#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PB11MP)
+#undef NR_IRQS
+#define NR_IRQS                 NR_IRQS_PB11MP
+#endif
+
+#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PB11MP)
+#undef MAX_GIC_NR
+#define MAX_GIC_NR              NR_GIC_PB11MP
+#endif
+
+#endif  /* CONFIG_MACH_REALVIEW_PB11MP */
+
+#endif  /* __ASM_ARCH_BOARD_PB11MP_H */
diff --git a/arch/arm/mach-realview/include/mach/debug-macro.S b/arch/arm/mach-realview/include/mach/debug-macro.S
new file mode 100644
index 000000000000..7196bcadff0c
--- /dev/null
+++ b/arch/arm/mach-realview/include/mach/debug-macro.S
@@ -0,0 +1,22 @@
+/* arch/arm/mach-realview/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx,      #0x10000000
+                movne   \rx,      #0xf0000000   @ virtual base
+                orr     \rx, \rx, #0x00009000
+                .endm
+
+#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-realview/include/mach/dma.h b/arch/arm/mach-realview/include/mach/dma.h
new file mode 100644
index 000000000000..f1a5a1a10952
--- /dev/null
+++ b/arch/arm/mach-realview/include/mach/dma.h
@@ -0,0 +1,20 @@
+/*
+ *  arch/arm/mach-realview/include/mach/dma.h
+ *
+ *  Copyright (C) 2003 ARM Limited.
+ *  Copyright (C) 1997,1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
diff --git a/arch/arm/mach-realview/include/mach/entry-macro.S b/arch/arm/mach-realview/include/mach/entry-macro.S
new file mode 100644
index 000000000000..340a5c276946
--- /dev/null
+++ b/arch/arm/mach-realview/include/mach/entry-macro.S
@@ -0,0 +1,81 @@
+/*
+ * arch/arm/mach-realview/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for RealView platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <mach/hardware.h>
+#include <asm/hardware/gic.h>
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_preamble, base, tmp
+                ldr     \base, =gic_cpu_base_addr
+                ldr     \base, [\base]
+                .endm
+
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
+
+                /*
+                 * The interrupt numbering scheme is defined in the
+                 * interrupt controller spec.  To wit:
+                 *
+                 * Interrupts 0-15 are IPI
+                 * 16-28 are reserved
+                 * 29-31 are local.  We allow 30 to be used for the watchdog.
+                 * 32-1020 are global
+                 * 1021-1022 are reserved
+                 * 1023 is "spurious" (no interrupt)
+                 *
+                 * For now, we ignore all local interrupts so only return an interrupt if it's
+                 * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
+                 *
+                 * A simple read from the controller will tell us the number of the highest
+                 * priority enabled interrupt.  We then just need to check whether it is in the
+                 * valid range for an IRQ (30-1020 inclusive).
+                 */
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+                ldr     \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
+
+                ldr     \tmp, =1021
+
+                bic     \irqnr, \irqstat, #0x1c00
+
+                cmp     \irqnr, #29
+                cmpcc   \irqnr, \irqnr
+                cmpne   \irqnr, \tmp
+                cmpcs   \irqnr, \irqnr
+
+                .endm
+
+                /* We assume that irqstat (the raw value of the IRQ acknowledge
+                 * register) is preserved from the macro above.
+                 * If there is an IPI, we immediately signal end of interrupt on the
+                 * controller, since this requires the original irqstat value which
+                 * we won't easily be able to recreate later.
+                 */
+
+                .macro test_for_ipi, irqnr, irqstat, base, tmp
+                bic     \irqnr, \irqstat, #0x1c00
+                cmp     \irqnr, #16
+                strcc   \irqstat, [\base, #GIC_CPU_EOI]
+                cmpcs   \irqnr, \irqnr
+                .endm
+
+                /* As above, this assumes that irqstat and base are preserved.. */
+
+                .macro test_for_ltirq, irqnr, irqstat, base, tmp
+                bic     \irqnr, \irqstat, #0x1c00
+                mov     \tmp, #0
+                cmp     \irqnr, #29
+                moveq   \tmp, #1
+                streq   \irqstat, [\base, #GIC_CPU_EOI]
+                cmp     \tmp, #0
+                .endm
diff --git a/arch/arm/mach-realview/include/mach/hardware.h b/arch/arm/mach-realview/include/mach/hardware.h
new file mode 100644
index 000000000000..79a93b3dfca9
--- /dev/null
+++ b/arch/arm/mach-realview/include/mach/hardware.h
@@ -0,0 +1,31 @@
+/*
+ *  arch/arm/mach-realview/include/mach/hardware.h
+ *
+ *  This file contains the hardware definitions of the RealView boards.
+ *
+ *  Copyright (C) 2003 ARM Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/sizes.h>
+
+/* macro to get at IO space when running virtually */
+#define IO_ADDRESS(x)           (((x) & 0x0fffffff) + 0xf0000000)
+#define __io_address(n)         __io(IO_ADDRESS(n))
+
+#endif
diff --git a/arch/arm/mach-realview/include/mach/io.h b/arch/arm/mach-realview/include/mach/io.h
new file mode 100644
index 000000000000..aa069424d310
--- /dev/null
+++ b/arch/arm/mach-realview/include/mach/io.h
@@ -0,0 +1,33 @@
+/*
+ *  arch/arm/mach-realview/include/mach/io.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+static inline void __iomem *__io(unsigned long addr)
+{
+        return (void __iomem *)addr;
+}
+
+#define __io(a)                 __io(a)
+#define __mem_pci(a)            (a)
+
+#endif
diff --git a/arch/arm/mach-realview/include/mach/irqs.h b/arch/arm/mach-realview/include/mach/irqs.h
new file mode 100644
index 000000000000..02a918529db3
--- /dev/null
+++ b/arch/arm/mach-realview/include/mach/irqs.h
@@ -0,0 +1,38 @@
+/*
+ *  arch/arm/mach-realview/include/mach/irqs.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#include <mach/board-eb.h>
+#include <mach/board-pb11mp.h>
+#include <mach/board-pb1176.h>
+
+#define IRQ_LOCALTIMER          29
+#define IRQ_LOCALWDOG           30
+
+#define IRQ_GIC_START           32
+
+#ifndef NR_IRQS
+#error "NR_IRQS not defined by the board-specific files"
+#endif
+
+#endif
diff --git a/arch/arm/mach-realview/include/mach/memory.h b/arch/arm/mach-realview/include/mach/memory.h
new file mode 100644
index 000000000000..0e673483a141
--- /dev/null
+++ b/arch/arm/mach-realview/include/mach/memory.h
@@ -0,0 +1,38 @@
+/*
+ *  arch/arm/mach-realview/include/mach/memory.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET             UL(0x00000000)
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+#define __virt_to_bus(x)        ((x) - PAGE_OFFSET)
+#define __bus_to_virt(x)        ((x) + PAGE_OFFSET)
+
+#endif
diff --git a/arch/arm/mach-realview/include/mach/platform.h b/arch/arm/mach-realview/include/mach/platform.h
new file mode 100644
index 000000000000..4034b54950c2
--- /dev/null
+++ b/arch/arm/mach-realview/include/mach/platform.h
@@ -0,0 +1,293 @@
+/*
+ * arch/arm/mach-realview/include/mach/platform.h
+ *
+ * Copyright (c) ARM Limited 2003.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_PLATFORM_H
+#define __ASM_ARCH_PLATFORM_H
+
+/*
+ * Memory definitions
+ */
+#define REALVIEW_BOOT_ROM_LO          0x30000000                /* DoC Base (64Mb)...*/
+#define REALVIEW_BOOT_ROM_HI          0x30000000
+#define REALVIEW_BOOT_ROM_BASE        REALVIEW_BOOT_ROM_HI       /*  Normal position */
+#define REALVIEW_BOOT_ROM_SIZE        SZ_64M
+
+#define REALVIEW_SSRAM_BASE           /* REALVIEW_SSMC_BASE ? */
+#define REALVIEW_SSRAM_SIZE           SZ_2M
+
+/* 
+ *  SDRAM
+ */
+#define REALVIEW_SDRAM_BASE           0x00000000
+
+/* 
+ *  Logic expansion modules
+ * 
+ */
+
+
+/* ------------------------------------------------------------------------
+ *  RealView Registers
+ * ------------------------------------------------------------------------
+ * 
+ */
+#define REALVIEW_SYS_ID_OFFSET               0x00
+#define REALVIEW_SYS_SW_OFFSET               0x04
+#define REALVIEW_SYS_LED_OFFSET              0x08
+#define REALVIEW_SYS_OSC0_OFFSET             0x0C
+
+#define REALVIEW_SYS_OSC1_OFFSET             0x10
+#define REALVIEW_SYS_OSC2_OFFSET             0x14
+#define REALVIEW_SYS_OSC3_OFFSET             0x18
+#define REALVIEW_SYS_OSC4_OFFSET             0x1C       /* OSC1 for RealView/AB */
+
+#define REALVIEW_SYS_LOCK_OFFSET             0x20
+#define REALVIEW_SYS_100HZ_OFFSET            0x24
+#define REALVIEW_SYS_CFGDATA1_OFFSET         0x28
+#define REALVIEW_SYS_CFGDATA2_OFFSET         0x2C
+#define REALVIEW_SYS_FLAGS_OFFSET            0x30
+#define REALVIEW_SYS_FLAGSSET_OFFSET         0x30
+#define REALVIEW_SYS_FLAGSCLR_OFFSET         0x34
+#define REALVIEW_SYS_NVFLAGS_OFFSET          0x38
+#define REALVIEW_SYS_NVFLAGSSET_OFFSET       0x38
+#define REALVIEW_SYS_NVFLAGSCLR_OFFSET       0x3C
+#define REALVIEW_SYS_RESETCTL_OFFSET         0x40
+#define REALVIEW_SYS_PCICTL_OFFSET           0x44
+#define REALVIEW_SYS_MCI_OFFSET              0x48
+#define REALVIEW_SYS_FLASH_OFFSET            0x4C
+#define REALVIEW_SYS_CLCD_OFFSET             0x50
+#define REALVIEW_SYS_CLCDSER_OFFSET          0x54
+#define REALVIEW_SYS_BOOTCS_OFFSET           0x58
+#define REALVIEW_SYS_24MHz_OFFSET            0x5C
+#define REALVIEW_SYS_MISC_OFFSET             0x60
+#define REALVIEW_SYS_IOSEL_OFFSET            0x70
+#define REALVIEW_SYS_PROCID_OFFSET           0x84
+#define REALVIEW_SYS_TEST_OSC0_OFFSET        0xC0
+#define REALVIEW_SYS_TEST_OSC1_OFFSET        0xC4
+#define REALVIEW_SYS_TEST_OSC2_OFFSET        0xC8
+#define REALVIEW_SYS_TEST_OSC3_OFFSET        0xCC
+#define REALVIEW_SYS_TEST_OSC4_OFFSET        0xD0
+
+#define REALVIEW_SYS_BASE                    0x10000000
+#define REALVIEW_SYS_ID                      (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET)
+#define REALVIEW_SYS_SW                      (REALVIEW_SYS_BASE + REALVIEW_SYS_SW_OFFSET)
+#define REALVIEW_SYS_LED                     (REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET)
+#define REALVIEW_SYS_OSC0                    (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC0_OFFSET)
+#define REALVIEW_SYS_OSC1                    (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC1_OFFSET)
+
+#define REALVIEW_SYS_LOCK                    (REALVIEW_SYS_BASE + REALVIEW_SYS_LOCK_OFFSET)
+#define REALVIEW_SYS_100HZ                   (REALVIEW_SYS_BASE + REALVIEW_SYS_100HZ_OFFSET)
+#define REALVIEW_SYS_CFGDATA1                (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA1_OFFSET)
+#define REALVIEW_SYS_CFGDATA2                (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA2_OFFSET)
+#define REALVIEW_SYS_FLAGS                   (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGS_OFFSET)
+#define REALVIEW_SYS_FLAGSSET                (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSSET_OFFSET)
+#define REALVIEW_SYS_FLAGSCLR                (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSCLR_OFFSET)
+#define REALVIEW_SYS_NVFLAGS                 (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGS_OFFSET)
+#define REALVIEW_SYS_NVFLAGSSET              (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSSET_OFFSET)
+#define REALVIEW_SYS_NVFLAGSCLR              (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSCLR_OFFSET)
+#define REALVIEW_SYS_RESETCTL                (REALVIEW_SYS_BASE + REALVIEW_SYS_RESETCTL_OFFSET)
+#define REALVIEW_SYS_PCICTL                  (REALVIEW_SYS_BASE + REALVIEW_SYS_PCICTL_OFFSET)
+#define REALVIEW_SYS_MCI                     (REALVIEW_SYS_BASE + REALVIEW_SYS_MCI_OFFSET)
+#define REALVIEW_SYS_FLASH                   (REALVIEW_SYS_BASE + REALVIEW_SYS_FLASH_OFFSET)
+#define REALVIEW_SYS_CLCD                    (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCD_OFFSET)
+#define REALVIEW_SYS_CLCDSER                 (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCDSER_OFFSET)
+#define REALVIEW_SYS_BOOTCS                  (REALVIEW_SYS_BASE + REALVIEW_SYS_BOOTCS_OFFSET)
+#define REALVIEW_SYS_24MHz                   (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET)
+#define REALVIEW_SYS_MISC                    (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET)
+#define REALVIEW_SYS_IOSEL                   (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET)
+#define REALVIEW_SYS_PROCID                  (REALVIEW_SYS_BASE + REALVIEW_SYS_PROCID_OFFSET)
+#define REALVIEW_SYS_TEST_OSC0               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET)
+#define REALVIEW_SYS_TEST_OSC1               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET)
+#define REALVIEW_SYS_TEST_OSC2               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET)
+#define REALVIEW_SYS_TEST_OSC3               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC3_OFFSET)
+#define REALVIEW_SYS_TEST_OSC4               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC4_OFFSET)
+
+/* 
+ * Values for REALVIEW_SYS_RESET_CTRL
+ */
+#define REALVIEW_SYS_CTRL_RESET_CONFIGCLR    0x01
+#define REALVIEW_SYS_CTRL_RESET_CONFIGINIT   0x02
+#define REALVIEW_SYS_CTRL_RESET_DLLRESET     0x03
+#define REALVIEW_SYS_CTRL_RESET_PLLRESET     0x04
+#define REALVIEW_SYS_CTRL_RESET_POR          0x05
+#define REALVIEW_SYS_CTRL_RESET_DoC          0x06
+
+#define REALVIEW_SYS_CTRL_LED         (1 << 0)
+
+
+/* ------------------------------------------------------------------------
+ *  RealView control registers
+ * ------------------------------------------------------------------------
+ */
+
+/* 
+ * REALVIEW_IDFIELD
+ *
+ * 31:24 = manufacturer (0x41 = ARM)
+ * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus)
+ * 15:12 = FPGA (0x3 = XVC600 or XVC600E)
+ * 11:4  = build value
+ * 3:0   = revision number (0x1 = rev B (AHB))
+ */
+
+/*
+ * REALVIEW_SYS_LOCK
+ *     control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL, 
+ *     SYS_CLD, SYS_BOOTCS
+ */
+#define REALVIEW_SYS_LOCK_LOCKED    (1 << 16)
+#define REALVIEW_SYS_LOCKVAL_MASK       0xFFFF          /* write 0xA05F to enable write access */
+
+/*
+ * REALVIEW_SYS_FLASH
+ */
+#define REALVIEW_FLASHPROG_FLVPPEN      (1 << 0)        /* Enable writing to flash */
+
+/*
+ * REALVIEW_INTREG
+ *     - used to acknowledge and control MMCI and UART interrupts 
+ */
+#define REALVIEW_INTREG_WPROT        0x00    /* MMC protection status (no interrupt generated) */
+#define REALVIEW_INTREG_RI0          0x01    /* Ring indicator UART0 is asserted,              */
+#define REALVIEW_INTREG_CARDIN       0x08    /* MMCI card in detect                            */
+                                                /* write 1 to acknowledge and clear               */
+#define REALVIEW_INTREG_RI1          0x02    /* Ring indicator UART1 is asserted,              */
+#define REALVIEW_INTREG_CARDINSERT   0x03    /* Signal insertion of MMC card                   */
+
+/*
+ * RealView common peripheral addresses
+ */
+#define REALVIEW_SCTL_BASE            0x10001000        /* System controller */
+#define REALVIEW_I2C_BASE             0x10002000        /* I2C control */
+#define REALVIEW_AACI_BASE            0x10004000        /* Audio */
+#define REALVIEW_MMCI0_BASE           0x10005000        /* MMC interface */
+#define REALVIEW_KMI0_BASE            0x10006000        /* KMI interface */
+#define REALVIEW_KMI1_BASE            0x10007000        /* KMI 2nd interface */
+#define REALVIEW_CHAR_LCD_BASE        0x10008000        /* Character LCD */
+#define REALVIEW_SCI_BASE             0x1000E000        /* Smart card controller */
+#define REALVIEW_GPIO1_BASE           0x10014000        /* GPIO port 1 */
+#define REALVIEW_GPIO2_BASE           0x10015000        /* GPIO port 2 */
+#define REALVIEW_DMC_BASE             0x10018000        /* DMC configuration */
+#define REALVIEW_DMAC_BASE            0x10030000        /* DMA controller */
+
+/* PCI space */
+#define REALVIEW_PCI_BASE             0x41000000        /* PCI Interface */
+#define REALVIEW_PCI_CFG_BASE         0x42000000
+#define REALVIEW_PCI_MEM_BASE0        0x44000000
+#define REALVIEW_PCI_MEM_BASE1        0x50000000
+#define REALVIEW_PCI_MEM_BASE2        0x60000000
+/* Sizes of above maps */
+#define REALVIEW_PCI_BASE_SIZE         0x01000000
+#define REALVIEW_PCI_CFG_BASE_SIZE    0x02000000
+#define REALVIEW_PCI_MEM_BASE0_SIZE   0x0c000000        /* 32Mb */
+#define REALVIEW_PCI_MEM_BASE1_SIZE   0x10000000        /* 256Mb */
+#define REALVIEW_PCI_MEM_BASE2_SIZE   0x10000000        /* 256Mb */
+
+#define REALVIEW_SDRAM67_BASE         0x70000000        /* SDRAM banks 6 and 7 */
+#define REALVIEW_LT_BASE              0x80000000        /* Logic Tile expansion */
+
+/*
+ * Disk on Chip
+ */
+#define REALVIEW_DOC_BASE             0x2C000000
+#define REALVIEW_DOC_SIZE             (16 << 20)
+#define REALVIEW_DOC_PAGE_SIZE        512
+#define REALVIEW_DOC_TOTAL_PAGES     (DOC_SIZE / PAGE_SIZE)
+
+#define ERASE_UNIT_PAGES    32
+#define START_PAGE          0x80
+
+/* 
+ *  LED settings, bits [7:0]
+ */
+#define REALVIEW_SYS_LED0             (1 << 0)
+#define REALVIEW_SYS_LED1             (1 << 1)
+#define REALVIEW_SYS_LED2             (1 << 2)
+#define REALVIEW_SYS_LED3             (1 << 3)
+#define REALVIEW_SYS_LED4             (1 << 4)
+#define REALVIEW_SYS_LED5             (1 << 5)
+#define REALVIEW_SYS_LED6             (1 << 6)
+#define REALVIEW_SYS_LED7             (1 << 7)
+
+#define ALL_LEDS                  0xFF
+
+#define LED_BANK                  REALVIEW_SYS_LED
+
+/* 
+ * Control registers
+ */
+#define REALVIEW_IDFIELD_OFFSET 0x0     /* RealView build information */
+#define REALVIEW_FLASHPROG_OFFSET       0x4     /* Flash devices */
+#define REALVIEW_INTREG_OFFSET          0x8     /* Interrupt control */
+#define REALVIEW_DECODE_OFFSET          0xC     /* Fitted logic modules */
+
+/* 
+ *  Application Flash
+ * 
+ */
+#define FLASH_BASE                      REALVIEW_FLASH_BASE
+#define FLASH_SIZE                      REALVIEW_FLASH_SIZE
+#define FLASH_END                       (FLASH_BASE + FLASH_SIZE - 1)
+#define FLASH_BLOCK_SIZE                SZ_128K
+
+/* 
+ *  Boot Flash
+ * 
+ */
+#define EPROM_BASE                      REALVIEW_BOOT_ROM_HI
+#define EPROM_SIZE                      REALVIEW_BOOT_ROM_SIZE
+#define EPROM_END                       (EPROM_BASE + EPROM_SIZE - 1)
+
+/* 
+ *  Clean base - dummy
+ * 
+ */
+#define CLEAN_BASE                      EPROM_BASE
+
+/*
+ * System controller bit assignment
+ */
+#define REALVIEW_REFCLK 0
+#define REALVIEW_TIMCLK 1
+
+#define REALVIEW_TIMER1_EnSel   15
+#define REALVIEW_TIMER2_EnSel   17
+#define REALVIEW_TIMER3_EnSel   19
+#define REALVIEW_TIMER4_EnSel   21
+
+
+#define MAX_TIMER                       2
+#define MAX_PERIOD                      699050
+#define TICKS_PER_uSEC                  1
+
+/* 
+ *  These are useconds NOT ticks.  
+ * 
+ */
+#define mSEC_1                          1000
+#define mSEC_5                          (mSEC_1 * 5)
+#define mSEC_10                         (mSEC_1 * 10)
+#define mSEC_25                         (mSEC_1 * 25)
+#define SEC_1                           (mSEC_1 * 1000)
+
+#define REALVIEW_CSR_BASE             0x10000000
+#define REALVIEW_CSR_SIZE             0x10000000
+
+#endif  /* __ASM_ARCH_PLATFORM_H */
diff --git a/include/asm-arm/arch-realview/scu.h b/arch/arm/mach-realview/include/mach/scu.h
index d55802d645af..d55802d645af 100644
--- a/include/asm-arm/arch-realview/scu.h
+++ b/arch/arm/mach-realview/include/mach/scu.h
diff --git a/include/asm-arm/arch-realview/smp.h b/arch/arm/mach-realview/include/mach/smp.h
index 515819efd046..515819efd046 100644
--- a/include/asm-arm/arch-realview/smp.h
+++ b/arch/arm/mach-realview/include/mach/smp.h
diff --git a/arch/arm/mach-realview/include/mach/system.h b/arch/arm/mach-realview/include/mach/system.h
new file mode 100644
index 000000000000..4d3c8f3f8053
--- /dev/null
+++ b/arch/arm/mach-realview/include/mach/system.h
@@ -0,0 +1,51 @@
+/*
+ *  arch/arm/mach-realview/include/mach/system.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <mach/hardware.h>
+#include <asm/io.h>
+#include <mach/platform.h>
+
+static inline void arch_idle(void)
+{
+        /*
+         * This should do all the clock switching
+         * and wait for interrupt tricks
+         */
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        void __iomem *hdr_ctrl = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_RESETCTL_OFFSET;
+        unsigned int val;
+
+        /*
+         * To reset, we hit the on-board reset register
+         * in the system FPGA
+         */
+        val = __raw_readl(hdr_ctrl);
+        val |= REALVIEW_SYS_CTRL_RESET_CONFIGCLR;
+        __raw_writel(val, hdr_ctrl);
+}
+
+#endif
diff --git a/arch/arm/mach-realview/include/mach/timex.h b/arch/arm/mach-realview/include/mach/timex.h
new file mode 100644
index 000000000000..4eeb069373c2
--- /dev/null
+++ b/arch/arm/mach-realview/include/mach/timex.h
@@ -0,0 +1,23 @@
+/*
+ *  arch/arm/mach-realview/include/mach/timex.h
+ *
+ *  RealView architecture timex specifications
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#define CLOCK_TICK_RATE         (50000000 / 16)
diff --git a/arch/arm/mach-realview/include/mach/uncompress.h b/arch/arm/mach-realview/include/mach/uncompress.h
new file mode 100644
index 000000000000..79f50f218e77
--- /dev/null
+++ b/arch/arm/mach-realview/include/mach/uncompress.h
@@ -0,0 +1,72 @@
+/*
+ *  arch/arm/mach-realview/include/mach/uncompress.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+
+#include <mach/board-eb.h>
+#include <mach/board-pb11mp.h>
+#include <mach/board-pb1176.h>
+
+#define AMBA_UART_DR(base)      (*(volatile unsigned char *)((base) + 0x00))
+#define AMBA_UART_LCRH(base)    (*(volatile unsigned char *)((base) + 0x2c))
+#define AMBA_UART_CR(base)      (*(volatile unsigned char *)((base) + 0x30))
+#define AMBA_UART_FR(base)      (*(volatile unsigned char *)((base) + 0x18))
+
+/*
+ * Return the UART base address
+ */
+static inline unsigned long get_uart_base(void)
+{
+        if (machine_is_realview_eb())
+                return REALVIEW_EB_UART0_BASE;
+        else if (machine_is_realview_pb11mp())
+                return REALVIEW_PB11MP_UART0_BASE;
+        else if (machine_is_realview_pb1176())
+                return REALVIEW_PB1176_UART0_BASE;
+        else
+                return 0;
+}
+
+/*
+ * This does not append a newline
+ */
+static inline void putc(int c)
+{
+        unsigned long base = get_uart_base();
+
+        while (AMBA_UART_FR(base) & (1 << 5))
+                barrier();
+
+        AMBA_UART_DR(base) = c;
+}
+
+static inline void flush(void)
+{
+        unsigned long base = get_uart_base();
+
+        while (AMBA_UART_FR(base) & (1 << 3))
+                barrier();
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-realview/include/mach/vmalloc.h b/arch/arm/mach-realview/include/mach/vmalloc.h
new file mode 100644
index 000000000000..48cbcc873db2
--- /dev/null
+++ b/arch/arm/mach-realview/include/mach/vmalloc.h
@@ -0,0 +1,21 @@
+/*
+ *  arch/arm/mach-realview/include/mach/vmalloc.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *  Copyright (C) 2000 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#define VMALLOC_END             (PAGE_OFFSET + 0x18000000)
diff --git a/arch/arm/mach-realview/localtimer.c b/arch/arm/mach-realview/localtimer.c
index 7631f3ea851b..82fa1f26e026 100644
--- a/arch/arm/mach-realview/localtimer.c
+++ b/arch/arm/mach-realview/localtimer.c
@@ -20,7 +20,7 @@
 
 #include <asm/hardware/arm_twd.h>
 #include <asm/hardware/gic.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index c1e579cbaa76..1907d22f4fed 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -15,13 +15,13 @@
 #include <linux/smp.h>
 
 #include <asm/cacheflush.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/board-eb.h>
-#include <asm/arch/board-pb11mp.h>
-#include <asm/arch/scu.h>
+#include <mach/board-eb.h>
+#include <mach/board-pb11mp.h>
+#include <mach/scu.h>
 
 extern void realview_secondary_startup(void);
 
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 66c1f3e47f69..19a9968fc5b9 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -24,7 +24,7 @@
 #include <linux/sysdev.h>
 #include <linux/amba/bus.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/leds.h>
@@ -38,8 +38,8 @@
 #include <asm/mach/mmc.h>
 #include <asm/mach/time.h>
 
-#include <asm/arch/board-eb.h>
-#include <asm/arch/irqs.h>
+#include <mach/board-eb.h>
+#include <mach/irqs.h>
 
 #include "core.h"
 #include "clock.h"
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index a00588a8d8f8..0986cbd15943 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -24,7 +24,7 @@
 #include <linux/sysdev.h>
 #include <linux/amba/bus.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/leds.h>
@@ -39,8 +39,8 @@
 #include <asm/mach/mmc.h>
 #include <asm/mach/time.h>
 
-#include <asm/arch/board-pb1176.h>
-#include <asm/arch/irqs.h>
+#include <mach/board-pb1176.h>
+#include <mach/irqs.h>
 
 #include "core.h"
 #include "clock.h"
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index 018898708b7a..f4e7135e3eb5 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -24,7 +24,7 @@
 #include <linux/sysdev.h>
 #include <linux/amba/bus.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/leds.h>
@@ -39,8 +39,8 @@
 #include <asm/mach/mmc.h>
 #include <asm/mach/time.h>
 
-#include <asm/arch/board-pb11mp.h>
-#include <asm/arch/irqs.h>
+#include <mach/board-pb11mp.h>
+#include <mach/irqs.h>
 
 #include "core.h"
 #include "clock.h"
diff --git a/arch/arm/mach-rpc/dma.c b/arch/arm/mach-rpc/dma.c
index fb1d42b53785..4b19fe484190 100644
--- a/arch/arm/mach-rpc/dma.c
+++ b/arch/arm/mach-rpc/dma.c
@@ -20,7 +20,7 @@
 #include <asm/fiq.h>
 #include <asm/io.h>
 #include <asm/irq.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/uaccess.h>
 
 #include <asm/mach/dma.h>
diff --git a/arch/arm/mach-rpc/include/mach/acornfb.h b/arch/arm/mach-rpc/include/mach/acornfb.h
new file mode 100644
index 000000000000..395d76288ffe
--- /dev/null
+++ b/arch/arm/mach-rpc/include/mach/acornfb.h
@@ -0,0 +1,140 @@
+/*
+ *  arch/arm/mach-rpc/include/mach/acornfb.h
+ *
+ *  Copyright (C) 1999 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  AcornFB architecture specific code
+ */
+
+#define acornfb_bandwidth(var) ((var)->pixclock * 8 / (var)->bits_per_pixel)
+
+static inline int
+acornfb_valid_pixrate(struct fb_var_screeninfo *var)
+{
+        u_long limit;
+
+        if (!var->pixclock)
+                return 0;
+
+        /*
+         * Limits below are taken from RISC OS bandwidthlimit file
+         */
+        if (current_par.using_vram) {
+                if (current_par.vram_half_sam == 2048)
+                        limit = 6578;
+                else
+                        limit = 13157;
+        } else {
+                limit = 26315;
+        }
+
+        return acornfb_bandwidth(var) >= limit;
+}
+
+/*
+ * Try to find the best PLL parameters for the pixel clock.
+ * This algorithm seems to give best predictable results,
+ * and produces the same values as detailed in the VIDC20
+ * data sheet.
+ */
+static inline u_int
+acornfb_vidc20_find_pll(u_int pixclk)
+{
+        u_int r, best_r = 2, best_v = 2;
+        int best_d = 0x7fffffff;
+
+        for (r = 2; r <= 32; r++) {
+                u_int rr, v, p;
+                int d;
+
+                rr = 41667 * r;
+
+                v = (rr + pixclk / 2) / pixclk;
+
+                if (v > 32 || v < 2)
+                        continue;
+
+                p = (rr + v / 2) / v;
+
+                d = pixclk - p;
+
+                if (d < 0)
+                        d = -d;
+
+                if (d < best_d) {
+                        best_d = d;
+                        best_v = v - 1;
+                        best_r = r - 1;
+                }
+
+                if (d == 0)
+                        break;
+        }
+
+        return best_v << 8 | best_r;
+}
+
+static inline void
+acornfb_vidc20_find_rates(struct vidc_timing *vidc,
+                          struct fb_var_screeninfo *var)
+{
+        u_int div;
+
+        /* Select pixel-clock divisor to keep PLL in range */
+        div = var->pixclock / 9090; /*9921*/
+
+        /* Limit divisor */
+        if (div == 0)
+                div = 1;
+        if (div > 8)
+                div = 8;
+
+        /* Encode divisor to VIDC20 setting */
+        switch (div) {
+        case 1: vidc->control |= VIDC20_CTRL_PIX_CK;  break;
+        case 2: vidc->control |= VIDC20_CTRL_PIX_CK2; break;
+        case 3: vidc->control |= VIDC20_CTRL_PIX_CK3; break;
+        case 4: vidc->control |= VIDC20_CTRL_PIX_CK4; break;
+        case 5: vidc->control |= VIDC20_CTRL_PIX_CK5; break;
+        case 6: vidc->control |= VIDC20_CTRL_PIX_CK6; break;
+        case 7: vidc->control |= VIDC20_CTRL_PIX_CK7; break;
+        case 8: vidc->control |= VIDC20_CTRL_PIX_CK8; break;
+        }
+
+        /*
+         * With VRAM, the FIFO can be set to the highest possible setting
+         * because there are no latency considerations for other memory
+         * accesses. However, in 64 bit bus mode the FIFO preload value
+         * must not be set to VIDC20_CTRL_FIFO_28 because this will let
+         * the FIFO overflow. See VIDC20 manual page 33 (6.0 Setting the
+         * FIFO preload value).
+         */
+        if (current_par.using_vram) {
+                if (current_par.vram_half_sam == 2048)
+                        vidc->control |= VIDC20_CTRL_FIFO_24;
+                else
+                        vidc->control |= VIDC20_CTRL_FIFO_28;
+        } else {
+                unsigned long bandwidth = acornfb_bandwidth(var);
+
+                /* Encode bandwidth as VIDC20 setting */
+                if (bandwidth > 33334)          /* < 30.0MB/s */
+                        vidc->control |= VIDC20_CTRL_FIFO_16;
+                else if (bandwidth > 26666)     /* < 37.5MB/s */
+                        vidc->control |= VIDC20_CTRL_FIFO_20;
+                else if (bandwidth > 22222)     /* < 45.0MB/s */
+                        vidc->control |= VIDC20_CTRL_FIFO_24;
+                else                            /* > 45.0MB/s */
+                        vidc->control |= VIDC20_CTRL_FIFO_28;
+        }
+
+        /* Find the PLL values */
+        vidc->pll_ctl = acornfb_vidc20_find_pll(var->pixclock / div);
+}
+
+#define acornfb_default_control()       (VIDC20_CTRL_PIX_VCLK)
+#define acornfb_default_econtrol()      (VIDC20_ECTL_DAC | VIDC20_ECTL_REG(3))
diff --git a/arch/arm/mach-rpc/include/mach/debug-macro.S b/arch/arm/mach-rpc/include/mach/debug-macro.S
new file mode 100644
index 000000000000..b2a939ffdcde
--- /dev/null
+++ b/arch/arm/mach-rpc/include/mach/debug-macro.S
@@ -0,0 +1,25 @@
+/* arch/arm/mach-rpc/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx, #0x03000000
+                movne   \rx, #0xe0000000
+                orr     \rx, \rx, #0x00010000
+                orr     \rx, \rx, #0x00000fe0
+                .endm
+
+#define UART_SHIFT      2
+#define FLOW_CONTROL
+#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-rpc/include/mach/dma.h b/arch/arm/mach-rpc/include/mach/dma.h
new file mode 100644
index 000000000000..360b56f8f29f
--- /dev/null
+++ b/arch/arm/mach-rpc/include/mach/dma.h
@@ -0,0 +1,33 @@
+/*
+ *  arch/arm/mach-rpc/include/mach/dma.h
+ *
+ *  Copyright (C) 1997 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+/*
+ * This is the maximum DMA address that can be DMAd to.
+ * There should not be more than (0xd0000000 - 0xc0000000)
+ * bytes of RAM.
+ */
+#define MAX_DMA_ADDRESS         0xd0000000
+#define MAX_DMA_CHANNELS        8
+
+#define DMA_0                   0
+#define DMA_1                   1
+#define DMA_2                   2
+#define DMA_3                   3
+#define DMA_S0                  4
+#define DMA_S1                  5
+#define DMA_VIRTUAL_FLOPPY      6
+#define DMA_VIRTUAL_SOUND       7
+
+#define DMA_FLOPPY              DMA_VIRTUAL_FLOPPY
+
+#endif /* _ASM_ARCH_DMA_H */
+
diff --git a/arch/arm/mach-rpc/include/mach/entry-macro.S b/arch/arm/mach-rpc/include/mach/entry-macro.S
new file mode 100644
index 000000000000..4e7e54144093
--- /dev/null
+++ b/arch/arm/mach-rpc/include/mach/entry-macro.S
@@ -0,0 +1,16 @@
+#include <mach/hardware.h>
+#include <asm/hardware/entry-macro-iomd.S>
+
+        .equ    ioc_base_high, IOC_BASE & 0xff000000
+        .equ    ioc_base_low, IOC_BASE & 0x00ff0000
+
+        .macro  get_irqnr_preamble, base, tmp
+        mov     \base, #ioc_base_high           @ point at IOC
+        .if     ioc_base_low
+        orr     \base, \base, #ioc_base_low
+        .endif
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
diff --git a/arch/arm/mach-rpc/include/mach/hardware.h b/arch/arm/mach-rpc/include/mach/hardware.h
new file mode 100644
index 000000000000..dde6b3c0e299
--- /dev/null
+++ b/arch/arm/mach-rpc/include/mach/hardware.h
@@ -0,0 +1,83 @@
+/*
+ *  arch/arm/mach-rpc/include/mach/hardware.h
+ *
+ *  Copyright (C) 1996-1999 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  This file contains the hardware definitions of the RiscPC series machines.
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <mach/memory.h>
+
+#ifndef __ASSEMBLY__
+#define IOMEM(x) ((void __iomem *)(unsigned long)(x))
+#else
+#define IOMEM(x) x
+#endif /* __ASSEMBLY__ */
+
+/*
+ * What hardware must be present
+ */
+#define HAS_IOMD
+#define HAS_VIDC20
+
+/* Hardware addresses of major areas.
+ *  *_START is the physical address
+ *  *_SIZE  is the size of the region
+ *  *_BASE  is the virtual address
+ */
+#define RAM_SIZE                0x10000000
+#define RAM_START               0x10000000
+
+#define EASI_SIZE               0x08000000      /* EASI I/O */
+#define EASI_START              0x08000000
+#define EASI_BASE               0xe5000000
+
+#define IO_START                0x03000000      /* I/O */
+#define IO_SIZE                 0x01000000
+#define IO_BASE                 IOMEM(0xe0000000)
+
+#define SCREEN_START            0x02000000      /* VRAM */
+#define SCREEN_END              0xdfc00000
+#define SCREEN_BASE             0xdf800000
+
+#define UNCACHEABLE_ADDR        0xdf010000
+
+/*
+ * IO Addresses
+ */
+#define VIDC_BASE               IOMEM(0xe0400000)
+#define EXPMASK_BASE            0xe0360000
+#define IOMD_BASE               IOMEM(0xe0200000)
+#define IOC_BASE                IOMEM(0xe0200000)
+#define PCIO_BASE               IOMEM(0xe0010000)
+#define FLOPPYDMA_BASE          IOMEM(0xe002a000)
+
+#define vidc_writel(val)        __raw_writel(val, VIDC_BASE)
+
+#define IO_EC_EASI_BASE         0x81400000
+#define IO_EC_IOC4_BASE         0x8009c000
+#define IO_EC_IOC_BASE          0x80090000
+#define IO_EC_MEMC8_BASE        0x8000ac00
+#define IO_EC_MEMC_BASE         0x80000000
+
+#define NETSLOT_BASE            0x0302b000
+#define NETSLOT_SIZE            0x00001000
+
+#define PODSLOT_IOC0_BASE       0x03240000
+#define PODSLOT_IOC4_BASE       0x03270000
+#define PODSLOT_IOC_SIZE        (1 << 14)
+#define PODSLOT_MEMC_BASE       0x03000000
+#define PODSLOT_MEMC_SIZE       (1 << 14)
+#define PODSLOT_EASI_BASE       0x08000000
+#define PODSLOT_EASI_SIZE       (1 << 24)
+
+#define EXPMASK_STATUS          (EXPMASK_BASE + 0x00)
+#define EXPMASK_ENABLE          (EXPMASK_BASE + 0x04)
+
+#endif
diff --git a/arch/arm/mach-rpc/include/mach/io.h b/arch/arm/mach-rpc/include/mach/io.h
new file mode 100644
index 000000000000..9f0553b7ec28
--- /dev/null
+++ b/arch/arm/mach-rpc/include/mach/io.h
@@ -0,0 +1,258 @@
+/*
+ *  arch/arm/mach-rpc/include/mach/io.h
+ *
+ *  Copyright (C) 1997 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ *  06-Dec-1997 RMK     Created.
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#include <mach/hardware.h>
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * GCC is totally crap at loading/storing data.  We try to persuade it
+ * to do the right thing by using these whereever possible instead of
+ * the above.
+ */
+#define __arch_base_getb(b,o)                   \
+ ({                                             \
+        unsigned int __v, __r = (b);            \
+        __asm__ __volatile__(                   \
+                "ldrb   %0, [%1, %2]"           \
+                : "=r" (__v)                    \
+                : "r" (__r), "Ir" (o));         \
+        __v;                                    \
+ })
+
+#define __arch_base_getl(b,o)                   \
+ ({                                             \
+        unsigned int __v, __r = (b);            \
+        __asm__ __volatile__(                   \
+                "ldr    %0, [%1, %2]"           \
+                : "=r" (__v)                    \
+                : "r" (__r), "Ir" (o));         \
+        __v;                                    \
+ })
+
+#define __arch_base_putb(v,b,o)                 \
+ ({                                             \
+        unsigned int __r = (b);                 \
+        __asm__ __volatile__(                   \
+                "strb   %0, [%1, %2]"           \
+                :                               \
+                : "r" (v), "r" (__r), "Ir" (o));\
+ })
+
+#define __arch_base_putl(v,b,o)                 \
+ ({                                             \
+        unsigned int __r = (b);                 \
+        __asm__ __volatile__(                   \
+                "str    %0, [%1, %2]"           \
+                :                               \
+                : "r" (v), "r" (__r), "Ir" (o));\
+ })
+
+/*
+ * We use two different types of addressing - PC style addresses, and ARM
+ * addresses.  PC style accesses the PC hardware with the normal PC IO
+ * addresses, eg 0x3f8 for serial#1.  ARM addresses are 0x80000000+
+ * and are translated to the start of IO.  Note that all addresses are
+ * shifted left!
+ */
+#define __PORT_PCIO(x)  (!((x) & 0x80000000))
+
+/*
+ * Dynamic IO functions.
+ */
+static inline void __outb (unsigned int value, unsigned int port)
+{
+        unsigned long temp;
+        __asm__ __volatile__(
+        "tst    %2, #0x80000000\n\t"
+        "mov    %0, %4\n\t"
+        "addeq  %0, %0, %3\n\t"
+        "strb   %1, [%0, %2, lsl #2]    @ outb"
+        : "=&r" (temp)
+        : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
+        : "cc");
+}
+
+static inline void __outw (unsigned int value, unsigned int port)
+{
+        unsigned long temp;
+        __asm__ __volatile__(
+        "tst    %2, #0x80000000\n\t"
+        "mov    %0, %4\n\t"
+        "addeq  %0, %0, %3\n\t"
+        "str    %1, [%0, %2, lsl #2]    @ outw"
+        : "=&r" (temp)
+        : "r" (value|value<<16), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
+        : "cc");
+}
+
+static inline void __outl (unsigned int value, unsigned int port)
+{
+        unsigned long temp;
+        __asm__ __volatile__(
+        "tst    %2, #0x80000000\n\t"
+        "mov    %0, %4\n\t"
+        "addeq  %0, %0, %3\n\t"
+        "str    %1, [%0, %2, lsl #2]    @ outl"
+        : "=&r" (temp)
+        : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
+        : "cc");
+}
+
+#define DECLARE_DYN_IN(sz,fnsuffix,instr)                                       \
+static inline unsigned sz __in##fnsuffix (unsigned int port)            \
+{                                                                               \
+        unsigned long temp, value;                                              \
+        __asm__ __volatile__(                                                   \
+        "tst    %2, #0x80000000\n\t"                                            \
+        "mov    %0, %4\n\t"                                                     \
+        "addeq  %0, %0, %3\n\t"                                                 \
+        "ldr" instr "   %1, [%0, %2, lsl #2]    @ in" #fnsuffix                 \
+        : "=&r" (temp), "=r" (value)                                            \
+        : "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)                \
+        : "cc");                                                                \
+        return (unsigned sz)value;                                              \
+}
+
+static inline void __iomem *__deprecated __ioaddr(unsigned int port)
+{
+        void __iomem *ret;
+        if (__PORT_PCIO(port))
+                ret = PCIO_BASE;
+        else
+                ret = IO_BASE;
+        return ret + (port << 2);
+}
+
+#define DECLARE_IO(sz,fnsuffix,instr)   \
+        DECLARE_DYN_IN(sz,fnsuffix,instr)
+
+DECLARE_IO(char,b,"b")
+DECLARE_IO(short,w,"")
+DECLARE_IO(int,l,"")
+
+#undef DECLARE_IO
+#undef DECLARE_DYN_IN
+
+/*
+ * Constant address IO functions
+ *
+ * These have to be macros for the 'J' constraint to work -
+ * +/-4096 immediate operand.
+ */
+#define __outbc(value,port)                                                     \
+({                                                                              \
+        if (__PORT_PCIO((port)))                                                \
+                __asm__ __volatile__(                                           \
+                "strb   %0, [%1, %2]    @ outbc"                                \
+                : : "r" (value), "r" (PCIO_BASE), "Jr" ((port) << 2));          \
+        else                                                                    \
+                __asm__ __volatile__(                                           \
+                "strb   %0, [%1, %2]    @ outbc"                                \
+                : : "r" (value), "r" (IO_BASE), "r" ((port) << 2));             \
+})
+
+#define __inbc(port)                                                            \
+({                                                                              \
+        unsigned char result;                                                   \
+        if (__PORT_PCIO((port)))                                                \
+                __asm__ __volatile__(                                           \
+                "ldrb   %0, [%1, %2]    @ inbc"                                 \
+                : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2));         \
+        else                                                                    \
+                __asm__ __volatile__(                                           \
+                "ldrb   %0, [%1, %2]    @ inbc"                                 \
+                : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2));            \
+        result;                                                                 \
+})
+
+#define __outwc(value,port)                                                     \
+({                                                                              \
+        unsigned long __v = value;                                              \
+        if (__PORT_PCIO((port)))                                                \
+                __asm__ __volatile__(                                           \
+                "str    %0, [%1, %2]    @ outwc"                                \
+                : : "r" (__v|__v<<16), "r" (PCIO_BASE), "Jr" ((port) << 2));    \
+        else                                                                    \
+                __asm__ __volatile__(                                           \
+                "str    %0, [%1, %2]    @ outwc"                                \
+                : : "r" (__v|__v<<16), "r" (IO_BASE), "r" ((port) << 2));               \
+})
+
+#define __inwc(port)                                                            \
+({                                                                              \
+        unsigned short result;                                                  \
+        if (__PORT_PCIO((port)))                                                \
+                __asm__ __volatile__(                                           \
+                "ldr    %0, [%1, %2]    @ inwc"                                 \
+                : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2));         \
+        else                                                                    \
+                __asm__ __volatile__(                                           \
+                "ldr    %0, [%1, %2]    @ inwc"                                 \
+                : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2));            \
+        result & 0xffff;                                                        \
+})
+
+#define __outlc(value,port)                                                     \
+({                                                                              \
+        unsigned long __v = value;                                              \
+        if (__PORT_PCIO((port)))                                                \
+                __asm__ __volatile__(                                           \
+                "str    %0, [%1, %2]    @ outlc"                                \
+                : : "r" (__v), "r" (PCIO_BASE), "Jr" ((port) << 2));            \
+        else                                                                    \
+                __asm__ __volatile__(                                           \
+                "str    %0, [%1, %2]    @ outlc"                                \
+                : : "r" (__v), "r" (IO_BASE), "r" ((port) << 2));               \
+})
+
+#define __inlc(port)                                                            \
+({                                                                              \
+        unsigned long result;                                                   \
+        if (__PORT_PCIO((port)))                                                \
+                __asm__ __volatile__(                                           \
+                "ldr    %0, [%1, %2]    @ inlc"                                 \
+                : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2));         \
+        else                                                                    \
+                __asm__ __volatile__(                                           \
+                "ldr    %0, [%1, %2]    @ inlc"                                 \
+                : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2));            \
+        result;                                                                 \
+})
+
+#define __ioaddrc(port)         __ioaddr(port)
+
+#define inb(p)          (__builtin_constant_p((p)) ? __inbc(p)    : __inb(p))
+#define inw(p)          (__builtin_constant_p((p)) ? __inwc(p)    : __inw(p))
+#define inl(p)          (__builtin_constant_p((p)) ? __inlc(p)    : __inl(p))
+#define outb(v,p)       (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p))
+#define outw(v,p)       (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p))
+#define outl(v,p)       (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p))
+#define __ioaddr(p)     (__builtin_constant_p((p)) ? __ioaddr(p)  : __ioaddrc(p))
+/* the following macro is deprecated */
+#define ioaddr(port)    ((unsigned long)__ioaddr((port)))
+
+#define insb(p,d,l)     __raw_readsb(__ioaddr(p),d,l)
+#define insw(p,d,l)     __raw_readsw(__ioaddr(p),d,l)
+
+#define outsb(p,d,l)    __raw_writesb(__ioaddr(p),d,l)
+#define outsw(p,d,l)    __raw_writesw(__ioaddr(p),d,l)
+
+/*
+ * 1:1 mapping for ioremapped regions.
+ */
+#define __mem_pci(x)    (x)
+
+#endif
diff --git a/arch/arm/mach-rpc/include/mach/irqs.h b/arch/arm/mach-rpc/include/mach/irqs.h
new file mode 100644
index 000000000000..4ce6ca97f669
--- /dev/null
+++ b/arch/arm/mach-rpc/include/mach/irqs.h
@@ -0,0 +1,46 @@
+/*
+ *  arch/arm/mach-rpc/include/mach/irqs.h
+ *
+ *  Copyright (C) 1996 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define IRQ_PRINTER             0
+#define IRQ_BATLOW              1
+#define IRQ_FLOPPYINDEX         2
+#define IRQ_VSYNCPULSE          3
+#define IRQ_POWERON             4
+#define IRQ_TIMER0              5
+#define IRQ_TIMER1              6
+#define IRQ_IMMEDIATE           7
+#define IRQ_EXPCARDFIQ          8
+#define IRQ_HARDDISK            9
+#define IRQ_SERIALPORT          10
+#define IRQ_FLOPPYDISK          12
+#define IRQ_EXPANSIONCARD       13
+#define IRQ_KEYBOARDTX          14
+#define IRQ_KEYBOARDRX          15
+
+#define IRQ_DMA0                16
+#define IRQ_DMA1                17
+#define IRQ_DMA2                18
+#define IRQ_DMA3                19
+#define IRQ_DMAS0               20
+#define IRQ_DMAS1               21
+
+#define FIQ_FLOPPYDATA          0
+#define FIQ_ECONET              2
+#define FIQ_SERIALPORT          4
+#define FIQ_EXPANSIONCARD       6
+#define FIQ_FORCE               7
+
+/*
+ * This is the offset of the FIQ "IRQ" numbers
+ */
+#define FIQ_START               64
+
+#define IRQ_TIMER               IRQ_TIMER0
+
diff --git a/arch/arm/mach-rpc/include/mach/memory.h b/arch/arm/mach-rpc/include/mach/memory.h
new file mode 100644
index 000000000000..05425d558ee7
--- /dev/null
+++ b/arch/arm/mach-rpc/include/mach/memory.h
@@ -0,0 +1,39 @@
+/*
+ *  arch/arm/mach-rpc/include/mach/memory.h
+ *
+ *  Copyright (C) 1996,1997,1998 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   20-Oct-1996 RMK    Created
+ *   31-Dec-1997 RMK    Fixed definitions to reduce warnings
+ *   11-Jan-1998 RMK    Uninlined to reduce hits on cache
+ *   08-Feb-1998 RMK    Added __virt_to_bus and __bus_to_virt
+ *   21-Mar-1999 RMK    Renamed to memory.h
+ *               RMK    Added TASK_SIZE and PAGE_OFFSET
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     UL(0x10000000)
+
+/*
+ * These are exactly the same on the RiscPC as the
+ * physical memory view.
+ */
+#define __virt_to_bus(x) __virt_to_phys(x)
+#define __bus_to_virt(x) __phys_to_virt(x)
+
+/*
+ * Cache flushing area - ROM
+ */
+#define FLUSH_BASE_PHYS         0x00000000
+#define FLUSH_BASE              0xdf000000
+
+#endif
diff --git a/arch/arm/mach-rpc/include/mach/system.h b/arch/arm/mach-rpc/include/mach/system.h
new file mode 100644
index 000000000000..54d6e3f2d319
--- /dev/null
+++ b/arch/arm/mach-rpc/include/mach/system.h
@@ -0,0 +1,27 @@
+/*
+ *  arch/arm/mach-rpc/include/mach/system.h
+ *
+ *  Copyright (C) 1996-1999 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <mach/hardware.h>
+#include <asm/hardware/iomd.h>
+#include <asm/io.h>
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        iomd_writeb(0, IOMD_ROMCR0);
+
+        /*
+         * Jump into the ROM
+         */
+        cpu_reset(0);
+}
diff --git a/arch/arm/mach-rpc/include/mach/timex.h b/arch/arm/mach-rpc/include/mach/timex.h
new file mode 100644
index 000000000000..dd75e7387bbe
--- /dev/null
+++ b/arch/arm/mach-rpc/include/mach/timex.h
@@ -0,0 +1,17 @@
+/*
+ *  arch/arm/mach-rpc/include/mach/timex.h
+ *
+ *  Copyright (C) 1997, 1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  RiscPC architecture timex specifications
+ */
+
+/*
+ * On the RiscPC, the clock ticks at 2MHz.
+ */
+#define CLOCK_TICK_RATE         2000000
+
diff --git a/arch/arm/mach-rpc/include/mach/uncompress.h b/arch/arm/mach-rpc/include/mach/uncompress.h
new file mode 100644
index 000000000000..baa9c866d7bf
--- /dev/null
+++ b/arch/arm/mach-rpc/include/mach/uncompress.h
@@ -0,0 +1,198 @@
+/*
+ *  arch/arm/mach-rpc/include/mach/uncompress.h
+ *
+ *  Copyright (C) 1996 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#define VIDMEM ((char *)SCREEN_START)
+ 
+#include <mach/hardware.h>
+#include <asm/io.h>
+#include <asm/setup.h>
+#include <asm/page.h>
+
+int video_size_row;
+unsigned char bytes_per_char_h;
+extern unsigned long con_charconvtable[256];
+
+struct param_struct {
+        unsigned long page_size;
+        unsigned long nr_pages;
+        unsigned long ramdisk_size;
+        unsigned long mountrootrdonly;
+        unsigned long rootdev;
+        unsigned long video_num_cols;
+        unsigned long video_num_rows;
+        unsigned long video_x;
+        unsigned long video_y;
+        unsigned long memc_control_reg;
+        unsigned char sounddefault;
+        unsigned char adfsdrives;
+        unsigned char bytes_per_char_h;
+        unsigned char bytes_per_char_v;
+        unsigned long unused[256/4-11];
+};
+
+static const unsigned long palette_4[16] = {
+        0x00000000,
+        0x000000cc,
+        0x0000cc00,             /* Green   */
+        0x0000cccc,             /* Yellow  */
+        0x00cc0000,             /* Blue    */
+        0x00cc00cc,             /* Magenta */
+        0x00cccc00,             /* Cyan    */
+        0x00cccccc,             /* White   */
+        0x00000000,
+        0x000000ff,
+        0x0000ff00,
+        0x0000ffff,
+        0x00ff0000,
+        0x00ff00ff,
+        0x00ffff00,
+        0x00ffffff
+};
+
+#define palette_setpixel(p)     *(unsigned long *)(IO_START+0x00400000) = 0x10000000|((p) & 255)
+#define palette_write(v)        *(unsigned long *)(IO_START+0x00400000) = 0x00000000|((v) & 0x00ffffff)
+
+/*
+ * params_phys is a linker defined symbol - see
+ * arch/arm/boot/compressed/Makefile
+ */
+extern __attribute__((pure)) struct param_struct *params(void);
+#define params (params())
+
+#ifndef STANDALONE_DEBUG 
+static unsigned long video_num_cols;
+static unsigned long video_num_rows;
+static unsigned long video_x;
+static unsigned long video_y;
+static unsigned char bytes_per_char_v;
+static int white;
+
+/*
+ * This does not append a newline
+ */
+static void putc(int c)
+{
+        extern void ll_write_char(char *, char c, char white);
+        int x,y;
+        char *ptr;
+
+        x = video_x;
+        y = video_y;
+
+        if (c == '\n') {
+                if (++y >= video_num_rows)
+                        y--;
+        } else if (c == '\r') {
+                x = 0;
+        } else {
+                ptr = VIDMEM + ((y*video_num_cols*bytes_per_char_v+x)*bytes_per_char_h);
+                ll_write_char(ptr, c, white);
+                if (++x >= video_num_cols) {
+                        x = 0;
+                        if ( ++y >= video_num_rows ) {
+                                y--;
+                        }
+                }
+        }
+
+        video_x = x;
+        video_y = y;
+}
+
+static inline void flush(void)
+{
+}
+
+static void error(char *x);
+
+/*
+ * Setup for decompression
+ */
+static void arch_decomp_setup(void)
+{
+        int i;
+        struct tag *t = (struct tag *)params;
+        unsigned int nr_pages = 0, page_size = PAGE_SIZE;
+
+        if (t->hdr.tag == ATAG_CORE)
+        {
+                for (; t->hdr.size; t = tag_next(t))
+                {
+                        if (t->hdr.tag == ATAG_VIDEOTEXT)
+                        {
+                                video_num_rows = t->u.videotext.video_lines;
+                                video_num_cols = t->u.videotext.video_cols;
+                                bytes_per_char_h = t->u.videotext.video_points;
+                                bytes_per_char_v = t->u.videotext.video_points;
+                                video_x = t->u.videotext.x;
+                                video_y = t->u.videotext.y;
+                        }
+
+                        if (t->hdr.tag == ATAG_MEM)
+                        {
+                                page_size = PAGE_SIZE;
+                                nr_pages += (t->u.mem.size / PAGE_SIZE);
+                        }
+                }
+        }
+        else
+        {
+                nr_pages = params->nr_pages;
+                page_size = params->page_size;
+                video_num_rows = params->video_num_rows;
+                video_num_cols = params->video_num_cols;
+                video_x = params->video_x;
+                video_y = params->video_y;
+                bytes_per_char_h = params->bytes_per_char_h;
+                bytes_per_char_v = params->bytes_per_char_v;
+        }
+
+        video_size_row = video_num_cols * bytes_per_char_h;
+        
+        if (bytes_per_char_h == 4)
+                for (i = 0; i < 256; i++)
+                        con_charconvtable[i] =
+                                (i & 128 ? 1 << 0  : 0) |
+                                (i & 64  ? 1 << 4  : 0) |
+                                (i & 32  ? 1 << 8  : 0) |
+                                (i & 16  ? 1 << 12 : 0) |
+                                (i & 8   ? 1 << 16 : 0) |
+                                (i & 4   ? 1 << 20 : 0) |
+                                (i & 2   ? 1 << 24 : 0) |
+                                (i & 1   ? 1 << 28 : 0);
+        else
+                for (i = 0; i < 16; i++)
+                        con_charconvtable[i] =
+                                (i & 8   ? 1 << 0  : 0) |
+                                (i & 4   ? 1 << 8  : 0) |
+                                (i & 2   ? 1 << 16 : 0) |
+                                (i & 1   ? 1 << 24 : 0);
+
+
+        palette_setpixel(0);
+        if (bytes_per_char_h == 1) {
+                palette_write (0);
+                palette_write (0x00ffffff);
+                for (i = 2; i < 256; i++)
+                        palette_write (0);
+                white = 1;
+        } else {
+                for (i = 0; i < 256; i++)
+                        palette_write (i < 16 ? palette_4[i] : 0);
+                white = 7;
+        }
+
+        if (nr_pages * page_size < 4096*1024) error("<4M of mem\n");
+}
+#endif
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-rpc/include/mach/vmalloc.h b/arch/arm/mach-rpc/include/mach/vmalloc.h
new file mode 100644
index 000000000000..9a96fd69e705
--- /dev/null
+++ b/arch/arm/mach-rpc/include/mach/vmalloc.h
@@ -0,0 +1,10 @@
+/*
+ *  arch/arm/mach-rpc/include/mach/vmalloc.h
+ *
+ *  Copyright (C) 1997 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#define VMALLOC_END       (PAGE_OFFSET + 0x1c000000)
diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c
index 54a6c756584c..ce8470fea887 100644
--- a/arch/arm/mach-rpc/riscpc.c
+++ b/arch/arm/mach-rpc/riscpc.c
@@ -22,7 +22,7 @@
 #include <asm/elf.h>
 #include <asm/io.h>
 #include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/page.h>
 #include <asm/domain.h>
 #include <asm/setup.h>
diff --git a/arch/arm/mach-s3c2400/gpio.c b/arch/arm/mach-s3c2400/gpio.c
index 140fd2548b46..148d0ddef3e8 100644
--- a/arch/arm/mach-s3c2400/gpio.c
+++ b/arch/arm/mach-s3c2400/gpio.c
@@ -25,11 +25,11 @@
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/io.h>
 
-#include <asm/arch/regs-gpio.h>
+#include <mach/regs-gpio.h>
 
 int s3c2400_gpio_getirq(unsigned int pin)
 {
diff --git a/arch/arm/mach-s3c2400/include/mach/map.h b/arch/arm/mach-s3c2400/include/mach/map.h
new file mode 100644
index 000000000000..1535540edc82
--- /dev/null
+++ b/arch/arm/mach-s3c2400/include/mach/map.h
@@ -0,0 +1,66 @@
+/* arch/arm/mach-s3c2400/include/mach/map.h
+ *
+ * Copyright 2003,2007  Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Copyright 2003, Lucas Correia Villa Real
+ *
+ * S3C2400 - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C2400_PA_MEMCTRL      (0x14000000)
+#define S3C2400_PA_USBHOST      (0x14200000)
+#define S3C2400_PA_IRQ          (0x14400000)
+#define S3C2400_PA_DMA          (0x14600000)
+#define S3C2400_PA_CLKPWR       (0x14800000)
+#define S3C2400_PA_LCD          (0x14A00000)
+#define S3C2400_PA_UART         (0x15000000)
+#define S3C2400_PA_TIMER        (0x15100000)
+#define S3C2400_PA_USBDEV       (0x15200140)
+#define S3C2400_PA_WATCHDOG     (0x15300000)
+#define S3C2400_PA_IIC          (0x15400000)
+#define S3C2400_PA_IIS          (0x15508000)
+#define S3C2400_PA_GPIO         (0x15600000)
+#define S3C2400_PA_RTC          (0x15700040)
+#define S3C2400_PA_ADC          (0x15800000)
+#define S3C2400_PA_SPI          (0x15900000)
+
+#define S3C2400_PA_MMC          (0x15A00000)
+#define S3C2400_SZ_MMC          SZ_1M
+
+/* physical addresses of all the chip-select areas */
+
+#define S3C2400_CS0     (0x00000000)
+#define S3C2400_CS1     (0x02000000)
+#define S3C2400_CS2     (0x04000000)
+#define S3C2400_CS3     (0x06000000)
+#define S3C2400_CS4     (0x08000000)
+#define S3C2400_CS5     (0x0A000000)
+#define S3C2400_CS6     (0x0C000000)
+#define S3C2400_CS7     (0x0E000000)
+
+#define S3C2400_SDRAM_PA    (S3C2400_CS6)
+
+/* Use a single interface for common resources between S3C24XX cpus */
+
+#define S3C24XX_PA_IRQ          S3C2400_PA_IRQ
+#define S3C24XX_PA_MEMCTRL      S3C2400_PA_MEMCTRL
+#define S3C24XX_PA_USBHOST      S3C2400_PA_USBHOST
+#define S3C24XX_PA_DMA          S3C2400_PA_DMA
+#define S3C24XX_PA_CLKPWR       S3C2400_PA_CLKPWR
+#define S3C24XX_PA_LCD          S3C2400_PA_LCD
+#define S3C24XX_PA_UART         S3C2400_PA_UART
+#define S3C24XX_PA_TIMER        S3C2400_PA_TIMER
+#define S3C24XX_PA_USBDEV       S3C2400_PA_USBDEV
+#define S3C24XX_PA_WATCHDOG     S3C2400_PA_WATCHDOG
+#define S3C24XX_PA_IIC          S3C2400_PA_IIC
+#define S3C24XX_PA_IIS          S3C2400_PA_IIS
+#define S3C24XX_PA_GPIO         S3C2400_PA_GPIO
+#define S3C24XX_PA_RTC          S3C2400_PA_RTC
+#define S3C24XX_PA_ADC          S3C2400_PA_ADC
+#define S3C24XX_PA_SPI          S3C2400_PA_SPI
diff --git a/arch/arm/mach-s3c2400/include/mach/memory.h b/arch/arm/mach-s3c2400/include/mach/memory.h
new file mode 100644
index 000000000000..8f4878e4f591
--- /dev/null
+++ b/arch/arm/mach-s3c2400/include/mach/memory.h
@@ -0,0 +1,23 @@
+/* arch/arm/mach-s3c2400/include/mach/memory.h
+ *  from arch/arm/mach-rpc/include/mach/memory.h
+ *
+ *  Copyright 2007 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ *  Copyright (C) 1996,1997,1998 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#define PHYS_OFFSET     UL(0x0C000000)
+
+#define __virt_to_bus(x) __virt_to_phys(x)
+#define __bus_to_virt(x) __phys_to_virt(x)
+
+#endif
diff --git a/arch/arm/mach-s3c2410/bast-ide.c b/arch/arm/mach-s3c2410/bast-ide.c
index df95fe37cdc8..298ececfa366 100644
--- a/arch/arm/mach-s3c2410/bast-ide.c
+++ b/arch/arm/mach-s3c2410/bast-ide.c
@@ -24,9 +24,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/map.h>
-#include <asm/arch/bast-map.h>
-#include <asm/arch/bast-irq.h>
+#include <mach/map.h>
+#include <mach/bast-map.h>
+#include <mach/bast-irq.h>
 
 /* IDE ports */
 
diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c
index 4e58bc0e30e3..c66021b5fa4d 100644
--- a/arch/arm/mach-s3c2410/bast-irq.c
+++ b/arch/arm/mach-s3c2410/bast-irq.c
@@ -28,15 +28,15 @@
 
 #include <asm/mach-types.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/io.h>
 
 #include <asm/mach/irq.h>
 
-#include <asm/arch/regs-irq.h>
-#include <asm/arch/bast-map.h>
-#include <asm/arch/bast-irq.h>
+#include <mach/regs-irq.h>
+#include <mach/bast-map.h>
+#include <mach/bast-irq.h>
 
 #include <asm/plat-s3c24xx/irq.h>
 
diff --git a/arch/arm/mach-s3c2410/clock.c b/arch/arm/mach-s3c2410/clock.c
index 4e6239726aae..1322851d1acb 100644
--- a/arch/arm/mach-s3c2410/clock.c
+++ b/arch/arm/mach-s3c2410/clock.c
@@ -34,12 +34,12 @@
 
 #include <asm/mach/map.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 
 #include <asm/plat-s3c/regs-serial.h>
-#include <asm/arch/regs-clock.h>
-#include <asm/arch/regs-gpio.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-gpio.h>
 
 #include <asm/plat-s3c24xx/s3c2410.h>
 #include <asm/plat-s3c24xx/clock.h>
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c
index 8f12e855ef5f..8730797749e3 100644
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c2410/dma.c
@@ -18,17 +18,17 @@
 #include <linux/serial_core.h>
 
 #include <asm/dma.h>
-#include <asm/arch/dma.h>
+#include <mach/dma.h>
 
 #include <asm/plat-s3c24xx/cpu.h>
 #include <asm/plat-s3c24xx/dma.h>
 
 #include <asm/plat-s3c/regs-serial.h>
-#include <asm/arch/regs-gpio.h>
+#include <mach/regs-gpio.h>
 #include <asm/plat-s3c/regs-ac97.h>
-#include <asm/arch/regs-mem.h>
-#include <asm/arch/regs-lcd.h>
-#include <asm/arch/regs-sdi.h>
+#include <mach/regs-mem.h>
+#include <mach/regs-lcd.h>
+#include <mach/regs-sdi.h>
 #include <asm/plat-s3c24xx/regs-iis.h>
 #include <asm/plat-s3c24xx/regs-spi.h>
 
diff --git a/arch/arm/mach-s3c2410/gpio.c b/arch/arm/mach-s3c2410/gpio.c
index d15621ef5b67..c6eefb1d590c 100644
--- a/arch/arm/mach-s3c2410/gpio.c
+++ b/arch/arm/mach-s3c2410/gpio.c
@@ -26,11 +26,11 @@
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/io.h>
 
-#include <asm/arch/regs-gpio.h>
+#include <mach/regs-gpio.h>
 
 int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
                            unsigned int config)
diff --git a/arch/arm/mach-s3c2410/h1940-bluetooth.c b/arch/arm/mach-s3c2410/h1940-bluetooth.c
index affa4fa12ac1..5a6bc56f186b 100644
--- a/arch/arm/mach-s3c2410/h1940-bluetooth.c
+++ b/arch/arm/mach-s3c2410/h1940-bluetooth.c
@@ -16,9 +16,9 @@
 #include <linux/string.h>
 #include <linux/ctype.h>
 #include <linux/leds.h>
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/h1940-latch.h>
+#include <mach/regs-gpio.h>
+#include <mach/hardware.h>
+#include <mach/h1940-latch.h>
 
 #define DRV_NAME              "h1940-bt"
 
diff --git a/arch/arm/mach-s3c2410/include/mach/anubis-cpld.h b/arch/arm/mach-s3c2410/include/mach/anubis-cpld.h
new file mode 100644
index 000000000000..1b614d5a81f3
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/anubis-cpld.h
@@ -0,0 +1,25 @@
+/* arch/arm/mach-s3c2410/include/mach/anubis-cpld.h
+ *
+ * Copyright (c) 2005 Simtec Electronics
+ *      http://www.simtec.co.uk/products/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * ANUBIS - CPLD control constants
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_ANUBISCPLD_H
+#define __ASM_ARCH_ANUBISCPLD_H
+
+/* CTRL2 - NAND WP control, IDE Reset assert/check */
+
+#define ANUBIS_CTRL1_NANDSEL            (0x3)
+
+/* IDREG - revision */
+
+#define ANUBIS_IDREG_REVMASK            (0x7)
+
+#endif /* __ASM_ARCH_ANUBISCPLD_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/anubis-irq.h b/arch/arm/mach-s3c2410/include/mach/anubis-irq.h
new file mode 100644
index 000000000000..a2a328134e34
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/anubis-irq.h
@@ -0,0 +1,21 @@
+/* arch/arm/mach-s3c2410/include/mach/anubis-irq.h
+ *
+ * Copyright (c) 2005 Simtec Electronics
+ *      http://www.simtec.co.uk/products/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ *  ANUBIS - IRQ Number definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_ANUBISIRQ_H
+#define __ASM_ARCH_ANUBISIRQ_H
+
+#define IRQ_IDE0       IRQ_EINT2
+#define IRQ_IDE1       IRQ_EINT3
+#define IRQ_ASIX       IRQ_EINT1
+
+#endif /* __ASM_ARCH_ANUBISIRQ_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/anubis-map.h b/arch/arm/mach-s3c2410/include/mach/anubis-map.h
new file mode 100644
index 000000000000..c9deb3a5b2c3
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/anubis-map.h
@@ -0,0 +1,38 @@
+/* arch/arm/mach-s3c2410/include/mach/anubis-map.h
+ *
+ * Copyright (c) 2005 Simtec Electronics
+ *      http://www.simtec.co.uk/products/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * ANUBIS - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* needs arch/map.h including with this */
+
+#ifndef __ASM_ARCH_ANUBISMAP_H
+#define __ASM_ARCH_ANUBISMAP_H
+
+/* start peripherals off after the S3C2410 */
+
+#define ANUBIS_IOADDR(x)        (S3C2410_ADDR((x) + 0x01800000))
+
+#define ANUBIS_PA_CPLD          (S3C2410_CS1 | (1<<26))
+
+/* we put the CPLD registers next, to get them out of the way */
+
+#define ANUBIS_VA_CTRL1     ANUBIS_IOADDR(0x00000000)    /* 0x01800000 */
+#define ANUBIS_PA_CTRL1     (ANUBIS_PA_CPLD)
+
+#define ANUBIS_VA_IDREG     ANUBIS_IOADDR(0x00300000)    /* 0x01B00000 */
+#define ANUBIS_PA_IDREG     (ANUBIS_PA_CPLD + (3<<23))
+
+#define ANUBIS_IDEPRI       ANUBIS_IOADDR(0x01000000)
+#define ANUBIS_IDEPRIAUX    ANUBIS_IOADDR(0x01100000)
+#define ANUBIS_IDESEC       ANUBIS_IOADDR(0x01200000)
+#define ANUBIS_IDESECAUX    ANUBIS_IOADDR(0x01300000)
+
+#endif /* __ASM_ARCH_ANUBISMAP_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/audio.h b/arch/arm/mach-s3c2410/include/mach/audio.h
new file mode 100644
index 000000000000..de0e8da48bc3
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/audio.h
@@ -0,0 +1,45 @@
+/* arch/arm/mach-s3c2410/include/mach/audio.h
+ *
+ * Copyright (c) 2004-2005 Simtec Electronics
+ *      http://www.simtec.co.uk/products/SWLINUX/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24XX - Audio platfrom_device info
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_AUDIO_H
+#define __ASM_ARCH_AUDIO_H __FILE__
+
+/* struct s3c24xx_iis_ops
+ *
+ * called from the s3c24xx audio core to deal with the architecture
+ * or the codec's setup and control.
+ *
+ * the pointer to itself is passed through in case the caller wants to
+ * embed this in an larger structure for easy reference to it's context.
+*/
+
+struct s3c24xx_iis_ops {
+        struct module *owner;
+
+        int     (*startup)(struct s3c24xx_iis_ops *me);
+        void    (*shutdown)(struct s3c24xx_iis_ops *me);
+        int     (*suspend)(struct s3c24xx_iis_ops *me);
+        int     (*resume)(struct s3c24xx_iis_ops *me);
+
+        int     (*open)(struct s3c24xx_iis_ops *me, struct snd_pcm_substream *strm);
+        int     (*close)(struct s3c24xx_iis_ops *me, struct snd_pcm_substream *strm);
+        int     (*prepare)(struct s3c24xx_iis_ops *me, struct snd_pcm_substream *strm, struct snd_pcm_runtime *rt);
+};
+
+struct s3c24xx_platdata_iis {
+        const char              *codec_clk;
+        struct s3c24xx_iis_ops  *ops;
+        int                     (*match_dev)(struct device *dev);
+};
+
+#endif /* __ASM_ARCH_AUDIO_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/bast-cpld.h b/arch/arm/mach-s3c2410/include/mach/bast-cpld.h
new file mode 100644
index 000000000000..20493b048360
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/bast-cpld.h
@@ -0,0 +1,53 @@
+/* arch/arm/mach-s3c2410/include/mach/bast-cpld.h
+ *
+ * Copyright (c) 2003,2004 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * BAST - CPLD control constants
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_BASTCPLD_H
+#define __ASM_ARCH_BASTCPLD_H
+
+/* CTRL1 - Audio LR routing */
+
+#define BAST_CPLD_CTRL1_LRCOFF      (0x00)
+#define BAST_CPLD_CTRL1_LRCADC      (0x01)
+#define BAST_CPLD_CTRL1_LRCDAC      (0x02)
+#define BAST_CPLD_CTRL1_LRCARM      (0x03)
+#define BAST_CPLD_CTRL1_LRMASK      (0x03)
+
+/* CTRL2 - NAND WP control, IDE Reset assert/check */
+
+#define BAST_CPLD_CTRL2_WNAND       (0x04)
+#define BAST_CPLD_CTLR2_IDERST      (0x08)
+
+/* CTRL3 - rom write control, CPLD identity */
+
+#define BAST_CPLD_CTRL3_IDMASK      (0x0e)
+#define BAST_CPLD_CTRL3_ROMWEN      (0x01)
+
+/* CTRL4 - 8bit LCD interface control/status */
+
+#define BAST_CPLD_CTRL4_LLAT        (0x01)
+#define BAST_CPLD_CTRL4_LCDRW       (0x02)
+#define BAST_CPLD_CTRL4_LCDCMD      (0x04)
+#define BAST_CPLD_CTRL4_LCDE2       (0x01)
+
+/* CTRL5 - DMA routing */
+
+#define BAST_CPLD_DMA0_PRIIDE      (0<<0)
+#define BAST_CPLD_DMA0_SECIDE      (1<<0)
+#define BAST_CPLD_DMA0_ISA15       (2<<0)
+#define BAST_CPLD_DMA0_ISA36       (3<<0)
+
+#define BAST_CPLD_DMA1_PRIIDE      (0<<2)
+#define BAST_CPLD_DMA1_SECIDE      (1<<2)
+#define BAST_CPLD_DMA1_ISA15       (2<<2)
+#define BAST_CPLD_DMA1_ISA36       (3<<2)
+
+#endif /* __ASM_ARCH_BASTCPLD_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/bast-irq.h b/arch/arm/mach-s3c2410/include/mach/bast-irq.h
new file mode 100644
index 000000000000..501c202b53cf
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/bast-irq.h
@@ -0,0 +1,29 @@
+/* arch/arm/mach-s3c2410/include/mach/bast-irq.h
+ *
+ * Copyright (c) 2003,2004 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Machine BAST - IRQ Number definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_BASTIRQ_H
+#define __ASM_ARCH_BASTIRQ_H
+
+/* irq numbers to onboard peripherals */
+
+#define IRQ_USBOC      IRQ_EINT18
+#define IRQ_IDE0       IRQ_EINT16
+#define IRQ_IDE1       IRQ_EINT17
+#define IRQ_PCSERIAL1  IRQ_EINT15
+#define IRQ_PCSERIAL2  IRQ_EINT14
+#define IRQ_PCPARALLEL IRQ_EINT13
+#define IRQ_ASIX       IRQ_EINT11
+#define IRQ_DM9000     IRQ_EINT10
+#define IRQ_ISA        IRQ_EINT9
+#define IRQ_SMALERT    IRQ_EINT8
+
+#endif /* __ASM_ARCH_BASTIRQ_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/bast-map.h b/arch/arm/mach-s3c2410/include/mach/bast-map.h
new file mode 100644
index 000000000000..c2c5baf07345
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/bast-map.h
@@ -0,0 +1,146 @@
+/* arch/arm/mach-s3c2410/include/mach/bast-map.h
+ *
+ * Copyright (c) 2003,2004 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Machine BAST - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* needs arch/map.h including with this */
+
+/* ok, we've used up to 0x13000000, now we need to find space for the
+ * peripherals that live in the nGCS[x] areas, which are quite numerous
+ * in their space. We also have the board's CPLD to find register space
+ * for.
+ */
+
+#ifndef __ASM_ARCH_BASTMAP_H
+#define __ASM_ARCH_BASTMAP_H
+
+#define BAST_IOADDR(x)     (S3C2410_ADDR((x) + 0x01300000))
+
+/* we put the CPLD registers next, to get them out of the way */
+
+#define BAST_VA_CTRL1       BAST_IOADDR(0x00000000)      /* 0x01300000 */
+#define BAST_PA_CTRL1       (S3C2410_CS5 | 0x7800000)
+
+#define BAST_VA_CTRL2       BAST_IOADDR(0x00100000)      /* 0x01400000 */
+#define BAST_PA_CTRL2       (S3C2410_CS1 | 0x6000000)
+
+#define BAST_VA_CTRL3       BAST_IOADDR(0x00200000)      /* 0x01500000 */
+#define BAST_PA_CTRL3       (S3C2410_CS1 | 0x6800000)
+
+#define BAST_VA_CTRL4       BAST_IOADDR(0x00300000)      /* 0x01600000 */
+#define BAST_PA_CTRL4       (S3C2410_CS1 | 0x7000000)
+
+/* next, we have the PC104 ISA interrupt registers */
+
+#define BAST_PA_PC104_IRQREQ  (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
+#define BAST_VA_PC104_IRQREQ  BAST_IOADDR(0x00400000)
+
+#define BAST_PA_PC104_IRQRAW  (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
+#define BAST_VA_PC104_IRQRAW  BAST_IOADDR(0x00500000)
+
+#define BAST_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
+#define BAST_VA_PC104_IRQMASK BAST_IOADDR(0x00600000)
+
+#define BAST_PA_LCD_RCMD1     (0x8800000)
+#define BAST_VA_LCD_RCMD1     BAST_IOADDR(0x00700000)
+
+#define BAST_PA_LCD_WCMD1     (0x8000000)
+#define BAST_VA_LCD_WCMD1     BAST_IOADDR(0x00800000)
+
+#define BAST_PA_LCD_RDATA1    (0x9800000)
+#define BAST_VA_LCD_RDATA1    BAST_IOADDR(0x00900000)
+
+#define BAST_PA_LCD_WDATA1    (0x9000000)
+#define BAST_VA_LCD_WDATA1    BAST_IOADDR(0x00A00000)
+
+#define BAST_PA_LCD_RCMD2     (0xA800000)
+#define BAST_VA_LCD_RCMD2     BAST_IOADDR(0x00B00000)
+
+#define BAST_PA_LCD_WCMD2     (0xA000000)
+#define BAST_VA_LCD_WCMD2     BAST_IOADDR(0x00C00000)
+
+#define BAST_PA_LCD_RDATA2    (0xB800000)
+#define BAST_VA_LCD_RDATA2    BAST_IOADDR(0x00D00000)
+
+#define BAST_PA_LCD_WDATA2    (0xB000000)
+#define BAST_VA_LCD_WDATA2    BAST_IOADDR(0x00E00000)
+
+
+/* 0xE0000000 contains the IO space that is split by speed and
+ * wether the access is for 8 or 16bit IO... this ensures that
+ * the correct access is made
+ *
+ * 0x10000000 of space, partitioned as so:
+ *
+ * 0x00000000 to 0x04000000  8bit,  slow
+ * 0x04000000 to 0x08000000  16bit, slow
+ * 0x08000000 to 0x0C000000  16bit, net
+ * 0x0C000000 to 0x10000000  16bit, fast
+ *
+ * each of these spaces has the following in:
+ *
+ * 0x00000000 to 0x01000000 16MB ISA IO space
+ * 0x01000000 to 0x02000000 16MB ISA memory space
+ * 0x02000000 to 0x02100000 1MB  IDE primary channel
+ * 0x02100000 to 0x02200000 1MB  IDE primary channel aux
+ * 0x02200000 to 0x02400000 1MB  IDE secondary channel
+ * 0x02300000 to 0x02400000 1MB  IDE secondary channel aux
+ * 0x02400000 to 0x02500000 1MB  ASIX ethernet controller
+ * 0x02500000 to 0x02600000 1MB  Davicom DM9000 ethernet controller
+ * 0x02600000 to 0x02700000 1MB  PC SuperIO controller
+ *
+ * the phyiscal layout of the zones are:
+ *  nGCS2 - 8bit, slow
+ *  nGCS3 - 16bit, slow
+ *  nGCS4 - 16bit, net
+ *  nGCS5 - 16bit, fast
+ */
+
+#define BAST_VA_MULTISPACE (0xE0000000)
+
+#define BAST_VA_ISAIO      (BAST_VA_MULTISPACE + 0x00000000)
+#define BAST_VA_ISAMEM     (BAST_VA_MULTISPACE + 0x01000000)
+#define BAST_VA_IDEPRI     (BAST_VA_MULTISPACE + 0x02000000)
+#define BAST_VA_IDEPRIAUX  (BAST_VA_MULTISPACE + 0x02100000)
+#define BAST_VA_IDESEC     (BAST_VA_MULTISPACE + 0x02200000)
+#define BAST_VA_IDESECAUX  (BAST_VA_MULTISPACE + 0x02300000)
+#define BAST_VA_ASIXNET    (BAST_VA_MULTISPACE + 0x02400000)
+#define BAST_VA_DM9000     (BAST_VA_MULTISPACE + 0x02500000)
+#define BAST_VA_SUPERIO    (BAST_VA_MULTISPACE + 0x02600000)
+
+#define BAST_VA_MULTISPACE (0xE0000000)
+
+#define BAST_VAM_CS2 (0x00000000)
+#define BAST_VAM_CS3 (0x04000000)
+#define BAST_VAM_CS4 (0x08000000)
+#define BAST_VAM_CS5 (0x0C000000)
+
+/* physical offset addresses for the peripherals */
+
+#define BAST_PA_ISAIO     (0x00000000)
+#define BAST_PA_ASIXNET   (0x01000000)
+#define BAST_PA_SUPERIO   (0x01800000)
+#define BAST_PA_IDEPRI    (0x02000000)
+#define BAST_PA_IDEPRIAUX (0x02800000)
+#define BAST_PA_IDESEC    (0x03000000)
+#define BAST_PA_IDESECAUX (0x03800000)
+#define BAST_PA_ISAMEM    (0x04000000)
+#define BAST_PA_DM9000    (0x05000000)
+
+/* some configurations for the peripherals */
+
+#define BAST_PCSIO (BAST_VA_SUPERIO + BAST_VAM_CS2)
+/*  */
+
+#define BAST_ASIXNET_CS  BAST_VAM_CS5
+#define BAST_IDE_CS      BAST_VAM_CS5
+#define BAST_DM9000_CS   BAST_VAM_CS4
+
+#endif /* __ASM_ARCH_BASTMAP_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/bast-pmu.h b/arch/arm/mach-s3c2410/include/mach/bast-pmu.h
new file mode 100644
index 000000000000..61684cb8ce59
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/bast-pmu.h
@@ -0,0 +1,40 @@
+/* arch/arm/mach-s3c2410/include/mach/bast-pmu.h
+ *
+ * Copyright (c) 2003,2004 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      Vincent Sanders <vince@simtec.co.uk>
+ *
+ * Machine BAST - Power Management chip
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_BASTPMU_H
+#define __ASM_ARCH_BASTPMU_H "08_OCT_2004"
+
+#define BASTPMU_REG_IDENT       (0x00)
+#define BASTPMU_REG_VERSION     (0x01)
+#define BASTPMU_REG_DDCCTRL     (0x02)
+#define BASTPMU_REG_POWER       (0x03)
+#define BASTPMU_REG_RESET       (0x04)
+#define BASTPMU_REG_GWO         (0x05)
+#define BASTPMU_REG_WOL         (0x06)
+#define BASTPMU_REG_WOR         (0x07)
+#define BASTPMU_REG_UID         (0x09)
+
+#define BASTPMU_EEPROM          (0xC0)
+
+#define BASTPMU_EEP_UID         (BASTPMU_EEPROM + 0)
+#define BASTPMU_EEP_WOL         (BASTPMU_EEPROM + 8)
+#define BASTPMU_EEP_WOR         (BASTPMU_EEPROM + 9)
+
+#define BASTPMU_IDENT_0         0x53
+#define BASTPMU_IDENT_1         0x42
+#define BASTPMU_IDENT_2         0x50
+#define BASTPMU_IDENT_3         0x4d
+
+#define BASTPMU_RESET_GUARD     (0x55)
+
+#endif /* __ASM_ARCH_BASTPMU_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/debug-macro.S b/arch/arm/mach-s3c2410/include/mach/debug-macro.S
new file mode 100644
index 000000000000..682df23087ab
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/debug-macro.S
@@ -0,0 +1,102 @@
+/* arch/arm/mach-s3c2410/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Copyright (C) 2005 Simtec Electronics
+ *
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <mach/map.h>
+#include <mach/regs-gpio.h>
+#include <asm/plat-s3c/regs-serial.h>
+
+#define S3C2410_UART1_OFF (0x4000)
+#define SHIFT_2440TXF (14-9)
+
+        .macro addruart, rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1
+                ldreq   \rx, = S3C24XX_PA_UART
+                ldrne   \rx, = S3C24XX_VA_UART
+#if CONFIG_DEBUG_S3C_UART != 0
+                add     \rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
+#endif
+        .endm
+
+        .macro fifo_full_s3c24xx rd, rx
+                @ check for arm920 vs arm926. currently assume all arm926
+                @ devices have an 64 byte FIFO identical to the s3c2440
+                mrc     p15, 0, \rd, c0, c0
+                and     \rd, \rd, #0xff0
+                teq     \rd, #0x260
+                beq     1004f
+                mrc     p15, 0, \rd, c1, c0
+                tst     \rd, #1
+                addeq   \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
+                addne   \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART)
+                bic     \rd, \rd, #0xff000
+                ldr     \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ]
+                and     \rd, \rd, #0x00ff0000
+                teq     \rd, #0x00440000                @ is it 2440?
+1004:
+                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                moveq   \rd, \rd, lsr #SHIFT_2440TXF
+                tst     \rd, #S3C2410_UFSTAT_TXFULL
+        .endm
+
+        .macro  fifo_full_s3c2410 rd, rx
+                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                tst     \rd, #S3C2410_UFSTAT_TXFULL
+        .endm
+
+/* fifo level reading */
+
+        .macro fifo_level_s3c24xx rd, rx
+                @ check for arm920 vs arm926. currently assume all arm926
+                @ devices have an 64 byte FIFO identical to the s3c2440
+                mrc     p15, 0, \rd, c0, c0
+                and     \rd, \rd, #0xff0
+                teq     \rd, #0x260
+                beq     10000f
+                mrc     p15, 0, \rd, c1, c0
+                tst     \rd, #1
+                addeq   \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
+                addne   \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART)
+                bic     \rd, \rd, #0xff000
+                ldr     \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ]
+                and     \rd, \rd, #0x00ff0000
+                teq     \rd, #0x00440000                @ is it 2440?
+
+10000:
+                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                andne   \rd, \rd, #S3C2410_UFSTAT_TXMASK
+                andeq   \rd, \rd, #S3C2440_UFSTAT_TXMASK
+        .endm
+
+        .macro fifo_level_s3c2410 rd, rx
+                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                and     \rd, \rd, #S3C2410_UFSTAT_TXMASK
+        .endm
+
+/* Select the correct implementation depending on the configuration. The
+ * S3C2440 will get selected by default, as these are the most widely
+ * used variants of these
+*/
+
+#if defined(CONFIG_CPU_LLSERIAL_S3C2410_ONLY)
+#define fifo_full  fifo_full_s3c2410
+#define fifo_level fifo_level_s3c2410
+#elif !defined(CONFIG_CPU_LLSERIAL_S3C2440_ONLY)
+#define fifo_full  fifo_full_s3c24xx
+#define fifo_level fifo_level_s3c24xx
+#endif
+
+/* include the reset of the code which will do the work */
+
+#include <asm/plat-s3c/debug-macro.S>
diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h
new file mode 100644
index 000000000000..891b53cd69b8
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/dma.h
@@ -0,0 +1,453 @@
+/* arch/arm/mach-s3c2410/include/mach/dma.h
+ *
+ * Copyright (C) 2003,2004,2006 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Samsung S3C241XX DMA support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H __FILE__
+
+#include <linux/sysdev.h>
+#include <mach/hardware.h>
+
+/*
+ * This is the maximum DMA address(physical address) that can be DMAd to.
+ *
+ */
+#define MAX_DMA_ADDRESS         0x40000000
+#define MAX_DMA_TRANSFER_SIZE   0x100000 /* Data Unit is half word  */
+
+/* We use `virtual` dma channels to hide the fact we have only a limited
+ * number of DMA channels, and not of all of them (dependant on the device)
+ * can be attached to any DMA source. We therefore let the DMA core handle
+ * the allocation of hardware channels to clients.
+*/
+
+enum dma_ch {
+        DMACH_XD0,
+        DMACH_XD1,
+        DMACH_SDI,
+        DMACH_SPI0,
+        DMACH_SPI1,
+        DMACH_UART0,
+        DMACH_UART1,
+        DMACH_UART2,
+        DMACH_TIMER,
+        DMACH_I2S_IN,
+        DMACH_I2S_OUT,
+        DMACH_PCM_IN,
+        DMACH_PCM_OUT,
+        DMACH_MIC_IN,
+        DMACH_USB_EP1,
+        DMACH_USB_EP2,
+        DMACH_USB_EP3,
+        DMACH_USB_EP4,
+        DMACH_UART0_SRC2,       /* s3c2412 second uart sources */
+        DMACH_UART1_SRC2,
+        DMACH_UART2_SRC2,
+        DMACH_UART3,            /* s3c2443 has extra uart */
+        DMACH_UART3_SRC2,
+        DMACH_MAX,              /* the end entry */
+};
+
+#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
+
+/* we have 4 dma channels */
+#ifndef CONFIG_CPU_S3C2443
+#define S3C2410_DMA_CHANNELS            (4)
+#else
+#define S3C2410_DMA_CHANNELS            (6)
+#endif
+
+/* types */
+
+enum s3c2410_dma_state {
+        S3C2410_DMA_IDLE,
+        S3C2410_DMA_RUNNING,
+        S3C2410_DMA_PAUSED
+};
+
+
+/* enum s3c2410_dma_loadst
+ *
+ * This represents the state of the DMA engine, wrt to the loaded / running
+ * transfers. Since we don't have any way of knowing exactly the state of
+ * the DMA transfers, we need to know the state to make decisions on wether
+ * we can
+ *
+ * S3C2410_DMA_NONE
+ *
+ * There are no buffers loaded (the channel should be inactive)
+ *
+ * S3C2410_DMA_1LOADED
+ *
+ * There is one buffer loaded, however it has not been confirmed to be
+ * loaded by the DMA engine. This may be because the channel is not
+ * yet running, or the DMA driver decided that it was too costly to
+ * sit and wait for it to happen.
+ *
+ * S3C2410_DMA_1RUNNING
+ *
+ * The buffer has been confirmed running, and not finisged
+ *
+ * S3C2410_DMA_1LOADED_1RUNNING
+ *
+ * There is a buffer waiting to be loaded by the DMA engine, and one
+ * currently running.
+*/
+
+enum s3c2410_dma_loadst {
+        S3C2410_DMALOAD_NONE,
+        S3C2410_DMALOAD_1LOADED,
+        S3C2410_DMALOAD_1RUNNING,
+        S3C2410_DMALOAD_1LOADED_1RUNNING,
+};
+
+enum s3c2410_dma_buffresult {
+        S3C2410_RES_OK,
+        S3C2410_RES_ERR,
+        S3C2410_RES_ABORT
+};
+
+enum s3c2410_dmasrc {
+        S3C2410_DMASRC_HW,              /* source is memory */
+        S3C2410_DMASRC_MEM              /* source is hardware */
+};
+
+/* enum s3c2410_chan_op
+ *
+ * operation codes passed to the DMA code by the user, and also used
+ * to inform the current channel owner of any changes to the system state
+*/
+
+enum s3c2410_chan_op {
+        S3C2410_DMAOP_START,
+        S3C2410_DMAOP_STOP,
+        S3C2410_DMAOP_PAUSE,
+        S3C2410_DMAOP_RESUME,
+        S3C2410_DMAOP_FLUSH,
+        S3C2410_DMAOP_TIMEOUT,          /* internal signal to handler */
+        S3C2410_DMAOP_STARTED,          /* indicate channel started */
+};
+
+/* flags */
+
+#define S3C2410_DMAF_SLOW         (1<<0)   /* slow, so don't worry about
+                                            * waiting for reloads */
+#define S3C2410_DMAF_AUTOSTART    (1<<1)   /* auto-start if buffer queued */
+
+/* dma buffer */
+
+struct s3c2410_dma_client {
+        char                *name;
+};
+
+/* s3c2410_dma_buf_s
+ *
+ * internally used buffer structure to describe a queued or running
+ * buffer.
+*/
+
+struct s3c2410_dma_buf;
+struct s3c2410_dma_buf {
+        struct s3c2410_dma_buf  *next;
+        int                      magic;         /* magic */
+        int                      size;          /* buffer size in bytes */
+        dma_addr_t               data;          /* start of DMA data */
+        dma_addr_t               ptr;           /* where the DMA got to [1] */
+        void                    *id;            /* client's id */
+};
+
+/* [1] is this updated for both recv/send modes? */
+
+struct s3c2410_dma_chan;
+
+/* s3c2410_dma_cbfn_t
+ *
+ * buffer callback routine type
+*/
+
+typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
+                                   void *buf, int size,
+                                   enum s3c2410_dma_buffresult result);
+
+typedef int  (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
+                                   enum s3c2410_chan_op );
+
+struct s3c2410_dma_stats {
+        unsigned long           loads;
+        unsigned long           timeout_longest;
+        unsigned long           timeout_shortest;
+        unsigned long           timeout_avg;
+        unsigned long           timeout_failed;
+};
+
+struct s3c2410_dma_map;
+
+/* struct s3c2410_dma_chan
+ *
+ * full state information for each DMA channel
+*/
+
+struct s3c2410_dma_chan {
+        /* channel state flags and information */
+        unsigned char            number;      /* number of this dma channel */
+        unsigned char            in_use;      /* channel allocated */
+        unsigned char            irq_claimed; /* irq claimed for channel */
+        unsigned char            irq_enabled; /* irq enabled for channel */
+        unsigned char            xfer_unit;   /* size of an transfer */
+
+        /* channel state */
+
+        enum s3c2410_dma_state   state;
+        enum s3c2410_dma_loadst  load_state;
+        struct s3c2410_dma_client *client;
+
+        /* channel configuration */
+        enum s3c2410_dmasrc      source;
+        unsigned long            dev_addr;
+        unsigned long            load_timeout;
+        unsigned int             flags;         /* channel flags */
+        unsigned int             hw_cfg;        /* last hw config */
+
+        struct s3c24xx_dma_map  *map;           /* channel hw maps */
+
+        /* channel's hardware position and configuration */
+        void __iomem            *regs;          /* channels registers */
+        void __iomem            *addr_reg;      /* data address register */
+        unsigned int             irq;           /* channel irq */
+        unsigned long            dcon;          /* default value of DCON */
+
+        /* driver handles */
+        s3c2410_dma_cbfn_t       callback_fn;   /* buffer done callback */
+        s3c2410_dma_opfn_t       op_fn;         /* channel op callback */
+
+        /* stats gathering */
+        struct s3c2410_dma_stats *stats;
+        struct s3c2410_dma_stats  stats_store;
+
+        /* buffer list and information */
+        struct s3c2410_dma_buf  *curr;          /* current dma buffer */
+        struct s3c2410_dma_buf  *next;          /* next buffer to load */
+        struct s3c2410_dma_buf  *end;           /* end of queue */
+
+        /* system device */
+        struct sys_device       dev;
+};
+
+/* the currently allocated channel information */
+extern struct s3c2410_dma_chan s3c2410_chans[];
+
+/* note, we don't really use dma_device_t at the moment */
+typedef unsigned long dma_device_t;
+
+/* functions --------------------------------------------------------------- */
+
+/* s3c2410_dma_request
+ *
+ * request a dma channel exclusivley
+*/
+
+extern int s3c2410_dma_request(dmach_t channel,
+                               struct s3c2410_dma_client *, void *dev);
+
+
+/* s3c2410_dma_ctrl
+ *
+ * change the state of the dma channel
+*/
+
+extern int s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op);
+
+/* s3c2410_dma_setflags
+ *
+ * set the channel's flags to a given state
+*/
+
+extern int s3c2410_dma_setflags(dmach_t channel,
+                                unsigned int flags);
+
+/* s3c2410_dma_free
+ *
+ * free the dma channel (will also abort any outstanding operations)
+*/
+
+extern int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *);
+
+/* s3c2410_dma_enqueue
+ *
+ * place the given buffer onto the queue of operations for the channel.
+ * The buffer must be allocated from dma coherent memory, or the Dcache/WB
+ * drained before the buffer is given to the DMA system.
+*/
+
+extern int s3c2410_dma_enqueue(dmach_t channel, void *id,
+                               dma_addr_t data, int size);
+
+/* s3c2410_dma_config
+ *
+ * configure the dma channel
+*/
+
+extern int s3c2410_dma_config(dmach_t channel, int xferunit, int dcon);
+
+/* s3c2410_dma_devconfig
+ *
+ * configure the device we're talking to
+*/
+
+extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
+                                 int hwcfg, unsigned long devaddr);
+
+/* s3c2410_dma_getposition
+ *
+ * get the position that the dma transfer is currently at
+*/
+
+extern int s3c2410_dma_getposition(dmach_t channel,
+                                   dma_addr_t *src, dma_addr_t *dest);
+
+extern int s3c2410_dma_set_opfn(dmach_t, s3c2410_dma_opfn_t rtn);
+extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn);
+
+/* DMA Register definitions */
+
+#define S3C2410_DMA_DISRC       (0x00)
+#define S3C2410_DMA_DISRCC      (0x04)
+#define S3C2410_DMA_DIDST       (0x08)
+#define S3C2410_DMA_DIDSTC      (0x0C)
+#define S3C2410_DMA_DCON        (0x10)
+#define S3C2410_DMA_DSTAT       (0x14)
+#define S3C2410_DMA_DCSRC       (0x18)
+#define S3C2410_DMA_DCDST       (0x1C)
+#define S3C2410_DMA_DMASKTRIG   (0x20)
+#define S3C2412_DMA_DMAREQSEL   (0x24)
+#define S3C2443_DMA_DMAREQSEL   (0x24)
+
+#define S3C2410_DISRCC_INC      (1<<0)
+#define S3C2410_DISRCC_APB      (1<<1)
+
+#define S3C2410_DMASKTRIG_STOP   (1<<2)
+#define S3C2410_DMASKTRIG_ON     (1<<1)
+#define S3C2410_DMASKTRIG_SWTRIG (1<<0)
+
+#define S3C2410_DCON_DEMAND     (0<<31)
+#define S3C2410_DCON_HANDSHAKE  (1<<31)
+#define S3C2410_DCON_SYNC_PCLK  (0<<30)
+#define S3C2410_DCON_SYNC_HCLK  (1<<30)
+
+#define S3C2410_DCON_INTREQ     (1<<29)
+
+#define S3C2410_DCON_CH0_XDREQ0 (0<<24)
+#define S3C2410_DCON_CH0_UART0  (1<<24)
+#define S3C2410_DCON_CH0_SDI    (2<<24)
+#define S3C2410_DCON_CH0_TIMER  (3<<24)
+#define S3C2410_DCON_CH0_USBEP1 (4<<24)
+
+#define S3C2410_DCON_CH1_XDREQ1 (0<<24)
+#define S3C2410_DCON_CH1_UART1  (1<<24)
+#define S3C2410_DCON_CH1_I2SSDI (2<<24)
+#define S3C2410_DCON_CH1_SPI    (3<<24)
+#define S3C2410_DCON_CH1_USBEP2 (4<<24)
+
+#define S3C2410_DCON_CH2_I2SSDO (0<<24)
+#define S3C2410_DCON_CH2_I2SSDI (1<<24)
+#define S3C2410_DCON_CH2_SDI    (2<<24)
+#define S3C2410_DCON_CH2_TIMER  (3<<24)
+#define S3C2410_DCON_CH2_USBEP3 (4<<24)
+
+#define S3C2410_DCON_CH3_UART2  (0<<24)
+#define S3C2410_DCON_CH3_SDI    (1<<24)
+#define S3C2410_DCON_CH3_SPI    (2<<24)
+#define S3C2410_DCON_CH3_TIMER  (3<<24)
+#define S3C2410_DCON_CH3_USBEP4 (4<<24)
+
+#define S3C2410_DCON_SRCSHIFT   (24)
+#define S3C2410_DCON_SRCMASK    (7<<24)
+
+#define S3C2410_DCON_BYTE       (0<<20)
+#define S3C2410_DCON_HALFWORD   (1<<20)
+#define S3C2410_DCON_WORD       (2<<20)
+
+#define S3C2410_DCON_AUTORELOAD (0<<22)
+#define S3C2410_DCON_NORELOAD   (1<<22)
+#define S3C2410_DCON_HWTRIG     (1<<23)
+
+#ifdef CONFIG_CPU_S3C2440
+#define S3C2440_DIDSTC_CHKINT   (1<<2)
+
+#define S3C2440_DCON_CH0_I2SSDO (5<<24)
+#define S3C2440_DCON_CH0_PCMIN  (6<<24)
+
+#define S3C2440_DCON_CH1_PCMOUT (5<<24)
+#define S3C2440_DCON_CH1_SDI    (6<<24)
+
+#define S3C2440_DCON_CH2_PCMIN  (5<<24)
+#define S3C2440_DCON_CH2_MICIN  (6<<24)
+
+#define S3C2440_DCON_CH3_MICIN  (5<<24)
+#define S3C2440_DCON_CH3_PCMOUT (6<<24)
+#endif
+
+#ifdef CONFIG_CPU_S3C2412
+
+#define S3C2412_DMAREQSEL_SRC(x)        ((x)<<1)
+
+#define S3C2412_DMAREQSEL_HW            (1)
+
+#define S3C2412_DMAREQSEL_SPI0TX        S3C2412_DMAREQSEL_SRC(0)
+#define S3C2412_DMAREQSEL_SPI0RX        S3C2412_DMAREQSEL_SRC(1)
+#define S3C2412_DMAREQSEL_SPI1TX        S3C2412_DMAREQSEL_SRC(2)
+#define S3C2412_DMAREQSEL_SPI1RX        S3C2412_DMAREQSEL_SRC(3)
+#define S3C2412_DMAREQSEL_I2STX         S3C2412_DMAREQSEL_SRC(4)
+#define S3C2412_DMAREQSEL_I2SRX         S3C2412_DMAREQSEL_SRC(5)
+#define S3C2412_DMAREQSEL_TIMER         S3C2412_DMAREQSEL_SRC(9)
+#define S3C2412_DMAREQSEL_SDI           S3C2412_DMAREQSEL_SRC(10)
+#define S3C2412_DMAREQSEL_USBEP1        S3C2412_DMAREQSEL_SRC(13)
+#define S3C2412_DMAREQSEL_USBEP2        S3C2412_DMAREQSEL_SRC(14)
+#define S3C2412_DMAREQSEL_USBEP3        S3C2412_DMAREQSEL_SRC(15)
+#define S3C2412_DMAREQSEL_USBEP4        S3C2412_DMAREQSEL_SRC(16)
+#define S3C2412_DMAREQSEL_XDREQ0        S3C2412_DMAREQSEL_SRC(17)
+#define S3C2412_DMAREQSEL_XDREQ1        S3C2412_DMAREQSEL_SRC(18)
+#define S3C2412_DMAREQSEL_UART0_0       S3C2412_DMAREQSEL_SRC(19)
+#define S3C2412_DMAREQSEL_UART0_1       S3C2412_DMAREQSEL_SRC(20)
+#define S3C2412_DMAREQSEL_UART1_0       S3C2412_DMAREQSEL_SRC(21)
+#define S3C2412_DMAREQSEL_UART1_1       S3C2412_DMAREQSEL_SRC(22)
+#define S3C2412_DMAREQSEL_UART2_0       S3C2412_DMAREQSEL_SRC(23)
+#define S3C2412_DMAREQSEL_UART2_1       S3C2412_DMAREQSEL_SRC(24)
+
+#endif
+
+#define S3C2443_DMAREQSEL_SRC(x)        ((x)<<1)
+
+#define S3C2443_DMAREQSEL_HW            (1)
+
+#define S3C2443_DMAREQSEL_SPI0TX        S3C2443_DMAREQSEL_SRC(0)
+#define S3C2443_DMAREQSEL_SPI0RX        S3C2443_DMAREQSEL_SRC(1)
+#define S3C2443_DMAREQSEL_SPI1TX        S3C2443_DMAREQSEL_SRC(2)
+#define S3C2443_DMAREQSEL_SPI1RX        S3C2443_DMAREQSEL_SRC(3)
+#define S3C2443_DMAREQSEL_I2STX         S3C2443_DMAREQSEL_SRC(4)
+#define S3C2443_DMAREQSEL_I2SRX         S3C2443_DMAREQSEL_SRC(5)
+#define S3C2443_DMAREQSEL_TIMER         S3C2443_DMAREQSEL_SRC(9)
+#define S3C2443_DMAREQSEL_SDI           S3C2443_DMAREQSEL_SRC(10)
+#define S3C2443_DMAREQSEL_XDREQ0        S3C2443_DMAREQSEL_SRC(17)
+#define S3C2443_DMAREQSEL_XDREQ1        S3C2443_DMAREQSEL_SRC(18)
+#define S3C2443_DMAREQSEL_UART0_0       S3C2443_DMAREQSEL_SRC(19)
+#define S3C2443_DMAREQSEL_UART0_1       S3C2443_DMAREQSEL_SRC(20)
+#define S3C2443_DMAREQSEL_UART1_0       S3C2443_DMAREQSEL_SRC(21)
+#define S3C2443_DMAREQSEL_UART1_1       S3C2443_DMAREQSEL_SRC(22)
+#define S3C2443_DMAREQSEL_UART2_0       S3C2443_DMAREQSEL_SRC(23)
+#define S3C2443_DMAREQSEL_UART2_1       S3C2443_DMAREQSEL_SRC(24)
+#define S3C2443_DMAREQSEL_UART3_0       S3C2443_DMAREQSEL_SRC(25)
+#define S3C2443_DMAREQSEL_UART3_1       S3C2443_DMAREQSEL_SRC(26)
+#define S3C2443_DMAREQSEL_PCMOUT        S3C2443_DMAREQSEL_SRC(27)
+#define S3C2443_DMAREQSEL_PCMIN         S3C2443_DMAREQSEL_SRC(28)
+#define S3C2443_DMAREQSEL_MICIN         S3C2443_DMAREQSEL_SRC(29)
+
+#endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/entry-macro.S b/arch/arm/mach-s3c2410/include/mach/entry-macro.S
new file mode 100644
index 000000000000..473b3cd37d9b
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/entry-macro.S
@@ -0,0 +1,78 @@
+/*
+ * arch/arm/mach-s3c2410/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for S3C2410-based platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+*/
+
+/* We have a problem that the INTOFFSET register does not always
+ * show one interrupt. Occasionally we get two interrupts through
+ * the prioritiser, and this causes the INTOFFSET register to show
+ * what looks like the logical-or of the two interrupt numbers.
+ *
+ * Thanks to Klaus, Shannon, et al for helping to debug this problem
+*/
+
+#define INTPND          (0x10)
+#define INTOFFSET       (0x14)
+
+#include <mach/hardware.h>
+#include <asm/irq.h>
+
+        .macro  get_irqnr_preamble, base, tmp
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+                mov     \base, #S3C24XX_VA_IRQ
+
+                @@ try the interrupt offset register, since it is there
+
+                ldr     \irqstat, [ \base, #INTPND ]
+                teq     \irqstat, #0
+                beq     1002f
+                ldr     \irqnr, [ \base, #INTOFFSET ]
+                mov     \tmp, #1
+                tst     \irqstat, \tmp, lsl \irqnr
+                bne     1001f
+
+                @@ the number specified is not a valid irq, so try
+                @@ and work it out for ourselves
+
+                mov     \irqnr, #0              @@ start here
+
+                @@ work out which irq (if any) we got
+
+                movs    \tmp, \irqstat, lsl#16
+                addeq   \irqnr, \irqnr, #16
+                moveq   \irqstat, \irqstat, lsr#16
+                tst     \irqstat, #0xff
+                addeq   \irqnr, \irqnr, #8
+                moveq   \irqstat, \irqstat, lsr#8
+                tst     \irqstat, #0xf
+                addeq   \irqnr, \irqnr, #4
+                moveq   \irqstat, \irqstat, lsr#4
+                tst     \irqstat, #0x3
+                addeq   \irqnr, \irqnr, #2
+                moveq   \irqstat, \irqstat, lsr#2
+                tst     \irqstat, #0x1
+                addeq   \irqnr, \irqnr, #1
+
+                @@ we have the value
+1001:
+                adds    \irqnr, \irqnr, #IRQ_EINT0
+1002:
+                @@ exit here, Z flag unset if IRQ
+
+        .endm
+
+                /* currently don't need an disable_fiq macro */
+
+                .macro  disable_fiq
+                .endm
diff --git a/arch/arm/mach-s3c2410/include/mach/fb.h b/arch/arm/mach-s3c2410/include/mach/fb.h
new file mode 100644
index 000000000000..eee0654eb8fb
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/fb.h
@@ -0,0 +1,74 @@
+/* arch/arm/mach-s3c2410/include/mach/fb.h
+ *
+ * Copyright (c) 2004 Arnaud Patard <arnaud.patard@rtp-net.org>
+ *
+ * Inspired by pxafb.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARM_FB_H
+#define __ASM_ARM_FB_H
+
+#include <mach/regs-lcd.h>
+
+struct s3c2410fb_hw {
+        unsigned long   lcdcon1;
+        unsigned long   lcdcon2;
+        unsigned long   lcdcon3;
+        unsigned long   lcdcon4;
+        unsigned long   lcdcon5;
+};
+
+/* LCD description */
+struct s3c2410fb_display {
+        /* LCD type */
+        unsigned type;
+
+        /* Screen size */
+        unsigned short width;
+        unsigned short height;
+
+        /* Screen info */
+        unsigned short xres;
+        unsigned short yres;
+        unsigned short bpp;
+
+        unsigned pixclock;              /* pixclock in picoseconds */
+        unsigned short left_margin;  /* value in pixels (TFT) or HCLKs (STN) */
+        unsigned short right_margin; /* value in pixels (TFT) or HCLKs (STN) */
+        unsigned short hsync_len;    /* value in pixels (TFT) or HCLKs (STN) */
+        unsigned short upper_margin;    /* value in lines (TFT) or 0 (STN) */
+        unsigned short lower_margin;    /* value in lines (TFT) or 0 (STN) */
+        unsigned short vsync_len;       /* value in lines (TFT) or 0 (STN) */
+
+        /* lcd configuration registers */
+        unsigned long   lcdcon5;
+};
+
+struct s3c2410fb_mach_info {
+
+        struct s3c2410fb_display *displays;     /* attached diplays info */
+        unsigned num_displays;                  /* number of defined displays */
+        unsigned default_display;
+
+        /* GPIOs */
+
+        unsigned long   gpcup;
+        unsigned long   gpcup_mask;
+        unsigned long   gpccon;
+        unsigned long   gpccon_mask;
+        unsigned long   gpdup;
+        unsigned long   gpdup_mask;
+        unsigned long   gpdcon;
+        unsigned long   gpdcon_mask;
+
+        /* lpc3600 control register */
+        unsigned long   lpcsel;
+};
+
+extern void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *);
+
+#endif /* __ASM_ARM_FB_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio.h b/arch/arm/mach-s3c2410/include/mach/gpio.h
new file mode 100644
index 000000000000..3b52b86498a6
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/gpio.h
@@ -0,0 +1,18 @@
+/* arch/arm/mach-s3c2410/include/mach/gpio.h
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - GPIO lib support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
+
+#include <asm-generic/gpio.h>
diff --git a/arch/arm/mach-s3c2410/include/mach/h1940-latch.h b/arch/arm/mach-s3c2410/include/mach/h1940-latch.h
new file mode 100644
index 000000000000..d8a832729a8a
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/h1940-latch.h
@@ -0,0 +1,64 @@
+/* arch/arm/mach-s3c2410/include/mach/h1940-latch.h
+ *
+ * Copyright (c) 2005 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ *  iPAQ H1940 series - latch definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_H1940_LATCH_H
+#define __ASM_ARCH_H1940_LATCH_H
+
+
+#ifndef __ASSEMBLY__
+#define H1940_LATCH             ((void __force __iomem *)0xF8000000)
+#else
+#define H1940_LATCH             0xF8000000
+#endif
+
+#define H1940_PA_LATCH          (S3C2410_CS2)
+
+/* SD layer latch */
+
+#define H1940_LATCH_SDQ1                (1<<16)
+#define H1940_LATCH_LCD_P1              (1<<17)
+#define H1940_LATCH_LCD_P2              (1<<18)
+#define H1940_LATCH_LCD_P3              (1<<19)
+#define H1940_LATCH_MAX1698_nSHUTDOWN   (1<<20)         /* LCD backlight */
+#define H1940_LATCH_LED_RED             (1<<21)
+#define H1940_LATCH_SDQ7                (1<<22)
+#define H1940_LATCH_USB_DP              (1<<23)
+
+/* CPU layer latch */
+
+#define H1940_LATCH_UDA_POWER           (1<<24)
+#define H1940_LATCH_AUDIO_POWER         (1<<25)
+#define H1940_LATCH_SM803_ENABLE        (1<<26)
+#define H1940_LATCH_LCD_P4              (1<<27)
+#define H1940_LATCH_CPUQ5               (1<<28)         /* untraced */
+#define H1940_LATCH_BLUETOOTH_POWER     (1<<29)         /* active high */
+#define H1940_LATCH_LED_GREEN           (1<<30)
+#define H1940_LATCH_LED_FLASH           (1<<31)
+
+/* default settings */
+
+#define H1940_LATCH_DEFAULT             \
+        H1940_LATCH_LCD_P4              | \
+        H1940_LATCH_SM803_ENABLE        | \
+        H1940_LATCH_SDQ1                | \
+        H1940_LATCH_LCD_P1              | \
+        H1940_LATCH_LCD_P2              | \
+        H1940_LATCH_LCD_P3              | \
+        H1940_LATCH_MAX1698_nSHUTDOWN   | \
+        H1940_LATCH_CPUQ5
+
+/* control functions */
+
+extern void h1940_latch_control(unsigned int clear, unsigned int set);
+
+#endif /* __ASM_ARCH_H1940_LATCH_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/h1940.h b/arch/arm/mach-s3c2410/include/mach/h1940.h
new file mode 100644
index 000000000000..4559784129c0
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/h1940.h
@@ -0,0 +1,21 @@
+/* arch/arm/mach-s3c2410/include/mach/h1940.h
+ *
+ * Copyright 2006 Ben Dooks <ben-linux@fluff.org>
+ *
+ * H1940 definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_H1940_H
+#define __ASM_ARCH_H1940_H
+
+#define H1940_SUSPEND_CHECKSUM          (0x30003ff8)
+#define H1940_SUSPEND_RESUMEAT          (0x30081000)
+#define H1940_SUSPEND_CHECK             (0x30080000)
+
+extern void h1940_pm_return(void);
+
+#endif /* __ASM_ARCH_H1940_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/hardware.h b/arch/arm/mach-s3c2410/include/mach/hardware.h
new file mode 100644
index 000000000000..74d5a1a4024c
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/hardware.h
@@ -0,0 +1,137 @@
+/* arch/arm/mach-s3c2410/include/mach/hardware.h
+ *
+ * Copyright (c) 2003 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - hardware
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#ifndef __ASSEMBLY__
+
+/* external functions for GPIO support
+ *
+ * These allow various different clients to access the same GPIO
+ * registers without conflicting. If your driver only owns the entire
+ * GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
+*/
+
+/* s3c2410_gpio_cfgpin
+ *
+ * set the configuration of the given pin to the value passed.
+ *
+ * eg:
+ *    s3c2410_gpio_cfgpin(S3C2410_GPA0, S3C2410_GPA0_ADDR0);
+ *    s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1);
+*/
+
+extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function);
+
+extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
+
+/* s3c2410_gpio_getirq
+ *
+ * turn the given pin number into the corresponding IRQ number
+ *
+ * returns:
+ *      < 0 = no interrupt for this pin
+ *      >=0 = interrupt number for the pin
+*/
+
+extern int s3c2410_gpio_getirq(unsigned int pin);
+
+/* s3c2410_gpio_irq2pin
+ *
+ * turn the given irq number into the corresponding GPIO number
+ *
+ * returns:
+ *      < 0 = no pin
+ *      >=0 = gpio pin number
+*/
+
+extern int s3c2410_gpio_irq2pin(unsigned int irq);
+
+#ifdef CONFIG_CPU_S3C2400
+
+extern int s3c2400_gpio_getirq(unsigned int pin);
+
+#endif /* CONFIG_CPU_S3C2400 */
+
+/* s3c2410_gpio_irqfilter
+ *
+ * set the irq filtering on the given pin
+ *
+ * on = 0 => disable filtering
+ *      1 => enable filtering
+ *
+ * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with
+ *          width of filter (0 through 63)
+ *
+ *
+*/
+
+extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
+                                  unsigned int config);
+
+/* s3c2410_gpio_pullup
+ *
+ * configure the pull-up control on the given pin
+ *
+ * to = 1 => disable the pull-up
+ *      0 => enable the pull-up
+ *
+ * eg;
+ *
+ *   s3c2410_gpio_pullup(S3C2410_GPB0, 0);
+ *   s3c2410_gpio_pullup(S3C2410_GPE8, 0);
+*/
+
+extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
+
+/* s3c2410_gpio_getpull
+ *
+ * Read the state of the pull-up on a given pin
+ *
+ * return:
+ *      < 0 => error code
+ *        0 => enabled
+ *        1 => disabled
+*/
+
+extern int s3c2410_gpio_getpull(unsigned int pin);
+
+extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
+
+extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
+
+extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg);
+
+#ifdef CONFIG_CPU_S3C2440
+
+extern int s3c2440_set_dsc(unsigned int pin, unsigned int value);
+
+#endif /* CONFIG_CPU_S3C2440 */
+
+#ifdef CONFIG_CPU_S3C2412
+
+extern int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state);
+
+#endif /* CONFIG_CPU_S3C2412 */
+
+#endif /* __ASSEMBLY__ */
+
+#include <asm/sizes.h>
+#include <mach/map.h>
+
+/* machine specific hardware definitions should go after this */
+
+/* currently here until moved into config (todo) */
+#define CONFIG_NO_MULTIWORD_IO
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/idle.h b/arch/arm/mach-s3c2410/include/mach/idle.h
new file mode 100644
index 000000000000..e9ddd706b16e
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/idle.h
@@ -0,0 +1,24 @@
+/* arch/arm/mach-s3c2410/include/mach/idle.h
+ *
+ * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
+ *              http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 CPU Idle controls
+*/
+
+#ifndef __ASM_ARCH_IDLE_H
+#define __ASM_ARCH_IDLE_H __FILE__
+
+/* This allows the over-ride of the default idle code, in case there
+ * is any other things to be done over idle (like DVS)
+*/
+
+extern void (*s3c24xx_idle)(void);
+
+extern void s3c24xx_default_idle(void);
+
+#endif /* __ASM_ARCH_IDLE_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/io.h b/arch/arm/mach-s3c2410/include/mach/io.h
new file mode 100644
index 000000000000..9813dbf2ae4f
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/io.h
@@ -0,0 +1,218 @@
+/*
+ * arch/arm/mach-s3c2410/include/mach/io.h
+ *  from arch/arm/mach-rpc/include/mach/io.h
+ *
+ * Copyright (C) 1997 Russell King
+ *           (C) 2003 Simtec Electronics
+*/
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#include <mach/hardware.h>
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * We use two different types of addressing - PC style addresses, and ARM
+ * addresses.  PC style accesses the PC hardware with the normal PC IO
+ * addresses, eg 0x3f8 for serial#1.  ARM addresses are above A28
+ * and are translated to the start of IO.  Note that all addresses are
+ * not shifted left!
+ */
+
+#define __PORT_PCIO(x)  ((x) < (1<<28))
+
+#define PCIO_BASE        (S3C24XX_VA_ISA_WORD)
+#define PCIO_BASE_b      (S3C24XX_VA_ISA_BYTE)
+#define PCIO_BASE_w      (S3C24XX_VA_ISA_WORD)
+#define PCIO_BASE_l      (S3C24XX_VA_ISA_WORD)
+/*
+ * Dynamic IO functions - let the compiler
+ * optimize the expressions
+ */
+
+#define DECLARE_DYN_OUT(sz,fnsuffix,instr) \
+static inline void __out##fnsuffix (unsigned int val, unsigned int port) \
+{ \
+        unsigned long temp;                                   \
+        __asm__ __volatile__(                                 \
+        "cmp    %2, #(1<<28)\n\t"                             \
+        "mov    %0, %2\n\t"                                   \
+        "addcc  %0, %0, %3\n\t"                               \
+        "str" instr " %1, [%0, #0 ]     @ out" #fnsuffix      \
+        : "=&r" (temp)                                        \
+        : "r" (val), "r" (port), "Ir" (PCIO_BASE_##fnsuffix)  \
+        : "cc");                                              \
+}
+
+
+#define DECLARE_DYN_IN(sz,fnsuffix,instr)                               \
+static inline unsigned sz __in##fnsuffix (unsigned int port)            \
+{                                                                       \
+        unsigned long temp, value;                                      \
+        __asm__ __volatile__(                                           \
+        "cmp    %2, #(1<<28)\n\t"                                       \
+        "mov    %0, %2\n\t"                                             \
+        "addcc  %0, %0, %3\n\t"                                         \
+        "ldr" instr "   %1, [%0, #0 ]   @ in" #fnsuffix         \
+        : "=&r" (temp), "=r" (value)                                    \
+        : "r" (port), "Ir" (PCIO_BASE_##fnsuffix)       \
+        : "cc");                                                        \
+        return (unsigned sz)value;                                      \
+}
+
+static inline void __iomem *__ioaddr (unsigned long port)
+{
+        return __PORT_PCIO(port) ? (PCIO_BASE + port) : (void __iomem *)port;
+}
+
+#define DECLARE_IO(sz,fnsuffix,instr)   \
+        DECLARE_DYN_IN(sz,fnsuffix,instr) \
+        DECLARE_DYN_OUT(sz,fnsuffix,instr)
+
+DECLARE_IO(char,b,"b")
+DECLARE_IO(short,w,"h")
+DECLARE_IO(int,l,"")
+
+#undef DECLARE_IO
+#undef DECLARE_DYN_IN
+
+/*
+ * Constant address IO functions
+ *
+ * These have to be macros for the 'J' constraint to work -
+ * +/-4096 immediate operand.
+ */
+#define __outbc(value,port)                                             \
+({                                                                      \
+        if (__PORT_PCIO((port)))                                        \
+                __asm__ __volatile__(                                   \
+                "strb   %0, [%1, %2]    @ outbc"                        \
+                : : "r" (value), "r" (PCIO_BASE), "Jr" ((port)));       \
+        else                                                            \
+                __asm__ __volatile__(                                   \
+                "strb   %0, [%1, #0]    @ outbc"                        \
+                : : "r" (value), "r" ((port)));                         \
+})
+
+#define __inbc(port)                                                    \
+({                                                                      \
+        unsigned char result;                                           \
+        if (__PORT_PCIO((port)))                                        \
+                __asm__ __volatile__(                                   \
+                "ldrb   %0, [%1, %2]    @ inbc"                         \
+                : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port)));      \
+        else                                                            \
+                __asm__ __volatile__(                                   \
+                "ldrb   %0, [%1, #0]    @ inbc"                         \
+                : "=r" (result) : "r" ((port)));                        \
+        result;                                                         \
+})
+
+#define __outwc(value,port)                                             \
+({                                                                      \
+        unsigned long v = value;                                        \
+        if (__PORT_PCIO((port))) {                                      \
+                if ((port) < 256 && (port) > -256)                      \
+                        __asm__ __volatile__(                           \
+                        "strh   %0, [%1, %2]    @ outwc"                \
+                        : : "r" (v), "r" (PCIO_BASE), "Jr" ((port)));   \
+                else if ((port) > 0)                                    \
+                        __asm__ __volatile__(                           \
+                        "strh   %0, [%1, %2]    @ outwc"                \
+                        : : "r" (v),                                    \
+                            "r" (PCIO_BASE + ((port) & ~0xff)),         \
+                             "Jr" (((port) & 0xff)));                   \
+                else                                                    \
+                        __asm__ __volatile__(                           \
+                        "strh   %0, [%1, #0]    @ outwc"                \
+                        : : "r" (v),                                    \
+                            "r" (PCIO_BASE + (port)));                  \
+        } else                                                          \
+                __asm__ __volatile__(                                   \
+                "strh   %0, [%1, #0]    @ outwc"                        \
+                : : "r" (v), "r" ((port)));                             \
+})
+
+#define __inwc(port)                                                    \
+({                                                                      \
+        unsigned short result;                                          \
+        if (__PORT_PCIO((port))) {                                      \
+                if ((port) < 256 && (port) > -256 )                     \
+                        __asm__ __volatile__(                           \
+                        "ldrh   %0, [%1, %2]    @ inwc"                 \
+                        : "=r" (result)                                 \
+                        : "r" (PCIO_BASE),                              \
+                          "Jr" ((port)));                               \
+                else if ((port) > 0)                                    \
+                        __asm__ __volatile__(                           \
+                        "ldrh   %0, [%1, %2]    @ inwc"                 \
+                        : "=r" (result)                                 \
+                        : "r" (PCIO_BASE + ((port) & ~0xff)),           \
+                          "Jr" (((port) & 0xff)));                      \
+                else                                                    \
+                        __asm__ __volatile__(                           \
+                        "ldrh   %0, [%1, #0]    @ inwc"                 \
+                        : "=r" (result)                                 \
+                        : "r" (PCIO_BASE + ((port))));                  \
+        } else                                                          \
+                __asm__ __volatile__(                                   \
+                "ldrh   %0, [%1, #0]    @ inwc"                         \
+                : "=r" (result) : "r" ((port)));                        \
+        result;                                                         \
+})
+
+#define __outlc(value,port)                                             \
+({                                                                      \
+        unsigned long v = value;                                        \
+        if (__PORT_PCIO((port)))                                        \
+                __asm__ __volatile__(                                   \
+                "str    %0, [%1, %2]    @ outlc"                        \
+                : : "r" (v), "r" (PCIO_BASE), "Jr" ((port)));   \
+        else                                                            \
+                __asm__ __volatile__(                                   \
+                "str    %0, [%1, #0]    @ outlc"                        \
+                : : "r" (v), "r" ((port)));             \
+})
+
+#define __inlc(port)                                                    \
+({                                                                      \
+        unsigned long result;                                           \
+        if (__PORT_PCIO((port)))                                        \
+                __asm__ __volatile__(                                   \
+                "ldr    %0, [%1, %2]    @ inlc"                         \
+                : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port)));      \
+        else                                                            \
+                __asm__ __volatile__(                                   \
+                "ldr    %0, [%1, #0]    @ inlc"                         \
+                : "=r" (result) : "r" ((port)));                \
+        result;                                                         \
+})
+
+#define __ioaddrc(port) ((__PORT_PCIO(port) ? PCIO_BASE + (port) : (void __iomem *)(port)))
+
+#define inb(p)          (__builtin_constant_p((p)) ? __inbc(p)     : __inb(p))
+#define inw(p)          (__builtin_constant_p((p)) ? __inwc(p)     : __inw(p))
+#define inl(p)          (__builtin_constant_p((p)) ? __inlc(p)     : __inl(p))
+#define outb(v,p)       (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p))
+#define outw(v,p)       (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p))
+#define outl(v,p)       (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p))
+#define __ioaddr(p)     (__builtin_constant_p((p)) ? __ioaddr(p)  : __ioaddrc(p))
+/* the following macro is deprecated */
+#define ioaddr(port)    __ioaddr((port))
+
+#define insb(p,d,l)     __raw_readsb(__ioaddr(p),d,l)
+#define insw(p,d,l)     __raw_readsw(__ioaddr(p),d,l)
+#define insl(p,d,l)     __raw_readsl(__ioaddr(p),d,l)
+
+#define outsb(p,d,l)    __raw_writesb(__ioaddr(p),d,l)
+#define outsw(p,d,l)    __raw_writesw(__ioaddr(p),d,l)
+#define outsl(p,d,l)    __raw_writesl(__ioaddr(p),d,l)
+
+/*
+ * 1:1 mapping for ioremapped regions.
+ */
+#define __mem_pci(x)    (x)
+
+#endif
diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c2410/include/mach/irqs.h
new file mode 100644
index 000000000000..950c71bf1489
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/irqs.h
@@ -0,0 +1,166 @@
+/* arch/arm/mach-s3c2410/include/mach/irqs.h
+ *
+ * Copyright (c) 2003-2005 Simtec Electronics
+ *   Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H __FILE__
+
+#ifndef __ASM_ARM_IRQ_H
+#error "Do not include this directly, instead #include <asm/irq.h>"
+#endif
+
+/* we keep the first set of CPU IRQs out of the range of
+ * the ISA space, so that the PC104 has them to itself
+ * and we don't end up having to do horrible things to the
+ * standard ISA drivers....
+ */
+
+#define S3C2410_CPUIRQ_OFFSET    (16)
+
+#define S3C2410_IRQ(x) ((x) + S3C2410_CPUIRQ_OFFSET)
+
+/* main cpu interrupts */
+#define IRQ_EINT0      S3C2410_IRQ(0)       /* 16 */
+#define IRQ_EINT1      S3C2410_IRQ(1)
+#define IRQ_EINT2      S3C2410_IRQ(2)
+#define IRQ_EINT3      S3C2410_IRQ(3)
+#define IRQ_EINT4t7    S3C2410_IRQ(4)       /* 20 */
+#define IRQ_EINT8t23   S3C2410_IRQ(5)
+#define IRQ_RESERVED6  S3C2410_IRQ(6)       /* for s3c2410 */
+#define IRQ_CAM        S3C2410_IRQ(6)       /* for s3c2440,s3c2443 */
+#define IRQ_BATT_FLT   S3C2410_IRQ(7)
+#define IRQ_TICK       S3C2410_IRQ(8)       /* 24 */
+#define IRQ_WDT        S3C2410_IRQ(9)       /* WDT/AC97 for s3c2443 */
+#define IRQ_TIMER0     S3C2410_IRQ(10)
+#define IRQ_TIMER1     S3C2410_IRQ(11)
+#define IRQ_TIMER2     S3C2410_IRQ(12)
+#define IRQ_TIMER3     S3C2410_IRQ(13)
+#define IRQ_TIMER4     S3C2410_IRQ(14)
+#define IRQ_UART2      S3C2410_IRQ(15)
+#define IRQ_LCD        S3C2410_IRQ(16)      /* 32 */
+#define IRQ_DMA0       S3C2410_IRQ(17)      /* IRQ_DMA for s3c2443 */
+#define IRQ_DMA1       S3C2410_IRQ(18)
+#define IRQ_DMA2       S3C2410_IRQ(19)
+#define IRQ_DMA3       S3C2410_IRQ(20)
+#define IRQ_SDI        S3C2410_IRQ(21)
+#define IRQ_SPI0       S3C2410_IRQ(22)
+#define IRQ_UART1      S3C2410_IRQ(23)
+#define IRQ_RESERVED24 S3C2410_IRQ(24)      /* 40 */
+#define IRQ_NFCON      S3C2410_IRQ(24)      /* for s3c2440 */
+#define IRQ_USBD       S3C2410_IRQ(25)
+#define IRQ_USBH       S3C2410_IRQ(26)
+#define IRQ_IIC        S3C2410_IRQ(27)
+#define IRQ_UART0      S3C2410_IRQ(28)      /* 44 */
+#define IRQ_SPI1       S3C2410_IRQ(29)
+#define IRQ_RTC        S3C2410_IRQ(30)
+#define IRQ_ADCPARENT  S3C2410_IRQ(31)
+
+/* interrupts generated from the external interrupts sources */
+#define IRQ_EINT4      S3C2410_IRQ(32)     /* 48 */
+#define IRQ_EINT5      S3C2410_IRQ(33)
+#define IRQ_EINT6      S3C2410_IRQ(34)
+#define IRQ_EINT7      S3C2410_IRQ(35)
+#define IRQ_EINT8      S3C2410_IRQ(36)
+#define IRQ_EINT9      S3C2410_IRQ(37)
+#define IRQ_EINT10     S3C2410_IRQ(38)
+#define IRQ_EINT11     S3C2410_IRQ(39)
+#define IRQ_EINT12     S3C2410_IRQ(40)
+#define IRQ_EINT13     S3C2410_IRQ(41)
+#define IRQ_EINT14     S3C2410_IRQ(42)
+#define IRQ_EINT15     S3C2410_IRQ(43)
+#define IRQ_EINT16     S3C2410_IRQ(44)
+#define IRQ_EINT17     S3C2410_IRQ(45)
+#define IRQ_EINT18     S3C2410_IRQ(46)
+#define IRQ_EINT19     S3C2410_IRQ(47)
+#define IRQ_EINT20     S3C2410_IRQ(48)     /* 64 */
+#define IRQ_EINT21     S3C2410_IRQ(49)
+#define IRQ_EINT22     S3C2410_IRQ(50)
+#define IRQ_EINT23     S3C2410_IRQ(51)
+
+
+#define IRQ_EINT(x)    (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x)))
+
+#define IRQ_LCD_FIFO   S3C2410_IRQ(52)
+#define IRQ_LCD_FRAME  S3C2410_IRQ(53)
+
+/* IRQs for the interal UARTs, and ADC
+ * these need to be ordered in number of appearance in the
+ * SUBSRC mask register
+*/
+
+#define S3C2410_IRQSUB(x)       S3C2410_IRQ((x)+54)
+
+#define IRQ_S3CUART_RX0         S3C2410_IRQSUB(0)       /* 70 */
+#define IRQ_S3CUART_TX0         S3C2410_IRQSUB(1)
+#define IRQ_S3CUART_ERR0        S3C2410_IRQSUB(2)
+
+#define IRQ_S3CUART_RX1         S3C2410_IRQSUB(3)       /* 73 */
+#define IRQ_S3CUART_TX1         S3C2410_IRQSUB(4)
+#define IRQ_S3CUART_ERR1        S3C2410_IRQSUB(5)
+
+#define IRQ_S3CUART_RX2         S3C2410_IRQSUB(6)       /* 76 */
+#define IRQ_S3CUART_TX2         S3C2410_IRQSUB(7)
+#define IRQ_S3CUART_ERR2        S3C2410_IRQSUB(8)
+
+#define IRQ_TC                  S3C2410_IRQSUB(9)
+#define IRQ_ADC                 S3C2410_IRQSUB(10)
+
+/* extra irqs for s3c2412 */
+
+#define IRQ_S3C2412_CFSDI       S3C2410_IRQ(21)
+
+#define IRQ_S3C2412_SDI         S3C2410_IRQSUB(13)
+#define IRQ_S3C2412_CF          S3C2410_IRQSUB(14)
+
+/* extra irqs for s3c2440 */
+
+#define IRQ_S3C2440_CAM_C       S3C2410_IRQSUB(11)      /* S3C2443 too */
+#define IRQ_S3C2440_CAM_P       S3C2410_IRQSUB(12)      /* S3C2443 too */
+#define IRQ_S3C2440_WDT         S3C2410_IRQSUB(13)
+#define IRQ_S3C2440_AC97        S3C2410_IRQSUB(14)
+
+/* irqs for s3c2443 */
+
+#define IRQ_S3C2443_DMA         S3C2410_IRQ(17)         /* IRQ_DMA1 */
+#define IRQ_S3C2443_UART3       S3C2410_IRQ(18)         /* IRQ_DMA2 */
+#define IRQ_S3C2443_CFCON       S3C2410_IRQ(19)         /* IRQ_DMA3 */
+#define IRQ_S3C2443_HSMMC       S3C2410_IRQ(20)         /* IRQ_SDI */
+#define IRQ_S3C2443_NAND        S3C2410_IRQ(24)         /* reserved */
+
+#define IRQ_S3C2443_LCD1        S3C2410_IRQSUB(14)
+#define IRQ_S3C2443_LCD2        S3C2410_IRQSUB(15)
+#define IRQ_S3C2443_LCD3        S3C2410_IRQSUB(16)
+#define IRQ_S3C2443_LCD4        S3C2410_IRQSUB(17)
+
+#define IRQ_S3C2443_DMA0        S3C2410_IRQSUB(18)
+#define IRQ_S3C2443_DMA1        S3C2410_IRQSUB(19)
+#define IRQ_S3C2443_DMA2        S3C2410_IRQSUB(20)
+#define IRQ_S3C2443_DMA3        S3C2410_IRQSUB(21)
+#define IRQ_S3C2443_DMA4        S3C2410_IRQSUB(22)
+#define IRQ_S3C2443_DMA5        S3C2410_IRQSUB(23)
+
+/* UART3 */
+#define IRQ_S3C2443_RX3         S3C2410_IRQSUB(24)
+#define IRQ_S3C2443_TX3         S3C2410_IRQSUB(25)
+#define IRQ_S3C2443_ERR3        S3C2410_IRQSUB(26)
+
+#define IRQ_S3C2443_WDT         S3C2410_IRQSUB(27)
+#define IRQ_S3C2443_AC97        S3C2410_IRQSUB(28)
+
+#ifdef CONFIG_CPU_S3C2443
+#define NR_IRQS (IRQ_S3C2443_AC97+1)
+#else
+#define NR_IRQS (IRQ_S3C2440_AC97+1)
+#endif
+
+/* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */
+#define FIQ_START               IRQ_EINT0
+
+#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/leds-gpio.h b/arch/arm/mach-s3c2410/include/mach/leds-gpio.h
new file mode 100644
index 000000000000..d8a7672519b6
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/leds-gpio.h
@@ -0,0 +1,28 @@
+/* arch/arm/mach-s3c2410/include/mach/leds-gpio.h
+ *
+ * Copyright (c) 2006 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24XX - LEDs GPIO connector
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_LEDSGPIO_H
+#define __ASM_ARCH_LEDSGPIO_H "leds-gpio.h"
+
+#define S3C24XX_LEDF_ACTLOW     (1<<0)          /* LED is on when GPIO low */
+#define S3C24XX_LEDF_TRISTATE   (1<<1)          /* tristate to turn off */
+
+struct s3c24xx_led_platdata {
+        unsigned int             gpio;
+        unsigned int             flags;
+
+        char                    *name;
+        char                    *def_trigger;
+};
+
+#endif /* __ASM_ARCH_LEDSGPIO_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h
new file mode 100644
index 000000000000..64bf7e94a5bf
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/map.h
@@ -0,0 +1,178 @@
+/* arch/arm/mach-s3c2410/include/mach/map.h
+ *
+ * Copyright (c) 2003 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_MAP_H
+#define __ASM_ARCH_MAP_H
+
+#include <asm/plat-s3c/map.h>
+
+#define S3C2410_ADDR(x)         S3C_ADDR(x)
+
+/* interrupt controller is the first thing we put in, to make
+ * the assembly code for the irq detection easier
+ */
+#define S3C24XX_VA_IRQ     S3C_VA_IRQ
+#define S3C2410_PA_IRQ     (0x4A000000)
+#define S3C24XX_SZ_IRQ     SZ_1M
+
+/* memory controller registers */
+#define S3C24XX_VA_MEMCTRL S3C_VA_MEM
+#define S3C2410_PA_MEMCTRL (0x48000000)
+#define S3C24XX_SZ_MEMCTRL SZ_1M
+
+/* USB host controller */
+#define S3C2410_PA_USBHOST (0x49000000)
+#define S3C24XX_SZ_USBHOST SZ_1M
+
+/* DMA controller */
+#define S3C2410_PA_DMA     (0x4B000000)
+#define S3C24XX_SZ_DMA     SZ_1M
+
+/* Clock and Power management */
+#define S3C24XX_VA_CLKPWR  S3C_VA_SYS
+#define S3C2410_PA_CLKPWR  (0x4C000000)
+#define S3C24XX_SZ_CLKPWR  SZ_1M
+
+/* LCD controller */
+#define S3C2410_PA_LCD     (0x4D000000)
+#define S3C24XX_SZ_LCD     SZ_1M
+
+/* NAND flash controller */
+#define S3C2410_PA_NAND    (0x4E000000)
+#define S3C24XX_SZ_NAND    SZ_1M
+
+/* UARTs */
+#define S3C24XX_VA_UART    S3C_VA_UART
+#define S3C2410_PA_UART    (0x50000000)
+#define S3C24XX_SZ_UART    SZ_1M
+
+/* Timers */
+#define S3C24XX_VA_TIMER   S3C_VA_TIMER
+#define S3C2410_PA_TIMER   (0x51000000)
+#define S3C24XX_SZ_TIMER   SZ_1M
+
+/* USB Device port */
+#define S3C2410_PA_USBDEV  (0x52000000)
+#define S3C24XX_SZ_USBDEV  SZ_1M
+
+/* Watchdog */
+#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG
+#define S3C2410_PA_WATCHDOG (0x53000000)
+#define S3C24XX_SZ_WATCHDOG SZ_1M
+
+/* IIC hardware controller */
+#define S3C2410_PA_IIC     (0x54000000)
+#define S3C24XX_SZ_IIC     SZ_1M
+
+/* IIS controller */
+#define S3C2410_PA_IIS     (0x55000000)
+#define S3C24XX_SZ_IIS     SZ_1M
+
+/* GPIO ports */
+
+/* the calculation for the VA of this must ensure that
+ * it is the same distance apart from the UART in the
+ * phsyical address space, as the initial mapping for the IO
+ * is done as a 1:1 maping. This puts it (currently) at
+ * 0xFA800000, which is not in the way of any current mapping
+ * by the base system.
+*/
+
+#define S3C2410_PA_GPIO    (0x56000000)
+#define S3C24XX_VA_GPIO    ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
+#define S3C24XX_SZ_GPIO    SZ_1M
+
+/* RTC */
+#define S3C2410_PA_RTC     (0x57000000)
+#define S3C24XX_SZ_RTC     SZ_1M
+
+/* ADC */
+#define S3C2410_PA_ADC     (0x58000000)
+#define S3C24XX_SZ_ADC     SZ_1M
+
+/* SPI */
+#define S3C2410_PA_SPI     (0x59000000)
+#define S3C24XX_SZ_SPI     SZ_1M
+
+/* SDI */
+#define S3C2410_PA_SDI     (0x5A000000)
+#define S3C24XX_SZ_SDI     SZ_1M
+
+/* CAMIF */
+#define S3C2440_PA_CAMIF   (0x4F000000)
+#define S3C2440_SZ_CAMIF   SZ_1M
+
+/* AC97 */
+
+#define S3C2440_PA_AC97    (0x5B000000)
+#define S3C2440_SZ_AC97    SZ_1M
+
+/* S3C2443 High-speed SD/MMC */
+#define S3C2443_PA_HSMMC   (0x4A800000)
+#define S3C2443_SZ_HSMMC   (256)
+
+/* ISA style IO, for each machine to sort out mappings for, if it
+ * implements it. We reserve two 16M regions for ISA.
+ */
+
+#define S3C24XX_VA_ISA_WORD  S3C2410_ADDR(0x02000000)
+#define S3C24XX_VA_ISA_BYTE  S3C2410_ADDR(0x03000000)
+
+/* physical addresses of all the chip-select areas */
+
+#define S3C2410_CS0 (0x00000000)
+#define S3C2410_CS1 (0x08000000)
+#define S3C2410_CS2 (0x10000000)
+#define S3C2410_CS3 (0x18000000)
+#define S3C2410_CS4 (0x20000000)
+#define S3C2410_CS5 (0x28000000)
+#define S3C2410_CS6 (0x30000000)
+#define S3C2410_CS7 (0x38000000)
+
+#define S3C2410_SDRAM_PA    (S3C2410_CS6)
+
+/* Use a single interface for common resources between S3C24XX cpus */
+
+#define S3C24XX_PA_IRQ      S3C2410_PA_IRQ
+#define S3C24XX_PA_MEMCTRL  S3C2410_PA_MEMCTRL
+#define S3C24XX_PA_USBHOST  S3C2410_PA_USBHOST
+#define S3C24XX_PA_DMA      S3C2410_PA_DMA
+#define S3C24XX_PA_CLKPWR   S3C2410_PA_CLKPWR
+#define S3C24XX_PA_LCD      S3C2410_PA_LCD
+#define S3C24XX_PA_UART     S3C2410_PA_UART
+#define S3C24XX_PA_TIMER    S3C2410_PA_TIMER
+#define S3C24XX_PA_USBDEV   S3C2410_PA_USBDEV
+#define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
+#define S3C24XX_PA_IIC      S3C2410_PA_IIC
+#define S3C24XX_PA_IIS      S3C2410_PA_IIS
+#define S3C24XX_PA_GPIO     S3C2410_PA_GPIO
+#define S3C24XX_PA_RTC      S3C2410_PA_RTC
+#define S3C24XX_PA_ADC      S3C2410_PA_ADC
+#define S3C24XX_PA_SPI      S3C2410_PA_SPI
+
+/* deal with the registers that move under the 2412/2413 */
+
+#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
+#ifndef __ASSEMBLY__
+extern void __iomem *s3c24xx_va_gpio2;
+#endif
+#ifdef CONFIG_CPU_S3C2412_ONLY
+#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
+#else
+#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
+#endif
+#else
+#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
+#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
+#endif
+
+#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/memory.h b/arch/arm/mach-s3c2410/include/mach/memory.h
new file mode 100644
index 000000000000..93782628a786
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/memory.h
@@ -0,0 +1,19 @@
+/* arch/arm/mach-s3c2410/include/mach/memory.h
+ *  from arch/arm/mach-rpc/include/mach/memory.h
+ *
+ *  Copyright (C) 1996,1997,1998 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#define PHYS_OFFSET     UL(0x30000000)
+
+#define __virt_to_bus(x) __virt_to_phys(x)
+#define __bus_to_virt(x) __phys_to_virt(x)
+
+#endif
diff --git a/arch/arm/mach-s3c2410/include/mach/osiris-cpld.h b/arch/arm/mach-s3c2410/include/mach/osiris-cpld.h
new file mode 100644
index 000000000000..e9e36b0abbac
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/osiris-cpld.h
@@ -0,0 +1,30 @@
+/* arch/arm/mach-s3c2410/include/mach/osiris-cpld.h
+ *
+ * Copyright 2005 Simtec Electronics
+ *      http://www.simtec.co.uk/products/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * OSIRIS - CPLD control constants
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_OSIRISCPLD_H
+#define __ASM_ARCH_OSIRISCPLD_H
+
+/* CTRL0 - NAND WP control */
+
+#define OSIRIS_CTRL0_NANDSEL            (0x3)
+#define OSIRIS_CTRL0_BOOT_INT           (1<<3)
+#define OSIRIS_CTRL0_PCMCIA             (1<<4)
+#define OSIRIS_CTRL0_FIX8               (1<<5)
+#define OSIRIS_CTRL0_PCMCIA_nWAIT       (1<<6)
+#define OSIRIS_CTRL0_PCMCIA_nIOIS16     (1<<7)
+
+#define OSIRIS_CTRL1_FIX8               (1<<0)
+
+#define OSIRIS_ID_REVMASK               (0x7)
+
+#endif /* __ASM_ARCH_OSIRISCPLD_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/osiris-map.h b/arch/arm/mach-s3c2410/include/mach/osiris-map.h
new file mode 100644
index 000000000000..639eff523d4e
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/osiris-map.h
@@ -0,0 +1,42 @@
+/* arch/arm/mach-s3c2410/include/mach/osiris-map.h
+ *
+ * (c) 2005 Simtec Electronics
+ *      http://www.simtec.co.uk/products/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * OSIRIS - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* needs arch/map.h including with this */
+
+#ifndef __ASM_ARCH_OSIRISMAP_H
+#define __ASM_ARCH_OSIRISMAP_H
+
+/* start peripherals off after the S3C2410 */
+
+#define OSIRIS_IOADDR(x)        (S3C2410_ADDR((x) + 0x04000000))
+
+#define OSIRIS_PA_CPLD          (S3C2410_CS1 | (1<<26))
+
+/* we put the CPLD registers next, to get them out of the way */
+
+#define OSIRIS_VA_CTRL0         OSIRIS_IOADDR(0x00000000)
+#define OSIRIS_PA_CTRL0         (OSIRIS_PA_CPLD)
+
+#define OSIRIS_VA_CTRL1         OSIRIS_IOADDR(0x00100000)
+#define OSIRIS_PA_CTRL1         (OSIRIS_PA_CPLD + (1<<23))
+
+#define OSIRIS_VA_CTRL2         OSIRIS_IOADDR(0x00200000)
+#define OSIRIS_PA_CTRL2         (OSIRIS_PA_CPLD + (2<<23))
+
+#define OSIRIS_VA_CTRL3         OSIRIS_IOADDR(0x00300000)
+#define OSIRIS_PA_CTRL3         (OSIRIS_PA_CPLD + (2<<23))
+
+#define OSIRIS_VA_IDREG         OSIRIS_IOADDR(0x00700000)
+#define OSIRIS_PA_IDREG         (OSIRIS_PA_CPLD + (7<<23))
+
+#endif /* __ASM_ARCH_OSIRISMAP_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/otom-map.h b/arch/arm/mach-s3c2410/include/mach/otom-map.h
new file mode 100644
index 000000000000..f9277a52c145
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/otom-map.h
@@ -0,0 +1,30 @@
+/* arch/arm/mach-s3c2410/include/mach/otom-map.h
+ *
+ * (c) 2005 Guillaume GOURAT / NexVision
+ *          guillaume.gourat@nexvision.fr
+ *
+ * NexVision OTOM board memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* needs arch/map.h including with this */
+
+/* ok, we've used up to 0x01300000, now we need to find space for the
+ * peripherals that live in the nGCS[x] areas, which are quite numerous
+ * in their space.
+ */
+
+#ifndef __ASM_ARCH_OTOMMAP_H
+#define __ASM_ARCH_OTOMMAP_H
+
+#define OTOM_PA_CS8900A_BASE       (S3C2410_CS3 + 0x01000000)   /* nGCS3 +0x01000000 */
+#define OTOM_VA_CS8900A_BASE       S3C2410_ADDR(0x04000000)             /* 0xF4000000 */
+
+/* physical offset addresses for the peripherals */
+
+#define OTOM_PA_FLASH0_BASE        (S3C2410_CS0)                                /* Bank 0 */
+
+#endif /* __ASM_ARCH_OTOMMAP_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-clock.h
new file mode 100644
index 000000000000..d583688458a4
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/regs-clock.h
@@ -0,0 +1,197 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-clock.h
+ *
+ * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk>
+ *                    http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 clock register definitions
+*/
+
+#ifndef __ASM_ARM_REGS_CLOCK
+#define __ASM_ARM_REGS_CLOCK "$Id: clock.h,v 1.4 2003/04/30 14:50:51 ben Exp $"
+
+#define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
+
+#define S3C2410_PLLVAL(_m,_p,_s) ((_m) << 12 | ((_p) << 4) | ((_s)))
+
+#define S3C2410_LOCKTIME    S3C2410_CLKREG(0x00)
+#define S3C2410_MPLLCON     S3C2410_CLKREG(0x04)
+#define S3C2410_UPLLCON     S3C2410_CLKREG(0x08)
+#define S3C2410_CLKCON      S3C2410_CLKREG(0x0C)
+#define S3C2410_CLKSLOW     S3C2410_CLKREG(0x10)
+#define S3C2410_CLKDIVN     S3C2410_CLKREG(0x14)
+
+#define S3C2410_CLKCON_IDLE          (1<<2)
+#define S3C2410_CLKCON_POWER         (1<<3)
+#define S3C2410_CLKCON_NAND          (1<<4)
+#define S3C2410_CLKCON_LCDC          (1<<5)
+#define S3C2410_CLKCON_USBH          (1<<6)
+#define S3C2410_CLKCON_USBD          (1<<7)
+#define S3C2410_CLKCON_PWMT          (1<<8)
+#define S3C2410_CLKCON_SDI           (1<<9)
+#define S3C2410_CLKCON_UART0         (1<<10)
+#define S3C2410_CLKCON_UART1         (1<<11)
+#define S3C2410_CLKCON_UART2         (1<<12)
+#define S3C2410_CLKCON_GPIO          (1<<13)
+#define S3C2410_CLKCON_RTC           (1<<14)
+#define S3C2410_CLKCON_ADC           (1<<15)
+#define S3C2410_CLKCON_IIC           (1<<16)
+#define S3C2410_CLKCON_IIS           (1<<17)
+#define S3C2410_CLKCON_SPI           (1<<18)
+
+#define S3C2410_PLLCON_MDIVSHIFT     12
+#define S3C2410_PLLCON_PDIVSHIFT     4
+#define S3C2410_PLLCON_SDIVSHIFT     0
+#define S3C2410_PLLCON_MDIVMASK      ((1<<(1+(19-12)))-1)
+#define S3C2410_PLLCON_PDIVMASK      ((1<<5)-1)
+#define S3C2410_PLLCON_SDIVMASK      3
+
+/* DCLKCON register addresses in gpio.h */
+
+#define S3C2410_DCLKCON_DCLK0EN      (1<<0)
+#define S3C2410_DCLKCON_DCLK0_PCLK   (0<<1)
+#define S3C2410_DCLKCON_DCLK0_UCLK   (1<<1)
+#define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4)
+#define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8)
+#define S3C2410_DCLKCON_DCLK0_DIV_MASK ((0xf)<<4)
+#define S3C2410_DCLKCON_DCLK0_CMP_MASK ((0xf)<<8)
+
+#define S3C2410_DCLKCON_DCLK1EN      (1<<16)
+#define S3C2410_DCLKCON_DCLK1_PCLK   (0<<17)
+#define S3C2410_DCLKCON_DCLK1_UCLK   (1<<17)
+#define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20)
+#define S3C2410_DCLKCON_DCLK1_CMP(x) (((x) - 1) <<24)
+#define S3C2410_DCLKCON_DCLK1_DIV_MASK ((0xf) <<20)
+#define S3C2410_DCLKCON_DCLK1_CMP_MASK ((0xf) <<24)
+
+#define S3C2410_CLKDIVN_PDIVN        (1<<0)
+#define S3C2410_CLKDIVN_HDIVN        (1<<1)
+
+#define S3C2410_CLKSLOW_UCLK_OFF        (1<<7)
+#define S3C2410_CLKSLOW_MPLL_OFF        (1<<5)
+#define S3C2410_CLKSLOW_SLOW            (1<<4)
+#define S3C2410_CLKSLOW_SLOWVAL(x)      (x)
+#define S3C2410_CLKSLOW_GET_SLOWVAL(x)  ((x) & 7)
+
+#ifndef __ASSEMBLY__
+
+#include <asm/div64.h>
+
+static inline unsigned int
+s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
+{
+        unsigned int mdiv, pdiv, sdiv;
+        uint64_t fvco;
+
+        mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT;
+        pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT;
+        sdiv = pllval >> S3C2410_PLLCON_SDIVSHIFT;
+
+        mdiv &= S3C2410_PLLCON_MDIVMASK;
+        pdiv &= S3C2410_PLLCON_PDIVMASK;
+        sdiv &= S3C2410_PLLCON_SDIVMASK;
+
+        fvco = (uint64_t)baseclk * (mdiv + 8);
+        do_div(fvco, (pdiv + 2) << sdiv);
+
+        return (unsigned int)fvco;
+}
+
+#endif /* __ASSEMBLY__ */
+
+#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
+
+/* extra registers */
+#define S3C2440_CAMDIVN     S3C2410_CLKREG(0x18)
+
+#define S3C2440_CLKCON_CAMERA        (1<<19)
+#define S3C2440_CLKCON_AC97          (1<<20)
+
+#define S3C2440_CLKDIVN_PDIVN        (1<<0)
+#define S3C2440_CLKDIVN_HDIVN_MASK   (3<<1)
+#define S3C2440_CLKDIVN_HDIVN_1      (0<<1)
+#define S3C2440_CLKDIVN_HDIVN_2      (1<<1)
+#define S3C2440_CLKDIVN_HDIVN_4_8    (2<<1)
+#define S3C2440_CLKDIVN_HDIVN_3_6    (3<<1)
+#define S3C2440_CLKDIVN_UCLK         (1<<3)
+
+#define S3C2440_CAMDIVN_CAMCLK_MASK  (0xf<<0)
+#define S3C2440_CAMDIVN_CAMCLK_SEL   (1<<4)
+#define S3C2440_CAMDIVN_HCLK3_HALF   (1<<8)
+#define S3C2440_CAMDIVN_HCLK4_HALF   (1<<9)
+#define S3C2440_CAMDIVN_DVSEN        (1<<12)
+
+#define S3C2442_CAMDIVN_CAMCLK_DIV3  (1<<5)
+
+#endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */
+
+#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
+
+#define S3C2412_OSCSET          S3C2410_CLKREG(0x18)
+#define S3C2412_CLKSRC          S3C2410_CLKREG(0x1C)
+
+#define S3C2412_PLLCON_OFF              (1<<20)
+
+#define S3C2412_CLKDIVN_PDIVN           (1<<2)
+#define S3C2412_CLKDIVN_HDIVN_MASK      (3<<0)
+#define S3C2412_CLKDIVN_ARMDIVN         (1<<3)
+#define S3C2412_CLKDIVN_DVSEN           (1<<4)
+#define S3C2412_CLKDIVN_HALFHCLK        (1<<5)
+#define S3C2412_CLKDIVN_USB48DIV        (1<<6)
+#define S3C2412_CLKDIVN_UARTDIV_MASK    (15<<8)
+#define S3C2412_CLKDIVN_UARTDIV_SHIFT   (8)
+#define S3C2412_CLKDIVN_I2SDIV_MASK     (15<<12)
+#define S3C2412_CLKDIVN_I2SDIV_SHIFT    (12)
+#define S3C2412_CLKDIVN_CAMDIV_MASK     (15<<16)
+#define S3C2412_CLKDIVN_CAMDIV_SHIFT    (16)
+
+#define S3C2412_CLKCON_WDT              (1<<28)
+#define S3C2412_CLKCON_SPI              (1<<27)
+#define S3C2412_CLKCON_IIS              (1<<26)
+#define S3C2412_CLKCON_IIC              (1<<25)
+#define S3C2412_CLKCON_ADC              (1<<24)
+#define S3C2412_CLKCON_RTC              (1<<23)
+#define S3C2412_CLKCON_GPIO             (1<<22)
+#define S3C2412_CLKCON_UART2            (1<<21)
+#define S3C2412_CLKCON_UART1            (1<<20)
+#define S3C2412_CLKCON_UART0            (1<<19)
+#define S3C2412_CLKCON_SDI              (1<<18)
+#define S3C2412_CLKCON_PWMT             (1<<17)
+#define S3C2412_CLKCON_USBD             (1<<16)
+#define S3C2412_CLKCON_CAMCLK           (1<<15)
+#define S3C2412_CLKCON_UARTCLK          (1<<14)
+/* missing 13 */
+#define S3C2412_CLKCON_USB_HOST48       (1<<12)
+#define S3C2412_CLKCON_USB_DEV48        (1<<11)
+#define S3C2412_CLKCON_HCLKdiv2         (1<<10)
+#define S3C2412_CLKCON_HCLKx2           (1<<9)
+#define S3C2412_CLKCON_SDRAM            (1<<8)
+/* missing 7 */
+#define S3C2412_CLKCON_USBH             S3C2410_CLKCON_USBH
+#define S3C2412_CLKCON_LCDC             S3C2410_CLKCON_LCDC
+#define S3C2412_CLKCON_NAND             S3C2410_CLKCON_NAND
+#define S3C2412_CLKCON_DMA3             (1<<3)
+#define S3C2412_CLKCON_DMA2             (1<<2)
+#define S3C2412_CLKCON_DMA1             (1<<1)
+#define S3C2412_CLKCON_DMA0             (1<<0)
+
+/* clock sourec controls */
+
+#define S3C2412_CLKSRC_EXTCLKDIV_MASK           (7 << 0)
+#define S3C2412_CLKSRC_EXTCLKDIV_SHIFT          (0)
+#define S3C2412_CLKSRC_MDIVCLK_EXTCLKDIV        (1<<3)
+#define S3C2412_CLKSRC_MSYSCLK_MPLL             (1<<4)
+#define S3C2412_CLKSRC_USYSCLK_UPLL             (1<<5)
+#define S3C2412_CLKSRC_UARTCLK_MPLL             (1<<8)
+#define S3C2412_CLKSRC_I2SCLK_MPLL              (1<<9)
+#define S3C2412_CLKSRC_USBCLK_HCLK              (1<<10)
+#define S3C2412_CLKSRC_CAMCLK_HCLK              (1<<11)
+#define S3C2412_CLKSRC_UREFCLK_EXTCLK   (1<<12)
+#define S3C2412_CLKSRC_EREFCLK_EXTCLK   (1<<14)
+
+#endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */
+
+#endif /* __ASM_ARM_REGS_CLOCK */
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-dsc.h b/arch/arm/mach-s3c2410/include/mach/regs-dsc.h
new file mode 100644
index 000000000000..3c3853cd3cf7
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/regs-dsc.h
@@ -0,0 +1,184 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-dsc.h
+ *
+ * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
+ *                    http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2440/S3C2412 Signal Drive Strength Control
+*/
+
+
+#ifndef __ASM_ARCH_REGS_DSC_H
+#define __ASM_ARCH_REGS_DSC_H "2440-dsc"
+
+#if defined(CONFIG_CPU_S3C2412)
+#define S3C2412_DSC0       S3C2410_GPIOREG(0xdc)
+#define S3C2412_DSC1       S3C2410_GPIOREG(0xe0)
+#endif
+
+#if defined(CONFIG_CPU_S3C244X)
+
+#define S3C2440_DSC0       S3C2410_GPIOREG(0xc4)
+#define S3C2440_DSC1       S3C2410_GPIOREG(0xc8)
+
+#define S3C2440_SELECT_DSC0 (0)
+#define S3C2440_SELECT_DSC1 (1<<31)
+
+#define S3C2440_DSC_GETSHIFT(x) ((x) & 31)
+
+#define S3C2440_DSC0_DISABLE    (1<<31)
+
+#define S3C2440_DSC0_ADDR       (S3C2440_SELECT_DSC0 | 8)
+#define S3C2440_DSC0_ADDR_12mA  (0<<8)
+#define S3C2440_DSC0_ADDR_10mA  (1<<8)
+#define S3C2440_DSC0_ADDR_8mA   (2<<8)
+#define S3C2440_DSC0_ADDR_6mA   (3<<8)
+#define S3C2440_DSC0_ADDR_MASK  (3<<8)
+
+/* D24..D31 */
+#define S3C2440_DSC0_DATA3      (S3C2440_SELECT_DSC0 | 6)
+#define S3C2440_DSC0_DATA3_12mA (0<<6)
+#define S3C2440_DSC0_DATA3_10mA (1<<6)
+#define S3C2440_DSC0_DATA3_8mA  (2<<6)
+#define S3C2440_DSC0_DATA3_6mA  (3<<6)
+#define S3C2440_DSC0_DATA3_MASK (3<<6)
+
+/* D16..D23 */
+#define S3C2440_DSC0_DATA2      (S3C2440_SELECT_DSC0 | 4)
+#define S3C2440_DSC0_DATA2_12mA (0<<4)
+#define S3C2440_DSC0_DATA2_10mA (1<<4)
+#define S3C2440_DSC0_DATA2_8mA  (2<<4)
+#define S3C2440_DSC0_DATA2_6mA  (3<<4)
+#define S3C2440_DSC0_DATA2_MASK (3<<4)
+
+/* D8..D15 */
+#define S3C2440_DSC0_DATA1      (S3C2440_SELECT_DSC0 | 2)
+#define S3C2440_DSC0_DATA1_12mA (0<<2)
+#define S3C2440_DSC0_DATA1_10mA (1<<2)
+#define S3C2440_DSC0_DATA1_8mA  (2<<2)
+#define S3C2440_DSC0_DATA1_6mA  (3<<2)
+#define S3C2440_DSC0_DATA1_MASK (3<<2)
+
+/* D0..D7 */
+#define S3C2440_DSC0_DATA0      (S3C2440_SELECT_DSC0 | 0)
+#define S3C2440_DSC0_DATA0_12mA (0<<0)
+#define S3C2440_DSC0_DATA0_10mA (1<<0)
+#define S3C2440_DSC0_DATA0_8mA  (2<<0)
+#define S3C2440_DSC0_DATA0_6mA  (3<<0)
+#define S3C2440_DSC0_DATA0_MASK (3<<0)
+
+#define S3C2440_DSC1_SCK1       (S3C2440_SELECT_DSC1 | 28)
+#define S3C2440_DSC1_SCK1_12mA  (0<<28)
+#define S3C2440_DSC1_SCK1_10mA  (1<<28)
+#define S3C2440_DSC1_SCK1_8mA   (2<<28)
+#define S3C2440_DSC1_SCK1_6mA   (3<<28)
+#define S3C2440_DSC1_SCK1_MASK  (3<<28)
+
+#define S3C2440_DSC1_SCK0       (S3C2440_SELECT_DSC1 | 26)
+#define S3C2440_DSC1_SCK0_12mA  (0<<26)
+#define S3C2440_DSC1_SCK0_10mA  (1<<26)
+#define S3C2440_DSC1_SCK0_8mA   (2<<26)
+#define S3C2440_DSC1_SCK0_6mA   (3<<26)
+#define S3C2440_DSC1_SCK0_MASK  (3<<26)
+
+#define S3C2440_DSC1_SCKE       (S3C2440_SELECT_DSC1 | 24)
+#define S3C2440_DSC1_SCKE_10mA  (0<<24)
+#define S3C2440_DSC1_SCKE_8mA   (1<<24)
+#define S3C2440_DSC1_SCKE_6mA   (2<<24)
+#define S3C2440_DSC1_SCKE_4mA   (3<<24)
+#define S3C2440_DSC1_SCKE_MASK  (3<<24)
+
+/* SDRAM nRAS/nCAS */
+#define S3C2440_DSC1_SDR        (S3C2440_SELECT_DSC1 | 22)
+#define S3C2440_DSC1_SDR_10mA   (0<<22)
+#define S3C2440_DSC1_SDR_8mA    (1<<22)
+#define S3C2440_DSC1_SDR_6mA    (2<<22)
+#define S3C2440_DSC1_SDR_4mA    (3<<22)
+#define S3C2440_DSC1_SDR_MASK   (3<<22)
+
+/* NAND Flash Controller */
+#define S3C2440_DSC1_NFC        (S3C2440_SELECT_DSC1 | 20)
+#define S3C2440_DSC1_NFC_10mA   (0<<20)
+#define S3C2440_DSC1_NFC_8mA    (1<<20)
+#define S3C2440_DSC1_NFC_6mA    (2<<20)
+#define S3C2440_DSC1_NFC_4mA    (3<<20)
+#define S3C2440_DSC1_NFC_MASK   (3<<20)
+
+/* nBE[0..3] */
+#define S3C2440_DSC1_nBE        (S3C2440_SELECT_DSC1 | 18)
+#define S3C2440_DSC1_nBE_10mA   (0<<18)
+#define S3C2440_DSC1_nBE_8mA    (1<<18)
+#define S3C2440_DSC1_nBE_6mA    (2<<18)
+#define S3C2440_DSC1_nBE_4mA    (3<<18)
+#define S3C2440_DSC1_nBE_MASK   (3<<18)
+
+#define S3C2440_DSC1_WOE        (S3C2440_SELECT_DSC1 | 16)
+#define S3C2440_DSC1_WOE_10mA   (0<<16)
+#define S3C2440_DSC1_WOE_8mA    (1<<16)
+#define S3C2440_DSC1_WOE_6mA    (2<<16)
+#define S3C2440_DSC1_WOE_4mA    (3<<16)
+#define S3C2440_DSC1_WOE_MASK   (3<<16)
+
+#define S3C2440_DSC1_CS7        (S3C2440_SELECT_DSC1 | 14)
+#define S3C2440_DSC1_CS7_10mA   (0<<14)
+#define S3C2440_DSC1_CS7_8mA    (1<<14)
+#define S3C2440_DSC1_CS7_6mA    (2<<14)
+#define S3C2440_DSC1_CS7_4mA    (3<<14)
+#define S3C2440_DSC1_CS7_MASK   (3<<14)
+
+#define S3C2440_DSC1_CS6        (S3C2440_SELECT_DSC1 | 12)
+#define S3C2440_DSC1_CS6_10mA   (0<<12)
+#define S3C2440_DSC1_CS6_8mA    (1<<12)
+#define S3C2440_DSC1_CS6_6mA    (2<<12)
+#define S3C2440_DSC1_CS6_4mA    (3<<12)
+#define S3C2440_DSC1_CS6_MASK   (3<<12)
+
+#define S3C2440_DSC1_CS5        (S3C2440_SELECT_DSC1 | 10)
+#define S3C2440_DSC1_CS5_10mA   (0<<10)
+#define S3C2440_DSC1_CS5_8mA    (1<<10)
+#define S3C2440_DSC1_CS5_6mA    (2<<10)
+#define S3C2440_DSC1_CS5_4mA    (3<<10)
+#define S3C2440_DSC1_CS5_MASK   (3<<10)
+
+#define S3C2440_DSC1_CS4        (S3C2440_SELECT_DSC1 | 8)
+#define S3C2440_DSC1_CS4_10mA   (0<<8)
+#define S3C2440_DSC1_CS4_8mA    (1<<8)
+#define S3C2440_DSC1_CS4_6mA    (2<<8)
+#define S3C2440_DSC1_CS4_4mA    (3<<8)
+#define S3C2440_DSC1_CS4_MASK   (3<<8)
+
+#define S3C2440_DSC1_CS3        (S3C2440_SELECT_DSC1 | 6)
+#define S3C2440_DSC1_CS3_10mA   (0<<6)
+#define S3C2440_DSC1_CS3_8mA    (1<<6)
+#define S3C2440_DSC1_CS3_6mA    (2<<6)
+#define S3C2440_DSC1_CS3_4mA    (3<<6)
+#define S3C2440_DSC1_CS3_MASK   (3<<6)
+
+#define S3C2440_DSC1_CS2        (S3C2440_SELECT_DSC1 | 4)
+#define S3C2440_DSC1_CS2_10mA   (0<<4)
+#define S3C2440_DSC1_CS2_8mA    (1<<4)
+#define S3C2440_DSC1_CS2_6mA    (2<<4)
+#define S3C2440_DSC1_CS2_4mA    (3<<4)
+#define S3C2440_DSC1_CS2_MASK   (3<<4)
+
+#define S3C2440_DSC1_CS1        (S3C2440_SELECT_DSC1 | 2)
+#define S3C2440_DSC1_CS1_10mA   (0<<2)
+#define S3C2440_DSC1_CS1_8mA    (1<<2)
+#define S3C2440_DSC1_CS1_6mA    (2<<2)
+#define S3C2440_DSC1_CS1_4mA    (3<<2)
+#define S3C2440_DSC1_CS1_MASK   (3<<2)
+
+#define S3C2440_DSC1_CS0        (S3C2440_SELECT_DSC1 | 0)
+#define S3C2440_DSC1_CS0_10mA   (0<<0)
+#define S3C2440_DSC1_CS0_8mA    (1<<0)
+#define S3C2440_DSC1_CS0_6mA    (2<<0)
+#define S3C2440_DSC1_CS0_4mA    (3<<0)
+#define S3C2440_DSC1_CS0_MASK   (3<<0)
+
+#endif /* CONFIG_CPU_S3C2440 */
+
+#endif  /* __ASM_ARCH_REGS_DSC_H */
+
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
new file mode 100644
index 000000000000..30bec027f5fa
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
@@ -0,0 +1,1163 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-gpio.h
+ *
+ * Copyright (c) 2003,2004 Simtec Electronics <linux@simtec.co.uk>
+ *                         http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 GPIO register definitions
+*/
+
+
+#ifndef __ASM_ARCH_REGS_GPIO_H
+#define __ASM_ARCH_REGS_GPIO_H "$Id: gpio.h,v 1.5 2003/05/19 12:51:08 ben Exp $"
+
+#define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
+
+#define S3C2410_GPIO_BANKA   (32*0)
+#define S3C2410_GPIO_BANKB   (32*1)
+#define S3C2410_GPIO_BANKC   (32*2)
+#define S3C2410_GPIO_BANKD   (32*3)
+#define S3C2410_GPIO_BANKE   (32*4)
+#define S3C2410_GPIO_BANKF   (32*5)
+#define S3C2410_GPIO_BANKG   (32*6)
+#define S3C2410_GPIO_BANKH   (32*7)
+
+#ifdef CONFIG_CPU_S3C2400
+#define S3C24XX_GPIO_BASE(x)  S3C2400_GPIO_BASE(x)
+#define S3C24XX_MISCCR        S3C2400_MISCCR
+#else
+#define S3C24XX_GPIO_BASE(x)  S3C2410_GPIO_BASE(x)
+#define S3C24XX_MISCCR        S3C24XX_GPIOREG2(0x80)
+#endif /* CONFIG_CPU_S3C2400 */
+
+
+/* S3C2400 doesn't have a 1:1 mapping to S3C2410 gpio base pins */
+
+#define S3C2400_BANKNUM(pin)     (((pin) & ~31) / 32)
+#define S3C2400_BASEA2B(pin)     ((((pin) & ~31) >> 2))
+#define S3C2400_BASEC2H(pin)     ((S3C2400_BANKNUM(pin) * 10) + \
+                                 (2 * (S3C2400_BANKNUM(pin)-2)))
+
+#define S3C2400_GPIO_BASE(pin)   (pin < S3C2410_GPIO_BANKC ? \
+                                 S3C2400_BASEA2B(pin)+S3C24XX_VA_GPIO : \
+                                 S3C2400_BASEC2H(pin)+S3C24XX_VA_GPIO)
+
+
+#define S3C2410_GPIO_BASE(pin)   ((((pin) & ~31) >> 1) + S3C24XX_VA_GPIO)
+#define S3C2410_GPIO_OFFSET(pin) ((pin) & 31)
+
+/* general configuration options */
+
+#define S3C2410_GPIO_LEAVE   (0xFFFFFFFF)
+#define S3C2410_GPIO_INPUT   (0xFFFFFFF0)       /* not available on A */
+#define S3C2410_GPIO_OUTPUT  (0xFFFFFFF1)
+#define S3C2410_GPIO_IRQ     (0xFFFFFFF2)       /* not available for all */
+#define S3C2410_GPIO_SFN2    (0xFFFFFFF2)       /* bank A => addr/cs/nand */
+#define S3C2410_GPIO_SFN3    (0xFFFFFFF3)       /* not available on A */
+
+/* register address for the GPIO registers.
+ * S3C24XX_GPIOREG2 is for the second set of registers in the
+ * GPIO which move between s3c2410 and s3c2412 type systems */
+
+#define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO)
+#define S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2)
+
+
+/* configure GPIO ports A..G */
+
+/* port A - S3C2410: 22bits, zero in bit X makes pin X output
+ *          S3C2400: 18bits, zero in bit X makes pin X output
+ * 1 makes port special function, this is default
+*/
+#define S3C2410_GPACON     S3C2410_GPIOREG(0x00)
+#define S3C2410_GPADAT     S3C2410_GPIOREG(0x04)
+
+#define S3C2400_GPACON     S3C2410_GPIOREG(0x00)
+#define S3C2400_GPADAT     S3C2410_GPIOREG(0x04)
+
+#define S3C2410_GPA0         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0)
+#define S3C2410_GPA0_OUT     (0<<0)
+#define S3C2410_GPA0_ADDR0   (1<<0)
+
+#define S3C2410_GPA1         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 1)
+#define S3C2410_GPA1_OUT     (0<<1)
+#define S3C2410_GPA1_ADDR16  (1<<1)
+
+#define S3C2410_GPA2         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 2)
+#define S3C2410_GPA2_OUT     (0<<2)
+#define S3C2410_GPA2_ADDR17  (1<<2)
+
+#define S3C2410_GPA3         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 3)
+#define S3C2410_GPA3_OUT     (0<<3)
+#define S3C2410_GPA3_ADDR18  (1<<3)
+
+#define S3C2410_GPA4         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 4)
+#define S3C2410_GPA4_OUT     (0<<4)
+#define S3C2410_GPA4_ADDR19  (1<<4)
+
+#define S3C2410_GPA5         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 5)
+#define S3C2410_GPA5_OUT     (0<<5)
+#define S3C2410_GPA5_ADDR20  (1<<5)
+
+#define S3C2410_GPA6         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 6)
+#define S3C2410_GPA6_OUT     (0<<6)
+#define S3C2410_GPA6_ADDR21  (1<<6)
+
+#define S3C2410_GPA7         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 7)
+#define S3C2410_GPA7_OUT     (0<<7)
+#define S3C2410_GPA7_ADDR22  (1<<7)
+
+#define S3C2410_GPA8         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 8)
+#define S3C2410_GPA8_OUT     (0<<8)
+#define S3C2410_GPA8_ADDR23  (1<<8)
+
+#define S3C2410_GPA9         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 9)
+#define S3C2410_GPA9_OUT     (0<<9)
+#define S3C2410_GPA9_ADDR24  (1<<9)
+
+#define S3C2410_GPA10        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10)
+#define S3C2410_GPA10_OUT    (0<<10)
+#define S3C2410_GPA10_ADDR25 (1<<10)
+#define S3C2400_GPA10_SCKE   (1<<10)
+
+#define S3C2410_GPA11        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11)
+#define S3C2410_GPA11_OUT    (0<<11)
+#define S3C2410_GPA11_ADDR26 (1<<11)
+#define S3C2400_GPA11_nCAS0  (1<<11)
+
+#define S3C2410_GPA12        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12)
+#define S3C2410_GPA12_OUT    (0<<12)
+#define S3C2410_GPA12_nGCS1  (1<<12)
+#define S3C2400_GPA12_nCAS1  (1<<12)
+
+#define S3C2410_GPA13        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13)
+#define S3C2410_GPA13_OUT    (0<<13)
+#define S3C2410_GPA13_nGCS2  (1<<13)
+#define S3C2400_GPA13_nGCS1  (1<<13)
+
+#define S3C2410_GPA14        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14)
+#define S3C2410_GPA14_OUT    (0<<14)
+#define S3C2410_GPA14_nGCS3  (1<<14)
+#define S3C2400_GPA14_nGCS2  (1<<14)
+
+#define S3C2410_GPA15        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15)
+#define S3C2410_GPA15_OUT    (0<<15)
+#define S3C2410_GPA15_nGCS4  (1<<15)
+#define S3C2400_GPA15_nGCS3  (1<<15)
+
+#define S3C2410_GPA16        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16)
+#define S3C2410_GPA16_OUT    (0<<16)
+#define S3C2410_GPA16_nGCS5  (1<<16)
+#define S3C2400_GPA16_nGCS4  (1<<16)
+
+#define S3C2410_GPA17        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17)
+#define S3C2410_GPA17_OUT    (0<<17)
+#define S3C2410_GPA17_CLE    (1<<17)
+#define S3C2400_GPA17_nGCS5  (1<<17)
+
+#define S3C2410_GPA18        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18)
+#define S3C2410_GPA18_OUT    (0<<18)
+#define S3C2410_GPA18_ALE    (1<<18)
+
+#define S3C2410_GPA19        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 19)
+#define S3C2410_GPA19_OUT    (0<<19)
+#define S3C2410_GPA19_nFWE   (1<<19)
+
+#define S3C2410_GPA20        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 20)
+#define S3C2410_GPA20_OUT    (0<<20)
+#define S3C2410_GPA20_nFRE   (1<<20)
+
+#define S3C2410_GPA21        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 21)
+#define S3C2410_GPA21_OUT    (0<<21)
+#define S3C2410_GPA21_nRSTOUT (1<<21)
+
+#define S3C2410_GPA22        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 22)
+#define S3C2410_GPA22_OUT    (0<<22)
+#define S3C2410_GPA22_nFCE   (1<<22)
+
+/* 0x08 and 0x0c are reserved on S3C2410 */
+
+/* S3C2410:
+ * GPB is 10 IO pins, each configured by 2 bits each in GPBCON.
+ *   00 = input, 01 = output, 10=special function, 11=reserved
+
+ * S3C2400:
+ * GPB is 16 IO pins, each configured by 2 bits each in GPBCON.
+ *   00 = input, 01 = output, 10=data, 11=special function
+
+ * bit 0,1 = pin 0, 2,3= pin 1...
+ *
+ * CPBUP = pull up resistor control, 1=disabled, 0=enabled
+*/
+
+#define S3C2410_GPBCON     S3C2410_GPIOREG(0x10)
+#define S3C2410_GPBDAT     S3C2410_GPIOREG(0x14)
+#define S3C2410_GPBUP      S3C2410_GPIOREG(0x18)
+
+#define S3C2400_GPBCON     S3C2410_GPIOREG(0x08)
+#define S3C2400_GPBDAT     S3C2410_GPIOREG(0x0C)
+#define S3C2400_GPBUP      S3C2410_GPIOREG(0x10)
+
+/* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */
+
+#define S3C2410_GPB0         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0)
+#define S3C2410_GPB0_INP     (0x00 << 0)
+#define S3C2410_GPB0_OUTP    (0x01 << 0)
+#define S3C2410_GPB0_TOUT0   (0x02 << 0)
+#define S3C2400_GPB0_DATA16  (0x02 << 0)
+
+#define S3C2410_GPB1         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1)
+#define S3C2410_GPB1_INP     (0x00 << 2)
+#define S3C2410_GPB1_OUTP    (0x01 << 2)
+#define S3C2410_GPB1_TOUT1   (0x02 << 2)
+#define S3C2400_GPB1_DATA17  (0x02 << 2)
+
+#define S3C2410_GPB2         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2)
+#define S3C2410_GPB2_INP     (0x00 << 4)
+#define S3C2410_GPB2_OUTP    (0x01 << 4)
+#define S3C2410_GPB2_TOUT2   (0x02 << 4)
+#define S3C2400_GPB2_DATA18  (0x02 << 4)
+#define S3C2400_GPB2_TCLK1   (0x03 << 4)
+
+#define S3C2410_GPB3         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3)
+#define S3C2410_GPB3_INP     (0x00 << 6)
+#define S3C2410_GPB3_OUTP    (0x01 << 6)
+#define S3C2410_GPB3_TOUT3   (0x02 << 6)
+#define S3C2400_GPB3_DATA19  (0x02 << 6)
+#define S3C2400_GPB3_TXD1    (0x03 << 6)
+
+#define S3C2410_GPB4         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4)
+#define S3C2410_GPB4_INP     (0x00 << 8)
+#define S3C2410_GPB4_OUTP    (0x01 << 8)
+#define S3C2410_GPB4_TCLK0   (0x02 << 8)
+#define S3C2400_GPB4_DATA20  (0x02 << 8)
+#define S3C2410_GPB4_MASK    (0x03 << 8)
+#define S3C2400_GPB4_RXD1    (0x03 << 8)
+#define S3C2400_GPB4_MASK    (0x03 << 8)
+
+#define S3C2410_GPB5         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5)
+#define S3C2410_GPB5_INP     (0x00 << 10)
+#define S3C2410_GPB5_OUTP    (0x01 << 10)
+#define S3C2410_GPB5_nXBACK  (0x02 << 10)
+#define S3C2443_GPB5_XBACK   (0x03 << 10)
+#define S3C2400_GPB5_DATA21  (0x02 << 10)
+#define S3C2400_GPB5_nCTS1   (0x03 << 10)
+
+#define S3C2410_GPB6         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6)
+#define S3C2410_GPB6_INP     (0x00 << 12)
+#define S3C2410_GPB6_OUTP    (0x01 << 12)
+#define S3C2410_GPB6_nXBREQ  (0x02 << 12)
+#define S3C2443_GPB6_XBREQ   (0x03 << 12)
+#define S3C2400_GPB6_DATA22  (0x02 << 12)
+#define S3C2400_GPB6_nRTS1   (0x03 << 12)
+
+#define S3C2410_GPB7         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7)
+#define S3C2410_GPB7_INP     (0x00 << 14)
+#define S3C2410_GPB7_OUTP    (0x01 << 14)
+#define S3C2410_GPB7_nXDACK1 (0x02 << 14)
+#define S3C2443_GPB7_XDACK1  (0x03 << 14)
+#define S3C2400_GPB7_DATA23  (0x02 << 14)
+
+#define S3C2410_GPB8         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8)
+#define S3C2410_GPB8_INP     (0x00 << 16)
+#define S3C2410_GPB8_OUTP    (0x01 << 16)
+#define S3C2410_GPB8_nXDREQ1 (0x02 << 16)
+#define S3C2400_GPB8_DATA24  (0x02 << 16)
+
+#define S3C2410_GPB9         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9)
+#define S3C2410_GPB9_INP     (0x00 << 18)
+#define S3C2410_GPB9_OUTP    (0x01 << 18)
+#define S3C2410_GPB9_nXDACK0 (0x02 << 18)
+#define S3C2443_GPB9_XDACK0  (0x03 << 18)
+#define S3C2400_GPB9_DATA25  (0x02 << 18)
+#define S3C2400_GPB9_I2SSDI  (0x03 << 18)
+
+#define S3C2410_GPB10        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10)
+#define S3C2410_GPB10_INP    (0x00 << 20)
+#define S3C2410_GPB10_OUTP   (0x01 << 20)
+#define S3C2410_GPB10_nXDRE0 (0x02 << 20)
+#define S3C2443_GPB10_XDREQ0 (0x03 << 20)
+#define S3C2400_GPB10_DATA26 (0x02 << 20)
+#define S3C2400_GPB10_nSS    (0x03 << 20)
+
+#define S3C2400_GPB11        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 11)
+#define S3C2400_GPB11_INP    (0x00 << 22)
+#define S3C2400_GPB11_OUTP   (0x01 << 22)
+#define S3C2400_GPB11_DATA27 (0x02 << 22)
+
+#define S3C2400_GPB12        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 12)
+#define S3C2400_GPB12_INP    (0x00 << 24)
+#define S3C2400_GPB12_OUTP   (0x01 << 24)
+#define S3C2400_GPB12_DATA28 (0x02 << 24)
+
+#define S3C2400_GPB13        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 13)
+#define S3C2400_GPB13_INP    (0x00 << 26)
+#define S3C2400_GPB13_OUTP   (0x01 << 26)
+#define S3C2400_GPB13_DATA29 (0x02 << 26)
+
+#define S3C2400_GPB14        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 14)
+#define S3C2400_GPB14_INP    (0x00 << 28)
+#define S3C2400_GPB14_OUTP   (0x01 << 28)
+#define S3C2400_GPB14_DATA30 (0x02 << 28)
+
+#define S3C2400_GPB15        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 15)
+#define S3C2400_GPB15_INP    (0x00 << 30)
+#define S3C2400_GPB15_OUTP   (0x01 << 30)
+#define S3C2400_GPB15_DATA31 (0x02 << 30)
+
+#define S3C2410_GPB_PUPDIS(x)  (1<<(x))
+
+/* Port C consits of 16 GPIO/Special function
+ *
+ * almost identical setup to port b, but the special functions are mostly
+ * to do with the video system's sync/etc.
+*/
+
+#define S3C2410_GPCCON     S3C2410_GPIOREG(0x20)
+#define S3C2410_GPCDAT     S3C2410_GPIOREG(0x24)
+#define S3C2410_GPCUP      S3C2410_GPIOREG(0x28)
+
+#define S3C2400_GPCCON     S3C2410_GPIOREG(0x14)
+#define S3C2400_GPCDAT     S3C2410_GPIOREG(0x18)
+#define S3C2400_GPCUP      S3C2410_GPIOREG(0x1C)
+
+#define S3C2410_GPC0            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0)
+#define S3C2410_GPC0_INP        (0x00 << 0)
+#define S3C2410_GPC0_OUTP       (0x01 << 0)
+#define S3C2410_GPC0_LEND       (0x02 << 0)
+#define S3C2400_GPC0_VD0        (0x02 << 0)
+
+#define S3C2410_GPC1            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1)
+#define S3C2410_GPC1_INP        (0x00 << 2)
+#define S3C2410_GPC1_OUTP       (0x01 << 2)
+#define S3C2410_GPC1_VCLK       (0x02 << 2)
+#define S3C2400_GPC1_VD1        (0x02 << 2)
+
+#define S3C2410_GPC2            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2)
+#define S3C2410_GPC2_INP        (0x00 << 4)
+#define S3C2410_GPC2_OUTP       (0x01 << 4)
+#define S3C2410_GPC2_VLINE      (0x02 << 4)
+#define S3C2400_GPC2_VD2        (0x02 << 4)
+
+#define S3C2410_GPC3            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3)
+#define S3C2410_GPC3_INP        (0x00 << 6)
+#define S3C2410_GPC3_OUTP       (0x01 << 6)
+#define S3C2410_GPC3_VFRAME     (0x02 << 6)
+#define S3C2400_GPC3_VD3        (0x02 << 6)
+
+#define S3C2410_GPC4            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4)
+#define S3C2410_GPC4_INP        (0x00 << 8)
+#define S3C2410_GPC4_OUTP       (0x01 << 8)
+#define S3C2410_GPC4_VM         (0x02 << 8)
+#define S3C2400_GPC4_VD4        (0x02 << 8)
+
+#define S3C2410_GPC5            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5)
+#define S3C2410_GPC5_INP        (0x00 << 10)
+#define S3C2410_GPC5_OUTP       (0x01 << 10)
+#define S3C2410_GPC5_LCDVF0     (0x02 << 10)
+#define S3C2400_GPC5_VD5        (0x02 << 10)
+
+#define S3C2410_GPC6            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6)
+#define S3C2410_GPC6_INP        (0x00 << 12)
+#define S3C2410_GPC6_OUTP       (0x01 << 12)
+#define S3C2410_GPC6_LCDVF1     (0x02 << 12)
+#define S3C2400_GPC6_VD6        (0x02 << 12)
+
+#define S3C2410_GPC7            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7)
+#define S3C2410_GPC7_INP        (0x00 << 14)
+#define S3C2410_GPC7_OUTP       (0x01 << 14)
+#define S3C2410_GPC7_LCDVF2     (0x02 << 14)
+#define S3C2400_GPC7_VD7        (0x02 << 14)
+
+#define S3C2410_GPC8            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8)
+#define S3C2410_GPC8_INP        (0x00 << 16)
+#define S3C2410_GPC8_OUTP       (0x01 << 16)
+#define S3C2410_GPC8_VD0        (0x02 << 16)
+#define S3C2400_GPC8_VD8        (0x02 << 16)
+
+#define S3C2410_GPC9            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9)
+#define S3C2410_GPC9_INP        (0x00 << 18)
+#define S3C2410_GPC9_OUTP       (0x01 << 18)
+#define S3C2410_GPC9_VD1        (0x02 << 18)
+#define S3C2400_GPC9_VD9        (0x02 << 18)
+
+#define S3C2410_GPC10           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10)
+#define S3C2410_GPC10_INP       (0x00 << 20)
+#define S3C2410_GPC10_OUTP      (0x01 << 20)
+#define S3C2410_GPC10_VD2       (0x02 << 20)
+#define S3C2400_GPC10_VD10      (0x02 << 20)
+
+#define S3C2410_GPC11           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11)
+#define S3C2410_GPC11_INP       (0x00 << 22)
+#define S3C2410_GPC11_OUTP      (0x01 << 22)
+#define S3C2410_GPC11_VD3       (0x02 << 22)
+#define S3C2400_GPC11_VD11      (0x02 << 22)
+
+#define S3C2410_GPC12           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12)
+#define S3C2410_GPC12_INP       (0x00 << 24)
+#define S3C2410_GPC12_OUTP      (0x01 << 24)
+#define S3C2410_GPC12_VD4       (0x02 << 24)
+#define S3C2400_GPC12_VD12      (0x02 << 24)
+
+#define S3C2410_GPC13           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13)
+#define S3C2410_GPC13_INP       (0x00 << 26)
+#define S3C2410_GPC13_OUTP      (0x01 << 26)
+#define S3C2410_GPC13_VD5       (0x02 << 26)
+#define S3C2400_GPC13_VD13      (0x02 << 26)
+
+#define S3C2410_GPC14           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14)
+#define S3C2410_GPC14_INP       (0x00 << 28)
+#define S3C2410_GPC14_OUTP      (0x01 << 28)
+#define S3C2410_GPC14_VD6       (0x02 << 28)
+#define S3C2400_GPC14_VD14      (0x02 << 28)
+
+#define S3C2410_GPC15           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15)
+#define S3C2410_GPC15_INP       (0x00 << 30)
+#define S3C2410_GPC15_OUTP      (0x01 << 30)
+#define S3C2410_GPC15_VD7       (0x02 << 30)
+#define S3C2400_GPC15_VD15      (0x02 << 30)
+
+#define S3C2410_GPC_PUPDIS(x)  (1<<(x))
+
+/*
+ * S3C2410: Port D consists of 16 GPIO/Special function
+ *
+ * almost identical setup to port b, but the special functions are mostly
+ * to do with the video system's data.
+ *
+ * S3C2400: Port D consists of 11 GPIO/Special function
+ *
+ * almost identical setup to port c
+*/
+
+#define S3C2410_GPDCON     S3C2410_GPIOREG(0x30)
+#define S3C2410_GPDDAT     S3C2410_GPIOREG(0x34)
+#define S3C2410_GPDUP      S3C2410_GPIOREG(0x38)
+
+#define S3C2400_GPDCON     S3C2410_GPIOREG(0x20)
+#define S3C2400_GPDDAT     S3C2410_GPIOREG(0x24)
+#define S3C2400_GPDUP      S3C2410_GPIOREG(0x28)
+
+#define S3C2410_GPD0            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0)
+#define S3C2410_GPD0_INP        (0x00 << 0)
+#define S3C2410_GPD0_OUTP       (0x01 << 0)
+#define S3C2410_GPD0_VD8        (0x02 << 0)
+#define S3C2400_GPD0_VFRAME     (0x02 << 0)
+#define S3C2442_GPD0_nSPICS1    (0x03 << 0)
+
+#define S3C2410_GPD1            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1)
+#define S3C2410_GPD1_INP        (0x00 << 2)
+#define S3C2410_GPD1_OUTP       (0x01 << 2)
+#define S3C2410_GPD1_VD9        (0x02 << 2)
+#define S3C2400_GPD1_VM         (0x02 << 2)
+#define S3C2442_GPD1_SPICLK1    (0x03 << 2)
+
+#define S3C2410_GPD2            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2)
+#define S3C2410_GPD2_INP        (0x00 << 4)
+#define S3C2410_GPD2_OUTP       (0x01 << 4)
+#define S3C2410_GPD2_VD10       (0x02 << 4)
+#define S3C2400_GPD2_VLINE      (0x02 << 4)
+
+#define S3C2410_GPD3            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3)
+#define S3C2410_GPD3_INP        (0x00 << 6)
+#define S3C2410_GPD3_OUTP       (0x01 << 6)
+#define S3C2410_GPD3_VD11       (0x02 << 6)
+#define S3C2400_GPD3_VCLK       (0x02 << 6)
+
+#define S3C2410_GPD4            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4)
+#define S3C2410_GPD4_INP        (0x00 << 8)
+#define S3C2410_GPD4_OUTP       (0x01 << 8)
+#define S3C2410_GPD4_VD12       (0x02 << 8)
+#define S3C2400_GPD4_LEND       (0x02 << 8)
+
+#define S3C2410_GPD5            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5)
+#define S3C2410_GPD5_INP        (0x00 << 10)
+#define S3C2410_GPD5_OUTP       (0x01 << 10)
+#define S3C2410_GPD5_VD13       (0x02 << 10)
+#define S3C2400_GPD5_TOUT0      (0x02 << 10)
+
+#define S3C2410_GPD6            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6)
+#define S3C2410_GPD6_INP        (0x00 << 12)
+#define S3C2410_GPD6_OUTP       (0x01 << 12)
+#define S3C2410_GPD6_VD14       (0x02 << 12)
+#define S3C2400_GPD6_TOUT1      (0x02 << 12)
+
+#define S3C2410_GPD7            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7)
+#define S3C2410_GPD7_INP        (0x00 << 14)
+#define S3C2410_GPD7_OUTP       (0x01 << 14)
+#define S3C2410_GPD7_VD15       (0x02 << 14)
+#define S3C2400_GPD7_TOUT2      (0x02 << 14)
+
+#define S3C2410_GPD8            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8)
+#define S3C2410_GPD8_INP        (0x00 << 16)
+#define S3C2410_GPD8_OUTP       (0x01 << 16)
+#define S3C2410_GPD8_VD16       (0x02 << 16)
+#define S3C2400_GPD8_TOUT3      (0x02 << 16)
+
+#define S3C2410_GPD9            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9)
+#define S3C2410_GPD9_INP        (0x00 << 18)
+#define S3C2410_GPD9_OUTP       (0x01 << 18)
+#define S3C2410_GPD9_VD17       (0x02 << 18)
+#define S3C2400_GPD9_TCLK0      (0x02 << 18)
+#define S3C2410_GPD9_MASK       (0x03 << 18)
+
+#define S3C2410_GPD10           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10)
+#define S3C2410_GPD10_INP       (0x00 << 20)
+#define S3C2410_GPD10_OUTP      (0x01 << 20)
+#define S3C2410_GPD10_VD18      (0x02 << 20)
+#define S3C2400_GPD10_nWAIT     (0x02 << 20)
+
+#define S3C2410_GPD11           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11)
+#define S3C2410_GPD11_INP       (0x00 << 22)
+#define S3C2410_GPD11_OUTP      (0x01 << 22)
+#define S3C2410_GPD11_VD19      (0x02 << 22)
+
+#define S3C2410_GPD12           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 12)
+#define S3C2410_GPD12_INP       (0x00 << 24)
+#define S3C2410_GPD12_OUTP      (0x01 << 24)
+#define S3C2410_GPD12_VD20      (0x02 << 24)
+
+#define S3C2410_GPD13           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 13)
+#define S3C2410_GPD13_INP       (0x00 << 26)
+#define S3C2410_GPD13_OUTP      (0x01 << 26)
+#define S3C2410_GPD13_VD21      (0x02 << 26)
+
+#define S3C2410_GPD14           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 14)
+#define S3C2410_GPD14_INP       (0x00 << 28)
+#define S3C2410_GPD14_OUTP      (0x01 << 28)
+#define S3C2410_GPD14_VD22      (0x02 << 28)
+#define S3C2410_GPD14_nSS1      (0x03 << 28)
+
+#define S3C2410_GPD15           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15)
+#define S3C2410_GPD15_INP       (0x00 << 30)
+#define S3C2410_GPD15_OUTP      (0x01 << 30)
+#define S3C2410_GPD15_VD23      (0x02 << 30)
+#define S3C2410_GPD15_nSS0      (0x03 << 30)
+
+#define S3C2410_GPD_PUPDIS(x)  (1<<(x))
+
+/* S3C2410:
+ * Port E consists of 16 GPIO/Special function
+ *
+ * again, the same as port B, but dealing with I2S, SDI, and
+ * more miscellaneous functions
+ *
+ * S3C2400:
+ * Port E consists of 12 GPIO/Special function
+ *
+ * GPIO / interrupt inputs
+*/
+
+#define S3C2410_GPECON     S3C2410_GPIOREG(0x40)
+#define S3C2410_GPEDAT     S3C2410_GPIOREG(0x44)
+#define S3C2410_GPEUP      S3C2410_GPIOREG(0x48)
+
+#define S3C2400_GPECON     S3C2410_GPIOREG(0x2C)
+#define S3C2400_GPEDAT     S3C2410_GPIOREG(0x30)
+#define S3C2400_GPEUP      S3C2410_GPIOREG(0x34)
+
+#define S3C2410_GPE0           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0)
+#define S3C2410_GPE0_INP       (0x00 << 0)
+#define S3C2410_GPE0_OUTP      (0x01 << 0)
+#define S3C2410_GPE0_I2SLRCK   (0x02 << 0)
+#define S3C2443_GPE0_AC_nRESET (0x03 << 0)
+#define S3C2400_GPE0_EINT0     (0x02 << 0)
+#define S3C2410_GPE0_MASK      (0x03 << 0)
+
+#define S3C2410_GPE1           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1)
+#define S3C2410_GPE1_INP       (0x00 << 2)
+#define S3C2410_GPE1_OUTP      (0x01 << 2)
+#define S3C2410_GPE1_I2SSCLK   (0x02 << 2)
+#define S3C2443_GPE1_AC_SYNC   (0x03 << 2)
+#define S3C2400_GPE1_EINT1     (0x02 << 2)
+#define S3C2400_GPE1_nSS       (0x03 << 2)
+#define S3C2410_GPE1_MASK      (0x03 << 2)
+
+#define S3C2410_GPE2           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2)
+#define S3C2410_GPE2_INP       (0x00 << 4)
+#define S3C2410_GPE2_OUTP      (0x01 << 4)
+#define S3C2410_GPE2_CDCLK     (0x02 << 4)
+#define S3C2443_GPE2_AC_BITCLK (0x03 << 4)
+#define S3C2400_GPE2_EINT2     (0x02 << 4)
+#define S3C2400_GPE2_I2SSDI    (0x03 << 4)
+
+#define S3C2410_GPE3           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3)
+#define S3C2410_GPE3_INP       (0x00 << 6)
+#define S3C2410_GPE3_OUTP      (0x01 << 6)
+#define S3C2410_GPE3_I2SSDI    (0x02 << 6)
+#define S3C2443_GPE3_AC_SDI    (0x03 << 6)
+#define S3C2400_GPE3_EINT3     (0x02 << 6)
+#define S3C2400_GPE3_nCTS1     (0x03 << 6)
+#define S3C2410_GPE3_nSS0      (0x03 << 6)
+#define S3C2410_GPE3_MASK      (0x03 << 6)
+
+#define S3C2410_GPE4           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 4)
+#define S3C2410_GPE4_INP       (0x00 << 8)
+#define S3C2410_GPE4_OUTP      (0x01 << 8)
+#define S3C2410_GPE4_I2SSDO    (0x02 << 8)
+#define S3C2443_GPE4_AC_SDO    (0x03 << 8)
+#define S3C2400_GPE4_EINT4     (0x02 << 8)
+#define S3C2400_GPE4_nRTS1     (0x03 << 8)
+#define S3C2410_GPE4_I2SSDI    (0x03 << 8)
+#define S3C2410_GPE4_MASK      (0x03 << 8)
+
+#define S3C2410_GPE5           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 5)
+#define S3C2410_GPE5_INP       (0x00 << 10)
+#define S3C2410_GPE5_OUTP      (0x01 << 10)
+#define S3C2410_GPE5_SDCLK     (0x02 << 10)
+#define S3C2443_GPE5_SD1_CLK   (0x02 << 10)
+#define S3C2400_GPE5_EINT5     (0x02 << 10)
+#define S3C2400_GPE5_TCLK1     (0x03 << 10)
+
+#define S3C2410_GPE6           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6)
+#define S3C2410_GPE6_INP       (0x00 << 12)
+#define S3C2410_GPE6_OUTP      (0x01 << 12)
+#define S3C2410_GPE6_SDCMD     (0x02 << 12)
+#define S3C2443_GPE6_SD1_CMD   (0x02 << 12)
+#define S3C2443_GPE6_AC_BITCLK (0x03 << 12)
+#define S3C2400_GPE6_EINT6     (0x02 << 12)
+
+#define S3C2410_GPE7           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7)
+#define S3C2410_GPE7_INP       (0x00 << 14)
+#define S3C2410_GPE7_OUTP      (0x01 << 14)
+#define S3C2410_GPE7_SDDAT0    (0x02 << 14)
+#define S3C2443_GPE5_SD1_DAT0  (0x02 << 14)
+#define S3C2443_GPE7_AC_SDI    (0x03 << 14)
+#define S3C2400_GPE7_EINT7     (0x02 << 14)
+
+#define S3C2410_GPE8           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8)
+#define S3C2410_GPE8_INP       (0x00 << 16)
+#define S3C2410_GPE8_OUTP      (0x01 << 16)
+#define S3C2410_GPE8_SDDAT1    (0x02 << 16)
+#define S3C2443_GPE8_SD1_DAT1  (0x02 << 16)
+#define S3C2443_GPE8_AC_SDO    (0x03 << 16)
+#define S3C2400_GPE8_nXDACK0   (0x02 << 16)
+
+#define S3C2410_GPE9           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9)
+#define S3C2410_GPE9_INP       (0x00 << 18)
+#define S3C2410_GPE9_OUTP      (0x01 << 18)
+#define S3C2410_GPE9_SDDAT2    (0x02 << 18)
+#define S3C2443_GPE9_SD1_DAT2  (0x02 << 18)
+#define S3C2443_GPE9_AC_SYNC   (0x03 << 18)
+#define S3C2400_GPE9_nXDACK1   (0x02 << 18)
+#define S3C2400_GPE9_nXBACK    (0x03 << 18)
+
+#define S3C2410_GPE10          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10)
+#define S3C2410_GPE10_INP      (0x00 << 20)
+#define S3C2410_GPE10_OUTP     (0x01 << 20)
+#define S3C2410_GPE10_SDDAT3   (0x02 << 20)
+#define S3C2443_GPE10_SD1_DAT3 (0x02 << 20)
+#define S3C2443_GPE10_AC_nRESET (0x03 << 20)
+#define S3C2400_GPE10_nXDREQ0  (0x02 << 20)
+
+#define S3C2410_GPE11          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11)
+#define S3C2410_GPE11_INP      (0x00 << 22)
+#define S3C2410_GPE11_OUTP     (0x01 << 22)
+#define S3C2410_GPE11_SPIMISO0 (0x02 << 22)
+#define S3C2400_GPE11_nXDREQ1  (0x02 << 22)
+#define S3C2400_GPE11_nXBREQ   (0x03 << 22)
+
+#define S3C2410_GPE12          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12)
+#define S3C2410_GPE12_INP      (0x00 << 24)
+#define S3C2410_GPE12_OUTP     (0x01 << 24)
+#define S3C2410_GPE12_SPIMOSI0 (0x02 << 24)
+
+#define S3C2410_GPE13          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 13)
+#define S3C2410_GPE13_INP      (0x00 << 26)
+#define S3C2410_GPE13_OUTP     (0x01 << 26)
+#define S3C2410_GPE13_SPICLK0  (0x02 << 26)
+
+#define S3C2410_GPE14          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 14)
+#define S3C2410_GPE14_INP      (0x00 << 28)
+#define S3C2410_GPE14_OUTP     (0x01 << 28)
+#define S3C2410_GPE14_IICSCL   (0x02 << 28)
+#define S3C2410_GPE14_MASK     (0x03 << 28)
+
+#define S3C2410_GPE15          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 15)
+#define S3C2410_GPE15_INP      (0x00 << 30)
+#define S3C2410_GPE15_OUTP     (0x01 << 30)
+#define S3C2410_GPE15_IICSDA   (0x02 << 30)
+#define S3C2410_GPE15_MASK     (0x03 << 30)
+
+#define S3C2440_GPE0_ACSYNC    (0x03 << 0)
+#define S3C2440_GPE1_ACBITCLK  (0x03 << 2)
+#define S3C2440_GPE2_ACRESET   (0x03 << 4)
+#define S3C2440_GPE3_ACIN      (0x03 << 6)
+#define S3C2440_GPE4_ACOUT     (0x03 << 8)
+
+#define S3C2410_GPE_PUPDIS(x)  (1<<(x))
+
+/* S3C2410:
+ * Port F consists of 8 GPIO/Special function
+ *
+ * GPIO / interrupt inputs
+ *
+ * GPFCON has 2 bits for each of the input pins on port F
+ *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined
+ *
+ * pull up works like all other ports.
+ *
+ * S3C2400:
+ * Port F consists of 7 GPIO/Special function
+ *
+ * GPIO/serial/misc pins
+*/
+
+#define S3C2410_GPFCON     S3C2410_GPIOREG(0x50)
+#define S3C2410_GPFDAT     S3C2410_GPIOREG(0x54)
+#define S3C2410_GPFUP      S3C2410_GPIOREG(0x58)
+
+#define S3C2400_GPFCON     S3C2410_GPIOREG(0x38)
+#define S3C2400_GPFDAT     S3C2410_GPIOREG(0x3C)
+#define S3C2400_GPFUP      S3C2410_GPIOREG(0x40)
+
+#define S3C2410_GPF0        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0)
+#define S3C2410_GPF0_INP    (0x00 << 0)
+#define S3C2410_GPF0_OUTP   (0x01 << 0)
+#define S3C2410_GPF0_EINT0  (0x02 << 0)
+#define S3C2400_GPF0_RXD0   (0x02 << 0)
+
+#define S3C2410_GPF1        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1)
+#define S3C2410_GPF1_INP    (0x00 << 2)
+#define S3C2410_GPF1_OUTP   (0x01 << 2)
+#define S3C2410_GPF1_EINT1  (0x02 << 2)
+#define S3C2400_GPF1_RXD1   (0x02 << 2)
+#define S3C2400_GPF1_IICSDA (0x03 << 2)
+
+#define S3C2410_GPF2        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2)
+#define S3C2410_GPF2_INP    (0x00 << 4)
+#define S3C2410_GPF2_OUTP   (0x01 << 4)
+#define S3C2410_GPF2_EINT2  (0x02 << 4)
+#define S3C2400_GPF2_TXD0   (0x02 << 4)
+
+#define S3C2410_GPF3        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3)
+#define S3C2410_GPF3_INP    (0x00 << 6)
+#define S3C2410_GPF3_OUTP   (0x01 << 6)
+#define S3C2410_GPF3_EINT3  (0x02 << 6)
+#define S3C2400_GPF3_TXD1   (0x02 << 6)
+#define S3C2400_GPF3_IICSCL (0x03 << 6)
+
+#define S3C2410_GPF4        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4)
+#define S3C2410_GPF4_INP    (0x00 << 8)
+#define S3C2410_GPF4_OUTP   (0x01 << 8)
+#define S3C2410_GPF4_EINT4  (0x02 << 8)
+#define S3C2400_GPF4_nRTS0  (0x02 << 8)
+#define S3C2400_GPF4_nXBACK (0x03 << 8)
+
+#define S3C2410_GPF5        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5)
+#define S3C2410_GPF5_INP    (0x00 << 10)
+#define S3C2410_GPF5_OUTP   (0x01 << 10)
+#define S3C2410_GPF5_EINT5  (0x02 << 10)
+#define S3C2400_GPF5_nCTS0  (0x02 << 10)
+#define S3C2400_GPF5_nXBREQ (0x03 << 10)
+
+#define S3C2410_GPF6        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6)
+#define S3C2410_GPF6_INP    (0x00 << 12)
+#define S3C2410_GPF6_OUTP   (0x01 << 12)
+#define S3C2410_GPF6_EINT6  (0x02 << 12)
+#define S3C2400_GPF6_CLKOUT (0x02 << 12)
+
+#define S3C2410_GPF7        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7)
+#define S3C2410_GPF7_INP    (0x00 << 14)
+#define S3C2410_GPF7_OUTP   (0x01 << 14)
+#define S3C2410_GPF7_EINT7  (0x02 << 14)
+
+#define S3C2410_GPF_PUPDIS(x)  (1<<(x))
+
+/* S3C2410:
+ * Port G consists of 8 GPIO/IRQ/Special function
+ *
+ * GPGCON has 2 bits for each of the input pins on port F
+ *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
+ *
+ * pull up works like all other ports.
+ *
+ * S3C2400:
+ * Port G consists of 10 GPIO/Special function
+*/
+
+#define S3C2410_GPGCON     S3C2410_GPIOREG(0x60)
+#define S3C2410_GPGDAT     S3C2410_GPIOREG(0x64)
+#define S3C2410_GPGUP      S3C2410_GPIOREG(0x68)
+
+#define S3C2400_GPGCON     S3C2410_GPIOREG(0x44)
+#define S3C2400_GPGDAT     S3C2410_GPIOREG(0x48)
+#define S3C2400_GPGUP      S3C2410_GPIOREG(0x4C)
+
+#define S3C2410_GPG0          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0)
+#define S3C2410_GPG0_INP      (0x00 << 0)
+#define S3C2410_GPG0_OUTP     (0x01 << 0)
+#define S3C2410_GPG0_EINT8    (0x02 << 0)
+#define S3C2400_GPG0_I2SLRCK  (0x02 << 0)
+
+#define S3C2410_GPG1          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1)
+#define S3C2410_GPG1_INP      (0x00 << 2)
+#define S3C2410_GPG1_OUTP     (0x01 << 2)
+#define S3C2410_GPG1_EINT9    (0x02 << 2)
+#define S3C2400_GPG1_I2SSCLK  (0x02 << 2)
+
+#define S3C2410_GPG2          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2)
+#define S3C2410_GPG2_INP      (0x00 << 4)
+#define S3C2410_GPG2_OUTP     (0x01 << 4)
+#define S3C2410_GPG2_EINT10   (0x02 << 4)
+#define S3C2410_GPG2_nSS0     (0x03 << 4)
+#define S3C2400_GPG2_CDCLK    (0x02 << 4)
+
+#define S3C2410_GPG3          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3)
+#define S3C2410_GPG3_INP      (0x00 << 6)
+#define S3C2410_GPG3_OUTP     (0x01 << 6)
+#define S3C2410_GPG3_EINT11   (0x02 << 6)
+#define S3C2410_GPG3_nSS1     (0x03 << 6)
+#define S3C2400_GPG3_I2SSDO   (0x02 << 6)
+#define S3C2400_GPG3_I2SSDI   (0x03 << 6)
+
+#define S3C2410_GPG4          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4)
+#define S3C2410_GPG4_INP      (0x00 << 8)
+#define S3C2410_GPG4_OUTP     (0x01 << 8)
+#define S3C2410_GPG4_EINT12   (0x02 << 8)
+#define S3C2400_GPG4_MMCCLK   (0x02 << 8)
+#define S3C2400_GPG4_I2SSDI   (0x03 << 8)
+#define S3C2410_GPG4_LCDPWREN (0x03 << 8)
+#define S3C2443_GPG4_LCDPWRDN (0x03 << 8)
+
+#define S3C2410_GPG5          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5)
+#define S3C2410_GPG5_INP      (0x00 << 10)
+#define S3C2410_GPG5_OUTP     (0x01 << 10)
+#define S3C2410_GPG5_EINT13   (0x02 << 10)
+#define S3C2400_GPG5_MMCCMD   (0x02 << 10)
+#define S3C2400_GPG5_IICSDA   (0x03 << 10)
+#define S3C2410_GPG5_SPIMISO1 (0x03 << 10)      /* not s3c2443 */
+
+#define S3C2410_GPG6          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6)
+#define S3C2410_GPG6_INP      (0x00 << 12)
+#define S3C2410_GPG6_OUTP     (0x01 << 12)
+#define S3C2410_GPG6_EINT14   (0x02 << 12)
+#define S3C2400_GPG6_MMCDAT   (0x02 << 12)
+#define S3C2400_GPG6_IICSCL   (0x03 << 12)
+#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)
+
+#define S3C2410_GPG7          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7)
+#define S3C2410_GPG7_INP      (0x00 << 14)
+#define S3C2410_GPG7_OUTP     (0x01 << 14)
+#define S3C2410_GPG7_EINT15   (0x02 << 14)
+#define S3C2410_GPG7_SPICLK1  (0x03 << 14)
+#define S3C2400_GPG7_SPIMISO  (0x02 << 14)
+#define S3C2400_GPG7_IICSDA   (0x03 << 14)
+
+#define S3C2410_GPG8          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8)
+#define S3C2410_GPG8_INP      (0x00 << 16)
+#define S3C2410_GPG8_OUTP     (0x01 << 16)
+#define S3C2410_GPG8_EINT16   (0x02 << 16)
+#define S3C2400_GPG8_SPIMOSI  (0x02 << 16)
+#define S3C2400_GPG8_IICSCL   (0x03 << 16)
+
+#define S3C2410_GPG9          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9)
+#define S3C2410_GPG9_INP      (0x00 << 18)
+#define S3C2410_GPG9_OUTP     (0x01 << 18)
+#define S3C2410_GPG9_EINT17   (0x02 << 18)
+#define S3C2400_GPG9_SPICLK   (0x02 << 18)
+#define S3C2400_GPG9_MMCCLK   (0x03 << 18)
+
+#define S3C2410_GPG10         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
+#define S3C2410_GPG10_INP     (0x00 << 20)
+#define S3C2410_GPG10_OUTP    (0x01 << 20)
+#define S3C2410_GPG10_EINT18  (0x02 << 20)
+
+#define S3C2410_GPG11         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 11)
+#define S3C2410_GPG11_INP     (0x00 << 22)
+#define S3C2410_GPG11_OUTP    (0x01 << 22)
+#define S3C2410_GPG11_EINT19  (0x02 << 22)
+#define S3C2410_GPG11_TCLK1   (0x03 << 22)
+#define S3C2443_GPG11_CF_nIREQ (0x03 << 22)
+
+#define S3C2410_GPG12         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 12)
+#define S3C2410_GPG12_INP     (0x00 << 24)
+#define S3C2410_GPG12_OUTP    (0x01 << 24)
+#define S3C2410_GPG12_EINT20  (0x02 << 24)
+#define S3C2410_GPG12_XMON    (0x03 << 24)
+#define S3C2442_GPG12_nSPICS0 (0x03 << 24)
+#define S3C2443_GPG12_nINPACK (0x03 << 24)
+
+#define S3C2410_GPG13         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13)
+#define S3C2410_GPG13_INP     (0x00 << 26)
+#define S3C2410_GPG13_OUTP    (0x01 << 26)
+#define S3C2410_GPG13_EINT21  (0x02 << 26)
+#define S3C2410_GPG13_nXPON   (0x03 << 26)
+#define S3C2443_GPG13_CF_nREG (0x03 << 26)
+
+#define S3C2410_GPG14         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 14)
+#define S3C2410_GPG14_INP     (0x00 << 28)
+#define S3C2410_GPG14_OUTP    (0x01 << 28)
+#define S3C2410_GPG14_EINT22  (0x02 << 28)
+#define S3C2410_GPG14_YMON    (0x03 << 28)
+#define S3C2443_GPG14_CF_RESET (0x03 << 28)
+
+#define S3C2410_GPG15         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 15)
+#define S3C2410_GPG15_INP     (0x00 << 30)
+#define S3C2410_GPG15_OUTP    (0x01 << 30)
+#define S3C2410_GPG15_EINT23  (0x02 << 30)
+#define S3C2410_GPG15_nYPON   (0x03 << 30)
+#define S3C2443_GPG15_CF_PWR  (0x03 << 30)
+
+#define S3C2410_GPG_PUPDIS(x)  (1<<(x))
+
+/* Port H consists of11 GPIO/serial/Misc pins
+ *
+ * GPGCON has 2 bits for each of the input pins on port F
+ *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
+ *
+ * pull up works like all other ports.
+*/
+
+#define S3C2410_GPHCON     S3C2410_GPIOREG(0x70)
+#define S3C2410_GPHDAT     S3C2410_GPIOREG(0x74)
+#define S3C2410_GPHUP      S3C2410_GPIOREG(0x78)
+
+#define S3C2410_GPH0        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 0)
+#define S3C2410_GPH0_INP    (0x00 << 0)
+#define S3C2410_GPH0_OUTP   (0x01 << 0)
+#define S3C2410_GPH0_nCTS0  (0x02 << 0)
+
+#define S3C2410_GPH1        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 1)
+#define S3C2410_GPH1_INP    (0x00 << 2)
+#define S3C2410_GPH1_OUTP   (0x01 << 2)
+#define S3C2410_GPH1_nRTS0  (0x02 << 2)
+
+#define S3C2410_GPH2        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 2)
+#define S3C2410_GPH2_INP    (0x00 << 4)
+#define S3C2410_GPH2_OUTP   (0x01 << 4)
+#define S3C2410_GPH2_TXD0   (0x02 << 4)
+
+#define S3C2410_GPH3        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 3)
+#define S3C2410_GPH3_INP    (0x00 << 6)
+#define S3C2410_GPH3_OUTP   (0x01 << 6)
+#define S3C2410_GPH3_RXD0   (0x02 << 6)
+
+#define S3C2410_GPH4        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 4)
+#define S3C2410_GPH4_INP    (0x00 << 8)
+#define S3C2410_GPH4_OUTP   (0x01 << 8)
+#define S3C2410_GPH4_TXD1   (0x02 << 8)
+
+#define S3C2410_GPH5        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 5)
+#define S3C2410_GPH5_INP    (0x00 << 10)
+#define S3C2410_GPH5_OUTP   (0x01 << 10)
+#define S3C2410_GPH5_RXD1   (0x02 << 10)
+
+#define S3C2410_GPH6        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 6)
+#define S3C2410_GPH6_INP    (0x00 << 12)
+#define S3C2410_GPH6_OUTP   (0x01 << 12)
+#define S3C2410_GPH6_TXD2   (0x02 << 12)
+#define S3C2410_GPH6_nRTS1  (0x03 << 12)
+
+#define S3C2410_GPH7        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 7)
+#define S3C2410_GPH7_INP    (0x00 << 14)
+#define S3C2410_GPH7_OUTP   (0x01 << 14)
+#define S3C2410_GPH7_RXD2   (0x02 << 14)
+#define S3C2410_GPH7_nCTS1  (0x03 << 14)
+
+#define S3C2410_GPH8        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 8)
+#define S3C2410_GPH8_INP    (0x00 << 16)
+#define S3C2410_GPH8_OUTP   (0x01 << 16)
+#define S3C2410_GPH8_UCLK   (0x02 << 16)
+
+#define S3C2410_GPH9          S3C2410_GPIONO(S3C2410_GPIO_BANKH, 9)
+#define S3C2410_GPH9_INP      (0x00 << 18)
+#define S3C2410_GPH9_OUTP     (0x01 << 18)
+#define S3C2410_GPH9_CLKOUT0  (0x02 << 18)
+#define S3C2442_GPH9_nSPICS0  (0x03 << 18)
+
+#define S3C2410_GPH10         S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10)
+#define S3C2410_GPH10_INP     (0x00 << 20)
+#define S3C2410_GPH10_OUTP    (0x01 << 20)
+#define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
+
+/* The S3C2412 and S3C2413 move the GPJ register set to after
+ * GPH, which means all registers after 0x80 are now offset by 0x10
+ * for the 2412/2413 from the 2410/2440/2442
+*/
+
+/* miscellaneous control */
+#define S3C2400_MISCCR     S3C2410_GPIOREG(0x54)
+#define S3C2410_MISCCR     S3C2410_GPIOREG(0x80)
+#define S3C2410_DCLKCON    S3C2410_GPIOREG(0x84)
+
+#define S3C24XX_DCLKCON    S3C24XX_GPIOREG2(0x84)
+
+/* see clock.h for dclk definitions */
+
+/* pullup control on databus */
+#define S3C2410_MISCCR_SPUCR_HEN    (0<<0)
+#define S3C2410_MISCCR_SPUCR_HDIS   (1<<0)
+#define S3C2410_MISCCR_SPUCR_LEN    (0<<1)
+#define S3C2410_MISCCR_SPUCR_LDIS   (1<<1)
+
+#define S3C2400_MISCCR_SPUCR_LEN    (0<<0)
+#define S3C2400_MISCCR_SPUCR_LDIS   (1<<0)
+#define S3C2400_MISCCR_SPUCR_HEN    (0<<1)
+#define S3C2400_MISCCR_SPUCR_HDIS   (1<<1)
+
+#define S3C2400_MISCCR_HZ_STOPEN    (0<<2)
+#define S3C2400_MISCCR_HZ_STOPPREV  (1<<2)
+
+#define S3C2410_MISCCR_USBDEV       (0<<3)
+#define S3C2410_MISCCR_USBHOST      (1<<3)
+
+#define S3C2410_MISCCR_CLK0_MPLL    (0<<4)
+#define S3C2410_MISCCR_CLK0_UPLL    (1<<4)
+#define S3C2410_MISCCR_CLK0_FCLK    (2<<4)
+#define S3C2410_MISCCR_CLK0_HCLK    (3<<4)
+#define S3C2410_MISCCR_CLK0_PCLK    (4<<4)
+#define S3C2410_MISCCR_CLK0_DCLK0   (5<<4)
+#define S3C2410_MISCCR_CLK0_MASK    (7<<4)
+
+#define S3C2412_MISCCR_CLK0_RTC     (2<<4)
+
+#define S3C2410_MISCCR_CLK1_MPLL    (0<<8)
+#define S3C2410_MISCCR_CLK1_UPLL    (1<<8)
+#define S3C2410_MISCCR_CLK1_FCLK    (2<<8)
+#define S3C2410_MISCCR_CLK1_HCLK    (3<<8)
+#define S3C2410_MISCCR_CLK1_PCLK    (4<<8)
+#define S3C2410_MISCCR_CLK1_DCLK1   (5<<8)
+#define S3C2410_MISCCR_CLK1_MASK    (7<<8)
+
+#define S3C2412_MISCCR_CLK1_CLKsrc  (0<<8)
+
+#define S3C2410_MISCCR_USBSUSPND0   (1<<12)
+#define S3C2410_MISCCR_USBSUSPND1   (1<<13)
+
+#define S3C2410_MISCCR_nRSTCON      (1<<16)
+
+#define S3C2410_MISCCR_nEN_SCLK0    (1<<17)
+#define S3C2410_MISCCR_nEN_SCLK1    (1<<18)
+#define S3C2410_MISCCR_nEN_SCLKE    (1<<19)     /* not 2412 */
+#define S3C2410_MISCCR_SDSLEEP      (7<<17)
+
+/* external interrupt control... */
+/* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7
+ * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15
+ * S3C2410_EXTINT2 -> irq sense control for EINT16..EINT23
+ *
+ * note S3C2410_EXTINT2 has filtering options for EINT16..EINT23
+ *
+ * Samsung datasheet p9-25
+*/
+#define S3C2400_EXTINT0    S3C2410_GPIOREG(0x58)
+#define S3C2410_EXTINT0    S3C2410_GPIOREG(0x88)
+#define S3C2410_EXTINT1    S3C2410_GPIOREG(0x8C)
+#define S3C2410_EXTINT2    S3C2410_GPIOREG(0x90)
+
+#define S3C24XX_EXTINT0    S3C24XX_GPIOREG2(0x88)
+#define S3C24XX_EXTINT1    S3C24XX_GPIOREG2(0x8C)
+#define S3C24XX_EXTINT2    S3C24XX_GPIOREG2(0x90)
+
+/* values for S3C2410_EXTINT0/1/2 */
+#define S3C2410_EXTINT_LOWLEV    (0x00)
+#define S3C2410_EXTINT_HILEV     (0x01)
+#define S3C2410_EXTINT_FALLEDGE  (0x02)
+#define S3C2410_EXTINT_RISEEDGE  (0x04)
+#define S3C2410_EXTINT_BOTHEDGE  (0x06)
+
+/* interrupt filtering conrrol for EINT16..EINT23 */
+#define S3C2410_EINFLT0    S3C2410_GPIOREG(0x94)
+#define S3C2410_EINFLT1    S3C2410_GPIOREG(0x98)
+#define S3C2410_EINFLT2    S3C2410_GPIOREG(0x9C)
+#define S3C2410_EINFLT3    S3C2410_GPIOREG(0xA0)
+
+#define S3C24XX_EINFLT0    S3C24XX_GPIOREG2(0x94)
+#define S3C24XX_EINFLT1    S3C24XX_GPIOREG2(0x98)
+#define S3C24XX_EINFLT2    S3C24XX_GPIOREG2(0x9C)
+#define S3C24XX_EINFLT3    S3C24XX_GPIOREG2(0xA0)
+
+/* values for interrupt filtering */
+#define S3C2410_EINTFLT_PCLK            (0x00)
+#define S3C2410_EINTFLT_EXTCLK          (1<<7)
+#define S3C2410_EINTFLT_WIDTHMSK(x)     ((x) & 0x3f)
+
+/* removed EINTxxxx defs from here, not meant for this */
+
+/* GSTATUS have miscellaneous information in them
+ *
+ * These move between s3c2410 and s3c2412 style systems.
+ */
+
+#define S3C2410_GSTATUS0   S3C2410_GPIOREG(0x0AC)
+#define S3C2410_GSTATUS1   S3C2410_GPIOREG(0x0B0)
+#define S3C2410_GSTATUS2   S3C2410_GPIOREG(0x0B4)
+#define S3C2410_GSTATUS3   S3C2410_GPIOREG(0x0B8)
+#define S3C2410_GSTATUS4   S3C2410_GPIOREG(0x0BC)
+
+#define S3C2412_GSTATUS0   S3C2410_GPIOREG(0x0BC)
+#define S3C2412_GSTATUS1   S3C2410_GPIOREG(0x0C0)
+#define S3C2412_GSTATUS2   S3C2410_GPIOREG(0x0C4)
+#define S3C2412_GSTATUS3   S3C2410_GPIOREG(0x0C8)
+#define S3C2412_GSTATUS4   S3C2410_GPIOREG(0x0CC)
+
+#define S3C24XX_GSTATUS0   S3C24XX_GPIOREG2(0x0AC)
+#define S3C24XX_GSTATUS1   S3C24XX_GPIOREG2(0x0B0)
+#define S3C24XX_GSTATUS2   S3C24XX_GPIOREG2(0x0B4)
+#define S3C24XX_GSTATUS3   S3C24XX_GPIOREG2(0x0B8)
+#define S3C24XX_GSTATUS4   S3C24XX_GPIOREG2(0x0BC)
+
+#define S3C2410_GSTATUS0_nWAIT     (1<<3)
+#define S3C2410_GSTATUS0_NCON      (1<<2)
+#define S3C2410_GSTATUS0_RnB       (1<<1)
+#define S3C2410_GSTATUS0_nBATTFLT  (1<<0)
+
+#define S3C2410_GSTATUS1_IDMASK    (0xffff0000)
+#define S3C2410_GSTATUS1_2410      (0x32410000)
+#define S3C2410_GSTATUS1_2412      (0x32412001)
+#define S3C2410_GSTATUS1_2440      (0x32440000)
+#define S3C2410_GSTATUS1_2442      (0x32440aaa)
+
+#define S3C2410_GSTATUS2_WTRESET   (1<<2)
+#define S3C2410_GSTATUS2_OFFRESET  (1<<1)
+#define S3C2410_GSTATUS2_PONRESET  (1<<0)
+
+/* open drain control register */
+#define S3C2400_OPENCR     S3C2410_GPIOREG(0x50)
+
+#define S3C2400_OPENCR_OPC_RXD1DIS  (0<<0)
+#define S3C2400_OPENCR_OPC_RXD1EN   (1<<0)
+#define S3C2400_OPENCR_OPC_TXD1DIS  (0<<1)
+#define S3C2400_OPENCR_OPC_TXD1EN   (1<<1)
+#define S3C2400_OPENCR_OPC_CMDDIS   (0<<2)
+#define S3C2400_OPENCR_OPC_CMDEN    (1<<2)
+#define S3C2400_OPENCR_OPC_DATDIS   (0<<3)
+#define S3C2400_OPENCR_OPC_DATEN    (1<<3)
+#define S3C2400_OPENCR_OPC_MISODIS  (0<<4)
+#define S3C2400_OPENCR_OPC_MISOEN   (1<<4)
+#define S3C2400_OPENCR_OPC_MOSIDIS  (0<<5)
+#define S3C2400_OPENCR_OPC_MOSIEN   (1<<5)
+
+/* 2412/2413 sleep configuration registers */
+
+#define S3C2412_GPBSLPCON       S3C2410_GPIOREG(0x1C)
+#define S3C2412_GPCSLPCON       S3C2410_GPIOREG(0x2C)
+#define S3C2412_GPDSLPCON       S3C2410_GPIOREG(0x3C)
+#define S3C2412_GPFSLPCON       S3C2410_GPIOREG(0x5C)
+#define S3C2412_GPGSLPCON       S3C2410_GPIOREG(0x6C)
+#define S3C2412_GPHSLPCON       S3C2410_GPIOREG(0x7C)
+
+/* definitions for each pin bit */
+#define S3C2412_GPIO_SLPCON_LOW  ( 0x00 )
+#define S3C2412_GPIO_SLPCON_HIGH ( 0x01 )
+#define S3C2412_GPIO_SLPCON_IN   ( 0x02 )
+#define S3C2412_GPIO_SLPCON_PULL ( 0x03 )
+
+#define S3C2412_SLPCON_LOW(x)   ( 0x00 << ((x) * 2))
+#define S3C2412_SLPCON_HIGH(x)  ( 0x01 << ((x) * 2))
+#define S3C2412_SLPCON_IN(x)    ( 0x02 << ((x) * 2))
+#define S3C2412_SLPCON_PULL(x)  ( 0x03 << ((x) * 2))
+#define S3C2412_SLPCON_EINT(x)  ( 0x02 << ((x) * 2))  /* only IRQ pins */
+#define S3C2412_SLPCON_MASK(x)  ( 0x03 << ((x) * 2))
+
+#define S3C2412_SLPCON_ALL_LOW  (0x0)
+#define S3C2412_SLPCON_ALL_HIGH (0x11111111 | 0x44444444)
+#define S3C2412_SLPCON_ALL_IN   (0x22222222 | 0x88888888)
+#define S3C2412_SLPCON_ALL_PULL (0x33333333)
+
+#endif  /* __ASM_ARCH_REGS_GPIO_H */
+
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h b/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h
new file mode 100644
index 000000000000..1202ca5e99f6
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h
@@ -0,0 +1,106 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-gpioj.h
+ *
+ * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
+ *                    http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2440 GPIO J register definitions
+*/
+
+
+#ifndef __ASM_ARCH_REGS_GPIOJ_H
+#define __ASM_ARCH_REGS_GPIOJ_H "gpioj"
+
+/* Port J consists of 13 GPIO/Camera pins
+ *
+ * GPJCON has 2 bits for each of the input pins on port F
+ *   00 = 0 input, 1 output, 2 Camera
+ *
+ * pull up works like all other ports.
+*/
+
+#define S3C2440_GPIO_BANKJ  (416)
+
+#define S3C2440_GPJCON      S3C2410_GPIOREG(0xd0)
+#define S3C2440_GPJDAT      S3C2410_GPIOREG(0xd4)
+#define S3C2440_GPJUP       S3C2410_GPIOREG(0xd8)
+
+#define S3C2413_GPJCON          S3C2410_GPIOREG(0x80)
+#define S3C2413_GPJDAT          S3C2410_GPIOREG(0x84)
+#define S3C2413_GPJUP           S3C2410_GPIOREG(0x88)
+#define S3C2413_GPJSLPCON       S3C2410_GPIOREG(0x8C)
+
+#define S3C2440_GPJ0            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 0)
+#define S3C2440_GPJ0_INP        (0x00 << 0)
+#define S3C2440_GPJ0_OUTP       (0x01 << 0)
+#define S3C2440_GPJ0_CAMDATA0   (0x02 << 0)
+
+#define S3C2440_GPJ1            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 1)
+#define S3C2440_GPJ1_INP        (0x00 << 2)
+#define S3C2440_GPJ1_OUTP       (0x01 << 2)
+#define S3C2440_GPJ1_CAMDATA1   (0x02 << 2)
+
+#define S3C2440_GPJ2            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 2)
+#define S3C2440_GPJ2_INP        (0x00 << 4)
+#define S3C2440_GPJ2_OUTP       (0x01 << 4)
+#define S3C2440_GPJ2_CAMDATA2   (0x02 << 4)
+
+#define S3C2440_GPJ3            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 3)
+#define S3C2440_GPJ3_INP        (0x00 << 6)
+#define S3C2440_GPJ3_OUTP       (0x01 << 6)
+#define S3C2440_GPJ3_CAMDATA3   (0x02 << 6)
+
+#define S3C2440_GPJ4            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 4)
+#define S3C2440_GPJ4_INP        (0x00 << 8)
+#define S3C2440_GPJ4_OUTP       (0x01 << 8)
+#define S3C2440_GPJ4_CAMDATA4   (0x02 << 8)
+
+#define S3C2440_GPJ5            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 5)
+#define S3C2440_GPJ5_INP        (0x00 << 10)
+#define S3C2440_GPJ5_OUTP       (0x01 << 10)
+#define S3C2440_GPJ5_CAMDATA5   (0x02 << 10)
+
+#define S3C2440_GPJ6            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 6)
+#define S3C2440_GPJ6_INP        (0x00 << 12)
+#define S3C2440_GPJ6_OUTP       (0x01 << 12)
+#define S3C2440_GPJ6_CAMDATA6   (0x02 << 12)
+
+#define S3C2440_GPJ7            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 7)
+#define S3C2440_GPJ7_INP        (0x00 << 14)
+#define S3C2440_GPJ7_OUTP       (0x01 << 14)
+#define S3C2440_GPJ7_CAMDATA7   (0x02 << 14)
+
+#define S3C2440_GPJ8            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 8)
+#define S3C2440_GPJ8_INP        (0x00 << 16)
+#define S3C2440_GPJ8_OUTP       (0x01 << 16)
+#define S3C2440_GPJ8_CAMPCLK    (0x02 << 16)
+
+#define S3C2440_GPJ9            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 9)
+#define S3C2440_GPJ9_INP        (0x00 << 18)
+#define S3C2440_GPJ9_OUTP       (0x01 << 18)
+#define S3C2440_GPJ9_CAMVSYNC   (0x02 << 18)
+
+#define S3C2440_GPJ10           S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 10)
+#define S3C2440_GPJ10_INP       (0x00 << 20)
+#define S3C2440_GPJ10_OUTP      (0x01 << 20)
+#define S3C2440_GPJ10_CAMHREF   (0x02 << 20)
+
+#define S3C2440_GPJ11           S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 11)
+#define S3C2440_GPJ11_INP       (0x00 << 22)
+#define S3C2440_GPJ11_OUTP      (0x01 << 22)
+#define S3C2440_GPJ11_CAMCLKOUT (0x02 << 22)
+
+#define S3C2440_GPJ12           S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 12)
+#define S3C2440_GPJ12_INP       (0x00 << 24)
+#define S3C2440_GPJ12_OUTP      (0x01 << 24)
+#define S3C2440_GPJ12_CAMRESET  (0x02 << 24)
+
+#define S3C2443_GPJ13           S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 13)
+#define S3C2443_GPJ14           S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 14)
+#define S3C2443_GPJ15           S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 15)
+
+#endif  /* __ASM_ARCH_REGS_GPIOJ_H */
+
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-irq.h b/arch/arm/mach-s3c2410/include/mach/regs-irq.h
new file mode 100644
index 000000000000..b057c06d167a
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/regs-irq.h
@@ -0,0 +1,43 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-irq.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ *                    http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+
+#ifndef ___ASM_ARCH_REGS_IRQ_H
+#define ___ASM_ARCH_REGS_IRQ_H "$Id: irq.h,v 1.3 2003/03/25 21:29:06 ben Exp $"
+
+/* interrupt controller */
+
+#define S3C2410_IRQREG(x)   ((x) + S3C24XX_VA_IRQ)
+#define S3C2410_EINTREG(x)  ((x) + S3C24XX_VA_GPIO)
+#define S3C24XX_EINTREG(x)  ((x) + S3C24XX_VA_GPIO2)
+
+#define S3C2410_SRCPND         S3C2410_IRQREG(0x000)
+#define S3C2410_INTMOD         S3C2410_IRQREG(0x004)
+#define S3C2410_INTMSK         S3C2410_IRQREG(0x008)
+#define S3C2410_PRIORITY       S3C2410_IRQREG(0x00C)
+#define S3C2410_INTPND         S3C2410_IRQREG(0x010)
+#define S3C2410_INTOFFSET      S3C2410_IRQREG(0x014)
+#define S3C2410_SUBSRCPND      S3C2410_IRQREG(0x018)
+#define S3C2410_INTSUBMSK      S3C2410_IRQREG(0x01C)
+
+/* mask: 0=enable, 1=disable
+ * 1 bit EINT, 4=EINT4, 23=EINT23
+ * EINT0,1,2,3 are not handled here.
+*/
+
+#define S3C2410_EINTMASK       S3C2410_EINTREG(0x0A4)
+#define S3C2410_EINTPEND       S3C2410_EINTREG(0X0A8)
+#define S3C2412_EINTMASK       S3C2410_EINTREG(0x0B4)
+#define S3C2412_EINTPEND       S3C2410_EINTREG(0X0B8)
+
+#define S3C24XX_EINTMASK       S3C24XX_EINTREG(0x0A4)
+#define S3C24XX_EINTPEND       S3C24XX_EINTREG(0X0A8)
+
+#endif /* ___ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-lcd.h b/arch/arm/mach-s3c2410/include/mach/regs-lcd.h
new file mode 100644
index 000000000000..893b8742f954
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/regs-lcd.h
@@ -0,0 +1,162 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-lcd.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ *                    http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+
+#ifndef ___ASM_ARCH_REGS_LCD_H
+#define ___ASM_ARCH_REGS_LCD_H "$Id: lcd.h,v 1.3 2003/06/26 13:25:06 ben Exp $"
+
+#define S3C2410_LCDREG(x)       (x)
+
+/* LCD control registers */
+#define S3C2410_LCDCON1     S3C2410_LCDREG(0x00)
+#define S3C2410_LCDCON2     S3C2410_LCDREG(0x04)
+#define S3C2410_LCDCON3     S3C2410_LCDREG(0x08)
+#define S3C2410_LCDCON4     S3C2410_LCDREG(0x0C)
+#define S3C2410_LCDCON5     S3C2410_LCDREG(0x10)
+
+#define S3C2410_LCDCON1_CLKVAL(x)  ((x) << 8)
+#define S3C2410_LCDCON1_MMODE      (1<<7)
+#define S3C2410_LCDCON1_DSCAN4     (0<<5)
+#define S3C2410_LCDCON1_STN4       (1<<5)
+#define S3C2410_LCDCON1_STN8       (2<<5)
+#define S3C2410_LCDCON1_TFT        (3<<5)
+
+#define S3C2410_LCDCON1_STN1BPP    (0<<1)
+#define S3C2410_LCDCON1_STN2GREY   (1<<1)
+#define S3C2410_LCDCON1_STN4GREY   (2<<1)
+#define S3C2410_LCDCON1_STN8BPP    (3<<1)
+#define S3C2410_LCDCON1_STN12BPP   (4<<1)
+
+#define S3C2410_LCDCON1_TFT1BPP    (8<<1)
+#define S3C2410_LCDCON1_TFT2BPP    (9<<1)
+#define S3C2410_LCDCON1_TFT4BPP    (10<<1)
+#define S3C2410_LCDCON1_TFT8BPP    (11<<1)
+#define S3C2410_LCDCON1_TFT16BPP   (12<<1)
+#define S3C2410_LCDCON1_TFT24BPP   (13<<1)
+
+#define S3C2410_LCDCON1_ENVID      (1)
+
+#define S3C2410_LCDCON1_MODEMASK    0x1E
+
+#define S3C2410_LCDCON2_VBPD(x)     ((x) << 24)
+#define S3C2410_LCDCON2_LINEVAL(x)  ((x) << 14)
+#define S3C2410_LCDCON2_VFPD(x)     ((x) << 6)
+#define S3C2410_LCDCON2_VSPW(x)     ((x) << 0)
+
+#define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF)
+#define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >>  6) & 0xFF)
+#define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >>  0) & 0x3F)
+
+#define S3C2410_LCDCON3_HBPD(x)     ((x) << 19)
+#define S3C2410_LCDCON3_WDLY(x)     ((x) << 19)
+#define S3C2410_LCDCON3_HOZVAL(x)   ((x) << 8)
+#define S3C2410_LCDCON3_HFPD(x)     ((x) << 0)
+#define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0)
+
+#define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F)
+#define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >>  0) & 0xFF)
+
+/* LDCCON4 changes for STN mode on the S3C2412 */
+
+#define S3C2410_LCDCON4_MVAL(x)     ((x) << 8)
+#define S3C2410_LCDCON4_HSPW(x)     ((x) << 0)
+#define S3C2410_LCDCON4_WLH(x)      ((x) << 0)
+
+#define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >>  0) & 0xFF)
+
+#define S3C2410_LCDCON5_BPP24BL     (1<<12)
+#define S3C2410_LCDCON5_FRM565      (1<<11)
+#define S3C2410_LCDCON5_INVVCLK     (1<<10)
+#define S3C2410_LCDCON5_INVVLINE    (1<<9)
+#define S3C2410_LCDCON5_INVVFRAME   (1<<8)
+#define S3C2410_LCDCON5_INVVD       (1<<7)
+#define S3C2410_LCDCON5_INVVDEN     (1<<6)
+#define S3C2410_LCDCON5_INVPWREN    (1<<5)
+#define S3C2410_LCDCON5_INVLEND     (1<<4)
+#define S3C2410_LCDCON5_PWREN       (1<<3)
+#define S3C2410_LCDCON5_ENLEND      (1<<2)
+#define S3C2410_LCDCON5_BSWP        (1<<1)
+#define S3C2410_LCDCON5_HWSWP       (1<<0)
+
+/* framebuffer start addressed */
+#define S3C2410_LCDSADDR1   S3C2410_LCDREG(0x14)
+#define S3C2410_LCDSADDR2   S3C2410_LCDREG(0x18)
+#define S3C2410_LCDSADDR3   S3C2410_LCDREG(0x1C)
+
+#define S3C2410_LCDBANK(x)      ((x) << 21)
+#define S3C2410_LCDBASEU(x)     (x)
+
+#define S3C2410_OFFSIZE(x)      ((x) << 11)
+#define S3C2410_PAGEWIDTH(x)    (x)
+
+/* colour lookup and miscellaneous controls */
+
+#define S3C2410_REDLUT     S3C2410_LCDREG(0x20)
+#define S3C2410_GREENLUT   S3C2410_LCDREG(0x24)
+#define S3C2410_BLUELUT    S3C2410_LCDREG(0x28)
+
+#define S3C2410_DITHMODE   S3C2410_LCDREG(0x4C)
+#define S3C2410_TPAL       S3C2410_LCDREG(0x50)
+
+#define S3C2410_TPAL_EN         (1<<24)
+
+/* interrupt info */
+#define S3C2410_LCDINTPND  S3C2410_LCDREG(0x54)
+#define S3C2410_LCDSRCPND  S3C2410_LCDREG(0x58)
+#define S3C2410_LCDINTMSK  S3C2410_LCDREG(0x5C)
+#define S3C2410_LCDINT_FIWSEL   (1<<2)
+#define S3C2410_LCDINT_FRSYNC   (1<<1)
+#define S3C2410_LCDINT_FICNT    (1<<0)
+
+/* s3c2442 extra stn registers */
+
+#define S3C2442_REDLUT          S3C2410_LCDREG(0x20)
+#define S3C2442_GREENLUT        S3C2410_LCDREG(0x24)
+#define S3C2442_BLUELUT         S3C2410_LCDREG(0x28)
+#define S3C2442_DITHMODE        S3C2410_LCDREG(0x20)
+
+#define S3C2410_LPCSEL     S3C2410_LCDREG(0x60)
+
+#define S3C2410_TFTPAL(x)  S3C2410_LCDREG((0x400 + (x)*4))
+
+/* S3C2412 registers */
+
+#define S3C2412_TPAL            S3C2410_LCDREG(0x20)
+
+#define S3C2412_LCDINTPND       S3C2410_LCDREG(0x24)
+#define S3C2412_LCDSRCPND       S3C2410_LCDREG(0x28)
+#define S3C2412_LCDINTMSK       S3C2410_LCDREG(0x2C)
+
+#define S3C2412_TCONSEL         S3C2410_LCDREG(0x30)
+
+#define S3C2412_LCDCON6         S3C2410_LCDREG(0x34)
+#define S3C2412_LCDCON7         S3C2410_LCDREG(0x38)
+#define S3C2412_LCDCON8         S3C2410_LCDREG(0x3C)
+#define S3C2412_LCDCON9         S3C2410_LCDREG(0x40)
+
+#define S3C2412_REDLUT(x)       S3C2410_LCDREG(0x44 + ((x)*4))
+#define S3C2412_GREENLUT(x)     S3C2410_LCDREG(0x60 + ((x)*4))
+#define S3C2412_BLUELUT(x)      S3C2410_LCDREG(0x98 + ((x)*4))
+
+#define S3C2412_FRCPAT(x)       S3C2410_LCDREG(0xB4 + ((x)*4))
+
+/* general registers */
+
+/* base of the LCD registers, where INTPND, INTSRC and then INTMSK
+ * are available. */
+
+#define S3C2410_LCDINTBASE      S3C2410_LCDREG(0x54)
+#define S3C2412_LCDINTBASE      S3C2410_LCDREG(0x24)
+
+#define S3C24XX_LCDINTPND       (0x00)
+#define S3C24XX_LCDSRCPND       (0x04)
+#define S3C24XX_LCDINTMSK       (0x08)
+
+#endif /* ___ASM_ARCH_REGS_LCD_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-mem.h
new file mode 100644
index 000000000000..f9926abd5cde
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/regs-mem.h
@@ -0,0 +1,220 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-mem.h
+ *
+ * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
+ *              http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 Memory Control register definitions
+*/
+
+#ifndef __ASM_ARM_MEMREGS_H
+#define __ASM_ARM_MEMREGS_H "$Id: regs.h,v 1.8 2003/05/01 15:55:41 ben Exp $"
+
+#ifndef S3C2410_MEMREG
+#define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
+#endif
+
+/* bus width, and wait state control */
+#define S3C2410_BWSCON                  S3C2410_MEMREG(0x0000)
+
+/* bank zero config - note, pinstrapped from OM pins! */
+#define S3C2410_BWSCON_DW0_16           (1<<1)
+#define S3C2410_BWSCON_DW0_32           (2<<1)
+
+/* bank one configs */
+#define S3C2410_BWSCON_DW1_8            (0<<4)
+#define S3C2410_BWSCON_DW1_16           (1<<4)
+#define S3C2410_BWSCON_DW1_32           (2<<4)
+#define S3C2410_BWSCON_WS1              (1<<6)
+#define S3C2410_BWSCON_ST1              (1<<7)
+
+/* bank 2 configurations */
+#define S3C2410_BWSCON_DW2_8            (0<<8)
+#define S3C2410_BWSCON_DW2_16           (1<<8)
+#define S3C2410_BWSCON_DW2_32           (2<<8)
+#define S3C2410_BWSCON_WS2              (1<<10)
+#define S3C2410_BWSCON_ST2              (1<<11)
+
+/* bank 3 configurations */
+#define S3C2410_BWSCON_DW3_8            (0<<12)
+#define S3C2410_BWSCON_DW3_16           (1<<12)
+#define S3C2410_BWSCON_DW3_32           (2<<12)
+#define S3C2410_BWSCON_WS3              (1<<14)
+#define S3C2410_BWSCON_ST3              (1<<15)
+
+/* bank 4 configurations */
+#define S3C2410_BWSCON_DW4_8            (0<<16)
+#define S3C2410_BWSCON_DW4_16           (1<<16)
+#define S3C2410_BWSCON_DW4_32           (2<<16)
+#define S3C2410_BWSCON_WS4              (1<<18)
+#define S3C2410_BWSCON_ST4              (1<<19)
+
+/* bank 5 configurations */
+#define S3C2410_BWSCON_DW5_8            (0<<20)
+#define S3C2410_BWSCON_DW5_16           (1<<20)
+#define S3C2410_BWSCON_DW5_32           (2<<20)
+#define S3C2410_BWSCON_WS5              (1<<22)
+#define S3C2410_BWSCON_ST5              (1<<23)
+
+/* bank 6 configurations */
+#define S3C2410_BWSCON_DW6_8            (0<<24)
+#define S3C2410_BWSCON_DW6_16           (1<<24)
+#define S3C2410_BWSCON_DW6_32           (2<<24)
+#define S3C2410_BWSCON_WS6              (1<<26)
+#define S3C2410_BWSCON_ST6              (1<<27)
+
+/* bank 7 configurations */
+#define S3C2410_BWSCON_DW7_8            (0<<28)
+#define S3C2410_BWSCON_DW7_16           (1<<28)
+#define S3C2410_BWSCON_DW7_32           (2<<28)
+#define S3C2410_BWSCON_WS7              (1<<30)
+#define S3C2410_BWSCON_ST7              (1<<31)
+
+/* memory set (rom, ram) */
+#define S3C2410_BANKCON0                S3C2410_MEMREG(0x0004)
+#define S3C2410_BANKCON1                S3C2410_MEMREG(0x0008)
+#define S3C2410_BANKCON2                S3C2410_MEMREG(0x000C)
+#define S3C2410_BANKCON3                S3C2410_MEMREG(0x0010)
+#define S3C2410_BANKCON4                S3C2410_MEMREG(0x0014)
+#define S3C2410_BANKCON5                S3C2410_MEMREG(0x0018)
+#define S3C2410_BANKCON6                S3C2410_MEMREG(0x001C)
+#define S3C2410_BANKCON7                S3C2410_MEMREG(0x0020)
+
+/* bank configuration registers */
+
+#define S3C2410_BANKCON_PMCnorm         (0x00)
+#define S3C2410_BANKCON_PMC4            (0x01)
+#define S3C2410_BANKCON_PMC8            (0x02)
+#define S3C2410_BANKCON_PMC16           (0x03)
+
+/* bank configurations for banks 0..7, note banks
+ * 6 and 7 have differnt configurations depending on
+ * the memory type bits */
+
+#define S3C2410_BANKCON_Tacp2           (0x0 << 2)
+#define S3C2410_BANKCON_Tacp3           (0x1 << 2)
+#define S3C2410_BANKCON_Tacp4           (0x2 << 2)
+#define S3C2410_BANKCON_Tacp6           (0x3 << 2)
+#define S3C2410_BANKCON_Tacp_SHIFT      (2)
+
+#define S3C2410_BANKCON_Tcah0           (0x0 << 4)
+#define S3C2410_BANKCON_Tcah1           (0x1 << 4)
+#define S3C2410_BANKCON_Tcah2           (0x2 << 4)
+#define S3C2410_BANKCON_Tcah4           (0x3 << 4)
+#define S3C2410_BANKCON_Tcah_SHIFT      (4)
+
+#define S3C2410_BANKCON_Tcoh0           (0x0 << 6)
+#define S3C2410_BANKCON_Tcoh1           (0x1 << 6)
+#define S3C2410_BANKCON_Tcoh2           (0x2 << 6)
+#define S3C2410_BANKCON_Tcoh4           (0x3 << 6)
+#define S3C2410_BANKCON_Tcoh_SHIFT      (6)
+
+#define S3C2410_BANKCON_Tacc1           (0x0 << 8)
+#define S3C2410_BANKCON_Tacc2           (0x1 << 8)
+#define S3C2410_BANKCON_Tacc3           (0x2 << 8)
+#define S3C2410_BANKCON_Tacc4           (0x3 << 8)
+#define S3C2410_BANKCON_Tacc6           (0x4 << 8)
+#define S3C2410_BANKCON_Tacc8           (0x5 << 8)
+#define S3C2410_BANKCON_Tacc10          (0x6 << 8)
+#define S3C2410_BANKCON_Tacc14          (0x7 << 8)
+#define S3C2410_BANKCON_Tacc_SHIFT      (8)
+
+#define S3C2410_BANKCON_Tcos0           (0x0 << 11)
+#define S3C2410_BANKCON_Tcos1           (0x1 << 11)
+#define S3C2410_BANKCON_Tcos2           (0x2 << 11)
+#define S3C2410_BANKCON_Tcos4           (0x3 << 11)
+#define S3C2410_BANKCON_Tcos_SHIFT      (11)
+
+#define S3C2410_BANKCON_Tacs0           (0x0 << 13)
+#define S3C2410_BANKCON_Tacs1           (0x1 << 13)
+#define S3C2410_BANKCON_Tacs2           (0x2 << 13)
+#define S3C2410_BANKCON_Tacs4           (0x3 << 13)
+#define S3C2410_BANKCON_Tacs_SHIFT      (13)
+
+#define S3C2410_BANKCON_SRAM            (0x0 << 15)
+#define S3C2400_BANKCON_EDODRAM         (0x2 << 15)
+#define S3C2410_BANKCON_SDRAM           (0x3 << 15)
+
+/* next bits only for EDO DRAM in 6,7 */
+#define S3C2400_BANKCON_EDO_Trcd1      (0x00 << 4)
+#define S3C2400_BANKCON_EDO_Trcd2      (0x01 << 4)
+#define S3C2400_BANKCON_EDO_Trcd3      (0x02 << 4)
+#define S3C2400_BANKCON_EDO_Trcd4      (0x03 << 4)
+
+/* CAS pulse width */
+#define S3C2400_BANKCON_EDO_PULSE1     (0x00 << 3)
+#define S3C2400_BANKCON_EDO_PULSE2     (0x01 << 3)
+
+/* CAS pre-charge */
+#define S3C2400_BANKCON_EDO_TCP1       (0x00 << 2)
+#define S3C2400_BANKCON_EDO_TCP2       (0x01 << 2)
+
+/* control column address select */
+#define S3C2400_BANKCON_EDO_SCANb8     (0x00 << 0)
+#define S3C2400_BANKCON_EDO_SCANb9     (0x01 << 0)
+#define S3C2400_BANKCON_EDO_SCANb10    (0x02 << 0)
+#define S3C2400_BANKCON_EDO_SCANb11    (0x03 << 0)
+
+/* next bits only for SDRAM in 6,7 */
+#define S3C2410_BANKCON_Trcd2           (0x00 << 2)
+#define S3C2410_BANKCON_Trcd3           (0x01 << 2)
+#define S3C2410_BANKCON_Trcd4           (0x02 << 2)
+
+/* control column address select */
+#define S3C2410_BANKCON_SCANb8          (0x00 << 0)
+#define S3C2410_BANKCON_SCANb9          (0x01 << 0)
+#define S3C2410_BANKCON_SCANb10         (0x02 << 0)
+
+#define S3C2410_REFRESH                 S3C2410_MEMREG(0x0024)
+#define S3C2410_BANKSIZE                S3C2410_MEMREG(0x0028)
+#define S3C2410_MRSRB6                  S3C2410_MEMREG(0x002C)
+#define S3C2410_MRSRB7                  S3C2410_MEMREG(0x0030)
+
+/* refresh control */
+
+#define S3C2410_REFRESH_REFEN           (1<<23)
+#define S3C2410_REFRESH_SELF            (1<<22)
+#define S3C2410_REFRESH_REFCOUNTER      ((1<<11)-1)
+
+#define S3C2410_REFRESH_TRP_MASK        (3<<20)
+#define S3C2410_REFRESH_TRP_2clk        (0<<20)
+#define S3C2410_REFRESH_TRP_3clk        (1<<20)
+#define S3C2410_REFRESH_TRP_4clk        (2<<20)
+
+#define S3C2400_REFRESH_DRAM_TRP_MASK   (3<<20)
+#define S3C2400_REFRESH_DRAM_TRP_1_5clk (0<<20)
+#define S3C2400_REFRESH_DRAM_TRP_2_5clk (1<<20)
+#define S3C2400_REFRESH_DRAM_TRP_3_5clk (2<<20)
+#define S3C2400_REFRESH_DRAM_TRP_4_5clk (3<<20)
+
+#define S3C2410_REFRESH_TSRC_MASK       (3<<18)
+#define S3C2410_REFRESH_TSRC_4clk       (0<<18)
+#define S3C2410_REFRESH_TSRC_5clk       (1<<18)
+#define S3C2410_REFRESH_TSRC_6clk       (2<<18)
+#define S3C2410_REFRESH_TSRC_7clk       (3<<18)
+
+
+/* mode select register(s) */
+
+#define  S3C2410_MRSRB_CL1              (0x00 << 4)
+#define  S3C2410_MRSRB_CL2              (0x02 << 4)
+#define  S3C2410_MRSRB_CL3              (0x03 << 4)
+
+/* bank size register */
+#define S3C2410_BANKSIZE_128M           (0x2 << 0)
+#define S3C2410_BANKSIZE_64M            (0x1 << 0)
+#define S3C2410_BANKSIZE_32M            (0x0 << 0)
+#define S3C2410_BANKSIZE_16M            (0x7 << 0)
+#define S3C2410_BANKSIZE_8M             (0x6 << 0)
+#define S3C2410_BANKSIZE_4M             (0x5 << 0)
+#define S3C2410_BANKSIZE_2M             (0x4 << 0)
+#define S3C2410_BANKSIZE_MASK           (0x7 << 0)
+#define S3C2400_BANKSIZE_MASK           (0x4 << 0)
+#define S3C2410_BANKSIZE_SCLK_EN        (1<<4)
+#define S3C2410_BANKSIZE_SCKE_EN        (1<<5)
+#define S3C2410_BANKSIZE_BURST          (1<<7)
+
+#endif /* __ASM_ARM_MEMREGS_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-power.h b/arch/arm/mach-s3c2410/include/mach/regs-power.h
new file mode 100644
index 000000000000..2d36353f57d7
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/regs-power.h
@@ -0,0 +1,40 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-power.h
+ *
+ * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk>
+ *                    http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C24XX power control register definitions
+*/
+
+#ifndef __ASM_ARM_REGS_PWR
+#define __ASM_ARM_REGS_PWR __FILE__
+
+#define S3C24XX_PWRREG(x) ((x) + S3C24XX_VA_CLKPWR)
+
+#define S3C2412_PWRMODECON      S3C24XX_PWRREG(0x20)
+#define S3C2412_PWRCFG          S3C24XX_PWRREG(0x24)
+
+#define S3C2412_INFORM0         S3C24XX_PWRREG(0x70)
+#define S3C2412_INFORM1         S3C24XX_PWRREG(0x74)
+#define S3C2412_INFORM2         S3C24XX_PWRREG(0x78)
+#define S3C2412_INFORM3         S3C24XX_PWRREG(0x7C)
+
+#define S3C2412_PWRCFG_BATF_IRQ                 (1<<0)
+#define S3C2412_PWRCFG_BATF_IGNORE              (2<<0)
+#define S3C2412_PWRCFG_BATF_SLEEP               (3<<0)
+#define S3C2412_PWRCFG_BATF_MASK                (3<<0)
+
+#define S3C2412_PWRCFG_STANDBYWFI_IGNORE        (0<<6)
+#define S3C2412_PWRCFG_STANDBYWFI_IDLE          (1<<6)
+#define S3C2412_PWRCFG_STANDBYWFI_STOP          (2<<6)
+#define S3C2412_PWRCFG_STANDBYWFI_SLEEP         (3<<6)
+#define S3C2412_PWRCFG_STANDBYWFI_MASK          (3<<6)
+
+#define S3C2412_PWRCFG_RTC_MASKIRQ              (1<<8)
+#define S3C2412_PWRCFG_NAND_NORST               (1<<9)
+
+#endif /* __ASM_ARM_REGS_PWR */
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h
new file mode 100644
index 000000000000..a4bf27123170
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h
@@ -0,0 +1,29 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2412 memory register definitions
+*/
+
+#ifndef __ASM_ARM_REGS_S3C2412_MEM
+#define __ASM_ARM_REGS_S3C2412_MEM
+
+#ifndef S3C2412_MEMREG
+#define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
+#endif
+
+#define S3C2412_BANKCFG                 S3C2412_MEMREG(0x00)
+#define S3C2412_BANKCON1                S3C2412_MEMREG(0x04)
+#define S3C2412_BANKCON2                S3C2412_MEMREG(0x08)
+#define S3C2412_BANKCON3                S3C2412_MEMREG(0x0C)
+
+#define S3C2412_REFRESH                 S3C2412_MEMREG(0x10)
+#define S3C2412_TIMEOUT                 S3C2412_MEMREG(0x14)
+
+#endif /*  __ASM_ARM_REGS_S3C2412_MEM */
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2412.h
new file mode 100644
index 000000000000..aa69dc79bc38
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2412.h
@@ -0,0 +1,23 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-s3c2412.h
+ *
+ * Copyright 2007 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2412 specific register definitions
+*/
+
+#ifndef __ASM_ARCH_REGS_S3C2412_H
+#define __ASM_ARCH_REGS_S3C2412_H "s3c2412"
+
+#define S3C2412_SWRST           (S3C24XX_VA_CLKPWR + 0x30)
+#define S3C2412_SWRST_RESET     (0x533C2412)
+
+/* see regs-power.h for the other registers in the power block. */
+
+#endif  /* __ASM_ARCH_REGS_S3C2412_H */
+
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
new file mode 100644
index 000000000000..7dd458363a51
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
@@ -0,0 +1,195 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
+ *
+ * Copyright (c) 2007 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2443 clock register definitions
+*/
+
+#ifndef __ASM_ARM_REGS_S3C2443_CLOCK
+#define __ASM_ARM_REGS_S3C2443_CLOCK
+
+#define S3C2443_CLKREG(x)               ((x) + S3C24XX_VA_CLKPWR)
+
+#define S3C2443_PLLCON_MDIVSHIFT        16
+#define S3C2443_PLLCON_PDIVSHIFT        8
+#define S3C2443_PLLCON_SDIVSHIFT        0
+#define S3C2443_PLLCON_MDIVMASK         ((1<<(1+(23-16)))-1)
+#define S3C2443_PLLCON_PDIVMASK         ((1<<(1+(9-8)))-1)
+#define S3C2443_PLLCON_SDIVMASK         (3)
+
+#define S3C2443_MPLLCON                 S3C2443_CLKREG(0x10)
+#define S3C2443_EPLLCON                 S3C2443_CLKREG(0x18)
+#define S3C2443_CLKSRC                  S3C2443_CLKREG(0x20)
+#define S3C2443_CLKDIV0                 S3C2443_CLKREG(0x24)
+#define S3C2443_CLKDIV1                 S3C2443_CLKREG(0x28)
+#define S3C2443_HCLKCON                 S3C2443_CLKREG(0x30)
+#define S3C2443_PCLKCON                 S3C2443_CLKREG(0x34)
+#define S3C2443_SCLKCON                 S3C2443_CLKREG(0x38)
+#define S3C2443_PWRMODE                 S3C2443_CLKREG(0x40)
+#define S3C2443_SWRST                   S3C2443_CLKREG(0x44)
+#define S3C2443_BUSPRI0                 S3C2443_CLKREG(0x50)
+#define S3C2443_SYSID                   S3C2443_CLKREG(0x5C)
+#define S3C2443_PWRCFG                  S3C2443_CLKREG(0x60)
+#define S3C2443_RSTCON                  S3C2443_CLKREG(0x64)
+
+#define S3C2443_SWRST_RESET             (0x533c2443)
+
+#define S3C2443_PLLCON_OFF              (1<<24)
+
+#define S3C2443_CLKSRC_I2S_EXT          (1<<14)
+#define S3C2443_CLKSRC_I2S_EPLLDIV      (0<<14)
+#define S3C2443_CLKSRC_I2S_EPLLREF      (2<<14)
+#define S3C2443_CLKSRC_I2S_EPLLREF3     (3<<14)
+#define S3C2443_CLKSRC_I2S_MASK         (3<<14)
+
+#define S3C2443_CLKSRC_EPLLREF_XTAL     (2<<8)
+#define S3C2443_CLKSRC_EPLLREF_EXTCLK   (3<<8)
+#define S3C2443_CLKSRC_EPLLREF_MPLLREF  (0<<8)
+#define S3C2443_CLKSRC_EPLLREF_MPLLREF2 (1<<8)
+#define S3C2443_CLKSRC_EPLLREF_MASK     (3<<8)
+
+#define S3C2443_CLKSRC_ESYSCLK_EPLL     (1<<6)
+#define S3C2443_CLKSRC_MSYSCLK_MPLL     (1<<4)
+#define S3C2443_CLKSRC_EXTCLK_DIV       (1<<3)
+
+#define S3C2443_CLKDIV0_DVS             (1<<13)
+#define S3C2443_CLKDIV0_HALF_HCLK       (1<<3)
+#define S3C2443_CLKDIV0_HALF_PCLK       (1<<2)
+
+#define S3C2443_CLKDIV0_HCLKDIV_MASK    (3<<0)
+
+#define S3C2443_CLKDIV0_EXTDIV_MASK     (3<<6)
+#define S3C2443_CLKDIV0_EXTDIV_SHIFT    (6)
+
+#define S3C2443_CLKDIV0_PREDIV_MASK     (3<<4)
+#define S3C2443_CLKDIV0_PREDIV_SHIFT    (4)
+
+#define S3C2443_CLKDIV0_ARMDIV_MASK     (15<<9)
+#define S3C2443_CLKDIV0_ARMDIV_SHIFT    (9)
+#define S3C2443_CLKDIV0_ARMDIV_1        (0<<9)
+#define S3C2443_CLKDIV0_ARMDIV_2        (8<<9)
+#define S3C2443_CLKDIV0_ARMDIV_3        (2<<9)
+#define S3C2443_CLKDIV0_ARMDIV_4        (9<<9)
+#define S3C2443_CLKDIV0_ARMDIV_6        (10<<9)
+#define S3C2443_CLKDIV0_ARMDIV_8        (11<<9)
+#define S3C2443_CLKDIV0_ARMDIV_12       (13<<9)
+#define S3C2443_CLKDIV0_ARMDIV_16       (15<<9)
+
+/* S3C2443_CLKDIV1 */
+
+#define S3C2443_CLKDIV1_CAMDIV_MASK     (15<<26)
+#define S3C2443_CLKDIV1_CAMDIV_SHIFT    (26)
+
+#define S3C2443_CLKDIV1_HSSPIDIV_MASK   (3<<24)
+#define S3C2443_CLKDIV1_HSSPIDIV_SHIFT  (24)
+
+#define S3C2443_CLKDIV1_DISPDIV_MASK    (0xff<<16)
+#define S3C2443_CLKDIV1_DISPDIV_SHIFT   (16)
+
+#define S3C2443_CLKDIV1_I2SDIV_MASK     (15<<12)
+#define S3C2443_CLKDIV1_I2SDIV_SHIFT    (12)
+
+#define S3C2443_CLKDIV1_UARTDIV_MASK    (15<<8)
+#define S3C2443_CLKDIV1_UARTDIV_SHIFT   (8)
+
+#define S3C2443_CLKDIV1_HSMMCDIV_MASK   (3<<6)
+#define S3C2443_CLKDIV1_HSMMCDIV_SHIFT  (6)
+
+#define S3C2443_CLKDIV1_USBHOSTDIV_MASK (3<<4)
+#define S3C2443_CLKDIV1_USBHOSTDIV_SHIFT (4)
+
+#define S3C2443_CLKCON_NAND
+
+#define S3C2443_HCLKCON_DMA0            (1<<0)
+#define S3C2443_HCLKCON_DMA1            (1<<1)
+#define S3C2443_HCLKCON_DMA2            (1<<2)
+#define S3C2443_HCLKCON_DMA3            (1<<3)
+#define S3C2443_HCLKCON_DMA4            (1<<4)
+#define S3C2443_HCLKCON_DMA5            (1<<5)
+#define S3C2443_HCLKCON_CAMIF           (1<<8)
+#define S3C2443_HCLKCON_DISP            (1<<9)
+#define S3C2443_HCLKCON_LCDC            (1<<10)
+#define S3C2443_HCLKCON_USBH            (1<<11)
+#define S3C2443_HCLKCON_USBD            (1<<12)
+#define S3C2443_HCLKCON_HSMMC           (1<<16)
+#define S3C2443_HCLKCON_CFC             (1<<17)
+#define S3C2443_HCLKCON_SSMC            (1<<18)
+#define S3C2443_HCLKCON_DRAMC           (1<<19)
+
+#define S3C2443_PCLKCON_UART0           (1<<0)
+#define S3C2443_PCLKCON_UART1           (1<<1)
+#define S3C2443_PCLKCON_UART2           (1<<2)
+#define S3C2443_PCLKCON_UART3           (1<<3)
+#define S3C2443_PCLKCON_IIC             (1<<4)
+#define S3C2443_PCLKCON_SDI             (1<<5)
+#define S3C2443_PCLKCON_ADC             (1<<7)
+#define S3C2443_PCLKCON_AC97            (1<<8)
+#define S3C2443_PCLKCON_IIS             (1<<9)
+#define S3C2443_PCLKCON_PWMT            (1<<10)
+#define S3C2443_PCLKCON_WDT             (1<<11)
+#define S3C2443_PCLKCON_RTC             (1<<12)
+#define S3C2443_PCLKCON_GPIO            (1<<13)
+#define S3C2443_PCLKCON_SPI0            (1<<14)
+#define S3C2443_PCLKCON_SPI1            (1<<15)
+
+#define S3C2443_SCLKCON_DDRCLK          (1<<16)
+#define S3C2443_SCLKCON_SSMCCLK         (1<<15)
+#define S3C2443_SCLKCON_HSSPICLK        (1<<14)
+#define S3C2443_SCLKCON_HSMMCCLK_EXT    (1<<13)
+#define S3C2443_SCLKCON_HSMMCCLK_EPLL   (1<<12)
+#define S3C2443_SCLKCON_CAMCLK          (1<<11)
+#define S3C2443_SCLKCON_DISPCLK         (1<<10)
+#define S3C2443_SCLKCON_I2SCLK          (1<<9)
+#define S3C2443_SCLKCON_UARTCLK         (1<<8)
+#define S3C2443_SCLKCON_USBHOST         (1<<1)
+
+#include <asm/div64.h>
+
+static inline unsigned int
+s3c2443_get_mpll(unsigned int pllval, unsigned int baseclk)
+{
+        unsigned int mdiv, pdiv, sdiv;
+        uint64_t fvco;
+
+        mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT;
+        pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT;
+        sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT;
+
+        mdiv &= S3C2443_PLLCON_MDIVMASK;
+        pdiv &= S3C2443_PLLCON_PDIVMASK;
+        sdiv &= S3C2443_PLLCON_SDIVMASK;
+
+        fvco = (uint64_t)baseclk * (2 * (mdiv + 8));
+        do_div(fvco, pdiv << sdiv);
+
+        return (unsigned int)fvco;
+}
+
+static inline unsigned int
+s3c2443_get_epll(unsigned int pllval, unsigned int baseclk)
+{
+        unsigned int mdiv, pdiv, sdiv;
+        uint64_t fvco;
+
+        mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT;
+        pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT;
+        sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT;
+
+        mdiv &= S3C2443_PLLCON_MDIVMASK;
+        pdiv &= S3C2443_PLLCON_PDIVMASK;
+        sdiv &= S3C2443_PLLCON_SDIVMASK;
+
+        fvco = (uint64_t)baseclk * (mdiv + 8);
+        do_div(fvco, (pdiv + 2) << sdiv);
+
+        return (unsigned int)fvco;
+}
+
+#endif /*  __ASM_ARM_REGS_S3C2443_CLOCK */
+
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-sdi.h b/arch/arm/mach-s3c2410/include/mach/regs-sdi.h
new file mode 100644
index 000000000000..cbf2d8884e30
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/regs-sdi.h
@@ -0,0 +1,127 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-sdi.h
+ *
+ * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
+ *                    http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 MMC/SDIO register definitions
+*/
+
+#ifndef __ASM_ARM_REGS_SDI
+#define __ASM_ARM_REGS_SDI "regs-sdi.h"
+
+#define S3C2410_SDICON                (0x00)
+#define S3C2410_SDIPRE                (0x04)
+#define S3C2410_SDICMDARG             (0x08)
+#define S3C2410_SDICMDCON             (0x0C)
+#define S3C2410_SDICMDSTAT            (0x10)
+#define S3C2410_SDIRSP0               (0x14)
+#define S3C2410_SDIRSP1               (0x18)
+#define S3C2410_SDIRSP2               (0x1C)
+#define S3C2410_SDIRSP3               (0x20)
+#define S3C2410_SDITIMER              (0x24)
+#define S3C2410_SDIBSIZE              (0x28)
+#define S3C2410_SDIDCON               (0x2C)
+#define S3C2410_SDIDCNT               (0x30)
+#define S3C2410_SDIDSTA               (0x34)
+#define S3C2410_SDIFSTA               (0x38)
+
+#define S3C2410_SDIDATA               (0x3C)
+#define S3C2410_SDIIMSK               (0x40)
+
+#define S3C2440_SDIDATA               (0x40)
+#define S3C2440_SDIIMSK               (0x3C)
+
+#define S3C2440_SDICON_SDRESET        (1<<8)
+#define S3C2440_SDICON_MMCCLOCK       (1<<5)
+#define S3C2410_SDICON_BYTEORDER      (1<<4)
+#define S3C2410_SDICON_SDIOIRQ        (1<<3)
+#define S3C2410_SDICON_RWAITEN        (1<<2)
+#define S3C2410_SDICON_FIFORESET      (1<<1)
+#define S3C2410_SDICON_CLOCKTYPE      (1<<0)
+
+#define S3C2410_SDICMDCON_ABORT       (1<<12)
+#define S3C2410_SDICMDCON_WITHDATA    (1<<11)
+#define S3C2410_SDICMDCON_LONGRSP     (1<<10)
+#define S3C2410_SDICMDCON_WAITRSP     (1<<9)
+#define S3C2410_SDICMDCON_CMDSTART    (1<<8)
+#define S3C2410_SDICMDCON_SENDERHOST  (1<<6)
+#define S3C2410_SDICMDCON_INDEX       (0x3f)
+
+#define S3C2410_SDICMDSTAT_CRCFAIL    (1<<12)
+#define S3C2410_SDICMDSTAT_CMDSENT    (1<<11)
+#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1<<10)
+#define S3C2410_SDICMDSTAT_RSPFIN     (1<<9)
+#define S3C2410_SDICMDSTAT_XFERING    (1<<8)
+#define S3C2410_SDICMDSTAT_INDEX      (0xff)
+
+#define S3C2440_SDIDCON_DS_BYTE       (0<<22)
+#define S3C2440_SDIDCON_DS_HALFWORD   (1<<22)
+#define S3C2440_SDIDCON_DS_WORD       (2<<22)
+#define S3C2410_SDIDCON_IRQPERIOD     (1<<21)
+#define S3C2410_SDIDCON_TXAFTERRESP   (1<<20)
+#define S3C2410_SDIDCON_RXAFTERCMD    (1<<19)
+#define S3C2410_SDIDCON_BUSYAFTERCMD  (1<<18)
+#define S3C2410_SDIDCON_BLOCKMODE     (1<<17)
+#define S3C2410_SDIDCON_WIDEBUS       (1<<16)
+#define S3C2410_SDIDCON_DMAEN         (1<<15)
+#define S3C2410_SDIDCON_STOP          (1<<14)
+#define S3C2440_SDIDCON_DATSTART      (1<<14)
+#define S3C2410_SDIDCON_DATMODE       (3<<12)
+#define S3C2410_SDIDCON_BLKNUM        (0x7ff)
+
+/* constants for S3C2410_SDIDCON_DATMODE */
+#define S3C2410_SDIDCON_XFER_READY    (0<<12)
+#define S3C2410_SDIDCON_XFER_CHKSTART (1<<12)
+#define S3C2410_SDIDCON_XFER_RXSTART  (2<<12)
+#define S3C2410_SDIDCON_XFER_TXSTART  (3<<12)
+
+#define S3C2410_SDIDCON_BLKNUM_MASK   (0xFFF)
+#define S3C2410_SDIDCNT_BLKNUM_SHIFT  (12)
+
+#define S3C2410_SDIDSTA_RDYWAITREQ    (1<<10)
+#define S3C2410_SDIDSTA_SDIOIRQDETECT (1<<9)
+#define S3C2410_SDIDSTA_FIFOFAIL      (1<<8)    /* reserved on 2440 */
+#define S3C2410_SDIDSTA_CRCFAIL       (1<<7)
+#define S3C2410_SDIDSTA_RXCRCFAIL     (1<<6)
+#define S3C2410_SDIDSTA_DATATIMEOUT   (1<<5)
+#define S3C2410_SDIDSTA_XFERFINISH    (1<<4)
+#define S3C2410_SDIDSTA_BUSYFINISH    (1<<3)
+#define S3C2410_SDIDSTA_SBITERR       (1<<2)    /* reserved on 2410a/2440 */
+#define S3C2410_SDIDSTA_TXDATAON      (1<<1)
+#define S3C2410_SDIDSTA_RXDATAON      (1<<0)
+
+#define S3C2440_SDIFSTA_FIFORESET      (1<<16)
+#define S3C2440_SDIFSTA_FIFOFAIL       (3<<14)  /* 3 is correct (2 bits) */
+#define S3C2410_SDIFSTA_TFDET          (1<<13)
+#define S3C2410_SDIFSTA_RFDET          (1<<12)
+#define S3C2410_SDIFSTA_TFHALF         (1<<11)
+#define S3C2410_SDIFSTA_TFEMPTY        (1<<10)
+#define S3C2410_SDIFSTA_RFLAST         (1<<9)
+#define S3C2410_SDIFSTA_RFFULL         (1<<8)
+#define S3C2410_SDIFSTA_RFHALF         (1<<7)
+#define S3C2410_SDIFSTA_COUNTMASK      (0x7f)
+
+#define S3C2410_SDIIMSK_RESPONSECRC    (1<<17)
+#define S3C2410_SDIIMSK_CMDSENT        (1<<16)
+#define S3C2410_SDIIMSK_CMDTIMEOUT     (1<<15)
+#define S3C2410_SDIIMSK_RESPONSEND     (1<<14)
+#define S3C2410_SDIIMSK_READWAIT       (1<<13)
+#define S3C2410_SDIIMSK_SDIOIRQ        (1<<12)
+#define S3C2410_SDIIMSK_FIFOFAIL       (1<<11)
+#define S3C2410_SDIIMSK_CRCSTATUS      (1<<10)
+#define S3C2410_SDIIMSK_DATACRC        (1<<9)
+#define S3C2410_SDIIMSK_DATATIMEOUT    (1<<8)
+#define S3C2410_SDIIMSK_DATAFINISH     (1<<7)
+#define S3C2410_SDIIMSK_BUSYFINISH     (1<<6)
+#define S3C2410_SDIIMSK_SBITERR        (1<<5)   /* reserved 2440/2410a */
+#define S3C2410_SDIIMSK_TXFIFOHALF     (1<<4)
+#define S3C2410_SDIIMSK_TXFIFOEMPTY    (1<<3)
+#define S3C2410_SDIIMSK_RXFIFOLAST     (1<<2)
+#define S3C2410_SDIIMSK_RXFIFOFULL     (1<<1)
+#define S3C2410_SDIIMSK_RXFIFOHALF     (1<<0)
+
+#endif /* __ASM_ARM_REGS_SDI */
diff --git a/arch/arm/mach-s3c2410/include/mach/reset.h b/arch/arm/mach-s3c2410/include/mach/reset.h
new file mode 100644
index 000000000000..f8c9387b049d
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/reset.h
@@ -0,0 +1,22 @@
+/* arch/arm/mach-s3c2410/include/mach/reset.h
+ *
+ * Copyright (c) 2007 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 CPU reset controls
+*/
+
+#ifndef __ASM_ARCH_RESET_H
+#define __ASM_ARCH_RESET_H __FILE__
+
+/* This allows the over-ride of the default reset code
+*/
+
+extern void (*s3c24xx_reset_hook)(void);
+
+#endif /* __ASM_ARCH_RESET_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/spi-gpio.h b/arch/arm/mach-s3c2410/include/mach/spi-gpio.h
new file mode 100644
index 000000000000..3fe8be9ca110
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/spi-gpio.h
@@ -0,0 +1,27 @@
+/* arch/arm/mach-s3c2410/include/mach/spi-gpio.h
+ *
+ * Copyright (c) 2006 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - SPI Controller platfrom_device info
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_SPIGPIO_H
+#define __ASM_ARCH_SPIGPIO_H __FILE__
+
+struct s3c2410_spigpio_info {
+        unsigned long            pin_clk;
+        unsigned long            pin_mosi;
+        unsigned long            pin_miso;
+
+        int                      bus_num;
+
+        void (*chip_select)(struct s3c2410_spigpio_info *spi, int cs);
+};
+
+
+#endif /* __ASM_ARCH_SPIGPIO_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/spi.h b/arch/arm/mach-s3c2410/include/mach/spi.h
new file mode 100644
index 000000000000..921b13b4f0a0
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/spi.h
@@ -0,0 +1,25 @@
+/* arch/arm/mach-s3c2410/include/mach/spi.h
+ *
+ * Copyright (c) 2006 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - SPI Controller platform_device info
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_SPI_H
+#define __ASM_ARCH_SPI_H __FILE__
+
+struct s3c2410_spi_info {
+        unsigned long            pin_cs;        /* simple gpio cs */
+        unsigned int             num_cs;        /* total chipselects */
+        int                      bus_num;       /* bus number to use. */
+
+        void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol);
+};
+
+
+#endif /* __ASM_ARCH_SPI_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/system-reset.h b/arch/arm/mach-s3c2410/include/mach/system-reset.h
new file mode 100644
index 000000000000..ec2defebf0d5
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/system-reset.h
@@ -0,0 +1,64 @@
+/* arch/arm/mach-s3c2410/include/mach/system-reset.h
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - System define for arch_reset() function
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <mach/hardware.h>
+#include <asm/io.h>
+
+#include <asm/plat-s3c/regs-watchdog.h>
+#include <mach/regs-clock.h>
+
+#include <linux/clk.h>
+#include <linux/err.h>
+
+extern void (*s3c24xx_reset_hook)(void);
+
+static void
+arch_reset(char mode)
+{
+        struct clk *wdtclk;
+
+        if (mode == 's') {
+                cpu_reset(0);
+        }
+
+        if (s3c24xx_reset_hook)
+                s3c24xx_reset_hook();
+
+        printk("arch_reset: attempting watchdog reset\n");
+
+        __raw_writel(0, S3C2410_WTCON);   /* disable watchdog, to be safe  */
+
+        wdtclk = clk_get(NULL, "watchdog");
+        if (!IS_ERR(wdtclk)) {
+                clk_enable(wdtclk);
+        } else
+                printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
+
+        /* put initial values into count and data */
+        __raw_writel(0x80, S3C2410_WTCNT);
+        __raw_writel(0x80, S3C2410_WTDAT);
+
+        /* set the watchdog to go and reset... */
+        __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
+                     S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON);
+
+        /* wait for reset to assert... */
+        mdelay(500);
+
+        printk(KERN_ERR "Watchdog reset failed to assert reset\n");
+
+        /* delay to allow the serial port to show the message */
+        mdelay(50);
+
+        /* we'll take a jump through zero as a poor second */
+        cpu_reset(0);
+}
diff --git a/arch/arm/mach-s3c2410/include/mach/system.h b/arch/arm/mach-s3c2410/include/mach/system.h
new file mode 100644
index 000000000000..e9f676bc0116
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/system.h
@@ -0,0 +1,58 @@
+/* arch/arm/mach-s3c2410/include/mach/system.h
+ *
+ * Copyright (c) 2003 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - System function defines and includes
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <mach/hardware.h>
+#include <asm/io.h>
+
+#include <mach/map.h>
+#include <mach/idle.h>
+#include <mach/reset.h>
+
+#include <mach/regs-clock.h>
+
+void (*s3c24xx_idle)(void);
+void (*s3c24xx_reset_hook)(void);
+
+void s3c24xx_default_idle(void)
+{
+        unsigned long tmp;
+        int i;
+
+        /* idle the system by using the idle mode which will wait for an
+         * interrupt to happen before restarting the system.
+         */
+
+        /* Warning: going into idle state upsets jtag scanning */
+
+        __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
+                     S3C2410_CLKCON);
+
+        /* the samsung port seems to do a loop and then unset idle.. */
+        for (i = 0; i < 50; i++) {
+                tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
+        }
+
+        /* this bit is not cleared on re-start... */
+
+        __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
+                     S3C2410_CLKCON);
+}
+
+static void arch_idle(void)
+{
+        if (s3c24xx_idle != NULL)
+                (s3c24xx_idle)();
+        else
+                s3c24xx_default_idle();
+}
+
+#include <mach/system-reset.h>
diff --git a/arch/arm/mach-s3c2410/include/mach/timex.h b/arch/arm/mach-s3c2410/include/mach/timex.h
new file mode 100644
index 000000000000..2a425ed0a7e0
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/timex.h
@@ -0,0 +1,26 @@
+/* arch/arm/mach-s3c2410/include/mach/timex.h
+ *
+ * Copyright (c) 2003-2005 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - time parameters
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+
+/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
+ * a variable is useless. It seems as long as we make our timers an
+ * exact multiple of HZ, any value that makes a 1->1 correspondence
+ * for the time conversion functions to/from jiffies is acceptable.
+*/
+
+
+#define CLOCK_TICK_RATE 12000000
+
+
+#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/uncompress.h b/arch/arm/mach-s3c2410/include/mach/uncompress.h
new file mode 100644
index 000000000000..708e47459ffc
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/uncompress.h
@@ -0,0 +1,52 @@
+/* arch/arm/mach-s3c2410/include/mach/uncompress.h
+ *
+ * Copyright (c) 2003, 2007 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - uncompress code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+
+#include <mach/regs-gpio.h>
+#include <mach/map.h>
+
+/* working in physical space... */
+#undef S3C2410_GPIOREG
+#define S3C2410_GPIOREG(x) ((S3C24XX_PA_GPIO + (x)))
+
+#include <asm/plat-s3c/uncompress.h>
+
+static inline int is_arm926(void)
+{
+        unsigned int cpuid;
+
+        asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (cpuid));
+
+        return ((cpuid & 0xff0) == 0x260);
+}
+
+static void arch_detect_cpu(void)
+{
+        unsigned int cpuid;
+
+        cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1);
+        cpuid &= S3C2410_GSTATUS1_IDMASK;
+
+        if (is_arm926() || cpuid == S3C2410_GSTATUS1_2440 ||
+            cpuid == S3C2410_GSTATUS1_2442) {
+                fifo_mask = S3C2440_UFSTAT_TXMASK;
+                fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
+        } else {
+                fifo_mask = S3C2410_UFSTAT_TXMASK;
+                fifo_max = 15 << S3C2410_UFSTAT_TXSHIFT;
+        }
+}
+
+#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/usb-control.h b/arch/arm/mach-s3c2410/include/mach/usb-control.h
new file mode 100644
index 000000000000..cd91d1591f31
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/usb-control.h
@@ -0,0 +1,41 @@
+/* arch/arm/mach-s3c2410/include/mach/usb-control.h
+ *
+ * Copyright (c) 2004 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - usb port information
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_USBCONTROL_H
+#define __ASM_ARCH_USBCONTROL_H "arch/arm/mach-s3c2410/include/mach/usb-control.h"
+
+#define S3C_HCDFLG_USED (1)
+
+struct s3c2410_hcd_port {
+        unsigned char   flags;
+        unsigned char   power;
+        unsigned char   oc_status;
+        unsigned char   oc_changed;
+};
+
+struct s3c2410_hcd_info {
+        struct usb_hcd          *hcd;
+        struct s3c2410_hcd_port port[2];
+
+        void            (*power_control)(int port, int to);
+        void            (*enable_oc)(struct s3c2410_hcd_info *, int on);
+        void            (*report_oc)(struct s3c2410_hcd_info *, int ports);
+};
+
+static void inline s3c2410_usb_report_oc(struct s3c2410_hcd_info *info, int ports)
+{
+        if (info->report_oc != NULL) {
+                (info->report_oc)(info, ports);
+        }
+}
+
+#endif /*__ASM_ARCH_USBCONTROL_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/vmalloc.h b/arch/arm/mach-s3c2410/include/mach/vmalloc.h
new file mode 100644
index 000000000000..315b0078a34d
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/vmalloc.h
@@ -0,0 +1,20 @@
+/* arch/arm/mach-s3c2410/include/mach/vmalloc.h
+ *
+ * from arch/arm/mach-iop3xx/include/mach/vmalloc.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ *                    http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 vmalloc definition
+*/
+
+#ifndef __ASM_ARCH_VMALLOC_H
+#define __ASM_ARCH_VMALLOC_H
+
+#define VMALLOC_END       (0xE0000000)
+
+#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h b/arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h
new file mode 100644
index 000000000000..e4119913d7c5
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h
@@ -0,0 +1,18 @@
+/* arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h
+ *
+ * Copyright (c) 2003 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * VR1000 - CPLD control constants
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_VR1000CPLD_H
+#define __ASM_ARCH_VR1000CPLD_H
+
+#define VR1000_CPLD_CTRL2_RAMWEN     (0x04)   /* SRAM Write Enable */
+
+#endif /* __ASM_ARCH_VR1000CPLD_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/vr1000-irq.h b/arch/arm/mach-s3c2410/include/mach/vr1000-irq.h
new file mode 100644
index 000000000000..f53f85b4ad8b
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/vr1000-irq.h
@@ -0,0 +1,26 @@
+/* arch/arm/mach-s3c2410/include/mach/vr1000-irq.h
+ *
+ * Copyright (c) 2003,2004 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Machine VR1000 - IRQ Number definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_VR1000IRQ_H
+#define __ASM_ARCH_VR1000IRQ_H
+
+/* irq numbers to onboard peripherals */
+
+#define IRQ_USBOC            IRQ_EINT19
+#define IRQ_IDE0             IRQ_EINT16
+#define IRQ_IDE1             IRQ_EINT17
+#define IRQ_VR1000_SERIAL    IRQ_EINT12
+#define IRQ_VR1000_DM9000A   IRQ_EINT10
+#define IRQ_VR1000_DM9000N   IRQ_EINT9
+#define IRQ_SMALERT          IRQ_EINT8
+
+#endif /* __ASM_ARCH_VR1000IRQ_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/vr1000-map.h b/arch/arm/mach-s3c2410/include/mach/vr1000-map.h
new file mode 100644
index 000000000000..99612fcc4eb2
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/vr1000-map.h
@@ -0,0 +1,110 @@
+/* arch/arm/mach-s3c2410/include/mach/vr1000-map.h
+ *
+ * Copyright (c) 2003-2005 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Machine VR1000 - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* needs arch/map.h including with this */
+
+/* ok, we've used up to 0x13000000, now we need to find space for the
+ * peripherals that live in the nGCS[x] areas, which are quite numerous
+ * in their space. We also have the board's CPLD to find register space
+ * for.
+ */
+
+#ifndef __ASM_ARCH_VR1000MAP_H
+#define __ASM_ARCH_VR1000MAP_H
+
+#include <mach/bast-map.h>
+
+#define VR1000_IOADDR(x) BAST_IOADDR(x)
+
+/* we put the CPLD registers next, to get them out of the way */
+
+#define VR1000_VA_CTRL1     VR1000_IOADDR(0x00000000)    /* 0x01300000 */
+#define VR1000_PA_CTRL1     (S3C2410_CS5 | 0x7800000)
+
+#define VR1000_VA_CTRL2     VR1000_IOADDR(0x00100000)    /* 0x01400000 */
+#define VR1000_PA_CTRL2     (S3C2410_CS1 | 0x6000000)
+
+#define VR1000_VA_CTRL3     VR1000_IOADDR(0x00200000)    /* 0x01500000 */
+#define VR1000_PA_CTRL3     (S3C2410_CS1 | 0x6800000)
+
+#define VR1000_VA_CTRL4     VR1000_IOADDR(0x00300000)    /* 0x01600000 */
+#define VR1000_PA_CTRL4     (S3C2410_CS1 | 0x7000000)
+
+/* next, we have the PC104 ISA interrupt registers */
+
+#define VR1000_PA_PC104_IRQREQ  (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
+#define VR1000_VA_PC104_IRQREQ  VR1000_IOADDR(0x00400000)
+
+#define VR1000_PA_PC104_IRQRAW  (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
+#define VR1000_VA_PC104_IRQRAW  VR1000_IOADDR(0x00500000)
+
+#define VR1000_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
+#define VR1000_VA_PC104_IRQMASK VR1000_IOADDR(0x00600000)
+
+/* 0xE0000000 contains the IO space that is split by speed and
+ * wether the access is for 8 or 16bit IO... this ensures that
+ * the correct access is made
+ *
+ * 0x10000000 of space, partitioned as so:
+ *
+ * 0x00000000 to 0x04000000  8bit,  slow
+ * 0x04000000 to 0x08000000  16bit, slow
+ * 0x08000000 to 0x0C000000  16bit, net
+ * 0x0C000000 to 0x10000000  16bit, fast
+ *
+ * each of these spaces has the following in:
+ *
+ * 0x02000000 to 0x02100000 1MB  IDE primary channel
+ * 0x02100000 to 0x02200000 1MB  IDE primary channel aux
+ * 0x02200000 to 0x02400000 1MB  IDE secondary channel
+ * 0x02300000 to 0x02400000 1MB  IDE secondary channel aux
+ * 0x02500000 to 0x02600000 1MB  Davicom DM9000 ethernet controllers
+ * 0x02600000 to 0x02700000 1MB
+ *
+ * the phyiscal layout of the zones are:
+ *  nGCS2 - 8bit, slow
+ *  nGCS3 - 16bit, slow
+ *  nGCS4 - 16bit, net
+ *  nGCS5 - 16bit, fast
+ */
+
+#define VR1000_VA_MULTISPACE (0xE0000000)
+
+#define VR1000_VA_ISAIO            (VR1000_VA_MULTISPACE + 0x00000000)
+#define VR1000_VA_ISAMEM           (VR1000_VA_MULTISPACE + 0x01000000)
+#define VR1000_VA_IDEPRI           (VR1000_VA_MULTISPACE + 0x02000000)
+#define VR1000_VA_IDEPRIAUX        (VR1000_VA_MULTISPACE + 0x02100000)
+#define VR1000_VA_IDESEC           (VR1000_VA_MULTISPACE + 0x02200000)
+#define VR1000_VA_IDESECAUX        (VR1000_VA_MULTISPACE + 0x02300000)
+#define VR1000_VA_ASIXNET          (VR1000_VA_MULTISPACE + 0x02400000)
+#define VR1000_VA_DM9000           (VR1000_VA_MULTISPACE + 0x02500000)
+#define VR1000_VA_SUPERIO          (VR1000_VA_MULTISPACE + 0x02600000)
+
+/* physical offset addresses for the peripherals */
+
+#define VR1000_PA_IDEPRI           (0x02000000)
+#define VR1000_PA_IDEPRIAUX        (0x02800000)
+#define VR1000_PA_IDESEC           (0x03000000)
+#define VR1000_PA_IDESECAUX        (0x03800000)
+#define VR1000_PA_DM9000           (0x05000000)
+
+#define VR1000_PA_SERIAL           (0x11800000)
+#define VR1000_VA_SERIAL           (VR1000_IOADDR(0x00700000))
+
+/* VR1000 ram is in CS1, with A26..A24 = 2_101 */
+#define VR1000_PA_SRAM             (S3C2410_CS1 | 0x05000000)
+
+/* some configurations for the peripherals */
+
+#define VR1000_DM9000_CS         VR1000_VAM_CS4
+
+#endif /* __ASM_ARCH_VR1000MAP_H */
diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c
index 2d72496ed09f..f0de3c23ce78 100644
--- a/arch/arm/mach-s3c2410/mach-amlm5900.c
+++ b/arch/arm/mach-s3c2410/mach-amlm5900.c
@@ -42,15 +42,15 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/flash.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
-#include <asm/arch/fb.h>
+#include <mach/fb.h>
 
 #include <asm/plat-s3c/regs-serial.h>
-#include <asm/arch/regs-lcd.h>
-#include <asm/arch/regs-gpio.h>
+#include <mach/regs-lcd.h>
+#include <mach/regs-gpio.h>
 
 #include <asm/plat-s3c24xx/devs.h>
 #include <asm/plat-s3c24xx/cpu.h>
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 9c76df6662a1..fb1e78e28e50 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -29,24 +29,24 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/bast-map.h>
-#include <asm/arch/bast-irq.h>
-#include <asm/arch/bast-cpld.h>
+#include <mach/bast-map.h>
+#include <mach/bast-irq.h>
+#include <mach/bast-cpld.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
 //#include <asm/debug-ll.h>
 #include <asm/plat-s3c/regs-serial.h>
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-mem.h>
-#include <asm/arch/regs-lcd.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-mem.h>
+#include <mach/regs-lcd.h>
 
 #include <asm/plat-s3c/nand.h>
 #include <asm/plat-s3c/iic.h>
-#include <asm/arch/fb.h>
+#include <mach/fb.h>
 
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index f658b8421302..e35933a46d10 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -25,19 +25,19 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
 #include <asm/plat-s3c/regs-serial.h>
-#include <asm/arch/regs-lcd.h>
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-clock.h>
+#include <mach/regs-lcd.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-clock.h>
 
-#include <asm/arch/h1940.h>
-#include <asm/arch/h1940-latch.h>
-#include <asm/arch/fb.h>
+#include <mach/h1940.h>
+#include <mach/h1940-latch.h>
+#include <mach/fb.h>
 #include <asm/plat-s3c24xx/udc.h>
 
 #include <asm/plat-s3c24xx/clock.h>
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index cbc7956a24e1..80fe2ed0775c 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -26,15 +26,15 @@
 #include <linux/serial_core.h>
 #include <linux/timer.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/fb.h>
-#include <asm/arch/leds-gpio.h>
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-lcd.h>
+#include <mach/fb.h>
+#include <mach/leds-gpio.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-lcd.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
diff --git a/arch/arm/mach-s3c2410/mach-otom.c b/arch/arm/mach-s3c2410/mach-otom.c
index 3b5dc6e81ea5..606ee15911b6 100644
--- a/arch/arm/mach-s3c2410/mach-otom.c
+++ b/arch/arm/mach-s3c2410/mach-otom.c
@@ -22,15 +22,15 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/otom-map.h>
+#include <mach/otom-map.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
 #include <asm/plat-s3c/regs-serial.h>
-#include <asm/arch/regs-gpio.h>
+#include <mach/regs-gpio.h>
 
 #include <asm/plat-s3c24xx/s3c2410.h>
 #include <asm/plat-s3c24xx/clock.h>
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index 012dc14ffb2b..7d34844debde 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -42,19 +42,19 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/leds-gpio.h>
+#include <mach/regs-gpio.h>
+#include <mach/leds-gpio.h>
 #include <asm/plat-s3c/regs-serial.h>
-#include <asm/arch/fb.h>
+#include <mach/fb.h>
 #include <asm/plat-s3c/nand.h>
 #include <asm/plat-s3c24xx/udc.h>
-#include <asm/arch/spi.h>
-#include <asm/arch/spi-gpio.h>
+#include <mach/spi.h>
+#include <mach/spi-gpio.h>
 
 #include <asm/plat-s3c24xx/common-smdk.h>
 #include <asm/plat-s3c24xx/devs.h>
diff --git a/arch/arm/mach-s3c2410/mach-smdk2410.c b/arch/arm/mach-s3c2410/mach-smdk2410.c
index 849ebe92adcc..c9040080727e 100644
--- a/arch/arm/mach-s3c2410/mach-smdk2410.c
+++ b/arch/arm/mach-s3c2410/mach-smdk2410.c
@@ -42,7 +42,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-s3c2410/mach-tct_hammer.c b/arch/arm/mach-s3c2410/mach-tct_hammer.c
index d7646a91a1ef..ec87306a8c24 100644
--- a/arch/arm/mach-s3c2410/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c2410/mach-tct_hammer.c
@@ -39,7 +39,7 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/flash.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index a3f60cd0bba7..12cbca68f57d 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -30,19 +30,19 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/bast-map.h>
-#include <asm/arch/vr1000-map.h>
-#include <asm/arch/vr1000-irq.h>
-#include <asm/arch/vr1000-cpld.h>
+#include <mach/bast-map.h>
+#include <mach/vr1000-map.h>
+#include <mach/vr1000-irq.h>
+#include <mach/vr1000-cpld.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
 #include <asm/plat-s3c/regs-serial.h>
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/leds-gpio.h>
+#include <mach/regs-gpio.h>
+#include <mach/leds-gpio.h>
 
 #include <asm/plat-s3c24xx/clock.h>
 #include <asm/plat-s3c24xx/devs.h>
diff --git a/arch/arm/mach-s3c2410/nor-simtec.c b/arch/arm/mach-s3c2410/nor-simtec.c
index f44e21b9c3ba..b2ae237042a5 100644
--- a/arch/arm/mach-s3c2410/nor-simtec.c
+++ b/arch/arm/mach-s3c2410/nor-simtec.c
@@ -26,9 +26,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/map.h>
-#include <asm/arch/bast-map.h>
-#include <asm/arch/bast-cpld.h>
+#include <mach/map.h>
+#include <mach/bast-map.h>
+#include <mach/bast-cpld.h>
 
 
 static void simtec_nor_vpp(struct map_info *map, int vpp)
diff --git a/arch/arm/mach-s3c2410/pm-h1940.S b/arch/arm/mach-s3c2410/pm-h1940.S
index cb87c941fe47..c93bf2db9f4d 100644
--- a/arch/arm/mach-s3c2410/pm-h1940.S
+++ b/arch/arm/mach-s3c2410/pm-h1940.S
@@ -20,10 +20,10 @@
 
 #include <linux/linkage.h>
 #include <asm/assembler.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/map.h>
+#include <mach/hardware.h>
+#include <mach/map.h>
 
-#include <asm/arch/regs-gpio.h>
+#include <mach/regs-gpio.h>
 
         .text
         .global h1940_pm_return
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c
index b9087273c244..ba43ff9e8164 100644
--- a/arch/arm/mach-s3c2410/pm.c
+++ b/arch/arm/mach-s3c2410/pm.c
@@ -26,13 +26,13 @@
 #include <linux/time.h>
 #include <linux/sysdev.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/h1940.h>
+#include <mach/regs-gpio.h>
+#include <mach/h1940.h>
 
 #include <asm/plat-s3c24xx/cpu.h>
 #include <asm/plat-s3c24xx/pm.h>
diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c
index 54d4b7983c95..5d977f9c88ac 100644
--- a/arch/arm/mach-s3c2410/s3c2410.c
+++ b/arch/arm/mach-s3c2410/s3c2410.c
@@ -24,11 +24,11 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 
-#include <asm/arch/regs-clock.h>
+#include <mach/regs-clock.h>
 #include <asm/plat-s3c/regs-serial.h>
 
 #include <asm/plat-s3c24xx/s3c2410.h>
diff --git a/arch/arm/mach-s3c2410/sleep.S b/arch/arm/mach-s3c2410/sleep.S
index 1597fcf9d7a1..be37f221a177 100644
--- a/arch/arm/mach-s3c2410/sleep.S
+++ b/arch/arm/mach-s3c2410/sleep.S
@@ -26,12 +26,12 @@
 
 #include <linux/linkage.h>
 #include <asm/assembler.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/map.h>
+#include <mach/hardware.h>
+#include <mach/map.h>
 
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-clock.h>
-#include <asm/arch/regs-mem.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-mem.h>
 #include <asm/plat-s3c/regs-serial.h>
 
         /* s3c2410_cpu_suspend
diff --git a/arch/arm/mach-s3c2410/usb-simtec.c b/arch/arm/mach-s3c2410/usb-simtec.c
index 28942e0acc98..4dacf8a1750d 100644
--- a/arch/arm/mach-s3c2410/usb-simtec.c
+++ b/arch/arm/mach-s3c2410/usb-simtec.c
@@ -26,12 +26,12 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/bast-map.h>
-#include <asm/arch/bast-irq.h>
-#include <asm/arch/usb-control.h>
-#include <asm/arch/regs-gpio.h>
+#include <mach/bast-map.h>
+#include <mach/bast-irq.h>
+#include <mach/usb-control.h>
+#include <mach/regs-gpio.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 
diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c
index b1552b2e8ea8..af4b2ce516f9 100644
--- a/arch/arm/mach-s3c2412/clock.c
+++ b/arch/arm/mach-s3c2412/clock.c
@@ -34,12 +34,12 @@
 
 #include <asm/mach/map.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 
 #include <asm/plat-s3c/regs-serial.h>
-#include <asm/arch/regs-clock.h>
-#include <asm/arch/regs-gpio.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-gpio.h>
 
 #include <asm/plat-s3c24xx/s3c2412.h>
 #include <asm/plat-s3c24xx/clock.h>
diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c
index 1dd864993566..22fc04a3b533 100644
--- a/arch/arm/mach-s3c2412/dma.c
+++ b/arch/arm/mach-s3c2412/dma.c
@@ -18,18 +18,18 @@
 #include <linux/serial_core.h>
 
 #include <asm/dma.h>
-#include <asm/arch/dma.h>
+#include <mach/dma.h>
 #include <asm/io.h>
 
 #include <asm/plat-s3c24xx/dma.h>
 #include <asm/plat-s3c24xx/cpu.h>
 
 #include <asm/plat-s3c/regs-serial.h>
-#include <asm/arch/regs-gpio.h>
+#include <mach/regs-gpio.h>
 #include <asm/plat-s3c/regs-ac97.h>
-#include <asm/arch/regs-mem.h>
-#include <asm/arch/regs-lcd.h>
-#include <asm/arch/regs-sdi.h>
+#include <mach/regs-mem.h>
+#include <mach/regs-lcd.h>
+#include <mach/regs-sdi.h>
 #include <asm/plat-s3c24xx/regs-s3c2412-iis.h>
 #include <asm/plat-s3c24xx/regs-iis.h>
 #include <asm/plat-s3c24xx/regs-spi.h>
diff --git a/arch/arm/mach-s3c2412/gpio.c b/arch/arm/mach-s3c2412/gpio.c
index 4f86693b05fd..f7afece7fc38 100644
--- a/arch/arm/mach-s3c2412/gpio.c
+++ b/arch/arm/mach-s3c2412/gpio.c
@@ -20,9 +20,9 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <asm/arch/regs-gpio.h>
+#include <mach/regs-gpio.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state)
 {
diff --git a/arch/arm/mach-s3c2412/irq.c b/arch/arm/mach-s3c2412/irq.c
index 0230b2f6353a..ac62b79044f4 100644
--- a/arch/arm/mach-s3c2412/irq.c
+++ b/arch/arm/mach-s3c2412/irq.c
@@ -25,15 +25,15 @@
 #include <linux/ioport.h>
 #include <linux/sysdev.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/io.h>
 
 #include <asm/mach/irq.h>
 
-#include <asm/arch/regs-irq.h>
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-power.h>
+#include <mach/regs-irq.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-power.h>
 
 #include <asm/plat-s3c24xx/cpu.h>
 #include <asm/plat-s3c24xx/irq.h>
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c
index 7f5924713485..30f613a79bfe 100644
--- a/arch/arm/mach-s3c2412/mach-jive.c
+++ b/arch/arm/mach-s3c2412/mach-jive.c
@@ -37,12 +37,12 @@
 #include <asm/plat-s3c/nand.h>
 #include <asm/plat-s3c/iic.h>
 
-#include <asm/arch/regs-power.h>
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-mem.h>
-#include <asm/arch/regs-lcd.h>
-#include <asm/arch/spi-gpio.h>
-#include <asm/arch/fb.h>
+#include <mach/regs-power.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-mem.h>
+#include <mach/regs-lcd.h>
+#include <mach/spi-gpio.h>
+#include <mach/fb.h>
 
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c
index d7d0e95949c5..80affb1ee4cd 100644
--- a/arch/arm/mach-s3c2412/mach-smdk2413.c
+++ b/arch/arm/mach-s3c2412/mach-smdk2413.c
@@ -24,7 +24,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/hardware/iomd.h>
 #include <asm/setup.h>
 #include <asm/io.h>
@@ -33,12 +33,12 @@
 
 //#include <asm/debug-ll.h>
 #include <asm/plat-s3c/regs-serial.h>
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-lcd.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-lcd.h>
 
-#include <asm/arch/idle.h>
+#include <mach/idle.h>
 #include <asm/plat-s3c24xx/udc.h>
-#include <asm/arch/fb.h>
+#include <mach/fb.h>
 
 #include <asm/plat-s3c24xx/s3c2410.h>
 #include <asm/plat-s3c24xx/s3c2412.h>
diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c2412/mach-vstms.c
index d7087d0dbad2..7a08b3789915 100644
--- a/arch/arm/mach-s3c2412/mach-vstms.c
+++ b/arch/arm/mach-s3c2412/mach-vstms.c
@@ -27,18 +27,18 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
 #include <asm/plat-s3c/regs-serial.h>
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-lcd.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-lcd.h>
 
-#include <asm/arch/idle.h>
-#include <asm/arch/fb.h>
+#include <mach/idle.h>
+#include <mach/fb.h>
 
 #include <asm/plat-s3c/nand.h>
 
diff --git a/arch/arm/mach-s3c2412/pm.c b/arch/arm/mach-s3c2412/pm.c
index a71d6c6cd447..737523a4e037 100644
--- a/arch/arm/mach-s3c2412/pm.c
+++ b/arch/arm/mach-s3c2412/pm.c
@@ -19,14 +19,14 @@
 #include <linux/sysdev.h>
 #include <linux/platform_device.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 
-#include <asm/arch/regs-power.h>
-#include <asm/arch/regs-gpioj.h>
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-dsc.h>
+#include <mach/regs-power.h>
+#include <mach/regs-gpioj.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-dsc.h>
 
 #include <asm/plat-s3c24xx/cpu.h>
 #include <asm/plat-s3c24xx/pm.h>
diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c
index 5ce001b5c275..d278010b9f60 100644
--- a/arch/arm/mach-s3c2412/s3c2412.c
+++ b/arch/arm/mach-s3c2412/s3c2412.c
@@ -25,22 +25,22 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/proc-fns.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 
-#include <asm/arch/reset.h>
-#include <asm/arch/idle.h>
+#include <mach/reset.h>
+#include <mach/idle.h>
 
-#include <asm/arch/regs-clock.h>
+#include <mach/regs-clock.h>
 #include <asm/plat-s3c/regs-serial.h>
-#include <asm/arch/regs-power.h>
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-gpioj.h>
-#include <asm/arch/regs-dsc.h>
+#include <mach/regs-power.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-gpioj.h>
+#include <mach/regs-dsc.h>
 #include <asm/plat-s3c24xx/regs-spi.h>
-#include <asm/arch/regs-s3c2412.h>
+#include <mach/regs-s3c2412.h>
 
 #include <asm/plat-s3c24xx/s3c2412.h>
 #include <asm/plat-s3c24xx/cpu.h>
diff --git a/arch/arm/mach-s3c2412/sleep.S b/arch/arm/mach-s3c2412/sleep.S
index 609312b62023..c82418ed714d 100644
--- a/arch/arm/mach-s3c2412/sleep.S
+++ b/arch/arm/mach-s3c2412/sleep.S
@@ -22,10 +22,10 @@
 
 #include <linux/linkage.h>
 #include <asm/assembler.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/map.h>
+#include <mach/hardware.h>
+#include <mach/map.h>
 
-#include <asm/arch/regs-irq.h>
+#include <mach/regs-irq.h>
 
         .text
 
diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c2440/clock.c
index 9ef4efd7e235..95567e6daea1 100644
--- a/arch/arm/mach-s3c2440/clock.c
+++ b/arch/arm/mach-s3c2440/clock.c
@@ -34,12 +34,12 @@
 #include <linux/mutex.h>
 #include <linux/clk.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/atomic.h>
 #include <asm/irq.h>
 #include <asm/io.h>
 
-#include <asm/arch/regs-clock.h>
+#include <mach/regs-clock.h>
 
 #include <asm/plat-s3c24xx/clock.h>
 #include <asm/plat-s3c24xx/cpu.h>
diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c2440/dma.c
index 0b1260827ac6..cdd4e6e79ac0 100644
--- a/arch/arm/mach-s3c2440/dma.c
+++ b/arch/arm/mach-s3c2440/dma.c
@@ -18,17 +18,17 @@
 #include <linux/serial_core.h>
 
 #include <asm/dma.h>
-#include <asm/arch/dma.h>
+#include <mach/dma.h>
 
 #include <asm/plat-s3c24xx/dma.h>
 #include <asm/plat-s3c24xx/cpu.h>
 
 #include <asm/plat-s3c/regs-serial.h>
-#include <asm/arch/regs-gpio.h>
+#include <mach/regs-gpio.h>
 #include <asm/plat-s3c/regs-ac97.h>
-#include <asm/arch/regs-mem.h>
-#include <asm/arch/regs-lcd.h>
-#include <asm/arch/regs-sdi.h>
+#include <mach/regs-mem.h>
+#include <mach/regs-lcd.h>
+#include <mach/regs-sdi.h>
 #include <asm/plat-s3c24xx/regs-iis.h>
 #include <asm/plat-s3c24xx/regs-spi.h>
 
diff --git a/arch/arm/mach-s3c2440/dsc.c b/arch/arm/mach-s3c2440/dsc.c
index e7f1ca1e6730..c0c67438d0a4 100644
--- a/arch/arm/mach-s3c2440/dsc.c
+++ b/arch/arm/mach-s3c2440/dsc.c
@@ -20,12 +20,12 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-dsc.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-dsc.h>
 
 #include <asm/plat-s3c24xx/cpu.h>
 #include <asm/plat-s3c24xx/s3c2440.h>
diff --git a/arch/arm/mach-s3c2440/irq.c b/arch/arm/mach-s3c2440/irq.c
index 457255d1f08e..276b823f4e27 100644
--- a/arch/arm/mach-s3c2440/irq.c
+++ b/arch/arm/mach-s3c2440/irq.c
@@ -25,14 +25,14 @@
 #include <linux/ioport.h>
 #include <linux/sysdev.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/io.h>
 
 #include <asm/mach/irq.h>
 
-#include <asm/arch/regs-irq.h>
-#include <asm/arch/regs-gpio.h>
+#include <mach/regs-irq.h>
+#include <mach/regs-gpio.h>
 
 #include <asm/plat-s3c24xx/cpu.h>
 #include <asm/plat-s3c24xx/pm.h>
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c
index f53eba751a6c..265c77dec9d7 100644
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -27,19 +27,19 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/anubis-map.h>
-#include <asm/arch/anubis-irq.h>
-#include <asm/arch/anubis-cpld.h>
+#include <mach/anubis-map.h>
+#include <mach/anubis-irq.h>
+#include <mach/anubis-cpld.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
 #include <asm/plat-s3c/regs-serial.h>
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-mem.h>
-#include <asm/arch/regs-lcd.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-mem.h>
+#include <mach/regs-lcd.h>
 #include <asm/plat-s3c/nand.h>
 
 #include <linux/mtd/mtd.h>
diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c
index 48e8fb6d18b3..f0f0cc6afcf4 100644
--- a/arch/arm/mach-s3c2440/mach-at2440evb.c
+++ b/arch/arm/mach-s3c2440/mach-at2440evb.c
@@ -27,14 +27,14 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
 #include <asm/plat-s3c/regs-serial.h>
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-mem.h>
-#include <asm/arch/regs-lcd.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-mem.h>
+#include <mach/regs-lcd.h>
 #include <asm/plat-s3c/nand.h>
 
 #include <linux/mtd/mtd.h>
diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c2440/mach-nexcoder.c
index 0f4437b79ef3..1a5e7027b41b 100644
--- a/arch/arm/mach-s3c2440/mach-nexcoder.c
+++ b/arch/arm/mach-s3c2440/mach-nexcoder.c
@@ -29,13 +29,13 @@
 #include <asm/mach/irq.h>
 
 #include <asm/setup.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
 //#include <asm/debug-ll.h>
-#include <asm/arch/regs-gpio.h>
+#include <mach/regs-gpio.h>
 #include <asm/plat-s3c/regs-serial.h>
 
 #include <asm/plat-s3c24xx/s3c2410.h>
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index c4008d5c42fd..d2ee0cd148c6 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -25,18 +25,18 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/osiris-map.h>
-#include <asm/arch/osiris-cpld.h>
+#include <mach/osiris-map.h>
+#include <mach/osiris-cpld.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
 #include <asm/plat-s3c/regs-serial.h>
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-mem.h>
-#include <asm/arch/regs-lcd.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-mem.h>
+#include <mach/regs-lcd.h>
 #include <asm/plat-s3c/nand.h>
 
 #include <linux/mtd/mtd.h>
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
index 569f00bc9296..e0b07e6a0a18 100644
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -33,18 +33,18 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
 #include <asm/plat-s3c/regs-serial.h>
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-lcd.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-lcd.h>
 
-#include <asm/arch/h1940.h>
+#include <mach/h1940.h>
 #include <asm/plat-s3c/nand.h>
-#include <asm/arch/fb.h>
+#include <mach/fb.h>
 
 #include <asm/plat-s3c24xx/clock.h>
 #include <asm/plat-s3c24xx/devs.h>
diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c
index 52deb5a6d91c..327c8f371984 100644
--- a/arch/arm/mach-s3c2440/mach-smdk2440.c
+++ b/arch/arm/mach-s3c2440/mach-smdk2440.c
@@ -26,17 +26,17 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
 #include <asm/plat-s3c/regs-serial.h>
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-lcd.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-lcd.h>
 
-#include <asm/arch/idle.h>
-#include <asm/arch/fb.h>
+#include <mach/idle.h>
+#include <mach/fb.h>
 
 #include <asm/plat-s3c24xx/s3c2410.h>
 #include <asm/plat-s3c24xx/s3c2440.h>
diff --git a/arch/arm/mach-s3c2440/s3c2440.c b/arch/arm/mach-s3c2440/s3c2440.c
index 19f06c3c26aa..d6b9a92d284e 100644
--- a/arch/arm/mach-s3c2440/s3c2440.c
+++ b/arch/arm/mach-s3c2440/s3c2440.c
@@ -25,7 +25,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 
diff --git a/arch/arm/mach-s3c2442/clock.c b/arch/arm/mach-s3c2442/clock.c
index ad2e8a929787..569b5c3d334a 100644
--- a/arch/arm/mach-s3c2442/clock.c
+++ b/arch/arm/mach-s3c2442/clock.c
@@ -34,12 +34,12 @@
 #include <linux/mutex.h>
 #include <linux/clk.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/atomic.h>
 #include <asm/irq.h>
 #include <asm/io.h>
 
-#include <asm/arch/regs-clock.h>
+#include <mach/regs-clock.h>
 
 #include <asm/plat-s3c24xx/clock.h>
 #include <asm/plat-s3c24xx/cpu.h>
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
index 04d248aaa7a1..6a8d7cced4a2 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -34,10 +34,10 @@
 
 #include <asm/mach/map.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 
-#include <asm/arch/regs-s3c2443-clock.h>
+#include <mach/regs-s3c2443-clock.h>
 
 #include <asm/plat-s3c24xx/s3c2443.h>
 #include <asm/plat-s3c24xx/clock.h>
diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c2443/dma.c
index f6c006d4297b..c1ff03aebfda 100644
--- a/arch/arm/mach-s3c2443/dma.c
+++ b/arch/arm/mach-s3c2443/dma.c
@@ -18,18 +18,18 @@
 #include <linux/serial_core.h>
 
 #include <asm/dma.h>
-#include <asm/arch/dma.h>
+#include <mach/dma.h>
 #include <asm/io.h>
 
 #include <asm/plat-s3c24xx/dma.h>
 #include <asm/plat-s3c24xx/cpu.h>
 
 #include <asm/plat-s3c/regs-serial.h>
-#include <asm/arch/regs-gpio.h>
+#include <mach/regs-gpio.h>
 #include <asm/plat-s3c/regs-ac97.h>
-#include <asm/arch/regs-mem.h>
-#include <asm/arch/regs-lcd.h>
-#include <asm/arch/regs-sdi.h>
+#include <mach/regs-mem.h>
+#include <mach/regs-lcd.h>
+#include <mach/regs-sdi.h>
 #include <asm/plat-s3c24xx/regs-iis.h>
 #include <asm/plat-s3c24xx/regs-spi.h>
 
diff --git a/arch/arm/mach-s3c2443/irq.c b/arch/arm/mach-s3c2443/irq.c
index 499cddbbab41..9674de7223fd 100644
--- a/arch/arm/mach-s3c2443/irq.c
+++ b/arch/arm/mach-s3c2443/irq.c
@@ -25,14 +25,14 @@
 #include <linux/ioport.h>
 #include <linux/sysdev.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/io.h>
 
 #include <asm/mach/irq.h>
 
-#include <asm/arch/regs-irq.h>
-#include <asm/arch/regs-gpio.h>
+#include <mach/regs-irq.h>
+#include <mach/regs-gpio.h>
 
 #include <asm/plat-s3c24xx/cpu.h>
 #include <asm/plat-s3c24xx/pm.h>
diff --git a/arch/arm/mach-s3c2443/mach-smdk2443.c b/arch/arm/mach-s3c2443/mach-smdk2443.c
index 5a6d33310244..e3c0d587bd10 100644
--- a/arch/arm/mach-s3c2443/mach-smdk2443.c
+++ b/arch/arm/mach-s3c2443/mach-smdk2443.c
@@ -26,17 +26,17 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
 #include <asm/plat-s3c/regs-serial.h>
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-lcd.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-lcd.h>
 
-#include <asm/arch/idle.h>
-#include <asm/arch/fb.h>
+#include <mach/idle.h>
+#include <mach/fb.h>
 
 #include <asm/plat-s3c24xx/s3c2410.h>
 #include <asm/plat-s3c24xx/s3c2440.h>
diff --git a/arch/arm/mach-s3c2443/s3c2443.c b/arch/arm/mach-s3c2443/s3c2443.c
index 3e9f92383ed5..37793f924b5e 100644
--- a/arch/arm/mach-s3c2443/s3c2443.c
+++ b/arch/arm/mach-s3c2443/s3c2443.c
@@ -25,12 +25,12 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 
-#include <asm/arch/regs-s3c2443-clock.h>
-#include <asm/arch/reset.h>
+#include <mach/regs-s3c2443-clock.h>
+#include <mach/reset.h>
 
 #include <asm/plat-s3c24xx/s3c2443.h>
 #include <asm/plat-s3c24xx/devs.h>
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index d219845b10b8..55e64477a876 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -20,7 +20,7 @@
 #include <linux/delay.h>
 #include <linux/mm.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
 #include <asm/setup.h>
@@ -34,8 +34,8 @@
 #include <asm/mach/irda.h>
 #include <asm/mach/map.h>
 #include <asm/mach/serial_sa1100.h>
-#include <asm/arch/assabet.h>
-#include <asm/arch/mcp.h>
+#include <mach/assabet.h>
+#include <mach/mcp.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-sa1100/badge4.c b/arch/arm/mach-sa1100/badge4.c
index d087c3bf3feb..3efefbdd2527 100644
--- a/arch/arm/mach-sa1100/badge4.c
+++ b/arch/arm/mach-sa1100/badge4.c
@@ -23,10 +23,10 @@
 #include <linux/mtd/partitions.h>
 #include <linux/errno.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/setup.h>
-#include <asm/arch/irqs.h>
+#include <mach/irqs.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
@@ -34,7 +34,7 @@
 #include <asm/hardware/sa1111.h>
 #include <asm/mach/serial_sa1100.h>
 
-#include <asm/arch/badge4.h>
+#include <mach/badge4.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-sa1100/cerf.c b/arch/arm/mach-sa1100/cerf.c
index cfb65eb9f304..fd3ad9cfc912 100644
--- a/arch/arm/mach-sa1100/cerf.c
+++ b/arch/arm/mach-sa1100/cerf.c
@@ -19,7 +19,7 @@
 #include <linux/mtd/partitions.h>
 
 #include <asm/irq.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/setup.h>
 
 #include <asm/mach-types.h>
@@ -28,8 +28,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/serial_sa1100.h>
 
-#include <asm/arch/cerf.h>
-#include <asm/arch/mcp.h>
+#include <mach/cerf.h>
+#include <mach/mcp.h>
 #include "generic.h"
 
 static struct resource cerfuart2_resources[] = {
diff --git a/arch/arm/mach-sa1100/clock.c b/arch/arm/mach-sa1100/clock.c
index dbd1aaaa09a2..43c30f84abf2 100644
--- a/arch/arm/mach-sa1100/clock.c
+++ b/arch/arm/mach-sa1100/clock.c
@@ -11,7 +11,7 @@
 #include <linux/spinlock.h>
 #include <linux/mutex.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 /*
  * Very simple clock implementation - we only have one clock to
diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c
index 40893638be70..fe289997cfaf 100644
--- a/arch/arm/mach-sa1100/collie.c
+++ b/arch/arm/mach-sa1100/collie.c
@@ -26,11 +26,11 @@
 #include <linux/mtd/partitions.h>
 #include <linux/timer.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
 #include <asm/setup.h>
-#include <asm/arch/collie.h>
+#include <mach/collie.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
@@ -40,7 +40,7 @@
 #include <asm/hardware/scoop.h>
 #include <asm/mach/sharpsl_param.h>
 #include <asm/hardware/locomo.h>
-#include <asm/arch/mcp.h>
+#include <mach/mcp.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-sa1100/collie_pm.c b/arch/arm/mach-sa1100/collie_pm.c
index daa9d57c00fa..b1161fc80602 100644
--- a/arch/arm/mach-sa1100/collie_pm.c
+++ b/arch/arm/mach-sa1100/collie_pm.c
@@ -24,10 +24,10 @@
 #include <linux/platform_device.h>
 
 #include <asm/irq.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/hardware/scoop.h>
 #include <asm/dma.h>
-#include <asm/arch/collie.h>
+#include <mach/collie.h>
 #include <asm/mach/sharpsl_param.h>
 #include <asm/hardware/sharpsl_pm.h>
 
diff --git a/arch/arm/mach-sa1100/cpu-sa1100.c b/arch/arm/mach-sa1100/cpu-sa1100.c
index 61df76f85268..da3a898a6d66 100644
--- a/arch/arm/mach-sa1100/cpu-sa1100.c
+++ b/arch/arm/mach-sa1100/cpu-sa1100.c
@@ -88,7 +88,7 @@
 #include <linux/init.h>
 #include <linux/cpufreq.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-sa1100/cpu-sa1110.c b/arch/arm/mach-sa1100/cpu-sa1110.c
index a471f9f62731..39d38c801736 100644
--- a/arch/arm/mach-sa1100/cpu-sa1110.c
+++ b/arch/arm/mach-sa1100/cpu-sa1110.c
@@ -26,7 +26,7 @@
 #include <linux/delay.h>
 #include <linux/init.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/io.h>
 #include <asm/system.h>
diff --git a/arch/arm/mach-sa1100/dma.c b/arch/arm/mach-sa1100/dma.c
index 65d96eec9e60..f990a3e85846 100644
--- a/arch/arm/mach-sa1100/dma.c
+++ b/arch/arm/mach-sa1100/dma.c
@@ -18,7 +18,7 @@
 
 #include <asm/system.h>
 #include <asm/irq.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/dma.h>
 
 
@@ -76,7 +76,7 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
  *      address of the hardware registers for that channel as the channel
  *      identifier. This identifier is written to the location pointed by
  *      @dma_regs. The list of possible values for @device are listed into
- *      linux/include/asm-arm/arch-sa1100/dma.h as a dma_device_t enum.
+ *      arch/arm/mach-sa1100/include/mach/dma.h as a dma_device_t enum.
  *
  *      Note that reading from a port and writing to the same port are
  *      actually considered as two different streams requiring separate
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index e616130ae529..5a08fe20a319 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -21,7 +21,7 @@
 
 #include <asm/div64.h>
 #include <asm/cnt32_to_63.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/system.h>
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-sa1100/gpio.c b/arch/arm/mach-sa1100/gpio.c
index 184b04c0072a..0d3829a8c2c1 100644
--- a/arch/arm/mach-sa1100/gpio.c
+++ b/arch/arm/mach-sa1100/gpio.c
@@ -12,7 +12,7 @@
 #include <linux/module.h>
 
 #include <asm/gpio.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include "generic.h"
 
 static int sa1100_gpio_get(struct gpio_chip *chip, unsigned offset)
diff --git a/arch/arm/mach-sa1100/h3600.c b/arch/arm/mach-sa1100/h3600.c
index 8c560ae0869c..af25a78d705d 100644
--- a/arch/arm/mach-sa1100/h3600.c
+++ b/arch/arm/mach-sa1100/h3600.c
@@ -30,7 +30,7 @@
 #include <linux/serial_core.h>
 
 #include <asm/irq.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/setup.h>
 
@@ -41,14 +41,14 @@
 #include <asm/mach/map.h>
 #include <asm/mach/serial_sa1100.h>
 
-#include <asm/arch/h3600.h>
+#include <mach/h3600.h>
 
 #if defined (CONFIG_SA1100_H3600) || defined (CONFIG_SA1100_H3100)
-#include <asm/arch/h3600_gpio.h>
+#include <mach/h3600_gpio.h>
 #endif
 
 #ifdef CONFIG_SA1100_H3800
-#include <asm/arch/h3600_asic.h>
+#include <mach/h3600_asic.h>
 #endif
 
 #include "generic.h"
@@ -681,7 +681,7 @@ static struct ipaq_model_ops h3800_model_ops __initdata = {
 
 #define MAX_ASIC_ISR_LOOPS    20
 
-/* The order of these is important - see #include <asm/arch/irqs.h> */
+/* The order of these is important - see #include <mach/irqs.h> */
 static u32 kpio_irq_mask[] = {
         KPIO_KEY_ALL,
         KPIO_SPI_INT,
diff --git a/arch/arm/mach-sa1100/hackkit.c b/arch/arm/mach-sa1100/hackkit.c
index 270feb0fa4ac..e7056c0b562c 100644
--- a/arch/arm/mach-sa1100/hackkit.c
+++ b/arch/arm/mach-sa1100/hackkit.c
@@ -22,7 +22,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/setup.h>
 #include <asm/page.h>
diff --git a/include/asm-arm/arch-sa1100/SA-1100.h b/arch/arm/mach-sa1100/include/mach/SA-1100.h
index 62aaf04a3906..62aaf04a3906 100644
--- a/include/asm-arm/arch-sa1100/SA-1100.h
+++ b/arch/arm/mach-sa1100/include/mach/SA-1100.h
diff --git a/arch/arm/mach-sa1100/include/mach/SA-1101.h b/arch/arm/mach-sa1100/include/mach/SA-1101.h
new file mode 100644
index 000000000000..5d2ad7db991c
--- /dev/null
+++ b/arch/arm/mach-sa1100/include/mach/SA-1101.h
@@ -0,0 +1,925 @@
+/*
+ * SA-1101.h
+ *
+ * Copyright (c) Peter Danielsson 1999
+ *
+ * Definition of constants related to the sa1101
+ * support chip for the sa1100
+ *
+ */
+
+
+/* Be sure that virtual mapping is defined right */
+#ifndef __ASM_ARCH_HARDWARE_H
+#error You must include hardware.h not SA-1101.h
+#endif
+
+#ifndef SA1101_BASE
+#error You must define SA-1101 physical base address
+#endif
+
+#ifndef LANGUAGE
+# ifdef __ASSEMBLY__
+#  define LANGUAGE Assembly
+# else
+#  define LANGUAGE C
+# endif
+#endif
+
+/*
+ * We have mapped the sa1101 depending on the value of SA1101_BASE.
+ * It then appears from 0xf4000000.
+ */
+
+#define SA1101_p2v( x )         ((x) - SA1101_BASE + 0xf4000000)
+#define SA1101_v2p( x )         ((x) - 0xf4000000  + SA1101_BASE)
+
+#ifndef SA1101_p2v
+#define SA1101_p2v(PhAdd)  (PhAdd)
+#endif
+
+#include <mach/bitfield.h>
+
+#define C               0
+#define Assembly        1
+
+
+/*
+ * Memory map
+ */
+
+#define __SHMEM_CONTROL0        0x00000000
+#define __SYSTEM_CONTROL1       0x00000400
+#define __ARBITER               0x00020000
+#define __SYSTEM_CONTROL2       0x00040000
+#define __SYSTEM_CONTROL3       0x00060000
+#define __PARALLEL_PORT         0x00080000
+#define __VIDMEM_CONTROL        0x00100000
+#define __UPDATE_FIFO           0x00120000
+#define __SHMEM_CONTROL1        0x00140000
+#define __INTERRUPT_CONTROL     0x00160000
+#define __USB_CONTROL           0x00180000
+#define __TRACK_INTERFACE       0x001a0000
+#define __MOUSE_INTERFACE       0x001b0000
+#define __KEYPAD_INTERFACE      0x001c0000
+#define __PCMCIA_INTERFACE      0x001e0000
+#define __VGA_CONTROL           0x00200000
+#define __GPIO_INTERFACE        0x00300000
+
+/*
+ * Macro that calculates real address for registers in the SA-1101
+ */
+
+#define _SA1101( x )    ((x) + SA1101_BASE)
+
+/*
+ * Interface and shared memory controller registers
+ *
+ * Registers
+ *      SKCR            SA-1101 control register (read/write)
+ *      SMCR            Shared Memory Controller Register
+ *      SNPR            Snoop Register
+ */
+
+#define _SKCR           _SA1101( 0x00000000 ) /* SA-1101 Control Reg. */
+#define _SMCR           _SA1101( 0x00140000 ) /* Shared Mem. Control Reg. */
+#define _SNPR           _SA1101( 0x00140400 ) /* Snoop Reg. */
+
+#if LANGUAGE == C
+#define SKCR            (*((volatile Word *) SA1101_p2v (_SKCR)))
+#define SMCR            (*((volatile Word *) SA1101_p2v (_SMCR)))
+#define SNPR            (*((volatile Word *) SA1101_p2v (_SNPR)))
+
+#define SKCR_PLLEn        0x0001          /* Enable On-Chip PLL */
+#define SKCR_BCLKEn       0x0002          /* Enables BCLK */
+#define SKCR_Sleep        0x0004          /* Sleep Mode */
+#define SKCR_IRefEn       0x0008          /* DAC Iref input enable */
+#define SKCR_VCOON        0x0010          /* VCO bias */
+#define SKCR_ScanTestEn   0x0020          /* Enables scan test */
+#define SKCR_ClockTestEn  0x0040          /* Enables clock test */
+
+#define SMCR_DCAC         Fld(2,0)        /* Number of column address bits */
+#define SMCR_DRAC         Fld(2,2)        /* Number of row address bits */
+#define SMCR_ArbiterBias  0x0008          /* favor video or USB */
+#define SMCR_TopVidMem    Fld(4,5)        /* Top 4 bits of vidmem addr. */
+
+#define SMCR_ColAdrBits( x )              /* col. addr bits 8..11 */ \
+        (( (x) - 8 ) << FShft (SMCR_DCAC))
+#define SMCR_RowAdrBits( x )              /* row addr bits 9..12 */\
+        (( (x) - 9 ) << FShft (SMCR_DRAC))
+
+#define SNPR_VFBstart     Fld(12,0)     /* Video frame buffer addr */
+#define SNPR_VFBsize      Fld(11,12)    /* Video frame buffer size */
+#define SNPR_WholeBank    (1 << 23)     /* Whole bank bit */
+#define SNPR_BankSelect   Fld(2,27)     /* Bank select */
+#define SNPR_SnoopEn      (1 << 31)     /* Enable snoop operation */
+
+#define SNPR_Set_VFBsize( x )   /* set frame buffer size (in kb) */ \
+        ( (x) << FShft (SNPR_VFBsize))
+#define SNPR_Select_Bank(x)     /* select bank 0 or 1 */  \
+        (( (x) + 1 ) << FShft (SNPR_BankSelect ))
+
+#endif /* LANGUAGE == C */
+
+/*
+ * Video Memory Controller
+ *
+ * Registers
+ *    VMCCR     Configuration register
+ *    VMCAR     VMC address register
+ *    VMCDR     VMC data register
+ *
+ */
+
+#define _VMCCR          _SA1101( 0x00100000 )   /* Configuration register */
+#define _VMCAR          _SA1101( 0x00101000 )   /* VMC address register */
+#define _VMCDR          _SA1101( 0x00101400 )   /* VMC data register */
+
+#if LANGUAGE == C
+#define VMCCR           (*((volatile Word *) SA1101_p2v (_VMCCR)))
+#define VMCAR           (*((volatile Word *) SA1101_p2v (_VMCAR)))
+#define VMCDR           (*((volatile Word *) SA1101_p2v (_VMCDR)))
+
+#define VMCCR_RefreshEn     0x0000        /* Enable memory refresh */
+#define VMCCR_Config        0x0001        /* DRAM size */
+#define VMCCR_RefPeriod     Fld(2,3)      /* Refresh period */
+#define VMCCR_StaleDataWait Fld(4,5)      /* Stale FIFO data timeout counter */
+#define VMCCR_SleepState    (1<<9)        /* State of interface pins in sleep*/
+#define VMCCR_RefTest       (1<<10)       /* refresh test */
+#define VMCCR_RefLow        Fld(6,11)     /* refresh low counter */
+#define VMCCR_RefHigh       Fld(7,17)     /* refresh high counter */
+#define VMCCR_SDTCTest      Fld(7,24)     /* stale data timeout counter */
+#define VMCCR_ForceSelfRef  (1<<31)       /* Force self refresh */
+
+#endif LANGUAGE == C
+
+
+/* Update FIFO
+ *
+ * Registers
+ *    UFCR      Update FIFO Control Register
+ *    UFSR      Update FIFO Status Register
+ *    UFLVLR    update FIFO level register
+ *    UFDR      update FIFO data register
+ */
+
+#define _UFCR   _SA1101(0x00120000)   /* Update FIFO Control Reg. */
+#define _UFSR   _SA1101(0x00120400)   /* Update FIFO Status Reg. */     
+#define _UFLVLR _SA1101(0x00120800)   /* Update FIFO level reg. */
+#define _UFDR   _SA1101(0x00120c00)   /* Update FIFO data reg. */
+
+#if LANGUAGE == C
+
+#define UFCR    (*((volatile Word *) SA1101_p2v (_UFCR)))
+#define UFSR    (*((volatile Word *) SA1101_p2v (_UFSR)))
+#define UFLVLR  (*((volatile Word *) SA1101_p2v (_UFLVLR))) 
+#define UFDR    (*((volatile Word *) SA1101_p2v (_UFDR)))
+
+
+#define UFCR_FifoThreshhold     Fld(7,0)        /* Level for FifoGTn flag */
+
+#define UFSR_FifoGTnFlag        0x01            /* FifoGTn flag */#define UFSR_FifoEmpty                0x80            /* FIFO is empty */
+
+#endif /* LANGUAGE == C */
+
+/* System Controller
+ *
+ * Registers
+ *    SKPCR     Power Control Register
+ *    SKCDR     Clock Divider Register
+ *    DACDR1    DAC1 Data register
+ *    DACDR2    DAC2 Data register
+ */
+
+#define _SKPCR          _SA1101(0x00000400)
+#define _SKCDR          _SA1101(0x00040000)
+#define _DACDR1         _SA1101(0x00060000)
+#define _DACDR2         _SA1101(0x00060400)
+
+#if LANGUAGE == C
+#define SKPCR   (*((volatile Word *) SA1101_p2v (_SKPCR)))
+#define SKCDR   (*((volatile Word *) SA1101_p2v (_SKCDR)))
+#define DACDR1  (*((volatile Word *) SA1101_p2v (_DACDR1)))
+#define DACDR2  (*((volatile Word *) SA1101_p2v (_DACDR2)))
+
+#define SKPCR_UCLKEn         0x01    /* USB Enable */
+#define SKPCR_PCLKEn         0x02    /* PS/2 Enable */
+#define SKPCR_ICLKEn         0x04    /* Interrupt Controller Enable */
+#define SKPCR_VCLKEn         0x08    /* Video Controller Enable */
+#define SKPCR_PICLKEn        0x10    /* parallel port Enable */
+#define SKPCR_DCLKEn         0x20    /* DACs Enable */
+#define SKPCR_nKPADEn        0x40    /* Multiplexer */
+
+#define SKCDR_PLLMul         Fld(7,0)   /* PLL Multiplier */
+#define SKCDR_VCLKEn         Fld(2,7)   /* Video controller clock divider */
+#define SKDCR_BCLKEn         (1<<9)     /* BCLK Divider */
+#define SKDCR_UTESTCLKEn     (1<<10)    /* Route USB clock during test mode */
+#define SKDCR_DivRValue      Fld(6,11)  /* Input clock divider for PLL */
+#define SKDCR_DivNValue      Fld(5,17)  /* Output clock divider for PLL */
+#define SKDCR_PLLRSH         Fld(3,22)  /* PLL bandwidth control */
+#define SKDCR_ChargePump     (1<<25)    /* Charge pump control */
+#define SKDCR_ClkTestMode    (1<<26)    /* Clock output test mode */
+#define SKDCR_ClkTestEn      (1<<27)    /* Test clock generator */
+#define SKDCR_ClkJitterCntl  Fld(3,28)  /* video clock jitter compensation */
+
+#define DACDR_DACCount       Fld(8,0)   /* Count value */
+#define DACDR1_DACCount      DACDR_DACCount
+#define DACDR2_DACCount      DACDR_DACCount
+
+#endif /* LANGUAGE == C */
+
+/*
+ * Parallel Port Interface
+ *
+ * Registers
+ *    IEEE_Config       IEEE mode selection and programmable attributes
+ *    IEEE_Control      Controls the states of IEEE port control outputs
+ *    IEEE_Data         Forward transfer data register
+ *    IEEE_Addr         Forward transfer address register
+ *    IEEE_Status       Port IO signal status register
+ *    IEEE_IntStatus    Port interrupts status register
+ *    IEEE_FifoLevels   Rx and Tx FIFO interrupt generation levels
+ *    IEEE_InitTime     Forward timeout counter initial value
+ *    IEEE_TimerStatus  Forward timeout counter current value
+ *    IEEE_FifoReset    Reset forward transfer FIFO
+ *    IEEE_ReloadValue  Counter reload value
+ *    IEEE_TestControl  Control testmode
+ *    IEEE_TestDataIn   Test data register
+ *    IEEE_TestDataInEn Enable test data
+ *    IEEE_TestCtrlIn   Test control signals
+ *    IEEE_TestCtrlInEn Enable test control signals
+ *    IEEE_TestDataStat Current data bus value
+ *
+ */
+
+/*
+ * The control registers are defined as offsets from a base address 
+ */
+ 
+#define _IEEE( x ) _SA1101( (x) + __PARALLEL_PORT )
+
+#define _IEEE_Config        _IEEE( 0x0000 )
+#define _IEEE_Control       _IEEE( 0x0400 )
+#define _IEEE_Data          _IEEE( 0x4000 )
+#define _IEEE_Addr          _IEEE( 0x0800 )
+#define _IEEE_Status        _IEEE( 0x0c00 )
+#define _IEEE_IntStatus     _IEEE( 0x1000 )
+#define _IEEE_FifoLevels    _IEEE( 0x1400 )
+#define _IEEE_InitTime      _IEEE( 0x1800 )
+#define _IEEE_TimerStatus   _IEEE( 0x1c00 )
+#define _IEEE_FifoReset     _IEEE( 0x2000 )
+#define _IEEE_ReloadValue   _IEEE( 0x3c00 )
+#define _IEEE_TestControl   _IEEE( 0x2400 )
+#define _IEEE_TestDataIn    _IEEE( 0x2800 )
+#define _IEEE_TestDataInEn  _IEEE( 0x2c00 )
+#define _IEEE_TestCtrlIn    _IEEE( 0x3000 )
+#define _IEEE_TestCtrlInEn  _IEEE( 0x3400 )
+#define _IEEE_TestDataStat  _IEEE( 0x3800 )
+ 
+
+#if LANGUAGE == C
+#define IEEE_Config         (*((volatile Word *) SA1101_p2v (_IEEE_Config)))
+#define IEEE_Control        (*((volatile Word *) SA1101_p2v (_IEEE_Control)))
+#define IEEE_Data           (*((volatile Word *) SA1101_p2v (_IEEE_Data)))
+#define IEEE_Addr           (*((volatile Word *) SA1101_p2v (_IEEE_Addr)))
+#define IEEE_Status         (*((volatile Word *) SA1101_p2v (_IEEE_Status)))
+#define IEEE_IntStatus      (*((volatile Word *) SA1101_p2v (_IEEE_IntStatus)))
+#define IEEE_FifoLevels     (*((volatile Word *) SA1101_p2v (_IEEE_FifoLevels)))
+#define IEEE_InitTime       (*((volatile Word *) SA1101_p2v (_IEEE_InitTime)))
+#define IEEE_TimerStatus    (*((volatile Word *) SA1101_p2v (_IEEE_TimerStatus)))
+#define IEEE_FifoReset      (*((volatile Word *) SA1101_p2v (_IEEE_FifoReset)))
+#define IEEE_ReloadValue    (*((volatile Word *) SA1101_p2v (_IEEE_ReloadValue)))
+#define IEEE_TestControl    (*((volatile Word *) SA1101_p2v (_IEEE_TestControl)))
+#define IEEE_TestDataIn     (*((volatile Word *) SA1101_p2v (_IEEE_TestDataIn)))
+#define IEEE_TestDataInEn   (*((volatile Word *) SA1101_p2v (_IEEE_TestDataInEn)))
+#define IEEE_TestCtrlIn     (*((volatile Word *) SA1101_p2v (_IEEE_TestCtrlIn)))
+#define IEEE_TestCtrlInEn   (*((volatile Word *) SA1101_p2v (_IEEE_TestCtrlInEn)))
+#define IEEE_TestDataStat   (*((volatile Word *) SA1101_p2v (_IEEE_TestDataStat)))
+
+
+#define IEEE_Config_M       Fld(3,0)     /* Mode select */
+#define IEEE_Config_D       0x04         /* FIFO access enable */
+#define IEEE_Config_B       0x08         /* 9-bit word enable */
+#define IEEE_Config_T       0x10         /* Data transfer enable */
+#define IEEE_Config_A       0x20         /* Data transfer direction */
+#define IEEE_Config_E       0x40         /* Timer enable */
+#define IEEE_Control_A      0x08         /* AutoFd output */
+#define IEEE_Control_E      0x04         /* Selectin output */
+#define IEEE_Control_T      0x02         /* Strobe output */
+#define IEEE_Control_I      0x01         /* Port init output */
+#define IEEE_Data_C         (1<<31)      /* Byte count */
+#define IEEE_Data_Db        Fld(9,16)    /* Data byte 2 */
+#define IEEE_Data_Da        Fld(9,0)     /* Data byte 1 */
+#define IEEE_Addr_A         Fld(8,0)     /* forward address transfer byte */
+#define IEEE_Status_A       0x0100       /* nAutoFd port output status */
+#define IEEE_Status_E       0x0080       /* nSelectIn port output status */
+#define IEEE_Status_T       0x0040       /* nStrobe port output status */
+#define IEEE_Status_I       0x0020       /* nInit port output status */
+#define IEEE_Status_B       0x0010       /* Busy port inout status */
+#define IEEE_Status_S       0x0008       /* Select port input status */
+#define IEEE_Status_K       0x0004       /* nAck port input status */
+#define IEEE_Status_F       0x0002       /* nFault port input status */
+#define IEEE_Status_R       0x0001       /* pError port input status */
+
+#define IEEE_IntStatus_IntReqDat         0x0100
+#define IEEE_IntStatus_IntReqEmp         0x0080
+#define IEEE_IntStatus_IntReqInt         0x0040
+#define IEEE_IntStatus_IntReqRav         0x0020
+#define IEEE_IntStatus_IntReqTim         0x0010
+#define IEEE_IntStatus_RevAddrComp       0x0008
+#define IEEE_IntStatus_RevDataComp       0x0004
+#define IEEE_IntStatus_FwdAddrComp       0x0002
+#define IEEE_IntStatus_FwdDataComp       0x0001
+#define IEEE_FifoLevels_RevFifoLevel     2
+#define IEEE_FifoLevels_FwdFifoLevel     1
+#define IEEE_InitTime_TimValInit         Fld(22,0)
+#define IEEE_TimerStatus_TimValStat      Fld(22,0)
+#define IEEE_ReloadValue_Reload          Fld(4,0)
+
+#define IEEE_TestControl_RegClk          0x04
+#define IEEE_TestControl_ClockSelect     Fld(2,1)
+#define IEEE_TestControl_TimerTestModeEn 0x01
+#define IEEE_TestCtrlIn_PError           0x10
+#define IEEE_TestCtrlIn_nFault           0x08
+#define IEEE_TestCtrlIn_nAck             0x04
+#define IEEE_TestCtrlIn_PSel             0x02
+#define IEEE_TestCtrlIn_Busy             0x01
+
+#endif /* LANGUAGE == C */
+
+/*
+ * VGA Controller
+ *
+ * Registers
+ *    VideoControl      Video Control Register
+ *    VgaTiming0        VGA Timing Register 0
+ *    VgaTiming1        VGA Timing Register 1
+ *    VgaTiming2        VGA Timing Register 2
+ *    VgaTiming3        VGA Timing Register 3
+ *    VgaBorder         VGA Border Color Register
+ *    VgaDBAR           VGADMA Base Address Register
+ *    VgaDCAR           VGADMA Channel Current Address Register
+ *    VgaStatus         VGA Status Register
+ *    VgaInterruptMask  VGA Interrupt Mask Register
+ *    VgaPalette        VGA Palette Registers
+ *    DacControl        DAC Control Register
+ *    VgaTest           VGA Controller Test Register
+ */
+
+#define _VGA( x )       _SA1101( ( x ) + __VGA_CONTROL )
+
+#define _VideoControl       _VGA( 0x0000 )
+#define _VgaTiming0         _VGA( 0x0400 )
+#define _VgaTiming1         _VGA( 0x0800 )
+#define _VgaTiming2         _VGA( 0x0c00 )
+#define _VgaTiming3         _VGA( 0x1000 )
+#define _VgaBorder          _VGA( 0x1400 )
+#define _VgaDBAR            _VGA( 0x1800 )
+#define _VgaDCAR            _VGA( 0x1c00 )
+#define _VgaStatus          _VGA( 0x2000 )
+#define _VgaInterruptMask   _VGA( 0x2400 )
+#define _VgaPalette         _VGA( 0x40000 )
+#define _DacControl         _VGA( 0x3000 )
+#define _VgaTest            _VGA( 0x2c00 )
+
+#if (LANGUAGE == C)
+#define VideoControl   (*((volatile Word *) SA1101_p2v (_VideoControl)))
+#define VgaTiming0     (*((volatile Word *) SA1101_p2v (_VgaTiming0)))
+#define VgaTiming1     (*((volatile Word *) SA1101_p2v (_VgaTiming1)))
+#define VgaTiming2     (*((volatile Word *) SA1101_p2v (_VgaTiming2)))
+#define VgaTiming3     (*((volatile Word *) SA1101_p2v (_VgaTiming3)))
+#define VgaBorder      (*((volatile Word *) SA1101_p2v (_VgaBorder)))
+#define VgaDBAR        (*((volatile Word *) SA1101_p2v (_VgaDBAR)))
+#define VgaDCAR        (*((volatile Word *) SA1101_p2v (_VgaDCAR)))
+#define VgaStatus      (*((volatile Word *) SA1101_p2v (_VgaStatus)))
+#define VgaInterruptMask (*((volatile Word *) SA1101_p2v (_VgaInterruptMask)))
+#define VgaPalette     (*((volatile Word *) SA1101_p2v (_VgaPalette)))
+#define DacControl     (*((volatile Word *) SA1101_p2v (_DacControl)))
+#define VgaTest        (*((volatile Word *) SA1101_p2v (_VgaTest)))
+
+#define VideoControl_VgaEn    0x00000000
+#define VideoControl_BGR      0x00000001
+#define VideoControl_VCompVal Fld(2,2)
+#define VideoControl_VgaReq   Fld(4,4)
+#define VideoControl_VBurstL  Fld(4,8)
+#define VideoControl_VMode    (1<<12)
+#define VideoControl_PalRead  (1<<13)
+
+#define VgaTiming0_PPL        Fld(6,2)
+#define VgaTiming0_HSW        Fld(8,8)
+#define VgaTiming0_HFP        Fld(8,16)
+#define VgaTiming0_HBP        Fld(8,24)
+
+#define VgaTiming1_LPS        Fld(10,0)
+#define VgaTiming1_VSW        Fld(6,10)
+#define VgaTiming1_VFP        Fld(8,16)
+#define VgaTiming1_VBP        Fld(8,24)
+
+#define VgaTiming2_IVS        0x01
+#define VgaTiming2_IHS        0x02
+#define VgaTiming2_CVS        0x04
+#define VgaTiming2_CHS        0x08
+
+#define VgaTiming3_HBS        Fld(8,0)
+#define VgaTiming3_HBE        Fld(8,8)
+#define VgaTiming3_VBS        Fld(8,16)
+#define VgaTiming3_VBE        Fld(8,24)
+
+#define VgaBorder_BCOL        Fld(24,0)
+
+#define VgaStatus_VFUF        0x01
+#define VgaStatus_VNext       0x02
+#define VgaStatus_VComp       0x04
+
+#define VgaInterruptMask_VFUFMask   0x00
+#define VgaInterruptMask_VNextMask  0x01
+#define VgaInterruptMask_VCompMask  0x02
+
+#define VgaPalette_R          Fld(8,0)
+#define VgaPalette_G          Fld(8,8)
+#define VgaPalette_B          Fld(8,16)
+
+#define DacControl_DACON      0x0001
+#define DacControl_COMPON     0x0002
+#define DacControl_PEDON      0x0004
+#define DacControl_RTrim      Fld(5,4)
+#define DacControl_GTrim      Fld(5,9)
+#define DacControl_BTrim      Fld(5,14)
+
+#define VgaTest_TDAC          0x00
+#define VgaTest_Datatest      Fld(4,1)
+#define VgaTest_DACTESTDAC    0x10
+#define VgaTest_DACTESTOUT    Fld(3,5)
+
+#endif /* LANGUAGE == C */
+
+/*
+ * USB Host Interface Controller
+ *
+ * Registers
+ *    Revision
+ *    Control
+ *    CommandStatus
+ *    InterruptStatus
+ *    InterruptEnable
+ *    HCCA
+ *    PeriodCurrentED
+ *    ControlHeadED
+ *    BulkHeadED
+ *    BulkCurrentED
+ *    DoneHead
+ *    FmInterval
+ *    FmRemaining
+ *    FmNumber
+ *    PeriodicStart
+ *    LSThreshold
+ *    RhDescriptorA
+ *    RhDescriptorB
+ *    RhStatus
+ *    RhPortStatus
+ *    USBStatus
+ *    USBReset
+ *    USTAR
+ *    USWER
+ *    USRFR
+ *    USNFR
+ *    USTCSR
+ *    USSR
+ *    
+ */
+
+#define _USB( x )       _SA1101( ( x ) + __USB_CONTROL )
+
+
+#define _Revision         _USB( 0x0000 )
+#define _Control          _USB( 0x0888 )
+#define _CommandStatus    _USB( 0x0c00 )
+#define _InterruptStatus  _USB( 0x1000 )
+#define _InterruptEnable  _USB( 0x1400 )
+#define _HCCA             _USB( 0x1800 )
+#define _PeriodCurrentED  _USB( 0x1c00 )
+#define _ControlHeadED    _USB( 0x2000 )
+#define _BulkHeadED       _USB( 0x2800 )
+#define _BulkCurrentED    _USB( 0x2c00 )
+#define _DoneHead         _USB( 0x3000 )
+#define _FmInterval       _USB( 0x3400 )
+#define _FmRemaining      _USB( 0x3800 )
+#define _FmNumber         _USB( 0x3c00 )
+#define _PeriodicStart    _USB( 0x4000 )
+#define _LSThreshold      _USB( 0x4400 )
+#define _RhDescriptorA    _USB( 0x4800 )
+#define _RhDescriptorB    _USB( 0x4c00 )
+#define _RhStatus         _USB( 0x5000 )
+#define _RhPortStatus     _USB( 0x5400 )
+#define _USBStatus        _USB( 0x11800 )
+#define _USBReset         _USB( 0x11c00 )
+
+#define _USTAR            _USB( 0x10400 )
+#define _USWER            _USB( 0x10800 )
+#define _USRFR            _USB( 0x10c00 )
+#define _USNFR            _USB( 0x11000 )
+#define _USTCSR           _USB( 0x11400 )
+#define _USSR             _USB( 0x11800 )
+
+
+#if (LANGUAGE == C)
+
+#define Revision        (*((volatile Word *) SA1101_p2v (_Revision)))
+#define Control         (*((volatile Word *) SA1101_p2v (_Control)))
+#define CommandStatus   (*((volatile Word *) SA1101_p2v (_CommandStatus)))
+#define InterruptStatus (*((volatile Word *) SA1101_p2v (_InterruptStatus)))
+#define InterruptEnable (*((volatile Word *) SA1101_p2v (_InterruptEnable)))
+#define HCCA            (*((volatile Word *) SA1101_p2v (_HCCA)))
+#define PeriodCurrentED (*((volatile Word *) SA1101_p2v (_PeriodCurrentED)))
+#define ControlHeadED   (*((volatile Word *) SA1101_p2v (_ControlHeadED)))
+#define BulkHeadED      (*((volatile Word *) SA1101_p2v (_BulkHeadED)))
+#define BulkCurrentED   (*((volatile Word *) SA1101_p2v (_BulkCurrentED)))
+#define DoneHead        (*((volatile Word *) SA1101_p2v (_DoneHead)))
+#define FmInterval      (*((volatile Word *) SA1101_p2v (_FmInterval)))
+#define FmRemaining     (*((volatile Word *) SA1101_p2v (_FmRemaining)))
+#define FmNumber        (*((volatile Word *) SA1101_p2v (_FmNumber)))
+#define PeriodicStart   (*((volatile Word *) SA1101_p2v (_PeriodicStart)))
+#define LSThreshold     (*((volatile Word *) SA1101_p2v (_LSThreshold)))
+#define RhDescriptorA   (*((volatile Word *) SA1101_p2v (_RhDescriptorA)))
+#define RhDescriptorB   (*((volatile Word *) SA1101_p2v (_RhDescriptorB)))
+#define RhStatus        (*((volatile Word *) SA1101_p2v (_RhStatus)))
+#define RhPortStatus    (*((volatile Word *) SA1101_p2v (_RhPortStatus)))
+#define USBStatus       (*((volatile Word *) SA1101_p2v (_USBStatus)))
+#define USBReset        (*((volatile Word *) SA1101_p2v (_USBReset)))
+#define USTAR           (*((volatile Word *) SA1101_p2v (_USTAR)))
+#define USWER           (*((volatile Word *) SA1101_p2v (_USWER)))
+#define USRFR           (*((volatile Word *) SA1101_p2v (_USRFR)))
+#define USNFR           (*((volatile Word *) SA1101_p2v (_USNFR)))
+#define USTCSR          (*((volatile Word *) SA1101_p2v (_USTCSR)))
+#define USSR            (*((volatile Word *) SA1101_p2v (_USSR)))
+
+
+#define USBStatus_IrqHciRmtWkp       (1<<7)
+#define USBStatus_IrqHciBuffAcc      (1<<8)
+#define USBStatus_nIrqHciM           (1<<9)
+#define USBStatus_nHciMFClr          (1<<10)
+
+#define USBReset_ForceIfReset        0x01
+#define USBReset_ForceHcReset        0x02
+#define USBReset_ClkGenReset         0x04
+
+#define USTCR_RdBstCntrl             Fld(3,0)
+#define USTCR_ByteEnable             Fld(4,3)
+#define USTCR_WriteEn                (1<<7)
+#define USTCR_FifoCir                (1<<8)
+#define USTCR_TestXferSel            (1<<9)
+#define USTCR_FifoCirAtEnd           (1<<10)
+#define USTCR_nSimScaleDownClk       (1<<11)
+
+#define USSR_nAppMDEmpty             0x01
+#define USSR_nAppMDFirst             0x02
+#define USSR_nAppMDLast              0x04
+#define USSR_nAppMDFull              0x08
+#define USSR_nAppMAFull              0x10
+#define USSR_XferReq                 0x20
+#define USSR_XferEnd                 0x40
+
+#endif /* LANGUAGE == C */
+
+
+/*
+ * Interrupt Controller
+ *
+ * Registers
+ *    INTTEST0          Test register 0
+ *    INTTEST1          Test register 1
+ *    INTENABLE0        Interrupt Enable register 0
+ *    INTENABLE1        Interrupt Enable register 1
+ *    INTPOL0           Interrupt Polarity selection 0
+ *    INTPOL1           Interrupt Polarity selection 1
+ *    INTTSTSEL         Interrupt source selection
+ *    INTSTATCLR0       Interrupt Status 0
+ *    INTSTATCLR1       Interrupt Status 1
+ *    INTSET0           Interrupt Set 0
+ *    INTSET1           Interrupt Set 1
+ */
+
+#define _INT( x )       _SA1101( ( x ) + __INTERRUPT_CONTROL)
+
+#define _INTTEST0       _INT( 0x1000 )
+#define _INTTEST1       _INT( 0x1400 )
+#define _INTENABLE0     _INT( 0x2000 )
+#define _INTENABLE1     _INT( 0x2400 )
+#define _INTPOL0        _INT( 0x3000 )
+#define _INTPOL1        _INT( 0x3400 )
+#define _INTTSTSEL      _INT( 0x5000 )
+#define _INTSTATCLR0    _INT( 0x6000 )
+#define _INTSTATCLR1    _INT( 0x6400 )
+#define _INTSET0        _INT( 0x7000 )
+#define _INTSET1        _INT( 0x7400 )
+
+#if ( LANGUAGE == C )
+#define INTTEST0        (*((volatile Word *) SA1101_p2v (_INTTEST0)))
+#define INTTEST1        (*((volatile Word *) SA1101_p2v (_INTTEST1)))
+#define INTENABLE0      (*((volatile Word *) SA1101_p2v (_INTENABLE0)))
+#define INTENABLE1      (*((volatile Word *) SA1101_p2v (_INTENABLE1)))
+#define INTPOL0         (*((volatile Word *) SA1101_p2v (_INTPOL0)))
+#define INTPOL1         (*((volatile Word *) SA1101_p2v (_INTPOL1)))
+#define INTTSTSEL       (*((volatile Word *) SA1101_p2v (_INTTSTSEL)))
+#define INTSTATCLR0     (*((volatile Word *) SA1101_p2v (_INTSTATCLR0)))
+#define INTSTATCLR1     (*((volatile Word *) SA1101_p2v (_INTSTATCLR1)))
+#define INTSET0         (*((volatile Word *) SA1101_p2v (_INTSET0)))
+#define INTSET1         (*((volatile Word *) SA1101_p2v (_INTSET1)))
+
+#endif /* LANGUAGE == C */
+
+/*
+ * PS/2 Trackpad and Mouse Interfaces
+ *
+ * Registers   (prefix kbd applies to trackpad interface, mse to mouse)
+ *    KBDCR             Control Register
+ *    KBDSTAT           Status Register
+ *    KBDDATA           Transmit/Receive Data register
+ *    KBDCLKDIV         Clock Division Register
+ *    KBDPRECNT         Clock Precount Register
+ *    KBDTEST1          Test register 1
+ *    KBDTEST2          Test register 2
+ *    KBDTEST3          Test register 3
+ *    KBDTEST4          Test register 4
+ *    MSECR     
+ *    MSESTAT
+ *    MSEDATA
+ *    MSECLKDIV
+ *    MSEPRECNT
+ *    MSETEST1
+ *    MSETEST2
+ *    MSETEST3
+ *    MSETEST4
+ *     
+ */
+
+#define _KBD( x )       _SA1101( ( x ) + __TRACK_INTERFACE )
+#define _MSE( x )       _SA1101( ( x ) + __MOUSE_INTERFACE )
+
+#define _KBDCR          _KBD( 0x0000 )
+#define _KBDSTAT        _KBD( 0x0400 )
+#define _KBDDATA        _KBD( 0x0800 )
+#define _KBDCLKDIV      _KBD( 0x0c00 )
+#define _KBDPRECNT      _KBD( 0x1000 )
+#define _KBDTEST1       _KBD( 0x2000 )
+#define _KBDTEST2       _KBD( 0x2400 )
+#define _KBDTEST3       _KBD( 0x2800 )
+#define _KBDTEST4       _KBD( 0x2c00 )
+#define _MSECR          _MSE( 0x0000 )
+#define _MSESTAT        _MSE( 0x0400 )
+#define _MSEDATA        _MSE( 0x0800 )
+#define _MSECLKDIV      _MSE( 0x0c00 )
+#define _MSEPRECNT      _MSE( 0x1000 )
+#define _MSETEST1       _MSE( 0x2000 )
+#define _MSETEST2       _MSE( 0x2400 )
+#define _MSETEST3       _MSE( 0x2800 )
+#define _MSETEST4       _MSE( 0x2c00 )
+
+#if ( LANGUAGE == C )
+
+#define KBDCR       (*((volatile Word *) SA1101_p2v (_KBDCR)))
+#define KBDSTAT     (*((volatile Word *) SA1101_p2v (_KBDSTAT)))
+#define KBDDATA     (*((volatile Word *) SA1101_p2v (_KBDDATA)))
+#define KBDCLKDIV   (*((volatile Word *) SA1101_p2v (_KBDCLKDIV)))
+#define KBDPRECNT   (*((volatile Word *) SA1101_p2v (_KBDPRECNT)))
+#define KBDTEST1    (*((volatile Word *) SA1101_p2v (_KBDTEST1)))
+#define KBDTEST2    (*((volatile Word *) SA1101_p2v (_KBDTEST2)))
+#define KBDTEST3    (*((volatile Word *) SA1101_p2v (_KBDTEST3)))
+#define KBDTEST4    (*((volatile Word *) SA1101_p2v (_KBDTEST4)))
+#define MSECR       (*((volatile Word *) SA1101_p2v (_MSECR)))
+#define MSESTAT     (*((volatile Word *) SA1101_p2v (_MSESTAT)))
+#define MSEDATA     (*((volatile Word *) SA1101_p2v (_MSEDATA)))
+#define MSECLKDIV   (*((volatile Word *) SA1101_p2v (_MSECLKDIV)))
+#define MSEPRECNT   (*((volatile Word *) SA1101_p2v (_MSEPRECNT)))
+#define MSETEST1    (*((volatile Word *) SA1101_p2v (_MSETEST1)))
+#define MSETEST2    (*((volatile Word *) SA1101_p2v (_MSETEST2)))
+#define MSETEST3    (*((volatile Word *) SA1101_p2v (_MSETEST3)))
+#define MSETEST4    (*((volatile Word *) SA1101_p2v (_MSETEST4)))
+
+
+#define KBDCR_ENA                0x08
+#define KBDCR_FKD                0x02
+#define KBDCR_FKC                0x01
+
+#define KBDSTAT_TXE              0x80
+#define KBDSTAT_TXB              0x40
+#define KBDSTAT_RXF              0x20
+#define KBDSTAT_RXB              0x10
+#define KBDSTAT_ENA              0x08
+#define KBDSTAT_RXP              0x04
+#define KBDSTAT_KBD              0x02
+#define KBDSTAT_KBC              0x01
+
+#define KBDCLKDIV_DivVal         Fld(4,0)
+
+#define MSECR_ENA                0x08
+#define MSECR_FKD                0x02
+#define MSECR_FKC                0x01
+
+#define MSESTAT_TXE              0x80
+#define MSESTAT_TXB              0x40
+#define MSESTAT_RXF              0x20
+#define MSESTAT_RXB              0x10
+#define MSESTAT_ENA              0x08
+#define MSESTAT_RXP              0x04   
+#define MSESTAT_MSD              0x02
+#define MSESTAT_MSC              0x01
+
+#define MSECLKDIV_DivVal         Fld(4,0)
+
+#define KBDTEST1_CD              0x80
+#define KBDTEST1_RC1             0x40
+#define KBDTEST1_MC              0x20
+#define KBDTEST1_C               Fld(2,3)
+#define KBDTEST1_T2              0x40
+#define KBDTEST1_T1              0x20
+#define KBDTEST1_T0              0x10
+#define KBDTEST2_TICBnRES        0x08
+#define KBDTEST2_RKC             0x04
+#define KBDTEST2_RKD             0x02
+#define KBDTEST2_SEL             0x01
+#define KBDTEST3_ms_16           0x80
+#define KBDTEST3_us_64           0x40
+#define KBDTEST3_us_16           0x20
+#define KBDTEST3_DIV8            0x10
+#define KBDTEST3_DIn             0x08
+#define KBDTEST3_CIn             0x04
+#define KBDTEST3_KD              0x02
+#define KBDTEST3_KC              0x01
+#define KBDTEST4_BC12            0x80
+#define KBDTEST4_BC11            0x40
+#define KBDTEST4_TRES            0x20
+#define KBDTEST4_CLKOE           0x10
+#define KBDTEST4_CRES            0x08
+#define KBDTEST4_RXB             0x04
+#define KBDTEST4_TXB             0x02
+#define KBDTEST4_SRX             0x01
+
+#define MSETEST1_CD              0x80
+#define MSETEST1_RC1             0x40
+#define MSETEST1_MC              0x20
+#define MSETEST1_C               Fld(2,3)
+#define MSETEST1_T2              0x40
+#define MSETEST1_T1              0x20
+#define MSETEST1_T0              0x10
+#define MSETEST2_TICBnRES        0x08
+#define MSETEST2_RKC             0x04
+#define MSETEST2_RKD             0x02
+#define MSETEST2_SEL             0x01
+#define MSETEST3_ms_16           0x80
+#define MSETEST3_us_64           0x40
+#define MSETEST3_us_16           0x20
+#define MSETEST3_DIV8            0x10
+#define MSETEST3_DIn             0x08
+#define MSETEST3_CIn             0x04
+#define MSETEST3_KD              0x02
+#define MSETEST3_KC              0x01
+#define MSETEST4_BC12            0x80
+#define MSETEST4_BC11            0x40
+#define MSETEST4_TRES            0x20
+#define MSETEST4_CLKOE           0x10
+#define MSETEST4_CRES            0x08
+#define MSETEST4_RXB             0x04
+#define MSETEST4_TXB             0x02
+#define MSETEST4_SRX             0x01
+
+#endif  /* LANGUAGE == C */
+
+
+/*
+ * General-Purpose I/O Interface
+ *
+ * Registers
+ *    PADWR     Port A Data Write Register
+ *    PBDWR     Port B Data Write Register
+ *    PADRR     Port A Data Read Register
+ *    PBDRR     Port B Data Read Register
+ *    PADDR     Port A Data Direction Register
+ *    PBDDR     Port B Data Direction Register
+ *    PASSR     Port A Sleep State Register
+ *    PBSSR     Port B Sleep State Register
+ *
+ */
+
+#define _PIO( x )      _SA1101( ( x ) + __GPIO_INTERFACE )
+
+#define _PADWR         _PIO( 0x0000 )
+#define _PBDWR         _PIO( 0x0400 )
+#define _PADRR         _PIO( 0x0000 )
+#define _PBDRR         _PIO( 0x0400 )
+#define _PADDR         _PIO( 0x0800 )
+#define _PBDDR         _PIO( 0x0c00 )
+#define _PASSR         _PIO( 0x1000 )
+#define _PBSSR         _PIO( 0x1400 )
+
+
+#if ( LANGUAGE == C )
+
+
+#define PADWR       (*((volatile Word *) SA1101_p2v (_PADWR)))
+#define PBDWR       (*((volatile Word *) SA1101_p2v (_PBDWR)))
+#define PADRR       (*((volatile Word *) SA1101_p2v (_PADRR)))
+#define PBDRR       (*((volatile Word *) SA1101_p2v (_PBDRR)))
+#define PADDR       (*((volatile Word *) SA1101_p2v (_PADDR)))
+#define PBDDR       (*((volatile Word *) SA1101_p2v (_PBDDR)))
+#define PASSR       (*((volatile Word *) SA1101_p2v (_PASSR)))
+#define PBSSR       (*((volatile Word *) SA1101_p2v (_PBSSR)))
+
+#endif
+
+
+
+/*
+ * Keypad Interface
+ *
+ * Registers
+ *    PXDWR
+ *    PXDRR
+ *    PYDWR
+ *    PYDRR
+ *
+ */
+
+#define _KEYPAD( x )    _SA1101( ( x ) + __KEYPAD_INTERFACE ) 
+
+#define _PXDWR     _KEYPAD( 0x0000 )
+#define _PXDRR     _KEYPAD( 0x0000 )
+#define _PYDWR     _KEYPAD( 0x0400 )
+#define _PYDRR     _KEYPAD( 0x0400 )
+
+#if ( LANGUAGE == C )
+
+
+#define PXDWR       (*((volatile Word *) SA1101_p2v (_PXDWR)))
+#define PXDRR       (*((volatile Word *) SA1101_p2v (_PXDRR)))
+#define PYDWR       (*((volatile Word *) SA1101_p2v (_PYDWR)))
+#define PYDRR       (*((volatile Word *) SA1101_p2v (_PYDRR)))
+
+#endif
+
+
+
+/*
+ * PCMCIA Interface
+ *
+ * Registers
+ *    PCSR      Status Register
+ *    PCCR      Control Register
+ *    PCSSR     Sleep State Register
+ *
+ */
+
+#define _CARD( x )      _SA1101( ( x ) + __PCMCIA_INTERFACE )
+
+#define _PCSR      _CARD( 0x0000 )
+#define _PCCR      _CARD( 0x0400 )
+#define _PCSSR     _CARD( 0x0800 )
+
+#if ( LANGUAGE == C )
+#define PCSR    (*((volatile Word *) SA1101_p2v (_PCSR)))
+#define PCCR    (*((volatile Word *) SA1101_p2v (_PCCR)))
+#define PCSSR   (*((volatile Word *) SA1101_p2v (_PCSSR)))
+
+#define PCSR_S0_ready           0x0001
+#define PCSR_S1_ready           0x0002
+#define PCSR_S0_detected        0x0004
+#define PCSR_S1_detected        0x0008
+#define PCSR_S0_VS1             0x0010
+#define PCSR_S0_VS2             0x0020
+#define PCSR_S1_VS1             0x0040
+#define PCSR_S1_VS2             0x0080
+#define PCSR_S0_WP              0x0100
+#define PCSR_S1_WP              0x0200
+#define PCSR_S0_BVD1_nSTSCHG    0x0400
+#define PCSR_S0_BVD2_nSPKR      0x0800
+#define PCSR_S1_BVD1_nSTSCHG    0x1000
+#define PCSR_S1_BVD2_nSPKR      0x2000
+
+#define PCCR_S0_VPP0            0x0001
+#define PCCR_S0_VPP1            0x0002
+#define PCCR_S0_VCC0            0x0004
+#define PCCR_S0_VCC1            0x0008
+#define PCCR_S1_VPP0            0x0010
+#define PCCR_S1_VPP1            0x0020
+#define PCCR_S1_VCC0            0x0040
+#define PCCR_S1_VCC1            0x0080
+#define PCCR_S0_reset           0x0100
+#define PCCR_S1_reset           0x0200
+#define PCCR_S0_float           0x0400
+#define PCCR_S1_float           0x0800
+
+#define PCSSR_S0_VCC0           0x0001
+#define PCSSR_S0_VCC1           0x0002
+#define PCSSR_S0_VPP0           0x0004
+#define PCSSR_S0_VPP1           0x0008
+#define PCSSR_S0_control        0x0010
+#define PCSSR_S1_VCC0           0x0020
+#define PCSSR_S1_VCC1           0x0040
+#define PCSSR_S1_VPP0           0x0080
+#define PCSSR_S1_VPP1           0x0100
+#define PCSSR_S1_control        0x0200
+
+#endif
+
+#undef C
+#undef Assembly
diff --git a/include/asm-arm/arch-sa1100/SA-1111.h b/arch/arm/mach-sa1100/include/mach/SA-1111.h
index c38f60915cb6..c38f60915cb6 100644
--- a/include/asm-arm/arch-sa1100/SA-1111.h
+++ b/arch/arm/mach-sa1100/include/mach/SA-1111.h
diff --git a/arch/arm/mach-sa1100/include/mach/assabet.h b/arch/arm/mach-sa1100/include/mach/assabet.h
new file mode 100644
index 000000000000..3959b20d5d1c
--- /dev/null
+++ b/arch/arm/mach-sa1100/include/mach/assabet.h
@@ -0,0 +1,105 @@
+/*
+ * arch/arm/mach-sa1100/include/mach/assabet.h
+ *
+ * Created 2000/06/05 by Nicolas Pitre <nico@cam.org>
+ *
+ * This file contains the hardware specific definitions for Assabet
+ * Only include this file from SA1100-specific files.
+ *
+ * 2000/05/23 John Dorsey <john+@cs.cmu.edu>
+ *      Definitions for Neponset added.
+ */
+#ifndef __ASM_ARCH_ASSABET_H
+#define __ASM_ARCH_ASSABET_H
+
+
+/* System Configuration Register flags */
+
+#define ASSABET_SCR_SDRAM_LOW   (1<<2)  /* SDRAM size (low bit) */
+#define ASSABET_SCR_SDRAM_HIGH  (1<<3)  /* SDRAM size (high bit) */
+#define ASSABET_SCR_FLASH_LOW   (1<<4)  /* Flash size (low bit) */
+#define ASSABET_SCR_FLASH_HIGH  (1<<5)  /* Flash size (high bit) */
+#define ASSABET_SCR_GFX         (1<<8)  /* Graphics Accelerator (0 = present) */
+#define ASSABET_SCR_SA1111      (1<<9)  /* Neponset (0 = present) */
+
+#define ASSABET_SCR_INIT        -1
+
+extern unsigned long SCR_value;
+
+#ifdef CONFIG_ASSABET_NEPONSET
+#define machine_has_neponset()  ((SCR_value & ASSABET_SCR_SA1111) == 0)
+#else
+#define machine_has_neponset()  (0)
+#endif
+
+/* Board Control Register */
+
+#define ASSABET_BCR_BASE  0xf1000000
+#define ASSABET_BCR (*(volatile unsigned int *)(ASSABET_BCR_BASE))
+
+#define ASSABET_BCR_CF_PWR      (1<<0)  /* Compact Flash Power (1 = 3.3v, 0 = off) */
+#define ASSABET_BCR_CF_RST      (1<<1)  /* Compact Flash Reset (1 = power up reset) */
+#define ASSABET_BCR_GFX_RST     (1<<1)  /* Graphics Accelerator Reset (0 = hold reset) */
+#define ASSABET_BCR_CODEC_RST   (1<<2)  /* 0 = Holds UCB1300, ADI7171, and UDA1341 in reset */
+#define ASSABET_BCR_IRDA_FSEL   (1<<3)  /* IRDA Frequency select (0 = SIR, 1 = MIR/ FIR) */
+#define ASSABET_BCR_IRDA_MD0    (1<<4)  /* Range/Power select */
+#define ASSABET_BCR_IRDA_MD1    (1<<5)  /* Range/Power select */
+#define ASSABET_BCR_STEREO_LB   (1<<6)  /* Stereo Loopback */
+#define ASSABET_BCR_CF_BUS_OFF  (1<<7)  /* Compact Flash bus (0 = on, 1 = off (float)) */
+#define ASSABET_BCR_AUDIO_ON    (1<<8)  /* Audio power on */
+#define ASSABET_BCR_LIGHT_ON    (1<<9)  /* Backlight */
+#define ASSABET_BCR_LCD_12RGB   (1<<10) /* 0 = 16RGB, 1 = 12RGB */
+#define ASSABET_BCR_LCD_ON      (1<<11) /* LCD power on */
+#define ASSABET_BCR_RS232EN     (1<<12) /* RS232 transceiver enable */
+#define ASSABET_BCR_LED_RED     (1<<13) /* D9 (0 = on, 1 = off) */
+#define ASSABET_BCR_LED_GREEN   (1<<14) /* D8 (0 = on, 1 = off) */
+#define ASSABET_BCR_VIB_ON      (1<<15) /* Vibration motor (quiet alert) */
+#define ASSABET_BCR_COM_DTR     (1<<16) /* COMport Data Terminal Ready */
+#define ASSABET_BCR_COM_RTS     (1<<17) /* COMport Request To Send */
+#define ASSABET_BCR_RAD_WU      (1<<18) /* Radio wake up interrupt */
+#define ASSABET_BCR_SMB_EN      (1<<19) /* System management bus enable */
+#define ASSABET_BCR_TV_IR_DEC   (1<<20) /* TV IR Decode Enable (not implemented) */
+#define ASSABET_BCR_QMUTE       (1<<21) /* Quick Mute */
+#define ASSABET_BCR_RAD_ON      (1<<22) /* Radio Power On */
+#define ASSABET_BCR_SPK_OFF     (1<<23) /* 1 = Speaker amplifier power off */
+
+#ifdef CONFIG_SA1100_ASSABET
+extern void ASSABET_BCR_frob(unsigned int mask, unsigned int set);
+#else
+#define ASSABET_BCR_frob(x,y)   do { } while (0)
+#endif
+
+#define ASSABET_BCR_set(x)      ASSABET_BCR_frob((x), (x))
+#define ASSABET_BCR_clear(x)    ASSABET_BCR_frob((x), 0)
+
+#define ASSABET_BSR_BASE        0xf1000000
+#define ASSABET_BSR (*(volatile unsigned int*)(ASSABET_BSR_BASE))
+
+#define ASSABET_BSR_RS232_VALID (1 << 24)
+#define ASSABET_BSR_COM_DCD     (1 << 25)
+#define ASSABET_BSR_COM_CTS     (1 << 26)
+#define ASSABET_BSR_COM_DSR     (1 << 27)
+#define ASSABET_BSR_RAD_CTS     (1 << 28)
+#define ASSABET_BSR_RAD_DSR     (1 << 29)
+#define ASSABET_BSR_RAD_DCD     (1 << 30)
+#define ASSABET_BSR_RAD_RI      (1 << 31)
+
+
+/* GPIOs for which the generic definition doesn't say much */
+#define ASSABET_GPIO_RADIO_IRQ          GPIO_GPIO (14)  /* Radio interrupt request  */
+#define ASSABET_GPIO_PS_MODE_SYNC       GPIO_GPIO (16)  /* Power supply mode/sync   */
+#define ASSABET_GPIO_STEREO_64FS_CLK    GPIO_GPIO (19)  /* SSP UDA1341 clock input  */
+#define ASSABET_GPIO_CF_IRQ             GPIO_GPIO (21)  /* CF IRQ   */
+#define ASSABET_GPIO_CF_CD              GPIO_GPIO (22)  /* CF CD */
+#define ASSABET_GPIO_CF_BVD2            GPIO_GPIO (24)  /* CF BVD */
+#define ASSABET_GPIO_GFX_IRQ            GPIO_GPIO (24)  /* Graphics IRQ */
+#define ASSABET_GPIO_CF_BVD1            GPIO_GPIO (25)  /* CF BVD */
+#define ASSABET_GPIO_BATT_LOW           GPIO_GPIO (26)  /* Low battery */
+#define ASSABET_GPIO_RCLK               GPIO_GPIO (26)  /* CCLK/2  */
+
+#define ASSABET_IRQ_GPIO_CF_IRQ         IRQ_GPIO21
+#define ASSABET_IRQ_GPIO_CF_CD          IRQ_GPIO22
+#define ASSABET_IRQ_GPIO_CF_BVD2        IRQ_GPIO24
+#define ASSABET_IRQ_GPIO_CF_BVD1        IRQ_GPIO25
+
+#endif
diff --git a/arch/arm/mach-sa1100/include/mach/badge4.h b/arch/arm/mach-sa1100/include/mach/badge4.h
new file mode 100644
index 000000000000..44d2e1bfc04b
--- /dev/null
+++ b/arch/arm/mach-sa1100/include/mach/badge4.h
@@ -0,0 +1,75 @@
+/*
+ * arch/arm/mach-sa1100/include/mach/badge4.h
+ *
+ *   Tim Connors <connors@hpl.hp.com>
+ *   Christopher Hoover <ch@hpl.hp.com>
+ *
+ * Copyright (C) 2002 Hewlett-Packard Company
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#error "include <mach/hardware.h> instead"
+#endif
+
+#define BADGE4_SA1111_BASE              (0x48000000)
+
+/* GPIOs on the BadgePAD 4 */
+#define BADGE4_GPIO_INT_1111            GPIO_GPIO0   /* SA-1111 IRQ */
+
+#define BADGE4_GPIO_INT_VID             GPIO_GPIO1   /* Video expansion */
+#define BADGE4_GPIO_LGP2                GPIO_GPIO2   /* GPIO_LDD8 */
+#define BADGE4_GPIO_LGP3                GPIO_GPIO3   /* GPIO_LDD9 */
+#define BADGE4_GPIO_LGP4                GPIO_GPIO4   /* GPIO_LDD10 */
+#define BADGE4_GPIO_LGP5                GPIO_GPIO5   /* GPIO_LDD11 */
+#define BADGE4_GPIO_LGP6                GPIO_GPIO6   /* GPIO_LDD12 */
+#define BADGE4_GPIO_LGP7                GPIO_GPIO7   /* GPIO_LDD13 */
+#define BADGE4_GPIO_LGP8                GPIO_GPIO8   /* GPIO_LDD14 */
+#define BADGE4_GPIO_LGP9                GPIO_GPIO9   /* GPIO_LDD15 */
+#define BADGE4_GPIO_GPA_VID             GPIO_GPIO10  /* Video expansion */
+#define BADGE4_GPIO_GPB_VID             GPIO_GPIO11  /* Video expansion */
+#define BADGE4_GPIO_GPC_VID             GPIO_GPIO12  /* Video expansion */
+
+#define BADGE4_GPIO_UART_HS1            GPIO_GPIO13
+#define BADGE4_GPIO_UART_HS2            GPIO_GPIO14
+
+#define BADGE4_GPIO_MUXSEL0             GPIO_GPIO15
+#define BADGE4_GPIO_TESTPT_J7           GPIO_GPIO16
+
+#define BADGE4_GPIO_SDSDA               GPIO_GPIO17  /* SDRAM SPD Data */
+#define BADGE4_GPIO_SDSCL               GPIO_GPIO18  /* SDRAM SPD Clock */
+#define BADGE4_GPIO_SDTYP0              GPIO_GPIO19  /* SDRAM Type Control */
+#define BADGE4_GPIO_SDTYP1              GPIO_GPIO20  /* SDRAM Type Control */
+
+#define BADGE4_GPIO_BGNT_1111           GPIO_GPIO21  /* GPIO_MBGNT */
+#define BADGE4_GPIO_BREQ_1111           GPIO_GPIO22  /* GPIO_TREQA */
+
+#define BADGE4_GPIO_TESTPT_J6           GPIO_GPIO23
+
+#define BADGE4_GPIO_PCMEN5V             GPIO_GPIO24  /* 5V power */
+
+#define BADGE4_GPIO_SA1111_NRST         GPIO_GPIO25  /* SA-1111 nRESET */
+
+#define BADGE4_GPIO_TESTPT_J5           GPIO_GPIO26
+
+#define BADGE4_GPIO_CLK_1111            GPIO_GPIO27  /* GPIO_32_768kHz */
+
+/* Interrupts on the BadgePAD 4 */
+#define BADGE4_IRQ_GPIO_SA1111          IRQ_GPIO0    /* SA-1111 interrupt */
+
+
+/* PCM5ENV Usage tracking */
+
+#define BADGE4_5V_PCMCIA_SOCK0          (1<<0)
+#define BADGE4_5V_PCMCIA_SOCK1          (1<<1)
+#define BADGE4_5V_PCMCIA_SOCK(n)        (1<<(n))
+#define BADGE4_5V_USB                   (1<<2)
+#define BADGE4_5V_INITIALLY             (1<<3)
+
+#ifndef __ASSEMBLY__
+extern void badge4_set_5V(unsigned subsystem, int on);
+#endif
diff --git a/include/asm-arm/arch-sa1100/bitfield.h b/arch/arm/mach-sa1100/include/mach/bitfield.h
index f1f0e3387d9c..f1f0e3387d9c 100644
--- a/include/asm-arm/arch-sa1100/bitfield.h
+++ b/arch/arm/mach-sa1100/include/mach/bitfield.h
diff --git a/arch/arm/mach-sa1100/include/mach/cerf.h b/arch/arm/mach-sa1100/include/mach/cerf.h
new file mode 100644
index 000000000000..c3ac3d0f9465
--- /dev/null
+++ b/arch/arm/mach-sa1100/include/mach/cerf.h
@@ -0,0 +1,28 @@
+/*
+ * arch/arm/mach-sa1100/include/mach/cerf.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Apr-2003 : Removed some old PDA crud [FB]
+ */
+#ifndef _INCLUDE_CERF_H_
+#define _INCLUDE_CERF_H_
+
+
+#define CERF_ETH_IO                     0xf0000000
+#define CERF_ETH_IRQ IRQ_GPIO26
+
+#define CERF_GPIO_CF_BVD2               GPIO_GPIO (19)
+#define CERF_GPIO_CF_BVD1               GPIO_GPIO (20)
+#define CERF_GPIO_CF_RESET              GPIO_GPIO (21)
+#define CERF_GPIO_CF_IRQ                GPIO_GPIO (22)
+#define CERF_GPIO_CF_CD                 GPIO_GPIO (23)
+
+#define CERF_IRQ_GPIO_CF_BVD2           IRQ_GPIO19
+#define CERF_IRQ_GPIO_CF_BVD1           IRQ_GPIO20
+#define CERF_IRQ_GPIO_CF_IRQ            IRQ_GPIO22
+#define CERF_IRQ_GPIO_CF_CD             IRQ_GPIO23
+
+#endif // _INCLUDE_CERF_H_
diff --git a/arch/arm/mach-sa1100/include/mach/collie.h b/arch/arm/mach-sa1100/include/mach/collie.h
new file mode 100644
index 000000000000..69e962416e3f
--- /dev/null
+++ b/arch/arm/mach-sa1100/include/mach/collie.h
@@ -0,0 +1,88 @@
+/*
+ * arch/arm/mach-sa1100/include/mach/collie.h
+ *
+ * This file contains the hardware specific definitions for Assabet
+ * Only include this file from SA1100-specific files.
+ *
+ * ChangeLog:
+ *   04-06-2001 Lineo Japan, Inc.
+ *   04-16-2001 SHARP Corporation
+ *   07-07-2002 Chris Larson <clarson@digi.com>
+ *
+ */
+#ifndef __ASM_ARCH_COLLIE_H
+#define __ASM_ARCH_COLLIE_H
+
+
+#define COLLIE_SCP_CHARGE_ON    SCOOP_GPCR_PA11
+#define COLLIE_SCP_DIAG_BOOT1   SCOOP_GPCR_PA12
+#define COLLIE_SCP_DIAG_BOOT2   SCOOP_GPCR_PA13
+#define COLLIE_SCP_MUTE_L       SCOOP_GPCR_PA14
+#define COLLIE_SCP_MUTE_R       SCOOP_GPCR_PA15
+#define COLLIE_SCP_5VON         SCOOP_GPCR_PA16
+#define COLLIE_SCP_AMP_ON       SCOOP_GPCR_PA17
+#define COLLIE_SCP_VPEN         SCOOP_GPCR_PA18
+#define COLLIE_SCP_LB_VOL_CHG   SCOOP_GPCR_PA19
+
+#define COLLIE_SCOOP_IO_DIR     ( COLLIE_SCP_CHARGE_ON | COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | \
+                                COLLIE_SCP_5VON | COLLIE_SCP_AMP_ON | COLLIE_SCP_VPEN | \
+                                COLLIE_SCP_LB_VOL_CHG )
+#define COLLIE_SCOOP_IO_OUT     ( COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | COLLIE_SCP_VPEN | \
+                                COLLIE_SCP_CHARGE_ON )
+
+/* GPIOs for which the generic definition doesn't say much */
+
+#define COLLIE_GPIO_ON_KEY              GPIO_GPIO (0)
+#define COLLIE_GPIO_AC_IN               GPIO_GPIO (1)
+#define COLLIE_GPIO_SDIO_INT            GPIO_GPIO (11)
+#define COLLIE_GPIO_CF_IRQ              GPIO_GPIO (14)
+#define COLLIE_GPIO_nREMOCON_INT        GPIO_GPIO (15)
+#define COLLIE_GPIO_UCB1x00_RESET       GPIO_GPIO (16)
+#define COLLIE_GPIO_nMIC_ON             GPIO_GPIO (17)
+#define COLLIE_GPIO_nREMOCON_ON         GPIO_GPIO (18)
+#define COLLIE_GPIO_CO                  GPIO_GPIO (20)
+#define COLLIE_GPIO_MCP_CLK             GPIO_GPIO (21)
+#define COLLIE_GPIO_CF_CD               GPIO_GPIO (22)
+#define COLLIE_GPIO_UCB1x00_IRQ         GPIO_GPIO (23)
+#define COLLIE_GPIO_WAKEUP              GPIO_GPIO (24)
+#define COLLIE_GPIO_GA_INT              GPIO_GPIO (25)
+#define COLLIE_GPIO_MAIN_BAT_LOW        GPIO_GPIO (26)
+
+/* Interrupts */
+
+#define COLLIE_IRQ_GPIO_ON_KEY          IRQ_GPIO0
+#define COLLIE_IRQ_GPIO_AC_IN           IRQ_GPIO1
+#define COLLIE_IRQ_GPIO_SDIO_IRQ        IRQ_GPIO11
+#define COLLIE_IRQ_GPIO_CF_IRQ          IRQ_GPIO14
+#define COLLIE_IRQ_GPIO_nREMOCON_INT    IRQ_GPIO15
+#define COLLIE_IRQ_GPIO_CO              IRQ_GPIO20
+#define COLLIE_IRQ_GPIO_CF_CD           IRQ_GPIO22
+#define COLLIE_IRQ_GPIO_UCB1x00_IRQ     IRQ_GPIO23
+#define COLLIE_IRQ_GPIO_WAKEUP          IRQ_GPIO24
+#define COLLIE_IRQ_GPIO_GA_INT          IRQ_GPIO25
+#define COLLIE_IRQ_GPIO_MAIN_BAT_LOW    IRQ_GPIO26
+
+#define COLLIE_LCM_IRQ_GPIO_RTS         IRQ_LOCOMO_GPIO0
+#define COLLIE_LCM_IRQ_GPIO_CTS         IRQ_LOCOMO_GPIO1
+#define COLLIE_LCM_IRQ_GPIO_DSR         IRQ_LOCOMO_GPIO2
+#define COLLIE_LCM_IRQ_GPIO_DTR         IRQ_LOCOMO_GPIO3
+#define COLLIE_LCM_IRQ_GPIO_nSD_DETECT  IRQ_LOCOMO_GPIO13
+#define COLLIE_LCM_IRQ_GPIO_nSD_WP      IRQ_LOCOMO_GPIO14
+
+/* GPIO's on the TC35143AF (Toshiba Analog Frontend) */
+#define COLLIE_TC35143_GPIO_VERSION0    UCB_IO_0        /* GPIO0=Version                 */
+#define COLLIE_TC35143_GPIO_TBL_CHK     UCB_IO_1        /* GPIO1=TBL_CHK                 */
+#define COLLIE_TC35143_GPIO_VPEN_ON     UCB_IO_2        /* GPIO2=VPNE_ON                 */
+#define COLLIE_TC35143_GPIO_IR_ON       UCB_IO_3        /* GPIO3=IR_ON                   */
+#define COLLIE_TC35143_GPIO_AMP_ON      UCB_IO_4        /* GPIO4=AMP_ON                  */
+#define COLLIE_TC35143_GPIO_VERSION1    UCB_IO_5        /* GPIO5=Version                 */
+#define COLLIE_TC35143_GPIO_FS8KLPF     UCB_IO_5        /* GPIO5=fs 8k LPF               */
+#define COLLIE_TC35143_GPIO_BUZZER_BIAS UCB_IO_6        /* GPIO6=BUZZER BIAS             */
+#define COLLIE_TC35143_GPIO_MBAT_ON     UCB_IO_7        /* GPIO7=MBAT_ON                 */
+#define COLLIE_TC35143_GPIO_BBAT_ON     UCB_IO_8        /* GPIO8=BBAT_ON                 */
+#define COLLIE_TC35143_GPIO_TMP_ON      UCB_IO_9        /* GPIO9=TMP_ON                  */
+#define COLLIE_TC35143_GPIO_IN          ( UCB_IO_0 | UCB_IO_2 | UCB_IO_5 )
+#define COLLIE_TC35143_GPIO_OUT         ( UCB_IO_1 | UCB_IO_3 | UCB_IO_4 | UCB_IO_6 | \
+                                        UCB_IO_7 | UCB_IO_8 | UCB_IO_9 )
+
+#endif
diff --git a/arch/arm/mach-sa1100/include/mach/debug-macro.S b/arch/arm/mach-sa1100/include/mach/debug-macro.S
new file mode 100644
index 000000000000..1f0634d92702
--- /dev/null
+++ b/arch/arm/mach-sa1100/include/mach/debug-macro.S
@@ -0,0 +1,58 @@
+/* arch/arm/mach-sa1100/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+#include <mach/hardware.h>
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx, #0x80000000        @ physical base address
+                movne   \rx, #0xf8000000        @ virtual address
+
+                @ We probe for the active serial port here, coherently with
+                @ the comment in arch/arm/mach-sa1100/include/mach/uncompress.h.
+                @ We assume r1 can be clobbered.
+
+                @ see if Ser3 is active
+                add     \rx, \rx, #0x00050000
+                ldr     r1, [\rx, #UTCR3]
+                tst     r1, #UTCR3_TXE
+
+                @ if Ser3 is inactive, then try Ser1
+                addeq   \rx, \rx, #(0x00010000 - 0x00050000)
+                ldreq   r1, [\rx, #UTCR3]
+                tsteq   r1, #UTCR3_TXE
+
+                @ if Ser1 is inactive, then try Ser2
+                addeq   \rx, \rx, #(0x00030000 - 0x00010000)
+                ldreq   r1, [\rx, #UTCR3]
+                tsteq   r1, #UTCR3_TXE
+
+                @ if all ports are inactive, then there is nothing we can do
+                moveq   pc, lr
+                .endm
+
+                .macro  senduart,rd,rx
+                str     \rd, [\rx, #UTDR]
+                .endm
+
+                .macro  waituart,rd,rx
+1001:           ldr     \rd, [\rx, #UTSR1]
+                tst     \rd, #UTSR1_TNF
+                beq     1001b
+                .endm
+
+                .macro  busyuart,rd,rx
+1001:           ldr     \rd, [\rx, #UTSR1]
+                tst     \rd, #UTSR1_TBY
+                bne     1001b
+                .endm
diff --git a/arch/arm/mach-sa1100/include/mach/dma.h b/arch/arm/mach-sa1100/include/mach/dma.h
new file mode 100644
index 000000000000..dda1b351310d
--- /dev/null
+++ b/arch/arm/mach-sa1100/include/mach/dma.h
@@ -0,0 +1,117 @@
+/*
+ * arch/arm/mach-sa1100/include/mach/dma.h
+ *
+ * Generic SA1100 DMA support
+ *
+ * Copyright (C) 2000 Nicolas Pitre
+ *
+ */
+
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+#include "hardware.h"
+
+
+/*
+ * The SA1100 has six internal DMA channels.
+ */
+#define SA1100_DMA_CHANNELS     6
+
+/*
+ * Maximum physical DMA buffer size
+ */
+#define MAX_DMA_SIZE            0x1fff
+#define CUT_DMA_SIZE            0x1000
+
+/*
+ * All possible SA1100 devices a DMA channel can be attached to.
+ */
+typedef enum {
+        DMA_Ser0UDCWr  = DDAR_Ser0UDCWr,   /* Ser. port 0 UDC Write */
+        DMA_Ser0UDCRd  = DDAR_Ser0UDCRd,   /* Ser. port 0 UDC Read */
+        DMA_Ser1UARTWr = DDAR_Ser1UARTWr,  /* Ser. port 1 UART Write */
+        DMA_Ser1UARTRd = DDAR_Ser1UARTRd,  /* Ser. port 1 UART Read */
+        DMA_Ser1SDLCWr = DDAR_Ser1SDLCWr,  /* Ser. port 1 SDLC Write */
+        DMA_Ser1SDLCRd = DDAR_Ser1SDLCRd,  /* Ser. port 1 SDLC Read */
+        DMA_Ser2UARTWr = DDAR_Ser2UARTWr,  /* Ser. port 2 UART Write */
+        DMA_Ser2UARTRd = DDAR_Ser2UARTRd,  /* Ser. port 2 UART Read */
+        DMA_Ser2HSSPWr = DDAR_Ser2HSSPWr,  /* Ser. port 2 HSSP Write */
+        DMA_Ser2HSSPRd = DDAR_Ser2HSSPRd,  /* Ser. port 2 HSSP Read */
+        DMA_Ser3UARTWr = DDAR_Ser3UARTWr,  /* Ser. port 3 UART Write */
+        DMA_Ser3UARTRd = DDAR_Ser3UARTRd,  /* Ser. port 3 UART Read */
+        DMA_Ser4MCP0Wr = DDAR_Ser4MCP0Wr,  /* Ser. port 4 MCP 0 Write (audio) */
+        DMA_Ser4MCP0Rd = DDAR_Ser4MCP0Rd,  /* Ser. port 4 MCP 0 Read (audio) */
+        DMA_Ser4MCP1Wr = DDAR_Ser4MCP1Wr,  /* Ser. port 4 MCP 1 Write */
+        DMA_Ser4MCP1Rd = DDAR_Ser4MCP1Rd,  /* Ser. port 4 MCP 1 Read */
+        DMA_Ser4SSPWr  = DDAR_Ser4SSPWr,   /* Ser. port 4 SSP Write (16 bits) */
+        DMA_Ser4SSPRd  = DDAR_Ser4SSPRd    /* Ser. port 4 SSP Read (16 bits) */
+} dma_device_t;
+
+typedef struct {
+        volatile u_long DDAR;
+        volatile u_long SetDCSR;
+        volatile u_long ClrDCSR;
+        volatile u_long RdDCSR;
+        volatile dma_addr_t DBSA;
+        volatile u_long DBTA;
+        volatile dma_addr_t DBSB;
+        volatile u_long DBTB;
+} dma_regs_t;
+
+typedef void (*dma_callback_t)(void *data);
+
+/*
+ * DMA function prototypes
+ */
+
+extern int sa1100_request_dma( dma_device_t device, const char *device_id,
+                               dma_callback_t callback, void *data,
+                               dma_regs_t **regs );
+extern void sa1100_free_dma( dma_regs_t *regs );
+extern int sa1100_start_dma( dma_regs_t *regs, dma_addr_t dma_ptr, u_int size );
+extern dma_addr_t sa1100_get_dma_pos(dma_regs_t *regs);
+extern void sa1100_reset_dma(dma_regs_t *regs);
+
+/**
+ *      sa1100_stop_dma - stop DMA in progress
+ *      @regs: identifier for the channel to use
+ *
+ *      This stops DMA without clearing buffer pointers. Unlike
+ *      sa1100_clear_dma() this allows subsequent use of sa1100_resume_dma()
+ *      or sa1100_get_dma_pos().
+ *
+ *      The @regs identifier is provided by a successful call to
+ *      sa1100_request_dma().
+ **/
+
+#define sa1100_stop_dma(regs)   ((regs)->ClrDCSR = DCSR_IE|DCSR_RUN)
+
+/**
+ *      sa1100_resume_dma - resume DMA on a stopped channel
+ *      @regs: identifier for the channel to use
+ *
+ *      This resumes DMA on a channel previously stopped with
+ *      sa1100_stop_dma().
+ *
+ *      The @regs identifier is provided by a successful call to
+ *      sa1100_request_dma().
+ **/
+
+#define sa1100_resume_dma(regs) ((regs)->SetDCSR = DCSR_IE|DCSR_RUN)
+
+/**
+ *      sa1100_clear_dma - clear DMA pointers
+ *      @regs: identifier for the channel to use
+ *
+ *      This clear any DMA state so the DMA engine is ready to restart
+ *      with new buffers through sa1100_start_dma(). Any buffers in flight
+ *      are discarded.
+ *
+ *      The @regs identifier is provided by a successful call to
+ *      sa1100_request_dma().
+ **/
+
+#define sa1100_clear_dma(regs)  ((regs)->ClrDCSR = DCSR_IE|DCSR_RUN|DCSR_STRTA|DCSR_STRTB)
+
+#endif /* _ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-sa1100/include/mach/entry-macro.S b/arch/arm/mach-sa1100/include/mach/entry-macro.S
new file mode 100644
index 000000000000..6aa13c46c5d3
--- /dev/null
+++ b/arch/arm/mach-sa1100/include/mach/entry-macro.S
@@ -0,0 +1,47 @@
+/*
+ * arch/arm/mach-sa1100/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for SA1100-based platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_preamble, base, tmp
+                mov     \base, #0xfa000000              @ ICIP = 0xfa050000
+                add     \base, \base, #0x00050000
+                .endm
+
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                ldr     \irqstat, [\base]               @ get irqs
+                ldr     \irqnr, [\base, #4]             @ ICMR = 0xfa050004
+                ands    \irqstat, \irqstat, \irqnr
+                mov     \irqnr, #0
+                beq     1001f
+                tst     \irqstat, #0xff
+                moveq   \irqstat, \irqstat, lsr #8
+                addeq   \irqnr, \irqnr, #8
+                tsteq   \irqstat, #0xff
+                moveq   \irqstat, \irqstat, lsr #8
+                addeq   \irqnr, \irqnr, #8
+                tsteq   \irqstat, #0xff
+                moveq   \irqstat, \irqstat, lsr #8
+                addeq   \irqnr, \irqnr, #8
+                tst     \irqstat, #0x0f
+                moveq   \irqstat, \irqstat, lsr #4
+                addeq   \irqnr, \irqnr, #4
+                tst     \irqstat, #0x03
+                moveq   \irqstat, \irqstat, lsr #2
+                addeq   \irqnr, \irqnr, #2
+                tst     \irqstat, #0x01
+                addeqs  \irqnr, \irqnr, #1
+1001:
+                .endm
+
diff --git a/arch/arm/mach-sa1100/include/mach/gpio.h b/arch/arm/mach-sa1100/include/mach/gpio.h
new file mode 100644
index 000000000000..582a0c92da53
--- /dev/null
+++ b/arch/arm/mach-sa1100/include/mach/gpio.h
@@ -0,0 +1,68 @@
+/*
+ * arch/arm/mach-sa1100/include/mach/gpio.h
+ *
+ * SA1100 GPIO wrappers for arch-neutral GPIO calls
+ *
+ * Written by Philipp Zabel <philipp.zabel@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARCH_SA1100_GPIO_H
+#define __ASM_ARCH_SA1100_GPIO_H
+
+#include <mach/hardware.h>
+#include <asm/irq.h>
+#include <asm-generic/gpio.h>
+
+static inline int gpio_get_value(unsigned gpio)
+{
+        if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX))
+                return GPLR & GPIO_GPIO(gpio);
+        else
+                return __gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+        if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX))
+                if (value)
+                        GPSR = GPIO_GPIO(gpio);
+                else
+                        GPCR = GPIO_GPIO(gpio);
+        else
+                __gpio_set_value(gpio, value);
+}
+
+#define gpio_cansleep   __gpio_cansleep
+
+static inline unsigned gpio_to_irq(unsigned gpio)
+{
+        if (gpio < 11)
+                return IRQ_GPIO0 + gpio;
+        else
+                return IRQ_GPIO11 - 11 + gpio;
+}
+
+static inline unsigned irq_to_gpio(unsigned irq)
+{
+        if (irq < IRQ_GPIO11_27)
+                return irq - IRQ_GPIO0;
+        else
+                return irq - IRQ_GPIO11 + 11;
+}
+
+#endif
diff --git a/include/asm-arm/arch-sa1100/h3600.h b/arch/arm/mach-sa1100/include/mach/h3600.h
index 3ca0ecf095e6..3ca0ecf095e6 100644
--- a/include/asm-arm/arch-sa1100/h3600.h
+++ b/arch/arm/mach-sa1100/include/mach/h3600.h
diff --git a/include/asm-arm/arch-sa1100/h3600_gpio.h b/arch/arm/mach-sa1100/include/mach/h3600_gpio.h
index 62b0b7879685..62b0b7879685 100644
--- a/include/asm-arm/arch-sa1100/h3600_gpio.h
+++ b/arch/arm/mach-sa1100/include/mach/h3600_gpio.h
diff --git a/arch/arm/mach-sa1100/include/mach/hardware.h b/arch/arm/mach-sa1100/include/mach/hardware.h
new file mode 100644
index 000000000000..5976435f42c2
--- /dev/null
+++ b/arch/arm/mach-sa1100/include/mach/hardware.h
@@ -0,0 +1,57 @@
+/*
+ * arch/arm/mach-sa1100/include/mach/hardware.h
+ *
+ * Copyright (C) 1998 Nicolas Pitre <nico@cam.org>
+ *
+ * This file contains the hardware definitions for SA1100 architecture
+ *
+ * 2000/05/23 John Dorsey <john+@cs.cmu.edu>
+ *      Definitions for SA1111 added.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+
+#define UNCACHEABLE_ADDR        0xfa050000
+
+
+/*
+ * SA1100 internal I/O mappings
+ *
+ * We have the following mapping:
+ *      phys            virt
+ *      80000000        f8000000
+ *      90000000        fa000000
+ *      a0000000        fc000000
+ *      b0000000        fe000000
+ */
+
+#define VIO_BASE        0xf8000000      /* virtual start of IO space */
+#define VIO_SHIFT       3               /* x = IO space shrink power */
+#define PIO_START       0x80000000      /* physical start of IO space */
+
+#define io_p2v( x )             \
+   ( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE )
+#define io_v2p( x )             \
+   ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START )
+
+#ifndef __ASSEMBLY__
+
+# define __REG(x)       (*((volatile unsigned long *)io_p2v(x)))
+# define __PREG(x)      (io_v2p((unsigned long)&(x)))
+
+#else
+
+# define __REG(x)       io_p2v(x)
+# define __PREG(x)      io_v2p(x)
+
+#endif
+
+#include "SA-1100.h"
+
+#ifdef CONFIG_SA1101
+#include "SA-1101.h"
+#endif
+
+#endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-sa1100/include/mach/ide.h b/arch/arm/mach-sa1100/include/mach/ide.h
new file mode 100644
index 000000000000..4c99c8f5e617
--- /dev/null
+++ b/arch/arm/mach-sa1100/include/mach/ide.h
@@ -0,0 +1,75 @@
+/*
+ * arch/arm/mach-sa1100/include/mach/ide.h
+ *
+ * Copyright (c) 1998 Hugo Fiennes & Nicolas Pitre
+ *
+ * 18-aug-2000: Cleanup by Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
+ *              Get rid of the special ide_init_hwif_ports() functions
+ *              and make a generalised function that can be used by all
+ *              architectures.
+ */
+
+#include <asm/irq.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+
+#error "This code is broken and needs update to match with current ide support"
+
+
+/*
+ * Set up a hw structure for a specified data port, control port and IRQ.
+ * This should follow whatever the default interface uses.
+ */
+static inline void ide_init_hwif_ports(hw_regs_t *hw, unsigned long data_port,
+                                       unsigned long ctrl_port, int *irq)
+{
+        unsigned long reg = data_port;
+        int i;
+        int regincr = 1;
+
+        /* The Empeg board has the first two address lines unused */
+        if (machine_is_empeg())
+                regincr = 1 << 2;
+
+        /* The LART doesn't use A0 for IDE */
+        if (machine_is_lart())
+                regincr = 1 << 1;
+
+        memset(hw, 0, sizeof(*hw));
+
+        for (i = 0; i <= 7; i++) {
+                hw->io_ports_array[i] = reg;
+                reg += regincr;
+        }
+
+        hw->io_ports.ctl_addr = ctrl_port;
+
+        if (irq)
+                *irq = 0;
+}
+
+/*
+ * This registers the standard ports for this architecture with the IDE
+ * driver.
+ */
+static __inline__ void
+ide_init_default_hwifs(void)
+{
+    if (machine_is_lart()) {
+#ifdef CONFIG_SA1100_LART
+        hw_regs_t hw;
+
+        /* Enable GPIO as interrupt line */
+        GPDR &= ~LART_GPIO_IDE;
+        set_irq_type(LART_IRQ_IDE, IRQ_TYPE_EDGE_RISING);
+
+        /* set PCMCIA interface timing */
+        MECR = 0x00060006;
+
+        /* init the interface */
+        ide_init_hwif_ports(&hw, PCMCIA_IO_0_BASE + 0x0000, PCMCIA_IO_0_BASE + 0x1000, NULL);
+        hw.irq = LART_IRQ_IDE;
+        ide_register_hw(&hw);
+#endif
+    }
+}
diff --git a/arch/arm/mach-sa1100/include/mach/io.h b/arch/arm/mach-sa1100/include/mach/io.h
new file mode 100644
index 000000000000..0c070a6149bc
--- /dev/null
+++ b/arch/arm/mach-sa1100/include/mach/io.h
@@ -0,0 +1,26 @@
+/*
+ * arch/arm/mach-sa1100/include/mach/io.h
+ *
+ * Copyright (C) 1997-1999 Russell King
+ *
+ * Modifications:
+ *  06-12-1997  RMK     Created.
+ *  07-04-1999  RMK     Major cleanup
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * We don't actually have real ISA nor PCI buses, but there is so many 
+ * drivers out there that might just work if we fake them...
+ */
+static inline void __iomem *__io(unsigned long addr)
+{
+        return (void __iomem *)addr;
+}
+#define __io(a)                 __io(a)
+#define __mem_pci(a)            (a)
+
+#endif
diff --git a/arch/arm/mach-sa1100/include/mach/irqs.h b/arch/arm/mach-sa1100/include/mach/irqs.h
new file mode 100644
index 000000000000..0cb36609b3ac
--- /dev/null
+++ b/arch/arm/mach-sa1100/include/mach/irqs.h
@@ -0,0 +1,197 @@
+/*
+ * arch/arm/mach-sa1100/include/mach/irqs.h
+ *
+ * Copyright (C) 1996 Russell King
+ * Copyright (C) 1998 Deborah Wallach (updates for SA1100/Brutus).
+ * Copyright (C) 1999 Nicolas Pitre (full GPIO irq isolation)
+ *
+ * 2001/11/14   RMK     Cleaned up and standardised a lot of the IRQs.
+ */
+
+#define IRQ_GPIO0               0
+#define IRQ_GPIO1               1
+#define IRQ_GPIO2               2
+#define IRQ_GPIO3               3
+#define IRQ_GPIO4               4
+#define IRQ_GPIO5               5
+#define IRQ_GPIO6               6
+#define IRQ_GPIO7               7
+#define IRQ_GPIO8               8
+#define IRQ_GPIO9               9
+#define IRQ_GPIO10              10
+#define IRQ_GPIO11_27           11
+#define IRQ_LCD                 12      /* LCD controller           */
+#define IRQ_Ser0UDC             13      /* Ser. port 0 UDC          */
+#define IRQ_Ser1SDLC            14      /* Ser. port 1 SDLC         */
+#define IRQ_Ser1UART            15      /* Ser. port 1 UART         */
+#define IRQ_Ser2ICP             16      /* Ser. port 2 ICP          */
+#define IRQ_Ser3UART            17      /* Ser. port 3 UART         */
+#define IRQ_Ser4MCP             18      /* Ser. port 4 MCP          */
+#define IRQ_Ser4SSP             19      /* Ser. port 4 SSP          */
+#define IRQ_DMA0                20      /* DMA controller channel 0 */
+#define IRQ_DMA1                21      /* DMA controller channel 1 */
+#define IRQ_DMA2                22      /* DMA controller channel 2 */
+#define IRQ_DMA3                23      /* DMA controller channel 3 */
+#define IRQ_DMA4                24      /* DMA controller channel 4 */
+#define IRQ_DMA5                25      /* DMA controller channel 5 */
+#define IRQ_OST0                26      /* OS Timer match 0         */
+#define IRQ_OST1                27      /* OS Timer match 1         */
+#define IRQ_OST2                28      /* OS Timer match 2         */
+#define IRQ_OST3                29      /* OS Timer match 3         */
+#define IRQ_RTC1Hz              30      /* RTC 1 Hz clock           */
+#define IRQ_RTCAlrm             31      /* RTC Alarm                */
+
+#define IRQ_GPIO11              32
+#define IRQ_GPIO12              33
+#define IRQ_GPIO13              34
+#define IRQ_GPIO14              35
+#define IRQ_GPIO15              36
+#define IRQ_GPIO16              37
+#define IRQ_GPIO17              38
+#define IRQ_GPIO18              39
+#define IRQ_GPIO19              40
+#define IRQ_GPIO20              41
+#define IRQ_GPIO21              42
+#define IRQ_GPIO22              43
+#define IRQ_GPIO23              44
+#define IRQ_GPIO24              45
+#define IRQ_GPIO25              46
+#define IRQ_GPIO26              47
+#define IRQ_GPIO27              48
+
+/*
+ * The next 16 interrupts are for board specific purposes.  Since
+ * the kernel can only run on one machine at a time, we can re-use
+ * these.  If you need more, increase IRQ_BOARD_END, but keep it
+ * within sensible limits.  IRQs 49 to 64 are available.
+ */
+#define IRQ_BOARD_START         49
+#define IRQ_BOARD_END           65
+
+#define IRQ_SA1111_START        (IRQ_BOARD_END)
+#define IRQ_GPAIN0              (IRQ_BOARD_END + 0)
+#define IRQ_GPAIN1              (IRQ_BOARD_END + 1)
+#define IRQ_GPAIN2              (IRQ_BOARD_END + 2)
+#define IRQ_GPAIN3              (IRQ_BOARD_END + 3)
+#define IRQ_GPBIN0              (IRQ_BOARD_END + 4)
+#define IRQ_GPBIN1              (IRQ_BOARD_END + 5)
+#define IRQ_GPBIN2              (IRQ_BOARD_END + 6)
+#define IRQ_GPBIN3              (IRQ_BOARD_END + 7)
+#define IRQ_GPBIN4              (IRQ_BOARD_END + 8)
+#define IRQ_GPBIN5              (IRQ_BOARD_END + 9)
+#define IRQ_GPCIN0              (IRQ_BOARD_END + 10)
+#define IRQ_GPCIN1              (IRQ_BOARD_END + 11)
+#define IRQ_GPCIN2              (IRQ_BOARD_END + 12)
+#define IRQ_GPCIN3              (IRQ_BOARD_END + 13)
+#define IRQ_GPCIN4              (IRQ_BOARD_END + 14)
+#define IRQ_GPCIN5              (IRQ_BOARD_END + 15)
+#define IRQ_GPCIN6              (IRQ_BOARD_END + 16)
+#define IRQ_GPCIN7              (IRQ_BOARD_END + 17)
+#define IRQ_MSTXINT             (IRQ_BOARD_END + 18)
+#define IRQ_MSRXINT             (IRQ_BOARD_END + 19)
+#define IRQ_MSSTOPERRINT        (IRQ_BOARD_END + 20)
+#define IRQ_TPTXINT             (IRQ_BOARD_END + 21)
+#define IRQ_TPRXINT             (IRQ_BOARD_END + 22)
+#define IRQ_TPSTOPERRINT        (IRQ_BOARD_END + 23)
+#define SSPXMTINT               (IRQ_BOARD_END + 24)
+#define SSPRCVINT               (IRQ_BOARD_END + 25)
+#define SSPROR                  (IRQ_BOARD_END + 26)
+#define AUDXMTDMADONEA          (IRQ_BOARD_END + 32)
+#define AUDRCVDMADONEA          (IRQ_BOARD_END + 33)
+#define AUDXMTDMADONEB          (IRQ_BOARD_END + 34)
+#define AUDRCVDMADONEB          (IRQ_BOARD_END + 35)
+#define AUDTFSR                 (IRQ_BOARD_END + 36)
+#define AUDRFSR                 (IRQ_BOARD_END + 37)
+#define AUDTUR                  (IRQ_BOARD_END + 38)
+#define AUDROR                  (IRQ_BOARD_END + 39)
+#define AUDDTS                  (IRQ_BOARD_END + 40)
+#define AUDRDD                  (IRQ_BOARD_END + 41)
+#define AUDSTO                  (IRQ_BOARD_END + 42)
+#define IRQ_USBPWR              (IRQ_BOARD_END + 43)
+#define IRQ_HCIM                (IRQ_BOARD_END + 44)
+#define IRQ_HCIBUFFACC          (IRQ_BOARD_END + 45)
+#define IRQ_HCIRMTWKP           (IRQ_BOARD_END + 46)
+#define IRQ_NHCIMFCIR           (IRQ_BOARD_END + 47)
+#define IRQ_USB_PORT_RESUME     (IRQ_BOARD_END + 48)
+#define IRQ_S0_READY_NINT       (IRQ_BOARD_END + 49)
+#define IRQ_S1_READY_NINT       (IRQ_BOARD_END + 50)
+#define IRQ_S0_CD_VALID         (IRQ_BOARD_END + 51)
+#define IRQ_S1_CD_VALID         (IRQ_BOARD_END + 52)
+#define IRQ_S0_BVD1_STSCHG      (IRQ_BOARD_END + 53)
+#define IRQ_S1_BVD1_STSCHG      (IRQ_BOARD_END + 54)
+
+#define IRQ_LOCOMO_START        (IRQ_BOARD_END)
+#define IRQ_LOCOMO_KEY          (IRQ_BOARD_END + 0)
+#define IRQ_LOCOMO_GPIO0        (IRQ_BOARD_END + 1)
+#define IRQ_LOCOMO_GPIO1        (IRQ_BOARD_END + 2)
+#define IRQ_LOCOMO_GPIO2        (IRQ_BOARD_END + 3)
+#define IRQ_LOCOMO_GPIO3        (IRQ_BOARD_END + 4)
+#define IRQ_LOCOMO_GPIO4        (IRQ_BOARD_END + 5)
+#define IRQ_LOCOMO_GPIO5        (IRQ_BOARD_END + 6)
+#define IRQ_LOCOMO_GPIO6        (IRQ_BOARD_END + 7)
+#define IRQ_LOCOMO_GPIO7        (IRQ_BOARD_END + 8)
+#define IRQ_LOCOMO_GPIO8        (IRQ_BOARD_END + 9)
+#define IRQ_LOCOMO_GPIO9        (IRQ_BOARD_END + 10)
+#define IRQ_LOCOMO_GPIO10       (IRQ_BOARD_END + 11)
+#define IRQ_LOCOMO_GPIO11       (IRQ_BOARD_END + 12)
+#define IRQ_LOCOMO_GPIO12       (IRQ_BOARD_END + 13)
+#define IRQ_LOCOMO_GPIO13       (IRQ_BOARD_END + 14)
+#define IRQ_LOCOMO_GPIO14       (IRQ_BOARD_END + 15)
+#define IRQ_LOCOMO_GPIO15       (IRQ_BOARD_END + 16)
+#define IRQ_LOCOMO_LT           (IRQ_BOARD_END + 17)
+#define IRQ_LOCOMO_SPI_RFR      (IRQ_BOARD_END + 18)
+#define IRQ_LOCOMO_SPI_RFW      (IRQ_BOARD_END + 19)
+#define IRQ_LOCOMO_SPI_REND     (IRQ_BOARD_END + 20)
+#define IRQ_LOCOMO_SPI_TEND     (IRQ_BOARD_END + 21)
+
+/*
+ * Figure out the MAX IRQ number.
+ *
+ * If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1.
+ * If we have an LoCoMo, the max IRQ is IRQ_LOCOMO_SPI_TEND+1
+ * Otherwise, we have the standard IRQs only.
+ */
+#ifdef CONFIG_SA1111
+#define NR_IRQS                 (IRQ_S1_BVD1_STSCHG + 1)
+#elif defined(CONFIG_SA1100_H3800)
+#define NR_IRQS                 (IRQ_BOARD_END)
+#elif defined(CONFIG_SHARP_LOCOMO)
+#define NR_IRQS                 (IRQ_LOCOMO_SPI_TEND + 1)
+#else
+#define NR_IRQS                 (IRQ_BOARD_START)
+#endif
+
+/*
+ * Board specific IRQs.  Define them here.
+ * Do not surround them with ifdefs.
+ */
+#define IRQ_NEPONSET_SMC9196    (IRQ_BOARD_START + 0)
+#define IRQ_NEPONSET_USAR       (IRQ_BOARD_START + 1)
+#define IRQ_NEPONSET_SA1111     (IRQ_BOARD_START + 2)
+
+/* LoCoMo Interrupts (CONFIG_SHARP_LOCOMO) */
+#define IRQ_LOCOMO_KEY_BASE     (IRQ_BOARD_START + 0)
+#define IRQ_LOCOMO_GPIO_BASE    (IRQ_BOARD_START + 1)
+#define IRQ_LOCOMO_LT_BASE      (IRQ_BOARD_START + 2)
+#define IRQ_LOCOMO_SPI_BASE     (IRQ_BOARD_START + 3)
+
+/* H3800-specific IRQs (CONFIG_SA1100_H3800) */
+#define H3800_KPIO_IRQ_START    (IRQ_BOARD_START)
+#define IRQ_H3800_KEY           (IRQ_BOARD_START + 0)
+#define IRQ_H3800_SPI           (IRQ_BOARD_START + 1)
+#define IRQ_H3800_OWM           (IRQ_BOARD_START + 2)
+#define IRQ_H3800_ADC           (IRQ_BOARD_START + 3)
+#define IRQ_H3800_UART_0        (IRQ_BOARD_START + 4)
+#define IRQ_H3800_UART_1        (IRQ_BOARD_START + 5)
+#define IRQ_H3800_TIMER_0       (IRQ_BOARD_START + 6)
+#define IRQ_H3800_TIMER_1       (IRQ_BOARD_START + 7)
+#define IRQ_H3800_TIMER_2       (IRQ_BOARD_START + 8)
+#define H3800_KPIO_IRQ_COUNT    9
+
+#define H3800_GPIO_IRQ_START    (IRQ_BOARD_START + 9)
+#define IRQ_H3800_PEN           (IRQ_BOARD_START + 9)
+#define IRQ_H3800_SD_DETECT     (IRQ_BOARD_START + 10)
+#define IRQ_H3800_EAR_IN        (IRQ_BOARD_START + 11)
+#define IRQ_H3800_USB_DETECT    (IRQ_BOARD_START + 12)
+#define IRQ_H3800_SD_CON_SLT    (IRQ_BOARD_START + 13)
+#define H3800_GPIO_IRQ_COUNT    5
diff --git a/arch/arm/mach-sa1100/include/mach/jornada720.h b/arch/arm/mach-sa1100/include/mach/jornada720.h
new file mode 100644
index 000000000000..bc120850d313
--- /dev/null
+++ b/arch/arm/mach-sa1100/include/mach/jornada720.h
@@ -0,0 +1,27 @@
+/*
+ * arch/arm/mach-sa1100/include/mach/jornada720.h
+ *
+ * This file contains SSP/MCU communication definitions for HP Jornada 710/720/728
+ *
+ * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
+ *  Copyright (C) 2000 John Ankcorn <jca@lcs.mit.edu>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+ /* HP Jornada 7xx microprocessor commands */
+#define GETBATTERYDATA          0xc0
+#define GETSCANKEYCODE          0x90
+#define GETTOUCHSAMPLES         0xa0
+#define GETCONTRAST             0xD0
+#define SETCONTRAST             0xD1
+#define GETBRIGHTNESS           0xD2
+#define SETBRIGHTNESS           0xD3
+#define CONTRASTOFF             0xD8
+#define BRIGHTNESSOFF           0xD9
+#define PWMOFF                  0xDF
+#define TXDUMMY                 0x11
+#define ERRORCODE               0x00
diff --git a/include/asm-arm/arch-sa1100/lart.h b/arch/arm/mach-sa1100/include/mach/lart.h
index 8a5482d908db..8a5482d908db 100644
--- a/include/asm-arm/arch-sa1100/lart.h
+++ b/arch/arm/mach-sa1100/include/mach/lart.h
diff --git a/arch/arm/mach-sa1100/include/mach/mcp.h b/arch/arm/mach-sa1100/include/mach/mcp.h
new file mode 100644
index 000000000000..fb8b09a57ad7
--- /dev/null
+++ b/arch/arm/mach-sa1100/include/mach/mcp.h
@@ -0,0 +1,21 @@
+/*
+ *  arch/arm/mach-sa1100/include/mach/mcp.h
+ *
+ *  Copyright (C) 2005 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARM_ARCH_MCP_H
+#define __ASM_ARM_ARCH_MCP_H
+
+#include <linux/types.h>
+
+struct mcp_plat_data {
+        u32 mccr0;
+        u32 mccr1;
+        unsigned int sclk_rate;
+};
+
+#endif
diff --git a/arch/arm/mach-sa1100/include/mach/memory.h b/arch/arm/mach-sa1100/include/mach/memory.h
new file mode 100644
index 000000000000..29f639e2afc6
--- /dev/null
+++ b/arch/arm/mach-sa1100/include/mach/memory.h
@@ -0,0 +1,68 @@
+/*
+ * arch/arm/mach-sa1100/include/mach/memory.h
+ *
+ * Copyright (C) 1999-2000 Nicolas Pitre <nico@cam.org>
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#include <asm/sizes.h>
+
+/*
+ * Physical DRAM offset is 0xc0000000 on the SA1100
+ */
+#define PHYS_OFFSET     UL(0xc0000000)
+
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_SA1111
+void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes);
+
+#define arch_adjust_zones(node, size, holes) \
+        sa1111_adjust_zones(node, size, holes)
+
+#define ISA_DMA_THRESHOLD       (PHYS_OFFSET + SZ_1M - 1)
+
+#endif
+#endif
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ *
+ * On the SA1100, bus addresses are equivalent to physical addresses.
+ */
+#define __virt_to_bus(x)         __virt_to_phys(x)
+#define __bus_to_virt(x)         __phys_to_virt(x)
+
+/*
+ * Because of the wide memory address space between physical RAM banks on the 
+ * SA1100, it's much convenient to use Linux's NUMA support to implement our 
+ * memory map representation.  Assuming all memory nodes have equal access 
+ * characteristics, we then have generic discontiguous memory support.
+ *
+ * Of course, all this isn't mandatory for SA1100 implementations with only
+ * one used memory bank.  For those, simply undefine CONFIG_DISCONTIGMEM.
+ *
+ * The nodes are matched with the physical memory bank addresses which are 
+ * incidentally the same as virtual addresses.
+ * 
+ *      node 0:  0xc0000000 - 0xc7ffffff
+ *      node 1:  0xc8000000 - 0xcfffffff
+ *      node 2:  0xd0000000 - 0xd7ffffff
+ *      node 3:  0xd8000000 - 0xdfffffff
+ */
+#define NODE_MEM_SIZE_BITS      27
+
+/*
+ * Cache flushing area - SA1100 zero bank
+ */
+#define FLUSH_BASE_PHYS         0xe0000000
+#define FLUSH_BASE              0xf5000000
+#define FLUSH_BASE_MINICACHE    0xf5100000
+
+#endif
diff --git a/include/asm-arm/arch-sa1100/mtd-xip.h b/arch/arm/mach-sa1100/include/mach/mtd-xip.h
index 80cfdac2b944..80cfdac2b944 100644
--- a/include/asm-arm/arch-sa1100/mtd-xip.h
+++ b/arch/arm/mach-sa1100/include/mach/mtd-xip.h
diff --git a/arch/arm/mach-sa1100/include/mach/neponset.h b/arch/arm/mach-sa1100/include/mach/neponset.h
new file mode 100644
index 000000000000..d3f044f92c00
--- /dev/null
+++ b/arch/arm/mach-sa1100/include/mach/neponset.h
@@ -0,0 +1,74 @@
+/*
+ * arch/arm/mach-sa1100/include/mach/neponset.h
+ *
+ * Created 2000/06/05 by Nicolas Pitre <nico@cam.org>
+ *
+ * This file contains the hardware specific definitions for Assabet
+ * Only include this file from SA1100-specific files.
+ *
+ * 2000/05/23 John Dorsey <john+@cs.cmu.edu>
+ *      Definitions for Neponset added.
+ */
+#ifndef __ASM_ARCH_NEPONSET_H
+#define __ASM_ARCH_NEPONSET_H
+
+/*
+ * Neponset definitions: 
+ */
+
+#define NEPONSET_CPLD_BASE      (0x10000000)
+#define Nep_p2v( x )            ((x) - NEPONSET_CPLD_BASE + 0xf3000000)
+#define Nep_v2p( x )            ((x) - 0xf3000000 + NEPONSET_CPLD_BASE)
+
+#define _IRR                    0x10000024      /* Interrupt Reason Register */
+#define _AUD_CTL                0x100000c0      /* Audio controls (RW)       */
+#define _MDM_CTL_0              0x100000b0      /* Modem control 0 (RW)      */
+#define _MDM_CTL_1              0x100000b4      /* Modem control 1 (RW)      */
+#define _NCR_0                  0x100000a0      /* Control Register (RW)     */
+#define _KP_X_OUT               0x10000090      /* Keypad row write (RW)     */
+#define _KP_Y_IN                0x10000080      /* Keypad column read (RO)   */
+#define _SWPK                   0x10000020      /* Switch pack (RO)          */
+#define _WHOAMI                 0x10000000      /* System ID Register (RO)   */
+
+#define _LEDS                   0x10000010      /* LEDs [31:0] (WO)          */
+
+#define IRR                     (*((volatile u_char *) Nep_p2v(_IRR)))
+#define AUD_CTL                 (*((volatile u_char *) Nep_p2v(_AUD_CTL)))
+#define MDM_CTL_0               (*((volatile u_char *) Nep_p2v(_MDM_CTL_0)))
+#define MDM_CTL_1               (*((volatile u_char *) Nep_p2v(_MDM_CTL_1)))
+#define NCR_0                   (*((volatile u_char *) Nep_p2v(_NCR_0)))
+#define KP_X_OUT                (*((volatile u_char *) Nep_p2v(_KP_X_OUT)))
+#define KP_Y_IN                 (*((volatile u_char *) Nep_p2v(_KP_Y_IN)))
+#define SWPK                    (*((volatile u_char *) Nep_p2v(_SWPK)))
+#define WHOAMI                  (*((volatile u_char *) Nep_p2v(_WHOAMI)))
+
+#define LEDS                    (*((volatile Word   *) Nep_p2v(_LEDS)))
+
+#define IRR_ETHERNET            (1<<0)
+#define IRR_USAR                (1<<1)
+#define IRR_SA1111              (1<<2)
+
+#define AUD_SEL_1341            (1<<0)
+#define AUD_MUTE_1341           (1<<1)
+
+#define MDM_CTL0_RTS1           (1 << 0)
+#define MDM_CTL0_DTR1           (1 << 1)
+#define MDM_CTL0_RTS2           (1 << 2)
+#define MDM_CTL0_DTR2           (1 << 3)
+
+#define MDM_CTL1_CTS1           (1 << 0)
+#define MDM_CTL1_DSR1           (1 << 1)
+#define MDM_CTL1_DCD1           (1 << 2)
+#define MDM_CTL1_CTS2           (1 << 3)
+#define MDM_CTL1_DSR2           (1 << 4)
+#define MDM_CTL1_DCD2           (1 << 5)
+
+#define NCR_GP01_OFF            (1<<0)
+#define NCR_TP_PWR_EN           (1<<1)
+#define NCR_MS_PWR_EN           (1<<2)
+#define NCR_ENET_OSC_EN         (1<<3)
+#define NCR_SPI_KB_WK_UP        (1<<4)
+#define NCR_A0VPP               (1<<5)
+#define NCR_A1VPP               (1<<6)
+
+#endif
diff --git a/include/asm-arm/arch-sa1100/shannon.h b/arch/arm/mach-sa1100/include/mach/shannon.h
index ec27d6e12140..ec27d6e12140 100644
--- a/include/asm-arm/arch-sa1100/shannon.h
+++ b/arch/arm/mach-sa1100/include/mach/shannon.h
diff --git a/arch/arm/mach-sa1100/include/mach/simpad.h b/arch/arm/mach-sa1100/include/mach/simpad.h
new file mode 100644
index 000000000000..9296c4513ce1
--- /dev/null
+++ b/arch/arm/mach-sa1100/include/mach/simpad.h
@@ -0,0 +1,112 @@
+/*
+ * arch/arm/mach-sa1100/include/mach/simpad.h
+ *
+ * based of assabet.h same as HUW_Webpanel
+ *
+ * This file contains the hardware specific definitions for SIMpad
+ *
+ * 2001/05/14 Juergen Messerer <juergen.messerer@freesurf.ch>
+ */
+
+#ifndef __ASM_ARCH_SIMPAD_H
+#define __ASM_ARCH_SIMPAD_H
+
+
+#define GPIO_UART1_RTS  GPIO_GPIO14
+#define GPIO_UART1_DTR  GPIO_GPIO7
+#define GPIO_UART1_CTS  GPIO_GPIO8
+#define GPIO_UART1_DCD  GPIO_GPIO23
+#define GPIO_UART1_DSR  GPIO_GPIO6
+
+#define GPIO_UART3_RTS  GPIO_GPIO12
+#define GPIO_UART3_DTR  GPIO_GPIO16
+#define GPIO_UART3_CTS  GPIO_GPIO13
+#define GPIO_UART3_DCD  GPIO_GPIO18
+#define GPIO_UART3_DSR  GPIO_GPIO17
+
+#define GPIO_POWER_BUTTON       GPIO_GPIO0
+#define GPIO_UCB1300_IRQ        GPIO_GPIO22     /* UCB GPIO and touchscreen */
+
+#define IRQ_UART1_CTS   IRQ_GPIO15
+#define IRQ_UART1_DCD   GPIO_GPIO23
+#define IRQ_UART1_DSR   GPIO_GPIO6
+#define IRQ_UART3_CTS   GPIO_GPIO13
+#define IRQ_UART3_DCD   GPIO_GPIO18
+#define IRQ_UART3_DSR   GPIO_GPIO17
+
+#define IRQ_GPIO_UCB1300_IRQ IRQ_GPIO22
+#define IRQ_GPIO_POWER_BUTTON IRQ_GPIO0
+
+
+/*---  PCMCIA  ---*/
+#define GPIO_CF_CD              GPIO_GPIO24
+#define GPIO_CF_IRQ             GPIO_GPIO1
+#define IRQ_GPIO_CF_IRQ         IRQ_GPIO1
+#define IRQ_GPIO_CF_CD          IRQ_GPIO24
+
+/*--- SmartCard ---*/
+#define GPIO_SMART_CARD         GPIO_GPIO10
+#define IRQ_GPIO_SMARD_CARD     IRQ_GPIO10
+
+// CS3 Latch is write only, a shadow is necessary
+
+#define CS3BUSTYPE unsigned volatile long
+#define CS3_BASE        0xf1000000
+
+#define VCC_5V_EN       0x0001 // For 5V PCMCIA
+#define VCC_3V_EN       0x0002 // FOR 3.3V PCMCIA
+#define EN1             0x0004 // This is only for EPROM's
+#define EN0             0x0008 // Both should be enable for 3.3V or 5V
+#define DISPLAY_ON      0x0010
+#define PCMCIA_BUFF_DIS 0x0020
+#define MQ_RESET        0x0040
+#define PCMCIA_RESET    0x0080
+#define DECT_POWER_ON   0x0100
+#define IRDA_SD         0x0200 // Shutdown for powersave
+#define RS232_ON        0x0400
+#define SD_MEDIAQ       0x0800 // Shutdown for powersave
+#define LED2_ON         0x1000
+#define IRDA_MODE       0x2000 // Fast/Slow IrDA mode
+#define ENABLE_5V       0x4000 // Enable 5V circuit
+#define RESET_SIMCARD   0x8000
+
+#define RS232_ENABLE    0x0440
+#define PCMCIAMASK      0x402f
+
+
+struct simpad_battery {
+        unsigned char ac_status;        /* line connected yes/no */
+        unsigned char status;           /* battery loading yes/no */
+        unsigned char percentage;       /* percentage loaded */
+        unsigned short life;            /* life till empty */
+};
+
+/* These should match the apm_bios.h definitions */
+#define SIMPAD_AC_STATUS_AC_OFFLINE      0x00
+#define SIMPAD_AC_STATUS_AC_ONLINE       0x01
+#define SIMPAD_AC_STATUS_AC_BACKUP       0x02   /* What does this mean? */
+#define SIMPAD_AC_STATUS_AC_UNKNOWN      0xff
+
+/* These bitfields are rarely "or'd" together */
+#define SIMPAD_BATT_STATUS_HIGH          0x01
+#define SIMPAD_BATT_STATUS_LOW           0x02
+#define SIMPAD_BATT_STATUS_CRITICAL      0x04
+#define SIMPAD_BATT_STATUS_CHARGING      0x08
+#define SIMPAD_BATT_STATUS_CHARGE_MAIN   0x10
+#define SIMPAD_BATT_STATUS_DEAD          0x20   /* Battery will not charge */
+#define SIMPAD_BATT_NOT_INSTALLED        0x20   /* For expansion pack batteries */
+#define SIMPAD_BATT_STATUS_FULL          0x40   /* Battery fully charged (and connected to AC) */
+#define SIMPAD_BATT_STATUS_NOBATT        0x80
+#define SIMPAD_BATT_STATUS_UNKNOWN       0xff
+
+extern int simpad_get_battery(struct simpad_battery* );
+
+#endif // __ASM_ARCH_SIMPAD_H
+
+
+
+
+
+
+
+
diff --git a/arch/arm/mach-sa1100/include/mach/system.h b/arch/arm/mach-sa1100/include/mach/system.h
new file mode 100644
index 000000000000..63755ca5b1b4
--- /dev/null
+++ b/arch/arm/mach-sa1100/include/mach/system.h
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/mach-sa1100/include/mach/system.h
+ *
+ * Copyright (c) 1999 Nicolas Pitre <nico@cam.org>
+ */
+#include <mach/hardware.h>
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        if (mode == 's') {
+                /* Jump into ROM at address 0 */
+                cpu_reset(0);
+        } else {
+                /* Use on-chip reset capability */
+                RSRR = RSRR_SWR;
+        }
+}
diff --git a/arch/arm/mach-sa1100/include/mach/timex.h b/arch/arm/mach-sa1100/include/mach/timex.h
new file mode 100644
index 000000000000..7a5d017b58b3
--- /dev/null
+++ b/arch/arm/mach-sa1100/include/mach/timex.h
@@ -0,0 +1,12 @@
+/*
+ * arch/arm/mach-sa1100/include/mach/timex.h
+ *
+ * SA1100 architecture timex specifications
+ *
+ * Copyright (C) 1998 
+ */
+
+/*
+ * SA1100 timer
+ */
+#define CLOCK_TICK_RATE         3686400
diff --git a/arch/arm/mach-sa1100/include/mach/uncompress.h b/arch/arm/mach-sa1100/include/mach/uncompress.h
new file mode 100644
index 000000000000..714160b03d7a
--- /dev/null
+++ b/arch/arm/mach-sa1100/include/mach/uncompress.h
@@ -0,0 +1,50 @@
+/*
+ * arch/arm/mach-sa1100/include/mach/uncompress.h
+ *
+ * (C) 1999 Nicolas Pitre <nico@cam.org>
+ *
+ * Reorganised to be machine independent.
+ */
+
+#include "hardware.h"
+
+/*
+ * The following code assumes the serial port has already been
+ * initialized by the bootloader.  We search for the first enabled
+ * port in the most probable order.  If you didn't setup a port in
+ * your bootloader then nothing will appear (which might be desired).
+ */
+
+#define UART(x)         (*(volatile unsigned long *)(serial_port + (x)))
+
+static void putc(int c)
+{
+        unsigned long serial_port;
+
+        do {
+                serial_port = _Ser3UTCR0;
+                if (UART(UTCR3) & UTCR3_TXE) break;
+                serial_port = _Ser1UTCR0;
+                if (UART(UTCR3) & UTCR3_TXE) break;
+                serial_port = _Ser2UTCR0;
+                if (UART(UTCR3) & UTCR3_TXE) break;
+                return;
+        } while (0);
+
+        /* wait for space in the UART's transmitter */
+        while (!(UART(UTSR1) & UTSR1_TNF))
+                barrier();
+
+        /* send the character out. */
+        UART(UTDR) = c;
+}
+
+static inline void flush(void)
+{
+}
+
+/*
+ * Nothing to do for these
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-sa1100/include/mach/vmalloc.h b/arch/arm/mach-sa1100/include/mach/vmalloc.h
new file mode 100644
index 000000000000..ec8fdc5a3606
--- /dev/null
+++ b/arch/arm/mach-sa1100/include/mach/vmalloc.h
@@ -0,0 +1,4 @@
+/*
+ * arch/arm/mach-sa1100/include/mach/vmalloc.h
+ */
+#define VMALLOC_END       (0xe8000000)
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index 280e111ba069..86369a8f0cea 100644
--- a/arch/arm/mach-sa1100/irq.c
+++ b/arch/arm/mach-sa1100/irq.c
@@ -16,7 +16,7 @@
 #include <linux/ioport.h>
 #include <linux/sysdev.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach/irq.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-sa1100/jornada720.c b/arch/arm/mach-sa1100/jornada720.c
index 2fefd195375e..81848aa96424 100644
--- a/arch/arm/mach-sa1100/jornada720.c
+++ b/arch/arm/mach-sa1100/jornada720.c
@@ -23,7 +23,7 @@
 #include <linux/mtd/partitions.h>
 #include <video/s1d13xxxfb.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/hardware/sa1111.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-sa1100/jornada720_ssp.c b/arch/arm/mach-sa1100/jornada720_ssp.c
index e319c361fc6c..06ea7abd9170 100644
--- a/arch/arm/mach-sa1100/jornada720_ssp.c
+++ b/arch/arm/mach-sa1100/jornada720_ssp.c
@@ -20,9 +20,9 @@
 #include <linux/sched.h>
 #include <linux/slab.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/hardware/ssp.h>
-#include <asm/arch/jornada720.h>
+#include <mach/jornada720.h>
 
 static DEFINE_SPINLOCK(jornada_ssp_lock);
 static unsigned long jornada_ssp_flags;
diff --git a/arch/arm/mach-sa1100/lart.c b/arch/arm/mach-sa1100/lart.c
index 7b991217a7f7..0cd52692d2f7 100644
--- a/arch/arm/mach-sa1100/lart.c
+++ b/arch/arm/mach-sa1100/lart.c
@@ -6,14 +6,14 @@
 #include <linux/kernel.h>
 #include <linux/tty.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/serial_sa1100.h>
-#include <asm/arch/mcp.h>
+#include <mach/mcp.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-sa1100/leds-assabet.c b/arch/arm/mach-sa1100/leds-assabet.c
index 0af944ea1b64..64e9b4b11b54 100644
--- a/arch/arm/mach-sa1100/leds-assabet.c
+++ b/arch/arm/mach-sa1100/leds-assabet.c
@@ -11,10 +11,10 @@
  */
 #include <linux/init.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/system.h>
-#include <asm/arch/assabet.h>
+#include <mach/assabet.h>
 
 #include "leds.h"
 
diff --git a/arch/arm/mach-sa1100/leds-badge4.c b/arch/arm/mach-sa1100/leds-badge4.c
index 9aead5f0a506..cf1e38458b81 100644
--- a/arch/arm/mach-sa1100/leds-badge4.c
+++ b/arch/arm/mach-sa1100/leds-badge4.c
@@ -12,7 +12,7 @@
 
 #include <linux/init.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/system.h>
 
diff --git a/arch/arm/mach-sa1100/leds-cerf.c b/arch/arm/mach-sa1100/leds-cerf.c
index 0c61ce5fddd0..259b48e0be89 100644
--- a/arch/arm/mach-sa1100/leds-cerf.c
+++ b/arch/arm/mach-sa1100/leds-cerf.c
@@ -5,7 +5,7 @@
  */
 #include <linux/init.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/system.h>
 
diff --git a/arch/arm/mach-sa1100/leds-hackkit.c b/arch/arm/mach-sa1100/leds-hackkit.c
index afa82f400480..2bce137462e4 100644
--- a/arch/arm/mach-sa1100/leds-hackkit.c
+++ b/arch/arm/mach-sa1100/leds-hackkit.c
@@ -11,7 +11,7 @@
  */
 #include <linux/init.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/system.h>
 
diff --git a/arch/arm/mach-sa1100/leds-lart.c b/arch/arm/mach-sa1100/leds-lart.c
index 066c7dc2f3f1..0505a1fdcdb2 100644
--- a/arch/arm/mach-sa1100/leds-lart.c
+++ b/arch/arm/mach-sa1100/leds-lart.c
@@ -11,7 +11,7 @@
  */
 #include <linux/init.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/system.h>
 
diff --git a/arch/arm/mach-sa1100/leds-simpad.c b/arch/arm/mach-sa1100/leds-simpad.c
index 1a3564b97e4a..d50f4eeaa12e 100644
--- a/arch/arm/mach-sa1100/leds-simpad.c
+++ b/arch/arm/mach-sa1100/leds-simpad.c
@@ -5,10 +5,10 @@
  */
 #include <linux/init.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/system.h>
-#include <asm/arch/simpad.h>
+#include <mach/simpad.h>
 
 #include "leds.h"
 
diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c
index dd7949f4f577..4856a6bd2482 100644
--- a/arch/arm/mach-sa1100/neponset.c
+++ b/arch/arm/mach-sa1100/neponset.c
@@ -10,14 +10,14 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/serial_sa1100.h>
-#include <asm/arch/assabet.h>
-#include <asm/arch/neponset.h>
+#include <mach/assabet.h>
+#include <mach/neponset.h>
 #include <asm/hardware/sa1111.h>
 #include <asm/sizes.h>
 
diff --git a/arch/arm/mach-sa1100/pleb.c b/arch/arm/mach-sa1100/pleb.c
index 84e956e23597..83be1c6c5f80 100644
--- a/arch/arm/mach-sa1100/pleb.c
+++ b/arch/arm/mach-sa1100/pleb.c
@@ -11,7 +11,7 @@
 
 #include <linux/mtd/partitions.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -20,7 +20,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 #include <asm/mach/serial_sa1100.h>
-#include <asm/arch/irqs.h>
+#include <mach/irqs.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-sa1100/pm.c b/arch/arm/mach-sa1100/pm.c
index 41ac21057b78..111cce67ad2f 100644
--- a/arch/arm/mach-sa1100/pm.c
+++ b/arch/arm/mach-sa1100/pm.c
@@ -27,7 +27,7 @@
 #include <linux/errno.h>
 #include <linux/time.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/memory.h>
 #include <asm/system.h>
 #include <asm/mach/time.h>
diff --git a/arch/arm/mach-sa1100/shannon.c b/arch/arm/mach-sa1100/shannon.c
index 60b4d847b489..9ccdd09cf69f 100644
--- a/arch/arm/mach-sa1100/shannon.c
+++ b/arch/arm/mach-sa1100/shannon.c
@@ -9,7 +9,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/setup.h>
 
@@ -17,8 +17,8 @@
 #include <asm/mach/flash.h>
 #include <asm/mach/map.h>
 #include <asm/mach/serial_sa1100.h>
-#include <asm/arch/mcp.h>
-#include <asm/arch/shannon.h>
+#include <mach/mcp.h>
+#include <mach/shannon.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c
index cc1df0703fca..8dd635317959 100644
--- a/arch/arm/mach-sa1100/simpad.c
+++ b/arch/arm/mach-sa1100/simpad.c
@@ -14,7 +14,7 @@
 #include <linux/mtd/partitions.h>
 
 #include <asm/irq.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/setup.h>
 
 #include <asm/mach-types.h>
@@ -22,8 +22,8 @@
 #include <asm/mach/flash.h>
 #include <asm/mach/map.h>
 #include <asm/mach/serial_sa1100.h>
-#include <asm/arch/mcp.h>
-#include <asm/arch/simpad.h>
+#include <mach/mcp.h>
+#include <mach/simpad.h>
 
 #include <linux/serial_core.h>
 #include <linux/ioport.h>
diff --git a/arch/arm/mach-sa1100/sleep.S b/arch/arm/mach-sa1100/sleep.S
index 29bdd3d1d1f7..171441f96710 100644
--- a/arch/arm/mach-sa1100/sleep.S
+++ b/arch/arm/mach-sa1100/sleep.S
@@ -18,7 +18,7 @@
 
 #include <linux/linkage.h>
 #include <asm/assembler.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 
 
diff --git a/arch/arm/mach-sa1100/ssp.c b/arch/arm/mach-sa1100/ssp.c
index db491659c8c1..641f361c56f4 100644
--- a/arch/arm/mach-sa1100/ssp.c
+++ b/arch/arm/mach-sa1100/ssp.c
@@ -20,7 +20,7 @@
 
 #include <asm/io.h>
 #include <asm/irq.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/hardware/ssp.h>
 
 #define TIMEOUT 100000
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c
index 428c2127834a..24c0a4bae850 100644
--- a/arch/arm/mach-sa1100/time.c
+++ b/arch/arm/mach-sa1100/time.c
@@ -16,7 +16,7 @@
 #include <linux/clockchips.h>
 
 #include <asm/mach/time.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 #define MIN_OSCR_DELTA 2
 
diff --git a/arch/arm/mach-shark/include/mach/debug-macro.S b/arch/arm/mach-shark/include/mach/debug-macro.S
new file mode 100644
index 000000000000..0836cb78b29a
--- /dev/null
+++ b/arch/arm/mach-shark/include/mach/debug-macro.S
@@ -0,0 +1,31 @@
+/* arch/arm/mach-shark/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+                .macro  addruart,rx
+                mov     \rx, #0xe0000000
+                orr     \rx, \rx, #0x000003f8
+                .endm
+
+                .macro  senduart,rd,rx
+                strb    \rd, [\rx]
+                .endm
+
+                .macro  busyuart,rd,rx
+                mov     \rd, #0
+1001:           add     \rd, \rd, #1
+                teq     \rd, #0x10000
+                bne     1001b
+                .endm
+
+                .macro  waituart,rd,rx
+                .endm
diff --git a/arch/arm/mach-shark/include/mach/dma.h b/arch/arm/mach-shark/include/mach/dma.h
new file mode 100644
index 000000000000..c0a29bd2a74f
--- /dev/null
+++ b/arch/arm/mach-shark/include/mach/dma.h
@@ -0,0 +1,18 @@
+/*
+ * arch/arm/mach-shark/include/mach/dma.h
+ *
+ * by Alexander Schulz
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+/* Use only the lowest 4MB, nothing else works.
+ * The rest is not DMAable. See dev /  .properties
+ * in OpenFirmware.
+ */
+#define MAX_DMA_ADDRESS         0xC0400000
+#define MAX_DMA_CHANNELS        8
+#define DMA_ISA_CASCADE         4
+
+#endif /* _ASM_ARCH_DMA_H */
+
diff --git a/arch/arm/mach-shark/include/mach/entry-macro.S b/arch/arm/mach-shark/include/mach/entry-macro.S
new file mode 100644
index 000000000000..e2853c0a3333
--- /dev/null
+++ b/arch/arm/mach-shark/include/mach/entry-macro.S
@@ -0,0 +1,41 @@
+/*
+ * arch/arm/mach-shark/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for Shark platform
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_preamble, base, tmp
+                .endm
+
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                mov     r4, #0xe0000000
+
+                mov     \irqstat, #0x0C
+                strb    \irqstat, [r4, #0x20]           @outb(0x0C, 0x20) /* Poll command */
+                ldrb    \irqnr, [r4, #0x20]             @irq = inb(0x20) & 7
+                and     \irqstat, \irqnr, #0x80
+                teq     \irqstat, #0
+                beq     43f
+                and     \irqnr, \irqnr, #7
+                teq     \irqnr, #2
+                bne     44f
+43:             mov     \irqstat, #0x0C
+                strb    \irqstat, [r4, #0xa0]           @outb(0x0C, 0xA0) /* Poll command */
+                ldrb    \irqnr, [r4, #0xa0]             @irq = (inb(0xA0) & 7) + 8
+                and     \irqstat, \irqnr, #0x80
+                teq     \irqstat, #0
+                beq     44f
+                and     \irqnr, \irqnr, #7
+                add     \irqnr, \irqnr, #8
+44:             teq     \irqstat, #0
+                .endm
+
diff --git a/arch/arm/mach-shark/include/mach/hardware.h b/arch/arm/mach-shark/include/mach/hardware.h
new file mode 100644
index 000000000000..cb0ee2943c1a
--- /dev/null
+++ b/arch/arm/mach-shark/include/mach/hardware.h
@@ -0,0 +1,51 @@
+/*
+ * arch/arm/mach-shark/include/mach/hardware.h
+ *
+ * by Alexander Schulz
+ *
+ * derived from:
+ * arch/arm/mach-ebsa110/include/mach/hardware.h
+ * Copyright (C) 1996-1999 Russell King.
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Mapping areas
+ */
+#define IO_BASE                 0xe0000000
+
+#else
+
+#define IO_BASE                 0
+
+#endif
+
+#define IO_SIZE                 0x08000000
+#define IO_START                0x40000000
+#define ROMCARD_SIZE            0x08000000
+#define ROMCARD_START           0x10000000
+
+#define PCIO_BASE               0xe0000000
+
+
+/* defines for the Framebuffer */
+#define FB_START                0x06000000
+#define FB_SIZE                 0x01000000
+
+#define UNCACHEABLE_ADDR        0xdf010000
+
+#define SEQUOIA_LED_GREEN       (1<<6)
+#define SEQUOIA_LED_AMBER       (1<<5)
+#define SEQUOIA_LED_BACK        (1<<7)
+
+#define pcibios_assign_all_busses()     1
+
+#define PCIBIOS_MIN_IO          0x6000
+#define PCIBIOS_MIN_MEM         0x50000000
+#define PCIMEM_BASE             0xe8000000
+
+#endif
+
diff --git a/arch/arm/mach-shark/include/mach/io.h b/arch/arm/mach-shark/include/mach/io.h
new file mode 100644
index 000000000000..92475922c068
--- /dev/null
+++ b/arch/arm/mach-shark/include/mach/io.h
@@ -0,0 +1,56 @@
+/*
+ * arch/arm/mach-shark/include/mach/io.h
+ *
+ * by Alexander Schulz
+ *
+ * derived from:
+ * arch/arm/mach-ebsa110/include/mach/io.h
+ * Copyright (C) 1997,1998 Russell King
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#include <mach/hardware.h>
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * We use two different types of addressing - PC style addresses, and ARM
+ * addresses.  PC style accesses the PC hardware with the normal PC IO
+ * addresses, eg 0x3f8 for serial#1.  ARM addresses are 0x80000000+
+ * and are translated to the start of IO.
+ */
+#define __PORT_PCIO(x)  (!((x) & 0x80000000))
+
+#define __io(a)                 ((void __iomem *)(PCIO_BASE + (a)))
+
+
+static inline unsigned int __ioaddr (unsigned int port)                 \
+{                                                                               \
+        if (__PORT_PCIO(port))                                                  \
+                return (unsigned int)(PCIO_BASE + (port));                      \
+        else                                                                    \
+                return (unsigned int)(IO_BASE + (port));                        \
+}
+
+#define __mem_pci(addr) (addr)
+
+/*
+ * Translated address IO functions
+ *
+ * IO address has already been translated to a virtual address
+ */
+#define outb_t(v,p)                                                             \
+        (*(volatile unsigned char *)(p) = (v))
+
+#define inb_t(p)                                                                \
+        (*(volatile unsigned char *)(p))
+
+#define outl_t(v,p)                                                             \
+        (*(volatile unsigned long *)(p) = (v))
+
+#define inl_t(p)                                                                \
+        (*(volatile unsigned long *)(p))
+
+#endif
diff --git a/arch/arm/mach-shark/include/mach/irqs.h b/arch/arm/mach-shark/include/mach/irqs.h
new file mode 100644
index 000000000000..0586acd7cdd5
--- /dev/null
+++ b/arch/arm/mach-shark/include/mach/irqs.h
@@ -0,0 +1,13 @@
+/*
+ * arch/arm/mach-shark/include/mach/irqs.h
+ *
+ * by Alexander Schulz
+ */
+
+#define NR_IRQS                 16
+
+#define IRQ_ISA_KEYBOARD         1
+#define RTC_IRQ                  8
+#define I8042_KBD_IRQ            1
+#define I8042_AUX_IRQ           12
+#define IRQ_HARDDISK            14
diff --git a/arch/arm/mach-shark/include/mach/memory.h b/arch/arm/mach-shark/include/mach/memory.h
new file mode 100644
index 000000000000..b7874ad9f9f6
--- /dev/null
+++ b/arch/arm/mach-shark/include/mach/memory.h
@@ -0,0 +1,48 @@
+/*
+ * arch/arm/mach-shark/include/mach/memory.h
+ *
+ * by Alexander Schulz
+ *
+ * derived from:
+ * arch/arm/mach-ebsa110/include/mach/memory.h
+ * Copyright (c) 1996-1999 Russell King.
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#include <asm/sizes.h>
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     UL(0x08000000)
+
+#ifndef __ASSEMBLY__
+
+static inline void __arch_adjust_zones(int node, unsigned long *zone_size, unsigned long *zhole_size) 
+{
+  if (node != 0) return;
+  /* Only the first 4 MB (=1024 Pages) are usable for DMA */
+  zone_size[1] = zone_size[0] - 1024;
+  zone_size[0] = 1024;
+  zhole_size[1] = zhole_size[0];
+  zhole_size[0] = 0;
+}
+
+#define arch_adjust_zones(node, size, holes) \
+        __arch_adjust_zones(node, size, holes)
+
+#define ISA_DMA_THRESHOLD       (PHYS_OFFSET + SZ_4M - 1)
+
+#endif
+
+#define __virt_to_bus(x)        __virt_to_phys(x)
+#define __bus_to_virt(x)        __phys_to_virt(x)
+
+/*
+ * Cache flushing area
+ */
+#define FLUSH_BASE_PHYS         0x80000000
+#define FLUSH_BASE              0xdf000000
+
+#endif
diff --git a/arch/arm/mach-shark/include/mach/system.h b/arch/arm/mach-shark/include/mach/system.h
new file mode 100644
index 000000000000..85aceef6f874
--- /dev/null
+++ b/arch/arm/mach-shark/include/mach/system.h
@@ -0,0 +1,28 @@
+/*
+ * arch/arm/mach-shark/include/mach/system.h
+ *
+ * by Alexander Schulz
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <asm/io.h>
+
+static void arch_reset(char mode)
+{
+        short temp;
+        local_irq_disable();
+        /* Reset the Machine via pc[3] of the sequoia chipset */
+        outw(0x09,0x24);
+        temp=inw(0x26);
+        temp = temp | (1<<3) | (1<<10);
+        outw(0x09,0x24);
+        outw(temp,0x26);
+
+}
+
+static inline void arch_idle(void)
+{
+}
+
+#endif
diff --git a/arch/arm/mach-shark/include/mach/timex.h b/arch/arm/mach-shark/include/mach/timex.h
new file mode 100644
index 000000000000..bb6eeaebed86
--- /dev/null
+++ b/arch/arm/mach-shark/include/mach/timex.h
@@ -0,0 +1,7 @@
+/*
+ * arch/arm/mach-shark/include/mach/timex.h
+ *
+ * by Alexander Schulz
+ */
+
+#define CLOCK_TICK_RATE 1193180
diff --git a/arch/arm/mach-shark/include/mach/uncompress.h b/arch/arm/mach-shark/include/mach/uncompress.h
new file mode 100644
index 000000000000..3725e1633418
--- /dev/null
+++ b/arch/arm/mach-shark/include/mach/uncompress.h
@@ -0,0 +1,51 @@
+/*
+ * arch/arm/mach-shark/include/mach/uncompress.h
+ * by Alexander Schulz
+ *
+ * derived from:
+ * arch/arm/mach-footbridge/include/mach/uncompress.h
+ * Copyright (C) 1996,1997,1998 Russell King
+ */
+
+#define SERIAL_BASE ((volatile unsigned char *)0x400003f8)
+
+static inline void putc(int c)
+{
+        int t;
+
+        SERIAL_BASE[0] = c;
+        t=0x10000;
+        while (t--);
+}
+
+static inline void flush(void)
+{
+}
+
+#ifdef DEBUG
+static void putn(unsigned long z)
+{
+        int i;
+        char x;
+
+        putc('0');
+        putc('x');
+        for (i=0;i<8;i++) {
+                x='0'+((z>>((7-i)*4))&0xf);
+                if (x>'9') x=x-'0'+'A'-10;
+                putc(x);
+        }
+}
+
+static void putr()
+{
+        putc('\n');
+        putc('\r');
+}
+#endif
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-shark/include/mach/vmalloc.h b/arch/arm/mach-shark/include/mach/vmalloc.h
new file mode 100644
index 000000000000..f6c6837c5451
--- /dev/null
+++ b/arch/arm/mach-shark/include/mach/vmalloc.h
@@ -0,0 +1,4 @@
+/*
+ * arch/arm/mach-shark/include/mach/vmalloc.h
+ */
+#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
diff --git a/arch/arm/mach-shark/irq.c b/arch/arm/mach-shark/irq.c
index 5b0c6af44ec6..44b0811b400c 100644
--- a/arch/arm/mach-shark/irq.c
+++ b/arch/arm/mach-shark/irq.c
@@ -4,7 +4,7 @@
  * by Alexander Schulz
  *
  * derived from linux/arch/ppc/kernel/i8259.c and:
- * include/asm-arm/arch-ebsa110/irq.h
+ * arch/arm/mach-ebsa110/include/mach/irq.h
  * Copyright (C) 1996-1998 Russell King
  */
 
diff --git a/arch/arm/mach-shark/leds.c b/arch/arm/mach-shark/leds.c
index 333ece0aad49..b1896471aa3c 100644
--- a/arch/arm/mach-shark/leds.c
+++ b/arch/arm/mach-shark/leds.c
@@ -21,7 +21,7 @@
 #include <linux/spinlock.h>
 #include <linux/ioport.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/io.h>
 #include <asm/system.h>
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 12097f441a8a..d75e795c893e 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -31,7 +31,7 @@
 
 #include <asm/cnt32_to_63.h>
 #include <asm/system.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/leds.h>
diff --git a/arch/arm/mach-versatile/include/mach/debug-macro.S b/arch/arm/mach-versatile/include/mach/debug-macro.S
new file mode 100644
index 000000000000..b4ac00eacf68
--- /dev/null
+++ b/arch/arm/mach-versatile/include/mach/debug-macro.S
@@ -0,0 +1,23 @@
+/* arch/arm/mach-versatile/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx,      #0x10000000
+                movne   \rx,      #0xf1000000   @ virtual base
+                orr     \rx, \rx, #0x001F0000
+                orr     \rx, \rx, #0x00001000
+                .endm
+
+#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-versatile/include/mach/dma.h b/arch/arm/mach-versatile/include/mach/dma.h
new file mode 100644
index 000000000000..0aabf12c8834
--- /dev/null
+++ b/arch/arm/mach-versatile/include/mach/dma.h
@@ -0,0 +1,20 @@
+/*
+ *  arch/arm/mach-versatile/include/mach/dma.h
+ *
+ *  Copyright (C) 2003 ARM Limited.
+ *  Copyright (C) 1997,1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
diff --git a/arch/arm/mach-versatile/include/mach/entry-macro.S b/arch/arm/mach-versatile/include/mach/entry-macro.S
new file mode 100644
index 000000000000..8c8020980585
--- /dev/null
+++ b/arch/arm/mach-versatile/include/mach/entry-macro.S
@@ -0,0 +1,44 @@
+/*
+ * arch/arm/mach-versatile/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for Versatile platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <mach/hardware.h>
+#include <asm/hardware/vic.h>
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_preamble, base, tmp
+                ldr     \base, =IO_ADDRESS(VERSATILE_VIC_BASE)
+                .endm
+
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                ldr     \irqstat, [\base, #VIC_IRQ_STATUS]      @ get masked status
+                mov     \irqnr, #0
+                teq     \irqstat, #0
+                beq     1003f
+
+1001:           tst     \irqstat, #15
+                bne     1002f
+                add     \irqnr, \irqnr, #4
+                movs    \irqstat, \irqstat, lsr #4
+                bne     1001b
+1002:           tst     \irqstat, #1
+                bne     1003f
+                add     \irqnr, \irqnr, #1
+                movs    \irqstat, \irqstat, lsr #1
+                bne     1002b
+1003:           /* EQ will be set if no irqs pending */
+
+@               clz     \irqnr, \irqstat
+@1003:          /* EQ will be set if we reach MAXIRQNUM */
+                .endm
+
diff --git a/arch/arm/mach-versatile/include/mach/hardware.h b/arch/arm/mach-versatile/include/mach/hardware.h
new file mode 100644
index 000000000000..7aa906c93154
--- /dev/null
+++ b/arch/arm/mach-versatile/include/mach/hardware.h
@@ -0,0 +1,52 @@
+/*
+ *  arch/arm/mach-versatile/include/mach/hardware.h
+ *
+ *  This file contains the hardware definitions of the Versatile boards.
+ *
+ *  Copyright (C) 2003 ARM Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/sizes.h>
+#include <mach/platform.h>
+
+/*
+ * PCI space virtual addresses
+ */
+#define VERSATILE_PCI_VIRT_BASE         (void __iomem *)0xe8000000ul
+#define VERSATILE_PCI_CFG_VIRT_BASE     (void __iomem *)0xe9000000ul
+
+#if 0
+#define VERSATILE_PCI_VIRT_MEM_BASE0    0xf4000000
+#define VERSATILE_PCI_VIRT_MEM_BASE1    0xf5000000
+#define VERSATILE_PCI_VIRT_MEM_BASE2    0xf6000000
+
+#define PCIO_BASE                       VERSATILE_PCI_VIRT_MEM_BASE0
+#define PCIMEM_BASE                     VERSATILE_PCI_VIRT_MEM_BASE1
+#endif
+
+/* CIK guesswork */
+#define PCIBIOS_MIN_IO                  0x44000000
+#define PCIBIOS_MIN_MEM                 0x50000000
+
+#define pcibios_assign_all_busses()     1
+
+/* macro to get at IO space when running virtually */
+#define IO_ADDRESS(x)           (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
+
+#endif
diff --git a/arch/arm/mach-versatile/include/mach/io.h b/arch/arm/mach-versatile/include/mach/io.h
new file mode 100644
index 000000000000..c0b9dd1d0257
--- /dev/null
+++ b/arch/arm/mach-versatile/include/mach/io.h
@@ -0,0 +1,32 @@
+/*
+ *  arch/arm/mach-versatile/include/mach/io.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+static inline void __iomem *__io(unsigned long addr)
+{
+        return (void __iomem *)addr;
+}
+#define __io(a) __io(a)
+#define __mem_pci(a)            (a)
+
+#endif
diff --git a/arch/arm/mach-versatile/include/mach/irqs.h b/arch/arm/mach-versatile/include/mach/irqs.h
new file mode 100644
index 000000000000..216a1312e62e
--- /dev/null
+++ b/arch/arm/mach-versatile/include/mach/irqs.h
@@ -0,0 +1,211 @@
+/*
+ *  arch/arm/mach-versatile/include/mach/irqs.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <mach/platform.h>
+
+/* 
+ *  IRQ interrupts definitions are the same as the INT definitions
+ *  held within platform.h
+ */
+#define IRQ_VIC_START           0
+#define IRQ_WDOGINT             (IRQ_VIC_START + INT_WDOGINT)
+#define IRQ_SOFTINT             (IRQ_VIC_START + INT_SOFTINT)
+#define IRQ_COMMRx              (IRQ_VIC_START + INT_COMMRx)
+#define IRQ_COMMTx              (IRQ_VIC_START + INT_COMMTx)
+#define IRQ_TIMERINT0_1         (IRQ_VIC_START + INT_TIMERINT0_1)
+#define IRQ_TIMERINT2_3         (IRQ_VIC_START + INT_TIMERINT2_3)
+#define IRQ_GPIOINT0            (IRQ_VIC_START + INT_GPIOINT0)
+#define IRQ_GPIOINT1            (IRQ_VIC_START + INT_GPIOINT1)
+#define IRQ_GPIOINT2            (IRQ_VIC_START + INT_GPIOINT2)
+#define IRQ_GPIOINT3            (IRQ_VIC_START + INT_GPIOINT3)
+#define IRQ_RTCINT              (IRQ_VIC_START + INT_RTCINT)
+#define IRQ_SSPINT              (IRQ_VIC_START + INT_SSPINT)
+#define IRQ_UARTINT0            (IRQ_VIC_START + INT_UARTINT0)
+#define IRQ_UARTINT1            (IRQ_VIC_START + INT_UARTINT1)
+#define IRQ_UARTINT2            (IRQ_VIC_START + INT_UARTINT2)
+#define IRQ_SCIINT              (IRQ_VIC_START + INT_SCIINT)
+#define IRQ_CLCDINT             (IRQ_VIC_START + INT_CLCDINT)
+#define IRQ_DMAINT              (IRQ_VIC_START + INT_DMAINT)
+#define IRQ_PWRFAILINT          (IRQ_VIC_START + INT_PWRFAILINT)
+#define IRQ_MBXINT              (IRQ_VIC_START + INT_MBXINT)
+#define IRQ_GNDINT              (IRQ_VIC_START + INT_GNDINT)
+#define IRQ_VICSOURCE21         (IRQ_VIC_START + INT_VICSOURCE21)
+#define IRQ_VICSOURCE22         (IRQ_VIC_START + INT_VICSOURCE22)
+#define IRQ_VICSOURCE23         (IRQ_VIC_START + INT_VICSOURCE23)
+#define IRQ_VICSOURCE24         (IRQ_VIC_START + INT_VICSOURCE24)
+#define IRQ_VICSOURCE25         (IRQ_VIC_START + INT_VICSOURCE25)
+#define IRQ_VICSOURCE26         (IRQ_VIC_START + INT_VICSOURCE26)
+#define IRQ_VICSOURCE27         (IRQ_VIC_START + INT_VICSOURCE27)
+#define IRQ_VICSOURCE28         (IRQ_VIC_START + INT_VICSOURCE28)
+#define IRQ_VICSOURCE29         (IRQ_VIC_START + INT_VICSOURCE29)
+#define IRQ_VICSOURCE30         (IRQ_VIC_START + INT_VICSOURCE30)
+#define IRQ_VICSOURCE31         (IRQ_VIC_START + INT_VICSOURCE31)
+#define IRQ_VIC_END             (IRQ_VIC_START + 31)
+
+#define IRQMASK_WDOGINT         INTMASK_WDOGINT
+#define IRQMASK_SOFTINT         INTMASK_SOFTINT
+#define IRQMASK_COMMRx          INTMASK_COMMRx
+#define IRQMASK_COMMTx          INTMASK_COMMTx
+#define IRQMASK_TIMERINT0_1     INTMASK_TIMERINT0_1
+#define IRQMASK_TIMERINT2_3     INTMASK_TIMERINT2_3
+#define IRQMASK_GPIOINT0        INTMASK_GPIOINT0
+#define IRQMASK_GPIOINT1        INTMASK_GPIOINT1
+#define IRQMASK_GPIOINT2        INTMASK_GPIOINT2
+#define IRQMASK_GPIOINT3        INTMASK_GPIOINT3
+#define IRQMASK_RTCINT          INTMASK_RTCINT
+#define IRQMASK_SSPINT          INTMASK_SSPINT
+#define IRQMASK_UARTINT0        INTMASK_UARTINT0
+#define IRQMASK_UARTINT1        INTMASK_UARTINT1
+#define IRQMASK_UARTINT2        INTMASK_UARTINT2
+#define IRQMASK_SCIINT          INTMASK_SCIINT
+#define IRQMASK_CLCDINT         INTMASK_CLCDINT
+#define IRQMASK_DMAINT          INTMASK_DMAINT
+#define IRQMASK_PWRFAILINT      INTMASK_PWRFAILINT
+#define IRQMASK_MBXINT          INTMASK_MBXINT
+#define IRQMASK_GNDINT          INTMASK_GNDINT
+#define IRQMASK_VICSOURCE21     INTMASK_VICSOURCE21
+#define IRQMASK_VICSOURCE22     INTMASK_VICSOURCE22
+#define IRQMASK_VICSOURCE23     INTMASK_VICSOURCE23
+#define IRQMASK_VICSOURCE24     INTMASK_VICSOURCE24
+#define IRQMASK_VICSOURCE25     INTMASK_VICSOURCE25
+#define IRQMASK_VICSOURCE26     INTMASK_VICSOURCE26
+#define IRQMASK_VICSOURCE27     INTMASK_VICSOURCE27
+#define IRQMASK_VICSOURCE28     INTMASK_VICSOURCE28
+#define IRQMASK_VICSOURCE29     INTMASK_VICSOURCE29
+#define IRQMASK_VICSOURCE30     INTMASK_VICSOURCE30
+#define IRQMASK_VICSOURCE31     INTMASK_VICSOURCE31
+
+/* 
+ *  FIQ interrupts definitions are the same as the INT definitions.
+ */
+#define FIQ_WDOGINT             INT_WDOGINT
+#define FIQ_SOFTINT             INT_SOFTINT
+#define FIQ_COMMRx              INT_COMMRx
+#define FIQ_COMMTx              INT_COMMTx
+#define FIQ_TIMERINT0_1         INT_TIMERINT0_1
+#define FIQ_TIMERINT2_3         INT_TIMERINT2_3
+#define FIQ_GPIOINT0            INT_GPIOINT0
+#define FIQ_GPIOINT1            INT_GPIOINT1
+#define FIQ_GPIOINT2            INT_GPIOINT2
+#define FIQ_GPIOINT3            INT_GPIOINT3
+#define FIQ_RTCINT              INT_RTCINT
+#define FIQ_SSPINT              INT_SSPINT
+#define FIQ_UARTINT0            INT_UARTINT0
+#define FIQ_UARTINT1            INT_UARTINT1
+#define FIQ_UARTINT2            INT_UARTINT2
+#define FIQ_SCIINT              INT_SCIINT
+#define FIQ_CLCDINT             INT_CLCDINT
+#define FIQ_DMAINT              INT_DMAINT
+#define FIQ_PWRFAILINT          INT_PWRFAILINT
+#define FIQ_MBXINT              INT_MBXINT
+#define FIQ_GNDINT              INT_GNDINT
+#define FIQ_VICSOURCE21         INT_VICSOURCE21
+#define FIQ_VICSOURCE22         INT_VICSOURCE22
+#define FIQ_VICSOURCE23         INT_VICSOURCE23
+#define FIQ_VICSOURCE24         INT_VICSOURCE24
+#define FIQ_VICSOURCE25         INT_VICSOURCE25
+#define FIQ_VICSOURCE26         INT_VICSOURCE26
+#define FIQ_VICSOURCE27         INT_VICSOURCE27
+#define FIQ_VICSOURCE28         INT_VICSOURCE28
+#define FIQ_VICSOURCE29         INT_VICSOURCE29
+#define FIQ_VICSOURCE30         INT_VICSOURCE30
+#define FIQ_VICSOURCE31         INT_VICSOURCE31
+
+
+#define FIQMASK_WDOGINT         INTMASK_WDOGINT
+#define FIQMASK_SOFTINT         INTMASK_SOFTINT
+#define FIQMASK_COMMRx          INTMASK_COMMRx
+#define FIQMASK_COMMTx          INTMASK_COMMTx
+#define FIQMASK_TIMERINT0_1     INTMASK_TIMERINT0_1
+#define FIQMASK_TIMERINT2_3     INTMASK_TIMERINT2_3
+#define FIQMASK_GPIOINT0        INTMASK_GPIOINT0
+#define FIQMASK_GPIOINT1        INTMASK_GPIOINT1
+#define FIQMASK_GPIOINT2        INTMASK_GPIOINT2
+#define FIQMASK_GPIOINT3        INTMASK_GPIOINT3
+#define FIQMASK_RTCINT          INTMASK_RTCINT
+#define FIQMASK_SSPINT          INTMASK_SSPINT
+#define FIQMASK_UARTINT0        INTMASK_UARTINT0
+#define FIQMASK_UARTINT1        INTMASK_UARTINT1
+#define FIQMASK_UARTINT2        INTMASK_UARTINT2
+#define FIQMASK_SCIINT          INTMASK_SCIINT
+#define FIQMASK_CLCDINT         INTMASK_CLCDINT
+#define FIQMASK_DMAINT          INTMASK_DMAINT
+#define FIQMASK_PWRFAILINT      INTMASK_PWRFAILINT
+#define FIQMASK_MBXINT          INTMASK_MBXINT
+#define FIQMASK_GNDINT          INTMASK_GNDINT
+#define FIQMASK_VICSOURCE21     INTMASK_VICSOURCE21
+#define FIQMASK_VICSOURCE22     INTMASK_VICSOURCE22
+#define FIQMASK_VICSOURCE23     INTMASK_VICSOURCE23
+#define FIQMASK_VICSOURCE24     INTMASK_VICSOURCE24
+#define FIQMASK_VICSOURCE25     INTMASK_VICSOURCE25
+#define FIQMASK_VICSOURCE26     INTMASK_VICSOURCE26
+#define FIQMASK_VICSOURCE27     INTMASK_VICSOURCE27
+#define FIQMASK_VICSOURCE28     INTMASK_VICSOURCE28
+#define FIQMASK_VICSOURCE29     INTMASK_VICSOURCE29
+#define FIQMASK_VICSOURCE30     INTMASK_VICSOURCE30
+#define FIQMASK_VICSOURCE31     INTMASK_VICSOURCE31
+
+/*
+ * Secondary interrupt controller
+ */
+#define IRQ_SIC_START           32
+#define IRQ_SIC_MMCI0B          (IRQ_SIC_START + SIC_INT_MMCI0B)
+#define IRQ_SIC_MMCI1B          (IRQ_SIC_START + SIC_INT_MMCI1B)
+#define IRQ_SIC_KMI0            (IRQ_SIC_START + SIC_INT_KMI0)
+#define IRQ_SIC_KMI1            (IRQ_SIC_START + SIC_INT_KMI1)
+#define IRQ_SIC_SCI3            (IRQ_SIC_START + SIC_INT_SCI3)
+#define IRQ_SIC_UART3           (IRQ_SIC_START + SIC_INT_UART3)
+#define IRQ_SIC_CLCD            (IRQ_SIC_START + SIC_INT_CLCD)
+#define IRQ_SIC_TOUCH           (IRQ_SIC_START + SIC_INT_TOUCH)
+#define IRQ_SIC_KEYPAD          (IRQ_SIC_START + SIC_INT_KEYPAD)
+#define IRQ_SIC_DoC             (IRQ_SIC_START + SIC_INT_DoC)
+#define IRQ_SIC_MMCI0A          (IRQ_SIC_START + SIC_INT_MMCI0A)
+#define IRQ_SIC_MMCI1A          (IRQ_SIC_START + SIC_INT_MMCI1A)
+#define IRQ_SIC_AACI            (IRQ_SIC_START + SIC_INT_AACI)
+#define IRQ_SIC_ETH             (IRQ_SIC_START + SIC_INT_ETH)
+#define IRQ_SIC_USB             (IRQ_SIC_START + SIC_INT_USB)
+#define IRQ_SIC_PCI0            (IRQ_SIC_START + SIC_INT_PCI0)
+#define IRQ_SIC_PCI1            (IRQ_SIC_START + SIC_INT_PCI1)
+#define IRQ_SIC_PCI2            (IRQ_SIC_START + SIC_INT_PCI2)
+#define IRQ_SIC_PCI3            (IRQ_SIC_START + SIC_INT_PCI3)
+#define IRQ_SIC_END             63
+
+#define SIC_IRQMASK_MMCI0B      SIC_INTMASK_MMCI0B
+#define SIC_IRQMASK_MMCI1B      SIC_INTMASK_MMCI1B
+#define SIC_IRQMASK_KMI0        SIC_INTMASK_KMI0
+#define SIC_IRQMASK_KMI1        SIC_INTMASK_KMI1
+#define SIC_IRQMASK_SCI3        SIC_INTMASK_SCI3
+#define SIC_IRQMASK_UART3       SIC_INTMASK_UART3
+#define SIC_IRQMASK_CLCD        SIC_INTMASK_CLCD
+#define SIC_IRQMASK_TOUCH       SIC_INTMASK_TOUCH
+#define SIC_IRQMASK_KEYPAD      SIC_INTMASK_KEYPAD
+#define SIC_IRQMASK_DoC         SIC_INTMASK_DoC
+#define SIC_IRQMASK_MMCI0A      SIC_INTMASK_MMCI0A
+#define SIC_IRQMASK_MMCI1A      SIC_INTMASK_MMCI1A
+#define SIC_IRQMASK_AACI        SIC_INTMASK_AACI
+#define SIC_IRQMASK_ETH         SIC_INTMASK_ETH
+#define SIC_IRQMASK_USB         SIC_INTMASK_USB
+#define SIC_IRQMASK_PCI0        SIC_INTMASK_PCI0
+#define SIC_IRQMASK_PCI1        SIC_INTMASK_PCI1
+#define SIC_IRQMASK_PCI2        SIC_INTMASK_PCI2
+#define SIC_IRQMASK_PCI3        SIC_INTMASK_PCI3
+
+#define NR_IRQS                 64
diff --git a/arch/arm/mach-versatile/include/mach/memory.h b/arch/arm/mach-versatile/include/mach/memory.h
new file mode 100644
index 000000000000..b6315c0602ac
--- /dev/null
+++ b/arch/arm/mach-versatile/include/mach/memory.h
@@ -0,0 +1,38 @@
+/*
+ *  arch/arm/mach-versatile/include/mach/memory.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     UL(0x00000000)
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+#define __virt_to_bus(x)        ((x) - PAGE_OFFSET)
+#define __bus_to_virt(x)        ((x) + PAGE_OFFSET)
+
+#endif
diff --git a/arch/arm/mach-versatile/include/mach/platform.h b/arch/arm/mach-versatile/include/mach/platform.h
new file mode 100644
index 000000000000..27cbe6a3f220
--- /dev/null
+++ b/arch/arm/mach-versatile/include/mach/platform.h
@@ -0,0 +1,510 @@
+/*
+ * arch/arm/mach-versatile/include/mach/platform.h
+ *
+ * Copyright (c) ARM Limited 2003.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __address_h
+#define __address_h                     1
+
+/*
+ * Memory definitions
+ */
+#define VERSATILE_BOOT_ROM_LO          0x30000000               /* DoC Base (64Mb)...*/
+#define VERSATILE_BOOT_ROM_HI          0x30000000
+#define VERSATILE_BOOT_ROM_BASE        VERSATILE_BOOT_ROM_HI     /*  Normal position */
+#define VERSATILE_BOOT_ROM_SIZE        SZ_64M
+
+#define VERSATILE_SSRAM_BASE           /* VERSATILE_SSMC_BASE ? */
+#define VERSATILE_SSRAM_SIZE           SZ_2M
+
+#define VERSATILE_FLASH_BASE           0x34000000
+#define VERSATILE_FLASH_SIZE           SZ_64M
+
+/* 
+ *  SDRAM
+ */
+#define VERSATILE_SDRAM_BASE           0x00000000
+
+/* 
+ *  Logic expansion modules
+ * 
+ */
+
+
+/* ------------------------------------------------------------------------
+ *  Versatile Registers
+ * ------------------------------------------------------------------------
+ * 
+ */
+#define VERSATILE_SYS_ID_OFFSET               0x00
+#define VERSATILE_SYS_SW_OFFSET               0x04
+#define VERSATILE_SYS_LED_OFFSET              0x08
+#define VERSATILE_SYS_OSC0_OFFSET             0x0C
+
+#if defined(CONFIG_ARCH_VERSATILE_PB)
+#define VERSATILE_SYS_OSC1_OFFSET             0x10
+#define VERSATILE_SYS_OSC2_OFFSET             0x14
+#define VERSATILE_SYS_OSC3_OFFSET             0x18
+#define VERSATILE_SYS_OSC4_OFFSET             0x1C
+#elif defined(CONFIG_MACH_VERSATILE_AB)
+#define VERSATILE_SYS_OSC1_OFFSET             0x1C
+#endif
+
+#define VERSATILE_SYS_OSCCLCD_OFFSET          0x1c
+
+#define VERSATILE_SYS_LOCK_OFFSET             0x20
+#define VERSATILE_SYS_100HZ_OFFSET            0x24
+#define VERSATILE_SYS_CFGDATA1_OFFSET         0x28
+#define VERSATILE_SYS_CFGDATA2_OFFSET         0x2C
+#define VERSATILE_SYS_FLAGS_OFFSET            0x30
+#define VERSATILE_SYS_FLAGSSET_OFFSET         0x30
+#define VERSATILE_SYS_FLAGSCLR_OFFSET         0x34
+#define VERSATILE_SYS_NVFLAGS_OFFSET          0x38
+#define VERSATILE_SYS_NVFLAGSSET_OFFSET       0x38
+#define VERSATILE_SYS_NVFLAGSCLR_OFFSET       0x3C
+#define VERSATILE_SYS_RESETCTL_OFFSET         0x40
+#define VERSATILE_SYS_PCICTL_OFFSET           0x44
+#define VERSATILE_SYS_MCI_OFFSET              0x48
+#define VERSATILE_SYS_FLASH_OFFSET            0x4C
+#define VERSATILE_SYS_CLCD_OFFSET             0x50
+#define VERSATILE_SYS_CLCDSER_OFFSET          0x54
+#define VERSATILE_SYS_BOOTCS_OFFSET           0x58
+#define VERSATILE_SYS_24MHz_OFFSET            0x5C
+#define VERSATILE_SYS_MISC_OFFSET             0x60
+#define VERSATILE_SYS_TEST_OSC0_OFFSET        0x80
+#define VERSATILE_SYS_TEST_OSC1_OFFSET        0x84
+#define VERSATILE_SYS_TEST_OSC2_OFFSET        0x88
+#define VERSATILE_SYS_TEST_OSC3_OFFSET        0x8C
+#define VERSATILE_SYS_TEST_OSC4_OFFSET        0x90
+
+#define VERSATILE_SYS_BASE                    0x10000000
+#define VERSATILE_SYS_ID                      (VERSATILE_SYS_BASE + VERSATILE_SYS_ID_OFFSET)
+#define VERSATILE_SYS_SW                      (VERSATILE_SYS_BASE + VERSATILE_SYS_SW_OFFSET)
+#define VERSATILE_SYS_LED                     (VERSATILE_SYS_BASE + VERSATILE_SYS_LED_OFFSET)
+#define VERSATILE_SYS_OSC0                    (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC0_OFFSET)
+#define VERSATILE_SYS_OSC1                    (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC1_OFFSET)
+
+#if defined(CONFIG_ARCH_VERSATILE_PB)
+#define VERSATILE_SYS_OSC2                    (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC2_OFFSET)
+#define VERSATILE_SYS_OSC3                    (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC3_OFFSET)
+#define VERSATILE_SYS_OSC4                    (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC4_OFFSET)
+#endif
+
+#define VERSATILE_SYS_LOCK                    (VERSATILE_SYS_BASE + VERSATILE_SYS_LOCK_OFFSET)
+#define VERSATILE_SYS_100HZ                   (VERSATILE_SYS_BASE + VERSATILE_SYS_100HZ_OFFSET)
+#define VERSATILE_SYS_CFGDATA1                (VERSATILE_SYS_BASE + VERSATILE_SYS_CFGDATA1_OFFSET)
+#define VERSATILE_SYS_CFGDATA2                (VERSATILE_SYS_BASE + VERSATILE_SYS_CFGDATA2_OFFSET)
+#define VERSATILE_SYS_FLAGS                   (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGS_OFFSET)
+#define VERSATILE_SYS_FLAGSSET                (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGSSET_OFFSET)
+#define VERSATILE_SYS_FLAGSCLR                (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGSCLR_OFFSET)
+#define VERSATILE_SYS_NVFLAGS                 (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGS_OFFSET)
+#define VERSATILE_SYS_NVFLAGSSET              (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSSET_OFFSET)
+#define VERSATILE_SYS_NVFLAGSCLR              (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSCLR_OFFSET)
+#define VERSATILE_SYS_RESETCTL                (VERSATILE_SYS_BASE + VERSATILE_SYS_RESETCTL_OFFSET)
+#define VERSATILE_SYS_PCICTL                  (VERSATILE_SYS_BASE + VERSATILE_SYS_PCICTL_OFFSET)
+#define VERSATILE_SYS_MCI                     (VERSATILE_SYS_BASE + VERSATILE_SYS_MCI_OFFSET)
+#define VERSATILE_SYS_FLASH                   (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET)
+#define VERSATILE_SYS_CLCD                    (VERSATILE_SYS_BASE + VERSATILE_SYS_CLCD_OFFSET)
+#define VERSATILE_SYS_CLCDSER                 (VERSATILE_SYS_BASE + VERSATILE_SYS_CLCDSER_OFFSET)
+#define VERSATILE_SYS_BOOTCS                  (VERSATILE_SYS_BASE + VERSATILE_SYS_BOOTCS_OFFSET)
+#define VERSATILE_SYS_24MHz                   (VERSATILE_SYS_BASE + VERSATILE_SYS_24MHz_OFFSET)
+#define VERSATILE_SYS_MISC                    (VERSATILE_SYS_BASE + VERSATILE_SYS_MISC_OFFSET)
+#define VERSATILE_SYS_TEST_OSC0               (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC0_OFFSET)
+#define VERSATILE_SYS_TEST_OSC1               (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC1_OFFSET)
+#define VERSATILE_SYS_TEST_OSC2               (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC2_OFFSET)
+#define VERSATILE_SYS_TEST_OSC3               (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC3_OFFSET)
+#define VERSATILE_SYS_TEST_OSC4               (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC4_OFFSET)
+
+/* 
+ * Values for VERSATILE_SYS_RESET_CTRL
+ */
+#define VERSATILE_SYS_CTRL_RESET_CONFIGCLR    0x01
+#define VERSATILE_SYS_CTRL_RESET_CONFIGINIT   0x02
+#define VERSATILE_SYS_CTRL_RESET_DLLRESET     0x03
+#define VERSATILE_SYS_CTRL_RESET_PLLRESET     0x04
+#define VERSATILE_SYS_CTRL_RESET_POR          0x05
+#define VERSATILE_SYS_CTRL_RESET_DoC          0x06
+
+#define VERSATILE_SYS_CTRL_LED         (1 << 0)
+
+
+/* ------------------------------------------------------------------------
+ *  Versatile control registers
+ * ------------------------------------------------------------------------
+ */
+
+/* 
+ * VERSATILE_IDFIELD
+ *
+ * 31:24 = manufacturer (0x41 = ARM)
+ * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus)
+ * 15:12 = FPGA (0x3 = XVC600 or XVC600E)
+ * 11:4  = build value
+ * 3:0   = revision number (0x1 = rev B (AHB))
+ */
+
+/*
+ * VERSATILE_SYS_LOCK
+ *     control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL, 
+ *     SYS_CLD, SYS_BOOTCS
+ */
+#define VERSATILE_SYS_LOCK_LOCKED    (1 << 16)
+#define VERSATILE_SYS_LOCKVAL_MASK      0xFFFF          /* write 0xA05F to enable write access */
+
+/*
+ * VERSATILE_SYS_FLASH
+ */
+#define VERSATILE_FLASHPROG_FLVPPEN     (1 << 0)        /* Enable writing to flash */
+
+/*
+ * VERSATILE_INTREG
+ *     - used to acknowledge and control MMCI and UART interrupts 
+ */
+#define VERSATILE_INTREG_WPROT        0x00    /* MMC protection status (no interrupt generated) */
+#define VERSATILE_INTREG_RI0          0x01    /* Ring indicator UART0 is asserted,              */
+#define VERSATILE_INTREG_CARDIN       0x08    /* MMCI card in detect                            */
+                                                /* write 1 to acknowledge and clear               */
+#define VERSATILE_INTREG_RI1          0x02    /* Ring indicator UART1 is asserted,              */
+#define VERSATILE_INTREG_CARDINSERT   0x03    /* Signal insertion of MMC card                   */
+
+/*
+ * VERSATILE peripheral addresses
+ */
+#define VERSATILE_PCI_CORE_BASE        0x10001000       /* PCI core control */
+#define VERSATILE_I2C_BASE             0x10002000       /* I2C control */
+#define VERSATILE_SIC_BASE             0x10003000       /* Secondary interrupt controller */
+#define VERSATILE_AACI_BASE            0x10004000       /* Audio */
+#define VERSATILE_MMCI0_BASE           0x10005000       /* MMC interface */
+#define VERSATILE_KMI0_BASE            0x10006000       /* KMI interface */
+#define VERSATILE_KMI1_BASE            0x10007000       /* KMI 2nd interface */
+#define VERSATILE_CHAR_LCD_BASE        0x10008000       /* Character LCD */
+#define VERSATILE_UART3_BASE           0x10009000       /* UART 3 */
+#define VERSATILE_SCI1_BASE            0x1000A000
+#define VERSATILE_MMCI1_BASE           0x1000B000    /* MMC Interface */
+        /* 0x1000C000 - 0x1000CFFF = reserved */
+#define VERSATILE_ETH_BASE             0x10010000       /* Ethernet */
+#define VERSATILE_USB_BASE             0x10020000       /* USB */
+        /* 0x10030000 - 0x100FFFFF = reserved */
+#define VERSATILE_SMC_BASE             0x10100000       /* SMC */
+#define VERSATILE_MPMC_BASE            0x10110000       /* MPMC */
+#define VERSATILE_CLCD_BASE            0x10120000       /* CLCD */
+#define VERSATILE_DMAC_BASE            0x10130000       /* DMA controller */
+#define VERSATILE_VIC_BASE             0x10140000       /* Vectored interrupt controller */
+#define VERSATILE_PERIPH_BASE          0x10150000    /* off-chip peripherals alias from */
+                                                /* 0x10000000 - 0x100FFFFF */
+#define VERSATILE_AHBM_BASE            0x101D0000       /* AHB monitor */
+#define VERSATILE_SCTL_BASE            0x101E0000       /* System controller */
+#define VERSATILE_WATCHDOG_BASE        0x101E1000       /* Watchdog */
+#define VERSATILE_TIMER0_1_BASE        0x101E2000       /* Timer 0 and 1 */
+#define VERSATILE_TIMER2_3_BASE        0x101E3000       /* Timer 2 and 3 */
+#define VERSATILE_GPIO0_BASE           0x101E4000       /* GPIO port 0 */
+#define VERSATILE_GPIO1_BASE           0x101E5000    /* GPIO port 1 */
+#define VERSATILE_GPIO2_BASE           0x101E6000       /* GPIO port 2 */
+#define VERSATILE_GPIO3_BASE           0x101E7000       /* GPIO port 3 */
+#define VERSATILE_RTC_BASE             0x101E8000       /* Real Time Clock */
+        /* 0x101E9000 - reserved */
+#define VERSATILE_SCI_BASE             0x101F0000       /* Smart card controller */
+#define VERSATILE_UART0_BASE           0x101F1000       /* Uart 0 */
+#define VERSATILE_UART1_BASE           0x101F2000       /* Uart 1 */
+#define VERSATILE_UART2_BASE           0x101F3000       /* Uart 2 */
+#define VERSATILE_SSP_BASE             0x101F4000       /* Synchronous Serial Port */
+
+#define VERSATILE_SSMC_BASE            0x20000000       /* SSMC */
+#define VERSATILE_IB2_BASE             0x24000000       /* IB2 module */
+#define VERSATILE_MBX_BASE             0x40000000       /* MBX */
+
+/* PCI space */
+#define VERSATILE_PCI_BASE             0x41000000       /* PCI Interface */
+#define VERSATILE_PCI_CFG_BASE         0x42000000
+#define VERSATILE_PCI_MEM_BASE0        0x44000000
+#define VERSATILE_PCI_MEM_BASE1        0x50000000
+#define VERSATILE_PCI_MEM_BASE2        0x60000000
+/* Sizes of above maps */
+#define VERSATILE_PCI_BASE_SIZE        0x01000000
+#define VERSATILE_PCI_CFG_BASE_SIZE    0x02000000
+#define VERSATILE_PCI_MEM_BASE0_SIZE   0x0c000000       /* 32Mb */
+#define VERSATILE_PCI_MEM_BASE1_SIZE   0x10000000       /* 256Mb */
+#define VERSATILE_PCI_MEM_BASE2_SIZE   0x10000000       /* 256Mb */
+
+#define VERSATILE_SDRAM67_BASE         0x70000000       /* SDRAM banks 6 and 7 */
+#define VERSATILE_LT_BASE              0x80000000       /* Logic Tile expansion */
+
+/*
+ * Disk on Chip
+ */
+#define VERSATILE_DOC_BASE             0x2C000000
+#define VERSATILE_DOC_SIZE             (16 << 20)
+#define VERSATILE_DOC_PAGE_SIZE        512
+#define VERSATILE_DOC_TOTAL_PAGES     (DOC_SIZE / PAGE_SIZE)
+
+#define ERASE_UNIT_PAGES    32
+#define START_PAGE          0x80
+
+/* 
+ *  LED settings, bits [7:0]
+ */
+#define VERSATILE_SYS_LED0             (1 << 0)
+#define VERSATILE_SYS_LED1             (1 << 1)
+#define VERSATILE_SYS_LED2             (1 << 2)
+#define VERSATILE_SYS_LED3             (1 << 3)
+#define VERSATILE_SYS_LED4             (1 << 4)
+#define VERSATILE_SYS_LED5             (1 << 5)
+#define VERSATILE_SYS_LED6             (1 << 6)
+#define VERSATILE_SYS_LED7             (1 << 7)
+
+#define ALL_LEDS                  0xFF
+
+#define LED_BANK                  VERSATILE_SYS_LED
+
+/* 
+ * Control registers
+ */
+#define VERSATILE_IDFIELD_OFFSET        0x0     /* Versatile build information */
+#define VERSATILE_FLASHPROG_OFFSET      0x4     /* Flash devices */
+#define VERSATILE_INTREG_OFFSET         0x8     /* Interrupt control */
+#define VERSATILE_DECODE_OFFSET         0xC     /* Fitted logic modules */
+
+
+/* ------------------------------------------------------------------------
+ *  Versatile Interrupt Controller - control registers
+ * ------------------------------------------------------------------------
+ * 
+ *  Offsets from interrupt controller base 
+ * 
+ *  System Controller interrupt controller base is
+ * 
+ *      VERSATILE_IC_BASE
+ * 
+ *  Core Module interrupt controller base is
+ * 
+ *      VERSATILE_SYS_IC 
+ * 
+ */
+/* VIC definitions in include/asm-arm/hardware/vic.h */
+
+#define SIC_IRQ_STATUS                  0
+#define SIC_IRQ_RAW_STATUS              0x04
+#define SIC_IRQ_ENABLE                  0x08
+#define SIC_IRQ_ENABLE_SET              0x08
+#define SIC_IRQ_ENABLE_CLEAR            0x0C
+#define SIC_INT_SOFT_SET                0x10
+#define SIC_INT_SOFT_CLEAR              0x14
+#define SIC_INT_PIC_ENABLE              0x20    /* read status of pass through mask */
+#define SIC_INT_PIC_ENABLES             0x20    /* set interrupt pass through bits */
+#define SIC_INT_PIC_ENABLEC             0x24    /* Clear interrupt pass through bits */
+
+/* ------------------------------------------------------------------------
+ *  Interrupts - bit assignment (primary)
+ * ------------------------------------------------------------------------
+ */
+
+#define INT_WDOGINT                     0       /* Watchdog timer */
+#define INT_SOFTINT                     1       /* Software interrupt */
+#define INT_COMMRx                      2       /* Debug Comm Rx interrupt */
+#define INT_COMMTx                      3       /* Debug Comm Tx interrupt */
+#define INT_TIMERINT0_1                 4       /* Timer 0 and 1 */
+#define INT_TIMERINT2_3                 5       /* Timer 2 and 3 */
+#define INT_GPIOINT0                    6       /* GPIO 0 */
+#define INT_GPIOINT1                    7       /* GPIO 1 */
+#define INT_GPIOINT2                    8       /* GPIO 2 */
+#define INT_GPIOINT3                    9       /* GPIO 3 */
+#define INT_RTCINT                      10      /* Real Time Clock */
+#define INT_SSPINT                      11      /* Synchronous Serial Port */
+#define INT_UARTINT0                    12      /* UART 0 on development chip */
+#define INT_UARTINT1                    13      /* UART 1 on development chip */
+#define INT_UARTINT2                    14      /* UART 2 on development chip */
+#define INT_SCIINT                      15      /* Smart Card Interface */
+#define INT_CLCDINT                     16      /* CLCD controller */
+#define INT_DMAINT                      17      /* DMA controller */
+#define INT_PWRFAILINT                  18      /* Power failure */
+#define INT_MBXINT                      19      /* Graphics processor */
+#define INT_GNDINT                      20      /* Reserved */
+        /* External interrupt signals from logic tiles or secondary controller */
+#define INT_VICSOURCE21                 21      /* Disk on Chip */
+#define INT_VICSOURCE22                 22      /* MCI0A */
+#define INT_VICSOURCE23                 23      /* MCI1A */
+#define INT_VICSOURCE24                 24      /* AACI */
+#define INT_VICSOURCE25                 25      /* Ethernet */
+#define INT_VICSOURCE26                 26      /* USB */
+#define INT_VICSOURCE27                 27      /* PCI 0 */
+#define INT_VICSOURCE28                 28      /* PCI 1 */
+#define INT_VICSOURCE29                 29      /* PCI 2 */
+#define INT_VICSOURCE30                 30      /* PCI 3 */
+#define INT_VICSOURCE31                 31      /* SIC source */
+
+/* 
+ *  Interrupt bit positions
+ * 
+ */
+#define INTMASK_WDOGINT                 (1 << INT_WDOGINT)
+#define INTMASK_SOFTINT                 (1 << INT_SOFTINT)
+#define INTMASK_COMMRx                  (1 << INT_COMMRx)
+#define INTMASK_COMMTx                  (1 << INT_COMMTx)
+#define INTMASK_TIMERINT0_1             (1 << INT_TIMERINT0_1)
+#define INTMASK_TIMERINT2_3             (1 << INT_TIMERINT2_3)
+#define INTMASK_GPIOINT0                (1 << INT_GPIOINT0)
+#define INTMASK_GPIOINT1                (1 << INT_GPIOINT1)
+#define INTMASK_GPIOINT2                (1 << INT_GPIOINT2)
+#define INTMASK_GPIOINT3                (1 << INT_GPIOINT3)
+#define INTMASK_RTCINT                  (1 << INT_RTCINT)
+#define INTMASK_SSPINT                  (1 << INT_SSPINT)
+#define INTMASK_UARTINT0                (1 << INT_UARTINT0)
+#define INTMASK_UARTINT1                (1 << INT_UARTINT1)
+#define INTMASK_UARTINT2                (1 << INT_UARTINT2)
+#define INTMASK_SCIINT                  (1 << INT_SCIINT)
+#define INTMASK_CLCDINT                 (1 << INT_CLCDINT)
+#define INTMASK_DMAINT                  (1 << INT_DMAINT)
+#define INTMASK_PWRFAILINT              (1 << INT_PWRFAILINT)
+#define INTMASK_MBXINT                  (1 << INT_MBXINT)
+#define INTMASK_GNDINT                  (1 << INT_GNDINT)
+#define INTMASK_VICSOURCE21             (1 << INT_VICSOURCE21)
+#define INTMASK_VICSOURCE22             (1 << INT_VICSOURCE22)
+#define INTMASK_VICSOURCE23             (1 << INT_VICSOURCE23)
+#define INTMASK_VICSOURCE24             (1 << INT_VICSOURCE24)
+#define INTMASK_VICSOURCE25             (1 << INT_VICSOURCE25)
+#define INTMASK_VICSOURCE26             (1 << INT_VICSOURCE26)
+#define INTMASK_VICSOURCE27             (1 << INT_VICSOURCE27)
+#define INTMASK_VICSOURCE28             (1 << INT_VICSOURCE28)
+#define INTMASK_VICSOURCE29             (1 << INT_VICSOURCE29)
+#define INTMASK_VICSOURCE30             (1 << INT_VICSOURCE30)
+#define INTMASK_VICSOURCE31             (1 << INT_VICSOURCE31)
+
+
+#define VERSATILE_SC_VALID_INT               0x003FFFFF
+
+#define MAXIRQNUM                       31
+#define MAXFIQNUM                       31
+#define MAXSWINUM                       31
+
+/* ------------------------------------------------------------------------
+ *  Interrupts - bit assignment (secondary)
+ * ------------------------------------------------------------------------
+ */
+#define SIC_INT_MMCI0B                  1       /* Multimedia Card 0B */
+#define SIC_INT_MMCI1B                  2       /* Multimedia Card 1B */
+#define SIC_INT_KMI0                    3       /* Keyboard/Mouse port 0 */
+#define SIC_INT_KMI1                    4       /* Keyboard/Mouse port 1 */
+#define SIC_INT_SCI3                    5       /* Smart Card interface */
+#define SIC_INT_UART3                   6       /* UART 3 empty or data available */
+#define SIC_INT_CLCD                    7       /* Character LCD */
+#define SIC_INT_TOUCH                   8       /* Touchscreen */
+#define SIC_INT_KEYPAD                  9       /* Key pressed on display keypad */
+        /* 10:20 - reserved */
+#define SIC_INT_DoC                     21      /* Disk on Chip memory controller */
+#define SIC_INT_MMCI0A                  22      /* MMC 0A */
+#define SIC_INT_MMCI1A                  23      /* MMC 1A */
+#define SIC_INT_AACI                    24      /* Audio Codec */
+#define SIC_INT_ETH                     25      /* Ethernet controller */
+#define SIC_INT_USB                     26      /* USB controller */
+#define SIC_INT_PCI0                    27
+#define SIC_INT_PCI1                    28
+#define SIC_INT_PCI2                    29
+#define SIC_INT_PCI3                    30
+
+
+#define SIC_INTMASK_MMCI0B              (1 << SIC_INT_MMCI0B)
+#define SIC_INTMASK_MMCI1B              (1 << SIC_INT_MMCI1B)
+#define SIC_INTMASK_KMI0                (1 << SIC_INT_KMI0)
+#define SIC_INTMASK_KMI1                (1 << SIC_INT_KMI1)
+#define SIC_INTMASK_SCI3                (1 << SIC_INT_SCI3)
+#define SIC_INTMASK_UART3               (1 << SIC_INT_UART3)
+#define SIC_INTMASK_CLCD                (1 << SIC_INT_CLCD)
+#define SIC_INTMASK_TOUCH               (1 << SIC_INT_TOUCH)
+#define SIC_INTMASK_KEYPAD              (1 << SIC_INT_KEYPAD)
+#define SIC_INTMASK_DoC                 (1 << SIC_INT_DoC)
+#define SIC_INTMASK_MMCI0A              (1 << SIC_INT_MMCI0A)
+#define SIC_INTMASK_MMCI1A              (1 << SIC_INT_MMCI1A)
+#define SIC_INTMASK_AACI                (1 << SIC_INT_AACI)
+#define SIC_INTMASK_ETH                 (1 << SIC_INT_ETH)
+#define SIC_INTMASK_USB                 (1 << SIC_INT_USB)
+#define SIC_INTMASK_PCI0                (1 << SIC_INT_PCI0)
+#define SIC_INTMASK_PCI1                (1 << SIC_INT_PCI1)
+#define SIC_INTMASK_PCI2                (1 << SIC_INT_PCI2)
+#define SIC_INTMASK_PCI3                (1 << SIC_INT_PCI3)
+/* 
+ *  Application Flash
+ * 
+ */
+#define FLASH_BASE                      VERSATILE_FLASH_BASE
+#define FLASH_SIZE                      VERSATILE_FLASH_SIZE
+#define FLASH_END                       (FLASH_BASE + FLASH_SIZE - 1)
+#define FLASH_BLOCK_SIZE                SZ_128K
+
+/* 
+ *  Boot Flash
+ * 
+ */
+#define EPROM_BASE                      VERSATILE_BOOT_ROM_HI
+#define EPROM_SIZE                      VERSATILE_BOOT_ROM_SIZE
+#define EPROM_END                       (EPROM_BASE + EPROM_SIZE - 1)
+
+/* 
+ *  Clean base - dummy
+ * 
+ */
+#define CLEAN_BASE                      EPROM_BASE
+
+/*
+ * System controller bit assignment
+ */
+#define VERSATILE_REFCLK        0
+#define VERSATILE_TIMCLK        1
+
+#define VERSATILE_TIMER1_EnSel  15
+#define VERSATILE_TIMER2_EnSel  17
+#define VERSATILE_TIMER3_EnSel  19
+#define VERSATILE_TIMER4_EnSel  21
+
+
+#define MAX_TIMER                       2
+#define MAX_PERIOD                      699050
+#define TICKS_PER_uSEC                  1
+
+/* 
+ *  These are useconds NOT ticks.  
+ * 
+ */
+#define mSEC_1                          1000
+#define mSEC_5                          (mSEC_1 * 5)
+#define mSEC_10                         (mSEC_1 * 10)
+#define mSEC_25                         (mSEC_1 * 25)
+#define SEC_1                           (mSEC_1 * 1000)
+
+#define VERSATILE_CSR_BASE             0x10000000
+#define VERSATILE_CSR_SIZE             0x10000000
+
+#ifdef CONFIG_MACH_VERSATILE_AB
+/*
+ * IB2 Versatile/AB expansion board definitions
+ */
+#define VERSATILE_IB2_CAMERA_BANK       VERSATILE_IB2_BASE
+#define VERSATILE_IB2_KBD_DATAREG       (VERSATILE_IB2_BASE + 0x01000000)
+
+/* VICINTSOURCE27 */
+#define VERSATILE_IB2_INT_BASE          (VERSATILE_IB2_BASE + 0x02000000)
+#define VERSATILE_IB2_IER               (VERSATILE_IB2_INT_BASE + 0)
+#define VERSATILE_IB2_ISR               (VERSATILE_IB2_INT_BASE + 4)
+
+#define VERSATILE_IB2_CTL_BASE          (VERSATILE_IB2_BASE + 0x03000000)
+#define VERSATILE_IB2_CTRL              (VERSATILE_IB2_CTL_BASE + 0)
+#define VERSATILE_IB2_STAT              (VERSATILE_IB2_CTL_BASE + 4)
+#endif
+
+#endif
+
+/*      END */
diff --git a/arch/arm/mach-versatile/include/mach/system.h b/arch/arm/mach-versatile/include/mach/system.h
new file mode 100644
index 000000000000..91fa559c7cca
--- /dev/null
+++ b/arch/arm/mach-versatile/include/mach/system.h
@@ -0,0 +1,49 @@
+/*
+ *  arch/arm/mach-versatile/include/mach/system.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <mach/hardware.h>
+#include <asm/io.h>
+#include <mach/platform.h>
+
+static inline void arch_idle(void)
+{
+        /*
+         * This should do all the clock switching
+         * and wait for interrupt tricks
+         */
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        u32 val;
+
+        val = __raw_readl(IO_ADDRESS(VERSATILE_SYS_RESETCTL)) & ~0x7;
+        val |= 0x105;
+
+        __raw_writel(0xa05f, IO_ADDRESS(VERSATILE_SYS_LOCK));
+        __raw_writel(val, IO_ADDRESS(VERSATILE_SYS_RESETCTL));
+        __raw_writel(0, IO_ADDRESS(VERSATILE_SYS_LOCK));
+}
+
+#endif
diff --git a/arch/arm/mach-versatile/include/mach/timex.h b/arch/arm/mach-versatile/include/mach/timex.h
new file mode 100644
index 000000000000..426199b1add5
--- /dev/null
+++ b/arch/arm/mach-versatile/include/mach/timex.h
@@ -0,0 +1,23 @@
+/*
+ *  arch/arm/mach-versatile/include/mach/timex.h
+ *
+ *  Versatile architecture timex specifications
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#define CLOCK_TICK_RATE         (50000000 / 16)
diff --git a/arch/arm/mach-versatile/include/mach/uncompress.h b/arch/arm/mach-versatile/include/mach/uncompress.h
new file mode 100644
index 000000000000..3dd0048afb34
--- /dev/null
+++ b/arch/arm/mach-versatile/include/mach/uncompress.h
@@ -0,0 +1,46 @@
+/*
+ *  arch/arm/mach-versatile/include/mach/uncompress.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#define AMBA_UART_DR    (*(volatile unsigned char *)0x101F1000)
+#define AMBA_UART_LCRH  (*(volatile unsigned char *)0x101F102C)
+#define AMBA_UART_CR    (*(volatile unsigned char *)0x101F1030)
+#define AMBA_UART_FR    (*(volatile unsigned char *)0x101F1018)
+
+/*
+ * This does not append a newline
+ */
+static inline void putc(int c)
+{
+        while (AMBA_UART_FR & (1 << 5))
+                barrier();
+
+        AMBA_UART_DR = c;
+}
+
+static inline void flush(void)
+{
+        while (AMBA_UART_FR & (1 << 3))
+                barrier();
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-versatile/include/mach/vmalloc.h b/arch/arm/mach-versatile/include/mach/vmalloc.h
new file mode 100644
index 000000000000..427e3612db5d
--- /dev/null
+++ b/arch/arm/mach-versatile/include/mach/vmalloc.h
@@ -0,0 +1,21 @@
+/*
+ *  arch/arm/mach-versatile/include/mach/vmalloc.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *  Copyright (C) 2000 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#define VMALLOC_END             (PAGE_OFFSET + 0x18000000)
diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c
index 4335c07b8652..36f23f896503 100644
--- a/arch/arm/mach-versatile/pci.c
+++ b/arch/arm/mach-versatile/pci.c
@@ -22,7 +22,7 @@
 #include <linux/spinlock.h>
 #include <linux/init.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/system.h>
diff --git a/arch/arm/mach-versatile/versatile_ab.c b/arch/arm/mach-versatile/versatile_ab.c
index 6e1fe3b450d4..76375c64413a 100644
--- a/arch/arm/mach-versatile/versatile_ab.c
+++ b/arch/arm/mach-versatile/versatile_ab.c
@@ -24,7 +24,7 @@
 #include <linux/sysdev.h>
 #include <linux/amba/bus.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c
index 2eeda4b0107d..1725f019fc85 100644
--- a/arch/arm/mach-versatile/versatile_pb.c
+++ b/arch/arm/mach-versatile/versatile_pb.c
@@ -24,7 +24,7 @@
 #include <linux/sysdev.h>
 #include <linux/amba/bus.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mm/cache-v3.S b/arch/arm/mm/cache-v3.S
index 3e8d8c798562..3b3639eb7ca5 100644
--- a/arch/arm/mm/cache-v3.S
+++ b/arch/arm/mm/cache-v3.S
@@ -9,7 +9,7 @@
  */
 #include <linux/linkage.h>
 #include <linux/init.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/page.h>
 #include "proc-macros.S"
 
diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S
index 8e23c8d69e7a..33926c9fcda6 100644
--- a/arch/arm/mm/cache-v4.S
+++ b/arch/arm/mm/cache-v4.S
@@ -9,7 +9,7 @@
  */
 #include <linux/linkage.h>
 #include <linux/init.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/page.h>
 #include "proc-macros.S"
 
diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S
index d67829f00ee7..51a9b0b273b6 100644
--- a/arch/arm/mm/cache-v4wt.S
+++ b/arch/arm/mm/cache-v4wt.S
@@ -13,7 +13,7 @@
  */
 #include <linux/linkage.h>
 #include <linux/init.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/page.h>
 #include "proc-macros.S"
 
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index d05e2358b824..bbe10576c861 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -18,7 +18,7 @@
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
 #include <asm/elf.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/ptrace.h>
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 56bd3bfa2942..871ba018252e 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -23,7 +23,7 @@
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
 #include <asm/elf.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 6a0adecfe0ed..7bd9e7197f60 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -28,7 +28,7 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/elf.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/pgtable.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/page.h>
diff --git a/arch/arm/oprofile/op_model_mpcore.c b/arch/arm/oprofile/op_model_mpcore.c
index 65e26c17f8a2..92db6e035c65 100644
--- a/arch/arm/oprofile/op_model_mpcore.c
+++ b/arch/arm/oprofile/op_model_mpcore.c
@@ -40,7 +40,7 @@
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/system.h>
 
 #include "op_counter.h"
diff --git a/arch/arm/plat-iop/adma.c b/arch/arm/plat-iop/adma.c
index 53c5e9a52eb1..f72420821619 100644
--- a/arch/arm/plat-iop/adma.c
+++ b/arch/arm/plat-iop/adma.c
@@ -19,7 +19,7 @@
 #include <linux/platform_device.h>
 #include <asm/hardware/iop3xx.h>
 #include <linux/dma-mapping.h>
-#include <asm/arch/adma.h>
+#include <mach/adma.h>
 #include <asm/hardware/iop_adma.h>
 
 #ifdef CONFIG_ARCH_IOP32X
diff --git a/arch/arm/plat-iop/i2c.c b/arch/arm/plat-iop/i2c.c
index b7b8fcb9108c..6dcbcc4ad419 100644
--- a/arch/arm/plat-iop/i2c.c
+++ b/arch/arm/plat-iop/i2c.c
@@ -25,7 +25,7 @@
 #include <asm/setup.h>
 #include <asm/system.h>
 #include <asm/memory.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/hardware/iop3xx.h>
 #include <asm/mach/arch.h>
 
diff --git a/arch/arm/plat-iop/io.c b/arch/arm/plat-iop/io.c
index c30d1885af3d..39dcfb4bdc71 100644
--- a/arch/arm/plat-iop/io.c
+++ b/arch/arm/plat-iop/io.c
@@ -18,7 +18,7 @@
  */
 #include <linux/kernel.h>
 #include <linux/module.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 
 void * __iomem __iop3xx_ioremap(unsigned long cookie, size_t size,
diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c
index e32054fbe524..54708bf9cb15 100644
--- a/arch/arm/plat-iop/pci.c
+++ b/arch/arm/plat-iop/pci.c
@@ -21,7 +21,7 @@
 #include <asm/irq.h>
 #include <asm/signal.h>
 #include <asm/system.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach/pci.h>
 #include <asm/hardware/iop3xx.h>
 
diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c
index da9e82441c53..c53fefb6aac4 100644
--- a/arch/arm/plat-iop/time.c
+++ b/arch/arm/plat-iop/time.c
@@ -18,13 +18,13 @@
 #include <linux/time.h>
 #include <linux/init.h>
 #include <linux/timex.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/uaccess.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
-#include <asm/arch/time.h>
+#include <mach/time.h>
 
 static unsigned long ticks_per_jiffy;
 static unsigned long ticks_per_usec;
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
index 1aa86fd60d71..2f8627218839 100644
--- a/arch/arm/plat-mxc/clock.c
+++ b/arch/arm/plat-mxc/clock.c
@@ -39,7 +39,7 @@
 #include <linux/string.h>
 #include <linux/version.h>
 
-#include <asm/arch/clock.h>
+#include <mach/clock.h>
 
 static LIST_HEAD(clocks);
 static DEFINE_MUTEX(clocks_mutex);
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index 73d304633642..733e0acac916 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -23,7 +23,7 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/gpio.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm-generic/bug.h>
 
 static struct mxc_gpio_port *mxc_gpio_ports;
diff --git a/include/asm-arm/arch-mxc/board-mx27ads.h b/arch/arm/plat-mxc/include/mach/board-mx27ads.h
index 61e66dac90ef..61e66dac90ef 100644
--- a/include/asm-arm/arch-mxc/board-mx27ads.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx27ads.h
diff --git a/include/asm-arm/arch-mxc/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
index 1bc6fb0f9a83..1bc6fb0f9a83 100644
--- a/include/asm-arm/arch-mxc/board-mx31ads.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
diff --git a/include/asm-arm/arch-mxc/board-mx31lite.h b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
index e4e5cf5ad7db..e4e5cf5ad7db 100644
--- a/include/asm-arm/arch-mxc/board-mx31lite.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
diff --git a/include/asm-arm/arch-mxc/board-pcm037.h b/arch/arm/plat-mxc/include/mach/board-pcm037.h
index 82232ba3c8fc..82232ba3c8fc 100644
--- a/include/asm-arm/arch-mxc/board-pcm037.h
+++ b/arch/arm/plat-mxc/include/mach/board-pcm037.h
diff --git a/include/asm-arm/arch-mxc/board-pcm038.h b/arch/arm/plat-mxc/include/mach/board-pcm038.h
index 750c62afd90f..750c62afd90f 100644
--- a/include/asm-arm/arch-mxc/board-pcm038.h
+++ b/arch/arm/plat-mxc/include/mach/board-pcm038.h
diff --git a/include/asm-arm/arch-mxc/clock.h b/arch/arm/plat-mxc/include/mach/clock.h
index 24caa2b7c91d..24caa2b7c91d 100644
--- a/include/asm-arm/arch-mxc/clock.h
+++ b/arch/arm/plat-mxc/include/mach/clock.h
diff --git a/include/asm-arm/arch-mxc/common.h b/arch/arm/plat-mxc/include/mach/common.h
index a6d2e24aab15..a6d2e24aab15 100644
--- a/include/asm-arm/arch-mxc/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
new file mode 100644
index 000000000000..b9907bebba3b
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -0,0 +1,49 @@
+/* arch/arm/mach-imx/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <mach/hardware.h>
+
+#ifdef CONFIG_MACH_MX31ADS
+#include <mach/board-mx31ads.h>
+#endif
+#ifdef CONFIG_MACH_PCM037
+#include <mach/board-pcm037.h>
+#endif
+#ifdef CONFIG_MACH_MX31LITE
+#include <mach/board-mx31lite.h>
+#endif
+#ifdef CONFIG_MACH_MX27ADS
+#include <mach/board-mx27ads.h>
+#endif
+#ifdef CONFIG_MACH_PCM038
+#include <mach/board-pcm038.h>
+#endif
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                ldreq   \rx, =MXC_LL_UART_PADDR @ physical
+                ldrne   \rx, =MXC_LL_UART_VADDR @ virtual
+                .endm
+
+                .macro  senduart,rd,rx
+                str     \rd, [\rx, #0x40]       @ TXDATA
+                .endm
+
+                .macro  waituart,rd,rx
+                .endm
+
+                .macro  busyuart,rd,rx
+1002:           ldr     \rd, [\rx, #0x98]       @ SR2
+                tst     \rd, #1 << 3            @ TXDC
+                beq     1002b                   @ wait until transmit done
+                .endm
diff --git a/include/asm-arm/arch-mxc/dma.h b/arch/arm/plat-mxc/include/mach/dma.h
index c822d569a05e..c822d569a05e 100644
--- a/include/asm-arm/arch-mxc/dma.h
+++ b/arch/arm/plat-mxc/include/mach/dma.h
diff --git a/include/asm-arm/arch-mxc/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
index b542433afb1b..b542433afb1b 100644
--- a/include/asm-arm/arch-mxc/entry-macro.S
+++ b/arch/arm/plat-mxc/include/mach/entry-macro.S
diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h
new file mode 100644
index 000000000000..65eedc0d196f
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/gpio.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_MXC_GPIO_H__
+#define __ASM_ARCH_MXC_GPIO_H__
+
+#include <mach/hardware.h>
+#include <asm-generic/gpio.h>
+
+/* use gpiolib dispatchers */
+#define gpio_get_value          __gpio_get_value
+#define gpio_set_value          __gpio_set_value
+#define gpio_cansleep           __gpio_cansleep
+
+#define gpio_to_irq(gpio)       (MXC_MAX_INT_LINES + (gpio))
+#define irq_to_gpio(irq)        ((irq) - MXC_MAX_INT_LINES)
+
+struct mxc_gpio_port {
+        void __iomem *base;
+        int irq;
+        int virtual_irq_start;
+        struct gpio_chip chip;
+};
+
+int mxc_gpio_init(struct mxc_gpio_port*, int);
+
+#endif
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
new file mode 100644
index 000000000000..3caadeeda701
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_MXC_HARDWARE_H__
+#define __ASM_ARCH_MXC_HARDWARE_H__
+
+#include <asm/sizes.h>
+
+#ifdef CONFIG_ARCH_MX3
+# include <mach/mx31.h>
+#endif
+
+#ifdef CONFIG_ARCH_MX2
+# ifdef CONFIG_MACH_MX27
+#  include <mach/mx27.h>
+# endif
+#endif
+
+#include <mach/mxc.h>
+
+#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/include/asm-arm/arch-mxc/iim.h b/arch/arm/plat-mxc/include/mach/iim.h
index 315bffadafda..315bffadafda 100644
--- a/include/asm-arm/arch-mxc/iim.h
+++ b/arch/arm/plat-mxc/include/mach/iim.h
diff --git a/include/asm-arm/arch-mxc/imx-uart.h b/arch/arm/plat-mxc/include/mach/imx-uart.h
index 83fb72c4048a..83fb72c4048a 100644
--- a/include/asm-arm/arch-mxc/imx-uart.h
+++ b/arch/arm/plat-mxc/include/mach/imx-uart.h
diff --git a/include/asm-arm/arch-mxc/io.h b/arch/arm/plat-mxc/include/mach/io.h
index 65b6810124c1..65b6810124c1 100644
--- a/include/asm-arm/arch-mxc/io.h
+++ b/arch/arm/plat-mxc/include/mach/io.h
diff --git a/include/asm-arm/arch-mxc/iomux-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h
index 076d37b38eb2..076d37b38eb2 100644
--- a/include/asm-arm/arch-mxc/iomux-mx1-mx2.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h
diff --git a/include/asm-arm/arch-mxc/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index 7509e7692f08..7509e7692f08 100644
--- a/include/asm-arm/arch-mxc/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
new file mode 100644
index 000000000000..228c4f68ccdf
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -0,0 +1,16 @@
+/*
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_IRQS_H__
+#define __ASM_ARCH_MXC_IRQS_H__
+
+#include <mach/hardware.h>
+
+#endif /* __ASM_ARCH_MXC_IRQS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
new file mode 100644
index 000000000000..d7a8d3ebed57
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_MEMORY_H__
+#define __ASM_ARCH_MXC_MEMORY_H__
+
+#include <mach/hardware.h>
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * This macro is used to translate the virtual address to an address
+ * suitable to be passed to set_dma_addr()
+ */
+#define __virt_to_bus(a)        __virt_to_phys(a)
+
+/*
+ * Used to convert an address for DMA operations to an address that the
+ * kernel can use.
+ */
+#define __bus_to_virt(a)        __phys_to_virt(a)
+
+#endif /* __ASM_ARCH_MXC_MEMORY_H__ */
diff --git a/include/asm-arm/arch-mxc/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index 212ecc246626..212ecc246626 100644
--- a/include/asm-arm/arch-mxc/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
diff --git a/include/asm-arm/arch-mxc/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index a7373e4a56cb..a7373e4a56cb 100644
--- a/include/asm-arm/arch-mxc/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
diff --git a/include/asm-arm/arch-mxc/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 332eda4dbd3b..332eda4dbd3b 100644
--- a/include/asm-arm/arch-mxc/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
diff --git a/arch/arm/plat-mxc/include/mach/mxc_timer.h b/arch/arm/plat-mxc/include/mach/mxc_timer.h
new file mode 100644
index 000000000000..130aebfbe168
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mxc_timer.h
@@ -0,0 +1,158 @@
+/*
+ * mxc_timer.h
+ *
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * Platform independent (i.MX1, i.MX2, i.MX3) definition for timer handling.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __PLAT_MXC_TIMER_H
+#define __PLAT_MXC_TIMER_H
+
+#include <linux/clk.h>
+#include <mach/hardware.h>
+
+#ifdef CONFIG_ARCH_IMX
+#define TIMER_BASE              IO_ADDRESS(TIM1_BASE_ADDR)
+#define TIMER_INTERRUPT         TIM1_INT
+
+#define TCTL_VAL                TCTL_CLK_PCLK1
+#define TCTL_IRQEN              (1<<4)
+#define TCTL_FRR                (1<<8)
+#define TCTL_CLK_PCLK1          (1<<1)
+#define TCTL_CLK_PCLK1_4        (2<<1)
+#define TCTL_CLK_TIN            (3<<1)
+#define TCTL_CLK_32             (4<<1)
+
+#define MXC_TCTL   0x00
+#define MXC_TPRER  0x04
+#define MXC_TCMP   0x08
+#define MXC_TCR    0x0c
+#define MXC_TCN    0x10
+#define MXC_TSTAT  0x14
+#define TSTAT_CAPT              (1<<1)
+#define TSTAT_COMP              (1<<0)
+
+static inline void gpt_irq_disable(void)
+{
+        unsigned int tmp;
+
+        tmp = __raw_readl(TIMER_BASE + MXC_TCTL);
+        __raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL);
+}
+
+static inline void gpt_irq_enable(void)
+{
+        __raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN,
+                                TIMER_BASE + MXC_TCTL);
+}
+
+static void gpt_irq_acknowledge(void)
+{
+        __raw_writel(0, TIMER_BASE + MXC_TSTAT);
+}
+#endif /* CONFIG_ARCH_IMX */
+
+#ifdef CONFIG_ARCH_MX2
+#define TIMER_BASE              IO_ADDRESS(GPT1_BASE_ADDR)
+#define TIMER_INTERRUPT         MXC_INT_GPT1
+
+#define MXC_TCTL   0x00
+#define TCTL_VAL                TCTL_CLK_PCLK1
+#define TCTL_CLK_PCLK1          (1<<1)
+#define TCTL_CLK_PCLK1_4        (2<<1)
+#define TCTL_IRQEN              (1<<4)
+#define TCTL_FRR                (1<<8)
+#define MXC_TPRER  0x04
+#define MXC_TCMP   0x08
+#define MXC_TCR    0x0c
+#define MXC_TCN    0x10
+#define MXC_TSTAT  0x14
+#define TSTAT_CAPT              (1<<1)
+#define TSTAT_COMP              (1<<0)
+
+static inline void gpt_irq_disable(void)
+{
+        unsigned int tmp;
+
+        tmp = __raw_readl(TIMER_BASE + MXC_TCTL);
+        __raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL);
+}
+
+static inline void gpt_irq_enable(void)
+{
+        __raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN,
+                                TIMER_BASE + MXC_TCTL);
+}
+
+static void gpt_irq_acknowledge(void)
+{
+        __raw_writel(TSTAT_CAPT | TSTAT_COMP, TIMER_BASE + MXC_TSTAT);
+}
+#endif /* CONFIG_ARCH_MX2 */
+
+#ifdef CONFIG_ARCH_MX3
+#define TIMER_BASE              IO_ADDRESS(GPT1_BASE_ADDR)
+#define TIMER_INTERRUPT         MXC_INT_GPT
+
+#define MXC_TCTL   0x00
+#define TCTL_VAL                (TCTL_CLK_IPG | TCTL_WAITEN)
+#define TCTL_CLK_IPG            (1<<6)
+#define TCTL_FRR                (1<<9)
+#define TCTL_WAITEN             (1<<3)
+
+#define MXC_TPRER  0x04
+#define MXC_TSTAT  0x08
+#define TSTAT_OF1               (1<<0)
+#define TSTAT_OF2               (1<<1)
+#define TSTAT_OF3               (1<<2)
+#define TSTAT_IF1               (1<<3)
+#define TSTAT_IF2               (1<<4)
+#define TSTAT_ROV               (1<<5)
+#define MXC_IR     0x0c
+#define MXC_TCMP   0x10
+#define MXC_TCMP2  0x14
+#define MXC_TCMP3  0x18
+#define MXC_TCR    0x1c
+#define MXC_TCN    0x24
+
+static inline void gpt_irq_disable(void)
+{
+        __raw_writel(0, TIMER_BASE + MXC_IR);
+}
+
+static inline void gpt_irq_enable(void)
+{
+        __raw_writel(1<<0, TIMER_BASE + MXC_IR);
+}
+
+static inline void gpt_irq_acknowledge(void)
+{
+        __raw_writel(TSTAT_OF1, TIMER_BASE + MXC_TSTAT);
+}
+#endif /* CONFIG_ARCH_MX3 */
+
+#define TCTL_SWR                (1<<15)
+#define TCTL_CC                 (1<<10)
+#define TCTL_OM                 (1<<9)
+#define TCTL_CAP_RIS            (1<<6)
+#define TCTL_CAP_FAL            (2<<6)
+#define TCTL_CAP_RIS_FAL        (3<<6)
+#define TCTL_CAP_ENA            (1<<5)
+#define TCTL_TEN                (1<<0)
+
+#endif
diff --git a/include/asm-arm/arch-mxc/system.h b/arch/arm/plat-mxc/include/mach/system.h
index bbfc37465fc5..bbfc37465fc5 100644
--- a/include/asm-arm/arch-mxc/system.h
+++ b/arch/arm/plat-mxc/include/mach/system.h
diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h
new file mode 100644
index 000000000000..0b0af0253e91
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/timex.h
@@ -0,0 +1,25 @@
+/*
+ *  Copyright (C) 1999 ARM Limited
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_MXC_TIMEX_H__
+#define __ASM_ARCH_MXC_TIMEX_H__
+
+#include <mach/hardware.h>      /* for CLOCK_TICK_RATE */
+
+#endif                          /* __ASM_ARCH_MXC_TIMEX_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
new file mode 100644
index 000000000000..de6fe0365982
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -0,0 +1,78 @@
+/*
+ *  arch/arm/plat-mxc/include/mach/uncompress.h
+ *
+ *
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) Shane Nay (shane@minirl.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__
+#define __ASM_ARCH_MXC_UNCOMPRESS_H__
+
+#define __MXC_BOOT_UNCOMPRESS
+
+#include <mach/hardware.h>
+
+#define UART(x) (*(volatile unsigned long *)(serial_port + (x)))
+
+#define USR2 0x98
+#define USR2_TXFE (1<<14)
+#define TXR  0x40
+#define UCR1 0x80
+#define UCR1_UARTEN 1
+
+/*
+ * The following code assumes the serial port has already been
+ * initialized by the bootloader.  We search for the first enabled
+ * port in the most probable order.  If you didn't setup a port in
+ * your bootloader then nothing will appear (which might be desired).
+ *
+ * This does not append a newline
+ */
+
+static void putc(int ch)
+{
+        static unsigned long serial_port = 0;
+
+        if (unlikely(serial_port == 0)) {
+                do {
+                        serial_port = UART1_BASE_ADDR;
+                        if (UART(UCR1) & UCR1_UARTEN)
+                                break;
+                        serial_port = UART2_BASE_ADDR;
+                        if (UART(UCR1) & UCR1_UARTEN)
+                                break;
+                        return;
+                } while (0);
+        }
+
+        while (!(UART(USR2) & USR2_TXFE))
+                barrier();
+
+        UART(TXR) = ch;
+}
+
+#define flush() do { } while (0)
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+
+#define arch_decomp_wdog()
+
+#endif                          /* __ASM_ARCH_MXC_UNCOMPRESS_H__ */
diff --git a/include/asm-arm/arch-mxc/vmalloc.h b/arch/arm/plat-mxc/include/mach/vmalloc.h
index 62d97623412f..62d97623412f 100644
--- a/include/asm-arm/arch-mxc/vmalloc.h
+++ b/arch/arm/plat-mxc/include/mach/vmalloc.h
diff --git a/arch/arm/plat-mxc/iomux-mx1-mx2.c b/arch/arm/plat-mxc/iomux-mx1-mx2.c
index 1204456d61a9..d97387aa9a42 100644
--- a/arch/arm/plat-mxc/iomux-mx1-mx2.c
+++ b/arch/arm/plat-mxc/iomux-mx1-mx2.c
@@ -30,9 +30,9 @@
 #include <linux/string.h>
 #include <linux/gpio.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach/map.h>
-#include <asm/arch/iomux-mx1-mx2.h>
+#include <mach/iomux-mx1-mx2.h>
 
 void mxc_gpio_mode(int gpio_mode)
 {
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c
index 1fbe01da6925..1053b666c676 100644
--- a/arch/arm/plat-mxc/irq.c
+++ b/arch/arm/plat-mxc/irq.c
@@ -19,7 +19,7 @@
 
 #include <linux/irq.h>
 #include <asm/io.h>
-#include <asm/arch/common.h>
+#include <mach/common.h>
 
 #define AVIC_BASE               IO_ADDRESS(AVIC_BASE_ADDR)
 #define AVIC_INTCNTL            (AVIC_BASE + 0x00)      /* int control reg */
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index be9680a88b02..fd28f5194f71 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -26,10 +26,10 @@
 #include <linux/clockchips.h>
 #include <linux/clk.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach/time.h>
-#include <asm/arch/common.h>
-#include <asm/arch/mxc_timer.h>
+#include <mach/common.h>
+#include <mach/mxc_timer.h>
 
 static struct clock_event_device clockevent_mxc;
 static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index c2e741de0203..23a070599993 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -26,7 +26,7 @@
 
 #include <asm/io.h>
 
-#include <asm/arch/clock.h>
+#include <mach/clock.h>
 
 static LIST_HEAD(clocks);
 static DEFINE_MUTEX(clocks_mutex);
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 6a955296e8c1..f4dff423ae7c 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -19,20 +19,20 @@
 #include <linux/serial_reg.h>
 #include <linux/clk.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/system.h>
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
 #include <asm/io.h>
 #include <asm/setup.h>
 
-#include <asm/arch/common.h>
-#include <asm/arch/board.h>
-#include <asm/arch/control.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/fpga.h>
+#include <mach/common.h>
+#include <mach/board.h>
+#include <mach/control.h>
+#include <mach/mux.h>
+#include <mach/fpga.h>
 
-#include <asm/arch/clock.h>
+#include <mach/clock.h>
 
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
 # include "../mach-omap2/sdrc.h"
diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c
index 3c8ef1ac5f3d..ae1de308aaad 100644
--- a/arch/arm/plat-omap/cpu-omap.c
+++ b/arch/arm/plat-omap/cpu-omap.c
@@ -21,7 +21,7 @@
 #include <linux/err.h>
 #include <linux/clk.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/system.h>
 
diff --git a/arch/arm/plat-omap/debug-devices.c b/arch/arm/plat-omap/debug-devices.c
index 7228ef8534b7..5b73bb274452 100644
--- a/arch/arm/plat-omap/debug-devices.c
+++ b/arch/arm/plat-omap/debug-devices.c
@@ -13,11 +13,11 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/gpio.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
 
 
 /* Many OMAP development platforms reuse the same "debug board"; these
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
index a47695c3171a..9422dee7de84 100644
--- a/arch/arm/plat-omap/debug-leds.c
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -13,13 +13,13 @@
 #include <linux/leds.h>
 
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/system.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/fpga.h>
-#include <asm/arch/gpio.h>
+#include <mach/fpga.h>
+#include <mach/gpio.h>
 
 
 /* Many OMAP development platforms reuse the same "debug board"; these
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 9b4240b9d65f..187e3d8bfdfe 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -14,17 +14,17 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
 
-#include <asm/arch/tc.h>
-#include <asm/arch/board.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/menelaus.h>
-#include <asm/arch/mcbsp.h>
+#include <mach/tc.h>
+#include <mach/board.h>
+#include <mach/mux.h>
+#include <mach/gpio.h>
+#include <mach/menelaus.h>
+#include <mach/mcbsp.h>
 
 #if     defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
 
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 69450d61cf4f..a63b644ad305 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -28,10 +28,10 @@
 #include <linux/io.h>
 
 #include <asm/system.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/dma.h>
 
-#include <asm/arch/tc.h>
+#include <mach/tc.h>
 
 #undef DEBUG
 
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 30b6f2c9cb33..743a4abcd85d 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -32,10 +32,10 @@
 #include <linux/list.h>
 #include <linux/clk.h>
 #include <linux/delay.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/dmtimer.h>
+#include <mach/hardware.h>
+#include <mach/dmtimer.h>
 #include <asm/io.h>
-#include <asm/arch/irqs.h>
+#include <mach/irqs.h>
 
 /* register offsets */
 #define _OMAP_TIMER_ID_OFFSET           0x00
diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
index b0b3c5419b0a..17a92a31e746 100644
--- a/arch/arm/plat-omap/fb.c
+++ b/arch/arm/plat-omap/fb.c
@@ -28,13 +28,13 @@
 #include <linux/platform_device.h>
 #include <linux/bootmem.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/mach/map.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/sram.h>
-#include <asm/arch/omapfb.h>
+#include <mach/board.h>
+#include <mach/sram.h>
+#include <mach/omapfb.h>
 
 #if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE)
 
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 7112b5db4a36..3e76ee2bc731 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -18,10 +18,10 @@
 #include <linux/err.h>
 #include <linux/clk.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/arch/irqs.h>
-#include <asm/arch/gpio.h>
+#include <mach/irqs.h>
+#include <mach/gpio.h>
 #include <asm/mach/irq.h>
 
 #include <asm/io.h>
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index 647ed5971c60..0e6d147ab6f8 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -26,7 +26,7 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/i2c.h>
-#include <asm/arch/mux.h>
+#include <mach/mux.h>
 
 #define OMAP_I2C_SIZE           0x3f
 #define OMAP1_I2C_BASE          0xfffb3800
diff --git a/arch/arm/plat-omap/include/mach/aic23.h b/arch/arm/plat-omap/include/mach/aic23.h
new file mode 100644
index 000000000000..5ccedac77526
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/aic23.h
@@ -0,0 +1,116 @@
+/*
+ * arch/arm/plat-omap/include/mach/aic23.h
+ *
+ * Hardware definitions for TI TLV320AIC23 audio codec
+ *
+ * Copyright (C) 2002 RidgeRun, Inc.
+ * Author: Steve Johnson
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_AIC23_H
+#define __ASM_ARCH_AIC23_H
+
+// Codec TLV320AIC23
+#define LEFT_LINE_VOLUME_ADDR           0x00
+#define RIGHT_LINE_VOLUME_ADDR          0x01
+#define LEFT_CHANNEL_VOLUME_ADDR        0x02
+#define RIGHT_CHANNEL_VOLUME_ADDR       0x03
+#define ANALOG_AUDIO_CONTROL_ADDR       0x04
+#define DIGITAL_AUDIO_CONTROL_ADDR      0x05
+#define POWER_DOWN_CONTROL_ADDR         0x06
+#define DIGITAL_AUDIO_FORMAT_ADDR       0x07
+#define SAMPLE_RATE_CONTROL_ADDR        0x08
+#define DIGITAL_INTERFACE_ACT_ADDR      0x09
+#define RESET_CONTROL_ADDR              0x0F
+
+// Left (right) line input volume control register
+#define LRS_ENABLED                     0x0100
+#define LIM_MUTED                       0x0080
+#define LIV_DEFAULT                     0x0017
+#define LIV_MAX                         0x001f
+#define LIV_MIN                         0x0000
+
+// Left (right) channel headphone volume control register
+#define LZC_ON                          0x0080
+#define LHV_DEFAULT                     0x0079
+#define LHV_MAX                         0x007f
+#define LHV_MIN                         0x0000
+
+// Analog audio path control register
+#define STA_REG(x)                      ((x)<<6)
+#define STE_ENABLED                     0x0020
+#define DAC_SELECTED                    0x0010
+#define BYPASS_ON                       0x0008
+#define INSEL_MIC                       0x0004
+#define MICM_MUTED                      0x0002
+#define MICB_20DB                       0x0001
+
+// Digital audio path control register
+#define DACM_MUTE                       0x0008
+#define DEEMP_32K                       0x0002
+#define DEEMP_44K                       0x0004
+#define DEEMP_48K                       0x0006
+#define ADCHP_ON                        0x0001
+
+// Power control down register
+#define DEVICE_POWER_OFF                0x0080
+#define CLK_OFF                         0x0040
+#define OSC_OFF                         0x0020
+#define OUT_OFF                         0x0010
+#define DAC_OFF                         0x0008
+#define ADC_OFF                         0x0004
+#define MIC_OFF                         0x0002
+#define LINE_OFF                        0x0001
+
+// Digital audio interface register
+#define MS_MASTER                       0x0040
+#define LRSWAP_ON                       0x0020
+#define LRP_ON                          0x0010
+#define IWL_16                          0x0000
+#define IWL_20                          0x0004
+#define IWL_24                          0x0008
+#define IWL_32                          0x000C
+#define FOR_I2S                         0x0002
+#define FOR_DSP                         0x0003
+
+// Sample rate control register
+#define CLKOUT_HALF                     0x0080
+#define CLKIN_HALF                      0x0040
+#define BOSR_384fs                      0x0002 // BOSR_272fs when in USB mode
+#define USB_CLK_ON                      0x0001
+#define SR_MASK                         0xf
+#define CLKOUT_SHIFT                    7
+#define CLKIN_SHIFT                     6
+#define SR_SHIFT                        2
+#define BOSR_SHIFT                      1
+
+// Digital interface register
+#define ACT_ON                          0x0001
+
+#define TLV320AIC23ID1                  (0x1a)  // cs low
+#define TLV320AIC23ID2                  (0x1b)  // cs high
+
+void aic23_power_up(void);
+void aic23_power_down(void);
+
+#endif /* __ASM_ARCH_AIC23_H */
diff --git a/include/asm-arm/arch-omap/blizzard.h b/arch/arm/plat-omap/include/mach/blizzard.h
index 8d160f171372..8d160f171372 100644
--- a/include/asm-arm/arch-omap/blizzard.h
+++ b/arch/arm/plat-omap/include/mach/blizzard.h
diff --git a/arch/arm/plat-omap/include/mach/board-2430sdp.h b/arch/arm/plat-omap/include/mach/board-2430sdp.h
new file mode 100644
index 000000000000..cf1dc0223949
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/board-2430sdp.h
@@ -0,0 +1,39 @@
+/*
+ * arch/arm/plat-omap/include/mach/board-2430sdp.h
+ *
+ * Hardware definitions for TI OMAP2430 SDP board.
+ *
+ * Based on board-h4.h by Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_OMAP_2430SDP_H
+#define __ASM_ARCH_OMAP_2430SDP_H
+
+/* Placeholder for 2430SDP specific defines */
+#define OMAP24XX_ETHR_START              0x08000300
+#define OMAP24XX_ETHR_GPIO_IRQ          149
+#define SDP2430_CS0_BASE                0x04000000
+
+#define TWL4030_IRQNUM                  INT_24XX_SYS_NIRQ
+
+#endif /* __ASM_ARCH_OMAP_2430SDP_H */
diff --git a/arch/arm/plat-omap/include/mach/board-ams-delta.h b/arch/arm/plat-omap/include/mach/board-ams-delta.h
new file mode 100644
index 000000000000..51b102dc906b
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/board-ams-delta.h
@@ -0,0 +1,76 @@
+/*
+ * arch/arm/plat-omap/include/mach/board-ams-delta.h
+ *
+ * Copyright (C) 2006 Jonathan McDowell <noodles@earth.li>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ASM_ARCH_OMAP_AMS_DELTA_H
+#define __ASM_ARCH_OMAP_AMS_DELTA_H
+
+#if defined (CONFIG_MACH_AMS_DELTA)
+
+#define AMS_DELTA_LATCH1_PHYS           0x01000000
+#define AMS_DELTA_LATCH1_VIRT           0xEA000000
+#define AMS_DELTA_MODEM_PHYS            0x04000000
+#define AMS_DELTA_MODEM_VIRT            0xEB000000
+#define AMS_DELTA_LATCH2_PHYS           0x08000000
+#define AMS_DELTA_LATCH2_VIRT           0xEC000000
+
+#define AMS_DELTA_LATCH1_LED_CAMERA     0x01
+#define AMS_DELTA_LATCH1_LED_ADVERT     0x02
+#define AMS_DELTA_LATCH1_LED_EMAIL      0x04
+#define AMS_DELTA_LATCH1_LED_HANDSFREE  0x08
+#define AMS_DELTA_LATCH1_LED_VOICEMAIL  0x10
+#define AMS_DELTA_LATCH1_LED_VOICE      0x20
+
+#define AMS_DELTA_LATCH2_LCD_VBLEN      0x0001
+#define AMS_DELTA_LATCH2_LCD_NDISP      0x0002
+#define AMS_DELTA_LATCH2_NAND_NCE       0x0004
+#define AMS_DELTA_LATCH2_NAND_NRE       0x0008
+#define AMS_DELTA_LATCH2_NAND_NWP       0x0010
+#define AMS_DELTA_LATCH2_NAND_NWE       0x0020
+#define AMS_DELTA_LATCH2_NAND_ALE       0x0040
+#define AMS_DELTA_LATCH2_NAND_CLE       0x0080
+#define AMD_DELTA_LATCH2_KEYBRD_PWR     0x0100
+#define AMD_DELTA_LATCH2_KEYBRD_DATA    0x0200
+#define AMD_DELTA_LATCH2_SCARD_RSTIN    0x0400
+#define AMD_DELTA_LATCH2_SCARD_CMDVCC   0x0800
+#define AMS_DELTA_LATCH2_MODEM_NRESET   0x1000
+#define AMS_DELTA_LATCH2_MODEM_CODEC    0x2000
+
+#define AMS_DELTA_GPIO_PIN_KEYBRD_DATA  0
+#define AMS_DELTA_GPIO_PIN_KEYBRD_CLK   1
+#define AMS_DELTA_GPIO_PIN_MODEM_IRQ    2
+#define AMS_DELTA_GPIO_PIN_HOOK_SWITCH  4
+#define AMS_DELTA_GPIO_PIN_SCARD_NOFF   6
+#define AMS_DELTA_GPIO_PIN_SCARD_IO     7
+#define AMS_DELTA_GPIO_PIN_CONFIG       11
+#define AMS_DELTA_GPIO_PIN_NAND_RB      12
+
+#ifndef __ASSEMBLY__
+void ams_delta_latch1_write(u8 mask, u8 value);
+void ams_delta_latch2_write(u16 mask, u16 value);
+#endif
+
+#endif /* CONFIG_MACH_AMS_DELTA */
+
+#endif /* __ASM_ARCH_OMAP_AMS_DELTA_H */
diff --git a/arch/arm/plat-omap/include/mach/board-apollon.h b/arch/arm/plat-omap/include/mach/board-apollon.h
new file mode 100644
index 000000000000..d6f2a8e963d5
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/board-apollon.h
@@ -0,0 +1,38 @@
+/*
+ * arch/arm/plat-omap/include/mach/board-apollon.h
+ *
+ * Hardware definitions for Samsung OMAP24XX Apollon board.
+ *
+ * Initial creation by Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_OMAP_APOLLON_H
+#define __ASM_ARCH_OMAP_APOLLON_H
+
+extern void apollon_mmc_init(void);
+
+/* Placeholder for APOLLON specific defines */
+#define APOLLON_ETHR_GPIO_IRQ           74
+
+#endif /*  __ASM_ARCH_OMAP_APOLLON_H */
+
diff --git a/arch/arm/plat-omap/include/mach/board-fsample.h b/arch/arm/plat-omap/include/mach/board-fsample.h
new file mode 100644
index 000000000000..cb3c5ae12776
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/board-fsample.h
@@ -0,0 +1,51 @@
+/*
+ * arch/arm/plat-omap/include/mach/board-fsample.h
+ *
+ * Board-specific goodies for TI F-Sample.
+ *
+ * Copyright (C) 2006 Google, Inc.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_OMAP_FSAMPLE_H
+#define __ASM_ARCH_OMAP_FSAMPLE_H
+
+/* fsample is pretty close to p2-sample */
+#include <mach/board-perseus2.h>
+
+#define fsample_cpld_read(reg) __raw_readb(reg)
+#define fsample_cpld_write(val, reg) __raw_writeb(val, reg)
+
+#define FSAMPLE_CPLD_BASE    0xE8100000
+#define FSAMPLE_CPLD_SIZE    SZ_4K
+#define FSAMPLE_CPLD_START   0x05080000
+
+#define FSAMPLE_CPLD_REG_A   (FSAMPLE_CPLD_BASE + 0x00)
+#define FSAMPLE_CPLD_SWITCH  (FSAMPLE_CPLD_BASE + 0x02)
+#define FSAMPLE_CPLD_UART    (FSAMPLE_CPLD_BASE + 0x02)
+#define FSAMPLE_CPLD_REG_B   (FSAMPLE_CPLD_BASE + 0x04)
+#define FSAMPLE_CPLD_VERSION (FSAMPLE_CPLD_BASE + 0x06)
+#define FSAMPLE_CPLD_SET_CLR (FSAMPLE_CPLD_BASE + 0x06)
+
+#define FSAMPLE_CPLD_BIT_BT_RESET         0
+#define FSAMPLE_CPLD_BIT_LCD_RESET        1
+#define FSAMPLE_CPLD_BIT_CAM_PWDN         2
+#define FSAMPLE_CPLD_BIT_CHARGER_ENABLE   3
+#define FSAMPLE_CPLD_BIT_SD_MMC_EN        4
+#define FSAMPLE_CPLD_BIT_aGPS_PWREN       5
+#define FSAMPLE_CPLD_BIT_BACKLIGHT        6
+#define FSAMPLE_CPLD_BIT_aGPS_EN_RESET    7
+#define FSAMPLE_CPLD_BIT_aGPS_SLEEPx_N    8
+#define FSAMPLE_CPLD_BIT_OTG_RESET        9
+
+#define fsample_cpld_set(bit) \
+    fsample_cpld_write((((bit) & 15) << 4) | 0x0f, FSAMPLE_CPLD_SET_CLR)
+
+#define fsample_cpld_clear(bit) \
+    fsample_cpld_write(0xf0 | ((bit) & 15), FSAMPLE_CPLD_SET_CLR)
+
+#endif
diff --git a/arch/arm/plat-omap/include/mach/board-h2.h b/arch/arm/plat-omap/include/mach/board-h2.h
new file mode 100644
index 000000000000..2a050e9be65f
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/board-h2.h
@@ -0,0 +1,41 @@
+/*
+ * arch/arm/plat-omap/include/mach/board-h2.h
+ *
+ * Hardware definitions for TI OMAP1610 H2 board.
+ *
+ * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_OMAP_H2_H
+#define __ASM_ARCH_OMAP_H2_H
+
+/* Placeholder for H2 specific defines */
+
+/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
+#define OMAP1610_ETHR_START             0x04000300
+
+extern void h2_mmc_init(void);
+extern void h2_mmc_slot_cover_handler(void *arg, int state);
+
+#endif /*  __ASM_ARCH_OMAP_H2_H */
+
diff --git a/arch/arm/plat-omap/include/mach/board-h3.h b/arch/arm/plat-omap/include/mach/board-h3.h
new file mode 100644
index 000000000000..14909dc7858a
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/board-h3.h
@@ -0,0 +1,36 @@
+/*
+ * arch/arm/plat-omap/include/mach/board-h3.h
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Copyright (C) 2004 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ASM_ARCH_OMAP_H3_H
+#define __ASM_ARCH_OMAP_H3_H
+
+/* In OMAP1710 H3 the Ethernet is directly connected to CS1 */
+#define OMAP1710_ETHR_START             0x04000300
+
+extern void h3_mmc_init(void);
+extern void h3_mmc_slot_cover_handler(void *arg, int state);
+
+#endif /*  __ASM_ARCH_OMAP_H3_H */
diff --git a/arch/arm/plat-omap/include/mach/board-h4.h b/arch/arm/plat-omap/include/mach/board-h4.h
new file mode 100644
index 000000000000..1470cd3e519b
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/board-h4.h
@@ -0,0 +1,35 @@
+/*
+ * arch/arm/plat-omap/include/mach/board-h4.h
+ *
+ * Hardware definitions for TI OMAP1610 H4 board.
+ *
+ * Initial creation by Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_OMAP_H4_H
+#define __ASM_ARCH_OMAP_H4_H
+
+/* Placeholder for H4 specific defines */
+#define OMAP24XX_ETHR_GPIO_IRQ          92
+#endif /*  __ASM_ARCH_OMAP_H4_H */
+
diff --git a/arch/arm/plat-omap/include/mach/board-innovator.h b/arch/arm/plat-omap/include/mach/board-innovator.h
new file mode 100644
index 000000000000..5ae3e79b9f9c
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/board-innovator.h
@@ -0,0 +1,52 @@
+/*
+ * arch/arm/plat-omap/include/mach/board-innovator.h
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ASM_ARCH_OMAP_INNOVATOR_H
+#define __ASM_ARCH_OMAP_INNOVATOR_H
+
+#if defined (CONFIG_ARCH_OMAP15XX)
+
+#ifndef OMAP_SDRAM_DEVICE
+#define OMAP_SDRAM_DEVICE                       D256M_1X16_4B
+#endif
+
+#define OMAP1510P1_IMIF_PRI_VALUE               0x00
+#define OMAP1510P1_EMIFS_PRI_VALUE              0x00
+#define OMAP1510P1_EMIFF_PRI_VALUE              0x00
+
+#ifndef __ASSEMBLY__
+void fpga_write(unsigned char val, int reg);
+unsigned char fpga_read(int reg);
+#endif
+
+#endif /* CONFIG_ARCH_OMAP15XX */
+
+#if defined (CONFIG_ARCH_OMAP16XX)
+
+/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
+#define INNOVATOR1610_ETHR_START        0x04000300
+
+#endif /* CONFIG_ARCH_OMAP1610 */
+#endif /* __ASM_ARCH_OMAP_INNOVATOR_H */
diff --git a/arch/arm/plat-omap/include/mach/board-nokia.h b/arch/arm/plat-omap/include/mach/board-nokia.h
new file mode 100644
index 000000000000..2abbe001af8c
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/board-nokia.h
@@ -0,0 +1,54 @@
+/*
+ *  arch/arm/plat-omap/include/mach/board-nokia.h
+ *
+ *  Information structures for Nokia-specific board config data
+ *
+ *  Copyright (C) 2005  Nokia Corporation
+ */
+
+#ifndef _OMAP_BOARD_NOKIA_H
+#define _OMAP_BOARD_NOKIA_H
+
+#include <linux/types.h>
+
+#define OMAP_TAG_NOKIA_BT       0x4e01
+#define OMAP_TAG_WLAN_CX3110X   0x4e02
+#define OMAP_TAG_CBUS           0x4e03
+#define OMAP_TAG_EM_ASIC_BB5    0x4e04
+
+
+#define BT_CHIP_CSR             1
+#define BT_CHIP_TI              2
+
+#define BT_SYSCLK_12            1
+#define BT_SYSCLK_38_4          2
+
+struct omap_bluetooth_config {
+        u8    chip_type;
+        u8    bt_wakeup_gpio;
+        u8    host_wakeup_gpio;
+        u8    reset_gpio;
+        u8    bt_uart;
+        u8    bd_addr[6];
+        u8    bt_sysclk;
+};
+
+struct omap_wlan_cx3110x_config {
+        u8  chip_type;
+        s16 power_gpio;
+        s16 irq_gpio;
+        s16 spi_cs_gpio;
+};
+
+struct omap_cbus_config {
+        s16 clk_gpio;
+        s16 dat_gpio;
+        s16 sel_gpio;
+};
+
+struct omap_em_asic_bb5_config {
+        s16 retu_irq_gpio;
+        s16 tahvo_irq_gpio;
+};
+
+#endif
diff --git a/arch/arm/plat-omap/include/mach/board-osk.h b/arch/arm/plat-omap/include/mach/board-osk.h
new file mode 100644
index 000000000000..3850cb1f220a
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/board-osk.h
@@ -0,0 +1,47 @@
+/*
+ * arch/arm/plat-omap/include/mach/board-osk.h
+ *
+ * Hardware definitions for TI OMAP5912 OSK board.
+ *
+ * Written by Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_OMAP_OSK_H
+#define __ASM_ARCH_OMAP_OSK_H
+
+/* At OMAP5912 OSK the Ethernet is directly connected to CS1 */
+#define OMAP_OSK_ETHR_START             0x04800300
+
+/* TPS65010 has four GPIOs.  nPG and LED2 can be treated like GPIOs with
+ * alternate pin configurations for hardware-controlled blinking.
+ */
+#define OSK_TPS_GPIO_BASE               (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */)
+#       define OSK_TPS_GPIO_USB_PWR_EN  (OSK_TPS_GPIO_BASE + 0)
+#       define OSK_TPS_GPIO_LED_D3      (OSK_TPS_GPIO_BASE + 1)
+#       define OSK_TPS_GPIO_LAN_RESET   (OSK_TPS_GPIO_BASE + 2)
+#       define OSK_TPS_GPIO_DSP_PWR_EN  (OSK_TPS_GPIO_BASE + 3)
+#       define OSK_TPS_GPIO_LED_D9      (OSK_TPS_GPIO_BASE + 4)
+#       define OSK_TPS_GPIO_LED_D2      (OSK_TPS_GPIO_BASE + 5)
+
+#endif /*  __ASM_ARCH_OMAP_OSK_H */
+
diff --git a/arch/arm/plat-omap/include/mach/board-palmte.h b/arch/arm/plat-omap/include/mach/board-palmte.h
new file mode 100644
index 000000000000..6906cdebbcfb
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/board-palmte.h
@@ -0,0 +1,32 @@
+/*
+ * arch/arm/plat-omap/include/mach/board-palmte.h
+ *
+ * Hardware definitions for the Palm Tungsten E device.
+ *
+ * Maintainters :       http://palmtelinux.sf.net
+ *                      palmtelinux-developpers@lists.sf.net
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __OMAP_BOARD_PALMTE_H
+#define __OMAP_BOARD_PALMTE_H
+
+#define PALMTE_USBDETECT_GPIO   0
+#define PALMTE_USB_OR_DC_GPIO   1
+#define PALMTE_TSC_GPIO         4
+#define PALMTE_PINTDAV_GPIO     6
+#define PALMTE_MMC_WP_GPIO      8
+#define PALMTE_MMC_POWER_GPIO   9
+#define PALMTE_HDQ_GPIO         11
+#define PALMTE_HEADPHONES_GPIO  14
+#define PALMTE_SPEAKER_GPIO     15
+#define PALMTE_DC_GPIO          OMAP_MPUIO(2)
+#define PALMTE_MMC_SWITCH_GPIO  OMAP_MPUIO(4)
+#define PALMTE_MMC1_GPIO        OMAP_MPUIO(6)
+#define PALMTE_MMC2_GPIO        OMAP_MPUIO(7)
+#define PALMTE_MMC3_GPIO        OMAP_MPUIO(11)
+
+#endif  /* __OMAP_BOARD_PALMTE_H */
diff --git a/arch/arm/plat-omap/include/mach/board-palmtt.h b/arch/arm/plat-omap/include/mach/board-palmtt.h
new file mode 100644
index 000000000000..e79f382b5931
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/board-palmtt.h
@@ -0,0 +1,23 @@
+/*
+ * arch/arm/plat-omap/include/mach/board-palmte.h
+ *
+ * Hardware definitions for the Palm Tungsten|T device.
+ *
+ * Maintainters :       Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __OMAP_BOARD_PALMTT_H
+#define __OMAP_BOARD_PALMTT_H
+
+#define PALMTT_USBDETECT_GPIO   0
+#define PALMTT_CABLE_GPIO       1
+#define PALMTT_LED_GPIO         3
+#define PALMTT_PENIRQ_GPIO      6
+#define PALMTT_MMC_WP_GPIO      8
+#define PALMTT_HDQ_GPIO         11
+
+#endif  /* __OMAP_BOARD_PALMTT_H */
diff --git a/arch/arm/plat-omap/include/mach/board-palmz71.h b/arch/arm/plat-omap/include/mach/board-palmz71.h
new file mode 100644
index 000000000000..b1d7d579b313
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/board-palmz71.h
@@ -0,0 +1,26 @@
+/*
+ * arch/arm/plat-omap/include/mach/board-palmz71.h
+ *
+ * Hardware definitions for the Palm Zire71 device.
+ *
+ * Maintainters :       Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __OMAP_BOARD_PALMZ71_H
+#define __OMAP_BOARD_PALMZ71_H
+
+#define PALMZ71_USBDETECT_GPIO  0
+#define PALMZ71_PENIRQ_GPIO     6
+#define PALMZ71_MMC_WP_GPIO     8
+#define PALMZ71_HDQ_GPIO        11
+
+#define PALMZ71_HOTSYNC_GPIO    OMAP_MPUIO(1)
+#define PALMZ71_CABLE_GPIO      OMAP_MPUIO(2)
+#define PALMZ71_SLIDER_GPIO     OMAP_MPUIO(3)
+#define PALMZ71_MMC_IN_GPIO     OMAP_MPUIO(4)
+
+#endif  /* __OMAP_BOARD_PALMZ71_H */
diff --git a/arch/arm/plat-omap/include/mach/board-perseus2.h b/arch/arm/plat-omap/include/mach/board-perseus2.h
new file mode 100644
index 000000000000..c06c3d717d57
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/board-perseus2.h
@@ -0,0 +1,39 @@
+/*
+ *  arch/arm/plat-omap/include/mach/board-perseus2.h
+ *
+ *  Copyright 2003 by Texas Instruments Incorporated
+ *    OMAP730 / Perseus2 support by Jean Pihet
+ *
+ * Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com)
+ * Author: RidgeRun, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ASM_ARCH_OMAP_PERSEUS2_H
+#define __ASM_ARCH_OMAP_PERSEUS2_H
+
+#include <mach/fpga.h>
+
+#ifndef OMAP_SDRAM_DEVICE
+#define OMAP_SDRAM_DEVICE               D256M_1X16_4B
+#endif
+
+#endif
diff --git a/include/asm-arm/arch-omap/board-sx1.h b/arch/arm/plat-omap/include/mach/board-sx1.h
index 355adbdaae33..355adbdaae33 100644
--- a/include/asm-arm/arch-omap/board-sx1.h
+++ b/arch/arm/plat-omap/include/mach/board-sx1.h
diff --git a/include/asm-arm/arch-omap/board-voiceblue.h b/arch/arm/plat-omap/include/mach/board-voiceblue.h
index ed6d346ee123..ed6d346ee123 100644
--- a/include/asm-arm/arch-omap/board-voiceblue.h
+++ b/arch/arm/plat-omap/include/mach/board-voiceblue.h
diff --git a/arch/arm/plat-omap/include/mach/board.h b/arch/arm/plat-omap/include/mach/board.h
new file mode 100644
index 000000000000..54445642f35d
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/board.h
@@ -0,0 +1,186 @@
+/*
+ *  arch/arm/plat-omap/include/mach/board.h
+ *
+ *  Information structures for board-specific data
+ *
+ *  Copyright (C) 2004  Nokia Corporation
+ *  Written by Juha Yrjölä <juha.yrjola@nokia.com>
+ */
+
+#ifndef _OMAP_BOARD_H
+#define _OMAP_BOARD_H
+
+#include <linux/types.h>
+
+#include <mach/gpio-switch.h>
+
+/* Different peripheral ids */
+#define OMAP_TAG_CLOCK          0x4f01
+#define OMAP_TAG_MMC            0x4f02
+#define OMAP_TAG_SERIAL_CONSOLE 0x4f03
+#define OMAP_TAG_USB            0x4f04
+#define OMAP_TAG_LCD            0x4f05
+#define OMAP_TAG_GPIO_SWITCH    0x4f06
+#define OMAP_TAG_UART           0x4f07
+#define OMAP_TAG_FBMEM          0x4f08
+#define OMAP_TAG_STI_CONSOLE    0x4f09
+#define OMAP_TAG_CAMERA_SENSOR  0x4f0a
+
+#define OMAP_TAG_BOOT_REASON    0x4f80
+#define OMAP_TAG_FLASH_PART     0x4f81
+#define OMAP_TAG_VERSION_STR    0x4f82
+
+struct omap_clock_config {
+        /* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */
+        u8 system_clock_type;
+};
+
+struct omap_mmc_conf {
+        unsigned enabled:1;
+        /* nomux means "standard" muxing is wrong on this board, and that
+         * board-specific code handled it before common init logic.
+         */
+        unsigned nomux:1;
+        /* switch pin can be for card detect (default) or card cover */
+        unsigned cover:1;
+        /* 4 wire signaling is optional, and is only used for SD/SDIO */
+        unsigned wire4:1;
+        s16 power_pin;
+        s16 switch_pin;
+        s16 wp_pin;
+};
+
+struct omap_mmc_config {
+        struct omap_mmc_conf mmc[2];
+};
+
+struct omap_serial_console_config {
+        u8 console_uart;
+        u32 console_speed;
+};
+
+struct omap_sti_console_config {
+        unsigned enable:1;
+        u8 channel;
+};
+
+struct omap_camera_sensor_config {
+        u16 reset_gpio;
+        int (*power_on)(void * data);
+        int (*power_off)(void * data);
+};
+
+struct omap_usb_config {
+        /* Configure drivers according to the connectors on your board:
+         *  - "A" connector (rectagular)
+         *      ... for host/OHCI use, set "register_host".
+         *  - "B" connector (squarish) or "Mini-B"
+         *      ... for device/gadget use, set "register_dev".
+         *  - "Mini-AB" connector (very similar to Mini-B)
+         *      ... for OTG use as device OR host, initialize "otg"
+         */
+        unsigned        register_host:1;
+        unsigned        register_dev:1;
+        u8              otg;    /* port number, 1-based:  usb1 == 2 */
+
+        u8              hmc_mode;
+
+        /* implicitly true if otg:  host supports remote wakeup? */
+        u8              rwc;
+
+        /* signaling pins used to talk to transceiver on usbN:
+         *  0 == usbN unused
+         *  2 == usb0-only, using internal transceiver
+         *  3 == 3 wire bidirectional
+         *  4 == 4 wire bidirectional
+         *  6 == 6 wire unidirectional (or TLL)
+         */
+        u8              pins[3];
+};
+
+struct omap_lcd_config {
+        char panel_name[16];
+        char ctrl_name[16];
+        s16  nreset_gpio;
+        u8   data_lines;
+};
+
+struct device;
+struct fb_info;
+struct omap_backlight_config {
+        int default_intensity;
+        int (*set_power)(struct device *dev, int state);
+        int (*check_fb)(struct fb_info *fb);
+};
+
+struct omap_fbmem_config {
+        u32 start;
+        u32 size;
+};
+
+struct omap_pwm_led_platform_data {
+        const char *name;
+        int intensity_timer;
+        int blink_timer;
+        void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off);
+};
+
+/* See arch/arm/plat-omap/include/mach/gpio-switch.h for definitions */
+struct omap_gpio_switch_config {
+        char name[12];
+        u16 gpio;
+        int flags:4;
+        int type:4;
+        int key_code:24; /* Linux key code */
+};
+
+struct omap_uart_config {
+        /* Bit field of UARTs present; bit 0 --> UART1 */
+        unsigned int enabled_uarts;
+};
+
+
+struct omap_flash_part_config {
+        char part_table[0];
+};
+
+struct omap_boot_reason_config {
+        char reason_str[12];
+};
+
+struct omap_version_config {
+        char component[12];
+        char version[12];
+};
+
+
+#include <mach/board-nokia.h>
+
+struct omap_board_config_entry {
+        u16 tag;
+        u16 len;
+        u8  data[0];
+};
+
+struct omap_board_config_kernel {
+        u16 tag;
+        const void *data;
+};
+
+extern const void *__omap_get_config(u16 tag, size_t len, int nr);
+
+#define omap_get_config(tag, type) \
+        ((const type *) __omap_get_config((tag), sizeof(type), 0))
+#define omap_get_nr_config(tag, type, nr) \
+        ((const type *) __omap_get_config((tag), sizeof(type), (nr)))
+
+extern const void *omap_get_var_config(u16 tag, size_t *len);
+
+extern struct omap_board_config_kernel *omap_board_config;
+extern int omap_board_config_size;
+
+
+/* for TI reference platforms sharing the same debug card */
+extern int debug_card_init(u32 addr, unsigned gpio);
+
+#endif
diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h
new file mode 100644
index 000000000000..92f7c7238fcd
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/clock.h
@@ -0,0 +1,162 @@
+/*
+ *  arch/arm/plat-omap/include/mach/clock.h
+ *
+ *  Copyright (C) 2004 - 2005 Nokia corporation
+ *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
+ *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_OMAP_CLOCK_H
+#define __ARCH_ARM_OMAP_CLOCK_H
+
+struct module;
+struct clk;
+
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+
+struct clksel_rate {
+        u8                      div;
+        u32                     val;
+        u8                      flags;
+};
+
+struct clksel {
+        struct clk               *parent;
+        const struct clksel_rate *rates;
+};
+
+struct dpll_data {
+        void __iomem            *mult_div1_reg;
+        u32                     mult_mask;
+        u32                     div1_mask;
+        u16                     last_rounded_m;
+        u8                      last_rounded_n;
+        unsigned long           last_rounded_rate;
+        unsigned int            rate_tolerance;
+        u16                     max_multiplier;
+        u8                      max_divider;
+        u32                     max_tolerance;
+#  if defined(CONFIG_ARCH_OMAP3)
+        u8                      modes;
+        void __iomem            *control_reg;
+        u32                     enable_mask;
+        u8                      auto_recal_bit;
+        u8                      recal_en_bit;
+        u8                      recal_st_bit;
+        void __iomem            *autoidle_reg;
+        u32                     autoidle_mask;
+        void __iomem            *idlest_reg;
+        u8                      idlest_bit;
+#  endif
+};
+
+#endif
+
+struct clk {
+        struct list_head        node;
+        struct module           *owner;
+        const char              *name;
+        int                     id;
+        struct clk              *parent;
+        unsigned long           rate;
+        __u32                   flags;
+        void __iomem            *enable_reg;
+        __u8                    enable_bit;
+        __s8                    usecount;
+        void                    (*recalc)(struct clk *);
+        int                     (*set_rate)(struct clk *, unsigned long);
+        long                    (*round_rate)(struct clk *, unsigned long);
+        void                    (*init)(struct clk *);
+        int                     (*enable)(struct clk *);
+        void                    (*disable)(struct clk *);
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+        u8                      fixed_div;
+        void __iomem            *clksel_reg;
+        u32                     clksel_mask;
+        const struct clksel     *clksel;
+        struct dpll_data        *dpll_data;
+#else
+        __u8                    rate_offset;
+        __u8                    src_offset;
+#endif
+#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
+        struct dentry           *dent;  /* For visible tree hierarchy */
+#endif
+};
+
+struct cpufreq_frequency_table;
+
+struct clk_functions {
+        int             (*clk_enable)(struct clk *clk);
+        void            (*clk_disable)(struct clk *clk);
+        long            (*clk_round_rate)(struct clk *clk, unsigned long rate);
+        int             (*clk_set_rate)(struct clk *clk, unsigned long rate);
+        int             (*clk_set_parent)(struct clk *clk, struct clk *parent);
+        struct clk *    (*clk_get_parent)(struct clk *clk);
+        void            (*clk_allow_idle)(struct clk *clk);
+        void            (*clk_deny_idle)(struct clk *clk);
+        void            (*clk_disable_unused)(struct clk *clk);
+#ifdef CONFIG_CPU_FREQ
+        void            (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
+#endif
+};
+
+extern unsigned int mpurate;
+
+extern int clk_init(struct clk_functions * custom_clocks);
+extern int clk_register(struct clk *clk);
+extern void clk_unregister(struct clk *clk);
+extern void propagate_rate(struct clk *clk);
+extern void recalculate_root_clocks(void);
+extern void followparent_recalc(struct clk * clk);
+extern void clk_allow_idle(struct clk *clk);
+extern void clk_deny_idle(struct clk *clk);
+extern int clk_get_usecount(struct clk *clk);
+extern void clk_enable_init_clocks(void);
+
+/* Clock flags */
+#define RATE_CKCTL              (1 << 0)        /* Main fixed ratio clocks */
+#define RATE_FIXED              (1 << 1)        /* Fixed clock rate */
+#define RATE_PROPAGATES         (1 << 2)        /* Program children too */
+#define VIRTUAL_CLOCK           (1 << 3)        /* Composite clock from table */
+#define ALWAYS_ENABLED          (1 << 4)        /* Clock cannot be disabled */
+#define ENABLE_REG_32BIT        (1 << 5)        /* Use 32-bit access */
+#define VIRTUAL_IO_ADDRESS      (1 << 6)        /* Clock in virtual address */
+#define CLOCK_IDLE_CONTROL      (1 << 7)
+#define CLOCK_NO_IDLE_PARENT    (1 << 8)
+#define DELAYED_APP             (1 << 9)        /* Delay application of clock */
+#define CONFIG_PARTICIPANT      (1 << 10)       /* Fundamental clock */
+#define ENABLE_ON_INIT          (1 << 11)       /* Enable upon framework init */
+#define INVERT_ENABLE           (1 << 12)       /* 0 enables, 1 disables */
+/* bits 13-20 are currently free */
+#define CLOCK_IN_OMAP310        (1 << 21)
+#define CLOCK_IN_OMAP730        (1 << 22)
+#define CLOCK_IN_OMAP1510       (1 << 23)
+#define CLOCK_IN_OMAP16XX       (1 << 24)
+#define CLOCK_IN_OMAP242X       (1 << 25)
+#define CLOCK_IN_OMAP243X       (1 << 26)
+#define CLOCK_IN_OMAP343X       (1 << 27)       /* clocks common to all 343X */
+#define PARENT_CONTROLS_CLOCK   (1 << 28)
+#define CLOCK_IN_OMAP3430ES1    (1 << 29)       /* 3430ES1 clocks only */
+#define CLOCK_IN_OMAP3430ES2    (1 << 30)       /* 3430ES2 clocks only */
+
+/* Clksel_rate flags */
+#define DEFAULT_RATE            (1 << 0)
+#define RATE_IN_242X            (1 << 1)
+#define RATE_IN_243X            (1 << 2)
+#define RATE_IN_343X            (1 << 3)        /* rates common to all 343X */
+#define RATE_IN_3430ES2         (1 << 4)        /* 3430ES2 rates only */
+
+#define RATE_IN_24XX            (RATE_IN_242X | RATE_IN_243X)
+
+
+/* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */
+#define CORE_CLK_SRC_32K                0
+#define CORE_CLK_SRC_DPLL               1
+#define CORE_CLK_SRC_DPLL_X2            2
+
+#endif
diff --git a/arch/arm/plat-omap/include/mach/common.h b/arch/arm/plat-omap/include/mach/common.h
new file mode 100644
index 000000000000..06093112b665
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/common.h
@@ -0,0 +1,69 @@
+/*
+ * arch/arm/plat-omap/include/mach/common.h
+ *
+ * Header for code common to all OMAP machines.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
+#define __ARCH_ARM_MACH_OMAP_COMMON_H
+
+#include <linux/i2c.h>
+
+struct sys_timer;
+
+extern void omap_map_common_io(void);
+extern struct sys_timer omap_timer;
+extern void omap_serial_init(void);
+#ifdef CONFIG_I2C_OMAP
+extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
+                                 struct i2c_board_info const *info,
+                                 unsigned len);
+#else
+static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
+                                 struct i2c_board_info const *info,
+                                 unsigned len)
+{
+        return 0;
+}
+#endif
+
+/* IO bases for various OMAP processors */
+struct omap_globals {
+        void __iomem    *tap;           /* Control module ID code */
+        void __iomem    *sdrc;          /* SDRAM Controller */
+        void __iomem    *sms;           /* SDRAM Memory Scheduler */
+        void __iomem    *ctrl;          /* System Control Module */
+        void __iomem    *prm;           /* Power and Reset Management */
+        void __iomem    *cm;            /* Clock Management */
+};
+
+void omap2_set_globals_242x(void);
+void omap2_set_globals_243x(void);
+void omap2_set_globals_343x(void);
+
+/* These get called from omap2_set_globals_xxxx(), do not call these */
+void omap2_set_globals_memory(struct omap_globals *);
+void omap2_set_globals_control(struct omap_globals *);
+void omap2_set_globals_prcm(struct omap_globals *);
+
+#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/arch/arm/plat-omap/include/mach/control.h b/arch/arm/plat-omap/include/mach/control.h
new file mode 100644
index 000000000000..e3fd62d9a995
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/control.h
@@ -0,0 +1,189 @@
+#ifndef __ASM_ARCH_CONTROL_H
+#define __ASM_ARCH_CONTROL_H
+
+/*
+ * arch/arm/plat-omap/include/mach/control.h
+ *
+ * OMAP2/3 System Control Module definitions
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation.
+ */
+
+#include <mach/io.h>
+
+#define OMAP242X_CTRL_REGADDR(reg)                                      \
+        (void __iomem *)IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
+#define OMAP243X_CTRL_REGADDR(reg)                                      \
+        (void __iomem *)IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
+#define OMAP343X_CTRL_REGADDR(reg)                                      \
+        (void __iomem *)IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
+
+/*
+ * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
+ * OMAP24XX and OMAP34XX.
+ */
+
+/* Control submodule offsets */
+
+#define OMAP2_CONTROL_INTERFACE         0x000
+#define OMAP2_CONTROL_PADCONFS          0x030
+#define OMAP2_CONTROL_GENERAL           0x270
+#define OMAP343X_CONTROL_MEM_WKUP       0x600
+#define OMAP343X_CONTROL_PADCONFS_WKUP  0xa00
+#define OMAP343X_CONTROL_GENERAL_WKUP   0xa60
+
+/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
+
+#define OMAP2_CONTROL_SYSCONFIG         (OMAP2_CONTROL_INTERFACE + 0x10)
+
+/* CONTROL_GENERAL register offsets common to OMAP2 & 3 */
+#define OMAP2_CONTROL_DEVCONF0          (OMAP2_CONTROL_GENERAL + 0x0004)
+#define OMAP2_CONTROL_MSUSPENDMUX_0     (OMAP2_CONTROL_GENERAL + 0x0020)
+#define OMAP2_CONTROL_MSUSPENDMUX_1     (OMAP2_CONTROL_GENERAL + 0x0024)
+#define OMAP2_CONTROL_MSUSPENDMUX_2     (OMAP2_CONTROL_GENERAL + 0x0028)
+#define OMAP2_CONTROL_MSUSPENDMUX_3     (OMAP2_CONTROL_GENERAL + 0x002c)
+#define OMAP2_CONTROL_MSUSPENDMUX_4     (OMAP2_CONTROL_GENERAL + 0x0030)
+#define OMAP2_CONTROL_MSUSPENDMUX_5     (OMAP2_CONTROL_GENERAL + 0x0034)
+#define OMAP2_CONTROL_SEC_CTRL          (OMAP2_CONTROL_GENERAL + 0x0040)
+#define OMAP2_CONTROL_RPUB_KEY_H_0      (OMAP2_CONTROL_GENERAL + 0x0090)
+#define OMAP2_CONTROL_RPUB_KEY_H_1      (OMAP2_CONTROL_GENERAL + 0x0094)
+#define OMAP2_CONTROL_RPUB_KEY_H_2      (OMAP2_CONTROL_GENERAL + 0x0098)
+#define OMAP2_CONTROL_RPUB_KEY_H_3      (OMAP2_CONTROL_GENERAL + 0x009c)
+
+/* 242x-only CONTROL_GENERAL register offsets */
+#define OMAP242X_CONTROL_DEVCONF        OMAP2_CONTROL_DEVCONF0 /* match TRM */
+#define OMAP242X_CONTROL_OCM_RAM_PERM   (OMAP2_CONTROL_GENERAL + 0x0068)
+
+/* 243x-only CONTROL_GENERAL register offsets */
+/* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
+#define OMAP243X_CONTROL_DEVCONF1       (OMAP2_CONTROL_GENERAL + 0x0078)
+#define OMAP243X_CONTROL_CSIRXFE        (OMAP2_CONTROL_GENERAL + 0x007c)
+#define OMAP243X_CONTROL_IVA2_BOOTADDR  (OMAP2_CONTROL_GENERAL + 0x0190)
+#define OMAP243X_CONTROL_IVA2_BOOTMOD   (OMAP2_CONTROL_GENERAL + 0x0194)
+#define OMAP243X_CONTROL_IVA2_GEMCFG    (OMAP2_CONTROL_GENERAL + 0x0198)
+
+/* 24xx-only CONTROL_GENERAL register offsets */
+#define OMAP24XX_CONTROL_DEBOBS         (OMAP2_CONTROL_GENERAL + 0x0000)
+#define OMAP24XX_CONTROL_EMU_SUPPORT    (OMAP2_CONTROL_GENERAL + 0x0008)
+#define OMAP24XX_CONTROL_SEC_TEST       (OMAP2_CONTROL_GENERAL + 0x0044)
+#define OMAP24XX_CONTROL_PSA_CTRL       (OMAP2_CONTROL_GENERAL + 0x0048)
+#define OMAP24XX_CONTROL_PSA_CMD        (OMAP2_CONTROL_GENERAL + 0x004c)
+#define OMAP24XX_CONTROL_PSA_VALUE      (OMAP2_CONTROL_GENERAL + 0x0050)
+#define OMAP24XX_CONTROL_SEC_EMU        (OMAP2_CONTROL_GENERAL + 0x0060)
+#define OMAP24XX_CONTROL_SEC_TAP        (OMAP2_CONTROL_GENERAL + 0x0064)
+#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD        (OMAP2_CONTROL_GENERAL + 0x006c)
+#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD  (OMAP2_CONTROL_GENERAL + 0x0070)
+#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD   (OMAP2_CONTROL_GENERAL + 0x0074)
+#define OMAP24XX_CONTROL_SEC_STATUS             (OMAP2_CONTROL_GENERAL + 0x0080)
+#define OMAP24XX_CONTROL_SEC_ERR_STATUS         (OMAP2_CONTROL_GENERAL + 0x0084)
+#define OMAP24XX_CONTROL_STATUS                 (OMAP2_CONTROL_GENERAL + 0x0088)
+#define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c)
+#define OMAP24XX_CONTROL_RAND_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00a0)
+#define OMAP24XX_CONTROL_RAND_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00a4)
+#define OMAP24XX_CONTROL_RAND_KEY_2     (OMAP2_CONTROL_GENERAL + 0x00a8)
+#define OMAP24XX_CONTROL_RAND_KEY_3     (OMAP2_CONTROL_GENERAL + 0x00ac)
+#define OMAP24XX_CONTROL_CUST_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00b0)
+#define OMAP24XX_CONTROL_CUST_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00b4)
+#define OMAP24XX_CONTROL_TEST_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00c0)
+#define OMAP24XX_CONTROL_TEST_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00c4)
+#define OMAP24XX_CONTROL_TEST_KEY_2     (OMAP2_CONTROL_GENERAL + 0x00c8)
+#define OMAP24XX_CONTROL_TEST_KEY_3     (OMAP2_CONTROL_GENERAL + 0x00cc)
+#define OMAP24XX_CONTROL_TEST_KEY_4     (OMAP2_CONTROL_GENERAL + 0x00d0)
+#define OMAP24XX_CONTROL_TEST_KEY_5     (OMAP2_CONTROL_GENERAL + 0x00d4)
+#define OMAP24XX_CONTROL_TEST_KEY_6     (OMAP2_CONTROL_GENERAL + 0x00d8)
+#define OMAP24XX_CONTROL_TEST_KEY_7     (OMAP2_CONTROL_GENERAL + 0x00dc)
+#define OMAP24XX_CONTROL_TEST_KEY_8     (OMAP2_CONTROL_GENERAL + 0x00e0)
+#define OMAP24XX_CONTROL_TEST_KEY_9     (OMAP2_CONTROL_GENERAL + 0x00e4)
+
+/* 34xx-only CONTROL_GENERAL register offsets */
+#define OMAP343X_CONTROL_PADCONF_OFF    (OMAP2_CONTROL_GENERAL + 0x0000)
+#define OMAP343X_CONTROL_MEM_DFTRW0     (OMAP2_CONTROL_GENERAL + 0x0008)
+#define OMAP343X_CONTROL_MEM_DFTRW1     (OMAP2_CONTROL_GENERAL + 0x000c)
+#define OMAP343X_CONTROL_DEVCONF1       (OMAP2_CONTROL_GENERAL + 0x0068)
+#define OMAP343X_CONTROL_CSIRXFE                (OMAP2_CONTROL_GENERAL + 0x006c)
+#define OMAP343X_CONTROL_SEC_STATUS             (OMAP2_CONTROL_GENERAL + 0x0070)
+#define OMAP343X_CONTROL_SEC_ERR_STATUS         (OMAP2_CONTROL_GENERAL + 0x0074)
+#define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG   (OMAP2_CONTROL_GENERAL + 0x0078)
+#define OMAP343X_CONTROL_STATUS                 (OMAP2_CONTROL_GENERAL + 0x0080)
+#define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
+#define OMAP343X_CONTROL_RPUB_KEY_H_4   (OMAP2_CONTROL_GENERAL + 0x00a0)
+#define OMAP343X_CONTROL_RAND_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00a8)
+#define OMAP343X_CONTROL_RAND_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00ac)
+#define OMAP343X_CONTROL_RAND_KEY_2     (OMAP2_CONTROL_GENERAL + 0x00b0)
+#define OMAP343X_CONTROL_RAND_KEY_3     (OMAP2_CONTROL_GENERAL + 0x00b4)
+#define OMAP343X_CONTROL_TEST_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00c8)
+#define OMAP343X_CONTROL_TEST_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00cc)
+#define OMAP343X_CONTROL_TEST_KEY_2     (OMAP2_CONTROL_GENERAL + 0x00d0)
+#define OMAP343X_CONTROL_TEST_KEY_3     (OMAP2_CONTROL_GENERAL + 0x00d4)
+#define OMAP343X_CONTROL_TEST_KEY_4     (OMAP2_CONTROL_GENERAL + 0x00d8)
+#define OMAP343X_CONTROL_TEST_KEY_5     (OMAP2_CONTROL_GENERAL + 0x00dc)
+#define OMAP343X_CONTROL_TEST_KEY_6     (OMAP2_CONTROL_GENERAL + 0x00e0)
+#define OMAP343X_CONTROL_TEST_KEY_7     (OMAP2_CONTROL_GENERAL + 0x00e4)
+#define OMAP343X_CONTROL_TEST_KEY_8     (OMAP2_CONTROL_GENERAL + 0x00e8)
+#define OMAP343X_CONTROL_TEST_KEY_9     (OMAP2_CONTROL_GENERAL + 0x00ec)
+#define OMAP343X_CONTROL_TEST_KEY_10    (OMAP2_CONTROL_GENERAL + 0x00f0)
+#define OMAP343X_CONTROL_TEST_KEY_11    (OMAP2_CONTROL_GENERAL + 0x00f4)
+#define OMAP343X_CONTROL_TEST_KEY_12    (OMAP2_CONTROL_GENERAL + 0x00f8)
+#define OMAP343X_CONTROL_TEST_KEY_13    (OMAP2_CONTROL_GENERAL + 0x00fc)
+#define OMAP343X_CONTROL_IVA2_BOOTADDR  (OMAP2_CONTROL_GENERAL + 0x0190)
+#define OMAP343X_CONTROL_IVA2_BOOTMOD   (OMAP2_CONTROL_GENERAL + 0x0194)
+
+/*
+ * REVISIT: This list of registers is not comprehensive - there are more
+ * that should be added.
+ */
+
+/*
+ * Control module register bit defines - these should eventually go into
+ * their own regbits file.  Some of these will be complicated, depending
+ * on the device type (general-purpose, emulator, test, secure, bad, other)
+ * and the security mode (secure, non-secure, don't care)
+ */
+/* CONTROL_DEVCONF0 bits */
+#define OMAP24XX_USBSTANDBYCTRL         (1 << 15)
+#define OMAP2_MCBSP2_CLKS_MASK          (1 << 6)
+#define OMAP2_MCBSP1_CLKS_MASK          (1 << 2)
+
+/* CONTROL_DEVCONF1 bits */
+#define OMAP2_MCBSP5_CLKS_MASK          (1 << 4) /* > 242x */
+#define OMAP2_MCBSP4_CLKS_MASK          (1 << 2) /* > 242x */
+#define OMAP2_MCBSP3_CLKS_MASK          (1 << 0) /* > 242x */
+
+/* CONTROL_STATUS bits */
+#define OMAP2_DEVICETYPE_MASK           (0x7 << 8)
+#define OMAP2_SYSBOOT_5_MASK            (1 << 5)
+#define OMAP2_SYSBOOT_4_MASK            (1 << 4)
+#define OMAP2_SYSBOOT_3_MASK            (1 << 3)
+#define OMAP2_SYSBOOT_2_MASK            (1 << 2)
+#define OMAP2_SYSBOOT_1_MASK            (1 << 1)
+#define OMAP2_SYSBOOT_0_MASK            (1 << 0)
+
+#ifndef __ASSEMBLY__
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+extern void __iomem *omap_ctrl_base_get(void);
+extern u8 omap_ctrl_readb(u16 offset);
+extern u16 omap_ctrl_readw(u16 offset);
+extern u32 omap_ctrl_readl(u16 offset);
+extern void omap_ctrl_writeb(u8 val, u16 offset);
+extern void omap_ctrl_writew(u16 val, u16 offset);
+extern void omap_ctrl_writel(u32 val, u16 offset);
+#else
+#define omap_ctrl_base_get()            0
+#define omap_ctrl_readb(x)              0
+#define omap_ctrl_readw(x)              0
+#define omap_ctrl_readl(x)              0
+#define omap_ctrl_writeb(x, y)          WARN_ON(1)
+#define omap_ctrl_writew(x, y)          WARN_ON(1)
+#define omap_ctrl_writel(x, y)          WARN_ON(1)
+#endif
+#endif  /* __ASSEMBLY__ */
+
+#endif /* __ASM_ARCH_CONTROL_H */
+
diff --git a/arch/arm/plat-omap/include/mach/cpu.h b/arch/arm/plat-omap/include/mach/cpu.h
new file mode 100644
index 000000000000..05aee0eda34f
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/cpu.h
@@ -0,0 +1,402 @@
+/*
+ * arch/arm/plat-omap/include/mach/cpu.h
+ *
+ * OMAP cpu type detection
+ *
+ * Copyright (C) 2004, 2008 Nokia Corporation
+ *
+ * Written by Tony Lindgren <tony.lindgren@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARCH_OMAP_CPU_H
+#define __ASM_ARCH_OMAP_CPU_H
+
+struct omap_chip_id {
+        u8 oc;
+};
+
+#define OMAP_CHIP_INIT(x)       { .oc = x }
+
+extern unsigned int system_rev;
+
+#define omap2_cpu_rev()         ((system_rev >> 12) & 0x0f)
+
+/*
+ * Test if multicore OMAP support is needed
+ */
+#undef MULTI_OMAP1
+#undef MULTI_OMAP2
+#undef OMAP_NAME
+
+#ifdef CONFIG_ARCH_OMAP730
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP1
+#  define MULTI_OMAP1
+# else
+#  define OMAP_NAME omap730
+# endif
+#endif
+#ifdef CONFIG_ARCH_OMAP15XX
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP1
+#  define MULTI_OMAP1
+# else
+#  define OMAP_NAME omap1510
+# endif
+#endif
+#ifdef CONFIG_ARCH_OMAP16XX
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP1
+#  define MULTI_OMAP1
+# else
+#  define OMAP_NAME omap16xx
+# endif
+#endif
+#if (defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX))
+# if (defined(OMAP_NAME) || defined(MULTI_OMAP1))
+#  error "OMAP1 and OMAP2 can't be selected at the same time"
+# endif
+#endif
+#ifdef CONFIG_ARCH_OMAP2420
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP2
+#  define MULTI_OMAP2
+# else
+#  define OMAP_NAME omap2420
+# endif
+#endif
+#ifdef CONFIG_ARCH_OMAP2430
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP2
+#  define MULTI_OMAP2
+# else
+#  define OMAP_NAME omap2430
+# endif
+#endif
+#ifdef CONFIG_ARCH_OMAP3430
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP2
+#  define MULTI_OMAP2
+# else
+#  define OMAP_NAME omap3430
+# endif
+#endif
+
+/*
+ * Macros to group OMAP into cpu classes.
+ * These can be used in most places.
+ * cpu_is_omap7xx():    True for OMAP730
+ * cpu_is_omap15xx():   True for OMAP1510, OMAP5910 and OMAP310
+ * cpu_is_omap16xx():   True for OMAP1610, OMAP5912 and OMAP1710
+ * cpu_is_omap24xx():   True for OMAP2420, OMAP2422, OMAP2423, OMAP2430
+ * cpu_is_omap242x():   True for OMAP2420, OMAP2422, OMAP2423
+ * cpu_is_omap243x():   True for OMAP2430
+ * cpu_is_omap343x():   True for OMAP3430
+ */
+#define GET_OMAP_CLASS  ((system_rev >> 24) & 0xff)
+
+#define IS_OMAP_CLASS(class, id)                        \
+static inline int is_omap ##class (void)                \
+{                                                       \
+        return (GET_OMAP_CLASS == (id)) ? 1 : 0;        \
+}
+
+#define GET_OMAP_SUBCLASS       ((system_rev >> 20) & 0x0fff)
+
+#define IS_OMAP_SUBCLASS(subclass, id)                  \
+static inline int is_omap ##subclass (void)             \
+{                                                       \
+        return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;     \
+}
+
+IS_OMAP_CLASS(7xx, 0x07)
+IS_OMAP_CLASS(15xx, 0x15)
+IS_OMAP_CLASS(16xx, 0x16)
+IS_OMAP_CLASS(24xx, 0x24)
+IS_OMAP_CLASS(34xx, 0x34)
+
+IS_OMAP_SUBCLASS(242x, 0x242)
+IS_OMAP_SUBCLASS(243x, 0x243)
+IS_OMAP_SUBCLASS(343x, 0x343)
+
+#define cpu_is_omap7xx()                0
+#define cpu_is_omap15xx()               0
+#define cpu_is_omap16xx()               0
+#define cpu_is_omap24xx()               0
+#define cpu_is_omap242x()               0
+#define cpu_is_omap243x()               0
+#define cpu_is_omap34xx()               0
+#define cpu_is_omap343x()               0
+
+#if defined(MULTI_OMAP1)
+# if defined(CONFIG_ARCH_OMAP730)
+#  undef  cpu_is_omap7xx
+#  define cpu_is_omap7xx()              is_omap7xx()
+# endif
+# if defined(CONFIG_ARCH_OMAP15XX)
+#  undef  cpu_is_omap15xx
+#  define cpu_is_omap15xx()             is_omap15xx()
+# endif
+# if defined(CONFIG_ARCH_OMAP16XX)
+#  undef  cpu_is_omap16xx
+#  define cpu_is_omap16xx()             is_omap16xx()
+# endif
+#else
+# if defined(CONFIG_ARCH_OMAP730)
+#  undef  cpu_is_omap7xx
+#  define cpu_is_omap7xx()              1
+# endif
+# if defined(CONFIG_ARCH_OMAP15XX)
+#  undef  cpu_is_omap15xx
+#  define cpu_is_omap15xx()             1
+# endif
+# if defined(CONFIG_ARCH_OMAP16XX)
+#  undef  cpu_is_omap16xx
+#  define cpu_is_omap16xx()             1
+# endif
+#endif
+
+#if defined(MULTI_OMAP2)
+# if defined(CONFIG_ARCH_OMAP24XX)
+#  undef  cpu_is_omap24xx
+#  undef  cpu_is_omap242x
+#  undef  cpu_is_omap243x
+#  define cpu_is_omap24xx()             is_omap24xx()
+#  define cpu_is_omap242x()             is_omap242x()
+#  define cpu_is_omap243x()             is_omap243x()
+# endif
+# if defined(CONFIG_ARCH_OMAP34XX)
+#  undef  cpu_is_omap34xx
+#  undef  cpu_is_omap343x
+#  define cpu_is_omap34xx()             is_omap34xx()
+#  define cpu_is_omap343x()             is_omap343x()
+# endif
+#else
+# if defined(CONFIG_ARCH_OMAP24XX)
+#  undef  cpu_is_omap24xx
+#  define cpu_is_omap24xx()             1
+# endif
+# if defined(CONFIG_ARCH_OMAP2420)
+#  undef  cpu_is_omap242x
+#  define cpu_is_omap242x()             1
+# endif
+# if defined(CONFIG_ARCH_OMAP2430)
+#  undef  cpu_is_omap243x
+#  define cpu_is_omap243x()             1
+# endif
+# if defined(CONFIG_ARCH_OMAP34XX)
+#  undef  cpu_is_omap34xx
+#  define cpu_is_omap34xx()             1
+# endif
+# if defined(CONFIG_ARCH_OMAP3430)
+#  undef  cpu_is_omap343x
+#  define cpu_is_omap343x()             1
+# endif
+#endif
+
+/*
+ * Macros to detect individual cpu types.
+ * These are only rarely needed.
+ * cpu_is_omap330():    True for OMAP330
+ * cpu_is_omap730():    True for OMAP730
+ * cpu_is_omap1510():   True for OMAP1510
+ * cpu_is_omap1610():   True for OMAP1610
+ * cpu_is_omap1611():   True for OMAP1611
+ * cpu_is_omap5912():   True for OMAP5912
+ * cpu_is_omap1621():   True for OMAP1621
+ * cpu_is_omap1710():   True for OMAP1710
+ * cpu_is_omap2420():   True for OMAP2420
+ * cpu_is_omap2422():   True for OMAP2422
+ * cpu_is_omap2423():   True for OMAP2423
+ * cpu_is_omap2430():   True for OMAP2430
+ * cpu_is_omap3430():   True for OMAP3430
+ */
+#define GET_OMAP_TYPE   ((system_rev >> 16) & 0xffff)
+
+#define IS_OMAP_TYPE(type, id)                          \
+static inline int is_omap ##type (void)                 \
+{                                                       \
+        return (GET_OMAP_TYPE == (id)) ? 1 : 0;         \
+}
+
+IS_OMAP_TYPE(310, 0x0310)
+IS_OMAP_TYPE(730, 0x0730)
+IS_OMAP_TYPE(1510, 0x1510)
+IS_OMAP_TYPE(1610, 0x1610)
+IS_OMAP_TYPE(1611, 0x1611)
+IS_OMAP_TYPE(5912, 0x1611)
+IS_OMAP_TYPE(1621, 0x1621)
+IS_OMAP_TYPE(1710, 0x1710)
+IS_OMAP_TYPE(2420, 0x2420)
+IS_OMAP_TYPE(2422, 0x2422)
+IS_OMAP_TYPE(2423, 0x2423)
+IS_OMAP_TYPE(2430, 0x2430)
+IS_OMAP_TYPE(3430, 0x3430)
+
+#define cpu_is_omap310()                0
+#define cpu_is_omap730()                0
+#define cpu_is_omap1510()               0
+#define cpu_is_omap1610()               0
+#define cpu_is_omap5912()               0
+#define cpu_is_omap1611()               0
+#define cpu_is_omap1621()               0
+#define cpu_is_omap1710()               0
+#define cpu_is_omap2420()               0
+#define cpu_is_omap2422()               0
+#define cpu_is_omap2423()               0
+#define cpu_is_omap2430()               0
+#define cpu_is_omap3430()               0
+
+#if defined(MULTI_OMAP1)
+# if defined(CONFIG_ARCH_OMAP730)
+#  undef  cpu_is_omap730
+#  define cpu_is_omap730()              is_omap730()
+# endif
+#else
+# if defined(CONFIG_ARCH_OMAP730)
+#  undef  cpu_is_omap730
+#  define cpu_is_omap730()              1
+# endif
+#endif
+
+/*
+ * Whether we have MULTI_OMAP1 or not, we still need to distinguish
+ * between 330 vs. 1510 and 1611B/5912 vs. 1710.
+ */
+#if defined(CONFIG_ARCH_OMAP15XX)
+# undef  cpu_is_omap310
+# undef  cpu_is_omap1510
+# define cpu_is_omap310()               is_omap310()
+# define cpu_is_omap1510()              is_omap1510()
+#endif
+
+#if defined(CONFIG_ARCH_OMAP16XX)
+# undef  cpu_is_omap1610
+# undef  cpu_is_omap1611
+# undef  cpu_is_omap5912
+# undef  cpu_is_omap1621
+# undef  cpu_is_omap1710
+# define cpu_is_omap1610()              is_omap1610()
+# define cpu_is_omap1611()              is_omap1611()
+# define cpu_is_omap5912()              is_omap5912()
+# define cpu_is_omap1621()              is_omap1621()
+# define cpu_is_omap1710()              is_omap1710()
+#endif
+
+#if defined(CONFIG_ARCH_OMAP24XX)
+# undef  cpu_is_omap2420
+# undef  cpu_is_omap2422
+# undef  cpu_is_omap2423
+# undef  cpu_is_omap2430
+# define cpu_is_omap2420()              is_omap2420()
+# define cpu_is_omap2422()              is_omap2422()
+# define cpu_is_omap2423()              is_omap2423()
+# define cpu_is_omap2430()              is_omap2430()
+#endif
+
+#if defined(CONFIG_ARCH_OMAP34XX)
+# undef cpu_is_omap3430
+# define cpu_is_omap3430()              is_omap3430()
+#endif
+
+/* Macros to detect if we have OMAP1 or OMAP2 */
+#define cpu_class_is_omap1()    (cpu_is_omap730() || cpu_is_omap15xx() || \
+                                cpu_is_omap16xx())
+#define cpu_class_is_omap2()    (cpu_is_omap24xx() || cpu_is_omap34xx())
+
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+/*
+ * Macros to detect silicon revision of OMAP2/3 processors.
+ * is_sil_rev_greater_than:     true if passed cpu type & its rev is greater.
+ * is_sil_rev_lesser_than:      true if passed cpu type & its rev is lesser.
+ * is_sil_rev_equal_to:         true if passed cpu type & its rev is equal.
+ * get_sil_rev:                 return the silicon rev value.
+ */
+#define get_sil_omap_type(rev)  ((rev & 0xffff0000) >> 16)
+#define get_sil_revision(rev)   ((rev & 0x0000f000) >> 12)
+
+#define is_sil_rev_greater_than(rev) \
+                ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \
+                (get_sil_revision(system_rev) > get_sil_revision(rev)))
+
+#define is_sil_rev_less_than(rev) \
+                ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \
+                (get_sil_revision(system_rev) < get_sil_revision(rev)))
+
+#define is_sil_rev_equal_to(rev) \
+                ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \
+                (get_sil_revision(system_rev) == get_sil_revision(rev)))
+
+#define get_sil_rev() \
+                get_sil_revision(system_rev)
+
+/* Various silicon macros defined here */
+#define OMAP2420_REV_ES1_0      0x24200000
+#define OMAP2420_REV_ES2_0      0x24201000
+#define OMAP2430_REV_ES1_0      0x24300000
+#define OMAP3430_REV_ES1_0      0x34300000
+#define OMAP3430_REV_ES2_0      0x34301000
+#define OMAP3430_REV_ES2_1      0x34302000
+#define OMAP3430_REV_ES2_2      0x34303000
+
+/*
+ * omap_chip bits
+ *
+ * CHIP_IS_OMAP{2420,2430,3430} indicate that a particular structure is
+ * valid on all chips of that type.  CHIP_IS_OMAP3430ES{1,2} indicates
+ * something that is only valid on that particular ES revision.
+ *
+ * These bits may be ORed together to indicate structures that are
+ * available on multiple chip types.
+ *
+ * To test whether a particular structure matches the current OMAP chip type,
+ * use omap_chip_is().
+ *
+ */
+#define CHIP_IS_OMAP2420       (1 << 0)
+#define CHIP_IS_OMAP2430       (1 << 1)
+#define CHIP_IS_OMAP3430       (1 << 2)
+#define CHIP_IS_OMAP3430ES1    (1 << 3)
+#define CHIP_IS_OMAP3430ES2    (1 << 4)
+
+#define CHIP_IS_OMAP24XX       (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
+
+int omap_chip_is(struct omap_chip_id oci);
+
+
+/*
+ * Macro to detect device type i.e. EMU/HS/TST/GP/BAD
+ */
+#define DEVICE_TYPE_TEST        0
+#define DEVICE_TYPE_EMU         1
+#define DEVICE_TYPE_SEC         2
+#define DEVICE_TYPE_GP          3
+#define DEVICE_TYPE_BAD         4
+
+#define get_device_type()       ((system_rev & 0x700) >> 8)
+#define is_device_type_test()   (get_device_type() == DEVICE_TYPE_TEST)
+#define is_device_type_emu()    (get_device_type() == DEVICE_TYPE_EMU)
+#define is_device_type_sec()    (get_device_type() == DEVICE_TYPE_SEC)
+#define is_device_type_gp()     (get_device_type() == DEVICE_TYPE_GP)
+#define is_device_type_bad()    (get_device_type() == DEVICE_TYPE_BAD)
+
+void omap2_check_revision(void);
+
+#endif    /* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */
+
+#endif
diff --git a/arch/arm/plat-omap/include/mach/debug-macro.S b/arch/arm/plat-omap/include/mach/debug-macro.S
new file mode 100644
index 000000000000..1b0039bdeb4e
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/debug-macro.S
@@ -0,0 +1,58 @@
+/* arch/arm/plat-omap/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+#ifdef CONFIG_ARCH_OMAP1
+                moveq   \rx, #0xff000000        @ physical base address
+                movne   \rx, #0xfe000000        @ virtual base
+                orr     \rx, \rx, #0x00fb0000
+#ifdef CONFIG_OMAP_LL_DEBUG_UART3
+                orr     \rx, \rx, #0x00009000   @ UART 3
+#endif
+#if defined(CONFIG_OMAP_LL_DEBUG_UART2) || defined(CONFIG_OMAP_LL_DEBUG_UART3)
+                orr     \rx, \rx, #0x00000800   @ UART 2 & 3
+#endif
+
+#elif  CONFIG_ARCH_OMAP2
+                moveq   \rx, #0x48000000        @ physical base address
+                movne   \rx, #0xd8000000        @ virtual base
+                orr     \rx, \rx, #0x0006a000
+#ifdef CONFIG_OMAP_LL_DEBUG_UART2
+                add     \rx, \rx, #0x00002000   @ UART 2
+#endif
+#ifdef CONFIG_OMAP_LL_DEBUG_UART3
+                add     \rx, \rx, #0x00004000   @ UART 3
+#endif
+#endif
+                .endm
+
+                .macro  senduart,rd,rx
+                strb    \rd, [\rx]
+                .endm
+
+                .macro  busyuart,rd,rx
+1001:           ldrb    \rd, [\rx, #(0x5 << 2)] @ OMAP-1510 and friends
+                and     \rd, \rd, #0x60
+                teq     \rd, #0x60
+                beq     1002f
+                ldrb    \rd, [\rx, #(0x5 << 0)] @ OMAP-730 only
+                and     \rd, \rd, #0x60
+                teq     \rd, #0x60
+                bne     1001b
+1002:
+                .endm
+
+                .macro  waituart,rd,rx
+                .endm
diff --git a/arch/arm/plat-omap/include/mach/dma.h b/arch/arm/plat-omap/include/mach/dma.h
new file mode 100644
index 000000000000..54fe9665b182
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/dma.h
@@ -0,0 +1,570 @@
+/*
+ *  arch/arm/plat-omap/include/mach/dma.h
+ *
+ *  Copyright (C) 2003 Nokia Corporation
+ *  Author: Juha Yrjölä <juha.yrjola@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+/* Hardware registers for omap1 */
+#define OMAP1_DMA_BASE                  (0xfffed800)
+
+#define OMAP1_DMA_GCR                   0x400
+#define OMAP1_DMA_GSCR                  0x404
+#define OMAP1_DMA_GRST                  0x408
+#define OMAP1_DMA_HW_ID                 0x442
+#define OMAP1_DMA_PCH2_ID               0x444
+#define OMAP1_DMA_PCH0_ID               0x446
+#define OMAP1_DMA_PCH1_ID               0x448
+#define OMAP1_DMA_PCHG_ID               0x44a
+#define OMAP1_DMA_PCHD_ID               0x44c
+#define OMAP1_DMA_CAPS_0_U              0x44e
+#define OMAP1_DMA_CAPS_0_L              0x450
+#define OMAP1_DMA_CAPS_1_U              0x452
+#define OMAP1_DMA_CAPS_1_L              0x454
+#define OMAP1_DMA_CAPS_2                0x456
+#define OMAP1_DMA_CAPS_3                0x458
+#define OMAP1_DMA_CAPS_4                0x45a
+#define OMAP1_DMA_PCH2_SR               0x460
+#define OMAP1_DMA_PCH0_SR               0x480
+#define OMAP1_DMA_PCH1_SR               0x482
+#define OMAP1_DMA_PCHD_SR               0x4c0
+
+/* Hardware registers for omap2 and omap3 */
+#define OMAP24XX_DMA4_BASE              (L4_24XX_BASE + 0x56000)
+#define OMAP34XX_DMA4_BASE              (L4_34XX_BASE + 0x56000)
+
+#define OMAP_DMA4_REVISION              0x00
+#define OMAP_DMA4_GCR                   0x78
+#define OMAP_DMA4_IRQSTATUS_L0          0x08
+#define OMAP_DMA4_IRQSTATUS_L1          0x0c
+#define OMAP_DMA4_IRQSTATUS_L2          0x10
+#define OMAP_DMA4_IRQSTATUS_L3          0x14
+#define OMAP_DMA4_IRQENABLE_L0          0x18
+#define OMAP_DMA4_IRQENABLE_L1          0x1c
+#define OMAP_DMA4_IRQENABLE_L2          0x20
+#define OMAP_DMA4_IRQENABLE_L3          0x24
+#define OMAP_DMA4_SYSSTATUS             0x28
+#define OMAP_DMA4_OCP_SYSCONFIG         0x2c
+#define OMAP_DMA4_CAPS_0                0x64
+#define OMAP_DMA4_CAPS_2                0x6c
+#define OMAP_DMA4_CAPS_3                0x70
+#define OMAP_DMA4_CAPS_4                0x74
+
+#define OMAP1_LOGICAL_DMA_CH_COUNT      17
+#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT  32      /* REVISIT: Is this 32 + 2? */
+
+/* Common channel specific registers for omap1 */
+#define OMAP1_DMA_CH_BASE(n)            (0x40 * (n) + 0x00)
+#define OMAP1_DMA_CSDP(n)               (0x40 * (n) + 0x00)
+#define OMAP1_DMA_CCR(n)                (0x40 * (n) + 0x02)
+#define OMAP1_DMA_CICR(n)               (0x40 * (n) + 0x04)
+#define OMAP1_DMA_CSR(n)                (0x40 * (n) + 0x06)
+#define OMAP1_DMA_CEN(n)                (0x40 * (n) + 0x10)
+#define OMAP1_DMA_CFN(n)                (0x40 * (n) + 0x12)
+#define OMAP1_DMA_CSFI(n)               (0x40 * (n) + 0x14)
+#define OMAP1_DMA_CSEI(n)               (0x40 * (n) + 0x16)
+#define OMAP1_DMA_CPC(n)                (0x40 * (n) + 0x18)     /* 15xx only */
+#define OMAP1_DMA_CSAC(n)               (0x40 * (n) + 0x18)
+#define OMAP1_DMA_CDAC(n)               (0x40 * (n) + 0x1a)
+#define OMAP1_DMA_CDEI(n)               (0x40 * (n) + 0x1c)
+#define OMAP1_DMA_CDFI(n)               (0x40 * (n) + 0x1e)
+#define OMAP1_DMA_CLNK_CTRL(n)          (0x40 * (n) + 0x28)
+
+/* Common channel specific registers for omap2 */
+#define OMAP_DMA4_CH_BASE(n)            (0x60 * (n) + 0x80)
+#define OMAP_DMA4_CCR(n)                (0x60 * (n) + 0x80)
+#define OMAP_DMA4_CLNK_CTRL(n)          (0x60 * (n) + 0x84)
+#define OMAP_DMA4_CICR(n)               (0x60 * (n) + 0x88)
+#define OMAP_DMA4_CSR(n)                (0x60 * (n) + 0x8c)
+#define OMAP_DMA4_CSDP(n)               (0x60 * (n) + 0x90)
+#define OMAP_DMA4_CEN(n)                (0x60 * (n) + 0x94)
+#define OMAP_DMA4_CFN(n)                (0x60 * (n) + 0x98)
+#define OMAP_DMA4_CSEI(n)               (0x60 * (n) + 0xa4)
+#define OMAP_DMA4_CSFI(n)               (0x60 * (n) + 0xa8)
+#define OMAP_DMA4_CDEI(n)               (0x60 * (n) + 0xac)
+#define OMAP_DMA4_CDFI(n)               (0x60 * (n) + 0xb0)
+#define OMAP_DMA4_CSAC(n)               (0x60 * (n) + 0xb4)
+#define OMAP_DMA4_CDAC(n)               (0x60 * (n) + 0xb8)
+
+/* Channel specific registers only on omap1 */
+#define OMAP1_DMA_CSSA_L(n)             (0x40 * (n) + 0x08)
+#define OMAP1_DMA_CSSA_U(n)             (0x40 * (n) + 0x0a)
+#define OMAP1_DMA_CDSA_L(n)             (0x40 * (n) + 0x0c)
+#define OMAP1_DMA_CDSA_U(n)             (0x40 * (n) + 0x0e)
+#define OMAP1_DMA_COLOR_L(n)            (0x40 * (n) + 0x20)
+#define OMAP1_DMA_COLOR_U(n)            (0x40 * (n) + 0x22)
+#define OMAP1_DMA_CCR2(n)               (0x40 * (n) + 0x24)
+#define OMAP1_DMA_LCH_CTRL(n)           (0x40 * (n) + 0x2a)     /* not on 15xx */
+#define OMAP1_DMA_CCEN(n)               0
+#define OMAP1_DMA_CCFN(n)               0
+
+/* Channel specific registers only on omap2 */
+#define OMAP_DMA4_CSSA(n)               (0x60 * (n) + 0x9c)
+#define OMAP_DMA4_CDSA(n)               (0x60 * (n) + 0xa0)
+#define OMAP_DMA4_CCEN(n)               (0x60 * (n) + 0xbc)
+#define OMAP_DMA4_CCFN(n)               (0x60 * (n) + 0xc0)
+#define OMAP_DMA4_COLOR(n)              (0x60 * (n) + 0xc4)
+
+/* Dummy defines to keep multi-omap compiles happy */
+#define OMAP1_DMA_REVISION              0
+#define OMAP1_DMA_IRQSTATUS_L0          0
+#define OMAP1_DMA_IRQENABLE_L0          0
+#define OMAP1_DMA_OCP_SYSCONFIG         0
+#define OMAP_DMA4_HW_ID                 0
+#define OMAP_DMA4_CAPS_0_L              0
+#define OMAP_DMA4_CAPS_0_U              0
+#define OMAP_DMA4_CAPS_1_L              0
+#define OMAP_DMA4_CAPS_1_U              0
+#define OMAP_DMA4_GSCR                  0
+#define OMAP_DMA4_CPC(n)                0
+
+#define OMAP_DMA4_LCH_CTRL(n)           0
+#define OMAP_DMA4_COLOR_L(n)            0
+#define OMAP_DMA4_COLOR_U(n)            0
+#define OMAP_DMA4_CCR2(n)               0
+#define OMAP1_DMA_CSSA(n)               0
+#define OMAP1_DMA_CDSA(n)               0
+#define OMAP_DMA4_CSSA_L(n)             0
+#define OMAP_DMA4_CSSA_U(n)             0
+#define OMAP_DMA4_CDSA_L(n)             0
+#define OMAP_DMA4_CDSA_U(n)             0
+
+/*----------------------------------------------------------------------------*/
+
+/* DMA channels for omap1 */
+#define OMAP_DMA_NO_DEVICE              0
+#define OMAP_DMA_MCSI1_TX               1
+#define OMAP_DMA_MCSI1_RX               2
+#define OMAP_DMA_I2C_RX                 3
+#define OMAP_DMA_I2C_TX                 4
+#define OMAP_DMA_EXT_NDMA_REQ           5
+#define OMAP_DMA_EXT_NDMA_REQ2          6
+#define OMAP_DMA_UWIRE_TX               7
+#define OMAP_DMA_MCBSP1_TX              8
+#define OMAP_DMA_MCBSP1_RX              9
+#define OMAP_DMA_MCBSP3_TX              10
+#define OMAP_DMA_MCBSP3_RX              11
+#define OMAP_DMA_UART1_TX               12
+#define OMAP_DMA_UART1_RX               13
+#define OMAP_DMA_UART2_TX               14
+#define OMAP_DMA_UART2_RX               15
+#define OMAP_DMA_MCBSP2_TX              16
+#define OMAP_DMA_MCBSP2_RX              17
+#define OMAP_DMA_UART3_TX               18
+#define OMAP_DMA_UART3_RX               19
+#define OMAP_DMA_CAMERA_IF_RX           20
+#define OMAP_DMA_MMC_TX                 21
+#define OMAP_DMA_MMC_RX                 22
+#define OMAP_DMA_NAND                   23
+#define OMAP_DMA_IRQ_LCD_LINE           24
+#define OMAP_DMA_MEMORY_STICK           25
+#define OMAP_DMA_USB_W2FC_RX0           26
+#define OMAP_DMA_USB_W2FC_RX1           27
+#define OMAP_DMA_USB_W2FC_RX2           28
+#define OMAP_DMA_USB_W2FC_TX0           29
+#define OMAP_DMA_USB_W2FC_TX1           30
+#define OMAP_DMA_USB_W2FC_TX2           31
+
+/* These are only for 1610 */
+#define OMAP_DMA_CRYPTO_DES_IN          32
+#define OMAP_DMA_SPI_TX                 33
+#define OMAP_DMA_SPI_RX                 34
+#define OMAP_DMA_CRYPTO_HASH            35
+#define OMAP_DMA_CCP_ATTN               36
+#define OMAP_DMA_CCP_FIFO_NOT_EMPTY     37
+#define OMAP_DMA_CMT_APE_TX_CHAN_0      38
+#define OMAP_DMA_CMT_APE_RV_CHAN_0      39
+#define OMAP_DMA_CMT_APE_TX_CHAN_1      40
+#define OMAP_DMA_CMT_APE_RV_CHAN_1      41
+#define OMAP_DMA_CMT_APE_TX_CHAN_2      42
+#define OMAP_DMA_CMT_APE_RV_CHAN_2      43
+#define OMAP_DMA_CMT_APE_TX_CHAN_3      44
+#define OMAP_DMA_CMT_APE_RV_CHAN_3      45
+#define OMAP_DMA_CMT_APE_TX_CHAN_4      46
+#define OMAP_DMA_CMT_APE_RV_CHAN_4      47
+#define OMAP_DMA_CMT_APE_TX_CHAN_5      48
+#define OMAP_DMA_CMT_APE_RV_CHAN_5      49
+#define OMAP_DMA_CMT_APE_TX_CHAN_6      50
+#define OMAP_DMA_CMT_APE_RV_CHAN_6      51
+#define OMAP_DMA_CMT_APE_TX_CHAN_7      52
+#define OMAP_DMA_CMT_APE_RV_CHAN_7      53
+#define OMAP_DMA_MMC2_TX                54
+#define OMAP_DMA_MMC2_RX                55
+#define OMAP_DMA_CRYPTO_DES_OUT         56
+
+/* DMA channels for 24xx */
+#define OMAP24XX_DMA_NO_DEVICE          0
+#define OMAP24XX_DMA_XTI_DMA            1       /* S_DMA_0 */
+#define OMAP24XX_DMA_EXT_DMAREQ0        2       /* S_DMA_1 */
+#define OMAP24XX_DMA_EXT_DMAREQ1        3       /* S_DMA_2 */
+#define OMAP24XX_DMA_GPMC               4       /* S_DMA_3 */
+#define OMAP24XX_DMA_GFX                5       /* S_DMA_4 */
+#define OMAP24XX_DMA_DSS                6       /* S_DMA_5 */
+#define OMAP242X_DMA_VLYNQ_TX           7       /* S_DMA_6 */
+#define OMAP24XX_DMA_EXT_DMAREQ2        7       /* S_DMA_6 */
+#define OMAP24XX_DMA_CWT                8       /* S_DMA_7 */
+#define OMAP24XX_DMA_AES_TX             9       /* S_DMA_8 */
+#define OMAP24XX_DMA_AES_RX             10      /* S_DMA_9 */
+#define OMAP24XX_DMA_DES_TX             11      /* S_DMA_10 */
+#define OMAP24XX_DMA_DES_RX             12      /* S_DMA_11 */
+#define OMAP24XX_DMA_SHA1MD5_RX         13      /* S_DMA_12 */
+#define OMAP34XX_DMA_SHA2MD5_RX         13      /* S_DMA_12 */
+#define OMAP242X_DMA_EXT_DMAREQ2        14      /* S_DMA_13 */
+#define OMAP242X_DMA_EXT_DMAREQ3        15      /* S_DMA_14 */
+#define OMAP242X_DMA_EXT_DMAREQ4        16      /* S_DMA_15 */
+#define OMAP242X_DMA_EAC_AC_RD          17      /* S_DMA_16 */
+#define OMAP242X_DMA_EAC_AC_WR          18      /* S_DMA_17 */
+#define OMAP242X_DMA_EAC_MD_UL_RD       19      /* S_DMA_18 */
+#define OMAP242X_DMA_EAC_MD_UL_WR       20      /* S_DMA_19 */
+#define OMAP242X_DMA_EAC_MD_DL_RD       21      /* S_DMA_20 */
+#define OMAP242X_DMA_EAC_MD_DL_WR       22      /* S_DMA_21 */
+#define OMAP242X_DMA_EAC_BT_UL_RD       23      /* S_DMA_22 */
+#define OMAP242X_DMA_EAC_BT_UL_WR       24      /* S_DMA_23 */
+#define OMAP242X_DMA_EAC_BT_DL_RD       25      /* S_DMA_24 */
+#define OMAP242X_DMA_EAC_BT_DL_WR       26      /* S_DMA_25 */
+#define OMAP243X_DMA_EXT_DMAREQ3        14      /* S_DMA_13 */
+#define OMAP24XX_DMA_SPI3_TX0           15      /* S_DMA_14 */
+#define OMAP24XX_DMA_SPI3_RX0           16      /* S_DMA_15 */
+#define OMAP24XX_DMA_MCBSP3_TX          17      /* S_DMA_16 */
+#define OMAP24XX_DMA_MCBSP3_RX          18      /* S_DMA_17 */
+#define OMAP24XX_DMA_MCBSP4_TX          19      /* S_DMA_18 */
+#define OMAP24XX_DMA_MCBSP4_RX          20      /* S_DMA_19 */
+#define OMAP24XX_DMA_MCBSP5_TX          21      /* S_DMA_20 */
+#define OMAP24XX_DMA_MCBSP5_RX          22      /* S_DMA_21 */
+#define OMAP24XX_DMA_SPI3_TX1           23      /* S_DMA_22 */
+#define OMAP24XX_DMA_SPI3_RX1           24      /* S_DMA_23 */
+#define OMAP243X_DMA_EXT_DMAREQ4        25      /* S_DMA_24 */
+#define OMAP243X_DMA_EXT_DMAREQ5        26      /* S_DMA_25 */
+#define OMAP34XX_DMA_I2C3_TX            25      /* S_DMA_24 */
+#define OMAP34XX_DMA_I2C3_RX            26      /* S_DMA_25 */
+#define OMAP24XX_DMA_I2C1_TX            27      /* S_DMA_26 */
+#define OMAP24XX_DMA_I2C1_RX            28      /* S_DMA_27 */
+#define OMAP24XX_DMA_I2C2_TX            29      /* S_DMA_28 */
+#define OMAP24XX_DMA_I2C2_RX            30      /* S_DMA_29 */
+#define OMAP24XX_DMA_MCBSP1_TX          31      /* S_DMA_30 */
+#define OMAP24XX_DMA_MCBSP1_RX          32      /* S_DMA_31 */
+#define OMAP24XX_DMA_MCBSP2_TX          33      /* S_DMA_32 */
+#define OMAP24XX_DMA_MCBSP2_RX          34      /* S_DMA_33 */
+#define OMAP24XX_DMA_SPI1_TX0           35      /* S_DMA_34 */
+#define OMAP24XX_DMA_SPI1_RX0           36      /* S_DMA_35 */
+#define OMAP24XX_DMA_SPI1_TX1           37      /* S_DMA_36 */
+#define OMAP24XX_DMA_SPI1_RX1           38      /* S_DMA_37 */
+#define OMAP24XX_DMA_SPI1_TX2           39      /* S_DMA_38 */
+#define OMAP24XX_DMA_SPI1_RX2           40      /* S_DMA_39 */
+#define OMAP24XX_DMA_SPI1_TX3           41      /* S_DMA_40 */
+#define OMAP24XX_DMA_SPI1_RX3           42      /* S_DMA_41 */
+#define OMAP24XX_DMA_SPI2_TX0           43      /* S_DMA_42 */
+#define OMAP24XX_DMA_SPI2_RX0           44      /* S_DMA_43 */
+#define OMAP24XX_DMA_SPI2_TX1           45      /* S_DMA_44 */
+#define OMAP24XX_DMA_SPI2_RX1           46      /* S_DMA_45 */
+#define OMAP24XX_DMA_MMC2_TX            47      /* S_DMA_46 */
+#define OMAP24XX_DMA_MMC2_RX            48      /* S_DMA_47 */
+#define OMAP24XX_DMA_UART1_TX           49      /* S_DMA_48 */
+#define OMAP24XX_DMA_UART1_RX           50      /* S_DMA_49 */
+#define OMAP24XX_DMA_UART2_TX           51      /* S_DMA_50 */
+#define OMAP24XX_DMA_UART2_RX           52      /* S_DMA_51 */
+#define OMAP24XX_DMA_UART3_TX           53      /* S_DMA_52 */
+#define OMAP24XX_DMA_UART3_RX           54      /* S_DMA_53 */
+#define OMAP24XX_DMA_USB_W2FC_TX0       55      /* S_DMA_54 */
+#define OMAP24XX_DMA_USB_W2FC_RX0       56      /* S_DMA_55 */
+#define OMAP24XX_DMA_USB_W2FC_TX1       57      /* S_DMA_56 */
+#define OMAP24XX_DMA_USB_W2FC_RX1       58      /* S_DMA_57 */
+#define OMAP24XX_DMA_USB_W2FC_TX2       59      /* S_DMA_58 */
+#define OMAP24XX_DMA_USB_W2FC_RX2       60      /* S_DMA_59 */
+#define OMAP24XX_DMA_MMC1_TX            61      /* S_DMA_60 */
+#define OMAP24XX_DMA_MMC1_RX            62      /* S_DMA_61 */
+#define OMAP24XX_DMA_MS                 63      /* S_DMA_62 */
+#define OMAP242X_DMA_EXT_DMAREQ5        64      /* S_DMA_63 */
+#define OMAP243X_DMA_EXT_DMAREQ6        64      /* S_DMA_63 */
+#define OMAP34XX_DMA_EXT_DMAREQ3        64      /* S_DMA_63 */
+#define OMAP34XX_DMA_AES2_TX            65      /* S_DMA_64 */
+#define OMAP34XX_DMA_AES2_RX            66      /* S_DMA_65 */
+#define OMAP34XX_DMA_DES2_TX            67      /* S_DMA_66 */
+#define OMAP34XX_DMA_DES2_RX            68      /* S_DMA_67 */
+#define OMAP34XX_DMA_SHA1MD5_RX         69      /* S_DMA_68 */
+#define OMAP34XX_DMA_SPI4_TX0           70      /* S_DMA_69 */
+#define OMAP34XX_DMA_SPI4_RX0           71      /* S_DMA_70 */
+#define OMAP34XX_DSS_DMA0               72      /* S_DMA_71 */
+#define OMAP34XX_DSS_DMA1               73      /* S_DMA_72 */
+#define OMAP34XX_DSS_DMA2               74      /* S_DMA_73 */
+#define OMAP34XX_DSS_DMA3               75      /* S_DMA_74 */
+#define OMAP34XX_DMA_MMC3_TX            77      /* S_DMA_76 */
+#define OMAP34XX_DMA_MMC3_RX            78      /* S_DMA_77 */
+#define OMAP34XX_DMA_USIM_TX            79      /* S_DMA_78 */
+#define OMAP34XX_DMA_USIM_RX            80      /* S_DMA_79 */
+
+/*----------------------------------------------------------------------------*/
+
+/* Hardware registers for LCD DMA */
+#define OMAP1510_DMA_LCD_BASE           (0xfffedb00)
+#define OMAP1510_DMA_LCD_CTRL           (OMAP1510_DMA_LCD_BASE + 0x00)
+#define OMAP1510_DMA_LCD_TOP_F1_L       (OMAP1510_DMA_LCD_BASE + 0x02)
+#define OMAP1510_DMA_LCD_TOP_F1_U       (OMAP1510_DMA_LCD_BASE + 0x04)
+#define OMAP1510_DMA_LCD_BOT_F1_L       (OMAP1510_DMA_LCD_BASE + 0x06)
+#define OMAP1510_DMA_LCD_BOT_F1_U       (OMAP1510_DMA_LCD_BASE + 0x08)
+
+#define OMAP1610_DMA_LCD_BASE           (0xfffee300)
+#define OMAP1610_DMA_LCD_CSDP           (OMAP1610_DMA_LCD_BASE + 0xc0)
+#define OMAP1610_DMA_LCD_CCR            (OMAP1610_DMA_LCD_BASE + 0xc2)
+#define OMAP1610_DMA_LCD_CTRL           (OMAP1610_DMA_LCD_BASE + 0xc4)
+#define OMAP1610_DMA_LCD_TOP_B1_L       (OMAP1610_DMA_LCD_BASE + 0xc8)
+#define OMAP1610_DMA_LCD_TOP_B1_U       (OMAP1610_DMA_LCD_BASE + 0xca)
+#define OMAP1610_DMA_LCD_BOT_B1_L       (OMAP1610_DMA_LCD_BASE + 0xcc)
+#define OMAP1610_DMA_LCD_BOT_B1_U       (OMAP1610_DMA_LCD_BASE + 0xce)
+#define OMAP1610_DMA_LCD_TOP_B2_L       (OMAP1610_DMA_LCD_BASE + 0xd0)
+#define OMAP1610_DMA_LCD_TOP_B2_U       (OMAP1610_DMA_LCD_BASE + 0xd2)
+#define OMAP1610_DMA_LCD_BOT_B2_L       (OMAP1610_DMA_LCD_BASE + 0xd4)
+#define OMAP1610_DMA_LCD_BOT_B2_U       (OMAP1610_DMA_LCD_BASE + 0xd6)
+#define OMAP1610_DMA_LCD_SRC_EI_B1      (OMAP1610_DMA_LCD_BASE + 0xd8)
+#define OMAP1610_DMA_LCD_SRC_FI_B1_L    (OMAP1610_DMA_LCD_BASE + 0xda)
+#define OMAP1610_DMA_LCD_SRC_EN_B1      (OMAP1610_DMA_LCD_BASE + 0xe0)
+#define OMAP1610_DMA_LCD_SRC_FN_B1      (OMAP1610_DMA_LCD_BASE + 0xe4)
+#define OMAP1610_DMA_LCD_LCH_CTRL       (OMAP1610_DMA_LCD_BASE + 0xea)
+#define OMAP1610_DMA_LCD_SRC_FI_B1_U    (OMAP1610_DMA_LCD_BASE + 0xf4)
+
+#define OMAP1_DMA_TOUT_IRQ              (1 << 0)
+#define OMAP_DMA_DROP_IRQ               (1 << 1)
+#define OMAP_DMA_HALF_IRQ               (1 << 2)
+#define OMAP_DMA_FRAME_IRQ              (1 << 3)
+#define OMAP_DMA_LAST_IRQ               (1 << 4)
+#define OMAP_DMA_BLOCK_IRQ              (1 << 5)
+#define OMAP1_DMA_SYNC_IRQ              (1 << 6)
+#define OMAP2_DMA_PKT_IRQ               (1 << 7)
+#define OMAP2_DMA_TRANS_ERR_IRQ         (1 << 8)
+#define OMAP2_DMA_SECURE_ERR_IRQ        (1 << 9)
+#define OMAP2_DMA_SUPERVISOR_ERR_IRQ    (1 << 10)
+#define OMAP2_DMA_MISALIGNED_ERR_IRQ    (1 << 11)
+
+#define OMAP_DMA_DATA_TYPE_S8           0x00
+#define OMAP_DMA_DATA_TYPE_S16          0x01
+#define OMAP_DMA_DATA_TYPE_S32          0x02
+
+#define OMAP_DMA_SYNC_ELEMENT           0x00
+#define OMAP_DMA_SYNC_FRAME             0x01
+#define OMAP_DMA_SYNC_BLOCK             0x02
+#define OMAP_DMA_SYNC_PACKET            0x03
+
+#define OMAP_DMA_SRC_SYNC               0x01
+#define OMAP_DMA_DST_SYNC               0x00
+
+#define OMAP_DMA_PORT_EMIFF             0x00
+#define OMAP_DMA_PORT_EMIFS             0x01
+#define OMAP_DMA_PORT_OCP_T1            0x02
+#define OMAP_DMA_PORT_TIPB              0x03
+#define OMAP_DMA_PORT_OCP_T2            0x04
+#define OMAP_DMA_PORT_MPUI              0x05
+
+#define OMAP_DMA_AMODE_CONSTANT         0x00
+#define OMAP_DMA_AMODE_POST_INC         0x01
+#define OMAP_DMA_AMODE_SINGLE_IDX       0x02
+#define OMAP_DMA_AMODE_DOUBLE_IDX       0x03
+
+#define DMA_DEFAULT_FIFO_DEPTH          0x10
+#define DMA_DEFAULT_ARB_RATE            0x01
+/* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
+#define DMA_THREAD_RESERVE_NORM         (0x00 << 12) /* Def */
+#define DMA_THREAD_RESERVE_ONET         (0x01 << 12)
+#define DMA_THREAD_RESERVE_TWOT         (0x02 << 12)
+#define DMA_THREAD_RESERVE_THREET       (0x03 << 12)
+#define DMA_THREAD_FIFO_NONE            (0x00 << 14) /* Def */
+#define DMA_THREAD_FIFO_75              (0x01 << 14)
+#define DMA_THREAD_FIFO_25              (0x02 << 14)
+#define DMA_THREAD_FIFO_50              (0x03 << 14)
+
+/* Chaining modes*/
+#ifndef CONFIG_ARCH_OMAP1
+#define OMAP_DMA_STATIC_CHAIN           0x1
+#define OMAP_DMA_DYNAMIC_CHAIN          0x2
+#define OMAP_DMA_CHAIN_ACTIVE           0x1
+#define OMAP_DMA_CHAIN_INACTIVE         0x0
+#endif
+
+#define DMA_CH_PRIO_HIGH                0x1
+#define DMA_CH_PRIO_LOW                 0x0 /* Def */
+
+/* LCD DMA block numbers */
+enum {
+        OMAP_LCD_DMA_B1_TOP,
+        OMAP_LCD_DMA_B1_BOTTOM,
+        OMAP_LCD_DMA_B2_TOP,
+        OMAP_LCD_DMA_B2_BOTTOM
+};
+
+enum omap_dma_burst_mode {
+        OMAP_DMA_DATA_BURST_DIS = 0,
+        OMAP_DMA_DATA_BURST_4,
+        OMAP_DMA_DATA_BURST_8,
+        OMAP_DMA_DATA_BURST_16,
+};
+
+enum end_type {
+        OMAP_DMA_LITTLE_ENDIAN = 0,
+        OMAP_DMA_BIG_ENDIAN
+};
+
+enum omap_dma_color_mode {
+        OMAP_DMA_COLOR_DIS = 0,
+        OMAP_DMA_CONSTANT_FILL,
+        OMAP_DMA_TRANSPARENT_COPY
+};
+
+enum omap_dma_write_mode {
+        OMAP_DMA_WRITE_NON_POSTED = 0,
+        OMAP_DMA_WRITE_POSTED,
+        OMAP_DMA_WRITE_LAST_NON_POSTED
+};
+
+enum omap_dma_channel_mode {
+        OMAP_DMA_LCH_2D = 0,
+        OMAP_DMA_LCH_G,
+        OMAP_DMA_LCH_P,
+        OMAP_DMA_LCH_PD
+};
+
+struct omap_dma_channel_params {
+        int data_type;          /* data type 8,16,32 */
+        int elem_count;         /* number of elements in a frame */
+        int frame_count;        /* number of frames in a element */
+
+        int src_port;           /* Only on OMAP1 REVISIT: Is this needed? */
+        int src_amode;          /* constant, post increment, indexed,
+                                        double indexed */
+        unsigned long src_start;        /* source address : physical */
+        int src_ei;             /* source element index */
+        int src_fi;             /* source frame index */
+
+        int dst_port;           /* Only on OMAP1 REVISIT: Is this needed? */
+        int dst_amode;          /* constant, post increment, indexed,
+                                        double indexed */
+        unsigned long dst_start;        /* source address : physical */
+        int dst_ei;             /* source element index */
+        int dst_fi;             /* source frame index */
+
+        int trigger;            /* trigger attached if the channel is
+                                        synchronized */
+        int sync_mode;          /* sycn on element, frame , block or packet */
+        int src_or_dst_synch;   /* source synch(1) or destination synch(0) */
+
+        int ie;                 /* interrupt enabled */
+
+        unsigned char read_prio;/* read priority */
+        unsigned char write_prio;/* write priority */
+
+#ifndef CONFIG_ARCH_OMAP1
+        enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
+#endif
+};
+
+
+extern void omap_set_dma_priority(int lch, int dst_port, int priority);
+extern int omap_request_dma(int dev_id, const char *dev_name,
+                        void (*callback)(int lch, u16 ch_status, void *data),
+                        void *data, int *dma_ch);
+extern void omap_enable_dma_irq(int ch, u16 irq_bits);
+extern void omap_disable_dma_irq(int ch, u16 irq_bits);
+extern void omap_free_dma(int ch);
+extern void omap_start_dma(int lch);
+extern void omap_stop_dma(int lch);
+extern void omap_set_dma_transfer_params(int lch, int data_type,
+                                         int elem_count, int frame_count,
+                                         int sync_mode,
+                                         int dma_trigger, int src_or_dst_synch);
+extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
+                                    u32 color);
+extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
+extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
+
+extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
+                                    unsigned long src_start,
+                                    int src_ei, int src_fi);
+extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
+extern void omap_set_dma_src_data_pack(int lch, int enable);
+extern void omap_set_dma_src_burst_mode(int lch,
+                                        enum omap_dma_burst_mode burst_mode);
+
+extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
+                                     unsigned long dest_start,
+                                     int dst_ei, int dst_fi);
+extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
+extern void omap_set_dma_dest_data_pack(int lch, int enable);
+extern void omap_set_dma_dest_burst_mode(int lch,
+                                         enum omap_dma_burst_mode burst_mode);
+
+extern void omap_set_dma_params(int lch,
+                                struct omap_dma_channel_params *params);
+
+extern void omap_dma_link_lch(int lch_head, int lch_queue);
+extern void omap_dma_unlink_lch(int lch_head, int lch_queue);
+
+extern int omap_set_dma_callback(int lch,
+                        void (*callback)(int lch, u16 ch_status, void *data),
+                        void *data);
+extern dma_addr_t omap_get_dma_src_pos(int lch);
+extern dma_addr_t omap_get_dma_dst_pos(int lch);
+extern void omap_clear_dma(int lch);
+extern int omap_get_dma_active_status(int lch);
+extern int omap_dma_running(void);
+extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
+                                       int tparams);
+extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
+                                 unsigned char write_prio);
+extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
+extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
+extern int omap_get_dma_index(int lch, int *ei, int *fi);
+
+/* Chaining APIs */
+#ifndef CONFIG_ARCH_OMAP1
+extern int omap_request_dma_chain(int dev_id, const char *dev_name,
+                                  void (*callback) (int chain_id, u16 ch_status,
+                                                    void *data),
+                                  int *chain_id, int no_of_chans,
+                                  int chain_mode,
+                                  struct omap_dma_channel_params params);
+extern int omap_free_dma_chain(int chain_id);
+extern int omap_dma_chain_a_transfer(int chain_id, int src_start,
+                                     int dest_start, int elem_count,
+                                     int frame_count, void *callbk_data);
+extern int omap_start_dma_chain_transfers(int chain_id);
+extern int omap_stop_dma_chain_transfers(int chain_id);
+extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi);
+extern int omap_get_dma_chain_dst_pos(int chain_id);
+extern int omap_get_dma_chain_src_pos(int chain_id);
+
+extern int omap_modify_dma_chain_params(int chain_id,
+                                        struct omap_dma_channel_params params);
+extern int omap_dma_chain_status(int chain_id);
+#endif
+
+/* LCD DMA functions */
+extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
+                                void *data);
+extern void omap_free_lcd_dma(void);
+extern void omap_setup_lcd_dma(void);
+extern void omap_enable_lcd_dma(void);
+extern void omap_stop_lcd_dma(void);
+extern void omap_set_lcd_dma_ext_controller(int external);
+extern void omap_set_lcd_dma_single_transfer(int single);
+extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
+                                int data_type);
+extern void omap_set_lcd_dma_b1_rotation(int rotate);
+extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres);
+extern void omap_set_lcd_dma_b1_mirror(int mirror);
+extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale);
+
+#endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/plat-omap/include/mach/dmtimer.h b/arch/arm/plat-omap/include/mach/dmtimer.h
new file mode 100644
index 000000000000..6dc703138210
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/dmtimer.h
@@ -0,0 +1,84 @@
+/*
+ * arch/arm/plat-omap/include/mach/dmtimer.h
+ *
+ * OMAP Dual-Mode Timers
+ *
+ * Copyright (C) 2005 Nokia Corporation
+ * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
+ * PWM and clock framwork support by Timo Teras.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_DMTIMER_H
+#define __ASM_ARCH_DMTIMER_H
+
+/* clock sources */
+#define OMAP_TIMER_SRC_SYS_CLK                  0x00
+#define OMAP_TIMER_SRC_32_KHZ                   0x01
+#define OMAP_TIMER_SRC_EXT_CLK                  0x02
+
+/* timer interrupt enable bits */
+#define OMAP_TIMER_INT_CAPTURE                  (1 << 2)
+#define OMAP_TIMER_INT_OVERFLOW                 (1 << 1)
+#define OMAP_TIMER_INT_MATCH                    (1 << 0)
+
+/* trigger types */
+#define OMAP_TIMER_TRIGGER_NONE                 0x00
+#define OMAP_TIMER_TRIGGER_OVERFLOW             0x01
+#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
+
+struct omap_dm_timer;
+struct clk;
+
+int omap_dm_timer_init(void);
+
+struct omap_dm_timer *omap_dm_timer_request(void);
+struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
+void omap_dm_timer_free(struct omap_dm_timer *timer);
+void omap_dm_timer_enable(struct omap_dm_timer *timer);
+void omap_dm_timer_disable(struct omap_dm_timer *timer);
+
+int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
+
+u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
+struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
+
+void omap_dm_timer_trigger(struct omap_dm_timer *timer);
+void omap_dm_timer_start(struct omap_dm_timer *timer);
+void omap_dm_timer_stop(struct omap_dm_timer *timer);
+
+void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
+void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
+void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
+void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
+void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
+void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
+
+void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
+
+unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
+void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
+unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
+void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
+
+int omap_dm_timers_active(void);
+
+
+#endif /* __ASM_ARCH_DMTIMER_H */
diff --git a/include/asm-arm/arch-omap/dsp_common.h b/arch/arm/plat-omap/include/mach/dsp_common.h
index da97736f3efa..da97736f3efa 100644
--- a/include/asm-arm/arch-omap/dsp_common.h
+++ b/arch/arm/plat-omap/include/mach/dsp_common.h
diff --git a/arch/arm/plat-omap/include/mach/eac.h b/arch/arm/plat-omap/include/mach/eac.h
new file mode 100644
index 000000000000..9e62cf030270
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/eac.h
@@ -0,0 +1,100 @@
+/*
+ * arch/arm/plat-omap/include/mach2/eac.h
+ *
+ * Defines for Enhanced Audio Controller
+ *
+ * Contact: Jarkko Nikula <jarkko.nikula@nokia.com>
+ *
+ * Copyright (C) 2006 Nokia Corporation
+ * Copyright (C) 2004 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_OMAP2_EAC_H
+#define __ASM_ARM_ARCH_OMAP2_EAC_H
+
+#include <mach/io.h>
+#include <mach/hardware.h>
+#include <asm/irq.h>
+
+#include <sound/core.h>
+
+/* master codec clock source */
+#define EAC_MCLK_EXT_MASK       0x100
+enum eac_mclk_src {
+        EAC_MCLK_INT_11290000, /* internal 96 MHz / 8.5 = 11.29 Mhz */
+        EAC_MCLK_EXT_11289600 = EAC_MCLK_EXT_MASK,
+        EAC_MCLK_EXT_12288000,
+        EAC_MCLK_EXT_2x11289600,
+        EAC_MCLK_EXT_2x12288000,
+};
+
+/* codec port interface mode */
+enum eac_codec_mode {
+        EAC_CODEC_PCM,
+        EAC_CODEC_AC97,
+        EAC_CODEC_I2S_MASTER, /* codec port, I.e. EAC is the master */
+        EAC_CODEC_I2S_SLAVE,
+};
+
+/* configuration structure for I2S mode */
+struct eac_i2s_conf {
+        /* if enabled, then first data slot (left channel) is signaled as
+         * positive level of frame sync EAC.AC_FS */
+        unsigned        polarity_changed_mode:1;
+        /* if enabled, then serial data starts one clock cycle after the
+         * of EAC.AC_FS for first audio slot */
+        unsigned        sync_delay_enable:1;
+};
+
+/* configuration structure for EAC codec port */
+struct eac_codec {
+        enum eac_mclk_src       mclk_src;
+
+        enum eac_codec_mode     codec_mode;
+        union {
+                struct eac_i2s_conf     i2s;
+        } codec_conf;
+
+        int             default_rate; /* audio sampling rate */
+
+        int             (* set_power)(void *private_data, int dac, int adc);
+        int             (* register_controls)(void *private_data,
+                                              struct snd_card *card);
+        const char      *short_name;
+
+        void            *private_data;
+};
+
+/* structure for passing platform dependent data to the EAC driver */
+struct eac_platform_data {
+        int     (* init)(struct device *eac_dev);
+        void    (* cleanup)(struct device *eac_dev);
+        /* these callbacks are used to configure & control external MCLK
+         * source. NULL if not used */
+        int     (* enable_ext_clocks)(struct device *eac_dev);
+        void    (* disable_ext_clocks)(struct device *eac_dev);
+};
+
+extern void omap_init_eac(struct eac_platform_data *pdata);
+
+extern int eac_register_codec(struct device *eac_dev, struct eac_codec *codec);
+extern void eac_unregister_codec(struct device *eac_dev);
+
+extern int eac_set_mode(struct device *eac_dev, int play, int rec);
+
+#endif /* __ASM_ARM_ARCH_OMAP2_EAC_H */
diff --git a/arch/arm/plat-omap/include/mach/entry-macro.S b/arch/arm/plat-omap/include/mach/entry-macro.S
new file mode 100644
index 000000000000..d4e9043bf201
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/entry-macro.S
@@ -0,0 +1,89 @@
+/*
+ * arch/arm/plat-omap/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for OMAP-based platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <mach/hardware.h>
+#include <mach/io.h>
+#include <mach/irqs.h>
+
+#if defined(CONFIG_ARCH_OMAP1)
+
+#if defined(CONFIG_ARCH_OMAP730) && \
+        (defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX))
+#error "FIXME: OMAP730 doesn't support multiple-OMAP"
+#elif defined(CONFIG_ARCH_OMAP730)
+#define INT_IH2_IRQ             INT_730_IH2_IRQ
+#elif defined(CONFIG_ARCH_OMAP15XX)
+#define INT_IH2_IRQ             INT_1510_IH2_IRQ
+#elif defined(CONFIG_ARCH_OMAP16XX)
+#define INT_IH2_IRQ             INT_1610_IH2_IRQ
+#else
+#warning "IH2 IRQ defaulted"
+#define INT_IH2_IRQ             INT_1510_IH2_IRQ
+#endif
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_preamble, base, tmp
+                .endm
+
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                ldr     \base, =IO_ADDRESS(OMAP_IH1_BASE)
+                ldr     \irqnr, [\base, #IRQ_ITR_REG_OFFSET]
+                ldr     \tmp, [\base, #IRQ_MIR_REG_OFFSET]
+                mov     \irqstat, #0xffffffff
+                bic     \tmp, \irqstat, \tmp
+                tst     \irqnr, \tmp
+                beq     1510f
+
+                ldr     \irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET]
+                cmp     \irqnr, #0
+                ldreq   \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
+                cmpeq   \irqnr, #INT_IH2_IRQ
+                ldreq   \base, =IO_ADDRESS(OMAP_IH2_BASE)
+                ldreq   \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
+                addeqs  \irqnr, \irqnr, #32
+1510:
+                .endm
+
+#elif defined(CONFIG_ARCH_OMAP24XX)
+
+#include <mach/omap24xx.h>
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_preamble, base, tmp
+                .endm
+
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                ldr     \base, =OMAP2_VA_IC_BASE
+                ldr     \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
+                cmp     \irqnr, #0x0
+                bne     2222f
+                ldr     \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
+                cmp     \irqnr, #0x0
+                bne     2222f
+                ldr     \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
+                cmp     \irqnr, #0x0
+2222:
+                ldrne   \irqnr, [\base, #IRQ_SIR_IRQ]
+
+                .endm
+
+                .macro  irq_prio_table
+                .endm
+
+#endif
diff --git a/arch/arm/plat-omap/include/mach/fpga.h b/arch/arm/plat-omap/include/mach/fpga.h
new file mode 100644
index 000000000000..c92e4b42b289
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/fpga.h
@@ -0,0 +1,197 @@
+/*
+ * arch/arm/plat-omap/include/mach/fpga.h
+ *
+ * Interrupt handler for OMAP-1510 FPGA
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * Copyright (C) 2002 MontaVista Software, Inc.
+ *
+ * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
+ * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_OMAP_FPGA_H
+#define __ASM_ARCH_OMAP_FPGA_H
+
+#if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
+extern void omap1510_fpga_init_irq(void);
+#else
+#define omap1510_fpga_init_irq()        (0)
+#endif
+
+#define fpga_read(reg)                  __raw_readb(reg)
+#define fpga_write(val, reg)            __raw_writeb(val, reg)
+
+/*
+ * ---------------------------------------------------------------------------
+ *  H2/P2 Debug board FPGA
+ * ---------------------------------------------------------------------------
+ */
+/* maps in the FPGA registers and the ETHR registers */
+#define H2P2_DBG_FPGA_BASE              0xE8000000      /* VA */
+#define H2P2_DBG_FPGA_SIZE              SZ_4K           /* SIZE */
+#define H2P2_DBG_FPGA_START             0x04000000      /* PA */
+
+#define H2P2_DBG_FPGA_ETHR_START        (H2P2_DBG_FPGA_START + 0x300)
+#define H2P2_DBG_FPGA_FPGA_REV          (H2P2_DBG_FPGA_BASE + 0x10)     /* FPGA Revision */
+#define H2P2_DBG_FPGA_BOARD_REV         (H2P2_DBG_FPGA_BASE + 0x12)     /* Board Revision */
+#define H2P2_DBG_FPGA_GPIO              (H2P2_DBG_FPGA_BASE + 0x14)     /* GPIO outputs */
+#define H2P2_DBG_FPGA_LEDS              (H2P2_DBG_FPGA_BASE + 0x16)     /* LEDs outputs */
+#define H2P2_DBG_FPGA_MISC_INPUTS       (H2P2_DBG_FPGA_BASE + 0x18)     /* Misc inputs */
+#define H2P2_DBG_FPGA_LAN_STATUS        (H2P2_DBG_FPGA_BASE + 0x1A)     /* LAN Status line */
+#define H2P2_DBG_FPGA_LAN_RESET         (H2P2_DBG_FPGA_BASE + 0x1C)     /* LAN Reset line */
+
+/* NOTE:  most boards don't have a static mapping for the FPGA ... */
+struct h2p2_dbg_fpga {
+        /* offset 0x00 */
+        u16             smc91x[8];
+        /* offset 0x10 */
+        u16             fpga_rev;
+        u16             board_rev;
+        u16             gpio_outputs;
+        u16             leds;
+        /* offset 0x18 */
+        u16             misc_inputs;
+        u16             lan_status;
+        u16             lan_reset;
+        u16             reserved0;
+        /* offset 0x20 */
+        u16             ps2_data;
+        u16             ps2_ctrl;
+        /* plus also 4 rs232 ports ... */
+};
+
+/* LEDs definition on debug board (16 LEDs, all physically green) */
+#define H2P2_DBG_FPGA_LED_GREEN         (1 << 15)
+#define H2P2_DBG_FPGA_LED_AMBER         (1 << 14)
+#define H2P2_DBG_FPGA_LED_RED           (1 << 13)
+#define H2P2_DBG_FPGA_LED_BLUE          (1 << 12)
+/*  cpu0 load-meter LEDs */
+#define H2P2_DBG_FPGA_LOAD_METER        (1 << 0)        // A bit of fun on our board ...
+#define H2P2_DBG_FPGA_LOAD_METER_SIZE   11
+#define H2P2_DBG_FPGA_LOAD_METER_MASK   ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1)
+
+#define H2P2_DBG_FPGA_P2_LED_TIMER              (1 << 0)
+#define H2P2_DBG_FPGA_P2_LED_IDLE               (1 << 1)
+
+/*
+ * ---------------------------------------------------------------------------
+ *  OMAP-1510 FPGA
+ * ---------------------------------------------------------------------------
+ */
+#define OMAP1510_FPGA_BASE                      0xE8000000      /* Virtual */
+#define OMAP1510_FPGA_SIZE                      SZ_4K
+#define OMAP1510_FPGA_START                     0x08000000      /* Physical */
+
+/* Revision */
+#define OMAP1510_FPGA_REV_LOW                   (OMAP1510_FPGA_BASE + 0x0)
+#define OMAP1510_FPGA_REV_HIGH                  (OMAP1510_FPGA_BASE + 0x1)
+
+#define OMAP1510_FPGA_LCD_PANEL_CONTROL         (OMAP1510_FPGA_BASE + 0x2)
+#define OMAP1510_FPGA_LED_DIGIT                 (OMAP1510_FPGA_BASE + 0x3)
+#define INNOVATOR_FPGA_HID_SPI                  (OMAP1510_FPGA_BASE + 0x4)
+#define OMAP1510_FPGA_POWER                     (OMAP1510_FPGA_BASE + 0x5)
+
+/* Interrupt status */
+#define OMAP1510_FPGA_ISR_LO                    (OMAP1510_FPGA_BASE + 0x6)
+#define OMAP1510_FPGA_ISR_HI                    (OMAP1510_FPGA_BASE + 0x7)
+
+/* Interrupt mask */
+#define OMAP1510_FPGA_IMR_LO                    (OMAP1510_FPGA_BASE + 0x8)
+#define OMAP1510_FPGA_IMR_HI                    (OMAP1510_FPGA_BASE + 0x9)
+
+/* Reset registers */
+#define OMAP1510_FPGA_HOST_RESET                (OMAP1510_FPGA_BASE + 0xa)
+#define OMAP1510_FPGA_RST                       (OMAP1510_FPGA_BASE + 0xb)
+
+#define OMAP1510_FPGA_AUDIO                     (OMAP1510_FPGA_BASE + 0xc)
+#define OMAP1510_FPGA_DIP                       (OMAP1510_FPGA_BASE + 0xe)
+#define OMAP1510_FPGA_FPGA_IO                   (OMAP1510_FPGA_BASE + 0xf)
+#define OMAP1510_FPGA_UART1                     (OMAP1510_FPGA_BASE + 0x14)
+#define OMAP1510_FPGA_UART2                     (OMAP1510_FPGA_BASE + 0x15)
+#define OMAP1510_FPGA_OMAP1510_STATUS           (OMAP1510_FPGA_BASE + 0x16)
+#define OMAP1510_FPGA_BOARD_REV                 (OMAP1510_FPGA_BASE + 0x18)
+#define OMAP1510P1_PPT_DATA                     (OMAP1510_FPGA_BASE + 0x100)
+#define OMAP1510P1_PPT_STATUS                   (OMAP1510_FPGA_BASE + 0x101)
+#define OMAP1510P1_PPT_CONTROL                  (OMAP1510_FPGA_BASE + 0x102)
+
+#define OMAP1510_FPGA_TOUCHSCREEN               (OMAP1510_FPGA_BASE + 0x204)
+
+#define INNOVATOR_FPGA_INFO                     (OMAP1510_FPGA_BASE + 0x205)
+#define INNOVATOR_FPGA_LCD_BRIGHT_LO            (OMAP1510_FPGA_BASE + 0x206)
+#define INNOVATOR_FPGA_LCD_BRIGHT_HI            (OMAP1510_FPGA_BASE + 0x207)
+#define INNOVATOR_FPGA_LED_GRN_LO               (OMAP1510_FPGA_BASE + 0x208)
+#define INNOVATOR_FPGA_LED_GRN_HI               (OMAP1510_FPGA_BASE + 0x209)
+#define INNOVATOR_FPGA_LED_RED_LO               (OMAP1510_FPGA_BASE + 0x20a)
+#define INNOVATOR_FPGA_LED_RED_HI               (OMAP1510_FPGA_BASE + 0x20b)
+#define INNOVATOR_FPGA_CAM_USB_CONTROL          (OMAP1510_FPGA_BASE + 0x20c)
+#define INNOVATOR_FPGA_EXP_CONTROL              (OMAP1510_FPGA_BASE + 0x20d)
+#define INNOVATOR_FPGA_ISR2                     (OMAP1510_FPGA_BASE + 0x20e)
+#define INNOVATOR_FPGA_IMR2                     (OMAP1510_FPGA_BASE + 0x210)
+
+#define OMAP1510_FPGA_ETHR_START                (OMAP1510_FPGA_START + 0x300)
+
+/*
+ * Power up Giga UART driver, turn on HID clock.
+ * Turn off BT power, since we're not using it and it
+ * draws power.
+ */
+#define OMAP1510_FPGA_RESET_VALUE               0x42
+
+#define OMAP1510_FPGA_PCR_IF_PD0                (1 << 7)
+#define OMAP1510_FPGA_PCR_COM2_EN               (1 << 6)
+#define OMAP1510_FPGA_PCR_COM1_EN               (1 << 5)
+#define OMAP1510_FPGA_PCR_EXP_PD0               (1 << 4)
+#define OMAP1510_FPGA_PCR_EXP_PD1               (1 << 3)
+#define OMAP1510_FPGA_PCR_48MHZ_CLK             (1 << 2)
+#define OMAP1510_FPGA_PCR_4MHZ_CLK              (1 << 1)
+#define OMAP1510_FPGA_PCR_RSRVD_BIT0            (1 << 0)
+
+/*
+ * Innovator/OMAP1510 FPGA HID register bit definitions
+ */
+#define OMAP1510_FPGA_HID_SCLK  (1<<0)  /* output */
+#define OMAP1510_FPGA_HID_MOSI  (1<<1)  /* output */
+#define OMAP1510_FPGA_HID_nSS   (1<<2)  /* output 0/1 chip idle/select */
+#define OMAP1510_FPGA_HID_nHSUS (1<<3)  /* output 0/1 host active/suspended */
+#define OMAP1510_FPGA_HID_MISO  (1<<4)  /* input */
+#define OMAP1510_FPGA_HID_ATN   (1<<5)  /* input  0/1 chip idle/ATN */
+#define OMAP1510_FPGA_HID_rsrvd (1<<6)
+#define OMAP1510_FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */
+
+/* The FPGA IRQ is cascaded through GPIO_13 */
+#define OMAP1510_INT_FPGA               (IH_GPIO_BASE + 13)
+
+/* IRQ Numbers for interrupts muxed through the FPGA */
+#define OMAP1510_INT_FPGA_ATN           (OMAP_FPGA_IRQ_BASE + 0)
+#define OMAP1510_INT_FPGA_ACK           (OMAP_FPGA_IRQ_BASE + 1)
+#define OMAP1510_INT_FPGA2              (OMAP_FPGA_IRQ_BASE + 2)
+#define OMAP1510_INT_FPGA3              (OMAP_FPGA_IRQ_BASE + 3)
+#define OMAP1510_INT_FPGA4              (OMAP_FPGA_IRQ_BASE + 4)
+#define OMAP1510_INT_FPGA5              (OMAP_FPGA_IRQ_BASE + 5)
+#define OMAP1510_INT_FPGA6              (OMAP_FPGA_IRQ_BASE + 6)
+#define OMAP1510_INT_FPGA7              (OMAP_FPGA_IRQ_BASE + 7)
+#define OMAP1510_INT_FPGA8              (OMAP_FPGA_IRQ_BASE + 8)
+#define OMAP1510_INT_FPGA9              (OMAP_FPGA_IRQ_BASE + 9)
+#define OMAP1510_INT_FPGA10             (OMAP_FPGA_IRQ_BASE + 10)
+#define OMAP1510_INT_FPGA11             (OMAP_FPGA_IRQ_BASE + 11)
+#define OMAP1510_INT_FPGA12             (OMAP_FPGA_IRQ_BASE + 12)
+#define OMAP1510_INT_ETHER              (OMAP_FPGA_IRQ_BASE + 13)
+#define OMAP1510_INT_FPGAUART1          (OMAP_FPGA_IRQ_BASE + 14)
+#define OMAP1510_INT_FPGAUART2          (OMAP_FPGA_IRQ_BASE + 15)
+#define OMAP1510_INT_FPGA_TS            (OMAP_FPGA_IRQ_BASE + 16)
+#define OMAP1510_INT_FPGA17             (OMAP_FPGA_IRQ_BASE + 17)
+#define OMAP1510_INT_FPGA_CAM           (OMAP_FPGA_IRQ_BASE + 18)
+#define OMAP1510_INT_FPGA_RTC_A         (OMAP_FPGA_IRQ_BASE + 19)
+#define OMAP1510_INT_FPGA_RTC_B         (OMAP_FPGA_IRQ_BASE + 20)
+#define OMAP1510_INT_FPGA_CD            (OMAP_FPGA_IRQ_BASE + 21)
+#define OMAP1510_INT_FPGA22             (OMAP_FPGA_IRQ_BASE + 22)
+#define OMAP1510_INT_FPGA23             (OMAP_FPGA_IRQ_BASE + 23)
+
+#endif
diff --git a/include/asm-arm/arch-omap/gpio-switch.h b/arch/arm/plat-omap/include/mach/gpio-switch.h
index 10da0e07c0cf..10da0e07c0cf 100644
--- a/include/asm-arm/arch-omap/gpio-switch.h
+++ b/arch/arm/plat-omap/include/mach/gpio-switch.h
diff --git a/arch/arm/plat-omap/include/mach/gpio.h b/arch/arm/plat-omap/include/mach/gpio.h
new file mode 100644
index 000000000000..94ce2780e8ee
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/gpio.h
@@ -0,0 +1,122 @@
+/*
+ * arch/arm/plat-omap/include/mach/gpio.h
+ *
+ * OMAP GPIO handling defines and functions
+ *
+ * Copyright (C) 2003-2005 Nokia Corporation
+ *
+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARCH_OMAP_GPIO_H
+#define __ASM_ARCH_OMAP_GPIO_H
+
+#include <mach/irqs.h>
+#include <asm/io.h>
+
+#define OMAP_MPUIO_BASE                 (void __iomem *)0xfffb5000
+
+#ifdef CONFIG_ARCH_OMAP730
+#define OMAP_MPUIO_INPUT_LATCH          0x00
+#define OMAP_MPUIO_OUTPUT               0x02
+#define OMAP_MPUIO_IO_CNTL              0x04
+#define OMAP_MPUIO_KBR_LATCH            0x08
+#define OMAP_MPUIO_KBC                  0x0a
+#define OMAP_MPUIO_GPIO_EVENT_MODE      0x0c
+#define OMAP_MPUIO_GPIO_INT_EDGE        0x0e
+#define OMAP_MPUIO_KBD_INT              0x10
+#define OMAP_MPUIO_GPIO_INT             0x12
+#define OMAP_MPUIO_KBD_MASKIT           0x14
+#define OMAP_MPUIO_GPIO_MASKIT          0x16
+#define OMAP_MPUIO_GPIO_DEBOUNCING      0x18
+#define OMAP_MPUIO_LATCH                0x1a
+#else
+#define OMAP_MPUIO_INPUT_LATCH          0x00
+#define OMAP_MPUIO_OUTPUT               0x04
+#define OMAP_MPUIO_IO_CNTL              0x08
+#define OMAP_MPUIO_KBR_LATCH            0x10
+#define OMAP_MPUIO_KBC                  0x14
+#define OMAP_MPUIO_GPIO_EVENT_MODE      0x18
+#define OMAP_MPUIO_GPIO_INT_EDGE        0x1c
+#define OMAP_MPUIO_KBD_INT              0x20
+#define OMAP_MPUIO_GPIO_INT             0x24
+#define OMAP_MPUIO_KBD_MASKIT           0x28
+#define OMAP_MPUIO_GPIO_MASKIT          0x2c
+#define OMAP_MPUIO_GPIO_DEBOUNCING      0x30
+#define OMAP_MPUIO_LATCH                0x34
+#endif
+
+#define OMAP34XX_NR_GPIOS               6
+
+#define OMAP_MPUIO(nr)          (OMAP_MAX_GPIO_LINES + (nr))
+#define OMAP_GPIO_IS_MPUIO(nr)  ((nr) >= OMAP_MAX_GPIO_LINES)
+
+#define OMAP_GPIO_IRQ(nr)       (OMAP_GPIO_IS_MPUIO(nr) ? \
+                                 IH_MPUIO_BASE + ((nr) & 0x0f) : \
+                                 IH_GPIO_BASE + (nr))
+
+extern int omap_gpio_init(void);        /* Call from board init only */
+extern int omap_request_gpio(int gpio);
+extern void omap_free_gpio(int gpio);
+extern void omap_set_gpio_direction(int gpio, int is_input);
+extern void omap_set_gpio_dataout(int gpio, int enable);
+extern int omap_get_gpio_datain(int gpio);
+extern void omap_set_gpio_debounce(int gpio, int enable);
+extern void omap_set_gpio_debounce_time(int gpio, int enable);
+
+/*-------------------------------------------------------------------------*/
+
+/* Wrappers for "new style" GPIO calls, using the new infrastructure
+ * which lets us plug in FPGA, I2C, and other implementations.
+ * *
+ * The original OMAP-specfic calls should eventually be removed.
+ */
+
+#include <linux/errno.h>
+#include <asm-generic/gpio.h>
+
+static inline int gpio_get_value(unsigned gpio)
+{
+        return __gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+        __gpio_set_value(gpio, value);
+}
+
+static inline int gpio_cansleep(unsigned gpio)
+{
+        return __gpio_cansleep(gpio);
+}
+
+static inline int gpio_to_irq(unsigned gpio)
+{
+        if (gpio < (OMAP_MAX_GPIO_LINES + 16))
+                return OMAP_GPIO_IRQ(gpio);
+        return -EINVAL;
+}
+
+static inline int irq_to_gpio(unsigned irq)
+{
+        if (cpu_class_is_omap1() && (irq < (IH_MPUIO_BASE + 16)))
+                return (irq - IH_MPUIO_BASE) + OMAP_MAX_GPIO_LINES;
+        return irq - IH_GPIO_BASE;
+}
+
+#endif
diff --git a/arch/arm/plat-omap/include/mach/gpioexpander.h b/arch/arm/plat-omap/include/mach/gpioexpander.h
new file mode 100644
index 000000000000..90444a0d6b1a
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/gpioexpander.h
@@ -0,0 +1,35 @@
+/*
+ * arch/arm/plat-omap/include/mach/gpioexpander.h
+ *
+ *
+ * Copyright (C) 2004 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#ifndef __ASM_ARCH_OMAP_GPIOEXPANDER_H
+#define __ASM_ARCH_OMAP_GPIOEXPANDER_H
+
+/* Function Prototypes for GPIO Expander functions */
+
+#ifdef CONFIG_GPIOEXPANDER_OMAP
+int read_gpio_expa(u8 *, int);
+int write_gpio_expa(u8 , int);
+#else
+static inline int read_gpio_expa(u8 *val, int addr)
+{
+        return 0;
+}
+static inline int write_gpio_expa(u8 val, int addr)
+{
+        return 0;
+}
+#endif
+
+#endif /* __ASM_ARCH_OMAP_GPIOEXPANDER_H */
diff --git a/include/asm-arm/arch-omap/gpmc.h b/arch/arm/plat-omap/include/mach/gpmc.h
index 6a8e07ffc2d0..6a8e07ffc2d0 100644
--- a/include/asm-arm/arch-omap/gpmc.h
+++ b/arch/arm/plat-omap/include/mach/gpmc.h
diff --git a/arch/arm/plat-omap/include/mach/hardware.h b/arch/arm/plat-omap/include/mach/hardware.h
new file mode 100644
index 000000000000..07f5d7f21528
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/hardware.h
@@ -0,0 +1,355 @@
+/*
+ * arch/arm/plat-omap/include/mach/hardware.h
+ *
+ * Hardware definitions for TI OMAP processors and boards
+ *
+ * NOTE: Please put device driver specific defines into a separate header
+ *       file for each driver.
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
+ *                          and Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_OMAP_HARDWARE_H
+#define __ASM_ARCH_OMAP_HARDWARE_H
+
+#include <asm/sizes.h>
+#ifndef __ASSEMBLER__
+#include <asm/types.h>
+#include <mach/cpu.h>
+#endif
+#include <mach/serial.h>
+
+/*
+ * ---------------------------------------------------------------------------
+ * Common definitions for all OMAP processors
+ * NOTE: Put all processor or board specific parts to the special header
+ *       files.
+ * ---------------------------------------------------------------------------
+ */
+
+/*
+ * ----------------------------------------------------------------------------
+ * Timers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP_MPU_TIMER1_BASE    (0xfffec500)
+#define OMAP_MPU_TIMER2_BASE    (0xfffec600)
+#define OMAP_MPU_TIMER3_BASE    (0xfffec700)
+#define MPU_TIMER_FREE          (1 << 6)
+#define MPU_TIMER_CLOCK_ENABLE  (1 << 5)
+#define MPU_TIMER_AR            (1 << 1)
+#define MPU_TIMER_ST            (1 << 0)
+
+/*
+ * ----------------------------------------------------------------------------
+ * Clocks
+ * ----------------------------------------------------------------------------
+ */
+#define CLKGEN_REG_BASE         (0xfffece00)
+#define ARM_CKCTL               (CLKGEN_REG_BASE + 0x0)
+#define ARM_IDLECT1             (CLKGEN_REG_BASE + 0x4)
+#define ARM_IDLECT2             (CLKGEN_REG_BASE + 0x8)
+#define ARM_EWUPCT              (CLKGEN_REG_BASE + 0xC)
+#define ARM_RSTCT1              (CLKGEN_REG_BASE + 0x10)
+#define ARM_RSTCT2              (CLKGEN_REG_BASE + 0x14)
+#define ARM_SYSST               (CLKGEN_REG_BASE + 0x18)
+#define ARM_IDLECT3             (CLKGEN_REG_BASE + 0x24)
+
+#define CK_RATEF                1
+#define CK_IDLEF                2
+#define CK_ENABLEF              4
+#define CK_SELECTF              8
+#define SETARM_IDLE_SHIFT
+
+/* DPLL control registers */
+#define DPLL_CTL                (0xfffecf00)
+
+/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
+#define DSP_CONFIG_REG_BASE     (0xe1008000)
+#define DSP_CKCTL               (DSP_CONFIG_REG_BASE + 0x0)
+#define DSP_IDLECT1             (DSP_CONFIG_REG_BASE + 0x4)
+#define DSP_IDLECT2             (DSP_CONFIG_REG_BASE + 0x8)
+#define DSP_RSTCT2              (DSP_CONFIG_REG_BASE + 0x14)
+
+/*
+ * ---------------------------------------------------------------------------
+ * UPLD
+ * ---------------------------------------------------------------------------
+ */
+#define ULPD_REG_BASE           (0xfffe0800)
+#define ULPD_IT_STATUS          (ULPD_REG_BASE + 0x14)
+#define ULPD_SETUP_ANALOG_CELL_3        (ULPD_REG_BASE + 0x24)
+#define ULPD_CLOCK_CTRL         (ULPD_REG_BASE + 0x30)
+#       define DIS_USB_PVCI_CLK         (1 << 5)        /* no USB/FAC synch */
+#       define USB_MCLK_EN              (1 << 4)        /* enable W4_USB_CLKO */
+#define ULPD_SOFT_REQ           (ULPD_REG_BASE + 0x34)
+#       define SOFT_UDC_REQ             (1 << 4)
+#       define SOFT_USB_CLK_REQ         (1 << 3)
+#       define SOFT_DPLL_REQ            (1 << 0)
+#define ULPD_DPLL_CTRL          (ULPD_REG_BASE + 0x3c)
+#define ULPD_STATUS_REQ         (ULPD_REG_BASE + 0x40)
+#define ULPD_APLL_CTRL          (ULPD_REG_BASE + 0x4c)
+#define ULPD_POWER_CTRL         (ULPD_REG_BASE + 0x50)
+#define ULPD_SOFT_DISABLE_REQ_REG       (ULPD_REG_BASE + 0x68)
+#       define DIS_MMC2_DPLL_REQ        (1 << 11)
+#       define DIS_MMC1_DPLL_REQ        (1 << 10)
+#       define DIS_UART3_DPLL_REQ       (1 << 9)
+#       define DIS_UART2_DPLL_REQ       (1 << 8)
+#       define DIS_UART1_DPLL_REQ       (1 << 7)
+#       define DIS_USB_HOST_DPLL_REQ    (1 << 6)
+#define ULPD_SDW_CLK_DIV_CTRL_SEL       (ULPD_REG_BASE + 0x74)
+#define ULPD_CAM_CLK_CTRL       (ULPD_REG_BASE + 0x7c)
+
+/*
+ * ---------------------------------------------------------------------------
+ * Watchdog timer
+ * ---------------------------------------------------------------------------
+ */
+
+/* Watchdog timer within the OMAP3.2 gigacell */
+#define OMAP_MPU_WATCHDOG_BASE  (0xfffec800)
+#define OMAP_WDT_TIMER          (OMAP_MPU_WATCHDOG_BASE + 0x0)
+#define OMAP_WDT_LOAD_TIM       (OMAP_MPU_WATCHDOG_BASE + 0x4)
+#define OMAP_WDT_READ_TIM       (OMAP_MPU_WATCHDOG_BASE + 0x4)
+#define OMAP_WDT_TIMER_MODE     (OMAP_MPU_WATCHDOG_BASE + 0x8)
+
+/*
+ * ---------------------------------------------------------------------------
+ * Interrupts
+ * ---------------------------------------------------------------------------
+ */
+#ifdef CONFIG_ARCH_OMAP1
+
+/*
+ * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c
+ * or something similar.. -- PFM.
+ */
+
+#define OMAP_IH1_BASE           0xfffecb00
+#define OMAP_IH2_BASE           0xfffe0000
+
+#define OMAP_IH1_ITR            (OMAP_IH1_BASE + 0x00)
+#define OMAP_IH1_MIR            (OMAP_IH1_BASE + 0x04)
+#define OMAP_IH1_SIR_IRQ        (OMAP_IH1_BASE + 0x10)
+#define OMAP_IH1_SIR_FIQ        (OMAP_IH1_BASE + 0x14)
+#define OMAP_IH1_CONTROL        (OMAP_IH1_BASE + 0x18)
+#define OMAP_IH1_ILR0           (OMAP_IH1_BASE + 0x1c)
+#define OMAP_IH1_ISR            (OMAP_IH1_BASE + 0x9c)
+
+#define OMAP_IH2_ITR            (OMAP_IH2_BASE + 0x00)
+#define OMAP_IH2_MIR            (OMAP_IH2_BASE + 0x04)
+#define OMAP_IH2_SIR_IRQ        (OMAP_IH2_BASE + 0x10)
+#define OMAP_IH2_SIR_FIQ        (OMAP_IH2_BASE + 0x14)
+#define OMAP_IH2_CONTROL        (OMAP_IH2_BASE + 0x18)
+#define OMAP_IH2_ILR0           (OMAP_IH2_BASE + 0x1c)
+#define OMAP_IH2_ISR            (OMAP_IH2_BASE + 0x9c)
+
+#define IRQ_ITR_REG_OFFSET      0x00
+#define IRQ_MIR_REG_OFFSET      0x04
+#define IRQ_SIR_IRQ_REG_OFFSET  0x10
+#define IRQ_SIR_FIQ_REG_OFFSET  0x14
+#define IRQ_CONTROL_REG_OFFSET  0x18
+#define IRQ_ISR_REG_OFFSET      0x9c
+#define IRQ_ILR0_REG_OFFSET     0x1c
+#define IRQ_GMR_REG_OFFSET      0xa0
+
+#endif
+
+/*
+ * ----------------------------------------------------------------------------
+ * System control registers
+ * ----------------------------------------------------------------------------
+ */
+#define MOD_CONF_CTRL_0         0xfffe1080
+#define MOD_CONF_CTRL_1         0xfffe1110
+
+/*
+ * ----------------------------------------------------------------------------
+ * Pin multiplexing registers
+ * ----------------------------------------------------------------------------
+ */
+#define FUNC_MUX_CTRL_0         0xfffe1000
+#define FUNC_MUX_CTRL_1         0xfffe1004
+#define FUNC_MUX_CTRL_2         0xfffe1008
+#define COMP_MODE_CTRL_0        0xfffe100c
+#define FUNC_MUX_CTRL_3         0xfffe1010
+#define FUNC_MUX_CTRL_4         0xfffe1014
+#define FUNC_MUX_CTRL_5         0xfffe1018
+#define FUNC_MUX_CTRL_6         0xfffe101C
+#define FUNC_MUX_CTRL_7         0xfffe1020
+#define FUNC_MUX_CTRL_8         0xfffe1024
+#define FUNC_MUX_CTRL_9         0xfffe1028
+#define FUNC_MUX_CTRL_A         0xfffe102C
+#define FUNC_MUX_CTRL_B         0xfffe1030
+#define FUNC_MUX_CTRL_C         0xfffe1034
+#define FUNC_MUX_CTRL_D         0xfffe1038
+#define PULL_DWN_CTRL_0         0xfffe1040
+#define PULL_DWN_CTRL_1         0xfffe1044
+#define PULL_DWN_CTRL_2         0xfffe1048
+#define PULL_DWN_CTRL_3         0xfffe104c
+#define PULL_DWN_CTRL_4         0xfffe10ac
+
+/* OMAP-1610 specific multiplexing registers */
+#define FUNC_MUX_CTRL_E         0xfffe1090
+#define FUNC_MUX_CTRL_F         0xfffe1094
+#define FUNC_MUX_CTRL_10        0xfffe1098
+#define FUNC_MUX_CTRL_11        0xfffe109c
+#define FUNC_MUX_CTRL_12        0xfffe10a0
+#define PU_PD_SEL_0             0xfffe10b4
+#define PU_PD_SEL_1             0xfffe10b8
+#define PU_PD_SEL_2             0xfffe10bc
+#define PU_PD_SEL_3             0xfffe10c0
+#define PU_PD_SEL_4             0xfffe10c4
+
+/* Timer32K for 1610 and 1710*/
+#define OMAP_TIMER32K_BASE      0xFFFBC400
+
+/*
+ * ---------------------------------------------------------------------------
+ * TIPB bus interface
+ * ---------------------------------------------------------------------------
+ */
+#define TIPB_PUBLIC_CNTL_BASE           0xfffed300
+#define MPU_PUBLIC_TIPB_CNTL            (TIPB_PUBLIC_CNTL_BASE + 0x8)
+#define TIPB_PRIVATE_CNTL_BASE          0xfffeca00
+#define MPU_PRIVATE_TIPB_CNTL           (TIPB_PRIVATE_CNTL_BASE + 0x8)
+
+/*
+ * ----------------------------------------------------------------------------
+ * MPUI interface
+ * ----------------------------------------------------------------------------
+ */
+#define MPUI_BASE                       (0xfffec900)
+#define MPUI_CTRL                       (MPUI_BASE + 0x0)
+#define MPUI_DEBUG_ADDR                 (MPUI_BASE + 0x4)
+#define MPUI_DEBUG_DATA                 (MPUI_BASE + 0x8)
+#define MPUI_DEBUG_FLAG                 (MPUI_BASE + 0xc)
+#define MPUI_STATUS_REG                 (MPUI_BASE + 0x10)
+#define MPUI_DSP_STATUS                 (MPUI_BASE + 0x14)
+#define MPUI_DSP_BOOT_CONFIG            (MPUI_BASE + 0x18)
+#define MPUI_DSP_API_CONFIG             (MPUI_BASE + 0x1c)
+
+/*
+ * ----------------------------------------------------------------------------
+ * LED Pulse Generator
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP_LPG1_BASE                  0xfffbd000
+#define OMAP_LPG2_BASE                  0xfffbd800
+#define OMAP_LPG1_LCR                   (OMAP_LPG1_BASE + 0x00)
+#define OMAP_LPG1_PMR                   (OMAP_LPG1_BASE + 0x04)
+#define OMAP_LPG2_LCR                   (OMAP_LPG2_BASE + 0x00)
+#define OMAP_LPG2_PMR                   (OMAP_LPG2_BASE + 0x04)
+
+/*
+ * ----------------------------------------------------------------------------
+ * Pulse-Width Light
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP_PWL_BASE                   0xfffb5800
+#define OMAP_PWL_ENABLE                 (OMAP_PWL_BASE + 0x00)
+#define OMAP_PWL_CLK_ENABLE             (OMAP_PWL_BASE + 0x04)
+
+/*
+ * ---------------------------------------------------------------------------
+ * Processor specific defines
+ * ---------------------------------------------------------------------------
+ */
+
+#include "omap730.h"
+#include "omap1510.h"
+#include "omap24xx.h"
+#include "omap16xx.h"
+#include "omap34xx.h"
+
+#ifndef __ASSEMBLER__
+
+/*
+ * ---------------------------------------------------------------------------
+ * Board specific defines
+ * ---------------------------------------------------------------------------
+ */
+
+#ifdef CONFIG_MACH_OMAP_INNOVATOR
+#include "board-innovator.h"
+#endif
+
+#ifdef CONFIG_MACH_OMAP_H2
+#include "board-h2.h"
+#endif
+
+#ifdef CONFIG_MACH_OMAP_PERSEUS2
+#include "board-perseus2.h"
+#endif
+
+#ifdef CONFIG_MACH_OMAP_FSAMPLE
+#include "board-fsample.h"
+#endif
+
+#ifdef CONFIG_MACH_OMAP_H3
+#include "board-h3.h"
+#endif
+
+#ifdef CONFIG_MACH_OMAP_H4
+#include "board-h4.h"
+#endif
+
+#ifdef CONFIG_MACH_OMAP_2430SDP
+#include "board-2430sdp.h"
+#endif
+
+#ifdef CONFIG_MACH_OMAP_APOLLON
+#include "board-apollon.h"
+#endif
+
+#ifdef CONFIG_MACH_OMAP_OSK
+#include "board-osk.h"
+#endif
+
+#ifdef CONFIG_MACH_VOICEBLUE
+#include "board-voiceblue.h"
+#endif
+
+#ifdef CONFIG_MACH_OMAP_PALMTE
+#include "board-palmte.h"
+#endif
+
+#ifdef CONFIG_MACH_OMAP_PALMZ71
+#include "board-palmz71.h"
+#endif
+
+#ifdef CONFIG_MACH_OMAP_PALMTT
+#include "board-palmtt.h"
+#endif
+
+#ifdef CONFIG_MACH_SX1
+#include "board-sx1.h"
+#endif
+
+#endif /* !__ASSEMBLER__ */
+
+#endif  /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/include/asm-arm/arch-omap/hwa742.h b/arch/arm/plat-omap/include/mach/hwa742.h
index 577f492f2d3c..577f492f2d3c 100644
--- a/include/asm-arm/arch-omap/hwa742.h
+++ b/arch/arm/plat-omap/include/mach/hwa742.h
diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/mach/io.h
new file mode 100644
index 000000000000..2a30b7d88cde
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/io.h
@@ -0,0 +1,197 @@
+/*
+ * arch/arm/plat-omap/include/mach/io.h
+ *
+ * IO definitions for TI OMAP processors and boards
+ *
+ * Copied from arch/arm/mach-sa1100/include/mach/io.h
+ * Copyright (C) 1997-1999 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Modifications:
+ *  06-12-1997  RMK     Created.
+ *  07-04-1999  RMK     Major cleanup
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#include <mach/hardware.h>
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * We don't actually have real ISA nor PCI buses, but there is so many
+ * drivers out there that might just work if we fake them...
+ */
+#define __io(a)                 ((void __iomem *)(PCIO_BASE + (a)))
+#define __mem_pci(a)            (a)
+
+/*
+ * ----------------------------------------------------------------------------
+ * I/O mapping
+ * ----------------------------------------------------------------------------
+ */
+
+#define PCIO_BASE       0
+
+#if defined(CONFIG_ARCH_OMAP1)
+
+#define IO_PHYS         0xFFFB0000
+#define IO_OFFSET       0x01000000      /* Virtual IO = 0xfefb0000 */
+#define IO_SIZE         0x40000
+#define IO_VIRT         (IO_PHYS - IO_OFFSET)
+#define IO_ADDRESS(pa)  ((pa) - IO_OFFSET)
+#define OMAP1_IO_ADDRESS(pa)    ((pa) - IO_OFFSET)
+#define io_p2v(pa)      ((pa) - IO_OFFSET)
+#define io_v2p(va)      ((va) + IO_OFFSET)
+
+#elif defined(CONFIG_ARCH_OMAP2)
+
+/* We map both L3 and L4 on OMAP2 */
+#define L3_24XX_PHYS    L3_24XX_BASE    /* 0x68000000 */
+#define L3_24XX_VIRT    0xf8000000
+#define L3_24XX_SIZE    SZ_1M           /* 44kB of 128MB used, want 1MB sect */
+#define L4_24XX_PHYS    L4_24XX_BASE    /* 0x48000000 */
+#define L4_24XX_VIRT    0xd8000000
+#define L4_24XX_SIZE    SZ_1M           /* 1MB of 128MB used, want 1MB sect */
+
+#ifdef CONFIG_ARCH_OMAP2430
+#define L4_WK_243X_PHYS         L4_WK_243X_BASE         /* 0x49000000 */
+#define L4_WK_243X_VIRT         0xd9000000
+#define L4_WK_243X_SIZE         SZ_1M
+#define OMAP243X_GPMC_PHYS      OMAP243X_GPMC_BASE      /* 0x49000000 */
+#define OMAP243X_GPMC_VIRT      0xFE000000
+#define OMAP243X_GPMC_SIZE      SZ_1M
+#define OMAP243X_SDRC_PHYS      OMAP243X_SDRC_BASE
+#define OMAP243X_SDRC_VIRT      0xFD000000
+#define OMAP243X_SDRC_SIZE      SZ_1M
+#define OMAP243X_SMS_PHYS       OMAP243X_SMS_BASE
+#define OMAP243X_SMS_VIRT       0xFC000000
+#define OMAP243X_SMS_SIZE       SZ_1M
+
+#endif
+
+#define IO_OFFSET       0x90000000
+#define IO_ADDRESS(pa)  ((pa) + IO_OFFSET)      /* Works for L3 and L4 */
+#define OMAP2_IO_ADDRESS(pa)    ((pa) + IO_OFFSET)      /* Works for L3 and L4 */
+#define io_p2v(pa)      ((pa) + IO_OFFSET)      /* Works for L3 and L4 */
+#define io_v2p(va)      ((va) - IO_OFFSET)      /* Works for L3 and L4 */
+
+/* DSP */
+#define DSP_MEM_24XX_PHYS       OMAP2420_DSP_MEM_BASE   /* 0x58000000 */
+#define DSP_MEM_24XX_VIRT       0xe0000000
+#define DSP_MEM_24XX_SIZE       0x28000
+#define DSP_IPI_24XX_PHYS       OMAP2420_DSP_IPI_BASE   /* 0x59000000 */
+#define DSP_IPI_24XX_VIRT       0xe1000000
+#define DSP_IPI_24XX_SIZE       SZ_4K
+#define DSP_MMU_24XX_PHYS       OMAP2420_DSP_MMU_BASE   /* 0x5a000000 */
+#define DSP_MMU_24XX_VIRT       0xe2000000
+#define DSP_MMU_24XX_SIZE       SZ_4K
+
+#elif defined(CONFIG_ARCH_OMAP3)
+
+/* We map both L3 and L4 on OMAP3 */
+#define L3_34XX_PHYS            L3_34XX_BASE    /* 0x68000000 */
+#define L3_34XX_VIRT            0xf8000000
+#define L3_34XX_SIZE            SZ_1M   /* 44kB of 128MB used, want 1MB sect */
+
+#define L4_34XX_PHYS            L4_34XX_BASE    /* 0x48000000 */
+#define L4_34XX_VIRT            0xd8000000
+#define L4_34XX_SIZE            SZ_4M   /* 1MB of 128MB used, want 1MB sect */
+
+/*
+ * Need to look at the Size 4M for L4.
+ * VPOM3430 was not working for Int controller
+ */
+
+#define L4_WK_34XX_PHYS         L4_WK_34XX_BASE /* 0x48300000 */
+#define L4_WK_34XX_VIRT         0xd8300000
+#define L4_WK_34XX_SIZE         SZ_1M
+
+#define L4_PER_34XX_PHYS        L4_PER_34XX_BASE /* 0x49000000 */
+#define L4_PER_34XX_VIRT        0xd9000000
+#define L4_PER_34XX_SIZE        SZ_1M
+
+#define L4_EMU_34XX_PHYS        L4_EMU_34XX_BASE /* 0x54000000 */
+#define L4_EMU_34XX_VIRT        0xe4000000
+#define L4_EMU_34XX_SIZE        SZ_64M
+
+#define OMAP34XX_GPMC_PHYS      OMAP34XX_GPMC_BASE /* 0x6E000000 */
+#define OMAP34XX_GPMC_VIRT      0xFE000000
+#define OMAP34XX_GPMC_SIZE      SZ_1M
+
+#define OMAP343X_SMS_PHYS       OMAP343X_SMS_BASE /* 0x6C000000 */
+#define OMAP343X_SMS_VIRT       0xFC000000
+#define OMAP343X_SMS_SIZE       SZ_1M
+
+#define OMAP343X_SDRC_PHYS      OMAP343X_SDRC_BASE /* 0x6D000000 */
+#define OMAP343X_SDRC_VIRT      0xFD000000
+#define OMAP343X_SDRC_SIZE      SZ_1M
+
+
+#define IO_OFFSET               0x90000000
+#define IO_ADDRESS(pa)          ((pa) + IO_OFFSET)/* Works for L3 and L4 */
+#define OMAP2_IO_ADDRESS(pa)    ((pa) + IO_OFFSET)/* Works for L3 and L4 */
+#define io_p2v(pa)              ((pa) + IO_OFFSET)/* Works for L3 and L4 */
+#define io_v2p(va)              ((va) - IO_OFFSET)/* Works for L3 and L4 */
+
+/* DSP */
+#define DSP_MEM_34XX_PHYS       OMAP34XX_DSP_MEM_BASE   /* 0x58000000 */
+#define DSP_MEM_34XX_VIRT       0xe0000000
+#define DSP_MEM_34XX_SIZE       0x28000
+#define DSP_IPI_34XX_PHYS       OMAP34XX_DSP_IPI_BASE   /* 0x59000000 */
+#define DSP_IPI_34XX_VIRT       0xe1000000
+#define DSP_IPI_34XX_SIZE       SZ_4K
+#define DSP_MMU_34XX_PHYS       OMAP34XX_DSP_MMU_BASE   /* 0x5a000000 */
+#define DSP_MMU_34XX_VIRT       0xe2000000
+#define DSP_MMU_34XX_SIZE       SZ_4K
+
+#endif
+
+#ifndef __ASSEMBLER__
+
+/*
+ * Functions to access the OMAP IO region
+ *
+ * NOTE: - Use omap_read/write[bwl] for physical register addresses
+ *       - Use __raw_read/write[bwl]() for virtual register addresses
+ *       - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses
+ *       - DO NOT use hardcoded virtual addresses to allow changing the
+ *         IO address space again if needed
+ */
+#define omap_readb(a)           (*(volatile unsigned char  *)IO_ADDRESS(a))
+#define omap_readw(a)           (*(volatile unsigned short *)IO_ADDRESS(a))
+#define omap_readl(a)           (*(volatile unsigned int   *)IO_ADDRESS(a))
+
+#define omap_writeb(v,a)        (*(volatile unsigned char  *)IO_ADDRESS(a) = (v))
+#define omap_writew(v,a)        (*(volatile unsigned short *)IO_ADDRESS(a) = (v))
+#define omap_writel(v,a)        (*(volatile unsigned int   *)IO_ADDRESS(a) = (v))
+
+extern void omap1_map_common_io(void);
+extern void omap1_init_common_hw(void);
+
+extern void omap2_map_common_io(void);
+extern void omap2_init_common_hw(void);
+
+#endif
+
+#endif
diff --git a/arch/arm/plat-omap/include/mach/irda.h b/arch/arm/plat-omap/include/mach/irda.h
new file mode 100644
index 000000000000..8372a00d8e0b
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/irda.h
@@ -0,0 +1,37 @@
+/*
+ *  arch/arm/plat-omap/include/mach/irda.h
+ *
+ *  Copyright (C) 2005-2006 Komal Shah <komal_shah802003@yahoo.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef ASMARM_ARCH_IRDA_H
+#define ASMARM_ARCH_IRDA_H
+
+/* board specific transceiver capabilities */
+
+#define IR_SEL          1       /* Selects IrDA */
+#define IR_SIRMODE      2
+#define IR_FIRMODE      4
+#define IR_MIRMODE      8
+
+struct omap_irda_config {
+        int transceiver_cap;
+        int (*transceiver_mode)(struct device *dev, int mode);
+        int (*select_irda)(struct device *dev, int state);
+        /* Very specific to the needs of some platforms (h3,h4)
+         * having calls which can sleep in irda_set_speed.
+         */
+        struct delayed_work gpio_expa;
+        int rx_channel;
+        int tx_channel;
+        unsigned long dest_start;
+        unsigned long src_start;
+        int tx_trigger;
+        int rx_trigger;
+        int mode;
+};
+
+#endif
diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/mach/irqs.h
new file mode 100644
index 000000000000..17248bbf3f27
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/irqs.h
@@ -0,0 +1,332 @@
+/*
+ *  arch/arm/plat-omap/include/mach/irqs.h
+ *
+ *  Copyright (C) Greg Lonnon 2001
+ *  Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
+ *       are different.
+ */
+
+#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
+#define __ASM_ARCH_OMAP15XX_IRQS_H
+
+/*
+ * IRQ numbers for interrupt handler 1
+ *
+ * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
+ *
+ */
+#define INT_CAMERA              1
+#define INT_FIQ                 3
+#define INT_RTDX                6
+#define INT_DSP_MMU_ABORT       7
+#define INT_HOST                8
+#define INT_ABORT               9
+#define INT_BRIDGE_PRIV         13
+#define INT_GPIO_BANK1          14
+#define INT_UART3               15
+#define INT_TIMER3              16
+#define INT_DMA_CH0_6           19
+#define INT_DMA_CH1_7           20
+#define INT_DMA_CH2_8           21
+#define INT_DMA_CH3             22
+#define INT_DMA_CH4             23
+#define INT_DMA_CH5             24
+#define INT_DMA_LCD             25
+#define INT_TIMER1              26
+#define INT_WD_TIMER            27
+#define INT_BRIDGE_PUB          28
+#define INT_TIMER2              30
+#define INT_LCD_CTRL            31
+
+/*
+ * OMAP-1510 specific IRQ numbers for interrupt handler 1
+ */
+#define INT_1510_IH2_IRQ        0
+#define INT_1510_RES2           2
+#define INT_1510_SPI_TX         4
+#define INT_1510_SPI_RX         5
+#define INT_1510_DSP_MAILBOX1   10
+#define INT_1510_DSP_MAILBOX2   11
+#define INT_1510_RES12          12
+#define INT_1510_LB_MMU         17
+#define INT_1510_RES18          18
+#define INT_1510_LOCAL_BUS      29
+
+/*
+ * OMAP-1610 specific IRQ numbers for interrupt handler 1
+ */
+#define INT_1610_IH2_IRQ        0
+#define INT_1610_IH2_FIQ        2
+#define INT_1610_McBSP2_TX      4
+#define INT_1610_McBSP2_RX      5
+#define INT_1610_DSP_MAILBOX1   10
+#define INT_1610_DSP_MAILBOX2   11
+#define INT_1610_LCD_LINE       12
+#define INT_1610_GPTIMER1       17
+#define INT_1610_GPTIMER2       18
+#define INT_1610_SSR_FIFO_0     29
+
+/*
+ * OMAP-730 specific IRQ numbers for interrupt handler 1
+ */
+#define INT_730_IH2_FIQ         0
+#define INT_730_IH2_IRQ         1
+#define INT_730_USB_NON_ISO     2
+#define INT_730_USB_ISO         3
+#define INT_730_ICR             4
+#define INT_730_EAC             5
+#define INT_730_GPIO_BANK1      6
+#define INT_730_GPIO_BANK2      7
+#define INT_730_GPIO_BANK3      8
+#define INT_730_McBSP2TX        10
+#define INT_730_McBSP2RX        11
+#define INT_730_McBSP2RX_OVF    12
+#define INT_730_LCD_LINE        14
+#define INT_730_GSM_PROTECT     15
+#define INT_730_TIMER3          16
+#define INT_730_GPIO_BANK5      17
+#define INT_730_GPIO_BANK6      18
+#define INT_730_SPGIO_WR        29
+
+/*
+ * IRQ numbers for interrupt handler 2
+ *
+ * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
+ */
+#define IH2_BASE                32
+
+#define INT_KEYBOARD            (1 + IH2_BASE)
+#define INT_uWireTX             (2 + IH2_BASE)
+#define INT_uWireRX             (3 + IH2_BASE)
+#define INT_I2C                 (4 + IH2_BASE)
+#define INT_MPUIO               (5 + IH2_BASE)
+#define INT_USB_HHC_1           (6 + IH2_BASE)
+#define INT_McBSP3TX            (10 + IH2_BASE)
+#define INT_McBSP3RX            (11 + IH2_BASE)
+#define INT_McBSP1TX            (12 + IH2_BASE)
+#define INT_McBSP1RX            (13 + IH2_BASE)
+#define INT_UART1               (14 + IH2_BASE)
+#define INT_UART2               (15 + IH2_BASE)
+#define INT_BT_MCSI1TX          (16 + IH2_BASE)
+#define INT_BT_MCSI1RX          (17 + IH2_BASE)
+#define INT_USB_W2FC            (20 + IH2_BASE)
+#define INT_1WIRE               (21 + IH2_BASE)
+#define INT_OS_TIMER            (22 + IH2_BASE)
+#define INT_MMC                 (23 + IH2_BASE)
+#define INT_GAUGE_32K           (24 + IH2_BASE)
+#define INT_RTC_TIMER           (25 + IH2_BASE)
+#define INT_RTC_ALARM           (26 + IH2_BASE)
+#define INT_MEM_STICK           (27 + IH2_BASE)
+
+/*
+ * OMAP-1510 specific IRQ numbers for interrupt handler 2
+ */
+#define INT_1510_DSP_MMU        (28 + IH2_BASE)
+#define INT_1510_COM_SPI_RO     (31 + IH2_BASE)
+
+/*
+ * OMAP-1610 specific IRQ numbers for interrupt handler 2
+ */
+#define INT_1610_FAC            (0 + IH2_BASE)
+#define INT_1610_USB_HHC_2      (7 + IH2_BASE)
+#define INT_1610_USB_OTG        (8 + IH2_BASE)
+#define INT_1610_SoSSI          (9 + IH2_BASE)
+#define INT_1610_SoSSI_MATCH    (19 + IH2_BASE)
+#define INT_1610_DSP_MMU        (28 + IH2_BASE)
+#define INT_1610_McBSP2RX_OF    (31 + IH2_BASE)
+#define INT_1610_STI            (32 + IH2_BASE)
+#define INT_1610_STI_WAKEUP     (33 + IH2_BASE)
+#define INT_1610_GPTIMER3       (34 + IH2_BASE)
+#define INT_1610_GPTIMER4       (35 + IH2_BASE)
+#define INT_1610_GPTIMER5       (36 + IH2_BASE)
+#define INT_1610_GPTIMER6       (37 + IH2_BASE)
+#define INT_1610_GPTIMER7       (38 + IH2_BASE)
+#define INT_1610_GPTIMER8       (39 + IH2_BASE)
+#define INT_1610_GPIO_BANK2     (40 + IH2_BASE)
+#define INT_1610_GPIO_BANK3     (41 + IH2_BASE)
+#define INT_1610_MMC2           (42 + IH2_BASE)
+#define INT_1610_CF             (43 + IH2_BASE)
+#define INT_1610_WAKE_UP_REQ    (46 + IH2_BASE)
+#define INT_1610_GPIO_BANK4     (48 + IH2_BASE)
+#define INT_1610_SPI            (49 + IH2_BASE)
+#define INT_1610_DMA_CH6        (53 + IH2_BASE)
+#define INT_1610_DMA_CH7        (54 + IH2_BASE)
+#define INT_1610_DMA_CH8        (55 + IH2_BASE)
+#define INT_1610_DMA_CH9        (56 + IH2_BASE)
+#define INT_1610_DMA_CH10       (57 + IH2_BASE)
+#define INT_1610_DMA_CH11       (58 + IH2_BASE)
+#define INT_1610_DMA_CH12       (59 + IH2_BASE)
+#define INT_1610_DMA_CH13       (60 + IH2_BASE)
+#define INT_1610_DMA_CH14       (61 + IH2_BASE)
+#define INT_1610_DMA_CH15       (62 + IH2_BASE)
+#define INT_1610_NAND           (63 + IH2_BASE)
+
+/*
+ * OMAP-730 specific IRQ numbers for interrupt handler 2
+ */
+#define INT_730_HW_ERRORS       (0 + IH2_BASE)
+#define INT_730_NFIQ_PWR_FAIL   (1 + IH2_BASE)
+#define INT_730_CFCD            (2 + IH2_BASE)
+#define INT_730_CFIREQ          (3 + IH2_BASE)
+#define INT_730_I2C             (4 + IH2_BASE)
+#define INT_730_PCC             (5 + IH2_BASE)
+#define INT_730_MPU_EXT_NIRQ    (6 + IH2_BASE)
+#define INT_730_SPI_100K_1      (7 + IH2_BASE)
+#define INT_730_SYREN_SPI       (8 + IH2_BASE)
+#define INT_730_VLYNQ           (9 + IH2_BASE)
+#define INT_730_GPIO_BANK4      (10 + IH2_BASE)
+#define INT_730_McBSP1TX        (11 + IH2_BASE)
+#define INT_730_McBSP1RX        (12 + IH2_BASE)
+#define INT_730_McBSP1RX_OF     (13 + IH2_BASE)
+#define INT_730_UART_MODEM_IRDA_2 (14 + IH2_BASE)
+#define INT_730_UART_MODEM_1    (15 + IH2_BASE)
+#define INT_730_MCSI            (16 + IH2_BASE)
+#define INT_730_uWireTX         (17 + IH2_BASE)
+#define INT_730_uWireRX         (18 + IH2_BASE)
+#define INT_730_SMC_CD          (19 + IH2_BASE)
+#define INT_730_SMC_IREQ        (20 + IH2_BASE)
+#define INT_730_HDQ_1WIRE       (21 + IH2_BASE)
+#define INT_730_TIMER32K        (22 + IH2_BASE)
+#define INT_730_MMC_SDIO        (23 + IH2_BASE)
+#define INT_730_UPLD            (24 + IH2_BASE)
+#define INT_730_USB_HHC_1       (27 + IH2_BASE)
+#define INT_730_USB_HHC_2       (28 + IH2_BASE)
+#define INT_730_USB_GENI        (29 + IH2_BASE)
+#define INT_730_USB_OTG         (30 + IH2_BASE)
+#define INT_730_CAMERA_IF       (31 + IH2_BASE)
+#define INT_730_RNG             (32 + IH2_BASE)
+#define INT_730_DUAL_MODE_TIMER (33 + IH2_BASE)
+#define INT_730_DBB_RF_EN       (34 + IH2_BASE)
+#define INT_730_MPUIO_KEYPAD    (35 + IH2_BASE)
+#define INT_730_SHA1_MD5        (36 + IH2_BASE)
+#define INT_730_SPI_100K_2      (37 + IH2_BASE)
+#define INT_730_RNG_IDLE        (38 + IH2_BASE)
+#define INT_730_MPUIO           (39 + IH2_BASE)
+#define INT_730_LLPC_LCD_CTRL_CAN_BE_OFF        (40 + IH2_BASE)
+#define INT_730_LLPC_OE_FALLING (41 + IH2_BASE)
+#define INT_730_LLPC_OE_RISING  (42 + IH2_BASE)
+#define INT_730_LLPC_VSYNC      (43 + IH2_BASE)
+#define INT_730_WAKE_UP_REQ     (46 + IH2_BASE)
+#define INT_730_DMA_CH6         (53 + IH2_BASE)
+#define INT_730_DMA_CH7         (54 + IH2_BASE)
+#define INT_730_DMA_CH8         (55 + IH2_BASE)
+#define INT_730_DMA_CH9         (56 + IH2_BASE)
+#define INT_730_DMA_CH10        (57 + IH2_BASE)
+#define INT_730_DMA_CH11        (58 + IH2_BASE)
+#define INT_730_DMA_CH12        (59 + IH2_BASE)
+#define INT_730_DMA_CH13        (60 + IH2_BASE)
+#define INT_730_DMA_CH14        (61 + IH2_BASE)
+#define INT_730_DMA_CH15        (62 + IH2_BASE)
+#define INT_730_NAND            (63 + IH2_BASE)
+
+#define INT_24XX_SYS_NIRQ       7
+#define INT_24XX_SDMA_IRQ0      12
+#define INT_24XX_SDMA_IRQ1      13
+#define INT_24XX_SDMA_IRQ2      14
+#define INT_24XX_SDMA_IRQ3      15
+#define INT_24XX_CAM_IRQ        24
+#define INT_24XX_DSS_IRQ        25
+#define INT_24XX_MAIL_U0_MPU    26
+#define INT_24XX_DSP_UMA        27
+#define INT_24XX_DSP_MMU        28
+#define INT_24XX_GPIO_BANK1     29
+#define INT_24XX_GPIO_BANK2     30
+#define INT_24XX_GPIO_BANK3     31
+#define INT_24XX_GPIO_BANK4     32
+#define INT_24XX_GPIO_BANK5     33
+#define INT_24XX_MAIL_U3_MPU    34
+#define INT_24XX_GPTIMER1       37
+#define INT_24XX_GPTIMER2       38
+#define INT_24XX_GPTIMER3       39
+#define INT_24XX_GPTIMER4       40
+#define INT_24XX_GPTIMER5       41
+#define INT_24XX_GPTIMER6       42
+#define INT_24XX_GPTIMER7       43
+#define INT_24XX_GPTIMER8       44
+#define INT_24XX_GPTIMER9       45
+#define INT_24XX_GPTIMER10      46
+#define INT_24XX_GPTIMER11      47
+#define INT_24XX_GPTIMER12      48
+#define INT_24XX_I2C1_IRQ       56
+#define INT_24XX_I2C2_IRQ       57
+#define INT_24XX_MCBSP1_IRQ_TX  59
+#define INT_24XX_MCBSP1_IRQ_RX  60
+#define INT_24XX_MCBSP2_IRQ_TX  62
+#define INT_24XX_MCBSP2_IRQ_RX  63
+#define INT_24XX_UART1_IRQ      72
+#define INT_24XX_UART2_IRQ      73
+#define INT_24XX_UART3_IRQ      74
+#define INT_24XX_USB_IRQ_GEN    75
+#define INT_24XX_USB_IRQ_NISO   76
+#define INT_24XX_USB_IRQ_ISO    77
+#define INT_24XX_USB_IRQ_HGEN   78
+#define INT_24XX_USB_IRQ_HSOF   79
+#define INT_24XX_USB_IRQ_OTG    80
+#define INT_24XX_MMC_IRQ        83
+
+/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and
+ * 16 MPUIO lines */
+#define OMAP_MAX_GPIO_LINES     192
+#define IH_GPIO_BASE            (128 + IH2_BASE)
+#define IH_MPUIO_BASE           (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
+#define OMAP_IRQ_END            (IH_MPUIO_BASE + 16)
+
+/* External FPGA handles interrupts on Innovator boards */
+#define OMAP_FPGA_IRQ_BASE      (OMAP_IRQ_END)
+#ifdef  CONFIG_MACH_OMAP_INNOVATOR
+#define OMAP_FPGA_NR_IRQS       24
+#else
+#define OMAP_FPGA_NR_IRQS       0
+#endif
+#define OMAP_FPGA_IRQ_END       (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
+
+/* External TWL4030 can handle interrupts on 2430 and 34xx boards */
+#define TWL4030_IRQ_BASE        (OMAP_FPGA_IRQ_END)
+#ifdef  CONFIG_TWL4030_CORE
+#define TWL4030_BASE_NR_IRQS    8
+#define TWL4030_PWR_NR_IRQS     8
+#else
+#define TWL4030_BASE_NR_IRQS    0
+#define TWL4030_PWR_NR_IRQS     0
+#endif
+#define TWL4030_IRQ_END         (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
+#define TWL4030_PWR_IRQ_BASE    TWL4030_IRQ_END
+#define TWL4030_PWR_IRQ_END     (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)
+
+/* External TWL4030 gpio interrupts are optional */
+#define TWL4030_GPIO_IRQ_BASE   TWL4030_PWR_IRQ_END
+#ifdef  CONFIG_TWL4030_GPIO
+#define TWL4030_GPIO_NR_IRQS    18
+#else
+#define TWL4030_GPIO_NR_IRQS    0
+#endif
+#define TWL4030_GPIO_IRQ_END    (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
+
+/* Total number of interrupts depends on the enabled blocks above */
+#define NR_IRQS                 TWL4030_GPIO_IRQ_END
+
+#define OMAP_IRQ_BIT(irq)       (1 << ((irq) % 32))
+
+#ifndef __ASSEMBLY__
+extern void omap_init_irq(void);
+#endif
+
+#include <mach/hardware.h>
+
+#endif
diff --git a/arch/arm/plat-omap/include/mach/keypad.h b/arch/arm/plat-omap/include/mach/keypad.h
new file mode 100644
index 000000000000..232923aaf61d
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/keypad.h
@@ -0,0 +1,39 @@
+/*
+ *  arch/arm/plat-omap/include/mach/keypad.h
+ *
+ *  Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef ASMARM_ARCH_KEYPAD_H
+#define ASMARM_ARCH_KEYPAD_H
+
+struct omap_kp_platform_data {
+        int rows;
+        int cols;
+        int *keymap;
+        unsigned int keymapsize;
+        unsigned int rep:1;
+        unsigned long delay;
+        unsigned int dbounce:1;
+        /* specific to OMAP242x*/
+        unsigned int *row_gpios;
+        unsigned int *col_gpios;
+};
+
+/* Group (0..3) -- when multiple keys are pressed, only the
+ * keys pressed in the same group are considered as pressed. This is
+ * in order to workaround certain crappy HW designs that produce ghost
+ * keypresses. */
+#define GROUP_0         (0 << 16)
+#define GROUP_1         (1 << 16)
+#define GROUP_2         (2 << 16)
+#define GROUP_3         (3 << 16)
+#define GROUP_MASK      GROUP_3
+
+#define KEY(col, row, val) (((col) << 28) | ((row) << 24) | (val))
+
+#endif
+
diff --git a/include/asm-arm/arch-omap/lcd_mipid.h b/arch/arm/plat-omap/include/mach/lcd_mipid.h
index f8fbc4801e52..f8fbc4801e52 100644
--- a/include/asm-arm/arch-omap/lcd_mipid.h
+++ b/arch/arm/plat-omap/include/mach/lcd_mipid.h
diff --git a/arch/arm/plat-omap/include/mach/led.h b/arch/arm/plat-omap/include/mach/led.h
new file mode 100644
index 000000000000..25e451e7e2fd
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/led.h
@@ -0,0 +1,24 @@
+/*
+ *  arch/arm/plat-omap/include/mach/led.h
+ *
+ *  Copyright (C) 2006 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef ASMARM_ARCH_LED_H
+#define ASMARM_ARCH_LED_H
+
+struct omap_led_config {
+        struct led_classdev     cdev;
+        s16                     gpio;
+};
+
+struct omap_led_platform_data {
+        s16                     nr_leds;
+        struct omap_led_config  *leds;
+};
+
+#endif
diff --git a/include/asm-arm/arch-omap/mailbox.h b/arch/arm/plat-omap/include/mach/mailbox.h
index 7cbed9332e16..7cbed9332e16 100644
--- a/include/asm-arm/arch-omap/mailbox.h
+++ b/arch/arm/plat-omap/include/mach/mailbox.h
diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h b/arch/arm/plat-omap/include/mach/mcbsp.h
new file mode 100644
index 000000000000..6eb44a92871d
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/mcbsp.h
@@ -0,0 +1,380 @@
+/*
+ * arch/arm/plat-omap/include/mach/mcbsp.h
+ *
+ * Defines for Multi-Channel Buffered Serial Port
+ *
+ * Copyright (C) 2002 RidgeRun, Inc.
+ * Author: Steve Johnson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+#ifndef __ASM_ARCH_OMAP_MCBSP_H
+#define __ASM_ARCH_OMAP_MCBSP_H
+
+#include <linux/completion.h>
+#include <linux/spinlock.h>
+
+#include <mach/hardware.h>
+#include <mach/clock.h>
+
+#define OMAP730_MCBSP1_BASE     0xfffb1000
+#define OMAP730_MCBSP2_BASE     0xfffb1800
+
+#define OMAP1510_MCBSP1_BASE    0xe1011800
+#define OMAP1510_MCBSP2_BASE    0xfffb1000
+#define OMAP1510_MCBSP3_BASE    0xe1017000
+
+#define OMAP1610_MCBSP1_BASE    0xe1011800
+#define OMAP1610_MCBSP2_BASE    0xfffb1000
+#define OMAP1610_MCBSP3_BASE    0xe1017000
+
+#define OMAP24XX_MCBSP1_BASE    0x48074000
+#define OMAP24XX_MCBSP2_BASE    0x48076000
+
+#define OMAP34XX_MCBSP1_BASE    0x48074000
+#define OMAP34XX_MCBSP2_BASE    0x49022000
+
+#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)
+
+#define OMAP_MCBSP_REG_DRR2     0x00
+#define OMAP_MCBSP_REG_DRR1     0x02
+#define OMAP_MCBSP_REG_DXR2     0x04
+#define OMAP_MCBSP_REG_DXR1     0x06
+#define OMAP_MCBSP_REG_SPCR2    0x08
+#define OMAP_MCBSP_REG_SPCR1    0x0a
+#define OMAP_MCBSP_REG_RCR2     0x0c
+#define OMAP_MCBSP_REG_RCR1     0x0e
+#define OMAP_MCBSP_REG_XCR2     0x10
+#define OMAP_MCBSP_REG_XCR1     0x12
+#define OMAP_MCBSP_REG_SRGR2    0x14
+#define OMAP_MCBSP_REG_SRGR1    0x16
+#define OMAP_MCBSP_REG_MCR2     0x18
+#define OMAP_MCBSP_REG_MCR1     0x1a
+#define OMAP_MCBSP_REG_RCERA    0x1c
+#define OMAP_MCBSP_REG_RCERB    0x1e
+#define OMAP_MCBSP_REG_XCERA    0x20
+#define OMAP_MCBSP_REG_XCERB    0x22
+#define OMAP_MCBSP_REG_PCR0     0x24
+#define OMAP_MCBSP_REG_RCERC    0x26
+#define OMAP_MCBSP_REG_RCERD    0x28
+#define OMAP_MCBSP_REG_XCERC    0x2A
+#define OMAP_MCBSP_REG_XCERD    0x2C
+#define OMAP_MCBSP_REG_RCERE    0x2E
+#define OMAP_MCBSP_REG_RCERF    0x30
+#define OMAP_MCBSP_REG_XCERE    0x32
+#define OMAP_MCBSP_REG_XCERF    0x34
+#define OMAP_MCBSP_REG_RCERG    0x36
+#define OMAP_MCBSP_REG_RCERH    0x38
+#define OMAP_MCBSP_REG_XCERG    0x3A
+#define OMAP_MCBSP_REG_XCERH    0x3C
+
+#define OMAP_MAX_MCBSP_COUNT    3
+#define MAX_MCBSP_CLOCKS        3
+
+#define AUDIO_MCBSP_DATAWRITE   (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
+#define AUDIO_MCBSP_DATAREAD    (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
+
+#define AUDIO_MCBSP             OMAP_MCBSP1
+#define AUDIO_DMA_TX            OMAP_DMA_MCBSP1_TX
+#define AUDIO_DMA_RX            OMAP_DMA_MCBSP1_RX
+
+#elif defined(CONFIG_ARCH_OMAP24XX)
+
+#define OMAP_MCBSP_REG_DRR2     0x00
+#define OMAP_MCBSP_REG_DRR1     0x04
+#define OMAP_MCBSP_REG_DXR2     0x08
+#define OMAP_MCBSP_REG_DXR1     0x0C
+#define OMAP_MCBSP_REG_SPCR2    0x10
+#define OMAP_MCBSP_REG_SPCR1    0x14
+#define OMAP_MCBSP_REG_RCR2     0x18
+#define OMAP_MCBSP_REG_RCR1     0x1C
+#define OMAP_MCBSP_REG_XCR2     0x20
+#define OMAP_MCBSP_REG_XCR1     0x24
+#define OMAP_MCBSP_REG_SRGR2    0x28
+#define OMAP_MCBSP_REG_SRGR1    0x2C
+#define OMAP_MCBSP_REG_MCR2     0x30
+#define OMAP_MCBSP_REG_MCR1     0x34
+#define OMAP_MCBSP_REG_RCERA    0x38
+#define OMAP_MCBSP_REG_RCERB    0x3C
+#define OMAP_MCBSP_REG_XCERA    0x40
+#define OMAP_MCBSP_REG_XCERB    0x44
+#define OMAP_MCBSP_REG_PCR0     0x48
+#define OMAP_MCBSP_REG_RCERC    0x4C
+#define OMAP_MCBSP_REG_RCERD    0x50
+#define OMAP_MCBSP_REG_XCERC    0x54
+#define OMAP_MCBSP_REG_XCERD    0x58
+#define OMAP_MCBSP_REG_RCERE    0x5C
+#define OMAP_MCBSP_REG_RCERF    0x60
+#define OMAP_MCBSP_REG_XCERE    0x64
+#define OMAP_MCBSP_REG_XCERF    0x68
+#define OMAP_MCBSP_REG_RCERG    0x6C
+#define OMAP_MCBSP_REG_RCERH    0x70
+#define OMAP_MCBSP_REG_XCERG    0x74
+#define OMAP_MCBSP_REG_XCERH    0x78
+
+#define OMAP_MAX_MCBSP_COUNT    2
+#define MAX_MCBSP_CLOCKS        2
+
+#define AUDIO_MCBSP_DATAWRITE   (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
+#define AUDIO_MCBSP_DATAREAD    (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
+
+#define AUDIO_MCBSP             OMAP_MCBSP2
+#define AUDIO_DMA_TX            OMAP24XX_DMA_MCBSP2_TX
+#define AUDIO_DMA_RX            OMAP24XX_DMA_MCBSP2_RX
+
+#endif
+
+#define OMAP_MCBSP_READ(base, reg)              __raw_readw((base) + OMAP_MCBSP_REG_##reg)
+#define OMAP_MCBSP_WRITE(base, reg, val)        __raw_writew((val), (base) + OMAP_MCBSP_REG_##reg)
+
+
+/************************** McBSP SPCR1 bit definitions ***********************/
+#define RRST                    0x0001
+#define RRDY                    0x0002
+#define RFULL                   0x0004
+#define RSYNC_ERR               0x0008
+#define RINTM(value)            ((value)<<4)    /* bits 4:5 */
+#define ABIS                    0x0040
+#define DXENA                   0x0080
+#define CLKSTP(value)           ((value)<<11)   /* bits 11:12 */
+#define RJUST(value)            ((value)<<13)   /* bits 13:14 */
+#define DLB                     0x8000
+
+/************************** McBSP SPCR2 bit definitions ***********************/
+#define XRST            0x0001
+#define XRDY            0x0002
+#define XEMPTY          0x0004
+#define XSYNC_ERR       0x0008
+#define XINTM(value)    ((value)<<4)            /* bits 4:5 */
+#define GRST            0x0040
+#define FRST            0x0080
+#define SOFT            0x0100
+#define FREE            0x0200
+
+/************************** McBSP PCR bit definitions *************************/
+#define CLKRP           0x0001
+#define CLKXP           0x0002
+#define FSRP            0x0004
+#define FSXP            0x0008
+#define DR_STAT         0x0010
+#define DX_STAT         0x0020
+#define CLKS_STAT       0x0040
+#define SCLKME          0x0080
+#define CLKRM           0x0100
+#define CLKXM           0x0200
+#define FSRM            0x0400
+#define FSXM            0x0800
+#define RIOEN           0x1000
+#define XIOEN           0x2000
+#define IDLE_EN         0x4000
+
+/************************** McBSP RCR1 bit definitions ************************/
+#define RWDLEN1(value)          ((value)<<5)    /* Bits 5:7 */
+#define RFRLEN1(value)          ((value)<<8)    /* Bits 8:14 */
+
+/************************** McBSP XCR1 bit definitions ************************/
+#define XWDLEN1(value)          ((value)<<5)    /* Bits 5:7 */
+#define XFRLEN1(value)          ((value)<<8)    /* Bits 8:14 */
+
+/*************************** McBSP RCR2 bit definitions ***********************/
+#define RDATDLY(value)          (value)         /* Bits 0:1 */
+#define RFIG                    0x0004
+#define RCOMPAND(value)         ((value)<<3)    /* Bits 3:4 */
+#define RWDLEN2(value)          ((value)<<5)    /* Bits 5:7 */
+#define RFRLEN2(value)          ((value)<<8)    /* Bits 8:14 */
+#define RPHASE                  0x8000
+
+/*************************** McBSP XCR2 bit definitions ***********************/
+#define XDATDLY(value)          (value)         /* Bits 0:1 */
+#define XFIG                    0x0004
+#define XCOMPAND(value)         ((value)<<3)    /* Bits 3:4 */
+#define XWDLEN2(value)          ((value)<<5)    /* Bits 5:7 */
+#define XFRLEN2(value)          ((value)<<8)    /* Bits 8:14 */
+#define XPHASE                  0x8000
+
+/************************* McBSP SRGR1 bit definitions ************************/
+#define CLKGDV(value)           (value)         /* Bits 0:7 */
+#define FWID(value)             ((value)<<8)    /* Bits 8:15 */
+
+/************************* McBSP SRGR2 bit definitions ************************/
+#define FPER(value)             (value)         /* Bits 0:11 */
+#define FSGM                    0x1000
+#define CLKSM                   0x2000
+#define CLKSP                   0x4000
+#define GSYNC                   0x8000
+
+/************************* McBSP MCR1 bit definitions *************************/
+#define RMCM                    0x0001
+#define RCBLK(value)            ((value)<<2)    /* Bits 2:4 */
+#define RPABLK(value)           ((value)<<5)    /* Bits 5:6 */
+#define RPBBLK(value)           ((value)<<7)    /* Bits 7:8 */
+
+/************************* McBSP MCR2 bit definitions *************************/
+#define XMCM(value)             (value)         /* Bits 0:1 */
+#define XCBLK(value)            ((value)<<2)    /* Bits 2:4 */
+#define XPABLK(value)           ((value)<<5)    /* Bits 5:6 */
+#define XPBBLK(value)           ((value)<<7)    /* Bits 7:8 */
+
+
+/* we don't do multichannel for now */
+struct omap_mcbsp_reg_cfg {
+        u16 spcr2;
+        u16 spcr1;
+        u16 rcr2;
+        u16 rcr1;
+        u16 xcr2;
+        u16 xcr1;
+        u16 srgr2;
+        u16 srgr1;
+        u16 mcr2;
+        u16 mcr1;
+        u16 pcr0;
+        u16 rcerc;
+        u16 rcerd;
+        u16 xcerc;
+        u16 xcerd;
+        u16 rcere;
+        u16 rcerf;
+        u16 xcere;
+        u16 xcerf;
+        u16 rcerg;
+        u16 rcerh;
+        u16 xcerg;
+        u16 xcerh;
+};
+
+typedef enum {
+        OMAP_MCBSP1 = 0,
+        OMAP_MCBSP2,
+        OMAP_MCBSP3,
+} omap_mcbsp_id;
+
+typedef int __bitwise omap_mcbsp_io_type_t;
+#define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
+#define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)
+
+typedef enum {
+        OMAP_MCBSP_WORD_8 = 0,
+        OMAP_MCBSP_WORD_12,
+        OMAP_MCBSP_WORD_16,
+        OMAP_MCBSP_WORD_20,
+        OMAP_MCBSP_WORD_24,
+        OMAP_MCBSP_WORD_32,
+} omap_mcbsp_word_length;
+
+typedef enum {
+        OMAP_MCBSP_CLK_RISING = 0,
+        OMAP_MCBSP_CLK_FALLING,
+} omap_mcbsp_clk_polarity;
+
+typedef enum {
+        OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
+        OMAP_MCBSP_FS_ACTIVE_LOW,
+} omap_mcbsp_fs_polarity;
+
+typedef enum {
+        OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
+        OMAP_MCBSP_CLK_STP_MODE_DELAY,
+} omap_mcbsp_clk_stp_mode;
+
+
+/******* SPI specific mode **********/
+typedef enum {
+        OMAP_MCBSP_SPI_MASTER = 0,
+        OMAP_MCBSP_SPI_SLAVE,
+} omap_mcbsp_spi_mode;
+
+struct omap_mcbsp_spi_cfg {
+        omap_mcbsp_spi_mode             spi_mode;
+        omap_mcbsp_clk_polarity         rx_clock_polarity;
+        omap_mcbsp_clk_polarity         tx_clock_polarity;
+        omap_mcbsp_fs_polarity          fsx_polarity;
+        u8                              clk_div;
+        omap_mcbsp_clk_stp_mode         clk_stp_mode;
+        omap_mcbsp_word_length          word_length;
+};
+
+/* Platform specific configuration */
+struct omap_mcbsp_ops {
+        void (*request)(unsigned int);
+        void (*free)(unsigned int);
+        int (*check)(unsigned int);
+};
+
+struct omap_mcbsp_platform_data {
+        u32 virt_base;
+        u8 dma_rx_sync, dma_tx_sync;
+        u16 rx_irq, tx_irq;
+        struct omap_mcbsp_ops *ops;
+        char const *clk_name;
+};
+
+struct omap_mcbsp {
+        struct device *dev;
+        u32 io_base;
+        u8 id;
+        u8 free;
+        omap_mcbsp_word_length rx_word_length;
+        omap_mcbsp_word_length tx_word_length;
+
+        omap_mcbsp_io_type_t io_type; /* IRQ or poll */
+        /* IRQ based TX/RX */
+        int rx_irq;
+        int tx_irq;
+
+        /* DMA stuff */
+        u8 dma_rx_sync;
+        short dma_rx_lch;
+        u8 dma_tx_sync;
+        short dma_tx_lch;
+
+        /* Completion queues */
+        struct completion tx_irq_completion;
+        struct completion rx_irq_completion;
+        struct completion tx_dma_completion;
+        struct completion rx_dma_completion;
+
+        /* Protect the field .free, while checking if the mcbsp is in use */
+        spinlock_t lock;
+        struct omap_mcbsp_platform_data *pdata;
+        struct clk *clk;
+};
+
+int omap_mcbsp_init(void);
+void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
+                                        int size);
+void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
+int omap_mcbsp_request(unsigned int id);
+void omap_mcbsp_free(unsigned int id);
+void omap_mcbsp_start(unsigned int id);
+void omap_mcbsp_stop(unsigned int id);
+void omap_mcbsp_xmit_word(unsigned int id, u32 word);
+u32 omap_mcbsp_recv_word(unsigned int id);
+
+int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
+int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
+int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
+int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
+
+
+/* SPI specific API */
+void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
+
+/* Polled read/write functions */
+int omap_mcbsp_pollread(unsigned int id, u16 * buf);
+int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
+
+#endif
diff --git a/include/asm-arm/arch-omap/mcspi.h b/arch/arm/plat-omap/include/mach/mcspi.h
index 1254e4945b6f..1254e4945b6f 100644
--- a/include/asm-arm/arch-omap/mcspi.h
+++ b/arch/arm/plat-omap/include/mach/mcspi.h
diff --git a/arch/arm/plat-omap/include/mach/memory.h b/arch/arm/plat-omap/include/mach/memory.h
new file mode 100644
index 000000000000..037486c5f4a4
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/memory.h
@@ -0,0 +1,103 @@
+/*
+ * arch/arm/plat-omap/include/mach/memory.h
+ *
+ * Memory map for OMAP-1510 and 1610
+ *
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Author: Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * This file was derived from arch/arm/mach-intergrator/include/mach/memory.h
+ * Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset.
+ */
+#if defined(CONFIG_ARCH_OMAP1)
+#define PHYS_OFFSET             UL(0x10000000)
+#elif defined(CONFIG_ARCH_OMAP2)
+#define PHYS_OFFSET             UL(0x80000000)
+#endif
+
+/*
+ * Conversion between SDRAM and fake PCI bus, used by USB
+ * NOTE: Physical address must be converted to Local Bus address
+ *       on OMAP-1510 only
+ */
+
+/*
+ * Bus address is physical address, except for OMAP-1510 Local Bus.
+ */
+#define __virt_to_bus(x)        __virt_to_phys(x)
+#define __bus_to_virt(x)        __phys_to_virt(x)
+
+/*
+ * OMAP-1510 bus address is translated into a Local Bus address if the
+ * OMAP bus type is lbus. We do the address translation based on the
+ * device overriding the defaults used in the dma-mapping API.
+ * Note that the is_lbus_device() test is not very efficient on 1510
+ * because of the strncmp().
+ */
+#ifdef CONFIG_ARCH_OMAP15XX
+
+/*
+ * OMAP-1510 Local Bus address offset
+ */
+#define OMAP1510_LB_OFFSET      UL(0x30000000)
+
+#define virt_to_lbus(x)         ((x) - PAGE_OFFSET + OMAP1510_LB_OFFSET)
+#define lbus_to_virt(x)         ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET)
+#define is_lbus_device(dev)     (cpu_is_omap15xx() && dev && (strncmp(dev->bus_id, "ohci", 4) == 0))
+
+#define __arch_page_to_dma(dev, page)   ({is_lbus_device(dev) ? \
+                                        (dma_addr_t)virt_to_lbus(page_address(page)) : \
+                                        (dma_addr_t)__virt_to_bus(page_address(page));})
+
+#define __arch_dma_to_virt(dev, addr)   ({is_lbus_device(dev) ? \
+                                        lbus_to_virt(addr) : \
+                                        __bus_to_virt(addr);})
+
+#define __arch_virt_to_dma(dev, addr)   ({is_lbus_device(dev) ? \
+                                        virt_to_lbus(addr) : \
+                                        __virt_to_bus(addr);})
+
+#endif  /* CONFIG_ARCH_OMAP15XX */
+
+/* Override the ARM default */
+#ifdef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
+
+#if (CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE == 0)
+#undef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
+#define CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE 2
+#endif
+
+#define CONSISTENT_DMA_SIZE \
+        (((CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE + 1) & ~1) * 1024 * 1024)
+
+#endif
+
+#endif
+
diff --git a/arch/arm/plat-omap/include/mach/menelaus.h b/arch/arm/plat-omap/include/mach/menelaus.h
new file mode 100644
index 000000000000..3122bf68c7ce
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/menelaus.h
@@ -0,0 +1,49 @@
+/*
+ * arch/arm/plat-omap/include/mach/menelaus.h
+ *
+ * Functions to access Menelaus power management chip
+ */
+
+#ifndef __ASM_ARCH_MENELAUS_H
+#define __ASM_ARCH_MENELAUS_H
+
+struct device;
+
+struct menelaus_platform_data {
+        int (* late_init)(struct device *dev);
+};
+
+extern int menelaus_register_mmc_callback(void (*callback)(void *data, u8 card_mask),
+                                          void *data);
+extern void menelaus_unregister_mmc_callback(void);
+extern int menelaus_set_mmc_opendrain(int slot, int enable);
+extern int menelaus_set_mmc_slot(int slot, int enable, int power, int cd_on);
+
+extern int menelaus_set_vmem(unsigned int mV);
+extern int menelaus_set_vio(unsigned int mV);
+extern int menelaus_set_vmmc(unsigned int mV);
+extern int menelaus_set_vaux(unsigned int mV);
+extern int menelaus_set_vdcdc(int dcdc, unsigned int mV);
+extern int menelaus_set_slot_sel(int enable);
+extern int menelaus_get_slot_pin_states(void);
+extern int menelaus_set_vcore_sw(unsigned int mV);
+extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV);
+
+#define EN_VPLL_SLEEP   (1 << 7)
+#define EN_VMMC_SLEEP   (1 << 6)
+#define EN_VAUX_SLEEP   (1 << 5)
+#define EN_VIO_SLEEP    (1 << 4)
+#define EN_VMEM_SLEEP   (1 << 3)
+#define EN_DC3_SLEEP    (1 << 2)
+#define EN_DC2_SLEEP    (1 << 1)
+#define EN_VC_SLEEP     (1 << 0)
+
+extern int menelaus_set_regulator_sleep(int enable, u32 val);
+
+#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_MENELAUS)
+#define omap_has_menelaus()     1
+#else
+#define omap_has_menelaus()     0
+#endif
+
+#endif
diff --git a/arch/arm/plat-omap/include/mach/mmc.h b/arch/arm/plat-omap/include/mach/mmc.h
new file mode 100644
index 000000000000..fc15d13058fc
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/mmc.h
@@ -0,0 +1,74 @@
+/*
+ * MMC definitions for OMAP2
+ *
+ * Copyright (C) 2006 Nokia Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __OMAP2_MMC_H
+#define __OMAP2_MMC_H
+
+#include <linux/types.h>
+#include <linux/device.h>
+#include <linux/mmc/host.h>
+
+#include <mach/board.h>
+
+#define OMAP_MMC_MAX_SLOTS      2
+
+struct omap_mmc_platform_data {
+        struct omap_mmc_conf    conf;
+
+        /* number of slots on board */
+        unsigned nr_slots:2;
+
+        /* set if your board has components or wiring that limits the
+         * maximum frequency on the MMC bus */
+        unsigned int max_freq;
+
+        /* switch the bus to a new slot */
+        int (* switch_slot)(struct device *dev, int slot);
+        /* initialize board-specific MMC functionality, can be NULL if
+         * not supported */
+        int (* init)(struct device *dev);
+        void (* cleanup)(struct device *dev);
+        void (* shutdown)(struct device *dev);
+
+        /* To handle board related suspend/resume functionality for MMC */
+        int (*suspend)(struct device *dev, int slot);
+        int (*resume)(struct device *dev, int slot);
+
+        struct omap_mmc_slot_data {
+                int (* set_bus_mode)(struct device *dev, int slot, int bus_mode);
+                int (* set_power)(struct device *dev, int slot, int power_on, int vdd);
+                int (* get_ro)(struct device *dev, int slot);
+
+                /* return MMC cover switch state, can be NULL if not supported.
+                 *
+                 * possible return values:
+                 *   0 - open
+                 *   1 - closed
+                 */
+                int (* get_cover_state)(struct device *dev, int slot);
+
+                const char *name;
+                u32 ocr_mask;
+
+                /* Card detection IRQs */
+                int card_detect_irq;
+                int (* card_detect)(int irq);
+
+                unsigned int ban_openended:1;
+
+        } slots[OMAP_MMC_MAX_SLOTS];
+};
+
+extern void omap_set_mmc_info(int host, const struct omap_mmc_platform_data *info);
+
+/* called from board-specific card detection service routine */
+extern void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed);
+
+#endif
diff --git a/arch/arm/plat-omap/include/mach/mtd-xip.h b/arch/arm/plat-omap/include/mach/mtd-xip.h
new file mode 100644
index 000000000000..5cee7e16a1b4
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/mtd-xip.h
@@ -0,0 +1,61 @@
+/*
+ * MTD primitives for XIP support. Architecture specific functions.
+ *
+ * Do not include this file directly. It's included from linux/mtd/xip.h
+ *
+ * Author: Vladimir Barinov <vbarinov@ru.mvista.com>
+ *
+ * (c) 2005 MontaVista Software, Inc.  This file is licensed under the
+ * terms of the GNU General Public License version 2.  This program is
+ * licensed "as is" without any warranty of any kind, whether express or
+ * implied.
+ */
+
+#ifndef __ARCH_OMAP_MTD_XIP_H__
+#define __ARCH_OMAP_MTD_XIP_H__
+
+#include <mach/hardware.h>
+#define OMAP_MPU_TIMER_BASE     (0xfffec500)
+#define OMAP_MPU_TIMER_OFFSET   0x100
+
+typedef struct {
+        u32 cntl;                       /* CNTL_TIMER, R/W */
+        u32 load_tim;                   /* LOAD_TIM,   W */
+        u32 read_tim;                   /* READ_TIM,   R */
+} xip_omap_mpu_timer_regs_t;
+
+#define xip_omap_mpu_timer_base(n)                                      \
+((volatile xip_omap_mpu_timer_regs_t*)IO_ADDRESS(OMAP_MPU_TIMER_BASE +  \
+        (n)*OMAP_MPU_TIMER_OFFSET))
+
+static inline unsigned long xip_omap_mpu_timer_read(int nr)
+{
+        volatile xip_omap_mpu_timer_regs_t* timer = xip_omap_mpu_timer_base(nr);
+        return timer->read_tim;
+}
+
+#define xip_irqpending()        \
+        (omap_readl(OMAP_IH1_ITR) & ~omap_readl(OMAP_IH1_MIR))
+#define xip_currtime()          (~xip_omap_mpu_timer_read(0))
+
+/*
+ * It's permitted to do approxmation for xip_elapsed_since macro
+ * (see linux/mtd/xip.h)
+ */
+
+#ifdef CONFIG_MACH_OMAP_PERSEUS2
+#define xip_elapsed_since(x)    (signed)((~xip_omap_mpu_timer_read(0) - (x)) / 7)
+#else
+#define xip_elapsed_since(x)    (signed)((~xip_omap_mpu_timer_read(0) - (x)) / 6)
+#endif
+
+/*
+ * xip_cpu_idle() is used when waiting for a delay equal or larger than
+ * the system timer tick period.  This should put the CPU into idle mode
+ * to save power and to be woken up only when some interrupts are pending.
+ * As above, this should not rely upon standard kernel code.
+ */
+
+#define xip_cpu_idle()  asm volatile ("mcr p15, 0, %0, c7, c0, 4" :: "r" (1))
+
+#endif /* __ARCH_OMAP_MTD_XIP_H__ */
diff --git a/arch/arm/plat-omap/include/mach/mux.h b/arch/arm/plat-omap/include/mach/mux.h
new file mode 100644
index 000000000000..614b2c1327c7
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/mux.h
@@ -0,0 +1,615 @@
+/*
+ * arch/arm/plat-omap/include/mach/mux.h
+ *
+ * Table of the Omap register configurations for the FUNC_MUX and
+ * PULL_DWN combinations.
+ *
+ * Copyright (C) 2004 - 2008 Texas Instruments Inc.
+ * Copyright (C) 2003 - 2008 Nokia Corporation
+ *
+ * Written by Tony Lindgren
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * NOTE: Please use the following naming style for new pin entries.
+ *       For example, W8_1610_MMC2_DAT0, where:
+ *       - W8        = ball
+ *       - 1610      = 1510 or 1610, none if common for both 1510 and 1610
+ *       - MMC2_DAT0 = function
+ */
+
+#ifndef __ASM_ARCH_MUX_H
+#define __ASM_ARCH_MUX_H
+
+#define PU_PD_SEL_NA            0       /* No pu_pd reg available */
+#define PULL_DWN_CTRL_NA        0       /* No pull-down control needed */
+
+#ifdef  CONFIG_OMAP_MUX_DEBUG
+#define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
+                                        .mux_reg = FUNC_MUX_CTRL_##reg, \
+                                        .mask_offset = mode_offset, \
+                                        .mask = mode,
+
+#define PULL_REG(reg, bit, status)      .pull_name = "PULL_DWN_CTRL_"#reg, \
+                                        .pull_reg = PULL_DWN_CTRL_##reg, \
+                                        .pull_bit = bit, \
+                                        .pull_val = status,
+
+#define PU_PD_REG(reg, status)          .pu_pd_name = "PU_PD_SEL_"#reg, \
+                                        .pu_pd_reg = PU_PD_SEL_##reg, \
+                                        .pu_pd_val = status,
+
+#define MUX_REG_730(reg, mode_offset, mode) .mux_reg_name = "OMAP730_IO_CONF_"#reg, \
+                                        .mux_reg = OMAP730_IO_CONF_##reg, \
+                                        .mask_offset = mode_offset, \
+                                        .mask = mode,
+
+#define PULL_REG_730(reg, bit, status)  .pull_name = "OMAP730_IO_CONF_"#reg, \
+                                        .pull_reg = OMAP730_IO_CONF_##reg, \
+                                        .pull_bit = bit, \
+                                        .pull_val = status,
+
+#else
+
+#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
+                                        .mask_offset = mode_offset, \
+                                        .mask = mode,
+
+#define PULL_REG(reg, bit, status)      .pull_reg = PULL_DWN_CTRL_##reg, \
+                                        .pull_bit = bit, \
+                                        .pull_val = status,
+
+#define PU_PD_REG(reg, status)          .pu_pd_reg = PU_PD_SEL_##reg, \
+                                        .pu_pd_val = status,
+
+#define MUX_REG_730(reg, mode_offset, mode) \
+                                        .mux_reg = OMAP730_IO_CONF_##reg, \
+                                        .mask_offset = mode_offset, \
+                                        .mask = mode,
+
+#define PULL_REG_730(reg, bit, status)  .pull_reg = OMAP730_IO_CONF_##reg, \
+                                        .pull_bit = bit, \
+                                        .pull_val = status,
+
+#endif /* CONFIG_OMAP_MUX_DEBUG */
+
+#define MUX_CFG(desc, mux_reg, mode_offset, mode,       \
+                pull_reg, pull_bit, pull_status,        \
+                pu_pd_reg, pu_pd_status, debug_status)  \
+{                                                       \
+        .name =  desc,                                  \
+        .debug = debug_status,                          \
+        MUX_REG(mux_reg, mode_offset, mode)             \
+        PULL_REG(pull_reg, pull_bit, pull_status)       \
+        PU_PD_REG(pu_pd_reg, pu_pd_status)              \
+},
+
+
+/*
+ * OMAP730 has a slightly different config for the pin mux.
+ * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and
+ *   not the FUNC_MUX_CTRL_x regs from hardware.h
+ * - for pull-up/down, only has one enable bit which is is in the same register
+ *   as mux config
+ */
+#define MUX_CFG_730(desc, mux_reg, mode_offset, mode,   \
+                   pull_bit, pull_status, debug_status)\
+{                                                       \
+        .name =  desc,                                  \
+        .debug = debug_status,                          \
+        MUX_REG_730(mux_reg, mode_offset, mode)         \
+        PULL_REG_730(mux_reg, pull_bit, pull_status)    \
+        PU_PD_REG(NA, 0)                \
+},
+
+#define MUX_CFG_24XX(desc, reg_offset, mode,                    \
+                                pull_en, pull_mode, dbg)        \
+{                                                               \
+        .name           = desc,                                 \
+        .debug          = dbg,                                  \
+        .mux_reg        = reg_offset,                           \
+        .mask           = mode,                                 \
+        .pull_val       = pull_en,                              \
+        .pu_pd_val      = pull_mode,                            \
+},
+
+
+#define PULL_DISABLED   0
+#define PULL_ENABLED    1
+
+#define PULL_DOWN       0
+#define PULL_UP         1
+
+struct pin_config {
+        char *name;
+        unsigned char busy;
+        unsigned char debug;
+
+        const char *mux_reg_name;
+        const unsigned int mux_reg;
+        const unsigned char mask_offset;
+        const unsigned char mask;
+
+        const char *pull_name;
+        const unsigned int pull_reg;
+        const unsigned char pull_val;
+        const unsigned char pull_bit;
+
+        const char *pu_pd_name;
+        const unsigned int pu_pd_reg;
+        const unsigned char pu_pd_val;
+};
+
+enum omap730_index {
+        /* OMAP 730 keyboard */
+        E2_730_KBR0,
+        J7_730_KBR1,
+        E1_730_KBR2,
+        F3_730_KBR3,
+        D2_730_KBR4,
+        C2_730_KBC0,
+        D3_730_KBC1,
+        E4_730_KBC2,
+        F4_730_KBC3,
+        E3_730_KBC4,
+
+        /* USB */
+        AA17_730_USB_DM,
+        W16_730_USB_PU_EN,
+        W17_730_USB_VBUSI,
+};
+
+enum omap1xxx_index {
+        /* UART1 (BT_UART_GATING)*/
+        UART1_TX = 0,
+        UART1_RTS,
+
+        /* UART2 (COM_UART_GATING)*/
+        UART2_TX,
+        UART2_RX,
+        UART2_CTS,
+        UART2_RTS,
+
+        /* UART3 (GIGA_UART_GATING) */
+        UART3_TX,
+        UART3_RX,
+        UART3_CTS,
+        UART3_RTS,
+        UART3_CLKREQ,
+        UART3_BCLK,     /* 12MHz clock out */
+        Y15_1610_UART3_RTS,
+
+        /* PWT & PWL */
+        PWT,
+        PWL,
+
+        /* USB master generic */
+        R18_USB_VBUS,
+        R18_1510_USB_GPIO0,
+        W4_USB_PUEN,
+        W4_USB_CLKO,
+        W4_USB_HIGHZ,
+        W4_GPIO58,
+
+        /* USB1 master */
+        USB1_SUSP,
+        USB1_SEO,
+        W13_1610_USB1_SE0,
+        USB1_TXEN,
+        USB1_TXD,
+        USB1_VP,
+        USB1_VM,
+        USB1_RCV,
+        USB1_SPEED,
+        R13_1610_USB1_SPEED,
+        R13_1710_USB1_SE0,
+
+        /* USB2 master */
+        USB2_SUSP,
+        USB2_VP,
+        USB2_TXEN,
+        USB2_VM,
+        USB2_RCV,
+        USB2_SEO,
+        USB2_TXD,
+
+        /* OMAP-1510 GPIO */
+        R18_1510_GPIO0,
+        R19_1510_GPIO1,
+        M14_1510_GPIO2,
+
+        /* OMAP1610 GPIO */
+        P18_1610_GPIO3,
+        Y15_1610_GPIO17,
+
+        /* OMAP-1710 GPIO */
+        R18_1710_GPIO0,
+        V2_1710_GPIO10,
+        N21_1710_GPIO14,
+        W15_1710_GPIO40,
+
+        /* MPUIO */
+        MPUIO2,
+        N15_1610_MPUIO2,
+        MPUIO4,
+        MPUIO5,
+        T20_1610_MPUIO5,
+        W11_1610_MPUIO6,
+        V10_1610_MPUIO7,
+        W11_1610_MPUIO9,
+        V10_1610_MPUIO10,
+        W10_1610_MPUIO11,
+        E20_1610_MPUIO13,
+        U20_1610_MPUIO14,
+        E19_1610_MPUIO15,
+
+        /* MCBSP2 */
+        MCBSP2_CLKR,
+        MCBSP2_CLKX,
+        MCBSP2_DR,
+        MCBSP2_DX,
+        MCBSP2_FSR,
+        MCBSP2_FSX,
+
+        /* MCBSP3 */
+        MCBSP3_CLKX,
+
+        /* Misc ballouts */
+        BALLOUT_V8_ARMIO3,
+        N20_HDQ,
+
+        /* OMAP-1610 MMC2 */
+        W8_1610_MMC2_DAT0,
+        V8_1610_MMC2_DAT1,
+        W15_1610_MMC2_DAT2,
+        R10_1610_MMC2_DAT3,
+        Y10_1610_MMC2_CLK,
+        Y8_1610_MMC2_CMD,
+        V9_1610_MMC2_CMDDIR,
+        V5_1610_MMC2_DATDIR0,
+        W19_1610_MMC2_DATDIR1,
+        R18_1610_MMC2_CLKIN,
+
+        /* OMAP-1610 External Trace Interface */
+        M19_1610_ETM_PSTAT0,
+        L15_1610_ETM_PSTAT1,
+        L18_1610_ETM_PSTAT2,
+        L19_1610_ETM_D0,
+        J19_1610_ETM_D6,
+        J18_1610_ETM_D7,
+
+        /* OMAP16XX GPIO */
+        P20_1610_GPIO4,
+        V9_1610_GPIO7,
+        W8_1610_GPIO9,
+        N20_1610_GPIO11,
+        N19_1610_GPIO13,
+        P10_1610_GPIO22,
+        V5_1610_GPIO24,
+        AA20_1610_GPIO_41,
+        W19_1610_GPIO48,
+        M7_1610_GPIO62,
+        V14_16XX_GPIO37,
+        R9_16XX_GPIO18,
+        L14_16XX_GPIO49,
+
+        /* OMAP-1610 uWire */
+        V19_1610_UWIRE_SCLK,
+        U18_1610_UWIRE_SDI,
+        W21_1610_UWIRE_SDO,
+        N14_1610_UWIRE_CS0,
+        P15_1610_UWIRE_CS3,
+        N15_1610_UWIRE_CS1,
+
+        /* OMAP-1610 SPI */
+        U19_1610_SPIF_SCK,
+        U18_1610_SPIF_DIN,
+        P20_1610_SPIF_DIN,
+        W21_1610_SPIF_DOUT,
+        R18_1610_SPIF_DOUT,
+        N14_1610_SPIF_CS0,
+        N15_1610_SPIF_CS1,
+        T19_1610_SPIF_CS2,
+        P15_1610_SPIF_CS3,
+
+        /* OMAP-1610 Flash */
+        L3_1610_FLASH_CS2B_OE,
+        M8_1610_FLASH_CS2B_WE,
+
+        /* First MMC */
+        MMC_CMD,
+        MMC_DAT1,
+        MMC_DAT2,
+        MMC_DAT0,
+        MMC_CLK,
+        MMC_DAT3,
+
+        /* OMAP-1710 MMC CMDDIR and DATDIR0 */
+        M15_1710_MMC_CLKI,
+        P19_1710_MMC_CMDDIR,
+        P20_1710_MMC_DATDIR0,
+
+        /* OMAP-1610 USB0 alternate pin configuration */
+        W9_USB0_TXEN,
+        AA9_USB0_VP,
+        Y5_USB0_RCV,
+        R9_USB0_VM,
+        V6_USB0_TXD,
+        W5_USB0_SE0,
+        V9_USB0_SPEED,
+        V9_USB0_SUSP,
+
+        /* USB2 */
+        W9_USB2_TXEN,
+        AA9_USB2_VP,
+        Y5_USB2_RCV,
+        R9_USB2_VM,
+        V6_USB2_TXD,
+        W5_USB2_SE0,
+
+        /* 16XX UART */
+        R13_1610_UART1_TX,
+        V14_16XX_UART1_RX,
+        R14_1610_UART1_CTS,
+        AA15_1610_UART1_RTS,
+        R9_16XX_UART2_RX,
+        L14_16XX_UART3_RX,
+
+        /* I2C OMAP-1610 */
+        I2C_SCL,
+        I2C_SDA,
+
+        /* Keypad */
+        F18_1610_KBC0,
+        D20_1610_KBC1,
+        D19_1610_KBC2,
+        E18_1610_KBC3,
+        C21_1610_KBC4,
+        G18_1610_KBR0,
+        F19_1610_KBR1,
+        H14_1610_KBR2,
+        E20_1610_KBR3,
+        E19_1610_KBR4,
+        N19_1610_KBR5,
+
+        /* Power management */
+        T20_1610_LOW_PWR,
+
+        /* MCLK Settings */
+        V5_1710_MCLK_ON,
+        V5_1710_MCLK_OFF,
+        R10_1610_MCLK_ON,
+        R10_1610_MCLK_OFF,
+
+        /* CompactFlash controller */
+        P11_1610_CF_CD2,
+        R11_1610_CF_IOIS16,
+        V10_1610_CF_IREQ,
+        W10_1610_CF_RESET,
+        W11_1610_CF_CD1,
+
+        /* parallel camera */
+        J15_1610_CAM_LCLK,
+        J18_1610_CAM_D7,
+        J19_1610_CAM_D6,
+        J14_1610_CAM_D5,
+        K18_1610_CAM_D4,
+        K19_1610_CAM_D3,
+        K15_1610_CAM_D2,
+        K14_1610_CAM_D1,
+        L19_1610_CAM_D0,
+        L18_1610_CAM_VS,
+        L15_1610_CAM_HS,
+        M19_1610_CAM_RSTZ,
+        Y15_1610_CAM_OUTCLK,
+
+        /* serial camera */
+        H19_1610_CAM_EXCLK,
+        Y12_1610_CCP_CLKP,
+        W13_1610_CCP_CLKM,
+        W14_1610_CCP_DATAP,
+        Y14_1610_CCP_DATAM,
+
+};
+
+enum omap24xx_index {
+        /* 24xx I2C */
+        M19_24XX_I2C1_SCL,
+        L15_24XX_I2C1_SDA,
+        J15_24XX_I2C2_SCL,
+        H19_24XX_I2C2_SDA,
+
+        /* 24xx Menelaus interrupt */
+        W19_24XX_SYS_NIRQ,
+
+        /* 24xx clock */
+        W14_24XX_SYS_CLKOUT,
+
+        /* 24xx GPMC chipselects, wait pin monitoring */
+        E2_GPMC_NCS2,
+        L2_GPMC_NCS7,
+        L3_GPMC_WAIT0,
+        N7_GPMC_WAIT1,
+        M1_GPMC_WAIT2,
+        P1_GPMC_WAIT3,
+
+        /* 242X McBSP */
+        Y15_24XX_MCBSP2_CLKX,
+        R14_24XX_MCBSP2_FSX,
+        W15_24XX_MCBSP2_DR,
+        V15_24XX_MCBSP2_DX,
+
+        /* 24xx GPIO */
+        M21_242X_GPIO11,
+        P21_242X_GPIO12,
+        AA10_242X_GPIO13,
+        AA6_242X_GPIO14,
+        AA4_242X_GPIO15,
+        Y11_242X_GPIO16,
+        AA12_242X_GPIO17,
+        AA8_242X_GPIO58,
+        Y20_24XX_GPIO60,
+        W4__24XX_GPIO74,
+        N15_24XX_GPIO85,
+        M15_24XX_GPIO92,
+        P20_24XX_GPIO93,
+        P18_24XX_GPIO95,
+        M18_24XX_GPIO96,
+        L14_24XX_GPIO97,
+        J15_24XX_GPIO99,
+        V14_24XX_GPIO117,
+        P14_24XX_GPIO125,
+
+        /* 242x DBG GPIO */
+        V4_242X_GPIO49,
+        W2_242X_GPIO50,
+        U4_242X_GPIO51,
+        V3_242X_GPIO52,
+        V2_242X_GPIO53,
+        V6_242X_GPIO53,
+        T4_242X_GPIO54,
+        Y4_242X_GPIO54,
+        T3_242X_GPIO55,
+        U2_242X_GPIO56,
+
+        /* 24xx external DMA requests */
+        AA10_242X_DMAREQ0,
+        AA6_242X_DMAREQ1,
+        E4_242X_DMAREQ2,
+        G4_242X_DMAREQ3,
+        D3_242X_DMAREQ4,
+        E3_242X_DMAREQ5,
+
+        /* UART3 */
+        K15_24XX_UART3_TX,
+        K14_24XX_UART3_RX,
+
+        /* MMC/SDIO */
+        G19_24XX_MMC_CLKO,
+        H18_24XX_MMC_CMD,
+        F20_24XX_MMC_DAT0,
+        H14_24XX_MMC_DAT1,
+        E19_24XX_MMC_DAT2,
+        D19_24XX_MMC_DAT3,
+        F19_24XX_MMC_DAT_DIR0,
+        E20_24XX_MMC_DAT_DIR1,
+        F18_24XX_MMC_DAT_DIR2,
+        E18_24XX_MMC_DAT_DIR3,
+        G18_24XX_MMC_CMD_DIR,
+        H15_24XX_MMC_CLKI,
+
+        /* Full speed USB */
+        J20_24XX_USB0_PUEN,
+        J19_24XX_USB0_VP,
+        K20_24XX_USB0_VM,
+        J18_24XX_USB0_RCV,
+        K19_24XX_USB0_TXEN,
+        J14_24XX_USB0_SE0,
+        K18_24XX_USB0_DAT,
+
+        N14_24XX_USB1_SE0,
+        W12_24XX_USB1_SE0,
+        P15_24XX_USB1_DAT,
+        R13_24XX_USB1_DAT,
+        W20_24XX_USB1_TXEN,
+        P13_24XX_USB1_TXEN,
+        V19_24XX_USB1_RCV,
+        V12_24XX_USB1_RCV,
+
+        AA10_24XX_USB2_SE0,
+        Y11_24XX_USB2_DAT,
+        AA12_24XX_USB2_TXEN,
+        AA6_24XX_USB2_RCV,
+        AA4_24XX_USB2_TLLSE0,
+
+        /* Keypad GPIO*/
+        T19_24XX_KBR0,
+        R19_24XX_KBR1,
+        V18_24XX_KBR2,
+        M21_24XX_KBR3,
+        E5__24XX_KBR4,
+        M18_24XX_KBR5,
+        R20_24XX_KBC0,
+        M14_24XX_KBC1,
+        H19_24XX_KBC2,
+        V17_24XX_KBC3,
+        P21_24XX_KBC4,
+        L14_24XX_KBC5,
+        N19_24XX_KBC6,
+
+        /* 24xx Menelaus Keypad GPIO */
+        B3__24XX_KBR5,
+        AA4_24XX_KBC2,
+        B13_24XX_KBC6,
+
+        /* 2430 USB */
+        AD9_2430_USB0_PUEN,
+        Y11_2430_USB0_VP,
+        AD7_2430_USB0_VM,
+        AE7_2430_USB0_RCV,
+        AD4_2430_USB0_TXEN,
+        AF9_2430_USB0_SE0,
+        AE6_2430_USB0_DAT,
+        AD24_2430_USB1_SE0,
+        AB24_2430_USB1_RCV,
+        Y25_2430_USB1_TXEN,
+        AA26_2430_USB1_DAT,
+
+        /* 2430 HS-USB */
+        AD9_2430_USB0HS_DATA3,
+        Y11_2430_USB0HS_DATA4,
+        AD7_2430_USB0HS_DATA5,
+        AE7_2430_USB0HS_DATA6,
+        AD4_2430_USB0HS_DATA2,
+        AF9_2430_USB0HS_DATA0,
+        AE6_2430_USB0HS_DATA1,
+        AE8_2430_USB0HS_CLK,
+        AD8_2430_USB0HS_DIR,
+        AE5_2430_USB0HS_STP,
+        AE9_2430_USB0HS_NXT,
+        AC7_2430_USB0HS_DATA7,
+
+        /* 2430 McBSP */
+        AC10_2430_MCBSP2_FSX,
+        AD16_2430_MCBSP2_CLX,
+        AE13_2430_MCBSP2_DX,
+        AD13_2430_MCBSP2_DR,
+        AC10_2430_MCBSP2_FSX_OFF,
+        AD16_2430_MCBSP2_CLX_OFF,
+        AE13_2430_MCBSP2_DX_OFF,
+        AD13_2430_MCBSP2_DR_OFF,
+
+};
+
+struct omap_mux_cfg {
+        struct pin_config       *pins;
+        unsigned long           size;
+        int                     (*cfg_reg)(const struct pin_config *cfg);
+};
+
+#ifdef  CONFIG_OMAP_MUX
+/* setup pin muxing in Linux */
+extern int omap1_mux_init(void);
+extern int omap2_mux_init(void);
+extern int omap_mux_register(struct omap_mux_cfg *);
+extern int omap_cfg_reg(unsigned long reg_cfg);
+#else
+/* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
+static inline int omap1_mux_init(void) { return 0; }
+static inline int omap2_mux_init(void) { return 0; }
+static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
+#endif
+
+#endif
diff --git a/arch/arm/plat-omap/include/mach/nand.h b/arch/arm/plat-omap/include/mach/nand.h
new file mode 100644
index 000000000000..631a7bed1eef
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/nand.h
@@ -0,0 +1,24 @@
+/*
+ * arch/arm/plat-omap/include/mach/nand.h
+ *
+ * Copyright (C) 2006 Micron Technology Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/mtd/partitions.h>
+
+struct omap_nand_platform_data {
+        unsigned int            options;
+        int                     cs;
+        int                     gpio_irq;
+        struct mtd_partition    *parts;
+        int                     nr_parts;
+        int                     (*nand_setup)(void __iomem *);
+        int                     (*dev_ready)(struct omap_nand_platform_data *);
+        int                     dma_channel;
+        void __iomem            *gpmc_cs_baseaddr;
+        void __iomem            *gpmc_baseaddr;
+};
diff --git a/arch/arm/plat-omap/include/mach/omap-alsa.h b/arch/arm/plat-omap/include/mach/omap-alsa.h
new file mode 100644
index 000000000000..bdf30a0f87f2
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/omap-alsa.h
@@ -0,0 +1,123 @@
+/*
+ * arch/arm/plat-omap/include/mach/omap-alsa.h
+ *
+ * Alsa Driver for AIC23 and TSC2101 codecs on OMAP platform boards.
+ *
+ * Copyright (C) 2006 Mika Laitio <lamikr@cc.jyu.fi>
+ *
+ * Copyright (C) 2005 Instituto Nokia de Tecnologia - INdT - Manaus Brazil
+ * Written by Daniel Petrini, David Cohen, Anderson Briglia
+ *            {daniel.petrini, david.cohen, anderson.briglia}@indt.org.br
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *  History
+ *  -------
+ *
+ *  2005/07/25 INdT-10LE Kernel Team -  Alsa driver for omap osk,
+ *                                      original version based in sa1100 driver
+ *                                      and omap oss driver.
+ */
+
+#ifndef __OMAP_ALSA_H
+#define __OMAP_ALSA_H
+
+#include <mach/dma.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <mach/mcbsp.h>
+#include <linux/platform_device.h>
+
+#define DMA_BUF_SIZE    (1024 * 8)
+
+/*
+ * Buffer management for alsa and dma
+ */
+struct audio_stream {
+        char *id;               /* identification string */
+        int stream_id;          /* numeric identification */
+        int dma_dev;            /* dma number of that device */
+        int *lch;               /* Chain of channels this stream is linked to */
+        char started;           /* to store if the chain was started or not */
+        int dma_q_head;         /* DMA Channel Q Head */
+        int dma_q_tail;         /* DMA Channel Q Tail */
+        char dma_q_count;       /* DMA Channel Q Count */
+        int active:1;           /* we are using this stream for transfer now */
+        int period;             /* current transfer period */
+        int periods;            /* current count of periods registerd in the DMA engine */
+        spinlock_t dma_lock;    /* for locking in DMA operations */
+        struct snd_pcm_substream *stream;       /* the pcm stream */
+        unsigned linked:1;      /* dma channels linked */
+        int offset;             /* store start position of the last period in the alsa buffer */
+        int (*hw_start)(void);  /* interface to start HW interface, e.g. McBSP */
+        int (*hw_stop)(void);   /* interface to stop HW interface, e.g. McBSP */
+};
+
+/*
+ * Alsa card structure for aic23
+ */
+struct snd_card_omap_codec {
+        struct snd_card *card;
+        struct snd_pcm *pcm;
+        long samplerate;
+        struct audio_stream s[2];       /* playback & capture */
+};
+
+/* Codec specific information and function pointers.
+ * Codec (omap-alsa-aic23.c and omap-alsa-tsc2101.c)
+ * are responsible for defining the function pointers.
+ */
+struct omap_alsa_codec_config {
+        char    *name;
+        struct  omap_mcbsp_reg_cfg *mcbsp_regs_alsa;
+        struct  snd_pcm_hw_constraint_list *hw_constraints_rates;
+        struct  snd_pcm_hardware *snd_omap_alsa_playback;
+        struct  snd_pcm_hardware *snd_omap_alsa_capture;
+        void    (*codec_configure_dev)(void);
+        void    (*codec_set_samplerate)(long);
+        void    (*codec_clock_setup)(void);
+        int     (*codec_clock_on)(void);
+        int     (*codec_clock_off)(void);
+        int     (*get_default_samplerate)(void);
+};
+
+/*********** Mixer function prototypes *************************/
+int snd_omap_mixer(struct snd_card_omap_codec *);
+void snd_omap_init_mixer(void);
+
+#ifdef CONFIG_PM
+void snd_omap_suspend_mixer(void);
+void snd_omap_resume_mixer(void);
+#endif
+
+int snd_omap_alsa_post_probe(struct platform_device *pdev, struct omap_alsa_codec_config *config);
+int snd_omap_alsa_remove(struct platform_device *pdev);
+#ifdef CONFIG_PM
+int snd_omap_alsa_suspend(struct platform_device *pdev, pm_message_t state);
+int snd_omap_alsa_resume(struct platform_device *pdev);
+#else
+#define snd_omap_alsa_suspend   NULL
+#define snd_omap_alsa_resume    NULL
+#endif
+
+void callback_omap_alsa_sound_dma(void *);
+
+#endif
diff --git a/arch/arm/plat-omap/include/mach/omap1510.h b/arch/arm/plat-omap/include/mach/omap1510.h
new file mode 100644
index 000000000000..505a38af8b22
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/omap1510.h
@@ -0,0 +1,48 @@
+/* arch/arm/plat-omap/include/mach/omap1510.h
+ *
+ * Hardware definitions for TI OMAP1510 processor.
+ *
+ * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_OMAP15XX_H
+#define __ASM_ARCH_OMAP15XX_H
+
+/*
+ * ----------------------------------------------------------------------------
+ * Base addresses
+ * ----------------------------------------------------------------------------
+ */
+
+/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
+
+#define OMAP1510_DSP_BASE       0xE0000000
+#define OMAP1510_DSP_SIZE       0x28000
+#define OMAP1510_DSP_START      0xE0000000
+
+#define OMAP1510_DSPREG_BASE    0xE1000000
+#define OMAP1510_DSPREG_SIZE    SZ_128K
+#define OMAP1510_DSPREG_START   0xE1000000
+
+#endif /*  __ASM_ARCH_OMAP15XX_H */
+
diff --git a/arch/arm/plat-omap/include/mach/omap16xx.h b/arch/arm/plat-omap/include/mach/omap16xx.h
new file mode 100644
index 000000000000..c6c93afb2788
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/omap16xx.h
@@ -0,0 +1,197 @@
+/* arch/arm/plat-omap/include/mach/omap16xx.h
+ *
+ * Hardware definitions for TI OMAP1610/5912/1710 processors.
+ *
+ * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_OMAP16XX_H
+#define __ASM_ARCH_OMAP16XX_H
+
+/*
+ * ----------------------------------------------------------------------------
+ * Base addresses
+ * ----------------------------------------------------------------------------
+ */
+
+/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
+
+#define OMAP16XX_DSP_BASE       0xE0000000
+#define OMAP16XX_DSP_SIZE       0x28000
+#define OMAP16XX_DSP_START      0xE0000000
+
+#define OMAP16XX_DSPREG_BASE    0xE1000000
+#define OMAP16XX_DSPREG_SIZE    SZ_128K
+#define OMAP16XX_DSPREG_START   0xE1000000
+
+/*
+ * ---------------------------------------------------------------------------
+ * Interrupts
+ * ---------------------------------------------------------------------------
+ */
+#define OMAP_IH2_0_BASE         (0xfffe0000)
+#define OMAP_IH2_1_BASE         (0xfffe0100)
+#define OMAP_IH2_2_BASE         (0xfffe0200)
+#define OMAP_IH2_3_BASE         (0xfffe0300)
+
+#define OMAP_IH2_0_ITR          (OMAP_IH2_0_BASE + 0x00)
+#define OMAP_IH2_0_MIR          (OMAP_IH2_0_BASE + 0x04)
+#define OMAP_IH2_0_SIR_IRQ      (OMAP_IH2_0_BASE + 0x10)
+#define OMAP_IH2_0_SIR_FIQ      (OMAP_IH2_0_BASE + 0x14)
+#define OMAP_IH2_0_CONTROL      (OMAP_IH2_0_BASE + 0x18)
+#define OMAP_IH2_0_ILR0         (OMAP_IH2_0_BASE + 0x1c)
+#define OMAP_IH2_0_ISR          (OMAP_IH2_0_BASE + 0x9c)
+
+#define OMAP_IH2_1_ITR          (OMAP_IH2_1_BASE + 0x00)
+#define OMAP_IH2_1_MIR          (OMAP_IH2_1_BASE + 0x04)
+#define OMAP_IH2_1_SIR_IRQ      (OMAP_IH2_1_BASE + 0x10)
+#define OMAP_IH2_1_SIR_FIQ      (OMAP_IH2_1_BASE + 0x14)
+#define OMAP_IH2_1_CONTROL      (OMAP_IH2_1_BASE + 0x18)
+#define OMAP_IH2_1_ILR1         (OMAP_IH2_1_BASE + 0x1c)
+#define OMAP_IH2_1_ISR          (OMAP_IH2_1_BASE + 0x9c)
+
+#define OMAP_IH2_2_ITR          (OMAP_IH2_2_BASE + 0x00)
+#define OMAP_IH2_2_MIR          (OMAP_IH2_2_BASE + 0x04)
+#define OMAP_IH2_2_SIR_IRQ      (OMAP_IH2_2_BASE + 0x10)
+#define OMAP_IH2_2_SIR_FIQ      (OMAP_IH2_2_BASE + 0x14)
+#define OMAP_IH2_2_CONTROL      (OMAP_IH2_2_BASE + 0x18)
+#define OMAP_IH2_2_ILR2         (OMAP_IH2_2_BASE + 0x1c)
+#define OMAP_IH2_2_ISR          (OMAP_IH2_2_BASE + 0x9c)
+
+#define OMAP_IH2_3_ITR          (OMAP_IH2_3_BASE + 0x00)
+#define OMAP_IH2_3_MIR          (OMAP_IH2_3_BASE + 0x04)
+#define OMAP_IH2_3_SIR_IRQ      (OMAP_IH2_3_BASE + 0x10)
+#define OMAP_IH2_3_SIR_FIQ      (OMAP_IH2_3_BASE + 0x14)
+#define OMAP_IH2_3_CONTROL      (OMAP_IH2_3_BASE + 0x18)
+#define OMAP_IH2_3_ILR3         (OMAP_IH2_3_BASE + 0x1c)
+#define OMAP_IH2_3_ISR          (OMAP_IH2_3_BASE + 0x9c)
+
+/*
+ * ----------------------------------------------------------------------------
+ * Clocks
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP16XX_ARM_IDLECT3    (CLKGEN_REG_BASE + 0x24)
+
+/*
+ * ----------------------------------------------------------------------------
+ * Pin configuration registers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP16XX_CONF_VOLTAGE_VDDSHV6   (1 << 8)
+#define OMAP16XX_CONF_VOLTAGE_VDDSHV7   (1 << 9)
+#define OMAP16XX_CONF_VOLTAGE_VDDSHV8   (1 << 10)
+#define OMAP16XX_CONF_VOLTAGE_VDDSHV9   (1 << 11)
+#define OMAP16XX_SUBLVDS_CONF_VALID     (1 << 13)
+
+/*
+ * ----------------------------------------------------------------------------
+ * System control registers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP1610_RESET_CONTROL  0xfffe1140
+
+/*
+ * ---------------------------------------------------------------------------
+ * TIPB bus interface
+ * ---------------------------------------------------------------------------
+ */
+#define TIPB_SWITCH_BASE                 (0xfffbc800)
+#define OMAP16XX_MMCSD2_SSW_MPU_CONF    (TIPB_SWITCH_BASE + 0x160)
+
+/* UART3 Registers Maping through MPU bus */
+#define UART3_RHR               (OMAP_UART3_BASE + 0)
+#define UART3_THR               (OMAP_UART3_BASE + 0)
+#define UART3_DLL               (OMAP_UART3_BASE + 0)
+#define UART3_IER               (OMAP_UART3_BASE + 4)
+#define UART3_DLH               (OMAP_UART3_BASE + 4)
+#define UART3_IIR               (OMAP_UART3_BASE + 8)
+#define UART3_FCR               (OMAP_UART3_BASE + 8)
+#define UART3_EFR               (OMAP_UART3_BASE + 8)
+#define UART3_LCR               (OMAP_UART3_BASE + 0x0C)
+#define UART3_MCR               (OMAP_UART3_BASE + 0x10)
+#define UART3_XON1_ADDR1        (OMAP_UART3_BASE + 0x10)
+#define UART3_XON2_ADDR2        (OMAP_UART3_BASE + 0x14)
+#define UART3_LSR               (OMAP_UART3_BASE + 0x14)
+#define UART3_TCR               (OMAP_UART3_BASE + 0x18)
+#define UART3_MSR               (OMAP_UART3_BASE + 0x18)
+#define UART3_XOFF1             (OMAP_UART3_BASE + 0x18)
+#define UART3_XOFF2             (OMAP_UART3_BASE + 0x1C)
+#define UART3_SPR               (OMAP_UART3_BASE + 0x1C)
+#define UART3_TLR               (OMAP_UART3_BASE + 0x1C)
+#define UART3_MDR1              (OMAP_UART3_BASE + 0x20)
+#define UART3_MDR2              (OMAP_UART3_BASE + 0x24)
+#define UART3_SFLSR             (OMAP_UART3_BASE + 0x28)
+#define UART3_TXFLL             (OMAP_UART3_BASE + 0x28)
+#define UART3_RESUME            (OMAP_UART3_BASE + 0x2C)
+#define UART3_TXFLH             (OMAP_UART3_BASE + 0x2C)
+#define UART3_SFREGL            (OMAP_UART3_BASE + 0x30)
+#define UART3_RXFLL             (OMAP_UART3_BASE + 0x30)
+#define UART3_SFREGH            (OMAP_UART3_BASE + 0x34)
+#define UART3_RXFLH             (OMAP_UART3_BASE + 0x34)
+#define UART3_BLR               (OMAP_UART3_BASE + 0x38)
+#define UART3_ACREG             (OMAP_UART3_BASE + 0x3C)
+#define UART3_DIV16             (OMAP_UART3_BASE + 0x3C)
+#define UART3_SCR               (OMAP_UART3_BASE + 0x40)
+#define UART3_SSR               (OMAP_UART3_BASE + 0x44)
+#define UART3_EBLR              (OMAP_UART3_BASE + 0x48)
+#define UART3_OSC_12M_SEL       (OMAP_UART3_BASE + 0x4C)
+#define UART3_MVR               (OMAP_UART3_BASE + 0x50)
+
+/*
+ * ---------------------------------------------------------------------------
+ * Watchdog timer
+ * ---------------------------------------------------------------------------
+ */
+
+/* 32-bit Watchdog timer in OMAP 16XX */
+#define OMAP_16XX_WATCHDOG_BASE        (0xfffeb000)
+#define OMAP_16XX_WIDR         (OMAP_16XX_WATCHDOG_BASE + 0x00)
+#define OMAP_16XX_WD_SYSCONFIG (OMAP_16XX_WATCHDOG_BASE + 0x10)
+#define OMAP_16XX_WD_SYSSTATUS (OMAP_16XX_WATCHDOG_BASE + 0x14)
+#define OMAP_16XX_WCLR         (OMAP_16XX_WATCHDOG_BASE + 0x24)
+#define OMAP_16XX_WCRR         (OMAP_16XX_WATCHDOG_BASE + 0x28)
+#define OMAP_16XX_WLDR         (OMAP_16XX_WATCHDOG_BASE + 0x2c)
+#define OMAP_16XX_WTGR         (OMAP_16XX_WATCHDOG_BASE + 0x30)
+#define OMAP_16XX_WWPS         (OMAP_16XX_WATCHDOG_BASE + 0x34)
+#define OMAP_16XX_WSPR         (OMAP_16XX_WATCHDOG_BASE + 0x48)
+
+#define WCLR_PRE_SHIFT         5
+#define WCLR_PTV_SHIFT         2
+
+#define WWPS_W_PEND_WSPR       (1 << 4)
+#define WWPS_W_PEND_WTGR       (1 << 3)
+#define WWPS_W_PEND_WLDR       (1 << 2)
+#define WWPS_W_PEND_WCRR       (1 << 1)
+#define WWPS_W_PEND_WCLR       (1 << 0)
+
+#define WSPR_ENABLE_0          (0x0000bbbb)
+#define WSPR_ENABLE_1          (0x00004444)
+#define WSPR_DISABLE_0         (0x0000aaaa)
+#define WSPR_DISABLE_1         (0x00005555)
+
+/* Mailbox */
+#define OMAP16XX_MAILBOX_BASE   (0xfffcf000)
+
+#endif /*  __ASM_ARCH_OMAP16XX_H */
+
diff --git a/arch/arm/plat-omap/include/mach/omap24xx.h b/arch/arm/plat-omap/include/mach/omap24xx.h
new file mode 100644
index 000000000000..bb8319d66e9f
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/omap24xx.h
@@ -0,0 +1,107 @@
+/*
+ * arch/arm/plat-omap/include/mach/omap24xx.h
+ *
+ * This file contains the processor specific definitions
+ * of the TI OMAP24XX.
+ *
+ * Copyright (C) 2007 Texas Instruments.
+ * Copyright (C) 2007 Nokia Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __ASM_ARCH_OMAP24XX_H
+#define __ASM_ARCH_OMAP24XX_H
+
+/*
+ * Please place only base defines here and put the rest in device
+ * specific headers. Note also that some of these defines are needed
+ * for omap1 to compile without adding ifdefs.
+ */
+
+#define L4_24XX_BASE            0x48000000
+#define L4_WK_243X_BASE         0x49000000
+#define L3_24XX_BASE            0x68000000
+
+/* interrupt controller */
+#define OMAP24XX_IC_BASE        (L4_24XX_BASE + 0xfe000)
+#define OMAP24XX_IVA_INTC_BASE  0x40000000
+#define IRQ_SIR_IRQ             0x0040
+
+#define OMAP2420_CTRL_BASE      L4_24XX_BASE
+#define OMAP2420_32KSYNCT_BASE  (L4_24XX_BASE + 0x4000)
+#define OMAP2420_PRCM_BASE      (L4_24XX_BASE + 0x8000)
+#define OMAP2420_CM_BASE        (L4_24XX_BASE + 0x8000)
+#define OMAP2420_PRM_BASE       OMAP2420_CM_BASE
+#define OMAP2420_SDRC_BASE      (L3_24XX_BASE + 0x9000)
+#define OMAP2420_SMS_BASE       0x68008000
+
+#define OMAP2430_32KSYNCT_BASE  (L4_WK_243X_BASE + 0x20000)
+#define OMAP2430_PRCM_BASE      (L4_WK_243X_BASE + 0x6000)
+#define OMAP2430_CM_BASE        (L4_WK_243X_BASE + 0x6000)
+#define OMAP2430_PRM_BASE       OMAP2430_CM_BASE
+
+#define OMAP243X_SMS_BASE       0x6C000000
+#define OMAP243X_SDRC_BASE      0x6D000000
+#define OMAP243X_GPMC_BASE      0x6E000000
+#define OMAP243X_SCM_BASE       (L4_WK_243X_BASE + 0x2000)
+#define OMAP243X_CTRL_BASE      OMAP243X_SCM_BASE
+#define OMAP243X_HS_BASE        (L4_24XX_BASE + 0x000ac000)
+
+/* DSP SS */
+#define OMAP2420_DSP_BASE       0x58000000
+#define OMAP2420_DSP_MEM_BASE   (OMAP2420_DSP_BASE + 0x0)
+#define OMAP2420_DSP_IPI_BASE   (OMAP2420_DSP_BASE + 0x1000000)
+#define OMAP2420_DSP_MMU_BASE   (OMAP2420_DSP_BASE + 0x2000000)
+
+#define OMAP243X_DSP_BASE       0x5C000000
+#define OMAP243X_DSP_MEM_BASE   (OMAP243X_DSP_BASE + 0x0)
+#define OMAP243X_DSP_MMU_BASE   (OMAP243X_DSP_BASE + 0x1000000)
+
+/* Mailbox */
+#define OMAP24XX_MAILBOX_BASE   (L4_24XX_BASE + 0x94000)
+
+/* Camera */
+#define OMAP24XX_CAMERA_BASE    (L4_24XX_BASE + 0x52000)
+
+/* Security */
+#define OMAP24XX_SEC_BASE       (L4_24XX_BASE + 0xA0000)
+#define OMAP24XX_SEC_RNG_BASE   (OMAP24XX_SEC_BASE + 0x0000)
+#define OMAP24XX_SEC_DES_BASE   (OMAP24XX_SEC_BASE + 0x2000)
+#define OMAP24XX_SEC_SHA1MD5_BASE (OMAP24XX_SEC_BASE + 0x4000)
+#define OMAP24XX_SEC_AES_BASE   (OMAP24XX_SEC_BASE + 0x6000)
+#define OMAP24XX_SEC_PKA_BASE   (OMAP24XX_SEC_BASE + 0x8000)
+
+#if defined(CONFIG_ARCH_OMAP2420)
+
+#define OMAP2_32KSYNCT_BASE     OMAP2420_32KSYNCT_BASE
+#define OMAP2_PRCM_BASE         OMAP2420_PRCM_BASE
+#define OMAP2_CM_BASE           OMAP2420_CM_BASE
+#define OMAP2_PRM_BASE          OMAP2420_PRM_BASE
+#define OMAP2_VA_IC_BASE        IO_ADDRESS(OMAP24XX_IC_BASE)
+
+#elif defined(CONFIG_ARCH_OMAP2430)
+
+#define OMAP2_32KSYNCT_BASE     OMAP2430_32KSYNCT_BASE
+#define OMAP2_PRCM_BASE         OMAP2430_PRCM_BASE
+#define OMAP2_CM_BASE           OMAP2430_CM_BASE
+#define OMAP2_PRM_BASE          OMAP2430_PRM_BASE
+#define OMAP2_VA_IC_BASE        IO_ADDRESS(OMAP24XX_IC_BASE)
+
+#endif
+
+#endif /* __ASM_ARCH_OMAP24XX_H */
+
diff --git a/arch/arm/plat-omap/include/mach/omap34xx.h b/arch/arm/plat-omap/include/mach/omap34xx.h
new file mode 100644
index 000000000000..8e0479fff05a
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/omap34xx.h
@@ -0,0 +1,72 @@
+/*
+ * arch/arm/plat-omap/include/mach/omap34xx.h
+ *
+ * This file contains the processor specific definitions of the TI OMAP34XX.
+ *
+ * Copyright (C) 2007 Texas Instruments.
+ * Copyright (C) 2007 Nokia Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_OMAP34XX_H
+#define __ASM_ARCH_OMAP34XX_H
+
+/*
+ * Please place only base defines here and put the rest in device
+ * specific headers.
+ */
+
+#define L4_34XX_BASE            0x48000000
+#define L4_WK_34XX_BASE         0x48300000
+#define L4_WK_OMAP_BASE         L4_WK_34XX_BASE
+#define L4_PER_34XX_BASE        0x49000000
+#define L4_PER_OMAP_BASE        L4_PER_34XX_BASE
+#define L4_EMU_34XX_BASE        0x54000000
+#define L4_EMU_BASE             L4_EMU_34XX_BASE
+#define L3_34XX_BASE            0x68000000
+#define L3_OMAP_BASE            L3_34XX_BASE
+
+#define OMAP3430_32KSYNCT_BASE  0x48320000
+#define OMAP3430_CM_BASE        0x48004800
+#define OMAP3430_PRM_BASE       0x48306800
+#define OMAP343X_SMS_BASE       0x6C000000
+#define OMAP343X_SDRC_BASE      0x6D000000
+#define OMAP34XX_GPMC_BASE      0x6E000000
+#define OMAP343X_SCM_BASE       0x48002000
+#define OMAP343X_CTRL_BASE      OMAP343X_SCM_BASE
+
+#define OMAP34XX_IC_BASE        0x48200000
+#define OMAP34XX_IVA_INTC_BASE  0x40000000
+#define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
+#define OMAP34XX_HSUSB_HOST_BASE        (L4_34XX_BASE + 0x64000)
+#define OMAP34XX_USBTLL_BASE    (L4_34XX_BASE + 0x62000)
+
+
+#if defined(CONFIG_ARCH_OMAP3430)
+
+#define OMAP2_32KSYNCT_BASE             OMAP3430_32KSYNCT_BASE
+#define OMAP2_CM_BASE                   OMAP3430_CM_BASE
+#define OMAP2_PRM_BASE                  OMAP3430_PRM_BASE
+#define OMAP2_VA_IC_BASE                IO_ADDRESS(OMAP34XX_IC_BASE)
+
+#endif
+
+#define OMAP34XX_DSP_BASE       0x58000000
+#define OMAP34XX_DSP_MEM_BASE   (OMAP34XX_DSP_BASE + 0x0)
+#define OMAP34XX_DSP_IPI_BASE   (OMAP34XX_DSP_BASE + 0x1000000)
+#define OMAP34XX_DSP_MMU_BASE   (OMAP34XX_DSP_BASE + 0x2000000)
+#endif /* __ASM_ARCH_OMAP34XX_H */
+
diff --git a/arch/arm/plat-omap/include/mach/omap730.h b/arch/arm/plat-omap/include/mach/omap730.h
new file mode 100644
index 000000000000..14272bc1a6fd
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/omap730.h
@@ -0,0 +1,102 @@
+/* arch/arm/plat-omap/include/mach/omap730.h
+ *
+ * Hardware definitions for TI OMAP730 processor.
+ *
+ * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_OMAP730_H
+#define __ASM_ARCH_OMAP730_H
+
+/*
+ * ----------------------------------------------------------------------------
+ * Base addresses
+ * ----------------------------------------------------------------------------
+ */
+
+/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
+
+#define OMAP730_DSP_BASE        0xE0000000
+#define OMAP730_DSP_SIZE        0x50000
+#define OMAP730_DSP_START       0xE0000000
+
+#define OMAP730_DSPREG_BASE     0xE1000000
+#define OMAP730_DSPREG_SIZE     SZ_128K
+#define OMAP730_DSPREG_START    0xE1000000
+
+/*
+ * ----------------------------------------------------------------------------
+ * OMAP730 specific configuration registers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP730_CONFIG_BASE     0xfffe1000
+#define OMAP730_IO_CONF_0       0xfffe1070
+#define OMAP730_IO_CONF_1       0xfffe1074
+#define OMAP730_IO_CONF_2       0xfffe1078
+#define OMAP730_IO_CONF_3       0xfffe107c
+#define OMAP730_IO_CONF_4       0xfffe1080
+#define OMAP730_IO_CONF_5       0xfffe1084
+#define OMAP730_IO_CONF_6       0xfffe1088
+#define OMAP730_IO_CONF_7       0xfffe108c
+#define OMAP730_IO_CONF_8       0xfffe1090
+#define OMAP730_IO_CONF_9       0xfffe1094
+#define OMAP730_IO_CONF_10      0xfffe1098
+#define OMAP730_IO_CONF_11      0xfffe109c
+#define OMAP730_IO_CONF_12      0xfffe10a0
+#define OMAP730_IO_CONF_13      0xfffe10a4
+
+#define OMAP730_MODE_1          0xfffe1010
+#define OMAP730_MODE_2          0xfffe1014
+
+/* CSMI specials: in terms of base + offset */
+#define OMAP730_MODE2_OFFSET    0x14
+
+/*
+ * ----------------------------------------------------------------------------
+ * OMAP730 traffic controller configuration registers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP730_FLASH_CFG_0     0xfffecc10
+#define OMAP730_FLASH_ACFG_0    0xfffecc50
+#define OMAP730_FLASH_CFG_1     0xfffecc14
+#define OMAP730_FLASH_ACFG_1    0xfffecc54
+
+/*
+ * ----------------------------------------------------------------------------
+ * OMAP730 DSP control registers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP730_ICR_BASE        0xfffbb800
+#define OMAP730_DSP_M_CTL       0xfffbb804
+#define OMAP730_DSP_MMU_BASE    0xfffed200
+
+/*
+ * ----------------------------------------------------------------------------
+ * OMAP730 PCC_UPLD configuration registers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP730_PCC_UPLD_CTRL_BASE      (0xfffe0900)
+#define OMAP730_PCC_UPLD_CTRL           (OMAP730_PCC_UPLD_CTRL_BASE + 0x00)
+
+#endif /*  __ASM_ARCH_OMAP730_H */
+
diff --git a/arch/arm/plat-omap/include/mach/omapfb.h b/arch/arm/plat-omap/include/mach/omapfb.h
new file mode 100644
index 000000000000..cae037d13079
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/omapfb.h
@@ -0,0 +1,395 @@
+/*
+ * File: arch/arm/plat-omap/include/mach/omapfb.h
+ *
+ * Framebuffer driver for TI OMAP boards
+ *
+ * Copyright (C) 2004 Nokia Corporation
+ * Author: Imre Deak <imre.deak@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+
+#ifndef __OMAPFB_H
+#define __OMAPFB_H
+
+#include <asm/ioctl.h>
+#include <asm/types.h>
+
+/* IOCTL commands. */
+
+#define OMAP_IOW(num, dtype)    _IOW('O', num, dtype)
+#define OMAP_IOR(num, dtype)    _IOR('O', num, dtype)
+#define OMAP_IOWR(num, dtype)   _IOWR('O', num, dtype)
+#define OMAP_IO(num)            _IO('O', num)
+
+#define OMAPFB_MIRROR           OMAP_IOW(31, int)
+#define OMAPFB_SYNC_GFX         OMAP_IO(37)
+#define OMAPFB_VSYNC            OMAP_IO(38)
+#define OMAPFB_SET_UPDATE_MODE  OMAP_IOW(40, int)
+#define OMAPFB_GET_CAPS         OMAP_IOR(42, struct omapfb_caps)
+#define OMAPFB_GET_UPDATE_MODE  OMAP_IOW(43, int)
+#define OMAPFB_LCD_TEST         OMAP_IOW(45, int)
+#define OMAPFB_CTRL_TEST        OMAP_IOW(46, int)
+#define OMAPFB_UPDATE_WINDOW_OLD OMAP_IOW(47, struct omapfb_update_window_old)
+#define OMAPFB_SET_COLOR_KEY    OMAP_IOW(50, struct omapfb_color_key)
+#define OMAPFB_GET_COLOR_KEY    OMAP_IOW(51, struct omapfb_color_key)
+#define OMAPFB_SETUP_PLANE      OMAP_IOW(52, struct omapfb_plane_info)
+#define OMAPFB_QUERY_PLANE      OMAP_IOW(53, struct omapfb_plane_info)
+#define OMAPFB_UPDATE_WINDOW    OMAP_IOW(54, struct omapfb_update_window)
+#define OMAPFB_SETUP_MEM        OMAP_IOW(55, struct omapfb_mem_info)
+#define OMAPFB_QUERY_MEM        OMAP_IOW(56, struct omapfb_mem_info)
+
+#define OMAPFB_CAPS_GENERIC_MASK        0x00000fff
+#define OMAPFB_CAPS_LCDC_MASK           0x00fff000
+#define OMAPFB_CAPS_PANEL_MASK          0xff000000
+
+#define OMAPFB_CAPS_MANUAL_UPDATE       0x00001000
+#define OMAPFB_CAPS_TEARSYNC            0x00002000
+#define OMAPFB_CAPS_PLANE_RELOCATE_MEM  0x00004000
+#define OMAPFB_CAPS_PLANE_SCALE         0x00008000
+#define OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE 0x00010000
+#define OMAPFB_CAPS_WINDOW_SCALE        0x00020000
+#define OMAPFB_CAPS_WINDOW_OVERLAY      0x00040000
+#define OMAPFB_CAPS_SET_BACKLIGHT       0x01000000
+
+/* Values from DSP must map to lower 16-bits */
+#define OMAPFB_FORMAT_MASK              0x00ff
+#define OMAPFB_FORMAT_FLAG_DOUBLE       0x0100
+#define OMAPFB_FORMAT_FLAG_TEARSYNC     0x0200
+#define OMAPFB_FORMAT_FLAG_FORCE_VSYNC  0x0400
+#define OMAPFB_FORMAT_FLAG_ENABLE_OVERLAY       0x0800
+#define OMAPFB_FORMAT_FLAG_DISABLE_OVERLAY      0x1000
+
+#define OMAPFB_EVENT_READY      1
+#define OMAPFB_EVENT_DISABLED   2
+
+#define OMAPFB_MEMTYPE_SDRAM            0
+#define OMAPFB_MEMTYPE_SRAM             1
+#define OMAPFB_MEMTYPE_MAX              1
+
+enum omapfb_color_format {
+        OMAPFB_COLOR_RGB565 = 0,
+        OMAPFB_COLOR_YUV422,
+        OMAPFB_COLOR_YUV420,
+        OMAPFB_COLOR_CLUT_8BPP,
+        OMAPFB_COLOR_CLUT_4BPP,
+        OMAPFB_COLOR_CLUT_2BPP,
+        OMAPFB_COLOR_CLUT_1BPP,
+        OMAPFB_COLOR_RGB444,
+        OMAPFB_COLOR_YUY422,
+};
+
+struct omapfb_update_window {
+        __u32 x, y;
+        __u32 width, height;
+        __u32 format;
+        __u32 out_x, out_y;
+        __u32 out_width, out_height;
+        __u32 reserved[8];
+};
+
+struct omapfb_update_window_old {
+        __u32 x, y;
+        __u32 width, height;
+        __u32 format;
+};
+
+enum omapfb_plane {
+        OMAPFB_PLANE_GFX = 0,
+        OMAPFB_PLANE_VID1,
+        OMAPFB_PLANE_VID2,
+};
+
+enum omapfb_channel_out {
+        OMAPFB_CHANNEL_OUT_LCD = 0,
+        OMAPFB_CHANNEL_OUT_DIGIT,
+};
+
+struct omapfb_plane_info {
+        __u32 pos_x;
+        __u32 pos_y;
+        __u8  enabled;
+        __u8  channel_out;
+        __u8  mirror;
+        __u8  reserved1;
+        __u32 out_width;
+        __u32 out_height;
+        __u32 reserved2[12];
+};
+
+struct omapfb_mem_info {
+        __u32 size;
+        __u8  type;
+        __u8  reserved[3];
+};
+
+struct omapfb_caps {
+        __u32 ctrl;
+        __u32 plane_color;
+        __u32 wnd_color;
+};
+
+enum omapfb_color_key_type {
+        OMAPFB_COLOR_KEY_DISABLED = 0,
+        OMAPFB_COLOR_KEY_GFX_DST,
+        OMAPFB_COLOR_KEY_VID_SRC,
+};
+
+struct omapfb_color_key {
+        __u8  channel_out;
+        __u32 background;
+        __u32 trans_key;
+        __u8  key_type;
+};
+
+enum omapfb_update_mode {
+        OMAPFB_UPDATE_DISABLED = 0,
+        OMAPFB_AUTO_UPDATE,
+        OMAPFB_MANUAL_UPDATE
+};
+
+#ifdef __KERNEL__
+
+#include <linux/completion.h>
+#include <linux/interrupt.h>
+#include <linux/fb.h>
+#include <linux/mutex.h>
+
+#include <mach/board.h>
+
+#define OMAP_LCDC_INV_VSYNC             0x0001
+#define OMAP_LCDC_INV_HSYNC             0x0002
+#define OMAP_LCDC_INV_PIX_CLOCK         0x0004
+#define OMAP_LCDC_INV_OUTPUT_EN         0x0008
+#define OMAP_LCDC_HSVS_RISING_EDGE      0x0010
+#define OMAP_LCDC_HSVS_OPPOSITE         0x0020
+
+#define OMAP_LCDC_SIGNAL_MASK           0x003f
+
+#define OMAP_LCDC_PANEL_TFT             0x0100
+
+#define OMAPFB_PLANE_XRES_MIN           8
+#define OMAPFB_PLANE_YRES_MIN           8
+
+#ifdef CONFIG_ARCH_OMAP1
+#define OMAPFB_PLANE_NUM                1
+#else
+#define OMAPFB_PLANE_NUM                3
+#endif
+
+struct omapfb_device;
+
+struct lcd_panel {
+        const char      *name;
+        int             config;         /* TFT/STN, signal inversion */
+        int             bpp;            /* Pixel format in fb mem */
+        int             data_lines;     /* Lines on LCD HW interface */
+
+        int             x_res, y_res;
+        int             pixel_clock;    /* In kHz */
+        int             hsw;            /* Horizontal synchronization
+                                           pulse width */
+        int             hfp;            /* Horizontal front porch */
+        int             hbp;            /* Horizontal back porch */
+        int             vsw;            /* Vertical synchronization
+                                           pulse width */
+        int             vfp;            /* Vertical front porch */
+        int             vbp;            /* Vertical back porch */
+        int             acb;            /* ac-bias pin frequency */
+        int             pcd;            /* pixel clock divider.
+                                           Obsolete use pixel_clock instead */
+
+        int             (*init)         (struct lcd_panel *panel,
+                                         struct omapfb_device *fbdev);
+        void            (*cleanup)      (struct lcd_panel *panel);
+        int             (*enable)       (struct lcd_panel *panel);
+        void            (*disable)      (struct lcd_panel *panel);
+        unsigned long   (*get_caps)     (struct lcd_panel *panel);
+        int             (*set_bklight_level)(struct lcd_panel *panel,
+                                             unsigned int level);
+        unsigned int    (*get_bklight_level)(struct lcd_panel *panel);
+        unsigned int    (*get_bklight_max)  (struct lcd_panel *panel);
+        int             (*run_test)     (struct lcd_panel *panel, int test_num);
+};
+
+struct extif_timings {
+        int cs_on_time;
+        int cs_off_time;
+        int we_on_time;
+        int we_off_time;
+        int re_on_time;
+        int re_off_time;
+        int we_cycle_time;
+        int re_cycle_time;
+        int cs_pulse_width;
+        int access_time;
+
+        int clk_div;
+
+        u32 tim[5];             /* set by extif->convert_timings */
+
+        int converted;
+};
+
+struct lcd_ctrl_extif {
+        int  (*init)            (struct omapfb_device *fbdev);
+        void (*cleanup)         (void);
+        void (*get_clk_info)    (u32 *clk_period, u32 *max_clk_div);
+        unsigned long (*get_max_tx_rate)(void);
+        int  (*convert_timings) (struct extif_timings *timings);
+        void (*set_timings)     (const struct extif_timings *timings);
+        void (*set_bits_per_cycle)(int bpc);
+        void (*write_command)   (const void *buf, unsigned int len);
+        void (*read_data)       (void *buf, unsigned int len);
+        void (*write_data)      (const void *buf, unsigned int len);
+        void (*transfer_area)   (int width, int height,
+                                 void (callback)(void * data), void *data);
+        int  (*setup_tearsync)  (unsigned pin_cnt,
+                                 unsigned hs_pulse_time, unsigned vs_pulse_time,
+                                 int hs_pol_inv, int vs_pol_inv, int div);
+        int  (*enable_tearsync) (int enable, unsigned line);
+
+        unsigned long           max_transmit_size;
+};
+
+struct omapfb_notifier_block {
+        struct notifier_block   nb;
+        void                    *data;
+        int                     plane_idx;
+};
+
+typedef int (*omapfb_notifier_callback_t)(struct notifier_block *,
+                                          unsigned long event,
+                                          void *fbi);
+
+struct omapfb_mem_region {
+        dma_addr_t      paddr;
+        void            *vaddr;
+        unsigned long   size;
+        u8              type;           /* OMAPFB_PLANE_MEM_* */
+        unsigned        alloc:1;        /* allocated by the driver */
+        unsigned        map:1;          /* kernel mapped by the driver */
+};
+
+struct omapfb_mem_desc {
+        int                             region_cnt;
+        struct omapfb_mem_region        region[OMAPFB_PLANE_NUM];
+};
+
+struct lcd_ctrl {
+        const char      *name;
+        void            *data;
+
+        int             (*init)           (struct omapfb_device *fbdev,
+                                           int ext_mode,
+                                           struct omapfb_mem_desc *req_md);
+        void            (*cleanup)        (void);
+        void            (*bind_client)    (struct omapfb_notifier_block *nb);
+        void            (*get_caps)       (int plane, struct omapfb_caps *caps);
+        int             (*set_update_mode)(enum omapfb_update_mode mode);
+        enum omapfb_update_mode (*get_update_mode)(void);
+        int             (*setup_plane)    (int plane, int channel_out,
+                                           unsigned long offset,
+                                           int screen_width,
+                                           int pos_x, int pos_y, int width,
+                                           int height, int color_mode);
+        int             (*setup_mem)      (int plane, size_t size,
+                                           int mem_type, unsigned long *paddr);
+        int             (*mmap)           (struct fb_info *info,
+                                           struct vm_area_struct *vma);
+        int             (*set_scale)      (int plane,
+                                           int orig_width, int orig_height,
+                                           int out_width, int out_height);
+        int             (*enable_plane)   (int plane, int enable);
+        int             (*update_window)  (struct fb_info *fbi,
+                                           struct omapfb_update_window *win,
+                                           void (*callback)(void *),
+                                           void *callback_data);
+        void            (*sync)           (void);
+        void            (*suspend)        (void);
+        void            (*resume)         (void);
+        int             (*run_test)       (int test_num);
+        int             (*setcolreg)      (u_int regno, u16 red, u16 green,
+                                           u16 blue, u16 transp,
+                                           int update_hw_mem);
+        int             (*set_color_key)  (struct omapfb_color_key *ck);
+        int             (*get_color_key)  (struct omapfb_color_key *ck);
+};
+
+enum omapfb_state {
+        OMAPFB_DISABLED = 0,
+        OMAPFB_SUSPENDED= 99,
+        OMAPFB_ACTIVE   = 100
+};
+
+struct omapfb_plane_struct {
+        int                             idx;
+        struct omapfb_plane_info        info;
+        enum omapfb_color_format        color_mode;
+        struct omapfb_device            *fbdev;
+};
+
+struct omapfb_device {
+        int                     state;
+        int                     ext_lcdc;               /* Using external
+                                                           LCD controller */
+        struct mutex            rqueue_mutex;
+
+        int                     palette_size;
+        u32                     pseudo_palette[17];
+
+        struct lcd_panel        *panel;                 /* LCD panel */
+        struct lcd_ctrl         *ctrl;                  /* LCD controller */
+        struct lcd_ctrl         *int_ctrl;              /* internal LCD ctrl */
+        struct lcd_ctrl_extif   *ext_if;                /* LCD ctrl external
+                                                           interface */
+        struct device           *dev;
+        struct fb_var_screeninfo        new_var;        /* for mode changes */
+
+        struct omapfb_mem_desc          mem_desc;
+        struct fb_info                  *fb_info[OMAPFB_PLANE_NUM];
+};
+
+struct omapfb_platform_data {
+        struct omap_lcd_config          lcd;
+        struct omapfb_mem_desc          mem_desc;
+        void                            *ctrl_platform_data;
+};
+
+#ifdef CONFIG_ARCH_OMAP1
+extern struct lcd_ctrl omap1_lcd_ctrl;
+#else
+extern struct lcd_ctrl omap2_disp_ctrl;
+#endif
+
+extern void omapfb_register_panel(struct lcd_panel *panel);
+extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval);
+extern void omapfb_notify_clients(struct omapfb_device *fbdev,
+                                  unsigned long event);
+extern int  omapfb_register_client(struct omapfb_notifier_block *nb,
+                                   omapfb_notifier_callback_t callback,
+                                   void *callback_data);
+extern int  omapfb_unregister_client(struct omapfb_notifier_block *nb);
+extern int  omapfb_update_window_async(struct fb_info *fbi,
+                                       struct omapfb_update_window *win,
+                                       void (*callback)(void *),
+                                       void *callback_data);
+
+/* in arch/arm/plat-omap/fb.c */
+extern void omapfb_set_ctrl_platform_data(void *pdata);
+
+#endif /* __KERNEL__ */
+
+#endif /* __OMAPFB_H */
diff --git a/arch/arm/plat-omap/include/mach/onenand.h b/arch/arm/plat-omap/include/mach/onenand.h
new file mode 100644
index 000000000000..d57f20226b28
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/onenand.h
@@ -0,0 +1,21 @@
+/*
+ * arch/arm/plat-omap/include/mach/onenand.h
+ *
+ * Copyright (C) 2006 Nokia Corporation
+ * Author: Juha Yrjola
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/mtd/partitions.h>
+
+struct omap_onenand_platform_data {
+        int                     cs;
+        int                     gpio_irq;
+        struct mtd_partition    *parts;
+        int                     nr_parts;
+        int                     (*onenand_setup)(void __iomem *);
+        int                     dma_channel;
+};
diff --git a/arch/arm/plat-omap/include/mach/param.h b/arch/arm/plat-omap/include/mach/param.h
new file mode 100644
index 000000000000..1eb4dc326979
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/param.h
@@ -0,0 +1,8 @@
+/*
+ *  arch/arm/plat-omap/include/mach/param.h
+ *
+ */
+
+#ifdef CONFIG_OMAP_32K_TIMER_HZ
+#define HZ      CONFIG_OMAP_32K_TIMER_HZ
+#endif
diff --git a/arch/arm/plat-omap/include/mach/pm.h b/arch/arm/plat-omap/include/mach/pm.h
new file mode 100644
index 000000000000..bfa09325a5ff
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/pm.h
@@ -0,0 +1,356 @@
+/*
+ * arch/arm/plat-omap/include/mach/pm.h
+ *
+ * Header file for OMAP Power Management Routines
+ *
+ * Author: MontaVista Software, Inc.
+ *         support@mvista.com
+ *
+ * Copyright 2002 MontaVista Software Inc.
+ *
+ * Cleanup 2004 for Linux 2.6 by Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_OMAP_PM_H
+#define __ASM_ARCH_OMAP_PM_H
+
+/*
+ * ----------------------------------------------------------------------------
+ * Register and offset definitions to be used in PM assembler code
+ * ----------------------------------------------------------------------------
+ */
+#define CLKGEN_REG_ASM_BASE             io_p2v(0xfffece00)
+#define ARM_IDLECT1_ASM_OFFSET          0x04
+#define ARM_IDLECT2_ASM_OFFSET          0x08
+
+#define TCMIF_ASM_BASE                  io_p2v(0xfffecc00)
+#define EMIFS_CONFIG_ASM_OFFSET         0x0c
+#define EMIFF_SDRAM_CONFIG_ASM_OFFSET   0x20
+
+/*
+ * ----------------------------------------------------------------------------
+ * Power management bitmasks
+ * ----------------------------------------------------------------------------
+ */
+#define IDLE_WAIT_CYCLES                0x00000fff
+#define PERIPHERAL_ENABLE               0x2
+
+#define SELF_REFRESH_MODE               0x0c000001
+#define IDLE_EMIFS_REQUEST              0xc
+#define MODEM_32K_EN                    0x1
+#define PER_EN                          0x1
+
+#define CPU_SUSPEND_SIZE                200
+#define ULPD_LOW_PWR_EN                 0x0001
+#define ULPD_DEEP_SLEEP_TRANSITION_EN   0x0010
+#define ULPD_SETUP_ANALOG_CELL_3_VAL    0
+#define ULPD_POWER_CTRL_REG_VAL         0x0219
+
+#define DSP_IDLE_DELAY                  10
+#define DSP_IDLE                        0x0040
+#define DSP_RST                         0x0004
+#define DSP_ENABLE                      0x0002
+#define SUFFICIENT_DSP_RESET_TIME       1000
+#define DEFAULT_MPUI_CONFIG             0x05cf
+#define ENABLE_XORCLK                   0x2
+#define DSP_CLOCK_ENABLE                0x2000
+#define DSP_IDLE_MODE                   0x2
+#define TC_IDLE_REQUEST                 (0x0000000c)
+
+#define IRQ_LEVEL2                      (1<<0)
+#define IRQ_KEYBOARD                    (1<<1)
+#define IRQ_UART2                       (1<<15)
+
+#define PDE_BIT                         0x08
+#define PWD_EN_BIT                      0x04
+#define EN_PERCK_BIT                    0x04
+
+#define OMAP1510_DEEP_SLEEP_REQUEST     0x0ec7
+#define OMAP1510_BIG_SLEEP_REQUEST      0x0cc5
+#define OMAP1510_IDLE_LOOP_REQUEST      0x0c00
+#define OMAP1510_IDLE_CLOCK_DOMAINS     0x2
+
+/* Both big sleep and deep sleep use same values. Difference is in ULPD. */
+#define OMAP1610_IDLECT1_SLEEP_VAL      0x13c7
+#define OMAP1610_IDLECT2_SLEEP_VAL      0x09c7
+#define OMAP1610_IDLECT3_VAL            0x3f
+#define OMAP1610_IDLECT3_SLEEP_ORMASK   0x2c
+#define OMAP1610_IDLECT3                0xfffece24
+#define OMAP1610_IDLE_LOOP_REQUEST      0x0400
+
+#define OMAP730_IDLECT1_SLEEP_VAL       0x16c7
+#define OMAP730_IDLECT2_SLEEP_VAL       0x09c7
+#define OMAP730_IDLECT3_VAL             0x3f
+#define OMAP730_IDLECT3         0xfffece24
+#define OMAP730_IDLE_LOOP_REQUEST       0x0C00
+
+#if     !defined(CONFIG_ARCH_OMAP730) && \
+        !defined(CONFIG_ARCH_OMAP15XX) && \
+        !defined(CONFIG_ARCH_OMAP16XX) && \
+        !defined(CONFIG_ARCH_OMAP24XX)
+#error "Power management for this processor not implemented yet"
+#endif
+
+#ifndef __ASSEMBLER__
+
+#include <linux/clk.h>
+
+extern void prevent_idle_sleep(void);
+extern void allow_idle_sleep(void);
+
+/**
+ * clk_deny_idle - Prevents the clock from being idled during MPU idle
+ * @clk: clock signal handle
+ */
+void clk_deny_idle(struct clk *clk);
+
+/**
+ * clk_allow_idle - Counters previous clk_deny_idle
+ * @clk: clock signal handle
+ */
+void clk_deny_idle(struct clk *clk);
+
+extern void omap_pm_idle(void);
+extern void omap_pm_suspend(void);
+extern void omap730_cpu_suspend(unsigned short, unsigned short);
+extern void omap1510_cpu_suspend(unsigned short, unsigned short);
+extern void omap1610_cpu_suspend(unsigned short, unsigned short);
+extern void omap24xx_cpu_suspend(u32 dll_ctrl, u32 cpu_revision);
+extern void omap730_idle_loop_suspend(void);
+extern void omap1510_idle_loop_suspend(void);
+extern void omap1610_idle_loop_suspend(void);
+extern void omap24xx_idle_loop_suspend(void);
+
+extern unsigned int omap730_cpu_suspend_sz;
+extern unsigned int omap1510_cpu_suspend_sz;
+extern unsigned int omap1610_cpu_suspend_sz;
+extern unsigned int omap24xx_cpu_suspend_sz;
+extern unsigned int omap730_idle_loop_suspend_sz;
+extern unsigned int omap1510_idle_loop_suspend_sz;
+extern unsigned int omap1610_idle_loop_suspend_sz;
+extern unsigned int omap24xx_idle_loop_suspend_sz;
+
+#ifdef CONFIG_OMAP_SERIAL_WAKE
+extern void omap_serial_wake_trigger(int enable);
+#else
+#define omap_serial_wakeup_init()       {}
+#define omap_serial_wake_trigger(x)     {}
+#endif  /* CONFIG_OMAP_SERIAL_WAKE */
+
+#define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = omap_readl(x)
+#define ARM_RESTORE(x) omap_writel((arm_sleep_save[ARM_SLEEP_SAVE_##x]), (x))
+#define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x]
+
+#define DSP_SAVE(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x] = __raw_readw(x)
+#define DSP_RESTORE(x) __raw_writew((dsp_sleep_save[DSP_SLEEP_SAVE_##x]), (x))
+#define DSP_SHOW(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x]
+
+#define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = omap_readw(x)
+#define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x))
+#define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
+
+#define MPUI730_SAVE(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x] = omap_readl(x)
+#define MPUI730_RESTORE(x) omap_writel((mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]), (x))
+#define MPUI730_SHOW(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]
+
+#define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x)
+#define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x))
+#define MPUI1510_SHOW(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]
+
+#define MPUI1610_SAVE(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] = omap_readl(x)
+#define MPUI1610_RESTORE(x) omap_writel((mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]), (x))
+#define MPUI1610_SHOW(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]
+
+#define OMAP24XX_SAVE(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x] = x
+#define OMAP24XX_RESTORE(x) x = omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x]
+#define OMAP24XX_SHOW(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x]
+
+/*
+ * List of global OMAP registers to preserve.
+ * More ones like CP and general purpose register values are preserved
+ * with the stack pointer in sleep.S.
+ */
+
+enum arm_save_state {
+        ARM_SLEEP_SAVE_START = 0,
+        /*
+         * MPU control registers 32 bits
+         */
+        ARM_SLEEP_SAVE_ARM_CKCTL,
+        ARM_SLEEP_SAVE_ARM_IDLECT1,
+        ARM_SLEEP_SAVE_ARM_IDLECT2,
+        ARM_SLEEP_SAVE_ARM_IDLECT3,
+        ARM_SLEEP_SAVE_ARM_EWUPCT,
+        ARM_SLEEP_SAVE_ARM_RSTCT1,
+        ARM_SLEEP_SAVE_ARM_RSTCT2,
+        ARM_SLEEP_SAVE_ARM_SYSST,
+        ARM_SLEEP_SAVE_SIZE
+};
+
+enum dsp_save_state {
+        DSP_SLEEP_SAVE_START = 0,
+        /*
+         * DSP registers 16 bits
+         */
+        DSP_SLEEP_SAVE_DSP_IDLECT2,
+        DSP_SLEEP_SAVE_SIZE
+};
+
+enum ulpd_save_state {
+        ULPD_SLEEP_SAVE_START = 0,
+        /*
+         * ULPD registers 16 bits
+         */
+        ULPD_SLEEP_SAVE_ULPD_IT_STATUS,
+        ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL,
+        ULPD_SLEEP_SAVE_ULPD_SOFT_REQ,
+        ULPD_SLEEP_SAVE_ULPD_STATUS_REQ,
+        ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL,
+        ULPD_SLEEP_SAVE_ULPD_POWER_CTRL,
+        ULPD_SLEEP_SAVE_SIZE
+};
+
+enum mpui1510_save_state {
+        MPUI1510_SLEEP_SAVE_START = 0,
+        /*
+         * MPUI registers 32 bits
+         */
+        MPUI1510_SLEEP_SAVE_MPUI_CTRL,
+        MPUI1510_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
+        MPUI1510_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
+        MPUI1510_SLEEP_SAVE_MPUI_DSP_STATUS,
+        MPUI1510_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
+        MPUI1510_SLEEP_SAVE_EMIFS_CONFIG,
+        MPUI1510_SLEEP_SAVE_OMAP_IH1_MIR,
+        MPUI1510_SLEEP_SAVE_OMAP_IH2_MIR,
+#if defined(CONFIG_ARCH_OMAP15XX)
+        MPUI1510_SLEEP_SAVE_SIZE
+#else
+        MPUI1510_SLEEP_SAVE_SIZE = 0
+#endif
+};
+
+enum mpui730_save_state {
+        MPUI730_SLEEP_SAVE_START = 0,
+        /*
+         * MPUI registers 32 bits
+         */
+        MPUI730_SLEEP_SAVE_MPUI_CTRL,
+        MPUI730_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
+        MPUI730_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
+        MPUI730_SLEEP_SAVE_MPUI_DSP_STATUS,
+        MPUI730_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
+        MPUI730_SLEEP_SAVE_EMIFS_CONFIG,
+        MPUI730_SLEEP_SAVE_OMAP_IH1_MIR,
+        MPUI730_SLEEP_SAVE_OMAP_IH2_0_MIR,
+        MPUI730_SLEEP_SAVE_OMAP_IH2_1_MIR,
+#if defined(CONFIG_ARCH_OMAP730)
+        MPUI730_SLEEP_SAVE_SIZE
+#else
+        MPUI730_SLEEP_SAVE_SIZE = 0
+#endif
+};
+
+enum mpui1610_save_state {
+        MPUI1610_SLEEP_SAVE_START = 0,
+        /*
+         * MPUI registers 32 bits
+         */
+        MPUI1610_SLEEP_SAVE_MPUI_CTRL,
+        MPUI1610_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
+        MPUI1610_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
+        MPUI1610_SLEEP_SAVE_MPUI_DSP_STATUS,
+        MPUI1610_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
+        MPUI1610_SLEEP_SAVE_EMIFS_CONFIG,
+        MPUI1610_SLEEP_SAVE_OMAP_IH1_MIR,
+        MPUI1610_SLEEP_SAVE_OMAP_IH2_0_MIR,
+        MPUI1610_SLEEP_SAVE_OMAP_IH2_1_MIR,
+        MPUI1610_SLEEP_SAVE_OMAP_IH2_2_MIR,
+        MPUI1610_SLEEP_SAVE_OMAP_IH2_3_MIR,
+#if defined(CONFIG_ARCH_OMAP16XX)
+        MPUI1610_SLEEP_SAVE_SIZE
+#else
+        MPUI1610_SLEEP_SAVE_SIZE = 0
+#endif
+};
+
+enum omap24xx_save_state {
+        OMAP24XX_SLEEP_SAVE_START = 0,
+        OMAP24XX_SLEEP_SAVE_INTC_MIR0,
+        OMAP24XX_SLEEP_SAVE_INTC_MIR1,
+        OMAP24XX_SLEEP_SAVE_INTC_MIR2,
+
+        OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_MPU,
+        OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_CORE,
+        OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_GFX,
+        OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_DSP,
+        OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_MDM,
+
+        OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_MPU,
+        OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_CORE,
+        OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_GFX,
+        OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_DSP,
+        OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_MDM,
+
+        OMAP24XX_SLEEP_SAVE_CM_IDLEST1_CORE,
+        OMAP24XX_SLEEP_SAVE_CM_IDLEST2_CORE,
+        OMAP24XX_SLEEP_SAVE_CM_IDLEST3_CORE,
+        OMAP24XX_SLEEP_SAVE_CM_IDLEST4_CORE,
+        OMAP24XX_SLEEP_SAVE_CM_IDLEST_GFX,
+        OMAP24XX_SLEEP_SAVE_CM_IDLEST_WKUP,
+        OMAP24XX_SLEEP_SAVE_CM_IDLEST_CKGEN,
+        OMAP24XX_SLEEP_SAVE_CM_IDLEST_DSP,
+        OMAP24XX_SLEEP_SAVE_CM_IDLEST_MDM,
+
+        OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE1_CORE,
+        OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE2_CORE,
+        OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE3_CORE,
+        OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE4_CORE,
+        OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_WKUP,
+        OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_PLL,
+        OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_DSP,
+        OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_MDM,
+
+        OMAP24XX_SLEEP_SAVE_CM_FCLKEN1_CORE,
+        OMAP24XX_SLEEP_SAVE_CM_FCLKEN2_CORE,
+        OMAP24XX_SLEEP_SAVE_CM_ICLKEN1_CORE,
+        OMAP24XX_SLEEP_SAVE_CM_ICLKEN2_CORE,
+        OMAP24XX_SLEEP_SAVE_CM_ICLKEN3_CORE,
+        OMAP24XX_SLEEP_SAVE_CM_ICLKEN4_CORE,
+        OMAP24XX_SLEEP_SAVE_GPIO1_IRQENABLE1,
+        OMAP24XX_SLEEP_SAVE_GPIO2_IRQENABLE1,
+        OMAP24XX_SLEEP_SAVE_GPIO3_IRQENABLE1,
+        OMAP24XX_SLEEP_SAVE_GPIO4_IRQENABLE1,
+        OMAP24XX_SLEEP_SAVE_GPIO3_OE,
+        OMAP24XX_SLEEP_SAVE_GPIO4_OE,
+        OMAP24XX_SLEEP_SAVE_GPIO3_RISINGDETECT,
+        OMAP24XX_SLEEP_SAVE_GPIO3_FALLINGDETECT,
+        OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SPI1_NCS2,
+        OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_MCBSP1_DX,
+        OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SSI1_FLAG_TX,
+        OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SYS_NIRQW0,
+        OMAP24XX_SLEEP_SAVE_SIZE
+};
+
+#endif /* ASSEMBLER */
+#endif /* __ASM_ARCH_OMAP_PM_H */
diff --git a/arch/arm/plat-omap/include/mach/prcm.h b/arch/arm/plat-omap/include/mach/prcm.h
new file mode 100644
index 000000000000..56eba0fd6f6a
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/prcm.h
@@ -0,0 +1,33 @@
+/*
+ * arch/arm/plat-omap/include/mach/prcm.h
+ *
+ * Access definations for use in OMAP24XX clock and power management
+ *
+ * Copyright (C) 2005 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARM_ARCH_DPM_PRCM_H
+#define __ASM_ARM_ARCH_DPM_PRCM_H
+
+u32 omap_prcm_get_reset_sources(void);
+
+#endif
+
+
+
+
+
diff --git a/arch/arm/plat-omap/include/mach/sdrc.h b/arch/arm/plat-omap/include/mach/sdrc.h
new file mode 100644
index 000000000000..787b7acec546
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/sdrc.h
@@ -0,0 +1,75 @@
+#ifndef ____ASM_ARCH_SDRC_H
+#define ____ASM_ARCH_SDRC_H
+
+/*
+ * OMAP2/3 SDRC/SMS register definitions
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <mach/io.h>
+
+/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
+
+#define SDRC_SYSCONFIG          0x010
+#define SDRC_DLLA_CTRL          0x060
+#define SDRC_DLLA_STATUS        0x064
+#define SDRC_DLLB_CTRL          0x068
+#define SDRC_DLLB_STATUS        0x06C
+#define SDRC_POWER              0x070
+#define SDRC_MR_0               0x084
+#define SDRC_RFR_CTRL_0         0x0a4
+
+/*
+ * These values represent the number of memory clock cycles between
+ * autorefresh initiation.  They assume 1 refresh per 64 ms (JEDEC), 8192
+ * rows per device, and include a subtraction of a 50 cycle window in the
+ * event that the autorefresh command is delayed due to other SDRC activity.
+ * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
+ * counter reaches 0.
+ *
+ * These represent optimal values for common parts, it won't work for all.
+ * As long as you scale down, most parameters are still work, they just
+ * become sub-optimal. The RFR value goes in the opposite direction. If you
+ * don't adjust it down as your clock period increases the refresh interval
+ * will not be met. Setting all parameters for complete worst case may work,
+ * but may cut memory performance by 2x. Due to errata the DLLs need to be
+ * unlocked and their value needs run time calibration. A dynamic call is
+ * need for that as no single right value exists acorss production samples.
+ *
+ * Only the FULL speed values are given. Current code is such that rate
+ * changes must be made at DPLLoutx2. The actual value adjustment for low
+ * frequency operation will be handled by omap_set_performance()
+ *
+ * By having the boot loader boot up in the fastest L4 speed available likely
+ * will result in something which you can switch between.
+ */
+#define SDRC_RFR_CTRL_165MHz    (0x00044c00 | 1)
+#define SDRC_RFR_CTRL_133MHz    (0x0003de00 | 1)
+#define SDRC_RFR_CTRL_100MHz    (0x0002da01 | 1)
+#define SDRC_RFR_CTRL_110MHz    (0x0002da01 | 1) /* Need to calc */
+#define SDRC_RFR_CTRL_BYPASS    (0x00005000 | 1) /* Need to calc */
+
+
+/*
+ * SMS register access
+ */
+
+
+#define OMAP242X_SMS_REGADDR(reg)       (void __iomem *)IO_ADDRESS(OMAP2420_SMS_BASE + reg)
+#define OMAP243X_SMS_REGADDR(reg)       (void __iomem *)IO_ADDRESS(OMAP243X_SMS_BASE + reg)
+#define OMAP343X_SMS_REGADDR(reg)       (void __iomem *)IO_ADDRESS(OMAP343X_SMS_BASE + reg)
+
+/* SMS register offsets - read/write with sms_{read,write}_reg() */
+
+#define SMS_SYSCONFIG           0x010
+/* REVISIT: fill in other SMS registers here */
+
+#endif
diff --git a/arch/arm/plat-omap/include/mach/serial.h b/arch/arm/plat-omap/include/mach/serial.h
new file mode 100644
index 000000000000..cc6bfa51ccb5
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/serial.h
@@ -0,0 +1,37 @@
+/*
+ *  arch/arm/plat-omap/include/mach/serial.h
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_SERIAL_H
+#define __ASM_ARCH_SERIAL_H
+
+#if defined(CONFIG_ARCH_OMAP1)
+/* OMAP1 serial ports */
+#define OMAP_UART1_BASE         0xfffb0000
+#define OMAP_UART2_BASE         0xfffb0800
+#define OMAP_UART3_BASE         0xfffb9800
+#elif defined(CONFIG_ARCH_OMAP2)
+/* OMAP2 serial ports */
+#define OMAP_UART1_BASE         0x4806a000
+#define OMAP_UART2_BASE         0x4806c000
+#define OMAP_UART3_BASE         0x4806e000
+#endif
+
+#define OMAP_MAX_NR_PORTS       3
+#define OMAP1510_BASE_BAUD      (12000000/16)
+#define OMAP16XX_BASE_BAUD      (48000000/16)
+
+#define is_omap_port(p) ({int __ret = 0;                        \
+                        if (p == IO_ADDRESS(OMAP_UART1_BASE) || \
+                            p == IO_ADDRESS(OMAP_UART2_BASE) || \
+                            p == IO_ADDRESS(OMAP_UART3_BASE))   \
+                                __ret = 1;                      \
+                        __ret;                                  \
+                        })
+
+#endif
diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/mach/sram.h
new file mode 100644
index 000000000000..e09323449981
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/sram.h
@@ -0,0 +1,56 @@
+/*
+ * arch/arm/plat-omap/include/mach/sram.h
+ *
+ * Interface for functions that need to be run in internal SRAM
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_OMAP_SRAM_H
+#define __ARCH_ARM_OMAP_SRAM_H
+
+extern int __init omap_sram_init(void);
+extern void * omap_sram_push(void * start, unsigned long size);
+extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
+
+extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
+                                u32 base_cs, u32 force_unlock);
+extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
+                                      u32 mem_type);
+extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
+
+/* Do not use these */
+extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
+extern unsigned long omap1_sram_reprogram_clock_sz;
+
+extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
+extern unsigned long omap24xx_sram_reprogram_clock_sz;
+
+extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
+                                                u32 base_cs, u32 force_unlock);
+extern unsigned long omap242x_sram_ddr_init_sz;
+
+extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
+                                                int bypass);
+extern unsigned long omap242x_sram_set_prcm_sz;
+
+extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
+                                                u32 mem_type);
+extern unsigned long omap242x_sram_reprogram_sdrc_sz;
+
+
+extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
+                                                u32 base_cs, u32 force_unlock);
+extern unsigned long omap243x_sram_ddr_init_sz;
+
+extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
+                                                int bypass);
+extern unsigned long omap243x_sram_set_prcm_sz;
+
+extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
+                                                u32 mem_type);
+extern unsigned long omap243x_sram_reprogram_sdrc_sz;
+
+#endif
diff --git a/arch/arm/plat-omap/include/mach/system.h b/arch/arm/plat-omap/include/mach/system.h
new file mode 100644
index 000000000000..06a28c7b98de
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/system.h
@@ -0,0 +1,49 @@
+/*
+ * Copied from arch/arm/mach-sa1100/include/mach/system.h
+ * Copyright (c) 1999 Nicolas Pitre <nico@cam.org>
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+#include <linux/clk.h>
+
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+
+#ifndef CONFIG_MACH_VOICEBLUE
+#define voiceblue_reset()               do {} while (0)
+#endif
+
+extern void omap_prcm_arch_reset(char mode);
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void omap1_arch_reset(char mode)
+{
+        /*
+         * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
+         * "Global Software Reset Affects Traffic Controller Frequency".
+         */
+        if (cpu_is_omap5912()) {
+                omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4),
+                                 DPLL_CTL);
+                omap_writew(0x8, ARM_RSTCT1);
+        }
+
+        if (machine_is_voiceblue())
+                voiceblue_reset();
+        else
+                omap_writew(1, ARM_RSTCT1);
+}
+
+static inline void arch_reset(char mode)
+{
+        if (!cpu_is_omap24xx())
+                omap1_arch_reset(mode);
+        else
+                omap_prcm_arch_reset(mode);
+}
+
+#endif
diff --git a/arch/arm/plat-omap/include/mach/tc.h b/arch/arm/plat-omap/include/mach/tc.h
new file mode 100644
index 000000000000..d2fcd789bb9a
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/tc.h
@@ -0,0 +1,106 @@
+/*
+ * arch/arm/plat-omap/include/mach/tc.h
+ *
+ * OMAP Traffic Controller
+ *
+ * Copyright (C) 2004 Nokia Corporation
+ * Author: Imre Deak <imre.deak@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+
+#ifndef __ASM_ARCH_TC_H
+#define __ASM_ARCH_TC_H
+
+#define TCMIF_BASE              0xfffecc00
+#define OMAP_TC_OCPT1_PRIOR     (TCMIF_BASE + 0x00)
+#define OMAP_TC_EMIFS_PRIOR     (TCMIF_BASE + 0x04)
+#define OMAP_TC_EMIFF_PRIOR     (TCMIF_BASE + 0x08)
+#define EMIFS_CONFIG            (TCMIF_BASE + 0x0c)
+#define EMIFS_CS0_CONFIG        (TCMIF_BASE + 0x10)
+#define EMIFS_CS1_CONFIG        (TCMIF_BASE + 0x14)
+#define EMIFS_CS2_CONFIG        (TCMIF_BASE + 0x18)
+#define EMIFS_CS3_CONFIG        (TCMIF_BASE + 0x1c)
+#define EMIFF_SDRAM_CONFIG      (TCMIF_BASE + 0x20)
+#define EMIFF_MRS               (TCMIF_BASE + 0x24)
+#define TC_TIMEOUT1             (TCMIF_BASE + 0x28)
+#define TC_TIMEOUT2             (TCMIF_BASE + 0x2c)
+#define TC_TIMEOUT3             (TCMIF_BASE + 0x30)
+#define TC_ENDIANISM            (TCMIF_BASE + 0x34)
+#define EMIFF_SDRAM_CONFIG_2    (TCMIF_BASE + 0x3c)
+#define EMIF_CFG_DYNAMIC_WS     (TCMIF_BASE + 0x40)
+#define EMIFS_ACS0              (TCMIF_BASE + 0x50)
+#define EMIFS_ACS1              (TCMIF_BASE + 0x54)
+#define EMIFS_ACS2              (TCMIF_BASE + 0x58)
+#define EMIFS_ACS3              (TCMIF_BASE + 0x5c)
+#define OMAP_TC_OCPT2_PRIOR     (TCMIF_BASE + 0xd0)
+
+/* external EMIFS chipselect regions */
+#define OMAP_CS0_PHYS           0x00000000
+#define OMAP_CS0_SIZE           SZ_64M
+
+#define OMAP_CS1_PHYS           0x04000000
+#define OMAP_CS1_SIZE           SZ_64M
+
+#define OMAP_CS1A_PHYS          OMAP_CS1_PHYS
+#define OMAP_CS1A_SIZE          SZ_32M
+
+#define OMAP_CS1B_PHYS          (OMAP_CS1A_PHYS + OMAP_CS1A_SIZE)
+#define OMAP_CS1B_SIZE          SZ_32M
+
+#define OMAP_CS2_PHYS           0x08000000
+#define OMAP_CS2_SIZE           SZ_64M
+
+#define OMAP_CS2A_PHYS          OMAP_CS2_PHYS
+#define OMAP_CS2A_SIZE          SZ_32M
+
+#define OMAP_CS2B_PHYS          (OMAP_CS2A_PHYS + OMAP_CS2A_SIZE)
+#define OMAP_CS2B_SIZE          SZ_32M
+
+#define OMAP_CS3_PHYS           0x0c000000
+#define OMAP_CS3_SIZE           SZ_64M
+
+#ifndef __ASSEMBLER__
+
+/* EMIF Slow Interface Configuration Register */
+#define OMAP_EMIFS_CONFIG_FR            (1 << 4)
+#define OMAP_EMIFS_CONFIG_PDE           (1 << 3)
+#define OMAP_EMIFS_CONFIG_PWD_EN        (1 << 2)
+#define OMAP_EMIFS_CONFIG_BM            (1 << 1)
+#define OMAP_EMIFS_CONFIG_WP            (1 << 0)
+
+#define EMIFS_CCS(n)            (EMIFS_CS0_CONFIG + (4 * (n)))
+#define EMIFS_ACS(n)            (EMIFS_ACS0 + (4 * (n)))
+
+/* Almost all documentation for chip and board memory maps assumes
+ * BM is clear.  Most devel boards have a switch to control booting
+ * from NOR flash (using external chipselect 3) rather than mask ROM,
+ * which uses BM to interchange the physical CS0 and CS3 addresses.
+ */
+static inline u32 omap_cs0_phys(void)
+{
+        return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
+                        ?  OMAP_CS3_PHYS : 0;
+}
+
+static inline u32 omap_cs3_phys(void)
+{
+        return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
+                        ? 0 : OMAP_CS3_PHYS;
+}
+
+#endif  /* __ASSEMBLER__ */
+
+#endif  /* __ASM_ARCH_TC_H */
diff --git a/arch/arm/plat-omap/include/mach/timex.h b/arch/arm/plat-omap/include/mach/timex.h
new file mode 100644
index 000000000000..6d35767bc48f
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/timex.h
@@ -0,0 +1,41 @@
+/*
+ * arch/arm/plat-omap/include/mach/timex.h
+ *
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Author:  Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#if !defined(__ASM_ARCH_OMAP_TIMEX_H)
+#define __ASM_ARCH_OMAP_TIMEX_H
+
+/*
+ * OMAP 32KHz timer updates time one jiffie at a time from a secondary timer,
+ * and that's why the CLOCK_TICK_RATE is not 32768.
+ */
+#ifdef CONFIG_OMAP_32K_TIMER
+#define CLOCK_TICK_RATE         (CONFIG_OMAP_32K_TIMER_HZ)
+#else
+#define CLOCK_TICK_RATE         (HZ * 100000UL)
+#endif
+
+#endif /* __ASM_ARCH_OMAP_TIMEX_H */
diff --git a/arch/arm/plat-omap/include/mach/uncompress.h b/arch/arm/plat-omap/include/mach/uncompress.h
new file mode 100644
index 000000000000..0814c5f210c3
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/uncompress.h
@@ -0,0 +1,83 @@
+/*
+ * arch/arm/plat-omap/include/mach/uncompress.h
+ *
+ * Serial port stubs for kernel decompress status messages
+ *
+ * Initially based on:
+ * linux-2.4.15-rmk1-dsplinux1.6/arch/arm/plat-omap/include/mach1510/uncompress.h
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Author: Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * Rewritten by:
+ * Author: <source@mvista.com>
+ * 2004 (c) MontaVista Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/types.h>
+#include <linux/serial_reg.h>
+#include <mach/serial.h>
+
+unsigned int system_rev;
+
+#define UART_OMAP_MDR1          0x08    /* mode definition register */
+#define OMAP_ID_730             0x355F
+#define ID_MASK                 0x7fff
+#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0)
+#define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK
+
+static void putc(int c)
+{
+        volatile u8 * uart = 0;
+        int shift = 2;
+
+#ifdef CONFIG_MACH_OMAP_PALMTE
+        return;
+#endif
+
+#ifdef CONFIG_ARCH_OMAP
+#ifdef  CONFIG_OMAP_LL_DEBUG_UART3
+        uart = (volatile u8 *)(OMAP_UART3_BASE);
+#elif defined(CONFIG_OMAP_LL_DEBUG_UART2)
+        uart = (volatile u8 *)(OMAP_UART2_BASE);
+#else
+        uart = (volatile u8 *)(OMAP_UART1_BASE);
+#endif
+
+#ifdef CONFIG_ARCH_OMAP1
+        /* Determine which serial port to use */
+        do {
+                /* MMU is not on, so cpu_is_omapXXXX() won't work here */
+                unsigned int omap_id = omap_get_id();
+
+                if (omap_id == OMAP_ID_730)
+                        shift = 0;
+
+                if (check_port(uart, shift))
+                        break;
+                /* Silent boot if no serial ports are enabled. */
+                return;
+        } while (0);
+#endif /* CONFIG_ARCH_OMAP1 */
+#endif
+
+        /*
+         * Now, xmit each character
+         */
+        while (!(uart[UART_LSR << shift] & UART_LSR_THRE))
+                barrier();
+        uart[UART_TX << shift] = c;
+}
+
+static inline void flush(void)
+{
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/plat-omap/include/mach/usb.h b/arch/arm/plat-omap/include/mach/usb.h
new file mode 100644
index 000000000000..a56a610950c2
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/usb.h
@@ -0,0 +1,141 @@
+// include/asm-arm/mach-omap/usb.h
+
+#ifndef __ASM_ARCH_OMAP_USB_H
+#define __ASM_ARCH_OMAP_USB_H
+
+#include <mach/board.h>
+
+/*-------------------------------------------------------------------------*/
+
+#define OMAP1_OTG_BASE                  0xfffb0400
+#define OMAP1_UDC_BASE                  0xfffb4000
+#define OMAP1_OHCI_BASE                 0xfffba000
+
+#define OMAP2_OHCI_BASE                 0x4805e000
+#define OMAP2_UDC_BASE                  0x4805e200
+#define OMAP2_OTG_BASE                  0x4805e300
+
+#ifdef CONFIG_ARCH_OMAP1
+
+#define OTG_BASE                        OMAP1_OTG_BASE
+#define UDC_BASE                        OMAP1_UDC_BASE
+#define OMAP_OHCI_BASE                  OMAP1_OHCI_BASE
+
+#else
+
+#define OTG_BASE                        OMAP2_OTG_BASE
+#define UDC_BASE                        OMAP2_UDC_BASE
+#define OMAP_OHCI_BASE                  OMAP2_OHCI_BASE
+
+#endif
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * OTG and transceiver registers, for OMAPs starting with ARM926
+ */
+#define OTG_REV                         (OTG_BASE + 0x00)
+#define OTG_SYSCON_1                    (OTG_BASE + 0x04)
+#       define   USB2_TRX_MODE(w)       (((w)>>24)&0x07)
+#       define   USB1_TRX_MODE(w)       (((w)>>20)&0x07)
+#       define   USB0_TRX_MODE(w)       (((w)>>16)&0x07)
+#       define   OTG_IDLE_EN            (1 << 15)
+#       define   HST_IDLE_EN            (1 << 14)
+#       define   DEV_IDLE_EN            (1 << 13)
+#       define   OTG_RESET_DONE         (1 << 2)
+#       define   OTG_SOFT_RESET         (1 << 1)
+#define OTG_SYSCON_2                    (OTG_BASE + 0x08)
+#       define   OTG_EN                 (1 << 31)
+#       define   USBX_SYNCHRO           (1 << 30)
+#       define   OTG_MST16              (1 << 29)
+#       define   SRP_GPDATA             (1 << 28)
+#       define   SRP_GPDVBUS            (1 << 27)
+#       define   SRP_GPUVBUS(w)         (((w)>>24)&0x07)
+#       define   A_WAIT_VRISE(w)        (((w)>>20)&0x07)
+#       define   B_ASE_BRST(w)          (((w)>>16)&0x07)
+#       define   SRP_DPW                (1 << 14)
+#       define   SRP_DATA               (1 << 13)
+#       define   SRP_VBUS               (1 << 12)
+#       define   OTG_PADEN              (1 << 10)
+#       define   HMC_PADEN              (1 << 9)
+#       define   UHOST_EN               (1 << 8)
+#       define   HMC_TLLSPEED           (1 << 7)
+#       define   HMC_TLLATTACH          (1 << 6)
+#       define   OTG_HMC(w)             (((w)>>0)&0x3f)
+#define OTG_CTRL                        (OTG_BASE + 0x0c)
+#       define   OTG_USB2_EN            (1 << 29)
+#       define   OTG_USB2_DP            (1 << 28)
+#       define   OTG_USB2_DM            (1 << 27)
+#       define   OTG_USB1_EN            (1 << 26)
+#       define   OTG_USB1_DP            (1 << 25)
+#       define   OTG_USB1_DM            (1 << 24)
+#       define   OTG_USB0_EN            (1 << 23)
+#       define   OTG_USB0_DP            (1 << 22)
+#       define   OTG_USB0_DM            (1 << 21)
+#       define   OTG_ASESSVLD           (1 << 20)
+#       define   OTG_BSESSEND           (1 << 19)
+#       define   OTG_BSESSVLD           (1 << 18)
+#       define   OTG_VBUSVLD            (1 << 17)
+#       define   OTG_ID                 (1 << 16)
+#       define   OTG_DRIVER_SEL         (1 << 15)
+#       define   OTG_A_SETB_HNPEN       (1 << 12)
+#       define   OTG_A_BUSREQ           (1 << 11)
+#       define   OTG_B_HNPEN            (1 << 9)
+#       define   OTG_B_BUSREQ           (1 << 8)
+#       define   OTG_BUSDROP            (1 << 7)
+#       define   OTG_PULLDOWN           (1 << 5)
+#       define   OTG_PULLUP             (1 << 4)
+#       define   OTG_DRV_VBUS           (1 << 3)
+#       define   OTG_PD_VBUS            (1 << 2)
+#       define   OTG_PU_VBUS            (1 << 1)
+#       define   OTG_PU_ID              (1 << 0)
+#define OTG_IRQ_EN                      (OTG_BASE + 0x10)       /* 16-bit */
+#       define   DRIVER_SWITCH          (1 << 15)
+#       define   A_VBUS_ERR             (1 << 13)
+#       define   A_REQ_TMROUT           (1 << 12)
+#       define   A_SRP_DETECT           (1 << 11)
+#       define   B_HNP_FAIL             (1 << 10)
+#       define   B_SRP_TMROUT           (1 << 9)
+#       define   B_SRP_DONE             (1 << 8)
+#       define   B_SRP_STARTED          (1 << 7)
+#       define   OPRT_CHG               (1 << 0)
+#define OTG_IRQ_SRC                     (OTG_BASE + 0x14)       /* 16-bit */
+        // same bits as in IRQ_EN
+#define OTG_OUTCTRL                     (OTG_BASE + 0x18)       /* 16-bit */
+#       define   OTGVPD                 (1 << 14)
+#       define   OTGVPU                 (1 << 13)
+#       define   OTGPUID                (1 << 12)
+#       define   USB2VDR                (1 << 10)
+#       define   USB2PDEN               (1 << 9)
+#       define   USB2PUEN               (1 << 8)
+#       define   USB1VDR                (1 << 6)
+#       define   USB1PDEN               (1 << 5)
+#       define   USB1PUEN               (1 << 4)
+#       define   USB0VDR                (1 << 2)
+#       define   USB0PDEN               (1 << 1)
+#       define   USB0PUEN               (1 << 0)
+#define OTG_TEST                        (OTG_BASE + 0x20)       /* 16-bit */
+#define OTG_VENDOR_CODE                 (OTG_BASE + 0xfc)       /* 16-bit */
+
+/*-------------------------------------------------------------------------*/
+
+/* OMAP1 */
+#define USB_TRANSCEIVER_CTRL            (0xfffe1000 + 0x0064)
+#       define  CONF_USB2_UNI_R         (1 << 8)
+#       define  CONF_USB1_UNI_R         (1 << 7)
+#       define  CONF_USB_PORT0_R(x)     (((x)>>4)&0x7)
+#       define  CONF_USB0_ISOLATE_R     (1 << 3)
+#       define  CONF_USB_PWRDN_DM_R     (1 << 2)
+#       define  CONF_USB_PWRDN_DP_R     (1 << 1)
+
+/* OMAP2 */
+#       define  USB_UNIDIR                      0x0
+#       define  USB_UNIDIR_TLL                  0x1
+#       define  USB_BIDIR                       0x2
+#       define  USB_BIDIR_TLL                   0x3
+#       define  USBTXWRMODEI(port, x)   ((x) << (22 - (port * 2)))
+#       define  USBT2TLL5PI             (1 << 17)
+#       define  USB0PUENACTLOI          (1 << 16)
+#       define  USBSTANDBYCTRL          (1 << 15)
+
+#endif  /* __ASM_ARCH_OMAP_USB_H */
diff --git a/arch/arm/plat-omap/include/mach/vmalloc.h b/arch/arm/plat-omap/include/mach/vmalloc.h
new file mode 100644
index 000000000000..dc104cd96197
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/vmalloc.h
@@ -0,0 +1,21 @@
+/*
+ *  arch/arm/plat-omap/include/mach/vmalloc.h
+ *
+ *  Copyright (C) 2000 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index ff1413eae0b8..1d7aec1a691a 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -31,7 +31,7 @@
 #include <linux/err.h>
 #include <linux/delay.h>
 #include <asm/io.h>
-#include <asm/arch/mailbox.h>
+#include <mach/mailbox.h>
 #include "mailbox.h"
 
 static struct omap_mbox *mboxes;
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index c7f74064696c..d0844050f2d2 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -24,8 +24,8 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 
-#include <asm/arch/dma.h>
-#include <asm/arch/mcbsp.h>
+#include <mach/dma.h>
+#include <mach/mcbsp.h>
 
 static struct omap_mcbsp mcbsp[OMAP_MAX_MCBSP_COUNT];
 
diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c
index 6f3f459731c8..847df208c46c 100644
--- a/arch/arm/plat-omap/mux.c
+++ b/arch/arm/plat-omap/mux.c
@@ -28,7 +28,7 @@
 #include <asm/system.h>
 #include <asm/io.h>
 #include <linux/spinlock.h>
-#include <asm/arch/mux.h>
+#include <mach/mux.h>
 
 #ifdef CONFIG_OMAP_MUX
 
diff --git a/arch/arm/plat-omap/ocpi.c b/arch/arm/plat-omap/ocpi.c
index 005261a4e720..8bdbf979a257 100644
--- a/arch/arm/plat-omap/ocpi.c
+++ b/arch/arm/plat-omap/ocpi.c
@@ -33,7 +33,7 @@
 #include <linux/clk.h>
 
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 #define OCPI_BASE               0xfffec320
 #define OCPI_FAULT              (OCPI_BASE + 0x00)
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 554ee58e1294..ac67eeb6ca6a 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -22,10 +22,10 @@
 
 #include <asm/mach/map.h>
 
-#include <asm/arch/sram.h>
-#include <asm/arch/board.h>
+#include <mach/sram.h>
+#include <mach/board.h>
 
-#include <asm/arch/control.h>
+#include <mach/control.h>
 
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
 # include "../mach-omap2/prm.h"
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
index 359912ffed7f..777485e0636b 100644
--- a/arch/arm/plat-omap/usb.c
+++ b/arch/arm/plat-omap/usb.c
@@ -31,12 +31,12 @@
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/system.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
-#include <asm/arch/control.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/usb.h>
-#include <asm/arch/board.h>
+#include <mach/control.h>
+#include <mach/mux.h>
+#include <mach/usb.h>
+#include <mach/board.h>
 
 #ifdef CONFIG_ARCH_OMAP1
 
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
index 93c4ef9f0067..544d6b327f3a 100644
--- a/arch/arm/plat-orion/time.c
+++ b/arch/arm/plat-orion/time.c
@@ -16,7 +16,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <asm/mach/time.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 /*
  * Number of timer ticks per jiffy.
diff --git a/arch/arm/plat-s3c24xx/clock.c b/arch/arm/plat-s3c24xx/clock.c
index 373d04358485..54d4b8e2263c 100644
--- a/arch/arm/plat-s3c24xx/clock.c
+++ b/arch/arm/plat-s3c24xx/clock.c
@@ -40,12 +40,12 @@
 #include <linux/mutex.h>
 #include <linux/delay.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/io.h>
 
-#include <asm/arch/regs-clock.h>
-#include <asm/arch/regs-gpio.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-gpio.h>
 
 #include <asm/plat-s3c24xx/clock.h>
 #include <asm/plat-s3c24xx/cpu.h>
diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c
index a608aa388820..1863a1b1bc49 100644
--- a/arch/arm/plat-s3c24xx/common-smdk.c
+++ b/arch/arm/plat-s3c24xx/common-smdk.c
@@ -31,12 +31,12 @@
 #include <asm/mach/irq.h>
 
 #include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/leds-gpio.h>
+#include <mach/regs-gpio.h>
+#include <mach/leds-gpio.h>
 
 #include <asm/plat-s3c/nand.h>
 
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index 05a1d9cc280c..6d60f0476bb8 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -30,7 +30,7 @@
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/io.h>
 #include <asm/delay.h>
@@ -39,9 +39,9 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <asm/arch/system-reset.h>
+#include <mach/system-reset.h>
 
-#include <asm/arch/regs-gpio.h>
+#include <mach/regs-gpio.h>
 #include <asm/plat-s3c/regs-serial.h>
 
 #include <asm/plat-s3c24xx/cpu.h>
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c
index 5c6f446a1fa9..d6fb76578b11 100644
--- a/arch/arm/plat-s3c24xx/devs.c
+++ b/arch/arm/plat-s3c24xx/devs.c
@@ -23,8 +23,8 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <asm/arch/fb.h>
-#include <asm/arch/hardware.h>
+#include <mach/fb.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index 8ae5719d6b3b..08c2aaf14c41 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -29,12 +29,12 @@
 
 #include <asm/system.h>
 #include <asm/irq.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/dma.h>
 
 #include <asm/mach/dma.h>
-#include <asm/arch/map.h>
+#include <mach/map.h>
 
 #include <asm/plat-s3c24xx/dma.h>
 
diff --git a/arch/arm/plat-s3c24xx/gpio.c b/arch/arm/plat-s3c24xx/gpio.c
index ace8bec5de5a..dd27334e3d7e 100644
--- a/arch/arm/plat-s3c24xx/gpio.c
+++ b/arch/arm/plat-s3c24xx/gpio.c
@@ -27,11 +27,11 @@
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/io.h>
 
-#include <asm/arch/regs-gpio.h>
+#include <mach/regs-gpio.h>
 
 void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function)
 {
diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c
index 6dd5211c9c67..849f8469714a 100644
--- a/arch/arm/plat-s3c24xx/gpiolib.c
+++ b/arch/arm/plat-s3c24xx/gpiolib.c
@@ -19,10 +19,10 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 
-#include <asm/arch/regs-gpio.h>
+#include <mach/regs-gpio.h>
 
 struct s3c24xx_gpio_chip {
         struct gpio_chip        chip;
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
index f524d765c8aa..36cefe176835 100644
--- a/arch/arm/plat-s3c24xx/irq.c
+++ b/arch/arm/plat-s3c24xx/irq.c
@@ -56,14 +56,14 @@
 #include <linux/ioport.h>
 #include <linux/sysdev.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/io.h>
 
 #include <asm/mach/irq.h>
 
-#include <asm/arch/regs-irq.h>
-#include <asm/arch/regs-gpio.h>
+#include <mach/regs-irq.h>
+#include <mach/regs-gpio.h>
 
 #include <asm/plat-s3c24xx/cpu.h>
 #include <asm/plat-s3c24xx/pm.h>
diff --git a/arch/arm/plat-s3c24xx/pm-simtec.c b/arch/arm/plat-s3c24xx/pm-simtec.c
index 9919419e3273..e6705014b2a0 100644
--- a/arch/arm/plat-s3c24xx/pm-simtec.c
+++ b/arch/arm/plat-s3c24xx/pm-simtec.c
@@ -24,12 +24,12 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 
-#include <asm/arch/map.h>
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-mem.h>
+#include <mach/map.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-mem.h>
 
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c
index 0d044bcbe1ac..fc4b731a949c 100644
--- a/arch/arm/plat-s3c24xx/pm.c
+++ b/arch/arm/plat-s3c24xx/pm.c
@@ -37,14 +37,14 @@
 #include <linux/serial_core.h>
 
 #include <asm/cacheflush.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 
 #include <asm/plat-s3c/regs-serial.h>
-#include <asm/arch/regs-clock.h>
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-mem.h>
-#include <asm/arch/regs-irq.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-mem.h>
+#include <mach/regs-irq.h>
 
 #include <asm/mach/time.h>
 
diff --git a/arch/arm/plat-s3c24xx/pwm-clock.c b/arch/arm/plat-s3c24xx/pwm-clock.c
index 489e32abf3ac..ccfdc9d7ae4b 100644
--- a/arch/arm/plat-s3c24xx/pwm-clock.c
+++ b/arch/arm/plat-s3c24xx/pwm-clock.c
@@ -18,11 +18,11 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 
-#include <asm/arch/regs-clock.h>
-#include <asm/arch/regs-gpio.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-gpio.h>
 
 #include <asm/plat-s3c24xx/clock.h>
 #include <asm/plat-s3c24xx/cpu.h>
diff --git a/arch/arm/plat-s3c24xx/s3c244x-clock.c b/arch/arm/plat-s3c24xx/s3c244x-clock.c
index a811e8b6d455..8a5fffde6631 100644
--- a/arch/arm/plat-s3c24xx/s3c244x-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c244x-clock.c
@@ -34,12 +34,12 @@
 #include <linux/mutex.h>
 #include <linux/clk.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/atomic.h>
 #include <asm/irq.h>
 #include <asm/io.h>
 
-#include <asm/arch/regs-clock.h>
+#include <mach/regs-clock.h>
 
 #include <asm/plat-s3c24xx/clock.h>
 #include <asm/plat-s3c24xx/cpu.h>
diff --git a/arch/arm/plat-s3c24xx/s3c244x-irq.c b/arch/arm/plat-s3c24xx/s3c244x-irq.c
index 2eefe16bd2a8..f3dc38cf1de4 100644
--- a/arch/arm/plat-s3c24xx/s3c244x-irq.c
+++ b/arch/arm/plat-s3c24xx/s3c244x-irq.c
@@ -25,14 +25,14 @@
 #include <linux/ioport.h>
 #include <linux/sysdev.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/io.h>
 
 #include <asm/mach/irq.h>
 
-#include <asm/arch/regs-irq.h>
-#include <asm/arch/regs-gpio.h>
+#include <mach/regs-irq.h>
+#include <mach/regs-gpio.h>
 
 #include <asm/plat-s3c24xx/cpu.h>
 #include <asm/plat-s3c24xx/pm.h>
diff --git a/arch/arm/plat-s3c24xx/s3c244x.c b/arch/arm/plat-s3c24xx/s3c244x.c
index eb9dd4f9b8ec..281b4804ed38 100644
--- a/arch/arm/plat-s3c24xx/s3c244x.c
+++ b/arch/arm/plat-s3c24xx/s3c244x.c
@@ -25,15 +25,15 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 
-#include <asm/arch/regs-clock.h>
+#include <mach/regs-clock.h>
 #include <asm/plat-s3c/regs-serial.h>
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-gpioj.h>
-#include <asm/arch/regs-dsc.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-gpioj.h>
+#include <mach/regs-dsc.h>
 
 #include <asm/plat-s3c24xx/s3c2410.h>
 #include <asm/plat-s3c24xx/s3c2440.h>
diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S
index 4f8756e19bb1..4981a08b6ebb 100644
--- a/arch/arm/plat-s3c24xx/sleep.S
+++ b/arch/arm/plat-s3c24xx/sleep.S
@@ -26,12 +26,12 @@
 
 #include <linux/linkage.h>
 #include <asm/assembler.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/map.h>
+#include <mach/hardware.h>
+#include <mach/map.h>
 
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-clock.h>
-#include <asm/arch/regs-mem.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-mem.h>
 #include <asm/plat-s3c/regs-serial.h>
 
 /* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not
diff --git a/arch/arm/plat-s3c24xx/time.c b/arch/arm/plat-s3c24xx/time.c
index 766473b3f98b..b471a21ae2e4 100644
--- a/arch/arm/plat-s3c24xx/time.c
+++ b/arch/arm/plat-s3c24xx/time.c
@@ -32,9 +32,9 @@
 
 #include <asm/io.h>
 #include <asm/irq.h>
-#include <asm/arch/map.h>
+#include <mach/map.h>
 #include <asm/plat-s3c/regs-timer.h>
-#include <asm/arch/regs-irq.h>
+#include <mach/regs-irq.h>
 #include <asm/mach/time.h>
 
 #include <asm/plat-s3c24xx/clock.h>
diff --git a/drivers/char/ds1620.c b/drivers/char/ds1620.c
index be85c6d1edfe..74e9cd81b5b2 100644
--- a/drivers/char/ds1620.c
+++ b/drivers/char/ds1620.c
@@ -10,7 +10,7 @@
 #include <linux/init.h>
 #include <linux/smp_lock.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/uaccess.h>
 #include <asm/therm.h>
diff --git a/drivers/char/hw_random/ixp4xx-rng.c b/drivers/char/hw_random/ixp4xx-rng.c
index b4402b5958e8..263567f5f392 100644
--- a/drivers/char/hw_random/ixp4xx-rng.c
+++ b/drivers/char/hw_random/ixp4xx-rng.c
@@ -23,7 +23,7 @@
 #include <linux/hw_random.h>
 
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 
 static int ixp4xx_rng_data_read(struct hwrng *rng, u32 *buffer)
diff --git a/drivers/crypto/ixp4xx_crypto.c b/drivers/crypto/ixp4xx_crypto.c
index 42a107fe9233..2d637e0fbc03 100644
--- a/drivers/crypto/ixp4xx_crypto.c
+++ b/drivers/crypto/ixp4xx_crypto.c
@@ -27,8 +27,8 @@
 #include <crypto/authenc.h>
 #include <crypto/scatterwalk.h>
 
-#include <asm/arch/npe.h>
-#include <asm/arch/qmgr.h>
+#include <mach/npe.h>
+#include <mach/qmgr.h>
 
 #define MAX_KEYLEN 32
 
diff --git a/drivers/dma/iop-adma.c b/drivers/dma/iop-adma.c
index 85bfeba4d85e..71fba82462cb 100644
--- a/drivers/dma/iop-adma.c
+++ b/drivers/dma/iop-adma.c
@@ -33,7 +33,7 @@
 #include <linux/memory.h>
 #include <linux/ioport.h>
 
-#include <asm/arch/adma.h>
+#include <mach/adma.h>
 
 #define to_iop_adma_chan(chan) container_of(chan, struct iop_adma_chan, common)
 #define to_iop_adma_device(dev) \
diff --git a/drivers/i2c/busses/i2c-acorn.c b/drivers/i2c/busses/i2c-acorn.c
index 5ec60d141ce1..75089febbc13 100644
--- a/drivers/i2c/busses/i2c-acorn.c
+++ b/drivers/i2c/busses/i2c-acorn.c
@@ -16,7 +16,7 @@
 #include <linux/i2c.h>
 #include <linux/i2c-algo-bit.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/hardware/ioc.h>
 #include <asm/system.h>
diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index 73d61946a534..c1adcdbf7979 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -27,9 +27,9 @@
 
 #include <asm/io.h>
 
-#include <asm/arch/at91_twi.h>
-#include <asm/arch/board.h>
-#include <asm/arch/cpu.h>
+#include <mach/at91_twi.h>
+#include <mach/board.h>
+#include <mach/cpu.h>
 
 #define TWI_CLOCK               100000          /* Hz. max 400 Kbits/sec */
 
diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davinci.c
index eccbb7451562..5d7789834b95 100644
--- a/drivers/i2c/busses/i2c-davinci.c
+++ b/drivers/i2c/busses/i2c-davinci.c
@@ -36,9 +36,9 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
-#include <asm/arch/i2c.h>
+#include <mach/i2c.h>
 
 /* ----- global defines ----------------------------------------------- */
 
diff --git a/drivers/i2c/busses/i2c-ixp2000.c b/drivers/i2c/busses/i2c-ixp2000.c
index bd0f3f4323bc..05d72e981353 100644
--- a/drivers/i2c/busses/i2c-ixp2000.c
+++ b/drivers/i2c/busses/i2c-ixp2000.c
@@ -33,8 +33,8 @@
 #include <linux/i2c.h>
 #include <linux/i2c-algo-bit.h>
 
-#include <asm/arch/hardware.h>  /* Pick up IXP2000-specific bits */
-#include <asm/arch/gpio.h>
+#include <mach/hardware.h>      /* Pick up IXP2000-specific bits */
+#include <mach/gpio.h>
 
 static inline int ixp2000_scl_pin(void *data)
 {
diff --git a/drivers/i2c/busses/i2c-pnx.c b/drivers/i2c/busses/i2c-pnx.c
index e06ccc6c5e97..ec15cff556b9 100644
--- a/drivers/i2c/busses/i2c-pnx.c
+++ b/drivers/i2c/busses/i2c-pnx.c
@@ -19,7 +19,7 @@
 #include <linux/completion.h>
 #include <linux/platform_device.h>
 #include <linux/i2c-pnx.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/uaccess.h>
 
diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c
index d65b7fbb4694..44d838410f15 100644
--- a/drivers/i2c/busses/i2c-pxa.c
+++ b/drivers/i2c/busses/i2c-pxa.c
@@ -34,11 +34,11 @@
 #include <linux/err.h>
 #include <linux/clk.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/io.h>
-#include <asm/arch/i2c.h>
-#include <asm/arch/pxa-regs.h>
+#include <mach/i2c.h>
+#include <mach/pxa-regs.h>
 
 struct pxa_i2c {
         spinlock_t              lock;
diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c
index b216bfbea78c..c772e02c2803 100644
--- a/drivers/i2c/busses/i2c-s3c2410.c
+++ b/drivers/i2c/busses/i2c-s3c2410.c
@@ -35,11 +35,11 @@
 #include <linux/clk.h>
 #include <linux/cpufreq.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/io.h>
 
-#include <asm/arch/regs-gpio.h>
+#include <mach/regs-gpio.h>
 #include <asm/plat-s3c/regs-iic.h>
 #include <asm/plat-s3c/iic.h>
 
diff --git a/drivers/i2c/chips/isp1301_omap.c b/drivers/i2c/chips/isp1301_omap.c
index 03a33f1b9cd3..18355ae2155d 100644
--- a/drivers/i2c/chips/isp1301_omap.c
+++ b/drivers/i2c/chips/isp1301_omap.c
@@ -33,7 +33,7 @@
 #include <linux/workqueue.h>
 
 #include <asm/irq.h>
-#include <asm/arch/usb.h>
+#include <mach/usb.h>
 
 
 #ifndef DEBUG
@@ -94,7 +94,7 @@ struct isp1301 {
 /* board-specific PM hooks */
 
 #include <asm/gpio.h>
-#include <asm/arch/mux.h>
+#include <mach/mux.h>
 #include <asm/mach-types.h>
 
 
diff --git a/drivers/i2c/chips/menelaus.c b/drivers/i2c/chips/menelaus.c
index e3c12e365c49..176126d3a01d 100644
--- a/drivers/i2c/chips/menelaus.c
+++ b/drivers/i2c/chips/menelaus.c
@@ -43,8 +43,8 @@
 
 #include <asm/mach/irq.h>
 
-#include <asm/arch/gpio.h>
-#include <asm/arch/menelaus.h>
+#include <mach/gpio.h>
+#include <mach/menelaus.h>
 
 #define DRIVER_NAME                     "menelaus"
 
diff --git a/drivers/ide/arm/ide_arm.c b/drivers/ide/arm/ide_arm.c
index 8a3bb23f8ae7..f728f2927b5a 100644
--- a/drivers/ide/arm/ide_arm.c
+++ b/drivers/ide/arm/ide_arm.c
@@ -16,7 +16,7 @@
 #define DRV_NAME "ide_arm"
 
 #ifdef CONFIG_ARCH_CLPS7500
-# include <asm/arch/hardware.h>
+# include <mach/hardware.h>
 #
 # define IDE_ARM_IO     (ISASLOT_IO + 0x1f0)
 # define IDE_ARM_IRQ    IRQ_ISA_14
diff --git a/drivers/input/keyboard/aaed2000_kbd.c b/drivers/input/keyboard/aaed2000_kbd.c
index 8a77bfcd05bc..18222a689a03 100644
--- a/drivers/input/keyboard/aaed2000_kbd.c
+++ b/drivers/input/keyboard/aaed2000_kbd.c
@@ -20,8 +20,8 @@
 #include <linux/module.h>
 #include <linux/slab.h>
 
-#include <asm/arch/hardware.h>
-#include <asm/arch/aaed2000.h>
+#include <mach/hardware.h>
+#include <mach/aaed2000.h>
 
 #define KB_ROWS                 12
 #define KB_COLS                 8
diff --git a/drivers/input/keyboard/corgikbd.c b/drivers/input/keyboard/corgikbd.c
index 1aa46ae12630..134e67bf6a90 100644
--- a/drivers/input/keyboard/corgikbd.c
+++ b/drivers/input/keyboard/corgikbd.c
@@ -20,10 +20,10 @@
 #include <linux/module.h>
 #include <linux/slab.h>
 
-#include <asm/arch/corgi.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-gpio.h>
+#include <mach/corgi.h>
+#include <mach/hardware.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-gpio.h>
 #include <asm/hardware/scoop.h>
 
 #define KB_ROWS                         8
diff --git a/drivers/input/keyboard/jornada720_kbd.c b/drivers/input/keyboard/jornada720_kbd.c
index 63774b53d75c..4e016d823069 100644
--- a/drivers/input/keyboard/jornada720_kbd.c
+++ b/drivers/input/keyboard/jornada720_kbd.c
@@ -24,8 +24,8 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 
-#include <asm/arch/jornada720.h>
-#include <asm/arch/hardware.h>
+#include <mach/jornada720.h>
+#include <mach/hardware.h>
 
 MODULE_AUTHOR("Kristoffer Ericson <Kristoffer.Ericson@gmail.com>");
 MODULE_DESCRIPTION("HP Jornada 710/720/728 keyboard driver");
diff --git a/drivers/input/keyboard/omap-keypad.c b/drivers/input/keyboard/omap-keypad.c
index b79648508324..dcea87a0bc56 100644
--- a/drivers/input/keyboard/omap-keypad.c
+++ b/drivers/input/keyboard/omap-keypad.c
@@ -34,13 +34,13 @@
 #include <linux/platform_device.h>
 #include <linux/mutex.h>
 #include <linux/errno.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/keypad.h>
-#include <asm/arch/menelaus.h>
+#include <mach/gpio.h>
+#include <mach/keypad.h>
+#include <mach/menelaus.h>
 #include <asm/irq.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
-#include <asm/arch/mux.h>
+#include <mach/mux.h>
 
 #undef NEW_BOARD_LEARNING_MODE
 
diff --git a/drivers/input/keyboard/pxa27x_keypad.c b/drivers/input/keyboard/pxa27x_keypad.c
index 8a925359d82e..6d30c6d334c3 100644
--- a/drivers/input/keyboard/pxa27x_keypad.c
+++ b/drivers/input/keyboard/pxa27x_keypad.c
@@ -29,8 +29,8 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa27x_keypad.h>
+#include <mach/hardware.h>
+#include <mach/pxa27x_keypad.h>
 
 /*
  * Keypad Controller registers
diff --git a/drivers/input/keyboard/spitzkbd.c b/drivers/input/keyboard/spitzkbd.c
index 1aa37181c40f..de67b8e0a799 100644
--- a/drivers/input/keyboard/spitzkbd.c
+++ b/drivers/input/keyboard/spitzkbd.c
@@ -20,10 +20,10 @@
 #include <linux/module.h>
 #include <linux/slab.h>
 
-#include <asm/arch/spitz.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-gpio.h>
+#include <mach/spitz.h>
+#include <mach/hardware.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-gpio.h>
 
 #define KB_ROWS                 7
 #define KB_COLS                 11
diff --git a/drivers/input/keyboard/tosakbd.c b/drivers/input/keyboard/tosakbd.c
index b12b7ee4b6aa..44cb50af3ce9 100644
--- a/drivers/input/keyboard/tosakbd.c
+++ b/drivers/input/keyboard/tosakbd.c
@@ -19,8 +19,8 @@
 #include <linux/delay.h>
 #include <linux/interrupt.h>
 
-#include <asm/arch/gpio.h>
-#include <asm/arch/tosa.h>
+#include <mach/gpio.h>
+#include <mach/tosa.h>
 
 #define KB_ROWMASK(r)           (1 << (r))
 #define SCANCODE(r, c)          (((r)<<4) + (c) + 1)
diff --git a/drivers/input/misc/ixp4xx-beeper.c b/drivers/input/misc/ixp4xx-beeper.c
index 7908f5c12b08..9946d73624b9 100644
--- a/drivers/input/misc/ixp4xx-beeper.c
+++ b/drivers/input/misc/ixp4xx-beeper.c
@@ -20,7 +20,7 @@
 #include <linux/delay.h>
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 MODULE_AUTHOR("Alessandro Zummo <a.zummo@towertech.it>");
 MODULE_DESCRIPTION("ixp4xx beeper driver");
diff --git a/drivers/input/mouse/rpcmouse.c b/drivers/input/mouse/rpcmouse.c
index 536e3be31b40..56c079ef5018 100644
--- a/drivers/input/mouse/rpcmouse.c
+++ b/drivers/input/mouse/rpcmouse.c
@@ -23,7 +23,7 @@
 #include <linux/init.h>
 #include <linux/input.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/io.h>
 #include <asm/hardware/iomd.h>
diff --git a/drivers/input/serio/rpckbd.c b/drivers/input/serio/rpckbd.c
index 22374d0d998f..7f36edd34f8b 100644
--- a/drivers/input/serio/rpckbd.c
+++ b/drivers/input/serio/rpckbd.c
@@ -35,7 +35,7 @@
 #include <linux/platform_device.h>
 
 #include <asm/irq.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/hardware/iomd.h>
 #include <asm/system.h>
diff --git a/drivers/input/touchscreen/corgi_ts.c b/drivers/input/touchscreen/corgi_ts.c
index d0e13fc4a88c..65202c9f63ff 100644
--- a/drivers/input/touchscreen/corgi_ts.c
+++ b/drivers/input/touchscreen/corgi_ts.c
@@ -19,10 +19,10 @@
 #include <linux/slab.h>
 #include <linux/irq.h>
 
-#include <asm/arch/sharpsl.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-gpio.h>
+#include <mach/sharpsl.h>
+#include <mach/hardware.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-gpio.h>
 
 
 #define PWR_MODE_ACTIVE         0
diff --git a/drivers/input/touchscreen/h3600_ts_input.c b/drivers/input/touchscreen/h3600_ts_input.c
index 4f86081dc7fc..4d3139e2099d 100644
--- a/drivers/input/touchscreen/h3600_ts_input.c
+++ b/drivers/input/touchscreen/h3600_ts_input.c
@@ -39,8 +39,8 @@
 #include <linux/delay.h>
 
 /* SA1100 serial defines */
-#include <asm/arch/hardware.h>
-#include <asm/arch/irqs.h>
+#include <mach/hardware.h>
+#include <mach/irqs.h>
 
 #define DRIVER_DESC     "H3600 touchscreen driver"
 
diff --git a/drivers/input/touchscreen/jornada720_ts.c b/drivers/input/touchscreen/jornada720_ts.c
index 19f40772c2fd..bf44f9d68342 100644
--- a/drivers/input/touchscreen/jornada720_ts.c
+++ b/drivers/input/touchscreen/jornada720_ts.c
@@ -19,8 +19,8 @@
 #include <linux/interrupt.h>
 #include <linux/module.h>
 
-#include <asm/arch/hardware.h>
-#include <asm/arch/jornada720.h>
+#include <mach/hardware.h>
+#include <mach/jornada720.h>
 
 MODULE_AUTHOR("Kristoffer Ericson <kristoffer.ericson@gmail.com>");
 MODULE_DESCRIPTION("HP Jornada 710/720/728 touchscreen driver");
diff --git a/drivers/input/touchscreen/mainstone-wm97xx.c b/drivers/input/touchscreen/mainstone-wm97xx.c
index 590a1379aa32..283f93a0cee2 100644
--- a/drivers/input/touchscreen/mainstone-wm97xx.c
+++ b/drivers/input/touchscreen/mainstone-wm97xx.c
@@ -33,7 +33,7 @@
 #include <linux/interrupt.h>
 #include <linux/wm97xx.h>
 #include <linux/io.h>
-#include <asm/arch/pxa-regs.h>
+#include <mach/pxa-regs.h>
 
 #define VERSION         "0.13"
 
diff --git a/drivers/leds/leds-ams-delta.c b/drivers/leds/leds-ams-delta.c
index c37bb0d5a0c5..32c98b2efa3f 100644
--- a/drivers/leds/leds-ams-delta.c
+++ b/drivers/leds/leds-ams-delta.c
@@ -12,7 +12,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/leds.h>
-#include <asm/arch/board-ams-delta.h>
+#include <mach/board-ams-delta.h>
 
 /*
  * Our context
diff --git a/drivers/leds/leds-cm-x270.c b/drivers/leds/leds-cm-x270.c
index accc7eddb788..836a43d776e6 100644
--- a/drivers/leds/leds-cm-x270.c
+++ b/drivers/leds/leds-cm-x270.c
@@ -18,8 +18,8 @@
 #include <linux/platform_device.h>
 #include <linux/leds.h>
 
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa-regs.h>
+#include <mach/hardware.h>
+#include <mach/pxa-regs.h>
 
 #define GPIO_RED_LED                    (93)
 #define GPIO_GREEN_LED                  (94)
diff --git a/drivers/leds/leds-corgi.c b/drivers/leds/leds-corgi.c
index e9d419ff784e..bc2dcd89f635 100644
--- a/drivers/leds/leds-corgi.c
+++ b/drivers/leds/leds-corgi.c
@@ -15,9 +15,9 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/leds.h>
-#include <asm/arch/corgi.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa-regs.h>
+#include <mach/corgi.h>
+#include <mach/hardware.h>
+#include <mach/pxa-regs.h>
 #include <asm/hardware/scoop.h>
 
 static void corgiled_amber_set(struct led_classdev *led_cdev,
diff --git a/drivers/leds/leds-fsg.c b/drivers/leds/leds-fsg.c
index a7421b8c47d8..be0e12144b8b 100644
--- a/drivers/leds/leds-fsg.c
+++ b/drivers/leds/leds-fsg.c
@@ -19,7 +19,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/leds.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 
 static short __iomem *latch_address;
diff --git a/drivers/leds/leds-h1940.c b/drivers/leds/leds-h1940.c
index 5227585e74bf..11b77a70bbcb 100644
--- a/drivers/leds/leds-h1940.c
+++ b/drivers/leds/leds-h1940.c
@@ -16,9 +16,9 @@
 #include <linux/string.h>
 #include <linux/ctype.h>
 #include <linux/leds.h>
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/h1940-latch.h>
+#include <mach/regs-gpio.h>
+#include <mach/hardware.h>
+#include <mach/h1940-latch.h>
 
 /*
  * Green led.
diff --git a/drivers/leds/leds-locomo.c b/drivers/leds/leds-locomo.c
index 17ebfe283e76..5d91362e3066 100644
--- a/drivers/leds/leds-locomo.c
+++ b/drivers/leds/leds-locomo.c
@@ -13,7 +13,7 @@
 #include <linux/device.h>
 #include <linux/leds.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/hardware/locomo.h>
 
 static void locomoled_brightness_set(struct led_classdev *led_cdev,
diff --git a/drivers/leds/leds-s3c24xx.c b/drivers/leds/leds-s3c24xx.c
index cb74c1890b36..25a07f2643ad 100644
--- a/drivers/leds/leds-s3c24xx.c
+++ b/drivers/leds/leds-s3c24xx.c
@@ -16,9 +16,9 @@
 #include <linux/platform_device.h>
 #include <linux/leds.h>
 
-#include <asm/arch/hardware.h>
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/leds-gpio.h>
+#include <mach/hardware.h>
+#include <mach/regs-gpio.h>
+#include <mach/leds-gpio.h>
 
 /* our context */
 
diff --git a/drivers/leds/leds-spitz.c b/drivers/leds/leds-spitz.c
index e75e8543bc5a..178831c64bfb 100644
--- a/drivers/leds/leds-spitz.c
+++ b/drivers/leds/leds-spitz.c
@@ -17,9 +17,9 @@
 #include <linux/leds.h>
 #include <asm/hardware/scoop.h>
 #include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/spitz.h>
+#include <mach/hardware.h>
+#include <mach/pxa-regs.h>
+#include <mach/spitz.h>
 
 static void spitzled_amber_set(struct led_classdev *led_cdev,
                                enum led_brightness value)
diff --git a/drivers/media/video/pxa_camera.c b/drivers/media/video/pxa_camera.c
index b15f82c49766..5e7ebca1968e 100644
--- a/drivers/media/video/pxa_camera.c
+++ b/drivers/media/video/pxa_camera.c
@@ -36,8 +36,8 @@
 #include <linux/videodev2.h>
 
 #include <asm/dma.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/camera.h>
+#include <mach/pxa-regs.h>
+#include <mach/camera.h>
 
 #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
 #define PXA_CAM_DRV_NAME "pxa27x-camera"
diff --git a/drivers/mfd/mcp-sa11x0.c b/drivers/mfd/mcp-sa11x0.c
index 6a2a2a8c3878..28380b20bc70 100644
--- a/drivers/mfd/mcp-sa11x0.c
+++ b/drivers/mfd/mcp-sa11x0.c
@@ -21,12 +21,12 @@
 #include <linux/platform_device.h>
 
 #include <asm/dma.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/system.h>
-#include <asm/arch/mcp.h>
+#include <mach/mcp.h>
 
-#include <asm/arch/assabet.h>
+#include <mach/assabet.h>
 
 #include "mcp.h"
 
diff --git a/drivers/mfd/ucb1x00-core.c b/drivers/mfd/ucb1x00-core.c
index a67541113e1d..a316f1b75933 100644
--- a/drivers/mfd/ucb1x00-core.c
+++ b/drivers/mfd/ucb1x00-core.c
@@ -26,7 +26,7 @@
 #include <linux/mutex.h>
 
 #include <asm/dma.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 #include "ucb1x00.h"
 
diff --git a/drivers/mfd/ucb1x00-ts.c b/drivers/mfd/ucb1x00-ts.c
index ad34e2d22524..44762ca86a8d 100644
--- a/drivers/mfd/ucb1x00-ts.c
+++ b/drivers/mfd/ucb1x00-ts.c
@@ -32,7 +32,7 @@
 #include <linux/kthread.h>
 
 #include <asm/dma.h>
-#include <asm/arch/collie.h>
+#include <mach/collie.h>
 #include <asm/mach-types.h>
 
 #include "ucb1x00.h"
diff --git a/drivers/mmc/host/at91_mci.c b/drivers/mmc/host/at91_mci.c
index f15e2064305c..6915f40ac8ab 100644
--- a/drivers/mmc/host/at91_mci.c
+++ b/drivers/mmc/host/at91_mci.c
@@ -73,9 +73,9 @@
 #include <asm/gpio.h>
 
 #include <asm/mach/mmc.h>
-#include <asm/arch/board.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/at91_mci.h>
+#include <mach/board.h>
+#include <mach/cpu.h>
+#include <mach/at91_mci.h>
 
 #define DRIVER_NAME "at91_mci"
 
diff --git a/drivers/mmc/host/imxmmc.c b/drivers/mmc/host/imxmmc.c
index f61406da65d2..2f0fcdb869b7 100644
--- a/drivers/mmc/host/imxmmc.c
+++ b/drivers/mmc/host/imxmmc.c
@@ -42,8 +42,8 @@
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/sizes.h>
-#include <asm/arch/mmc.h>
-#include <asm/arch/imx-dma.h>
+#include <mach/mmc.h>
+#include <mach/imx-dma.h>
 
 #include "imxmmc.h"
 
diff --git a/drivers/mmc/host/omap.c b/drivers/mmc/host/omap.c
index 1f587a239b02..c16028872bbb 100644
--- a/drivers/mmc/host/omap.c
+++ b/drivers/mmc/host/omap.c
@@ -30,12 +30,12 @@
 #include <asm/io.h>
 #include <asm/irq.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/mmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/dma.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/fpga.h>
+#include <mach/board.h>
+#include <mach/mmc.h>
+#include <mach/gpio.h>
+#include <mach/dma.h>
+#include <mach/mux.h>
+#include <mach/fpga.h>
 
 #define OMAP_MMC_REG_CMD        0x00
 #define OMAP_MMC_REG_ARGL       0x04
diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c
index a8e18fe53077..55093ad132ca 100644
--- a/drivers/mmc/host/pxamci.c
+++ b/drivers/mmc/host/pxamci.c
@@ -31,8 +31,8 @@
 #include <asm/io.h>
 #include <asm/sizes.h>
 
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/mmc.h>
+#include <mach/pxa-regs.h>
+#include <mach/mmc.h>
 
 #include "pxamci.h"
 
diff --git a/drivers/mmc/host/s3cmci.c b/drivers/mmc/host/s3cmci.c
index be550c26da68..7c994e1ae276 100644
--- a/drivers/mmc/host/s3cmci.c
+++ b/drivers/mmc/host/s3cmci.c
@@ -18,8 +18,8 @@
 
 #include <asm/dma.h>
 
-#include <asm/arch/regs-sdi.h>
-#include <asm/arch/regs-gpio.h>
+#include <mach/regs-sdi.h>
+#include <mach/regs-gpio.h>
 
 #include <asm/plat-s3c24xx/mci.h>
 
diff --git a/drivers/mtd/maps/autcpu12-nvram.c b/drivers/mtd/maps/autcpu12-nvram.c
index f199b16de2db..53664188fc47 100644
--- a/drivers/mtd/maps/autcpu12-nvram.c
+++ b/drivers/mtd/maps/autcpu12-nvram.c
@@ -25,8 +25,8 @@
 #include <linux/init.h>
 #include <asm/io.h>
 #include <asm/sizes.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/autcpu12.h>
+#include <mach/hardware.h>
+#include <mach/autcpu12.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/map.h>
 #include <linux/mtd/partitions.h>
diff --git a/drivers/mtd/maps/cdb89712.c b/drivers/mtd/maps/cdb89712.c
index cb507da0a87d..e5059aa3c724 100644
--- a/drivers/mtd/maps/cdb89712.c
+++ b/drivers/mtd/maps/cdb89712.c
@@ -9,7 +9,7 @@
 #include <linux/ioport.h>
 #include <linux/init.h>
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/map.h>
 #include <linux/mtd/partitions.h>
diff --git a/drivers/mtd/maps/ceiva.c b/drivers/mtd/maps/ceiva.c
index 468204ca238f..60e68bde0fea 100644
--- a/drivers/mtd/maps/ceiva.c
+++ b/drivers/mtd/maps/ceiva.c
@@ -25,7 +25,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/concat.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/io.h>
 #include <asm/sizes.h>
diff --git a/drivers/mtd/maps/h720x-flash.c b/drivers/mtd/maps/h720x-flash.c
index 873ff1523bbe..35fef655ccc4 100644
--- a/drivers/mtd/maps/h720x-flash.c
+++ b/drivers/mtd/maps/h720x-flash.c
@@ -16,7 +16,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/map.h>
 #include <linux/mtd/partitions.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 
 static struct mtd_info *mymtd;
diff --git a/drivers/mtd/maps/integrator-flash.c b/drivers/mtd/maps/integrator-flash.c
index d0282ceecc9f..7100ee3c7b01 100644
--- a/drivers/mtd/maps/integrator-flash.c
+++ b/drivers/mtd/maps/integrator-flash.c
@@ -37,7 +37,7 @@
 #include <linux/mtd/partitions.h>
 
 #include <asm/mach/flash.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/system.h>
 
diff --git a/drivers/mtd/maps/ipaq-flash.c b/drivers/mtd/maps/ipaq-flash.c
index 6447e8be9922..ed58f6a77bd9 100644
--- a/drivers/mtd/maps/ipaq-flash.c
+++ b/drivers/mtd/maps/ipaq-flash.c
@@ -24,8 +24,8 @@
 #include <linux/mtd/concat.h>
 #endif
 
-#include <asm/arch/hardware.h>
-#include <asm/arch/h3600.h>
+#include <mach/hardware.h>
+#include <mach/h3600.h>
 #include <asm/io.h>
 
 
diff --git a/drivers/mtd/maps/ixp2000.c b/drivers/mtd/maps/ixp2000.c
index 33b583e0d1bf..dcdb1f17577d 100644
--- a/drivers/mtd/maps/ixp2000.c
+++ b/drivers/mtd/maps/ixp2000.c
@@ -30,7 +30,7 @@
 #include <linux/mtd/partitions.h>
 
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach/flash.h>
 
 #include <linux/reboot.h>
diff --git a/drivers/mtd/maps/omap_nor.c b/drivers/mtd/maps/omap_nor.c
index 771e6806c58d..05f276af15da 100644
--- a/drivers/mtd/maps/omap_nor.c
+++ b/drivers/mtd/maps/omap_nor.c
@@ -43,9 +43,9 @@
 #include <linux/mtd/partitions.h>
 
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach/flash.h>
-#include <asm/arch/tc.h>
+#include <mach/tc.h>
 
 #ifdef CONFIG_MTD_PARTITIONS
 static const char *part_probes[] = { /* "RedBoot", */ "cmdlinepart", NULL };
diff --git a/drivers/mtd/maps/pxa2xx-flash.c b/drivers/mtd/maps/pxa2xx-flash.c
index fe070cc0a49f..771139c5bf87 100644
--- a/drivers/mtd/maps/pxa2xx-flash.c
+++ b/drivers/mtd/maps/pxa2xx-flash.c
@@ -19,7 +19,7 @@
 #include <linux/mtd/partitions.h>
 
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/cacheflush.h>
 
 #include <asm/mach/flash.h>
diff --git a/drivers/mtd/maps/sa1100-flash.c b/drivers/mtd/maps/sa1100-flash.c
index 7fc3204eee7e..7df6bbf0e4d9 100644
--- a/drivers/mtd/maps/sa1100-flash.c
+++ b/drivers/mtd/maps/sa1100-flash.c
@@ -18,7 +18,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/concat.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/sizes.h>
 #include <asm/mach/flash.h>
diff --git a/drivers/mtd/nand/ams-delta.c b/drivers/mtd/nand/ams-delta.c
index a0ba07c36ee9..26d42987971f 100644
--- a/drivers/mtd/nand/ams-delta.c
+++ b/drivers/mtd/nand/ams-delta.c
@@ -22,10 +22,10 @@
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/sizes.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/board-ams-delta.h>
+#include <mach/gpio.h>
+#include <mach/board-ams-delta.h>
 
 /*
  * MTD structure for E3 (Delta)
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 99aec46e2145..3387e0d5076b 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -32,8 +32,8 @@
 #include <linux/gpio.h>
 #include <linux/io.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/cpu.h>
+#include <mach/board.h>
+#include <mach/cpu.h>
 
 #ifdef CONFIG_MTD_NAND_ATMEL_ECC_HW
 #define hard_ecc        1
diff --git a/drivers/mtd/nand/autcpu12.c b/drivers/mtd/nand/autcpu12.c
index 553dd7e9b41c..7c95da1f612c 100644
--- a/drivers/mtd/nand/autcpu12.c
+++ b/drivers/mtd/nand/autcpu12.c
@@ -32,9 +32,9 @@
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/sizes.h>
-#include <asm/arch/autcpu12.h>
+#include <mach/autcpu12.h>
 
 /*
  * MTD structure for AUTCPU12 board
diff --git a/drivers/mtd/nand/cmx270_nand.c b/drivers/mtd/nand/cmx270_nand.c
index fc8529bedfdf..9eba3f04783a 100644
--- a/drivers/mtd/nand/cmx270_nand.c
+++ b/drivers/mtd/nand/cmx270_nand.c
@@ -26,8 +26,8 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa-regs.h>
+#include <mach/hardware.h>
+#include <mach/pxa-regs.h>
 
 #define GPIO_NAND_CS    (11)
 #define GPIO_NAND_RB    (89)
diff --git a/drivers/mtd/nand/edb7312.c b/drivers/mtd/nand/edb7312.c
index 387e4352903e..86366bfba9f8 100644
--- a/drivers/mtd/nand/edb7312.c
+++ b/drivers/mtd/nand/edb7312.c
@@ -23,7 +23,7 @@
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 #include <asm/io.h>
-#include <asm/arch/hardware.h>  /* for CLPS7111_VIRT_BASE */
+#include <mach/hardware.h>      /* for CLPS7111_VIRT_BASE */
 #include <asm/sizes.h>
 #include <asm/hardware/clps7111.h>
 
diff --git a/drivers/mtd/nand/h1910.c b/drivers/mtd/nand/h1910.c
index 9e59de501c2e..f8ce79b446ed 100644
--- a/drivers/mtd/nand/h1910.c
+++ b/drivers/mtd/nand/h1910.c
@@ -24,10 +24,10 @@
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 #include <asm/io.h>
-#include <asm/arch/hardware.h>  /* for CLPS7111_VIRT_BASE */
+#include <mach/hardware.h>      /* for CLPS7111_VIRT_BASE */
 #include <asm/sizes.h>
-#include <asm/arch/h1900-gpio.h>
-#include <asm/arch/ipaq.h>
+#include <mach/h1900-gpio.h>
+#include <mach/ipaq.h>
 
 /*
  * MTD structure for EDB7312 board
diff --git a/drivers/mtd/nand/orion_nand.c b/drivers/mtd/nand/orion_nand.c
index ee2ac3948cd8..64002488c6ee 100644
--- a/drivers/mtd/nand/orion_nand.c
+++ b/drivers/mtd/nand/orion_nand.c
@@ -18,7 +18,7 @@
 #include <linux/mtd/partitions.h>
 #include <asm/io.h>
 #include <asm/sizes.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/plat-orion/orion_nand.h>
 
 #ifdef CONFIG_MTD_CMDLINE_PARTS
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index fe2bc7e42119..a64ad15b8fdd 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -22,8 +22,8 @@
 #include <linux/irq.h>
 #include <asm/dma.h>
 
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa3xx_nand.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa3xx_nand.h>
 
 #define CHIP_DELAY_TIMEOUT      (2 * HZ/10)
 
diff --git a/drivers/mtd/nand/sharpsl.c b/drivers/mtd/nand/sharpsl.c
index 18d2cd395b24..30a518e211bd 100644
--- a/drivers/mtd/nand/sharpsl.c
+++ b/drivers/mtd/nand/sharpsl.c
@@ -21,7 +21,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/interrupt.h>
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 
 static void __iomem *sharpsl_io_base;
diff --git a/drivers/mtd/nand/ts7250.c b/drivers/mtd/nand/ts7250.c
index 807a72752eeb..2c410a011317 100644
--- a/drivers/mtd/nand/ts7250.c
+++ b/drivers/mtd/nand/ts7250.c
@@ -25,7 +25,7 @@
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/sizes.h>
 #include <asm/mach-types.h>
 
diff --git a/drivers/net/arm/am79c961a.c b/drivers/net/arm/am79c961a.c
index 0ece4f9f1fa1..aa4a5246be53 100644
--- a/drivers/net/arm/am79c961a.c
+++ b/drivers/net/arm/am79c961a.c
@@ -28,7 +28,7 @@
 #include <linux/bitops.h>
 #include <linux/platform_device.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/system.h>
 
diff --git a/drivers/net/arm/at91_ether.c b/drivers/net/arm/at91_ether.c
index ffae266e2d7f..0fa53464efb2 100644
--- a/drivers/net/arm/at91_ether.c
+++ b/drivers/net/arm/at91_ether.c
@@ -32,9 +32,9 @@
 #include <asm/uaccess.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/at91rm9200_emac.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/board.h>
+#include <mach/at91rm9200_emac.h>
+#include <mach/gpio.h>
+#include <mach/board.h>
 
 #include "at91_ether.h"
 
diff --git a/drivers/net/arm/ep93xx_eth.c b/drivers/net/arm/ep93xx_eth.c
index 18d3eeb7eab2..1267444d79da 100644
--- a/drivers/net/arm/ep93xx_eth.c
+++ b/drivers/net/arm/ep93xx_eth.c
@@ -20,8 +20,8 @@
 #include <linux/moduleparam.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
-#include <asm/arch/ep93xx-regs.h>
-#include <asm/arch/platform.h>
+#include <mach/ep93xx-regs.h>
+#include <mach/platform.h>
 #include <asm/io.h>
 
 #define DRV_MODULE_NAME         "ep93xx-eth"
diff --git a/drivers/net/arm/ixp4xx_eth.c b/drivers/net/arm/ixp4xx_eth.c
index 9b777d9433cd..020771bfb603 100644
--- a/drivers/net/arm/ixp4xx_eth.c
+++ b/drivers/net/arm/ixp4xx_eth.c
@@ -32,8 +32,8 @@
 #include <linux/kernel.h>
 #include <linux/mii.h>
 #include <linux/platform_device.h>
-#include <asm/arch/npe.h>
-#include <asm/arch/qmgr.h>
+#include <mach/npe.h>
+#include <mach/qmgr.h>
 
 #define DEBUG_QUEUES            0
 #define DEBUG_DESC              0
diff --git a/drivers/net/cs89x0.c b/drivers/net/cs89x0.c
index fba87abe78ee..ea6144a9565e 100644
--- a/drivers/net/cs89x0.c
+++ b/drivers/net/cs89x0.c
@@ -189,7 +189,7 @@ static unsigned int netcard_portlist[] __used __initdata = {IXDP2X01_CS8900_VIRT
 static unsigned int cs8900_irq_map[] = {IRQ_IXDP2X01_CS8900, 0, 0, 0};
 #elif defined(CONFIG_ARCH_PNX010X)
 #include <asm/irq.h>
-#include <asm/arch/gpio.h>
+#include <mach/gpio.h>
 #define CIRRUS_DEFAULT_BASE     IO_ADDRESS(EXT_STATIC2_s0_BASE + 0x200000)      /* = Physical address 0x48200000 */
 #define CIRRUS_DEFAULT_IRQ      VH_INTC_INT_NUM_CASCADED_INTERRUPT_1 /* Event inputs bank 1 - ID 35/bit 3 */
 static unsigned int netcard_portlist[] __used __initdata = {CIRRUS_DEFAULT_BASE, 0};
diff --git a/drivers/net/irda/ep7211-sir.c b/drivers/net/irda/ep7211-sir.c
index 2f89d47a37c5..f83c5b881d2d 100644
--- a/drivers/net/irda/ep7211-sir.c
+++ b/drivers/net/irda/ep7211-sir.c
@@ -14,7 +14,7 @@
 #include <net/irda/irda_device.h>
 
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 #include "sir-dev.h"
 
diff --git a/drivers/net/irda/pxaficp_ir.c b/drivers/net/irda/pxaficp_ir.c
index f76b0b6c277d..4aa61a1a3d55 100644
--- a/drivers/net/irda/pxaficp_ir.c
+++ b/drivers/net/irda/pxaficp_ir.c
@@ -23,8 +23,8 @@
 #include <net/irda/irda_device.h>
 
 #include <asm/dma.h>
-#include <asm/arch/irda.h>
-#include <asm/arch/pxa-regs.h>
+#include <mach/irda.h>
+#include <mach/pxa-regs.h>
 
 #define IrSR_RXPL_NEG_IS_ZERO (1<<4)
 #define IrSR_RXPL_POS_IS_ZERO 0x0
diff --git a/drivers/net/irda/sa1100_ir.c b/drivers/net/irda/sa1100_ir.c
index d16594a5dbc7..a95188948de7 100644
--- a/drivers/net/irda/sa1100_ir.c
+++ b/drivers/net/irda/sa1100_ir.c
@@ -37,7 +37,7 @@
 
 #include <asm/irq.h>
 #include <asm/dma.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach/irda.h>
 
 static int power_level = 3;
diff --git a/drivers/net/ixp2000/ixp2400-msf.c b/drivers/net/ixp2000/ixp2400-msf.c
index 65267c973109..f5ffd7e05d26 100644
--- a/drivers/net/ixp2000/ixp2400-msf.c
+++ b/drivers/net/ixp2000/ixp2400-msf.c
@@ -13,8 +13,8 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/ixp2000-regs.h>
+#include <mach/hardware.h>
+#include <mach/ixp2000-regs.h>
 #include <asm/delay.h>
 #include <asm/io.h>
 #include "ixp2400-msf.h"
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index daba82bbcb56..84c77f1f9a5c 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -21,8 +21,8 @@
 #include <linux/platform_device.h>
 #include <linux/phy.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/cpu.h>
+#include <mach/board.h>
+#include <mach/cpu.h>
 
 #include "macb.h"
 
diff --git a/drivers/net/netx-eth.c b/drivers/net/netx-eth.c
index f2655ce526b9..3f9af759cb90 100644
--- a/drivers/net/netx-eth.c
+++ b/drivers/net/netx-eth.c
@@ -29,11 +29,11 @@
 #include <linux/mii.h>
 
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/netx-regs.h>
-#include <asm/arch/pfifo.h>
-#include <asm/arch/xc.h>
-#include <asm/arch/eth.h>
+#include <mach/hardware.h>
+#include <mach/netx-regs.h>
+#include <mach/pfifo.h>
+#include <mach/xc.h>
+#include <mach/eth.h>
 
 /* XC Fifo Offsets */
 #define EMPTY_PTR_FIFO(xcno)    (0 + ((xcno) << 3))     /* Index of the empty pointer FIFO */
diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h
index 76c17c28fab4..2abfc2845198 100644
--- a/drivers/net/smc911x.h
+++ b/drivers/net/smc911x.h
@@ -222,7 +222,7 @@ static inline void SMC_outsl(struct smc911x_local *lp, int reg,
  */
 #include <linux/dma-mapping.h>
 #include <asm/dma.h>
-#include <asm/arch/pxa-regs.h>
+#include <mach/pxa-regs.h>
 
 static dma_addr_t rx_dmabuf, tx_dmabuf;
 static int rx_dmalen, tx_dmalen;
diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h
index 22209b6f1405..997e7f1d5c6e 100644
--- a/drivers/net/smc91x.h
+++ b/drivers/net/smc91x.h
@@ -187,7 +187,7 @@ static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg)
 
 #elif defined(CONFIG_SA1100_ASSABET)
 
-#include <asm/arch/neponset.h>
+#include <mach/neponset.h>
 
 /* We can only do 8-bit reads and writes in the static memory space. */
 #define SMC_CAN_USE_8BIT        1
@@ -339,7 +339,7 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg)
  * IOBARRIER on entry to their ISR.
  */
 
-#include <asm/arch/constants.h> /* IOBARRIER_VIRT */
+#include <mach/constants.h>     /* IOBARRIER_VIRT */
 
 #define SMC_CAN_USE_8BIT        0
 #define SMC_CAN_USE_16BIT       1
@@ -525,7 +525,7 @@ struct smc_local {
  */
 #include <linux/dma-mapping.h>
 #include <asm/dma.h>
-#include <asm/arch/pxa-regs.h>
+#include <mach/pxa-regs.h>
 
 #ifdef SMC_insl
 #undef SMC_insl
diff --git a/drivers/pcmcia/at91_cf.c b/drivers/pcmcia/at91_cf.c
index ab6b4bee3187..a0ffb8ebfe00 100644
--- a/drivers/pcmcia/at91_cf.c
+++ b/drivers/pcmcia/at91_cf.c
@@ -18,13 +18,13 @@
 
 #include <pcmcia/ss.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/sizes.h>
 #include <asm/gpio.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/at91rm9200_mc.h>
+#include <mach/board.h>
+#include <mach/at91rm9200_mc.h>
 
 
 /*
diff --git a/drivers/pcmcia/omap_cf.c b/drivers/pcmcia/omap_cf.c
index 36cf9bcf3ac1..f3736398900e 100644
--- a/drivers/pcmcia/omap_cf.c
+++ b/drivers/pcmcia/omap_cf.c
@@ -19,12 +19,12 @@
 
 #include <pcmcia/ss.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/sizes.h>
 
-#include <asm/arch/mux.h>
-#include <asm/arch/tc.h>
+#include <mach/mux.h>
+#include <mach/tc.h>
 
 
 /* NOTE:  don't expect this to support many I/O cards.  The 16xx chips have
diff --git a/drivers/pcmcia/pxa2xx_base.c b/drivers/pcmcia/pxa2xx_base.c
index ff5e3f324f3e..1b07af5a2ed3 100644
--- a/drivers/pcmcia/pxa2xx_base.c
+++ b/drivers/pcmcia/pxa2xx_base.c
@@ -24,12 +24,12 @@
 #include <linux/spinlock.h>
 #include <linux/platform_device.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/system.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-regs.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-regs.h>
 
 #include <pcmcia/cs_types.h>
 #include <pcmcia/ss.h>
diff --git a/drivers/pcmcia/pxa2xx_cm_x270.c b/drivers/pcmcia/pxa2xx_cm_x270.c
index bb95db7d2b76..bcff5cfed051 100644
--- a/drivers/pcmcia/pxa2xx_cm_x270.c
+++ b/drivers/pcmcia/pxa2xx_cm_x270.c
@@ -16,7 +16,7 @@
 #include <linux/gpio.h>
 
 #include <asm/mach-types.h>
-#include <asm/arch/pxa-regs.h>
+#include <mach/pxa-regs.h>
 
 #include "soc_common.h"
 
diff --git a/drivers/pcmcia/pxa2xx_lubbock.c b/drivers/pcmcia/pxa2xx_lubbock.c
index 64f709d0113d..37ec55df086e 100644
--- a/drivers/pcmcia/pxa2xx_lubbock.c
+++ b/drivers/pcmcia/pxa2xx_lubbock.c
@@ -21,11 +21,11 @@
 #include <linux/init.h>
 #include <linux/delay.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/hardware/sa1111.h>
 #include <asm/mach-types.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/lubbock.h>
+#include <mach/pxa-regs.h>
+#include <mach/lubbock.h>
 
 #include "sa1111_generic.h"
 
diff --git a/drivers/pcmcia/pxa2xx_mainstone.c b/drivers/pcmcia/pxa2xx_mainstone.c
index b0dcda481522..877001db4916 100644
--- a/drivers/pcmcia/pxa2xx_mainstone.c
+++ b/drivers/pcmcia/pxa2xx_mainstone.c
@@ -21,12 +21,12 @@
 
 #include <pcmcia/ss.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
 
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/mainstone.h>
+#include <mach/pxa-regs.h>
+#include <mach/mainstone.h>
 
 #include "soc_common.h"
 
diff --git a/drivers/pcmcia/pxa2xx_palmtx.c b/drivers/pcmcia/pxa2xx_palmtx.c
index 4abde190c1f5..a8771ffc61e8 100644
--- a/drivers/pcmcia/pxa2xx_palmtx.c
+++ b/drivers/pcmcia/pxa2xx_palmtx.c
@@ -16,8 +16,8 @@
 
 #include <asm/mach-types.h>
 
-#include <asm/arch/gpio.h>
-#include <asm/arch/palmtx.h>
+#include <mach/gpio.h>
+#include <mach/palmtx.h>
 
 #include "soc_common.h"
 
diff --git a/drivers/pcmcia/pxa2xx_sharpsl.c b/drivers/pcmcia/pxa2xx_sharpsl.c
index 58395bff9a72..1cd02f5a23a0 100644
--- a/drivers/pcmcia/pxa2xx_sharpsl.c
+++ b/drivers/pcmcia/pxa2xx_sharpsl.c
@@ -19,7 +19,7 @@
 #include <linux/platform_device.h>
 
 #include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/hardware/scoop.h>
 
diff --git a/drivers/pcmcia/sa1100_assabet.c b/drivers/pcmcia/sa1100_assabet.c
index 71fbb62804b1..f424146a2bc9 100644
--- a/drivers/pcmcia/sa1100_assabet.c
+++ b/drivers/pcmcia/sa1100_assabet.c
@@ -11,11 +11,11 @@
 #include <linux/device.h>
 #include <linux/init.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
 #include <asm/signal.h>
-#include <asm/arch/assabet.h>
+#include <mach/assabet.h>
 
 #include "sa1100_generic.h"
 
diff --git a/drivers/pcmcia/sa1100_badge4.c b/drivers/pcmcia/sa1100_badge4.c
index a34279a6788b..1ca9737ea79e 100644
--- a/drivers/pcmcia/sa1100_badge4.c
+++ b/drivers/pcmcia/sa1100_badge4.c
@@ -18,9 +18,9 @@
 #include <linux/errno.h>
 #include <linux/init.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
-#include <asm/arch/badge4.h>
+#include <mach/badge4.h>
 #include <asm/hardware/sa1111.h>
 
 #include "sa1111_generic.h"
diff --git a/drivers/pcmcia/sa1100_cerf.c b/drivers/pcmcia/sa1100_cerf.c
index bd843bffde59..63e6bc431a0d 100644
--- a/drivers/pcmcia/sa1100_cerf.c
+++ b/drivers/pcmcia/sa1100_cerf.c
@@ -11,10 +11,10 @@
 #include <linux/init.h>
 #include <linux/delay.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
-#include <asm/arch/cerf.h>
+#include <mach/cerf.h>
 #include "sa1100_generic.h"
 
 #define CERF_SOCKET     1
diff --git a/drivers/pcmcia/sa1100_h3600.c b/drivers/pcmcia/sa1100_h3600.c
index 9017b1302cc7..6de4e1b41d60 100644
--- a/drivers/pcmcia/sa1100_h3600.c
+++ b/drivers/pcmcia/sa1100_h3600.c
@@ -11,10 +11,10 @@
 #include <linux/init.h>
 #include <linux/delay.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
-#include <asm/arch/h3600.h>
+#include <mach/h3600.h>
 
 #include "sa1100_generic.h"
 
diff --git a/drivers/pcmcia/sa1100_jornada720.c b/drivers/pcmcia/sa1100_jornada720.c
index 15c31dbb0f3c..57ca085473d5 100644
--- a/drivers/pcmcia/sa1100_jornada720.c
+++ b/drivers/pcmcia/sa1100_jornada720.c
@@ -10,7 +10,7 @@
 #include <linux/errno.h>
 #include <linux/init.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/hardware/sa1111.h>
 #include <asm/mach-types.h>
 
diff --git a/drivers/pcmcia/sa1100_neponset.c b/drivers/pcmcia/sa1100_neponset.c
index ace391b69e96..4c41e86ccff9 100644
--- a/drivers/pcmcia/sa1100_neponset.c
+++ b/drivers/pcmcia/sa1100_neponset.c
@@ -9,9 +9,9 @@
 #include <linux/errno.h>
 #include <linux/init.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
-#include <asm/arch/neponset.h>
+#include <mach/neponset.h>
 #include <asm/hardware/sa1111.h>
 
 #include "sa1111_generic.h"
diff --git a/drivers/pcmcia/sa1100_shannon.c b/drivers/pcmcia/sa1100_shannon.c
index 16b04270508a..46d8c1977c2a 100644
--- a/drivers/pcmcia/sa1100_shannon.c
+++ b/drivers/pcmcia/sa1100_shannon.c
@@ -9,9 +9,9 @@
 #include <linux/device.h>
 #include <linux/init.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
-#include <asm/arch/shannon.h>
+#include <mach/shannon.h>
 #include <asm/irq.h>
 #include "sa1100_generic.h"
 
diff --git a/drivers/pcmcia/sa1100_simpad.c b/drivers/pcmcia/sa1100_simpad.c
index 6e6e98654381..33a08ae09fdf 100644
--- a/drivers/pcmcia/sa1100_simpad.c
+++ b/drivers/pcmcia/sa1100_simpad.c
@@ -9,10 +9,10 @@
 #include <linux/device.h>
 #include <linux/init.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
-#include <asm/arch/simpad.h>
+#include <mach/simpad.h>
 #include "sa1100_generic.h"
  
 extern long get_cs3_shadow(void);
diff --git a/drivers/pcmcia/sa1111_generic.c b/drivers/pcmcia/sa1111_generic.c
index 432c0610582a..6924d0ea8d32 100644
--- a/drivers/pcmcia/sa1111_generic.c
+++ b/drivers/pcmcia/sa1111_generic.c
@@ -14,7 +14,7 @@
 
 #include <pcmcia/ss.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/hardware/sa1111.h>
 #include <asm/io.h>
 #include <asm/irq.h>
diff --git a/drivers/pcmcia/sa11xx_base.c b/drivers/pcmcia/sa11xx_base.c
index 7d48201ae102..7cb1273202cc 100644
--- a/drivers/pcmcia/sa11xx_base.c
+++ b/drivers/pcmcia/sa11xx_base.c
@@ -37,7 +37,7 @@
 #include <linux/kernel.h>
 #include <linux/spinlock.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/system.h>
diff --git a/drivers/pcmcia/soc_common.c b/drivers/pcmcia/soc_common.c
index 95dff38e85f5..c48f3f69bdaf 100644
--- a/drivers/pcmcia/soc_common.c
+++ b/drivers/pcmcia/soc_common.c
@@ -43,7 +43,7 @@
 #include <linux/spinlock.h>
 #include <linux/cpufreq.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/system.h>
 
@@ -51,7 +51,7 @@
 
 /* FIXME: platform dependent resource declaration has to move out of this file */
 #ifdef CONFIG_ARCH_PXA
-#include <asm/arch/pxa-regs.h>
+#include <mach/pxa-regs.h>
 #endif
 
 #ifdef DEBUG
diff --git a/drivers/power/palmtx_battery.c b/drivers/power/palmtx_battery.c
index 244bb273a637..7035bfa41c62 100644
--- a/drivers/power/palmtx_battery.c
+++ b/drivers/power/palmtx_battery.c
@@ -22,7 +22,7 @@
 #include <linux/gpio.h>
 
 #include <asm/mach-types.h>
-#include <asm/arch/palmtx.h>
+#include <mach/palmtx.h>
 
 static DEFINE_MUTEX(bat_lock);
 static struct work_struct bat_work;
diff --git a/drivers/power/tosa_battery.c b/drivers/power/tosa_battery.c
index bf664fbd6610..2eab35aab311 100644
--- a/drivers/power/tosa_battery.c
+++ b/drivers/power/tosa_battery.c
@@ -19,7 +19,7 @@
 #include <linux/gpio.h>
 
 #include <asm/mach-types.h>
-#include <asm/arch/tosa.h>
+#include <mach/tosa.h>
 
 static DEFINE_MUTEX(bat_lock); /* protects gpio pins */
 static struct work_struct bat_work;
diff --git a/drivers/rtc/rtc-at91rm9200.c b/drivers/rtc/rtc-at91rm9200.c
index cd32d05db773..4e888cc8be5b 100644
--- a/drivers/rtc/rtc-at91rm9200.c
+++ b/drivers/rtc/rtc-at91rm9200.c
@@ -29,7 +29,7 @@
 #include <linux/completion.h>
 
 #include <asm/uaccess.h>
-#include <asm/arch/at91_rtc.h>
+#include <mach/at91_rtc.h>
 
 
 #define AT91_RTC_FREQ           1
diff --git a/drivers/rtc/rtc-at91sam9.c b/drivers/rtc/rtc-at91sam9.c
index f0246ef413a4..2133f37906f2 100644
--- a/drivers/rtc/rtc-at91sam9.c
+++ b/drivers/rtc/rtc-at91sam9.c
@@ -19,8 +19,8 @@
 #include <linux/interrupt.h>
 #include <linux/ioctl.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/at91_rtt.h>
+#include <mach/board.h>
+#include <mach/at91_rtt.h>
 
 
 /*
diff --git a/drivers/rtc/rtc-ep93xx.c b/drivers/rtc/rtc-ep93xx.c
index 9ab53ec63138..36e4ac0bd69c 100644
--- a/drivers/rtc/rtc-ep93xx.c
+++ b/drivers/rtc/rtc-ep93xx.c
@@ -12,7 +12,7 @@
 #include <linux/module.h>
 #include <linux/rtc.h>
 #include <linux/platform_device.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 #define EP93XX_RTC_REG(x)       (EP93XX_RTC_BASE + (x))
 #define EP93XX_RTC_DATA         EP93XX_RTC_REG(0x0000)
diff --git a/drivers/rtc/rtc-s3c.c b/drivers/rtc/rtc-s3c.c
index 8054112fc041..e7d19b6c265a 100644
--- a/drivers/rtc/rtc-s3c.c
+++ b/drivers/rtc/rtc-s3c.c
@@ -22,7 +22,7 @@
 #include <linux/clk.h>
 #include <linux/log2.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/uaccess.h>
 #include <asm/io.h>
 #include <asm/irq.h>
diff --git a/drivers/rtc/rtc-sa1100.c b/drivers/rtc/rtc-sa1100.c
index a0982d67e085..66a9bb85bbe8 100644
--- a/drivers/rtc/rtc-sa1100.c
+++ b/drivers/rtc/rtc-sa1100.c
@@ -31,11 +31,11 @@
 #include <linux/pm.h>
 #include <linux/bitops.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 
 #ifdef CONFIG_ARCH_PXA
-#include <asm/arch/pxa-regs.h>
+#include <mach/pxa-regs.h>
 #endif
 
 #define TIMER_FREQ              CLOCK_TICK_RATE
diff --git a/drivers/scsi/arm/acornscsi-io.S b/drivers/scsi/arm/acornscsi-io.S
index 075df199cdec..22171b2110a8 100644
--- a/drivers/scsi/arm/acornscsi-io.S
+++ b/drivers/scsi/arm/acornscsi-io.S
@@ -8,7 +8,7 @@
 #include <linux/linkage.h>
 
 #include <asm/assembler.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 #if defined(__APCS_32__)
 #define LOADREGS(t,r,l...)      ldm##t  r, l
diff --git a/drivers/serial/21285.c b/drivers/serial/21285.c
index 73d7773c8416..f31c6698419c 100644
--- a/drivers/serial/21285.c
+++ b/drivers/serial/21285.c
@@ -19,7 +19,7 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 #include <asm/hardware/dec21285.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 #define BAUD_BASE               (mem_fclk_21285/64)
 
diff --git a/drivers/serial/atmel_serial.c b/drivers/serial/atmel_serial.c
index 1fee12c1f4f8..3a6da80b081c 100644
--- a/drivers/serial/atmel_serial.c
+++ b/drivers/serial/atmel_serial.c
@@ -42,11 +42,11 @@
 #include <asm/io.h>
 
 #include <asm/mach/serial_at91.h>
-#include <asm/arch/board.h>
+#include <mach/board.h>
 
 #ifdef CONFIG_ARM
-#include <asm/arch/cpu.h>
-#include <asm/arch/gpio.h>
+#include <mach/cpu.h>
+#include <mach/gpio.h>
 #endif
 
 #define PDC_BUFFER_SIZE         512
diff --git a/drivers/serial/clps711x.c b/drivers/serial/clps711x.c
index 44d5d267ca17..459f3420a429 100644
--- a/drivers/serial/clps711x.c
+++ b/drivers/serial/clps711x.c
@@ -39,7 +39,7 @@
 #include <linux/serial_core.h>
 #include <linux/serial.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/hardware/clps7111.h>
diff --git a/drivers/serial/imx.c b/drivers/serial/imx.c
index db3a2df5e5c9..6a29f9330a73 100644
--- a/drivers/serial/imx.c
+++ b/drivers/serial/imx.c
@@ -44,8 +44,8 @@
 
 #include <asm/io.h>
 #include <asm/irq.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/imx-uart.h>
+#include <mach/hardware.h>
+#include <mach/imx-uart.h>
 
 /* Register definitions */
 #define URXD0 0x0  /* Receiver Register */
diff --git a/drivers/serial/netx-serial.c b/drivers/serial/netx-serial.c
index edbb85a2cc5b..3f489329e8d3 100644
--- a/drivers/serial/netx-serial.c
+++ b/drivers/serial/netx-serial.c
@@ -35,8 +35,8 @@
 
 #include <asm/io.h>
 #include <asm/irq.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/netx-regs.h>
+#include <mach/hardware.h>
+#include <mach/netx-regs.h>
 
 /* We've been assigned a range on the "Low-density serial ports" major */
 #define SERIAL_NX_MAJOR 204
diff --git a/drivers/serial/pxa.c b/drivers/serial/pxa.c
index 033767bed049..f7a0d37c4221 100644
--- a/drivers/serial/pxa.c
+++ b/drivers/serial/pxa.c
@@ -45,9 +45,9 @@
 #include <linux/clk.h>
 
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/arch/pxa-regs.h>
+#include <mach/pxa-regs.h>
 
 
 struct uart_pxa_port {
diff --git a/drivers/serial/s3c2400.c b/drivers/serial/s3c2400.c
index 525130d67f97..c8b4266ac35f 100644
--- a/drivers/serial/s3c2400.c
+++ b/drivers/serial/s3c2400.c
@@ -17,10 +17,10 @@
 
 #include <asm/irq.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 #include <asm/plat-s3c/regs-serial.h>
-#include <asm/arch/regs-gpio.h>
+#include <mach/regs-gpio.h>
 
 #include "samsung.h"
 
diff --git a/drivers/serial/s3c2410.c b/drivers/serial/s3c2410.c
index f9630c6e6f7e..40a2531b5541 100644
--- a/drivers/serial/s3c2410.c
+++ b/drivers/serial/s3c2410.c
@@ -19,10 +19,10 @@
 #include <linux/serial.h>
 
 #include <asm/irq.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 #include <asm/plat-s3c/regs-serial.h>
-#include <asm/arch/regs-gpio.h>
+#include <mach/regs-gpio.h>
 
 #include "samsung.h"
 
diff --git a/drivers/serial/s3c2412.c b/drivers/serial/s3c2412.c
index b4c0bb5a0415..d0170319c729 100644
--- a/drivers/serial/s3c2412.c
+++ b/drivers/serial/s3c2412.c
@@ -19,10 +19,10 @@
 #include <linux/serial.h>
 
 #include <asm/irq.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 #include <asm/plat-s3c/regs-serial.h>
-#include <asm/arch/regs-gpio.h>
+#include <mach/regs-gpio.h>
 
 #include "samsung.h"
 
diff --git a/drivers/serial/s3c2440.c b/drivers/serial/s3c2440.c
index ea34faa2f653..d4a2b17b2498 100644
--- a/drivers/serial/s3c2440.c
+++ b/drivers/serial/s3c2440.c
@@ -19,10 +19,10 @@
 #include <linux/serial.h>
 
 #include <asm/irq.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 #include <asm/plat-s3c/regs-serial.h>
-#include <asm/arch/regs-gpio.h>
+#include <mach/regs-gpio.h>
 
 #include "samsung.h"
 
diff --git a/drivers/serial/sa1100.c b/drivers/serial/sa1100.c
index 6c37a58652c2..b24a25ea6bc5 100644
--- a/drivers/serial/sa1100.c
+++ b/drivers/serial/sa1100.c
@@ -39,7 +39,7 @@
 
 #include <asm/io.h>
 #include <asm/irq.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach/serial_sa1100.h>
 
 /* We've been assigned a range on the "Low-density serial ports" major */
diff --git a/drivers/serial/samsung.c b/drivers/serial/samsung.c
index 5b964d4bc04d..5a88b3f9fe9b 100644
--- a/drivers/serial/samsung.c
+++ b/drivers/serial/samsung.c
@@ -45,10 +45,10 @@
 
 #include <asm/irq.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 #include <asm/plat-s3c/regs-serial.h>
-#include <asm/arch/regs-gpio.h>
+#include <mach/regs-gpio.h>
 
 #include "samsung.h"
 
diff --git a/drivers/serial/serial_ks8695.c b/drivers/serial/serial_ks8695.c
index 0edbc5dd378b..b9cbfc87f616 100644
--- a/drivers/serial/serial_ks8695.c
+++ b/drivers/serial/serial_ks8695.c
@@ -26,8 +26,8 @@
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/regs-uart.h>
-#include <asm/arch/regs-irq.h>
+#include <mach/regs-uart.h>
+#include <mach/regs-irq.h>
 
 #if defined(CONFIG_SERIAL_KS8695_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
 #define SUPPORT_SYSRQ
diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c
index 95190c619c10..02f9320f3efc 100644
--- a/drivers/spi/atmel_spi.c
+++ b/drivers/spi/atmel_spi.c
@@ -20,9 +20,9 @@
 #include <linux/spi/spi.h>
 
 #include <asm/io.h>
-#include <asm/arch/board.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/cpu.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/cpu.h>
 
 #include "atmel_spi.h"
 
diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
index f6f987bb71ca..9d2186fd74aa 100644
--- a/drivers/spi/omap2_mcspi.c
+++ b/drivers/spi/omap2_mcspi.c
@@ -35,8 +35,8 @@
 
 #include <linux/spi/spi.h>
 
-#include <asm/arch/dma.h>
-#include <asm/arch/clock.h>
+#include <mach/dma.h>
+#include <mach/clock.h>
 
 
 #define OMAP2_MCSPI_MAX_FREQ            48000000
diff --git a/drivers/spi/omap_uwire.c b/drivers/spi/omap_uwire.c
index e7588e112ec6..5515eb97d7c5 100644
--- a/drivers/spi/omap_uwire.c
+++ b/drivers/spi/omap_uwire.c
@@ -47,12 +47,12 @@
 
 #include <asm/system.h>
 #include <asm/irq.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/mux.h>
-#include <asm/arch/omap730.h>   /* OMAP730_IO_CONF registers */
+#include <mach/mux.h>
+#include <mach/omap730.h>       /* OMAP730_IO_CONF registers */
 
 
 /* FIXME address is now a platform device resource,
diff --git a/drivers/spi/pxa2xx_spi.c b/drivers/spi/pxa2xx_spi.c
index 70786f57cdcf..34c7c9875681 100644
--- a/drivers/spi/pxa2xx_spi.c
+++ b/drivers/spi/pxa2xx_spi.c
@@ -34,11 +34,11 @@
 #include <asm/delay.h>
 #include <asm/dma.h>
 
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/regs-ssp.h>
-#include <asm/arch/ssp.h>
-#include <asm/arch/pxa2xx_spi.h>
+#include <mach/hardware.h>
+#include <mach/pxa-regs.h>
+#include <mach/regs-ssp.h>
+#include <mach/ssp.h>
+#include <mach/pxa2xx_spi.h>
 
 MODULE_AUTHOR("Stephen Street");
 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
diff --git a/drivers/spi/spi_imx.c b/drivers/spi/spi_imx.c
index 8d7c902c87c5..61ba147e384d 100644
--- a/drivers/spi/spi_imx.c
+++ b/drivers/spi/spi_imx.c
@@ -35,9 +35,9 @@
 #include <asm/irq.h>
 #include <asm/delay.h>
 
-#include <asm/arch/hardware.h>
-#include <asm/arch/imx-dma.h>
-#include <asm/arch/spi_imx.h>
+#include <mach/hardware.h>
+#include <mach/imx-dma.h>
+#include <mach/spi_imx.h>
 
 /*-------------------------------------------------------------------------*/
 /* SPI Registers offsets from peripheral base address */
diff --git a/drivers/spi/spi_s3c24xx.c b/drivers/spi/spi_s3c24xx.c
index 89da39f02d68..98abc73c1a1d 100644
--- a/drivers/spi/spi_s3c24xx.c
+++ b/drivers/spi/spi_s3c24xx.c
@@ -25,11 +25,11 @@
 
 #include <asm/io.h>
 #include <asm/dma.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
-#include <asm/arch/regs-gpio.h>
+#include <mach/regs-gpio.h>
 #include <asm/plat-s3c24xx/regs-spi.h>
-#include <asm/arch/spi.h>
+#include <mach/spi.h>
 
 struct s3c24xx_spi {
         /* bitbang has to be first */
diff --git a/drivers/spi/spi_s3c24xx_gpio.c b/drivers/spi/spi_s3c24xx_gpio.c
index d44fd0af0da1..cc1f647f579b 100644
--- a/drivers/spi/spi_s3c24xx_gpio.c
+++ b/drivers/spi/spi_s3c24xx_gpio.c
@@ -21,9 +21,9 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/spi_bitbang.h>
 
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/spi-gpio.h>
-#include <asm/arch/hardware.h>
+#include <mach/regs-gpio.h>
+#include <mach/spi-gpio.h>
+#include <mach/hardware.h>
 
 struct s3c2410_spigpio {
         struct spi_bitbang               bitbang;
diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c
index 5b935e9ebf99..a8a1de413321 100644
--- a/drivers/usb/gadget/at91_udc.c
+++ b/drivers/usb/gadget/at91_udc.c
@@ -40,15 +40,15 @@
 #include <linux/usb/gadget.h>
 
 #include <asm/byteorder.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/system.h>
 #include <asm/gpio.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/at91sam9261_matrix.h>
+#include <mach/board.h>
+#include <mach/cpu.h>
+#include <mach/at91sam9261_matrix.h>
 
 #include "at91_udc.h"
 
diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
index 07e5a0b5dcda..ae30ab1d264f 100644
--- a/drivers/usb/gadget/atmel_usba_udc.c
+++ b/drivers/usb/gadget/atmel_usba_udc.c
@@ -22,7 +22,7 @@
 #include <linux/delay.h>
 
 #include <asm/gpio.h>
-#include <asm/arch/board.h>
+#include <mach/board.h>
 
 #include "atmel_usba_udc.h"
 
@@ -334,7 +334,7 @@ static void toggle_bias(int is_on)
 
 #elif defined(CONFIG_ARCH_AT91)
 
-#include <asm/arch/at91_pmc.h>
+#include <mach/at91_pmc.h>
 
 static void toggle_bias(int is_on)
 {
diff --git a/drivers/usb/gadget/lh7a40x_udc.h b/drivers/usb/gadget/lh7a40x_udc.h
index fd43b90df03e..ca861203a301 100644
--- a/drivers/usb/gadget/lh7a40x_udc.h
+++ b/drivers/usb/gadget/lh7a40x_udc.h
@@ -47,7 +47,7 @@
 #include <asm/irq.h>
 #include <asm/system.h>
 #include <asm/unaligned.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
diff --git a/drivers/usb/gadget/omap_udc.c b/drivers/usb/gadget/omap_udc.c
index 395bd1844482..376e80c07530 100644
--- a/drivers/usb/gadget/omap_udc.c
+++ b/drivers/usb/gadget/omap_udc.c
@@ -52,8 +52,8 @@
 #include <asm/unaligned.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/dma.h>
-#include <asm/arch/usb.h>
+#include <mach/dma.h>
+#include <mach/usb.h>
 
 #include "omap_udc.h"
 
diff --git a/drivers/usb/gadget/pxa25x_udc.c b/drivers/usb/gadget/pxa25x_udc.c
index 7e6725d89976..da6e93c201d2 100644
--- a/drivers/usb/gadget/pxa25x_udc.c
+++ b/drivers/usb/gadget/pxa25x_udc.c
@@ -61,7 +61,7 @@
  * This driver is PXA25x only.  Grab the right register definitions.
  */
 #ifdef CONFIG_ARCH_PXA
-#include <asm/arch/pxa25x-udc.h>
+#include <mach/pxa25x-udc.h>
 #endif
 
 #include <asm/mach/udc_pxa2xx.h>
diff --git a/drivers/usb/gadget/pxa25x_udc.h b/drivers/usb/gadget/pxa25x_udc.h
index c8a13215e02c..1d51aa21e6eb 100644
--- a/drivers/usb/gadget/pxa25x_udc.h
+++ b/drivers/usb/gadget/pxa25x_udc.h
@@ -139,7 +139,7 @@ struct pxa25x_udc {
 /*-------------------------------------------------------------------------*/
 
 #ifdef CONFIG_ARCH_LUBBOCK
-#include <asm/arch/lubbock.h>
+#include <mach/lubbock.h>
 /* lubbock can also report usb connect/disconnect irqs */
 #endif
 
diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c
index 06c81a3c9277..a28513ecbe5b 100644
--- a/drivers/usb/gadget/pxa27x_udc.c
+++ b/drivers/usb/gadget/pxa27x_udc.c
@@ -33,13 +33,13 @@
 #include <linux/irq.h>
 
 #include <asm/byteorder.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 #include <linux/usb.h>
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
-#include <asm/arch/pxa2xx-regs.h> /* FIXME: for PSSR */
-#include <asm/arch/udc.h>
+#include <mach/pxa2xx-regs.h> /* FIXME: for PSSR */
+#include <mach/udc.h>
 
 #include "pxa27x_udc.h"
 
diff --git a/drivers/usb/gadget/s3c2410_udc.c b/drivers/usb/gadget/s3c2410_udc.c
index 021955a57722..538807384592 100644
--- a/drivers/usb/gadget/s3c2410_udc.c
+++ b/drivers/usb/gadget/s3c2410_udc.c
@@ -49,10 +49,10 @@
 #include <asm/irq.h>
 #include <asm/system.h>
 #include <asm/unaligned.h>
-#include <asm/arch/irqs.h>
+#include <mach/irqs.h>
 
-#include <asm/arch/hardware.h>
-#include <asm/arch/regs-gpio.h>
+#include <mach/hardware.h>
+#include <mach/regs-gpio.h>
 
 #include <asm/plat-s3c24xx/regs-udc.h>
 #include <asm/plat-s3c24xx/udc.h>
@@ -887,7 +887,7 @@ static void s3c2410_udc_handle_ep(struct s3c2410_ep *ep)
         }
 }
 
-#include <asm/arch/regs-irq.h>
+#include <mach/regs-irq.h>
 
 /*
  *      s3c2410_udc_irq - interrupt handler
diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
index 389a8f1bbc69..6db7a2889e66 100644
--- a/drivers/usb/host/ohci-at91.c
+++ b/drivers/usb/host/ohci-at91.c
@@ -15,11 +15,11 @@
 #include <linux/clk.h>
 #include <linux/platform_device.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/gpio.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/cpu.h>
+#include <mach/board.h>
+#include <mach/cpu.h>
 
 #ifndef CONFIG_ARCH_AT91
 #error "CONFIG_ARCH_AT91 must be defined."
diff --git a/drivers/usb/host/ohci-ep93xx.c b/drivers/usb/host/ohci-ep93xx.c
index 4d628a9c6d89..cb0b506f8259 100644
--- a/drivers/usb/host/ohci-ep93xx.c
+++ b/drivers/usb/host/ohci-ep93xx.c
@@ -28,7 +28,7 @@
 #include <linux/signal.h>
 #include <linux/platform_device.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 static struct clk *usb_host_clock;
 
diff --git a/drivers/usb/host/ohci-lh7a404.c b/drivers/usb/host/ohci-lh7a404.c
index 020769b69431..9e31d440d115 100644
--- a/drivers/usb/host/ohci-lh7a404.c
+++ b/drivers/usb/host/ohci-lh7a404.c
@@ -19,7 +19,7 @@
 #include <linux/platform_device.h>
 #include <linux/signal.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 
 extern int usb_disabled(void);
diff --git a/drivers/usb/host/ohci-omap.c b/drivers/usb/host/ohci-omap.c
index 9b7e9102fb98..94dfca02f7e1 100644
--- a/drivers/usb/host/ohci-omap.c
+++ b/drivers/usb/host/ohci-omap.c
@@ -19,15 +19,15 @@
 #include <linux/platform_device.h>
 #include <linux/clk.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/mux.h>
-#include <asm/arch/irqs.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/fpga.h>
-#include <asm/arch/usb.h>
+#include <mach/mux.h>
+#include <mach/irqs.h>
+#include <mach/gpio.h>
+#include <mach/fpga.h>
+#include <mach/usb.h>
 
 
 /* OMAP-1510 OHCI has its own MMU for DMA */
diff --git a/drivers/usb/host/ohci-pnx4008.c b/drivers/usb/host/ohci-pnx4008.c
index ff4d928eb117..b02cd0761977 100644
--- a/drivers/usb/host/ohci-pnx4008.c
+++ b/drivers/usb/host/ohci-pnx4008.c
@@ -21,12 +21,12 @@
 #include <linux/platform_device.h>
 #include <linux/i2c.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 
-#include <asm/arch/platform.h>
-#include <asm/arch/irqs.h>
-#include <asm/arch/gpio.h>
+#include <mach/platform.h>
+#include <mach/irqs.h>
+#include <mach/gpio.h>
 
 #define USB_CTRL        IO_ADDRESS(PNX4008_PWRMAN_BASE + 0x64)
 
diff --git a/drivers/usb/host/ohci-pxa27x.c b/drivers/usb/host/ohci-pxa27x.c
index 3eb2c28e608d..8c9c4849db6e 100644
--- a/drivers/usb/host/ohci-pxa27x.c
+++ b/drivers/usb/host/ohci-pxa27x.c
@@ -24,10 +24,10 @@
 #include <linux/platform_device.h>
 #include <linux/clk.h>
 
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-regs.h> /* FIXME: for PSSR */
-#include <asm/arch/ohci.h>
+#include <mach/hardware.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-regs.h> /* FIXME: for PSSR */
+#include <mach/ohci.h>
 
 #define PXA_UHC_MAX_PORTNUM    3
 
diff --git a/drivers/usb/host/ohci-s3c2410.c b/drivers/usb/host/ohci-s3c2410.c
index 358100c8dfa3..9e3dc4069e8b 100644
--- a/drivers/usb/host/ohci-s3c2410.c
+++ b/drivers/usb/host/ohci-s3c2410.c
@@ -22,8 +22,8 @@
 #include <linux/platform_device.h>
 #include <linux/clk.h>
 
-#include <asm/arch/hardware.h>
-#include <asm/arch/usb-control.h>
+#include <mach/hardware.h>
+#include <mach/usb-control.h>
 
 #define valid_port(idx) ((idx) == 1 || (idx) == 2)
 
diff --git a/drivers/usb/host/ohci-sa1111.c b/drivers/usb/host/ohci-sa1111.c
index a3a8fea6d363..4626b002e670 100644
--- a/drivers/usb/host/ohci-sa1111.c
+++ b/drivers/usb/host/ohci-sa1111.c
@@ -13,10 +13,10 @@
  * This file is licenced under the GPL.
  */
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
-#include <asm/arch/assabet.h>
-#include <asm/arch/badge4.h>
+#include <mach/assabet.h>
+#include <mach/badge4.h>
 #include <asm/hardware/sa1111.h>
 
 #ifndef CONFIG_SA1111
diff --git a/drivers/video/acornfb.c b/drivers/video/acornfb.c
index bad26c65d9bf..61c3d3f40fd1 100644
--- a/drivers/video/acornfb.c
+++ b/drivers/video/acornfb.c
@@ -29,7 +29,7 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
@@ -339,7 +339,7 @@ acornfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 #endif
 
 #ifdef HAS_VIDC20
-#include <asm/arch/acornfb.h>
+#include <mach/acornfb.h>
 
 #define MAX_SIZE        2*1024*1024
 
diff --git a/drivers/video/am200epd.c b/drivers/video/am200epd.c
index 32dd85126931..0c35b8b0160e 100644
--- a/drivers/video/am200epd.c
+++ b/drivers/video/am200epd.c
@@ -33,7 +33,7 @@
 
 #include <video/metronomefb.h>
 
-#include <asm/arch/pxa-regs.h>
+#include <mach/pxa-regs.h>
 
 /* register offsets for gpio control */
 #define LED_GPIO_PIN 51
diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
index 5b3a15dffb5f..e7018a2f56af 100644
--- a/drivers/video/atmel_lcdfb.c
+++ b/drivers/video/atmel_lcdfb.c
@@ -18,9 +18,9 @@
 #include <linux/delay.h>
 #include <linux/backlight.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/gpio.h>
+#include <mach/board.h>
+#include <mach/cpu.h>
+#include <mach/gpio.h>
 
 #include <video/atmel_lcdc.h>
 
diff --git a/drivers/video/backlight/omap1_bl.c b/drivers/video/backlight/omap1_bl.c
index 891875d53a49..cbad67e89826 100644
--- a/drivers/video/backlight/omap1_bl.c
+++ b/drivers/video/backlight/omap1_bl.c
@@ -25,9 +25,9 @@
 #include <linux/fb.h>
 #include <linux/backlight.h>
 
-#include <asm/arch/hardware.h>
-#include <asm/arch/board.h>
-#include <asm/arch/mux.h>
+#include <mach/hardware.h>
+#include <mach/board.h>
+#include <mach/mux.h>
 
 #define OMAPBL_MAX_INTENSITY            0xff
 
diff --git a/drivers/video/clps711xfb.c b/drivers/video/clps711xfb.c
index 3701caa367e4..16f5db471ab5 100644
--- a/drivers/video/clps711xfb.c
+++ b/drivers/video/clps711xfb.c
@@ -27,12 +27,12 @@
 #include <linux/proc_fs.h>
 #include <linux/delay.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <linux/uaccess.h>
 
 #include <asm/hardware/clps7111.h>
-#include <asm/arch/syspld.h>
+#include <mach/syspld.h>
 
 struct fb_info  *cfb;
 
diff --git a/drivers/video/cyber2000fb.c b/drivers/video/cyber2000fb.c
index d0e4cb618269..41d62632dcdb 100644
--- a/drivers/video/cyber2000fb.c
+++ b/drivers/video/cyber2000fb.c
@@ -1425,7 +1425,7 @@ static void cyberpro_common_resume(struct cfb_info *cfb)
 
 #ifdef CONFIG_ARCH_SHARK
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 static int __devinit cyberpro_vl_probe(void)
 {
diff --git a/drivers/video/epson1355fb.c b/drivers/video/epson1355fb.c
index cc2810ef5de5..2735b79e52a1 100644
--- a/drivers/video/epson1355fb.c
+++ b/drivers/video/epson1355fb.c
@@ -71,7 +71,7 @@ struct epson1355_par {
 #if defined(CONFIG_ARM)
 
 # ifdef CONFIG_ARCH_CEIVA
-#  include <asm/arch/hardware.h>
+#  include <mach/hardware.h>
 #  define EPSON1355FB_BASE_PHYS (CEIVA_PHYS_SED1355)
 # endif
 
diff --git a/drivers/video/imxfb.c b/drivers/video/imxfb.c
index d28879fd3a29..ccd986140c95 100644
--- a/drivers/video/imxfb.c
+++ b/drivers/video/imxfb.c
@@ -33,9 +33,9 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
-#include <asm/arch/imxfb.h>
+#include <mach/imxfb.h>
 
 /*
  * Complain if VAR is out of range.
diff --git a/drivers/video/omap/blizzard.c b/drivers/video/omap/blizzard.c
index 4d8ad9cd0e19..9dfcf39d3367 100644
--- a/drivers/video/omap/blizzard.c
+++ b/drivers/video/omap/blizzard.c
@@ -26,9 +26,9 @@
 #include <linux/delay.h>
 #include <linux/clk.h>
 
-#include <asm/arch/dma.h>
-#include <asm/arch/omapfb.h>
-#include <asm/arch/blizzard.h>
+#include <mach/dma.h>
+#include <mach/omapfb.h>
+#include <mach/blizzard.h>
 
 #include "dispc.h"
 
diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c
index ab77c51fe9d6..6efcf89e7fbe 100644
--- a/drivers/video/omap/dispc.c
+++ b/drivers/video/omap/dispc.c
@@ -25,9 +25,9 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <asm/arch/sram.h>
-#include <asm/arch/omapfb.h>
-#include <asm/arch/board.h>
+#include <mach/sram.h>
+#include <mach/omapfb.h>
+#include <mach/board.h>
 
 #include "dispc.h"
 
diff --git a/drivers/video/omap/hwa742.c b/drivers/video/omap/hwa742.c
index 1e642b7a20fe..f24df0b54e1c 100644
--- a/drivers/video/omap/hwa742.c
+++ b/drivers/video/omap/hwa742.c
@@ -26,9 +26,9 @@
 #include <linux/delay.h>
 #include <linux/clk.h>
 
-#include <asm/arch/dma.h>
-#include <asm/arch/omapfb.h>
-#include <asm/arch/hwa742.h>
+#include <mach/dma.h>
+#include <mach/omapfb.h>
+#include <mach/hwa742.h>
 
 #define HWA742_REV_CODE_REG       0x0
 #define HWA742_CONFIG_REG         0x2
diff --git a/drivers/video/omap/lcd_h3.c b/drivers/video/omap/lcd_h3.c
index 31e978349a80..2486237ebba5 100644
--- a/drivers/video/omap/lcd_h3.c
+++ b/drivers/video/omap/lcd_h3.c
@@ -23,8 +23,8 @@
 #include <linux/platform_device.h>
 #include <linux/i2c/tps65010.h>
 
-#include <asm/arch/gpio.h>
-#include <asm/arch/omapfb.h>
+#include <mach/gpio.h>
+#include <mach/omapfb.h>
 
 #define MODULE_NAME     "omapfb-lcd_h3"
 
diff --git a/drivers/video/omap/lcd_h4.c b/drivers/video/omap/lcd_h4.c
index fd6f0eb16de1..88c19d424ef7 100644
--- a/drivers/video/omap/lcd_h4.c
+++ b/drivers/video/omap/lcd_h4.c
@@ -22,7 +22,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 
-#include <asm/arch/omapfb.h>
+#include <mach/omapfb.h>
 
 static int h4_panel_init(struct lcd_panel *panel, struct omapfb_device *fbdev)
 {
diff --git a/drivers/video/omap/lcd_inn1510.c b/drivers/video/omap/lcd_inn1510.c
index 551f385861d1..6953ed4b5820 100644
--- a/drivers/video/omap/lcd_inn1510.c
+++ b/drivers/video/omap/lcd_inn1510.c
@@ -23,8 +23,8 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 
-#include <asm/arch/fpga.h>
-#include <asm/arch/omapfb.h>
+#include <mach/fpga.h>
+#include <mach/omapfb.h>
 
 static int innovator1510_panel_init(struct lcd_panel *panel,
                                     struct omapfb_device *fbdev)
diff --git a/drivers/video/omap/lcd_inn1610.c b/drivers/video/omap/lcd_inn1610.c
index 5ef119c813e0..6a42c6a0cd99 100644
--- a/drivers/video/omap/lcd_inn1610.c
+++ b/drivers/video/omap/lcd_inn1610.c
@@ -22,8 +22,8 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 
-#include <asm/arch/gpio.h>
-#include <asm/arch/omapfb.h>
+#include <mach/gpio.h>
+#include <mach/omapfb.h>
 
 #define MODULE_NAME     "omapfb-lcd_h3"
 
diff --git a/drivers/video/omap/lcd_osk.c b/drivers/video/omap/lcd_osk.c
index a38038840fd6..a4a725f427a4 100644
--- a/drivers/video/omap/lcd_osk.c
+++ b/drivers/video/omap/lcd_osk.c
@@ -23,9 +23,9 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 
-#include <asm/arch/gpio.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/omapfb.h>
+#include <mach/gpio.h>
+#include <mach/mux.h>
+#include <mach/omapfb.h>
 
 static int osk_panel_init(struct lcd_panel *panel, struct omapfb_device *fbdev)
 {
diff --git a/drivers/video/omap/lcd_palmte.c b/drivers/video/omap/lcd_palmte.c
index 52bdfdac42c9..218317366e6e 100644
--- a/drivers/video/omap/lcd_palmte.c
+++ b/drivers/video/omap/lcd_palmte.c
@@ -23,8 +23,8 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 
-#include <asm/arch/fpga.h>
-#include <asm/arch/omapfb.h>
+#include <mach/fpga.h>
+#include <mach/omapfb.h>
 
 static int palmte_panel_init(struct lcd_panel *panel,
                                 struct omapfb_device *fbdev)
diff --git a/drivers/video/omap/lcd_palmtt.c b/drivers/video/omap/lcd_palmtt.c
index 4bb349f54356..57b0f6cf6a5a 100644
--- a/drivers/video/omap/lcd_palmtt.c
+++ b/drivers/video/omap/lcd_palmtt.c
@@ -29,8 +29,8 @@ GPIO13 - screen blanking
 #include <linux/module.h>
 #include <linux/io.h>
 
-#include <asm/arch/gpio.h>
-#include <asm/arch/omapfb.h>
+#include <mach/gpio.h>
+#include <mach/omapfb.h>
 
 static int palmtt_panel_init(struct lcd_panel *panel,
         struct omapfb_device *fbdev)
diff --git a/drivers/video/omap/lcd_palmz71.c b/drivers/video/omap/lcd_palmz71.c
index ea6170ddff35..d33d78b11723 100644
--- a/drivers/video/omap/lcd_palmz71.c
+++ b/drivers/video/omap/lcd_palmz71.c
@@ -24,7 +24,7 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 
-#include <asm/arch/omapfb.h>
+#include <mach/omapfb.h>
 
 static int palmz71_panel_init(struct lcd_panel *panel,
                               struct omapfb_device *fbdev)
diff --git a/drivers/video/omap/lcd_sx1.c b/drivers/video/omap/lcd_sx1.c
index c4f306a4e5c9..caa6a896cb8b 100644
--- a/drivers/video/omap/lcd_sx1.c
+++ b/drivers/video/omap/lcd_sx1.c
@@ -23,10 +23,10 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 
-#include <asm/arch/gpio.h>
-#include <asm/arch/omapfb.h>
-#include <asm/arch/mcbsp.h>
-#include <asm/arch/mux.h>
+#include <mach/gpio.h>
+#include <mach/omapfb.h>
+#include <mach/mcbsp.h>
+#include <mach/mux.h>
 
 /*
  * OMAP310 GPIO registers
diff --git a/drivers/video/omap/lcdc.c b/drivers/video/omap/lcdc.c
index fb19ed4992db..83514f066712 100644
--- a/drivers/video/omap/lcdc.c
+++ b/drivers/video/omap/lcdc.c
@@ -29,8 +29,8 @@
 #include <linux/vmalloc.h>
 #include <linux/clk.h>
 
-#include <asm/arch/dma.h>
-#include <asm/arch/omapfb.h>
+#include <mach/dma.h>
+#include <mach/omapfb.h>
 
 #include <asm/mach-types.h>
 
diff --git a/drivers/video/omap/omapfb_main.c b/drivers/video/omap/omapfb_main.c
index d9abc48a210b..51a138bd113c 100644
--- a/drivers/video/omap/omapfb_main.c
+++ b/drivers/video/omap/omapfb_main.c
@@ -28,8 +28,8 @@
 #include <linux/mm.h>
 #include <linux/uaccess.h>
 
-#include <asm/arch/dma.h>
-#include <asm/arch/omapfb.h>
+#include <mach/dma.h>
+#include <mach/omapfb.h>
 
 #define MODULE_NAME     "omapfb"
 
diff --git a/drivers/video/omap/rfbi.c b/drivers/video/omap/rfbi.c
index 789cfd23c36b..4a6f13d3facf 100644
--- a/drivers/video/omap/rfbi.c
+++ b/drivers/video/omap/rfbi.c
@@ -27,7 +27,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <asm/arch/omapfb.h>
+#include <mach/omapfb.h>
 
 #include "dispc.h"
 
diff --git a/drivers/video/omap/sossi.c b/drivers/video/omap/sossi.c
index fafd0f26b90f..6359353c2c67 100644
--- a/drivers/video/omap/sossi.c
+++ b/drivers/video/omap/sossi.c
@@ -24,8 +24,8 @@
 #include <linux/irq.h>
 #include <linux/io.h>
 
-#include <asm/arch/dma.h>
-#include <asm/arch/omapfb.h>
+#include <mach/dma.h>
+#include <mach/omapfb.h>
 
 #include "lcdc.h"
 
diff --git a/drivers/video/pnx4008/dum.h b/drivers/video/pnx4008/dum.h
index d80a614d89ed..1234d4375d92 100644
--- a/drivers/video/pnx4008/dum.h
+++ b/drivers/video/pnx4008/dum.h
@@ -12,7 +12,7 @@
 #ifndef __PNX008_DUM_H__
 #define __PNX008_DUM_H__
 
-#include <asm/arch/platform.h>
+#include <mach/platform.h>
 
 #define PNX4008_DUMCONF_VA_BASE         IO_ADDRESS(PNX4008_DUMCONF_BASE)
 #define PNX4008_DUM_MAIN_VA_BASE        IO_ADDRESS(PNX4008_DUM_MAINCFG_BASE)
diff --git a/drivers/video/pnx4008/sdum.c b/drivers/video/pnx4008/sdum.c
index d23bf0d659b6..2aa09bce3944 100644
--- a/drivers/video/pnx4008/sdum.c
+++ b/drivers/video/pnx4008/sdum.c
@@ -30,7 +30,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/clk.h>
 #include <asm/uaccess.h>
-#include <asm/arch/gpio.h>
+#include <mach/gpio.h>
 
 #include "sdum.h"
 #include "fbcommon.h"
diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c
index 3169ea4831ef..e7aa7ae8fca8 100644
--- a/drivers/video/pxafb.c
+++ b/drivers/video/pxafb.c
@@ -45,14 +45,14 @@
 #include <linux/kthread.h>
 #include <linux/freezer.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/div64.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-gpio.h>
-#include <asm/arch/bitfield.h>
-#include <asm/arch/pxafb.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-gpio.h>
+#include <mach/bitfield.h>
+#include <mach/pxafb.h>
 
 /*
  * Complain if VAR is out of range.
diff --git a/drivers/video/s3c2410fb.c b/drivers/video/s3c2410fb.c
index f0598961c6b0..79cf0b1976aa 100644
--- a/drivers/video/s3c2410fb.c
+++ b/drivers/video/s3c2410fb.c
@@ -29,9 +29,9 @@
 #include <asm/div64.h>
 
 #include <asm/mach/map.h>
-#include <asm/arch/regs-lcd.h>
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/fb.h>
+#include <mach/regs-lcd.h>
+#include <mach/regs-gpio.h>
+#include <mach/fb.h>
 
 #ifdef CONFIG_PM
 #include <linux/pm.h>
diff --git a/drivers/video/sa1100fb.c b/drivers/video/sa1100fb.c
index 8fbcce6d069d..c052bd4c0b06 100644
--- a/drivers/video/sa1100fb.c
+++ b/drivers/video/sa1100fb.c
@@ -177,11 +177,11 @@
 #include <linux/dma-mapping.h>
 #include <linux/mutex.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/mach-types.h>
-#include <asm/arch/assabet.h>
-#include <asm/arch/shannon.h>
+#include <mach/assabet.h>
+#include <mach/shannon.h>
 
 /*
  * debugging?
diff --git a/drivers/watchdog/at91rm9200_wdt.c b/drivers/watchdog/at91rm9200_wdt.c
index 9ff9a9565320..bf872aa2b9f3 100644
--- a/drivers/watchdog/at91rm9200_wdt.c
+++ b/drivers/watchdog/at91rm9200_wdt.c
@@ -21,7 +21,7 @@
 #include <linux/types.h>
 #include <linux/watchdog.h>
 #include <asm/uaccess.h>
-#include <asm/arch/at91_st.h>
+#include <mach/at91_st.h>
 
 
 #define WDT_DEFAULT_TIME        5       /* seconds */
diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c
index 2ec36e0d8cfe..003dffe5cb19 100644
--- a/drivers/watchdog/davinci_wdt.c
+++ b/drivers/watchdog/davinci_wdt.c
@@ -23,7 +23,7 @@
 #include <linux/platform_device.h>
 #include <linux/spinlock.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/uaccess.h>
 #include <asm/io.h>
 
diff --git a/drivers/watchdog/ep93xx_wdt.c b/drivers/watchdog/ep93xx_wdt.c
index 7476844dbac3..af8ef14c0e4c 100644
--- a/drivers/watchdog/ep93xx_wdt.c
+++ b/drivers/watchdog/ep93xx_wdt.c
@@ -29,7 +29,7 @@
 #include <linux/watchdog.h>
 #include <linux/timer.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/uaccess.h>
 
 #define WDT_VERSION     "0.3"
diff --git a/drivers/watchdog/iop_wdt.c b/drivers/watchdog/iop_wdt.c
index d37146f11e47..1946dd06d815 100644
--- a/drivers/watchdog/iop_wdt.c
+++ b/drivers/watchdog/iop_wdt.c
@@ -32,7 +32,7 @@
 #include <linux/miscdevice.h>
 #include <linux/watchdog.h>
 #include <linux/uaccess.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 static int nowayout = WATCHDOG_NOWAYOUT;
 static unsigned long wdt_status;
diff --git a/drivers/watchdog/ixp2000_wdt.c b/drivers/watchdog/ixp2000_wdt.c
index 884c2b435bea..4226dae7d260 100644
--- a/drivers/watchdog/ixp2000_wdt.c
+++ b/drivers/watchdog/ixp2000_wdt.c
@@ -26,7 +26,7 @@
 #include <linux/init.h>
 #include <linux/bitops.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/uaccess.h>
 
 static int nowayout = WATCHDOG_NOWAYOUT;
diff --git a/drivers/watchdog/ixp4xx_wdt.c b/drivers/watchdog/ixp4xx_wdt.c
index d4d37dac1072..2313fad0dbb1 100644
--- a/drivers/watchdog/ixp4xx_wdt.c
+++ b/drivers/watchdog/ixp4xx_wdt.c
@@ -23,7 +23,7 @@
 #include <linux/init.h>
 #include <linux/bitops.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/uaccess.h>
 
 static int nowayout = WATCHDOG_NOWAYOUT;
diff --git a/drivers/watchdog/ks8695_wdt.c b/drivers/watchdog/ks8695_wdt.c
index df5a6b811ccd..d21a6407fe21 100644
--- a/drivers/watchdog/ks8695_wdt.c
+++ b/drivers/watchdog/ks8695_wdt.c
@@ -21,7 +21,7 @@
 #include <linux/watchdog.h>
 #include <asm/io.h>
 #include <asm/uaccess.h>
-#include <asm/arch/regs-timer.h>
+#include <mach/regs-timer.h>
 
 
 #define WDT_DEFAULT_TIME        5       /* seconds */
diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c
index 6dfb9cf15582..74a10d50607b 100644
--- a/drivers/watchdog/omap_wdt.c
+++ b/drivers/watchdog/omap_wdt.c
@@ -43,9 +43,9 @@
 
 #include <asm/io.h>
 #include <asm/uaccess.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
-#include <asm/arch/prcm.h>
+#include <mach/prcm.h>
 
 #include "omap_wdt.h"
 
diff --git a/drivers/watchdog/pnx4008_wdt.c b/drivers/watchdog/pnx4008_wdt.c
index 11a206781d0f..f431a0427eaa 100644
--- a/drivers/watchdog/pnx4008_wdt.c
+++ b/drivers/watchdog/pnx4008_wdt.c
@@ -29,7 +29,7 @@
 #include <linux/clk.h>
 #include <linux/spinlock.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/uaccess.h>
 #include <asm/io.h>
 
diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
index 97b4a2e8eb09..f1fe800658f4 100644
--- a/drivers/watchdog/s3c2410_wdt.c
+++ b/drivers/watchdog/s3c2410_wdt.c
@@ -49,7 +49,7 @@
 #include <linux/uaccess.h>
 #include <linux/io.h>
 
-#include <asm/arch/map.h>
+#include <mach/map.h>
 
 #undef S3C_VA_WATCHDOG
 #define S3C_VA_WATCHDOG (0)
diff --git a/drivers/watchdog/sa1100_wdt.c b/drivers/watchdog/sa1100_wdt.c
index d985cba40dde..52a533c274fd 100644
--- a/drivers/watchdog/sa1100_wdt.c
+++ b/drivers/watchdog/sa1100_wdt.c
@@ -28,10 +28,10 @@
 #include <linux/bitops.h>
 
 #ifdef CONFIG_ARCH_PXA
-#include <asm/arch/pxa-regs.h>
+#include <mach/pxa-regs.h>
 #endif
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/uaccess.h>
 
 #define OSCR_FREQ               CLOCK_TICK_RATE
diff --git a/drivers/watchdog/wdt285.c b/drivers/watchdog/wdt285.c
index 00cd6f21e769..94e2d91c9ac9 100644
--- a/drivers/watchdog/wdt285.c
+++ b/drivers/watchdog/wdt285.c
@@ -29,7 +29,7 @@
 
 #include <asm/irq.h>
 #include <asm/uaccess.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/hardware/dec21285.h>
 
diff --git a/include/asm-arm/arch-aaec2000/aaec2000.h b/include/asm-arm/arch-aaec2000/aaec2000.h
deleted file mode 100644
index a6d1ee0980f2..000000000000
--- a/include/asm-arm/arch-aaec2000/aaec2000.h
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-aaec2000/aaec2000.h
- *
- *  AAEC-2000 registers definition
- *
- *  Copyright (c) 2005 Nicolas Bellido Y Ortega
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_AAEC2000_H
-#define __ASM_ARCH_AAEC2000_H
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#error You must include hardware.h not this file
-#endif /* __ASM_ARCH_HARDWARE_H */
-
-/* Chip selects */
-#define AAEC_CS0        0x00000000
-#define AAEC_CS1        0x10000000
-#define AAEC_CS2        0x20000000
-#define AAEC_CS3        0x30000000
-
-/* Flash */
-#define AAEC_FLASH_BASE AAEC_CS0
-#define AAEC_FLASH_SIZE SZ_64M
-
-/* Interrupt controller */
-#define IRQ_BASE        __REG(0x80000500)
-#define IRQ_INTSR       __REG(0x80000500)       /* Int Status Register */
-#define IRQ_INTRSR      __REG(0x80000504)       /* Int Raw (unmasked) Status */
-#define IRQ_INTENS      __REG(0x80000508)       /* Int Enable Set */
-#define IRQ_INTENC      __REG(0x8000050c)       /* Int Enable Clear */
-
-/* UART 1 */
-#define UART1_BASE      __REG(0x80000600)
-#define UART1_DR        __REG(0x80000600) /* Data/FIFO Register */
-#define UART1_LCR       __REG(0x80000604) /* Link Control Register */
-#define UART1_BRCR      __REG(0x80000608) /* Baud Rate Control Register */
-#define UART1_CR        __REG(0x8000060c) /* Control Register */
-#define UART1_SR        __REG(0x80000610) /* Status Register */
-#define UART1_INT       __REG(0x80000614) /* Interrupt Status Register */
-#define UART1_INTM      __REG(0x80000618) /* Interrupt Mask Register */
-#define UART1_INTRES    __REG(0x8000061c) /* Int Result (masked status) Register */
-
-/* UART 2 */
-#define UART2_BASE      __REG(0x80000700)
-#define UART2_DR        __REG(0x80000700) /* Data/FIFO Register */
-#define UART2_LCR       __REG(0x80000704) /* Link Control Register */
-#define UART2_BRCR      __REG(0x80000708) /* Baud Rate Control Register */
-#define UART2_CR        __REG(0x8000070c) /* Control Register */
-#define UART2_SR        __REG(0x80000710) /* Status Register */
-#define UART2_INT       __REG(0x80000714) /* Interrupt Status Register */
-#define UART2_INTM      __REG(0x80000718) /* Interrupt Mask Register */
-#define UART2_INTRES    __REG(0x8000071c) /* Int Result (masked status) Register */
-
-/* UART 3 */
-#define UART3_BASE      __REG(0x80000800)
-#define UART3_DR        __REG(0x80000800) /* Data/FIFO Register */
-#define UART3_LCR       __REG(0x80000804) /* Link Control Register */
-#define UART3_BRCR      __REG(0x80000808) /* Baud Rate Control Register */
-#define UART3_CR        __REG(0x8000080c) /* Control Register */
-#define UART3_SR        __REG(0x80000810) /* Status Register */
-#define UART3_INT       __REG(0x80000814) /* Interrupt Status Register */
-#define UART3_INTM      __REG(0x80000818) /* Interrupt Mask Register */
-#define UART3_INTRES    __REG(0x8000081c) /* Int Result (masked status) Register */
-
-/* These are used in some places */
-#define _UART1_BASE __PREG(UART1_BASE)
-#define _UART2_BASE __PREG(UART2_BASE)
-#define _UART3_BASE __PREG(UART3_BASE)
-
-/* UART Registers Offsets */
-#define UART_DR         0x00
-#define UART_LCR        0x04
-#define UART_BRCR       0x08
-#define UART_CR         0x0c
-#define UART_SR         0x10
-#define UART_INT        0x14
-#define UART_INTM       0x18
-#define UART_INTRES     0x1c
-
-/* UART_LCR Bitmask */
-#define UART_LCR_BRK    (1 << 0) /* Send Break */
-#define UART_LCR_PEN    (1 << 1) /* Parity Enable */
-#define UART_LCR_EP     (1 << 2) /* Even/Odd Parity */
-#define UART_LCR_S2     (1 << 3) /* One/Two Stop bits */
-#define UART_LCR_FIFO   (1 << 4) /* FIFO Enable */
-#define UART_LCR_WL5    (0 << 5) /* Word Length - 5 bits */
-#define UART_LCR_WL6    (1 << 5) /* Word Length - 6 bits */
-#define UART_LCR_WL7    (1 << 6) /* Word Length - 7 bits */
-#define UART_LCR_WL8    (1 << 7) /* Word Length - 8 bits */
-
-/* UART_CR Bitmask */
-#define UART_CR_EN      (1 << 0) /* UART Enable */
-#define UART_CR_SIR     (1 << 1) /* IrDA SIR Enable */
-#define UART_CR_SIRLP   (1 << 2) /* Low Power IrDA Enable */
-#define UART_CR_RXP     (1 << 3) /* Receive Pin Polarity */
-#define UART_CR_TXP     (1 << 4) /* Transmit Pin Polarity */
-#define UART_CR_MXP     (1 << 5) /* Modem Pin Polarity */
-#define UART_CR_LOOP    (1 << 6) /* Loopback Mode */
-
-/* UART_SR Bitmask */
-#define UART_SR_CTS     (1 << 0) /* Clear To Send Status */
-#define UART_SR_DSR     (1 << 1) /* Data Set Ready Status */
-#define UART_SR_DCD     (1 << 2) /* Data Carrier Detect Status */
-#define UART_SR_TxBSY   (1 << 3) /* Transmitter Busy Status */
-#define UART_SR_RxFE    (1 << 4) /* Receive FIFO Empty Status */
-#define UART_SR_TxFF    (1 << 5) /* Transmit FIFO Full Status */
-#define UART_SR_RxFF    (1 << 6) /* Receive FIFO Full Status */
-#define UART_SR_TxFE    (1 << 7) /* Transmit FIFO Empty Status */
-
-/* UART_INT Bitmask */
-#define UART_INT_RIS    (1 << 0) /* Rx Interrupt */
-#define UART_INT_TIS    (1 << 1) /* Tx Interrupt */
-#define UART_INT_MIS    (1 << 2) /* Modem Interrupt */
-#define UART_INT_RTIS   (1 << 3) /* Receive Timeout Interrupt */
-
-/* Timer 1 */
-#define TIMER1_BASE     __REG(0x80000c00)
-#define TIMER1_LOAD     __REG(0x80000c00)       /* Timer 1 Load Register */
-#define TIMER1_VAL      __REG(0x80000c04)       /* Timer 1 Value Register */
-#define TIMER1_CTRL     __REG(0x80000c08)       /* Timer 1 Control Register */
-#define TIMER1_CLEAR    __REG(0x80000c0c)       /* Timer 1 Clear Register */
-
-/* Timer 2 */
-#define TIMER2_BASE     __REG(0x80000d00)
-#define TIMER2_LOAD     __REG(0x80000d00)       /* Timer 2 Load Register */
-#define TIMER2_VAL      __REG(0x80000d04)       /* Timer 2 Value Register */
-#define TIMER2_CTRL     __REG(0x80000d08)       /* Timer 2 Control Register */
-#define TIMER2_CLEAR    __REG(0x80000d0c)       /* Timer 2 Clear Register */
-
-/* Timer 3 */
-#define TIMER3_BASE     __REG(0x80000e00)
-#define TIMER3_LOAD     __REG(0x80000e00)       /* Timer 3 Load Register */
-#define TIMER3_VAL      __REG(0x80000e04)       /* Timer 3 Value Register */
-#define TIMER3_CTRL     __REG(0x80000e08)       /* Timer 3 Control Register */
-#define TIMER3_CLEAR    __REG(0x80000e0c)       /* Timer 3 Clear Register */
-
-/* Timer Control register bits */
-#define TIMER_CTRL_ENABLE       (1 << 7) /* Enable (Start Timer) */
-#define TIMER_CTRL_PERIODIC     (1 << 6) /* Periodic Running Mode */
-#define TIMER_CTRL_FREE_RUNNING (0 << 6) /* Normal Running Mode */
-#define TIMER_CTRL_CLKSEL_508K  (1 << 3) /* 508KHz Clock select (Timer 1, 2) */
-#define TIMER_CTRL_CLKSEL_2K    (0 << 3) /* 2KHz Clock Select (Timer 1, 2) */
-
-/* Power and State Control */
-#define POWER_BASE      __REG(0x80000400)
-#define POWER_PWRSR     __REG(0x80000400) /* Power Status Register */
-#define POWER_PWRCNT    __REG(0x80000404) /* Power/Clock control */
-#define POWER_HALT      __REG(0x80000408) /* Power Idle Mode */
-#define POWER_STDBY     __REG(0x8000040c) /* Power Standby Mode */
-#define POWER_BLEOI     __REG(0x80000410) /* Battery Low End of Interrupt */
-#define POWER_MCEOI     __REG(0x80000414) /* Media Changed EoI */
-#define POWER_TEOI      __REG(0x80000418) /* Tick EoI */
-#define POWER_STFCLR    __REG(0x8000041c) /* NbFlg, RSTFlg, PFFlg, CLDFlg Clear */
-#define POWER_CLKSET    __REG(0x80000420) /* Clock Speed Control */
-
-/* GPIO Registers */
-#define AAEC_GPIO_PHYS  0x80000e00
-
-#define AAEC_GPIO_PADR          __REG(AAEC_GPIO_PHYS + 0x00)
-#define AAEC_GPIO_PBDR          __REG(AAEC_GPIO_PHYS + 0x04)
-#define AAEC_GPIO_PCDR          __REG(AAEC_GPIO_PHYS + 0x08)
-#define AAEC_GPIO_PDDR          __REG(AAEC_GPIO_PHYS + 0x0c)
-#define AAEC_GPIO_PADDR         __REG(AAEC_GPIO_PHYS + 0x10)
-#define AAEC_GPIO_PBDDR         __REG(AAEC_GPIO_PHYS + 0x14)
-#define AAEC_GPIO_PCDDR         __REG(AAEC_GPIO_PHYS + 0x18)
-#define AAEC_GPIO_PDDDR         __REG(AAEC_GPIO_PHYS + 0x1c)
-#define AAEC_GPIO_PEDR          __REG(AAEC_GPIO_PHYS + 0x20)
-#define AAEC_GPIO_PEDDR         __REG(AAEC_GPIO_PHYS + 0x24)
-#define AAEC_GPIO_KSCAN         __REG(AAEC_GPIO_PHYS + 0x28)
-#define AAEC_GPIO_PINMUX        __REG(AAEC_GPIO_PHYS + 0x2c)
-#define AAEC_GPIO_PFDR          __REG(AAEC_GPIO_PHYS + 0x30)
-#define AAEC_GPIO_PFDDR         __REG(AAEC_GPIO_PHYS + 0x34)
-#define AAEC_GPIO_PGDR          __REG(AAEC_GPIO_PHYS + 0x38)
-#define AAEC_GPIO_PGDDR         __REG(AAEC_GPIO_PHYS + 0x3c)
-#define AAEC_GPIO_PHDR          __REG(AAEC_GPIO_PHYS + 0x40)
-#define AAEC_GPIO_PHDDR         __REG(AAEC_GPIO_PHYS + 0x44)
-#define AAEC_GPIO_RAZ           __REG(AAEC_GPIO_PHYS + 0x48)
-#define AAEC_GPIO_INTTYPE1      __REG(AAEC_GPIO_PHYS + 0x4c)
-#define AAEC_GPIO_INTTYPE2      __REG(AAEC_GPIO_PHYS + 0x50)
-#define AAEC_GPIO_FEOI          __REG(AAEC_GPIO_PHYS + 0x54)
-#define AAEC_GPIO_INTEN         __REG(AAEC_GPIO_PHYS + 0x58)
-#define AAEC_GPIO_INTSTATUS     __REG(AAEC_GPIO_PHYS + 0x5c)
-#define AAEC_GPIO_RAWINTSTATUS  __REG(AAEC_GPIO_PHYS + 0x60)
-#define AAEC_GPIO_DB            __REG(AAEC_GPIO_PHYS + 0x64)
-#define AAEC_GPIO_PAPINDR       __REG(AAEC_GPIO_PHYS + 0x68)
-#define AAEC_GPIO_PBPINDR       __REG(AAEC_GPIO_PHYS + 0x6c)
-#define AAEC_GPIO_PCPINDR       __REG(AAEC_GPIO_PHYS + 0x70)
-#define AAEC_GPIO_PDPINDR       __REG(AAEC_GPIO_PHYS + 0x74)
-#define AAEC_GPIO_PEPINDR       __REG(AAEC_GPIO_PHYS + 0x78)
-#define AAEC_GPIO_PFPINDR       __REG(AAEC_GPIO_PHYS + 0x7c)
-#define AAEC_GPIO_PGPINDR       __REG(AAEC_GPIO_PHYS + 0x80)
-#define AAEC_GPIO_PHPINDR       __REG(AAEC_GPIO_PHYS + 0x84)
-
-#define AAEC_GPIO_PINMUX_PE0CON         (1 << 0)
-#define AAEC_GPIO_PINMUX_PD0CON         (1 << 1)
-#define AAEC_GPIO_PINMUX_CODECON        (1 << 2)
-#define AAEC_GPIO_PINMUX_UART3CON       (1 << 3)
-
-/* LCD Controller */
-#define AAEC_CLCD_PHYS  0x80003000
-
-#endif /* __ARM_ARCH_AAEC2000_H */
diff --git a/include/asm-arm/arch-aaec2000/aaed2000.h b/include/asm-arm/arch-aaec2000/aaed2000.h
deleted file mode 100644
index bc76d2badb91..000000000000
--- a/include/asm-arm/arch-aaec2000/aaed2000.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-aaec2000/aaed2000.h
- *
- *  AAED-2000 specific bits definition
- *
- *  Copyright (c) 2005 Nicolas Bellido Y Ortega
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_AAED2000_H
-#define __ASM_ARCH_AAED2000_H
-
-/* External GPIOs. */
-
-#define EXT_GPIO_PBASE  AAEC_CS3
-#define EXT_GPIO_VBASE  0xf8100000
-#define EXT_GPIO_LENGTH 0x00001000
-
-#define __ext_gpio_p2v(x)       ((x) - EXT_GPIO_PBASE + EXT_GPIO_VBASE)
-#define __ext_gpio_v2p(x)       ((x) + EXT_GPIO_PBASE - EXT_GPIO_VBASE)
-
-#define __EXT_GPIO_REG(x)       (*((volatile u32 *)__ext_gpio_p2v(x)))
-#define __EXT_GPIO_PREG(x)      (__ext_gpio_v2p((u32)&(x)))
-
-#define AAED_EXT_GPIO   __EXT_GPIO_REG(EXT_GPIO_PBASE)
-
-#define AAED_EGPIO_KBD_SCAN     0x00003fff /* Keyboard scan data */
-#define AAED_EGPIO_PWR_INT      0x00008fff /* Smart battery charger interrupt */
-#define AAED_EGPIO_SWITCHED     0x000f0000 /* DIP Switches */
-#define AAED_EGPIO_USB_VBUS     0x00400000 /* USB Vbus sense */
-#define AAED_EGPIO_LCD_PWR_EN   0x02000000 /* LCD and backlight PWR enable */
-#define AAED_EGPIO_nLED0        0x20000000 /* LED 0 */
-#define AAED_EGPIO_nLED1        0x20000000 /* LED 1 */
-#define AAED_EGPIO_nLED2        0x20000000 /* LED 2 */
-
-
-#endif /* __ARM_ARCH_AAED2000_H */
diff --git a/include/asm-arm/arch-aaec2000/debug-macro.S b/include/asm-arm/arch-aaec2000/debug-macro.S
deleted file mode 100644
index 7b1fce021d8a..000000000000
--- a/include/asm-arm/arch-aaec2000/debug-macro.S
+++ /dev/null
@@ -1,37 +0,0 @@
-/*  linux/include/asm-arm/arch-aaec2000/debug-macro.S
- *
- *  Debugging macro include header
- *
- *  Copyright (c) 2005 Nicolas Bellido Y Ortega
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-
-#include "hardware.h"
-                .macro  addruart,rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx, #0x80000000                @ physical
-                movne   \rx, #io_p2v(0x80000000)        @ virtual
-                orr     \rx, \rx, #0x00000800
-                .endm
-
-                .macro  senduart,rd,rx
-                str     \rd, [\rx, #0]
-                .endm
-
-                .macro  busyuart,rd,rx
-1002:           ldr     \rd, [\rx, #0x10]
-                tst     \rd, #(1 << 7)
-                beq     1002b
-                .endm
-
-                .macro  waituart,rd,rx
-#if 0
-1001:           ldr     \rd, [\rx, #0x10]
-                tst     \rd, #(1 << 5)
-                beq     1001b
-#endif
-                .endm
diff --git a/include/asm-arm/arch-aaec2000/dma.h b/include/asm-arm/arch-aaec2000/dma.h
deleted file mode 100644
index e100b1e526fe..000000000000
--- a/include/asm-arm/arch-aaec2000/dma.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-aaec2000/dma.h
- *
- *  Copyright (c) 2005 Nicolas Bellido Y Ortega
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
diff --git a/include/asm-arm/arch-aaec2000/entry-macro.S b/include/asm-arm/arch-aaec2000/entry-macro.S
deleted file mode 100644
index 83fdf68f6b7c..000000000000
--- a/include/asm-arm/arch-aaec2000/entry-macro.S
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-aaec2000/entry-macro.S
- *
- *  Low-level IRQ helper for aaec-2000 based platforms
- *
- *  Copyright (c) 2005 Nicolas Bellido Y Ortega
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- *
- */
-#include <asm/arch/irqs.h>
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                mov     r4, #0xf8000000
-                add     r4, r4, #0x00000500
-                mov     \base, r4
-                ldr     \irqstat, [\base, #0]
-                cmp     \irqstat, #0
-                bne     1001f
-                ldr     \irqnr, =NR_IRQS+1
-                b       1003f
-1001:           mov     \irqnr, #0
-1002:           ands    \tmp, \irqstat, #1
-                mov     \irqstat, \irqstat, LSR #1
-                add     \irqnr, \irqnr, #1
-                beq     1002b
-                sub     \irqnr, \irqnr, #1
-1003:
-                .endm
diff --git a/include/asm-arm/arch-aaec2000/hardware.h b/include/asm-arm/arch-aaec2000/hardware.h
deleted file mode 100644
index 153506fd06ed..000000000000
--- a/include/asm-arm/arch-aaec2000/hardware.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-aaec2000/hardware.h
- *
- *  Copyright (c) 2005 Nicolas Bellido Y Ortega
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <asm/sizes.h>
-#include <asm/arch/aaec2000.h>
-
-/* The kernel is loaded at physical address 0xf8000000.
- * We map the IO space a bit after
- */
-#define PIO_APB_BASE    0x80000000
-#define VIO_APB_BASE    0xf8000000
-#define IO_APB_LENGTH   0x2000
-#define PIO_AHB_BASE    0x80002000
-#define VIO_AHB_BASE    0xf8002000
-#define IO_AHB_LENGTH   0x2000
-
-#define VIO_BASE    VIO_APB_BASE
-#define PIO_BASE    PIO_APB_BASE
-
-#define io_p2v(x) ( (x) - PIO_BASE + VIO_BASE )
-#define io_v2p(x) ( (x) + PIO_BASE - VIO_BASE )
-
-#ifndef __ASSEMBLY__
-
-#include <asm/types.h>
-
-/* FIXME: Is it needed to optimize this a la pxa ?? */
-#define __REG(x)    (*((volatile u32 *)io_p2v(x)))
-#define __PREG(x)   (io_v2p((u32)&(x)))
-
-#else /* __ASSEMBLY__ */
-
-#define __REG(x)    io_p2v(x)
-#define __PREG(x)   io_v2p(x)
-
-#endif
-
-#include "aaec2000.h"
-
-#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-aaec2000/io.h b/include/asm-arm/arch-aaec2000/io.h
deleted file mode 100644
index bc2364ab8752..000000000000
--- a/include/asm-arm/arch-aaec2000/io.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-aaec2000/io.h
- *
- *  Copied from asm/arch/sa1100/io.h
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#include <asm/arch/hardware.h>
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/*
- * We don't actually have real ISA nor PCI buses, but there is so many
- * drivers out there that might just work if we fake them...
- */
-#define __io(a)                 ((void __iomem *)(a))
-#define __mem_pci(a)            (a)
-
-#endif
diff --git a/include/asm-arm/arch-aaec2000/irqs.h b/include/asm-arm/arch-aaec2000/irqs.h
deleted file mode 100644
index de252220e806..000000000000
--- a/include/asm-arm/arch-aaec2000/irqs.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-aaec2000/irqs.h
- *
- *  Copyright (c) 2005 Nicolas Bellido Y Ortega
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H
-
-
-#define INT_GPIOF0_FIQ  0  /* External GPIO Port F O Fast Interrupt Input */
-#define INT_BL_FIQ      1  /* Battery Low Fast Interrupt */
-#define INT_WE_FIQ      2  /* Watchdog Expired Fast Interrupt */
-#define INT_MV_FIQ      3  /* Media Changed Interrupt */
-#define INT_SC          4  /* Sound Codec Interrupt */
-#define INT_GPIO1       5  /* GPIO Port F Configurable Int 1 */
-#define INT_GPIO2       6  /* GPIO Port F Configurable Int 2 */
-#define INT_GPIO3       7  /* GPIO Port F Configurable Int 3 */
-#define INT_TMR1_OFL    8  /* Timer 1 Overflow Interrupt */
-#define INT_TMR2_OFL    9  /* Timer 2 Overflow Interrupt */
-#define INT_RTC_CM      10 /* RTC Compare Match Interrupt */
-#define INT_TICK        11 /* 64Hz Tick Interrupt */
-#define INT_UART1       12 /* UART1 Interrupt */
-#define INT_UART2       13 /* UART2 & Modem State Changed Interrupt */
-#define INT_LCD         14 /* LCD Interrupt */
-#define INT_SSI         15 /* SSI End of Transfer Interrupt */
-#define INT_UART3       16 /* UART3 Interrupt */
-#define INT_SCI         17 /* SCI Interrupt */
-#define INT_AAC         18 /* Advanced Audio Codec Interrupt */
-#define INT_MMC         19 /* MMC Interrupt */
-#define INT_USB         20 /* USB Interrupt */
-#define INT_DMA         21 /* DMA Interrupt */
-#define INT_TMR3_UOFL   22 /* Timer 3 Underflow Interrupt */
-#define INT_GPIO4       23 /* GPIO Port F Configurable Int 4 */
-#define INT_GPIO5       24 /* GPIO Port F Configurable Int 4 */
-#define INT_GPIO6       25 /* GPIO Port F Configurable Int 4 */
-#define INT_GPIO7       26 /* GPIO Port F Configurable Int 4 */
-#define INT_BMI         27 /* BMI Interrupt */
-
-#define NR_IRQS         (INT_BMI + 1)
-
-#endif /* __ASM_ARCH_IRQS_H */
diff --git a/include/asm-arm/arch-aaec2000/memory.h b/include/asm-arm/arch-aaec2000/memory.h
deleted file mode 100644
index 9eceb4148922..000000000000
--- a/include/asm-arm/arch-aaec2000/memory.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-aaec2000/memory.h
- *
- *  Copyright (c) 2005 Nicolas Bellido Y Ortega
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-
-#define PHYS_OFFSET     UL(0xf0000000)
-
-#define __virt_to_bus(x)        __virt_to_phys(x)
-#define __bus_to_virt(x)        __phys_to_virt(x)
-
-/*
- * The nodes are the followings:
- *
- *   node 0: 0xf000.0000 - 0xf3ff.ffff
- *   node 1: 0xf400.0000 - 0xf7ff.ffff
- *   node 2: 0xf800.0000 - 0xfbff.ffff
- *   node 3: 0xfc00.0000 - 0xffff.ffff
- */
-#define NODE_MEM_SIZE_BITS      26
-
-#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/include/asm-arm/arch-aaec2000/system.h b/include/asm-arm/arch-aaec2000/system.h
deleted file mode 100644
index 08de97b407a8..000000000000
--- a/include/asm-arm/arch-aaec2000/system.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-aaed2000/system.h
- *
- *  Copyright (c) 2005 Nicolas Bellido Y Ortega
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-static inline void arch_reset(char mode)
-{
-        cpu_reset(0);
-}
-
-#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/include/asm-arm/arch-aaec2000/timex.h b/include/asm-arm/arch-aaec2000/timex.h
deleted file mode 100644
index f5708b38fb7f..000000000000
--- a/include/asm-arm/arch-aaec2000/timex.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-aaec2000/timex.h
- *
- *  AAEC-2000 Architecture timex specification
- *
- *  Copyright (c) 2005 Nicolas Bellido Y Ortega
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_TIMEX_H
-#define __ASM_ARCH_TIMEX_H
-
-#define CLOCK_TICK_RATE         508000
-
-#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/include/asm-arm/arch-aaec2000/uncompress.h b/include/asm-arm/arch-aaec2000/uncompress.h
deleted file mode 100644
index 300f4bf3bc74..000000000000
--- a/include/asm-arm/arch-aaec2000/uncompress.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-aaec2000/uncompress.h
- *
- *  Copyright (c) 2005 Nicolas Bellido Y Ortega
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-
-#include "hardware.h"
-
-#define UART(x)         (*(volatile unsigned long *)(serial_port + (x)))
-
-static void putc(int c)
-{
-        unsigned long serial_port;
-        do {
-                serial_port = _UART3_BASE;
-                if (UART(UART_CR) & UART_CR_EN) break;
-                serial_port = _UART1_BASE;
-                if (UART(UART_CR) & UART_CR_EN) break;
-                serial_port = _UART2_BASE;
-                if (UART(UART_CR) & UART_CR_EN) break;
-                return;
-        } while (0);
-
-        /* wait for space in the UART's transmitter */
-        while ((UART(UART_SR) & UART_SR_TxFF))
-                barrier();
-
-        /* send the character out. */
-        UART(UART_DR) = c;
-}
-
-static inline void flush(void)
-{
-}
-
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
-
-#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/include/asm-arm/arch-aaec2000/vmalloc.h b/include/asm-arm/arch-aaec2000/vmalloc.h
deleted file mode 100644
index ecb991e2e4ff..000000000000
--- a/include/asm-arm/arch-aaec2000/vmalloc.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-aaec2000/vmalloc.h
- *
- *  Copyright (c) 2005 Nicolas Bellido Y Ortega
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H
-
-#define VMALLOC_END             (PAGE_OFFSET + 0x10000000)
-
-#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/include/asm-arm/arch-at91/at91_adc.h b/include/asm-arm/arch-at91/at91_adc.h
deleted file mode 100644
index 6d71ea2637b1..000000000000
--- a/include/asm-arm/arch-at91/at91_adc.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91_adc.h
- *
- * Copyright (C) SAN People
- *
- * Analog-to-Digital Converter (ADC) registers.
- * Based on AT91SAM9260 datasheet revision D.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_ADC_H
-#define AT91_ADC_H
-
-#define AT91_ADC_CR             0x00            /* Control Register */
-#define         AT91_ADC_SWRST          (1 << 0)        /* Software Reset */
-#define         AT91_ADC_START          (1 << 1)        /* Start Conversion */
-
-#define AT91_ADC_MR             0x04            /* Mode Register */
-#define         AT91_ADC_TRGEN          (1 << 0)        /* Trigger Enable */
-#define         AT91_ADC_TRGSEL         (7 << 1)        /* Trigger Selection */
-#define                 AT91_ADC_TRGSEL_TC0             (0 << 1)
-#define                 AT91_ADC_TRGSEL_TC1             (1 << 1)
-#define                 AT91_ADC_TRGSEL_TC2             (2 << 1)
-#define                 AT91_ADC_TRGSEL_EXTERNAL        (6 << 1)
-#define         AT91_ADC_LOWRES         (1 << 4)        /* Low Resolution */
-#define         AT91_ADC_SLEEP          (1 << 5)        /* Sleep Mode */
-#define         AT91_ADC_PRESCAL        (0x3f << 8)     /* Prescalar Rate Selection */
-#define                 AT91_ADC_PRESCAL_(x)    ((x) << 8)
-#define         AT91_ADC_STARTUP        (0x1f << 16)    /* Startup Up Time */
-#define                 AT91_ADC_STARTUP_(x)    ((x) << 16)
-#define         AT91_ADC_SHTIM          (0xf  << 24)    /* Sample & Hold Time */
-#define                 AT91_ADC_SHTIM_(x)      ((x) << 24)
-
-#define AT91_ADC_CHER           0x10            /* Channel Enable Register */
-#define AT91_ADC_CHDR           0x14            /* Channel Disable Register */
-#define AT91_ADC_CHSR           0x18            /* Channel Status Register */
-#define         AT91_ADC_CH(n)          (1 << (n))      /* Channel Number */
-
-#define AT91_ADC_SR             0x1C            /* Status Register */
-#define         AT91_ADC_EOC(n)         (1 << (n))      /* End of Conversion on Channel N */
-#define         AT91_ADC_OVRE(n)        (1 << ((n) + 8))/* Overrun Error on Channel N */
-#define         AT91_ADC_DRDY           (1 << 16)       /* Data Ready */
-#define         AT91_ADC_GOVRE          (1 << 17)       /* General Overrun Error */
-#define         AT91_ADC_ENDRX          (1 << 18)       /* End of RX Buffer */
-#define         AT91_ADC_RXFUFF         (1 << 19)       /* RX Buffer Full */
-
-#define AT91_ADC_LCDR           0x20            /* Last Converted Data Register */
-#define         AT91_ADC_LDATA          (0x3ff)
-
-#define AT91_ADC_IER            0x24            /* Interrupt Enable Register */
-#define AT91_ADC_IDR            0x28            /* Interrupt Disable Register */
-#define AT91_ADC_IMR            0x2C            /* Interrupt Mask Register */
-
-#define AT91_ADC_CHR(n)         (0x30 + ((n) * 4))      /* Channel Data Register N */
-#define         AT91_ADC_DATA           (0x3ff)
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91_aic.h b/include/asm-arm/arch-at91/at91_aic.h
deleted file mode 100644
index df44c12a12d4..000000000000
--- a/include/asm-arm/arch-at91/at91_aic.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91_aic.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * Advanced Interrupt Controller (AIC) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_AIC_H
-#define AT91_AIC_H
-
-#define AT91_AIC_SMR(n)         (AT91_AIC + ((n) * 4))  /* Source Mode Registers 0-31 */
-#define         AT91_AIC_PRIOR          (7 << 0)                /* Priority Level */
-#define         AT91_AIC_SRCTYPE        (3 << 5)                /* Interrupt Source Type */
-#define                 AT91_AIC_SRCTYPE_LOW            (0 << 5)
-#define                 AT91_AIC_SRCTYPE_FALLING        (1 << 5)
-#define                 AT91_AIC_SRCTYPE_HIGH           (2 << 5)
-#define                 AT91_AIC_SRCTYPE_RISING         (3 << 5)
-
-#define AT91_AIC_SVR(n)         (AT91_AIC + 0x80 + ((n) * 4))   /* Source Vector Registers 0-31 */
-#define AT91_AIC_IVR            (AT91_AIC + 0x100)      /* Interrupt Vector Register */
-#define AT91_AIC_FVR            (AT91_AIC + 0x104)      /* Fast Interrupt Vector Register */
-#define AT91_AIC_ISR            (AT91_AIC + 0x108)      /* Interrupt Status Register */
-#define         AT91_AIC_IRQID          (0x1f << 0)             /* Current Interrupt Identifier */
-
-#define AT91_AIC_IPR            (AT91_AIC + 0x10c)      /* Interrupt Pending Register */
-#define AT91_AIC_IMR            (AT91_AIC + 0x110)      /* Interrupt Mask Register */
-#define AT91_AIC_CISR           (AT91_AIC + 0x114)      /* Core Interrupt Status Register */
-#define         AT91_AIC_NFIQ           (1 << 0)                /* nFIQ Status */
-#define         AT91_AIC_NIRQ           (1 << 1)                /* nIRQ Status */
-
-#define AT91_AIC_IECR           (AT91_AIC + 0x120)      /* Interrupt Enable Command Register */
-#define AT91_AIC_IDCR           (AT91_AIC + 0x124)      /* Interrupt Disable Command Register */
-#define AT91_AIC_ICCR           (AT91_AIC + 0x128)      /* Interrupt Clear Command Register */
-#define AT91_AIC_ISCR           (AT91_AIC + 0x12c)      /* Interrupt Set Command Register */
-#define AT91_AIC_EOICR          (AT91_AIC + 0x130)      /* End of Interrupt Command Register */
-#define AT91_AIC_SPU            (AT91_AIC + 0x134)      /* Spurious Interrupt Vector Register */
-#define AT91_AIC_DCR            (AT91_AIC + 0x138)      /* Debug Control Register */
-#define         AT91_AIC_DCR_PROT       (1 << 0)                /* Protection Mode */
-#define         AT91_AIC_DCR_GMSK       (1 << 1)                /* General Mask */
-
-#define AT91_AIC_FFER           (AT91_AIC + 0x140)      /* Fast Forcing Enable Register [SAM9 only] */
-#define AT91_AIC_FFDR           (AT91_AIC + 0x144)      /* Fast Forcing Disable Register [SAM9 only] */
-#define AT91_AIC_FFSR           (AT91_AIC + 0x148)      /* Fast Forcing Status Register [SAM9 only] */
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91_dbgu.h b/include/asm-arm/arch-at91/at91_dbgu.h
deleted file mode 100644
index 8019ffd0ad3b..000000000000
--- a/include/asm-arm/arch-at91/at91_dbgu.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91_dbgu.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * Debug Unit (DBGU) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_DBGU_H
-#define AT91_DBGU_H
-
-#ifdef AT91_DBGU
-#define AT91_DBGU_CR            (AT91_DBGU + 0x00)      /* Control Register */
-#define AT91_DBGU_MR            (AT91_DBGU + 0x04)      /* Mode Register */
-#define AT91_DBGU_IER           (AT91_DBGU + 0x08)      /* Interrupt Enable Register */
-#define         AT91_DBGU_TXRDY         (1 << 1)                /* Transmitter Ready */
-#define         AT91_DBGU_TXEMPTY       (1 << 9)                /* Transmitter Empty */
-#define AT91_DBGU_IDR           (AT91_DBGU + 0x0c)      /* Interrupt Disable Register */
-#define AT91_DBGU_IMR           (AT91_DBGU + 0x10)      /* Interrupt Mask Register */
-#define AT91_DBGU_SR            (AT91_DBGU + 0x14)      /* Status Register */
-#define AT91_DBGU_RHR           (AT91_DBGU + 0x18)      /* Receiver Holding Register */
-#define AT91_DBGU_THR           (AT91_DBGU + 0x1c)      /* Transmitter Holding Register */
-#define AT91_DBGU_BRGR          (AT91_DBGU + 0x20)      /* Baud Rate Generator Register */
-
-#define AT91_DBGU_CIDR          (AT91_DBGU + 0x40)      /* Chip ID Register */
-#define AT91_DBGU_EXID          (AT91_DBGU + 0x44)      /* Chip ID Extension Register */
-#define AT91_DBGU_FNR           (AT91_DBGU + 0x48)      /* Force NTRST Register [SAM9 only] */
-#define         AT91_DBGU_FNTRST        (1 << 0)                /* Force NTRST */
-
-#endif /* AT91_DBGU */
-
-/*
- * Some AT91 parts that don't have full DEBUG units still support the ID
- * and extensions register.
- */
-#define         AT91_CIDR_VERSION       (0x1f << 0)             /* Version of the Device */
-#define         AT91_CIDR_EPROC         (7    << 5)             /* Embedded Processor */
-#define         AT91_CIDR_NVPSIZ        (0xf  << 8)             /* Nonvolatile Program Memory Size */
-#define         AT91_CIDR_NVPSIZ2       (0xf  << 12)            /* Second Nonvolatile Program Memory Size */
-#define         AT91_CIDR_SRAMSIZ       (0xf  << 16)            /* Internal SRAM Size */
-#define                 AT91_CIDR_SRAMSIZ_1K    (1 << 16)
-#define                 AT91_CIDR_SRAMSIZ_2K    (2 << 16)
-#define                 AT91_CIDR_SRAMSIZ_112K  (4 << 16)
-#define                 AT91_CIDR_SRAMSIZ_4K    (5 << 16)
-#define                 AT91_CIDR_SRAMSIZ_80K   (6 << 16)
-#define                 AT91_CIDR_SRAMSIZ_160K  (7 << 16)
-#define                 AT91_CIDR_SRAMSIZ_8K    (8 << 16)
-#define                 AT91_CIDR_SRAMSIZ_16K   (9 << 16)
-#define                 AT91_CIDR_SRAMSIZ_32K   (10 << 16)
-#define                 AT91_CIDR_SRAMSIZ_64K   (11 << 16)
-#define                 AT91_CIDR_SRAMSIZ_128K  (12 << 16)
-#define                 AT91_CIDR_SRAMSIZ_256K  (13 << 16)
-#define                 AT91_CIDR_SRAMSIZ_96K   (14 << 16)
-#define                 AT91_CIDR_SRAMSIZ_512K  (15 << 16)
-#define         AT91_CIDR_ARCH          (0xff << 20)            /* Architecture Identifier */
-#define         AT91_CIDR_NVPTYP        (7    << 28)            /* Nonvolatile Program Memory Type */
-#define         AT91_CIDR_EXT           (1    << 31)            /* Extension Flag */
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91_mci.h b/include/asm-arm/arch-at91/at91_mci.h
deleted file mode 100644
index 400ec10014b4..000000000000
--- a/include/asm-arm/arch-at91/at91_mci.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91_mci.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * MultiMedia Card Interface (MCI) registers.
- * Based on AT91RM9200 datasheet revision F.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_MCI_H
-#define AT91_MCI_H
-
-#define AT91_MCI_CR             0x00            /* Control Register */
-#define         AT91_MCI_MCIEN          (1 <<  0)       /* Multi-Media Interface Enable */
-#define         AT91_MCI_MCIDIS         (1 <<  1)       /* Multi-Media Interface Disable */
-#define         AT91_MCI_PWSEN          (1 <<  2)       /* Power Save Mode Enable */
-#define         AT91_MCI_PWSDIS         (1 <<  3)       /* Power Save Mode Disable */
-#define         AT91_MCI_SWRST          (1 <<  7)       /* Software Reset */
-
-#define AT91_MCI_MR             0x04            /* Mode Register */
-#define         AT91_MCI_CLKDIV         (0xff  <<  0)   /* Clock Divider */
-#define         AT91_MCI_PWSDIV         (7     <<  8)   /* Power Saving Divider */
-#define         AT91_MCI_RDPROOF        (1     << 11)   /* Read Proof Enable [SAM926[03] only] */
-#define         AT91_MCI_WRPROOF        (1     << 12)   /* Write Proof Enable [SAM926[03] only] */
-#define         AT91_MCI_PDCFBYTE       (1     << 13)   /* PDC Force Byte Transfer [SAM926[03] only] */
-#define         AT91_MCI_PDCPADV        (1     << 14)   /* PDC Padding Value */
-#define         AT91_MCI_PDCMODE        (1     << 15)   /* PDC-orientated Mode */
-#define         AT91_MCI_BLKLEN         (0xfff << 18)   /* Data Block Length */
-
-#define AT91_MCI_DTOR           0x08            /* Data Timeout Register */
-#define         AT91_MCI_DTOCYC         (0xf << 0)      /* Data Timeout Cycle Number */
-#define         AT91_MCI_DTOMUL         (7   << 4)      /* Data Timeout Multiplier */
-#define         AT91_MCI_DTOMUL_1               (0 <<  4)
-#define         AT91_MCI_DTOMUL_16              (1 <<  4)
-#define         AT91_MCI_DTOMUL_128             (2 <<  4)
-#define         AT91_MCI_DTOMUL_256             (3 <<  4)
-#define         AT91_MCI_DTOMUL_1K              (4 <<  4)
-#define         AT91_MCI_DTOMUL_4K              (5 <<  4)
-#define         AT91_MCI_DTOMUL_64K             (6 <<  4)
-#define         AT91_MCI_DTOMUL_1M              (7 <<  4)
-
-#define AT91_MCI_SDCR           0x0c            /* SD Card Register */
-#define         AT91_MCI_SDCSEL         (3 << 0)        /* SD Card Selector */
-#define         AT91_MCI_SDCBUS         (1 << 7)        /* 1-bit or 4-bit bus */
-
-#define AT91_MCI_ARGR           0x10            /* Argument Register */
-
-#define AT91_MCI_CMDR           0x14            /* Command Register */
-#define         AT91_MCI_CMDNB          (0x3f << 0)     /* Command Number */
-#define         AT91_MCI_RSPTYP         (3    << 6)     /* Response Type */
-#define                 AT91_MCI_RSPTYP_NONE    (0 <<  6)
-#define                 AT91_MCI_RSPTYP_48      (1 <<  6)
-#define                 AT91_MCI_RSPTYP_136     (2 <<  6)
-#define         AT91_MCI_SPCMD          (7    << 8)     /* Special Command */
-#define                 AT91_MCI_SPCMD_NONE     (0 <<  8)
-#define                 AT91_MCI_SPCMD_INIT     (1 <<  8)
-#define                 AT91_MCI_SPCMD_SYNC     (2 <<  8)
-#define                 AT91_MCI_SPCMD_ICMD     (4 <<  8)
-#define                 AT91_MCI_SPCMD_IRESP    (5 <<  8)
-#define         AT91_MCI_OPDCMD         (1 << 11)       /* Open Drain Command */
-#define         AT91_MCI_MAXLAT         (1 << 12)       /* Max Latency for Command to Response */
-#define         AT91_MCI_TRCMD          (3 << 16)       /* Transfer Command */
-#define                 AT91_MCI_TRCMD_NONE     (0 << 16)
-#define                 AT91_MCI_TRCMD_START    (1 << 16)
-#define                 AT91_MCI_TRCMD_STOP     (2 << 16)
-#define         AT91_MCI_TRDIR          (1 << 18)       /* Transfer Direction */
-#define         AT91_MCI_TRTYP          (3 << 19)       /* Transfer Type */
-#define                 AT91_MCI_TRTYP_BLOCK    (0 << 19)
-#define                 AT91_MCI_TRTYP_MULTIPLE (1 << 19)
-#define                 AT91_MCI_TRTYP_STREAM   (2 << 19)
-
-#define AT91_MCI_BLKR           0x18            /* Block Register */
-#define         AT91_MCI_BLKR_BCNT(n)   ((0xffff & (n)) << 0)   /* Block count */
-#define         AT91_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16)  /* Block lenght */
-
-#define AT91_MCI_RSPR(n)        (0x20 + ((n) * 4))      /* Response Registers 0-3 */
-#define AT91_MCR_RDR            0x30            /* Receive Data Register */
-#define AT91_MCR_TDR            0x34            /* Transmit Data Register */
-
-#define AT91_MCI_SR             0x40            /* Status Register */
-#define         AT91_MCI_CMDRDY         (1 <<  0)       /* Command Ready */
-#define         AT91_MCI_RXRDY          (1 <<  1)       /* Receiver Ready */
-#define         AT91_MCI_TXRDY          (1 <<  2)       /* Transmit Ready */
-#define         AT91_MCI_BLKE           (1 <<  3)       /* Data Block Ended */
-#define         AT91_MCI_DTIP           (1 <<  4)       /* Data Transfer in Progress */
-#define         AT91_MCI_NOTBUSY        (1 <<  5)       /* Data Not Busy */
-#define         AT91_MCI_ENDRX          (1 <<  6)       /* End of RX Buffer */
-#define         AT91_MCI_ENDTX          (1 <<  7)       /* End fo TX Buffer */
-#define         AT91_MCI_SDIOIRQA       (1 <<  8)       /* SDIO Interrupt for Slot A */
-#define         AT91_MCI_SDIOIRQB       (1 <<  9)       /* SDIO Interrupt for Slot B */
-#define         AT91_MCI_RXBUFF         (1 << 14)       /* RX Buffer Full */
-#define         AT91_MCI_TXBUFE         (1 << 15)       /* TX Buffer Empty */
-#define         AT91_MCI_RINDE          (1 << 16)       /* Response Index Error */
-#define         AT91_MCI_RDIRE          (1 << 17)       /* Response Direction Error */
-#define         AT91_MCI_RCRCE          (1 << 18)       /* Response CRC Error */
-#define         AT91_MCI_RENDE          (1 << 19)       /* Response End Bit Error */
-#define         AT91_MCI_RTOE           (1 << 20)       /* Reponse Time-out Error */
-#define         AT91_MCI_DCRCE          (1 << 21)       /* Data CRC Error */
-#define         AT91_MCI_DTOE           (1 << 22)       /* Data Time-out Error */
-#define         AT91_MCI_OVRE           (1 << 30)       /* Overrun */
-#define         AT91_MCI_UNRE           (1 << 31)       /* Underrun */
-
-#define AT91_MCI_IER            0x44            /* Interrupt Enable Register */
-#define AT91_MCI_IDR            0x48            /* Interrupt Disable Register */
-#define AT91_MCI_IMR            0x4c            /* Interrupt Mask Register */
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91_pio.h b/include/asm-arm/arch-at91/at91_pio.h
deleted file mode 100644
index 84c3866d309f..000000000000
--- a/include/asm-arm/arch-at91/at91_pio.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91_pio.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * Parallel I/O Controller (PIO) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_PIO_H
-#define AT91_PIO_H
-
-#define PIO_PER         0x00    /* Enable Register */
-#define PIO_PDR         0x04    /* Disable Register */
-#define PIO_PSR         0x08    /* Status Register */
-#define PIO_OER         0x10    /* Output Enable Register */
-#define PIO_ODR         0x14    /* Output Disable Register */
-#define PIO_OSR         0x18    /* Output Status Register */
-#define PIO_IFER        0x20    /* Glitch Input Filter Enable */
-#define PIO_IFDR        0x24    /* Glitch Input Filter Disable */
-#define PIO_IFSR        0x28    /* Glitch Input Filter Status */
-#define PIO_SODR        0x30    /* Set Output Data Register */
-#define PIO_CODR        0x34    /* Clear Output Data Register */
-#define PIO_ODSR        0x38    /* Output Data Status Register */
-#define PIO_PDSR        0x3c    /* Pin Data Status Register */
-#define PIO_IER         0x40    /* Interrupt Enable Register */
-#define PIO_IDR         0x44    /* Interrupt Disable Register */
-#define PIO_IMR         0x48    /* Interrupt Mask Register */
-#define PIO_ISR         0x4c    /* Interrupt Status Register */
-#define PIO_MDER        0x50    /* Multi-driver Enable Register */
-#define PIO_MDDR        0x54    /* Multi-driver Disable Register */
-#define PIO_MDSR        0x58    /* Multi-driver Status Register */
-#define PIO_PUDR        0x60    /* Pull-up Disable Register */
-#define PIO_PUER        0x64    /* Pull-up Enable Register */
-#define PIO_PUSR        0x68    /* Pull-up Status Register */
-#define PIO_ASR         0x70    /* Peripheral A Select Register */
-#define PIO_BSR         0x74    /* Peripheral B Select Register */
-#define PIO_ABSR        0x78    /* AB Status Register */
-#define PIO_OWER        0xa0    /* Output Write Enable Register */
-#define PIO_OWDR        0xa4    /* Output Write Disable Register */
-#define PIO_OWSR        0xa8    /* Output Write Status Register */
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91_pit.h b/include/asm-arm/arch-at91/at91_pit.h
deleted file mode 100644
index 5026325a5ae4..000000000000
--- a/include/asm-arm/arch-at91/at91_pit.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91_pit.h
- *
- * Periodic Interval Timer (PIT) - System peripherals regsters.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_PIT_H
-#define AT91_PIT_H
-
-#define AT91_PIT_MR             (AT91_PIT + 0x00)       /* Mode Register */
-#define         AT91_PIT_PITIEN         (1 << 25)               /* Timer Interrupt Enable */
-#define         AT91_PIT_PITEN          (1 << 24)               /* Timer Enabled */
-#define         AT91_PIT_PIV            (0xfffff)               /* Periodic Interval Value */
-
-#define AT91_PIT_SR             (AT91_PIT + 0x04)       /* Status Register */
-#define         AT91_PIT_PITS           (1 << 0)                /* Timer Status */
-
-#define AT91_PIT_PIVR           (AT91_PIT + 0x08)       /* Periodic Interval Value Register */
-#define AT91_PIT_PIIR           (AT91_PIT + 0x0c)       /* Periodic Interval Image Register */
-#define         AT91_PIT_PICNT          (0xfff << 20)           /* Interval Counter */
-#define         AT91_PIT_CPIV           (0xfffff)               /* Inverval Value */
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h
deleted file mode 100644
index 2001e81f2267..000000000000
--- a/include/asm-arm/arch-at91/at91_pmc.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91_pmc.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * Power Management Controller (PMC) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_PMC_H
-#define AT91_PMC_H
-
-#define AT91_PMC_SCER           (AT91_PMC + 0x00)       /* System Clock Enable Register */
-#define AT91_PMC_SCDR           (AT91_PMC + 0x04)       /* System Clock Disable Register */
-
-#define AT91_PMC_SCSR           (AT91_PMC + 0x08)       /* System Clock Status Register */
-#define         AT91_PMC_PCK            (1 <<  0)               /* Processor Clock */
-#define         AT91RM9200_PMC_UDP      (1 <<  1)               /* USB Devcice Port Clock [AT91RM9200 only] */
-#define         AT91RM9200_PMC_MCKUDP   (1 <<  2)               /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
-#define         AT91RM9200_PMC_UHP      (1 <<  4)               /* USB Host Port Clock [AT91RM9200 only] */
-#define         AT91SAM926x_PMC_UHP     (1 <<  6)               /* USB Host Port Clock [AT91SAM926x only] */
-#define         AT91CAP9_PMC_UHP        (1 <<  6)               /* USB Host Port Clock [AT91CAP9 only] */
-#define         AT91SAM926x_PMC_UDP     (1 <<  7)               /* USB Devcice Port Clock [AT91SAM926x only] */
-#define         AT91_PMC_PCK0           (1 <<  8)               /* Programmable Clock 0 */
-#define         AT91_PMC_PCK1           (1 <<  9)               /* Programmable Clock 1 */
-#define         AT91_PMC_PCK2           (1 << 10)               /* Programmable Clock 2 */
-#define         AT91_PMC_PCK3           (1 << 11)               /* Programmable Clock 3 */
-#define         AT91_PMC_HCK0           (1 << 16)               /* AHB Clock (USB host) [AT91SAM9261 only] */
-#define         AT91_PMC_HCK1           (1 << 17)               /* AHB Clock (LCD) [AT91SAM9261 only] */
-
-#define AT91_PMC_PCER           (AT91_PMC + 0x10)       /* Peripheral Clock Enable Register */
-#define AT91_PMC_PCDR           (AT91_PMC + 0x14)       /* Peripheral Clock Disable Register */
-#define AT91_PMC_PCSR           (AT91_PMC + 0x18)       /* Peripheral Clock Status Register */
-
-#define AT91_CKGR_UCKR          (AT91_PMC + 0x1C)       /* UTMI Clock Register [SAM9RL, CAP9] */
-#define         AT91_PMC_UPLLEN         (1   << 16)             /* UTMI PLL Enable */
-#define         AT91_PMC_UPLLCOUNT      (0xf << 20)             /* UTMI PLL Start-up Time */
-#define         AT91_PMC_BIASEN         (1   << 24)             /* UTMI BIAS Enable */
-#define         AT91_PMC_BIASCOUNT      (0xf << 28)             /* UTMI PLL Start-up Time */
-
-#define AT91_CKGR_MOR           (AT91_PMC + 0x20)       /* Main Oscillator Register [not on SAM9RL] */
-#define         AT91_PMC_MOSCEN         (1    << 0)             /* Main Oscillator Enable */
-#define         AT91_PMC_OSCBYPASS      (1    << 1)             /* Oscillator Bypass [SAM9x, CAP9] */
-#define         AT91_PMC_OSCOUNT        (0xff << 8)             /* Main Oscillator Start-up Time */
-
-#define AT91_CKGR_MCFR          (AT91_PMC + 0x24)       /* Main Clock Frequency Register */
-#define         AT91_PMC_MAINF          (0xffff <<  0)          /* Main Clock Frequency */
-#define         AT91_PMC_MAINRDY        (1      << 16)          /* Main Clock Ready */
-
-#define AT91_CKGR_PLLAR         (AT91_PMC + 0x28)       /* PLL A Register */
-#define AT91_CKGR_PLLBR         (AT91_PMC + 0x2c)       /* PLL B Register */
-#define         AT91_PMC_DIV            (0xff  <<  0)           /* Divider */
-#define         AT91_PMC_PLLCOUNT       (0x3f  <<  8)           /* PLL Counter */
-#define         AT91_PMC_OUT            (3     << 14)           /* PLL Clock Frequency Range */
-#define         AT91_PMC_MUL            (0x7ff << 16)           /* PLL Multiplier */
-#define         AT91_PMC_USBDIV         (3     << 28)           /* USB Divisor (PLLB only) */
-#define                 AT91_PMC_USBDIV_1               (0 << 28)
-#define                 AT91_PMC_USBDIV_2               (1 << 28)
-#define                 AT91_PMC_USBDIV_4               (2 << 28)
-#define         AT91_PMC_USB96M         (1     << 28)           /* Divider by 2 Enable (PLLB only) */
-
-#define AT91_PMC_MCKR           (AT91_PMC + 0x30)       /* Master Clock Register */
-#define         AT91_PMC_CSS            (3 <<  0)               /* Master Clock Selection */
-#define                 AT91_PMC_CSS_SLOW               (0 << 0)
-#define                 AT91_PMC_CSS_MAIN               (1 << 0)
-#define                 AT91_PMC_CSS_PLLA               (2 << 0)
-#define                 AT91_PMC_CSS_PLLB               (3 << 0)
-#define         AT91_PMC_PRES           (7 <<  2)               /* Master Clock Prescaler */
-#define                 AT91_PMC_PRES_1                 (0 << 2)
-#define                 AT91_PMC_PRES_2                 (1 << 2)
-#define                 AT91_PMC_PRES_4                 (2 << 2)
-#define                 AT91_PMC_PRES_8                 (3 << 2)
-#define                 AT91_PMC_PRES_16                (4 << 2)
-#define                 AT91_PMC_PRES_32                (5 << 2)
-#define                 AT91_PMC_PRES_64                (6 << 2)
-#define         AT91_PMC_MDIV           (3 <<  8)               /* Master Clock Division */
-#define                 AT91RM9200_PMC_MDIV_1           (0 << 8)        /* [AT91RM9200 only] */
-#define                 AT91RM9200_PMC_MDIV_2           (1 << 8)
-#define                 AT91RM9200_PMC_MDIV_3           (2 << 8)
-#define                 AT91RM9200_PMC_MDIV_4           (3 << 8)
-#define                 AT91SAM9_PMC_MDIV_1             (0 << 8)        /* [SAM9,CAP9 only] */
-#define                 AT91SAM9_PMC_MDIV_2             (1 << 8)
-#define                 AT91SAM9_PMC_MDIV_4             (2 << 8)
-#define                 AT91SAM9_PMC_MDIV_6             (3 << 8)
-#define         AT91_PMC_PDIV           (1 << 12)               /* Processor Clock Division [some SAM9 only] */
-#define                 AT91_PMC_PDIV_1                 (0 << 12)
-#define                 AT91_PMC_PDIV_2                 (1 << 12)
-
-#define AT91_PMC_PCKR(n)        (AT91_PMC + 0x40 + ((n) * 4))   /* Programmable Clock 0-3 Registers */
-
-#define AT91_PMC_IER            (AT91_PMC + 0x60)       /* Interrupt Enable Register */
-#define AT91_PMC_IDR            (AT91_PMC + 0x64)       /* Interrupt Disable Register */
-#define AT91_PMC_SR             (AT91_PMC + 0x68)       /* Status Register */
-#define         AT91_PMC_MOSCS          (1 <<  0)               /* MOSCS Flag */
-#define         AT91_PMC_LOCKA          (1 <<  1)               /* PLLA Lock */
-#define         AT91_PMC_LOCKB          (1 <<  2)               /* PLLB Lock */
-#define         AT91_PMC_MCKRDY         (1 <<  3)               /* Master Clock */
-#define         AT91_PMC_LOCKU          (1 <<  6)               /* UPLL Lock [AT91CAP9 only] */
-#define         AT91_PMC_PCK0RDY        (1 <<  8)               /* Programmable Clock 0 */
-#define         AT91_PMC_PCK1RDY        (1 <<  9)               /* Programmable Clock 1 */
-#define         AT91_PMC_PCK2RDY        (1 << 10)               /* Programmable Clock 2 */
-#define         AT91_PMC_PCK3RDY        (1 << 11)               /* Programmable Clock 3 */
-#define AT91_PMC_IMR            (AT91_PMC + 0x6c)       /* Interrupt Mask Register */
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91_rstc.h b/include/asm-arm/arch-at91/at91_rstc.h
deleted file mode 100644
index fb8d1618a231..000000000000
--- a/include/asm-arm/arch-at91/at91_rstc.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91_rstc.h
- *
- * Reset Controller (RSTC) - System peripherals regsters.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_RSTC_H
-#define AT91_RSTC_H
-
-#define AT91_RSTC_CR            (AT91_RSTC + 0x00)      /* Reset Controller Control Register */
-#define         AT91_RSTC_PROCRST       (1 << 0)                /* Processor Reset */
-#define         AT91_RSTC_PERRST        (1 << 2)                /* Peripheral Reset */
-#define         AT91_RSTC_EXTRST        (1 << 3)                /* External Reset */
-#define         AT91_RSTC_KEY           (0xa5 << 24)            /* KEY Password */
-
-#define AT91_RSTC_SR            (AT91_RSTC + 0x04)      /* Reset Controller Status Register */
-#define         AT91_RSTC_URSTS         (1 << 0)                /* User Reset Status */
-#define         AT91_RSTC_RSTTYP        (7 << 8)                /* Reset Type */
-#define                 AT91_RSTC_RSTTYP_GENERAL        (0 << 8)
-#define                 AT91_RSTC_RSTTYP_WAKEUP         (1 << 8)
-#define                 AT91_RSTC_RSTTYP_WATCHDOG       (2 << 8)
-#define                 AT91_RSTC_RSTTYP_SOFTWARE       (3 << 8)
-#define                 AT91_RSTC_RSTTYP_USER   (4 << 8)
-#define         AT91_RSTC_NRSTL         (1 << 16)               /* NRST Pin Level */
-#define         AT91_RSTC_SRCMP         (1 << 17)               /* Software Reset Command in Progress */
-
-#define AT91_RSTC_MR            (AT91_RSTC + 0x08)      /* Reset Controller Mode Register */
-#define         AT91_RSTC_URSTEN        (1 << 0)                /* User Reset Enable */
-#define         AT91_RSTC_URSTIEN       (1 << 4)                /* User Reset Interrupt Enable */
-#define         AT91_RSTC_ERSTL         (0xf << 8)              /* External Reset Length */
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91_rtc.h b/include/asm-arm/arch-at91/at91_rtc.h
deleted file mode 100644
index af9bd28174c0..000000000000
--- a/include/asm-arm/arch-at91/at91_rtc.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91_rtc.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * Real Time Clock (RTC) - System peripheral registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_RTC_H
-#define AT91_RTC_H
-
-#define AT91_RTC_CR             (AT91_RTC + 0x00)       /* Control Register */
-#define         AT91_RTC_UPDTIM         (1 <<  0)               /* Update Request Time Register */
-#define         AT91_RTC_UPDCAL         (1 <<  1)               /* Update Request Calendar Register */
-#define         AT91_RTC_TIMEVSEL       (3 <<  8)               /* Time Event Selection */
-#define                 AT91_RTC_TIMEVSEL_MINUTE        (0 << 8)
-#define                 AT91_RTC_TIMEVSEL_HOUR          (1 << 8)
-#define                 AT91_RTC_TIMEVSEL_DAY24         (2 << 8)
-#define                 AT91_RTC_TIMEVSEL_DAY12         (3 << 8)
-#define         AT91_RTC_CALEVSEL       (3 << 16)               /* Calendar Event Selection */
-#define                 AT91_RTC_CALEVSEL_WEEK          (0 << 16)
-#define                 AT91_RTC_CALEVSEL_MONTH         (1 << 16)
-#define                 AT91_RTC_CALEVSEL_YEAR          (2 << 16)
-
-#define AT91_RTC_MR             (AT91_RTC + 0x04)       /* Mode Register */
-#define                 AT91_RTC_HRMOD          (1 <<  0)               /* 12/24 Hour Mode */
-
-#define AT91_RTC_TIMR           (AT91_RTC + 0x08)       /* Time Register */
-#define         AT91_RTC_SEC            (0x7f <<  0)            /* Current Second */
-#define         AT91_RTC_MIN            (0x7f <<  8)            /* Current Minute */
-#define         AT91_RTC_HOUR           (0x3f << 16)            /* Current Hour */
-#define         AT91_RTC_AMPM           (1    << 22)            /* Ante Meridiem Post Meridiem Indicator */
-
-#define AT91_RTC_CALR           (AT91_RTC + 0x0c)       /* Calendar Register */
-#define         AT91_RTC_CENT           (0x7f <<  0)            /* Current Century */
-#define         AT91_RTC_YEAR           (0xff <<  8)            /* Current Year */
-#define         AT91_RTC_MONTH          (0x1f << 16)            /* Current Month */
-#define         AT91_RTC_DAY            (7    << 21)            /* Current Day */
-#define         AT91_RTC_DATE           (0x3f << 24)            /* Current Date */
-
-#define AT91_RTC_TIMALR         (AT91_RTC + 0x10)       /* Time Alarm Register */
-#define         AT91_RTC_SECEN          (1 <<  7)               /* Second Alarm Enable */
-#define         AT91_RTC_MINEN          (1 << 15)               /* Minute Alarm Enable */
-#define         AT91_RTC_HOUREN         (1 << 23)               /* Hour Alarm Enable */
-
-#define AT91_RTC_CALALR         (AT91_RTC + 0x14)       /* Calendar Alarm Register */
-#define         AT91_RTC_MTHEN          (1 << 23)               /* Month Alarm Enable */
-#define         AT91_RTC_DATEEN         (1 << 31)               /* Date Alarm Enable */
-
-#define AT91_RTC_SR             (AT91_RTC + 0x18)       /* Status Register */
-#define         AT91_RTC_ACKUPD         (1 <<  0)               /* Acknowledge for Update */
-#define         AT91_RTC_ALARM          (1 <<  1)               /* Alarm Flag */
-#define         AT91_RTC_SECEV          (1 <<  2)               /* Second Event */
-#define         AT91_RTC_TIMEV          (1 <<  3)               /* Time Event */
-#define         AT91_RTC_CALEV          (1 <<  4)               /* Calendar Event */
-
-#define AT91_RTC_SCCR           (AT91_RTC + 0x1c)       /* Status Clear Command Register */
-#define AT91_RTC_IER            (AT91_RTC + 0x20)       /* Interrupt Enable Register */
-#define AT91_RTC_IDR            (AT91_RTC + 0x24)       /* Interrupt Disable Register */
-#define AT91_RTC_IMR            (AT91_RTC + 0x28)       /* Interrupt Mask Register */
-
-#define AT91_RTC_VER            (AT91_RTC + 0x2c)       /* Valid Entry Register */
-#define         AT91_RTC_NVTIM          (1 <<  0)               /* Non valid Time */
-#define         AT91_RTC_NVCAL          (1 <<  1)               /* Non valid Calendar */
-#define         AT91_RTC_NVTIMALR       (1 <<  2)               /* Non valid Time Alarm */
-#define         AT91_RTC_NVCALALR       (1 <<  3)               /* Non valid Calendar Alarm */
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91_rtt.h b/include/asm-arm/arch-at91/at91_rtt.h
deleted file mode 100644
index 39a32633b275..000000000000
--- a/include/asm-arm/arch-at91/at91_rtt.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91_rtt.h
- *
- * Real-time Timer (RTT) - System peripherals regsters.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_RTT_H
-#define AT91_RTT_H
-
-#define AT91_RTT_MR             0x00                    /* Real-time Mode Register */
-#define         AT91_RTT_RTPRES         (0xffff << 0)           /* Real-time Timer Prescaler Value */
-#define         AT91_RTT_ALMIEN         (1 << 16)               /* Alarm Interrupt Enable */
-#define         AT91_RTT_RTTINCIEN      (1 << 17)               /* Real Time Timer Increment Interrupt Enable */
-#define         AT91_RTT_RTTRST         (1 << 18)               /* Real Time Timer Restart */
-
-#define AT91_RTT_AR             0x04                    /* Real-time Alarm Register */
-#define         AT91_RTT_ALMV           (0xffffffff)            /* Alarm Value */
-
-#define AT91_RTT_VR             0x08                    /* Real-time Value Register */
-#define         AT91_RTT_CRTV           (0xffffffff)            /* Current Real-time Value */
-
-#define AT91_RTT_SR             0x0c                    /* Real-time Status Register */
-#define         AT91_RTT_ALMS           (1 << 0)                /* Real-time Alarm Status */
-#define         AT91_RTT_RTTINC         (1 << 1)                /* Real-time Timer Increment */
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91_shdwc.h b/include/asm-arm/arch-at91/at91_shdwc.h
deleted file mode 100644
index 581fa41d90e8..000000000000
--- a/include/asm-arm/arch-at91/at91_shdwc.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91_shdwc.h
- *
- * Shutdown Controller (SHDWC) - System peripherals regsters.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_SHDWC_H
-#define AT91_SHDWC_H
-
-#define AT91_SHDW_CR            (AT91_SHDWC + 0x00)     /* Shut Down Control Register */
-#define         AT91_SHDW_SHDW          (1    << 0)             /* Shut Down command */
-#define         AT91_SHDW_KEY           (0xa5 << 24)            /* KEY Password */
-
-#define AT91_SHDW_MR            (AT91_SHDWC + 0x04)     /* Shut Down Mode Register */
-#define         AT91_SHDW_WKMODE0       (3 << 0)                /* Wake-up 0 Mode Selection */
-#define                 AT91_SHDW_WKMODE0_NONE          0
-#define                 AT91_SHDW_WKMODE0_HIGH          1
-#define                 AT91_SHDW_WKMODE0_LOW           2
-#define                 AT91_SHDW_WKMODE0_ANYLEVEL      3
-#define         AT91_SHDW_CPTWK0        (0xf << 4)              /* Counter On Wake Up 0 */
-#define                 AT91_SHDW_CPTWK0_(x)    ((x) << 4)
-#define         AT91_SHDW_RTTWKEN       (1   << 16)             /* Real Time Timer Wake-up Enable */
-
-#define AT91_SHDW_SR            (AT91_SHDWC + 0x08)     /* Shut Down Status Register */
-#define         AT91_SHDW_WAKEUP0       (1 <<  0)               /* Wake-up 0 Status */
-#define         AT91_SHDW_RTTWK         (1 << 16)               /* Real-time Timer Wake-up */
-#define         AT91_SHDW_RTCWK         (1 << 17)               /* Real-time Clock Wake-up [SAM9RL] */
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91_spi.h b/include/asm-arm/arch-at91/at91_spi.h
deleted file mode 100644
index f9b9a8464997..000000000000
--- a/include/asm-arm/arch-at91/at91_spi.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91_spi.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * Serial Peripheral Interface (SPI) registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_SPI_H
-#define AT91_SPI_H
-
-#define AT91_SPI_CR                     0x00            /* Control Register */
-#define         AT91_SPI_SPIEN          (1 <<  0)               /* SPI Enable */
-#define         AT91_SPI_SPIDIS         (1 <<  1)               /* SPI Disable */
-#define         AT91_SPI_SWRST          (1 <<  7)               /* SPI Software Reset */
-#define         AT91_SPI_LASTXFER       (1 << 24)               /* Last Transfer [SAM9261 only] */
-
-#define AT91_SPI_MR                     0x04            /* Mode Register */
-#define         AT91_SPI_MSTR           (1    <<  0)            /* Master/Slave Mode */
-#define         AT91_SPI_PS             (1    <<  1)            /* Peripheral Select */
-#define                 AT91_SPI_PS_FIXED       (0 << 1)
-#define                 AT91_SPI_PS_VARIABLE    (1 << 1)
-#define         AT91_SPI_PCSDEC         (1    <<  2)            /* Chip Select Decode */
-#define         AT91_SPI_DIV32          (1    <<  3)            /* Clock Selection [AT91RM9200 only] */
-#define         AT91_SPI_MODFDIS        (1    <<  4)            /* Mode Fault Detection */
-#define         AT91_SPI_LLB            (1    <<  7)            /* Local Loopback Enable */
-#define         AT91_SPI_PCS            (0xf  << 16)            /* Peripheral Chip Select */
-#define         AT91_SPI_DLYBCS         (0xff << 24)            /* Delay Between Chip Selects */
-
-#define AT91_SPI_RDR            0x08                    /* Receive Data Register */
-#define         AT91_SPI_RD             (0xffff <<  0)          /* Receive Data */
-#define         AT91_SPI_PCS            (0xf    << 16)          /* Peripheral Chip Select */
-
-#define AT91_SPI_TDR            0x0c                    /* Transmit Data Register */
-#define         AT91_SPI_TD             (0xffff <<  0)          /* Transmit Data */
-#define         AT91_SPI_PCS            (0xf    << 16)          /* Peripheral Chip Select */
-#define         AT91_SPI_LASTXFER       (1      << 24)          /* Last Transfer [SAM9261 only] */
-
-#define AT91_SPI_SR             0x10                    /* Status Register */
-#define         AT91_SPI_RDRF           (1 <<  0)               /* Receive Data Register Full */
-#define         AT91_SPI_TDRE           (1 <<  1)               /* Transmit Data Register Full */
-#define         AT91_SPI_MODF           (1 <<  2)               /* Mode Fault Error */
-#define         AT91_SPI_OVRES          (1 <<  3)               /* Overrun Error Status */
-#define         AT91_SPI_ENDRX          (1 <<  4)               /* End of RX buffer */
-#define         AT91_SPI_ENDTX          (1 <<  5)               /* End of TX buffer */
-#define         AT91_SPI_RXBUFF         (1 <<  6)               /* RX Buffer Full */
-#define         AT91_SPI_TXBUFE         (1 <<  7)               /* TX Buffer Empty */
-#define         AT91_SPI_NSSR           (1 <<  8)               /* NSS Rising [SAM9261 only] */
-#define         AT91_SPI_TXEMPTY        (1 <<  9)               /* Transmission Register Empty [SAM9261 only] */
-#define         AT91_SPI_SPIENS         (1 << 16)               /* SPI Enable Status */
-
-#define AT91_SPI_IER            0x14                    /* Interrupt Enable Register */
-#define AT91_SPI_IDR            0x18                    /* Interrupt Disable Register */
-#define AT91_SPI_IMR            0x1c                    /* Interrupt Mask Register */
-
-#define AT91_SPI_CSR(n)         (0x30 + ((n) * 4))      /* Chip Select Registers 0-3 */
-#define         AT91_SPI_CPOL           (1    <<  0)            /* Clock Polarity */
-#define         AT91_SPI_NCPHA          (1    <<  1)            /* Clock Phase */
-#define         AT91_SPI_CSAAT          (1    <<  3)            /* Chip Select Active After Transfer [SAM9261 only] */
-#define         AT91_SPI_BITS           (0xf  <<  4)            /* Bits Per Transfer */
-#define                 AT91_SPI_BITS_8         (0 << 4)
-#define                 AT91_SPI_BITS_9         (1 << 4)
-#define                 AT91_SPI_BITS_10        (2 << 4)
-#define                 AT91_SPI_BITS_11        (3 << 4)
-#define                 AT91_SPI_BITS_12        (4 << 4)
-#define                 AT91_SPI_BITS_13        (5 << 4)
-#define                 AT91_SPI_BITS_14        (6 << 4)
-#define                 AT91_SPI_BITS_15        (7 << 4)
-#define                 AT91_SPI_BITS_16        (8 << 4)
-#define         AT91_SPI_SCBR           (0xff <<  8)            /* Serial Clock Baud Rate */
-#define         AT91_SPI_DLYBS          (0xff << 16)            /* Delay before SPCK */
-#define         AT91_SPI_DLYBCT         (0xff << 24)            /* Delay between Consecutive Transfers */
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91_ssc.h b/include/asm-arm/arch-at91/at91_ssc.h
deleted file mode 100644
index 0ecc73460b50..000000000000
--- a/include/asm-arm/arch-at91/at91_ssc.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91_ssc.h
- *
- * Copyright (C) SAN People
- *
- * Serial Synchronous Controller (SSC) registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_SSC_H
-#define AT91_SSC_H
-
-#define AT91_SSC_CR             0x00    /* Control Register */
-#define         AT91_SSC_RXEN           (1 <<  0)       /* Receive Enable */
-#define         AT91_SSC_RXDIS          (1 <<  1)       /* Receive Disable */
-#define         AT91_SSC_TXEN           (1 <<  8)       /* Transmit Enable */
-#define         AT91_SSC_TXDIS          (1 <<  9)       /* Transmit Disable */
-#define         AT91_SSC_SWRST          (1 << 15)       /* Software Reset */
-
-#define AT91_SSC_CMR            0x04    /* Clock Mode Register */
-#define         AT91_SSC_CMR_DIV        (0xfff << 0)    /* Clock Divider */
-
-#define AT91_SSC_RCMR           0x10    /* Receive Clock Mode Register */
-#define         AT91_SSC_CKS            (3    <<  0)    /* Clock Selection */
-#define                 AT91_SSC_CKS_DIV                (0 << 0)
-#define                 AT91_SSC_CKS_CLOCK              (1 << 0)
-#define                 AT91_SSC_CKS_PIN                (2 << 0)
-#define         AT91_SSC_CKO            (7    <<  2)    /* Clock Output Mode Selection */
-#define                 AT91_SSC_CKO_NONE               (0 << 2)
-#define                 AT91_SSC_CKO_CONTINUOUS         (1 << 2)
-#define         AT91_SSC_CKI            (1    <<  5)    /* Clock Inversion */
-#define                 AT91_SSC_CKI_FALLING            (0 << 5)
-#define                 AT91_SSC_CK_RISING              (1 << 5)
-#define         AT91_SSC_CKG            (1    <<  6)    /* Receive Clock Gating Selection [AT91SAM9261 only] */
-#define                 AT91_SSC_CKG_NONE               (0 << 6)
-#define                 AT91_SSC_CKG_RFLOW              (1 << 6)
-#define                 AT91_SSC_CKG_RFHIGH             (2 << 6)
-#define         AT91_SSC_START          (0xf  <<  8)    /* Start Selection */
-#define                 AT91_SSC_START_CONTINUOUS       (0 << 8)
-#define                 AT91_SSC_START_TX_RX            (1 << 8)
-#define                 AT91_SSC_START_LOW_RF           (2 << 8)
-#define                 AT91_SSC_START_HIGH_RF          (3 << 8)
-#define                 AT91_SSC_START_FALLING_RF       (4 << 8)
-#define                 AT91_SSC_START_RISING_RF        (5 << 8)
-#define                 AT91_SSC_START_LEVEL_RF         (6 << 8)
-#define                 AT91_SSC_START_EDGE_RF          (7 << 8)
-#define         AT91_SSC_STOP           (1    << 12)    /* Receive Stop Selection [AT91SAM9261 only] */
-#define         AT91_SSC_STTDLY         (0xff << 16)    /* Start Delay */
-#define         AT91_SSC_PERIOD         (0xff << 24)    /* Period Divider Selection */
-
-#define AT91_SSC_RFMR           0x14    /* Receive Frame Mode Register */
-#define         AT91_SSC_DATALEN        (0x1f <<  0)    /* Data Length */
-#define         AT91_SSC_LOOP           (1    <<  5)    /* Loop Mode */
-#define         AT91_SSC_MSBF           (1    <<  7)    /* Most Significant Bit First */
-#define         AT91_SSC_DATNB          (0xf  <<  8)    /* Data Number per Frame */
-#define         AT91_SSC_FSLEN          (0xf  << 16)    /* Frame Sync Length */
-#define         AT91_SSC_FSOS           (7    << 20)    /* Frame Sync Output Selection */
-#define                 AT91_SSC_FSOS_NONE              (0 << 20)
-#define                 AT91_SSC_FSOS_NEGATIVE          (1 << 20)
-#define                 AT91_SSC_FSOS_POSITIVE          (2 << 20)
-#define                 AT91_SSC_FSOS_LOW               (3 << 20)
-#define                 AT91_SSC_FSOS_HIGH              (4 << 20)
-#define                 AT91_SSC_FSOS_TOGGLE            (5 << 20)
-#define         AT91_SSC_FSEDGE         (1    << 24)    /* Frame Sync Edge Detection */
-#define                 AT91_SSC_FSEDGE_POSITIVE        (0 << 24)
-#define                 AT91_SSC_FSEDGE_NEGATIVE        (1 << 24)
-
-#define AT91_SSC_TCMR           0x18    /* Transmit Clock Mode Register */
-#define AT91_SSC_TFMR           0x1c    /* Transmit Fram Mode Register */
-#define         AT91_SSC_DATDEF         (1 <<  5)       /* Data Default Value */
-#define         AT91_SSC_FSDEN          (1 << 23)       /* Frame Sync Data Enable */
-
-#define AT91_SSC_RHR            0x20    /* Receive Holding Register */
-#define AT91_SSC_THR            0x24    /* Transmit Holding Register */
-#define AT91_SSC_RSHR           0x30    /* Receive Sync Holding Register */
-#define AT91_SSC_TSHR           0x34    /* Transmit Sync Holding Register */
-
-#define AT91_SSC_RC0R           0x38    /* Receive Compare 0 Register [AT91SAM9261 only] */
-#define AT91_SSC_RC1R           0x3c    /* Receive Compare 1 Register [AT91SAM9261 only] */
-
-#define AT91_SSC_SR             0x40    /* Status Register */
-#define         AT91_SSC_TXRDY          (1 <<  0)       /* Transmit Ready */
-#define         AT91_SSC_TXEMPTY        (1 <<  1)       /* Transmit Empty */
-#define         AT91_SSC_ENDTX          (1 <<  2)       /* End of Transmission */
-#define         AT91_SSC_TXBUFE         (1 <<  3)       /* Transmit Buffer Empty */
-#define         AT91_SSC_RXRDY          (1 <<  4)       /* Receive Ready */
-#define         AT91_SSC_OVRUN          (1 <<  5)       /* Receive Overrun */
-#define         AT91_SSC_ENDRX          (1 <<  6)       /* End of Reception */
-#define         AT91_SSC_RXBUFF         (1 <<  7)       /* Receive Buffer Full */
-#define         AT91_SSC_CP0            (1 <<  8)       /* Compare 0 [AT91SAM9261 only] */
-#define         AT91_SSC_CP1            (1 <<  9)       /* Compare 1 [AT91SAM9261 only] */
-#define         AT91_SSC_TXSYN          (1 << 10)       /* Transmit Sync */
-#define         AT91_SSC_RXSYN          (1 << 11)       /* Receive Sync */
-#define         AT91_SSC_TXENA          (1 << 16)       /* Transmit Enable */
-#define         AT91_SSC_RXENA          (1 << 17)       /* Receive Enable */
-
-#define AT91_SSC_IER            0x44    /* Interrupt Enable Register */
-#define AT91_SSC_IDR            0x48    /* Interrupt Disable Register */
-#define AT91_SSC_IMR            0x4c    /* Interrupt Mask Register */
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91_st.h b/include/asm-arm/arch-at91/at91_st.h
deleted file mode 100644
index 30446e2ea772..000000000000
--- a/include/asm-arm/arch-at91/at91_st.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91_st.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * System Timer (ST) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_ST_H
-#define AT91_ST_H
-
-#define AT91_ST_CR              (AT91_ST + 0x00)        /* Control Register */
-#define         AT91_ST_WDRST           (1 << 0)                /* Watchdog Timer Restart */
-
-#define AT91_ST_PIMR            (AT91_ST + 0x04)        /* Period Interval Mode Register */
-#define         AT91_ST_PIV             (0xffff <<  0)          /* Period Interval Value */
-
-#define AT91_ST_WDMR            (AT91_ST + 0x08)        /* Watchdog Mode Register */
-#define         AT91_ST_WDV             (0xffff <<  0)          /* Watchdog Counter Value */
-#define         AT91_ST_RSTEN           (1      << 16)          /* Reset Enable */
-#define         AT91_ST_EXTEN           (1      << 17)          /* External Signal Assertion Enable */
-
-#define AT91_ST_RTMR            (AT91_ST + 0x0c)        /* Real-time Mode Register */
-#define         AT91_ST_RTPRES          (0xffff <<  0)          /* Real-time Prescalar Value */
-
-#define AT91_ST_SR              (AT91_ST + 0x10)        /* Status Register */
-#define         AT91_ST_PITS            (1 << 0)                /* Period Interval Timer Status */
-#define         AT91_ST_WDOVF           (1 << 1)                /* Watchdog Overflow */
-#define         AT91_ST_RTTINC          (1 << 2)                /* Real-time Timer Increment */
-#define         AT91_ST_ALMS            (1 << 3)                /* Alarm Status */
-
-#define AT91_ST_IER             (AT91_ST + 0x14)        /* Interrupt Enable Register */
-#define AT91_ST_IDR             (AT91_ST + 0x18)        /* Interrupt Disable Register */
-#define AT91_ST_IMR             (AT91_ST + 0x1c)        /* Interrupt Mask Register */
-
-#define AT91_ST_RTAR            (AT91_ST + 0x20)        /* Real-time Alarm Register */
-#define         AT91_ST_ALMV            (0xfffff << 0)          /* Alarm Value */
-
-#define AT91_ST_CRTR            (AT91_ST + 0x24)        /* Current Real-time Register */
-#define         AT91_ST_CRTV            (0xfffff << 0)          /* Current Real-Time Value */
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91_tc.h b/include/asm-arm/arch-at91/at91_tc.h
deleted file mode 100644
index b85d3faeef5c..000000000000
--- a/include/asm-arm/arch-at91/at91_tc.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91_tc.h
- *
- * Copyright (C) SAN People
- *
- * Timer/Counter Unit (TC) registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_TC_H
-#define AT91_TC_H
-
-#define AT91_TC_BCR             0xc0            /* TC Block Control Register */
-#define         AT91_TC_SYNC            (1 << 0)        /* Synchro Command */
-
-#define AT91_TC_BMR             0xc4            /* TC Block Mode Register */
-#define         AT91_TC_TC0XC0S         (3 << 0)        /* External Clock Signal 0 Selection */
-#define                 AT91_TC_TC0XC0S_TCLK0           (0 << 0)
-#define                 AT91_TC_TC0XC0S_NONE            (1 << 0)
-#define                 AT91_TC_TC0XC0S_TIOA1           (2 << 0)
-#define                 AT91_TC_TC0XC0S_TIOA2           (3 << 0)
-#define         AT91_TC_TC1XC1S         (3 << 2)        /* External Clock Signal 1 Selection */
-#define                 AT91_TC_TC1XC1S_TCLK1           (0 << 2)
-#define                 AT91_TC_TC1XC1S_NONE            (1 << 2)
-#define                 AT91_TC_TC1XC1S_TIOA0           (2 << 2)
-#define                 AT91_TC_TC1XC1S_TIOA2           (3 << 2)
-#define         AT91_TC_TC2XC2S         (3 << 4)        /* External Clock Signal 2 Selection */
-#define                 AT91_TC_TC2XC2S_TCLK2           (0 << 4)
-#define                 AT91_TC_TC2XC2S_NONE            (1 << 4)
-#define                 AT91_TC_TC2XC2S_TIOA0           (2 << 4)
-#define                 AT91_TC_TC2XC2S_TIOA1           (3 << 4)
-
-
-#define AT91_TC_CCR             0x00            /* Channel Control Register */
-#define         AT91_TC_CLKEN           (1 << 0)        /* Counter Clock Enable Command */
-#define         AT91_TC_CLKDIS          (1 << 1)        /* Counter CLock Disable Command */
-#define         AT91_TC_SWTRG           (1 << 2)        /* Software Trigger Command */
-
-#define AT91_TC_CMR             0x04            /* Channel Mode Register */
-#define         AT91_TC_TCCLKS          (7 << 0)        /* Capture/Waveform Mode: Clock Selection */
-#define                 AT91_TC_TIMER_CLOCK1            (0 << 0)
-#define                 AT91_TC_TIMER_CLOCK2            (1 << 0)
-#define                 AT91_TC_TIMER_CLOCK3            (2 << 0)
-#define                 AT91_TC_TIMER_CLOCK4            (3 << 0)
-#define                 AT91_TC_TIMER_CLOCK5            (4 << 0)
-#define                 AT91_TC_XC0                     (5 << 0)
-#define                 AT91_TC_XC1                     (6 << 0)
-#define                 AT91_TC_XC2                     (7 << 0)
-#define         AT91_TC_CLKI            (1 << 3)        /* Capture/Waveform Mode: Clock Invert */
-#define         AT91_TC_BURST           (3 << 4)        /* Capture/Waveform Mode: Burst Signal Selection */
-#define         AT91_TC_LDBSTOP         (1 << 6)        /* Capture Mode: Counter Clock Stopped with TB Loading */
-#define         AT91_TC_LDBDIS          (1 << 7)        /* Capture Mode: Counter Clock Disable with RB Loading */
-#define         AT91_TC_ETRGEDG         (3 << 8)        /* Capture Mode: External Trigger Edge Selection */
-#define         AT91_TC_ABETRG          (1 << 10)       /* Capture Mode: TIOA or TIOB External Trigger Selection */
-#define         AT91_TC_CPCTRG          (1 << 14)       /* Capture Mode: RC Compare Trigger Enable */
-#define         AT91_TC_WAVE            (1 << 15)       /* Capture/Waveform mode */
-#define         AT91_TC_LDRA            (3 << 16)       /* Capture Mode: RA Loading Selection */
-#define         AT91_TC_LDRB            (3 << 18)       /* Capture Mode: RB Loading Selection */
-
-#define         AT91_TC_CPCSTOP         (1 <<  6)       /* Waveform Mode: Counter Clock Stopped with RC Compare */
-#define         AT91_TC_CPCDIS          (1 <<  7)       /* Waveform Mode: Counter Clock Disable with RC Compare */
-#define         AT91_TC_EEVTEDG         (3 <<  8)       /* Waveform Mode: External Event Edge Selection */
-#define                 AT91_TC_EEVTEDG_NONE            (0 << 8)
-#define                 AT91_TC_EEVTEDG_RISING          (1 << 8)
-#define                 AT91_TC_EEVTEDG_FALLING         (2 << 8)
-#define                 AT91_TC_EEVTEDG_BOTH            (3 << 8)
-#define         AT91_TC_EEVT            (3 << 10)       /* Waveform Mode: External Event Selection */
-#define                 AT91_TC_EEVT_TIOB               (0 << 10)
-#define                 AT91_TC_EEVT_XC0                (1 << 10)
-#define                 AT91_TC_EEVT_XC1                (2 << 10)
-#define                 AT91_TC_EEVT_XC2                (3 << 10)
-#define         AT91_TC_ENETRG          (1 << 12)       /* Waveform Mode: External Event Trigger Enable */
-#define         AT91_TC_WAVESEL         (3 << 13)       /* Waveform Mode: Waveform Selection */
-#define                 AT91_TC_WAVESEL_UP              (0 << 13)
-#define                 AT91_TC_WAVESEL_UP_AUTO         (2 << 13)
-#define                 AT91_TC_WAVESEL_UPDOWN          (1 << 13)
-#define                 AT91_TC_WAVESEL_UPDOWN_AUTO     (3 << 13)
-#define         AT91_TC_ACPA            (3 << 16)       /* Waveform Mode: RA Compare Effect on TIOA */
-#define                 AT91_TC_ACPA_NONE               (0 << 16)
-#define                 AT91_TC_ACPA_SET                (1 << 16)
-#define                 AT91_TC_ACPA_CLEAR              (2 << 16)
-#define                 AT91_TC_ACPA_TOGGLE             (3 << 16)
-#define         AT91_TC_ACPC            (3 << 18)       /* Waveform Mode: RC Compre Effect on TIOA */
-#define                 AT91_TC_ACPC_NONE               (0 << 18)
-#define                 AT91_TC_ACPC_SET                (1 << 18)
-#define                 AT91_TC_ACPC_CLEAR              (2 << 18)
-#define                 AT91_TC_ACPC_TOGGLE             (3 << 18)
-#define         AT91_TC_AEEVT           (3 << 20)       /* Waveform Mode: External Event Effect on TIOA */
-#define                 AT91_TC_AEEVT_NONE              (0 << 20)
-#define                 AT91_TC_AEEVT_SET               (1 << 20)
-#define                 AT91_TC_AEEVT_CLEAR             (2 << 20)
-#define                 AT91_TC_AEEVT_TOGGLE            (3 << 20)
-#define         AT91_TC_ASWTRG          (3 << 22)       /* Waveform Mode: Software Trigger Effect on TIOA */
-#define                 AT91_TC_ASWTRG_NONE             (0 << 22)
-#define                 AT91_TC_ASWTRG_SET              (1 << 22)
-#define                 AT91_TC_ASWTRG_CLEAR            (2 << 22)
-#define                 AT91_TC_ASWTRG_TOGGLE           (3 << 22)
-#define         AT91_TC_BCPB            (3 << 24)       /* Waveform Mode: RB Compare Effect on TIOB */
-#define                 AT91_TC_BCPB_NONE               (0 << 24)
-#define                 AT91_TC_BCPB_SET                (1 << 24)
-#define                 AT91_TC_BCPB_CLEAR              (2 << 24)
-#define                 AT91_TC_BCPB_TOGGLE             (3 << 24)
-#define         AT91_TC_BCPC            (3 << 26)       /* Waveform Mode: RC Compare Effect on TIOB */
-#define                 AT91_TC_BCPC_NONE               (0 << 26)
-#define                 AT91_TC_BCPC_SET                (1 << 26)
-#define                 AT91_TC_BCPC_CLEAR              (2 << 26)
-#define                 AT91_TC_BCPC_TOGGLE             (3 << 26)
-#define         AT91_TC_BEEVT           (3 << 28)       /* Waveform Mode: External Event Effect on TIOB */
-#define                 AT91_TC_BEEVT_NONE              (0 << 28)
-#define                 AT91_TC_BEEVT_SET               (1 << 28)
-#define                 AT91_TC_BEEVT_CLEAR             (2 << 28)
-#define                 AT91_TC_BEEVT_TOGGLE            (3 << 28)
-#define         AT91_TC_BSWTRG          (3 << 30)       /* Waveform Mode: Software Trigger Effect on TIOB */
-#define                 AT91_TC_BSWTRG_NONE             (0 << 30)
-#define                 AT91_TC_BSWTRG_SET              (1 << 30)
-#define                 AT91_TC_BSWTRG_CLEAR            (2 << 30)
-#define                 AT91_TC_BSWTRG_TOGGLE           (3 << 30)
-
-#define AT91_TC_CV              0x10            /* Counter Value */
-#define AT91_TC_RA              0x14            /* Register A */
-#define AT91_TC_RB              0x18            /* Register B */
-#define AT91_TC_RC              0x1c            /* Register C */
-
-#define AT91_TC_SR              0x20            /* Status Register */
-#define         AT91_TC_COVFS           (1 <<  0)       /* Counter Overflow Status */
-#define         AT91_TC_LOVRS           (1 <<  1)       /* Load Overrun Status */
-#define         AT91_TC_CPAS            (1 <<  2)       /* RA Compare Status */
-#define         AT91_TC_CPBS            (1 <<  3)       /* RB Compare Status */
-#define         AT91_TC_CPCS            (1 <<  4)       /* RC Compare Status */
-#define         AT91_TC_LDRAS           (1 <<  5)       /* RA Loading Status */
-#define         AT91_TC_LDRBS           (1 <<  6)       /* RB Loading Status */
-#define         AT91_TC_ETRGS           (1 <<  7)       /* External Trigger Status */
-#define         AT91_TC_CLKSTA          (1 << 16)       /* Clock Enabling Status */
-#define         AT91_TC_MTIOA           (1 << 17)       /* TIOA Mirror */
-#define         AT91_TC_MTIOB           (1 << 18)       /* TIOB Mirror */
-
-#define AT91_TC_IER             0x24            /* Interrupt Enable Register */
-#define AT91_TC_IDR             0x28            /* Interrupt Disable Register */
-#define AT91_TC_IMR             0x2c            /* Interrupt Mask Register */
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91_twi.h b/include/asm-arm/arch-at91/at91_twi.h
deleted file mode 100644
index f9f2e3cd95c5..000000000000
--- a/include/asm-arm/arch-at91/at91_twi.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91_twi.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * Two-wire Interface (TWI) registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_TWI_H
-#define AT91_TWI_H
-
-#define AT91_TWI_CR             0x00            /* Control Register */
-#define         AT91_TWI_START          (1 <<  0)       /* Send a Start Condition */
-#define         AT91_TWI_STOP           (1 <<  1)       /* Send a Stop Condition */
-#define         AT91_TWI_MSEN           (1 <<  2)       /* Master Transfer Enable */
-#define         AT91_TWI_MSDIS          (1 <<  3)       /* Master Transfer Disable */
-#define         AT91_TWI_SVEN           (1 <<  4)       /* Slave Transfer Enable [SAM9260 only] */
-#define         AT91_TWI_SVDIS          (1 <<  5)       /* Slave Transfer Disable [SAM9260 only] */
-#define         AT91_TWI_SWRST          (1 <<  7)       /* Software Reset */
-
-#define AT91_TWI_MMR            0x04            /* Master Mode Register */
-#define         AT91_TWI_IADRSZ         (3    <<  8)    /* Internal Device Address Size */
-#define                 AT91_TWI_IADRSZ_NO              (0 << 8)
-#define                 AT91_TWI_IADRSZ_1               (1 << 8)
-#define                 AT91_TWI_IADRSZ_2               (2 << 8)
-#define                 AT91_TWI_IADRSZ_3               (3 << 8)
-#define         AT91_TWI_MREAD          (1    << 12)    /* Master Read Direction */
-#define         AT91_TWI_DADR           (0x7f << 16)    /* Device Address */
-
-#define AT91_TWI_SMR            0x08            /* Slave Mode Register [SAM9260 only] */
-#define         AT91_TWI_SADR           (0x7f << 16)    /* Slave Address */
-
-#define AT91_TWI_IADR           0x0c            /* Internal Address Register */
-
-#define AT91_TWI_CWGR           0x10            /* Clock Waveform Generator Register */
-#define         AT91_TWI_CLDIV          (0xff <<  0)    /* Clock Low Divisor */
-#define         AT91_TWI_CHDIV          (0xff <<  8)    /* Clock High Divisor */
-#define         AT91_TWI_CKDIV          (7    << 16)    /* Clock Divider */
-
-#define AT91_TWI_SR             0x20            /* Status Register */
-#define         AT91_TWI_TXCOMP         (1 <<  0)       /* Transmission Complete */
-#define         AT91_TWI_RXRDY          (1 <<  1)       /* Receive Holding Register Ready */
-#define         AT91_TWI_TXRDY          (1 <<  2)       /* Transmit Holding Register Ready */
-#define         AT91_TWI_SVREAD         (1 <<  3)       /* Slave Read [SAM9260 only] */
-#define         AT91_TWI_SVACC          (1 <<  4)       /* Slave Access [SAM9260 only] */
-#define         AT91_TWI_GACC           (1 <<  5)       /* General Call Access [SAM9260 only] */
-#define         AT91_TWI_OVRE           (1 <<  6)       /* Overrun Error [AT91RM9200 only] */
-#define         AT91_TWI_UNRE           (1 <<  7)       /* Underrun Error [AT91RM9200 only] */
-#define         AT91_TWI_NACK           (1 <<  8)       /* Not Acknowledged */
-#define         AT91_TWI_ARBLST         (1 <<  9)       /* Arbitration Lost [SAM9260 only] */
-#define         AT91_TWI_SCLWS          (1 << 10)       /* Clock Wait State [SAM9260 only] */
-#define         AT91_TWI_EOSACC         (1 << 11)       /* End of Slave Address [SAM9260 only] */
-
-#define AT91_TWI_IER            0x24            /* Interrupt Enable Register */
-#define AT91_TWI_IDR            0x28            /* Interrupt Disable Register */
-#define AT91_TWI_IMR            0x2c            /* Interrupt Mask Register */
-#define AT91_TWI_RHR            0x30            /* Receive Holding Register */
-#define AT91_TWI_THR            0x34            /* Transmit Holding Register */
-
-#endif
-
diff --git a/include/asm-arm/arch-at91/at91_wdt.h b/include/asm-arm/arch-at91/at91_wdt.h
deleted file mode 100644
index 1014e9bf181f..000000000000
--- a/include/asm-arm/arch-at91/at91_wdt.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91_wdt.h
- *
- * Watchdog Timer (WDT) - System peripherals regsters.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_WDT_H
-#define AT91_WDT_H
-
-#define AT91_WDT_CR             (AT91_WDT + 0x00)       /* Watchdog Control Register */
-#define         AT91_WDT_WDRSTT         (1    << 0)             /* Restart */
-#define         AT91_WDT_KEY            (0xa5 << 24)            /* KEY Password */
-
-#define AT91_WDT_MR             (AT91_WDT + 0x04)       /* Watchdog Mode Register */
-#define         AT91_WDT_WDV            (0xfff << 0)            /* Counter Value */
-#define         AT91_WDT_WDFIEN         (1     << 12)           /* Fault Interrupt Enable */
-#define         AT91_WDT_WDRSTEN        (1     << 13)           /* Reset Processor */
-#define         AT91_WDT_WDRPROC        (1     << 14)           /* Timer Restart */
-#define         AT91_WDT_WDDIS          (1     << 15)           /* Watchdog Disable */
-#define         AT91_WDT_WDD            (0xfff << 16)           /* Delta Value */
-#define         AT91_WDT_WDDBGHLT       (1     << 28)           /* Debug Halt */
-#define         AT91_WDT_WDIDLEHLT      (1     << 29)           /* Idle Halt */
-
-#define AT91_WDT_SR             (AT91_WDT + 0x08)       /* Watchdog Status Register */
-#define         AT91_WDT_WDUNF          (1 << 0)                /* Watchdog Underflow */
-#define         AT91_WDT_WDERR          (1 << 1)                /* Watchdog Error */
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91cap9.h b/include/asm-arm/arch-at91/at91cap9.h
deleted file mode 100644
index 6f14d9053ac7..000000000000
--- a/include/asm-arm/arch-at91/at91cap9.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91cap9.h
- *
- *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
- *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
- *  Copyright (C) 2007 Atmel Corporation.
- *
- * Common definitions.
- * Based on AT91CAP9 datasheet revision B (Preliminary).
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91CAP9_H
-#define AT91CAP9_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS             1       /* System Peripherals */
-#define AT91CAP9_ID_PIOABCD     2       /* Parallel IO Controller A, B, C and D */
-#define AT91CAP9_ID_MPB0        3       /* MP Block Peripheral 0 */
-#define AT91CAP9_ID_MPB1        4       /* MP Block Peripheral 1 */
-#define AT91CAP9_ID_MPB2        5       /* MP Block Peripheral 2 */
-#define AT91CAP9_ID_MPB3        6       /* MP Block Peripheral 3 */
-#define AT91CAP9_ID_MPB4        7       /* MP Block Peripheral 4 */
-#define AT91CAP9_ID_US0         8       /* USART 0 */
-#define AT91CAP9_ID_US1         9       /* USART 1 */
-#define AT91CAP9_ID_US2         10      /* USART 2 */
-#define AT91CAP9_ID_MCI0        11      /* Multimedia Card Interface 0 */
-#define AT91CAP9_ID_MCI1        12      /* Multimedia Card Interface 1 */
-#define AT91CAP9_ID_CAN         13      /* CAN */
-#define AT91CAP9_ID_TWI         14      /* Two-Wire Interface */
-#define AT91CAP9_ID_SPI0        15      /* Serial Peripheral Interface 0 */
-#define AT91CAP9_ID_SPI1        16      /* Serial Peripheral Interface 0 */
-#define AT91CAP9_ID_SSC0        17      /* Serial Synchronous Controller 0 */
-#define AT91CAP9_ID_SSC1        18      /* Serial Synchronous Controller 1 */
-#define AT91CAP9_ID_AC97C       19      /* AC97 Controller */
-#define AT91CAP9_ID_TCB         20      /* Timer Counter 0, 1 and 2 */
-#define AT91CAP9_ID_PWMC        21      /* Pulse Width Modulation Controller */
-#define AT91CAP9_ID_EMAC        22      /* Ethernet */
-#define AT91CAP9_ID_AESTDES     23      /* Advanced Encryption Standard, Triple DES */
-#define AT91CAP9_ID_ADC         24      /* Analog-to-Digital Converter */
-#define AT91CAP9_ID_ISI         25      /* Image Sensor Interface */
-#define AT91CAP9_ID_LCDC        26      /* LCD Controller */
-#define AT91CAP9_ID_DMA         27      /* DMA Controller */
-#define AT91CAP9_ID_UDPHS       28      /* USB High Speed Device Port */
-#define AT91CAP9_ID_UHP         29      /* USB Host Port */
-#define AT91CAP9_ID_IRQ0        30      /* Advanced Interrupt Controller (IRQ0) */
-#define AT91CAP9_ID_IRQ1        31      /* Advanced Interrupt Controller (IRQ1) */
-
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91CAP9_BASE_UDPHS             0xfff78000
-#define AT91CAP9_BASE_TCB0              0xfff7c000
-#define AT91CAP9_BASE_TC0               0xfff7c000
-#define AT91CAP9_BASE_TC1               0xfff7c040
-#define AT91CAP9_BASE_TC2               0xfff7c080
-#define AT91CAP9_BASE_MCI0              0xfff80000
-#define AT91CAP9_BASE_MCI1              0xfff84000
-#define AT91CAP9_BASE_TWI               0xfff88000
-#define AT91CAP9_BASE_US0               0xfff8c000
-#define AT91CAP9_BASE_US1               0xfff90000
-#define AT91CAP9_BASE_US2               0xfff94000
-#define AT91CAP9_BASE_SSC0              0xfff98000
-#define AT91CAP9_BASE_SSC1              0xfff9c000
-#define AT91CAP9_BASE_AC97C             0xfffa0000
-#define AT91CAP9_BASE_SPI0              0xfffa4000
-#define AT91CAP9_BASE_SPI1              0xfffa8000
-#define AT91CAP9_BASE_CAN               0xfffac000
-#define AT91CAP9_BASE_PWMC              0xfffb8000
-#define AT91CAP9_BASE_EMAC              0xfffbc000
-#define AT91CAP9_BASE_ADC               0xfffc0000
-#define AT91CAP9_BASE_ISI               0xfffc4000
-#define AT91_BASE_SYS                   0xffffe200
-
-/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_ECC        (0xffffe200 - AT91_BASE_SYS)
-#define AT91_BCRAMC     (0xffffe400 - AT91_BASE_SYS)
-#define AT91_DDRSDRC    (0xffffe600 - AT91_BASE_SYS)
-#define AT91_SMC        (0xffffe800 - AT91_BASE_SYS)
-#define AT91_MATRIX     (0xffffea00 - AT91_BASE_SYS)
-#define AT91_CCFG       (0xffffeb10 - AT91_BASE_SYS)
-#define AT91_DMA        (0xffffec00 - AT91_BASE_SYS)
-#define AT91_DBGU       (0xffffee00 - AT91_BASE_SYS)
-#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
-#define AT91_PIOA       (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOB       (0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOC       (0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOD       (0xfffff800 - AT91_BASE_SYS)
-#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC      (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT        (0xfffffd20 - AT91_BASE_SYS)
-#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
-#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
-#define AT91_GPBR       (0xfffffd50 - AT91_BASE_SYS)
-
-#define AT91_USART0     AT91CAP9_BASE_US0
-#define AT91_USART1     AT91CAP9_BASE_US1
-#define AT91_USART2     AT91CAP9_BASE_US2
-
-
-/*
- * Internal Memory.
- */
-#define AT91CAP9_SRAM_BASE      0x00100000      /* Internal SRAM base address */
-#define AT91CAP9_SRAM_SIZE      (32 * SZ_1K)    /* Internal SRAM size (32Kb) */
-
-#define AT91CAP9_ROM_BASE       0x00400000      /* Internal ROM base address */
-#define AT91CAP9_ROM_SIZE       (32 * SZ_1K)    /* Internal ROM size (32Kb) */
-
-#define AT91CAP9_LCDC_BASE      0x00500000      /* LCD Controller */
-#define AT91CAP9_UDPHS_FIFO     0x00600000      /* USB High Speed Device Port */
-#define AT91CAP9_UHP_BASE       0x00700000      /* USB Host controller */
-
-#define CONFIG_DRAM_BASE        AT91_CHIPSELECT_6
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91cap9_ddrsdr.h b/include/asm-arm/arch-at91/at91cap9_ddrsdr.h
deleted file mode 100644
index efdb23af1ee4..000000000000
--- a/include/asm-arm/arch-at91/at91cap9_ddrsdr.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91cap9_ddrsdr.h
- *
- * DDR/SDR Controller (DDRSDRC) - System peripherals registers.
- * Based on AT91CAP9 datasheet revision B.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91CAP9_DDRSDR_H
-#define AT91CAP9_DDRSDR_H
-
-#define AT91_DDRSDRC_MR         (AT91_DDRSDRC + 0x00)   /* Mode Register */
-#define         AT91_DDRSDRC_MODE       (0xf << 0)              /* Command Mode */
-#define                 AT91_DDRSDRC_MODE_NORMAL                0
-#define                 AT91_DDRSDRC_MODE_NOP           1
-#define                 AT91_DDRSDRC_MODE_PRECHARGE     2
-#define                 AT91_DDRSDRC_MODE_LMR           3
-#define                 AT91_DDRSDRC_MODE_REFRESH       4
-#define                 AT91_DDRSDRC_MODE_EXT_LMR       5
-#define                 AT91_DDRSDRC_MODE_DEEP          6
-
-#define AT91_DDRSDRC_RTR        (AT91_DDRSDRC + 0x04)   /* Refresh Timer Register */
-#define         AT91_DDRSDRC_COUNT      (0xfff << 0)            /* Refresh Timer Counter */
-
-#define AT91_DDRSDRC_CR         (AT91_DDRSDRC + 0x08)   /* Configuration Register */
-#define         AT91_DDRSDRC_NC         (3 << 0)                /* Number of Column Bits */
-#define                 AT91_DDRSDRC_NC_SDR8    (0 << 0)
-#define                 AT91_DDRSDRC_NC_SDR9    (1 << 0)
-#define                 AT91_DDRSDRC_NC_SDR10   (2 << 0)
-#define                 AT91_DDRSDRC_NC_SDR11   (3 << 0)
-#define                 AT91_DDRSDRC_NC_DDR9    (0 << 0)
-#define                 AT91_DDRSDRC_NC_DDR10   (1 << 0)
-#define                 AT91_DDRSDRC_NC_DDR11   (2 << 0)
-#define                 AT91_DDRSDRC_NC_DDR12   (3 << 0)
-#define         AT91_DDRSDRC_NR         (3 << 2)                /* Number of Row Bits */
-#define                 AT91_DDRSDRC_NR_11      (0 << 2)
-#define                 AT91_DDRSDRC_NR_12      (1 << 2)
-#define                 AT91_DDRSDRC_NR_13      (2 << 2)
-#define         AT91_DDRSDRC_CAS        (7 << 4)                /* CAS Latency */
-#define                 AT91_DDRSDRC_CAS_2      (2 << 4)
-#define                 AT91_DDRSDRC_CAS_3      (3 << 4)
-#define                 AT91_DDRSDRC_CAS_25     (6 << 4)
-#define         AT91_DDRSDRC_DLL        (1 << 7)                /* Reset DLL */
-#define         AT91_DDRSDRC_DICDS      (1 << 8)                /* Output impedance control */
-
-#define AT91_DDRSDRC_T0PR       (AT91_DDRSDRC + 0x0C)   /* Timing 0 Register */
-#define         AT91_DDRSDRC_TRAS       (0xf <<  0)             /* Active to Precharge delay */
-#define         AT91_DDRSDRC_TRCD       (0xf <<  4)             /* Row to Column delay */
-#define         AT91_DDRSDRC_TWR        (0xf <<  8)             /* Write recovery delay */
-#define         AT91_DDRSDRC_TRC        (0xf << 12)             /* Row cycle delay */
-#define         AT91_DDRSDRC_TRP        (0xf << 16)             /* Row precharge delay */
-#define         AT91_DDRSDRC_TRRD       (0xf << 20)             /* Active BankA to BankB */
-#define         AT91_DDRSDRC_TWTR       (1   << 24)             /* Internal Write to Read delay */
-#define         AT91_DDRSDRC_TMRD       (0xf << 28)             /* Load mode to active/refresh delay */
-
-#define AT91_DDRSDRC_T1PR       (AT91_DDRSDRC + 0x10)   /* Timing 1 Register */
-#define         AT91_DDRSDRC_TRFC       (0x1f << 0)             /* Row Cycle Delay */
-#define         AT91_DDRSDRC_TXSNR      (0xff << 8)             /* Exit self-refresh to non-read */
-#define         AT91_DDRSDRC_TXSRD      (0xff << 16)            /* Exit self-refresh to read */
-#define         AT91_DDRSDRC_TXP        (0xf  << 24)            /* Exit power-down delay */
-
-#define AT91_DDRSDRC_LPR        (AT91_DDRSDRC + 0x18)   /* Low Power Register */
-#define         AT91_DDRSDRC_LPCB               (3 << 0)        /* Low-power Configurations */
-#define                 AT91_DDRSDRC_LPCB_DISABLE               0
-#define                 AT91_DDRSDRC_LPCB_SELF_REFRESH          1
-#define                 AT91_DDRSDRC_LPCB_POWER_DOWN            2
-#define                 AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN       3
-#define         AT91_DDRSDRC_CLKFR              (1 << 2)        /* Clock Frozen */
-#define         AT91_DDRSDRC_PASR               (7 << 4)        /* Partial Array Self Refresh */
-#define         AT91_DDRSDRC_TCSR               (3 << 8)        /* Temperature Compensated Self Refresh */
-#define         AT91_DDRSDRC_DS                 (3 << 10)       /* Drive Strength */
-#define         AT91_DDRSDRC_TIMEOUT            (3 << 12)       /* Time to define when Low Power Mode is enabled */
-#define                 AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES       (0 << 12)
-#define                 AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES      (1 << 12)
-#define                 AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES     (2 << 12)
-
-#define AT91_DDRSDRC_MDR        (AT91_DDRSDRC + 0x1C)   /* Memory Device Register */
-#define         AT91_DDRSDRC_MD         (3 << 0)                /* Memory Device Type */
-#define                 AT91_DDRSDRC_MD_SDR             0
-#define                 AT91_DDRSDRC_MD_LOW_POWER_SDR   1
-#define                 AT91_DDRSDRC_MD_DDR             2
-#define                 AT91_DDRSDRC_MD_LOW_POWER_DDR   3
-
-#define AT91_DDRSDRC_DLLR       (AT91_DDRSDRC + 0x20)   /* DLL Information Register */
-#define         AT91_DDRSDRC_MDINC      (1 << 0)                /* Master Delay increment */
-#define         AT91_DDRSDRC_MDDEC      (1 << 1)                /* Master Delay decrement */
-#define         AT91_DDRSDRC_MDOVF      (1 << 2)                /* Master Delay Overflow */
-#define         AT91_DDRSDRC_SDCOVF     (1 << 3)                /* Slave Delay Correction Overflow */
-#define         AT91_DDRSDRC_SDCUDF     (1 << 4)                /* Slave Delay Correction Underflow */
-#define         AT91_DDRSDRC_SDERF      (1 << 5)                /* Slave Delay Correction error */
-#define         AT91_DDRSDRC_MDVAL      (0xff <<  8)            /* Master Delay value */
-#define         AT91_DDRSDRC_SDVAL      (0xff << 16)            /* Slave Delay value */
-#define         AT91_DDRSDRC_SDCVAL     (0xff << 24)            /* Slave Delay Correction value */
-
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91cap9_matrix.h b/include/asm-arm/arch-at91/at91cap9_matrix.h
deleted file mode 100644
index ddbd4873c842..000000000000
--- a/include/asm-arm/arch-at91/at91cap9_matrix.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91cap9_matrix.h
- *
- *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
- *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
- *  Copyright (C) 2006 Atmel Corporation.
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91CAP9 datasheet revision B (Preliminary).
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91CAP9_MATRIX_H
-#define AT91CAP9_MATRIX_H
-
-#define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
-#define AT91_MATRIX_MCFG6       (AT91_MATRIX + 0x18)    /* Master Configuration Register 6 */
-#define AT91_MATRIX_MCFG7       (AT91_MATRIX + 0x1C)    /* Master Configuration Register 7 */
-#define AT91_MATRIX_MCFG8       (AT91_MATRIX + 0x20)    /* Master Configuration Register 8 */
-#define AT91_MATRIX_MCFG9       (AT91_MATRIX + 0x24)    /* Master Configuration Register 9 */
-#define AT91_MATRIX_MCFG10      (AT91_MATRIX + 0x28)    /* Master Configuration Register 10 */
-#define AT91_MATRIX_MCFG11      (AT91_MATRIX + 0x2C)    /* Master Configuration Register 11 */
-#define         AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
-#define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
-#define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
-#define                 AT91_MATRIX_ULBT_FOUR           (2 << 0)
-#define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
-#define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
-
-#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5       (AT91_MATRIX + 0x54)    /* Slave Configuration Register 5 */
-#define AT91_MATRIX_SCFG6       (AT91_MATRIX + 0x58)    /* Slave Configuration Register 6 */
-#define AT91_MATRIX_SCFG7       (AT91_MATRIX + 0x5C)    /* Slave Configuration Register 7 */
-#define AT91_MATRIX_SCFG8       (AT91_MATRIX + 0x60)    /* Slave Configuration Register 8 */
-#define AT91_MATRIX_SCFG9       (AT91_MATRIX + 0x64)    /* Slave Configuration Register 9 */
-#define         AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
-#define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
-#define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
-#define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
-#define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
-#define         AT91_MATRIX_FIXED_DEFMSTR       (0xf  << 18)    /* Fixed Index of Default Master */
-#define         AT91_MATRIX_ARBT                (3    << 24)    /* Arbitration Type */
-#define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
-#define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
-
-#define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRBS0       (AT91_MATRIX + 0x84)    /* Priority Register B for Slave 0 */
-#define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRBS1       (AT91_MATRIX + 0x8C)    /* Priority Register B for Slave 1 */
-#define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRBS2       (AT91_MATRIX + 0x94)    /* Priority Register B for Slave 2 */
-#define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRBS3       (AT91_MATRIX + 0x9C)    /* Priority Register B for Slave 3 */
-#define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRBS4       (AT91_MATRIX + 0xA4)    /* Priority Register B for Slave 4 */
-#define AT91_MATRIX_PRAS5       (AT91_MATRIX + 0xA8)    /* Priority Register A for Slave 5 */
-#define AT91_MATRIX_PRBS5       (AT91_MATRIX + 0xAC)    /* Priority Register B for Slave 5 */
-#define AT91_MATRIX_PRAS6       (AT91_MATRIX + 0xB0)    /* Priority Register A for Slave 6 */
-#define AT91_MATRIX_PRBS6       (AT91_MATRIX + 0xB4)    /* Priority Register B for Slave 6 */
-#define AT91_MATRIX_PRAS7       (AT91_MATRIX + 0xB8)    /* Priority Register A for Slave 7 */
-#define AT91_MATRIX_PRBS7       (AT91_MATRIX + 0xBC)    /* Priority Register B for Slave 7 */
-#define AT91_MATRIX_PRAS8       (AT91_MATRIX + 0xC0)    /* Priority Register A for Slave 8 */
-#define AT91_MATRIX_PRBS8       (AT91_MATRIX + 0xC4)    /* Priority Register B for Slave 8 */
-#define AT91_MATRIX_PRAS9       (AT91_MATRIX + 0xC8)    /* Priority Register A for Slave 9 */
-#define AT91_MATRIX_PRBS9       (AT91_MATRIX + 0xCC)    /* Priority Register B for Slave 9 */
-#define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
-#define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
-#define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
-#define         AT91_MATRIX_M3PR                (3 << 12)       /* Master 3 Priority */
-#define         AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
-#define         AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
-#define         AT91_MATRIX_M6PR                (3 << 24)       /* Master 6 Priority */
-#define         AT91_MATRIX_M7PR                (3 << 28)       /* Master 7 Priority */
-#define         AT91_MATRIX_M8PR                (3 << 0)        /* Master 8 Priority (in Register B) */
-#define         AT91_MATRIX_M9PR                (3 << 4)        /* Master 9 Priority (in Register B) */
-#define         AT91_MATRIX_M10PR               (3 << 8)        /* Master 10 Priority (in Register B) */
-#define         AT91_MATRIX_M11PR               (3 << 12)       /* Master 11 Priority (in Register B) */
-
-#define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
-#define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define         AT91_MATRIX_RCB2                (1 << 2)
-#define         AT91_MATRIX_RCB3                (1 << 3)
-#define         AT91_MATRIX_RCB4                (1 << 4)
-#define         AT91_MATRIX_RCB5                (1 << 5)
-#define         AT91_MATRIX_RCB6                (1 << 6)
-#define         AT91_MATRIX_RCB7                (1 << 7)
-#define         AT91_MATRIX_RCB8                (1 << 8)
-#define         AT91_MATRIX_RCB9                (1 << 9)
-#define         AT91_MATRIX_RCB10               (1 << 10)
-#define         AT91_MATRIX_RCB11               (1 << 11)
-
-#define AT91_MPBS0_SFR          (AT91_MATRIX + 0x114)   /* MPBlock Slave 0 Special Function Register */
-#define AT91_MPBS1_SFR          (AT91_MATRIX + 0x11C)   /* MPBlock Slave 1 Special Function Register */
-
-#define AT91_MATRIX_UDPHS       (AT91_MATRIX + 0x118)   /* USBHS Special Function Register [AT91CAP9 only] */
-#define         AT91_MATRIX_SELECT_UDPHS        (0 << 31)       /* select High Speed UDP */
-#define         AT91_MATRIX_SELECT_UDP          (1 << 31)       /* select standard UDP */
-#define         AT91_MATRIX_UDPHS_BYPASS_LOCK   (1 << 30)       /* bypass lock bit */
-
-#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x120)   /* EBI Chip Select Assignment Register */
-#define         AT91_MATRIX_EBI_CS1A            (1 << 1)        /* Chip Select 1 Assignment */
-#define                 AT91_MATRIX_EBI_CS1A_SMC                (0 << 1)
-#define                 AT91_MATRIX_EBI_CS1A_BCRAMC             (1 << 1)
-#define         AT91_MATRIX_EBI_CS3A            (1 << 3)        /* Chip Select 3 Assignment */
-#define                 AT91_MATRIX_EBI_CS3A_SMC                (0 << 3)
-#define                 AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA     (1 << 3)
-#define         AT91_MATRIX_EBI_CS4A            (1 << 4)        /* Chip Select 4 Assignment */
-#define                 AT91_MATRIX_EBI_CS4A_SMC                (0 << 4)
-#define                 AT91_MATRIX_EBI_CS4A_SMC_CF1            (1 << 4)
-#define         AT91_MATRIX_EBI_CS5A            (1 << 5)        /* Chip Select 5 Assignment */
-#define                 AT91_MATRIX_EBI_CS5A_SMC                (0 << 5)
-#define                 AT91_MATRIX_EBI_CS5A_SMC_CF2            (1 << 5)
-#define         AT91_MATRIX_EBI_DBPUC           (1 << 8)        /* Data Bus Pull-up Configuration */
-#define         AT91_MATRIX_EBI_DQSPDC          (1 << 9)        /* Data Qualifier Strobe Pull-Down Configuration */
-#define         AT91_MATRIX_EBI_VDDIOMSEL       (1 << 16)       /* Memory voltage selection */
-#define                 AT91_MATRIX_EBI_VDDIOMSEL_1_8V          (0 << 16)
-#define                 AT91_MATRIX_EBI_VDDIOMSEL_3_3V          (1 << 16)
-
-#define AT91_MPBS2_SFR          (AT91_MATRIX + 0x12C)   /* MPBlock Slave 2 Special Function Register */
-#define AT91_MPBS3_SFR          (AT91_MATRIX + 0x130)   /* MPBlock Slave 3 Special Function Register */
-#define AT91_APB_SFR            (AT91_MATRIX + 0x134)   /* APB Bridge Special Function Register */
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91rm9200.h b/include/asm-arm/arch-at91/at91rm9200.h
deleted file mode 100644
index e8fc0b1c33f4..000000000000
--- a/include/asm-arm/arch-at91/at91rm9200.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91rm9200.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * Common definitions.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91RM9200_H
-#define AT91RM9200_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS             1       /* System Peripheral */
-#define AT91RM9200_ID_PIOA      2       /* Parallel IO Controller A */
-#define AT91RM9200_ID_PIOB      3       /* Parallel IO Controller B */
-#define AT91RM9200_ID_PIOC      4       /* Parallel IO Controller C */
-#define AT91RM9200_ID_PIOD      5       /* Parallel IO Controller D */
-#define AT91RM9200_ID_US0       6       /* USART 0 */
-#define AT91RM9200_ID_US1       7       /* USART 1 */
-#define AT91RM9200_ID_US2       8       /* USART 2 */
-#define AT91RM9200_ID_US3       9       /* USART 3 */
-#define AT91RM9200_ID_MCI       10      /* Multimedia Card Interface */
-#define AT91RM9200_ID_UDP       11      /* USB Device Port */
-#define AT91RM9200_ID_TWI       12      /* Two-Wire Interface */
-#define AT91RM9200_ID_SPI       13      /* Serial Peripheral Interface */
-#define AT91RM9200_ID_SSC0      14      /* Serial Synchronous Controller 0 */
-#define AT91RM9200_ID_SSC1      15      /* Serial Synchronous Controller 1 */
-#define AT91RM9200_ID_SSC2      16      /* Serial Synchronous Controller 2 */
-#define AT91RM9200_ID_TC0       17      /* Timer Counter 0 */
-#define AT91RM9200_ID_TC1       18      /* Timer Counter 1 */
-#define AT91RM9200_ID_TC2       19      /* Timer Counter 2 */
-#define AT91RM9200_ID_TC3       20      /* Timer Counter 3 */
-#define AT91RM9200_ID_TC4       21      /* Timer Counter 4 */
-#define AT91RM9200_ID_TC5       22      /* Timer Counter 5 */
-#define AT91RM9200_ID_UHP       23      /* USB Host port */
-#define AT91RM9200_ID_EMAC      24      /* Ethernet MAC */
-#define AT91RM9200_ID_IRQ0      25      /* Advanced Interrupt Controller (IRQ0) */
-#define AT91RM9200_ID_IRQ1      26      /* Advanced Interrupt Controller (IRQ1) */
-#define AT91RM9200_ID_IRQ2      27      /* Advanced Interrupt Controller (IRQ2) */
-#define AT91RM9200_ID_IRQ3      28      /* Advanced Interrupt Controller (IRQ3) */
-#define AT91RM9200_ID_IRQ4      29      /* Advanced Interrupt Controller (IRQ4) */
-#define AT91RM9200_ID_IRQ5      30      /* Advanced Interrupt Controller (IRQ5) */
-#define AT91RM9200_ID_IRQ6      31      /* Advanced Interrupt Controller (IRQ6) */
-
-
-/*
- * Peripheral physical base addresses.
- */
-#define AT91RM9200_BASE_TCB0    0xfffa0000
-#define AT91RM9200_BASE_TC0     0xfffa0000
-#define AT91RM9200_BASE_TC1     0xfffa0040
-#define AT91RM9200_BASE_TC2     0xfffa0080
-#define AT91RM9200_BASE_TCB1    0xfffa4000
-#define AT91RM9200_BASE_TC3     0xfffa4000
-#define AT91RM9200_BASE_TC4     0xfffa4040
-#define AT91RM9200_BASE_TC5     0xfffa4080
-#define AT91RM9200_BASE_UDP     0xfffb0000
-#define AT91RM9200_BASE_MCI     0xfffb4000
-#define AT91RM9200_BASE_TWI     0xfffb8000
-#define AT91RM9200_BASE_EMAC    0xfffbc000
-#define AT91RM9200_BASE_US0     0xfffc0000
-#define AT91RM9200_BASE_US1     0xfffc4000
-#define AT91RM9200_BASE_US2     0xfffc8000
-#define AT91RM9200_BASE_US3     0xfffcc000
-#define AT91RM9200_BASE_SSC0    0xfffd0000
-#define AT91RM9200_BASE_SSC1    0xfffd4000
-#define AT91RM9200_BASE_SSC2    0xfffd8000
-#define AT91RM9200_BASE_SPI     0xfffe0000
-#define AT91_BASE_SYS           0xfffff000
-
-
-/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)    /* Advanced Interrupt Controller */
-#define AT91_DBGU       (0xfffff200 - AT91_BASE_SYS)    /* Debug Unit */
-#define AT91_PIOA       (0xfffff400 - AT91_BASE_SYS)    /* PIO Controller A */
-#define AT91_PIOB       (0xfffff600 - AT91_BASE_SYS)    /* PIO Controller B */
-#define AT91_PIOC       (0xfffff800 - AT91_BASE_SYS)    /* PIO Controller C */
-#define AT91_PIOD       (0xfffffa00 - AT91_BASE_SYS)    /* PIO Controller D */
-#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)    /* Power Management Controller */
-#define AT91_ST         (0xfffffd00 - AT91_BASE_SYS)    /* System Timer */
-#define AT91_RTC        (0xfffffe00 - AT91_BASE_SYS)    /* Real-Time Clock */
-#define AT91_MC         (0xffffff00 - AT91_BASE_SYS)    /* Memory Controllers */
-
-#define AT91_USART0     AT91RM9200_BASE_US0
-#define AT91_USART1     AT91RM9200_BASE_US1
-#define AT91_USART2     AT91RM9200_BASE_US2
-#define AT91_USART3     AT91RM9200_BASE_US3
-
-#define AT91_MATRIX     0       /* not supported */
-
-/*
- * Internal Memory.
- */
-#define AT91RM9200_ROM_BASE     0x00100000      /* Internal ROM base address */
-#define AT91RM9200_ROM_SIZE     SZ_128K         /* Internal ROM size (128Kb) */
-
-#define AT91RM9200_SRAM_BASE    0x00200000      /* Internal SRAM base address */
-#define AT91RM9200_SRAM_SIZE    SZ_16K          /* Internal SRAM size (16Kb) */
-
-#define AT91RM9200_UHP_BASE     0x00300000      /* USB Host controller */
-
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91rm9200_emac.h b/include/asm-arm/arch-at91/at91rm9200_emac.h
deleted file mode 100644
index 0c417af5fe7f..000000000000
--- a/include/asm-arm/arch-at91/at91rm9200_emac.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91rm9200_emac.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * Ethernet MAC registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91RM9200_EMAC_H
-#define AT91RM9200_EMAC_H
-
-#define AT91_EMAC_CTL           0x00    /* Control Register */
-#define         AT91_EMAC_LB            (1 <<  0)       /* Loopback */
-#define         AT91_EMAC_LBL           (1 <<  1)       /* Loopback Local */
-#define         AT91_EMAC_RE            (1 <<  2)       /* Receive Enable */
-#define         AT91_EMAC_TE            (1 <<  3)       /* Transmit Enable */
-#define         AT91_EMAC_MPE           (1 <<  4)       /* Management Port Enable */
-#define         AT91_EMAC_CSR           (1 <<  5)       /* Clear Statistics Registers */
-#define         AT91_EMAC_INCSTAT       (1 <<  6)       /* Increment Statistics Registers */
-#define         AT91_EMAC_WES           (1 <<  7)       /* Write Enable for Statistics Registers */
-#define         AT91_EMAC_BP            (1 <<  8)       /* Back Pressure */
-
-#define AT91_EMAC_CFG           0x04    /* Configuration Register */
-#define         AT91_EMAC_SPD           (1 <<  0)       /* Speed */
-#define         AT91_EMAC_FD            (1 <<  1)       /* Full Duplex */
-#define         AT91_EMAC_BR            (1 <<  2)       /* Bit Rate */
-#define         AT91_EMAC_CAF           (1 <<  4)       /* Copy All Frames */
-#define         AT91_EMAC_NBC           (1 <<  5)       /* No Broadcast */
-#define         AT91_EMAC_MTI           (1 <<  6)       /* Multicast Hash Enable */
-#define         AT91_EMAC_UNI           (1 <<  7)       /* Unicast Hash Enable */
-#define         AT91_EMAC_BIG           (1 <<  8)       /* Receive 1522 Bytes */
-#define         AT91_EMAC_EAE           (1 <<  9)       /* External Address Match Enable */
-#define         AT91_EMAC_CLK           (3 << 10)       /* MDC Clock Divisor */
-#define         AT91_EMAC_CLK_DIV8              (0 << 10)
-#define         AT91_EMAC_CLK_DIV16             (1 << 10)
-#define         AT91_EMAC_CLK_DIV32             (2 << 10)
-#define         AT91_EMAC_CLK_DIV64             (3 << 10)
-#define         AT91_EMAC_RTY           (1 << 12)       /* Retry Test */
-#define         AT91_EMAC_RMII          (1 << 13)       /* Reduce MII (RMII) */
-
-#define AT91_EMAC_SR            0x08    /* Status Register */
-#define         AT91_EMAC_SR_LINK       (1 <<  0)       /* Link */
-#define         AT91_EMAC_SR_MDIO       (1 <<  1)       /* MDIO pin */
-#define         AT91_EMAC_SR_IDLE       (1 <<  2)       /* PHY idle */
-
-#define AT91_EMAC_TAR           0x0c    /* Transmit Address Register */
-
-#define AT91_EMAC_TCR           0x10    /* Transmit Control Register */
-#define         AT91_EMAC_LEN           (0x7ff << 0)    /* Transmit Frame Length */
-#define         AT91_EMAC_NCRC          (1     << 15)   /* No CRC */
-
-#define AT91_EMAC_TSR           0x14    /* Transmit Status Register */
-#define         AT91_EMAC_TSR_OVR       (1 <<  0)       /* Transmit Buffer Overrun */
-#define         AT91_EMAC_TSR_COL       (1 <<  1)       /* Collision Occurred */
-#define         AT91_EMAC_TSR_RLE       (1 <<  2)       /* Retry Limit Exceeded */
-#define         AT91_EMAC_TSR_IDLE      (1 <<  3)       /* Transmitter Idle */
-#define         AT91_EMAC_TSR_BNQ       (1 <<  4)       /* Transmit Buffer not Queued */
-#define         AT91_EMAC_TSR_COMP      (1 <<  5)       /* Transmit Complete */
-#define         AT91_EMAC_TSR_UND       (1 <<  6)       /* Transmit Underrun */
-
-#define AT91_EMAC_RBQP          0x18    /* Receive Buffer Queue Pointer */
-
-#define AT91_EMAC_RSR           0x20    /* Receive Status Register */
-#define         AT91_EMAC_RSR_BNA       (1 <<  0)       /* Buffer Not Available */
-#define         AT91_EMAC_RSR_REC       (1 <<  1)       /* Frame Received */
-#define         AT91_EMAC_RSR_OVR       (1 <<  2)       /* RX Overrun */
-
-#define AT91_EMAC_ISR           0x24    /* Interrupt Status Register */
-#define         AT91_EMAC_DONE          (1 <<  0)       /* Management Done */
-#define         AT91_EMAC_RCOM          (1 <<  1)       /* Receive Complete */
-#define         AT91_EMAC_RBNA          (1 <<  2)       /* Receive Buffer Not Available */
-#define         AT91_EMAC_TOVR          (1 <<  3)       /* Transmit Buffer Overrun */
-#define         AT91_EMAC_TUND          (1 <<  4)       /* Transmit Buffer Underrun */
-#define         AT91_EMAC_RTRY          (1 <<  5)       /* Retry Limit */
-#define         AT91_EMAC_TBRE          (1 <<  6)       /* Transmit Buffer Register Empty */
-#define         AT91_EMAC_TCOM          (1 <<  7)       /* Transmit Complete */
-#define         AT91_EMAC_TIDLE         (1 <<  8)       /* Transmit Idle */
-#define         AT91_EMAC_LINK          (1 <<  9)       /* Link */
-#define         AT91_EMAC_ROVR          (1 << 10)       /* RX Overrun */
-#define         AT91_EMAC_ABT           (1 << 11)       /* Abort */
-
-#define AT91_EMAC_IER           0x28    /* Interrupt Enable Register */
-#define AT91_EMAC_IDR           0x2c    /* Interrupt Disable Register */
-#define AT91_EMAC_IMR           0x30    /* Interrupt Mask Register */
-
-#define AT91_EMAC_MAN           0x34    /* PHY Maintenance Register */
-#define         AT91_EMAC_DATA          (0xffff << 0)   /* MDIO Data */
-#define         AT91_EMAC_REGA          (0x1f   << 18)  /* MDIO Register */
-#define         AT91_EMAC_PHYA          (0x1f   << 23)  /* MDIO PHY Address */
-#define         AT91_EMAC_RW            (3      << 28)  /* Read/Write operation */
-#define                 AT91_EMAC_RW_W          (1 << 28)
-#define                 AT91_EMAC_RW_R          (2 << 28)
-#define         AT91_EMAC_MAN_802_3     0x40020000      /* IEEE 802.3 value */
-
-/*
- * Statistics Registers.
- */
-#define AT91_EMAC_FRA           0x40    /* Frames Transmitted OK */
-#define AT91_EMAC_SCOL          0x44    /* Single Collision Frame */
-#define AT91_EMAC_MCOL          0x48    /* Multiple Collision Frame */
-#define AT91_EMAC_OK            0x4c    /* Frames Received OK */
-#define AT91_EMAC_SEQE          0x50    /* Frame Check Sequence Error */
-#define AT91_EMAC_ALE           0x54    /* Alignmemt Error */
-#define AT91_EMAC_DTE           0x58    /* Deffered Transmission Frame */
-#define AT91_EMAC_LCOL          0x5c    /* Late Collision */
-#define AT91_EMAC_ECOL          0x60    /* Excessive Collision */
-#define AT91_EMAC_TUE           0x64    /* Transmit Underrun Error */
-#define AT91_EMAC_CSE           0x68    /* Carrier Sense Error */
-#define AT91_EMAC_DRFC          0x6c    /* Discard RX Frame */
-#define AT91_EMAC_ROV           0x70    /* Receive Overrun */
-#define AT91_EMAC_CDE           0x74    /* Code Error */
-#define AT91_EMAC_ELR           0x78    /* Excessive Length Error */
-#define AT91_EMAC_RJB           0x7c    /* Receive Jabber */
-#define AT91_EMAC_USF           0x80    /* Undersize Frame */
-#define AT91_EMAC_SQEE          0x84    /* SQE Test Error */
-
-/*
- * Address Registers.
- */
-#define AT91_EMAC_HSL           0x90    /* Hash Address Low [31:0] */
-#define AT91_EMAC_HSH           0x94    /* Hash Address High [63:32] */
-#define AT91_EMAC_SA1L          0x98    /* Specific Address 1 Low, bytes 0-3 */
-#define AT91_EMAC_SA1H          0x9c    /* Specific Address 1 High, bytes 4-5 */
-#define AT91_EMAC_SA2L          0xa0    /* Specific Address 2 Low, bytes 0-3 */
-#define AT91_EMAC_SA2H          0xa4    /* Specific Address 2 High, bytes 4-5 */
-#define AT91_EMAC_SA3L          0xa8    /* Specific Address 3 Low, bytes 0-3 */
-#define AT91_EMAC_SA3H          0xac    /* Specific Address 3 High, bytes 4-5 */
-#define AT91_EMAC_SA4L          0xb0    /* Specific Address 4 Low, bytes 0-3 */
-#define AT91_EMAC_SA4H          0xb4    /* Specific Address 4 High, bytes 4-5 */
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91rm9200_mc.h b/include/asm-arm/arch-at91/at91rm9200_mc.h
deleted file mode 100644
index 24d012939cc4..000000000000
--- a/include/asm-arm/arch-at91/at91rm9200_mc.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91rm9200_mc.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91RM9200_MC_H
-#define AT91RM9200_MC_H
-
-/* Memory Controller */
-#define AT91_MC_RCR             (AT91_MC + 0x00)        /* MC Remap Control Register */
-#define         AT91_MC_RCB             (1 <<  0)               /* Remap Command Bit */
-
-#define AT91_MC_ASR             (AT91_MC + 0x04)        /* MC Abort Status Register */
-#define         AT91_MC_UNADD           (1 <<  0)               /* Undefined Address Abort Status */
-#define         AT91_MC_MISADD          (1 <<  1)               /* Misaligned Address Abort Status */
-#define         AT91_MC_ABTSZ           (3 <<  8)               /* Abort Size Status */
-#define                 AT91_MC_ABTSZ_BYTE              (0 << 8)
-#define                 AT91_MC_ABTSZ_HALFWORD          (1 << 8)
-#define                 AT91_MC_ABTSZ_WORD              (2 << 8)
-#define         AT91_MC_ABTTYP          (3 << 10)               /* Abort Type Status */
-#define                 AT91_MC_ABTTYP_DATAREAD         (0 << 10)
-#define                 AT91_MC_ABTTYP_DATAWRITE        (1 << 10)
-#define                 AT91_MC_ABTTYP_FETCH            (2 << 10)
-#define         AT91_MC_MST0            (1 << 16)               /* ARM920T Abort Source */
-#define         AT91_MC_MST1            (1 << 17)               /* PDC Abort Source */
-#define         AT91_MC_MST2            (1 << 18)               /* UHP Abort Source */
-#define         AT91_MC_MST3            (1 << 19)               /* EMAC Abort Source */
-#define         AT91_MC_SVMST0          (1 << 24)               /* Saved ARM920T Abort Source */
-#define         AT91_MC_SVMST1          (1 << 25)               /* Saved PDC Abort Source */
-#define         AT91_MC_SVMST2          (1 << 26)               /* Saved UHP Abort Source */
-#define         AT91_MC_SVMST3          (1 << 27)               /* Saved EMAC Abort Source */
-
-#define AT91_MC_AASR            (AT91_MC + 0x08)        /* MC Abort Address Status Register */
-
-#define AT91_MC_MPR             (AT91_MC + 0x0c)        /* MC Master Priority Register */
-#define         AT91_MPR_MSTP0          (7 <<  0)               /* ARM920T Priority */
-#define         AT91_MPR_MSTP1          (7 <<  4)               /* PDC Priority */
-#define         AT91_MPR_MSTP2          (7 <<  8)               /* UHP Priority */
-#define         AT91_MPR_MSTP3          (7 << 12)               /* EMAC Priority */
-
-/* External Bus Interface (EBI) registers */
-#define AT91_EBI_CSA            (AT91_MC + 0x60)        /* Chip Select Assignment Register */
-#define         AT91_EBI_CS0A           (1 << 0)                /* Chip Select 0 Assignment */
-#define                 AT91_EBI_CS0A_SMC               (0 << 0)
-#define                 AT91_EBI_CS0A_BFC               (1 << 0)
-#define         AT91_EBI_CS1A           (1 << 1)                /* Chip Select 1 Assignment */
-#define                 AT91_EBI_CS1A_SMC               (0 << 1)
-#define                 AT91_EBI_CS1A_SDRAMC            (1 << 1)
-#define         AT91_EBI_CS3A           (1 << 3)                /* Chip Select 2 Assignment */
-#define                 AT91_EBI_CS3A_SMC               (0 << 3)
-#define                 AT91_EBI_CS3A_SMC_SMARTMEDIA    (1 << 3)
-#define         AT91_EBI_CS4A           (1 << 4)                /* Chip Select 3 Assignment */
-#define                 AT91_EBI_CS4A_SMC               (0 << 4)
-#define                 AT91_EBI_CS4A_SMC_COMPACTFLASH  (1 << 4)
-#define AT91_EBI_CFGR           (AT91_MC + 0x64)        /* Configuration Register */
-#define         AT91_EBI_DBPUC          (1 << 0)                /* Data Bus Pull-Up Configuration */
-
-/* Static Memory Controller (SMC) registers */
-#define AT91_SMC_CSR(n)         (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
-#define         AT91_SMC_NWS            (0x7f <<  0)            /* Number of Wait States */
-#define                 AT91_SMC_NWS_(x)        ((x) << 0)
-#define         AT91_SMC_WSEN           (1    <<  7)            /* Wait State Enable */
-#define         AT91_SMC_TDF            (0xf  <<  8)            /* Data Float Time */
-#define                 AT91_SMC_TDF_(x)        ((x) << 8)
-#define         AT91_SMC_BAT            (1    << 12)            /* Byte Access Type */
-#define         AT91_SMC_DBW            (3    << 13)            /* Data Bus Width */
-#define                 AT91_SMC_DBW_16         (1 << 13)
-#define                 AT91_SMC_DBW_8          (2 << 13)
-#define         AT91_SMC_DPR            (1 << 15)               /* Data Read Protocol */
-#define         AT91_SMC_ACSS           (3 << 16)               /* Address to Chip Select Setup */
-#define                 AT91_SMC_ACSS_STD       (0 << 16)
-#define                 AT91_SMC_ACSS_1         (1 << 16)
-#define                 AT91_SMC_ACSS_2         (2 << 16)
-#define                 AT91_SMC_ACSS_3         (3 << 16)
-#define         AT91_SMC_RWSETUP        (7 << 24)               /* Read & Write Signal Time Setup */
-#define                 AT91_SMC_RWSETUP_(x)    ((x) << 24)
-#define         AT91_SMC_RWHOLD         (7 << 28)               /* Read & Write Signal Hold Time */
-#define                 AT91_SMC_RWHOLD_(x)     ((x) << 28)
-
-/* SDRAM Controller registers */
-#define AT91_SDRAMC_MR          (AT91_MC + 0x90)        /* Mode Register */
-#define         AT91_SDRAMC_MODE        (0xf << 0)              /* Command Mode */
-#define                 AT91_SDRAMC_MODE_NORMAL         (0 << 0)
-#define                 AT91_SDRAMC_MODE_NOP            (1 << 0)
-#define                 AT91_SDRAMC_MODE_PRECHARGE      (2 << 0)
-#define                 AT91_SDRAMC_MODE_LMR            (3 << 0)
-#define                 AT91_SDRAMC_MODE_REFRESH        (4 << 0)
-#define         AT91_SDRAMC_DBW         (1   << 4)              /* Data Bus Width */
-#define                 AT91_SDRAMC_DBW_32      (0 << 4)
-#define                 AT91_SDRAMC_DBW_16      (1 << 4)
-
-#define AT91_SDRAMC_TR          (AT91_MC + 0x94)        /* Refresh Timer Register */
-#define         AT91_SDRAMC_COUNT       (0xfff << 0)            /* Refresh Timer Count */
-
-#define AT91_SDRAMC_CR          (AT91_MC + 0x98)        /* Configuration Register */
-#define         AT91_SDRAMC_NC          (3   <<  0)             /* Number of Column Bits */
-#define                 AT91_SDRAMC_NC_8        (0 << 0)
-#define                 AT91_SDRAMC_NC_9        (1 << 0)
-#define                 AT91_SDRAMC_NC_10       (2 << 0)
-#define                 AT91_SDRAMC_NC_11       (3 << 0)
-#define         AT91_SDRAMC_NR          (3   <<  2)             /* Number of Row Bits */
-#define                 AT91_SDRAMC_NR_11       (0 << 2)
-#define                 AT91_SDRAMC_NR_12       (1 << 2)
-#define                 AT91_SDRAMC_NR_13       (2 << 2)
-#define         AT91_SDRAMC_NB          (1   <<  4)             /* Number of Banks */
-#define                 AT91_SDRAMC_NB_2        (0 << 4)
-#define                 AT91_SDRAMC_NB_4        (1 << 4)
-#define         AT91_SDRAMC_CAS         (3   <<  5)             /* CAS Latency */
-#define                 AT91_SDRAMC_CAS_2       (2 << 5)
-#define         AT91_SDRAMC_TWR         (0xf <<  7)             /* Write Recovery Delay */
-#define         AT91_SDRAMC_TRC         (0xf << 11)             /* Row Cycle Delay */
-#define         AT91_SDRAMC_TRP         (0xf << 15)             /* Row Precharge Delay */
-#define         AT91_SDRAMC_TRCD        (0xf << 19)             /* Row to Column Delay */
-#define         AT91_SDRAMC_TRAS        (0xf << 23)             /* Active to Precharge Delay */
-#define         AT91_SDRAMC_TXSR        (0xf << 27)             /* Exit Self Refresh to Active Delay */
-
-#define AT91_SDRAMC_SRR         (AT91_MC + 0x9c)        /* Self Refresh Register */
-#define AT91_SDRAMC_LPR         (AT91_MC + 0xa0)        /* Low Power Register */
-#define AT91_SDRAMC_IER         (AT91_MC + 0xa4)        /* Interrupt Enable Register */
-#define AT91_SDRAMC_IDR         (AT91_MC + 0xa8)        /* Interrupt Disable Register */
-#define AT91_SDRAMC_IMR         (AT91_MC + 0xac)        /* Interrupt Mask Register */
-#define AT91_SDRAMC_ISR         (AT91_MC + 0xb0)        /* Interrupt Status Register */
-
-/* Burst Flash Controller register */
-#define AT91_BFC_MR             (AT91_MC + 0xc0)        /* Mode Register */
-#define         AT91_BFC_BFCOM          (3   <<  0)             /* Burst Flash Controller Operating Mode */
-#define                 AT91_BFC_BFCOM_DISABLED (0 << 0)
-#define                 AT91_BFC_BFCOM_ASYNC    (1 << 0)
-#define                 AT91_BFC_BFCOM_BURST    (2 << 0)
-#define         AT91_BFC_BFCC           (3   <<  2)             /* Burst Flash Controller Clock */
-#define                 AT91_BFC_BFCC_MCK       (1 << 2)
-#define                 AT91_BFC_BFCC_DIV2      (2 << 2)
-#define                 AT91_BFC_BFCC_DIV4      (3 << 2)
-#define         AT91_BFC_AVL            (0xf <<  4)             /* Address Valid Latency */
-#define         AT91_BFC_PAGES          (7   <<  8)             /* Page Size */
-#define                 AT91_BFC_PAGES_NO_PAGE  (0 << 8)
-#define                 AT91_BFC_PAGES_16       (1 << 8)
-#define                 AT91_BFC_PAGES_32       (2 << 8)
-#define                 AT91_BFC_PAGES_64       (3 << 8)
-#define                 AT91_BFC_PAGES_128      (4 << 8)
-#define                 AT91_BFC_PAGES_256      (5 << 8)
-#define                 AT91_BFC_PAGES_512      (6 << 8)
-#define                 AT91_BFC_PAGES_1024     (7 << 8)
-#define         AT91_BFC_OEL            (3   << 12)             /* Output Enable Latency */
-#define         AT91_BFC_BAAEN          (1   << 16)             /* Burst Address Advance Enable */
-#define         AT91_BFC_BFOEH          (1   << 17)             /* Burst Flash Output Enable Handling */
-#define         AT91_BFC_MUXEN          (1   << 18)             /* Multiplexed Bus Enable */
-#define         AT91_BFC_RDYEN          (1   << 19)             /* Ready Enable Mode */
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91sam9260.h b/include/asm-arm/arch-at91/at91sam9260.h
deleted file mode 100644
index 889872a3f2a9..000000000000
--- a/include/asm-arm/arch-at91/at91sam9260.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91sam9260.h
- *
- * (C) 2006 Andrew Victor
- *
- * Common definitions.
- * Based on AT91SAM9260 datasheet revision A (Preliminary).
- *
- * Includes also definitions for AT91SAM9XE and AT91SAM9G families
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91SAM9260_H
-#define AT91SAM9260_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS             1       /* System Peripherals */
-#define AT91SAM9260_ID_PIOA     2       /* Parallel IO Controller A */
-#define AT91SAM9260_ID_PIOB     3       /* Parallel IO Controller B */
-#define AT91SAM9260_ID_PIOC     4       /* Parallel IO Controller C */
-#define AT91SAM9260_ID_ADC      5       /* Analog-to-Digital Converter */
-#define AT91SAM9260_ID_US0      6       /* USART 0 */
-#define AT91SAM9260_ID_US1      7       /* USART 1 */
-#define AT91SAM9260_ID_US2      8       /* USART 2 */
-#define AT91SAM9260_ID_MCI      9       /* Multimedia Card Interface */
-#define AT91SAM9260_ID_UDP      10      /* USB Device Port */
-#define AT91SAM9260_ID_TWI      11      /* Two-Wire Interface */
-#define AT91SAM9260_ID_SPI0     12      /* Serial Peripheral Interface 0 */
-#define AT91SAM9260_ID_SPI1     13      /* Serial Peripheral Interface 1 */
-#define AT91SAM9260_ID_SSC      14      /* Serial Synchronous Controller */
-#define AT91SAM9260_ID_TC0      17      /* Timer Counter 0 */
-#define AT91SAM9260_ID_TC1      18      /* Timer Counter 1 */
-#define AT91SAM9260_ID_TC2      19      /* Timer Counter 2 */
-#define AT91SAM9260_ID_UHP      20      /* USB Host port */
-#define AT91SAM9260_ID_EMAC     21      /* Ethernet */
-#define AT91SAM9260_ID_ISI      22      /* Image Sensor Interface */
-#define AT91SAM9260_ID_US3      23      /* USART 3 */
-#define AT91SAM9260_ID_US4      24      /* USART 4 */
-#define AT91SAM9260_ID_US5      25      /* USART 5 */
-#define AT91SAM9260_ID_TC3      26      /* Timer Counter 3 */
-#define AT91SAM9260_ID_TC4      27      /* Timer Counter 4 */
-#define AT91SAM9260_ID_TC5      28      /* Timer Counter 5 */
-#define AT91SAM9260_ID_IRQ0     29      /* Advanced Interrupt Controller (IRQ0) */
-#define AT91SAM9260_ID_IRQ1     30      /* Advanced Interrupt Controller (IRQ1) */
-#define AT91SAM9260_ID_IRQ2     31      /* Advanced Interrupt Controller (IRQ2) */
-
-
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91SAM9260_BASE_TCB0           0xfffa0000
-#define AT91SAM9260_BASE_TC0            0xfffa0000
-#define AT91SAM9260_BASE_TC1            0xfffa0040
-#define AT91SAM9260_BASE_TC2            0xfffa0080
-#define AT91SAM9260_BASE_UDP            0xfffa4000
-#define AT91SAM9260_BASE_MCI            0xfffa8000
-#define AT91SAM9260_BASE_TWI            0xfffac000
-#define AT91SAM9260_BASE_US0            0xfffb0000
-#define AT91SAM9260_BASE_US1            0xfffb4000
-#define AT91SAM9260_BASE_US2            0xfffb8000
-#define AT91SAM9260_BASE_SSC            0xfffbc000
-#define AT91SAM9260_BASE_ISI            0xfffc0000
-#define AT91SAM9260_BASE_EMAC           0xfffc4000
-#define AT91SAM9260_BASE_SPI0           0xfffc8000
-#define AT91SAM9260_BASE_SPI1           0xfffcc000
-#define AT91SAM9260_BASE_US3            0xfffd0000
-#define AT91SAM9260_BASE_US4            0xfffd4000
-#define AT91SAM9260_BASE_US5            0xfffd8000
-#define AT91SAM9260_BASE_TCB1           0xfffdc000
-#define AT91SAM9260_BASE_TC3            0xfffdc000
-#define AT91SAM9260_BASE_TC4            0xfffdc040
-#define AT91SAM9260_BASE_TC5            0xfffdc080
-#define AT91SAM9260_BASE_ADC            0xfffe0000
-#define AT91_BASE_SYS                   0xffffe800
-
-/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_ECC        (0xffffe800 - AT91_BASE_SYS)
-#define AT91_SDRAMC     (0xffffea00 - AT91_BASE_SYS)
-#define AT91_SMC        (0xffffec00 - AT91_BASE_SYS)
-#define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
-#define AT91_CCFG       (0xffffef10 - AT91_BASE_SYS)
-#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
-#define AT91_DBGU       (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOA       (0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOB       (0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOC       (0xfffff800 - AT91_BASE_SYS)
-#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC      (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT        (0xfffffd20 - AT91_BASE_SYS)
-#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
-#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
-#define AT91_GPBR       (0xfffffd50 - AT91_BASE_SYS)
-
-#define AT91_USART0     AT91SAM9260_BASE_US0
-#define AT91_USART1     AT91SAM9260_BASE_US1
-#define AT91_USART2     AT91SAM9260_BASE_US2
-#define AT91_USART3     AT91SAM9260_BASE_US3
-#define AT91_USART4     AT91SAM9260_BASE_US4
-#define AT91_USART5     AT91SAM9260_BASE_US5
-
-
-/*
- * Internal Memory.
- */
-#define AT91SAM9260_ROM_BASE    0x00100000      /* Internal ROM base address */
-#define AT91SAM9260_ROM_SIZE    SZ_32K          /* Internal ROM size (32Kb) */
-
-#define AT91SAM9260_SRAM0_BASE  0x00200000      /* Internal SRAM 0 base address */
-#define AT91SAM9260_SRAM0_SIZE  SZ_4K           /* Internal SRAM 0 size (4Kb) */
-#define AT91SAM9260_SRAM1_BASE  0x00300000      /* Internal SRAM 1 base address */
-#define AT91SAM9260_SRAM1_SIZE  SZ_4K           /* Internal SRAM 1 size (4Kb) */
-
-#define AT91SAM9260_UHP_BASE    0x00500000      /* USB Host controller */
-
-#define AT91SAM9XE_FLASH_BASE   0x00200000      /* Internal FLASH base address */
-#define AT91SAM9XE_SRAM_BASE    0x00300000      /* Internal SRAM base address */
-
-#define AT91SAM9G20_ROM_BASE    0x00100000      /* Internal ROM base address */
-#define AT91SAM9G20_ROM_SIZE    SZ_32K          /* Internal ROM size (32Kb) */
-
-#define AT91SAM9G20_SRAM0_BASE  0x00200000      /* Internal SRAM 0 base address */
-#define AT91SAM9G20_SRAM0_SIZE  SZ_16K          /* Internal SRAM 0 size (16Kb) */
-#define AT91SAM9G20_SRAM1_BASE  0x00300000      /* Internal SRAM 1 base address */
-#define AT91SAM9G20_SRAM1_SIZE  SZ_16K          /* Internal SRAM 1 size (16Kb) */
-
-#define AT91SAM9G20_UHP_BASE    0x00500000      /* USB Host controller */
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91sam9260_matrix.h b/include/asm-arm/arch-at91/at91sam9260_matrix.h
deleted file mode 100644
index a8e9fec6c735..000000000000
--- a/include/asm-arm/arch-at91/at91sam9260_matrix.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91sam9260_matrix.h
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9260 datasheet revision B.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91SAM9260_MATRIX_H
-#define AT91SAM9260_MATRIX_H
-
-#define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
-#define         AT91_MATRIX_ULBT                (7 << 0)        /* Undefined Length Burst Type */
-#define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
-#define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
-#define                 AT91_MATRIX_ULBT_FOUR           (2 << 0)
-#define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
-#define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
-
-#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
-#define         AT91_MATRIX_SLOT_CYCLE          (0xff <<  0)    /* Maximum Number of Allowed Cycles for a Burst */
-#define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
-#define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
-#define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
-#define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
-#define         AT91_MATRIX_FIXED_DEFMSTR       (7    << 18)    /* Fixed Index of Default Master */
-#define         AT91_MATRIX_ARBT                (3    << 24)    /* Arbitration Type */
-#define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
-#define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
-
-#define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
-#define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
-#define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
-#define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
-#define         AT91_MATRIX_M3PR                (3 << 12)       /* Master 3 Priority */
-#define         AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
-#define         AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
-
-#define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
-#define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-
-#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x11C)   /* EBI Chip Select Assignment Register */
-#define         AT91_MATRIX_CS1A                (1 << 1)        /* Chip Select 1 Assignment */
-#define                 AT91_MATRIX_CS1A_SMC            (0 << 1)
-#define                 AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
-#define         AT91_MATRIX_CS3A                (1 << 3)        /* Chip Select 3 Assignment */
-#define                 AT91_MATRIX_CS3A_SMC            (0 << 3)
-#define                 AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
-#define         AT91_MATRIX_CS4A                (1 << 4)        /* Chip Select 4 Assignment */
-#define                 AT91_MATRIX_CS4A_SMC            (0 << 4)
-#define                 AT91_MATRIX_CS4A_SMC_CF1        (1 << 4)
-#define         AT91_MATRIX_CS5A                (1 << 5)        /* Chip Select 5 Assignment */
-#define                 AT91_MATRIX_CS5A_SMC            (0 << 5)
-#define                 AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
-#define         AT91_MATRIX_DBPUC               (1 << 8)        /* Data Bus Pull-up Configuration */
-#define         AT91_MATRIX_VDDIOMSEL           (1 << 16)       /* Memory voltage selection */
-#define                 AT91_MATRIX_VDDIOMSEL_1_8V      (0 << 16)
-#define                 AT91_MATRIX_VDDIOMSEL_3_3V      (1 << 16)
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91sam9261.h b/include/asm-arm/arch-at91/at91sam9261.h
deleted file mode 100644
index c7c4778dac49..000000000000
--- a/include/asm-arm/arch-at91/at91sam9261.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91sam9261.h
- *
- * Copyright (C) SAN People
- *
- * Common definitions.
- * Based on AT91SAM9261 datasheet revision E. (Preliminary)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91SAM9261_H
-#define AT91SAM9261_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS             1       /* System Peripherals */
-#define AT91SAM9261_ID_PIOA     2       /* Parallel IO Controller A */
-#define AT91SAM9261_ID_PIOB     3       /* Parallel IO Controller B */
-#define AT91SAM9261_ID_PIOC     4       /* Parallel IO Controller C */
-#define AT91SAM9261_ID_US0      6       /* USART 0 */
-#define AT91SAM9261_ID_US1      7       /* USART 1 */
-#define AT91SAM9261_ID_US2      8       /* USART 2 */
-#define AT91SAM9261_ID_MCI      9       /* Multimedia Card Interface */
-#define AT91SAM9261_ID_UDP      10      /* USB Device Port */
-#define AT91SAM9261_ID_TWI      11      /* Two-Wire Interface */
-#define AT91SAM9261_ID_SPI0     12      /* Serial Peripheral Interface 0 */
-#define AT91SAM9261_ID_SPI1     13      /* Serial Peripheral Interface 1 */
-#define AT91SAM9261_ID_SSC0     14      /* Serial Synchronous Controller 0 */
-#define AT91SAM9261_ID_SSC1     15      /* Serial Synchronous Controller 1 */
-#define AT91SAM9261_ID_SSC2     16      /* Serial Synchronous Controller 2 */
-#define AT91SAM9261_ID_TC0      17      /* Timer Counter 0 */
-#define AT91SAM9261_ID_TC1      18      /* Timer Counter 1 */
-#define AT91SAM9261_ID_TC2      19      /* Timer Counter 2 */
-#define AT91SAM9261_ID_UHP      20      /* USB Host port */
-#define AT91SAM9261_ID_LCDC     21      /* LDC Controller */
-#define AT91SAM9261_ID_IRQ0     29      /* Advanced Interrupt Controller (IRQ0) */
-#define AT91SAM9261_ID_IRQ1     30      /* Advanced Interrupt Controller (IRQ1) */
-#define AT91SAM9261_ID_IRQ2     31      /* Advanced Interrupt Controller (IRQ2) */
-
-
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91SAM9261_BASE_TCB0           0xfffa0000
-#define AT91SAM9261_BASE_TC0            0xfffa0000
-#define AT91SAM9261_BASE_TC1            0xfffa0040
-#define AT91SAM9261_BASE_TC2            0xfffa0080
-#define AT91SAM9261_BASE_UDP            0xfffa4000
-#define AT91SAM9261_BASE_MCI            0xfffa8000
-#define AT91SAM9261_BASE_TWI            0xfffac000
-#define AT91SAM9261_BASE_US0            0xfffb0000
-#define AT91SAM9261_BASE_US1            0xfffb4000
-#define AT91SAM9261_BASE_US2            0xfffb8000
-#define AT91SAM9261_BASE_SSC0           0xfffbc000
-#define AT91SAM9261_BASE_SSC1           0xfffc0000
-#define AT91SAM9261_BASE_SSC2           0xfffc4000
-#define AT91SAM9261_BASE_SPI0           0xfffc8000
-#define AT91SAM9261_BASE_SPI1           0xfffcc000
-#define AT91_BASE_SYS                   0xffffea00
-
-
-/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_SDRAMC     (0xffffea00 - AT91_BASE_SYS)
-#define AT91_SMC        (0xffffec00 - AT91_BASE_SYS)
-#define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
-#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
-#define AT91_DBGU       (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOA       (0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOB       (0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOC       (0xfffff800 - AT91_BASE_SYS)
-#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC      (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT        (0xfffffd20 - AT91_BASE_SYS)
-#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
-#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
-#define AT91_GPBR       (0xfffffd50 - AT91_BASE_SYS)
-
-#define AT91_USART0     AT91SAM9261_BASE_US0
-#define AT91_USART1     AT91SAM9261_BASE_US1
-#define AT91_USART2     AT91SAM9261_BASE_US2
-
-
-/*
- * Internal Memory.
- */
-#define AT91SAM9261_SRAM_BASE   0x00300000      /* Internal SRAM base address */
-#define AT91SAM9261_SRAM_SIZE   0x00028000      /* Internal SRAM size (160Kb) */
-
-#define AT91SAM9261_ROM_BASE    0x00400000      /* Internal ROM base address */
-#define AT91SAM9261_ROM_SIZE    SZ_32K          /* Internal ROM size (32Kb) */
-
-#define AT91SAM9261_UHP_BASE    0x00500000      /* USB Host controller */
-#define AT91SAM9261_LCDC_BASE   0x00600000      /* LDC controller */
-
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91sam9261_matrix.h b/include/asm-arm/arch-at91/at91sam9261_matrix.h
deleted file mode 100644
index 6f072421be5b..000000000000
--- a/include/asm-arm/arch-at91/at91sam9261_matrix.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91sam9261_matrix.h
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91SAM9261_MATRIX_H
-#define AT91SAM9261_MATRIX_H
-
-#define AT91_MATRIX_MCFG        (AT91_MATRIX + 0x00)    /* Master Configuration Register */
-#define         AT91_MATRIX_RCB0        (1 << 0)                /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define         AT91_MATRIX_RCB1        (1 << 1)                /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-
-#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x04)    /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x08)    /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x0C)    /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x10)    /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x14)    /* Slave Configuration Register 4 */
-#define         AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
-#define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
-#define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
-#define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
-#define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
-#define         AT91_MATRIX_FIXED_DEFMSTR       (7    << 18)    /* Fixed Index of Default Master */
-
-#define AT91_MATRIX_TCR         (AT91_MATRIX + 0x24)    /* TCM Configuration Register */
-#define         AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
-#define                 AT91_MATRIX_ITCM_0              (0 << 0)
-#define                 AT91_MATRIX_ITCM_16             (5 << 0)
-#define                 AT91_MATRIX_ITCM_32             (6 << 0)
-#define                 AT91_MATRIX_ITCM_64             (7 << 0)
-#define         AT91_MATRIX_DTCM_SIZE           (0xf << 4)      /* Size of DTCM enabled memory block */
-#define                 AT91_MATRIX_DTCM_0              (0 << 4)
-#define                 AT91_MATRIX_DTCM_16             (5 << 4)
-#define                 AT91_MATRIX_DTCM_32             (6 << 4)
-#define                 AT91_MATRIX_DTCM_64             (7 << 4)
-
-#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x30)    /* EBI Chip Select Assignment Register */
-#define         AT91_MATRIX_CS1A                (1 << 1)        /* Chip Select 1 Assignment */
-#define                 AT91_MATRIX_CS1A_SMC            (0 << 1)
-#define                 AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
-#define         AT91_MATRIX_CS3A                (1 << 3)        /* Chip Select 3 Assignment */
-#define                 AT91_MATRIX_CS3A_SMC            (0 << 3)
-#define                 AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
-#define         AT91_MATRIX_CS4A                (1 << 4)        /* Chip Select 4 Assignment */
-#define                 AT91_MATRIX_CS4A_SMC            (0 << 4)
-#define                 AT91_MATRIX_CS4A_SMC_CF1        (1 << 4)
-#define         AT91_MATRIX_CS5A                (1 << 5)        /* Chip Select 5 Assignment */
-#define                 AT91_MATRIX_CS5A_SMC            (0 << 5)
-#define                 AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
-#define         AT91_MATRIX_DBPUC               (1 << 8)        /* Data Bus Pull-up Configuration */
-
-#define AT91_MATRIX_USBPUCR     (AT91_MATRIX + 0x34)    /* USB Pad Pull-Up Control Register */
-#define         AT91_MATRIX_USBPUCR_PUON        (1 << 30)       /* USB Device PAD Pull-up Enable */
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91sam9263.h b/include/asm-arm/arch-at91/at91sam9263.h
deleted file mode 100644
index 018a647311da..000000000000
--- a/include/asm-arm/arch-at91/at91sam9263.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91sam9263.h
- *
- * (C) 2007 Atmel Corporation.
- *
- * Common definitions.
- * Based on AT91SAM9263 datasheet revision B (Preliminary).
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91SAM9263_H
-#define AT91SAM9263_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS             1       /* System Peripherals */
-#define AT91SAM9263_ID_PIOA     2       /* Parallel IO Controller A */
-#define AT91SAM9263_ID_PIOB     3       /* Parallel IO Controller B */
-#define AT91SAM9263_ID_PIOCDE   4       /* Parallel IO Controller C, D and E */
-#define AT91SAM9263_ID_US0      7       /* USART 0 */
-#define AT91SAM9263_ID_US1      8       /* USART 1 */
-#define AT91SAM9263_ID_US2      9       /* USART 2 */
-#define AT91SAM9263_ID_MCI0     10      /* Multimedia Card Interface 0 */
-#define AT91SAM9263_ID_MCI1     11      /* Multimedia Card Interface 1 */
-#define AT91SAM9263_ID_CAN      12      /* CAN */
-#define AT91SAM9263_ID_TWI      13      /* Two-Wire Interface */
-#define AT91SAM9263_ID_SPI0     14      /* Serial Peripheral Interface 0 */
-#define AT91SAM9263_ID_SPI1     15      /* Serial Peripheral Interface 1 */
-#define AT91SAM9263_ID_SSC0     16      /* Serial Synchronous Controller 0 */
-#define AT91SAM9263_ID_SSC1     17      /* Serial Synchronous Controller 1 */
-#define AT91SAM9263_ID_AC97C    18      /* AC97 Controller */
-#define AT91SAM9263_ID_TCB      19      /* Timer Counter 0, 1 and 2 */
-#define AT91SAM9263_ID_PWMC     20      /* Pulse Width Modulation Controller */
-#define AT91SAM9263_ID_EMAC     21      /* Ethernet */
-#define AT91SAM9263_ID_2DGE     23      /* 2D Graphic Engine */
-#define AT91SAM9263_ID_UDP      24      /* USB Device Port */
-#define AT91SAM9263_ID_ISI      25      /* Image Sensor Interface */
-#define AT91SAM9263_ID_LCDC     26      /* LCD Controller */
-#define AT91SAM9263_ID_DMA      27      /* DMA Controller */
-#define AT91SAM9263_ID_UHP      29      /* USB Host port */
-#define AT91SAM9263_ID_IRQ0     30      /* Advanced Interrupt Controller (IRQ0) */
-#define AT91SAM9263_ID_IRQ1     31      /* Advanced Interrupt Controller (IRQ1) */
-
-
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91SAM9263_BASE_UDP            0xfff78000
-#define AT91SAM9263_BASE_TCB0           0xfff7c000
-#define AT91SAM9263_BASE_TC0            0xfff7c000
-#define AT91SAM9263_BASE_TC1            0xfff7c040
-#define AT91SAM9263_BASE_TC2            0xfff7c080
-#define AT91SAM9263_BASE_MCI0           0xfff80000
-#define AT91SAM9263_BASE_MCI1           0xfff84000
-#define AT91SAM9263_BASE_TWI            0xfff88000
-#define AT91SAM9263_BASE_US0            0xfff8c000
-#define AT91SAM9263_BASE_US1            0xfff90000
-#define AT91SAM9263_BASE_US2            0xfff94000
-#define AT91SAM9263_BASE_SSC0           0xfff98000
-#define AT91SAM9263_BASE_SSC1           0xfff9c000
-#define AT91SAM9263_BASE_AC97C          0xfffa0000
-#define AT91SAM9263_BASE_SPI0           0xfffa4000
-#define AT91SAM9263_BASE_SPI1           0xfffa8000
-#define AT91SAM9263_BASE_CAN            0xfffac000
-#define AT91SAM9263_BASE_PWMC           0xfffb8000
-#define AT91SAM9263_BASE_EMAC           0xfffbc000
-#define AT91SAM9263_BASE_ISI            0xfffc4000
-#define AT91SAM9263_BASE_2DGE           0xfffc8000
-#define AT91_BASE_SYS                   0xffffe000
-
-/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_ECC0       (0xffffe000 - AT91_BASE_SYS)
-#define AT91_SDRAMC0    (0xffffe200 - AT91_BASE_SYS)
-#define AT91_SMC0       (0xffffe400 - AT91_BASE_SYS)
-#define AT91_ECC1       (0xffffe600 - AT91_BASE_SYS)
-#define AT91_SDRAMC1    (0xffffe800 - AT91_BASE_SYS)
-#define AT91_SMC1       (0xffffea00 - AT91_BASE_SYS)
-#define AT91_MATRIX     (0xffffec00 - AT91_BASE_SYS)
-#define AT91_CCFG       (0xffffed10 - AT91_BASE_SYS)
-#define AT91_DBGU       (0xffffee00 - AT91_BASE_SYS)
-#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
-#define AT91_PIOA       (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOB       (0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOC       (0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOD       (0xfffff800 - AT91_BASE_SYS)
-#define AT91_PIOE       (0xfffffa00 - AT91_BASE_SYS)
-#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC      (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT0       (0xfffffd20 - AT91_BASE_SYS)
-#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
-#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
-#define AT91_RTT1       (0xfffffd50 - AT91_BASE_SYS)
-#define AT91_GPBR       (0xfffffd60 - AT91_BASE_SYS)
-
-#define AT91_USART0     AT91SAM9263_BASE_US0
-#define AT91_USART1     AT91SAM9263_BASE_US1
-#define AT91_USART2     AT91SAM9263_BASE_US2
-
-#define AT91_SMC        AT91_SMC0
-
-/*
- * Internal Memory.
- */
-#define AT91SAM9263_SRAM0_BASE  0x00300000      /* Internal SRAM 0 base address */
-#define AT91SAM9263_SRAM0_SIZE  (80 * SZ_1K)    /* Internal SRAM 0 size (80Kb) */
-
-#define AT91SAM9263_ROM_BASE    0x00400000      /* Internal ROM base address */
-#define AT91SAM9263_ROM_SIZE    SZ_128K         /* Internal ROM size (128Kb) */
-
-#define AT91SAM9263_SRAM1_BASE  0x00500000      /* Internal SRAM 1 base address */
-#define AT91SAM9263_SRAM1_SIZE  SZ_16K          /* Internal SRAM 1 size (16Kb) */
-
-#define AT91SAM9263_LCDC_BASE   0x00700000      /* LCD Controller */
-#define AT91SAM9263_DMAC_BASE   0x00800000      /* DMA Controller */
-#define AT91SAM9263_UHP_BASE    0x00a00000      /* USB Host controller */
-
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91sam9263_matrix.h b/include/asm-arm/arch-at91/at91sam9263_matrix.h
deleted file mode 100644
index 72f6e668e414..000000000000
--- a/include/asm-arm/arch-at91/at91sam9263_matrix.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91sam9263_matrix.h
- *
- *  Copyright (C) 2006 Atmel Corporation.
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9263 datasheet revision B (Preliminary).
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91SAM9263_MATRIX_H
-#define AT91SAM9263_MATRIX_H
-
-#define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
-#define AT91_MATRIX_MCFG6       (AT91_MATRIX + 0x18)    /* Master Configuration Register 6 */
-#define AT91_MATRIX_MCFG7       (AT91_MATRIX + 0x1C)    /* Master Configuration Register 7 */
-#define AT91_MATRIX_MCFG8       (AT91_MATRIX + 0x20)    /* Master Configuration Register 8 */
-#define         AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
-#define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
-#define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
-#define                 AT91_MATRIX_ULBT_FOUR           (2 << 0)
-#define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
-#define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
-
-#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5       (AT91_MATRIX + 0x54)    /* Slave Configuration Register 5 */
-#define AT91_MATRIX_SCFG6       (AT91_MATRIX + 0x58)    /* Slave Configuration Register 6 */
-#define AT91_MATRIX_SCFG7       (AT91_MATRIX + 0x5C)    /* Slave Configuration Register 7 */
-#define         AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
-#define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
-#define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
-#define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
-#define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
-#define         AT91_MATRIX_FIXED_DEFMSTR       (0xf  << 18)    /* Fixed Index of Default Master */
-#define         AT91_MATRIX_ARBT                (3    << 24)    /* Arbitration Type */
-#define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
-#define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
-
-#define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRBS0       (AT91_MATRIX + 0x84)    /* Priority Register B for Slave 0 */
-#define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRBS1       (AT91_MATRIX + 0x8C)    /* Priority Register B for Slave 1 */
-#define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRBS2       (AT91_MATRIX + 0x94)    /* Priority Register B for Slave 2 */
-#define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRBS3       (AT91_MATRIX + 0x9C)    /* Priority Register B for Slave 3 */
-#define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRBS4       (AT91_MATRIX + 0xA4)    /* Priority Register B for Slave 4 */
-#define AT91_MATRIX_PRAS5       (AT91_MATRIX + 0xA8)    /* Priority Register A for Slave 5 */
-#define AT91_MATRIX_PRBS5       (AT91_MATRIX + 0xAC)    /* Priority Register B for Slave 5 */
-#define AT91_MATRIX_PRAS6       (AT91_MATRIX + 0xB0)    /* Priority Register A for Slave 6 */
-#define AT91_MATRIX_PRBS6       (AT91_MATRIX + 0xB4)    /* Priority Register B for Slave 6 */
-#define AT91_MATRIX_PRAS7       (AT91_MATRIX + 0xB8)    /* Priority Register A for Slave 7 */
-#define AT91_MATRIX_PRBS7       (AT91_MATRIX + 0xBC)    /* Priority Register B for Slave 7 */
-#define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
-#define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
-#define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
-#define         AT91_MATRIX_M3PR                (3 << 12)       /* Master 3 Priority */
-#define         AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
-#define         AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
-#define         AT91_MATRIX_M6PR                (3 << 24)       /* Master 6 Priority */
-#define         AT91_MATRIX_M7PR                (3 << 28)       /* Master 7 Priority */
-#define         AT91_MATRIX_M8PR                (3 << 0)        /* Master 8 Priority (in Register B) */
-
-#define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
-#define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define         AT91_MATRIX_RCB2                (1 << 2)
-#define         AT91_MATRIX_RCB3                (1 << 3)
-#define         AT91_MATRIX_RCB4                (1 << 4)
-#define         AT91_MATRIX_RCB5                (1 << 5)
-#define         AT91_MATRIX_RCB6                (1 << 6)
-#define         AT91_MATRIX_RCB7                (1 << 7)
-#define         AT91_MATRIX_RCB8                (1 << 8)
-
-#define AT91_MATRIX_TCMR        (AT91_MATRIX + 0x114)   /* TCM Configuration Register */
-#define         AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
-#define                 AT91_MATRIX_ITCM_0              (0 << 0)
-#define                 AT91_MATRIX_ITCM_16             (5 << 0)
-#define                 AT91_MATRIX_ITCM_32             (6 << 0)
-#define         AT91_MATRIX_DTCM_SIZE           (0xf << 4)      /* Size of DTCM enabled memory block */
-#define                 AT91_MATRIX_DTCM_0              (0 << 4)
-#define                 AT91_MATRIX_DTCM_16             (5 << 4)
-#define                 AT91_MATRIX_DTCM_32             (6 << 4)
-
-#define AT91_MATRIX_EBI0CSA     (AT91_MATRIX + 0x120)   /* EBI0 Chip Select Assignment Register */
-#define         AT91_MATRIX_EBI0_CS1A           (1 << 1)        /* Chip Select 1 Assignment */
-#define                 AT91_MATRIX_EBI0_CS1A_SMC               (0 << 1)
-#define                 AT91_MATRIX_EBI0_CS1A_SDRAMC            (1 << 1)
-#define         AT91_MATRIX_EBI0_CS3A           (1 << 3)        /* Chip Select 3 Assignment */
-#define                 AT91_MATRIX_EBI0_CS3A_SMC               (0 << 3)
-#define                 AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA    (1 << 3)
-#define         AT91_MATRIX_EBI0_CS4A           (1 << 4)        /* Chip Select 4 Assignment */
-#define                 AT91_MATRIX_EBI0_CS4A_SMC               (0 << 4)
-#define                 AT91_MATRIX_EBI0_CS4A_SMC_CF1           (1 << 4)
-#define         AT91_MATRIX_EBI0_CS5A           (1 << 5)        /* Chip Select 5 Assignment */
-#define                 AT91_MATRIX_EBI0_CS5A_SMC               (0 << 5)
-#define                 AT91_MATRIX_EBI0_CS5A_SMC_CF2           (1 << 5)
-#define         AT91_MATRIX_EBI0_DBPUC          (1 << 8)        /* Data Bus Pull-up Configuration */
-#define         AT91_MATRIX_EBI0_VDDIOMSEL      (1 << 16)       /* Memory voltage selection */
-#define                 AT91_MATRIX_EBI0_VDDIOMSEL_1_8V         (0 << 16)
-#define                 AT91_MATRIX_EBI0_VDDIOMSEL_3_3V         (1 << 16)
-
-#define AT91_MATRIX_EBI1CSA     (AT91_MATRIX + 0x124)   /* EBI1 Chip Select Assignment Register */
-#define         AT91_MATRIX_EBI1_CS1A           (1 << 1)        /* Chip Select 1 Assignment */
-#define                 AT91_MATRIX_EBI1_CS1A_SMC               (0 << 1)
-#define                 AT91_MATRIX_EBI1_CS1A_SDRAMC            (1 << 1)
-#define         AT91_MATRIX_EBI1_CS2A           (1 << 3)        /* Chip Select 3 Assignment */
-#define                 AT91_MATRIX_EBI1_CS2A_SMC               (0 << 3)
-#define                 AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA    (1 << 3)
-#define         AT91_MATRIX_EBI1_DBPUC          (1 << 8)        /* Data Bus Pull-up Configuration */
-#define         AT91_MATRIX_EBI1_VDDIOMSEL      (1 << 16)       /* Memory voltage selection */
-#define                 AT91_MATRIX_EBI1_VDDIOMSEL_1_8V         (0 << 16)
-#define                 AT91_MATRIX_EBI1_VDDIOMSEL_3_3V         (1 << 16)
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91sam9_sdramc.h b/include/asm-arm/arch-at91/at91sam9_sdramc.h
deleted file mode 100644
index d3b8b3da6b4d..000000000000
--- a/include/asm-arm/arch-at91/at91sam9_sdramc.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91sam9_sdramc.h
- *
- * SDRAM Controllers (SDRAMC) - System peripherals registers.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91SAM9_SDRAMC_H
-#define AT91SAM9_SDRAMC_H
-
-/* SDRAM Controller (SDRAMC) registers */
-#define AT91_SDRAMC_MR          (AT91_SDRAMC + 0x00)    /* SDRAM Controller Mode Register */
-#define         AT91_SDRAMC_MODE        (0xf << 0)              /* Command Mode */
-#define                 AT91_SDRAMC_MODE_NORMAL         0
-#define                 AT91_SDRAMC_MODE_NOP            1
-#define                 AT91_SDRAMC_MODE_PRECHARGE      2
-#define                 AT91_SDRAMC_MODE_LMR            3
-#define                 AT91_SDRAMC_MODE_REFRESH        4
-#define                 AT91_SDRAMC_MODE_EXT_LMR        5
-#define                 AT91_SDRAMC_MODE_DEEP           6
-
-#define AT91_SDRAMC_TR          (AT91_SDRAMC + 0x04)    /* SDRAM Controller Refresh Timer Register */
-#define         AT91_SDRAMC_COUNT       (0xfff << 0)            /* Refresh Timer Counter */
-
-#define AT91_SDRAMC_CR          (AT91_SDRAMC + 0x08)    /* SDRAM Controller Configuration Register */
-#define         AT91_SDRAMC_NC          (3 << 0)                /* Number of Column Bits */
-#define                 AT91_SDRAMC_NC_8        (0 << 0)
-#define                 AT91_SDRAMC_NC_9        (1 << 0)
-#define                 AT91_SDRAMC_NC_10       (2 << 0)
-#define                 AT91_SDRAMC_NC_11       (3 << 0)
-#define         AT91_SDRAMC_NR          (3 << 2)                /* Number of Row Bits */
-#define                 AT91_SDRAMC_NR_11       (0 << 2)
-#define                 AT91_SDRAMC_NR_12       (1 << 2)
-#define                 AT91_SDRAMC_NR_13       (2 << 2)
-#define         AT91_SDRAMC_NB          (1 << 4)                /* Number of Banks */
-#define                 AT91_SDRAMC_NB_2        (0 << 4)
-#define                 AT91_SDRAMC_NB_4        (1 << 4)
-#define         AT91_SDRAMC_CAS         (3 << 5)                /* CAS Latency */
-#define                 AT91_SDRAMC_CAS_1       (1 << 5)
-#define                 AT91_SDRAMC_CAS_2       (2 << 5)
-#define                 AT91_SDRAMC_CAS_3       (3 << 5)
-#define         AT91_SDRAMC_DBW         (1 << 7)                /* Data Bus Width */
-#define                 AT91_SDRAMC_DBW_32      (0 << 7)
-#define                 AT91_SDRAMC_DBW_16      (1 << 7)
-#define         AT91_SDRAMC_TWR         (0xf <<  8)             /* Write Recovery Delay */
-#define         AT91_SDRAMC_TRC         (0xf << 12)             /* Row Cycle Delay */
-#define         AT91_SDRAMC_TRP         (0xf << 16)             /* Row Precharge Delay */
-#define         AT91_SDRAMC_TRCD        (0xf << 20)             /* Row to Column Delay */
-#define         AT91_SDRAMC_TRAS        (0xf << 24)             /* Active to Precharge Delay */
-#define         AT91_SDRAMC_TXSR        (0xf << 28)             /* Exit Self Refresh to Active Delay */
-
-#define AT91_SDRAMC_LPR         (AT91_SDRAMC + 0x10)    /* SDRAM Controller Low Power Register */
-#define         AT91_SDRAMC_LPCB                (3 << 0)        /* Low-power Configurations */
-#define                 AT91_SDRAMC_LPCB_DISABLE                0
-#define                 AT91_SDRAMC_LPCB_SELF_REFRESH           1
-#define                 AT91_SDRAMC_LPCB_POWER_DOWN             2
-#define                 AT91_SDRAMC_LPCB_DEEP_POWER_DOWN        3
-#define         AT91_SDRAMC_PASR                (7 << 4)        /* Partial Array Self Refresh */
-#define         AT91_SDRAMC_TCSR                (3 << 8)        /* Temperature Compensated Self Refresh */
-#define         AT91_SDRAMC_DS                  (3 << 10)       /* Drive Strength */
-#define         AT91_SDRAMC_TIMEOUT             (3 << 12)       /* Time to define when Low Power Mode is enabled */
-#define                 AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES        (0 << 12)
-#define                 AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES       (1 << 12)
-#define                 AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES      (2 << 12)
-
-#define AT91_SDRAMC_IER         (AT91_SDRAMC + 0x14)    /* SDRAM Controller Interrupt Enable Register */
-#define AT91_SDRAMC_IDR         (AT91_SDRAMC + 0x18)    /* SDRAM Controller Interrupt Disable Register */
-#define AT91_SDRAMC_IMR         (AT91_SDRAMC + 0x1C)    /* SDRAM Controller Interrupt Mask Register */
-#define AT91_SDRAMC_ISR         (AT91_SDRAMC + 0x20)    /* SDRAM Controller Interrupt Status Register */
-#define         AT91_SDRAMC_RES         (1 << 0)                /* Refresh Error Status */
-
-#define AT91_SDRAMC_MDR         (AT91_SDRAMC + 0x24)    /* SDRAM Memory Device Register */
-#define         AT91_SDRAMC_MD          (3 << 0)                /* Memory Device Type */
-#define                 AT91_SDRAMC_MD_SDRAM            0
-#define                 AT91_SDRAMC_MD_LOW_POWER_SDRAM  1
-
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91sam9_smc.h b/include/asm-arm/arch-at91/at91sam9_smc.h
deleted file mode 100644
index 9e49eed31e50..000000000000
--- a/include/asm-arm/arch-at91/at91sam9_smc.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91sam9_smc.h
- *
- * Static Memory Controllers (SMC) - System peripherals registers.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91SAM9_SMC_H
-#define AT91SAM9_SMC_H
-
-#define AT91_SMC_SETUP(n)       (AT91_SMC + 0x00 + ((n)*0x10))  /* Setup Register for CS n */
-#define         AT91_SMC_NWESETUP       (0x3f << 0)                     /* NWE Setup Length */
-#define                 AT91_SMC_NWESETUP_(x)   ((x) << 0)
-#define         AT91_SMC_NCS_WRSETUP    (0x3f << 8)                     /* NCS Setup Length in Write Access */
-#define                 AT91_SMC_NCS_WRSETUP_(x)        ((x) << 8)
-#define         AT91_SMC_NRDSETUP       (0x3f << 16)                    /* NRD Setup Length */
-#define                 AT91_SMC_NRDSETUP_(x)   ((x) << 16)
-#define         AT91_SMC_NCS_RDSETUP    (0x3f << 24)                    /* NCS Setup Length in Read Access */
-#define                 AT91_SMC_NCS_RDSETUP_(x)        ((x) << 24)
-
-#define AT91_SMC_PULSE(n)       (AT91_SMC + 0x04 + ((n)*0x10))  /* Pulse Register for CS n */
-#define         AT91_SMC_NWEPULSE       (0x7f <<  0)                    /* NWE Pulse Length */
-#define                 AT91_SMC_NWEPULSE_(x)   ((x) << 0)
-#define         AT91_SMC_NCS_WRPULSE    (0x7f <<  8)                    /* NCS Pulse Length in Write Access */
-#define                 AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
-#define         AT91_SMC_NRDPULSE       (0x7f << 16)                    /* NRD Pulse Length */
-#define                 AT91_SMC_NRDPULSE_(x)   ((x) << 16)
-#define         AT91_SMC_NCS_RDPULSE    (0x7f << 24)                    /* NCS Pulse Length in Read Access */
-#define                 AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
-
-#define AT91_SMC_CYCLE(n)       (AT91_SMC + 0x08 + ((n)*0x10))  /* Cycle Register for CS n */
-#define         AT91_SMC_NWECYCLE       (0x1ff << 0 )                   /* Total Write Cycle Length */
-#define                 AT91_SMC_NWECYCLE_(x)   ((x) << 0)
-#define         AT91_SMC_NRDCYCLE       (0x1ff << 16)                   /* Total Read Cycle Length */
-#define                 AT91_SMC_NRDCYCLE_(x)   ((x) << 16)
-
-#define AT91_SMC_MODE(n)        (AT91_SMC + 0x0c + ((n)*0x10))  /* Mode Register for CS n */
-#define         AT91_SMC_READMODE       (1 <<  0)                       /* Read Mode */
-#define         AT91_SMC_WRITEMODE      (1 <<  1)                       /* Write Mode */
-#define         AT91_SMC_EXNWMODE       (3 <<  4)                       /* NWAIT Mode */
-#define                 AT91_SMC_EXNWMODE_DISABLE       (0 << 4)
-#define                 AT91_SMC_EXNWMODE_FROZEN        (2 << 4)
-#define                 AT91_SMC_EXNWMODE_READY         (3 << 4)
-#define         AT91_SMC_BAT            (1 <<  8)                       /* Byte Access Type */
-#define                 AT91_SMC_BAT_SELECT             (0 << 8)
-#define                 AT91_SMC_BAT_WRITE              (1 << 8)
-#define         AT91_SMC_DBW            (3 << 12)                       /* Data Bus Width */
-#define                 AT91_SMC_DBW_8                  (0 << 12)
-#define                 AT91_SMC_DBW_16                 (1 << 12)
-#define                 AT91_SMC_DBW_32                 (2 << 12)
-#define         AT91_SMC_TDF            (0xf << 16)                     /* Data Float Time. */
-#define                 AT91_SMC_TDF_(x)                ((x) << 16)
-#define         AT91_SMC_TDFMODE        (1 << 20)                       /* TDF Optimization - Enabled */
-#define         AT91_SMC_PMEN           (1 << 24)                       /* Page Mode Enabled */
-#define         AT91_SMC_PS             (3 << 28)                       /* Page Size */
-#define                 AT91_SMC_PS_4                   (0 << 28)
-#define                 AT91_SMC_PS_8                   (1 << 28)
-#define                 AT91_SMC_PS_16                  (2 << 28)
-#define                 AT91_SMC_PS_32                  (3 << 28)
-
-#if defined(AT91_SMC1)          /* The AT91SAM9263 has 2 Static Memory contollers */
-#define AT91_SMC1_SETUP(n)      (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
-#define AT91_SMC1_PULSE(n)      (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
-#define AT91_SMC1_CYCLE(n)      (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
-#define AT91_SMC1_MODE(n)       (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
-#endif
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91sam9rl.h b/include/asm-arm/arch-at91/at91sam9rl.h
deleted file mode 100644
index 622e56f81d42..000000000000
--- a/include/asm-arm/arch-at91/at91sam9rl.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91sam9260.h
- *
- *  Copyright (C) 2007 Atmel Corporation
- *
- * Common definitions.
- * Based on AT91SAM9RL datasheet revision A. (Preliminary)
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file COPYING in the main directory of this archive for
- * more details.
- */
-
-#ifndef AT91SAM9RL_H
-#define AT91SAM9RL_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS             1       /* System Controller */
-#define AT91SAM9RL_ID_PIOA      2       /* Parallel IO Controller A */
-#define AT91SAM9RL_ID_PIOB      3       /* Parallel IO Controller B */
-#define AT91SAM9RL_ID_PIOC      4       /* Parallel IO Controller C */
-#define AT91SAM9RL_ID_PIOD      5       /* Parallel IO Controller D */
-#define AT91SAM9RL_ID_US0       6       /* USART 0 */
-#define AT91SAM9RL_ID_US1       7       /* USART 1 */
-#define AT91SAM9RL_ID_US2       8       /* USART 2 */
-#define AT91SAM9RL_ID_US3       9       /* USART 3 */
-#define AT91SAM9RL_ID_MCI       10      /* Multimedia Card Interface */
-#define AT91SAM9RL_ID_TWI0      11      /* TWI 0 */
-#define AT91SAM9RL_ID_TWI1      12      /* TWI 1 */
-#define AT91SAM9RL_ID_SPI       13      /* Serial Peripheral Interface */
-#define AT91SAM9RL_ID_SSC0      14      /* Serial Synchronous Controller 0 */
-#define AT91SAM9RL_ID_SSC1      15      /* Serial Synchronous Controller 1 */
-#define AT91SAM9RL_ID_TC0       16      /* Timer Counter 0 */
-#define AT91SAM9RL_ID_TC1       17      /* Timer Counter 1 */
-#define AT91SAM9RL_ID_TC2       18      /* Timer Counter 2 */
-#define AT91SAM9RL_ID_PWMC      19      /* Pulse Width Modulation Controller */
-#define AT91SAM9RL_ID_TSC       20      /* Touch Screen Controller */
-#define AT91SAM9RL_ID_DMA       21      /* DMA Controller */
-#define AT91SAM9RL_ID_UDPHS     22      /* USB Device HS */
-#define AT91SAM9RL_ID_LCDC      23      /* LCD Controller */
-#define AT91SAM9RL_ID_AC97C     24      /* AC97 Controller */
-#define AT91SAM9RL_ID_IRQ0      31      /* Advanced Interrupt Controller (IRQ0) */
-
-
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91SAM9RL_BASE_TCB0    0xfffa0000
-#define AT91SAM9RL_BASE_TC0     0xfffa0000
-#define AT91SAM9RL_BASE_TC1     0xfffa0040
-#define AT91SAM9RL_BASE_TC2     0xfffa0080
-#define AT91SAM9RL_BASE_MCI     0xfffa4000
-#define AT91SAM9RL_BASE_TWI0    0xfffa8000
-#define AT91SAM9RL_BASE_TWI1    0xfffac000
-#define AT91SAM9RL_BASE_US0     0xfffb0000
-#define AT91SAM9RL_BASE_US1     0xfffb4000
-#define AT91SAM9RL_BASE_US2     0xfffb8000
-#define AT91SAM9RL_BASE_US3     0xfffbc000
-#define AT91SAM9RL_BASE_SSC0    0xfffc0000
-#define AT91SAM9RL_BASE_SSC1    0xfffc4000
-#define AT91SAM9RL_BASE_PWMC    0xfffc8000
-#define AT91SAM9RL_BASE_SPI     0xfffcc000
-#define AT91SAM9RL_BASE_TSC     0xfffd0000
-#define AT91SAM9RL_BASE_UDPHS   0xfffd4000
-#define AT91SAM9RL_BASE_AC97C   0xfffd8000
-#define AT91_BASE_SYS           0xffffc000
-
-
-/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_DMA        (0xffffe600 - AT91_BASE_SYS)
-#define AT91_ECC        (0xffffe800 - AT91_BASE_SYS)
-#define AT91_SDRAMC     (0xffffea00 - AT91_BASE_SYS)
-#define AT91_SMC        (0xffffec00 - AT91_BASE_SYS)
-#define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
-#define AT91_CCFG       (0xffffef10 - AT91_BASE_SYS)
-#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
-#define AT91_DBGU       (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOA       (0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOB       (0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOC       (0xfffff800 - AT91_BASE_SYS)
-#define AT91_PIOD       (0xfffffa00 - AT91_BASE_SYS)
-#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC      (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT        (0xfffffd20 - AT91_BASE_SYS)
-#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
-#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
-#define AT91_SCKCR      (0xfffffd50 - AT91_BASE_SYS)
-#define AT91_GPBR       (0xfffffd60 - AT91_BASE_SYS)
-#define AT91_RTC        (0xfffffe00 - AT91_BASE_SYS)
-
-#define AT91_USART0     AT91SAM9RL_BASE_US0
-#define AT91_USART1     AT91SAM9RL_BASE_US1
-#define AT91_USART2     AT91SAM9RL_BASE_US2
-#define AT91_USART3     AT91SAM9RL_BASE_US3
-
-
-/*
- * Internal Memory.
- */
-#define AT91SAM9RL_SRAM_BASE    0x00300000      /* Internal SRAM base address */
-#define AT91SAM9RL_SRAM_SIZE    SZ_16K          /* Internal SRAM size (16Kb) */
-
-#define AT91SAM9RL_ROM_BASE     0x00400000      /* Internal ROM base address */
-#define AT91SAM9RL_ROM_SIZE     (2 * SZ_16K)    /* Internal ROM size (32Kb) */
-
-#define AT91SAM9RL_LCDC_BASE    0x00500000      /* LCD Controller */
-#define AT91SAM9RL_UDPHS_FIFO   0x00600000      /* USB Device HS controller */
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91sam9rl_matrix.h b/include/asm-arm/arch-at91/at91sam9rl_matrix.h
deleted file mode 100644
index 84224174e6a1..000000000000
--- a/include/asm-arm/arch-at91/at91sam9rl_matrix.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91sam9rl_matrix.h
- *
- *  Copyright (C) 2007 Atmel Corporation
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9RL datasheet revision A. (Preliminary)
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file COPYING in the main directory of this archive for
- * more details.
- */
-
-#ifndef AT91SAM9RL_MATRIX_H
-#define AT91SAM9RL_MATRIX_H
-
-#define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
-#define         AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
-#define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
-#define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
-#define                 AT91_MATRIX_ULBT_FOUR           (2 << 0)
-#define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
-#define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
-
-#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5       (AT91_MATRIX + 0x54)    /* Slave Configuration Register 5 */
-#define         AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
-#define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
-#define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
-#define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
-#define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
-#define         AT91_MATRIX_FIXED_DEFMSTR       (0xf  << 18)    /* Fixed Index of Default Master */
-#define         AT91_MATRIX_ARBT                (3    << 24)    /* Arbitration Type */
-#define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
-#define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
-
-#define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRAS5       (AT91_MATRIX + 0xA8)    /* Priority Register A for Slave 5 */
-#define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
-#define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
-#define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
-#define         AT91_MATRIX_M3PR                (3 << 12)       /* Master 3 Priority */
-#define         AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
-#define         AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
-
-#define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
-#define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define         AT91_MATRIX_RCB2                (1 << 2)
-#define         AT91_MATRIX_RCB3                (1 << 3)
-#define         AT91_MATRIX_RCB4                (1 << 4)
-#define         AT91_MATRIX_RCB5                (1 << 5)
-
-#define AT91_MATRIX_TCMR        (AT91_MATRIX + 0x114)   /* TCM Configuration Register */
-#define         AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
-#define                 AT91_MATRIX_ITCM_0              (0 << 0)
-#define                 AT91_MATRIX_ITCM_16             (5 << 0)
-#define                 AT91_MATRIX_ITCM_32             (6 << 0)
-#define         AT91_MATRIX_DTCM_SIZE           (0xf << 4)      /* Size of DTCM enabled memory block */
-#define                 AT91_MATRIX_DTCM_0              (0 << 4)
-#define                 AT91_MATRIX_DTCM_16             (5 << 4)
-#define                 AT91_MATRIX_DTCM_32             (6 << 4)
-
-#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x120)   /* EBI0 Chip Select Assignment Register */
-#define         AT91_MATRIX_CS1A                (1 << 1)        /* Chip Select 1 Assignment */
-#define                 AT91_MATRIX_CS1A_SMC            (0 << 1)
-#define                 AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
-#define         AT91_MATRIX_CS3A                (1 << 3)        /* Chip Select 3 Assignment */
-#define                 AT91_MATRIX_CS3A_SMC            (0 << 3)
-#define                 AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
-#define         AT91_MATRIX_CS4A                (1 << 4)        /* Chip Select 4 Assignment */
-#define                 AT91_MATRIX_CS4A_SMC            (0 << 4)
-#define                 AT91_MATRIX_CS4A_SMC_CF1        (1 << 4)
-#define         AT91_MATRIX_CS5A                (1 << 5)        /* Chip Select 5 Assignment */
-#define                 AT91_MATRIX_CS5A_SMC            (0 << 5)
-#define                 AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
-#define         AT91_MATRIX_DBPUC               (1 << 8)        /* Data Bus Pull-up Configuration */
-#define         AT91_MATRIX_VDDIOMSEL           (1 << 16)       /* Memory voltage selection */
-#define                 AT91_MATRIX_VDDIOMSEL_1_8V      (0 << 16)
-#define                 AT91_MATRIX_VDDIOMSEL_3_3V      (1 << 16)
-
-
-#endif
diff --git a/include/asm-arm/arch-at91/at91x40.h b/include/asm-arm/arch-at91/at91x40.h
deleted file mode 100644
index 612203e0177f..000000000000
--- a/include/asm-arm/arch-at91/at91x40.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91x40.h
- *
- * (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91X40_H
-#define AT91X40_H
-
-/*
- *      IRQ list.
- */
-#define AT91_ID_FIQ             0       /* FIQ */
-#define AT91_ID_SYS             1       /* System Peripheral */
-#define AT91X40_ID_USART0       2       /* USART port 0 */
-#define AT91X40_ID_USART1       3       /* USART port 1 */
-#define AT91X40_ID_TC0          4       /* Timer/Counter 0 */
-#define AT91X40_ID_TC1          5       /* Timer/Counter 1*/
-#define AT91X40_ID_TC2          6       /* Timer/Counter 2*/
-#define AT91X40_ID_WD           7       /* Watchdog? */
-#define AT91X40_ID_PIOA         8       /* Parallel IO Controller A */
-
-#define AT91X40_ID_IRQ0         16      /* External IRQ 0 */
-#define AT91X40_ID_IRQ1         17      /* External IRQ 1 */
-#define AT91X40_ID_IRQ2         18      /* External IRQ 2 */
-
-/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_BASE_SYS   0xffc00000
-
-#define AT91_EBI        (0xffe00000 - AT91_BASE_SYS)    /* External Bus Interface */
-#define AT91_SF         (0xfff00000 - AT91_BASE_SYS)    /* Special Function */
-#define AT91_USART1     (0xfffcc000 - AT91_BASE_SYS)    /* USART 1 */
-#define AT91_USART0     (0xfffd0000 - AT91_BASE_SYS)    /* USART 0 */
-#define AT91_TC         (0xfffe0000 - AT91_BASE_SYS)    /* Timer Counter */
-#define AT91_PIOA       (0xffff0000 - AT91_BASE_SYS)    /* PIO Controller A */
-#define AT91_PS         (0xffff4000 - AT91_BASE_SYS)    /* Power Save */
-#define AT91_WD         (0xffff8000 - AT91_BASE_SYS)    /* Watchdog Timer */
-#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)    /* Advanced Interrupt Controller */
-
-/*
- * The AT91x40 series doesn't have a debug unit like the other AT91 parts.
- * But it does have a chip identify register and extension ID, so define at
- * least these here.
- */
-#define AT91_DBGU_CIDR  (AT91_SF + 0)   /* CIDR in PS segment */
-#define AT91_DBGU_EXID  (AT91_SF + 4)   /* EXID in PS segment */
-
-#endif /* AT91X40_H */
diff --git a/include/asm-arm/arch-at91/board.h b/include/asm-arm/arch-at91/board.h
deleted file mode 100644
index 48bbd854f57d..000000000000
--- a/include/asm-arm/arch-at91/board.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * include/asm-arm/arch-at91/board.h
- *
- *  Copyright (C) 2005 HP Labs
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-/*
- * These are data structures found in platform_device.dev.platform_data,
- * and describing board-specific data needed by drivers.  For example,
- * which pin is used for a given GPIO role.
- *
- * In 2.6, drivers should strongly avoid board-specific knowledge so
- * that supporting new boards normally won't require driver patches.
- * Most board-specific knowledge should be in arch/.../board-*.c files.
- */
-
-#ifndef __ASM_ARCH_BOARD_H
-#define __ASM_ARCH_BOARD_H
-
-#include <linux/mtd/partitions.h>
-#include <linux/device.h>
-#include <linux/i2c.h>
-#include <linux/leds.h>
-#include <linux/spi/spi.h>
-#include <linux/usb/atmel_usba_udc.h>
-
- /* USB Device */
-struct at91_udc_data {
-        u8      vbus_pin;               /* high == host powering us */
-        u8      pullup_pin;             /* active == D+ pulled up */
-        u8      pullup_active_low;      /* true == pullup_pin is active low */
-};
-extern void __init at91_add_device_udc(struct at91_udc_data *data);
-
- /* USB High Speed Device */
-extern void __init at91_add_device_usba(struct usba_platform_data *data);
-
- /* Compact Flash */
-struct at91_cf_data {
-        u8      irq_pin;                /* I/O IRQ */
-        u8      det_pin;                /* Card detect */
-        u8      vcc_pin;                /* power switching */
-        u8      rst_pin;                /* card reset */
-        u8      chipselect;             /* EBI Chip Select number */
-};
-extern void __init at91_add_device_cf(struct at91_cf_data *data);
-
- /* MMC / SD */
-struct at91_mmc_data {
-        u8              det_pin;        /* card detect IRQ */
-        unsigned        slot_b:1;       /* uses Slot B */
-        unsigned        wire4:1;        /* (SD) supports DAT0..DAT3 */
-        u8              wp_pin;         /* (SD) writeprotect detect */
-        u8              vcc_pin;        /* power switching (high == on) */
-};
-extern void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data);
-
- /* Ethernet (EMAC & MACB) */
-struct at91_eth_data {
-        u32             phy_mask;
-        u8              phy_irq_pin;    /* PHY IRQ */
-        u8              is_rmii;        /* using RMII interface? */
-};
-extern void __init at91_add_device_eth(struct at91_eth_data *data);
-
-#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9)
-#define eth_platform_data       at91_eth_data
-#endif
-
- /* USB Host */
-struct at91_usbh_data {
-        u8              ports;          /* number of ports on root hub */
-        u8              vbus_pin[];     /* port power-control pin */
-};
-extern void __init at91_add_device_usbh(struct at91_usbh_data *data);
-
- /* NAND / SmartMedia */
-struct atmel_nand_data {
-        u8              enable_pin;     /* chip enable */
-        u8              det_pin;        /* card detect */
-        u8              rdy_pin;        /* ready/busy */
-        u8              ale;            /* address line number connected to ALE */
-        u8              cle;            /* address line number connected to CLE */
-        u8              bus_width_16;   /* buswidth is 16 bit */
-        struct mtd_partition* (*partition_info)(int, int*);
-};
-extern void __init at91_add_device_nand(struct atmel_nand_data *data);
-
- /* I2C*/
-extern void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices);
-
- /* SPI */
-extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices);
-
- /* Serial */
-#define ATMEL_UART_CTS  0x01
-#define ATMEL_UART_RTS  0x02
-#define ATMEL_UART_DSR  0x04
-#define ATMEL_UART_DTR  0x08
-#define ATMEL_UART_DCD  0x10
-#define ATMEL_UART_RI   0x20
-
-extern void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins);
-extern void __init at91_set_serial_console(unsigned portnr);
-
-struct at91_uart_config {
-        unsigned short  console_tty;    /* tty number of serial console */
-        unsigned short  nr_tty;         /* number of serial tty's */
-        short           tty_map[];      /* map UART to tty number */
-};
-extern struct platform_device *atmel_default_console_device;
-extern void __init __deprecated at91_init_serial(struct at91_uart_config *config);
-
-struct atmel_uart_data {
-        short           use_dma_tx;     /* use transmit DMA? */
-        short           use_dma_rx;     /* use receive DMA? */
-        void __iomem    *regs;          /* virtual base address, if any */
-};
-extern void __init at91_add_device_serial(void);
-
-/*
- * SSC -- accessed through ssc_request(id).  Drivers don't bind to SSC
- * platform devices.  Their SSC ID is part of their configuration data,
- * along with information about which SSC signals they should use.
- */
-#define ATMEL_SSC_TK    0x01
-#define ATMEL_SSC_TF    0x02
-#define ATMEL_SSC_TD    0x04
-#define ATMEL_SSC_TX    (ATMEL_SSC_TK | ATMEL_SSC_TF | ATMEL_SSC_TD)
-
-#define ATMEL_SSC_RK    0x10
-#define ATMEL_SSC_RF    0x20
-#define ATMEL_SSC_RD    0x40
-#define ATMEL_SSC_RX    (ATMEL_SSC_RK | ATMEL_SSC_RF | ATMEL_SSC_RD)
-
-extern void __init at91_add_device_ssc(unsigned id, unsigned pins);
-
- /* LCD Controller */
-struct atmel_lcdfb_info;
-extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data);
-
- /* AC97 */
-struct atmel_ac97_data {
-        u8              reset_pin;      /* reset */
-};
-extern void __init at91_add_device_ac97(struct atmel_ac97_data *data);
-
- /* ISI */
-extern void __init at91_add_device_isi(void);
-
- /* LEDs */
-extern void __init at91_init_leds(u8 cpu_led, u8 timer_led);
-extern void __init at91_gpio_leds(struct gpio_led *leds, int nr);
-
-/* FIXME: this needs a better location, but gets stuff building again */
-extern int at91_suspend_entering_slow_clock(void);
-
-#endif
diff --git a/include/asm-arm/arch-at91/cpu.h b/include/asm-arm/arch-at91/cpu.h
deleted file mode 100644
index f24b55c9083f..000000000000
--- a/include/asm-arm/arch-at91/cpu.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * include/asm-arm/arch-at91/cpu.h
- *
- *  Copyright (C) 2006 SAN People
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-
-#ifndef __ASM_ARCH_CPU_H
-#define __ASM_ARCH_CPU_H
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_dbgu.h>
-
-
-#define ARCH_ID_AT91RM9200      0x09290780
-#define ARCH_ID_AT91SAM9260     0x019803a0
-#define ARCH_ID_AT91SAM9261     0x019703a0
-#define ARCH_ID_AT91SAM9263     0x019607a0
-#define ARCH_ID_AT91SAM9G20     0x019905a0
-#define ARCH_ID_AT91SAM9RL64    0x019b03a0
-#define ARCH_ID_AT91CAP9        0x039A03A0
-
-#define ARCH_ID_AT91SAM9XE128   0x329973a0
-#define ARCH_ID_AT91SAM9XE256   0x329a93a0
-#define ARCH_ID_AT91SAM9XE512   0x329aa3a0
-
-#define ARCH_ID_AT91M40800      0x14080044
-#define ARCH_ID_AT91R40807      0x44080746
-#define ARCH_ID_AT91M40807      0x14080745
-#define ARCH_ID_AT91R40008      0x44000840
-
-static inline unsigned long at91_cpu_identify(void)
-{
-        return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION);
-}
-
-
-#define ARCH_FAMILY_AT91X92     0x09200000
-#define ARCH_FAMILY_AT91SAM9    0x01900000
-#define ARCH_FAMILY_AT91SAM9XE  0x02900000
-
-static inline unsigned long at91_arch_identify(void)
-{
-        return (at91_sys_read(AT91_DBGU_CIDR) & AT91_CIDR_ARCH);
-}
-
-
-#ifdef CONFIG_ARCH_AT91RM9200
-#define cpu_is_at91rm9200()     (at91_cpu_identify() == ARCH_ID_AT91RM9200)
-#else
-#define cpu_is_at91rm9200()     (0)
-#endif
-
-#ifdef CONFIG_ARCH_AT91SAM9260
-#define cpu_is_at91sam9xe()     (at91_arch_identify() == ARCH_FAMILY_AT91SAM9XE)
-#define cpu_is_at91sam9260()    ((at91_cpu_identify() == ARCH_ID_AT91SAM9260) || cpu_is_at91sam9xe())
-#else
-#define cpu_is_at91sam9xe()     (0)
-#define cpu_is_at91sam9260()    (0)
-#endif
-
-#ifdef CONFIG_ARCH_AT91SAM9G20
-#define cpu_is_at91sam9g20()    (at91_cpu_identify() == ARCH_ID_AT91SAM9G20)
-#else
-#define cpu_is_at91sam9g20()    (0)
-#endif
-
-#ifdef CONFIG_ARCH_AT91SAM9261
-#define cpu_is_at91sam9261()    (at91_cpu_identify() == ARCH_ID_AT91SAM9261)
-#else
-#define cpu_is_at91sam9261()    (0)
-#endif
-
-#ifdef CONFIG_ARCH_AT91SAM9263
-#define cpu_is_at91sam9263()    (at91_cpu_identify() == ARCH_ID_AT91SAM9263)
-#else
-#define cpu_is_at91sam9263()    (0)
-#endif
-
-#ifdef CONFIG_ARCH_AT91SAM9RL
-#define cpu_is_at91sam9rl()     (at91_cpu_identify() == ARCH_ID_AT91SAM9RL64)
-#else
-#define cpu_is_at91sam9rl()     (0)
-#endif
-
-#ifdef CONFIG_ARCH_AT91CAP9
-#define cpu_is_at91cap9()       (at91_cpu_identify() == ARCH_ID_AT91CAP9)
-#else
-#define cpu_is_at91cap9()       (0)
-#endif
-
-/*
- * Since this is ARM, we will never run on any AVR32 CPU. But these
- * definitions may reduce clutter in common drivers.
- */
-#define cpu_is_at32ap7000()     (0)
-
-#endif
diff --git a/include/asm-arm/arch-at91/debug-macro.S b/include/asm-arm/arch-at91/debug-macro.S
deleted file mode 100644
index ff28696b6d90..000000000000
--- a/include/asm-arm/arch-at91/debug-macro.S
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * include/asm-arm/arch-at91/debug-macro.S
- *
- *  Copyright (C) 2003-2005 SAN People
- *
- * Debugging macro include header
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_dbgu.h>
-
-        .macro  addruart,rx
-        mrc     p15, 0, \rx, c1, c0
-        tst     \rx, #1                                         @ MMU enabled?
-        ldreq   \rx, =(AT91_BASE_SYS + AT91_DBGU)               @ System peripherals (phys address)
-        ldrne   \rx, =(AT91_VA_BASE_SYS + AT91_DBGU)            @ System peripherals (virt address)
-        .endm
-
-        .macro  senduart,rd,rx
-        strb    \rd, [\rx, #(AT91_DBGU_THR - AT91_DBGU)]        @ Write to Transmitter Holding Register
-        .endm
-
-        .macro  waituart,rd,rx
-1001:   ldr     \rd, [\rx, #(AT91_DBGU_SR - AT91_DBGU)]         @ Read Status Register
-        tst     \rd, #AT91_DBGU_TXRDY                           @ DBGU_TXRDY = 1 when ready to transmit
-        beq     1001b
-        .endm
-
-        .macro  busyuart,rd,rx
-1001:   ldr     \rd, [\rx, #(AT91_DBGU_SR - AT91_DBGU)]         @ Read Status Register
-        tst     \rd, #AT91_DBGU_TXEMPTY                         @ DBGU_TXEMPTY = 1 when transmission complete
-        beq     1001b
-        .endm
-
diff --git a/include/asm-arm/arch-at91/dma.h b/include/asm-arm/arch-at91/dma.h
deleted file mode 100644
index 774565412beb..000000000000
--- a/include/asm-arm/arch-at91/dma.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * include/asm-arm/arch-at91/dma.h
- *
- *  Copyright (C) 2003 SAN People
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
diff --git a/include/asm-arm/arch-at91/entry-macro.S b/include/asm-arm/arch-at91/entry-macro.S
deleted file mode 100644
index cbaf6050154a..000000000000
--- a/include/asm-arm/arch-at91/entry-macro.S
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * include/asm-arm/arch-at91/entry-macro.S
- *
- *  Copyright (C) 2003-2005 SAN People
- *
- * Low-level IRQ helper macros for AT91RM9200 platforms
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_aic.h>
-
-        .macro  disable_fiq
-        .endm
-
-        .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =(AT91_VA_BASE_SYS + AT91_AIC)           @ base virtual address of AIC peripheral
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        ldr     \irqnr, [\base, #(AT91_AIC_IVR - AT91_AIC)]     @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
-        ldr     \irqstat, [\base, #(AT91_AIC_ISR - AT91_AIC)]   @ read interrupt source number
-        teq     \irqstat, #0                                    @ ISR is 0 when no current interrupt, or spurious interrupt
-        streq   \tmp, [\base, #(AT91_AIC_EOICR - AT91_AIC)]     @ not going to be handled further, then ACK it now.
-        .endm
-
diff --git a/include/asm-arm/arch-at91/gpio.h b/include/asm-arm/arch-at91/gpio.h
deleted file mode 100644
index 0a241e2fb672..000000000000
--- a/include/asm-arm/arch-at91/gpio.h
+++ /dev/null
@@ -1,252 +0,0 @@
-/*
- * include/asm-arm/arch-at91/gpio.h
- *
- *  Copyright (C) 2005 HP Labs
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-
-#ifndef __ASM_ARCH_AT91RM9200_GPIO_H
-#define __ASM_ARCH_AT91RM9200_GPIO_H
-
-#include <asm/irq.h>
-
-#define PIN_BASE                NR_AIC_IRQS
-
-#define MAX_GPIO_BANKS          5
-
-/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
-
-#define AT91_PIN_PA0    (PIN_BASE + 0x00 + 0)
-#define AT91_PIN_PA1    (PIN_BASE + 0x00 + 1)
-#define AT91_PIN_PA2    (PIN_BASE + 0x00 + 2)
-#define AT91_PIN_PA3    (PIN_BASE + 0x00 + 3)
-#define AT91_PIN_PA4    (PIN_BASE + 0x00 + 4)
-#define AT91_PIN_PA5    (PIN_BASE + 0x00 + 5)
-#define AT91_PIN_PA6    (PIN_BASE + 0x00 + 6)
-#define AT91_PIN_PA7    (PIN_BASE + 0x00 + 7)
-#define AT91_PIN_PA8    (PIN_BASE + 0x00 + 8)
-#define AT91_PIN_PA9    (PIN_BASE + 0x00 + 9)
-#define AT91_PIN_PA10   (PIN_BASE + 0x00 + 10)
-#define AT91_PIN_PA11   (PIN_BASE + 0x00 + 11)
-#define AT91_PIN_PA12   (PIN_BASE + 0x00 + 12)
-#define AT91_PIN_PA13   (PIN_BASE + 0x00 + 13)
-#define AT91_PIN_PA14   (PIN_BASE + 0x00 + 14)
-#define AT91_PIN_PA15   (PIN_BASE + 0x00 + 15)
-#define AT91_PIN_PA16   (PIN_BASE + 0x00 + 16)
-#define AT91_PIN_PA17   (PIN_BASE + 0x00 + 17)
-#define AT91_PIN_PA18   (PIN_BASE + 0x00 + 18)
-#define AT91_PIN_PA19   (PIN_BASE + 0x00 + 19)
-#define AT91_PIN_PA20   (PIN_BASE + 0x00 + 20)
-#define AT91_PIN_PA21   (PIN_BASE + 0x00 + 21)
-#define AT91_PIN_PA22   (PIN_BASE + 0x00 + 22)
-#define AT91_PIN_PA23   (PIN_BASE + 0x00 + 23)
-#define AT91_PIN_PA24   (PIN_BASE + 0x00 + 24)
-#define AT91_PIN_PA25   (PIN_BASE + 0x00 + 25)
-#define AT91_PIN_PA26   (PIN_BASE + 0x00 + 26)
-#define AT91_PIN_PA27   (PIN_BASE + 0x00 + 27)
-#define AT91_PIN_PA28   (PIN_BASE + 0x00 + 28)
-#define AT91_PIN_PA29   (PIN_BASE + 0x00 + 29)
-#define AT91_PIN_PA30   (PIN_BASE + 0x00 + 30)
-#define AT91_PIN_PA31   (PIN_BASE + 0x00 + 31)
-
-#define AT91_PIN_PB0    (PIN_BASE + 0x20 + 0)
-#define AT91_PIN_PB1    (PIN_BASE + 0x20 + 1)
-#define AT91_PIN_PB2    (PIN_BASE + 0x20 + 2)
-#define AT91_PIN_PB3    (PIN_BASE + 0x20 + 3)
-#define AT91_PIN_PB4    (PIN_BASE + 0x20 + 4)
-#define AT91_PIN_PB5    (PIN_BASE + 0x20 + 5)
-#define AT91_PIN_PB6    (PIN_BASE + 0x20 + 6)
-#define AT91_PIN_PB7    (PIN_BASE + 0x20 + 7)
-#define AT91_PIN_PB8    (PIN_BASE + 0x20 + 8)
-#define AT91_PIN_PB9    (PIN_BASE + 0x20 + 9)
-#define AT91_PIN_PB10   (PIN_BASE + 0x20 + 10)
-#define AT91_PIN_PB11   (PIN_BASE + 0x20 + 11)
-#define AT91_PIN_PB12   (PIN_BASE + 0x20 + 12)
-#define AT91_PIN_PB13   (PIN_BASE + 0x20 + 13)
-#define AT91_PIN_PB14   (PIN_BASE + 0x20 + 14)
-#define AT91_PIN_PB15   (PIN_BASE + 0x20 + 15)
-#define AT91_PIN_PB16   (PIN_BASE + 0x20 + 16)
-#define AT91_PIN_PB17   (PIN_BASE + 0x20 + 17)
-#define AT91_PIN_PB18   (PIN_BASE + 0x20 + 18)
-#define AT91_PIN_PB19   (PIN_BASE + 0x20 + 19)
-#define AT91_PIN_PB20   (PIN_BASE + 0x20 + 20)
-#define AT91_PIN_PB21   (PIN_BASE + 0x20 + 21)
-#define AT91_PIN_PB22   (PIN_BASE + 0x20 + 22)
-#define AT91_PIN_PB23   (PIN_BASE + 0x20 + 23)
-#define AT91_PIN_PB24   (PIN_BASE + 0x20 + 24)
-#define AT91_PIN_PB25   (PIN_BASE + 0x20 + 25)
-#define AT91_PIN_PB26   (PIN_BASE + 0x20 + 26)
-#define AT91_PIN_PB27   (PIN_BASE + 0x20 + 27)
-#define AT91_PIN_PB28   (PIN_BASE + 0x20 + 28)
-#define AT91_PIN_PB29   (PIN_BASE + 0x20 + 29)
-#define AT91_PIN_PB30   (PIN_BASE + 0x20 + 30)
-#define AT91_PIN_PB31   (PIN_BASE + 0x20 + 31)
-
-#define AT91_PIN_PC0    (PIN_BASE + 0x40 + 0)
-#define AT91_PIN_PC1    (PIN_BASE + 0x40 + 1)
-#define AT91_PIN_PC2    (PIN_BASE + 0x40 + 2)
-#define AT91_PIN_PC3    (PIN_BASE + 0x40 + 3)
-#define AT91_PIN_PC4    (PIN_BASE + 0x40 + 4)
-#define AT91_PIN_PC5    (PIN_BASE + 0x40 + 5)
-#define AT91_PIN_PC6    (PIN_BASE + 0x40 + 6)
-#define AT91_PIN_PC7    (PIN_BASE + 0x40 + 7)
-#define AT91_PIN_PC8    (PIN_BASE + 0x40 + 8)
-#define AT91_PIN_PC9    (PIN_BASE + 0x40 + 9)
-#define AT91_PIN_PC10   (PIN_BASE + 0x40 + 10)
-#define AT91_PIN_PC11   (PIN_BASE + 0x40 + 11)
-#define AT91_PIN_PC12   (PIN_BASE + 0x40 + 12)
-#define AT91_PIN_PC13   (PIN_BASE + 0x40 + 13)
-#define AT91_PIN_PC14   (PIN_BASE + 0x40 + 14)
-#define AT91_PIN_PC15   (PIN_BASE + 0x40 + 15)
-#define AT91_PIN_PC16   (PIN_BASE + 0x40 + 16)
-#define AT91_PIN_PC17   (PIN_BASE + 0x40 + 17)
-#define AT91_PIN_PC18   (PIN_BASE + 0x40 + 18)
-#define AT91_PIN_PC19   (PIN_BASE + 0x40 + 19)
-#define AT91_PIN_PC20   (PIN_BASE + 0x40 + 20)
-#define AT91_PIN_PC21   (PIN_BASE + 0x40 + 21)
-#define AT91_PIN_PC22   (PIN_BASE + 0x40 + 22)
-#define AT91_PIN_PC23   (PIN_BASE + 0x40 + 23)
-#define AT91_PIN_PC24   (PIN_BASE + 0x40 + 24)
-#define AT91_PIN_PC25   (PIN_BASE + 0x40 + 25)
-#define AT91_PIN_PC26   (PIN_BASE + 0x40 + 26)
-#define AT91_PIN_PC27   (PIN_BASE + 0x40 + 27)
-#define AT91_PIN_PC28   (PIN_BASE + 0x40 + 28)
-#define AT91_PIN_PC29   (PIN_BASE + 0x40 + 29)
-#define AT91_PIN_PC30   (PIN_BASE + 0x40 + 30)
-#define AT91_PIN_PC31   (PIN_BASE + 0x40 + 31)
-
-#define AT91_PIN_PD0    (PIN_BASE + 0x60 + 0)
-#define AT91_PIN_PD1    (PIN_BASE + 0x60 + 1)
-#define AT91_PIN_PD2    (PIN_BASE + 0x60 + 2)
-#define AT91_PIN_PD3    (PIN_BASE + 0x60 + 3)
-#define AT91_PIN_PD4    (PIN_BASE + 0x60 + 4)
-#define AT91_PIN_PD5    (PIN_BASE + 0x60 + 5)
-#define AT91_PIN_PD6    (PIN_BASE + 0x60 + 6)
-#define AT91_PIN_PD7    (PIN_BASE + 0x60 + 7)
-#define AT91_PIN_PD8    (PIN_BASE + 0x60 + 8)
-#define AT91_PIN_PD9    (PIN_BASE + 0x60 + 9)
-#define AT91_PIN_PD10   (PIN_BASE + 0x60 + 10)
-#define AT91_PIN_PD11   (PIN_BASE + 0x60 + 11)
-#define AT91_PIN_PD12   (PIN_BASE + 0x60 + 12)
-#define AT91_PIN_PD13   (PIN_BASE + 0x60 + 13)
-#define AT91_PIN_PD14   (PIN_BASE + 0x60 + 14)
-#define AT91_PIN_PD15   (PIN_BASE + 0x60 + 15)
-#define AT91_PIN_PD16   (PIN_BASE + 0x60 + 16)
-#define AT91_PIN_PD17   (PIN_BASE + 0x60 + 17)
-#define AT91_PIN_PD18   (PIN_BASE + 0x60 + 18)
-#define AT91_PIN_PD19   (PIN_BASE + 0x60 + 19)
-#define AT91_PIN_PD20   (PIN_BASE + 0x60 + 20)
-#define AT91_PIN_PD21   (PIN_BASE + 0x60 + 21)
-#define AT91_PIN_PD22   (PIN_BASE + 0x60 + 22)
-#define AT91_PIN_PD23   (PIN_BASE + 0x60 + 23)
-#define AT91_PIN_PD24   (PIN_BASE + 0x60 + 24)
-#define AT91_PIN_PD25   (PIN_BASE + 0x60 + 25)
-#define AT91_PIN_PD26   (PIN_BASE + 0x60 + 26)
-#define AT91_PIN_PD27   (PIN_BASE + 0x60 + 27)
-#define AT91_PIN_PD28   (PIN_BASE + 0x60 + 28)
-#define AT91_PIN_PD29   (PIN_BASE + 0x60 + 29)
-#define AT91_PIN_PD30   (PIN_BASE + 0x60 + 30)
-#define AT91_PIN_PD31   (PIN_BASE + 0x60 + 31)
-
-#define AT91_PIN_PE0    (PIN_BASE + 0x80 + 0)
-#define AT91_PIN_PE1    (PIN_BASE + 0x80 + 1)
-#define AT91_PIN_PE2    (PIN_BASE + 0x80 + 2)
-#define AT91_PIN_PE3    (PIN_BASE + 0x80 + 3)
-#define AT91_PIN_PE4    (PIN_BASE + 0x80 + 4)
-#define AT91_PIN_PE5    (PIN_BASE + 0x80 + 5)
-#define AT91_PIN_PE6    (PIN_BASE + 0x80 + 6)
-#define AT91_PIN_PE7    (PIN_BASE + 0x80 + 7)
-#define AT91_PIN_PE8    (PIN_BASE + 0x80 + 8)
-#define AT91_PIN_PE9    (PIN_BASE + 0x80 + 9)
-#define AT91_PIN_PE10   (PIN_BASE + 0x80 + 10)
-#define AT91_PIN_PE11   (PIN_BASE + 0x80 + 11)
-#define AT91_PIN_PE12   (PIN_BASE + 0x80 + 12)
-#define AT91_PIN_PE13   (PIN_BASE + 0x80 + 13)
-#define AT91_PIN_PE14   (PIN_BASE + 0x80 + 14)
-#define AT91_PIN_PE15   (PIN_BASE + 0x80 + 15)
-#define AT91_PIN_PE16   (PIN_BASE + 0x80 + 16)
-#define AT91_PIN_PE17   (PIN_BASE + 0x80 + 17)
-#define AT91_PIN_PE18   (PIN_BASE + 0x80 + 18)
-#define AT91_PIN_PE19   (PIN_BASE + 0x80 + 19)
-#define AT91_PIN_PE20   (PIN_BASE + 0x80 + 20)
-#define AT91_PIN_PE21   (PIN_BASE + 0x80 + 21)
-#define AT91_PIN_PE22   (PIN_BASE + 0x80 + 22)
-#define AT91_PIN_PE23   (PIN_BASE + 0x80 + 23)
-#define AT91_PIN_PE24   (PIN_BASE + 0x80 + 24)
-#define AT91_PIN_PE25   (PIN_BASE + 0x80 + 25)
-#define AT91_PIN_PE26   (PIN_BASE + 0x80 + 26)
-#define AT91_PIN_PE27   (PIN_BASE + 0x80 + 27)
-#define AT91_PIN_PE28   (PIN_BASE + 0x80 + 28)
-#define AT91_PIN_PE29   (PIN_BASE + 0x80 + 29)
-#define AT91_PIN_PE30   (PIN_BASE + 0x80 + 30)
-#define AT91_PIN_PE31   (PIN_BASE + 0x80 + 31)
-
-#ifndef __ASSEMBLY__
-/* setup setup routines, called from board init or driver probe() */
-extern int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup);
-extern int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup);
-extern int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup);
-extern int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup);
-extern int __init_or_module at91_set_gpio_output(unsigned pin, int value);
-extern int __init_or_module at91_set_deglitch(unsigned pin, int is_on);
-extern int __init_or_module at91_set_multi_drive(unsigned pin, int is_on);
-
-/* callable at any time */
-extern int at91_set_gpio_value(unsigned pin, int value);
-extern int at91_get_gpio_value(unsigned pin);
-
-/* callable only from core power-management code */
-extern void at91_gpio_suspend(void);
-extern void at91_gpio_resume(void);
-
-/*-------------------------------------------------------------------------*/
-
-/* wrappers for "new style" GPIO calls. the old AT91-specfic ones should
- * eventually be removed (along with this errno.h inclusion), and the
- * gpio request/free calls should probably be implemented.
- */
-
-#include <asm/errno.h>
-
-static inline int gpio_request(unsigned gpio, const char *label)
-{
-        return 0;
-}
-
-static inline void gpio_free(unsigned gpio)
-{
-}
-
-extern int gpio_direction_input(unsigned gpio);
-extern int gpio_direction_output(unsigned gpio, int value);
-
-static inline int gpio_get_value(unsigned gpio)
-{
-        return at91_get_gpio_value(gpio);
-}
-
-static inline void gpio_set_value(unsigned gpio, int value)
-{
-        at91_set_gpio_value(gpio, value);
-}
-
-#include <asm-generic/gpio.h>           /* cansleep wrappers */
-
-static inline int gpio_to_irq(unsigned gpio)
-{
-        return gpio;
-}
-
-static inline int irq_to_gpio(unsigned irq)
-{
-        return irq;
-}
-
-#endif  /* __ASSEMBLY__ */
-
-#endif
diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h
deleted file mode 100644
index 016a3a3f6633..000000000000
--- a/include/asm-arm/arch-at91/hardware.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * include/asm-arm/arch-at91/hardware.h
- *
- *  Copyright (C) 2003 SAN People
- *  Copyright (C) 2003 ATMEL
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <asm/sizes.h>
-
-#if defined(CONFIG_ARCH_AT91RM9200)
-#include <asm/arch/at91rm9200.h>
-#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)
-#include <asm/arch/at91sam9260.h>
-#elif defined(CONFIG_ARCH_AT91SAM9261)
-#include <asm/arch/at91sam9261.h>
-#elif defined(CONFIG_ARCH_AT91SAM9263)
-#include <asm/arch/at91sam9263.h>
-#elif defined(CONFIG_ARCH_AT91SAM9RL)
-#include <asm/arch/at91sam9rl.h>
-#elif defined(CONFIG_ARCH_AT91CAP9)
-#include <asm/arch/at91cap9.h>
-#elif defined(CONFIG_ARCH_AT91X40)
-#include <asm/arch/at91x40.h>
-#else
-#error "Unsupported AT91 processor"
-#endif
-
-
-#ifdef CONFIG_MMU
-/*
- * Remap the peripherals from address 0xFFF78000 .. 0xFFFFFFFF
- * to 0xFEF78000 .. 0xFF000000.  (544Kb)
- */
-#define AT91_IO_PHYS_BASE       0xFFF78000
-#define AT91_IO_VIRT_BASE       (0xFF000000 - AT91_IO_SIZE)
-#else
-/*
- * Identity mapping for the non MMU case.
- */
-#define AT91_IO_PHYS_BASE       AT91_BASE_SYS
-#define AT91_IO_VIRT_BASE       AT91_IO_PHYS_BASE
-#endif
-
-#define AT91_IO_SIZE            (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1)
-
- /* Convert a physical IO address to virtual IO address */
-#define AT91_IO_P2V(x)          ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE)
-
-/*
- * Virtual to Physical Address mapping for IO devices.
- */
-#define AT91_VA_BASE_SYS        AT91_IO_P2V(AT91_BASE_SYS)
-#define AT91_VA_BASE_EMAC       AT91_IO_P2V(AT91RM9200_BASE_EMAC)
-
- /* Internal SRAM is mapped below the IO devices */
-#define AT91_SRAM_MAX           SZ_1M
-#define AT91_VIRT_BASE          (AT91_IO_VIRT_BASE - AT91_SRAM_MAX)
-
-/* Serial ports */
-#define ATMEL_MAX_UART          7               /* 6 USART3's and one DBGU port (SAM9260) */
-
-/* External Memory Map */
-#define AT91_CHIPSELECT_0       0x10000000
-#define AT91_CHIPSELECT_1       0x20000000
-#define AT91_CHIPSELECT_2       0x30000000
-#define AT91_CHIPSELECT_3       0x40000000
-#define AT91_CHIPSELECT_4       0x50000000
-#define AT91_CHIPSELECT_5       0x60000000
-#define AT91_CHIPSELECT_6       0x70000000
-#define AT91_CHIPSELECT_7       0x80000000
-
-/* SDRAM */
-#ifdef CONFIG_DRAM_BASE
-#define AT91_SDRAM_BASE         CONFIG_DRAM_BASE
-#else
-#define AT91_SDRAM_BASE         AT91_CHIPSELECT_1
-#endif
-
-/* Clocks */
-#define AT91_SLOW_CLOCK         32768           /* slow clock */
-
-
-#endif
diff --git a/include/asm-arm/arch-at91/io.h b/include/asm-arm/arch-at91/io.h
deleted file mode 100644
index f8beaa228467..000000000000
--- a/include/asm-arm/arch-at91/io.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * include/asm-arm/arch-at91/io.h
- *
- *  Copyright (C) 2003 SAN People
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT          0xFFFFFFFF
-
-#define __io(a)                 ((void __iomem *)(a))
-#define __mem_pci(a)            (a)
-
-
-#ifndef __ASSEMBLY__
-
-static inline unsigned int at91_sys_read(unsigned int reg_offset)
-{
-        void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
-
-        return __raw_readl(addr + reg_offset);
-}
-
-static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
-{
-        void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
-
-        __raw_writel(value, addr + reg_offset);
-}
-
-#endif
-
-#endif
diff --git a/include/asm-arm/arch-at91/irqs.h b/include/asm-arm/arch-at91/irqs.h
deleted file mode 100644
index 70b1216dce5d..000000000000
--- a/include/asm-arm/arch-at91/irqs.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * include/asm-arm/arch-at91/irqs.h
- *
- *  Copyright (C) 2004 SAN People
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H
-
-#include <asm/io.h>
-#include <asm/arch/at91_aic.h>
-
-#define NR_AIC_IRQS 32
-
-
-/*
- * Acknowledge interrupt with AIC after interrupt has been handled.
- *   (by kernel/irq.c)
- */
-#define irq_finish(irq) do { at91_sys_write(AT91_AIC_EOICR, 0); } while (0)
-
-
-/*
- * IRQ interrupt symbols are the AT91xxx_ID_* symbols
- * for IRQs handled directly through the AIC, or else the AT91_PIN_*
- * symbols in gpio.h for ones handled indirectly as GPIOs.
- * We make provision for 5 banks of GPIO.
- */
-#define NR_IRQS         (NR_AIC_IRQS + (5 * 32))
-
-/* FIQ is AIC source 0. */
-#define FIQ_START AT91_ID_FIQ
-
-#endif
diff --git a/include/asm-arm/arch-at91/memory.h b/include/asm-arm/arch-at91/memory.h
deleted file mode 100644
index 904fbd60f0e4..000000000000
--- a/include/asm-arm/arch-at91/memory.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * include/asm-arm/arch-at91/memory.h
- *
- *  Copyright (C) 2004 SAN People
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-#include <asm/arch/hardware.h>
-
-#define PHYS_OFFSET     (AT91_SDRAM_BASE)
-
-
-/*
- * Virtual view <-> DMA view memory address translations
- * virt_to_bus: Used to translate the virtual address to an
- *              address suitable to be passed to set_dma_addr
- * bus_to_virt: Used to convert an address for DMA operations
- *              to an address that the kernel can use.
- */
-#define __virt_to_bus(x) __virt_to_phys(x)
-#define __bus_to_virt(x) __phys_to_virt(x)
-
-#endif
diff --git a/include/asm-arm/arch-at91/system.h b/include/asm-arm/arch-at91/system.h
deleted file mode 100644
index c5e3d0357263..000000000000
--- a/include/asm-arm/arch-at91/system.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * include/asm-arm/arch-at91/system.h
- *
- *  Copyright (C) 2003 SAN People
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_st.h>
-#include <asm/arch/at91_dbgu.h>
-
-static inline void arch_idle(void)
-{
-        /*
-         * Disable the processor clock.  The processor will be automatically
-         * re-enabled by an interrupt or by a reset.
-         */
-//      at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
-
-        /*
-         * Set the processor (CP15) into 'Wait for Interrupt' mode.
-         * Unlike disabling the processor clock via the PMC (above)
-         *  this allows the processor to be woken via JTAG.
-         */
-        cpu_do_idle();
-}
-
-void (*at91_arch_reset)(void);
-
-static inline void arch_reset(char mode)
-{
-        /* call the CPU-specific reset function */
-        if (at91_arch_reset)
-                (at91_arch_reset)();
-}
-
-#endif
diff --git a/include/asm-arm/arch-at91/timex.h b/include/asm-arm/arch-at91/timex.h
deleted file mode 100644
index 67c86a89828f..000000000000
--- a/include/asm-arm/arch-at91/timex.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * include/asm-arm/arch-at91/timex.h
- *
- *  Copyright (C) 2003 SAN People
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __ASM_ARCH_TIMEX_H
-#define __ASM_ARCH_TIMEX_H
-
-#include <asm/arch/hardware.h>
-
-#if defined(CONFIG_ARCH_AT91RM9200)
-
-#define CLOCK_TICK_RATE         (AT91_SLOW_CLOCK)
-
-#elif defined(CONFIG_ARCH_AT91SAM9260)
-
-#if defined(CONFIG_MACH_USB_A9260) || defined(CONFIG_MACH_QIL_A9260)
-#define AT91SAM9_MASTER_CLOCK   90000000
-#else
-#define AT91SAM9_MASTER_CLOCK   99300000
-#endif
-
-#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
-
-#elif defined(CONFIG_ARCH_AT91SAM9261)
-
-#define AT91SAM9_MASTER_CLOCK   99300000
-#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
-
-#elif defined(CONFIG_ARCH_AT91SAM9263)
-
-#if defined(CONFIG_MACH_USB_A9263)
-#define AT91SAM9_MASTER_CLOCK   90000000
-#else
-#define AT91SAM9_MASTER_CLOCK   99959500
-#endif
-
-#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
-
-#elif defined(CONFIG_ARCH_AT91SAM9RL)
-
-#define AT91SAM9_MASTER_CLOCK   100000000
-#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
-
-#elif defined(CONFIG_ARCH_AT91SAM9G20)
-
-#define AT91SAM9_MASTER_CLOCK   132096000
-#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
-
-#elif defined(CONFIG_ARCH_AT91CAP9)
-
-#define AT91CAP9_MASTER_CLOCK   100000000
-#define CLOCK_TICK_RATE         (AT91CAP9_MASTER_CLOCK/16)
-
-#elif defined(CONFIG_ARCH_AT91X40)
-
-#define AT91X40_MASTER_CLOCK    40000000
-#define CLOCK_TICK_RATE         (AT91X40_MASTER_CLOCK)
-
-#endif
-
-#endif
diff --git a/include/asm-arm/arch-at91/uncompress.h b/include/asm-arm/arch-at91/uncompress.h
deleted file mode 100644
index f5636a8f6132..000000000000
--- a/include/asm-arm/arch-at91/uncompress.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * include/asm-arm/arch-at91/uncompress.h
- *
- *  Copyright (C) 2003 SAN People
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-
-#include <asm/io.h>
-#include <linux/atmel_serial.h>
-
-#if defined(CONFIG_AT91_EARLY_DBGU)
-#define UART_OFFSET (AT91_DBGU + AT91_BASE_SYS)
-#elif defined(CONFIG_AT91_EARLY_USART0)
-#define UART_OFFSET AT91_USART0
-#elif defined(CONFIG_AT91_EARLY_USART1)
-#define UART_OFFSET AT91_USART1
-#elif defined(CONFIG_AT91_EARLY_USART2)
-#define UART_OFFSET AT91_USART2
-#elif defined(CONFIG_AT91_EARLY_USART3)
-#define UART_OFFSET AT91_USART3
-#elif defined(CONFIG_AT91_EARLY_USART4)
-#define UART_OFFSET AT91_USART4
-#elif defined(CONFIG_AT91_EARLY_USART5)
-#define UART_OFFSET AT91_USART5
-#endif
-
-/*
- * The following code assumes the serial port has already been
- * initialized by the bootloader.  If you didn't setup a port in
- * your bootloader then nothing will appear (which might be desired).
- *
- * This does not append a newline
- */
-static void putc(int c)
-{
-#ifdef UART_OFFSET
-        void __iomem *sys = (void __iomem *) UART_OFFSET;       /* physical address */
-
-        while (!(__raw_readl(sys + ATMEL_US_CSR) & ATMEL_US_TXRDY))
-                barrier();
-        __raw_writel(c, sys + ATMEL_US_THR);
-#endif
-}
-
-static inline void flush(void)
-{
-#ifdef UART_OFFSET
-        void __iomem *sys = (void __iomem *) UART_OFFSET;       /* physical address */
-
-        /* wait for transmission to complete */
-        while (!(__raw_readl(sys + ATMEL_US_CSR) & ATMEL_US_TXEMPTY))
-                barrier();
-#endif
-}
-
-#define arch_decomp_setup()
-
-#define arch_decomp_wdog()
-
-#endif
diff --git a/include/asm-arm/arch-at91/vmalloc.h b/include/asm-arm/arch-at91/vmalloc.h
deleted file mode 100644
index bb05e70e932a..000000000000
--- a/include/asm-arm/arch-at91/vmalloc.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * include/asm-arm/arch-at91/vmalloc.h
- *
- *  Copyright (C) 2003 SAN People
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H
-
-#define VMALLOC_END             (AT91_VIRT_BASE & PGDIR_MASK)
-
-#endif
diff --git a/include/asm-arm/arch-cl7500/debug-macro.S b/include/asm-arm/arch-cl7500/debug-macro.S
deleted file mode 100644
index 9a2b67d24098..000000000000
--- a/include/asm-arm/arch-cl7500/debug-macro.S
+++ /dev/null
@@ -1,21 +0,0 @@
-/* linux/include/asm-arm/arch-cl7500/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-                .macro  addruart,rx
-                mov     \rx, #0xe0000000
-                orr     \rx, \rx, #0x00010000
-                orr     \rx, \rx, #0x00000be0
-                .endm
-
-#define UART_SHIFT      2
-#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-cl7500/dma.h b/include/asm-arm/arch-cl7500/dma.h
deleted file mode 100644
index 591ed2551892..000000000000
--- a/include/asm-arm/arch-cl7500/dma.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * linux/include/asm-arm/arch-cl7500/dma.h
- *
- * Copyright (C) 1999 Nexus Electronics Ltd.
- */
-
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-
-/* DMA is not yet implemented! It should be the same as acorn, copy over.. */
-
-/*
- * This is the maximum DMA address that can be DMAd to.
- * There should not be more than (0xd0000000 - 0xc0000000)
- * bytes of RAM.
- */
-#define MAX_DMA_ADDRESS         0xd0000000
-
-#define DMA_S0                  0
-
-#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-cl7500/entry-macro.S b/include/asm-arm/arch-cl7500/entry-macro.S
deleted file mode 100644
index 5bd55557ccca..000000000000
--- a/include/asm-arm/arch-cl7500/entry-macro.S
+++ /dev/null
@@ -1,16 +0,0 @@
-#include <asm/arch/hardware.h>
-#include <asm/hardware/entry-macro-iomd.S>
-
-        .equ    ioc_base_high, IOC_BASE & 0xff000000
-        .equ    ioc_base_low, IOC_BASE & 0x00ff0000
-
-        .macro  get_irqnr_preamble, base, tmp
-        mov     \base, #ioc_base_high           @ point at IOC
-        .if     ioc_base_low
-        orr     \base, \base, #ioc_base_low
-        .endif
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
diff --git a/include/asm-arm/arch-cl7500/hardware.h b/include/asm-arm/arch-cl7500/hardware.h
deleted file mode 100644
index 1adfd18e6154..000000000000
--- a/include/asm-arm/arch-cl7500/hardware.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * linux/include/asm-arm/arch-cl7500/hardware.h
- *
- * Copyright (C) 1996-1999 Russell King.
- * Copyright (C) 1999 Nexus Electronics Ltd.
- *
- * This file contains the hardware definitions of the 
- * CL7500 evaluation board.
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <asm/arch/memory.h>
-#include <asm/hardware/iomd.h>
-
-#ifdef __ASSEMBLY__
-#define IOMEM(x) x
-#else
-#define IOMEM(x) ((void __iomem *)(x))
-#endif
-
-/*
- * What hardware must be present
- */
-#define HAS_IOMD
-#define HAS_VIDC20
-
-/* Hardware addresses of major areas.
- *  *_START is the physical address
- *  *_SIZE  is the size of the region
- *  *_BASE  is the virtual address
- */
-
-#define IO_START                0x03000000      /* I/O */
-#define IO_SIZE                 0x01000000
-#define IO_BASE                 IOMEM(0xe0000000)
-
-#define ISA_START               0x0c000000      /* ISA */
-#define ISA_SIZE                0x00010000
-#define ISA_BASE                0xe1000000
-
-#define FLASH_START             0x01000000      /* XXX */
-#define FLASH_SIZE              0x01000000
-#define FLASH_BASE              0xe2000000
-
-#define LED_START               0x0302B000
-#define LED_SIZE                0x00001000
-#define LED_BASE                0xe3000000
-#define LED_ADDRESS             (LED_BASE + 0xa00)
-
-/* Let's define SCREEN_START for CL7500, even though it's a lie. */
-#define SCREEN_START            0x02000000      /* VRAM */
-#define SCREEN_END              0xdfc00000
-#define SCREEN_BASE             0xdf800000
-
-#define VIDC_BASE               (void __iomem *)0xe0400000
-#define IOMD_BASE               IOMEM(0xe0200000)
-#define IOC_BASE                IOMEM(0xe0200000)
-#define FLOPPYDMA_BASE          IOMEM(0xe002a000)
-#define PCIO_BASE               IOMEM(0xe0010000)
-
-#define vidc_writel(val)        __raw_writel(val, VIDC_BASE)
-
-/* in/out bias for the ISA slot region */
-#define ISASLOT_IO              0x80400000
-
-#endif
diff --git a/include/asm-arm/arch-cl7500/io.h b/include/asm-arm/arch-cl7500/io.h
deleted file mode 100644
index 80f9b19cac9e..000000000000
--- a/include/asm-arm/arch-cl7500/io.h
+++ /dev/null
@@ -1,255 +0,0 @@
-/*
- * linux/include/asm-arm/arch-cl7500/io.h
- *  from linux/include/asm-arm/arch-rpc/io.h
- *
- * Copyright (C) 1997 Russell King
- *
- * Modifications:
- *  06-Dec-1997 RMK     Created.
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#include <asm/arch/hardware.h>
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/*
- * GCC is totally crap at loading/storing data.  We try to persuade it
- * to do the right thing by using these whereever possible instead of
- * the above.
- */
-#define __arch_base_getb(b,o)                   \
- ({                                             \
-        unsigned int v, r = (b);                \
-        __asm__ __volatile__(                   \
-                "ldrb   %0, [%1, %2]"           \
-                : "=r" (v)                      \
-                : "r" (r), "Ir" (o));           \
-        v;                                      \
- })
-
-#define __arch_base_getl(b,o)                   \
- ({                                             \
-        unsigned int v, r = (b);                \
-        __asm__ __volatile__(                   \
-                "ldr    %0, [%1, %2]"           \
-                : "=r" (v)                      \
-                : "r" (r), "Ir" (o));           \
-        v;                                      \
- })
-
-#define __arch_base_putb(v,b,o)                 \
- ({                                             \
-        unsigned int r = (b);                   \
-        __asm__ __volatile__(                   \
-                "strb   %0, [%1, %2]"           \
-                :                               \
-                : "r" (v), "r" (r), "Ir" (o));  \
- })
-
-#define __arch_base_putl(v,b,o)                 \
- ({                                             \
-        unsigned int r = (b);                   \
-        __asm__ __volatile__(                   \
-                "str    %0, [%1, %2]"           \
-                :                               \
-                : "r" (v), "r" (r), "Ir" (o));  \
- })
-
-/*
- * We use two different types of addressing - PC style addresses, and ARM
- * addresses.  PC style accesses the PC hardware with the normal PC IO
- * addresses, eg 0x3f8 for serial#1.  ARM addresses are 0x80000000+
- * and are translated to the start of IO.  Note that all addresses are
- * shifted left!
- */
-#define __PORT_PCIO(x)  (!((x) & 0x80000000))
-
-/*
- * Dynamic IO functions - let the compiler
- * optimize the expressions
- */
-static inline void __outb (unsigned int value, unsigned int port)
-{
-        unsigned long temp;
-        __asm__ __volatile__(
-        "tst    %2, #0x80000000\n\t"
-        "mov    %0, %4\n\t"
-        "addeq  %0, %0, %3\n\t"
-        "strb   %1, [%0, %2, lsl #2]    @ outb"
-        : "=&r" (temp)
-        : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
-        : "cc");
-}
-
-static inline void __outw (unsigned int value, unsigned int port)
-{
-        unsigned long temp;
-        __asm__ __volatile__(
-        "tst    %2, #0x80000000\n\t"
-        "mov    %0, %4\n\t"
-        "addeq  %0, %0, %3\n\t"
-        "str    %1, [%0, %2, lsl #2]    @ outw"
-        : "=&r" (temp)
-        : "r" (value|value<<16), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
-        : "cc");
-}
-
-static inline void __outl (unsigned int value, unsigned int port)
-{
-        unsigned long temp;
-        __asm__ __volatile__(
-        "tst    %2, #0x80000000\n\t"
-        "mov    %0, %4\n\t"
-        "addeq  %0, %0, %3\n\t"
-        "str    %1, [%0, %2, lsl #2]    @ outl"
-        : "=&r" (temp)
-        : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
-        : "cc");
-}
-
-#define DECLARE_DYN_IN(sz,fnsuffix,instr)                                       \
-static inline unsigned sz __in##fnsuffix (unsigned int port)            \
-{                                                                               \
-        unsigned long temp, value;                                              \
-        __asm__ __volatile__(                                                   \
-        "tst    %2, #0x80000000\n\t"                                            \
-        "mov    %0, %4\n\t"                                                     \
-        "addeq  %0, %0, %3\n\t"                                                 \
-        "ldr" instr "   %1, [%0, %2, lsl #2]    @ in" #fnsuffix                 \
-        : "=&r" (temp), "=r" (value)                                            \
-        : "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)                \
-        : "cc");                                                                \
-        return (unsigned sz)value;                                              \
-}
-
-static inline unsigned int __ioaddr (unsigned int port)                 \
-{                                                                               \
-        if (__PORT_PCIO(port))                                                  \
-                return (unsigned int)(PCIO_BASE + (port << 2));                 \
-        else                                                                    \
-                return (unsigned int)(IO_BASE + (port << 2));                   \
-}
-
-#define DECLARE_IO(sz,fnsuffix,instr)   \
-        DECLARE_DYN_IN(sz,fnsuffix,instr)
-
-DECLARE_IO(char,b,"b")
-DECLARE_IO(short,w,"")
-DECLARE_IO(int,l,"")
-
-#undef DECLARE_IO
-#undef DECLARE_DYN_IN
-
-/*
- * Constant address IO functions
- *
- * These have to be macros for the 'J' constraint to work -
- * +/-4096 immediate operand.
- */
-#define __outbc(value,port)                                                     \
-({                                                                              \
-        if (__PORT_PCIO((port)))                                                \
-                __asm__ __volatile__(                                           \
-                "strb   %0, [%1, %2]    @ outbc"                                \
-                : : "r" (value), "r" (PCIO_BASE), "Jr" ((port) << 2));          \
-        else                                                                    \
-                __asm__ __volatile__(                                           \
-                "strb   %0, [%1, %2]    @ outbc"                                \
-                : : "r" (value), "r" (IO_BASE), "r" ((port) << 2));             \
-})
-
-#define __inbc(port)                                                            \
-({                                                                              \
-        unsigned char result;                                                   \
-        if (__PORT_PCIO((port)))                                                \
-                __asm__ __volatile__(                                           \
-                "ldrb   %0, [%1, %2]    @ inbc"                                 \
-                : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2));         \
-        else                                                                    \
-                __asm__ __volatile__(                                           \
-                "ldrb   %0, [%1, %2]    @ inbc"                                 \
-                : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2));            \
-        result;                                                                 \
-})
-
-#define __outwc(value,port)                                                     \
-({                                                                              \
-        unsigned long v = value;                                                \
-        if (__PORT_PCIO((port)))                                                \
-                __asm__ __volatile__(                                           \
-                "str    %0, [%1, %2]    @ outwc"                                \
-                : : "r" (v|v<<16), "r" (PCIO_BASE), "Jr" ((port) << 2));        \
-        else                                                                    \
-                __asm__ __volatile__(                                           \
-                "str    %0, [%1, %2]    @ outwc"                                \
-                : : "r" (v|v<<16), "r" (IO_BASE), "r" ((port) << 2));           \
-})
-
-#define __inwc(port)                                                            \
-({                                                                              \
-        unsigned short result;                                                  \
-        if (__PORT_PCIO((port)))                                                \
-                __asm__ __volatile__(                                           \
-                "ldr    %0, [%1, %2]    @ inwc"                                 \
-                : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2));         \
-        else                                                                    \
-                __asm__ __volatile__(                                           \
-                "ldr    %0, [%1, %2]    @ inwc"                                 \
-                : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2));            \
-        result & 0xffff;                                                        \
-})
-
-#define __outlc(value,port)                                                     \
-({                                                                              \
-        unsigned long v = value;                                                \
-        if (__PORT_PCIO((port)))                                                \
-                __asm__ __volatile__(                                           \
-                "str    %0, [%1, %2]    @ outlc"                                \
-                : : "r" (v), "r" (PCIO_BASE), "Jr" ((port) << 2));              \
-        else                                                                    \
-                __asm__ __volatile__(                                           \
-                "str    %0, [%1, %2]    @ outlc"                                \
-                : : "r" (v), "r" (IO_BASE), "r" ((port) << 2));                 \
-})
-
-#define __inlc(port)                                                            \
-({                                                                              \
-        unsigned long result;                                                   \
-        if (__PORT_PCIO((port)))                                                \
-                __asm__ __volatile__(                                           \
-                "ldr    %0, [%1, %2]    @ inlc"                                 \
-                : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2));         \
-        else                                                                    \
-                __asm__ __volatile__(                                           \
-                "ldr    %0, [%1, %2]    @ inlc"                                 \
-                : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2));            \
-        result;                                                                 \
-})
-
-#define __ioaddrc(port)                                                         \
-        (__PORT_PCIO((port)) ? PCIO_BASE + ((port) << 2) : IO_BASE + ((port) << 2))
-
-#define inb(p)          (__builtin_constant_p((p)) ? __inbc(p)    : __inb(p))
-#define inw(p)          (__builtin_constant_p((p)) ? __inwc(p)    : __inw(p))
-#define inl(p)          (__builtin_constant_p((p)) ? __inlc(p)    : __inl(p))
-#define outb(v,p)       (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p))
-#define outw(v,p)       (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p))
-#define outl(v,p)       (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p))
-#define __ioaddr(p)     (__builtin_constant_p((p)) ? __ioaddr(p)  : __ioaddrc(p))
-/* the following macro is deprecated */
-#define ioaddr(port)                    __ioaddr((port))
-
-#define insb(p,d,l)     __raw_readsb(__ioaddr(p),d,l)
-#define insw(p,d,l)     __raw_readsw(__ioaddr(p),d,l)
-
-#define outsb(p,d,l)    __raw_writesb(__ioaddr(p),d,l)
-#define outsw(p,d,l)    __raw_writesw(__ioaddr(p),d,l)
-
-/*
- * 1:1 mapping for ioremapped regions.
- */
-#define __mem_pci(x)    (x)
-
-#endif
diff --git a/include/asm-arm/arch-cl7500/irq.h b/include/asm-arm/arch-cl7500/irq.h
deleted file mode 100644
index 4b286331f3f8..000000000000
--- a/include/asm-arm/arch-cl7500/irq.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * include/asm-arm/arch-cl7500/irq.h
- *
- * Copyright (C) 1996 Russell King
- * Copyright (C) 1999, 2001 Nexus Electronics Ltd.
- *
- * Changelog:
- *   10-10-1996 RMK     Brought up to date with arch-sa110eval
- *   22-08-1998 RMK     Restructured IRQ routines
- *   11-08-1999 PJB     Created ARM7500 version, derived from RiscPC code
- */
-
-#include <asm/hardware/iomd.h>
-#include <asm/io.h>
-
-static inline int fixup_irq(unsigned int irq)
-{
-        if (irq == IRQ_ISA) {
-                int isabits = *((volatile unsigned int *)0xe002b700);
-                if (isabits == 0) {
-                        printk("Spurious ISA IRQ!\n");
-                        return irq;
-                }
-                irq = IRQ_ISA_BASE;
-                while (!(isabits & 1)) {
-                        irq++;
-                        isabits >>= 1;
-                }
-        }
-
-        return irq;
-}
diff --git a/include/asm-arm/arch-cl7500/irqs.h b/include/asm-arm/arch-cl7500/irqs.h
deleted file mode 100644
index f20996eadf19..000000000000
--- a/include/asm-arm/arch-cl7500/irqs.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * linux/include/asm-arm/arch-cl7500/irqs.h
- *
- * Copyright (C) 1999 Nexus Electronics Ltd
- */
-
-#define IRQ_INT2                0
-#define IRQ_INT1                2
-#define IRQ_VSYNCPULSE          3
-#define IRQ_POWERON             4
-#define IRQ_TIMER0              5
-#define IRQ_TIMER1              6
-#define IRQ_FORCE               7
-#define IRQ_INT8                8
-#define IRQ_ISA                 9
-#define IRQ_INT6                10
-#define IRQ_INT5                11
-#define IRQ_INT4                12
-#define IRQ_INT3                13
-#define IRQ_KEYBOARDTX          14
-#define IRQ_KEYBOARDRX          15
-
-#define IRQ_DMA0                16
-#define IRQ_DMA1                17
-#define IRQ_DMA2                18
-#define IRQ_DMA3                19
-#define IRQ_DMAS0               20
-#define IRQ_DMAS1               21
-
-#define IRQ_IOP0                24
-#define IRQ_IOP1                25
-#define IRQ_IOP2                26
-#define IRQ_IOP3                27
-#define IRQ_IOP4                28
-#define IRQ_IOP5                29
-#define IRQ_IOP6                30
-#define IRQ_IOP7                31
-
-#define IRQ_MOUSERX             40
-#define IRQ_MOUSETX             41
-#define IRQ_ADC                 42
-#define IRQ_EVENT1              43
-#define IRQ_EVENT2              44
-
-#define IRQ_ISA_BASE            48
-#define IRQ_ISA_3               48
-#define IRQ_ISA_4               49
-#define IRQ_ISA_5               50
-#define IRQ_ISA_7               51
-#define IRQ_ISA_9               52
-#define IRQ_ISA_10              53
-#define IRQ_ISA_11              54
-#define IRQ_ISA_14              55      
-
-#define FIQ_INT9                0
-#define FIQ_INT5                1
-#define FIQ_INT6                4
-#define FIQ_INT8                6
-#define FIQ_FORCE               7
-
-/*
- * This is the offset of the FIQ "IRQ" numbers
- */
-#define FIQ_START               64
-
-#define IRQ_TIMER               IRQ_TIMER0
diff --git a/include/asm-arm/arch-cl7500/memory.h b/include/asm-arm/arch-cl7500/memory.h
deleted file mode 100644
index 3178140e24ca..000000000000
--- a/include/asm-arm/arch-cl7500/memory.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * linux/include/asm-arm/arch-cl7500/memory.h
- *
- * Copyright (c) 1996,1997,1998 Russell King.
- *
- * Changelog:
- *  20-Oct-1996 RMK     Created
- *  31-Dec-1997 RMK     Fixed definitions to reduce warnings
- *  11-Jan-1998 RMK     Uninlined to reduce hits on cache
- *  08-Feb-1998 RMK     Added __virt_to_bus and __bus_to_virt
- *  21-Mar-1999 RMK     Renamed to memory.h
- *              RMK     Added TASK_SIZE and PAGE_OFFSET
- */
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-/*
- * Physical DRAM offset.
- */
-#define PHYS_OFFSET     UL(0x10000000)
-
-/*
- * These are exactly the same on the RiscPC as the
- * physical memory view.
- */
-#define __virt_to_bus(x) __virt_to_phys(x)
-#define __bus_to_virt(x) __phys_to_virt(x)
-
-/*
- * Cache flushing area - ROM
- */
-#define FLUSH_BASE_PHYS         0x00000000
-#define FLUSH_BASE              0xdf000000
-
-#endif
diff --git a/include/asm-arm/arch-cl7500/system.h b/include/asm-arm/arch-cl7500/system.h
deleted file mode 100644
index a9505d6a74d7..000000000000
--- a/include/asm-arm/arch-cl7500/system.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * linux/include/asm-arm/arch-cl7500/system.h
- *
- * Copyright (c) 1999 Nexus Electronics Ltd.
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-#include <asm/hardware/iomd.h>
-#include <asm/io.h>
-
-static inline void arch_idle(void)
-{
-        iomd_writeb(0, IOMD_SUSMODE);
-}
-
-#define arch_reset(mode)                        \
-        do {                                    \
-                iomd_writeb(0, IOMD_ROMCR0);    \
-                cpu_reset(0);                   \
-        } while (0)
-
-#endif
diff --git a/include/asm-arm/arch-cl7500/timex.h b/include/asm-arm/arch-cl7500/timex.h
deleted file mode 100644
index 8a4175fc0106..000000000000
--- a/include/asm-arm/arch-cl7500/timex.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * linux/include/asm-arm/arch-cl7500/timex.h
- *
- * CL7500 architecture timex specifications
- *
- * Copyright (C) 1999 Nexus Electronics Ltd
- */
-
-/*
- * On the ARM7500, the clock ticks at 2MHz.
- */
-#define CLOCK_TICK_RATE         2000000
-
diff --git a/include/asm-arm/arch-cl7500/uncompress.h b/include/asm-arm/arch-cl7500/uncompress.h
deleted file mode 100644
index c437e0c88c3f..000000000000
--- a/include/asm-arm/arch-cl7500/uncompress.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * linux/include/asm-arm/arch-cl7500/uncompress.h
- *
- * Copyright (C) 1999, 2000 Nexus Electronics Ltd.
- */
-#define BASE 0x03010000
-#define SERBASE (BASE + (0x2f8 << 2))
-
-static inline void putc(char c)
-{
-        while (!(*((volatile unsigned int *)(SERBASE + 0x14)) & 0x20))
-                barrier();
-
-        *((volatile unsigned int *)(SERBASE)) = c;
-}
-
-static inline void flush(void)
-{
-}
-
-static __inline__ void arch_decomp_setup(void)
-{
-        int baud = 3686400 / (9600 * 32);
-
-        *((volatile unsigned int *)(SERBASE + 0xC)) = 0x80;
-        *((volatile unsigned int *)(SERBASE + 0x0)) = baud & 0xff;
-        *((volatile unsigned int *)(SERBASE + 0x4)) = (baud & 0xff00) >> 8;
-        *((volatile unsigned int *)(SERBASE + 0xC)) = 3; /* 8 bits */
-        *((volatile unsigned int *)(SERBASE + 0x10)) = 3; /* DTR, RTS */
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-cl7500/vmalloc.h b/include/asm-arm/arch-cl7500/vmalloc.h
deleted file mode 100644
index ba8d7a84456a..000000000000
--- a/include/asm-arm/arch-cl7500/vmalloc.h
+++ /dev/null
@@ -1,4 +0,0 @@
-/*
- * linux/include/asm-arm/arch-cl7500/vmalloc.h
- */
-#define VMALLOC_END       (PAGE_OFFSET + 0x1c000000)
diff --git a/include/asm-arm/arch-clps711x/debug-macro.S b/include/asm-arm/arch-clps711x/debug-macro.S
deleted file mode 100644
index bc0a5760722b..000000000000
--- a/include/asm-arm/arch-clps711x/debug-macro.S
+++ /dev/null
@@ -1,46 +0,0 @@
-/* linux/include/asm-arm/arch-clps711x/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-#include <asm/hardware/clps7111.h>
-
-                .macro  addruart,rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx, #CLPS7111_PHYS_BASE
-                movne   \rx, #CLPS7111_VIRT_BASE
-#ifndef CONFIG_DEBUG_CLPS711X_UART2
-                add     \rx, \rx, #0x0000       @ UART1
-#else
-                add     \rx, \rx, #0x1000       @ UART2
-#endif
-                .endm
-
-                .macro  senduart,rd,rx
-                str     \rd, [\rx, #0x0480]     @ UARTDR
-                .endm
-
-                .macro  waituart,rd,rx
-1001:           ldr     \rd, [\rx, #0x0140]     @ SYSFLGx
-                tst     \rd, #1 << 11           @ UBUSYx
-                bne     1001b
-                .endm
-
-                .macro  busyuart,rd,rx
-                tst     \rx, #0x1000            @ UART2 does not have CTS here
-                bne     1002f
-1001:           ldr     \rd, [\rx, #0x0140]     @ SYSFLGx
-                tst     \rd, #1 << 8            @ CTS
-                bne     1001b
-1002:
-                .endm
-
diff --git a/include/asm-arm/arch-clps711x/dma.h b/include/asm-arm/arch-clps711x/dma.h
deleted file mode 100644
index 610997938423..000000000000
--- a/include/asm-arm/arch-clps711x/dma.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-clps711x/dma.h
- *
- *  Copyright (C) 1997,1998 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
diff --git a/include/asm-arm/arch-clps711x/entry-macro.S b/include/asm-arm/arch-clps711x/entry-macro.S
deleted file mode 100644
index 3554887cbccb..000000000000
--- a/include/asm-arm/arch-clps711x/entry-macro.S
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * include/asm-arm/arch-clps711x/entry-macro.S
- *
- * Low-level IRQ helper macros for CLPS711X-based platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <asm/arch/hardware.h>
-#include <asm/hardware/clps7111.h>
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
-#if (INTSR2 - INTSR1) != (INTMR2 - INTMR1)
-#error INTSR stride != INTMR stride
-#endif
-
-                .macro  get_irqnr_and_base, irqnr, stat, base, mask
-                mov     \base, #CLPS7111_BASE
-                ldr     \stat, [\base, #INTSR1]
-                ldr     \mask, [\base, #INTMR1]
-                mov     \irqnr, #4
-                mov     \mask, \mask, lsl #16
-                and     \stat, \stat, \mask, lsr #16
-                movs    \stat, \stat, lsr #4
-                bne     1001f
-
-                add     \base, \base, #INTSR2 - INTSR1
-                ldr     \stat, [\base, #INTSR1]
-                ldr     \mask, [\base, #INTMR1]
-                mov     \irqnr, #16
-                mov     \mask, \mask, lsl #16
-                and     \stat, \stat, \mask, lsr #16
-
-1001:           tst     \stat, #255
-                addeq   \irqnr, \irqnr, #8
-                moveq   \stat, \stat, lsr #8
-                tst     \stat, #15
-                addeq   \irqnr, \irqnr, #4
-                moveq   \stat, \stat, lsr #4
-                tst     \stat, #3
-                addeq   \irqnr, \irqnr, #2
-                moveq   \stat, \stat, lsr #2
-                tst     \stat, #1
-                addeq   \irqnr, \irqnr, #1
-                moveq   \stat, \stat, lsr #1
-                tst     \stat, #1                       @ bit 0 should be set
-                .endm
-
-
diff --git a/include/asm-arm/arch-clps711x/hardware.h b/include/asm-arm/arch-clps711x/hardware.h
deleted file mode 100644
index 0fdbe72fff2a..000000000000
--- a/include/asm-arm/arch-clps711x/hardware.h
+++ /dev/null
@@ -1,237 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-clps711x/hardware.h
- *
- *  This file contains the hardware definitions of the Prospector P720T.
- *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-
-#define CLPS7111_VIRT_BASE      0xff000000
-#define CLPS7111_BASE           CLPS7111_VIRT_BASE
-
-/*
- * The physical addresses that the external chip select signals map to is
- * dependent on the setting of the nMEDCHG signal on EP7211 and EP7212
- * processors.  CONFIG_EP72XX_BOOT_ROM is only available if these
- * processors are in use.
- */
-#ifndef CONFIG_EP72XX_ROM_BOOT
-#define CS0_PHYS_BASE           (0x00000000)
-#define CS1_PHYS_BASE           (0x10000000)
-#define CS2_PHYS_BASE           (0x20000000)
-#define CS3_PHYS_BASE           (0x30000000)
-#define CS4_PHYS_BASE           (0x40000000)
-#define CS5_PHYS_BASE           (0x50000000)
-#define CS6_PHYS_BASE           (0x60000000)
-#define CS7_PHYS_BASE           (0x70000000)
-#else
-#define CS0_PHYS_BASE           (0x70000000)
-#define CS1_PHYS_BASE           (0x60000000)
-#define CS2_PHYS_BASE           (0x50000000)
-#define CS3_PHYS_BASE           (0x40000000)
-#define CS4_PHYS_BASE           (0x30000000)
-#define CS5_PHYS_BASE           (0x20000000)
-#define CS6_PHYS_BASE           (0x10000000)
-#define CS7_PHYS_BASE           (0x00000000)
-#endif
-
-#if defined (CONFIG_ARCH_EP7211)
-
-#define EP7211_VIRT_BASE        CLPS7111_VIRT_BASE
-#define EP7211_BASE             CLPS7111_VIRT_BASE
-#include <asm/hardware/ep7211.h>
-
-#elif defined (CONFIG_ARCH_EP7212)
-
-#define EP7212_VIRT_BASE        CLPS7111_VIRT_BASE
-#define EP7212_BASE             CLPS7111_VIRT_BASE
-#include <asm/hardware/ep7212.h>
-
-#endif
-
-#define SYSPLD_VIRT_BASE        0xfe000000
-#define SYSPLD_BASE             SYSPLD_VIRT_BASE
-
-#ifndef __ASSEMBLER__
-
-#define PCIO_BASE               IO_BASE
-
-#endif
-
-
-#if  defined (CONFIG_ARCH_AUTCPU12)
-
-#define  CS89712_VIRT_BASE      CLPS7111_VIRT_BASE
-#define  CS89712_BASE           CLPS7111_VIRT_BASE
-
-#include <asm/hardware/clps7111.h>
-#include <asm/hardware/ep7212.h>
-#include <asm/hardware/cs89712.h>
-
-#endif
-
-
-#if defined (CONFIG_ARCH_CDB89712)
-
-#include <asm/hardware/clps7111.h>
-#include <asm/hardware/ep7212.h>
-#include <asm/hardware/cs89712.h>
-
-/* dynamic ioremap() areas */
-#define FLASH_START      0x00000000
-#define FLASH_SIZE       0x800000
-#define FLASH_WIDTH      4
-
-#define SRAM_START       0x60000000
-#define SRAM_SIZE        0xc000
-#define SRAM_WIDTH       4
-
-#define BOOTROM_START    0x70000000
-#define BOOTROM_SIZE     0x80
-#define BOOTROM_WIDTH    4
-
-
-/* static cdb89712_map_io() areas */
-#define REGISTER_START   0x80000000
-#define REGISTER_SIZE    0x4000
-#define REGISTER_BASE    0xff000000
-
-#define ETHER_START      0x20000000
-#define ETHER_SIZE       0x1000
-#define ETHER_BASE       0xfe000000
-
-#endif
-
-
-#if defined (CONFIG_ARCH_EDB7211)
-
-/*
- * The extra 8 lines of the keyboard matrix are wired to chip select 3 (nCS3) 
- * and repeat across it. This is the mapping for it.
- *
- * In jumpered boot mode, nCS3 is mapped to 0x4000000, not 0x3000000. This 
- * was cause for much consternation and headscratching. This should probably
- * be made a compile/run time kernel option.
- */
-#define EP7211_PHYS_EXTKBD              CS3_PHYS_BASE   /* physical */
-
-#define EP7211_VIRT_EXTKBD              (0xfd000000)    /* virtual */
-
-
-/*
- * The CS8900A ethernet chip has its I/O registers wired to chip select 2 
- * (nCS2). This is the mapping for it.
- *
- * In jumpered boot mode, nCS2 is mapped to 0x5000000, not 0x2000000. This 
- * was cause for much consternation and headscratching. This should probably
- * be made a compile/run time kernel option.
- */
-#define EP7211_PHYS_CS8900A             CS2_PHYS_BASE   /* physical */
-
-#define EP7211_VIRT_CS8900A             (0xfc000000)    /* virtual */
-
-
-/*
- * The two flash banks are wired to chip selects 0 and 1. This is the mapping
- * for them.
- *
- * nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running
- * in jumpered boot mode.
- */
-#define EP7211_PHYS_FLASH1              CS0_PHYS_BASE   /* physical */
-#define EP7211_PHYS_FLASH2              CS1_PHYS_BASE   /* physical */
-
-#define EP7211_VIRT_FLASH1              (0xfa000000)    /* virtual */
-#define EP7211_VIRT_FLASH2              (0xfb000000)    /* virtual */
-
-#endif /* CONFIG_ARCH_EDB7211 */
-
-
-/*
- * Relevant bits in port D, which controls power to the various parts of
- * the LCD on the EDB7211.
- */
-#define EDB_PD1_LCD_DC_DC_EN    (1<<1)
-#define EDB_PD2_LCDEN           (1<<2)
-#define EDB_PD3_LCDBL           (1<<3)
-
-
-#if defined (CONFIG_ARCH_CEIVA)
-
-#define  CEIVA_VIRT_BASE        CLPS7111_VIRT_BASE
-#define  CEIVA_BASE             CLPS7111_VIRT_BASE
-
-#include <asm/hardware/clps7111.h>
-#include <asm/hardware/ep7212.h>
-
-
-/*
- * The two flash banks are wired to chip selects 0 and 1. This is the mapping
- * for them.
- *
- * nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running
- * in jumpered boot mode.
- */
-#define CEIVA_PHYS_FLASH1       CS0_PHYS_BASE   /* physical */
-#define CEIVA_PHYS_FLASH2       CS1_PHYS_BASE   /* physical */
-
-#define CEIVA_VIRT_FLASH1       (0xfa000000)    /* virtual */
-#define CEIVA_VIRT_FLASH2       (0xfb000000)    /* virtual */
-
-#define CEIVA_FLASH_SIZE        0x100000
-#define CEIVA_FLASH_WIDTH       2
-
-#define SRAM_START       0x60000000
-#define SRAM_SIZE        0xc000
-#define SRAM_WIDTH       4
-
-#define BOOTROM_START    0x70000000
-#define BOOTROM_SIZE     0x80
-#define BOOTROM_WIDTH    4
-
-/*
- * SED1355 LCD controller
- */
-#define CEIVA_PHYS_SED1355      CS2_PHYS_BASE
-#define CEIVA_VIRT_SED1355      (0xfc000000)
-
-/*
- * Relevant bits in port D, which controls power to the various parts of
- * the LCD on the Ceiva Photo Max, and reset to the LCD controller.
- */
-
-// Reset line to SED1355 (must be high to operate)
-#define CEIVA_PD1_LCDRST        (1<<1)
-// LCD panel enable (set to one, to enable LCD)
-#define CEIVA_PD4_LCDEN         (1<<4)
-// Backlight (set to one, to turn on backlight
-#define CEIVA_PD5_LCDBL         (1<<5)
-
-/*
- * Relevant bits in port B, which report the status of the buttons.
- */
-
-// White button
-#define CEIVA_PB4_WHT_BTN       (1<<4)
-// Black button
-#define CEIVA_PB0_BLK_BTN       (1<<0)
-#endif // #if defined (CONFIG_ARCH_CEIVA)
-
-#endif
diff --git a/include/asm-arm/arch-clps711x/io.h b/include/asm-arm/arch-clps711x/io.h
deleted file mode 100644
index 2b84dac8b2fa..000000000000
--- a/include/asm-arm/arch-clps711x/io.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-clps711x/io.h
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#include <asm/arch/hardware.h>
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-#define __io(a)                 ((void __iomem *)(a))
-#define __mem_pci(a)            (a)
-
-/*
- * We don't support ins[lb]/outs[lb].  Make them fault.
- */
-#define __raw_readsb(p,d,l)     do { *(int *)0 = 0; } while (0)
-#define __raw_readsl(p,d,l)     do { *(int *)0 = 0; } while (0)
-#define __raw_writesb(p,d,l)    do { *(int *)0 = 0; } while (0)
-#define __raw_writesl(p,d,l)    do { *(int *)0 = 0; } while (0)
-
-#endif
diff --git a/include/asm-arm/arch-clps711x/irqs.h b/include/asm-arm/arch-clps711x/irqs.h
deleted file mode 100644
index 76025dc87637..000000000000
--- a/include/asm-arm/arch-clps711x/irqs.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-clps711x/irqs.h
- *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-/*
- * Interrupts from INTSR1
- */
-#define IRQ_CSINT                       4
-#define IRQ_EINT1                       5
-#define IRQ_EINT2                       6
-#define IRQ_EINT3                       7
-#define IRQ_TC1OI                       8
-#define IRQ_TC2OI                       9
-#define IRQ_RTCMI                       10
-#define IRQ_TINT                        11
-#define IRQ_UTXINT1                     12
-#define IRQ_URXINT1                     13
-#define IRQ_UMSINT                      14
-#define IRQ_SSEOTI                      15
-
-#define INT1_IRQS                       (0x0000fff0)
-#define INT1_ACK_IRQS                   (0x00004f10)
-
-/*
- * Interrupts from INTSR2
- */
-#define IRQ_KBDINT                      (16+0)  /* bit 0 */
-#define IRQ_SS2RX                       (16+1)  /* bit 1 */
-#define IRQ_SS2TX                       (16+2)  /* bit 2 */
-#define IRQ_UTXINT2                     (16+12) /* bit 12 */
-#define IRQ_URXINT2                     (16+13) /* bit 13 */
-
-#define INT2_IRQS                       (0x30070000)
-#define INT2_ACK_IRQS                   (0x00010000)
-
-#define NR_IRQS                         30
-
diff --git a/include/asm-arm/arch-clps711x/memory.h b/include/asm-arm/arch-clps711x/memory.h
deleted file mode 100644
index 42768cc8bfb4..000000000000
--- a/include/asm-arm/arch-clps711x/memory.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-clps711x/memory.h
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-
-/*
- * Physical DRAM offset.
- */
-#define PHYS_OFFSET     UL(0xc0000000)
-
-/*
- * Virtual view <-> DMA view memory address translations
- * virt_to_bus: Used to translate the virtual address to an
- *              address suitable to be passed to set_dma_addr
- * bus_to_virt: Used to convert an address for DMA operations
- *              to an address that the kernel can use.
- */
-
-#if defined(CONFIG_ARCH_CDB89712)
-
-#define __virt_to_bus(x)        (x)
-#define __bus_to_virt(x)        (x)
-
-#elif defined (CONFIG_ARCH_AUTCPU12)
-
-#define __virt_to_bus(x)        (x)
-#define __bus_to_virt(x)        (x)
-
-#else
-
-#define __virt_to_bus(x)        ((x) - PAGE_OFFSET)
-#define __bus_to_virt(x)        ((x) + PAGE_OFFSET)
-
-#endif
-
-
-/*
- * Like the SA1100, the EDB7211 has a large gap between physical RAM
- * banks.  In 2.2, the Psion (CL-PS7110) port added custom support for
- * discontiguous physical memory.  In 2.4, we can use the standard
- * Linux NUMA support.
- *
- * This is not necessary for EP7211 implementations with only one used
- * memory bank.  For those systems, simply undefine CONFIG_DISCONTIGMEM.
- */
-
-/*
- * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211
- * uses only one of the two banks (bank #1).  However, even within
- * bank #1, memory is discontiguous.
- *
- * The EDB7211 has two 8MB DRAM areas with 8MB of empty space between
- * them, so we use 24 for the node max shift to get 16MB node sizes.
- */
-
-/*
- * Because of the wide memory address space between physical RAM banks on the 
- * SA1100, it's much more convenient to use Linux's NUMA support to implement
- * our memory map representation.  Assuming all memory nodes have equal access 
- * characteristics, we then have generic discontiguous memory support.
- *
- * Of course, all this isn't mandatory for SA1100 implementations with only
- * one used memory bank.  For those, simply undefine CONFIG_DISCONTIGMEM.
- *
- * The nodes are matched with the physical memory bank addresses which are 
- * incidentally the same as virtual addresses.
- * 
- *      node 0:  0xc0000000 - 0xc7ffffff
- *      node 1:  0xc8000000 - 0xcfffffff
- *      node 2:  0xd0000000 - 0xd7ffffff
- *      node 3:  0xd8000000 - 0xdfffffff
- */
-#define NODE_MEM_SIZE_BITS      24
-
-#endif
-
diff --git a/include/asm-arm/arch-clps711x/syspld.h b/include/asm-arm/arch-clps711x/syspld.h
deleted file mode 100644
index 960578a22a8e..000000000000
--- a/include/asm-arm/arch-clps711x/syspld.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-clps711x/syspld.h
- *
- *  System Control PLD register definitions.
- *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_SYSPLD_H
-#define __ASM_ARCH_SYSPLD_H
-
-#define SYSPLD_PHYS_BASE        (0x10000000)
-
-#ifndef __ASSEMBLY__
-#include <asm/types.h>
-
-#define SYSPLD_REG(type,off)    (*(volatile type *)(SYSPLD_BASE + off))
-#else
-#define SYSPLD_REG(type,off)    (off)
-#endif
-
-#define PLD_INT         SYSPLD_REG(u32, 0x000000)
-#define PLD_INT_PENIRQ          (1 << 5)
-#define PLD_INT_UCB_IRQ         (1 << 1)
-#define PLD_INT_KBD_ATN         (1 << 0)        /* EINT1 */
-
-#define PLD_PWR         SYSPLD_REG(u32, 0x000004)
-#define PLD_PWR_EXT             (1 << 5)
-#define PLD_PWR_MODE            (1 << 4)        /* 1 = PWM, 0 = PFM */
-#define PLD_S4_ON               (1 << 3)        /* LCD bias voltage enable */
-#define PLD_S3_ON               (1 << 2)        /* LCD backlight enable */
-#define PLD_S2_ON               (1 << 1)        /* LCD 3V3 supply enable */
-#define PLD_S1_ON               (1 << 0)        /* LCD 3V supply enable */
-
-#define PLD_KBD         SYSPLD_REG(u32, 0x000008)
-#define PLD_KBD_WAKE            (1 << 1)
-#define PLD_KBD_EN              (1 << 0)
-
-#define PLD_SPI         SYSPLD_REG(u32, 0x00000c)
-#define PLD_SPI_EN              (1 << 0)
-
-#define PLD_IO          SYSPLD_REG(u32, 0x000010)
-#define PLD_IO_BOOTSEL          (1 << 6)        /* boot sel switch */
-#define PLD_IO_USER             (1 << 5)        /* user defined switch */
-#define PLD_IO_LED3             (1 << 4)
-#define PLD_IO_LED2             (1 << 3)
-#define PLD_IO_LED1             (1 << 2)
-#define PLD_IO_LED0             (1 << 1)
-#define PLD_IO_LEDEN            (1 << 0)
-
-#define PLD_IRDA        SYSPLD_REG(u32, 0x000014)
-#define PLD_IRDA_EN             (1 << 0)
-
-#define PLD_COM2        SYSPLD_REG(u32, 0x000018)
-#define PLD_COM2_EN             (1 << 0)
-
-#define PLD_COM1        SYSPLD_REG(u32, 0x00001c)
-#define PLD_COM1_EN             (1 << 0)
-
-#define PLD_AUD         SYSPLD_REG(u32, 0x000020)
-#define PLD_AUD_DIV1            (1 << 6)
-#define PLD_AUD_DIV0            (1 << 5)
-#define PLD_AUD_CLK_SEL1        (1 << 4)
-#define PLD_AUD_CLK_SEL0        (1 << 3)
-#define PLD_AUD_MIC_PWR         (1 << 2)
-#define PLD_AUD_MIC_GAIN        (1 << 1)
-#define PLD_AUD_CODEC_EN        (1 << 0)
-
-#define PLD_CF          SYSPLD_REG(u32, 0x000024)
-#define PLD_CF2_SLEEP           (1 << 5)
-#define PLD_CF1_SLEEP           (1 << 4)
-#define PLD_CF2_nPDREQ          (1 << 3)
-#define PLD_CF1_nPDREQ          (1 << 2)
-#define PLD_CF2_nIRQ            (1 << 1)
-#define PLD_CF1_nIRQ            (1 << 0)
-
-#define PLD_SDC         SYSPLD_REG(u32, 0x000028)
-#define PLD_SDC_INT_EN          (1 << 2)
-#define PLD_SDC_WP              (1 << 1)
-#define PLD_SDC_CD              (1 << 0)
-
-#define PLD_FPGA        SYSPLD_REG(u32, 0x00002c)
-
-#define PLD_CODEC       SYSPLD_REG(u32, 0x400000)
-#define PLD_CODEC_IRQ3          (1 << 4)
-#define PLD_CODEC_IRQ2          (1 << 3)
-#define PLD_CODEC_IRQ1          (1 << 2)
-#define PLD_CODEC_EN            (1 << 0)
-
-#define PLD_BRITE       SYSPLD_REG(u32, 0x400004)
-#define PLD_BRITE_UP            (1 << 1)
-#define PLD_BRITE_DN            (1 << 0)
-
-#define PLD_LCDEN       SYSPLD_REG(u32, 0x400008)
-#define PLD_LCDEN_EN            (1 << 0)
-
-#define PLD_ID          SYSPLD_REG(u32, 0x40000c)
-
-#define PLD_TCH         SYSPLD_REG(u32, 0x400010)
-#define PLD_TCH_PENIRQ          (1 << 1)
-#define PLD_TCH_EN              (1 << 0)
-
-#define PLD_GPIO        SYSPLD_REG(u32, 0x400014)
-#define PLD_GPIO2               (1 << 2)
-#define PLD_GPIO1               (1 << 1)
-#define PLD_GPIO0               (1 << 0)
-
-#endif
diff --git a/include/asm-arm/arch-clps711x/system.h b/include/asm-arm/arch-clps711x/system.h
deleted file mode 100644
index 1f561772bee4..000000000000
--- a/include/asm-arm/arch-clps711x/system.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-clps711x/system.h
- *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-#include <asm/arch/hardware.h>
-#include <asm/hardware/clps7111.h>
-#include <asm/io.h>
-
-static inline void arch_idle(void)
-{
-        clps_writel(1, HALT);
-        __asm__ __volatile__(
-        "mov    r0, r0\n\
-        mov     r0, r0");
-}
-
-static inline void arch_reset(char mode)
-{
-        cpu_reset(0);
-}
-
-#endif
diff --git a/include/asm-arm/arch-clps711x/time.h b/include/asm-arm/arch-clps711x/time.h
deleted file mode 100644
index 5edaae1c61d3..000000000000
--- a/include/asm-arm/arch-clps711x/time.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-clps711x/time.h
- *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <asm/leds.h>
-#include <asm/hardware/clps7111.h>
-
-extern void clps711x_setup_timer(void);
-
-/*
- * IRQ handler for the timer
- */
-static irqreturn_t
-p720t_timer_interrupt(int irq, void *dev_id)
-{
-        struct pt_regs *regs = get_irq_regs();
-        do_leds();
-        do_timer(1);
-#ifndef CONFIG_SMP
-        update_process_times(user_mode(regs));
-#endif
-        do_profile(regs);
-        return IRQ_HANDLED;
-}
-
-/*
- * Set up timer interrupt, and return the current time in seconds.
- */
-void __init time_init(void)
-{
-        clps711x_setup_timer();
-        timer_irq.handler = p720t_timer_interrupt;
-        setup_irq(IRQ_TC2OI, &timer_irq);
-}
diff --git a/include/asm-arm/arch-clps711x/timex.h b/include/asm-arm/arch-clps711x/timex.h
deleted file mode 100644
index dcbb381da3dd..000000000000
--- a/include/asm-arm/arch-clps711x/timex.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-clps711x/timex.h
- *
- *  Prospector 720T architecture timex specifications
- *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#define CLOCK_TICK_RATE 512000
diff --git a/include/asm-arm/arch-clps711x/uncompress.h b/include/asm-arm/arch-clps711x/uncompress.h
deleted file mode 100644
index 8c5684ad086e..000000000000
--- a/include/asm-arm/arch-clps711x/uncompress.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-clps711x/uncompress.h
- *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <asm/arch/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/hardware/clps7111.h>
-
-#undef CLPS7111_BASE
-#define CLPS7111_BASE CLPS7111_PHYS_BASE
-
-#define __raw_readl(p)          (*(unsigned long *)(p))
-#define __raw_writel(v,p)       (*(unsigned long *)(p) = (v))
-
-#ifdef CONFIG_DEBUG_CLPS711X_UART2
-#define SYSFLGx SYSFLG2
-#define UARTDRx UARTDR2
-#else
-#define SYSFLGx SYSFLG1
-#define UARTDRx UARTDR1
-#endif
-
-/*
- * This does not append a newline
- */
-static inline void putc(int c)
-{
-        while (clps_readl(SYSFLGx) & SYSFLG_UTXFF)
-                barrier();
-        clps_writel(c, UARTDRx);
-}
-
-static inline void flush(void)
-{
-        while (clps_readl(SYSFLGx) & SYSFLG_UBUSY)
-                barrier();
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-
-#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-clps711x/vmalloc.h b/include/asm-arm/arch-clps711x/vmalloc.h
deleted file mode 100644
index a5dfe96abc96..000000000000
--- a/include/asm-arm/arch-clps711x/vmalloc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-clps711x/vmalloc.h
- *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
diff --git a/include/asm-arm/arch-davinci/clock.h b/include/asm-arm/arch-davinci/clock.h
deleted file mode 100644
index cc168b7a14f2..000000000000
--- a/include/asm-arm/arch-davinci/clock.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * include/asm-arm/arch-davinci/clock.h
- *
- * Clock control driver for DaVinci - header file
- *
- * Authors: Vladimir Barinov <source@mvista.com>
- *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ASM_ARCH_DAVINCI_CLOCK_H
-#define __ASM_ARCH_DAVINCI_CLOCK_H
-
-struct clk;
-
-extern int clk_register(struct clk *clk);
-extern void clk_unregister(struct clk *clk);
-extern int davinci_clk_init(void);
-
-#endif
diff --git a/include/asm-arm/arch-davinci/entry-macro.S b/include/asm-arm/arch-davinci/entry-macro.S
deleted file mode 100644
index 3ebfcc5cb58e..000000000000
--- a/include/asm-arm/arch-davinci/entry-macro.S
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Low-level IRQ helper macros for TI DaVinci-based platforms
- *
- * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
- *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <asm/arch/io.h>
-#include <asm/arch/irqs.h>
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  get_irqnr_preamble, base, tmp
-                ldr \base, =IO_ADDRESS(DAVINCI_ARM_INTC_BASE)
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr \tmp, [\base, #0x14]
-                mov \tmp, \tmp, lsr #2
-                sub \irqnr, \tmp, #1
-                cmp \tmp, #0
-                .endm
-
-                .macro  irq_prio_table
-                .endm
diff --git a/include/asm-arm/arch-davinci/gpio.h b/include/asm-arm/arch-davinci/gpio.h
deleted file mode 100644
index 54fda734649f..000000000000
--- a/include/asm-arm/arch-davinci/gpio.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * TI DaVinci GPIO Support
- *
- * Copyright (c) 2006 David Brownell
- * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef __DAVINCI_GPIO_H
-#define __DAVINCI_GPIO_H
-
-#include <linux/io.h>
-#include <asm/arch/hardware.h>
-
-/*
- * basic gpio routines
- *
- * board-specific init should be done by arch/.../.../board-XXX.c (maybe
- * initializing banks together) rather than boot loaders; kexec() won't
- * go through boot loaders.
- *
- * the gpio clock will be turned on when gpios are used, and you may also
- * need to pay attention to PINMUX0 and PINMUX1 to be sure those pins are
- * used as gpios, not with other peripherals.
- *
- * GPIOs are numbered 0..(DAVINCI_N_GPIO-1).  For documentation, and maybe
- * for later updates, code should write GPIO(N) or:
- *  - GPIOV18(N) for 1.8V pins, N in 0..53; same as GPIO(0)..GPIO(53)
- *  - GPIOV33(N) for 3.3V pins, N in 0..17; same as GPIO(54)..GPIO(70)
- *
- * For GPIO IRQs use gpio_to_irq(GPIO(N)) or gpio_to_irq(GPIOV33(N)) etc
- * for now, that's != GPIO(N)
- */
-#define GPIO(X)         (X)             /* 0 <= X <= 70 */
-#define GPIOV18(X)      (X)             /* 1.8V i/o; 0 <= X <= 53 */
-#define GPIOV33(X)      ((X)+54)        /* 3.3V i/o; 0 <= X <= 17 */
-
-struct gpio_controller {
-        u32     dir;
-        u32     out_data;
-        u32     set_data;
-        u32     clr_data;
-        u32     in_data;
-        u32     set_rising;
-        u32     clr_rising;
-        u32     set_falling;
-        u32     clr_falling;
-        u32     intstat;
-};
-
-/* The __gpio_to_controller() and __gpio_mask() functions inline to constants
- * with constant parameters; or in outlined code they execute at runtime.
- *
- * You'd access the controller directly when reading or writing more than
- * one gpio value at a time, and to support wired logic where the value
- * being driven by the cpu need not match the value read back.
- *
- * These are NOT part of the cross-platform GPIO interface
- */
-static inline struct gpio_controller *__iomem
-__gpio_to_controller(unsigned gpio)
-{
-        void *__iomem ptr;
-
-        if (gpio < 32)
-                ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10);
-        else if (gpio < 64)
-                ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38);
-        else if (gpio < DAVINCI_N_GPIO)
-                ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60);
-        else
-                ptr = NULL;
-        return ptr;
-}
-
-static inline u32 __gpio_mask(unsigned gpio)
-{
-        return 1 << (gpio % 32);
-}
-
-/* The get/set/clear functions will inline when called with constant
- * parameters, for low-overhead bitbanging.  Illegal constant parameters
- * cause link-time errors.
- *
- * Otherwise, calls with variable parameters use outlined functions.
- */
-extern int __error_inval_gpio(void);
-
-extern void __gpio_set(unsigned gpio, int value);
-extern int __gpio_get(unsigned gpio);
-
-static inline void gpio_set_value(unsigned gpio, int value)
-{
-        if (__builtin_constant_p(value)) {
-                struct gpio_controller  *__iomem g;
-                u32                     mask;
-
-                if (gpio >= DAVINCI_N_GPIO)
-                        __error_inval_gpio();
-
-                g = __gpio_to_controller(gpio);
-                mask = __gpio_mask(gpio);
-                if (value)
-                        __raw_writel(mask, &g->set_data);
-                else
-                        __raw_writel(mask, &g->clr_data);
-                return;
-        }
-
-        __gpio_set(gpio, value);
-}
-
-/* Returns zero or nonzero; works for gpios configured as inputs OR
- * as outputs.
- *
- * NOTE: changes in reported values are synchronized to the GPIO clock.
- * This is most easily seen after calling gpio_set_value() and then immediatly
- * gpio_get_value(), where the gpio_get_value() would return the old value
- * until the GPIO clock ticks and the new value gets latched.
- */
-
-static inline int gpio_get_value(unsigned gpio)
-{
-        struct gpio_controller *__iomem g;
-
-        if (!__builtin_constant_p(gpio))
-                return __gpio_get(gpio);
-
-        if (gpio >= DAVINCI_N_GPIO)
-                return __error_inval_gpio();
-
-        g = __gpio_to_controller(gpio);
-        return !!(__gpio_mask(gpio) & __raw_readl(&g->in_data));
-}
-
-/* powerup default direction is IN */
-extern int gpio_direction_input(unsigned gpio);
-extern int gpio_direction_output(unsigned gpio, int value);
-
-#include <asm-generic/gpio.h>   /* cansleep wrappers */
-
-extern int gpio_request(unsigned gpio, const char *tag);
-extern void gpio_free(unsigned gpio);
-
-static inline int gpio_to_irq(unsigned gpio)
-{
-        return DAVINCI_N_AINTC_IRQ + gpio;
-}
-
-static inline int irq_to_gpio(unsigned irq)
-{
-        return irq - DAVINCI_N_AINTC_IRQ;
-}
-
-#endif                          /* __DAVINCI_GPIO_H */
diff --git a/include/asm-arm/arch-davinci/serial.h b/include/asm-arm/arch-davinci/serial.h
deleted file mode 100644
index ed418ef76805..000000000000
--- a/include/asm-arm/arch-davinci/serial.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * DaVinci serial device definitions
- *
- * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
- *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ASM_ARCH_SERIAL_H
-#define __ASM_ARCH_SERIAL_H
-
-#include <asm/arch/io.h>
-
-#define DAVINCI_UART0_BASE   (IO_PHYS + 0x20000)
-#define DAVINCI_UART1_BASE   (IO_PHYS + 0x20400)
-#define DAVINCI_UART2_BASE   (IO_PHYS + 0x20800)
-
-#endif /* __ASM_ARCH_SERIAL_H */
diff --git a/include/asm-arm/arch-davinci/system.h b/include/asm-arm/arch-davinci/system.h
deleted file mode 100644
index 6713e4a44ee8..000000000000
--- a/include/asm-arm/arch-davinci/system.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * DaVinci system defines
- *
- * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
- *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-extern void davinci_watchdog_reset(void);
-
-static void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-static void arch_reset(char mode)
-{
-        davinci_watchdog_reset();
-}
-
-#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/include/asm-arm/arch-davinci/uncompress.h b/include/asm-arm/arch-davinci/uncompress.h
deleted file mode 100644
index f6d1570f7206..000000000000
--- a/include/asm-arm/arch-davinci/uncompress.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Serial port stubs for kernel decompress status messages
- *
- *  Author:     Anant Gole
- * (C) Copyright (C) 2006, Texas Instruments, Inc
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <linux/types.h>
-#include <linux/serial_reg.h>
-#include <asm/arch/serial.h>
-
-/* PORT_16C550A, in polled non-fifo mode */
-
-static void putc(char c)
-{
-        volatile u32 *uart = (volatile void *) DAVINCI_UART0_BASE;
-
-        while (!(uart[UART_LSR] & UART_LSR_THRE))
-                barrier();
-        uart[UART_TX] = c;
-}
-
-static inline void flush(void)
-{
-        volatile u32 *uart = (volatile void *) DAVINCI_UART0_BASE;
-        while (!(uart[UART_LSR] & UART_LSR_THRE))
-                barrier();
-}
-
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-davinci/vmalloc.h b/include/asm-arm/arch-davinci/vmalloc.h
deleted file mode 100644
index 9b47fa89b333..000000000000
--- a/include/asm-arm/arch-davinci/vmalloc.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * DaVinci vmalloc definitions
- *
- * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
- *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <asm/memory.h>
-#include <asm/arch/io.h>
-
-/* Allow vmalloc range until the IO virtual range minus a 2M "hole" */
-#define VMALLOC_END       (IO_VIRT - (2<<20))
diff --git a/include/asm-arm/arch-ebsa110/debug-macro.S b/include/asm-arm/arch-ebsa110/debug-macro.S
deleted file mode 100644
index 9213bfe4831d..000000000000
--- a/include/asm-arm/arch-ebsa110/debug-macro.S
+++ /dev/null
@@ -1,21 +0,0 @@
-/* linux/include/asm-arm/arch-ebsa110/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-**/
-
-                .macro  addruart,rx
-                mov     \rx, #0xf0000000
-                orr     \rx, \rx, #0x00000be0
-                .endm
-
-#define UART_SHIFT      2
-#define FLOW_CONTROL
-#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-ebsa110/dma.h b/include/asm-arm/arch-ebsa110/dma.h
deleted file mode 100644
index c52f9e2ab0bb..000000000000
--- a/include/asm-arm/arch-ebsa110/dma.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-ebsa110/dma.h
- *
- *  Copyright (C) 1997,1998 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  EBSA110 DMA definitions
- */
diff --git a/include/asm-arm/arch-ebsa110/entry-macro.S b/include/asm-arm/arch-ebsa110/entry-macro.S
deleted file mode 100644
index f242be5c49ba..000000000000
--- a/include/asm-arm/arch-ebsa110/entry-macro.S
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * include/asm-arm/arch-ebsa110/entry-macro.S
- *
- * Low-level IRQ helper macros for ebsa110 platform.
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-
-
-#define IRQ_STAT                0xff000000      /* read */
-
-        .macro  disable_fiq
-        .endm
-
-        .macro  get_irqnr_preamble, base, tmp
-        mov     \base, #IRQ_STAT
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
-        .macro  get_irqnr_and_base, irqnr, stat, base, tmp
-        ldrb    \stat, [\base]                  @ get interrupts
-        mov     \irqnr, #0
-        tst     \stat, #15
-        addeq   \irqnr, \irqnr, #4
-        moveq   \stat, \stat, lsr #4
-        tst     \stat, #3
-        addeq   \irqnr, \irqnr, #2
-        moveq   \stat, \stat, lsr #2
-        tst     \stat, #1
-        addeq   \irqnr, \irqnr, #1
-        moveq   \stat, \stat, lsr #1
-        tst     \stat, #1                       @ bit 0 should be set
-        .endm
-
diff --git a/include/asm-arm/arch-ebsa110/hardware.h b/include/asm-arm/arch-ebsa110/hardware.h
deleted file mode 100644
index 3ce864def41e..000000000000
--- a/include/asm-arm/arch-ebsa110/hardware.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-ebsa110/hardware.h
- *
- *  Copyright (C) 1996-2000 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This file contains the hardware definitions of the EBSA-110.
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-/*
- * The EBSA110 has a weird "ISA IO" region:
- *
- * Region 0 (addr = 0xf0000000 + io << 2)
- * --------------------------------------------------------
- * Physical region      IO region
- * f0000fe0 - f0000ffc  3f8 - 3ff  ttyS0
- * f0000e60 - f0000e64  398 - 399
- * f0000de0 - f0000dfc  378 - 37f  lp0
- * f0000be0 - f0000bfc  2f8 - 2ff  ttyS1
- *
- * Region 1 (addr = 0xf0000000 + (io & ~1) << 1 + (io & 1))
- * --------------------------------------------------------
- * Physical region      IO region
- * f00014f1             a79        pnp write data
- * f00007c0 - f00007c1  3e0 - 3e1  pcmcia
- * f00004f1             279        pnp address
- * f0000440 - f000046c  220 - 236  eth0
- * f0000405             203        pnp read data
- */
-
-#define ISAMEM_PHYS             0xe0000000
-#define ISAMEM_SIZE             0x10000000
-
-#define ISAIO_PHYS              0xf0000000
-#define ISAIO_SIZE              PGDIR_SIZE
-
-#define TRICK0_PHYS             0xf2000000
-#define TRICK1_PHYS             0xf2400000
-#define TRICK2_PHYS             0xf2800000
-#define TRICK3_PHYS             0xf2c00000
-#define TRICK4_PHYS             0xf3000000
-#define TRICK5_PHYS             0xf3400000
-#define TRICK6_PHYS             0xf3800000
-#define TRICK7_PHYS             0xf3c00000
-
-#define ISAMEM_BASE             0xe0000000
-#define ISAIO_BASE              0xf0000000
-
-#define PIT_BASE                0xfc000000
-#define SOFT_BASE               0xfd000000
-
-/*
- * RAM definitions
- */
-#define UNCACHEABLE_ADDR        0xff000000      /* IRQ_STAT */
-
-#endif
-
diff --git a/include/asm-arm/arch-ebsa110/io.h b/include/asm-arm/arch-ebsa110/io.h
deleted file mode 100644
index 44a4001de807..000000000000
--- a/include/asm-arm/arch-ebsa110/io.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-ebsa110/io.h
- *
- *  Copyright (C) 1997,1998 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Modifications:
- *  06-Dec-1997 RMK     Created.
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffff
-
-u8 __inb8(unsigned int port);
-void __outb8(u8  val, unsigned int port);
-
-u8 __inb16(unsigned int port);
-void __outb16(u8  val, unsigned int port);
-
-u16 __inw(unsigned int port);
-void __outw(u16 val, unsigned int port);
-
-u32 __inl(unsigned int port);
-void __outl(u32 val, unsigned int port);
-
-u8  __readb(const volatile void __iomem *addr);
-u16 __readw(const volatile void __iomem *addr);
-u32 __readl(const volatile void __iomem *addr);
-
-void __writeb(u8  val, void __iomem *addr);
-void __writew(u16 val, void __iomem *addr);
-void __writel(u32 val, void __iomem *addr);
-
-/*
- * Argh, someone forgot the IOCS16 line.  We therefore have to handle
- * the byte stearing by selecting the correct byte IO functions here.
- */
-#ifdef ISA_SIXTEEN_BIT_PERIPHERAL
-#define inb(p)                  __inb16(p)
-#define outb(v,p)               __outb16(v,p)
-#else
-#define inb(p)                  __inb8(p)
-#define outb(v,p)               __outb8(v,p)
-#endif
-
-#define inw(p)                  __inw(p)
-#define outw(v,p)               __outw(v,p)
-
-#define inl(p)                  __inl(p)
-#define outl(v,p)               __outl(v,p)
-
-#define readb(b)                __readb(b)
-#define readw(b)                __readw(b)
-#define readl(b)                __readl(b)
-#define readb_relaxed(addr)     readb(addr)
-#define readw_relaxed(addr)     readw(addr)
-#define readl_relaxed(addr)     readl(addr)
-
-#define writeb(v,b)             __writeb(v,b)
-#define writew(v,b)             __writew(v,b)
-#define writel(v,b)             __writel(v,b)
-
-static inline void __iomem *__arch_ioremap(unsigned long cookie, size_t size,
-                                           unsigned int flags)
-{
-        return (void __iomem *)cookie;
-}
-
-#define __arch_ioremap          __arch_ioremap
-#define __arch_iounmap(cookie)  do { } while (0)
-
-extern void insb(unsigned int port, void *buf, int sz);
-extern void insw(unsigned int port, void *buf, int sz);
-extern void insl(unsigned int port, void *buf, int sz);
-
-extern void outsb(unsigned int port, const void *buf, int sz);
-extern void outsw(unsigned int port, const void *buf, int sz);
-extern void outsl(unsigned int port, const void *buf, int sz);
-
-/* can't support writesb atm */
-extern void writesw(void __iomem *addr, const void *data, int wordlen);
-extern void writesl(void __iomem *addr, const void *data, int longlen);
-
-/* can't support readsb atm */
-extern void readsw(const void __iomem *addr, void *data, int wordlen);
-extern void readsl(const void __iomem *addr, void *data, int longlen);
-
-#endif
diff --git a/include/asm-arm/arch-ebsa110/irqs.h b/include/asm-arm/arch-ebsa110/irqs.h
deleted file mode 100644
index ded9bd9d7b8b..000000000000
--- a/include/asm-arm/arch-ebsa110/irqs.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-ebsa110/irqs.h
- *
- *  Copyright (C) 1996 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#define NR_IRQS                 8
-
-#define IRQ_EBSA110_PRINTER     0
-#define IRQ_EBSA110_COM1        1
-#define IRQ_EBSA110_COM2        2
-#define IRQ_EBSA110_ETHERNET    3
-#define IRQ_EBSA110_TIMER0      4
-#define IRQ_EBSA110_TIMER1      5
-#define IRQ_EBSA110_PCMCIA      6
-#define IRQ_EBSA110_IMMEDIATE   7
diff --git a/include/asm-arm/arch-ebsa110/memory.h b/include/asm-arm/arch-ebsa110/memory.h
deleted file mode 100644
index c7c500e176d0..000000000000
--- a/include/asm-arm/arch-ebsa110/memory.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-ebsa110/memory.h
- *
- *  Copyright (C) 1996-1999 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  Changelog:
- *   20-Oct-1996 RMK    Created
- *   31-Dec-1997 RMK    Fixed definitions to reduce warnings
- *   21-Mar-1999 RMK    Renamed to memory.h
- *               RMK    Moved TASK_SIZE and PAGE_OFFSET here
- */
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-/*
- * Physical DRAM offset.
- */
-#define PHYS_OFFSET     UL(0x00000000)
-
-/*
- * We keep this 1:1 so that we don't interfere
- * with the PCMCIA memory regions
- */
-#define __virt_to_bus(x)        (x)
-#define __bus_to_virt(x)        (x)
-
-/*
- * Cache flushing area - SRAM
- */
-#define FLUSH_BASE_PHYS         0x40000000
-#define FLUSH_BASE              0xdf000000
-
-#endif
diff --git a/include/asm-arm/arch-ebsa110/system.h b/include/asm-arm/arch-ebsa110/system.h
deleted file mode 100644
index d7c8fece0bc5..000000000000
--- a/include/asm-arm/arch-ebsa110/system.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-ebsa110/system.h
- *
- *  Copyright (C) 1996-2000 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-/*
- * EBSA110 idling methodology:
- *
- * We can not execute the "wait for interrupt" instruction since that
- * will stop our MCLK signal (which provides the clock for the glue
- * logic, and therefore the timer interrupt).
- *
- * Instead, we spin, polling the IRQ_STAT register for the occurrence
- * of any interrupt with core clock down to the memory clock.
- */
-static inline void arch_idle(void)
-{
-        const char *irq_stat = (char *)0xff000000;
-
-        /* disable clock switching */
-        asm volatile ("mcr p15, 0, ip, c15, c2, 2" : : : "cc");
-
-        /* wait for an interrupt to occur */
-        while (!*irq_stat);
-
-        /* enable clock switching */
-        asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc");
-}
-
-#define arch_reset(mode)        cpu_reset(0x80000000)
-
-#endif
diff --git a/include/asm-arm/arch-ebsa110/timex.h b/include/asm-arm/arch-ebsa110/timex.h
deleted file mode 100644
index 1e9ef045092b..000000000000
--- a/include/asm-arm/arch-ebsa110/timex.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-ebsa110/timex.h
- *
- *  Copyright (C) 1997, 1998 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  EBSA110 architecture timex specifications
- */
-
-/*
- * On the EBSA, the clock ticks at weird rates.
- * This is therefore not used to calculate the
- * divisor.
- */
-#define CLOCK_TICK_RATE         47894000
-
diff --git a/include/asm-arm/arch-ebsa110/uncompress.h b/include/asm-arm/arch-ebsa110/uncompress.h
deleted file mode 100644
index ae5b775eb0b7..000000000000
--- a/include/asm-arm/arch-ebsa110/uncompress.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-ebsa110/uncompress.h
- *
- *  Copyright (C) 1996,1997,1998 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/serial_reg.h>
-
-#define SERIAL_BASE     ((unsigned char *)0xf0000be0)
-
-/*
- * This does not append a newline
- */
-static inline void putc(int c)
-{
-        unsigned char v, *base = SERIAL_BASE;
-
-        do {
-                v = base[UART_LSR << 2];
-                barrier();
-        } while (!(v & UART_LSR_THRE));
-
-        base[UART_TX << 2] = c;
-}
-
-static inline void flush(void)
-{
-        unsigned char v, *base = SERIAL_BASE;
-
-        do {
-                v = base[UART_LSR << 2];
-                barrier();
-        } while ((v & (UART_LSR_TEMT|UART_LSR_THRE)) !=
-                 (UART_LSR_TEMT|UART_LSR_THRE));
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-ebsa110/vmalloc.h b/include/asm-arm/arch-ebsa110/vmalloc.h
deleted file mode 100644
index 26674ba4683c..000000000000
--- a/include/asm-arm/arch-ebsa110/vmalloc.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-ebsa110/vmalloc.h
- *
- *  Copyright (C) 1998 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#define VMALLOC_END       (PAGE_OFFSET + 0x1f000000)
diff --git a/include/asm-arm/arch-ebsa285/debug-macro.S b/include/asm-arm/arch-ebsa285/debug-macro.S
deleted file mode 100644
index b48cec4a0c45..000000000000
--- a/include/asm-arm/arch-ebsa285/debug-macro.S
+++ /dev/null
@@ -1,57 +0,0 @@
-/* linux/include/asm-arm/arch-ebsa285/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-#include <asm/hardware/dec21285.h>
-
-#ifndef CONFIG_DEBUG_DC21285_PORT
-        /* For NetWinder debugging */
-                .macro  addruart,rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx, #0x7c000000        @ physical
-                movne   \rx, #0xff000000        @ virtual
-                orr     \rx, \rx, #0x000003f8
-                .endm
-
-#define UART_SHIFT      0
-#define FLOW_CONTROL
-#include <asm/hardware/debug-8250.S>
-
-#else
-        /* For EBSA285 debugging */
-                .equ    dc21285_high, ARMCSR_BASE & 0xff000000
-                .equ    dc21285_low,  ARMCSR_BASE & 0x00ffffff
-
-                .macro  addruart,rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx, #0x42000000
-                movne   \rx, #dc21285_high
-                .if     dc21285_low
-                orrne   \rx, \rx, #dc21285_low
-                .endif
-                .endm
-
-                .macro  senduart,rd,rx
-                str     \rd, [\rx, #0x160]      @ UARTDR
-                .endm
-
-                .macro  busyuart,rd,rx
-1001:           ldr     \rd, [\rx, #0x178]      @ UARTFLG
-                tst     \rd, #1 << 3
-                bne     1001b
-                .endm
-
-                .macro  waituart,rd,rx
-                .endm
-#endif
diff --git a/include/asm-arm/arch-ebsa285/dma.h b/include/asm-arm/arch-ebsa285/dma.h
deleted file mode 100644
index 0259ad45d33c..000000000000
--- a/include/asm-arm/arch-ebsa285/dma.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-ebsa285/dma.h
- *
- *  Architecture DMA routines
- *
- *  Copyright (C) 1998,1999 Russell King
- *  Copyright (C) 1998,1999 Philip Blundell
- */
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-
-/*
- * The 21285 has two internal DMA channels; we call these 8 and 9.
- * On CATS hardware we have an additional eight ISA dma channels
- * numbered 0..7.
- */
-#define _ISA_DMA(x)             (0+(x))
-#define _DC21285_DMA(x)         (8+(x))
-
-#define MAX_DMA_CHANNELS        10
-
-#define DMA_FLOPPY              _ISA_DMA(2)
-#define DMA_ISA_CASCADE         _ISA_DMA(4)
-
-#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-ebsa285/entry-macro.S b/include/asm-arm/arch-ebsa285/entry-macro.S
deleted file mode 100644
index e203c628d500..000000000000
--- a/include/asm-arm/arch-ebsa285/entry-macro.S
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * include/asm-arm/arch-ebsa285/entry-macro.S
- *
- * Low-level IRQ helper macros for footbridge-based platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <asm/arch/hardware.h>
-#include <asm/arch/irqs.h>
-#include <asm/hardware/dec21285.h>
-
-                .equ    dc21285_high, ARMCSR_BASE & 0xff000000
-                .equ    dc21285_low, ARMCSR_BASE & 0x00ffffff
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  get_irqnr_preamble, base, tmp
-                mov     \base, #dc21285_high
-                .if     dc21285_low
-                orr     \base, \base, #dc21285_low
-                .endif
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \irqstat, [\base, #0x180]       @ get interrupts
-
-                mov     \irqnr, #IRQ_SDRAMPARITY
-                tst     \irqstat, #IRQ_MASK_SDRAMPARITY
-                bne     1001f
-
-                tst     \irqstat, #IRQ_MASK_UART_RX
-                movne   \irqnr, #IRQ_CONRX
-                bne     1001f
-
-                tst     \irqstat, #IRQ_MASK_DMA1
-                movne   \irqnr, #IRQ_DMA1
-                bne     1001f
-
-                tst     \irqstat, #IRQ_MASK_DMA2
-                movne   \irqnr, #IRQ_DMA2
-                bne     1001f
-
-                tst     \irqstat, #IRQ_MASK_IN0
-                movne   \irqnr, #IRQ_IN0
-                bne     1001f
-
-                tst     \irqstat, #IRQ_MASK_IN1
-                movne   \irqnr, #IRQ_IN1
-                bne     1001f
-
-                tst     \irqstat, #IRQ_MASK_IN2
-                movne   \irqnr, #IRQ_IN2
-                bne     1001f
-
-                tst     \irqstat, #IRQ_MASK_IN3
-                movne   \irqnr, #IRQ_IN3
-                bne     1001f
-
-                tst     \irqstat, #IRQ_MASK_PCI
-                movne   \irqnr, #IRQ_PCI
-                bne     1001f
-
-                tst     \irqstat, #IRQ_MASK_DOORBELLHOST
-                movne   \irqnr, #IRQ_DOORBELLHOST
-                bne     1001f
-
-                tst     \irqstat, #IRQ_MASK_I2OINPOST
-                movne   \irqnr, #IRQ_I2OINPOST
-                bne     1001f
-
-                tst     \irqstat, #IRQ_MASK_TIMER1
-                movne   \irqnr, #IRQ_TIMER1
-                bne     1001f
-
-                tst     \irqstat, #IRQ_MASK_TIMER2
-                movne   \irqnr, #IRQ_TIMER2
-                bne     1001f
-
-                tst     \irqstat, #IRQ_MASK_TIMER3
-                movne   \irqnr, #IRQ_TIMER3
-                bne     1001f
-
-                tst     \irqstat, #IRQ_MASK_UART_TX
-                movne   \irqnr, #IRQ_CONTX
-                bne     1001f
-
-                tst     \irqstat, #IRQ_MASK_PCI_ABORT
-                movne   \irqnr, #IRQ_PCI_ABORT
-                bne     1001f
-
-                tst     \irqstat, #IRQ_MASK_PCI_SERR
-                movne   \irqnr, #IRQ_PCI_SERR
-                bne     1001f
-
-                tst     \irqstat, #IRQ_MASK_DISCARD_TIMER
-                movne   \irqnr, #IRQ_DISCARD_TIMER
-                bne     1001f
-
-                tst     \irqstat, #IRQ_MASK_PCI_DPERR
-                movne   \irqnr, #IRQ_PCI_DPERR
-                bne     1001f
-
-                tst     \irqstat, #IRQ_MASK_PCI_PERR
-                movne   \irqnr, #IRQ_PCI_PERR
-1001:
-                .endm
-
diff --git a/include/asm-arm/arch-ebsa285/hardware.h b/include/asm-arm/arch-ebsa285/hardware.h
deleted file mode 100644
index 74610c2c63d4..000000000000
--- a/include/asm-arm/arch-ebsa285/hardware.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-ebsa285/hardware.h
- *
- *  Copyright (C) 1998-1999 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  This file contains the hardware definitions of the EBSA-285.
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <asm/arch/memory.h>
-
-/*   Virtual      Physical      Size
- * 0xff800000   0x40000000      1MB     X-Bus
- * 0xff000000   0x7c000000      1MB     PCI I/O space
- * 0xfe000000   0x42000000      1MB     CSR
- * 0xfd000000   0x78000000      1MB     Outbound write flush (not supported)
- * 0xfc000000   0x79000000      1MB     PCI IACK/special space
- * 0xfb000000   0x7a000000      16MB    PCI Config type 1
- * 0xfa000000   0x7b000000      16MB    PCI Config type 0
- * 0xf9000000   0x50000000      1MB     Cache flush
- * 0xf0000000   0x80000000      16MB    ISA memory
- */
-#define XBUS_SIZE               0x00100000
-#define XBUS_BASE               0xff800000
-
-#define PCIO_SIZE               0x00100000
-#define PCIO_BASE               0xff000000
-
-#define ARMCSR_SIZE             0x00100000
-#define ARMCSR_BASE             0xfe000000
-
-#define WFLUSH_SIZE             0x00100000
-#define WFLUSH_BASE             0xfd000000
-
-#define PCIIACK_SIZE            0x00100000
-#define PCIIACK_BASE            0xfc000000
-
-#define PCICFG1_SIZE            0x01000000
-#define PCICFG1_BASE            0xfb000000
-
-#define PCICFG0_SIZE            0x01000000
-#define PCICFG0_BASE            0xfa000000
-
-#define PCIMEM_SIZE             0x01000000
-#define PCIMEM_BASE             0xf0000000
-
-#define XBUS_LEDS               ((volatile unsigned char *)(XBUS_BASE + 0x12000))
-#define XBUS_LED_AMBER          (1 << 0)
-#define XBUS_LED_GREEN          (1 << 1)
-#define XBUS_LED_RED            (1 << 2)
-#define XBUS_LED_TOGGLE         (1 << 8)
-
-#define XBUS_SWITCH             ((volatile unsigned char *)(XBUS_BASE + 0x12000))
-#define XBUS_SWITCH_SWITCH      ((*XBUS_SWITCH) & 15)
-#define XBUS_SWITCH_J17_13      ((*XBUS_SWITCH) & (1 << 4))
-#define XBUS_SWITCH_J17_11      ((*XBUS_SWITCH) & (1 << 5))
-#define XBUS_SWITCH_J17_9       ((*XBUS_SWITCH) & (1 << 6))
-
-#define UNCACHEABLE_ADDR        (ARMCSR_BASE + 0x108)
-
-
-/* PIC irq control */
-#define PIC_LO                  0x20
-#define PIC_MASK_LO             0x21
-#define PIC_HI                  0xA0
-#define PIC_MASK_HI             0xA1
-
-/* GPIO pins */
-#define GPIO_CCLK               0x800
-#define GPIO_DSCLK              0x400
-#define GPIO_E2CLK              0x200
-#define GPIO_IOLOAD             0x100
-#define GPIO_RED_LED            0x080
-#define GPIO_WDTIMER            0x040
-#define GPIO_DATA               0x020
-#define GPIO_IOCLK              0x010
-#define GPIO_DONE               0x008
-#define GPIO_FAN                0x004
-#define GPIO_GREEN_LED          0x002
-#define GPIO_RESET              0x001
-
-/* CPLD pins */
-#define CPLD_DS_ENABLE          8
-#define CPLD_7111_DISABLE       4
-#define CPLD_UNMUTE             2
-#define CPLD_FLASH_WR_ENABLE    1
-
-#ifndef __ASSEMBLY__
-extern void gpio_modify_op(int mask, int set);
-extern void gpio_modify_io(int mask, int in);
-extern int  gpio_read(void);
-extern void cpld_modify(int mask, int set);
-#endif
-
-#define pcibios_assign_all_busses()     1
-
-#define PCIBIOS_MIN_IO          0x1000
-#define PCIBIOS_MIN_MEM         0x81000000
-
-#endif
diff --git a/include/asm-arm/arch-ebsa285/io.h b/include/asm-arm/arch-ebsa285/io.h
deleted file mode 100644
index e88c6e230387..000000000000
--- a/include/asm-arm/arch-ebsa285/io.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-ebsa285/io.h
- *
- *  Copyright (C) 1997-1999 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  Modifications:
- *   06-12-1997 RMK     Created.
- *   07-04-1999 RMK     Major cleanup
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#include <asm/arch/hardware.h>
-
-#define IO_SPACE_LIMIT 0xffff
-
-/*
- * Translation of various region addresses to virtual addresses
- */
-#define __io(a)                 ((void __iomem *)(PCIO_BASE + (a)))
-#if 1
-#define __mem_pci(a)            (a)
-#else
-
-static inline void __iomem *___mem_pci(void __iomem *p)
-{
-        unsigned long a = (unsigned long)p;
-        BUG_ON(a <= 0xc0000000 || a >= 0xe0000000);
-        return p;
-}
-
-#define __mem_pci(a)            ___mem_pci(a)
-#endif
-
-#endif
diff --git a/include/asm-arm/arch-ebsa285/irqs.h b/include/asm-arm/arch-ebsa285/irqs.h
deleted file mode 100644
index 3e766f1cecf1..000000000000
--- a/include/asm-arm/arch-ebsa285/irqs.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ebsa285/irqs.h
- *
- * Copyright (C) 1998 Russell King
- * Copyright (C) 1998 Phil Blundell
- *
- * Changelog:
- *  20-Jan-1998 RMK     Started merge of EBSA286, CATS and NetWinder
- *  01-Feb-1999 PJB     ISA IRQs start at 0 not 16
- */
-#include <asm/mach-types.h>
-
-#define NR_IRQS                 36
-#define NR_DC21285_IRQS         16
-
-#define _ISA_IRQ(x)             (0 + (x))
-#define _ISA_INR(x)             ((x) - 0)
-#define _DC21285_IRQ(x)         (16 + (x))
-#define _DC21285_INR(x)         ((x) - 16)
-
-/*
- * This is a list of all interrupts that the 21285
- * can generate and we handle.
- */
-#define IRQ_CONRX               _DC21285_IRQ(0)
-#define IRQ_CONTX               _DC21285_IRQ(1)
-#define IRQ_TIMER1              _DC21285_IRQ(2)
-#define IRQ_TIMER2              _DC21285_IRQ(3)
-#define IRQ_TIMER3              _DC21285_IRQ(4)
-#define IRQ_IN0                 _DC21285_IRQ(5)
-#define IRQ_IN1                 _DC21285_IRQ(6)
-#define IRQ_IN2                 _DC21285_IRQ(7)
-#define IRQ_IN3                 _DC21285_IRQ(8)
-#define IRQ_DOORBELLHOST        _DC21285_IRQ(9)
-#define IRQ_DMA1                _DC21285_IRQ(10)
-#define IRQ_DMA2                _DC21285_IRQ(11)
-#define IRQ_PCI                 _DC21285_IRQ(12)
-#define IRQ_SDRAMPARITY         _DC21285_IRQ(13)
-#define IRQ_I2OINPOST           _DC21285_IRQ(14)
-#define IRQ_PCI_ABORT           _DC21285_IRQ(15)
-#define IRQ_PCI_SERR            _DC21285_IRQ(16)
-#define IRQ_DISCARD_TIMER       _DC21285_IRQ(17)
-#define IRQ_PCI_DPERR           _DC21285_IRQ(18)
-#define IRQ_PCI_PERR            _DC21285_IRQ(19)
-
-#define IRQ_ISA_TIMER           _ISA_IRQ(0)
-#define IRQ_ISA_KEYBOARD        _ISA_IRQ(1)
-#define IRQ_ISA_CASCADE         _ISA_IRQ(2)
-#define IRQ_ISA_UART2           _ISA_IRQ(3)
-#define IRQ_ISA_UART            _ISA_IRQ(4)
-#define IRQ_ISA_FLOPPY          _ISA_IRQ(6)
-#define IRQ_ISA_PRINTER         _ISA_IRQ(7)
-#define IRQ_ISA_RTC_ALARM       _ISA_IRQ(8)
-#define IRQ_ISA_2               _ISA_IRQ(9)
-#define IRQ_ISA_PS2MOUSE        _ISA_IRQ(12)
-#define IRQ_ISA_HARDDISK1       _ISA_IRQ(14)
-#define IRQ_ISA_HARDDISK2       _ISA_IRQ(15)
-
-#define IRQ_MASK_UART_RX        (1 << 2)
-#define IRQ_MASK_UART_TX        (1 << 3)
-#define IRQ_MASK_TIMER1         (1 << 4)
-#define IRQ_MASK_TIMER2         (1 << 5)
-#define IRQ_MASK_TIMER3         (1 << 6)
-#define IRQ_MASK_IN0            (1 << 8)
-#define IRQ_MASK_IN1            (1 << 9)
-#define IRQ_MASK_IN2            (1 << 10)
-#define IRQ_MASK_IN3            (1 << 11)
-#define IRQ_MASK_DOORBELLHOST   (1 << 15)
-#define IRQ_MASK_DMA1           (1 << 16)
-#define IRQ_MASK_DMA2           (1 << 17)
-#define IRQ_MASK_PCI            (1 << 18)
-#define IRQ_MASK_SDRAMPARITY    (1 << 24)
-#define IRQ_MASK_I2OINPOST      (1 << 25)
-#define IRQ_MASK_PCI_ABORT      ((1 << 29) | (1 << 30))
-#define IRQ_MASK_PCI_SERR       (1 << 23)
-#define IRQ_MASK_DISCARD_TIMER  (1 << 27)
-#define IRQ_MASK_PCI_DPERR      (1 << 28)
-#define IRQ_MASK_PCI_PERR       (1 << 31)
-
-/*
- * Netwinder interrupt allocations
- */
-#define IRQ_NETWINDER_ETHER10   IRQ_IN0
-#define IRQ_NETWINDER_ETHER100  IRQ_IN1
-#define IRQ_NETWINDER_VIDCOMP   IRQ_IN2
-#define IRQ_NETWINDER_PS2MOUSE  _ISA_IRQ(5)
-#define IRQ_NETWINDER_IR        _ISA_IRQ(6)
-#define IRQ_NETWINDER_BUTTON    _ISA_IRQ(10)
-#define IRQ_NETWINDER_VGA       _ISA_IRQ(11)
-#define IRQ_NETWINDER_SOUND     _ISA_IRQ(12)
-
-#undef RTC_IRQ
-#define RTC_IRQ         IRQ_ISA_RTC_ALARM
-#define I8042_KBD_IRQ   IRQ_ISA_KEYBOARD
-#define I8042_AUX_IRQ   (machine_is_netwinder() ? IRQ_NETWINDER_PS2MOUSE : IRQ_ISA_PS2MOUSE)
-#define IRQ_FLOPPYDISK  IRQ_ISA_FLOPPY
-
-#define irq_canonicalize(_i)    (((_i) == IRQ_ISA_CASCADE) ? IRQ_ISA_2 : _i)
diff --git a/include/asm-arm/arch-ebsa285/memory.h b/include/asm-arm/arch-ebsa285/memory.h
deleted file mode 100644
index 9019a3bf5ab9..000000000000
--- a/include/asm-arm/arch-ebsa285/memory.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-ebsa285/memory.h
- *
- *  Copyright (C) 1996-1999 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  Changelog:
- *   20-Oct-1996 RMK    Created
- *   31-Dec-1997 RMK    Fixed definitions to reduce warnings.
- *   17-May-1998 DAG    Added __virt_to_bus and __bus_to_virt functions.
- *   21-Nov-1998 RMK    Changed __virt_to_bus and __bus_to_virt to macros.
- *   21-Mar-1999 RMK    Added PAGE_OFFSET for co285 architecture.
- *                      Renamed to memory.h
- *                      Moved PAGE_OFFSET and TASK_SIZE here
- */
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-
-#if defined(CONFIG_FOOTBRIDGE_ADDIN)
-/*
- * If we may be using add-in footbridge mode, then we must
- * use the out-of-line translation that makes use of the
- * PCI BAR
- */
-#ifndef __ASSEMBLY__
-extern unsigned long __virt_to_bus(unsigned long);
-extern unsigned long __bus_to_virt(unsigned long);
-#endif
-
-#elif defined(CONFIG_FOOTBRIDGE_HOST)
-
-#define __virt_to_bus(x)        ((x) - 0xe0000000)
-#define __bus_to_virt(x)        ((x) + 0xe0000000)
-
-#else
-
-#error "Undefined footbridge mode"
-
-#endif
-
-/* Task size and page offset at 3GB */
-#define TASK_SIZE               UL(0xbf000000)
-#define PAGE_OFFSET             UL(0xc0000000)
-
-/*
- * Cache flushing area.
- */
-#define FLUSH_BASE              0xf9000000
-
-/*
- * Physical DRAM offset.
- */
-#define PHYS_OFFSET             UL(0x00000000)
-
-/*
- * This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
-#define TASK_UNMAPPED_BASE ((TASK_SIZE + 0x01000000) / 3)
-
-#define FLUSH_BASE_PHYS         0x50000000
-
-#endif
diff --git a/include/asm-arm/arch-ebsa285/system.h b/include/asm-arm/arch-ebsa285/system.h
deleted file mode 100644
index a720bf7ca123..000000000000
--- a/include/asm-arm/arch-ebsa285/system.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-ebsa285/system.h
- *
- *  Copyright (C) 1996-1999 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <asm/hardware/dec21285.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-static inline void arch_reset(char mode)
-{
-        if (mode == 's') {
-                /*
-                 * Jump into the ROM
-                 */
-                cpu_reset(0x41000000);
-        } else {
-                if (machine_is_netwinder()) {
-                        /* open up the SuperIO chip
-                         */
-                        outb(0x87, 0x370);
-                        outb(0x87, 0x370);
-
-                        /* aux function group 1 (logical device 7)
-                         */
-                        outb(0x07, 0x370);
-                        outb(0x07, 0x371);
-
-                        /* set GP16 for WD-TIMER output
-                         */
-                        outb(0xe6, 0x370);
-                        outb(0x00, 0x371);
-
-                        /* set a RED LED and toggle WD_TIMER for rebooting
-                         */
-                        outb(0xc4, 0x338);
-                } else {
-                        /* 
-                         * Force the watchdog to do a CPU reset.
-                         *
-                         * After making sure that the watchdog is disabled
-                         * (so we can change the timer registers) we first
-                         * enable the timer to autoreload itself.  Next, the
-                         * timer interval is set really short and any
-                         * current interrupt request is cleared (so we can
-                         * see an edge transition).  Finally, TIMER4 is
-                         * enabled as the watchdog.
-                         */
-                        *CSR_SA110_CNTL &= ~(1 << 13);
-                        *CSR_TIMER4_CNTL = TIMER_CNTL_ENABLE |
-                                           TIMER_CNTL_AUTORELOAD |
-                                           TIMER_CNTL_DIV16;
-                        *CSR_TIMER4_LOAD = 0x2;
-                        *CSR_TIMER4_CLR  = 0;
-                        *CSR_SA110_CNTL |= (1 << 13);
-                }
-        }
-}
diff --git a/include/asm-arm/arch-ebsa285/timex.h b/include/asm-arm/arch-ebsa285/timex.h
deleted file mode 100644
index df60b3812d96..000000000000
--- a/include/asm-arm/arch-ebsa285/timex.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-ebsa285/timex.h
- *
- *  Copyright (C) 1998 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  EBSA285 architecture timex specifications
- */
-
-/*
- * We assume a constant here; this satisfies the maths in linux/timex.h
- * and linux/time.h.  CLOCK_TICK_RATE is actually system dependent, but
- * this must be a constant.
- */
-#define CLOCK_TICK_RATE         (50000000/16)
diff --git a/include/asm-arm/arch-ebsa285/uncompress.h b/include/asm-arm/arch-ebsa285/uncompress.h
deleted file mode 100644
index 86142c882b3a..000000000000
--- a/include/asm-arm/arch-ebsa285/uncompress.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-ebsa285/uncompress.h
- *
- *  Copyright (C) 1996-1999 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <asm/mach-types.h>
-
-/*
- * Note! This could cause problems on the NetWinder
- */
-#define DC21285_BASE ((volatile unsigned int *)0x42000160)
-#define SER0_BASE    ((volatile unsigned char *)0x7c0003f8)
-
-static inline void putc(char c)
-{
-        if (machine_is_netwinder()) {
-                while ((SER0_BASE[5] & 0x60) != 0x60)
-                        barrier();
-                SER0_BASE[0] = c;
-        } else {
-                while (DC21285_BASE[6] & 8);
-                DC21285_BASE[0] = c;
-        }
-}
-
-static inline void flush(void)
-{
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-ebsa285/vmalloc.h b/include/asm-arm/arch-ebsa285/vmalloc.h
deleted file mode 100644
index e487d7e8c8a6..000000000000
--- a/include/asm-arm/arch-ebsa285/vmalloc.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-ebsa285/vmalloc.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-
-#define VMALLOC_END       (PAGE_OFFSET + 0x30000000)
diff --git a/include/asm-arm/arch-ep93xx/debug-macro.S b/include/asm-arm/arch-ep93xx/debug-macro.S
deleted file mode 100644
index 397565a0c671..000000000000
--- a/include/asm-arm/arch-ep93xx/debug-macro.S
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ep93xx/debug-macro.S
- * Debugging macro include header
- *
- * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- */
-#include <asm/arch/ep93xx-regs.h>
-
-                .macro  addruart,rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                         @ MMU enabled?
-                ldreq   \rx, =EP93XX_APB_PHYS_BASE      @ Physical base
-                ldrne   \rx, =EP93XX_APB_VIRT_BASE      @ virtual base
-                orr     \rx, \rx, #0x000c0000
-                .endm
-
-#include <asm/hardware/debug-pl01x.S>
diff --git a/include/asm-arm/arch-ep93xx/dma.h b/include/asm-arm/arch-ep93xx/dma.h
deleted file mode 100644
index 898b3ab7fd46..000000000000
--- a/include/asm-arm/arch-ep93xx/dma.h
+++ /dev/null
@@ -1,3 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ep93xx/dma.h
- */
diff --git a/include/asm-arm/arch-ep93xx/entry-macro.S b/include/asm-arm/arch-ep93xx/entry-macro.S
deleted file mode 100644
index 241ec221a047..000000000000
--- a/include/asm-arm/arch-ep93xx/entry-macro.S
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ep93xx/entry-macro.S
- * IRQ demultiplexing for EP93xx
- *
- * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- */
-#include <asm/arch/ep93xx-regs.h>
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \base, =(EP93XX_AHB_VIRT_BASE)
-                orr     \base, \base, #0x000b0000
-                mov     \irqnr, #0
-                ldr     \irqstat, [\base]               @ lower 32 interrupts
-                cmp     \irqstat, #0
-                bne     1001f
-
-                eor     \base, \base, #0x00070000
-                ldr     \irqstat, [\base]               @ upper 32 interrupts
-                cmp     \irqstat, #0
-                beq     1002f
-                mov     \irqnr, #0x20
-
-1001:
-                movs    \tmp, \irqstat, lsl #16
-                movne   \irqstat, \tmp
-                addeq   \irqnr, \irqnr, #16
-
-                movs    \tmp, \irqstat, lsl #8
-                movne   \irqstat, \tmp
-                addeq   \irqnr, \irqnr, #8
-
-                movs    \tmp, \irqstat, lsl #4
-                movne   \irqstat, \tmp
-                addeq   \irqnr, \irqnr, #4
-
-                movs    \tmp, \irqstat, lsl #2
-                movne   \irqstat, \tmp
-                addeq   \irqnr, \irqnr, #2
-
-                movs    \tmp, \irqstat, lsl #1
-                addeq   \irqnr, \irqnr, #1
-                orrs    \base, \base, #1
-
-1002:
-                .endm
diff --git a/include/asm-arm/arch-ep93xx/ep93xx-regs.h b/include/asm-arm/arch-ep93xx/ep93xx-regs.h
deleted file mode 100644
index 625c6f0abc03..000000000000
--- a/include/asm-arm/arch-ep93xx/ep93xx-regs.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ep93xx/ep93xx-regs.h
- */
-
-#ifndef __ASM_ARCH_EP93XX_REGS_H
-#define __ASM_ARCH_EP93XX_REGS_H
-
-/*
- * EP93xx linux memory map:
- *
- * virt         phys            size
- * fe800000                     5M              per-platform mappings
- * fed00000     80800000        2M              APB
- * fef00000     80000000        1M              AHB
- */
-
-#define EP93XX_AHB_PHYS_BASE            0x80000000
-#define EP93XX_AHB_VIRT_BASE            0xfef00000
-#define EP93XX_AHB_SIZE                 0x00100000
-
-#define EP93XX_APB_PHYS_BASE            0x80800000
-#define EP93XX_APB_VIRT_BASE            0xfed00000
-#define EP93XX_APB_SIZE                 0x00200000
-
-
-/* AHB peripherals */
-#define EP93XX_DMA_BASE                 (EP93XX_AHB_VIRT_BASE + 0x00000000)
-
-#define EP93XX_ETHERNET_BASE            (EP93XX_AHB_VIRT_BASE + 0x00010000)
-#define EP93XX_ETHERNET_PHYS_BASE       (EP93XX_AHB_PHYS_BASE + 0x00010000)
-
-#define EP93XX_USB_BASE                 (EP93XX_AHB_VIRT_BASE + 0x00020000)
-#define EP93XX_USB_PHYS_BASE            (EP93XX_AHB_PHYS_BASE + 0x00020000)
-
-#define EP93XX_RASTER_BASE              (EP93XX_AHB_VIRT_BASE + 0x00030000)
-
-#define EP93XX_GRAPHICS_ACCEL_BASE      (EP93XX_AHB_VIRT_BASE + 0x00040000)
-
-#define EP93XX_SDRAM_CONTROLLER_BASE    (EP93XX_AHB_VIRT_BASE + 0x00060000)
-
-#define EP93XX_PCMCIA_CONTROLLER_BASE   (EP93XX_AHB_VIRT_BASE + 0x00080000)
-
-#define EP93XX_BOOT_ROM_BASE            (EP93XX_AHB_VIRT_BASE + 0x00090000)
-
-#define EP93XX_IDE_BASE                 (EP93XX_AHB_VIRT_BASE + 0x000a0000)
-
-#define EP93XX_VIC1_BASE                (EP93XX_AHB_VIRT_BASE + 0x000b0000)
-
-#define EP93XX_VIC2_BASE                (EP93XX_AHB_VIRT_BASE + 0x000c0000)
-
-
-/* APB peripherals */
-#define EP93XX_TIMER_BASE               (EP93XX_APB_VIRT_BASE + 0x00010000)
-#define EP93XX_TIMER_REG(x)             (EP93XX_TIMER_BASE + (x))
-#define EP93XX_TIMER1_LOAD              EP93XX_TIMER_REG(0x00)
-#define EP93XX_TIMER1_VALUE             EP93XX_TIMER_REG(0x04)
-#define EP93XX_TIMER1_CONTROL           EP93XX_TIMER_REG(0x08)
-#define EP93XX_TIMER1_CLEAR             EP93XX_TIMER_REG(0x0c)
-#define EP93XX_TIMER2_LOAD              EP93XX_TIMER_REG(0x20)
-#define EP93XX_TIMER2_VALUE             EP93XX_TIMER_REG(0x24)
-#define EP93XX_TIMER2_CONTROL           EP93XX_TIMER_REG(0x28)
-#define EP93XX_TIMER2_CLEAR             EP93XX_TIMER_REG(0x2c)
-#define EP93XX_TIMER4_VALUE_LOW         EP93XX_TIMER_REG(0x60)
-#define EP93XX_TIMER4_VALUE_HIGH        EP93XX_TIMER_REG(0x64)
-#define EP93XX_TIMER3_LOAD              EP93XX_TIMER_REG(0x80)
-#define EP93XX_TIMER3_VALUE             EP93XX_TIMER_REG(0x84)
-#define EP93XX_TIMER3_CONTROL           EP93XX_TIMER_REG(0x88)
-#define EP93XX_TIMER3_CLEAR             EP93XX_TIMER_REG(0x8c)
-
-#define EP93XX_I2S_BASE                 (EP93XX_APB_VIRT_BASE + 0x00020000)
-
-#define EP93XX_SECURITY_BASE            (EP93XX_APB_VIRT_BASE + 0x00030000)
-
-#define EP93XX_GPIO_BASE                (EP93XX_APB_VIRT_BASE + 0x00040000)
-#define EP93XX_GPIO_REG(x)              (EP93XX_GPIO_BASE + (x))
-#define EP93XX_GPIO_F_INT_TYPE1         EP93XX_GPIO_REG(0x4c)
-#define EP93XX_GPIO_F_INT_TYPE2         EP93XX_GPIO_REG(0x50)
-#define EP93XX_GPIO_F_INT_ACK           EP93XX_GPIO_REG(0x54)
-#define EP93XX_GPIO_F_INT_ENABLE        EP93XX_GPIO_REG(0x58)
-#define EP93XX_GPIO_F_INT_STATUS        EP93XX_GPIO_REG(0x5c)
-#define EP93XX_GPIO_A_INT_TYPE1         EP93XX_GPIO_REG(0x90)
-#define EP93XX_GPIO_A_INT_TYPE2         EP93XX_GPIO_REG(0x94)
-#define EP93XX_GPIO_A_INT_ACK           EP93XX_GPIO_REG(0x98)
-#define EP93XX_GPIO_A_INT_ENABLE        EP93XX_GPIO_REG(0x9c)
-#define EP93XX_GPIO_A_INT_STATUS        EP93XX_GPIO_REG(0xa0)
-#define EP93XX_GPIO_B_INT_TYPE1         EP93XX_GPIO_REG(0xac)
-#define EP93XX_GPIO_B_INT_TYPE2         EP93XX_GPIO_REG(0xb0)
-#define EP93XX_GPIO_B_INT_ACK           EP93XX_GPIO_REG(0xb4)
-#define EP93XX_GPIO_B_INT_ENABLE        EP93XX_GPIO_REG(0xb8)
-#define EP93XX_GPIO_B_INT_STATUS        EP93XX_GPIO_REG(0xbc)
-
-#define EP93XX_AAC_BASE                 (EP93XX_APB_VIRT_BASE + 0x00080000)
-
-#define EP93XX_SPI_BASE                 (EP93XX_APB_VIRT_BASE + 0x000a0000)
-
-#define EP93XX_IRDA_BASE                (EP93XX_APB_VIRT_BASE + 0x000b0000)
-
-#define EP93XX_UART1_BASE               (EP93XX_APB_VIRT_BASE + 0x000c0000)
-#define EP93XX_UART1_PHYS_BASE          (EP93XX_APB_PHYS_BASE + 0x000c0000)
-
-#define EP93XX_UART2_BASE               (EP93XX_APB_VIRT_BASE + 0x000d0000)
-#define EP93XX_UART2_PHYS_BASE          (EP93XX_APB_PHYS_BASE + 0x000d0000)
-
-#define EP93XX_UART3_BASE               (EP93XX_APB_VIRT_BASE + 0x000e0000)
-#define EP93XX_UART3_PHYS_BASE          (EP93XX_APB_PHYS_BASE + 0x000e0000)
-
-#define EP93XX_KEY_MATRIX_BASE          (EP93XX_APB_VIRT_BASE + 0x000f0000)
-
-#define EP93XX_ADC_BASE                 (EP93XX_APB_VIRT_BASE + 0x00100000)
-#define EP93XX_TOUCHSCREEN_BASE         (EP93XX_APB_VIRT_BASE + 0x00100000)
-
-#define EP93XX_PWM_BASE                 (EP93XX_APB_VIRT_BASE + 0x00110000)
-
-#define EP93XX_RTC_BASE                 (EP93XX_APB_VIRT_BASE + 0x00120000)
-
-#define EP93XX_SYSCON_BASE              (EP93XX_APB_VIRT_BASE + 0x00130000)
-#define EP93XX_SYSCON_REG(x)            (EP93XX_SYSCON_BASE + (x))
-#define EP93XX_SYSCON_POWER_STATE       EP93XX_SYSCON_REG(0x00)
-#define EP93XX_SYSCON_CLOCK_CONTROL     EP93XX_SYSCON_REG(0x04)
-#define EP93XX_SYSCON_CLOCK_UARTBAUD    0x20000000
-#define EP93XX_SYSCON_CLOCK_USH_EN      0x10000000
-#define EP93XX_SYSCON_HALT              EP93XX_SYSCON_REG(0x08)
-#define EP93XX_SYSCON_STANDBY           EP93XX_SYSCON_REG(0x0c)
-#define EP93XX_SYSCON_CLOCK_SET1        EP93XX_SYSCON_REG(0x20)
-#define EP93XX_SYSCON_CLOCK_SET2        EP93XX_SYSCON_REG(0x24)
-#define EP93XX_SYSCON_DEVICE_CONFIG     EP93XX_SYSCON_REG(0x80)
-#define EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE       0x00800000
-#define EP93XX_SYSCON_SWLOCK            EP93XX_SYSCON_REG(0xc0)
-
-#define EP93XX_WATCHDOG_BASE            (EP93XX_APB_VIRT_BASE + 0x00140000)
-
-
-#endif
diff --git a/include/asm-arm/arch-ep93xx/gesbc9312.h b/include/asm-arm/arch-ep93xx/gesbc9312.h
deleted file mode 100644
index 4d0b3023bff7..000000000000
--- a/include/asm-arm/arch-ep93xx/gesbc9312.h
+++ /dev/null
@@ -1,3 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ep93xx/gesbc9312.h
- */
diff --git a/include/asm-arm/arch-ep93xx/gpio.h b/include/asm-arm/arch-ep93xx/gpio.h
deleted file mode 100644
index 186e7c715f8a..000000000000
--- a/include/asm-arm/arch-ep93xx/gpio.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ep93xx/gpio.h
- */
-
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H
-
-/* GPIO port A.  */
-#define EP93XX_GPIO_LINE_A(x)           ((x) + 0)
-#define EP93XX_GPIO_LINE_EGPIO0         EP93XX_GPIO_LINE_A(0)
-#define EP93XX_GPIO_LINE_EGPIO1         EP93XX_GPIO_LINE_A(1)
-#define EP93XX_GPIO_LINE_EGPIO2         EP93XX_GPIO_LINE_A(2)
-#define EP93XX_GPIO_LINE_EGPIO3         EP93XX_GPIO_LINE_A(3)
-#define EP93XX_GPIO_LINE_EGPIO4         EP93XX_GPIO_LINE_A(4)
-#define EP93XX_GPIO_LINE_EGPIO5         EP93XX_GPIO_LINE_A(5)
-#define EP93XX_GPIO_LINE_EGPIO6         EP93XX_GPIO_LINE_A(6)
-#define EP93XX_GPIO_LINE_EGPIO7         EP93XX_GPIO_LINE_A(7)
-
-/* GPIO port B.  */
-#define EP93XX_GPIO_LINE_B(x)           ((x) + 8)
-#define EP93XX_GPIO_LINE_EGPIO8         EP93XX_GPIO_LINE_B(0)
-#define EP93XX_GPIO_LINE_EGPIO9         EP93XX_GPIO_LINE_B(1)
-#define EP93XX_GPIO_LINE_EGPIO10        EP93XX_GPIO_LINE_B(2)
-#define EP93XX_GPIO_LINE_EGPIO11        EP93XX_GPIO_LINE_B(3)
-#define EP93XX_GPIO_LINE_EGPIO12        EP93XX_GPIO_LINE_B(4)
-#define EP93XX_GPIO_LINE_EGPIO13        EP93XX_GPIO_LINE_B(5)
-#define EP93XX_GPIO_LINE_EGPIO14        EP93XX_GPIO_LINE_B(6)
-#define EP93XX_GPIO_LINE_EGPIO15        EP93XX_GPIO_LINE_B(7)
-
-/* GPIO port C.  */
-#define EP93XX_GPIO_LINE_C(x)           ((x) + 40)
-#define EP93XX_GPIO_LINE_ROW0           EP93XX_GPIO_LINE_C(0)
-#define EP93XX_GPIO_LINE_ROW1           EP93XX_GPIO_LINE_C(1)
-#define EP93XX_GPIO_LINE_ROW2           EP93XX_GPIO_LINE_C(2)
-#define EP93XX_GPIO_LINE_ROW3           EP93XX_GPIO_LINE_C(3)
-#define EP93XX_GPIO_LINE_ROW4           EP93XX_GPIO_LINE_C(4)
-#define EP93XX_GPIO_LINE_ROW5           EP93XX_GPIO_LINE_C(5)
-#define EP93XX_GPIO_LINE_ROW6           EP93XX_GPIO_LINE_C(6)
-#define EP93XX_GPIO_LINE_ROW7           EP93XX_GPIO_LINE_C(7)
-
-/* GPIO port D.  */
-#define EP93XX_GPIO_LINE_D(x)           ((x) + 24)
-#define EP93XX_GPIO_LINE_COL0           EP93XX_GPIO_LINE_D(0)
-#define EP93XX_GPIO_LINE_COL1           EP93XX_GPIO_LINE_D(1)
-#define EP93XX_GPIO_LINE_COL2           EP93XX_GPIO_LINE_D(2)
-#define EP93XX_GPIO_LINE_COL3           EP93XX_GPIO_LINE_D(3)
-#define EP93XX_GPIO_LINE_COL4           EP93XX_GPIO_LINE_D(4)
-#define EP93XX_GPIO_LINE_COL5           EP93XX_GPIO_LINE_D(5)
-#define EP93XX_GPIO_LINE_COL6           EP93XX_GPIO_LINE_D(6)
-#define EP93XX_GPIO_LINE_COL7           EP93XX_GPIO_LINE_D(7)
-
-/* GPIO port E.  */
-#define EP93XX_GPIO_LINE_E(x)           ((x) + 32)
-#define EP93XX_GPIO_LINE_GRLED          EP93XX_GPIO_LINE_E(0)
-#define EP93XX_GPIO_LINE_RDLED          EP93XX_GPIO_LINE_E(1)
-#define EP93XX_GPIO_LINE_DIORn          EP93XX_GPIO_LINE_E(2)
-#define EP93XX_GPIO_LINE_IDECS1n        EP93XX_GPIO_LINE_E(3)
-#define EP93XX_GPIO_LINE_IDECS2n        EP93XX_GPIO_LINE_E(4)
-#define EP93XX_GPIO_LINE_IDEDA0         EP93XX_GPIO_LINE_E(5)
-#define EP93XX_GPIO_LINE_IDEDA1         EP93XX_GPIO_LINE_E(6)
-#define EP93XX_GPIO_LINE_IDEDA2         EP93XX_GPIO_LINE_E(7)
-
-/* GPIO port F.  */
-#define EP93XX_GPIO_LINE_F(x)           ((x) + 16)
-#define EP93XX_GPIO_LINE_WP             EP93XX_GPIO_LINE_F(0)
-#define EP93XX_GPIO_LINE_MCCD1          EP93XX_GPIO_LINE_F(1)
-#define EP93XX_GPIO_LINE_MCCD2          EP93XX_GPIO_LINE_F(2)
-#define EP93XX_GPIO_LINE_MCBVD1         EP93XX_GPIO_LINE_F(3)
-#define EP93XX_GPIO_LINE_MCBVD2         EP93XX_GPIO_LINE_F(4)
-#define EP93XX_GPIO_LINE_VS1            EP93XX_GPIO_LINE_F(5)
-#define EP93XX_GPIO_LINE_READY          EP93XX_GPIO_LINE_F(6)
-#define EP93XX_GPIO_LINE_VS2            EP93XX_GPIO_LINE_F(7)
-
-/* GPIO port G.  */
-#define EP93XX_GPIO_LINE_G(x)           ((x) + 48)
-#define EP93XX_GPIO_LINE_EECLK          EP93XX_GPIO_LINE_G(0)
-#define EP93XX_GPIO_LINE_EEDAT          EP93XX_GPIO_LINE_G(1)
-#define EP93XX_GPIO_LINE_SLA0           EP93XX_GPIO_LINE_G(2)
-#define EP93XX_GPIO_LINE_SLA1           EP93XX_GPIO_LINE_G(3)
-#define EP93XX_GPIO_LINE_DD12           EP93XX_GPIO_LINE_G(4)
-#define EP93XX_GPIO_LINE_DD13           EP93XX_GPIO_LINE_G(5)
-#define EP93XX_GPIO_LINE_DD14           EP93XX_GPIO_LINE_G(6)
-#define EP93XX_GPIO_LINE_DD15           EP93XX_GPIO_LINE_G(7)
-
-/* GPIO port H.  */
-#define EP93XX_GPIO_LINE_H(x)           ((x) + 56)
-#define EP93XX_GPIO_LINE_DD0            EP93XX_GPIO_LINE_H(0)
-#define EP93XX_GPIO_LINE_DD1            EP93XX_GPIO_LINE_H(1)
-#define EP93XX_GPIO_LINE_DD2            EP93XX_GPIO_LINE_H(2)
-#define EP93XX_GPIO_LINE_DD3            EP93XX_GPIO_LINE_H(3)
-#define EP93XX_GPIO_LINE_DD4            EP93XX_GPIO_LINE_H(4)
-#define EP93XX_GPIO_LINE_DD5            EP93XX_GPIO_LINE_H(5)
-#define EP93XX_GPIO_LINE_DD6            EP93XX_GPIO_LINE_H(6)
-#define EP93XX_GPIO_LINE_DD7            EP93XX_GPIO_LINE_H(7)
-
-/* maximum value for gpio line identifiers */
-#define EP93XX_GPIO_LINE_MAX            EP93XX_GPIO_LINE_H(7)
-
-/* maximum value for irq capable line identifiers */
-#define EP93XX_GPIO_LINE_MAX_IRQ        EP93XX_GPIO_LINE_F(7)
-
-/* new generic GPIO API - see Documentation/gpio.txt */
-
-#include <asm-generic/gpio.h>
-
-#define gpio_get_value  __gpio_get_value
-#define gpio_set_value  __gpio_set_value
-#define gpio_cansleep   __gpio_cansleep
-
-/*
- * Map GPIO A0..A7  (0..7)  to irq 64..71,
- *          B0..B7  (7..15) to irq 72..79, and
- *          F0..F7 (16..24) to irq 80..87.
- */
-static inline int gpio_to_irq(unsigned gpio)
-{
-        if (gpio <= EP93XX_GPIO_LINE_MAX_IRQ)
-                return 64 + gpio;
-
-        return -EINVAL;
-}
-
-static inline int irq_to_gpio(unsigned irq)
-{
-        return irq - gpio_to_irq(0);
-}
-
-#endif
diff --git a/include/asm-arm/arch-ep93xx/hardware.h b/include/asm-arm/arch-ep93xx/hardware.h
deleted file mode 100644
index 4233f6e85150..000000000000
--- a/include/asm-arm/arch-ep93xx/hardware.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ep93xx/hardware.h
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include "ep93xx-regs.h"
-
-#define pcibios_assign_all_busses()     0
-
-#include "platform.h"
-
-#include "gesbc9312.h"
-#include "ts72xx.h"
-
-#endif
diff --git a/include/asm-arm/arch-ep93xx/io.h b/include/asm-arm/arch-ep93xx/io.h
deleted file mode 100644
index 7b4d25e29060..000000000000
--- a/include/asm-arm/arch-ep93xx/io.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ep93xx/io.h
- */
-
-#define IO_SPACE_LIMIT          0xffffffff
-
-#define __io(p)                 ((void __iomem *)(p))
-#define __mem_pci(p)            (p)
diff --git a/include/asm-arm/arch-ep93xx/irqs.h b/include/asm-arm/arch-ep93xx/irqs.h
deleted file mode 100644
index 53d4a68bfc88..000000000000
--- a/include/asm-arm/arch-ep93xx/irqs.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ep93xx/irqs.h
- */
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H
-
-#define IRQ_EP93XX_COMMRX               2
-#define IRQ_EP93XX_COMMTX               3
-#define IRQ_EP93XX_TIMER1               4
-#define IRQ_EP93XX_TIMER2               5
-#define IRQ_EP93XX_AACINTR              6
-#define IRQ_EP93XX_DMAM2P0              7
-#define IRQ_EP93XX_DMAM2P1              8
-#define IRQ_EP93XX_DMAM2P2              9
-#define IRQ_EP93XX_DMAM2P3              10
-#define IRQ_EP93XX_DMAM2P4              11
-#define IRQ_EP93XX_DMAM2P5              12
-#define IRQ_EP93XX_DMAM2P6              13
-#define IRQ_EP93XX_DMAM2P7              14
-#define IRQ_EP93XX_DMAM2P8              15
-#define IRQ_EP93XX_DMAM2P9              16
-#define IRQ_EP93XX_DMAM2M0              17
-#define IRQ_EP93XX_DMAM2M1              18
-#define IRQ_EP93XX_GPIO0MUX             19
-#define IRQ_EP93XX_GPIO1MUX             20
-#define IRQ_EP93XX_GPIO2MUX             21
-#define IRQ_EP93XX_GPIO3MUX             22
-#define IRQ_EP93XX_UART1RX              23
-#define IRQ_EP93XX_UART1TX              24
-#define IRQ_EP93XX_UART2RX              25
-#define IRQ_EP93XX_UART2TX              26
-#define IRQ_EP93XX_UART3RX              27
-#define IRQ_EP93XX_UART3TX              28
-#define IRQ_EP93XX_KEY                  29
-#define IRQ_EP93XX_TOUCH                30
-#define EP93XX_VIC1_VALID_IRQ_MASK      0x7ffffffc
-
-#define IRQ_EP93XX_EXT0                 32
-#define IRQ_EP93XX_EXT1                 33
-#define IRQ_EP93XX_EXT2                 34
-#define IRQ_EP93XX_64HZ                 35
-#define IRQ_EP93XX_WATCHDOG             36
-#define IRQ_EP93XX_RTC                  37
-#define IRQ_EP93XX_IRDA                 38
-#define IRQ_EP93XX_ETHERNET             39
-#define IRQ_EP93XX_EXT3                 40
-#define IRQ_EP93XX_PROG                 41
-#define IRQ_EP93XX_1HZ                  42
-#define IRQ_EP93XX_VSYNC                43
-#define IRQ_EP93XX_VIDEO_FIFO           44
-#define IRQ_EP93XX_SSP1RX               45
-#define IRQ_EP93XX_SSP1TX               46
-#define IRQ_EP93XX_GPIO4MUX             47
-#define IRQ_EP93XX_GPIO5MUX             48
-#define IRQ_EP93XX_GPIO6MUX             49
-#define IRQ_EP93XX_GPIO7MUX             50
-#define IRQ_EP93XX_TIMER3               51
-#define IRQ_EP93XX_UART1                52
-#define IRQ_EP93XX_SSP                  53
-#define IRQ_EP93XX_UART2                54
-#define IRQ_EP93XX_UART3                55
-#define IRQ_EP93XX_USB                  56
-#define IRQ_EP93XX_ETHERNET_PME         57
-#define IRQ_EP93XX_DSP                  58
-#define IRQ_EP93XX_GPIO_AB              59
-#define IRQ_EP93XX_SAI                  60
-#define EP93XX_VIC2_VALID_IRQ_MASK      0x1fffffff
-
-#define NR_EP93XX_IRQS                  (64 + 24)
-
-#define EP93XX_BOARD_IRQ(x)             (NR_EP93XX_IRQS + (x))
-#define EP93XX_BOARD_IRQS               32
-
-#define NR_IRQS                         (NR_EP93XX_IRQS + EP93XX_BOARD_IRQS)
-
-
-#endif
diff --git a/include/asm-arm/arch-ep93xx/memory.h b/include/asm-arm/arch-ep93xx/memory.h
deleted file mode 100644
index 4b1a5c7c8363..000000000000
--- a/include/asm-arm/arch-ep93xx/memory.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ep93xx/memory.h
- */
-
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-#define PHYS_OFFSET             UL(0x00000000)
-
-#define __bus_to_virt(x)        __phys_to_virt(x)
-#define __virt_to_bus(x)        __virt_to_phys(x)
-
-
-#endif
diff --git a/include/asm-arm/arch-ep93xx/platform.h b/include/asm-arm/arch-ep93xx/platform.h
deleted file mode 100644
index 44eccec2cba4..000000000000
--- a/include/asm-arm/arch-ep93xx/platform.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ep93xx/platform.h
- */
-
-#ifndef __ASSEMBLY__
-
-void ep93xx_map_io(void);
-void ep93xx_init_irq(void);
-void ep93xx_init_time(unsigned long);
-void ep93xx_init_devices(void);
-extern struct sys_timer ep93xx_timer;
-
-struct ep93xx_eth_data
-{
-        unsigned char   dev_addr[6];
-        unsigned char   phy_id;
-};
-
-
-#endif
diff --git a/include/asm-arm/arch-ep93xx/system.h b/include/asm-arm/arch-ep93xx/system.h
deleted file mode 100644
index f1a5acf51919..000000000000
--- a/include/asm-arm/arch-ep93xx/system.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ep93xx/system.h
- */
-
-#include <asm/arch/hardware.h>
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-static inline void arch_reset(char mode)
-{
-        u32 devicecfg;
-
-        local_irq_disable();
-
-        devicecfg = __raw_readl(EP93XX_SYSCON_DEVICE_CONFIG);
-        __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
-        __raw_writel(devicecfg | 0x80000000, EP93XX_SYSCON_DEVICE_CONFIG);
-        __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
-        __raw_writel(devicecfg & ~0x80000000, EP93XX_SYSCON_DEVICE_CONFIG);
-
-        while (1)
-                ;
-}
diff --git a/include/asm-arm/arch-ep93xx/timex.h b/include/asm-arm/arch-ep93xx/timex.h
deleted file mode 100644
index 4140bddc97e2..000000000000
--- a/include/asm-arm/arch-ep93xx/timex.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ep93xx/timex.h
- */
-
-#define CLOCK_TICK_RATE         983040
diff --git a/include/asm-arm/arch-ep93xx/ts72xx.h b/include/asm-arm/arch-ep93xx/ts72xx.h
deleted file mode 100644
index a94f63ff0535..000000000000
--- a/include/asm-arm/arch-ep93xx/ts72xx.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ep93xx/ts72xx.h
- */
-
-/*
- * TS72xx memory map:
- *
- * virt         phys            size
- * febff000     22000000        4K      model number register
- * febfe000     22400000        4K      options register
- * febfd000     22800000        4K      options register #2
- * febfc000     [67]0000000     4K      NAND data register
- * febfb000     [67]0400000     4K      NAND control register
- * febfa000     [67]0800000     4K      NAND busy register
- * febf9000     10800000        4K      TS-5620 RTC index register
- * febf8000     11700000        4K      TS-5620 RTC data register
- */
-
-#define TS72XX_MODEL_PHYS_BASE          0x22000000
-#define TS72XX_MODEL_VIRT_BASE          0xfebff000
-#define TS72XX_MODEL_SIZE               0x00001000
-
-#define TS72XX_MODEL_TS7200             0x00
-#define TS72XX_MODEL_TS7250             0x01
-#define TS72XX_MODEL_TS7260             0x02
-
-
-#define TS72XX_OPTIONS_PHYS_BASE        0x22400000
-#define TS72XX_OPTIONS_VIRT_BASE        0xfebfe000
-#define TS72XX_OPTIONS_SIZE             0x00001000
-
-#define TS72XX_OPTIONS_COM2_RS485       0x02
-#define TS72XX_OPTIONS_MAX197           0x01
-
-
-#define TS72XX_OPTIONS2_PHYS_BASE       0x22800000
-#define TS72XX_OPTIONS2_VIRT_BASE       0xfebfd000
-#define TS72XX_OPTIONS2_SIZE            0x00001000
-
-#define TS72XX_OPTIONS2_TS9420          0x04
-#define TS72XX_OPTIONS2_TS9420_BOOT     0x02
-
-
-#define TS72XX_NOR_PHYS_BASE            0x60000000
-#define TS72XX_NOR2_PHYS_BASE           0x62000000
-
-#define TS72XX_NAND1_DATA_PHYS_BASE     0x60000000
-#define TS72XX_NAND2_DATA_PHYS_BASE     0x70000000
-#define TS72XX_NAND_DATA_VIRT_BASE      0xfebfc000
-#define TS72XX_NAND_DATA_SIZE           0x00001000
-
-#define TS72XX_NAND1_CONTROL_PHYS_BASE  0x60400000
-#define TS72XX_NAND2_CONTROL_PHYS_BASE  0x70400000
-#define TS72XX_NAND_CONTROL_VIRT_BASE   0xfebfb000
-#define TS72XX_NAND_CONTROL_SIZE        0x00001000
-
-#define TS72XX_NAND1_BUSY_PHYS_BASE     0x60800000
-#define TS72XX_NAND2_BUSY_PHYS_BASE     0x70800000
-#define TS72XX_NAND_BUSY_VIRT_BASE      0xfebfa000
-#define TS72XX_NAND_BUSY_SIZE           0x00001000
-
-
-#define TS72XX_RTC_INDEX_VIRT_BASE      0xfebf9000
-#define TS72XX_RTC_INDEX_PHYS_BASE      0x10800000
-#define TS72XX_RTC_INDEX_SIZE           0x00001000
-
-#define TS72XX_RTC_DATA_VIRT_BASE       0xfebf8000
-#define TS72XX_RTC_DATA_PHYS_BASE       0x11700000
-#define TS72XX_RTC_DATA_SIZE            0x00001000
-
-
-#ifndef __ASSEMBLY__
-#include <asm/io.h>
-
-static inline int board_is_ts7200(void)
-{
-        return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7200;
-}
-
-static inline int board_is_ts7250(void)
-{
-        return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7250;
-}
-
-static inline int board_is_ts7260(void)
-{
-        return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7260;
-}
-
-static inline int is_max197_installed(void)
-{
-        return !!(__raw_readb(TS72XX_OPTIONS_VIRT_BASE) &
-                                        TS72XX_OPTIONS_MAX197);
-}
-
-static inline int is_ts9420_installed(void)
-{
-        return !!(__raw_readb(TS72XX_OPTIONS2_VIRT_BASE) &
-                                        TS72XX_OPTIONS2_TS9420);
-}
-#endif
diff --git a/include/asm-arm/arch-ep93xx/uncompress.h b/include/asm-arm/arch-ep93xx/uncompress.h
deleted file mode 100644
index c15274c85d5d..000000000000
--- a/include/asm-arm/arch-ep93xx/uncompress.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ep93xx/uncompress.h
- *
- * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- */
-
-#include <asm/arch/ep93xx-regs.h>
-
-static unsigned char __raw_readb(unsigned int ptr)
-{
-        return *((volatile unsigned char *)ptr);
-}
-
-static unsigned int __raw_readl(unsigned int ptr)
-{
-        return *((volatile unsigned int *)ptr);
-}
-
-static void __raw_writeb(unsigned char value, unsigned int ptr)
-{
-        *((volatile unsigned char *)ptr) = value;
-}
-
-static void __raw_writel(unsigned int value, unsigned int ptr)
-{
-        *((volatile unsigned int *)ptr) = value;
-}
-
-
-#define PHYS_UART1_DATA         0x808c0000
-#define PHYS_UART1_FLAG         0x808c0018
-#define UART1_FLAG_TXFF         0x20
-
-static inline void putc(int c)
-{
-        int i;
-
-        for (i = 0; i < 1000; i++) {
-                /* Transmit fifo not full?  */
-                if (!(__raw_readb(PHYS_UART1_FLAG) & UART1_FLAG_TXFF))
-                        break;
-        }
-
-        __raw_writeb(c, PHYS_UART1_DATA);
-}
-
-static inline void flush(void)
-{
-}
-
-
-/*
- * Some bootloaders don't turn off DMA from the ethernet MAC before
- * jumping to linux, which means that we might end up with bits of RX
- * status and packet data scribbled over the uncompressed kernel image.
- * Work around this by resetting the ethernet MAC before we uncompress.
- */
-#define PHYS_ETH_SELF_CTL               0x80010020
-#define ETH_SELF_CTL_RESET              0x00000001
-
-static void ethernet_reset(void)
-{
-        unsigned int v;
-
-        /* Reset the ethernet MAC.  */
-        v = __raw_readl(PHYS_ETH_SELF_CTL);
-        __raw_writel(v | ETH_SELF_CTL_RESET, PHYS_ETH_SELF_CTL);
-
-        /* Wait for reset to finish.  */
-        while (__raw_readl(PHYS_ETH_SELF_CTL) & ETH_SELF_CTL_RESET)
-                ;
-}
-
-
-static void arch_decomp_setup(void)
-{
-        ethernet_reset();
-}
-
-#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-ep93xx/vmalloc.h b/include/asm-arm/arch-ep93xx/vmalloc.h
deleted file mode 100644
index 205ea6b1cf5e..000000000000
--- a/include/asm-arm/arch-ep93xx/vmalloc.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ep93xx/vmalloc.h
- */
-
-#define VMALLOC_END     0xfe800000
diff --git a/include/asm-arm/arch-h720x/boards.h b/include/asm-arm/arch-h720x/boards.h
deleted file mode 100644
index 8021f81f0742..000000000000
--- a/include/asm-arm/arch-h720x/boards.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * linux/include/asm-arm/arch-h720x/boards.h
- *
- * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
- *           (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
- *
- * This file contains the board specific defines for various devices
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_INCMACH_H
-#error Do not include this file directly. Include asm/hardware.h instead !
-#endif
-
-/* Hynix H7202 developer board specific device defines */
-#ifdef CONFIG_ARCH_H7202
-
-/* FLASH */
-#define FLASH_VIRT              0xd0000000
-#define FLASH_PHYS              0x00000000
-#define FLASH_SIZE              0x02000000
-
-/* onboard LAN controller */
-# define ETH0_PHYS              0x08000000
-
-/* Touch screen defines */
-/* GPIO Port */
-#define PEN_GPIO                GPIO_B_VIRT
-/* Bitmask for pen down interrupt */
-#define PEN_INT_BIT             (1<<7)
-/* Bitmask for pen up interrupt */
-#define PEN_ENA_BIT             (1<<6)
-/* pen up interrupt */
-#define IRQ_PEN                 IRQ_MUX_GPIOB(7)
-
-#endif
-
-/* Hynix H7201 developer board specific device defines */
-#if defined (CONFIG_ARCH_H7201)
-/* ROM DISK SPACE */
-#define ROM_DISK_BASE           0xc1800000
-#define ROM_DISK_START          0x41800000
-#define ROM_DISK_SIZE           0x00700000
-
-/* SRAM DISK SPACE */
-#define SRAM_DISK_BASE          0xf1000000
-#define SRAM_DISK_START         0x04000000
-#define SRAM_DISK_SIZE          0x00400000
-#endif
-
diff --git a/include/asm-arm/arch-h720x/debug-macro.S b/include/asm-arm/arch-h720x/debug-macro.S
deleted file mode 100644
index 82822d362733..000000000000
--- a/include/asm-arm/arch-h720x/debug-macro.S
+++ /dev/null
@@ -1,40 +0,0 @@
-/* linux/include/asm-arm/arch-h720x/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-                .equ    io_virt, IO_BASE
-                .equ    io_phys, IO_START
-
-                .macro  addruart,rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                @ MMU enabled?
-                moveq   \rx, #io_phys          @ physical base address
-                movne   \rx, #io_virt          @ virtual address
-                add     \rx, \rx, #0x00020000   @ UART1
-                .endm
-
-                .macro  senduart,rd,rx
-                str     \rd, [\rx, #0x0]        @ UARTDR
-
-                .endm
-
-                .macro  waituart,rd,rx
-1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
-                tst     \rd, #1 << 5           @ UARTFLGUTXFF - 1 when full
-                bne     1001b
-                .endm
-
-                .macro  busyuart,rd,rx
-1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
-                tst     \rd, #1 << 3           @ UARTFLGUBUSY - 1 when busy
-                bne     1001b
-                .endm
diff --git a/include/asm-arm/arch-h720x/dma.h b/include/asm-arm/arch-h720x/dma.h
deleted file mode 100644
index bfc6636679f7..000000000000
--- a/include/asm-arm/arch-h720x/dma.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * linux/include/asm-arm/arch-h720x/dma.h
- *
- * Architecture DMA routes
- *
- * Copyright (C) 1997.1998 Russell King
- */
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-
-/*
- * This is the maximum DMA address that can be DMAd to.
- * There should not be more than (0xd0000000 - 0xc0000000)
- * bytes of RAM.
- */
-#define MAX_DMA_ADDRESS         0xd0000000
-
-#if defined (CONFIG_CPU_H7201)
-#define MAX_DMA_CHANNELS        3
-#elif defined (CONFIG_CPU_H7202)
-#define MAX_DMA_CHANNELS        4
-#else
-#error processor definition missmatch
-#endif
-
-#endif /* __ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-h720x/entry-macro.S b/include/asm-arm/arch-h720x/entry-macro.S
deleted file mode 100644
index 38dd63ae104e..000000000000
--- a/include/asm-arm/arch-h720x/entry-macro.S
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * include/asm-arm/arch-h720x/entry-macro.S
- *
- * Low-level IRQ helper macros for Hynix HMS720x based platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-#if defined (CONFIG_CPU_H7201) || defined (CONFIG_CPU_H7202)
-                @ we could use the id register on H7202, but this is not
-                @ properly updated when we come back from asm_do_irq
-                @ without a previous return from interrupt
-                @ (see loops below in irq_svc, irq_usr)
-                @ We see unmasked pending ints only, as the masked pending ints
-                @ are not visible here
-
-                mov     \base, #0xf0000000             @ base register
-                orr     \base, \base, #0x24000         @ irqbase
-                ldr     \irqstat, [\base, #0x04]        @ get interrupt status
-#if defined (CONFIG_CPU_H7201)
-                ldr     \tmp, =0x001fffff
-#else
-                mvn     \tmp, #0xc0000000
-#endif
-                and     \irqstat, \irqstat, \tmp        @ mask out unused ints
-                mov     \irqnr, #0
-
-                mov     \tmp, #0xff00
-                orr     \tmp, \tmp, #0xff
-                tst     \irqstat, \tmp
-                addeq   \irqnr, \irqnr, #16
-                moveq   \irqstat, \irqstat, lsr #16
-                tst     \irqstat, #255
-                addeq   \irqnr, \irqnr, #8
-                moveq   \irqstat, \irqstat, lsr #8
-                tst     \irqstat, #15
-                addeq   \irqnr, \irqnr, #4
-                moveq   \irqstat, \irqstat, lsr #4
-                tst     \irqstat, #3
-                addeq   \irqnr, \irqnr, #2
-                moveq   \irqstat, \irqstat, lsr #2
-                tst     \irqstat, #1
-                addeq   \irqnr, \irqnr, #1
-                moveq   \irqstat, \irqstat, lsr #1
-                tst     \irqstat, #1                   @ bit 0 should be set
-                .endm
-
-                .macro  irq_prio_table
-                .endm
-
-#else
-#error hynix processor selection missmatch
-#endif
-
diff --git a/include/asm-arm/arch-h720x/h7201-regs.h b/include/asm-arm/arch-h720x/h7201-regs.h
deleted file mode 100644
index 49d4f6bd3080..000000000000
--- a/include/asm-arm/arch-h720x/h7201-regs.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * linux/include/asm-arm/arch-h720x/h7201-regs.h
- *
- * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
- *           (C) 2003 Thomas Gleixner <tglx@linutronix.de>
- *           (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
- *           (C) 2004 Sascha Hauer    <s.hauer@pengutronix.de>
- *
- * This file contains the hardware definitions of the h720x processors
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Do not add implementations specific defines here. This files contains
- * only defines of the onchip peripherals. Add those defines to boards.h,
- * which is included by this file.
- */
-
-#define SERIAL2_VIRT            (IO_VIRT + 0x50100)
-#define SERIAL3_VIRT            (IO_VIRT + 0x50200)
-
-/*
- * PCMCIA
- */
-#define PCMCIA0_ATT_BASE        0xe5000000
-#define PCMCIA0_ATT_SIZE        0x00200000
-#define PCMCIA0_ATT_START       0x20000000
-#define PCMCIA0_MEM_BASE        0xe5200000
-#define PCMCIA0_MEM_SIZE        0x00200000
-#define PCMCIA0_MEM_START       0x24000000
-#define PCMCIA0_IO_BASE         0xe5400000
-#define PCMCIA0_IO_SIZE         0x00200000
-#define PCMCIA0_IO_START        0x28000000
-
-#define PCMCIA1_ATT_BASE        0xe5600000
-#define PCMCIA1_ATT_SIZE        0x00200000
-#define PCMCIA1_ATT_START       0x30000000
-#define PCMCIA1_MEM_BASE        0xe5800000
-#define PCMCIA1_MEM_SIZE        0x00200000
-#define PCMCIA1_MEM_START       0x34000000
-#define PCMCIA1_IO_BASE         0xe5a00000
-#define PCMCIA1_IO_SIZE         0x00200000
-#define PCMCIA1_IO_START        0x38000000
-
-#define PRIME3C_BASE            0xf0050000
-#define PRIME3C_SIZE            0x00001000
-#define PRIME3C_START           0x10000000
-
-/* VGA Controller */
-#define VGA_RAMBASE             0x50
-#define VGA_TIMING0             0x60
-#define VGA_TIMING1             0x64
-#define VGA_TIMING2             0x68
-#define VGA_TIMING3             0x6c
-
-#define LCD_CTRL_VGA_ENABLE     0x00000100
-#define LCD_CTRL_VGA_BPP_MASK   0x00000600
-#define LCD_CTRL_VGA_4BPP       0x00000000
-#define LCD_CTRL_VGA_8BPP       0x00000200
-#define LCD_CTRL_VGA_16BPP      0x00000300
-#define LCD_CTRL_SHARE_DMA      0x00000800
-#define LCD_CTRL_VDE            0x00100000
-#define LCD_CTRL_LPE            0x00400000      /* LCD Power enable */
-#define LCD_CTRL_BLE            0x00800000      /* LCD backlight enable */
-
-#define VGA_PALETTE_BASE        (IO_VIRT + 0x10800)
diff --git a/include/asm-arm/arch-h720x/h7202-regs.h b/include/asm-arm/arch-h720x/h7202-regs.h
deleted file mode 100644
index 43d8ba8a6013..000000000000
--- a/include/asm-arm/arch-h720x/h7202-regs.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * linux/include/asm-arm/arch-h720x/h7202-regs.h
- *
- * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
- *           (C) 2003 Thomas Gleixner <tglx@linutronix.de>
- *           (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
- *           (C) 2004 Sascha Hauer    <s.hauer@pengutronix.de>
- *
- * This file contains the hardware definitions of the h720x processors
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Do not add implementations specific defines here. This files contains
- * only defines of the onchip peripherals. Add those defines to boards.h,
- * which is included by this file.
- */
-
-#define SERIAL2_OFS             0x2d000
-#define SERIAL2_BASE            (IO_PHYS + SERIAL2_OFS)
-#define SERIAL2_VIRT            (IO_VIRT + SERIAL2_OFS)
-#define SERIAL3_OFS             0x2e000
-#define SERIAL3_BASE            (IO_PHYS + SERIAL3_OFS)
-#define SERIAL3_VIRT            (IO_VIRT + SERIAL3_OFS)
-
-/* Matrix Keyboard Controller */
-#define KBD_VIRT                (IO_VIRT + 0x22000)
-#define KBD_KBCR                0x00
-#define KBD_KBSC                0x04
-#define KBD_KBTR                0x08
-#define KBD_KBVR0               0x0C
-#define KBD_KBVR1               0x10
-#define KBD_KBSR                0x18
-
-#define KBD_KBCR_SCANENABLE     (1 << 7)
-#define KBD_KBCR_NPOWERDOWN     (1 << 2)
-#define KBD_KBCR_CLKSEL_MASK    (3)
-#define KBD_KBCR_CLKSEL_PCLK2   0x0
-#define KBD_KBCR_CLKSEL_PCLK128 0x1
-#define KBD_KBCR_CLKSEL_PCLK256 0x2
-#define KBD_KBCR_CLKSEL_PCLK512 0x3
-
-#define KBD_KBSR_INTR           (1 << 0)
-#define KBD_KBSR_WAKEUP         (1 << 1)
-
-/* USB device controller */
-
-#define USBD_BASE               (IO_VIRT + 0x12000)
-#define USBD_LENGTH             0x3C
-
-#define USBD_GCTRL              0x00
-#define USBD_EPCTRL             0x04
-#define USBD_INTMASK            0x08
-#define USBD_INTSTAT            0x0C
-#define USBD_PWR                0x10
-#define USBD_DMARXTX            0x14
-#define USBD_DEVID              0x18
-#define USBD_DEVCLASS           0x1C
-#define USBD_INTCLASS           0x20
-#define USBD_SETUP0             0x24
-#define USBD_SETUP1             0x28
-#define USBD_ENDP0RD            0x2C
-#define USBD_ENDP0WT            0x30
-#define USBD_ENDP1RD            0x34
-#define USBD_ENDP2WT            0x38
-
-/* PS/2 port */
-#define PSDATA 0x00
-#define PSSTAT 0x04
-#define PSSTAT_TXEMPTY (1<<0)
-#define PSSTAT_TXBUSY (1<<1)
-#define PSSTAT_RXFULL (1<<2)
-#define PSSTAT_RXBUSY (1<<3)
-#define PSSTAT_CLKIN (1<<4)
-#define PSSTAT_DATAIN (1<<5)
-#define PSSTAT_PARITY (1<<6)
-
-#define PSCONF 0x08
-#define PSCONF_ENABLE (1<<0)
-#define PSCONF_TXINTEN (1<<2)
-#define PSCONF_RXINTEN (1<<3)
-#define PSCONF_FORCECLKLOW (1<<4)
-#define PSCONF_FORCEDATLOW (1<<5)
-#define PSCONF_LCE (1<<6)
-
-#define PSINTR 0x0C
-#define PSINTR_TXINT (1<<0)
-#define PSINTR_RXINT (1<<1)
-#define PSINTR_PAR (1<<2)
-#define PSINTR_RXTO (1<<3)
-#define PSINTR_TXTO (1<<4)
-
-#define PSTDLO 0x10 /* clk low before start transmission */
-#define PSTPRI 0x14 /* PRI clock */
-#define PSTXMT 0x18 /* maximum transmission time */
-#define PSTREC 0x20 /* maximum receive time */
-#define PSPWDN 0x3c
-
-/* ADC converter */
-#define ADC_BASE                (IO_VIRT + 0x29000)
-#define ADC_CR                  0x00
-#define ADC_TSCTRL              0x04
-#define ADC_BT_CTRL             0x08
-#define ADC_MC_CTRL             0x0C
-#define ADC_STATUS              0x10
-
-/* ADC control register bits */
-#define ADC_CR_PW_CTRL          0x80
-#define ADC_CR_DIRECTC          0x04
-#define ADC_CR_CONTIME_NO       0x00
-#define ADC_CR_CONTIME_2        0x04
-#define ADC_CR_CONTIME_4        0x08
-#define ADC_CR_CONTIME_ADE      0x0c
-#define ADC_CR_LONGCALTIME      0x01
-
-/* ADC touch panel register bits */
-#define ADC_TSCTRL_ENABLE       0x80
-#define ADC_TSCTRL_INTR         0x40
-#define ADC_TSCTRL_SWBYPSS      0x20
-#define ADC_TSCTRL_SWINVT       0x10
-#define ADC_TSCTRL_S400         0x03
-#define ADC_TSCTRL_S200         0x02
-#define ADC_TSCTRL_S100         0x01
-#define ADC_TSCTRL_S50          0x00
-
-/* ADC Interrupt Status Register bits */
-#define ADC_STATUS_TS_BIT       0x80
-#define ADC_STATUS_MBT_BIT      0x40
-#define ADC_STATUS_BBT_BIT      0x20
-#define ADC_STATUS_MIC_BIT      0x10
-
-/* Touch data registers */
-#define ADC_TS_X0X1             0x30
-#define ADC_TS_X2X3             0x34
-#define ADC_TS_Y0Y1             0x38
-#define ADC_TS_Y2Y3             0x3c
-#define ADC_TS_X4X5             0x40
-#define ADC_TS_X6X7             0x44
-#define ADC_TS_Y4Y5             0x48
-#define ADC_TS_Y6Y7             0x50
-
-/* battery data */
-#define ADC_MB_DATA             0x54
-#define ADC_BB_DATA             0x58
-
-/* Sound data register */
-#define ADC_SD_DAT0             0x60
-#define ADC_SD_DAT1             0x64
-#define ADC_SD_DAT2             0x68
-#define ADC_SD_DAT3             0x6c
-#define ADC_SD_DAT4             0x70
-#define ADC_SD_DAT5             0x74
-#define ADC_SD_DAT6             0x78
-#define ADC_SD_DAT7             0x7c
diff --git a/include/asm-arm/arch-h720x/hardware.h b/include/asm-arm/arch-h720x/hardware.h
deleted file mode 100644
index dfb778906a9f..000000000000
--- a/include/asm-arm/arch-h720x/hardware.h
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- * linux/include/asm-arm/arch-h720x/hardware.h
- *
- * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
- *           (C) 2003 Thomas Gleixner <tglx@linutronix.de>
- *           (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
- *
- * This file contains the hardware definitions of the h720x processors
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Do not add implementations specific defines here. This files contains
- * only defines of the onchip peripherals. Add those defines to boards.h,
- * which is included by this file.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#define IOCLK (3686400L)
-
-/* Onchip peripherals */
-
-#define IO_VIRT                 0xf0000000      /* IO peripherals */
-#define IO_PHYS                 0x80000000
-#define IO_SIZE                 0x00050000
-
-#ifdef CONFIG_CPU_H7202
-#include "h7202-regs.h"
-#elif defined CONFIG_CPU_H7201
-#include "h7201-regs.h"
-#else
-#error machine definition mismatch
-#endif
-
-/* Macro to access the CPU IO */
-#define CPU_IO(x) (*(volatile u32*)(x))
-
-/* Macro to access general purpose regs (base, offset) */
-#define CPU_REG(x,y) CPU_IO(x+y)
-
-/* Macro to access irq related regs */
-#define IRQ_REG(x) CPU_REG(IRQC_VIRT,x)
-
-/* CPU registers */
-/* general purpose I/O */
-#define GPIO_VIRT(x)            (IO_VIRT + 0x23000 + ((x)<<5))
-#define GPIO_A_VIRT             (GPIO_VIRT(0))
-#define GPIO_B_VIRT             (GPIO_VIRT(1))
-#define GPIO_C_VIRT             (GPIO_VIRT(2))
-#define GPIO_D_VIRT             (GPIO_VIRT(3))
-#define GPIO_E_VIRT             (GPIO_VIRT(4))
-#define GPIO_AMULSEL            (GPIO_VIRT(0) + 0xA4)
-
-#define AMULSEL_USIN2   (1<<5)
-#define AMULSEL_USOUT2  (1<<6)
-#define AMULSEL_USIN3   (1<<13)
-#define AMULSEL_USOUT3  (1<<14)
-#define AMULSEL_IRDIN   (1<<15)
-#define AMULSEL_IRDOUT  (1<<7)
-
-/* Register offsets general purpose I/O */
-#define GPIO_DATA               0x00
-#define GPIO_DIR                0x04
-#define GPIO_MASK               0x08
-#define GPIO_STAT               0x0C
-#define GPIO_EDGE               0x10
-#define GPIO_CLR                0x14
-#define GPIO_POL                0x18
-#define GPIO_EN                 0x1C
-
-/*interrupt controller */
-#define IRQC_VIRT               (IO_VIRT + 0x24000)
-/* register offset interrupt controller */
-#define IRQC_IER                0x00
-#define IRQC_ISR                0x04
-
-/* timer unit */
-#define TIMER_VIRT              (IO_VIRT + 0x25000)
-/* Register offsets timer unit */
-#define TM0_PERIOD              0x00
-#define TM0_COUNT               0x08
-#define TM0_CTRL                0x10
-#define TM1_PERIOD              0x20
-#define TM1_COUNT               0x28
-#define TM1_CTRL                0x30
-#define TM2_PERIOD              0x40
-#define TM2_COUNT               0x48
-#define TM2_CTRL                0x50
-#define TIMER_TOPCTRL           0x60
-#define TIMER_TOPSTAT           0x64
-#define T64_COUNTL              0x80
-#define T64_COUNTH              0x84
-#define T64_CTRL                0x88
-#define T64_BASEL               0x94
-#define T64_BASEH               0x98
-/* Bitmaks timer unit TOPSTAT reg */
-#define TSTAT_T0INT             0x1
-#define TSTAT_T1INT             0x2
-#define TSTAT_T2INT             0x4
-#define TSTAT_T3INT             0x8
-/* Bit description of TMx_CTRL register */
-#define TM_START                0x1
-#define TM_REPEAT               0x2
-#define TM_RESET                0x4
-/* Bit description of TIMER_CTRL register */
-#define ENABLE_TM0_INTR         0x1
-#define ENABLE_TM1_INTR         0x2
-#define ENABLE_TM2_INTR         0x4
-#define TIMER_ENABLE_BIT        0x8
-#define ENABLE_TIMER64          0x10
-#define ENABLE_TIMER64_INT      0x20
-
-/* PMU & PLL */
-#define PMU_BASE                (IO_VIRT + 0x1000)
-#define PMU_MODE                0x00
-#define PMU_STAT                0x20
-#define PMU_PLL_CTRL            0x28
-
-/* PMU Mode bits */
-#define PMU_MODE_SLOW           0x00
-#define PMU_MODE_RUN            0x01
-#define PMU_MODE_IDLE           0x02
-#define PMU_MODE_SLEEP          0x03
-#define PMU_MODE_INIT           0x04
-#define PMU_MODE_DEEPSLEEP      0x07
-#define PMU_MODE_WAKEUP         0x08
-
-/* PMU ... */
-#define PLL_2_EN                0x8000
-#define PLL_1_EN                0x4000
-#define PLL_3_MUTE              0x0080
-
-/* Control bits for PMU/ PLL */
-#define PMU_WARMRESET           0x00010000
-#define PLL_CTRL_MASK23         0x000080ff
-
-/* LCD Controller */
-#define LCD_BASE                (IO_VIRT + 0x10000)
-#define LCD_CTRL                0x00
-#define LCD_STATUS              0x04
-#define LCD_STATUS_M            0x08
-#define LCD_INTERRUPT           0x0C
-#define LCD_DBAR                0x10
-#define LCD_DCAR                0x14
-#define LCD_TIMING0             0x20
-#define LCD_TIMING1             0x24
-#define LCD_TIMING2             0x28
-#define LCD_TEST                0x40
-
-/* LCD Control Bits */
-#define LCD_CTRL_LCD_ENABLE     0x00000001
-/* Bits per pixel */
-#define LCD_CTRL_LCD_BPP_MASK   0x00000006
-#define LCD_CTRL_LCD_4BPP       0x00000000
-#define LCD_CTRL_LCD_8BPP       0x00000002
-#define LCD_CTRL_LCD_16BPP      0x00000004
-#define LCD_CTRL_LCD_BW         0x00000008
-#define LCD_CTRL_LCD_TFT        0x00000010
-#define LCD_CTRL_BGR            0x00001000
-#define LCD_CTRL_LCD_VCOMP      0x00080000
-#define LCD_CTRL_LCD_MONO8      0x00200000
-#define LCD_CTRL_LCD_PWR        0x00400000
-#define LCD_CTRL_LCD_BLE        0x00800000
-#define LCD_CTRL_LDBUSEN        0x01000000
-
-/* Palette */
-#define LCD_PALETTE_BASE        (IO_VIRT + 0x10400)
-
-/* Serial ports */
-#define SERIAL0_OFS             0x20000
-#define SERIAL0_VIRT            (IO_VIRT + SERIAL0_OFS)
-#define SERIAL0_BASE            (IO_PHYS + SERIAL0_OFS)
-
-#define SERIAL1_OFS             0x21000
-#define SERIAL1_VIRT            (IO_VIRT + SERIAL1_OFS)
-#define SERIAL1_BASE            (IO_PHYS + SERIAL1_OFS)
-
-#define SERIAL_ENABLE           0x30
-#define SERIAL_ENABLE_EN        (1<<0)
-
-/* General defines to pacify gcc */
-#define PCIO_BASE               (0)     /* for inb, outb and friends */
-#define PCIO_VIRT               PCIO_BASE
-
-#define __ASM_ARCH_HARDWARE_INCMACH_H
-#include "boards.h"
-#undef __ASM_ARCH_HARDWARE_INCMACH_H
-
-#endif                          /* __ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-h720x/io.h b/include/asm-arm/arch-h720x/io.h
deleted file mode 100644
index 68814828c9a7..000000000000
--- a/include/asm-arm/arch-h720x/io.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * linux/include/asm-arm/arch-h720x/io.h
- *
- * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
- *
- * Changelog:
- *
- *  09-19-2001  JJKIM
- *              Created from linux/include/asm-arm/arch-l7200/io.h
- *
- *  03-27-2003  Robert Schwebel <r.schwebel@pengutronix.de>:
- *              re-unified header files for h720x
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#include <asm/arch/hardware.h>
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-#define __io(a)         ((void __iomem *)(a))
-#define __mem_pci(a)    (a)
-
-#endif
diff --git a/include/asm-arm/arch-h720x/irqs.h b/include/asm-arm/arch-h720x/irqs.h
deleted file mode 100644
index 8244413988be..000000000000
--- a/include/asm-arm/arch-h720x/irqs.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * linux/include/asm-arm/arch-h720x/irqs.h
- *
- * Copyright (C) 2000 Jungjun Kim
- *           (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
- *           (C) 2003 Thomas Gleixner <tglx@linutronix.de>
- *
- */
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H
-
-#if defined (CONFIG_CPU_H7201)
-
-#define IRQ_PMU         0               /* 0x000001 */
-#define IRQ_DMA         1               /* 0x000002 */
-#define IRQ_LCD         2               /* 0x000004 */
-#define IRQ_VGA         3               /* 0x000008 */
-#define IRQ_PCMCIA1     4               /* 0x000010 */
-#define IRQ_PCMCIA2     5               /* 0x000020 */
-#define IRQ_AFE         6               /* 0x000040 */
-#define IRQ_AIC         7               /* 0x000080 */
-#define IRQ_KEYBOARD    8               /* 0x000100 */
-#define IRQ_TIMER0      9               /* 0x000200 */
-#define IRQ_RTC         10              /* 0x000400 */
-#define IRQ_SOUND       11              /* 0x000800 */
-#define IRQ_USB         12              /* 0x001000 */
-#define IRQ_IrDA        13              /* 0x002000 */
-#define IRQ_UART0       14              /* 0x004000 */
-#define IRQ_UART1       15              /* 0x008000 */
-#define IRQ_SPI         16              /* 0x010000 */
-#define IRQ_GPIOA       17              /* 0x020000 */
-#define IRQ_GPIOB       18              /* 0x040000 */
-#define IRQ_GPIOC       19              /* 0x080000 */
-#define IRQ_GPIOD       20              /* 0x100000 */
-#define IRQ_CommRX      21              /* 0x200000 */
-#define IRQ_CommTX      22              /* 0x400000 */
-#define IRQ_Soft        23              /* 0x800000 */
-
-#define NR_GLBL_IRQS    24
-
-#define IRQ_CHAINED_GPIOA(x)  (NR_GLBL_IRQS + x)
-#define IRQ_CHAINED_GPIOB(x)  (IRQ_CHAINED_GPIOA(32) + x)
-#define IRQ_CHAINED_GPIOC(x)  (IRQ_CHAINED_GPIOB(32) + x)
-#define IRQ_CHAINED_GPIOD(x)  (IRQ_CHAINED_GPIOC(32) + x)
-#define NR_IRQS               IRQ_CHAINED_GPIOD(32)
-
-/* Enable mask for multiplexed interrupts */
-#define IRQ_ENA_MUX     (1<<IRQ_GPIOA) | (1<<IRQ_GPIOB) \
-                        | (1<<IRQ_GPIOC) | (1<<IRQ_GPIOD)
-
-
-#elif defined (CONFIG_CPU_H7202)
-
-#define IRQ_PMU         0               /* 0x00000001 */
-#define IRQ_DMA         1               /* 0x00000002 */
-#define IRQ_LCD         2               /* 0x00000004 */
-#define IRQ_SOUND       3               /* 0x00000008 */
-#define IRQ_I2S         4               /* 0x00000010 */
-#define IRQ_USB         5               /* 0x00000020 */
-#define IRQ_MMC         6               /* 0x00000040 */
-#define IRQ_RTC         7               /* 0x00000080 */
-#define IRQ_UART0       8               /* 0x00000100 */
-#define IRQ_UART1       9               /* 0x00000200 */
-#define IRQ_UART2       10              /* 0x00000400 */
-#define IRQ_UART3       11              /* 0x00000800 */
-#define IRQ_KBD         12              /* 0x00001000 */
-#define IRQ_PS2         13              /* 0x00002000 */
-#define IRQ_AIC         14              /* 0x00004000 */
-#define IRQ_TIMER0      15              /* 0x00008000 */
-#define IRQ_TIMERX      16              /* 0x00010000 */
-#define IRQ_WDT         17              /* 0x00020000 */
-#define IRQ_CAN0        18              /* 0x00040000 */
-#define IRQ_CAN1        19              /* 0x00080000 */
-#define IRQ_EXT0        20              /* 0x00100000 */
-#define IRQ_EXT1        21              /* 0x00200000 */
-#define IRQ_GPIOA       22              /* 0x00400000 */
-#define IRQ_GPIOB       23              /* 0x00800000 */
-#define IRQ_GPIOC       24              /* 0x01000000 */
-#define IRQ_GPIOD       25              /* 0x02000000 */
-#define IRQ_GPIOE       26              /* 0x04000000 */
-#define IRQ_COMMRX      27              /* 0x08000000 */
-#define IRQ_COMMTX      28              /* 0x10000000 */
-#define IRQ_SMC         29              /* 0x20000000 */
-#define IRQ_Soft        30              /* 0x40000000 */
-#define IRQ_RESERVED1   31              /* 0x80000000 */
-#define NR_GLBL_IRQS    32
-
-#define NR_TIMERX_IRQS  3
-
-#define IRQ_CHAINED_GPIOA(x)  (NR_GLBL_IRQS + x)
-#define IRQ_CHAINED_GPIOB(x)  (IRQ_CHAINED_GPIOA(32) + x)
-#define IRQ_CHAINED_GPIOC(x)  (IRQ_CHAINED_GPIOB(32) + x)
-#define IRQ_CHAINED_GPIOD(x)  (IRQ_CHAINED_GPIOC(32) + x)
-#define IRQ_CHAINED_GPIOE(x)  (IRQ_CHAINED_GPIOD(32) + x)
-#define IRQ_CHAINED_TIMERX(x) (IRQ_CHAINED_GPIOE(32) + x)
-#define IRQ_TIMER1            (IRQ_CHAINED_TIMERX(0))
-#define IRQ_TIMER2            (IRQ_CHAINED_TIMERX(1))
-#define IRQ_TIMER64B          (IRQ_CHAINED_TIMERX(2))
-
-#define NR_IRQS         (IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS))
-
-/* Enable mask for multiplexed interrupts */
-#define IRQ_ENA_MUX     (1<<IRQ_TIMERX) | (1<<IRQ_GPIOA) | (1<<IRQ_GPIOB) | \
-                        (1<<IRQ_GPIOC)  | (1<<IRQ_GPIOD) | (1<<IRQ_GPIOE) | \
-                        (1<<IRQ_TIMERX)
-
-#else
-#error cpu definition mismatch
-#endif
-
-/* decode irq number to register number */
-#define IRQ_TO_REGNO(irq) ((irq - NR_GLBL_IRQS) >> 5)
-#define IRQ_TO_BIT(irq) (1 << ((irq - NR_GLBL_IRQS) % 32))
-
-#endif
diff --git a/include/asm-arm/arch-h720x/memory.h b/include/asm-arm/arch-h720x/memory.h
deleted file mode 100644
index 53e923dba76e..000000000000
--- a/include/asm-arm/arch-h720x/memory.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * linux/include/asm-arm/arch-h720x/memory.h
- *
- * Copyright (c) 2000 Jungjun Kim
- *
- */
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-/*
- * Page offset:
- *    ( 0xc0000000UL )
- */
-#define PHYS_OFFSET     UL(0x40000000)
-
-/*
- * Virtual view <-> DMA view memory address translations
- * virt_to_bus: Used to translate the virtual address to an
- *              address suitable to be passed to set_dma_addr
- * bus_to_virt: Used to convert an address for DMA operations
- *              to an address that the kernel can use.
- *
- * There is something to do here later !, Mar 2000, Jungjun Kim
- */
-
-#define __virt_to_bus(x)        __virt_to_phys(x)
-#define __bus_to_virt(x)        __phys_to_virt(x)
-
-#endif
diff --git a/include/asm-arm/arch-h720x/system.h b/include/asm-arm/arch-h720x/system.h
deleted file mode 100644
index ddba93760b42..000000000000
--- a/include/asm-arm/arch-h720x/system.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * linux/include/asm-arm/arch-h720x/system.h
- *
- * Copyright (C) 2001-2002 Jungjun Kim, Hynix Semiconductor Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- * linux/include/asm-arm/arch-h720x/system.h
- *
- */
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-#include <asm/arch/hardware.h>
-
-static void arch_idle(void)
-{
-        CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_IDLE;
-        nop();
-        nop();
-        CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_RUN;
-        nop();
-        nop();
-}
-
-
-static __inline__ void arch_reset(char mode)
-{
-        CPU_REG (PMU_BASE, PMU_STAT) |= PMU_WARMRESET;
-}
-
-#endif
diff --git a/include/asm-arm/arch-h720x/timex.h b/include/asm-arm/arch-h720x/timex.h
deleted file mode 100644
index 48a391c4080f..000000000000
--- a/include/asm-arm/arch-h720x/timex.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * linux/include/asm-arm/arch-h720x/timex.h
- * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_TIMEX
-#define __ASM_ARCH_TIMEX
-
-#define CLOCK_TICK_RATE         3686400
-
-#endif
diff --git a/include/asm-arm/arch-h720x/uncompress.h b/include/asm-arm/arch-h720x/uncompress.h
deleted file mode 100644
index 61584cd5f425..000000000000
--- a/include/asm-arm/arch-h720x/uncompress.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * linux/include/asm-arm/arch-h720x/uncompress.h
- *
- * Copyright (C) 2001-2002 Jungjun Kim
- */
-
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-
-#include <asm/arch/hardware.h>
-
-#define LSR     0x14
-#define TEMPTY  0x40
-
-static inline void putc(int c)
-{
-        volatile unsigned char *p = (volatile unsigned char *)(IO_PHYS+0x20000);
-
-        /* wait until transmit buffer is empty */
-        while((p[LSR] & TEMPTY) == 0x0)
-                barrier();
-
-        /* write next character */
-        *p = c;
-}
-
-static inline void flush(void)
-{
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
-
-#endif
diff --git a/include/asm-arm/arch-h720x/vmalloc.h b/include/asm-arm/arch-h720x/vmalloc.h
deleted file mode 100644
index b4693cb821ef..000000000000
--- a/include/asm-arm/arch-h720x/vmalloc.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * linux/include/asm-arm/arch-h720x/vmalloc.h
- */
-
-#ifndef __ARCH_ARM_VMALLOC_H
-#define __ARCH_ARM_VMALLOC_H
-
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
-
-#endif
diff --git a/include/asm-arm/arch-imx/debug-macro.S b/include/asm-arm/arch-imx/debug-macro.S
deleted file mode 100644
index c611871643a2..000000000000
--- a/include/asm-arm/arch-imx/debug-macro.S
+++ /dev/null
@@ -1,34 +0,0 @@
-/* linux/include/asm-arm/arch-imx/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-                .macro  addruart,rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx, #0x00000000        @ physical
-                movne   \rx, #0xe0000000        @ virtual
-                orreq   \rx, \rx, #0x00200000   @ physical
-                orr     \rx, \rx, #0x00006000   @ UART1 offset
-                .endm
-
-                .macro  senduart,rd,rx
-                str     \rd, [\rx, #0x40]       @ TXDATA
-                .endm
-
-                .macro  waituart,rd,rx
-                .endm
-
-                .macro  busyuart,rd,rx
-1002:           ldr     \rd, [\rx, #0x98]       @ SR2
-                tst     \rd, #1 << 3            @ TXDC
-                beq     1002b                   @ wait until transmit done
-                .endm
diff --git a/include/asm-arm/arch-imx/entry-macro.S b/include/asm-arm/arch-imx/entry-macro.S
deleted file mode 100644
index 5dc0f307c1bb..000000000000
--- a/include/asm-arm/arch-imx/entry-macro.S
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * include/asm-arm/arch-imx/entry-macro.S
- *
- * Low-level IRQ helper macros for iMX-based platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <asm/arch/hardware.h>
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
-#define AITC_NIVECSR   0x40
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \base, =IO_ADDRESS(IMX_AITC_BASE)
-                @ Load offset & priority of the highest priority
-                @ interrupt pending.
-                ldr     \irqstat, [\base, #AITC_NIVECSR]
-                @ Shift off the priority leaving the offset or
-                @ "interrupt number", use arithmetic shift to
-                @ transform illegal source (0xffff) as -1
-                mov     \irqnr, \irqstat, asr #16
-                adds    \tmp, \irqnr, #1
-                .endm
diff --git a/include/asm-arm/arch-imx/gpio.h b/include/asm-arm/arch-imx/gpio.h
deleted file mode 100644
index 486023263f32..000000000000
--- a/include/asm-arm/arch-imx/gpio.h
+++ /dev/null
@@ -1,102 +0,0 @@
-#ifndef _IMX_GPIO_H
-
-#include <asm/arch/imx-regs.h>
-
-#define IMX_GPIO_ALLOC_MODE_NORMAL      0
-#define IMX_GPIO_ALLOC_MODE_NO_ALLOC    1
-#define IMX_GPIO_ALLOC_MODE_TRY_ALLOC   2
-#define IMX_GPIO_ALLOC_MODE_ALLOC_ONLY  4
-#define IMX_GPIO_ALLOC_MODE_RELEASE     8
-
-extern int imx_gpio_request(unsigned gpio, const char *label);
-
-extern void imx_gpio_free(unsigned gpio);
-
-extern int imx_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
-                                        int alloc_mode, const char *label);
-
-extern int imx_gpio_direction_input(unsigned gpio);
-
-extern int imx_gpio_direction_output(unsigned gpio, int value);
-
-extern void __imx_gpio_set_value(unsigned gpio, int value);
-
-static inline int imx_gpio_get_value(unsigned gpio)
-{
-        return SSR(gpio >> GPIO_PORT_SHIFT) & (1 << (gpio & GPIO_PIN_MASK));
-}
-
-static inline void imx_gpio_set_value_inline(unsigned gpio, int value)
-{
-        unsigned long flags;
-
-        raw_local_irq_save(flags);
-        if(value)
-                DR(gpio >> GPIO_PORT_SHIFT) |= (1 << (gpio & GPIO_PIN_MASK));
-        else
-                DR(gpio >> GPIO_PORT_SHIFT) &= ~(1 << (gpio & GPIO_PIN_MASK));
-        raw_local_irq_restore(flags);
-}
-
-static inline void imx_gpio_set_value(unsigned gpio, int value)
-{
-        if(__builtin_constant_p(gpio))
-                imx_gpio_set_value_inline(gpio, value);
-        else
-                __imx_gpio_set_value(gpio, value);
-}
-
-extern int imx_gpio_to_irq(unsigned gpio);
-
-extern int imx_irq_to_gpio(unsigned irq);
-
-/*-------------------------------------------------------------------------*/
-
-/* Wrappers for "new style" GPIO calls. These calls i.MX specific versions
- * to allow future extension of GPIO logic.
- */
-
-static inline int gpio_request(unsigned gpio, const char *label)
-{
-        return imx_gpio_request(gpio, label);
-}
-
-static inline void gpio_free(unsigned gpio)
-{
-        imx_gpio_free(gpio);
-}
-
-static inline  int gpio_direction_input(unsigned gpio)
-{
-        return imx_gpio_direction_input(gpio);
-}
-
-static inline int gpio_direction_output(unsigned gpio, int value)
-{
-        return imx_gpio_direction_output(gpio, value);
-}
-
-static inline int gpio_get_value(unsigned gpio)
-{
-        return imx_gpio_get_value(gpio);
-}
-
-static inline void gpio_set_value(unsigned gpio, int value)
-{
-        imx_gpio_set_value(gpio, value);
-}
-
-#include <asm-generic/gpio.h>           /* cansleep wrappers */
-
-static inline int gpio_to_irq(unsigned gpio)
-{
-        return imx_gpio_to_irq(gpio);
-}
-
-static inline int irq_to_gpio(unsigned irq)
-{
-        return imx_irq_to_gpio(irq);
-}
-
-
-#endif
diff --git a/include/asm-arm/arch-imx/hardware.h b/include/asm-arm/arch-imx/hardware.h
deleted file mode 100644
index 6542ca5e8c33..000000000000
--- a/include/asm-arm/arch-imx/hardware.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-imx/hardware.h
- *
- *  Copyright (C) 1999 ARM Limited.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <asm/sizes.h>
-#include "imx-regs.h"
-
-#ifndef __ASSEMBLY__
-# define __REG(x)       (*((volatile u32 *)IO_ADDRESS(x)))
-
-# define __REG2(x,y)        (*(volatile u32 *)((u32)&__REG(x) + (y)))
-#endif
-
-/*
- * Memory map
- */
-
-#define IMX_IO_PHYS             0x00200000
-#define IMX_IO_SIZE             0x00100000
-#define IMX_IO_BASE             0xe0000000
-
-#define IMX_CS0_PHYS            0x10000000
-#define IMX_CS0_SIZE            0x02000000
-#define IMX_CS0_VIRT            0xe8000000
-
-#define IMX_CS1_PHYS            0x12000000
-#define IMX_CS1_SIZE            0x01000000
-#define IMX_CS1_VIRT            0xea000000
-
-#define IMX_CS2_PHYS            0x13000000
-#define IMX_CS2_SIZE            0x01000000
-#define IMX_CS2_VIRT            0xeb000000
-
-#define IMX_CS3_PHYS            0x14000000
-#define IMX_CS3_SIZE            0x01000000
-#define IMX_CS3_VIRT            0xec000000
-
-#define IMX_CS4_PHYS            0x15000000
-#define IMX_CS4_SIZE            0x01000000
-#define IMX_CS4_VIRT            0xed000000
-
-#define IMX_CS5_PHYS            0x16000000
-#define IMX_CS5_SIZE            0x01000000
-#define IMX_CS5_VIRT            0xee000000
-
-#define IMX_FB_VIRT             0xF1000000
-#define IMX_FB_SIZE             (256*1024)
-
-/* macro to get at IO space when running virtually */
-#define IO_ADDRESS(x) ((x) | IMX_IO_BASE)
-
-#ifndef __ASSEMBLY__
-/*
- * Handy routine to set GPIO functions
- */
-extern void imx_gpio_mode( int gpio_mode );
-
-#endif
-
-#define MAXIRQNUM                       62
-#define MAXFIQNUM                       62
-#define MAXSWINUM                       62
-
-/*
- * Use SDRAM for memory
- */
-#define MEM_SIZE                0x01000000
-
-#ifdef CONFIG_ARCH_MX1ADS
-#include "mx1ads.h"
-#endif
-
-#endif
diff --git a/include/asm-arm/arch-imx/io.h b/include/asm-arm/arch-imx/io.h
deleted file mode 100644
index 1a1d9bb88631..000000000000
--- a/include/asm-arm/arch-imx/io.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-imxads/io.h
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#include <asm/arch/hardware.h>
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-#define __io(a)         ((void __iomem *)(a))
-#define __mem_pci(a)    (a)
-
-#endif
diff --git a/include/asm-arm/arch-imx/irqs.h b/include/asm-arm/arch-imx/irqs.h
deleted file mode 100644
index 238197cfb9d9..000000000000
--- a/include/asm-arm/arch-imx/irqs.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-imxads/irqs.h
- *
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __ARM_IRQS_H__
-#define __ARM_IRQS_H__
-
-/* Use the imx definitions */
-#include <asm/arch/hardware.h>
-
-/*
- *  IMX Interrupt numbers
- *
- */
-#define INT_SOFTINT                 0
-#define CSI_INT                     6
-#define DSPA_MAC_INT                7
-#define DSPA_INT                    8
-#define COMP_INT                    9
-#define MSHC_XINT                   10
-#define GPIO_INT_PORTA              11
-#define GPIO_INT_PORTB              12
-#define GPIO_INT_PORTC              13
-#define LCDC_INT                    14
-#define SIM_INT                     15
-#define SIM_DATA_INT                16
-#define RTC_INT                     17
-#define RTC_SAMINT                  18
-#define UART2_MINT_PFERR            19
-#define UART2_MINT_RTS              20
-#define UART2_MINT_DTR              21
-#define UART2_MINT_UARTC            22
-#define UART2_MINT_TX               23
-#define UART2_MINT_RX               24
-#define UART1_MINT_PFERR            25
-#define UART1_MINT_RTS              26
-#define UART1_MINT_DTR              27
-#define UART1_MINT_UARTC            28
-#define UART1_MINT_TX               29
-#define UART1_MINT_RX               30
-#define VOICE_DAC_INT               31
-#define VOICE_ADC_INT               32
-#define PEN_DATA_INT                33
-#define PWM_INT                     34
-#define SDHC_INT                    35
-#define I2C_INT                     39
-#define CSPI_INT                    41
-#define SSI_TX_INT                  42
-#define SSI_TX_ERR_INT              43
-#define SSI_RX_INT                  44
-#define SSI_RX_ERR_INT              45
-#define TOUCH_INT                   46
-#define USBD_INT0                   47
-#define USBD_INT1                   48
-#define USBD_INT2                   49
-#define USBD_INT3                   50
-#define USBD_INT4                   51
-#define USBD_INT5                   52
-#define USBD_INT6                   53
-#define BTSYS_INT                   55
-#define BTTIM_INT                   56
-#define BTWUI_INT                   57
-#define TIM2_INT                    58
-#define TIM1_INT                    59
-#define DMA_ERR                     60
-#define DMA_INT                     61
-#define GPIO_INT_PORTD              62
-
-#define IMX_IRQS                         (64)
-
-/* note: the IMX has four gpio ports (A-D), but only
- *       the following pins are connected to the outside
- *       world:
- *
- * PORT A: bits 0-31
- * PORT B: bits 8-31
- * PORT C: bits 3-17
- * PORT D: bits 6-31
- *
- * We map these interrupts straight on. As a result we have
- * several holes in the interrupt mapping. We do this for two
- * reasons:
- *   - mapping the interrupts without holes would get
- *     far more complicated
- *   - Motorola could well decide to bring some processor
- *     with more pins connected
- */
-
-#define IRQ_GPIOA(x)  (IMX_IRQS + x)
-#define IRQ_GPIOB(x)  (IRQ_GPIOA(32) + x)
-#define IRQ_GPIOC(x)  (IRQ_GPIOB(32) + x)
-#define IRQ_GPIOD(x)  (IRQ_GPIOC(32) + x)
-
-/* decode irq number to use with IMR(x), ISR(x) and friends */
-#define IRQ_TO_REG(irq) ((irq - IMX_IRQS) >> 5)
-
-#define NR_IRQS (IRQ_GPIOD(32) + 1)
-#define IRQ_GPIO(x)
-#endif
diff --git a/include/asm-arm/arch-imx/memory.h b/include/asm-arm/arch-imx/memory.h
deleted file mode 100644
index 5ad90127915f..000000000000
--- a/include/asm-arm/arch-imx/memory.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-imx/memory.h
- *
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_MMU_H
-#define __ASM_ARCH_MMU_H
-
-#define PHYS_OFFSET     UL(0x08000000)
-
-/*
- * Virtual view <-> DMA view memory address translations
- * virt_to_bus: Used to translate the virtual address to an
- *              address suitable to be passed to set_dma_addr
- * bus_to_virt: Used to convert an address for DMA operations
- *              to an address that the kernel can use.
- */
-#define __virt_to_bus(x)        (x - PAGE_OFFSET + PHYS_OFFSET)
-#define __bus_to_virt(x)        (x - PHYS_OFFSET + PAGE_OFFSET)
-
-#endif
diff --git a/include/asm-arm/arch-imx/mx1ads.h b/include/asm-arm/arch-imx/mx1ads.h
deleted file mode 100644
index d90fa4b49ce1..000000000000
--- a/include/asm-arm/arch-imx/mx1ads.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * linux/include/asm-arm/arch-imx/mx1ads.h
- *
- * Copyright (C) 2004 Robert Schwebel, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-
-#ifndef __ASM_ARCH_MX1ADS_H
-#define __ASM_ARCH_MX1ADS_H
-
-/* ------------------------------------------------------------------------ */
-/* Memory Map for the M9328MX1ADS (MX1ADS) Board                            */
-/* ------------------------------------------------------------------------ */
-
-#define MX1ADS_FLASH_PHYS               0x10000000
-#define MX1ADS_FLASH_SIZE               (16*1024*1024)
-
-#define IMX_FB_PHYS                     (0x0C000000 - 0x40000)
-
-#define CLK32 32000
-
-#endif /* __ASM_ARCH_MX1ADS_H */
diff --git a/include/asm-arm/arch-imx/spi_imx.h b/include/asm-arm/arch-imx/spi_imx.h
deleted file mode 100644
index 2165449e976e..000000000000
--- a/include/asm-arm/arch-imx/spi_imx.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * include/asm-arm/arch-imx/spi_imx.h
- *
- * Copyright (C) 2006 SWAPP
- *      Andrea Paterniani <a.paterniani@swapp-eng.it>
- *
- * Initial version inspired by:
- *      linux-2.6.17-rc3-mm1/include/asm-arm/arch-pxa/pxa2xx_spi.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef SPI_IMX_H_
-#define SPI_IMX_H_
-
-
-/*-------------------------------------------------------------------------*/
-/**
- * struct spi_imx_master - device.platform_data for SPI controller devices.
- * @num_chipselect: chipselects are used to distinguish individual
- *      SPI slaves, and are numbered from zero to num_chipselects - 1.
- *      each slave has a chipselect signal, but it's common that not
- *      every chipselect is connected to a slave.
- * @enable_dma: if true enables DMA driven transfers.
-*/
-struct spi_imx_master {
-        u8 num_chipselect;
-        u8 enable_dma:1;
-};
-/*-------------------------------------------------------------------------*/
-
-
-/*-------------------------------------------------------------------------*/
-/**
- * struct spi_imx_chip - spi_board_info.controller_data for SPI
- * slave devices, copied to spi_device.controller_data.
- * @enable_loopback : used for test purpouse to internally connect RX and TX
- *      sections.
- * @enable_dma : enables dma transfer (provided that controller driver has
- *      dma enabled too).
- * @ins_ss_pulse : enable /SS pulse insertion between SPI burst.
- * @bclk_wait : number of bclk waits between each bits_per_word SPI burst.
- * @cs_control : function pointer to board-specific function to assert/deassert
- *      I/O port to control HW generation of devices chip-select.
-*/
-struct spi_imx_chip {
-        u8      enable_loopback:1;
-        u8      enable_dma:1;
-        u8      ins_ss_pulse:1;
-        u16     bclk_wait:15;
-        void (*cs_control)(u32 control);
-};
-
-/* Chip-select state */
-#define SPI_CS_ASSERT                   (1 << 0)
-#define SPI_CS_DEASSERT                 (1 << 1)
-/*-------------------------------------------------------------------------*/
-
-
-#endif /* SPI_IMX_H_*/
diff --git a/include/asm-arm/arch-imx/system.h b/include/asm-arm/arch-imx/system.h
deleted file mode 100644
index c645fe9afb9d..000000000000
--- a/include/asm-arm/arch-imx/system.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-imxads/system.h
- *
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static void
-arch_idle(void)
-{
-        /*
-         * This should do all the clock switching
-         * and wait for interrupt tricks
-         */
-        cpu_do_idle();
-}
-
-static inline void
-arch_reset(char mode)
-{
-        cpu_reset(0);
-}
-
-#endif
diff --git a/include/asm-arm/arch-imx/uncompress.h b/include/asm-arm/arch-imx/uncompress.h
deleted file mode 100644
index da333f69136f..000000000000
--- a/include/asm-arm/arch-imx/uncompress.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-imxads/uncompress.h
- *
- *
- *
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) Shane Nay (shane@minirl.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#define UART(x) (*(volatile unsigned long *)(serial_port + (x)))
-
-#define UART1_BASE 0x206000
-#define UART2_BASE 0x207000
-#define USR2 0x98
-#define USR2_TXFE (1<<14)
-#define TXR  0x40
-#define UCR1 0x80
-#define UCR1_UARTEN 1
-
-/*
- * The following code assumes the serial port has already been
- * initialized by the bootloader.  We search for the first enabled
- * port in the most probable order.  If you didn't setup a port in
- * your bootloader then nothing will appear (which might be desired).
- *
- * This does not append a newline
- */
-static void putc(int c)
-{
-        unsigned long serial_port;
-
-        do {
-                serial_port = UART1_BASE;
-                if ( UART(UCR1) & UCR1_UARTEN )
-                        break;
-                serial_port = UART2_BASE;
-                if ( UART(UCR1) & UCR1_UARTEN )
-                        break;
-                return;
-        } while(0);
-
-        while (!(UART(USR2) & USR2_TXFE))
-                barrier();
-
-        UART(TXR) = c;
-}
-
-static inline void flush(void)
-{
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-
-#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-imx/vmalloc.h b/include/asm-arm/arch-imx/vmalloc.h
deleted file mode 100644
index cb6169127068..000000000000
--- a/include/asm-arm/arch-imx/vmalloc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-imx/vmalloc.h
- *
- *  Copyright (C) 2000 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
diff --git a/include/asm-arm/arch-integrator/debug-macro.S b/include/asm-arm/arch-integrator/debug-macro.S
deleted file mode 100644
index 85b327c352df..000000000000
--- a/include/asm-arm/arch-integrator/debug-macro.S
+++ /dev/null
@@ -1,22 +0,0 @@
-/* linux/include/asm-arm/arch-integrator/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-                .macro  addruart,rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx, #0x16000000        @ physical base address
-                movne   \rx, #0xf0000000        @ virtual base
-                addne   \rx, \rx, #0x16000000 >> 4
-                .endm
-
-#include <asm/hardware/debug-pl01x.S>
diff --git a/include/asm-arm/arch-integrator/dma.h b/include/asm-arm/arch-integrator/dma.h
deleted file mode 100644
index 83fd6bbaf9d3..000000000000
--- a/include/asm-arm/arch-integrator/dma.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-integrator/dma.h
- *
- *  Copyright (C) 1997,1998 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
diff --git a/include/asm-arm/arch-integrator/entry-macro.S b/include/asm-arm/arch-integrator/entry-macro.S
deleted file mode 100644
index ef535a68bdd3..000000000000
--- a/include/asm-arm/arch-integrator/entry-macro.S
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * include/asm-arm/arch-integrator/entry-macro.S
- *
- * Low-level IRQ helper macros for Integrator platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <asm/arch/hardware.h>
-#include <asm/arch/irqs.h>
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-/* FIXME: should not be using soo many LDRs here */
-                ldr     \base, =IO_ADDRESS(INTEGRATOR_IC_BASE)
-                mov     \irqnr, #IRQ_PIC_START
-                ldr     \irqstat, [\base, #IRQ_STATUS]          @ get masked status
-                ldr     \base, =IO_ADDRESS(INTEGRATOR_HDR_BASE)
-                teq     \irqstat, #0
-                ldreq   \irqstat, [\base, #(INTEGRATOR_HDR_IC_OFFSET+IRQ_STATUS)]
-                moveq   \irqnr, #IRQ_CIC_START
-
-1001:           tst     \irqstat, #15
-                bne     1002f
-                add     \irqnr, \irqnr, #4
-                movs    \irqstat, \irqstat, lsr #4
-                bne     1001b
-1002:           tst     \irqstat, #1
-                bne     1003f
-                add     \irqnr, \irqnr, #1
-                movs    \irqstat, \irqstat, lsr #1
-                bne     1002b
-1003:           /* EQ will be set if no irqs pending */
-                .endm
-
diff --git a/include/asm-arm/arch-integrator/hardware.h b/include/asm-arm/arch-integrator/hardware.h
deleted file mode 100644
index 6f0947bc500d..000000000000
--- a/include/asm-arm/arch-integrator/hardware.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-integrator/hardware.h
- *
- *  This file contains the hardware definitions of the Integrator.
- *
- *  Copyright (C) 1999 ARM Limited.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <asm/sizes.h>
-#include <asm/arch/platform.h>
-
-/*
- * Where in virtual memory the IO devices (timers, system controllers
- * and so on)
- */
-#define IO_BASE                 0xF0000000                 // VA of IO 
-#define IO_SIZE                 0x0B000000                 // How much?
-#define IO_START                INTEGRATOR_HDR_BASE        // PA of IO
-
-#define PCIO_BASE               PCI_IO_VADDR
-#define PCIMEM_BASE             PCI_MEMORY_VADDR
-
-/* macro to get at IO space when running virtually */
-#define IO_ADDRESS(x) (((x) >> 4) + IO_BASE) 
-
-#define pcibios_assign_all_busses()     1
-
-#define PCIBIOS_MIN_IO          0x6000
-#define PCIBIOS_MIN_MEM         0x00100000
-
-#endif
-
diff --git a/include/asm-arm/arch-integrator/io.h b/include/asm-arm/arch-integrator/io.h
deleted file mode 100644
index c8f2175948bd..000000000000
--- a/include/asm-arm/arch-integrator/io.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-integrator/io.h
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffff
-
-/*
- * WARNING: this has to mirror definitions in platform.h
- */
-#define PCI_MEMORY_VADDR        0xe8000000
-#define PCI_CONFIG_VADDR        0xec000000
-#define PCI_V3_VADDR            0xed000000
-#define PCI_IO_VADDR            0xee000000
-
-#define __io(a)                 ((void __iomem *)(PCI_IO_VADDR + (a)))
-#define __mem_pci(a)            (a)
-
-#endif
diff --git a/include/asm-arm/arch-integrator/irqs.h b/include/asm-arm/arch-integrator/irqs.h
deleted file mode 100644
index ba7b3afee445..000000000000
--- a/include/asm-arm/arch-integrator/irqs.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-integrator/irqs.h
- *
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-/* 
- *  Interrupt numbers
- */
-#define IRQ_PIC_START                   0
-#define IRQ_SOFTINT                     0
-#define IRQ_UARTINT0                    1
-#define IRQ_UARTINT1                    2
-#define IRQ_KMIINT0                     3
-#define IRQ_KMIINT1                     4
-#define IRQ_TIMERINT0                   5
-#define IRQ_TIMERINT1                   6
-#define IRQ_TIMERINT2                   7
-#define IRQ_RTCINT                      8
-#define IRQ_AP_EXPINT0                  9
-#define IRQ_AP_EXPINT1                  10
-#define IRQ_AP_EXPINT2                  11
-#define IRQ_AP_EXPINT3                  12
-#define IRQ_AP_PCIINT0                  13
-#define IRQ_AP_PCIINT1                  14
-#define IRQ_AP_PCIINT2                  15
-#define IRQ_AP_PCIINT3                  16
-#define IRQ_AP_V3INT                    17
-#define IRQ_AP_CPINT0                   18
-#define IRQ_AP_CPINT1                   19
-#define IRQ_AP_LBUSTIMEOUT              20
-#define IRQ_AP_APCINT                   21
-#define IRQ_CP_CLCDCINT                 22
-#define IRQ_CP_MMCIINT0                 23
-#define IRQ_CP_MMCIINT1                 24
-#define IRQ_CP_AACIINT                  25
-#define IRQ_CP_CPPLDINT                 26
-#define IRQ_CP_ETHINT                   27
-#define IRQ_CP_TSPENINT                 28
-#define IRQ_PIC_END                     31
-
-#define IRQ_CIC_START                   32
-#define IRQ_CM_SOFTINT                  32
-#define IRQ_CM_COMMRX                   33
-#define IRQ_CM_COMMTX                   34
-#define IRQ_CIC_END                     34
-
-/*
- * IntegratorCP only
- */
-#define IRQ_SIC_START                   35
-#define IRQ_SIC_CP_SOFTINT              35
-#define IRQ_SIC_CP_RI0                  36
-#define IRQ_SIC_CP_RI1                  37
-#define IRQ_SIC_CP_CARDIN               38
-#define IRQ_SIC_CP_LMINT0               39
-#define IRQ_SIC_CP_LMINT1               40
-#define IRQ_SIC_CP_LMINT2               41
-#define IRQ_SIC_CP_LMINT3               42
-#define IRQ_SIC_CP_LMINT4               43
-#define IRQ_SIC_CP_LMINT5               44
-#define IRQ_SIC_CP_LMINT6               45
-#define IRQ_SIC_CP_LMINT7               46
-#define IRQ_SIC_END                     46
-
-#define NR_IRQS                         47
-
diff --git a/include/asm-arm/arch-integrator/memory.h b/include/asm-arm/arch-integrator/memory.h
deleted file mode 100644
index 1ab56d783e7c..000000000000
--- a/include/asm-arm/arch-integrator/memory.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-integrator/memory.h
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-/*
- * Physical DRAM offset.
- */
-#define PHYS_OFFSET     UL(0x00000000)
-#define BUS_OFFSET      UL(0x80000000)
-
-/*
- * Virtual view <-> DMA view memory address translations
- * virt_to_bus: Used to translate the virtual address to an
- *              address suitable to be passed to set_dma_addr
- * bus_to_virt: Used to convert an address for DMA operations
- *              to an address that the kernel can use.
- */
-#define __virt_to_bus(x)        (x - PAGE_OFFSET + BUS_OFFSET)
-#define __bus_to_virt(x)        (x - BUS_OFFSET + PAGE_OFFSET)
-
-#endif
diff --git a/include/asm-arm/arch-integrator/system.h b/include/asm-arm/arch-integrator/system.h
deleted file mode 100644
index 8ea442237d20..000000000000
--- a/include/asm-arm/arch-integrator/system.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-integrator/system.h
- *
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-#include <asm/arch/cm.h>
-
-static inline void arch_idle(void)
-{
-        /*
-         * This should do all the clock switching
-         * and wait for interrupt tricks
-         */
-        cpu_do_idle();
-}
-
-static inline void arch_reset(char mode)
-{
-        /*
-         * To reset, we hit the on-board reset register
-         * in the system FPGA
-         */
-        cm_control(CM_CTRL_RESET, CM_CTRL_RESET);
-}
-
-#endif
diff --git a/include/asm-arm/arch-integrator/timex.h b/include/asm-arm/arch-integrator/timex.h
deleted file mode 100644
index 87a762818ba2..000000000000
--- a/include/asm-arm/arch-integrator/timex.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-integrator/timex.h
- *
- *  Integrator architecture timex specifications
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-/*
- * ??
- */
-#define CLOCK_TICK_RATE         (50000000 / 16)
diff --git a/include/asm-arm/arch-integrator/uncompress.h b/include/asm-arm/arch-integrator/uncompress.h
deleted file mode 100644
index f61825c4d901..000000000000
--- a/include/asm-arm/arch-integrator/uncompress.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-integrator/uncompress.h
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#define AMBA_UART_DR    (*(volatile unsigned char *)0x16000000)
-#define AMBA_UART_LCRH  (*(volatile unsigned char *)0x16000008)
-#define AMBA_UART_LCRM  (*(volatile unsigned char *)0x1600000c)
-#define AMBA_UART_LCRL  (*(volatile unsigned char *)0x16000010)
-#define AMBA_UART_CR    (*(volatile unsigned char *)0x16000014)
-#define AMBA_UART_FR    (*(volatile unsigned char *)0x16000018)
-
-/*
- * This does not append a newline
- */
-static void putc(int c)
-{
-        while (AMBA_UART_FR & (1 << 5))
-                barrier();
-
-        AMBA_UART_DR = c;
-}
-
-static inline void flush(void)
-{
-        while (AMBA_UART_FR & (1 << 3))
-                barrier();
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-
-#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-integrator/vmalloc.h b/include/asm-arm/arch-integrator/vmalloc.h
deleted file mode 100644
index 170cccece523..000000000000
--- a/include/asm-arm/arch-integrator/vmalloc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-integrator/vmalloc.h
- *
- *  Copyright (C) 2000 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
diff --git a/include/asm-arm/arch-iop13xx/adma.h b/include/asm-arm/arch-iop13xx/adma.h
deleted file mode 100644
index 26f60af67168..000000000000
--- a/include/asm-arm/arch-iop13xx/adma.h
+++ /dev/null
@@ -1,537 +0,0 @@
-/*
- * Copyright(c) 2006, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- *
- */
-#ifndef _ADMA_H
-#define _ADMA_H
-#include <linux/types.h>
-#include <linux/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/hardware/iop_adma.h>
-
-#define ADMA_ACCR(chan) (chan->mmr_base + 0x0)
-#define ADMA_ACSR(chan) (chan->mmr_base + 0x4)
-#define ADMA_ADAR(chan) (chan->mmr_base + 0x8)
-#define ADMA_IIPCR(chan)        (chan->mmr_base + 0x18)
-#define ADMA_IIPAR(chan)        (chan->mmr_base + 0x1c)
-#define ADMA_IIPUAR(chan)       (chan->mmr_base + 0x20)
-#define ADMA_ANDAR(chan)        (chan->mmr_base + 0x24)
-#define ADMA_ADCR(chan) (chan->mmr_base + 0x28)
-#define ADMA_CARMD(chan)        (chan->mmr_base + 0x2c)
-#define ADMA_ABCR(chan) (chan->mmr_base + 0x30)
-#define ADMA_DLADR(chan)        (chan->mmr_base + 0x34)
-#define ADMA_DUADR(chan)        (chan->mmr_base + 0x38)
-#define ADMA_SLAR(src, chan)    (chan->mmr_base + (0x3c + (src << 3)))
-#define ADMA_SUAR(src, chan)    (chan->mmr_base + (0x40 + (src << 3)))
-
-struct iop13xx_adma_src {
-        u32 src_addr;
-        union {
-                u32 upper_src_addr;
-                struct {
-                        unsigned int pq_upper_src_addr:24;
-                        unsigned int pq_dmlt:8;
-                };
-        };
-};
-
-struct iop13xx_adma_desc_ctrl {
-        unsigned int int_en:1;
-        unsigned int xfer_dir:2;
-        unsigned int src_select:4;
-        unsigned int zero_result:1;
-        unsigned int block_fill_en:1;
-        unsigned int crc_gen_en:1;
-        unsigned int crc_xfer_dis:1;
-        unsigned int crc_seed_fetch_dis:1;
-        unsigned int status_write_back_en:1;
-        unsigned int endian_swap_en:1;
-        unsigned int reserved0:2;
-        unsigned int pq_update_xfer_en:1;
-        unsigned int dual_xor_en:1;
-        unsigned int pq_xfer_en:1;
-        unsigned int p_xfer_dis:1;
-        unsigned int reserved1:10;
-        unsigned int relax_order_en:1;
-        unsigned int no_snoop_en:1;
-};
-
-struct iop13xx_adma_byte_count {
-        unsigned int byte_count:24;
-        unsigned int host_if:3;
-        unsigned int reserved:2;
-        unsigned int zero_result_err_q:1;
-        unsigned int zero_result_err:1;
-        unsigned int tx_complete:1;
-};
-
-struct iop13xx_adma_desc_hw {
-        u32 next_desc;
-        union {
-                u32 desc_ctrl;
-                struct iop13xx_adma_desc_ctrl desc_ctrl_field;
-        };
-        union {
-                u32 crc_addr;
-                u32 block_fill_data;
-                u32 q_dest_addr;
-        };
-        union {
-                u32 byte_count;
-                struct iop13xx_adma_byte_count byte_count_field;
-        };
-        union {
-                u32 dest_addr;
-                u32 p_dest_addr;
-        };
-        union {
-                u32 upper_dest_addr;
-                u32 pq_upper_dest_addr;
-        };
-        struct iop13xx_adma_src src[1];
-};
-
-struct iop13xx_adma_desc_dual_xor {
-        u32 next_desc;
-        u32 desc_ctrl;
-        u32 reserved;
-        u32 byte_count;
-        u32 h_dest_addr;
-        u32 h_upper_dest_addr;
-        u32 src0_addr;
-        u32 upper_src0_addr;
-        u32 src1_addr;
-        u32 upper_src1_addr;
-        u32 h_src_addr;
-        u32 h_upper_src_addr;
-        u32 d_src_addr;
-        u32 d_upper_src_addr;
-        u32 d_dest_addr;
-        u32 d_upper_dest_addr;
-};
-
-struct iop13xx_adma_desc_pq_update {
-        u32 next_desc;
-        u32 desc_ctrl;
-        u32 reserved;
-        u32 byte_count;
-        u32 p_dest_addr;
-        u32 p_upper_dest_addr;
-        u32 src0_addr;
-        u32 upper_src0_addr;
-        u32 src1_addr;
-        u32 upper_src1_addr;
-        u32 p_src_addr;
-        u32 p_upper_src_addr;
-        u32 q_src_addr;
-        struct {
-                unsigned int q_upper_src_addr:24;
-                unsigned int q_dmlt:8;
-        };
-        u32 q_dest_addr;
-        u32 q_upper_dest_addr;
-};
-
-static inline int iop_adma_get_max_xor(void)
-{
-        return 16;
-}
-
-static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan)
-{
-        return __raw_readl(ADMA_ADAR(chan));
-}
-
-static inline void iop_chan_set_next_descriptor(struct iop_adma_chan *chan,
-                                                u32 next_desc_addr)
-{
-        __raw_writel(next_desc_addr, ADMA_ANDAR(chan));
-}
-
-#define ADMA_STATUS_BUSY (1 << 13)
-
-static inline char iop_chan_is_busy(struct iop_adma_chan *chan)
-{
-        if (__raw_readl(ADMA_ACSR(chan)) &
-                ADMA_STATUS_BUSY)
-                return 1;
-        else
-                return 0;
-}
-
-static inline int
-iop_chan_get_desc_align(struct iop_adma_chan *chan, int num_slots)
-{
-        return 1;
-}
-#define iop_desc_is_aligned(x, y) 1
-
-static inline int
-iop_chan_memcpy_slot_count(size_t len, int *slots_per_op)
-{
-        *slots_per_op = 1;
-        return 1;
-}
-
-#define iop_chan_interrupt_slot_count(s, c) iop_chan_memcpy_slot_count(0, s)
-
-static inline int
-iop_chan_memset_slot_count(size_t len, int *slots_per_op)
-{
-        *slots_per_op = 1;
-        return 1;
-}
-
-static inline int
-iop_chan_xor_slot_count(size_t len, int src_cnt, int *slots_per_op)
-{
-        static const char slot_count_table[] = { 1, 2, 2, 2,
-                                                 2, 3, 3, 3,
-                                                 3, 4, 4, 4,
-                                                 4, 5, 5, 5,
-                                                };
-        *slots_per_op = slot_count_table[src_cnt - 1];
-        return *slots_per_op;
-}
-
-#define ADMA_MAX_BYTE_COUNT     (16 * 1024 * 1024)
-#define IOP_ADMA_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
-#define IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
-#define IOP_ADMA_XOR_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
-#define iop_chan_zero_sum_slot_count(l, s, o) iop_chan_xor_slot_count(l, s, o)
-
-static inline u32 iop_desc_get_dest_addr(struct iop_adma_desc_slot *desc,
-                                        struct iop_adma_chan *chan)
-{
-        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
-        return hw_desc->dest_addr;
-}
-
-static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc,
-                                        struct iop_adma_chan *chan)
-{
-        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
-        return hw_desc->byte_count_field.byte_count;
-}
-
-static inline u32 iop_desc_get_src_addr(struct iop_adma_desc_slot *desc,
-                                        struct iop_adma_chan *chan,
-                                        int src_idx)
-{
-        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
-        return hw_desc->src[src_idx].src_addr;
-}
-
-static inline u32 iop_desc_get_src_count(struct iop_adma_desc_slot *desc,
-                                        struct iop_adma_chan *chan)
-{
-        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
-        return hw_desc->desc_ctrl_field.src_select + 1;
-}
-
-static inline void
-iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, unsigned long flags)
-{
-        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
-        union {
-                u32 value;
-                struct iop13xx_adma_desc_ctrl field;
-        } u_desc_ctrl;
-
-        u_desc_ctrl.value = 0;
-        u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
-        u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
-        hw_desc->desc_ctrl = u_desc_ctrl.value;
-        hw_desc->crc_addr = 0;
-}
-
-static inline void
-iop_desc_init_memset(struct iop_adma_desc_slot *desc, unsigned long flags)
-{
-        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
-        union {
-                u32 value;
-                struct iop13xx_adma_desc_ctrl field;
-        } u_desc_ctrl;
-
-        u_desc_ctrl.value = 0;
-        u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
-        u_desc_ctrl.field.block_fill_en = 1;
-        u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
-        hw_desc->desc_ctrl = u_desc_ctrl.value;
-        hw_desc->crc_addr = 0;
-}
-
-/* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */
-static inline void
-iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt,
-                  unsigned long flags)
-{
-        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
-        union {
-                u32 value;
-                struct iop13xx_adma_desc_ctrl field;
-        } u_desc_ctrl;
-
-        u_desc_ctrl.value = 0;
-        u_desc_ctrl.field.src_select = src_cnt - 1;
-        u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
-        u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
-        hw_desc->desc_ctrl = u_desc_ctrl.value;
-        hw_desc->crc_addr = 0;
-
-}
-#define iop_desc_init_null_xor(d, s, i) iop_desc_init_xor(d, s, i)
-
-/* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */
-static inline int
-iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt,
-                       unsigned long flags)
-{
-        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
-        union {
-                u32 value;
-                struct iop13xx_adma_desc_ctrl field;
-        } u_desc_ctrl;
-
-        u_desc_ctrl.value = 0;
-        u_desc_ctrl.field.src_select = src_cnt - 1;
-        u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
-        u_desc_ctrl.field.zero_result = 1;
-        u_desc_ctrl.field.status_write_back_en = 1;
-        u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
-        hw_desc->desc_ctrl = u_desc_ctrl.value;
-        hw_desc->crc_addr = 0;
-
-        return 1;
-}
-
-static inline void iop_desc_set_byte_count(struct iop_adma_desc_slot *desc,
-                                        struct iop_adma_chan *chan,
-                                        u32 byte_count)
-{
-        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
-        hw_desc->byte_count = byte_count;
-}
-
-static inline void
-iop_desc_set_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len)
-{
-        int slots_per_op = desc->slots_per_op;
-        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter;
-        int i = 0;
-
-        if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) {
-                hw_desc->byte_count = len;
-        } else {
-                do {
-                        iter = iop_hw_desc_slot_idx(hw_desc, i);
-                        iter->byte_count = IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
-                        len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
-                        i += slots_per_op;
-                } while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT);
-
-                if (len) {
-                        iter = iop_hw_desc_slot_idx(hw_desc, i);
-                        iter->byte_count = len;
-                }
-        }
-}
-
-
-static inline void iop_desc_set_dest_addr(struct iop_adma_desc_slot *desc,
-                                        struct iop_adma_chan *chan,
-                                        dma_addr_t addr)
-{
-        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
-        hw_desc->dest_addr = addr;
-        hw_desc->upper_dest_addr = 0;
-}
-
-static inline void iop_desc_set_memcpy_src_addr(struct iop_adma_desc_slot *desc,
-                                        dma_addr_t addr)
-{
-        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
-        hw_desc->src[0].src_addr = addr;
-        hw_desc->src[0].upper_src_addr = 0;
-}
-
-static inline void iop_desc_set_xor_src_addr(struct iop_adma_desc_slot *desc,
-                                        int src_idx, dma_addr_t addr)
-{
-        int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op;
-        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter;
-        int i = 0;
-
-        do {
-                iter = iop_hw_desc_slot_idx(hw_desc, i);
-                iter->src[src_idx].src_addr = addr;
-                iter->src[src_idx].upper_src_addr = 0;
-                slot_cnt -= slots_per_op;
-                if (slot_cnt) {
-                        i += slots_per_op;
-                        addr += IOP_ADMA_XOR_MAX_BYTE_COUNT;
-                }
-        } while (slot_cnt);
-}
-
-static inline void
-iop_desc_init_interrupt(struct iop_adma_desc_slot *desc,
-        struct iop_adma_chan *chan)
-{
-        iop_desc_init_memcpy(desc, 1);
-        iop_desc_set_byte_count(desc, chan, 0);
-        iop_desc_set_dest_addr(desc, chan, 0);
-        iop_desc_set_memcpy_src_addr(desc, 0);
-}
-
-#define iop_desc_set_zero_sum_src_addr iop_desc_set_xor_src_addr
-
-static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc,
-                                        u32 next_desc_addr)
-{
-        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
-        BUG_ON(hw_desc->next_desc);
-        hw_desc->next_desc = next_desc_addr;
-}
-
-static inline u32 iop_desc_get_next_desc(struct iop_adma_desc_slot *desc)
-{
-        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
-        return hw_desc->next_desc;
-}
-
-static inline void iop_desc_clear_next_desc(struct iop_adma_desc_slot *desc)
-{
-        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
-        hw_desc->next_desc = 0;
-}
-
-static inline void iop_desc_set_block_fill_val(struct iop_adma_desc_slot *desc,
-                                                u32 val)
-{
-        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
-        hw_desc->block_fill_data = val;
-}
-
-static inline int iop_desc_get_zero_result(struct iop_adma_desc_slot *desc)
-{
-        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
-        struct iop13xx_adma_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field;
-        struct iop13xx_adma_byte_count byte_count = hw_desc->byte_count_field;
-
-        BUG_ON(!(byte_count.tx_complete && desc_ctrl.zero_result));
-
-        if (desc_ctrl.pq_xfer_en)
-                return byte_count.zero_result_err_q;
-        else
-                return byte_count.zero_result_err;
-}
-
-static inline void iop_chan_append(struct iop_adma_chan *chan)
-{
-        u32 adma_accr;
-
-        adma_accr = __raw_readl(ADMA_ACCR(chan));
-        adma_accr |= 0x2;
-        __raw_writel(adma_accr, ADMA_ACCR(chan));
-}
-
-static inline u32 iop_chan_get_status(struct iop_adma_chan *chan)
-{
-        return __raw_readl(ADMA_ACSR(chan));
-}
-
-static inline void iop_chan_disable(struct iop_adma_chan *chan)
-{
-        u32 adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan));
-        adma_chan_ctrl &= ~0x1;
-        __raw_writel(adma_chan_ctrl, ADMA_ACCR(chan));
-}
-
-static inline void iop_chan_enable(struct iop_adma_chan *chan)
-{
-        u32 adma_chan_ctrl;
-
-        adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan));
-        adma_chan_ctrl |= 0x1;
-        __raw_writel(adma_chan_ctrl, ADMA_ACCR(chan));
-}
-
-static inline void iop_adma_device_clear_eot_status(struct iop_adma_chan *chan)
-{
-        u32 status = __raw_readl(ADMA_ACSR(chan));
-        status &= (1 << 12);
-        __raw_writel(status, ADMA_ACSR(chan));
-}
-
-static inline void iop_adma_device_clear_eoc_status(struct iop_adma_chan *chan)
-{
-        u32 status = __raw_readl(ADMA_ACSR(chan));
-        status &= (1 << 11);
-        __raw_writel(status, ADMA_ACSR(chan));
-}
-
-static inline void iop_adma_device_clear_err_status(struct iop_adma_chan *chan)
-{
-        u32 status = __raw_readl(ADMA_ACSR(chan));
-        status &= (1 << 9) | (1 << 5) | (1 << 4) | (1 << 3);
-        __raw_writel(status, ADMA_ACSR(chan));
-}
-
-static inline int
-iop_is_err_int_parity(unsigned long status, struct iop_adma_chan *chan)
-{
-        return test_bit(9, &status);
-}
-
-static inline int
-iop_is_err_mcu_abort(unsigned long status, struct iop_adma_chan *chan)
-{
-        return test_bit(5, &status);
-}
-
-static inline int
-iop_is_err_int_tabort(unsigned long status, struct iop_adma_chan *chan)
-{
-        return test_bit(4, &status);
-}
-
-static inline int
-iop_is_err_int_mabort(unsigned long status, struct iop_adma_chan *chan)
-{
-        return test_bit(3, &status);
-}
-
-static inline int
-iop_is_err_pci_tabort(unsigned long status, struct iop_adma_chan *chan)
-{
-        return 0;
-}
-
-static inline int
-iop_is_err_pci_mabort(unsigned long status, struct iop_adma_chan *chan)
-{
-        return 0;
-}
-
-static inline int
-iop_is_err_split_tx(unsigned long status, struct iop_adma_chan *chan)
-{
-        return 0;
-}
-
-#endif /* _ADMA_H */
diff --git a/include/asm-arm/arch-iop13xx/debug-macro.S b/include/asm-arm/arch-iop13xx/debug-macro.S
deleted file mode 100644
index 788b4e386c16..000000000000
--- a/include/asm-arm/arch-iop13xx/debug-macro.S
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * include/asm-arm/arch-iop13xx/debug-macro.S
- *
- * Debugging macro include header
- *
- * Copyright (C) 1994-1999 Russell King
- * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-        .macro  addruart, rx
-        mrc     p15, 0, \rx, c1, c0
-        tst     \rx, #1                 @ mmu enabled?
-        moveq   \rx, #0xff000000        @ physical
-        orreq   \rx, \rx, #0x00d80000
-        movne   \rx, #0xfe000000        @ virtual
-        orrne   \rx, \rx, #0x00e80000
-        orr     \rx, \rx, #0x00002300
-        orr     \rx, \rx, #0x00000040
-        .endm
-
-#define UART_SHIFT      2
-#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-iop13xx/memory.h b/include/asm-arm/arch-iop13xx/memory.h
deleted file mode 100644
index 031a0fa78eff..000000000000
--- a/include/asm-arm/arch-iop13xx/memory.h
+++ /dev/null
@@ -1,64 +0,0 @@
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-#include <asm/arch/hardware.h>
-
-/*
- * Physical DRAM offset.
- */
-#define PHYS_OFFSET     UL(0x00000000)
-#define TASK_SIZE       UL(0x3f000000)
-#define PAGE_OFFSET     UL(0x40000000)
-#define TASK_UNMAPPED_BASE ((TASK_SIZE + 0x01000000) / 3)
-
-#ifndef __ASSEMBLY__
-
-#if defined(CONFIG_ARCH_IOP13XX)
-#define IOP13XX_PMMR_V_START (IOP13XX_PMMR_VIRT_MEM_BASE)
-#define IOP13XX_PMMR_V_END   (IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_SIZE)
-#define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE)
-#define IOP13XX_PMMR_P_END   (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE)
-
-/*
- * Virtual view <-> PCI DMA view memory address translations
- * virt_to_bus: Used to translate the virtual address to an
- *              address suitable to be passed to set_dma_addr
- * bus_to_virt: Used to convert an address for DMA operations
- *              to an address that the kernel can use.
- */
-
-/* RAM has 1:1 mapping on the PCIe/x Busses */
-#define __virt_to_bus(x)        (__virt_to_phys(x))
-#define __bus_to_virt(x)    (__phys_to_virt(x))
-
-#define virt_to_lbus(x)                                            \
-(( ((void*)(x) >= (void*)IOP13XX_PMMR_V_START) &&                  \
-((void*)(x) < (void*)IOP13XX_PMMR_V_END) ) ?                       \
-((x) - IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_PHYS_MEM_BASE) : \
-((x) - PAGE_OFFSET + PHYS_OFFSET))
-
-#define lbus_to_virt(x)                                            \
-(( ((x) >= IOP13XX_PMMR_P_START) && ((x) < IOP13XX_PMMR_P_END) ) ? \
-((x) - IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_VIRT_MEM_BASE ) : \
-((x) - PHYS_OFFSET + PAGE_OFFSET))
-
-/* Device is an lbus device if it is on the platform bus of the IOP13XX */
-#define is_lbus_device(dev) (dev &&\
-                             (strncmp(dev->bus->name, "platform", 8) == 0))
-
-#define __arch_page_to_dma(dev, page)                                   \
-({is_lbus_device(dev) ? (dma_addr_t)virt_to_lbus(page_address(page)) : \
-(dma_addr_t)__virt_to_bus(page_address(page));})
-
-#define __arch_dma_to_virt(dev, addr) \
-({is_lbus_device(dev) ? lbus_to_virt(addr) : __bus_to_virt(addr);})
-
-#define __arch_virt_to_dma(dev, addr) \
-({is_lbus_device(dev) ? virt_to_lbus(addr) : __virt_to_bus(addr);})
-
-#endif /* CONFIG_ARCH_IOP13XX */
-#endif /* !ASSEMBLY */
-
-#define PFN_TO_NID(addr)        (0)
-
-#endif
diff --git a/include/asm-arm/arch-iop13xx/pci.h b/include/asm-arm/arch-iop13xx/pci.h
deleted file mode 100644
index 4041f30d4cd3..000000000000
--- a/include/asm-arm/arch-iop13xx/pci.h
+++ /dev/null
@@ -1,57 +0,0 @@
-#ifndef _IOP13XX_PCI_H_
-#define _IOP13XX_PCI_H_
-#include <asm/arch/irqs.h>
-#include <asm/io.h>
-
-struct pci_sys_data;
-struct hw_pci;
-int iop13xx_pci_setup(int nr, struct pci_sys_data *sys);
-struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *);
-void iop13xx_atu_select(struct hw_pci *plat_pci);
-void iop13xx_pci_init(void);
-void iop13xx_map_pci_memory(void);
-
-#define IOP_PCI_STATUS_ERROR (PCI_STATUS_PARITY |            \
-                               PCI_STATUS_SIG_TARGET_ABORT | \
-                               PCI_STATUS_REC_TARGET_ABORT | \
-                               PCI_STATUS_REC_TARGET_ABORT | \
-                               PCI_STATUS_REC_MASTER_ABORT | \
-                               PCI_STATUS_SIG_SYSTEM_ERROR | \
-                               PCI_STATUS_DETECTED_PARITY)
-
-#define IOP13XX_ATUE_ATUISR_ERROR (IOP13XX_ATUE_STAT_HALT_ON_ERROR |  \
-                                    IOP13XX_ATUE_STAT_ROOT_SYS_ERR |   \
-                                    IOP13XX_ATUE_STAT_PCI_IFACE_ERR |  \
-                                    IOP13XX_ATUE_STAT_ERR_COR |        \
-                                    IOP13XX_ATUE_STAT_ERR_UNCOR |      \
-                                    IOP13XX_ATUE_STAT_CRS |            \
-                                    IOP13XX_ATUE_STAT_DET_PAR_ERR |    \
-                                    IOP13XX_ATUE_STAT_EXT_REC_MABORT | \
-                                    IOP13XX_ATUE_STAT_SIG_TABORT |     \
-                                    IOP13XX_ATUE_STAT_EXT_REC_TABORT | \
-                                    IOP13XX_ATUE_STAT_MASTER_DATA_PAR)
-
-#define IOP13XX_ATUX_ATUISR_ERROR (IOP13XX_ATUX_STAT_TX_SCEM |        \
-                                    IOP13XX_ATUX_STAT_REC_SCEM |       \
-                                    IOP13XX_ATUX_STAT_TX_SERR |        \
-                                    IOP13XX_ATUX_STAT_DET_PAR_ERR |    \
-                                    IOP13XX_ATUX_STAT_INT_REC_MABORT | \
-                                    IOP13XX_ATUX_STAT_REC_SERR |       \
-                                    IOP13XX_ATUX_STAT_EXT_REC_MABORT | \
-                                    IOP13XX_ATUX_STAT_EXT_REC_TABORT | \
-                                    IOP13XX_ATUX_STAT_EXT_SIG_TABORT | \
-                                    IOP13XX_ATUX_STAT_MASTER_DATA_PAR)
-
-/* PCI interrupts
- */
-#define ATUX_INTA IRQ_IOP13XX_XINT0
-#define ATUX_INTB IRQ_IOP13XX_XINT1
-#define ATUX_INTC IRQ_IOP13XX_XINT2
-#define ATUX_INTD IRQ_IOP13XX_XINT3
-
-#define ATUE_INTA IRQ_IOP13XX_ATUE_IMA
-#define ATUE_INTB IRQ_IOP13XX_ATUE_IMB
-#define ATUE_INTC IRQ_IOP13XX_ATUE_IMC
-#define ATUE_INTD IRQ_IOP13XX_ATUE_IMD
-
-#endif /* _IOP13XX_PCI_H_ */
diff --git a/include/asm-arm/arch-iop13xx/system.h b/include/asm-arm/arch-iop13xx/system.h
deleted file mode 100644
index 8575af8db78c..000000000000
--- a/include/asm-arm/arch-iop13xx/system.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * linux/include/asm-arm/arch-iop13xx/system.h
- *
- *  Copyright (C) 2004 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <asm/arch/iop13xx.h>
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-static inline void arch_reset(char mode)
-{
-        /*
-         * Reset the internal bus (warning both cores are reset)
-         */
-        write_wdtcr(IOP_WDTCR_EN_ARM);
-        write_wdtcr(IOP_WDTCR_EN);
-        write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
-        write_wdtcr(0x1000);
-
-        for(;;);
-}
diff --git a/include/asm-arm/arch-iop13xx/timex.h b/include/asm-arm/arch-iop13xx/timex.h
deleted file mode 100644
index 47564ecb3872..000000000000
--- a/include/asm-arm/arch-iop13xx/timex.h
+++ /dev/null
@@ -1,3 +0,0 @@
-#include <asm/arch/hardware.h>
-
-#define CLOCK_TICK_RATE (100 * HZ)
diff --git a/include/asm-arm/arch-iop13xx/uncompress.h b/include/asm-arm/arch-iop13xx/uncompress.h
deleted file mode 100644
index 5d4418decb86..000000000000
--- a/include/asm-arm/arch-iop13xx/uncompress.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#include <asm/types.h>
-#include <linux/serial_reg.h>
-#include <asm/arch/hardware.h>
-
-#define UART_BASE ((volatile u32 *)IOP13XX_UART1_PHYS)
-#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
-
-static inline void putc(char c)
-{
-        while ((UART_BASE[UART_LSR] & TX_DONE) != TX_DONE)
-                barrier();
-        UART_BASE[UART_TX] = c;
-}
-
-static inline void flush(void)
-{
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-iop32x/debug-macro.S b/include/asm-arm/arch-iop32x/debug-macro.S
deleted file mode 100644
index 9022b6849e23..000000000000
--- a/include/asm-arm/arch-iop32x/debug-macro.S
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * include/asm-arm/arch-iop32x/debug-macro.S
- *
- * Debugging macro include header
- *
- * Copyright (C) 1994-1999 Russell King
- * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-                .macro  addruart, rx
-                mov     \rx, #0xfe000000        @ physical as well as virtual
-                orr     \rx, \rx, #0x00800000   @ location of the UART
-                .endm
-
-#define UART_SHIFT      0
-#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-iop32x/dma.h b/include/asm-arm/arch-iop32x/dma.h
deleted file mode 100644
index e977a9ef3160..000000000000
--- a/include/asm-arm/arch-iop32x/dma.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * include/asm-arm/arch-iop32x/dma.h
- *
- * Copyright (C) 2004 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
diff --git a/include/asm-arm/arch-iop32x/entry-macro.S b/include/asm-arm/arch-iop32x/entry-macro.S
deleted file mode 100644
index 207db99dfbd2..000000000000
--- a/include/asm-arm/arch-iop32x/entry-macro.S
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * include/asm-arm/arch-iop32x/entry-macro.S
- *
- * Low-level IRQ helper macros for IOP32x-based platforms
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <asm/arch/iop32x.h>
-
-        .macro  disable_fiq
-        .endm
-
-        .macro get_irqnr_preamble, base, tmp
-        mrc     p15, 0, \tmp, c15, c1, 0
-        orr     \tmp, \tmp, #(1 << 6)
-        mcr     p15, 0, \tmp, c15, c1, 0        @ Enable cp6 access
-        mrc     p15, 0, \tmp, c15, c1, 0
-        mov     \tmp, \tmp
-        sub     pc, pc, #4                      @ cp_wait
-        .endm
-
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        mrc     p6, 0, \irqstat, c8, c0, 0      @ Read IINTSRC
-        cmp     \irqstat, #0
-        clzne   \irqnr, \irqstat
-        rsbne   \irqnr, \irqnr, #31
-        .endm
-
-        .macro arch_ret_to_user, tmp1, tmp2
-        mrc     p15, 0, \tmp1, c15, c1, 0
-        ands    \tmp2, \tmp1, #(1 << 6)
-        bicne   \tmp1, \tmp1, #(1 << 6)
-        mcrne   p15, 0, \tmp1, c15, c1, 0       @ Disable cp6 access
-        .endm
diff --git a/include/asm-arm/arch-iop32x/glantank.h b/include/asm-arm/arch-iop32x/glantank.h
deleted file mode 100644
index bf0665acc1c1..000000000000
--- a/include/asm-arm/arch-iop32x/glantank.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * include/asm-arm/arch-iop32x/glantank.h
- *
- * IO-Data GLAN Tank board registers
- */
-
-#ifndef __GLANTANK_H
-#define __GLANTANK_H
-
-#define GLANTANK_UART           0xfe800000      /* UART */
-
-
-#endif
diff --git a/include/asm-arm/arch-iop32x/hardware.h b/include/asm-arm/arch-iop32x/hardware.h
deleted file mode 100644
index 6556ed5eee31..000000000000
--- a/include/asm-arm/arch-iop32x/hardware.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * include/asm-arm/arch-iop32x/hardware.h
- */
-
-#ifndef __HARDWARE_H
-#define __HARDWARE_H
-
-#include <asm/types.h>
-
-/*
- * Note about PCI IO space mappings
- *
- * To make IO space accesses efficient, we store virtual addresses in
- * the IO resources.
- *
- * The PCI IO space is located at virtual 0xfe000000 from physical
- * 0x90000000. The PCI BARs must be programmed with physical addresses,
- * but when we read them, we convert them to virtual addresses. See
- * arch/arm/plat-iop/pci.c.
- */
-#define pcibios_assign_all_busses() 1
-#define PCIBIOS_MIN_IO          0x00000000
-#define PCIBIOS_MIN_MEM         0x00000000
-
-#ifndef __ASSEMBLY__
-void iop32x_init_irq(void);
-#endif
-
-
-/*
- * Generic chipset bits
- */
-#include "iop32x.h"
-
-/*
- * Board specific bits
- */
-#include "glantank.h"
-#include "iq80321.h"
-#include "iq31244.h"
-#include "n2100.h"
-
-
-#endif
diff --git a/include/asm-arm/arch-iop32x/io.h b/include/asm-arm/arch-iop32x/io.h
deleted file mode 100644
index 47b2736236e4..000000000000
--- a/include/asm-arm/arch-iop32x/io.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * include/asm-arm/arch-iop32x/io.h
- *
- * Copyright (C) 2001 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __IO_H
-#define __IO_H
-
-#include <asm/arch/hardware.h>
-
-extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size,
-        unsigned int mtype);
-extern void __iop3xx_iounmap(void __iomem *addr);
-
-#define IO_SPACE_LIMIT          0xffffffff
-#define __io(p)         ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
-#define __mem_pci(a)            (a)
-
-#define __arch_ioremap(a, s, f) __iop3xx_ioremap(a, s, f)
-#define __arch_iounmap(a)        __iop3xx_iounmap(a)
-
-#endif
diff --git a/include/asm-arm/arch-iop32x/iop32x.h b/include/asm-arm/arch-iop32x/iop32x.h
deleted file mode 100644
index 0d8af57221a1..000000000000
--- a/include/asm-arm/arch-iop32x/iop32x.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * include/asm-arm/arch-iop32x/iop32x.h
- *
- * Intel IOP32X Chip definitions
- *
- * Author: Rory Bolt <rorybolt@pacbell.net>
- * Copyright (C) 2002 Rory Bolt
- * Copyright (C) 2004 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __IOP32X_H
-#define __IOP32X_H
-
-/*
- * Peripherals that are shared between the iop32x and iop33x but
- * located at different addresses.
- */
-#define IOP3XX_GPIO_REG(reg)    (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07c4 + (reg))
-#define IOP3XX_TIMER_REG(reg)   (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg))
-
-#include <asm/hardware/iop3xx.h>
-
-/* ATU Parameters
- * set up a 1:1 bus to physical ram relationship
- * w/ physical ram on top of pci in the memory map
- */
-#define IOP32X_MAX_RAM_SIZE            0x40000000UL
-#define IOP3XX_MAX_RAM_SIZE            IOP32X_MAX_RAM_SIZE
-#define IOP3XX_PCI_LOWER_MEM_BA        0x80000000
-#define IOP32X_PCI_MEM_WINDOW_SIZE     0x04000000
-#define IOP3XX_PCI_MEM_WINDOW_SIZE     IOP32X_PCI_MEM_WINDOW_SIZE
-
-#endif
diff --git a/include/asm-arm/arch-iop32x/iq31244.h b/include/asm-arm/arch-iop32x/iq31244.h
deleted file mode 100644
index fff4eafa1f6b..000000000000
--- a/include/asm-arm/arch-iop32x/iq31244.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * include/asm-arm/arch-iop32x/iq31244.h
- *
- * Intel IQ31244 evaluation board registers
- */
-
-#ifndef __IQ31244_H
-#define __IQ31244_H
-
-#define IQ31244_UART            0xfe800000      /* UART #1 */
-#define IQ31244_7SEG_1          0xfe840000      /* 7-Segment MSB */
-#define IQ31244_7SEG_0          0xfe850000      /* 7-Segment LSB (WO) */
-#define IQ31244_ROTARY_SW       0xfe8d0000      /* Rotary Switch */
-#define IQ31244_BATT_STAT       0xfe8f0000      /* Battery Status */
-
-
-#endif
diff --git a/include/asm-arm/arch-iop32x/iq80321.h b/include/asm-arm/arch-iop32x/iq80321.h
deleted file mode 100644
index eb69db9b9a06..000000000000
--- a/include/asm-arm/arch-iop32x/iq80321.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * include/asm-arm/arch-iop32x/iq80321.h
- *
- * Intel IQ80321 evaluation board registers
- */
-
-#ifndef __IQ80321_H
-#define __IQ80321_H
-
-#define IQ80321_UART            0xfe800000      /* UART #1 */
-#define IQ80321_7SEG_1          0xfe840000      /* 7-Segment MSB */
-#define IQ80321_7SEG_0          0xfe850000      /* 7-Segment LSB (WO) */
-#define IQ80321_ROTARY_SW       0xfe8d0000      /* Rotary Switch */
-#define IQ80321_BATT_STAT       0xfe8f0000      /* Battery Status */
-
-
-#endif
diff --git a/include/asm-arm/arch-iop32x/irqs.h b/include/asm-arm/arch-iop32x/irqs.h
deleted file mode 100644
index bbaef873afce..000000000000
--- a/include/asm-arm/arch-iop32x/irqs.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * include/asm-arm/arch-iop32x/irqs.h
- *
- * Author:      Rory Bolt <rorybolt@pacbell.net>
- * Copyright:   (C) 2002 Rory Bolt
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __IRQS_H
-#define __IRQS_H
-
-/*
- * IOP80321 chipset interrupts
- */
-#define IRQ_IOP32X_DMA0_EOT     0
-#define IRQ_IOP32X_DMA0_EOC     1
-#define IRQ_IOP32X_DMA1_EOT     2
-#define IRQ_IOP32X_DMA1_EOC     3
-#define IRQ_IOP32X_AA_EOT       6
-#define IRQ_IOP32X_AA_EOC       7
-#define IRQ_IOP32X_CORE_PMON    8
-#define IRQ_IOP32X_TIMER0       9
-#define IRQ_IOP32X_TIMER1       10
-#define IRQ_IOP32X_I2C_0        11
-#define IRQ_IOP32X_I2C_1        12
-#define IRQ_IOP32X_MESSAGING    13
-#define IRQ_IOP32X_ATU_BIST     14
-#define IRQ_IOP32X_PERFMON      15
-#define IRQ_IOP32X_CORE_PMU     16
-#define IRQ_IOP32X_BIU_ERR      17
-#define IRQ_IOP32X_ATU_ERR      18
-#define IRQ_IOP32X_MCU_ERR      19
-#define IRQ_IOP32X_DMA0_ERR     20
-#define IRQ_IOP32X_DMA1_ERR     21
-#define IRQ_IOP32X_AA_ERR       23
-#define IRQ_IOP32X_MSG_ERR      24
-#define IRQ_IOP32X_SSP          25
-#define IRQ_IOP32X_XINT0        27
-#define IRQ_IOP32X_XINT1        28
-#define IRQ_IOP32X_XINT2        29
-#define IRQ_IOP32X_XINT3        30
-#define IRQ_IOP32X_HPI          31
-
-#define NR_IRQS                 32
-
-
-#endif
diff --git a/include/asm-arm/arch-iop32x/memory.h b/include/asm-arm/arch-iop32x/memory.h
deleted file mode 100644
index bdcf03895ee0..000000000000
--- a/include/asm-arm/arch-iop32x/memory.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * include/asm-arm/arch-iop32x/memory.h
- */
-
-#ifndef __MEMORY_H
-#define __MEMORY_H
-
-#include <asm/arch/hardware.h>
-
-/*
- * Physical DRAM offset.
- */
-#define PHYS_OFFSET     UL(0xa0000000)
-
-/*
- * Virtual view <-> PCI DMA view memory address translations
- * virt_to_bus: Used to translate the virtual address to an
- *              address suitable to be passed to set_dma_addr
- * bus_to_virt: Used to convert an address for DMA operations
- *              to an address that the kernel can use.
- */
-#define __virt_to_bus(x)        (__virt_to_phys(x))
-#define __bus_to_virt(x)        (__phys_to_virt(x))
-
-
-#endif
diff --git a/include/asm-arm/arch-iop32x/n2100.h b/include/asm-arm/arch-iop32x/n2100.h
deleted file mode 100644
index 77a8af476629..000000000000
--- a/include/asm-arm/arch-iop32x/n2100.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * include/asm-arm/arch-iop32x/n2100.h
- *
- * Thecus N2100 board registers
- */
-
-#ifndef __N2100_H
-#define __N2100_H
-
-#define N2100_UART              0xfe800000      /* UART */
-
-#define N2100_COPY_BUTTON       IOP3XX_GPIO_LINE(0)
-#define N2100_PCA9532_RESET     IOP3XX_GPIO_LINE(2)
-#define N2100_RESET_BUTTON      IOP3XX_GPIO_LINE(3)
-#define N2100_HARDWARE_RESET    IOP3XX_GPIO_LINE(4)
-#define N2100_POWER_BUTTON      IOP3XX_GPIO_LINE(5)
-
-
-#endif
diff --git a/include/asm-arm/arch-iop32x/system.h b/include/asm-arm/arch-iop32x/system.h
deleted file mode 100644
index 17b7eb7e9c0d..000000000000
--- a/include/asm-arm/arch-iop32x/system.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * include/asm-arm/arch-iop32x/system.h
- *
- * Copyright (C) 2001 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <asm/mach-types.h>
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-static inline void arch_reset(char mode)
-{
-        local_irq_disable();
-
-        if (machine_is_n2100()) {
-                gpio_line_set(N2100_HARDWARE_RESET, GPIO_LOW);
-                gpio_line_config(N2100_HARDWARE_RESET, GPIO_OUT);
-                while (1)
-                        ;
-        }
-
-        *IOP3XX_PCSR = 0x30;
-
-        /* Jump into ROM at address 0 */
-        cpu_reset(0);
-}
diff --git a/include/asm-arm/arch-iop32x/timex.h b/include/asm-arm/arch-iop32x/timex.h
deleted file mode 100644
index 445704619825..000000000000
--- a/include/asm-arm/arch-iop32x/timex.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * include/asm-arm/arch-iop32x/timex.h
- *
- * IOP32x architecture timex specifications
- */
-
-#include <asm/arch/hardware.h>
-
-#define CLOCK_TICK_RATE         (100 * HZ)
diff --git a/include/asm-arm/arch-iop32x/uncompress.h b/include/asm-arm/arch-iop32x/uncompress.h
deleted file mode 100644
index 07028786394e..000000000000
--- a/include/asm-arm/arch-iop32x/uncompress.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * include/asm-arm/arch-iop32x/uncompress.h
- */
-
-#include <asm/types.h>
-#include <asm/mach-types.h>
-#include <linux/serial_reg.h>
-#include <asm/arch/hardware.h>
-
-static volatile u8 *uart_base;
-
-#define TX_DONE         (UART_LSR_TEMT | UART_LSR_THRE)
-
-static inline void putc(char c)
-{
-        while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
-                barrier();
-        uart_base[UART_TX] = c;
-}
-
-static inline void flush(void)
-{
-}
-
-static __inline__ void __arch_decomp_setup(unsigned long arch_id)
-{
-        if (machine_is_iq80321())
-                uart_base = (volatile u8 *)IQ80321_UART;
-        else if (machine_is_iq31244() || machine_is_em7210())
-                uart_base = (volatile u8 *)IQ31244_UART;
-        else
-                uart_base = (volatile u8 *)0xfe800000;
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()     __arch_decomp_setup(arch_id)
-#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-iop32x/vmalloc.h b/include/asm-arm/arch-iop32x/vmalloc.h
deleted file mode 100644
index 0a70baa19517..000000000000
--- a/include/asm-arm/arch-iop32x/vmalloc.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * include/asm-arm/arch-iop32x/vmalloc.h
- */
-
-#define VMALLOC_END     0xfe000000
diff --git a/include/asm-arm/arch-iop33x/debug-macro.S b/include/asm-arm/arch-iop33x/debug-macro.S
deleted file mode 100644
index 9e7132ebe6a7..000000000000
--- a/include/asm-arm/arch-iop33x/debug-macro.S
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * include/asm-arm/arch-iop33x/debug-macro.S
- *
- * Debugging macro include header
- *
- * Copyright (C) 1994-1999 Russell King
- * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-                .macro  addruart, rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ mmu enabled?
-                moveq   \rx, #0xff000000        @ physical
-                movne   \rx, #0xfe000000        @ virtual
-                orr     \rx, \rx, #0x00ff0000
-                orr     \rx, \rx, #0x0000f700
-                .endm
-
-#define UART_SHIFT      2
-#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-iop33x/dma.h b/include/asm-arm/arch-iop33x/dma.h
deleted file mode 100644
index b7775fdc5ad3..000000000000
--- a/include/asm-arm/arch-iop33x/dma.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * include/asm-arm/arch-iop33x/dma.h
- *
- * Copyright (C) 2004 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
diff --git a/include/asm-arm/arch-iop33x/entry-macro.S b/include/asm-arm/arch-iop33x/entry-macro.S
deleted file mode 100644
index b8e3d449e882..000000000000
--- a/include/asm-arm/arch-iop33x/entry-macro.S
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * include/asm-arm/arch-iop33x/entry-macro.S
- *
- * Low-level IRQ helper macros for IOP33x-based platforms
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <asm/arch/iop33x.h>
-
-        .macro  disable_fiq
-        .endm
-
-        .macro get_irqnr_preamble, base, tmp
-        mrc     p15, 0, \tmp, c15, c1, 0
-        orr     \tmp, \tmp, #(1 << 6)
-        mcr     p15, 0, \tmp, c15, c1, 0        @ Enable cp6 access
-        mrc     p15, 0, \tmp, c15, c1, 0
-        mov     \tmp, \tmp
-        sub     pc, pc, #4                      @ cp_wait
-        .endm
-
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        mrc     p6, 0, \irqstat, c14, c0, 0     @ Read IINTVEC
-        cmp     \irqstat, #0
-        mrceq   p6, 0, \irqstat, c14, c0, 0     @ erratum 63 workaround
-        adds    \irqnr, \irqstat, #1
-        movne   \irqnr, \irqstat, lsr #2
-        .endm
-
-        .macro arch_ret_to_user, tmp1, tmp2
-        mrc     p15, 0, \tmp1, c15, c1, 0
-        ands    \tmp2, \tmp1, #(1 << 6)
-        bicne   \tmp1, \tmp1, #(1 << 6)
-        mcrne   p15, 0, \tmp1, c15, c1, 0       @ Disable cp6 access
-        .endm
diff --git a/include/asm-arm/arch-iop33x/hardware.h b/include/asm-arm/arch-iop33x/hardware.h
deleted file mode 100644
index 0659cf94d040..000000000000
--- a/include/asm-arm/arch-iop33x/hardware.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * include/asm-arm/arch-iop33x/hardware.h
- */
-
-#ifndef __HARDWARE_H
-#define __HARDWARE_H
-
-#include <asm/types.h>
-
-/*
- * Note about PCI IO space mappings
- *
- * To make IO space accesses efficient, we store virtual addresses in
- * the IO resources.
- *
- * The PCI IO space is located at virtual 0xfe000000 from physical
- * 0x90000000.  The PCI BARs must be programmed with physical addresses,
- * but when we read them, we convert them to virtual addresses.  See
- * arch/arm/mach-iop3xx/iop3xx-pci.c
- */
-#define pcibios_assign_all_busses()     1
-#define PCIBIOS_MIN_IO          0x00000000
-#define PCIBIOS_MIN_MEM         0x00000000
-
-#ifndef __ASSEMBLY__
-void iop33x_init_irq(void);
-
-extern struct platform_device iop33x_uart0_device;
-extern struct platform_device iop33x_uart1_device;
-#endif
-
-
-/*
- * Generic chipset bits
- *
- */
-#include "iop33x.h"
-
-/*
- * Board specific bits
- */
-#include "iq80331.h"
-#include "iq80332.h"
-
-
-#endif
diff --git a/include/asm-arm/arch-iop33x/io.h b/include/asm-arm/arch-iop33x/io.h
deleted file mode 100644
index 3fc607c46f03..000000000000
--- a/include/asm-arm/arch-iop33x/io.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * include/asm-arm/arch-iop33x/io.h
- *
- * Copyright (C) 2001  MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __IO_H
-#define __IO_H
-
-#include <asm/arch/hardware.h>
-
-extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size,
-        unsigned int mtype);
-extern void __iop3xx_iounmap(void __iomem *addr);
-
-#define IO_SPACE_LIMIT          0xffffffff
-#define __io(p)         ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
-#define __mem_pci(a)            (a)
-
-#define __arch_ioremap(a, s, f) __iop3xx_ioremap(a, s, f)
-#define __arch_iounmap(a)        __iop3xx_iounmap(a)
-
-#endif
diff --git a/include/asm-arm/arch-iop33x/iop33x.h b/include/asm-arm/arch-iop33x/iop33x.h
deleted file mode 100644
index 766985b9a723..000000000000
--- a/include/asm-arm/arch-iop33x/iop33x.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * include/asm-arm/arch-iop33x/iop33x.h
- *
- * Intel IOP33X Chip definitions
- *
- * Author: Dave Jiang (dave.jiang@intel.com)
- * Copyright (C) 2003, 2004 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __IOP33X_H
-#define __IOP33X_H
-
-/*
- * Peripherals that are shared between the iop32x and iop33x but
- * located at different addresses.
- */
-#define IOP3XX_GPIO_REG(reg)    (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1780 + (reg))
-#define IOP3XX_TIMER_REG(reg)   (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07d0 + (reg))
-
-#include <asm/hardware/iop3xx.h>
-
-/* UARTs  */
-#define IOP33X_UART0_PHYS       (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1700)
-#define IOP33X_UART0_VIRT       (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1700)
-#define IOP33X_UART1_PHYS       (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1740)
-#define IOP33X_UART1_VIRT       (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1740)
-
-/* ATU Parameters
- * set up a 1:1 bus to physical ram relationship
- * w/ pci on top of physical ram in memory map
- */
-#define IOP33X_MAX_RAM_SIZE             0x80000000UL
-#define IOP3XX_MAX_RAM_SIZE             IOP33X_MAX_RAM_SIZE
-#define IOP3XX_PCI_LOWER_MEM_BA (PHYS_OFFSET + IOP33X_MAX_RAM_SIZE)
-#define IOP33X_PCI_MEM_WINDOW_SIZE      0x08000000
-#define IOP3XX_PCI_MEM_WINDOW_SIZE      IOP33X_PCI_MEM_WINDOW_SIZE
-
-
-#endif
diff --git a/include/asm-arm/arch-iop33x/iq80331.h b/include/asm-arm/arch-iop33x/iq80331.h
deleted file mode 100644
index 79b9302017ea..000000000000
--- a/include/asm-arm/arch-iop33x/iq80331.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * include/asm-arm/arch-iop33x/iq80331.h
- *
- * Intel IQ80331 evaluation board registers
- */
-
-#ifndef __IQ80331_H
-#define __IQ80331_H
-
-#define IQ80331_7SEG_1          0xce840000      /* 7-Segment MSB */
-#define IQ80331_7SEG_0          0xce850000      /* 7-Segment LSB (WO) */
-#define IQ80331_ROTARY_SW       0xce8d0000      /* Rotary Switch */
-#define IQ80331_BATT_STAT       0xce8f0000      /* Battery Status */
-
-
-#endif
diff --git a/include/asm-arm/arch-iop33x/iq80332.h b/include/asm-arm/arch-iop33x/iq80332.h
deleted file mode 100644
index 053165629492..000000000000
--- a/include/asm-arm/arch-iop33x/iq80332.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * include/asm-arm/arch-iop33x/iq80332.h
- *
- * Intel IQ80332 evaluation board registers
- */
-
-#ifndef __IQ80332_H
-#define __IQ80332_H
-
-#define IQ80332_7SEG_1          0xce840000      /* 7-Segment MSB */
-#define IQ80332_7SEG_0          0xce850000      /* 7-Segment LSB (WO) */
-#define IQ80332_ROTARY_SW       0xce8d0000      /* Rotary Switch */
-#define IQ80332_BATT_STAT       0xce8f0000      /* Battery Status */
-
-
-#endif
diff --git a/include/asm-arm/arch-iop33x/irqs.h b/include/asm-arm/arch-iop33x/irqs.h
deleted file mode 100644
index d045f8403396..000000000000
--- a/include/asm-arm/arch-iop33x/irqs.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * include/asm-arm/arch-iop33x/irqs.h
- *
- * Author:      Dave Jiang (dave.jiang@intel.com)
- * Copyright:   (C) 2003 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __IRQS_H
-#define __IRQS_H
-
-/*
- * IOP80331 chipset interrupts
- */
-#define IRQ_IOP33X_DMA0_EOT     0
-#define IRQ_IOP33X_DMA0_EOC     1
-#define IRQ_IOP33X_DMA1_EOT     2
-#define IRQ_IOP33X_DMA1_EOC     3
-#define IRQ_IOP33X_AA_EOT       6
-#define IRQ_IOP33X_AA_EOC       7
-#define IRQ_IOP33X_TIMER0       8
-#define IRQ_IOP33X_TIMER1       9
-#define IRQ_IOP33X_I2C_0        10
-#define IRQ_IOP33X_I2C_1        11
-#define IRQ_IOP33X_MSG          12
-#define IRQ_IOP33X_MSGIBQ       13
-#define IRQ_IOP33X_ATU_BIST     14
-#define IRQ_IOP33X_PERFMON      15
-#define IRQ_IOP33X_CORE_PMU     16
-#define IRQ_IOP33X_XINT0        24
-#define IRQ_IOP33X_XINT1        25
-#define IRQ_IOP33X_XINT2        26
-#define IRQ_IOP33X_XINT3        27
-#define IRQ_IOP33X_XINT8        32
-#define IRQ_IOP33X_XINT9        33
-#define IRQ_IOP33X_XINT10       34
-#define IRQ_IOP33X_XINT11       35
-#define IRQ_IOP33X_XINT12       36
-#define IRQ_IOP33X_XINT13       37
-#define IRQ_IOP33X_XINT14       38
-#define IRQ_IOP33X_XINT15       39
-#define IRQ_IOP33X_UART0        51
-#define IRQ_IOP33X_UART1        52
-#define IRQ_IOP33X_PBIE         53
-#define IRQ_IOP33X_ATU_CRW      54
-#define IRQ_IOP33X_ATU_ERR      55
-#define IRQ_IOP33X_MCU_ERR      56
-#define IRQ_IOP33X_DMA0_ERR     57
-#define IRQ_IOP33X_DMA1_ERR     58
-#define IRQ_IOP33X_AA_ERR       60
-#define IRQ_IOP33X_MSG_ERR      62
-#define IRQ_IOP33X_HPI          63
-
-#define NR_IRQS                 64
-
-
-#endif
diff --git a/include/asm-arm/arch-iop33x/memory.h b/include/asm-arm/arch-iop33x/memory.h
deleted file mode 100644
index d798d83c83a5..000000000000
--- a/include/asm-arm/arch-iop33x/memory.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * include/asm-arm/arch-iop33x/memory.h
- */
-
-#ifndef __MEMORY_H
-#define __MEMORY_H
-
-#include <asm/arch/hardware.h>
-
-/*
- * Physical DRAM offset.
- */
-#define PHYS_OFFSET     UL(0x00000000)
-
-/*
- * Virtual view <-> PCI DMA view memory address translations
- * virt_to_bus: Used to translate the virtual address to an
- *              address suitable to be passed to set_dma_addr
- * bus_to_virt: Used to convert an address for DMA operations
- *              to an address that the kernel can use.
- */
-#define __virt_to_bus(x)        (__virt_to_phys(x))
-#define __bus_to_virt(x)        (__phys_to_virt(x))
-
-
-#endif
diff --git a/include/asm-arm/arch-iop33x/system.h b/include/asm-arm/arch-iop33x/system.h
deleted file mode 100644
index 00dd07ece262..000000000000
--- a/include/asm-arm/arch-iop33x/system.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * include/asm-arm/arch-iop33x/system.h
- *
- * Copyright (C) 2001 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-static inline void arch_reset(char mode)
-{
-        *IOP3XX_PCSR = 0x30;
-
-        /* Jump into ROM at address 0 */
-        cpu_reset(0);
-}
diff --git a/include/asm-arm/arch-iop33x/timex.h b/include/asm-arm/arch-iop33x/timex.h
deleted file mode 100644
index 75a001e93daf..000000000000
--- a/include/asm-arm/arch-iop33x/timex.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * include/asm-arm/arch-iop33x/timex.h
- *
- * IOP3xx architecture timex specifications
- */
-
-#include <asm/arch/hardware.h>
-
-#define CLOCK_TICK_RATE         (100 * HZ)
diff --git a/include/asm-arm/arch-iop33x/uncompress.h b/include/asm-arm/arch-iop33x/uncompress.h
deleted file mode 100644
index 34d9e8e8287a..000000000000
--- a/include/asm-arm/arch-iop33x/uncompress.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * include/asm-arm/arch-iop33x/uncompress.h
- */
-
-#include <asm/types.h>
-#include <asm/mach-types.h>
-#include <linux/serial_reg.h>
-#include <asm/arch/hardware.h>
-
-static volatile u32 *uart_base;
-
-#define TX_DONE         (UART_LSR_TEMT | UART_LSR_THRE)
-
-static inline void putc(char c)
-{
-        while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
-                barrier();
-        uart_base[UART_TX] = c;
-}
-
-static inline void flush(void)
-{
-}
-
-static __inline__ void __arch_decomp_setup(unsigned long arch_id)
-{
-        if (machine_is_iq80331() || machine_is_iq80332())
-                uart_base = (volatile u32 *)IOP33X_UART0_PHYS;
-        else
-                uart_base = (volatile u32 *)0xfe800000;
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()     __arch_decomp_setup(arch_id)
-#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-iop33x/vmalloc.h b/include/asm-arm/arch-iop33x/vmalloc.h
deleted file mode 100644
index 66f545a7f4fc..000000000000
--- a/include/asm-arm/arch-iop33x/vmalloc.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * include/asm-arm/arch-iop33x/vmalloc.h
- */
-
-#define VMALLOC_END     0xfe000000
diff --git a/include/asm-arm/arch-ixp2000/debug-macro.S b/include/asm-arm/arch-ixp2000/debug-macro.S
deleted file mode 100644
index bc8b39654793..000000000000
--- a/include/asm-arm/arch-ixp2000/debug-macro.S
+++ /dev/null
@@ -1,27 +0,0 @@
-/* linux/include/asm-arm/arch-ixp2000/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-                .macro  addruart,rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx, #0xc0000000        @ Physical base
-                movne   \rx, #0xfe000000        @ virtual base
-                orrne   \rx, \rx, #0x00f00000
-                orr     \rx, \rx, #0x00030000
-#ifdef  __ARMEB__
-                orr     \rx, \rx, #0x00000003
-#endif
-                .endm
-
-#define UART_SHIFT      2
-#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-ixp2000/dma.h b/include/asm-arm/arch-ixp2000/dma.h
deleted file mode 100644
index 548d8dc507eb..000000000000
--- a/include/asm-arm/arch-ixp2000/dma.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ixp2000/dma.h
- *
- * Copyright (C) 2002 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
diff --git a/include/asm-arm/arch-ixp2000/enp2611.h b/include/asm-arm/arch-ixp2000/enp2611.h
deleted file mode 100644
index 42f3c28dc5c4..000000000000
--- a/include/asm-arm/arch-ixp2000/enp2611.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * include/asm-arm/arch-ixp2000/enp2611.h
- *
- * Register and other defines for Radisys ENP-2611
- *
- * Created 2004 by Lennert Buytenhek from the ixdp2x01 code.  The
- * original version carries the following notices:
- *
- * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
- * Maintainer: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright (C) 2002 Intel Corp.
- * Copyright (C) 2003-2004 MontaVista Software, Inc.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- */
-
-#ifndef __ENP2611_H
-#define __ENP2611_H
-
-#define ENP2611_CALEB_PHYS_BASE         0xc5000000
-#define ENP2611_CALEB_VIRT_BASE         0xfe000000
-#define ENP2611_CALEB_SIZE              0x00100000
-
-#define ENP2611_PM3386_0_PHYS_BASE      0xc6000000
-#define ENP2611_PM3386_0_VIRT_BASE      0xfe100000
-#define ENP2611_PM3386_0_SIZE           0x00100000
-
-#define ENP2611_PM3386_1_PHYS_BASE      0xc6400000
-#define ENP2611_PM3386_1_VIRT_BASE      0xfe200000
-#define ENP2611_PM3386_1_SIZE           0x00100000
-
-#define ENP2611_GPIO_SCL                7
-#define ENP2611_GPIO_SDA                6
-
-#define IRQ_ENP2611_THERMAL             IRQ_IXP2000_GPIO4
-#define IRQ_ENP2611_OPTION_BOARD        IRQ_IXP2000_GPIO3
-#define IRQ_ENP2611_CALEB               IRQ_IXP2000_GPIO2
-#define IRQ_ENP2611_PM3386_1            IRQ_IXP2000_GPIO1
-#define IRQ_ENP2611_PM3386_0            IRQ_IXP2000_GPIO0
-
-
-#endif
diff --git a/include/asm-arm/arch-ixp2000/entry-macro.S b/include/asm-arm/arch-ixp2000/entry-macro.S
deleted file mode 100644
index 11d512ad5945..000000000000
--- a/include/asm-arm/arch-ixp2000/entry-macro.S
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * include/asm-arm/arch-ixp2000/entry-macro.S
- *
- * Low-level IRQ helper macros for IXP2000-based platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <asm/arch/irqs.h>
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-
-                mov     \irqnr, #0x0              @clear out irqnr as default
-                mov     \base, #0xfe000000
-                orr     \base, \base, #0x00e00000
-                orr     \base, \base, #0x08
-                ldr     \irqstat, [\base]         @ get interrupts
-
-                cmp     \irqstat, #0
-                beq     1001f
-
-                clz     \irqnr, \irqstat
-                mov     \base, #31
-                subs    \irqnr, \base, \irqnr
-
-                /*
-                 * We handle PCIA and PCIB here so we don't have an
-                 * extra layer of code just to check these two bits.
-                 */
-                cmp     \irqnr, #IRQ_IXP2000_PCI
-                bne     1001f
-
-                mov     \base, #0xfe000000
-                orr     \base, \base, #0x00c00000
-                orr     \base, \base, #0x00000100
-                orr     \base, \base, #0x00000058
-                ldr     \irqstat, [\base]
-
-                mov     \tmp, #(1<<26)
-                tst     \irqstat, \tmp
-                movne   \irqnr, #IRQ_IXP2000_PCIA
-                bne     1001f
-
-                mov     \tmp, #(1<<27)
-                tst     \irqstat, \tmp
-                movne   \irqnr, #IRQ_IXP2000_PCIB
-
-1001:
-                .endm
-
diff --git a/include/asm-arm/arch-ixp2000/gpio.h b/include/asm-arm/arch-ixp2000/gpio.h
deleted file mode 100644
index 03cbbe1fd9d8..000000000000
--- a/include/asm-arm/arch-ixp2000/gpio.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * include/asm-arm/arch-ixp2000/gpio.h
- *
- * Copyright (C) 2002 Intel Corporation.
- *
- * This program is free software, you can redistribute it and/or modify 
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-/*
- * IXP2000 GPIO in/out, edge/level detection for IRQs:
- * IRQs are generated on Falling-edge, Rising-Edge, Level-low, Level-High
- * or both Falling-edge and Rising-edge.  
- * This must be called *before* the corresponding IRQ is registerd.
- * Use this instead of directly setting the GPIO registers.
- * GPIOs may also be used as GPIOs (e.g. for emulating i2c/smb)
- */
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H
-
-#ifndef __ASSEMBLY__
-
-#define GPIO_IN                         0
-#define GPIO_OUT                        1
-
-#define IXP2000_GPIO_LOW                0
-#define IXP2000_GPIO_HIGH               1
-
-extern void gpio_line_config(int line, int direction);
-
-static inline int gpio_line_get(int line)
-{
-        return (((*IXP2000_GPIO_PLR) >> line) & 1);
-}
-
-static inline void gpio_line_set(int line, int value)
-{
-        if (value == IXP2000_GPIO_HIGH) {
-                ixp2000_reg_write(IXP2000_GPIO_POSR, 1 << line);
-        } else if (value == IXP2000_GPIO_LOW) {
-                ixp2000_reg_write(IXP2000_GPIO_POCR, 1 << line);
-        }
-}
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* ASM_ARCH_IXP2000_GPIO_H_ */
diff --git a/include/asm-arm/arch-ixp2000/hardware.h b/include/asm-arm/arch-ixp2000/hardware.h
deleted file mode 100644
index e7ea781c48aa..000000000000
--- a/include/asm-arm/arch-ixp2000/hardware.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ixp2000/hardware.h
- *
- * Hardware definitions for IXP2400/2800 based systems
- *
- * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
- *
- * Maintainer: Deepak Saxena <dsaxena@mvista.com>
- *
- * Copyright (C) 2001-2002 Intel Corp.
- * Copyright (C) 2003-2004 MontaVista Software, Inc.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H__
-#define __ASM_ARCH_HARDWARE_H__
-
-/*
- * This needs to be platform-specific?
- */
-#define PCIBIOS_MIN_IO          0x00000000
-#define PCIBIOS_MIN_MEM         0x00000000
-
-#include "ixp2000-regs.h"       /* Chipset Registers */
-
-#define pcibios_assign_all_busses() 0
-
-/*
- * Platform helper functions
- */
-#include "platform.h"
-
-/*
- * Platform-specific bits
- */
-#include "enp2611.h"            /* ENP-2611 */
-#include "ixdp2x00.h"           /* IXDP2400/2800 */
-#include "ixdp2x01.h"           /* IXDP2401/2801 */
-
-#endif  /* _ASM_ARCH_HARDWARE_H__ */
diff --git a/include/asm-arm/arch-ixp2000/io.h b/include/asm-arm/arch-ixp2000/io.h
deleted file mode 100644
index 5dc1d25dcb4f..000000000000
--- a/include/asm-arm/arch-ixp2000/io.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ixp2000/io.h
- *
- * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
- * Maintainer: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright (C) 2002  Intel Corp.
- * Copyrgiht (C) 2003-2004 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#include <asm/arch/hardware.h>
-
-#define IO_SPACE_LIMIT          0xffffffff
-#define __mem_pci(a)            (a)
-
-/*
- * The A? revisions of the IXP2000s assert byte lanes for PCI I/O
- * transactions the other way round (MEM transactions don't have this
- * issue), so if we want to support those models, we need to override
- * the standard I/O functions.
- *
- * B0 and later have a bit that can be set to 1 to get the proper
- * behavior for I/O transactions, which then allows us to use the
- * standard I/O functions.  This is what we do if the user does not
- * explicitly ask for support for pre-B0.
- */
-#ifdef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO
-#define ___io(p)                ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
-
-#define alignb(addr)            (void __iomem *)((unsigned long)(addr) ^ 3)
-#define alignw(addr)            (void __iomem *)((unsigned long)(addr) ^ 2)
-
-#define outb(v,p)               __raw_writeb((v),alignb(___io(p)))
-#define outw(v,p)               __raw_writew((v),alignw(___io(p)))
-#define outl(v,p)               __raw_writel((v),___io(p))
-
-#define inb(p)          ({ unsigned int __v = __raw_readb(alignb(___io(p))); __v; })
-#define inw(p)          \
-        ({ unsigned int __v = (__raw_readw(alignw(___io(p)))); __v; })
-#define inl(p)          \
-        ({ unsigned int __v = (__raw_readl(___io(p))); __v; })
-
-#define outsb(p,d,l)            __raw_writesb(alignb(___io(p)),d,l)
-#define outsw(p,d,l)            __raw_writesw(alignw(___io(p)),d,l)
-#define outsl(p,d,l)            __raw_writesl(___io(p),d,l)
-
-#define insb(p,d,l)             __raw_readsb(alignb(___io(p)),d,l)
-#define insw(p,d,l)             __raw_readsw(alignw(___io(p)),d,l)
-#define insl(p,d,l)             __raw_readsl(___io(p),d,l)
-
-#define __is_io_address(p)      ((((unsigned long)(p)) & ~(IXP2000_PCI_IO_SIZE - 1)) == IXP2000_PCI_IO_VIRT_BASE)
-
-#define ioread8(p)                                              \
-        ({                                                      \
-                unsigned int __v;                               \
-                                                                \
-                if (__is_io_address(p)) {                       \
-                        __v = __raw_readb(alignb(p));           \
-                } else {                                        \
-                        __v = __raw_readb(p);                   \
-                }                                               \
-                                                                \
-                __v;                                            \
-        })                                                      \
-
-#define ioread16(p)                                             \
-        ({                                                      \
-                unsigned int __v;                               \
-                                                                \
-                if (__is_io_address(p)) {                       \
-                        __v = __raw_readw(alignw(p));           \
-                } else {                                        \
-                        __v = le16_to_cpu(__raw_readw(p));      \
-                }                                               \
-                                                                \
-                __v;                                            \
-        })
-
-#define ioread32(p)                                             \
-        ({                                                      \
-                unsigned int __v;                               \
-                                                                \
-                if (__is_io_address(p)) {                       \
-                        __v = __raw_readl(p);                   \
-                } else {                                        \
-                        __v = le32_to_cpu(__raw_readl(p));      \
-                }                                               \
-                                                                \
-                 __v;                                           \
-        })
-
-#define iowrite8(v,p)                                           \
-        ({                                                      \
-                if (__is_io_address(p)) {                       \
-                        __raw_writeb((v), alignb(p));           \
-                } else {                                        \
-                        __raw_writeb((v), p);                   \
-                }                                               \
-        })
-
-#define iowrite16(v,p)                                          \
-        ({                                                      \
-                if (__is_io_address(p)) {                       \
-                        __raw_writew((v), alignw(p));           \
-                } else {                                        \
-                        __raw_writew(cpu_to_le16(v), p);        \
-                }                                               \
-        })
-
-#define iowrite32(v,p)                                          \
-        ({                                                      \
-                if (__is_io_address(p)) {                       \
-                        __raw_writel((v), p);                   \
-                } else {                                        \
-                        __raw_writel(cpu_to_le32(v), p);        \
-                }                                               \
-        })
-
-#define ioport_map(port, nr)    ___io(port)
-
-#define ioport_unmap(addr)
-#else
-#define __io(p)                 ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
-#endif
-
-
-#endif
diff --git a/include/asm-arm/arch-ixp2000/irqs.h b/include/asm-arm/arch-ixp2000/irqs.h
deleted file mode 100644
index 62f09c7ff420..000000000000
--- a/include/asm-arm/arch-ixp2000/irqs.h
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ixp2000/irqs.h
- *
- * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
- * Maintainer: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright (C) 2002 Intel Corp.
- * Copyright (C) 2003-2004 MontaVista Software, Inc.
- * 
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef _IRQS_H
-#define _IRQS_H
-
-/*
- * Do NOT add #ifdef MACHINE_FOO in here.
- * Simpy add your machine IRQs here and increase NR_IRQS if needed to
- * hold your machine's IRQ table.
- */
-
-/*
- * Some interrupt numbers go unused b/c the IRQ mask/ummask/status
- * register has those bit reserved. We just mark those interrupts
- * as invalid and this allows us to do mask/unmask with a single
- * shift operation instead of having to map the IRQ number to
- * a HW IRQ number.
- */
-#define IRQ_IXP2000_SOFT_INT            0 /* soft interrupt */
-#define IRQ_IXP2000_ERRSUM              1 /* OR of all bits in ErrorStatus reg*/
-#define IRQ_IXP2000_UART                2
-#define IRQ_IXP2000_GPIO                3
-#define IRQ_IXP2000_TIMER1              4
-#define IRQ_IXP2000_TIMER2              5
-#define IRQ_IXP2000_TIMER3              6
-#define IRQ_IXP2000_TIMER4              7
-#define IRQ_IXP2000_PMU                 8               
-#define IRQ_IXP2000_SPF                 9  /* Slow port framer IRQ */
-#define IRQ_IXP2000_DMA1                10
-#define IRQ_IXP2000_DMA2                11
-#define IRQ_IXP2000_DMA3                12
-#define IRQ_IXP2000_PCI_DOORBELL        13
-#define IRQ_IXP2000_ME_ATTN             14 
-#define IRQ_IXP2000_PCI                 15 /* PCI INTA or INTB */
-#define IRQ_IXP2000_THDA0               16 /* thread 0-31A */
-#define IRQ_IXP2000_THDA1               17 /* thread 32-63A, IXP2800 only */
-#define IRQ_IXP2000_THDA2               18 /* thread 64-95A */
-#define IRQ_IXP2000_THDA3               19 /* thread 96-127A, IXP2800 only */
-#define IRQ_IXP2000_THDB0               24 /* thread 0-31B */
-#define IRQ_IXP2000_THDB1               25 /* thread 32-63B, IXP2800 only */
-#define IRQ_IXP2000_THDB2               26 /* thread 64-95B */
-#define IRQ_IXP2000_THDB3               27 /* thread 96-127B, IXP2800 only */
-
-/* define generic GPIOs */
-#define IRQ_IXP2000_GPIO0               32
-#define IRQ_IXP2000_GPIO1               33
-#define IRQ_IXP2000_GPIO2               34
-#define IRQ_IXP2000_GPIO3               35
-#define IRQ_IXP2000_GPIO4               36
-#define IRQ_IXP2000_GPIO5               37
-#define IRQ_IXP2000_GPIO6               38
-#define IRQ_IXP2000_GPIO7               39
-
-/* split off the 2 PCI sources */
-#define IRQ_IXP2000_PCIA                40
-#define IRQ_IXP2000_PCIB                41
-
-/* Int sources from IRQ_ERROR_STATUS */
-#define IRQ_IXP2000_DRAM0_MIN_ERR       42
-#define IRQ_IXP2000_DRAM0_MAJ_ERR       43
-#define IRQ_IXP2000_DRAM1_MIN_ERR       44
-#define IRQ_IXP2000_DRAM1_MAJ_ERR       45
-#define IRQ_IXP2000_DRAM2_MIN_ERR       46
-#define IRQ_IXP2000_DRAM2_MAJ_ERR       47
-/* 48-57 reserved */
-#define IRQ_IXP2000_SRAM0_ERR           58
-#define IRQ_IXP2000_SRAM1_ERR           59
-#define IRQ_IXP2000_SRAM2_ERR           60
-#define IRQ_IXP2000_SRAM3_ERR           61
-/* 62-65 reserved */
-#define IRQ_IXP2000_MEDIA_ERR           66
-#define IRQ_IXP2000_PCI_ERR                     67
-#define IRQ_IXP2000_SP_INT                      68
-
-#define NR_IXP2000_IRQS                         69
-
-#define IXP2000_BOARD_IRQ(x)            (NR_IXP2000_IRQS + (x))
-
-#define IXP2000_BOARD_IRQ_MASK(irq)     (1 << (irq - NR_IXP2000_IRQS))  
-
-#define IXP2000_ERR_IRQ_MASK(irq) ( 1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR))
-#define IXP2000_VALID_ERR_IRQ_MASK (\
-                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MIN_ERR) | \
-                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MAJ_ERR) | \
-                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MIN_ERR) | \
-                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MAJ_ERR) | \
-                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MIN_ERR) | \
-                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MAJ_ERR) | \
-                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM0_ERR) | \
-                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM1_ERR) | \
-                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM2_ERR) | \
-                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM3_ERR) | \
-                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_MEDIA_ERR) | \
-                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_PCI_ERR) | \
-                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SP_INT)        )
-
-/*
- * This allows for all the on-chip sources plus up to 32 CPLD based
- * IRQs. Should be more than enough.
- */
-#define IXP2000_BOARD_IRQS              32
-#define NR_IRQS                         (NR_IXP2000_IRQS + IXP2000_BOARD_IRQS)
-
-
-/* 
- * IXDP2400 specific IRQs
- */
-#define IRQ_IXDP2400_INGRESS_NPU        IXP2000_BOARD_IRQ(0) 
-#define IRQ_IXDP2400_ENET               IXP2000_BOARD_IRQ(1) 
-#define IRQ_IXDP2400_MEDIA_PCI          IXP2000_BOARD_IRQ(2) 
-#define IRQ_IXDP2400_MEDIA_SP           IXP2000_BOARD_IRQ(3) 
-#define IRQ_IXDP2400_SF_PCI             IXP2000_BOARD_IRQ(4) 
-#define IRQ_IXDP2400_SF_SP              IXP2000_BOARD_IRQ(5) 
-#define IRQ_IXDP2400_PMC                IXP2000_BOARD_IRQ(6) 
-#define IRQ_IXDP2400_TVM                IXP2000_BOARD_IRQ(7) 
-
-#define NR_IXDP2400_IRQS                ((IRQ_IXDP2400_TVM)+1)  
-#define IXDP2400_NR_IRQS                NR_IXDP2400_IRQS - NR_IXP2000_IRQS
-
-/* IXDP2800 specific IRQs */
-#define IRQ_IXDP2800_EGRESS_ENET        IXP2000_BOARD_IRQ(0)
-#define IRQ_IXDP2800_INGRESS_NPU        IXP2000_BOARD_IRQ(1)
-#define IRQ_IXDP2800_PMC                IXP2000_BOARD_IRQ(2)
-#define IRQ_IXDP2800_FABRIC_PCI         IXP2000_BOARD_IRQ(3)
-#define IRQ_IXDP2800_FABRIC             IXP2000_BOARD_IRQ(4)
-#define IRQ_IXDP2800_MEDIA              IXP2000_BOARD_IRQ(5)
-
-#define NR_IXDP2800_IRQS                ((IRQ_IXDP2800_MEDIA)+1)
-#define IXDP2800_NR_IRQS                NR_IXDP2800_IRQS - NR_IXP2000_IRQS
-
-/* 
- * IRQs on both IXDP2x01 boards
- */
-#define IRQ_IXDP2X01_SPCI_DB_0          IXP2000_BOARD_IRQ(2)
-#define IRQ_IXDP2X01_SPCI_DB_1          IXP2000_BOARD_IRQ(3)
-#define IRQ_IXDP2X01_SPCI_PMC_INTA      IXP2000_BOARD_IRQ(4)
-#define IRQ_IXDP2X01_SPCI_PMC_INTB      IXP2000_BOARD_IRQ(5)
-#define IRQ_IXDP2X01_SPCI_PMC_INTC      IXP2000_BOARD_IRQ(6)
-#define IRQ_IXDP2X01_SPCI_PMC_INTD      IXP2000_BOARD_IRQ(7)
-#define IRQ_IXDP2X01_SPCI_FIC_INT       IXP2000_BOARD_IRQ(8)
-#define IRQ_IXDP2X01_IPMI_FROM          IXP2000_BOARD_IRQ(16)
-#define IRQ_IXDP2X01_125US              IXP2000_BOARD_IRQ(17)
-#define IRQ_IXDP2X01_DB_0_ADD           IXP2000_BOARD_IRQ(18)
-#define IRQ_IXDP2X01_DB_1_ADD           IXP2000_BOARD_IRQ(19)
-#define IRQ_IXDP2X01_UART1              IXP2000_BOARD_IRQ(21)
-#define IRQ_IXDP2X01_UART2              IXP2000_BOARD_IRQ(22)
-#define IRQ_IXDP2X01_FIC_ADD_INT        IXP2000_BOARD_IRQ(24)
-#define IRQ_IXDP2X01_CS8900             IXP2000_BOARD_IRQ(25)
-#define IRQ_IXDP2X01_BBSRAM             IXP2000_BOARD_IRQ(26)
-
-#define IXDP2X01_VALID_IRQ_MASK ( \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_0) | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_1) | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTA) | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTB) | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTC) | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTD) | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_FIC_INT) | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_IPMI_FROM) | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_125US) | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_0_ADD) | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_1_ADD) | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART1) | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART2) | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_FIC_ADD_INT) | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_CS8900) | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_BBSRAM) )
-
-/* 
- * IXDP2401 specific IRQs
- */
-#define IRQ_IXDP2401_INTA_82546         IXP2000_BOARD_IRQ(0)
-#define IRQ_IXDP2401_INTB_82546         IXP2000_BOARD_IRQ(1)
-
-#define IXDP2401_VALID_IRQ_MASK ( \
-                IXDP2X01_VALID_IRQ_MASK | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTA_82546) |\
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTB_82546))
-
-/*
- * IXDP2801-specific IRQs
- */
-#define IRQ_IXDP2801_RIV                IXP2000_BOARD_IRQ(0)
-#define IRQ_IXDP2801_CNFG_MEDIA         IXP2000_BOARD_IRQ(27)
-#define IRQ_IXDP2801_CLOCK_REF          IXP2000_BOARD_IRQ(28)
-
-#define IXDP2801_VALID_IRQ_MASK ( \
-                IXDP2X01_VALID_IRQ_MASK | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_RIV) |\
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CNFG_MEDIA) |\
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CLOCK_REF))
-
-#define NR_IXDP2X01_IRQS                ((IRQ_IXDP2801_CLOCK_REF) + 1)
-
-#endif /*_IRQS_H*/
diff --git a/include/asm-arm/arch-ixp2000/ixdp2x00.h b/include/asm-arm/arch-ixp2000/ixdp2x00.h
deleted file mode 100644
index 546e2e8e27b8..000000000000
--- a/include/asm-arm/arch-ixp2000/ixdp2x00.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * include/asm-arm/arch-ixp2000/ixdp2x00.h
- *
- * Register and other defines for IXDP2[48]00 platforms
- *
- * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
- * Maintainer: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright (C) 2002 Intel Corp.
- * Copyright (C) 2003-2004 MontaVista Software, Inc.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- */
-#ifndef _IXDP2X00_H_
-#define _IXDP2X00_H_
-
-/*
- * On board CPLD memory map
- */
-#define IXDP2X00_PHYS_CPLD_BASE         0xc7000000
-#define IXDP2X00_VIRT_CPLD_BASE         0xfe000000
-#define IXDP2X00_CPLD_SIZE              0x00100000
-
-
-#define IXDP2X00_CPLD_REG(x)    \
-        (volatile unsigned long *)(IXDP2X00_VIRT_CPLD_BASE | x)
-
-/*
- * IXDP2400 CPLD registers
- */
-#define IXDP2400_CPLD_SYSLED            IXDP2X00_CPLD_REG(0x0)  
-#define IXDP2400_CPLD_DISP_DATA         IXDP2X00_CPLD_REG(0x4)
-#define IXDP2400_CPLD_CLOCK_SPEED       IXDP2X00_CPLD_REG(0x8)
-#define IXDP2400_CPLD_INT_STAT          IXDP2X00_CPLD_REG(0xc)
-#define IXDP2400_CPLD_REV               IXDP2X00_CPLD_REG(0x10)
-#define IXDP2400_CPLD_SYS_CLK_M         IXDP2X00_CPLD_REG(0x14)
-#define IXDP2400_CPLD_SYS_CLK_N         IXDP2X00_CPLD_REG(0x18)
-#define IXDP2400_CPLD_INT_MASK          IXDP2X00_CPLD_REG(0x48)
-
-/*
- * IXDP2800 CPLD registers
- */
-#define IXDP2800_CPLD_INT_STAT          IXDP2X00_CPLD_REG(0x0)
-#define IXDP2800_CPLD_INT_MASK          IXDP2X00_CPLD_REG(0x140)
-
-
-#define IXDP2X00_GPIO_I2C_ENABLE        0x02
-#define IXDP2X00_GPIO_SCL               0x07
-#define IXDP2X00_GPIO_SDA               0x06
-
-/*
- * PCI devfns for on-board devices. We need these to be able to
- * properly translate IRQs and for device removal.
- */
-#define IXDP2400_SLAVE_ENET_DEVFN       0x18    /* Bus 1 */
-#define IXDP2400_MASTER_ENET_DEVFN      0x20    /* Bus 1 */
-#define IXDP2400_MEDIA_DEVFN            0x28    /* Bus 1 */
-#define IXDP2400_SWITCH_FABRIC_DEVFN    0x30    /* Bus 1 */
-
-#define IXDP2800_SLAVE_ENET_DEVFN       0x20    /* Bus 1 */
-#define IXDP2800_MASTER_ENET_DEVFN      0x18    /* Bus 1 */
-#define IXDP2800_SWITCH_FABRIC_DEVFN    0x30    /* Bus 1 */
-
-#define IXDP2X00_P2P_DEVFN              0x20    /* Bus 0 */
-#define IXDP2X00_21555_DEVFN            0x30    /* Bus 0 */
-#define IXDP2X00_SLAVE_NPU_DEVFN        0x28    /* Bus 1 */
-#define IXDP2X00_PMC_DEVFN              0x38    /* Bus 1 */
-#define IXDP2X00_MASTER_NPU_DEVFN       0x38    /* Bus 1 */
-
-#ifndef __ASSEMBLY__
-/*
- * The master NPU is always PCI master.
- */
-static inline unsigned int ixdp2x00_master_npu(void)
-{
-        return !!ixp2000_is_pcimaster();
-}
-
-/*
- * Helper functions used by ixdp2400 and ixdp2800 specific code
- */
-void ixdp2x00_init_irq(volatile unsigned long*, volatile unsigned long *, unsigned long);
-void ixdp2x00_slave_pci_postinit(void);
-void ixdp2x00_init_machine(void);
-void ixdp2x00_map_io(void);
-
-#endif
-
-#endif /*_IXDP2X00_H_ */
diff --git a/include/asm-arm/arch-ixp2000/ixdp2x01.h b/include/asm-arm/arch-ixp2000/ixdp2x01.h
deleted file mode 100644
index c6d51426e98f..000000000000
--- a/include/asm-arm/arch-ixp2000/ixdp2x01.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * include/asm-arm/arch-ixp2000/ixdp2x01.h
- *
- * Platform definitions for IXDP2X01 && IXDP2801 systems
- *
- * Author: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright 2004 (c) MontaVista Software, Inc. 
- *
- * Based on original code Copyright (c) 2002-2003 Intel Corporation
- * 
- * This file is licensed under  the terms of the GNU General Public 
- * License version 2. This program is licensed "as is" without any 
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __IXDP2X01_H__
-#define __IXDP2X01_H__
-
-#define IXDP2X01_PHYS_CPLD_BASE         0xc6024000
-#define IXDP2X01_VIRT_CPLD_BASE         0xfe000000
-#define IXDP2X01_CPLD_REGION_SIZE       0x00100000
-
-#define IXDP2X01_CPLD_VIRT_REG(reg) (volatile unsigned long*)(IXDP2X01_VIRT_CPLD_BASE | reg)
-#define IXDP2X01_CPLD_PHYS_REG(reg) (IXDP2X01_PHYS_CPLD_BASE | reg)
-
-#define IXDP2X01_UART1_VIRT_BASE        IXDP2X01_CPLD_VIRT_REG(0x40)
-#define IXDP2X01_UART1_PHYS_BASE        IXDP2X01_CPLD_PHYS_REG(0x40)
-
-#define IXDP2X01_UART2_VIRT_BASE        IXDP2X01_CPLD_VIRT_REG(0x60)
-#define IXDP2X01_UART2_PHYS_BASE        IXDP2X01_CPLD_PHYS_REG(0x60)
-
-#define IXDP2X01_CS8900_VIRT_BASE       IXDP2X01_CPLD_VIRT_REG(0x80)
-#define IXDP2X01_CS8900_VIRT_END        (IXDP2X01_CS8900_VIRT_BASE + 16)
-
-#define IXDP2X01_CPLD_RESET_REG         IXDP2X01_CPLD_VIRT_REG(0x00)
-#define IXDP2X01_INT_MASK_SET_REG       IXDP2X01_CPLD_VIRT_REG(0x08)
-#define IXDP2X01_INT_STAT_REG           IXDP2X01_CPLD_VIRT_REG(0x0C)
-#define IXDP2X01_INT_RAW_REG            IXDP2X01_CPLD_VIRT_REG(0x10) 
-#define IXDP2X01_INT_MASK_CLR_REG       IXDP2X01_INT_RAW_REG
-#define IXDP2X01_INT_SIM_REG            IXDP2X01_CPLD_VIRT_REG(0x14)
-
-#define IXDP2X01_CPLD_FLASH_REG         IXDP2X01_CPLD_VIRT_REG(0x20)
-
-#define IXDP2X01_CPLD_FLASH_INTERN      0x8000
-#define IXDP2X01_CPLD_FLASH_BANK_MASK   0xF
-#define IXDP2X01_FLASH_WINDOW_BITS      25
-#define IXDP2X01_FLASH_WINDOW_SIZE      (1 << IXDP2X01_FLASH_WINDOW_BITS)
-#define IXDP2X01_FLASH_WINDOW_MASK      (IXDP2X01_FLASH_WINDOW_SIZE - 1)
-
-#define IXDP2X01_UART_CLK               1843200
-
-#define IXDP2X01_GPIO_I2C_ENABLE        0x02
-#define IXDP2X01_GPIO_SCL               0x07
-#define IXDP2X01_GPIO_SDA               0x06
-
-#endif /* __IXDP2x01_H__ */
diff --git a/include/asm-arm/arch-ixp2000/ixp2000-regs.h b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
deleted file mode 100644
index ccae4bec92c5..000000000000
--- a/include/asm-arm/arch-ixp2000/ixp2000-regs.h
+++ /dev/null
@@ -1,457 +0,0 @@
-/*
- * include/asm-arm/arch-ixp2000/ixp2000-regs.h
- *
- * Chipset register definitions for IXP2400/2800 based systems.
- *
- * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
- *
- * Maintainer: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright (C) 2002 Intel Corp.
- * Copyright (C) 2003-2004 MontaVista Software, Inc.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- */
-#ifndef _IXP2000_REGS_H_
-#define _IXP2000_REGS_H_
-
-/*
- * IXP2000 linux memory map:
- *
- * virt         phys            size
- * fb000000     db000000        16M             PCI CFG1
- * fc000000     da000000        16M             PCI CFG0
- * fd000000     d8000000        16M             PCI I/O
- * fe[0-7]00000                 8M              per-platform mappings
- * fe900000     80000000        1M              SRAM #0 (first MB)
- * fea00000     cb400000        1M              SCRATCH ring get/put
- * feb00000     c8000000        1M              MSF
- * fec00000     df000000        1M              PCI CSRs
- * fed00000     de000000        1M              PCI CREG
- * fee00000     d6000000        1M              INTCTL
- * fef00000     c0000000        1M              CAP
- */
-
-/* 
- * Static I/O regions.
- *
- * Most of the registers are clumped in 4K regions spread throughout
- * the 0xc0000000 -> 0xc0100000 address range, but we just map in
- * the whole range using a single 1 MB section instead of small
- * 4K pages.  This has two advantages for us:
- *
- * 1) We use only one TLB entry for large number of on-chip I/O devices.
- *
- * 2) We can easily set the Section attributes to XCB=101 on the IXP2400
- *    as required per erratum #66.  We accomplish this by using a
- *    new MT_IXP2000_DEVICE memory type with the bits set as required.
- *
- * CAP stands for CSR Access Proxy.
- *
- * If you change the virtual address of this mapping, please propagate
- * the change to arch/arm/kernel/debug.S, which hardcodes the virtual
- * address of the UART located in this region.
- */
-
-#define IXP2000_CAP_PHYS_BASE           0xc0000000
-#define IXP2000_CAP_VIRT_BASE           0xfef00000
-#define IXP2000_CAP_SIZE                0x00100000
-
-/*
- * Addresses for specific on-chip peripherals.
- */
-#define IXP2000_SLOWPORT_CSR_VIRT_BASE  0xfef80000
-#define IXP2000_GLOBAL_REG_VIRT_BASE    0xfef04000
-#define IXP2000_UART_PHYS_BASE          0xc0030000
-#define IXP2000_UART_VIRT_BASE          0xfef30000
-#define IXP2000_TIMER_VIRT_BASE         0xfef20000
-#define IXP2000_UENGINE_CSR_VIRT_BASE   0xfef18000
-#define IXP2000_GPIO_VIRT_BASE          0xfef10000
-
-/*
- * Devices outside of the 0xc0000000 -> 0xc0100000 range.  The virtual
- * addresses of the INTCTL and PCI_CSR mappings are hardcoded in
- * entry-macro.S, so if you ever change these please propagate
- * the change.
- */
-#define IXP2000_INTCTL_PHYS_BASE        0xd6000000
-#define IXP2000_INTCTL_VIRT_BASE        0xfee00000
-#define IXP2000_INTCTL_SIZE             0x00100000
-
-#define IXP2000_PCI_CREG_PHYS_BASE      0xde000000
-#define IXP2000_PCI_CREG_VIRT_BASE      0xfed00000
-#define IXP2000_PCI_CREG_SIZE           0x00100000
-
-#define IXP2000_PCI_CSR_PHYS_BASE       0xdf000000
-#define IXP2000_PCI_CSR_VIRT_BASE       0xfec00000
-#define IXP2000_PCI_CSR_SIZE            0x00100000
-
-#define IXP2000_MSF_PHYS_BASE           0xc8000000
-#define IXP2000_MSF_VIRT_BASE           0xfeb00000
-#define IXP2000_MSF_SIZE                0x00100000
-
-#define IXP2000_SCRATCH_RING_PHYS_BASE  0xcb400000
-#define IXP2000_SCRATCH_RING_VIRT_BASE  0xfea00000
-#define IXP2000_SCRATCH_RING_SIZE       0x00100000
-
-#define IXP2000_SRAM0_PHYS_BASE         0x80000000
-#define IXP2000_SRAM0_VIRT_BASE         0xfe900000
-#define IXP2000_SRAM0_SIZE              0x00100000
-
-#define IXP2000_PCI_IO_PHYS_BASE        0xd8000000
-#define IXP2000_PCI_IO_VIRT_BASE        0xfd000000
-#define IXP2000_PCI_IO_SIZE             0x01000000
-
-#define IXP2000_PCI_CFG0_PHYS_BASE      0xda000000
-#define IXP2000_PCI_CFG0_VIRT_BASE      0xfc000000
-#define IXP2000_PCI_CFG0_SIZE           0x01000000
-
-#define IXP2000_PCI_CFG1_PHYS_BASE      0xdb000000
-#define IXP2000_PCI_CFG1_VIRT_BASE      0xfb000000
-#define IXP2000_PCI_CFG1_SIZE           0x01000000
-
-/* 
- * Timers
- */
-#define IXP2000_TIMER_REG(x)            ((volatile unsigned long*)(IXP2000_TIMER_VIRT_BASE | (x)))
-/* Timer control */
-#define IXP2000_T1_CTL                  IXP2000_TIMER_REG(0x00)
-#define IXP2000_T2_CTL                  IXP2000_TIMER_REG(0x04)
-#define IXP2000_T3_CTL                  IXP2000_TIMER_REG(0x08)
-#define IXP2000_T4_CTL                  IXP2000_TIMER_REG(0x0c)
-/* Store initial value */
-#define IXP2000_T1_CLD                  IXP2000_TIMER_REG(0x10)
-#define IXP2000_T2_CLD                  IXP2000_TIMER_REG(0x14)
-#define IXP2000_T3_CLD                  IXP2000_TIMER_REG(0x18)
-#define IXP2000_T4_CLD                  IXP2000_TIMER_REG(0x1c)
-/* Read current value */
-#define IXP2000_T1_CSR                  IXP2000_TIMER_REG(0x20)
-#define IXP2000_T2_CSR                  IXP2000_TIMER_REG(0x24)
-#define IXP2000_T3_CSR                  IXP2000_TIMER_REG(0x28)
-#define IXP2000_T4_CSR                  IXP2000_TIMER_REG(0x2c)
-/* Clear associated timer interrupt */
-#define IXP2000_T1_CLR                  IXP2000_TIMER_REG(0x30)
-#define IXP2000_T2_CLR                  IXP2000_TIMER_REG(0x34)
-#define IXP2000_T3_CLR                  IXP2000_TIMER_REG(0x38)
-#define IXP2000_T4_CLR                  IXP2000_TIMER_REG(0x3c)
-/* Timer watchdog enable for T4 */
-#define IXP2000_TWDE                    IXP2000_TIMER_REG(0x40)
-
-#define WDT_ENABLE                      0x00000001
-#define TIMER_DIVIDER_256               0x00000008
-#define TIMER_ENABLE                    0x00000080
-#define IRQ_MASK_TIMER1                 (1 << 4)
-
-/*
- * Interrupt controller registers
- */
-#define IXP2000_INTCTL_REG(x)           (volatile unsigned long*)(IXP2000_INTCTL_VIRT_BASE | (x))
-#define IXP2000_IRQ_STATUS              IXP2000_INTCTL_REG(0x08)
-#define IXP2000_IRQ_ENABLE              IXP2000_INTCTL_REG(0x10)
-#define IXP2000_IRQ_ENABLE_SET          IXP2000_INTCTL_REG(0x10)
-#define IXP2000_IRQ_ENABLE_CLR          IXP2000_INTCTL_REG(0x18)
-#define IXP2000_FIQ_ENABLE_CLR          IXP2000_INTCTL_REG(0x14)
-#define IXP2000_IRQ_ERR_STATUS          IXP2000_INTCTL_REG(0x24)
-#define IXP2000_IRQ_ERR_ENABLE_SET      IXP2000_INTCTL_REG(0x2c)
-#define IXP2000_FIQ_ERR_ENABLE_CLR      IXP2000_INTCTL_REG(0x30)
-#define IXP2000_IRQ_ERR_ENABLE_CLR      IXP2000_INTCTL_REG(0x34)
-#define IXP2000_IRQ_THD_RAW_STATUS_A_0  IXP2000_INTCTL_REG(0x60)
-#define IXP2000_IRQ_THD_RAW_STATUS_A_1  IXP2000_INTCTL_REG(0x64)
-#define IXP2000_IRQ_THD_RAW_STATUS_A_2  IXP2000_INTCTL_REG(0x68)
-#define IXP2000_IRQ_THD_RAW_STATUS_A_3  IXP2000_INTCTL_REG(0x6c)
-#define IXP2000_IRQ_THD_RAW_STATUS_B_0  IXP2000_INTCTL_REG(0x80)
-#define IXP2000_IRQ_THD_RAW_STATUS_B_1  IXP2000_INTCTL_REG(0x84)
-#define IXP2000_IRQ_THD_RAW_STATUS_B_2  IXP2000_INTCTL_REG(0x88)
-#define IXP2000_IRQ_THD_RAW_STATUS_B_3  IXP2000_INTCTL_REG(0x8c)
-#define IXP2000_IRQ_THD_STATUS_A_0      IXP2000_INTCTL_REG(0xe0)
-#define IXP2000_IRQ_THD_STATUS_A_1      IXP2000_INTCTL_REG(0xe4)
-#define IXP2000_IRQ_THD_STATUS_A_2      IXP2000_INTCTL_REG(0xe8)
-#define IXP2000_IRQ_THD_STATUS_A_3      IXP2000_INTCTL_REG(0xec)
-#define IXP2000_IRQ_THD_STATUS_B_0      IXP2000_INTCTL_REG(0x100)
-#define IXP2000_IRQ_THD_STATUS_B_1      IXP2000_INTCTL_REG(0x104)
-#define IXP2000_IRQ_THD_STATUS_B_2      IXP2000_INTCTL_REG(0x108)
-#define IXP2000_IRQ_THD_STATUS_B_3      IXP2000_INTCTL_REG(0x10c)
-#define IXP2000_IRQ_THD_ENABLE_SET_A_0  IXP2000_INTCTL_REG(0x160)
-#define IXP2000_IRQ_THD_ENABLE_SET_A_1  IXP2000_INTCTL_REG(0x164)
-#define IXP2000_IRQ_THD_ENABLE_SET_A_2  IXP2000_INTCTL_REG(0x168)
-#define IXP2000_IRQ_THD_ENABLE_SET_A_3  IXP2000_INTCTL_REG(0x16c)
-#define IXP2000_IRQ_THD_ENABLE_SET_B_0  IXP2000_INTCTL_REG(0x180)
-#define IXP2000_IRQ_THD_ENABLE_SET_B_1  IXP2000_INTCTL_REG(0x184)
-#define IXP2000_IRQ_THD_ENABLE_SET_B_2  IXP2000_INTCTL_REG(0x188)
-#define IXP2000_IRQ_THD_ENABLE_SET_B_3  IXP2000_INTCTL_REG(0x18c)
-#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_0        IXP2000_INTCTL_REG(0x1e0)
-#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_1        IXP2000_INTCTL_REG(0x1e4)
-#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_2        IXP2000_INTCTL_REG(0x1e8)
-#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_3        IXP2000_INTCTL_REG(0x1ec)
-#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_0        IXP2000_INTCTL_REG(0x200)
-#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_1        IXP2000_INTCTL_REG(0x204)
-#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_2        IXP2000_INTCTL_REG(0x208)
-#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_3        IXP2000_INTCTL_REG(0x20c)
-
-/*
- * Mask of valid IRQs in the 32-bit IRQ register. We use
- * this to mark certain IRQs as being invalid.
- */
-#define IXP2000_VALID_IRQ_MASK  0x0f0fffff
-
-/*
- * PCI config register access from core
- */
-#define IXP2000_PCI_CREG(x)             (volatile unsigned long*)(IXP2000_PCI_CREG_VIRT_BASE | (x))
-#define IXP2000_PCI_CMDSTAT             IXP2000_PCI_CREG(0x04)
-#define IXP2000_PCI_CSR_BAR             IXP2000_PCI_CREG(0x10)
-#define IXP2000_PCI_SRAM_BAR            IXP2000_PCI_CREG(0x14)
-#define IXP2000_PCI_SDRAM_BAR           IXP2000_PCI_CREG(0x18)
-
-/*
- * PCI CSRs
- */
-#define IXP2000_PCI_CSR(x)              (volatile unsigned long*)(IXP2000_PCI_CSR_VIRT_BASE | (x))
-
-/*
- * PCI outbound interrupts
- */
-#define IXP2000_PCI_OUT_INT_STATUS      IXP2000_PCI_CSR(0x30)
-#define IXP2000_PCI_OUT_INT_MASK        IXP2000_PCI_CSR(0x34)
-/*
- * PCI communications
- */
-#define IXP2000_PCI_MAILBOX0            IXP2000_PCI_CSR(0x50)
-#define IXP2000_PCI_MAILBOX1            IXP2000_PCI_CSR(0x54)
-#define IXP2000_PCI_MAILBOX2            IXP2000_PCI_CSR(0x58)
-#define IXP2000_PCI_MAILBOX3            IXP2000_PCI_CSR(0x5C)
-#define IXP2000_XSCALE_DOORBELL         IXP2000_PCI_CSR(0x60)
-#define IXP2000_XSCALE_DOORBELL_SETUP   IXP2000_PCI_CSR(0x64)
-#define IXP2000_PCI_DOORBELL            IXP2000_PCI_CSR(0x70)
-#define IXP2000_PCI_DOORBELL_SETUP      IXP2000_PCI_CSR(0x74)
-
-/*
- * DMA engines
- */
-#define IXP2000_PCI_CH1_BYTE_CNT        IXP2000_PCI_CSR(0x80)
-#define IXP2000_PCI_CH1_ADDR            IXP2000_PCI_CSR(0x84)
-#define IXP2000_PCI_CH1_DRAM_ADDR       IXP2000_PCI_CSR(0x88)
-#define IXP2000_PCI_CH1_DESC_PTR        IXP2000_PCI_CSR(0x8C)
-#define IXP2000_PCI_CH1_CNTRL           IXP2000_PCI_CSR(0x90)
-#define IXP2000_PCI_CH1_ME_PARAM        IXP2000_PCI_CSR(0x94)
-#define IXP2000_PCI_CH2_BYTE_CNT        IXP2000_PCI_CSR(0xA0)
-#define IXP2000_PCI_CH2_ADDR            IXP2000_PCI_CSR(0xA4)
-#define IXP2000_PCI_CH2_DRAM_ADDR       IXP2000_PCI_CSR(0xA8)
-#define IXP2000_PCI_CH2_DESC_PTR        IXP2000_PCI_CSR(0xAC)
-#define IXP2000_PCI_CH2_CNTRL           IXP2000_PCI_CSR(0xB0)
-#define IXP2000_PCI_CH2_ME_PARAM        IXP2000_PCI_CSR(0xB4)
-#define IXP2000_PCI_CH3_BYTE_CNT        IXP2000_PCI_CSR(0xC0)
-#define IXP2000_PCI_CH3_ADDR            IXP2000_PCI_CSR(0xC4)
-#define IXP2000_PCI_CH3_DRAM_ADDR       IXP2000_PCI_CSR(0xC8)
-#define IXP2000_PCI_CH3_DESC_PTR        IXP2000_PCI_CSR(0xCC)
-#define IXP2000_PCI_CH3_CNTRL           IXP2000_PCI_CSR(0xD0)
-#define IXP2000_PCI_CH3_ME_PARAM        IXP2000_PCI_CSR(0xD4)
-#define IXP2000_DMA_INF_MODE            IXP2000_PCI_CSR(0xE0)
-/*
- * Size masks for BARs
- */
-#define IXP2000_PCI_SRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0xFC)
-#define IXP2000_PCI_DRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0x100)
-/*
- * Control and uEngine related
- */
-#define IXP2000_PCI_CONTROL             IXP2000_PCI_CSR(0x13C)
-#define IXP2000_PCI_ADDR_EXT            IXP2000_PCI_CSR(0x140)
-#define IXP2000_PCI_ME_PUSH_STATUS      IXP2000_PCI_CSR(0x148)
-#define IXP2000_PCI_ME_PUSH_EN          IXP2000_PCI_CSR(0x14C)
-#define IXP2000_PCI_ERR_STATUS          IXP2000_PCI_CSR(0x150)
-#define IXP2000_PCI_ERR_ENABLE          IXP2000_PCI_CSR(0x154)
-/*
- * Inbound PCI interrupt control
- */
-#define IXP2000_PCI_XSCALE_INT_STATUS   IXP2000_PCI_CSR(0x158)
-#define IXP2000_PCI_XSCALE_INT_ENABLE   IXP2000_PCI_CSR(0x15C)
-
-#define IXP2000_PCICNTL_PNR             (1<<17) /* PCI not Reset bit of PCI_CONTROL */
-#define IXP2000_PCICNTL_PCF             (1<<28) /* PCI Central function bit */
-#define IXP2000_XSCALE_INT              (1<<1)  /* Interrupt from XScale to PCI */
-
-/* These are from the IRQ register in the PCI ISR register */
-#define PCI_CONTROL_BE_DEO              (1 << 22)       /* Big Endian Data Enable Out */
-#define PCI_CONTROL_BE_DEI              (1 << 21)       /* Big Endian Data Enable In  */
-#define PCI_CONTROL_BE_BEO              (1 << 20)       /* Big Endian Byte Enable Out */
-#define PCI_CONTROL_BE_BEI              (1 << 19)       /* Big Endian Byte Enable In  */
-#define PCI_CONTROL_IEE                 (1 << 17)       /* I/O cycle Endian swap Enable */
-
-#define IXP2000_PCI_RST_REL             (1 << 2)
-#define CFG_RST_DIR                     (*IXP2000_PCI_CONTROL & IXP2000_PCICNTL_PCF)
-#define CFG_PCI_BOOT_HOST               (1 << 2)
-#define CFG_BOOT_PROM                   (1 << 1)
-
-/*
- * SlowPort CSRs
- *
- * The slowport is used to access things like flash, SONET framer control
- * ports, slave microprocessors, CPLDs, and others of chip memory mapped
- * peripherals.
- */
-#define SLOWPORT_CSR(x)         (volatile unsigned long*)(IXP2000_SLOWPORT_CSR_VIRT_BASE | (x))
-
-#define IXP2000_SLOWPORT_CCR            SLOWPORT_CSR(0x00)
-#define IXP2000_SLOWPORT_WTC1           SLOWPORT_CSR(0x04)
-#define IXP2000_SLOWPORT_WTC2           SLOWPORT_CSR(0x08)
-#define IXP2000_SLOWPORT_RTC1           SLOWPORT_CSR(0x0c)
-#define IXP2000_SLOWPORT_RTC2           SLOWPORT_CSR(0x10)
-#define IXP2000_SLOWPORT_FSR            SLOWPORT_CSR(0x14)
-#define IXP2000_SLOWPORT_PCR            SLOWPORT_CSR(0x18)
-#define IXP2000_SLOWPORT_ADC            SLOWPORT_CSR(0x1C)
-#define IXP2000_SLOWPORT_FAC            SLOWPORT_CSR(0x20)
-#define IXP2000_SLOWPORT_FRM            SLOWPORT_CSR(0x24)
-#define IXP2000_SLOWPORT_FIN            SLOWPORT_CSR(0x28)
-
-/*
- * CCR values.  
- * The CCR configures the clock division for the slowport interface.
- */
-#define SLOWPORT_CCR_DIV_1              0x00
-#define SLOWPORT_CCR_DIV_2              0x01
-#define SLOWPORT_CCR_DIV_4              0x02
-#define SLOWPORT_CCR_DIV_6              0x03
-#define SLOWPORT_CCR_DIV_8              0x04
-#define SLOWPORT_CCR_DIV_10             0x05
-#define SLOWPORT_CCR_DIV_12             0x06
-#define SLOWPORT_CCR_DIV_14             0x07
-#define SLOWPORT_CCR_DIV_16             0x08
-#define SLOWPORT_CCR_DIV_18             0x09
-#define SLOWPORT_CCR_DIV_20             0x0a
-#define SLOWPORT_CCR_DIV_22             0x0b
-#define SLOWPORT_CCR_DIV_24             0x0c
-#define SLOWPORT_CCR_DIV_26             0x0d
-#define SLOWPORT_CCR_DIV_28             0x0e
-#define SLOWPORT_CCR_DIV_30             0x0f
-
-/*
- * PCR values.  PCR configure the mode of the interface.
- */
-#define SLOWPORT_MODE_FLASH             0x00
-#define SLOWPORT_MODE_LUCENT            0x01
-#define SLOWPORT_MODE_PMC_SIERRA        0x02
-#define SLOWPORT_MODE_INTEL_UP          0x03
-#define SLOWPORT_MODE_MOTOROLA_UP       0x04
-
-/*
- * ADC values.  Defines data and address bus widths.
- */
-#define SLOWPORT_ADDR_WIDTH_8           0x00
-#define SLOWPORT_ADDR_WIDTH_16          0x01
-#define SLOWPORT_ADDR_WIDTH_24          0x02
-#define SLOWPORT_ADDR_WIDTH_32          0x03
-#define SLOWPORT_DATA_WIDTH_8           0x00
-#define SLOWPORT_DATA_WIDTH_16          0x10
-#define SLOWPORT_DATA_WIDTH_24          0x20
-#define SLOWPORT_DATA_WIDTH_32          0x30
-
-/*
- * Masks and shifts for various fields in the WTC and RTC registers.
- */
-#define SLOWPORT_WRTC_MASK_HD           0x0003
-#define SLOWPORT_WRTC_MASK_PW           0x003c
-#define SLOWPORT_WRTC_MASK_SU           0x03c0
-
-#define SLOWPORT_WRTC_SHIFT_HD          0x00
-#define SLOWPORT_WRTC_SHIFT_SU          0x02
-#define SLOWPORT_WRTC_SHFIT_PW          0x06
-
-
-/*
- * GPIO registers & GPIO interface.
- */
-#define IXP2000_GPIO_REG(x)             ((volatile unsigned long*)(IXP2000_GPIO_VIRT_BASE+(x)))
-#define IXP2000_GPIO_PLR                IXP2000_GPIO_REG(0x00)
-#define IXP2000_GPIO_PDPR               IXP2000_GPIO_REG(0x04)
-#define IXP2000_GPIO_PDSR               IXP2000_GPIO_REG(0x08)
-#define IXP2000_GPIO_PDCR               IXP2000_GPIO_REG(0x0c)
-#define IXP2000_GPIO_POPR               IXP2000_GPIO_REG(0x10)
-#define IXP2000_GPIO_POSR               IXP2000_GPIO_REG(0x14)
-#define IXP2000_GPIO_POCR               IXP2000_GPIO_REG(0x18)
-#define IXP2000_GPIO_REDR               IXP2000_GPIO_REG(0x1c)
-#define IXP2000_GPIO_FEDR               IXP2000_GPIO_REG(0x20)
-#define IXP2000_GPIO_EDSR               IXP2000_GPIO_REG(0x24)
-#define IXP2000_GPIO_LSHR               IXP2000_GPIO_REG(0x28)
-#define IXP2000_GPIO_LSLR               IXP2000_GPIO_REG(0x2c)
-#define IXP2000_GPIO_LDSR               IXP2000_GPIO_REG(0x30)
-#define IXP2000_GPIO_INER               IXP2000_GPIO_REG(0x34)
-#define IXP2000_GPIO_INSR               IXP2000_GPIO_REG(0x38)
-#define IXP2000_GPIO_INCR               IXP2000_GPIO_REG(0x3c)
-#define IXP2000_GPIO_INST               IXP2000_GPIO_REG(0x40)
-
-/*
- * "Global" registers...whatever that's supposed to mean.
- */
-#define GLOBAL_REG_BASE                 (IXP2000_GLOBAL_REG_VIRT_BASE + 0x0a00)
-#define GLOBAL_REG(x)                   (volatile unsigned long*)(GLOBAL_REG_BASE | (x))
-
-#define IXP2000_MAJ_PROD_TYPE_MASK      0x001F0000
-#define IXP2000_MAJ_PROD_TYPE_IXP2000   0x00000000
-#define IXP2000_MIN_PROD_TYPE_MASK      0x0000FF00
-#define IXP2000_MIN_PROD_TYPE_IXP2400   0x00000200
-#define IXP2000_MIN_PROD_TYPE_IXP2850   0x00000100
-#define IXP2000_MIN_PROD_TYPE_IXP2800   0x00000000
-#define IXP2000_MAJ_REV_MASK            0x000000F0
-#define IXP2000_MIN_REV_MASK            0x0000000F
-#define IXP2000_PROD_ID_MASK            0xFFFFFFFF
-
-#define IXP2000_PRODUCT_ID              GLOBAL_REG(0x00)
-#define IXP2000_MISC_CONTROL            GLOBAL_REG(0x04)
-#define IXP2000_MSF_CLK_CNTRL           GLOBAL_REG(0x08)
-#define IXP2000_RESET0                  GLOBAL_REG(0x0c)
-#define IXP2000_RESET1                  GLOBAL_REG(0x10)
-#define IXP2000_CCR                     GLOBAL_REG(0x14)
-#define IXP2000_STRAP_OPTIONS           GLOBAL_REG(0x18)
-
-#define RSTALL                          (1 << 16)
-#define WDT_RESET_ENABLE                0x01000000
-
-
-/*
- * MSF registers.  The IXP2400 and IXP2800 have somewhat different MSF
- * units, but the registers that differ between the two don't overlap,
- * so we can have one register list for both.
- */
-#define IXP2000_MSF_REG(x)                      ((volatile unsigned long*)(IXP2000_MSF_VIRT_BASE + (x)))
-#define IXP2000_MSF_RX_CONTROL                  IXP2000_MSF_REG(0x0000)
-#define IXP2000_MSF_TX_CONTROL                  IXP2000_MSF_REG(0x0004)
-#define IXP2000_MSF_INTERRUPT_STATUS            IXP2000_MSF_REG(0x0008)
-#define IXP2000_MSF_INTERRUPT_ENABLE            IXP2000_MSF_REG(0x000c)
-#define IXP2000_MSF_CSIX_TYPE_MAP               IXP2000_MSF_REG(0x0010)
-#define IXP2000_MSF_FC_EGRESS_STATUS            IXP2000_MSF_REG(0x0014)
-#define IXP2000_MSF_FC_INGRESS_STATUS           IXP2000_MSF_REG(0x0018)
-#define IXP2000_MSF_HWM_CONTROL                 IXP2000_MSF_REG(0x0024)
-#define IXP2000_MSF_FC_STATUS_OVERRIDE          IXP2000_MSF_REG(0x0028)
-#define IXP2000_MSF_CLOCK_CONTROL               IXP2000_MSF_REG(0x002c)
-#define IXP2000_MSF_RX_PORT_MAP                 IXP2000_MSF_REG(0x0040)
-#define IXP2000_MSF_RBUF_ELEMENT_DONE           IXP2000_MSF_REG(0x0044)
-#define IXP2000_MSF_RX_MPHY_POLL_LIMIT          IXP2000_MSF_REG(0x0048)
-#define IXP2000_MSF_RX_CALENDAR_LENGTH          IXP2000_MSF_REG(0x0048)
-#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_0        IXP2000_MSF_REG(0x0050)
-#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_1        IXP2000_MSF_REG(0x0054)
-#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_2        IXP2000_MSF_REG(0x0058)
-#define IXP2000_MSF_TX_SEQUENCE_0               IXP2000_MSF_REG(0x0060)
-#define IXP2000_MSF_TX_SEQUENCE_1               IXP2000_MSF_REG(0x0064)
-#define IXP2000_MSF_TX_SEQUENCE_2               IXP2000_MSF_REG(0x0068)
-#define IXP2000_MSF_TX_MPHY_POLL_LIMIT          IXP2000_MSF_REG(0x0070)
-#define IXP2000_MSF_TX_CALENDAR_LENGTH          IXP2000_MSF_REG(0x0070)
-#define IXP2000_MSF_RX_UP_CONTROL_0             IXP2000_MSF_REG(0x0080)
-#define IXP2000_MSF_RX_UP_CONTROL_1             IXP2000_MSF_REG(0x0084)
-#define IXP2000_MSF_RX_UP_CONTROL_2             IXP2000_MSF_REG(0x0088)
-#define IXP2000_MSF_RX_UP_CONTROL_3             IXP2000_MSF_REG(0x008c)
-#define IXP2000_MSF_TX_UP_CONTROL_0             IXP2000_MSF_REG(0x0090)
-#define IXP2000_MSF_TX_UP_CONTROL_1             IXP2000_MSF_REG(0x0094)
-#define IXP2000_MSF_TX_UP_CONTROL_2             IXP2000_MSF_REG(0x0098)
-#define IXP2000_MSF_TX_UP_CONTROL_3             IXP2000_MSF_REG(0x009c)
-#define IXP2000_MSF_TRAIN_DATA                  IXP2000_MSF_REG(0x00a0)
-#define IXP2000_MSF_TRAIN_CALENDAR              IXP2000_MSF_REG(0x00a4)
-#define IXP2000_MSF_TRAIN_FLOW_CONTROL          IXP2000_MSF_REG(0x00a8)
-#define IXP2000_MSF_TX_CALENDAR_0               IXP2000_MSF_REG(0x1000)
-#define IXP2000_MSF_RX_PORT_CALENDAR_STATUS     IXP2000_MSF_REG(0x1400)
-
-
-#endif                          /* _IXP2000_H_ */
diff --git a/include/asm-arm/arch-ixp2000/memory.h b/include/asm-arm/arch-ixp2000/memory.h
deleted file mode 100644
index 21e1de51e3f6..000000000000
--- a/include/asm-arm/arch-ixp2000/memory.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ixp2000/memory.h
- *
- * Copyright (c) 2002 Intel Corp.
- * Copyright (c) 2003-2004 MontaVista Software, Inc.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- */
-
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-#define PHYS_OFFSET     UL(0x00000000)
-
-/*
- * Virtual view <-> DMA view memory address translations
- * virt_to_bus: Used to translate the virtual address to an
- *              address suitable to be passed to set_dma_addr
- * bus_to_virt: Used to convert an address for DMA operations
- *              to an address that the kernel can use.
- */
-#include <asm/arch/ixp2000-regs.h>
-
-#define __virt_to_bus(v) \
-        (((__virt_to_phys(v) - 0x0) + (*IXP2000_PCI_SDRAM_BAR & 0xfffffff0)))
-
-#define __bus_to_virt(b) \
-        __phys_to_virt((((b - (*IXP2000_PCI_SDRAM_BAR & 0xfffffff0)) + 0x0)))
-
-#endif
-
diff --git a/include/asm-arm/arch-ixp2000/platform.h b/include/asm-arm/arch-ixp2000/platform.h
deleted file mode 100644
index a66317ab2071..000000000000
--- a/include/asm-arm/arch-ixp2000/platform.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * include/asm-arm/arch-ixp2000/platform.h
- *
- * Various bits of code used by platform-level code.
- *
- * Author: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright 2004 (c) MontaVista Software, Inc. 
- * 
- * This file is licensed under  the terms of the GNU General Public 
- * License version 2. This program is licensed "as is" without any 
- * warranty of any kind, whether express or implied.
- */
-
-
-#ifndef __ASSEMBLY__
-
-static inline unsigned long ixp2000_reg_read(volatile void *reg)
-{
-        return *((volatile unsigned long *)reg);
-}
-
-static inline void ixp2000_reg_write(volatile void *reg, unsigned long val)
-{
-        *((volatile unsigned long *)reg) = val;
-}
-
-/*
- * On the IXP2400, we can't use XCB=000 due to chip bugs.  We use
- * XCB=101 instead, but that makes all I/O accesses bufferable.  This
- * is not a problem in general, but we do have to be slightly more
- * careful because I/O writes are no longer automatically flushed out
- * of the write buffer.
- *
- * In cases where we want to make sure that a write has been flushed
- * out of the write buffer before we proceed, for example when masking
- * a device interrupt before re-enabling IRQs in CPSR, we can use this
- * function, ixp2000_reg_wrb, which performs a write, a readback, and
- * issues a dummy instruction dependent on the value of the readback
- * (mov rX, rX) to make sure that the readback has completed before we
- * continue.
- */
-static inline void ixp2000_reg_wrb(volatile void *reg, unsigned long val)
-{
-        unsigned long dummy;
-
-        *((volatile unsigned long *)reg) = val;
-
-        dummy = *((volatile unsigned long *)reg);
-        __asm__ __volatile__("mov %0, %0" : "+r" (dummy));
-}
-
-/*
- * Boards may multiplex different devices on the 2nd channel of 
- * the slowport interface that each need different configuration 
- * settings.  For example, the IXDP2400 uses channel 2 on the interface 
- * to access the CPLD, the switch fabric card, and the media card.  Each
- * one needs a different mode so drivers must save/restore the mode 
- * before and after each operation.  
- *
- * acquire_slowport(&your_config);
- * ...
- * do slowport operations
- * ...
- * release_slowport();
- *
- * Note that while you have the slowport, you are holding a spinlock,
- * so your code should be written as if you explicitly acquired a lock.
- *
- * The configuration only affects device 2 on the slowport, so the
- * MTD map driver does not acquire/release the slowport.  
- */
-struct slowport_cfg {
-        unsigned long CCR;      /* Clock divide */
-        unsigned long WTC;      /* Write Timing Control */
-        unsigned long RTC;      /* Read Timing Control */
-        unsigned long PCR;      /* Protocol Control Register */
-        unsigned long ADC;      /* Address/Data Width Control */
-};
-
-
-void ixp2000_acquire_slowport(struct slowport_cfg *, struct slowport_cfg *);
-void ixp2000_release_slowport(struct slowport_cfg *);
-
-/*
- * IXP2400 A0/A1 and  IXP2800 A0/A1/A2 have broken slowport that requires
- * tweaking of addresses in the MTD driver.
- */
-static inline unsigned ixp2000_has_broken_slowport(void)
-{
-        unsigned long id = *IXP2000_PRODUCT_ID;
-        unsigned long id_prod = id & (IXP2000_MAJ_PROD_TYPE_MASK |
-                                      IXP2000_MIN_PROD_TYPE_MASK);
-        return (((id_prod ==
-                  /* fixed in IXP2400-B0 */
-                  (IXP2000_MAJ_PROD_TYPE_IXP2000 |
-                   IXP2000_MIN_PROD_TYPE_IXP2400)) &&
-                 ((id & IXP2000_MAJ_REV_MASK) == 0)) ||
-                ((id_prod ==
-                  /* fixed in IXP2800-B0 */
-                  (IXP2000_MAJ_PROD_TYPE_IXP2000 |
-                   IXP2000_MIN_PROD_TYPE_IXP2800)) &&
-                 ((id & IXP2000_MAJ_REV_MASK) == 0)) ||
-                ((id_prod ==
-                  /* fixed in IXP2850-B0 */
-                  (IXP2000_MAJ_PROD_TYPE_IXP2000 |
-                   IXP2000_MIN_PROD_TYPE_IXP2850)) &&
-                 ((id & IXP2000_MAJ_REV_MASK) == 0)));
-}
-
-static inline unsigned int ixp2000_has_flash(void)
-{
-        return ((*IXP2000_STRAP_OPTIONS) & (CFG_BOOT_PROM));
-}
-
-static inline unsigned int ixp2000_is_pcimaster(void)
-{
-        return ((*IXP2000_STRAP_OPTIONS) & (CFG_PCI_BOOT_HOST));
-}
-
-void ixp2000_map_io(void);
-void ixp2000_uart_init(void);
-void ixp2000_init_irq(void);
-void ixp2000_init_time(unsigned long);
-unsigned long ixp2000_gettimeoffset(void);
-
-struct pci_sys_data;
-
-u32 *ixp2000_pci_config_addr(unsigned int bus, unsigned int devfn, int where);
-void ixp2000_pci_preinit(void);
-int ixp2000_pci_setup(int, struct pci_sys_data*);
-struct pci_bus* ixp2000_pci_scan_bus(int, struct pci_sys_data*);
-int ixp2000_pci_read_config(struct pci_bus*, unsigned int, int, int, u32 *);
-int ixp2000_pci_write_config(struct pci_bus*, unsigned int, int, int, u32);
-
-/*
- * Several of the IXP2000 systems have banked flash so we need to extend the
- * flash_platform_data structure with some private pointers
- */
-struct ixp2000_flash_data {
-        struct flash_platform_data *platform_data;
-        int nr_banks;
-        unsigned long (*bank_setup)(unsigned long);
-};
-
-struct ixp2000_i2c_pins {
-        unsigned long sda_pin;
-        unsigned long scl_pin;
-};
-
-
-#endif /*  !__ASSEMBLY__ */
diff --git a/include/asm-arm/arch-ixp2000/system.h b/include/asm-arm/arch-ixp2000/system.h
deleted file mode 100644
index 8731dd36e452..000000000000
--- a/include/asm-arm/arch-ixp2000/system.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ixp2000/system.h
- *
- * Copyright (C) 2002 Intel Corp.
- * Copyricht (C) 2003-2005 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <asm/arch/hardware.h>
-#include <asm/mach-types.h>
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-static inline void arch_reset(char mode)
-{
-        local_irq_disable();
-
-        /*
-         * Reset flash banking register so that we are pointing at
-         * RedBoot bank.
-         */
-        if (machine_is_ixdp2401()) {
-                ixp2000_reg_write(IXDP2X01_CPLD_FLASH_REG,
-                                        ((0 >> IXDP2X01_FLASH_WINDOW_BITS)
-                                                | IXDP2X01_CPLD_FLASH_INTERN));
-                ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0xffffffff);
-        }
-
-        /*
-         * On IXDP2801 we need to write this magic sequence to the CPLD
-         * to cause a complete reset of the CPU and all external devices
-         * and move the flash bank register back to 0.
-         */
-        if (machine_is_ixdp2801() || machine_is_ixdp28x5()) {
-                unsigned long reset_reg = *IXDP2X01_CPLD_RESET_REG;
-
-                reset_reg = 0x55AA0000 | (reset_reg & 0x0000FFFF);
-                ixp2000_reg_write(IXDP2X01_CPLD_RESET_REG, reset_reg);
-                ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0x80000000);
-        }
-
-        ixp2000_reg_wrb(IXP2000_RESET0, RSTALL);
-}
diff --git a/include/asm-arm/arch-ixp2000/timex.h b/include/asm-arm/arch-ixp2000/timex.h
deleted file mode 100644
index b78a183d4698..000000000000
--- a/include/asm-arm/arch-ixp2000/timex.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ixp2000/timex.h
- *
- * IXP2000 architecture timex specifications
- */
-
-
-/*
- * Default clock is 50MHz APB, but platform code can override this
- */
-#define CLOCK_TICK_RATE 50000000
-
-
diff --git a/include/asm-arm/arch-ixp2000/uncompress.h b/include/asm-arm/arch-ixp2000/uncompress.h
deleted file mode 100644
index f66b408f363e..000000000000
--- a/include/asm-arm/arch-ixp2000/uncompress.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ixp2000/uncompress.h
- *
- *
- * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
- * Maintainer: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright 2002 Intel Corp.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- */
-
-#include <linux/serial_reg.h>
-
-#define UART_BASE       0xc0030000
-
-#define PHYS(x)          ((volatile unsigned long *)(UART_BASE + x))
-
-#define UARTDR          PHYS(0x00)      /* Transmit reg dlab=0 */
-#define UARTDLL         PHYS(0x00)      /* Divisor Latch reg dlab=1*/
-#define UARTDLM         PHYS(0x04)      /* Divisor Latch reg dlab=1*/
-#define UARTIER         PHYS(0x04)      /* Interrupt enable reg */
-#define UARTFCR         PHYS(0x08)      /* FIFO control reg dlab =0*/
-#define UARTLCR         PHYS(0x0c)      /* Control reg */
-#define UARTSR          PHYS(0x14)      /* Status reg */
-
-
-static inline void putc(int c)
-{
-        int j = 0x1000;
-
-        while (--j && !(*UARTSR & UART_LSR_THRE))
-                barrier();
-
-        *UARTDR = c;
-}
-
-static inline void flush(void)
-{
-}
-
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-ixp2000/vmalloc.h b/include/asm-arm/arch-ixp2000/vmalloc.h
deleted file mode 100644
index 275136963a0c..000000000000
--- a/include/asm-arm/arch-ixp2000/vmalloc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ixp2000/vmalloc.h
- *
- * Author: Naeem Afzal <naeem.m.afzal@intel.com>
- *
- * Copyright 2002 Intel Corp.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- * Just any arbitrary offset to the start of the vmalloc VM area: the
- * current 8MB value just means that there will be a 8MB "hole" after the
- * physical memory until the kernel virtual memory starts.  That means that
- * any out-of-bounds memory accesses will hopefully be caught.
- * The vmalloc() routines leaves a hole of 4kB between each vmalloced
- * area for the same reason. ;)
- */
-#define VMALLOC_END         0xfb000000
diff --git a/include/asm-arm/arch-ixp23xx/debug-macro.S b/include/asm-arm/arch-ixp23xx/debug-macro.S
deleted file mode 100644
index 2b25e640247d..000000000000
--- a/include/asm-arm/arch-ixp23xx/debug-macro.S
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * include/asm-arm/arch-ixp23xx/debug-macro.S
- *
- * Debugging macro include header
- *
- * Copyright (C) 1994-1999 Russell King
- * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <asm/arch/ixp23xx.h>
-
-                .macro  addruart,rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                         @ mmu enabled?
-                ldreq   \rx, =IXP23XX_PERIPHERAL_PHYS   @ physical
-                ldrne   \rx, =IXP23XX_PERIPHERAL_VIRT   @ virtual
-#ifdef __ARMEB__
-                orr     \rx, \rx, #0x00000003
-#endif
-                .endm
-
-#define UART_SHIFT      2
-#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-ixp23xx/dma.h b/include/asm-arm/arch-ixp23xx/dma.h
deleted file mode 100644
index 2f4335e3b836..000000000000
--- a/include/asm-arm/arch-ixp23xx/dma.h
+++ /dev/null
@@ -1,3 +0,0 @@
-/*
- * include/asm-arm/arch-ixp23xx/dma.h
- */
diff --git a/include/asm-arm/arch-ixp23xx/entry-macro.S b/include/asm-arm/arch-ixp23xx/entry-macro.S
deleted file mode 100644
index ec9dd6fc2d0f..000000000000
--- a/include/asm-arm/arch-ixp23xx/entry-macro.S
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * include/asm-arm/arch-ixp23xx/entry-macro.S
- */
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \irqnr, =(IXP23XX_INTC_VIRT + IXP23XX_INTR_IRQ_ENC_ST_OFFSET)
-                ldr     \irqnr, [\irqnr]        @ get interrupt number
-                cmp     \irqnr, #0x0            @ spurious interrupt ?
-                movne   \irqnr, \irqnr, lsr #2  @ skip unwanted low order bits
-                subne   \irqnr, \irqnr, #1      @ convert to 0 based
-
-#if 0
-                cmp     \irqnr, #IRQ_IXP23XX_PCI_INT_RPH
-                bne     1001f
-                mov     \irqnr, #IRQ_IXP23XX_INTA
-
-                ldr     \irqnr, =0xf5000030
-
-                mov     \tmp, #(1<<26)
-                tst     \irqnr, \tmp
-                movne   \irqnr, #IRQ_IXP23XX_INTB
-
-                mov     \tmp, #(1<<27)
-                tst     \irqnr, \tmp
-                movne   \irqnr, #IRQ_IXP23XX_INTA
-1001:
-#endif
-                .endm
diff --git a/include/asm-arm/arch-ixp23xx/hardware.h b/include/asm-arm/arch-ixp23xx/hardware.h
deleted file mode 100644
index c0010d21a684..000000000000
--- a/include/asm-arm/arch-ixp23xx/hardware.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * include/asm-arm/arch-ixp23xx/hardware.h
- *
- * Copyright (C) 2002-2004 Intel Corporation.
- * Copyricht (C) 2005 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Hardware definitions for IXP23XX based systems
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-/* PCI IO info */
-#define PCIO_BASE               IXP23XX_PCI_IO_VIRT
-#define PCIBIOS_MIN_IO          0x00000000
-#define PCIBIOS_MIN_MEM         0xe0000000
-
-#include "ixp23xx.h"
-
-#define pcibios_assign_all_busses()     0
-
-/*
- * Platform helper functions
- */
-#include "platform.h"
-
-/*
- * Platform-specific headers
- */
-#include "ixdp2351.h"
-
-
-#endif
diff --git a/include/asm-arm/arch-ixp23xx/io.h b/include/asm-arm/arch-ixp23xx/io.h
deleted file mode 100644
index 66f5bafc315c..000000000000
--- a/include/asm-arm/arch-ixp23xx/io.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * include/asm-arm/arch-ixp23xx/io.h
- *
- * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
- * Maintainer: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright (C) 2003-2005 Intel Corp.
- * Copyright (C) 2005 MontaVista Software, Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-#define __io(p)         ((void __iomem*)((p) + IXP23XX_PCI_IO_VIRT))
-#define __mem_pci(a)    (a)
-
-#include <linux/kernel.h>       /* For BUG */
-
-static inline void __iomem *
-ixp23xx_ioremap(unsigned long addr, unsigned long size, unsigned int mtype)
-{
-        if (addr >= IXP23XX_PCI_MEM_START &&
-                addr <= IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE) {
-                if (addr + size > IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE)
-                        return NULL;
-
-                return (void __iomem *)
-                        ((addr - IXP23XX_PCI_MEM_START) + IXP23XX_PCI_MEM_VIRT);
-        }
-
-        return __arm_ioremap(addr, size, mtype);
-}
-
-static inline void
-ixp23xx_iounmap(void __iomem *addr)
-{
-        if ((((u32)addr) >= IXP23XX_PCI_MEM_VIRT) &&
-            (((u32)addr) < IXP23XX_PCI_MEM_VIRT + IXP23XX_PCI_MEM_SIZE))
-                return;
-
-        __iounmap(addr);
-}
-
-#define __arch_ioremap(a,s,f)   ixp23xx_ioremap(a,s,f)
-#define __arch_iounmap(a)       ixp23xx_iounmap(a)
-
-
-#endif
diff --git a/include/asm-arm/arch-ixp23xx/irqs.h b/include/asm-arm/arch-ixp23xx/irqs.h
deleted file mode 100644
index 27c580898958..000000000000
--- a/include/asm-arm/arch-ixp23xx/irqs.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * include/asm-arm/arch-ixp23xx/irqs.h
- *
- * IRQ definitions for IXP23XX based systems
- *
- * Author: Naeem Afzal <naeem.m.afzal@intel.com>
- *
- * Copyright (C) 2003-2004 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H
-
-#define NR_IXP23XX_IRQS                 IRQ_IXP23XX_INTB+1
-#define IRQ_IXP23XX_EXTIRQS             NR_IXP23XX_IRQS
-
-
-#define IRQ_IXP23XX_DBG0                0       /* Debug/Execution/MBox */
-#define IRQ_IXP23XX_DBG1                1       /* Debug/Execution/MBox */
-#define IRQ_IXP23XX_NPE_TRG             2       /* npe_trigger */
-#define IRQ_IXP23XX_TIMER1              3       /* Timer[0] */
-#define IRQ_IXP23XX_TIMER2              4       /* Timer[1] */
-#define IRQ_IXP23XX_TIMESTAMP           5       /* Timer[2], Time-stamp */
-#define IRQ_IXP23XX_WDOG                6       /* Time[3], Watchdog Timer */
-#define IRQ_IXP23XX_PCI_DBELL           7       /* PCI Doorbell */
-#define IRQ_IXP23XX_PCI_DMA1            8       /* PCI DMA Channel 1 */
-#define IRQ_IXP23XX_PCI_DMA2            9       /* PCI DMA Channel 2 */
-#define IRQ_IXP23XX_PCI_DMA3            10      /* PCI DMA Channel 3 */
-#define IRQ_IXP23XX_PCI_INT_RPH         11      /* pcxg_pci_int_rph */
-#define IRQ_IXP23XX_CPP_PMU             12      /* xpxg_pm_int_rpl */
-#define IRQ_IXP23XX_SWINT0              13      /* S/W Interrupt0 */
-#define IRQ_IXP23XX_SWINT1              14      /* S/W Interrupt1 */
-#define IRQ_IXP23XX_UART2               15      /* UART1 Interrupt */
-#define IRQ_IXP23XX_UART1               16      /* UART0 Interrupt */
-#define IRQ_IXP23XX_XSI_PMU_ROLLOVER    17      /* AHB Performance M. Unit counter rollover */
-#define IRQ_IXP23XX_XSI_AHB_PM0         18      /* intr_pm_o */
-#define IRQ_IXP23XX_XSI_AHB_ECE0        19      /* intr_ece_o */
-#define IRQ_IXP23XX_XSI_AHB_GASKET      20      /* gas_intr_o */
-#define IRQ_IXP23XX_XSI_CPP             21      /* xsi2cpp_int */
-#define IRQ_IXP23XX_CPP_XSI             22      /* cpp2xsi_int */
-#define IRQ_IXP23XX_ME_ATTN0            23      /* ME_ATTN */
-#define IRQ_IXP23XX_ME_ATTN1            24      /* ME_ATTN */
-#define IRQ_IXP23XX_ME_ATTN2            25      /* ME_ATTN */
-#define IRQ_IXP23XX_ME_ATTN3            26      /* ME_ATTN */
-#define IRQ_IXP23XX_PCI_ERR_RPH         27      /* PCXG_PCI_ERR_RPH */
-#define IRQ_IXP23XX_D0XG_ECC_CORR       28      /* D0XG_DRAM_ECC_CORR */
-#define IRQ_IXP23XX_D0XG_ECC_UNCORR     29      /* D0XG_DRAM_ECC_UNCORR */
-#define IRQ_IXP23XX_SRAM_ERR1           30      /* SRAM1_ERR */
-#define IRQ_IXP23XX_SRAM_ERR0           31      /* SRAM0_ERR */
-#define IRQ_IXP23XX_MEDIA_ERR           32      /* MEDIA_ERR */
-#define IRQ_IXP23XX_STH_DRAM_ECC_MAJ    33      /* STH_DRAM0_ECC_MAJ */
-#define IRQ_IXP23XX_GPIO6               34      /* GPIO0 interrupts */
-#define IRQ_IXP23XX_GPIO7               35      /* GPIO1 interrupts */
-#define IRQ_IXP23XX_GPIO8               36      /* GPIO2 interrupts */
-#define IRQ_IXP23XX_GPIO9               37      /* GPIO3 interrupts */
-#define IRQ_IXP23XX_GPIO10              38      /* GPIO4 interrupts */
-#define IRQ_IXP23XX_GPIO11              39      /* GPIO5 interrupts */
-#define IRQ_IXP23XX_GPIO12              40      /* GPIO6 interrupts */
-#define IRQ_IXP23XX_GPIO13              41      /* GPIO7 interrupts */
-#define IRQ_IXP23XX_GPIO14              42      /* GPIO8 interrupts */
-#define IRQ_IXP23XX_GPIO15              43      /* GPIO9 interrupts */
-#define IRQ_IXP23XX_SHAC_RING0          44      /* SHAC Ring Full */
-#define IRQ_IXP23XX_SHAC_RING1          45      /* SHAC Ring Full */
-#define IRQ_IXP23XX_SHAC_RING2          46      /* SHAC Ring Full */
-#define IRQ_IXP23XX_SHAC_RING3          47      /* SHAC Ring Full */
-#define IRQ_IXP23XX_SHAC_RING4          48      /* SHAC Ring Full */
-#define IRQ_IXP23XX_SHAC_RING5          49      /* SHAC Ring Full */
-#define IRQ_IXP23XX_SHAC_RING6          50      /* SHAC RING Full */
-#define IRQ_IXP23XX_SHAC_RING7          51      /* SHAC Ring Full */
-#define IRQ_IXP23XX_SHAC_RING8          52      /* SHAC Ring Full */
-#define IRQ_IXP23XX_SHAC_RING9          53      /* SHAC Ring Full */
-#define IRQ_IXP23XX_SHAC_RING10         54      /* SHAC Ring Full */
-#define IRQ_IXP23XX_SHAC_RING11         55      /* SHAC Ring Full */
-#define IRQ_IXP23XX_ME_THREAD_A0_ME0    56      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A1_ME0    57      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A2_ME0    58      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A3_ME0    59      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A4_ME0    60      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A5_ME0    61      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A6_ME0    62      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A7_ME0    63      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A8_ME1    64      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A9_ME1    65      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A10_ME1   66      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A11_ME1   67      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A12_ME1   68      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A13_ME1   69      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A14_ME1   70      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A15_ME1   71      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A16_ME2   72      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A17_ME2   73      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A18_ME2   74      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A19_ME2   75      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A20_ME2   76      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A21_ME2   77      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A22_ME2   78      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A23_ME2   79      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A24_ME3   80      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A25_ME3   81      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A26_ME3   82      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A27_ME3   83      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A28_ME3   84      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A29_ME3   85      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A30_ME3   86      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A31_ME3   87      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_B0_ME0    88      /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B1_ME0    89      /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B2_ME0    90      /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B3_ME0    91      /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B4_ME0    92      /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B5_ME0    93      /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B6_ME0    94      /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B7_ME0    95      /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B8_ME1    96      /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B9_ME1    97      /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B10_ME1   98      /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B11_ME1   99      /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B12_ME1   100     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B13_ME1   101     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B14_ME1   102     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B15_ME1   103     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B16_ME2   104     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B17_ME2   105     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B18_ME2   106     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B19_ME2   107     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B20_ME2   108     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B21_ME2   109     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B22_ME2   110     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B23_ME2   111     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B24_ME3   112     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B25_ME3   113     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B26_ME3   114     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B27_ME3   115     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B28_ME3   116     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B29_ME3   117     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B30_ME3   118     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B31_ME3   119     /* ME_THREAD_B */
-
-#define NUM_IXP23XX_RAW_IRQS            120
-
-#define IRQ_IXP23XX_INTA                120     /* Indirect pcxg_pci_int_rph */
-#define IRQ_IXP23XX_INTB                121     /* Indirect pcxg_pci_int_rph */
-
-#define NR_IXP23XX_IRQ                  (IRQ_IXP23XX_INTB + 1)
-
-/*
- * We default to 32 per-board IRQs. Increase this number if you need
- * more, but keep it realistic.
- */
-#define NR_IXP23XX_MACH_IRQS            32
-
-#define NR_IRQS                         (NR_IXP23XX_IRQS + NR_IXP23XX_MACH_IRQS)
-
-#define IXP23XX_MACH_IRQ(irq)           (NR_IXP23XX_IRQ + (irq))
-
-
-/*
- * IXDP2351-specific interrupts
- */
-
-/*
- * External PCI interrupts signaled through INTB
- *
- */
-#define IXDP2351_INTB_IRQ_BASE          0
-#define IRQ_IXDP2351_INTA_82546         IXP23XX_MACH_IRQ(0)
-#define IRQ_IXDP2351_INTB_82546         IXP23XX_MACH_IRQ(1)
-#define IRQ_IXDP2351_SPCI_DB_0          IXP23XX_MACH_IRQ(2)
-#define IRQ_IXDP2351_SPCI_DB_1          IXP23XX_MACH_IRQ(3)
-#define IRQ_IXDP2351_SPCI_PMC_INTA      IXP23XX_MACH_IRQ(4)
-#define IRQ_IXDP2351_SPCI_PMC_INTB      IXP23XX_MACH_IRQ(5)
-#define IRQ_IXDP2351_SPCI_PMC_INTC      IXP23XX_MACH_IRQ(6)
-#define IRQ_IXDP2351_SPCI_PMC_INTD      IXP23XX_MACH_IRQ(7)
-#define IRQ_IXDP2351_SPCI_FIC           IXP23XX_MACH_IRQ(8)
-
-#define IXDP2351_INTB_IRQ_BIT(irq)      (irq - IXP23XX_MACH_IRQ(0))
-#define IXDP2351_INTB_IRQ_MASK(irq)     (1 << IXDP2351_INTB_IRQ_BIT(irq))
-#define IXDP2351_INTB_IRQ_VALID         0x01FF
-#define IXDP2351_INTB_IRQ_NUM           16
-
-/*
- * Other external interrupts signaled through INTA
- */
-#define IXDP2351_INTA_IRQ_BASE          16
-#define IRQ_IXDP2351_IPMI_FROM          IXP23XX_MACH_IRQ(16)
-#define IRQ_IXDP2351_125US              IXP23XX_MACH_IRQ(17)
-#define IRQ_IXDP2351_DB_0_ADD           IXP23XX_MACH_IRQ(18)
-#define IRQ_IXDP2351_DB_1_ADD           IXP23XX_MACH_IRQ(19)
-#define IRQ_IXDP2351_DEBUG1             IXP23XX_MACH_IRQ(20)
-#define IRQ_IXDP2351_ADD_UART           IXP23XX_MACH_IRQ(21)
-#define IRQ_IXDP2351_FIC_ADD            IXP23XX_MACH_IRQ(24)
-#define IRQ_IXDP2351_CS8900             IXP23XX_MACH_IRQ(25)
-#define IRQ_IXDP2351_BBSRAM             IXP23XX_MACH_IRQ(26)
-#define IRQ_IXDP2351_CONFIG_MEDIA       IXP23XX_MACH_IRQ(27)
-#define IRQ_IXDP2351_CLOCK_REF          IXP23XX_MACH_IRQ(28)
-#define IRQ_IXDP2351_A10_NP             IXP23XX_MACH_IRQ(29)
-#define IRQ_IXDP2351_A11_NP             IXP23XX_MACH_IRQ(30)
-#define IRQ_IXDP2351_DEBUG_NP           IXP23XX_MACH_IRQ(31)
-
-#define IXDP2351_INTA_IRQ_BIT(irq)      (irq - IXP23XX_MACH_IRQ(16))
-#define IXDP2351_INTA_IRQ_MASK(irq)     (1 << IXDP2351_INTA_IRQ_BIT(irq))
-#define IXDP2351_INTA_IRQ_VALID         0xFF3F
-#define IXDP2351_INTA_IRQ_NUM           16
-
-
-/*
- * ADI RoadRunner IRQs
- */
-#define IRQ_ROADRUNNER_PCI_INTA         IRQ_IXP23XX_INTA
-#define IRQ_ROADRUNNER_PCI_INTB         IRQ_IXP23XX_INTB
-#define IRQ_ROADRUNNER_PCI_INTC         IRQ_IXP23XX_GPIO11
-#define IRQ_ROADRUNNER_PCI_INTD         IRQ_IXP23XX_GPIO12
-
-/*
- * Put new board definitions here
- */
-
-
-#endif
diff --git a/include/asm-arm/arch-ixp23xx/ixdp2351.h b/include/asm-arm/arch-ixp23xx/ixdp2351.h
deleted file mode 100644
index d5e8a43d7bbd..000000000000
--- a/include/asm-arm/arch-ixp23xx/ixdp2351.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * include/asm-arm/arch-ixp23xx/ixdp2351.h
- *
- * Register and other defines for IXDP2351
- *
- * Copyright (c) 2002-2004 Intel Corp.
- * Copytight (c) 2005 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#ifndef __ASM_ARCH_IXDP2351_H
-#define __ASM_ARCH_IXDP2351_H
-
-/*
- * NP module memory map
- */
-#define IXDP2351_NP_PHYS_BASE           (IXP23XX_EXP_BUS_CS4_BASE)
-#define IXDP2351_NP_PHYS_SIZE           0x00100000
-#define IXDP2351_NP_VIRT_BASE           0xeff00000
-
-#define IXDP2351_VIRT_CS8900_BASE       (IXDP2351_NP_VIRT_BASE)
-#define IXDP2351_VIRT_CS8900_END        (IXDP2351_VIRT_CS8900_BASE + 16)
-
-#define IXDP2351_VIRT_NP_CPLD_BASE      (IXP23XX_EXP_BUS_CS4_BASE_VIRT + 0x00010000)
-
-#define IXDP2351_NP_CPLD_REG(reg) ((volatile u16 *)(IXDP2351_VIRT_NP_CPLD_BASE + reg))
-
-#define IXDP2351_NP_CPLD_RESET1_REG     IXDP2351_NP_CPLD_REG(0x00)
-#define IXDP2351_NP_CPLD_LED_REG        IXDP2351_NP_CPLD_REG(0x02)
-#define IXDP2351_NP_CPLD_VERSION_REG    IXDP2351_NP_CPLD_REG(0x04)
-
-/*
- * Base board module memory map
- */
-
-#define IXDP2351_BB_BASE_PHYS           (IXP23XX_EXP_BUS_CS5_BASE)
-#define IXDP2351_BB_SIZE                0x01000000
-#define IXDP2351_BB_BASE_VIRT           (0xee000000)
-
-#define IXDP2351_BB_AREA_BASE(offset)   (IXDP2351_BB_BASE_VIRT + offset)
-
-#define IXDP2351_VIRT_NVRAM_BASE        IXDP2351_BB_AREA_BASE(0x0)
-#define IXDP2351_NVRAM_SIZE             (0x20000)
-
-#define IXDP2351_VIRT_MB_IXF1104_BASE   IXDP2351_BB_AREA_BASE(0x00020000)
-#define IXDP2351_VIRT_ADD_UART_BASE     IXDP2351_BB_AREA_BASE(0x000240C0)
-#define IXDP2351_VIRT_FIC_BASE          IXDP2351_BB_AREA_BASE(0x00200000)
-#define IXDP2351_VIRT_DB0_BASE          IXDP2351_BB_AREA_BASE(0x00400000)
-#define IXDP2351_VIRT_DB1_BASE          IXDP2351_BB_AREA_BASE(0x00600000)
-#define IXDP2351_VIRT_CPLD_BASE         IXDP2351_BB_AREA_BASE(0x00024000)
-
-/*
- * On board CPLD registers
- */
-#define IXDP2351_CPLD_BB_REG(reg) ((volatile u16 *)(IXDP2351_VIRT_CPLD_BASE + reg))
-
-#define IXDP2351_CPLD_RESET0_REG        IXDP2351_CPLD_BB_REG(0x00)
-#define IXDP2351_CPLD_RESET1_REG        IXDP2351_CPLD_BB_REG(0x04)
-
-#define IXDP2351_CPLD_RESET1_MAGIC      0x55AA
-#define IXDP2351_CPLD_RESET1_ENABLE     0x8000
-
-#define IXDP2351_CPLD_FPGA_CONFIG_REG   IXDP2351_CPLD_BB_REG(0x08)
-#define IXDP2351_CPLD_INTB_MASK_SET_REG IXDP2351_CPLD_BB_REG(0x10)
-#define IXDP2351_CPLD_INTA_MASK_SET_REG IXDP2351_CPLD_BB_REG(0x14)
-#define IXDP2351_CPLD_INTB_STAT_REG     IXDP2351_CPLD_BB_REG(0x18)
-#define IXDP2351_CPLD_INTA_STAT_REG     IXDP2351_CPLD_BB_REG(0x1C)
-#define IXDP2351_CPLD_INTB_RAW_REG      IXDP2351_CPLD_BB_REG(0x20)      /* read */
-#define IXDP2351_CPLD_INTA_RAW_REG      IXDP2351_CPLD_BB_REG(0x24)      /* read */
-#define IXDP2351_CPLD_INTB_MASK_CLR_REG IXDP2351_CPLD_INTB_RAW_REG      /* write */
-#define IXDP2351_CPLD_INTA_MASK_CLR_REG IXDP2351_CPLD_INTA_RAW_REG      /* write */
-#define IXDP2351_CPLD_INTB_SIM_REG      IXDP2351_CPLD_BB_REG(0x28)
-#define IXDP2351_CPLD_INTA_SIM_REG      IXDP2351_CPLD_BB_REG(0x2C)
-        /* Interrupt bits are defined in irqs.h */
-#define IXDP2351_CPLD_BB_GBE0_REG       IXDP2351_CPLD_BB_REG(0x30)
-#define IXDP2351_CPLD_BB_GBE1_REG       IXDP2351_CPLD_BB_REG(0x34)
-
-/* #define IXDP2351_CPLD_BB_MISC_REG    IXDP2351_CPLD_REG(0x1C) */
-/* #define IXDP2351_CPLD_BB_MISC_REV_MASK       0xFF            */
-/* #define IXDP2351_CPLD_BB_GDXCS0_REG  IXDP2351_CPLD_REG(0x24) */
-/* #define IXDP2351_CPLD_BB_GDXCS1_REG  IXDP2351_CPLD_REG(0x28) */
-/* #define IXDP2351_CPLD_BB_CLOCK_REG   IXDP2351_CPLD_REG(0x04) */
-
-
-#endif
diff --git a/include/asm-arm/arch-ixp23xx/ixp23xx.h b/include/asm-arm/arch-ixp23xx/ixp23xx.h
deleted file mode 100644
index 3927b1d61b17..000000000000
--- a/include/asm-arm/arch-ixp23xx/ixp23xx.h
+++ /dev/null
@@ -1,298 +0,0 @@
-/*
- * include/asm-arm/arch-ixp23xx/ixp23xx.h
- *
- * Register definitions for IXP23XX
- *
- * Copyright (C) 2003-2005 Intel Corporation.
- * Copyright (C) 2005 MontaVista Software, Inc.
- *
- * Maintainer: Deepak Saxena <dsaxena@plexity.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_IXP23XX_H
-#define __ASM_ARCH_IXP23XX_H
-
-/*
- * IXP2300 linux memory map:
- *
- * virt         phys            size
- * fffd0000     a0000000        64K             XSI2CPP_CSR
- * fffc0000     c4000000        4K              EXP_CFG
- * fff00000     c8000000        64K             PERIPHERAL
- * fe000000     1c0000000       16M             CAP_CSR
- * fd000000     1c8000000       16M             MSF_CSR
- * fb000000                     16M             ---
- * fa000000     1d8000000       32M             PCI_IO
- * f8000000     1da000000       32M             PCI_CFG
- * f6000000     1de000000       32M             PCI_CREG
- * f4000000                     32M             ---
- * f0000000     1e0000000       64M             PCI_MEM
- * e[c-f]000000                                 per-platform mappings
- */
-
-
-/****************************************************************************
- * Static mappings.
- ****************************************************************************/
-#define IXP23XX_XSI2CPP_CSR_PHYS        0xa0000000
-#define IXP23XX_XSI2CPP_CSR_VIRT        0xfffd0000
-#define IXP23XX_XSI2CPP_CSR_SIZE        0x00010000
-
-#define IXP23XX_EXP_CFG_PHYS            0xc4000000
-#define IXP23XX_EXP_CFG_VIRT            0xfffc0000
-#define IXP23XX_EXP_CFG_SIZE            0x00001000
-
-#define IXP23XX_PERIPHERAL_PHYS         0xc8000000
-#define IXP23XX_PERIPHERAL_VIRT         0xfff00000
-#define IXP23XX_PERIPHERAL_SIZE         0x00010000
-
-#define IXP23XX_CAP_CSR_PHYS            0x1c0000000ULL
-#define IXP23XX_CAP_CSR_VIRT            0xfe000000
-#define IXP23XX_CAP_CSR_SIZE            0x01000000
-
-#define IXP23XX_MSF_CSR_PHYS            0x1c8000000ULL
-#define IXP23XX_MSF_CSR_VIRT            0xfd000000
-#define IXP23XX_MSF_CSR_SIZE            0x01000000
-
-#define IXP23XX_PCI_IO_PHYS             0x1d8000000ULL
-#define IXP23XX_PCI_IO_VIRT             0xfa000000
-#define IXP23XX_PCI_IO_SIZE             0x02000000
-
-#define IXP23XX_PCI_CFG_PHYS            0x1da000000ULL
-#define IXP23XX_PCI_CFG_VIRT            0xf8000000
-#define IXP23XX_PCI_CFG_SIZE            0x02000000
-#define IXP23XX_PCI_CFG0_VIRT           IXP23XX_PCI_CFG_VIRT
-#define IXP23XX_PCI_CFG1_VIRT           (IXP23XX_PCI_CFG_VIRT + 0x01000000)
-
-#define IXP23XX_PCI_CREG_PHYS           0x1de000000ULL
-#define IXP23XX_PCI_CREG_VIRT           0xf6000000
-#define IXP23XX_PCI_CREG_SIZE           0x02000000
-#define IXP23XX_PCI_CSR_VIRT            (IXP23XX_PCI_CREG_VIRT + 0x01000000)
-
-#define IXP23XX_PCI_MEM_START           0xe0000000
-#define IXP23XX_PCI_MEM_PHYS            0x1e0000000ULL
-#define IXP23XX_PCI_MEM_VIRT            0xf0000000
-#define IXP23XX_PCI_MEM_SIZE            0x04000000
-
-
-/****************************************************************************
- * XSI2CPP CSRs.
- ****************************************************************************/
-#define IXP23XX_XSI2CPP_REG(x)          ((volatile unsigned long *)(IXP23XX_XSI2CPP_CSR_VIRT + (x)))
-#define IXP23XX_CPP2XSI_CURR_XFER_REG3  IXP23XX_XSI2CPP_REG(0xf8)
-#define IXP23XX_CPP2XSI_ADDR_31         (1 << 19)
-#define IXP23XX_CPP2XSI_PSH_OFF         (1 << 20)
-#define IXP23XX_CPP2XSI_COH_OFF         (1 << 21)
-
-
-/****************************************************************************
- * Expansion Bus Config.
- ****************************************************************************/
-#define IXP23XX_EXP_CFG_REG(x)          ((volatile unsigned long *)(IXP23XX_EXP_CFG_VIRT + (x)))
-#define IXP23XX_EXP_CS0                 IXP23XX_EXP_CFG_REG(0x00)
-#define IXP23XX_EXP_CS1                 IXP23XX_EXP_CFG_REG(0x04)
-#define IXP23XX_EXP_CS2                 IXP23XX_EXP_CFG_REG(0x08)
-#define IXP23XX_EXP_CS3                 IXP23XX_EXP_CFG_REG(0x0c)
-#define IXP23XX_EXP_CS4                 IXP23XX_EXP_CFG_REG(0x10)
-#define IXP23XX_EXP_CS5                 IXP23XX_EXP_CFG_REG(0x14)
-#define IXP23XX_EXP_CS6                 IXP23XX_EXP_CFG_REG(0x18)
-#define IXP23XX_EXP_CS7                 IXP23XX_EXP_CFG_REG(0x1c)
-#define IXP23XX_FLASH_WRITABLE          (0x2)
-#define IXP23XX_FLASH_BUS8              (0x1)
-
-#define IXP23XX_EXP_CFG0                IXP23XX_EXP_CFG_REG(0x20)
-#define IXP23XX_EXP_CFG1                IXP23XX_EXP_CFG_REG(0x24)
-#define IXP23XX_EXP_CFG0_MEM_MAP                (1 << 31)
-#define IXP23XX_EXP_CFG0_XSCALE_SPEED_SEL       (3 << 22)
-#define IXP23XX_EXP_CFG0_XSCALE_SPEED_EN        (1 << 21)
-#define IXP23XX_EXP_CFG0_CPP_SPEED_SEL          (3 << 19)
-#define IXP23XX_EXP_CFG0_CPP_SPEED_EN           (1 << 18)
-#define IXP23XX_EXP_CFG0_PCI_SWIN               (3 << 16)
-#define IXP23XX_EXP_CFG0_PCI_DWIN               (3 << 14)
-#define IXP23XX_EXP_CFG0_PCI33_MODE             (1 << 13)
-#define IXP23XX_EXP_CFG0_QDR_SPEED_SEL          (1 << 12)
-#define IXP23XX_EXP_CFG0_CPP_DIV_SEL            (1 << 5)
-#define IXP23XX_EXP_CFG0_XSI_NOT_PRES           (1 << 4)
-#define IXP23XX_EXP_CFG0_PROM_BOOT              (1 << 3)
-#define IXP23XX_EXP_CFG0_PCI_ARB                (1 << 2)
-#define IXP23XX_EXP_CFG0_PCI_HOST               (1 << 1)
-#define IXP23XX_EXP_CFG0_FLASH_WIDTH            (1 << 0)
-
-#define IXP23XX_EXP_UNIT_FUSE           IXP23XX_EXP_CFG_REG(0x28)
-#define IXP23XX_EXP_MSF_MUX             IXP23XX_EXP_CFG_REG(0x30)
-#define IXP23XX_EXP_CFG_FUSE            IXP23XX_EXP_CFG_REG(0x34)
-
-#define IXP23XX_EXP_BUS_PHYS            0x90000000
-#define IXP23XX_EXP_BUS_WINDOW_SIZE     0x01000000
-
-#define IXP23XX_EXP_BUS_CS0_BASE        (IXP23XX_EXP_BUS_PHYS + 0x00000000)
-#define IXP23XX_EXP_BUS_CS1_BASE        (IXP23XX_EXP_BUS_PHYS + 0x01000000)
-#define IXP23XX_EXP_BUS_CS2_BASE        (IXP23XX_EXP_BUS_PHYS + 0x02000000)
-#define IXP23XX_EXP_BUS_CS3_BASE        (IXP23XX_EXP_BUS_PHYS + 0x03000000)
-#define IXP23XX_EXP_BUS_CS4_BASE        (IXP23XX_EXP_BUS_PHYS + 0x04000000)
-#define IXP23XX_EXP_BUS_CS5_BASE        (IXP23XX_EXP_BUS_PHYS + 0x05000000)
-#define IXP23XX_EXP_BUS_CS6_BASE        (IXP23XX_EXP_BUS_PHYS + 0x06000000)
-#define IXP23XX_EXP_BUS_CS7_BASE        (IXP23XX_EXP_BUS_PHYS + 0x07000000)
-
-
-/****************************************************************************
- * Peripherals.
- ****************************************************************************/
-#define IXP23XX_UART1_VIRT              (IXP23XX_PERIPHERAL_VIRT + 0x0000)
-#define IXP23XX_UART2_VIRT              (IXP23XX_PERIPHERAL_VIRT + 0x1000)
-#define IXP23XX_PMU_VIRT                (IXP23XX_PERIPHERAL_VIRT + 0x2000)
-#define IXP23XX_INTC_VIRT               (IXP23XX_PERIPHERAL_VIRT + 0x3000)
-#define IXP23XX_GPIO_VIRT               (IXP23XX_PERIPHERAL_VIRT + 0x4000)
-#define IXP23XX_TIMER_VIRT              (IXP23XX_PERIPHERAL_VIRT + 0x5000)
-#define IXP23XX_NPE0_VIRT               (IXP23XX_PERIPHERAL_VIRT + 0x6000)
-#define IXP23XX_DSR_VIRT                (IXP23XX_PERIPHERAL_VIRT + 0x7000)
-#define IXP23XX_NPE1_VIRT               (IXP23XX_PERIPHERAL_VIRT + 0x8000)
-#define IXP23XX_ETH0_VIRT               (IXP23XX_PERIPHERAL_VIRT + 0x9000)
-#define IXP23XX_ETH1_VIRT               (IXP23XX_PERIPHERAL_VIRT + 0xA000)
-#define IXP23XX_GIG0_VIRT               (IXP23XX_PERIPHERAL_VIRT + 0xB000)
-#define IXP23XX_GIG1_VIRT               (IXP23XX_PERIPHERAL_VIRT + 0xC000)
-#define IXP23XX_DDRS_VIRT               (IXP23XX_PERIPHERAL_VIRT + 0xD000)
-
-#define IXP23XX_UART1_PHYS              (IXP23XX_PERIPHERAL_PHYS + 0x0000)
-#define IXP23XX_UART2_PHYS              (IXP23XX_PERIPHERAL_PHYS + 0x1000)
-#define IXP23XX_PMU_PHYS                (IXP23XX_PERIPHERAL_PHYS + 0x2000)
-#define IXP23XX_INTC_PHYS               (IXP23XX_PERIPHERAL_PHYS + 0x3000)
-#define IXP23XX_GPIO_PHYS               (IXP23XX_PERIPHERAL_PHYS + 0x4000)
-#define IXP23XX_TIMER_PHYS              (IXP23XX_PERIPHERAL_PHYS + 0x5000)
-#define IXP23XX_NPE0_PHYS               (IXP23XX_PERIPHERAL_PHYS + 0x6000)
-#define IXP23XX_DSR_PHYS                (IXP23XX_PERIPHERAL_PHYS + 0x7000)
-#define IXP23XX_NPE1_PHYS               (IXP23XX_PERIPHERAL_PHYS + 0x8000)
-#define IXP23XX_ETH0_PHYS               (IXP23XX_PERIPHERAL_PHYS + 0x9000)
-#define IXP23XX_ETH1_PHYS               (IXP23XX_PERIPHERAL_PHYS + 0xA000)
-#define IXP23XX_GIG0_PHYS               (IXP23XX_PERIPHERAL_PHYS + 0xB000)
-#define IXP23XX_GIG1_PHYS               (IXP23XX_PERIPHERAL_PHYS + 0xC000)
-#define IXP23XX_DDRS_PHYS               (IXP23XX_PERIPHERAL_PHYS + 0xD000)
-
-
-/****************************************************************************
- * Interrupt controller.
- ****************************************************************************/
-#define IXP23XX_INTC_REG(x)              ((volatile unsigned long *)(IXP23XX_INTC_VIRT + (x)))
-#define IXP23XX_INTR_ST1                IXP23XX_INTC_REG(0x00)
-#define IXP23XX_INTR_ST2                IXP23XX_INTC_REG(0x04)
-#define IXP23XX_INTR_ST3                IXP23XX_INTC_REG(0x08)
-#define IXP23XX_INTR_ST4                IXP23XX_INTC_REG(0x0c)
-#define IXP23XX_INTR_EN1                IXP23XX_INTC_REG(0x10)
-#define IXP23XX_INTR_EN2                IXP23XX_INTC_REG(0x14)
-#define IXP23XX_INTR_EN3                IXP23XX_INTC_REG(0x18)
-#define IXP23XX_INTR_EN4                IXP23XX_INTC_REG(0x1c)
-#define IXP23XX_INTR_SEL1               IXP23XX_INTC_REG(0x20)
-#define IXP23XX_INTR_SEL2               IXP23XX_INTC_REG(0x24)
-#define IXP23XX_INTR_SEL3               IXP23XX_INTC_REG(0x28)
-#define IXP23XX_INTR_SEL4               IXP23XX_INTC_REG(0x2c)
-#define IXP23XX_INTR_IRQ_ST1            IXP23XX_INTC_REG(0x30)
-#define IXP23XX_INTR_IRQ_ST2            IXP23XX_INTC_REG(0x34)
-#define IXP23XX_INTR_IRQ_ST3            IXP23XX_INTC_REG(0x38)
-#define IXP23XX_INTR_IRQ_ST4            IXP23XX_INTC_REG(0x3c)
-#define IXP23XX_INTR_IRQ_ENC_ST_OFFSET  0x54
-
-
-/****************************************************************************
- * GPIO.
- ****************************************************************************/
-#define IXP23XX_GPIO_REG(x)             ((volatile unsigned long *)(IXP23XX_GPIO_VIRT + (x)))
-#define IXP23XX_GPIO_GPOUTR             IXP23XX_GPIO_REG(0x00)
-#define IXP23XX_GPIO_GPOER              IXP23XX_GPIO_REG(0x04)
-#define IXP23XX_GPIO_GPINR              IXP23XX_GPIO_REG(0x08)
-#define IXP23XX_GPIO_GPISR              IXP23XX_GPIO_REG(0x0c)
-#define IXP23XX_GPIO_GPIT1R             IXP23XX_GPIO_REG(0x10)
-#define IXP23XX_GPIO_GPIT2R             IXP23XX_GPIO_REG(0x14)
-#define IXP23XX_GPIO_GPCLKR             IXP23XX_GPIO_REG(0x18)
-#define IXP23XX_GPIO_GPDBSELR           IXP23XX_GPIO_REG(0x1c)
-
-#define IXP23XX_GPIO_STYLE_MASK         0x7
-#define IXP23XX_GPIO_STYLE_ACTIVE_HIGH  0x0
-#define IXP23XX_GPIO_STYLE_ACTIVE_LOW   0x1
-#define IXP23XX_GPIO_STYLE_RISING_EDGE  0x2
-#define IXP23XX_GPIO_STYLE_FALLING_EDGE 0x3
-#define IXP23XX_GPIO_STYLE_TRANSITIONAL 0x4
-
-#define IXP23XX_GPIO_STYLE_SIZE         3
-
-
-/****************************************************************************
- * Timer.
- ****************************************************************************/
-#define IXP23XX_TIMER_REG(x)            ((volatile unsigned long *)(IXP23XX_TIMER_VIRT + (x)))
-#define IXP23XX_TIMER_CONT              IXP23XX_TIMER_REG(0x00)
-#define IXP23XX_TIMER1_TIMESTAMP        IXP23XX_TIMER_REG(0x04)
-#define IXP23XX_TIMER1_RELOAD           IXP23XX_TIMER_REG(0x08)
-#define IXP23XX_TIMER2_TIMESTAMP        IXP23XX_TIMER_REG(0x0c)
-#define IXP23XX_TIMER2_RELOAD           IXP23XX_TIMER_REG(0x10)
-#define IXP23XX_TIMER_WDOG              IXP23XX_TIMER_REG(0x14)
-#define IXP23XX_TIMER_WDOG_EN           IXP23XX_TIMER_REG(0x18)
-#define IXP23XX_TIMER_WDOG_KEY          IXP23XX_TIMER_REG(0x1c)
-#define IXP23XX_TIMER_WDOG_KEY_MAGIC    0x482e
-#define IXP23XX_TIMER_STATUS            IXP23XX_TIMER_REG(0x20)
-#define IXP23XX_TIMER_SOFT_RESET        IXP23XX_TIMER_REG(0x24)
-#define IXP23XX_TIMER_SOFT_RESET_EN     IXP23XX_TIMER_REG(0x28)
-
-#define IXP23XX_TIMER_ENABLE            (1 << 0)
-#define IXP23XX_TIMER_ONE_SHOT          (1 << 1)
-/* Low order bits of reload value ignored */
-#define IXP23XX_TIMER_RELOAD_MASK       (0x3)
-#define IXP23XX_TIMER_DISABLED          (0x0)
-#define IXP23XX_TIMER1_INT_PEND         (1 << 0)
-#define IXP23XX_TIMER2_INT_PEND         (1 << 1)
-#define IXP23XX_TIMER_STATUS_TS_PEND    (1 << 2)
-#define IXP23XX_TIMER_STATUS_WDOG_PEND  (1 << 3)
-#define IXP23XX_TIMER_STATUS_WARM_RESET (1 << 4)
-
-
-/****************************************************************************
- * CAP CSRs.
- ****************************************************************************/
-#define IXP23XX_GLOBAL_REG(x)           ((volatile unsigned long *)(IXP23XX_CAP_CSR_VIRT + 0x4a00 + (x)))
-#define IXP23XX_PRODUCT_ID              IXP23XX_GLOBAL_REG(0x00)
-#define IXP23XX_MISC_CONTROL            IXP23XX_GLOBAL_REG(0x04)
-#define IXP23XX_MSF_CLK_CNTRL           IXP23XX_GLOBAL_REG(0x08)
-#define IXP23XX_RESET0                  IXP23XX_GLOBAL_REG(0x0c)
-#define IXP23XX_RESET1                  IXP23XX_GLOBAL_REG(0x10)
-#define IXP23XX_STRAP_OPTIONS           IXP23XX_GLOBAL_REG(0x18)
-
-#define IXP23XX_ENABLE_WATCHDOG         (1 << 24)
-#define IXP23XX_SHPC_INIT_COMP          (1 << 21)
-#define IXP23XX_RST_ALL                 (1 << 16)
-#define IXP23XX_RESET_PCI               (1 << 2)
-#define IXP23XX_PCI_UNIT_RESET          (1 << 1)
-#define IXP23XX_XSCALE_RESET            (1 << 0)
-
-#define IXP23XX_UENGINE_CSR_VIRT_BASE   (IXP23XX_CAP_CSR_VIRT + 0x18000)
-
-
-/****************************************************************************
- * PCI CSRs.
- ****************************************************************************/
-#define IXP23XX_PCI_CREG(x)             ((volatile unsigned long *)(IXP23XX_PCI_CREG_VIRT + (x)))
-#define IXP23XX_PCI_CMDSTAT             IXP23XX_PCI_CREG(0x04)
-#define IXP23XX_PCI_SRAM_BAR            IXP23XX_PCI_CREG(0x14)
-#define IXP23XX_PCI_SDRAM_BAR           IXP23XX_PCI_CREG(0x18)
-
-
-#define IXP23XX_PCI_CSR(x)              ((volatile unsigned long *)(IXP23XX_PCI_CREG_VIRT + 0x01000000 + (x)))
-#define IXP23XX_PCI_OUT_INT_STATUS      IXP23XX_PCI_CSR(0x0030)
-#define IXP23XX_PCI_OUT_INT_MASK        IXP23XX_PCI_CSR(0x0034)
-#define IXP23XX_PCI_SRAM_BASE_ADDR_MASK IXP23XX_PCI_CSR(0x00fc)
-#define IXP23XX_PCI_DRAM_BASE_ADDR_MASK IXP23XX_PCI_CSR(0x0100)
-#define IXP23XX_PCI_CONTROL             IXP23XX_PCI_CSR(0x013c)
-#define IXP23XX_PCI_ADDR_EXT            IXP23XX_PCI_CSR(0x0140)
-#define IXP23XX_PCI_ME_PUSH_STATUS      IXP23XX_PCI_CSR(0x0148)
-#define IXP23XX_PCI_ME_PUSH_EN          IXP23XX_PCI_CSR(0x014c)
-#define IXP23XX_PCI_ERR_STATUS          IXP23XX_PCI_CSR(0x0150)
-#define IXP23XX_PCI_ERROR_STATUS        IXP23XX_PCI_CSR(0x0150)
-#define IXP23XX_PCI_ERR_ENABLE          IXP23XX_PCI_CSR(0x0154)
-#define IXP23XX_PCI_XSCALE_INT_STATUS   IXP23XX_PCI_CSR(0x0158)
-#define IXP23XX_PCI_XSCALE_INT_ENABLE   IXP23XX_PCI_CSR(0x015c)
-#define IXP23XX_PCI_CPP_ADDR_BITS       IXP23XX_PCI_CSR(0x0160)
-
-
-#endif
diff --git a/include/asm-arm/arch-ixp23xx/memory.h b/include/asm-arm/arch-ixp23xx/memory.h
deleted file mode 100644
index c3d906af9fea..000000000000
--- a/include/asm-arm/arch-ixp23xx/memory.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * include/asm-arm/arch-ixp23xx/memory.h
- *
- * Copyright (c) 2003-2004 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-#include <asm/arch/hardware.h>
-
-/*
- * Physical DRAM offset.
- */
-#define PHYS_OFFSET             (0x00000000)
-
-
-/*
- * Virtual view <-> DMA view memory address translations
- * virt_to_bus: Used to translate the virtual address to an
- *              address suitable to be passed to set_dma_addr
- * bus_to_virt: Used to convert an address for DMA operations
- *              to an address that the kernel can use.
- */
-#ifndef __ASSEMBLY__
-
-#define __virt_to_bus(v)                                                \
-        ({ unsigned int ret;                                            \
-        ret = ((__virt_to_phys(v) - 0x00000000) +                       \
-         (*((volatile int *)IXP23XX_PCI_SDRAM_BAR) & 0xfffffff0));      \
-        ret; })
-
-#define __bus_to_virt(b)                                                \
-        ({ unsigned int data;                                           \
-        data = *((volatile int *)IXP23XX_PCI_SDRAM_BAR);                \
-         __phys_to_virt((((b - (data & 0xfffffff0)) + 0x00000000))); })
-
-#define arch_is_coherent()      1
-
-#endif
-
-
-#endif
diff --git a/include/asm-arm/arch-ixp23xx/platform.h b/include/asm-arm/arch-ixp23xx/platform.h
deleted file mode 100644
index db8aa304c93d..000000000000
--- a/include/asm-arm/arch-ixp23xx/platform.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * include/asm-arm/arch-ixp23xx/platform.h
- *
- * Various bits of code used by platform-level code.
- *
- * Author: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright 2005 (c) MontaVista Software, Inc.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASSEMBLY__
-
-static inline unsigned long ixp2000_reg_read(volatile void *reg)
-{
-        return *((volatile unsigned long *)reg);
-}
-
-static inline void ixp2000_reg_write(volatile void *reg, unsigned long val)
-{
-        *((volatile unsigned long *)reg) = val;
-}
-
-static inline void ixp2000_reg_wrb(volatile void *reg, unsigned long val)
-{
-        *((volatile unsigned long *)reg) = val;
-}
-
-struct pci_sys_data;
-
-void ixp23xx_map_io(void);
-void ixp23xx_init_irq(void);
-void ixp23xx_sys_init(void);
-int ixp23xx_pci_setup(int, struct pci_sys_data *);
-void ixp23xx_pci_preinit(void);
-struct pci_bus *ixp23xx_pci_scan_bus(int, struct pci_sys_data*);
-void ixp23xx_pci_slave_init(void);
-
-extern struct sys_timer ixp23xx_timer;
-
-#define IXP23XX_UART_XTAL               14745600
-
-#ifndef __ASSEMBLY__
-/*
- * Is system memory on the XSI or CPP bus?
- */
-static inline unsigned ixp23xx_cpp_boot(void)
-{
-        return (*IXP23XX_EXP_CFG0 & IXP23XX_EXP_CFG0_XSI_NOT_PRES);
-}
-#endif
-
-
-#endif
diff --git a/include/asm-arm/arch-ixp23xx/system.h b/include/asm-arm/arch-ixp23xx/system.h
deleted file mode 100644
index 54e8a51475e6..000000000000
--- a/include/asm-arm/arch-ixp23xx/system.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * include/asm-arm/arch-ixp23xx/system.h
- *
- * Copyright (C) 2003 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <asm/arch/hardware.h>
-#include <asm/mach-types.h>
-
-static inline void arch_idle(void)
-{
-#if 0
-        if (!hlt_counter)
-                cpu_do_idle();
-#endif
-}
-
-static inline void arch_reset(char mode)
-{
-        /* First try machine specific support */
-        if (machine_is_ixdp2351()) {
-                *IXDP2351_CPLD_RESET1_REG = IXDP2351_CPLD_RESET1_MAGIC;
-                (void) *IXDP2351_CPLD_RESET1_REG;
-                *IXDP2351_CPLD_RESET1_REG = IXDP2351_CPLD_RESET1_ENABLE;
-        }
-
-        /* Use on-chip reset capability */
-        *IXP23XX_RESET0 |= IXP23XX_RST_ALL;
-}
diff --git a/include/asm-arm/arch-ixp23xx/time.h b/include/asm-arm/arch-ixp23xx/time.h
deleted file mode 100644
index f6828fdd2883..000000000000
--- a/include/asm-arm/arch-ixp23xx/time.h
+++ /dev/null
@@ -1,3 +0,0 @@
-/*
- * include/asm-arm/arch-ixp23xx/time.h
- */
diff --git a/include/asm-arm/arch-ixp23xx/timex.h b/include/asm-arm/arch-ixp23xx/timex.h
deleted file mode 100644
index 516f72fe6082..000000000000
--- a/include/asm-arm/arch-ixp23xx/timex.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * include/asm-arm/arch-ixp23xx/timex.h
- *
- * XScale architecture timex specifications
- */
-
-#define CLOCK_TICK_RATE 75000000
diff --git a/include/asm-arm/arch-ixp23xx/uncompress.h b/include/asm-arm/arch-ixp23xx/uncompress.h
deleted file mode 100644
index 16c1110f2304..000000000000
--- a/include/asm-arm/arch-ixp23xx/uncompress.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * include/asm-arm/arch-ixp23xx/uncompress.h
- *
- * Copyright (C) 2002-2004 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-
-#include <asm/arch/ixp23xx.h>
-#include <linux/serial_reg.h>
-
-#define UART_BASE       ((volatile u32 *)IXP23XX_UART1_PHYS)
-
-static inline void putc(char c)
-{
-        int j;
-
-        for (j = 0; j < 0x1000; j++) {
-                if (UART_BASE[UART_LSR] & UART_LSR_THRE)
-                        break;
-                barrier();
-        }
-
-        UART_BASE[UART_TX] = c;
-}
-
-static inline void flush(void)
-{
-}
-
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
-
-
-#endif
diff --git a/include/asm-arm/arch-ixp23xx/vmalloc.h b/include/asm-arm/arch-ixp23xx/vmalloc.h
deleted file mode 100644
index 9f2566658541..000000000000
--- a/include/asm-arm/arch-ixp23xx/vmalloc.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * include/asm-arm/arch-ixp23xx/vmalloc.h
- *
- * Copyright (c) 2005 MontaVista Software, Inc.
- *
- * NPU mappings end at 0xf0000000 and we allocate 64MB for board
- * specific static I/O.
- */
-
-#define VMALLOC_END     (0xec000000)
diff --git a/include/asm-arm/arch-ixp4xx/avila.h b/include/asm-arm/arch-ixp4xx/avila.h
deleted file mode 100644
index 88f053d64430..000000000000
--- a/include/asm-arm/arch-ixp4xx/avila.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * include/asm-arm/arch-ixp4xx/avila.h
- *
- * Gateworks Avila platform specific definitions
- *
- * Author: Michael-Luke Jones <mlj28@cam.ac.uk>
- *
- * Based on ixdp425.h
- * Author: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright 2004 (c) MontaVista, Software, Inc.
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H__
-#error "Do not include this directly, instead #include <asm/arch/hardware.h>"
-#endif
-
-#define AVILA_SDA_PIN           7
-#define AVILA_SCL_PIN           6
-
-/*
- * AVILA PCI IRQs
- */
-#define AVILA_PCI_MAX_DEV       4
-#define LOFT_PCI_MAX_DEV    6
-#define AVILA_PCI_IRQ_LINES     4
-
-
-/* PCI controller GPIO to IRQ pin mappings */
-#define AVILA_PCI_INTA_PIN      11
-#define AVILA_PCI_INTB_PIN      10
-#define AVILA_PCI_INTC_PIN      9
-#define AVILA_PCI_INTD_PIN      8
-
-
diff --git a/include/asm-arm/arch-ixp4xx/coyote.h b/include/asm-arm/arch-ixp4xx/coyote.h
deleted file mode 100644
index 428b298afc1f..000000000000
--- a/include/asm-arm/arch-ixp4xx/coyote.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * include/asm-arm/arch-ixp4xx/coyote.h
- *
- * ADI Engineering platform specific definitions
- *
- * Author: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright 2004 (c) MontaVista, Software, Inc. 
- * 
- * This file is licensed under  the terms of the GNU General Public 
- * License version 2. This program is licensed "as is" without any 
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H__
-#error "Do not include this directly, instead #include <asm/arch/hardware.h>"
-#endif
-
-/* PCI controller GPIO to IRQ pin mappings */
-#define COYOTE_PCI_SLOT0_PIN    6
-#define COYOTE_PCI_SLOT1_PIN    11
-
-#define COYOTE_PCI_SLOT0_DEVID  14
-#define COYOTE_PCI_SLOT1_DEVID  15
-
-#define COYOTE_IDE_BASE_PHYS    IXP4XX_EXP_BUS_BASE(3)
-#define COYOTE_IDE_BASE_VIRT    0xFFFE1000
-#define COYOTE_IDE_REGION_SIZE  0x1000
-
-#define COYOTE_IDE_DATA_PORT    0xFFFE10E0
-#define COYOTE_IDE_CTRL_PORT    0xFFFE10FC
-#define COYOTE_IDE_ERROR_PORT   0xFFFE10E2
-
diff --git a/include/asm-arm/arch-ixp4xx/cpu.h b/include/asm-arm/arch-ixp4xx/cpu.h
deleted file mode 100644
index 2fa3d6b8dbb8..000000000000
--- a/include/asm-arm/arch-ixp4xx/cpu.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * include/asm-arm/arch-ixp4xx/cpu.h
- *
- * IXP4XX cpu type detection
- *
- * Copyright (C) 2007 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __ASM_ARCH_CPU_H__
-#define __ASM_ARCH_CPU_H__
-
-extern unsigned int processor_id;
-/* Processor id value in CP15 Register 0 */
-#define IXP425_PROCESSOR_ID_VALUE       0x690541c0
-#define IXP435_PROCESSOR_ID_VALUE       0x69054040
-#define IXP465_PROCESSOR_ID_VALUE       0x69054200
-#define IXP4XX_PROCESSOR_ID_MASK        0xfffffff0
-
-#define cpu_is_ixp42x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \
-                          IXP425_PROCESSOR_ID_VALUE)
-#define cpu_is_ixp43x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \
-                          IXP435_PROCESSOR_ID_VALUE)
-#define cpu_is_ixp46x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \
-                          IXP465_PROCESSOR_ID_VALUE)
-
-static inline u32 ixp4xx_read_feature_bits(void)
-{
-        unsigned int val = ~*IXP4XX_EXP_CFG2;
-        val &= ~IXP4XX_FEATURE_RESERVED;
-        if (!cpu_is_ixp46x())
-                val &= ~IXP4XX_FEATURE_IXP46X_ONLY;
-
-        return val;
-}
-
-static inline void ixp4xx_write_feature_bits(u32 value)
-{
-        *IXP4XX_EXP_CFG2 = ~value;
-}
-
-#endif  /* _ASM_ARCH_CPU_H */
diff --git a/include/asm-arm/arch-ixp4xx/debug-macro.S b/include/asm-arm/arch-ixp4xx/debug-macro.S
deleted file mode 100644
index 37bc8ef23e67..000000000000
--- a/include/asm-arm/arch-ixp4xx/debug-macro.S
+++ /dev/null
@@ -1,24 +0,0 @@
-/* linux/include/asm-arm/arch-ixp4xx/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-                .macro  addruart,rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx, #0xc8000000
-                movne   \rx, #0xff000000
-                orrne   \rx, \rx, #0x00b00000
-                add     \rx,\rx,#3              @ Uart regs are at off set of 3 if
-                                                @ byte writes used - Big Endian.
-                .endm
-
-#define UART_SHIFT      2
-#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-ixp4xx/dma.h b/include/asm-arm/arch-ixp4xx/dma.h
deleted file mode 100644
index 0b755d6e9198..000000000000
--- a/include/asm-arm/arch-ixp4xx/dma.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * include/asm-arm/arch-ixp4xx/dma.h
- *
- * Copyright (C) 2001-2004 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-
-#include <linux/device.h>
-#include <asm/page.h>
-#include <asm/sizes.h>
-#include <asm/arch/hardware.h>
-
-#define MAX_DMA_ADDRESS         (PAGE_OFFSET + SZ_64M)
-
-#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-ixp4xx/dsmg600.h b/include/asm-arm/arch-ixp4xx/dsmg600.h
deleted file mode 100644
index 5afae8c2e296..000000000000
--- a/include/asm-arm/arch-ixp4xx/dsmg600.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * DSM-G600 platform specific definitions
- *
- * Copyright (C) 2006 Tower Technologies
- * Author: Alessandro Zummo <a.zummo@towertech.it>
- *
- * based on ixdp425.h:
- *      Copyright 2004 (C) MontaVista, Software, Inc.
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H__
-#error "Do not include this directly, instead #include <asm/arch/hardware.h>"
-#endif
-
-#define DSMG600_SDA_PIN         5
-#define DSMG600_SCL_PIN         4
-
-/*
- * DSMG600 PCI IRQs
- */
-#define DSMG600_PCI_MAX_DEV     4
-#define DSMG600_PCI_IRQ_LINES   3
-
-
-/* PCI controller GPIO to IRQ pin mappings */
-#define DSMG600_PCI_INTA_PIN    11
-#define DSMG600_PCI_INTB_PIN    10
-#define DSMG600_PCI_INTC_PIN    9
-#define DSMG600_PCI_INTD_PIN    8
-#define DSMG600_PCI_INTE_PIN    7
-#define DSMG600_PCI_INTF_PIN    6
-
-/* DSM-G600 Timer Setting */
-#define DSMG600_FREQ 66000000
-
-/* Buttons */
-
-#define DSMG600_PB_GPIO         15      /* power button */
-#define DSMG600_RB_GPIO         3       /* reset button */
-
-/* Power control */
-
-#define DSMG600_PO_GPIO         2       /* power off */
-
-/* LEDs */
-
-#define DSMG600_LED_PWR_GPIO    0
-#define DSMG600_LED_WLAN_GPIO   14
diff --git a/include/asm-arm/arch-ixp4xx/entry-macro.S b/include/asm-arm/arch-ixp4xx/entry-macro.S
deleted file mode 100644
index ed313c52a8a4..000000000000
--- a/include/asm-arm/arch-ixp4xx/entry-macro.S
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * include/asm-arm/arch-ixp4xx/entry-macro.S
- *
- * Low-level IRQ helper macros for IXP4xx-based platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <asm/arch/hardware.h>
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP_OFFSET)
-                ldr     \irqstat, [\irqstat]            @ get interrupts
-                cmp     \irqstat, #0
-                beq     1001f                           @ upper IRQ?
-                clz     \irqnr, \irqstat
-                mov     \base, #31
-                sub     \irqnr, \base, \irqnr
-                b       1002f                           @ lower IRQ being
-                                                        @ handled
-
-1001:
-                /*
-                 * IXP465/IXP435 has an upper IRQ status register
-                 */
-#if defined(CONFIG_CPU_IXP46X) || defined(CONFIG_CPU_IXP43X)
-                ldr     \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP2_OFFSET)
-                ldr     \irqstat, [\irqstat]            @ get upper interrupts
-                mov     \irqnr, #63
-                clz     \irqstat, \irqstat
-                cmp     \irqstat, #32
-                subne   \irqnr, \irqnr, \irqstat
-#endif
-1002:
-                .endm
-
-
diff --git a/include/asm-arm/arch-ixp4xx/fsg.h b/include/asm-arm/arch-ixp4xx/fsg.h
deleted file mode 100644
index 168b9848eb4a..000000000000
--- a/include/asm-arm/arch-ixp4xx/fsg.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * include/asm-arm/arch-ixp4xx/fsg.h
- *
- * Freecom FSG-3 platform specific definitions
- *
- * Author: Rod Whitby <rod@whitby.id.au>
- * Author: Tomasz Chmielewski <mangoo@wpkg.org>
- * Maintainers: http://www.nslu2-linux.org
- *
- * Based on coyote.h by
- * Copyright 2004 (c) MontaVista, Software, Inc.
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H__
-#error "Do not include this directly, instead #include <asm/arch/hardware.h>"
-#endif
-
-#define FSG_SDA_PIN             12
-#define FSG_SCL_PIN             13
-
-/*
- * FSG PCI IRQs
- */
-#define FSG_PCI_MAX_DEV         3
-#define FSG_PCI_IRQ_LINES       3
-
-
-/* PCI controller GPIO to IRQ pin mappings */
-#define FSG_PCI_INTA_PIN        6
-#define FSG_PCI_INTB_PIN        7
-#define FSG_PCI_INTC_PIN        5
-
-/* Buttons */
-
-#define FSG_SB_GPIO             4       /* sync button */
-#define FSG_RB_GPIO             9       /* reset button */
-#define FSG_UB_GPIO             10      /* usb button */
-
-/* LEDs */
-
-#define FSG_LED_WLAN_BIT        0
-#define FSG_LED_WAN_BIT         1
-#define FSG_LED_SATA_BIT        2
-#define FSG_LED_USB_BIT         4
-#define FSG_LED_RING_BIT        5
-#define FSG_LED_SYNC_BIT        7
diff --git a/include/asm-arm/arch-ixp4xx/gpio.h b/include/asm-arm/arch-ixp4xx/gpio.h
deleted file mode 100644
index 28e7d27b1b8f..000000000000
--- a/include/asm-arm/arch-ixp4xx/gpio.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ixp4xx/gpio.h
- *
- * IXP4XX GPIO wrappers for arch-neutral GPIO calls
- *
- * Written by Milan Svoboda <msvoboda@ra.rockwell.com>
- * Based on PXA implementation by Philipp Zabel <philipp.zabel@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-#ifndef __ASM_ARCH_IXP4XX_GPIO_H
-#define __ASM_ARCH_IXP4XX_GPIO_H
-
-#include <asm/arch/hardware.h>
-
-static inline int gpio_request(unsigned gpio, const char *label)
-{
-        return 0;
-}
-
-static inline void gpio_free(unsigned gpio)
-{
-        return;
-}
-
-static inline int gpio_direction_input(unsigned gpio)
-{
-        gpio_line_config(gpio, IXP4XX_GPIO_IN);
-        return 0;
-}
-
-static inline int gpio_direction_output(unsigned gpio, int level)
-{
-        gpio_line_set(gpio, level);
-        gpio_line_config(gpio, IXP4XX_GPIO_OUT);
-        return 0;
-}
-
-static inline int gpio_get_value(unsigned gpio)
-{
-        int value;
-
-        gpio_line_get(gpio, &value);
-
-        return value;
-}
-
-static inline void gpio_set_value(unsigned gpio, int value)
-{
-        gpio_line_set(gpio, value);
-}
-
-#include <asm-generic/gpio.h>                   /* cansleep wrappers */
-
-extern int gpio_to_irq(int gpio);
-extern int irq_to_gpio(int gpio);
-
-#endif
-
diff --git a/include/asm-arm/arch-ixp4xx/gtwx5715.h b/include/asm-arm/arch-ixp4xx/gtwx5715.h
deleted file mode 100644
index 2192dedc2f59..000000000000
--- a/include/asm-arm/arch-ixp4xx/gtwx5715.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * include/asm-arm/arch-ixp4xx/gtwx5715.h
- *
- * Gemtek GTWX5715 Gateway (Linksys WRV54G)
- *
- * Copyright 2004 (c) George T. Joseph
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H__
-#error "Do not include this directly, instead #include <asm/arch/hardware.h>"
-#endif
-#include "irqs.h"
-
-#define GTWX5715_GPIO0  0
-#define GTWX5715_GPIO1  1
-#define GTWX5715_GPIO2  2
-#define GTWX5715_GPIO3  3
-#define GTWX5715_GPIO4  4
-#define GTWX5715_GPIO5  5
-#define GTWX5715_GPIO6  6
-#define GTWX5715_GPIO7  7
-#define GTWX5715_GPIO8  8
-#define GTWX5715_GPIO9  9
-#define GTWX5715_GPIO10 10
-#define GTWX5715_GPIO11 11
-#define GTWX5715_GPIO12 12
-#define GTWX5715_GPIO13 13
-#define GTWX5715_GPIO14 14
-
-#define GTWX5715_GPIO0_IRQ                      IRQ_IXP4XX_GPIO0
-#define GTWX5715_GPIO1_IRQ                      IRQ_IXP4XX_GPIO1
-#define GTWX5715_GPIO2_IRQ                      IRQ_IXP4XX_GPIO2
-#define GTWX5715_GPIO3_IRQ                      IRQ_IXP4XX_GPIO3
-#define GTWX5715_GPIO4_IRQ                      IRQ_IXP4XX_GPIO4
-#define GTWX5715_GPIO5_IRQ                      IRQ_IXP4XX_GPIO5
-#define GTWX5715_GPIO6_IRQ                      IRQ_IXP4XX_GPIO6
-#define GTWX5715_GPIO7_IRQ                      IRQ_IXP4XX_GPIO7
-#define GTWX5715_GPIO8_IRQ                      IRQ_IXP4XX_GPIO8
-#define GTWX5715_GPIO9_IRQ                      IRQ_IXP4XX_GPIO9
-#define GTWX5715_GPIO10_IRQ             IRQ_IXP4XX_GPIO10
-#define GTWX5715_GPIO11_IRQ             IRQ_IXP4XX_GPIO11
-#define GTWX5715_GPIO12_IRQ             IRQ_IXP4XX_GPIO12
-#define GTWX5715_GPIO13_IRQ             IRQ_IXP4XX_SW_INT1
-#define GTWX5715_GPIO14_IRQ             IRQ_IXP4XX_SW_INT2
-
-/* PCI controller GPIO to IRQ pin mappings
-
-                        INTA    INTB
-SLOT 0  10              11
-SLOT 1  11              10
-
-*/
-
-#define GTWX5715_PCI_SLOT0_DEVID        0
-#define GTWX5715_PCI_SLOT0_INTA_GPIO    GTWX5715_GPIO10
-#define GTWX5715_PCI_SLOT0_INTB_GPIO    GTWX5715_GPIO11
-#define GTWX5715_PCI_SLOT0_INTA_IRQ     GTWX5715_GPIO10_IRQ
-#define GTWX5715_PCI_SLOT0_INTB_IRQ     GTWX5715_GPIO11_IRQ
-
-#define GTWX5715_PCI_SLOT1_DEVID        1
-#define GTWX5715_PCI_SLOT1_INTA_GPIO    GTWX5715_GPIO11
-#define GTWX5715_PCI_SLOT1_INTB_GPIO    GTWX5715_GPIO10
-#define GTWX5715_PCI_SLOT1_INTA_IRQ     GTWX5715_GPIO11_IRQ
-#define GTWX5715_PCI_SLOT1_INTB_IRQ     GTWX5715_GPIO10_IRQ
-
-#define GTWX5715_PCI_SLOT_COUNT                 2
-#define GTWX5715_PCI_INT_PIN_COUNT              2
-
-/*
- * GPIO 5,6,7 and12 are hard wired to the Kendin KS8995M Switch
- * and operate as an SPI type interface.  The details of the interface
- * are available on Kendin/Micrel's web site.
- */
-
-#define GTWX5715_KSSPI_SELECT   GTWX5715_GPIO5
-#define GTWX5715_KSSPI_TXD              GTWX5715_GPIO6
-#define GTWX5715_KSSPI_CLOCK    GTWX5715_GPIO7
-#define GTWX5715_KSSPI_RXD              GTWX5715_GPIO12
-
-/*
- * The "reset" button is wired to GPIO 3.
- * The GPIO is brought "low" when the button is pushed.
- */
-
-#define GTWX5715_BUTTON_GPIO    GTWX5715_GPIO3
-#define GTWX5715_BUTTON_IRQ     GTWX5715_GPIO3_IRQ
-
-/*
- *  Board Label      Front Label
- *  LED1             Power
- *  LED2             Wireless-G
- *  LED3             not populated but could be
- *  LED4             Internet
- *  LED5 - LED8      Controlled by KS8995M Switch
- *  LED9             DMZ
- */
-
-#define GTWX5715_LED1_GPIO              GTWX5715_GPIO2
-#define GTWX5715_LED2_GPIO              GTWX5715_GPIO9
-#define GTWX5715_LED3_GPIO              GTWX5715_GPIO8
-#define GTWX5715_LED4_GPIO              GTWX5715_GPIO1
-#define GTWX5715_LED9_GPIO              GTWX5715_GPIO4
diff --git a/include/asm-arm/arch-ixp4xx/hardware.h b/include/asm-arm/arch-ixp4xx/hardware.h
deleted file mode 100644
index fa723a627854..000000000000
--- a/include/asm-arm/arch-ixp4xx/hardware.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * include/asm-arm/arch-ixp4xx/hardware.h 
- *
- * Copyright (C) 2002 Intel Corporation.
- * Copyright (C) 2003-2004 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-/*
- * Hardware definitions for IXP4xx based systems
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H__
-#define __ASM_ARCH_HARDWARE_H__
-
-#define PCIBIOS_MIN_IO          0x00001000
-#define PCIBIOS_MIN_MEM         (cpu_is_ixp43x() ? 0x40000000 : 0x48000000)
-
-/*
- * We override the standard dma-mask routines for bouncing.
- */
-#define HAVE_ARCH_PCI_SET_DMA_MASK
-
-#define pcibios_assign_all_busses()     1
-
-/* Register locations and bits */
-#include "ixp4xx-regs.h"
-
-#ifndef __ASSEMBLER__
-#include <asm/arch/cpu.h>
-#endif
-
-/* Platform helper functions and definitions */
-#include "platform.h"
-
-/* Platform specific details */
-#include "ixdp425.h"
-#include "avila.h"
-#include "coyote.h"
-#include "prpmc1100.h"
-#include "nslu2.h"
-#include "nas100d.h"
-#include "dsmg600.h"
-#include "fsg.h"
-
-#endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-ixp4xx/io.h b/include/asm-arm/arch-ixp4xx/io.h
deleted file mode 100644
index 8e7426081f0e..000000000000
--- a/include/asm-arm/arch-ixp4xx/io.h
+++ /dev/null
@@ -1,569 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ixp4xx/io.h
- *
- * Author: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright (C) 2002-2005  MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#include <linux/bitops.h>
-
-#include <asm/arch/hardware.h>
-
-#define IO_SPACE_LIMIT 0xffff0000
-
-extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
-extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
-
-
-/*
- * IXP4xx provides two methods of accessing PCI memory space:
- *
- * 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB).
- *    To access PCI via this space, we simply ioremap() the BAR
- *    into the kernel and we can use the standard read[bwl]/write[bwl]
- *    macros. This is the preffered method due to speed but it
- *    limits the system to just 64MB of PCI memory. This can be 
- *    problamatic if using video cards and other memory-heavy
- *    targets.
- *
- * 2) If > 64MB of memory space is required, the IXP4xx can be configured
- *    to use indirect registers to access PCI (as we do below for I/O
- *    transactions). This allows for up to 128MB (0x48000000 to 0x4fffffff)
- *    of memory on the bus. The disadvantage of this is that every 
- *    PCI access requires three local register accesses plus a spinlock,
- *    but in some cases the performance hit is acceptable. In addition,
- *    you cannot mmap() PCI devices in this case.
- *
- */
-#ifndef CONFIG_IXP4XX_INDIRECT_PCI
-
-#define __mem_pci(a)            (a)
-
-#else
-
-#include <linux/mm.h>
-
-/*
- * In the case of using indirect PCI, we simply return the actual PCI
- * address and our read/write implementation use that to drive the 
- * access registers. If something outside of PCI is ioremap'd, we
- * fallback to the default.
- */
-static inline void __iomem *
-__ixp4xx_ioremap(unsigned long addr, size_t size, unsigned int mtype)
-{
-        if((addr < PCIBIOS_MIN_MEM) || (addr > 0x4fffffff))
-                return __arm_ioremap(addr, size, mtype);
-
-        return (void __iomem *)addr;
-}
-
-static inline void
-__ixp4xx_iounmap(void __iomem *addr)
-{
-        if ((__force u32)addr >= VMALLOC_START)
-                __iounmap(addr);
-}
-
-#define __arch_ioremap(a, s, f)         __ixp4xx_ioremap(a, s, f)
-#define __arch_iounmap(a)               __ixp4xx_iounmap(a)
-
-#define writeb(v, p)                    __ixp4xx_writeb(v, p)
-#define writew(v, p)                    __ixp4xx_writew(v, p)
-#define writel(v, p)                    __ixp4xx_writel(v, p)
-
-#define writesb(p, v, l)                __ixp4xx_writesb(p, v, l)
-#define writesw(p, v, l)                __ixp4xx_writesw(p, v, l)
-#define writesl(p, v, l)                __ixp4xx_writesl(p, v, l)
-        
-#define readb(p)                        __ixp4xx_readb(p)
-#define readw(p)                        __ixp4xx_readw(p)
-#define readl(p)                        __ixp4xx_readl(p)
-        
-#define readsb(p, v, l)                 __ixp4xx_readsb(p, v, l)
-#define readsw(p, v, l)                 __ixp4xx_readsw(p, v, l)
-#define readsl(p, v, l)                 __ixp4xx_readsl(p, v, l)
-
-static inline void 
-__ixp4xx_writeb(u8 value, volatile void __iomem *p)
-{
-        u32 addr = (u32)p;
-        u32 n, byte_enables, data;
-
-        if (addr >= VMALLOC_START) {
-                __raw_writeb(value, addr);
-                return;
-        }
-
-        n = addr % 4;
-        byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
-        data = value << (8*n);
-        ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
-}
-
-static inline void
-__ixp4xx_writesb(volatile void __iomem *bus_addr, const u8 *vaddr, int count)
-{
-        while (count--)
-                writeb(*vaddr++, bus_addr);
-}
-
-static inline void 
-__ixp4xx_writew(u16 value, volatile void __iomem *p)
-{
-        u32 addr = (u32)p;
-        u32 n, byte_enables, data;
-
-        if (addr >= VMALLOC_START) {
-                __raw_writew(value, addr);
-                return;
-        }
-
-        n = addr % 4;
-        byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
-        data = value << (8*n);
-        ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
-}
-
-static inline void
-__ixp4xx_writesw(volatile void __iomem *bus_addr, const u16 *vaddr, int count)
-{
-        while (count--)
-                writew(*vaddr++, bus_addr);
-}
-
-static inline void 
-__ixp4xx_writel(u32 value, volatile void __iomem *p)
-{
-        u32 addr = (__force u32)p;
-        if (addr >= VMALLOC_START) {
-                __raw_writel(value, p);
-                return;
-        }
-
-        ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value);
-}
-
-static inline void
-__ixp4xx_writesl(volatile void __iomem *bus_addr, const u32 *vaddr, int count)
-{
-        while (count--)
-                writel(*vaddr++, bus_addr);
-}
-
-static inline unsigned char 
-__ixp4xx_readb(const volatile void __iomem *p)
-{
-        u32 addr = (u32)p;
-        u32 n, byte_enables, data;
-
-        if (addr >= VMALLOC_START)
-                return __raw_readb(addr);
-
-        n = addr % 4;
-        byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
-        if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data))
-                return 0xff;
-
-        return data >> (8*n);
-}
-
-static inline void
-__ixp4xx_readsb(const volatile void __iomem *bus_addr, u8 *vaddr, u32 count)
-{
-        while (count--)
-                *vaddr++ = readb(bus_addr);
-}
-
-static inline unsigned short 
-__ixp4xx_readw(const volatile void __iomem *p)
-{
-        u32 addr = (u32)p;
-        u32 n, byte_enables, data;
-
-        if (addr >= VMALLOC_START)
-                return __raw_readw(addr);
-
-        n = addr % 4;
-        byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
-        if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data))
-                return 0xffff;
-
-        return data>>(8*n);
-}
-
-static inline void 
-__ixp4xx_readsw(const volatile void __iomem *bus_addr, u16 *vaddr, u32 count)
-{
-        while (count--)
-                *vaddr++ = readw(bus_addr);
-}
-
-static inline unsigned long 
-__ixp4xx_readl(const volatile void __iomem *p)
-{
-        u32 addr = (__force u32)p;
-        u32 data;
-
-        if (addr >= VMALLOC_START)
-                return __raw_readl(p);
-
-        if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data))
-                return 0xffffffff;
-
-        return data;
-}
-
-static inline void 
-__ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count)
-{
-        while (count--)
-                *vaddr++ = readl(bus_addr);
-}
-
-
-/*
- * We can use the built-in functions b/c they end up calling writeb/readb
- */
-#define memset_io(c,v,l)                _memset_io((c),(v),(l))
-#define memcpy_fromio(a,c,l)            _memcpy_fromio((a),(c),(l))
-#define memcpy_toio(c,a,l)              _memcpy_toio((c),(a),(l))
-
-#endif
-
-#ifndef CONFIG_PCI
-
-#define __io(v)         v
-
-#else
-
-/*
- * IXP4xx does not have a transparent cpu -> PCI I/O translation
- * window.  Instead, it has a set of registers that must be tweaked
- * with the proper byte lanes, command types, and address for the
- * transaction.  This means that we need to override the default
- * I/O functions.
- */
-#define outb(p, v)                      __ixp4xx_outb(p, v)
-#define outw(p, v)                      __ixp4xx_outw(p, v)
-#define outl(p, v)                      __ixp4xx_outl(p, v)
-        
-#define outsb(p, v, l)                  __ixp4xx_outsb(p, v, l)
-#define outsw(p, v, l)                  __ixp4xx_outsw(p, v, l)
-#define outsl(p, v, l)                  __ixp4xx_outsl(p, v, l)
-
-#define inb(p)                          __ixp4xx_inb(p)
-#define inw(p)                          __ixp4xx_inw(p)
-#define inl(p)                          __ixp4xx_inl(p)
-
-#define insb(p, v, l)                   __ixp4xx_insb(p, v, l)
-#define insw(p, v, l)                   __ixp4xx_insw(p, v, l)
-#define insl(p, v, l)                   __ixp4xx_insl(p, v, l)
-
-
-static inline void 
-__ixp4xx_outb(u8 value, u32 addr)
-{
-        u32 n, byte_enables, data;
-        n = addr % 4;
-        byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
-        data = value << (8*n);
-        ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
-}
-
-static inline void 
-__ixp4xx_outsb(u32 io_addr, const u8 *vaddr, u32 count)
-{
-        while (count--)
-                outb(*vaddr++, io_addr);
-}
-
-static inline void 
-__ixp4xx_outw(u16 value, u32 addr)
-{
-        u32 n, byte_enables, data;
-        n = addr % 4;
-        byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
-        data = value << (8*n);
-        ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
-}
-
-static inline void 
-__ixp4xx_outsw(u32 io_addr, const u16 *vaddr, u32 count)
-{
-        while (count--)
-                outw(cpu_to_le16(*vaddr++), io_addr);
-}
-
-static inline void 
-__ixp4xx_outl(u32 value, u32 addr)
-{
-        ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value);
-}
-
-static inline void 
-__ixp4xx_outsl(u32 io_addr, const u32 *vaddr, u32 count)
-{
-        while (count--)
-                outl(*vaddr++, io_addr);
-}
-
-static inline u8 
-__ixp4xx_inb(u32 addr)
-{
-        u32 n, byte_enables, data;
-        n = addr % 4;
-        byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
-        if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data))
-                return 0xff;
-
-        return data >> (8*n);
-}
-
-static inline void 
-__ixp4xx_insb(u32 io_addr, u8 *vaddr, u32 count)
-{
-        while (count--)
-                *vaddr++ = inb(io_addr);
-}
-
-static inline u16 
-__ixp4xx_inw(u32 addr)
-{
-        u32 n, byte_enables, data;
-        n = addr % 4;
-        byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
-        if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data))
-                return 0xffff;
-
-        return data>>(8*n);
-}
-
-static inline void 
-__ixp4xx_insw(u32 io_addr, u16 *vaddr, u32 count)
-{
-        while (count--)
-                *vaddr++ = le16_to_cpu(inw(io_addr));
-}
-
-static inline u32 
-__ixp4xx_inl(u32 addr)
-{
-        u32 data;
-        if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data))
-                return 0xffffffff;
-
-        return data;
-}
-
-static inline void 
-__ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count)
-{
-        while (count--)
-                *vaddr++ = inl(io_addr);
-}
-
-#define PIO_OFFSET      0x10000UL
-#define PIO_MASK        0x0ffffUL
-
-#define __is_io_address(p)      (((unsigned long)p >= PIO_OFFSET) && \
-                                        ((unsigned long)p <= (PIO_MASK + PIO_OFFSET)))
-static inline unsigned int
-__ixp4xx_ioread8(const void __iomem *addr)
-{
-        unsigned long port = (unsigned long __force)addr;
-        if (__is_io_address(port))
-                return  (unsigned int)__ixp4xx_inb(port & PIO_MASK);
-        else
-#ifndef CONFIG_IXP4XX_INDIRECT_PCI
-                return (unsigned int)__raw_readb(port);
-#else
-                return (unsigned int)__ixp4xx_readb(addr);
-#endif
-}
-
-static inline void
-__ixp4xx_ioread8_rep(const void __iomem *addr, void *vaddr, u32 count)
-{
-        unsigned long port = (unsigned long __force)addr;
-        if (__is_io_address(port))
-                __ixp4xx_insb(port & PIO_MASK, vaddr, count);
-        else
-#ifndef CONFIG_IXP4XX_INDIRECT_PCI
-                __raw_readsb(addr, vaddr, count);
-#else
-                __ixp4xx_readsb(addr, vaddr, count);
-#endif
-}
-
-static inline unsigned int
-__ixp4xx_ioread16(const void __iomem *addr)
-{
-        unsigned long port = (unsigned long __force)addr;
-        if (__is_io_address(port))
-                return  (unsigned int)__ixp4xx_inw(port & PIO_MASK);
-        else
-#ifndef CONFIG_IXP4XX_INDIRECT_PCI
-                return le16_to_cpu(__raw_readw((u32)port));
-#else
-                return (unsigned int)__ixp4xx_readw(addr);
-#endif
-}
-
-static inline void
-__ixp4xx_ioread16_rep(const void __iomem *addr, void *vaddr, u32 count)
-{
-        unsigned long port = (unsigned long __force)addr;
-        if (__is_io_address(port))
-                __ixp4xx_insw(port & PIO_MASK, vaddr, count);
-        else
-#ifndef CONFIG_IXP4XX_INDIRECT_PCI
-                __raw_readsw(addr, vaddr, count);
-#else
-                __ixp4xx_readsw(addr, vaddr, count);
-#endif
-}
-
-static inline unsigned int
-__ixp4xx_ioread32(const void __iomem *addr)
-{
-        unsigned long port = (unsigned long __force)addr;
-        if (__is_io_address(port))
-                return  (unsigned int)__ixp4xx_inl(port & PIO_MASK);
-        else {
-#ifndef CONFIG_IXP4XX_INDIRECT_PCI
-                return le32_to_cpu((__force __le32)__raw_readl(addr));
-#else
-                return (unsigned int)__ixp4xx_readl(addr);
-#endif
-        }
-}
-
-static inline void
-__ixp4xx_ioread32_rep(const void __iomem *addr, void *vaddr, u32 count)
-{
-        unsigned long port = (unsigned long __force)addr;
-        if (__is_io_address(port))
-                __ixp4xx_insl(port & PIO_MASK, vaddr, count);
-        else
-#ifndef CONFIG_IXP4XX_INDIRECT_PCI
-                __raw_readsl(addr, vaddr, count);
-#else
-                __ixp4xx_readsl(addr, vaddr, count);
-#endif
-}
-
-static inline void
-__ixp4xx_iowrite8(u8 value, void __iomem *addr)
-{
-        unsigned long port = (unsigned long __force)addr;
-        if (__is_io_address(port))
-                __ixp4xx_outb(value, port & PIO_MASK);
-        else
-#ifndef CONFIG_IXP4XX_INDIRECT_PCI
-                __raw_writeb(value, port);
-#else
-                __ixp4xx_writeb(value, addr);
-#endif
-}
-
-static inline void
-__ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count)
-{
-        unsigned long port = (unsigned long __force)addr;
-        if (__is_io_address(port))
-                __ixp4xx_outsb(port & PIO_MASK, vaddr, count);
-        else
-#ifndef CONFIG_IXP4XX_INDIRECT_PCI
-                __raw_writesb(addr, vaddr, count);
-#else
-                __ixp4xx_writesb(addr, vaddr, count);
-#endif
-}
-
-static inline void
-__ixp4xx_iowrite16(u16 value, void __iomem *addr)
-{
-        unsigned long port = (unsigned long __force)addr;
-        if (__is_io_address(port))
-                __ixp4xx_outw(value, port & PIO_MASK);
-        else
-#ifndef CONFIG_IXP4XX_INDIRECT_PCI
-                __raw_writew(cpu_to_le16(value), addr);
-#else
-                __ixp4xx_writew(value, addr);
-#endif
-}
-
-static inline void
-__ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count)
-{
-        unsigned long port = (unsigned long __force)addr;
-        if (__is_io_address(port))
-                __ixp4xx_outsw(port & PIO_MASK, vaddr, count);
-        else
-#ifndef CONFIG_IXP4XX_INDIRECT_PCI
-                __raw_writesw(addr, vaddr, count);
-#else
-                __ixp4xx_writesw(addr, vaddr, count);
-#endif
-}
-
-static inline void
-__ixp4xx_iowrite32(u32 value, void __iomem *addr)
-{
-        unsigned long port = (unsigned long __force)addr;
-        if (__is_io_address(port))
-                __ixp4xx_outl(value, port & PIO_MASK);
-        else
-#ifndef CONFIG_IXP4XX_INDIRECT_PCI
-                __raw_writel((u32 __force)cpu_to_le32(value), addr);
-#else
-                __ixp4xx_writel(value, addr);
-#endif
-}
-
-static inline void
-__ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count)
-{
-        unsigned long port = (unsigned long __force)addr;
-        if (__is_io_address(port))
-                __ixp4xx_outsl(port & PIO_MASK, vaddr, count);
-        else
-#ifndef CONFIG_IXP4XX_INDIRECT_PCI
-                __raw_writesl(addr, vaddr, count);
-#else
-                __ixp4xx_writesl(addr, vaddr, count);
-#endif
-}
-
-#define ioread8(p)                      __ixp4xx_ioread8(p)
-#define ioread16(p)                     __ixp4xx_ioread16(p)
-#define ioread32(p)                     __ixp4xx_ioread32(p)
-
-#define ioread8_rep(p, v, c)            __ixp4xx_ioread8_rep(p, v, c)
-#define ioread16_rep(p, v, c)           __ixp4xx_ioread16_rep(p, v, c)
-#define ioread32_rep(p, v, c)           __ixp4xx_ioread32_rep(p, v, c)
-
-#define iowrite8(v,p)                   __ixp4xx_iowrite8(v,p)
-#define iowrite16(v,p)                  __ixp4xx_iowrite16(v,p)
-#define iowrite32(v,p)                  __ixp4xx_iowrite32(v,p)
-
-#define iowrite8_rep(p, v, c)           __ixp4xx_iowrite8_rep(p, v, c)
-#define iowrite16_rep(p, v, c)          __ixp4xx_iowrite16_rep(p, v, c)
-#define iowrite32_rep(p, v, c)          __ixp4xx_iowrite32_rep(p, v, c)
-
-#define ioport_map(port, nr)            ((void __iomem*)(port + PIO_OFFSET))
-#define ioport_unmap(addr)
-#endif  // !CONFIG_PCI
-
-#endif  //  __ASM_ARM_ARCH_IO_H
-
diff --git a/include/asm-arm/arch-ixp4xx/irqs.h b/include/asm-arm/arch-ixp4xx/irqs.h
deleted file mode 100644
index 674af4a84147..000000000000
--- a/include/asm-arm/arch-ixp4xx/irqs.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * include/asm-arm/arch-ixp4xx/irqs.h 
- *
- * IRQ definitions for IXP4XX based systems
- *
- * Copyright (C) 2002 Intel Corporation.
- * Copyright (C) 2003 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef _ARCH_IXP4XX_IRQS_H_
-#define _ARCH_IXP4XX_IRQS_H_
-
-
-#define IRQ_IXP4XX_NPEA         0
-#define IRQ_IXP4XX_NPEB         1
-#define IRQ_IXP4XX_NPEC         2
-#define IRQ_IXP4XX_QM1          3
-#define IRQ_IXP4XX_QM2          4
-#define IRQ_IXP4XX_TIMER1       5
-#define IRQ_IXP4XX_GPIO0        6
-#define IRQ_IXP4XX_GPIO1        7
-#define IRQ_IXP4XX_PCI_INT      8
-#define IRQ_IXP4XX_PCI_DMA1     9
-#define IRQ_IXP4XX_PCI_DMA2     10
-#define IRQ_IXP4XX_TIMER2       11
-#define IRQ_IXP4XX_USB          12
-#define IRQ_IXP4XX_UART2        13
-#define IRQ_IXP4XX_TIMESTAMP    14
-#define IRQ_IXP4XX_UART1        15
-#define IRQ_IXP4XX_WDOG         16
-#define IRQ_IXP4XX_AHB_PMU      17
-#define IRQ_IXP4XX_XSCALE_PMU   18
-#define IRQ_IXP4XX_GPIO2        19
-#define IRQ_IXP4XX_GPIO3        20
-#define IRQ_IXP4XX_GPIO4        21
-#define IRQ_IXP4XX_GPIO5        22
-#define IRQ_IXP4XX_GPIO6        23
-#define IRQ_IXP4XX_GPIO7        24
-#define IRQ_IXP4XX_GPIO8        25
-#define IRQ_IXP4XX_GPIO9        26
-#define IRQ_IXP4XX_GPIO10       27
-#define IRQ_IXP4XX_GPIO11       28
-#define IRQ_IXP4XX_GPIO12       29
-#define IRQ_IXP4XX_SW_INT1      30
-#define IRQ_IXP4XX_SW_INT2      31
-#define IRQ_IXP4XX_USB_HOST     32
-#define IRQ_IXP4XX_I2C          33
-#define IRQ_IXP4XX_SSP          34
-#define IRQ_IXP4XX_TSYNC        35
-#define IRQ_IXP4XX_EAU_DONE     36
-#define IRQ_IXP4XX_SHA_DONE     37
-#define IRQ_IXP4XX_SWCP_PE      58
-#define IRQ_IXP4XX_QM_PE        60
-#define IRQ_IXP4XX_MCU_ECC      61
-#define IRQ_IXP4XX_EXP_PE       62
-
-/*
- * Only first 32 sources are valid if running on IXP42x systems
- */
-#if defined(CONFIG_CPU_IXP46X) || defined(CONFIG_CPU_IXP43X)
-#define NR_IRQS                 64
-#else
-#define NR_IRQS                 32
-#endif
-
-#define XSCALE_PMU_IRQ          (IRQ_IXP4XX_XSCALE_PMU)
-
-/*
- * IXDP425 board IRQs
- */
-#define IRQ_IXDP425_PCI_INTA    IRQ_IXP4XX_GPIO11
-#define IRQ_IXDP425_PCI_INTB    IRQ_IXP4XX_GPIO10
-#define IRQ_IXDP425_PCI_INTC    IRQ_IXP4XX_GPIO9
-#define IRQ_IXDP425_PCI_INTD    IRQ_IXP4XX_GPIO8
-
-/*
- * Gateworks Avila board IRQs
- */
-#define IRQ_AVILA_PCI_INTA      IRQ_IXP4XX_GPIO11
-#define IRQ_AVILA_PCI_INTB      IRQ_IXP4XX_GPIO10
-#define IRQ_AVILA_PCI_INTC      IRQ_IXP4XX_GPIO9
-#define IRQ_AVILA_PCI_INTD      IRQ_IXP4XX_GPIO8
-
-
-/*
- * PrPMC1100 Board IRQs
- */
-#define IRQ_PRPMC1100_PCI_INTA  IRQ_IXP4XX_GPIO11
-#define IRQ_PRPMC1100_PCI_INTB  IRQ_IXP4XX_GPIO10
-#define IRQ_PRPMC1100_PCI_INTC  IRQ_IXP4XX_GPIO9
-#define IRQ_PRPMC1100_PCI_INTD  IRQ_IXP4XX_GPIO8
-
-/*
- * ADI Coyote Board IRQs
- */
-#define IRQ_COYOTE_PCI_SLOT0    IRQ_IXP4XX_GPIO6
-#define IRQ_COYOTE_PCI_SLOT1    IRQ_IXP4XX_GPIO11
-#define IRQ_COYOTE_IDE          IRQ_IXP4XX_GPIO5
-
-/*
- * NSLU2 board IRQs
- */
-#define        IRQ_NSLU2_PCI_INTA      IRQ_IXP4XX_GPIO11
-#define        IRQ_NSLU2_PCI_INTB      IRQ_IXP4XX_GPIO10
-#define        IRQ_NSLU2_PCI_INTC      IRQ_IXP4XX_GPIO9
-
-/*
- * NAS100D board IRQs
- */
-#define        IRQ_NAS100D_PCI_INTA    IRQ_IXP4XX_GPIO11
-#define        IRQ_NAS100D_PCI_INTB    IRQ_IXP4XX_GPIO10
-#define        IRQ_NAS100D_PCI_INTC    IRQ_IXP4XX_GPIO9
-#define        IRQ_NAS100D_PCI_INTD    IRQ_IXP4XX_GPIO8
-#define        IRQ_NAS100D_PCI_INTE    IRQ_IXP4XX_GPIO7
-
-/*
- * D-Link DSM-G600 RevA board IRQs
- */
-#define        IRQ_DSMG600_PCI_INTA    IRQ_IXP4XX_GPIO11
-#define        IRQ_DSMG600_PCI_INTB    IRQ_IXP4XX_GPIO10
-#define        IRQ_DSMG600_PCI_INTC    IRQ_IXP4XX_GPIO9
-#define        IRQ_DSMG600_PCI_INTD    IRQ_IXP4XX_GPIO8
-#define        IRQ_DSMG600_PCI_INTE    IRQ_IXP4XX_GPIO7
-#define        IRQ_DSMG600_PCI_INTF    IRQ_IXP4XX_GPIO6
-
-/*
- * Freecom FSG-3 Board IRQs
- */
-#define        IRQ_FSG_PCI_INTA        IRQ_IXP4XX_GPIO6
-#define        IRQ_FSG_PCI_INTB        IRQ_IXP4XX_GPIO7
-#define        IRQ_FSG_PCI_INTC        IRQ_IXP4XX_GPIO5
-
-#endif
diff --git a/include/asm-arm/arch-ixp4xx/ixdp425.h b/include/asm-arm/arch-ixp4xx/ixdp425.h
deleted file mode 100644
index d0a1dcb48d53..000000000000
--- a/include/asm-arm/arch-ixp4xx/ixdp425.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * include/asm-arm/arch-ixp4xx/ixdp425.h
- *
- * IXDP425 platform specific definitions
- *
- * Author: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright 2004 (c) MontaVista, Software, Inc. 
- * 
- * This file is licensed under  the terms of the GNU General Public 
- * License version 2. This program is licensed "as is" without any 
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H__
-#error "Do not include this directly, instead #include <asm/arch/hardware.h>"
-#endif
-
-#define IXDP425_SDA_PIN         7
-#define IXDP425_SCL_PIN         6
-
-/*
- * IXDP425 PCI IRQs
- */
-#define IXDP425_PCI_MAX_DEV     4
-#define IXDP425_PCI_IRQ_LINES   4
-
-
-/* PCI controller GPIO to IRQ pin mappings */
-#define IXDP425_PCI_INTA_PIN    11
-#define IXDP425_PCI_INTB_PIN    10
-#define IXDP425_PCI_INTC_PIN    9
-#define IXDP425_PCI_INTD_PIN    8
-
-/* NAND Flash pins */
-#define IXDP425_NAND_NCE_PIN    12
-
-#define IXDP425_NAND_CMD_BYTE   0x01
-#define IXDP425_NAND_ADDR_BYTE  0x02
diff --git a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
deleted file mode 100644
index 68aca8554f5a..000000000000
--- a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
+++ /dev/null
@@ -1,638 +0,0 @@
-/*
- * include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
- *
- * Register definitions for IXP4xx chipset. This file contains 
- * register location and bit definitions only. Platform specific 
- * definitions and helper function declarations are in platform.h 
- * and machine-name.h.
- *
- * Copyright (C) 2002 Intel Corporation.
- * Copyright (C) 2003-2004 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef _ASM_ARM_IXP4XX_H_
-#define _ASM_ARM_IXP4XX_H_
-
-/*
- * IXP4xx Linux Memory Map:
- *
- * Phy          Size            Virt            Description
- * =========================================================================
- *
- * 0x00000000   0x10000000(max) PAGE_OFFSET     System RAM
- *
- * 0x48000000   0x04000000      ioremap'd       PCI Memory Space
- *
- * 0x50000000   0x10000000      ioremap'd       EXP BUS
- *
- * 0x6000000    0x00004000      ioremap'd       QMgr
- *
- * 0xC0000000   0x00001000      0xffbff000      PCI CFG
- *
- * 0xC4000000   0x00001000      0xffbfe000      EXP CFG
- *
- * 0xC8000000   0x00013000      0xffbeb000      On-Chip Peripherals
- */
-
-/*
- * Queue Manager
- */
-#define IXP4XX_QMGR_BASE_PHYS           (0x60000000)
-#define IXP4XX_QMGR_REGION_SIZE         (0x00004000)
-
-/*
- * Expansion BUS Configuration registers
- */
-#define IXP4XX_EXP_CFG_BASE_PHYS        (0xC4000000)
-#define IXP4XX_EXP_CFG_BASE_VIRT        (0xFFBFE000)
-#define IXP4XX_EXP_CFG_REGION_SIZE      (0x00001000)
-
-/*
- * PCI Config registers
- */
-#define IXP4XX_PCI_CFG_BASE_PHYS        (0xC0000000)
-#define IXP4XX_PCI_CFG_BASE_VIRT        (0xFFBFF000)
-#define IXP4XX_PCI_CFG_REGION_SIZE      (0x00001000)
-
-/*
- * Peripheral space
- */
-#define IXP4XX_PERIPHERAL_BASE_PHYS     (0xC8000000)
-#define IXP4XX_PERIPHERAL_BASE_VIRT     (0xFFBEB000)
-#define IXP4XX_PERIPHERAL_REGION_SIZE   (0x00013000)
-
-/*
- * Debug UART
- *
- * This is basically a remap of UART1 into a region that is section
- * aligned so that it * can be used with the low-level debug code.
- */
-#define IXP4XX_DEBUG_UART_BASE_PHYS     (0xC8000000)
-#define IXP4XX_DEBUG_UART_BASE_VIRT     (0xffb00000)
-#define IXP4XX_DEBUG_UART_REGION_SIZE   (0x00001000)
-
-#define IXP4XX_EXP_CS0_OFFSET   0x00
-#define IXP4XX_EXP_CS1_OFFSET   0x04
-#define IXP4XX_EXP_CS2_OFFSET   0x08
-#define IXP4XX_EXP_CS3_OFFSET   0x0C
-#define IXP4XX_EXP_CS4_OFFSET   0x10
-#define IXP4XX_EXP_CS5_OFFSET   0x14
-#define IXP4XX_EXP_CS6_OFFSET   0x18
-#define IXP4XX_EXP_CS7_OFFSET   0x1C
-#define IXP4XX_EXP_CFG0_OFFSET  0x20
-#define IXP4XX_EXP_CFG1_OFFSET  0x24
-#define IXP4XX_EXP_CFG2_OFFSET  0x28
-#define IXP4XX_EXP_CFG3_OFFSET  0x2C
-
-/*
- * Expansion Bus Controller registers.
- */
-#define IXP4XX_EXP_REG(x) ((volatile u32 *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))
-
-#define IXP4XX_EXP_CS0      IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET)
-#define IXP4XX_EXP_CS1      IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET)
-#define IXP4XX_EXP_CS2      IXP4XX_EXP_REG(IXP4XX_EXP_CS2_OFFSET) 
-#define IXP4XX_EXP_CS3      IXP4XX_EXP_REG(IXP4XX_EXP_CS3_OFFSET)
-#define IXP4XX_EXP_CS4      IXP4XX_EXP_REG(IXP4XX_EXP_CS4_OFFSET)
-#define IXP4XX_EXP_CS5      IXP4XX_EXP_REG(IXP4XX_EXP_CS5_OFFSET)
-#define IXP4XX_EXP_CS6      IXP4XX_EXP_REG(IXP4XX_EXP_CS6_OFFSET)     
-#define IXP4XX_EXP_CS7      IXP4XX_EXP_REG(IXP4XX_EXP_CS7_OFFSET)
-
-#define IXP4XX_EXP_CFG0     IXP4XX_EXP_REG(IXP4XX_EXP_CFG0_OFFSET) 
-#define IXP4XX_EXP_CFG1     IXP4XX_EXP_REG(IXP4XX_EXP_CFG1_OFFSET) 
-#define IXP4XX_EXP_CFG2     IXP4XX_EXP_REG(IXP4XX_EXP_CFG2_OFFSET) 
-#define IXP4XX_EXP_CFG3     IXP4XX_EXP_REG(IXP4XX_EXP_CFG3_OFFSET)
-
-
-/*
- * Peripheral Space Register Region Base Addresses
- */
-#define IXP4XX_UART1_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000)
-#define IXP4XX_UART2_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000)
-#define IXP4XX_PMU_BASE_PHYS            (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000)
-#define IXP4XX_INTC_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000)
-#define IXP4XX_GPIO_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000)
-#define IXP4XX_TIMER_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)
-#define IXP4XX_NPEA_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000)
-#define IXP4XX_NPEB_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000)
-#define IXP4XX_NPEC_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000)
-#define IXP4XX_EthB_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)
-#define IXP4XX_EthC_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)
-#define IXP4XX_USB_BASE_PHYS            (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000)
-/* ixp46X only */
-#define IXP4XX_EthA_BASE_PHYS           (IXP4XX_PERIPHERAL_BASE_PHYS + 0xC000)
-#define IXP4XX_EthB1_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0xD000)
-#define IXP4XX_EthB2_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0xE000)
-#define IXP4XX_EthB3_BASE_PHYS          (IXP4XX_PERIPHERAL_BASE_PHYS + 0xF000)
-#define IXP4XX_TIMESYNC_BASE_PHYS       (IXP4XX_PERIPHERAL_BASE_PHYS + 0x10000)
-#define IXP4XX_I2C_BASE_PHYS            (IXP4XX_PERIPHERAL_BASE_PHYS + 0x11000)
-#define IXP4XX_SSP_BASE_PHYS            (IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000)
-
-
-#define IXP4XX_UART1_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)
-#define IXP4XX_UART2_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)
-#define IXP4XX_PMU_BASE_VIRT            (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)
-#define IXP4XX_INTC_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)
-#define IXP4XX_GPIO_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)
-#define IXP4XX_TIMER_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
-#define IXP4XX_NPEA_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0x6000)
-#define IXP4XX_NPEB_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0x7000)
-#define IXP4XX_NPEC_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0x8000)
-#define IXP4XX_EthB_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000)
-#define IXP4XX_EthC_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000)
-#define IXP4XX_USB_BASE_VIRT            (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000)
-/* ixp46X only */
-#define IXP4XX_EthA_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0xC000)
-#define IXP4XX_EthB1_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0xD000)
-#define IXP4XX_EthB2_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0xE000)
-#define IXP4XX_EthB3_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0xF000)
-#define IXP4XX_TIMESYNC_BASE_VIRT       (IXP4XX_PERIPHERAL_BASE_VIRT + 0x10000)
-#define IXP4XX_I2C_BASE_VIRT            (IXP4XX_PERIPHERAL_BASE_VIRT + 0x11000)
-#define IXP4XX_SSP_BASE_VIRT            (IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000)
-
-/*
- * Constants to make it easy to access  Interrupt Controller registers
- */
-#define IXP4XX_ICPR_OFFSET      0x00 /* Interrupt Status */
-#define IXP4XX_ICMR_OFFSET      0x04 /* Interrupt Enable */
-#define IXP4XX_ICLR_OFFSET      0x08 /* Interrupt IRQ/FIQ Select */
-#define IXP4XX_ICIP_OFFSET      0x0C /* IRQ Status */
-#define IXP4XX_ICFP_OFFSET      0x10 /* FIQ Status */
-#define IXP4XX_ICHR_OFFSET      0x14 /* Interrupt Priority */
-#define IXP4XX_ICIH_OFFSET      0x18 /* IRQ Highest Pri Int */
-#define IXP4XX_ICFH_OFFSET      0x1C /* FIQ Highest Pri Int */
-
-/*
- * IXP465-only
- */
-#define IXP4XX_ICPR2_OFFSET     0x20 /* Interrupt Status 2 */
-#define IXP4XX_ICMR2_OFFSET     0x24 /* Interrupt Enable 2 */
-#define IXP4XX_ICLR2_OFFSET     0x28 /* Interrupt IRQ/FIQ Select 2 */
-#define IXP4XX_ICIP2_OFFSET     0x2C /* IRQ Status */
-#define IXP4XX_ICFP2_OFFSET     0x30 /* FIQ Status */
-#define IXP4XX_ICEEN_OFFSET     0x34 /* Error High Pri Enable */
-
-
-/*
- * Interrupt Controller Register Definitions.
- */
-
-#define IXP4XX_INTC_REG(x) ((volatile u32 *)(IXP4XX_INTC_BASE_VIRT+(x)))
-
-#define IXP4XX_ICPR     IXP4XX_INTC_REG(IXP4XX_ICPR_OFFSET)
-#define IXP4XX_ICMR     IXP4XX_INTC_REG(IXP4XX_ICMR_OFFSET)
-#define IXP4XX_ICLR     IXP4XX_INTC_REG(IXP4XX_ICLR_OFFSET)
-#define IXP4XX_ICIP     IXP4XX_INTC_REG(IXP4XX_ICIP_OFFSET)
-#define IXP4XX_ICFP     IXP4XX_INTC_REG(IXP4XX_ICFP_OFFSET)
-#define IXP4XX_ICHR     IXP4XX_INTC_REG(IXP4XX_ICHR_OFFSET)
-#define IXP4XX_ICIH     IXP4XX_INTC_REG(IXP4XX_ICIH_OFFSET) 
-#define IXP4XX_ICFH     IXP4XX_INTC_REG(IXP4XX_ICFH_OFFSET)
-#define IXP4XX_ICPR2    IXP4XX_INTC_REG(IXP4XX_ICPR2_OFFSET)
-#define IXP4XX_ICMR2    IXP4XX_INTC_REG(IXP4XX_ICMR2_OFFSET)
-#define IXP4XX_ICLR2    IXP4XX_INTC_REG(IXP4XX_ICLR2_OFFSET)
-#define IXP4XX_ICIP2    IXP4XX_INTC_REG(IXP4XX_ICIP2_OFFSET)
-#define IXP4XX_ICFP2    IXP4XX_INTC_REG(IXP4XX_ICFP2_OFFSET)
-#define IXP4XX_ICEEN    IXP4XX_INTC_REG(IXP4XX_ICEEN_OFFSET)
-                                                                                
-/*
- * Constants to make it easy to access GPIO registers
- */
-#define IXP4XX_GPIO_GPOUTR_OFFSET       0x00
-#define IXP4XX_GPIO_GPOER_OFFSET        0x04
-#define IXP4XX_GPIO_GPINR_OFFSET        0x08
-#define IXP4XX_GPIO_GPISR_OFFSET        0x0C
-#define IXP4XX_GPIO_GPIT1R_OFFSET       0x10
-#define IXP4XX_GPIO_GPIT2R_OFFSET       0x14
-#define IXP4XX_GPIO_GPCLKR_OFFSET       0x18
-#define IXP4XX_GPIO_GPDBSELR_OFFSET     0x1C
-
-/* 
- * GPIO Register Definitions.
- * [Only perform 32bit reads/writes]
- */
-#define IXP4XX_GPIO_REG(x) ((volatile u32 *)(IXP4XX_GPIO_BASE_VIRT+(x)))
-
-#define IXP4XX_GPIO_GPOUTR      IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOUTR_OFFSET)
-#define IXP4XX_GPIO_GPOER       IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOER_OFFSET)
-#define IXP4XX_GPIO_GPINR       IXP4XX_GPIO_REG(IXP4XX_GPIO_GPINR_OFFSET)
-#define IXP4XX_GPIO_GPISR       IXP4XX_GPIO_REG(IXP4XX_GPIO_GPISR_OFFSET)
-#define IXP4XX_GPIO_GPIT1R      IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT1R_OFFSET)
-#define IXP4XX_GPIO_GPIT2R      IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT2R_OFFSET)
-#define IXP4XX_GPIO_GPCLKR      IXP4XX_GPIO_REG(IXP4XX_GPIO_GPCLKR_OFFSET)
-#define IXP4XX_GPIO_GPDBSELR    IXP4XX_GPIO_REG(IXP4XX_GPIO_GPDBSELR_OFFSET)
-
-/*
- * GPIO register bit definitions
- */
-
-/* Interrupt styles
- */
-#define IXP4XX_GPIO_STYLE_ACTIVE_HIGH   0x0
-#define IXP4XX_GPIO_STYLE_ACTIVE_LOW    0x1
-#define IXP4XX_GPIO_STYLE_RISING_EDGE   0x2
-#define IXP4XX_GPIO_STYLE_FALLING_EDGE  0x3
-#define IXP4XX_GPIO_STYLE_TRANSITIONAL  0x4
-
-/* 
- * Mask used to clear interrupt styles 
- */
-#define IXP4XX_GPIO_STYLE_CLEAR         0x7
-#define IXP4XX_GPIO_STYLE_SIZE          3
-
-/*
- * Constants to make it easy to access Timer Control/Status registers
- */
-#define IXP4XX_OSTS_OFFSET      0x00  /* Continious TimeStamp */
-#define IXP4XX_OST1_OFFSET      0x04  /* Timer 1 Timestamp */
-#define IXP4XX_OSRT1_OFFSET     0x08  /* Timer 1 Reload */
-#define IXP4XX_OST2_OFFSET      0x0C  /* Timer 2 Timestamp */
-#define IXP4XX_OSRT2_OFFSET     0x10  /* Timer 2 Reload */
-#define IXP4XX_OSWT_OFFSET      0x14  /* Watchdog Timer */
-#define IXP4XX_OSWE_OFFSET      0x18  /* Watchdog Enable */
-#define IXP4XX_OSWK_OFFSET      0x1C  /* Watchdog Key */
-#define IXP4XX_OSST_OFFSET      0x20  /* Timer Status */
-
-/*
- * Operating System Timer Register Definitions.
- */
-
-#define IXP4XX_TIMER_REG(x) ((volatile u32 *)(IXP4XX_TIMER_BASE_VIRT+(x)))
-
-#define IXP4XX_OSTS     IXP4XX_TIMER_REG(IXP4XX_OSTS_OFFSET)
-#define IXP4XX_OST1     IXP4XX_TIMER_REG(IXP4XX_OST1_OFFSET)
-#define IXP4XX_OSRT1    IXP4XX_TIMER_REG(IXP4XX_OSRT1_OFFSET)
-#define IXP4XX_OST2     IXP4XX_TIMER_REG(IXP4XX_OST2_OFFSET)
-#define IXP4XX_OSRT2    IXP4XX_TIMER_REG(IXP4XX_OSRT2_OFFSET)
-#define IXP4XX_OSWT     IXP4XX_TIMER_REG(IXP4XX_OSWT_OFFSET)
-#define IXP4XX_OSWE     IXP4XX_TIMER_REG(IXP4XX_OSWE_OFFSET)
-#define IXP4XX_OSWK     IXP4XX_TIMER_REG(IXP4XX_OSWK_OFFSET)
-#define IXP4XX_OSST     IXP4XX_TIMER_REG(IXP4XX_OSST_OFFSET)
-
-/*
- * Timer register values and bit definitions 
- */
-#define IXP4XX_OST_ENABLE               0x00000001
-#define IXP4XX_OST_ONE_SHOT             0x00000002
-/* Low order bits of reload value ignored */
-#define IXP4XX_OST_RELOAD_MASK          0x00000003
-#define IXP4XX_OST_DISABLED             0x00000000
-#define IXP4XX_OSST_TIMER_1_PEND        0x00000001
-#define IXP4XX_OSST_TIMER_2_PEND        0x00000002
-#define IXP4XX_OSST_TIMER_TS_PEND       0x00000004
-#define IXP4XX_OSST_TIMER_WDOG_PEND     0x00000008
-#define IXP4XX_OSST_TIMER_WARM_RESET    0x00000010
-
-#define IXP4XX_WDT_KEY                  0x0000482E
-
-#define IXP4XX_WDT_RESET_ENABLE         0x00000001
-#define IXP4XX_WDT_IRQ_ENABLE           0x00000002
-#define IXP4XX_WDT_COUNT_ENABLE         0x00000004
-
-
-/*
- * Constants to make it easy to access PCI Control/Status registers
- */
-#define PCI_NP_AD_OFFSET            0x00
-#define PCI_NP_CBE_OFFSET           0x04
-#define PCI_NP_WDATA_OFFSET         0x08
-#define PCI_NP_RDATA_OFFSET         0x0c
-#define PCI_CRP_AD_CBE_OFFSET       0x10
-#define PCI_CRP_WDATA_OFFSET        0x14
-#define PCI_CRP_RDATA_OFFSET        0x18
-#define PCI_CSR_OFFSET              0x1c
-#define PCI_ISR_OFFSET              0x20
-#define PCI_INTEN_OFFSET            0x24
-#define PCI_DMACTRL_OFFSET          0x28
-#define PCI_AHBMEMBASE_OFFSET       0x2c
-#define PCI_AHBIOBASE_OFFSET        0x30
-#define PCI_PCIMEMBASE_OFFSET       0x34
-#define PCI_AHBDOORBELL_OFFSET      0x38
-#define PCI_PCIDOORBELL_OFFSET      0x3C
-#define PCI_ATPDMA0_AHBADDR_OFFSET  0x40
-#define PCI_ATPDMA0_PCIADDR_OFFSET  0x44
-#define PCI_ATPDMA0_LENADDR_OFFSET  0x48
-#define PCI_ATPDMA1_AHBADDR_OFFSET  0x4C
-#define PCI_ATPDMA1_PCIADDR_OFFSET  0x50
-#define PCI_ATPDMA1_LENADDR_OFFSET      0x54
-
-/*
- * PCI Control/Status Registers
- */
-#define IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x)))
-
-#define PCI_NP_AD               IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET)
-#define PCI_NP_CBE              IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET)
-#define PCI_NP_WDATA            IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET)
-#define PCI_NP_RDATA            IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET)
-#define PCI_CRP_AD_CBE          IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)
-#define PCI_CRP_WDATA           IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET)
-#define PCI_CRP_RDATA           IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET)
-#define PCI_CSR                 IXP4XX_PCI_CSR(PCI_CSR_OFFSET) 
-#define PCI_ISR                 IXP4XX_PCI_CSR(PCI_ISR_OFFSET)
-#define PCI_INTEN               IXP4XX_PCI_CSR(PCI_INTEN_OFFSET)
-#define PCI_DMACTRL             IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET)
-#define PCI_AHBMEMBASE          IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET)
-#define PCI_AHBIOBASE           IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET)
-#define PCI_PCIMEMBASE          IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET)
-#define PCI_AHBDOORBELL         IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET)
-#define PCI_PCIDOORBELL         IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET)
-#define PCI_ATPDMA0_AHBADDR     IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)
-#define PCI_ATPDMA0_PCIADDR     IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)
-#define PCI_ATPDMA0_LENADDR     IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)
-#define PCI_ATPDMA1_AHBADDR     IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)
-#define PCI_ATPDMA1_PCIADDR     IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)
-#define PCI_ATPDMA1_LENADDR     IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)
-
-/*
- * PCI register values and bit definitions 
- */
-
-/* CSR bit definitions */
-#define PCI_CSR_HOST            0x00000001
-#define PCI_CSR_ARBEN           0x00000002
-#define PCI_CSR_ADS             0x00000004
-#define PCI_CSR_PDS             0x00000008
-#define PCI_CSR_ABE             0x00000010
-#define PCI_CSR_DBT             0x00000020
-#define PCI_CSR_ASE             0x00000100
-#define PCI_CSR_IC              0x00008000
-
-/* ISR (Interrupt status) Register bit definitions */
-#define PCI_ISR_PSE             0x00000001
-#define PCI_ISR_PFE             0x00000002
-#define PCI_ISR_PPE             0x00000004
-#define PCI_ISR_AHBE            0x00000008
-#define PCI_ISR_APDC            0x00000010
-#define PCI_ISR_PADC            0x00000020
-#define PCI_ISR_ADB             0x00000040
-#define PCI_ISR_PDB             0x00000080
-
-/* INTEN (Interrupt Enable) Register bit definitions */
-#define PCI_INTEN_PSE           0x00000001
-#define PCI_INTEN_PFE           0x00000002
-#define PCI_INTEN_PPE           0x00000004
-#define PCI_INTEN_AHBE          0x00000008
-#define PCI_INTEN_APDC          0x00000010
-#define PCI_INTEN_PADC          0x00000020
-#define PCI_INTEN_ADB           0x00000040
-#define PCI_INTEN_PDB           0x00000080
-
-/*
- * Shift value for byte enable on NP cmd/byte enable register
- */
-#define IXP4XX_PCI_NP_CBE_BESL          4
-
-/*
- * PCI commands supported by NP access unit
- */
-#define NP_CMD_IOREAD                   0x2
-#define NP_CMD_IOWRITE                  0x3
-#define NP_CMD_CONFIGREAD               0xa
-#define NP_CMD_CONFIGWRITE              0xb
-#define NP_CMD_MEMREAD                  0x6
-#define NP_CMD_MEMWRITE                 0x7
-
-/*
- * Constants for CRP access into local config space
- */
-#define CRP_AD_CBE_BESL         20
-#define CRP_AD_CBE_WRITE        0x00010000
-
-
-/*
- * USB Device Controller
- *
- * These are used by the USB gadget driver, so they don't follow the
- * IXP4XX_ naming convetions.
- *
- */
-# define IXP4XX_USB_REG(x)       (*((volatile u32 *)(x)))
-
-/* UDC Undocumented - Reserved1 */
-#define UDC_RES1        IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0004)  
-/* UDC Undocumented - Reserved2 */
-#define UDC_RES2        IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0008)  
-/* UDC Undocumented - Reserved3 */
-#define UDC_RES3        IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x000C)  
-/* UDC Control Register */
-#define UDCCR           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0000)  
-/* UDC Endpoint 0 Control/Status Register */
-#define UDCCS0          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0010)  
-/* UDC Endpoint 1 (IN) Control/Status Register */
-#define UDCCS1          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0014)  
-/* UDC Endpoint 2 (OUT) Control/Status Register */
-#define UDCCS2          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0018)  
-/* UDC Endpoint 3 (IN) Control/Status Register */
-#define UDCCS3          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x001C)  
-/* UDC Endpoint 4 (OUT) Control/Status Register */
-#define UDCCS4          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0020)  
-/* UDC Endpoint 5 (Interrupt) Control/Status Register */
-#define UDCCS5          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0024)  
-/* UDC Endpoint 6 (IN) Control/Status Register */
-#define UDCCS6          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0028)  
-/* UDC Endpoint 7 (OUT) Control/Status Register */
-#define UDCCS7          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x002C)  
-/* UDC Endpoint 8 (IN) Control/Status Register */
-#define UDCCS8          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0030)  
-/* UDC Endpoint 9 (OUT) Control/Status Register */
-#define UDCCS9          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0034)  
-/* UDC Endpoint 10 (Interrupt) Control/Status Register */
-#define UDCCS10         IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0038)  
-/* UDC Endpoint 11 (IN) Control/Status Register */
-#define UDCCS11         IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x003C)  
-/* UDC Endpoint 12 (OUT) Control/Status Register */
-#define UDCCS12         IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0040)  
-/* UDC Endpoint 13 (IN) Control/Status Register */
-#define UDCCS13         IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0044)  
-/* UDC Endpoint 14 (OUT) Control/Status Register */
-#define UDCCS14         IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0048)  
-/* UDC Endpoint 15 (Interrupt) Control/Status Register */
-#define UDCCS15         IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x004C)  
-/* UDC Frame Number Register High */
-#define UFNRH           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0060)  
-/* UDC Frame Number Register Low */
-#define UFNRL           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0064)  
-/* UDC Byte Count Reg 2 */
-#define UBCR2           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0068)  
-/* UDC Byte Count Reg 4 */
-#define UBCR4           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x006c)  
-/* UDC Byte Count Reg 7 */
-#define UBCR7           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0070)  
-/* UDC Byte Count Reg 9 */
-#define UBCR9           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0074)  
-/* UDC Byte Count Reg 12 */
-#define UBCR12          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0078)  
-/* UDC Byte Count Reg 14 */
-#define UBCR14          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x007c)  
-/* UDC Endpoint 0 Data Register */
-#define UDDR0           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0080)  
-/* UDC Endpoint 1 Data Register */
-#define UDDR1           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0100)  
-/* UDC Endpoint 2 Data Register */
-#define UDDR2           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0180)  
-/* UDC Endpoint 3 Data Register */
-#define UDDR3           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0200)  
-/* UDC Endpoint 4 Data Register */
-#define UDDR4           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0400)  
-/* UDC Endpoint 5 Data Register */
-#define UDDR5           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00A0)  
-/* UDC Endpoint 6 Data Register */
-#define UDDR6           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0600)  
-/* UDC Endpoint 7 Data Register */
-#define UDDR7           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0680)  
-/* UDC Endpoint 8 Data Register */
-#define UDDR8           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0700)  
-/* UDC Endpoint 9 Data Register */
-#define UDDR9           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0900)  
-/* UDC Endpoint 10 Data Register */
-#define UDDR10          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00C0)  
-/* UDC Endpoint 11 Data Register */
-#define UDDR11          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B00)  
-/* UDC Endpoint 12 Data Register */
-#define UDDR12          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B80)  
-/* UDC Endpoint 13 Data Register */
-#define UDDR13          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0C00)  
-/* UDC Endpoint 14 Data Register */
-#define UDDR14          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0E00)  
-/* UDC Endpoint 15 Data Register */
-#define UDDR15          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00E0)  
-/* UDC Interrupt Control Register 0 */
-#define UICR0           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0050)  
-/* UDC Interrupt Control Register 1 */
-#define UICR1           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0054)  
-/* UDC Status Interrupt Register 0 */
-#define USIR0           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0058)  
-/* UDC Status Interrupt Register 1 */
-#define USIR1           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x005C)  
-
-#define UDCCR_UDE       (1 << 0)        /* UDC enable */
-#define UDCCR_UDA       (1 << 1)        /* UDC active */
-#define UDCCR_RSM       (1 << 2)        /* Device resume */
-#define UDCCR_RESIR     (1 << 3)        /* Resume interrupt request */
-#define UDCCR_SUSIR     (1 << 4)        /* Suspend interrupt request */
-#define UDCCR_SRM       (1 << 5)        /* Suspend/resume interrupt mask */
-#define UDCCR_RSTIR     (1 << 6)        /* Reset interrupt request */
-#define UDCCR_REM       (1 << 7)        /* Reset interrupt mask */
-
-#define UDCCS0_OPR      (1 << 0)        /* OUT packet ready */
-#define UDCCS0_IPR      (1 << 1)        /* IN packet ready */
-#define UDCCS0_FTF      (1 << 2)        /* Flush Tx FIFO */
-#define UDCCS0_DRWF     (1 << 3)        /* Device remote wakeup feature */
-#define UDCCS0_SST      (1 << 4)        /* Sent stall */
-#define UDCCS0_FST      (1 << 5)        /* Force stall */
-#define UDCCS0_RNE      (1 << 6)        /* Receive FIFO no empty */
-#define UDCCS0_SA       (1 << 7)        /* Setup active */
-
-#define UDCCS_BI_TFS    (1 << 0)        /* Transmit FIFO service */
-#define UDCCS_BI_TPC    (1 << 1)        /* Transmit packet complete */
-#define UDCCS_BI_FTF    (1 << 2)        /* Flush Tx FIFO */
-#define UDCCS_BI_TUR    (1 << 3)        /* Transmit FIFO underrun */
-#define UDCCS_BI_SST    (1 << 4)        /* Sent stall */
-#define UDCCS_BI_FST    (1 << 5)        /* Force stall */
-#define UDCCS_BI_TSP    (1 << 7)        /* Transmit short packet */
-
-#define UDCCS_BO_RFS    (1 << 0)        /* Receive FIFO service */
-#define UDCCS_BO_RPC    (1 << 1)        /* Receive packet complete */
-#define UDCCS_BO_DME    (1 << 3)        /* DMA enable */
-#define UDCCS_BO_SST    (1 << 4)        /* Sent stall */
-#define UDCCS_BO_FST    (1 << 5)        /* Force stall */
-#define UDCCS_BO_RNE    (1 << 6)        /* Receive FIFO not empty */
-#define UDCCS_BO_RSP    (1 << 7)        /* Receive short packet */
-
-#define UDCCS_II_TFS    (1 << 0)        /* Transmit FIFO service */
-#define UDCCS_II_TPC    (1 << 1)        /* Transmit packet complete */
-#define UDCCS_II_FTF    (1 << 2)        /* Flush Tx FIFO */
-#define UDCCS_II_TUR    (1 << 3)        /* Transmit FIFO underrun */
-#define UDCCS_II_TSP    (1 << 7)        /* Transmit short packet */
-
-#define UDCCS_IO_RFS    (1 << 0)        /* Receive FIFO service */
-#define UDCCS_IO_RPC    (1 << 1)        /* Receive packet complete */
-#define UDCCS_IO_ROF    (1 << 3)        /* Receive overflow */
-#define UDCCS_IO_DME    (1 << 3)        /* DMA enable */
-#define UDCCS_IO_RNE    (1 << 6)        /* Receive FIFO not empty */
-#define UDCCS_IO_RSP    (1 << 7)        /* Receive short packet */
-
-#define UDCCS_INT_TFS   (1 << 0)        /* Transmit FIFO service */
-#define UDCCS_INT_TPC   (1 << 1)        /* Transmit packet complete */
-#define UDCCS_INT_FTF   (1 << 2)        /* Flush Tx FIFO */
-#define UDCCS_INT_TUR   (1 << 3)        /* Transmit FIFO underrun */
-#define UDCCS_INT_SST   (1 << 4)        /* Sent stall */
-#define UDCCS_INT_FST   (1 << 5)        /* Force stall */
-#define UDCCS_INT_TSP   (1 << 7)        /* Transmit short packet */
-
-#define UICR0_IM0       (1 << 0)        /* Interrupt mask ep 0 */
-#define UICR0_IM1       (1 << 1)        /* Interrupt mask ep 1 */
-#define UICR0_IM2       (1 << 2)        /* Interrupt mask ep 2 */
-#define UICR0_IM3       (1 << 3)        /* Interrupt mask ep 3 */
-#define UICR0_IM4       (1 << 4)        /* Interrupt mask ep 4 */
-#define UICR0_IM5       (1 << 5)        /* Interrupt mask ep 5 */
-#define UICR0_IM6       (1 << 6)        /* Interrupt mask ep 6 */
-#define UICR0_IM7       (1 << 7)        /* Interrupt mask ep 7 */
-
-#define UICR1_IM8       (1 << 0)        /* Interrupt mask ep 8 */
-#define UICR1_IM9       (1 << 1)        /* Interrupt mask ep 9 */
-#define UICR1_IM10      (1 << 2)        /* Interrupt mask ep 10 */
-#define UICR1_IM11      (1 << 3)        /* Interrupt mask ep 11 */
-#define UICR1_IM12      (1 << 4)        /* Interrupt mask ep 12 */
-#define UICR1_IM13      (1 << 5)        /* Interrupt mask ep 13 */
-#define UICR1_IM14      (1 << 6)        /* Interrupt mask ep 14 */
-#define UICR1_IM15      (1 << 7)        /* Interrupt mask ep 15 */
-
-#define USIR0_IR0       (1 << 0)        /* Interrupt request ep 0 */
-#define USIR0_IR1       (1 << 1)        /* Interrupt request ep 1 */
-#define USIR0_IR2       (1 << 2)        /* Interrupt request ep 2 */
-#define USIR0_IR3       (1 << 3)        /* Interrupt request ep 3 */
-#define USIR0_IR4       (1 << 4)        /* Interrupt request ep 4 */
-#define USIR0_IR5       (1 << 5)        /* Interrupt request ep 5 */
-#define USIR0_IR6       (1 << 6)        /* Interrupt request ep 6 */
-#define USIR0_IR7       (1 << 7)        /* Interrupt request ep 7 */
-
-#define USIR1_IR8       (1 << 0)        /* Interrupt request ep 8 */
-#define USIR1_IR9       (1 << 1)        /* Interrupt request ep 9 */
-#define USIR1_IR10      (1 << 2)        /* Interrupt request ep 10 */
-#define USIR1_IR11      (1 << 3)        /* Interrupt request ep 11 */
-#define USIR1_IR12      (1 << 4)        /* Interrupt request ep 12 */
-#define USIR1_IR13      (1 << 5)        /* Interrupt request ep 13 */
-#define USIR1_IR14      (1 << 6)        /* Interrupt request ep 14 */
-#define USIR1_IR15      (1 << 7)        /* Interrupt request ep 15 */
-
-#define DCMD_LENGTH     0x01fff         /* length mask (max = 8K - 1) */
-
-/* "fuse" bits of IXP_EXP_CFG2 */
-#define IXP4XX_FEATURE_RCOMP            (1 << 0)
-#define IXP4XX_FEATURE_USB_DEVICE       (1 << 1)
-#define IXP4XX_FEATURE_HASH             (1 << 2)
-#define IXP4XX_FEATURE_AES              (1 << 3)
-#define IXP4XX_FEATURE_DES              (1 << 4)
-#define IXP4XX_FEATURE_HDLC             (1 << 5)
-#define IXP4XX_FEATURE_AAL              (1 << 6)
-#define IXP4XX_FEATURE_HSS              (1 << 7)
-#define IXP4XX_FEATURE_UTOPIA           (1 << 8)
-#define IXP4XX_FEATURE_NPEB_ETH0        (1 << 9)
-#define IXP4XX_FEATURE_NPEC_ETH         (1 << 10)
-#define IXP4XX_FEATURE_RESET_NPEA       (1 << 11)
-#define IXP4XX_FEATURE_RESET_NPEB       (1 << 12)
-#define IXP4XX_FEATURE_RESET_NPEC       (1 << 13)
-#define IXP4XX_FEATURE_PCI              (1 << 14)
-#define IXP4XX_FEATURE_ECC_TIMESYNC     (1 << 15)
-#define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16)
-#define IXP4XX_FEATURE_USB_HOST         (1 << 18)
-#define IXP4XX_FEATURE_NPEA_ETH         (1 << 19)
-#define IXP4XX_FEATURE_NPEB_ETH_1_TO_3  (1 << 20)
-#define IXP4XX_FEATURE_RSA              (1 << 21)
-#define IXP4XX_FEATURE_XSCALE_MAX_FREQ  (3 << 22)
-#define IXP4XX_FEATURE_RESERVED         (0xFF << 24)
-
-#define IXP4XX_FEATURE_IXP46X_ONLY (IXP4XX_FEATURE_ECC_TIMESYNC |       \
-                                    IXP4XX_FEATURE_USB_HOST |           \
-                                    IXP4XX_FEATURE_NPEA_ETH |           \
-                                    IXP4XX_FEATURE_NPEB_ETH_1_TO_3 |    \
-                                    IXP4XX_FEATURE_RSA |                \
-                                    IXP4XX_FEATURE_XSCALE_MAX_FREQ)
-
-#endif
diff --git a/include/asm-arm/arch-ixp4xx/memory.h b/include/asm-arm/arch-ixp4xx/memory.h
deleted file mode 100644
index af9667b57ab3..000000000000
--- a/include/asm-arm/arch-ixp4xx/memory.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ixp4xx/memory.h
- *
- * Copyright (c) 2001-2004 MontaVista Software, Inc.
- */
-
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-#include <asm/sizes.h>
-
-/*
- * Physical DRAM offset.
- */
-#define PHYS_OFFSET     UL(0x00000000)
-
-#if !defined(__ASSEMBLY__) && defined(CONFIG_PCI)
-
-void ixp4xx_adjust_zones(int node, unsigned long *size, unsigned long *holes);
-
-#define arch_adjust_zones(node, size, holes) \
-        ixp4xx_adjust_zones(node, size, holes)
-
-#define ISA_DMA_THRESHOLD (SZ_64M - 1)
-
-#endif
-
-/*
- * Virtual view <-> DMA view memory address translations
- * virt_to_bus: Used to translate the virtual address to an
- *              address suitable to be passed to set_dma_addr
- * bus_to_virt: Used to convert an address for DMA operations
- *              to an address that the kernel can use.
- *
- * These are dummies for now.
- */
-#define __virt_to_bus(x)         __virt_to_phys(x)
-#define __bus_to_virt(x)         __phys_to_virt(x)
-
-#endif
diff --git a/include/asm-arm/arch-ixp4xx/nas100d.h b/include/asm-arm/arch-ixp4xx/nas100d.h
deleted file mode 100644
index ecb12d66399c..000000000000
--- a/include/asm-arm/arch-ixp4xx/nas100d.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * include/asm-arm/arch-ixp4xx/nas100d.h
- *
- * NAS100D platform specific definitions
- *
- * Copyright (c) 2005 Tower Technologies
- *
- * Author: Alessandro Zummo <a.zummo@towertech.it>
- *
- * based on ixdp425.h:
- *      Copyright 2004 (c) MontaVista, Software, Inc.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H__
-#error "Do not include this directly, instead #include <asm/arch/hardware.h>"
-#endif
-
-#define NAS100D_SDA_PIN         5
-#define NAS100D_SCL_PIN         6
-
-/*
- * NAS100D PCI IRQs
- */
-#define NAS100D_PCI_MAX_DEV     3
-#define NAS100D_PCI_IRQ_LINES   3
-
-
-/* PCI controller GPIO to IRQ pin mappings */
-#define NAS100D_PCI_INTA_PIN    11
-#define NAS100D_PCI_INTB_PIN    10
-#define NAS100D_PCI_INTC_PIN    9
-#define NAS100D_PCI_INTD_PIN    8
-#define NAS100D_PCI_INTE_PIN    7
-
-/* Buttons */
-
-#define NAS100D_PB_GPIO         14   /* power button */
-#define NAS100D_RB_GPIO         4    /* reset button */
-
-/* Power control */
-
-#define NAS100D_PO_GPIO         12   /* power off */
-
-/* LEDs */
-
-#define NAS100D_LED_WLAN_GPIO   0
-#define NAS100D_LED_DISK_GPIO   3
-#define NAS100D_LED_PWR_GPIO    15
diff --git a/include/asm-arm/arch-ixp4xx/nslu2.h b/include/asm-arm/arch-ixp4xx/nslu2.h
deleted file mode 100644
index fa895f44e431..000000000000
--- a/include/asm-arm/arch-ixp4xx/nslu2.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * include/asm-arm/arch-ixp4xx/nslu2.h
- *
- * NSLU2 platform specific definitions
- *
- * Author: Mark Rakes <mrakes AT mac.com>
- * Maintainers: http://www.nslu2-linux.org
- *
- * based on ixdp425.h:
- *      Copyright 2004 (c) MontaVista, Software, Inc.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H__
-#error "Do not include this directly, instead #include <asm/arch/hardware.h>"
-#endif
-
-#define NSLU2_SDA_PIN           7
-#define NSLU2_SCL_PIN           6
-
-/*
- * NSLU2 PCI IRQs
- */
-#define NSLU2_PCI_MAX_DEV       3
-#define NSLU2_PCI_IRQ_LINES     3
-
-
-/* PCI controller GPIO to IRQ pin mappings */
-#define NSLU2_PCI_INTA_PIN      11
-#define NSLU2_PCI_INTB_PIN      10
-#define NSLU2_PCI_INTC_PIN      9
-#define NSLU2_PCI_INTD_PIN      8
-
-/* NSLU2 Timer */
-#define NSLU2_FREQ 66000000
-
-/* Buttons */
-
-#define NSLU2_PB_GPIO           5       /* power button */
-#define NSLU2_PO_GPIO           8       /* power off */
-#define NSLU2_RB_GPIO           12      /* reset button */
-
-/* Buzzer */
-
-#define NSLU2_GPIO_BUZZ         4
-
-/* LEDs */
-
-#define NSLU2_LED_RED_GPIO      0
-#define NSLU2_LED_GRN_GPIO      1
-#define NSLU2_LED_DISK1_GPIO    3
-#define NSLU2_LED_DISK2_GPIO    2
diff --git a/include/asm-arm/arch-ixp4xx/platform.h b/include/asm-arm/arch-ixp4xx/platform.h
deleted file mode 100644
index b2af5154cef3..000000000000
--- a/include/asm-arm/arch-ixp4xx/platform.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * include/asm-arm/arch-ixp4xx/platform.h
- *
- * Constants and functions that are useful to IXP4xx platform-specific code
- * and device drivers.
- *
- * Copyright (C) 2004 MontaVista Software, Inc.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H__
-#error "Do not include this directly, instead #include <asm/arch/hardware.h>"
-#endif
-
-#ifndef __ASSEMBLY__
-
-#include <asm/types.h>
-
-#ifndef __ARMEB__
-#define REG_OFFSET      0
-#else
-#define REG_OFFSET      3
-#endif
-
-/*
- * Expansion bus memory regions
- */
-#define IXP4XX_EXP_BUS_BASE_PHYS        (0x50000000)
-
-/*
- * The expansion bus on the IXP4xx can be configured for either 16 or
- * 32MB windows and the CS offset for each region changes based on the
- * current configuration. This means that we cannot simply hardcode
- * each offset. ixp4xx_sys_init() looks at the expansion bus configuration
- * as setup by the bootloader to determine our window size.
- */
-extern unsigned long ixp4xx_exp_bus_size;
-
-#define IXP4XX_EXP_BUS_BASE(region)\
-                (IXP4XX_EXP_BUS_BASE_PHYS + ((region) * ixp4xx_exp_bus_size))
-
-#define IXP4XX_EXP_BUS_END(region)\
-                (IXP4XX_EXP_BUS_BASE(region) + ixp4xx_exp_bus_size - 1)
-
-/* Those macros can be used to adjust timing and configure
- * other features for each region.
- */
-
-#define IXP4XX_EXP_BUS_RECOVERY_T(x)    (((x) & 0x0f) << 16)
-#define IXP4XX_EXP_BUS_HOLD_T(x)        (((x) & 0x03) << 20)
-#define IXP4XX_EXP_BUS_STROBE_T(x)      (((x) & 0x0f) << 22)
-#define IXP4XX_EXP_BUS_SETUP_T(x)       (((x) & 0x03) << 26)
-#define IXP4XX_EXP_BUS_ADDR_T(x)        (((x) & 0x03) << 28)
-#define IXP4XX_EXP_BUS_SIZE(x)          (((x) & 0x0f) << 10)
-#define IXP4XX_EXP_BUS_CYCLES(x)        (((x) & 0x03) << 14)
-
-#define IXP4XX_EXP_BUS_CS_EN            (1L << 31)
-#define IXP4XX_EXP_BUS_BYTE_RD16        (1L << 6)
-#define IXP4XX_EXP_BUS_HRDY_POL         (1L << 5)
-#define IXP4XX_EXP_BUS_MUX_EN           (1L << 4)
-#define IXP4XX_EXP_BUS_SPLT_EN          (1L << 3)
-#define IXP4XX_EXP_BUS_WR_EN            (1L << 1)
-#define IXP4XX_EXP_BUS_BYTE_EN          (1L << 0)
-
-#define IXP4XX_EXP_BUS_CYCLES_INTEL     0x00
-#define IXP4XX_EXP_BUS_CYCLES_MOTOROLA  0x01
-#define IXP4XX_EXP_BUS_CYCLES_HPI       0x02
-
-#define IXP4XX_FLASH_WRITABLE   (0x2)
-#define IXP4XX_FLASH_DEFAULT    (0xbcd23c40)
-#define IXP4XX_FLASH_WRITE      (0xbcd23c42)
-
-/*
- * Clock Speed Definitions.
- */
-#define IXP4XX_PERIPHERAL_BUS_CLOCK     (66) /* 66Mhzi APB BUS   */ 
-#define IXP4XX_UART_XTAL                14745600
-
-/*
- * This structure provide a means for the board setup code
- * to give information to th pata_ixp4xx driver. It is
- * passed as platform_data.
- */
-struct ixp4xx_pata_data {
-        volatile u32    *cs0_cfg;
-        volatile u32    *cs1_cfg;
-        unsigned long   cs0_bits;
-        unsigned long   cs1_bits;
-        void __iomem    *cs0;
-        void __iomem    *cs1;
-};
-
-struct sys_timer;
-
-#define IXP4XX_ETH_NPEA         0x00
-#define IXP4XX_ETH_NPEB         0x10
-#define IXP4XX_ETH_NPEC         0x20
-
-/* Information about built-in Ethernet MAC interfaces */
-struct eth_plat_info {
-        u8 phy;         /* MII PHY ID, 0 - 31 */
-        u8 rxq;         /* configurable, currently 0 - 31 only */
-        u8 txreadyq;
-        u8 hwaddr[6];
-};
-
-/* Information about built-in HSS (synchronous serial) interfaces */
-struct hss_plat_info {
-        int (*set_clock)(int port, unsigned int clock_type);
-        int (*open)(int port, void *pdev,
-                    void (*set_carrier_cb)(void *pdev, int carrier));
-        void (*close)(int port, void *pdev);
-        u8 txreadyq;
-};
-
-/*
- * Frequency of clock used for primary clocksource
- */
-extern unsigned long ixp4xx_timer_freq;
-
-/*
- * Functions used by platform-level setup code
- */
-extern void ixp4xx_map_io(void);
-extern void ixp4xx_init_irq(void);
-extern void ixp4xx_sys_init(void);
-extern void ixp4xx_timer_init(void);
-extern struct sys_timer ixp4xx_timer;
-extern void ixp4xx_pci_preinit(void);
-struct pci_sys_data;
-extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
-extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
-
-/*
- * GPIO-functions
- */
-/*
- * The following converted to the real HW bits the gpio_line_config
- */
-/* GPIO pin types */
-#define IXP4XX_GPIO_OUT                 0x1
-#define IXP4XX_GPIO_IN                  0x2
-
-/* GPIO signal types */
-#define IXP4XX_GPIO_LOW                 0
-#define IXP4XX_GPIO_HIGH                1
-
-/* GPIO Clocks */
-#define IXP4XX_GPIO_CLK_0               14
-#define IXP4XX_GPIO_CLK_1               15
-
-static inline void gpio_line_config(u8 line, u32 direction)
-{
-        if (direction == IXP4XX_GPIO_IN)
-                *IXP4XX_GPIO_GPOER |= (1 << line);
-        else
-                *IXP4XX_GPIO_GPOER &= ~(1 << line);
-}
-
-static inline void gpio_line_get(u8 line, int *value)
-{
-        *value = (*IXP4XX_GPIO_GPINR >> line) & 0x1;
-}
-
-static inline void gpio_line_set(u8 line, int value)
-{
-        if (value == IXP4XX_GPIO_HIGH)
-            *IXP4XX_GPIO_GPOUTR |= (1 << line);
-        else if (value == IXP4XX_GPIO_LOW)
-            *IXP4XX_GPIO_GPOUTR &= ~(1 << line);
-}
-
-#endif // __ASSEMBLY__
-
diff --git a/include/asm-arm/arch-ixp4xx/prpmc1100.h b/include/asm-arm/arch-ixp4xx/prpmc1100.h
deleted file mode 100644
index 100855feafdd..000000000000
--- a/include/asm-arm/arch-ixp4xx/prpmc1100.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * include/asm-arm/arch-ixp4xx/prpmc1100.h
- *
- * Motorolla PrPMC1100 platform specific definitions
- *
- * Author: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright 2004 (c) MontaVista, Software, Inc. 
- * 
- * This file is licensed under  the terms of the GNU General Public 
- * License version 2. This program is licensed "as is" without any 
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H__
-#error "Do not include this directly, instead #include <asm/arch/hardware.h>"
-#endif
-
-#define PRPMC1100_FLASH_BASE    IXP4XX_EXP_BUS_CS0_BASE_PHYS
-#define PRPMC1100_FLASH_SIZE    IXP4XX_EXP_BUS_CSX_REGION_SIZE
-
-#define PRPMC1100_PCI_MIN_DEVID 10
-#define PRPMC1100_PCI_MAX_DEVID 16
-#define PRPMC1100_PCI_IRQ_LINES 4
-
-
-/* PCI controller GPIO to IRQ pin mappings */
-#define PRPMC1100_PCI_INTA_PIN  11
-#define PRPMC1100_PCI_INTB_PIN  10
-#define PRPMC1100_PCI_INTC_PIN  9
-#define PRPMC1100_PCI_INTD_PIN  8
-
-
diff --git a/include/asm-arm/arch-ixp4xx/system.h b/include/asm-arm/arch-ixp4xx/system.h
deleted file mode 100644
index f11b92262a07..000000000000
--- a/include/asm-arm/arch-ixp4xx/system.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * include/asm-arm/arch-ixp4xx/system.h
- *
- * Copyright (C) 2002 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <asm/arch/hardware.h>
-
-static inline void arch_idle(void)
-{
-#if 0
-        if (!hlt_counter)
-                cpu_do_idle(0);
-#endif
-}
-
-
-static inline void arch_reset(char mode)
-{
-        if ( 1 && mode == 's') {
-                /* Jump into ROM at address 0 */
-                cpu_reset(0);
-        } else {
-                /* Use on-chip reset capability */
-
-                /* set the "key" register to enable access to
-                 * "timer" and "enable" registers
-                 */
-                *IXP4XX_OSWK = IXP4XX_WDT_KEY;
-
-                /* write 0 to the timer register for an immediate reset */
-                *IXP4XX_OSWT = 0;
-
-                *IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;
-        }
-}
-
diff --git a/include/asm-arm/arch-ixp4xx/timex.h b/include/asm-arm/arch-ixp4xx/timex.h
deleted file mode 100644
index c2559e28cbcb..000000000000
--- a/include/asm-arm/arch-ixp4xx/timex.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ixp4xx/timex.h
- * 
- */
-
-#include <asm/arch/hardware.h>
-
-/*
- * We use IXP425 General purpose timer for our timer needs, it runs at 
- * 66.66... MHz. We do a convulted calculation of CLOCK_TICK_RATE b/c the
- * timer register ignores the bottom 2 bits of the LATCH value.
- */
-#define FREQ 66666666
-#define CLOCK_TICK_RATE (((FREQ / HZ & ~IXP4XX_OST_RELOAD_MASK) + 1) * HZ)
-
diff --git a/include/asm-arm/arch-ixp4xx/udc.h b/include/asm-arm/arch-ixp4xx/udc.h
deleted file mode 100644
index dbdec36ff0d1..000000000000
--- a/include/asm-arm/arch-ixp4xx/udc.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ixp4xx/udc.h
- *
- */
-#include <asm/mach/udc_pxa2xx.h>
-
-extern void ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info);
-
diff --git a/include/asm-arm/arch-ixp4xx/uncompress.h b/include/asm-arm/arch-ixp4xx/uncompress.h
deleted file mode 100644
index 34ef48fe327e..000000000000
--- a/include/asm-arm/arch-ixp4xx/uncompress.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * include/asm-arm/arch-ixp4xx/uncompress.h 
- *
- * Copyright (C) 2002 Intel Corporation.
- * Copyright (C) 2003-2004 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef _ARCH_UNCOMPRESS_H_
-#define _ARCH_UNCOMPRESS_H_
-
-#include "ixp4xx-regs.h"
-#include <asm/mach-types.h>
-#include <linux/serial_reg.h>
-
-#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE)
-
-static volatile u32* uart_base;
-
-static inline void putc(int c)
-{
-        /* Check THRE and TEMT bits before we transmit the character.
-         */
-        while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
-                barrier();
-
-        *uart_base = c;
-}
-
-static void flush(void)
-{
-}
-
-static __inline__ void __arch_decomp_setup(unsigned long arch_id)
-{
-        /*
-         * Some boards are using UART2 as console
-         */
-        if (machine_is_adi_coyote() || machine_is_gtwx5715() ||
-                         machine_is_gateway7001() || machine_is_wg302v2())
-                uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
-        else
-                uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;
-}
-
-/*
- * arch_id is a variable in decompress_kernel()
- */
-#define arch_decomp_setup()     __arch_decomp_setup(arch_id)
-
-#define arch_decomp_wdog()
-
-#endif
diff --git a/include/asm-arm/arch-ixp4xx/vmalloc.h b/include/asm-arm/arch-ixp4xx/vmalloc.h
deleted file mode 100644
index 050d46e6b126..000000000000
--- a/include/asm-arm/arch-ixp4xx/vmalloc.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ixp4xx/vmalloc.h
- */
-#define VMALLOC_END       (0xFF000000)
-
diff --git a/include/asm-arm/arch-kirkwood/debug-macro.S b/include/asm-arm/arch-kirkwood/debug-macro.S
deleted file mode 100644
index f55fb8ad9ee4..000000000000
--- a/include/asm-arm/arch-kirkwood/debug-macro.S
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * include/asm-arm/arch-kirkwood/debug-macro.S
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <asm/arch/kirkwood.h>
-
-        .macro  addruart,rx
-        mrc     p15, 0, \rx, c1, c0
-        tst     \rx, #1                                 @ MMU enabled?
-        ldreq   \rx, =KIRKWOOD_REGS_PHYS_BASE
-        ldrne   \rx, =KIRKWOOD_REGS_VIRT_BASE
-        orr     \rx, \rx, #0x00012000
-        .endm
-
-#define UART_SHIFT      2
-#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-kirkwood/entry-macro.S b/include/asm-arm/arch-kirkwood/entry-macro.S
deleted file mode 100644
index fc6a43d9355c..000000000000
--- a/include/asm-arm/arch-kirkwood/entry-macro.S
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * include/asm-arm/arch-kirkwood/entry-macro.S
- *
- * Low-level IRQ helper macros for Marvell Kirkwood platforms
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/arch/kirkwood.h>
-
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
-        .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =IRQ_VIRT_BASE
-        .endm
-
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        @ check low interrupts
-        ldr     \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
-        ldr     \tmp, [\base, #IRQ_MASK_LOW_OFF]
-        mov     \irqnr, #31
-        ands    \irqstat, \irqstat, \tmp
-        bne     1001f
-
-        @ if no low interrupts set, check high interrupts
-        ldr     \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
-        ldr     \tmp, [\base, #IRQ_MASK_HIGH_OFF]
-        mov     \irqnr, #63
-        ands    \irqstat, \irqstat, \tmp
-
-        @ find first active interrupt source
-1001:   clzne   \irqstat, \irqstat
-        subne   \irqnr, \irqnr, \irqstat
-        .endm
diff --git a/include/asm-arm/arch-kirkwood/hardware.h b/include/asm-arm/arch-kirkwood/hardware.h
deleted file mode 100644
index e695719771a5..000000000000
--- a/include/asm-arm/arch-kirkwood/hardware.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * include/asm-arm/arch-kirkwood/hardware.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include "kirkwood.h"
-
-#define pcibios_assign_all_busses()     1
-
-#define PCIBIOS_MIN_IO                  0x00001000
-#define PCIBIOS_MIN_MEM                 0x01000000
-#define PCIMEM_BASE                     KIRKWOOD_PCIE_MEM_PHYS_BASE /* mem base for VGA */
-
-
-#endif
diff --git a/include/asm-arm/arch-kirkwood/io.h b/include/asm-arm/arch-kirkwood/io.h
deleted file mode 100644
index 0ef6e95f5d5b..000000000000
--- a/include/asm-arm/arch-kirkwood/io.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * include/asm-arm/arch-kirkwood/io.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#include "kirkwood.h"
-
-#define IO_SPACE_LIMIT          0xffffffff
-
-static inline void __iomem *__io(unsigned long addr)
-{
-        return (void __iomem *)((addr - KIRKWOOD_PCIE_IO_PHYS_BASE)
-                                        + KIRKWOOD_PCIE_IO_VIRT_BASE);
-}
-
-#define __io(a)                 __io(a)
-#define __mem_pci(a)            (a)
-
-
-#endif
diff --git a/include/asm-arm/arch-kirkwood/irqs.h b/include/asm-arm/arch-kirkwood/irqs.h
deleted file mode 100644
index 2e7b5da6335c..000000000000
--- a/include/asm-arm/arch-kirkwood/irqs.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * include/asm-arm/arch-kirkwood/irqs.h
- *
- * IRQ definitions for Marvell Kirkwood SoCs
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H
-
-#include "kirkwood.h"   /* need GPIO_MAX */
-
-/*
- * Low Interrupt Controller
- */
-#define IRQ_KIRKWOOD_HIGH_SUM   0
-#define IRQ_KIRKWOOD_BRIDGE     1
-#define IRQ_KIRKWOOD_HOST2CPU   2
-#define IRQ_KIRKWOOD_CPU2HOST   3
-#define IRQ_KIRKWOOD_XOR_00     5
-#define IRQ_KIRKWOOD_XOR_01     6
-#define IRQ_KIRKWOOD_XOR_10     7
-#define IRQ_KIRKWOOD_XOR_11     8
-#define IRQ_KIRKWOOD_PCIE       9
-#define IRQ_KIRKWOOD_GE00_SUM   11
-#define IRQ_KIRKWOOD_GE01_SUM   15
-#define IRQ_KIRKWOOD_USB        19
-#define IRQ_KIRKWOOD_SATA       21
-#define IRQ_KIRKWOOD_CRYPTO     22
-#define IRQ_KIRKWOOD_SPI        23
-#define IRQ_KIRKWOOD_I2S        24
-#define IRQ_KIRKWOOD_TS_0       26
-#define IRQ_KIRKWOOD_SDIO       28
-#define IRQ_KIRKWOOD_TWSI       29
-#define IRQ_KIRKWOOD_AVB        30
-#define IRQ_KIRKWOOD_TDMI       31
-
-/*
- * High Interrupt Controller
- */
-#define IRQ_KIRKWOOD_UART_0     33
-#define IRQ_KIRKWOOD_UART_1     34
-#define IRQ_KIRKWOOD_GPIO_LOW_0_7       35
-#define IRQ_KIRKWOOD_GPIO_LOW_8_15      36
-#define IRQ_KIRKWOOD_GPIO_LOW_16_23     37
-#define IRQ_KIRKWOOD_GPIO_LOW_24_31     38
-#define IRQ_KIRKWOOD_GPIO_HIGH_0_7      39
-#define IRQ_KIRKWOOD_GPIO_HIGH_8_15     40
-#define IRQ_KIRKWOOD_GPIO_HIGH_16_23    41
-
-/*
- * KIRKWOOD General Purpose Pins
- */
-#define IRQ_KIRKWOOD_GPIO_START 64
-#define NR_GPIO_IRQS            GPIO_MAX
-
-#define NR_IRQS                 (IRQ_KIRKWOOD_GPIO_START + NR_GPIO_IRQS)
-
-
-#endif
diff --git a/include/asm-arm/arch-kirkwood/kirkwood.h b/include/asm-arm/arch-kirkwood/kirkwood.h
deleted file mode 100644
index bb31b315c350..000000000000
--- a/include/asm-arm/arch-kirkwood/kirkwood.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * include/asm-arm/arch-kirkwood/kirkwood.h
- *
- * Generic definitions for Marvell Kirkwood SoC flavors:
- *  88F6180, 88F6192 and 88F6281.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_KIRKWOOD_H
-#define __ASM_ARCH_KIRKWOOD_H
-
-/*
- * Marvell Kirkwood address maps.
- *
- * phys
- * e0000000     PCIe Memory space
- * f1000000     on-chip peripheral registers
- * f2000000     PCIe I/O space
- * f3000000     NAND controller address window
- *
- * virt         phys            size
- * fee00000     f1000000        1M      on-chip peripheral registers
- * fef00000     f2000000        1M      PCIe I/O space
- */
-
-#define KIRKWOOD_NAND_MEM_PHYS_BASE     0xf3000000
-#define KIRKWOOD_NAND_MEM_SIZE          SZ_64K /* 1K is sufficient, but 64K
-                                                * is the minimal window size
-                                                */
-
-#define KIRKWOOD_PCIE_IO_PHYS_BASE      0xf2000000
-#define KIRKWOOD_PCIE_IO_VIRT_BASE      0xfef00000
-#define KIRKWOOD_PCIE_IO_BUS_BASE       0x00000000
-#define KIRKWOOD_PCIE_IO_SIZE           SZ_1M
-
-#define KIRKWOOD_REGS_PHYS_BASE         0xf1000000
-#define KIRKWOOD_REGS_VIRT_BASE         0xfee00000
-#define KIRKWOOD_REGS_SIZE              SZ_1M
-
-#define KIRKWOOD_PCIE_MEM_PHYS_BASE     0xe0000000
-#define KIRKWOOD_PCIE_MEM_SIZE          SZ_128M
-
-/*
- * MBUS bridge registers.
- */
-#define BRIDGE_VIRT_BASE        (KIRKWOOD_REGS_VIRT_BASE | 0x20000)
-#define  CPU_CONTROL            (BRIDGE_VIRT_BASE | 0x0104)
-#define   CPU_RESET             0x00000002
-#define  RSTOUTn_MASK           (BRIDGE_VIRT_BASE | 0x0108)
-#define   SOFT_RESET_OUT_EN     0x00000004
-#define  SYSTEM_SOFT_RESET      (BRIDGE_VIRT_BASE | 0x010c)
-#define   SOFT_RESET            0x00000001
-#define  BRIDGE_CAUSE           (BRIDGE_VIRT_BASE | 0x0110)
-#define  BRIDGE_MASK            (BRIDGE_VIRT_BASE | 0x0114)
-#define   BRIDGE_INT_TIMER0     0x0002
-#define   BRIDGE_INT_TIMER1     0x0004
-#define   BRIDGE_INT_TIMER1_CLR (~0x0004)
-#define  IRQ_VIRT_BASE          (BRIDGE_VIRT_BASE | 0x0200)
-#define   IRQ_CAUSE_LOW_OFF     0x0000
-#define   IRQ_MASK_LOW_OFF      0x0004
-#define   IRQ_CAUSE_HIGH_OFF    0x0010
-#define   IRQ_MASK_HIGH_OFF     0x0014
-#define  TIMER_VIRT_BASE        (BRIDGE_VIRT_BASE | 0x0300)
-#define  L2_CONFIG_REG          (BRIDGE_VIRT_BASE | 0x0128)
-#define   L2_WRITETHROUGH       0x00000010
-
-/*
- * Register Map
- */
-#define DDR_VIRT_BASE           (KIRKWOOD_REGS_VIRT_BASE | 0x00000)
-#define  DDR_WINDOW_CPU_BASE    (DDR_VIRT_BASE | 0x1500)
-
-#define DEV_BUS_PHYS_BASE       (KIRKWOOD_REGS_PHYS_BASE | 0x10000)
-#define DEV_BUS_VIRT_BASE       (KIRKWOOD_REGS_VIRT_BASE | 0x10000)
-#define  SAMPLE_AT_RESET        (DEV_BUS_VIRT_BASE | 0x0030)
-#define  DEVICE_ID              (DEV_BUS_VIRT_BASE | 0x0034)
-#define  RTC_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x0300)
-#define  SPI_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x0600)
-#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2000)
-#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2000)
-#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2100)
-#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2100)
-
-#define PCIE_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
-
-#define USB_PHYS_BASE           (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
-
-#define GE00_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x70000)
-#define GE01_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x74000)
-
-#define SATA_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x80000)
-
-
-#define GPIO_MAX                50
-
-
-#endif
diff --git a/include/asm-arm/arch-kirkwood/memory.h b/include/asm-arm/arch-kirkwood/memory.h
deleted file mode 100644
index e5108f408ce6..000000000000
--- a/include/asm-arm/arch-kirkwood/memory.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * include/asm-arm/arch-kirkwood/memory.h
- */
-
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-#define PHYS_OFFSET             UL(0x00000000)
-
-#define __virt_to_bus(x)        __virt_to_phys(x)
-#define __bus_to_virt(x)        __phys_to_virt(x)
-
-
-#endif
diff --git a/include/asm-arm/arch-kirkwood/system.h b/include/asm-arm/arch-kirkwood/system.h
deleted file mode 100644
index 8dde7e379855..000000000000
--- a/include/asm-arm/arch-kirkwood/system.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * include/asm-arm/arch-kirkwood/system.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/kirkwood.h>
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-static inline void arch_reset(char mode)
-{
-        /*
-         * Enable soft reset to assert RSTOUTn.
-         */
-        writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
-
-        /*
-         * Assert soft reset.
-         */
-        writel(SOFT_RESET, SYSTEM_SOFT_RESET);
-
-        while (1)
-                ;
-}
-
-
-#endif
diff --git a/include/asm-arm/arch-kirkwood/timex.h b/include/asm-arm/arch-kirkwood/timex.h
deleted file mode 100644
index 82122e134e3c..000000000000
--- a/include/asm-arm/arch-kirkwood/timex.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * include/asm-arm/arch-kirkwood/timex.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#define CLOCK_TICK_RATE         (100 * HZ)
-
-#define KIRKWOOD_TCLK           166666667
diff --git a/include/asm-arm/arch-kirkwood/uncompress.h b/include/asm-arm/arch-kirkwood/uncompress.h
deleted file mode 100644
index a9062b6d7680..000000000000
--- a/include/asm-arm/arch-kirkwood/uncompress.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * include/asm-arm/arch-kirkwood/uncompress.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/serial_reg.h>
-#include <asm/arch/kirkwood.h>
-
-#define SERIAL_BASE     ((unsigned char *)UART0_PHYS_BASE)
-
-static void putc(const char c)
-{
-        unsigned char *base = SERIAL_BASE;
-        int i;
-
-        for (i = 0; i < 0x1000; i++) {
-                if (base[UART_LSR << 2] & UART_LSR_THRE)
-                        break;
-                barrier();
-        }
-
-        base[UART_TX << 2] = c;
-}
-
-static void flush(void)
-{
-        unsigned char *base = SERIAL_BASE;
-        unsigned char mask;
-        int i;
-
-        mask = UART_LSR_TEMT | UART_LSR_THRE;
-
-        for (i = 0; i < 0x1000; i++) {
-                if ((base[UART_LSR << 2] & mask) == mask)
-                        break;
-                barrier();
-        }
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-kirkwood/vmalloc.h b/include/asm-arm/arch-kirkwood/vmalloc.h
deleted file mode 100644
index 41852c6e77f3..000000000000
--- a/include/asm-arm/arch-kirkwood/vmalloc.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * include/asm-arm/arch-kirkwood/vmalloc.h
- */
-
-#define VMALLOC_END     0xfe800000
diff --git a/include/asm-arm/arch-ks8695/debug-macro.S b/include/asm-arm/arch-ks8695/debug-macro.S
deleted file mode 100644
index d2583ffffa95..000000000000
--- a/include/asm-arm/arch-ks8695/debug-macro.S
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * include/asm-arm/arch-ks8695/debug-macro.S
- *
- * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
- * Copyright (C) 2006 Simtec Electronics
- *
- * KS8695 - Debug macros
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/regs-uart.h>
-
-        .macro  addruart, rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                         @ MMU enabled?
-                ldreq   \rx, =KS8695_UART_PA            @ physical base address
-                ldrne   \rx, =KS8695_UART_VA            @ virtual base address
-        .endm
-
-        .macro  senduart, rd, rx
-                str     \rd, [\rx, #KS8695_URTH]        @ Write to Transmit Holding Register
-        .endm
-
-        .macro  busyuart, rd, rx
-1001:           ldr     \rd, [\rx, #KS8695_URLS]        @ Read Line Status Register
-                tst     \rd, #URLS_URTE                 @ Holding & Shift registers empty?
-                beq     1001b
-        .endm
-
-        .macro  waituart, rd, rx
-1001:           ldr     \rd, [\rx, #KS8695_URLS]        @ Read Line Status Register
-                tst     \rd, #URLS_URTHRE               @ Holding Register empty?
-                beq     1001b
-        .endm
diff --git a/include/asm-arm/arch-ks8695/devices.h b/include/asm-arm/arch-ks8695/devices.h
deleted file mode 100644
index 7ad2c656e162..000000000000
--- a/include/asm-arm/arch-ks8695/devices.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * include/asm-arm/arch-ks8695/devices.h
- *
- * Copyright (C) 2006 Andrew Victor
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_DEVICES_H
-#define __ASM_ARCH_DEVICES_H
-
-#include <linux/pci.h>
-
- /* Ethernet */
-extern void __init ks8695_add_device_wan(void);
-extern void __init ks8695_add_device_lan(void);
-extern void __init ks8695_add_device_hpna(void);
-
- /* LEDs */
-extern short ks8695_leds_cpu;
-extern short ks8695_leds_timer;
-extern void __init ks8695_init_leds(u8 cpu_led, u8 timer_led);
-
- /* PCI */
-#define KS8695_MODE_PCI         0
-#define KS8695_MODE_MINIPCI     1
-#define KS8695_MODE_CARDBUS     2
-
-struct ks8695_pci_cfg {
-        short mode;
-        int (*map_irq)(struct pci_dev *, u8, u8);
-};
-extern __init void ks8695_init_pci(struct ks8695_pci_cfg *);
-
-#endif
diff --git a/include/asm-arm/arch-ks8695/dma.h b/include/asm-arm/arch-ks8695/dma.h
deleted file mode 100644
index e5159ed42a4b..000000000000
--- a/include/asm-arm/arch-ks8695/dma.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * include/asm-arm/arch-ks8695/dma.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
diff --git a/include/asm-arm/arch-ks8695/entry-macro.S b/include/asm-arm/arch-ks8695/entry-macro.S
deleted file mode 100644
index 3993cfe67cfa..000000000000
--- a/include/asm-arm/arch-ks8695/entry-macro.S
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * include/asm-arm/arch-ks8695/entry-macro.S
- *
- * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
- * Copyright (C) 2006 Simtec Electronics
- *
- * Low-level IRQ helper macros for KS8695
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
-*/
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/regs-irq.h>
-
-        .macro  disable_fiq
-        .endm
-
-        .macro  get_irqnr_preamble, base, tmp
-                ldr     \base, =KS8695_IRQ_VA                   @ Base address of interrupt controller
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \irqstat, [\base, #KS8695_INTMS]        @ Mask Status register
-
-                teq     \irqstat, #0
-                beq     1001f
-
-                mov     \irqnr, #0
-
-                tst     \irqstat, #0xff
-                moveq   \irqstat, \irqstat, lsr #8
-                addeq   \irqnr, \irqnr, #8
-                tsteq   \irqstat, #0xff
-                moveq   \irqstat, \irqstat, lsr #8
-                addeq   \irqnr, \irqnr, #8
-                tsteq   \irqstat, #0xff
-                moveq   \irqstat, \irqstat, lsr #8
-                addeq   \irqnr, \irqnr, #8
-                tst     \irqstat, #0x0f
-                moveq   \irqstat, \irqstat, lsr #4
-                addeq   \irqnr, \irqnr, #4
-                tst     \irqstat, #0x03
-                moveq   \irqstat, \irqstat, lsr #2
-                addeq   \irqnr, \irqnr, #2
-                tst     \irqstat, #0x01
-                addeqs  \irqnr, \irqnr, #1
-1001:
-        .endm
diff --git a/include/asm-arm/arch-ks8695/gpio.h b/include/asm-arm/arch-ks8695/gpio.h
deleted file mode 100644
index 65ceea28607b..000000000000
--- a/include/asm-arm/arch-ks8695/gpio.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * include/asm-arm/arch-ks8695/gpio.h
- *
- * Copyright (C) 2006 Andrew Victor
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_GPIO_H_
-#define __ASM_ARCH_GPIO_H_
-
-#define KS8695_GPIO_0           0
-#define KS8695_GPIO_1           1
-#define KS8695_GPIO_2           2
-#define KS8695_GPIO_3           3
-#define KS8695_GPIO_4           4
-#define KS8695_GPIO_5           5
-#define KS8695_GPIO_6           6
-#define KS8695_GPIO_7           7
-#define KS8695_GPIO_8           8
-#define KS8695_GPIO_9           9
-#define KS8695_GPIO_10          10
-#define KS8695_GPIO_11          11
-#define KS8695_GPIO_12          12
-#define KS8695_GPIO_13          13
-#define KS8695_GPIO_14          14
-#define KS8695_GPIO_15          15
-
-
-/*
- * Configure GPIO pin as external interrupt source.
- */
-int __init_or_module ks8695_gpio_interrupt(unsigned int pin, unsigned int type);
-
-/*
- * Configure the GPIO line as an input.
- */
-int __init_or_module gpio_direction_input(unsigned int pin);
-
-/*
- * Configure the GPIO line as an output, with default state.
- */
-int __init_or_module gpio_direction_output(unsigned int pin, unsigned int state);
-
-/*
- * Set the state of an output GPIO line.
- */
-void gpio_set_value(unsigned int pin, unsigned int state);
-
-/*
- * Read the state of a GPIO line.
- */
-int gpio_get_value(unsigned int pin);
-
-/*
- * Map GPIO line to IRQ number.
- */
-int gpio_to_irq(unsigned int pin);
-
-/*
- * Map IRQ number to GPIO line.
- */
-int irq_to_gpio(unsigned int irq);
-
-
-#include <asm-generic/gpio.h>
-
-static inline int gpio_request(unsigned int pin, const char *label)
-{
-        return 0;
-}
-
-static inline void gpio_free(unsigned int pin)
-{
-}
-
-#endif
diff --git a/include/asm-arm/arch-ks8695/hardware.h b/include/asm-arm/arch-ks8695/hardware.h
deleted file mode 100644
index cb732bff3288..000000000000
--- a/include/asm-arm/arch-ks8695/hardware.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * include/asm-arm/arch-ks8695/hardware.h
- *
- * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
- * Copyright (C) 2006 Simtec Electronics
- *
- * KS8695 - Memory Map definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <asm/sizes.h>
-
-/*
- * Physical RAM address.
- */
-#define KS8695_SDRAM_PA         0x00000000
-
-
-/*
- * We map an entire MiB with the System Configuration Registers in even
- * though only 64KiB is needed. This makes it easier for use with the
- * head debug code as the initial MMU setup only deals in L1 sections.
- */
-#define KS8695_IO_PA            0x03F00000
-#define KS8695_IO_VA            0xF0000000
-#define KS8695_IO_SIZE          SZ_1M
-
-#define KS8695_PCIMEM_PA        0x60000000
-#define KS8695_PCIMEM_SIZE      SZ_512M
-
-#define KS8695_PCIIO_PA         0x80000000
-#define KS8695_PCIIO_SIZE       SZ_64K
-
-
-/*
- * PCI support
- */
-#define pcibios_assign_all_busses()     1
-
-#define PCIBIOS_MIN_IO          0
-#define PCIBIOS_MIN_MEM         0
-
-#endif
diff --git a/include/asm-arm/arch-ks8695/io.h b/include/asm-arm/arch-ks8695/io.h
deleted file mode 100644
index 8edc4bd6aadf..000000000000
--- a/include/asm-arm/arch-ks8695/io.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * include/asm-arm/arch-ks8695/io.h
- *
- * Copyright (C) 2006 Andrew Victor
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT          0xffffffff
-
-#define __io(a)                 ((void __iomem *)(a))
-#define __mem_pci(a)            (a)
-
-#endif
diff --git a/include/asm-arm/arch-ks8695/irqs.h b/include/asm-arm/arch-ks8695/irqs.h
deleted file mode 100644
index 8b1c4fe96a81..000000000000
--- a/include/asm-arm/arch-ks8695/irqs.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ks8695/irqs.h
- *
- * Copyright (C) 2006 Simtec Electronics
- *   Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H
-
-
-#define NR_IRQS                         32
-
-/*
- * IRQ definitions
- */
-#define KS8695_IRQ_COMM_RX              0
-#define KS8695_IRQ_COMM_TX              1
-#define KS8695_IRQ_EXTERN0              2
-#define KS8695_IRQ_EXTERN1              3
-#define KS8695_IRQ_EXTERN2              4
-#define KS8695_IRQ_EXTERN3              5
-#define KS8695_IRQ_TIMER0               6
-#define KS8695_IRQ_TIMER1               7
-#define KS8695_IRQ_UART_TX              8
-#define KS8695_IRQ_UART_RX              9
-#define KS8695_IRQ_UART_LINE_STATUS     10
-#define KS8695_IRQ_UART_MODEM_STATUS    11
-#define KS8695_IRQ_LAN_RX_STOP          12
-#define KS8695_IRQ_LAN_TX_STOP          13
-#define KS8695_IRQ_LAN_RX_BUF           14
-#define KS8695_IRQ_LAN_TX_BUF           15
-#define KS8695_IRQ_LAN_RX_STATUS        16
-#define KS8695_IRQ_LAN_TX_STATUS        17
-#define KS8695_IRQ_HPNA_RX_STOP         18
-#define KS8695_IRQ_HPNA_TX_STOP         19
-#define KS8695_IRQ_HPNA_RX_BUF          20
-#define KS8695_IRQ_HPNA_TX_BUF          21
-#define KS8695_IRQ_HPNA_RX_STATUS       22
-#define KS8695_IRQ_HPNA_TX_STATUS       23
-#define KS8695_IRQ_BUS_ERROR            24
-#define KS8695_IRQ_WAN_RX_STOP          25
-#define KS8695_IRQ_WAN_TX_STOP          26
-#define KS8695_IRQ_WAN_RX_BUF           27
-#define KS8695_IRQ_WAN_TX_BUF           28
-#define KS8695_IRQ_WAN_RX_STATUS        29
-#define KS8695_IRQ_WAN_TX_STATUS        30
-#define KS8695_IRQ_WAN_LINK             31
-
-#endif
diff --git a/include/asm-arm/arch-ks8695/memory.h b/include/asm-arm/arch-ks8695/memory.h
deleted file mode 100644
index 1b542f77977a..000000000000
--- a/include/asm-arm/arch-ks8695/memory.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * include/asm-arm/arch-ks8695/memory.h
- *
- * Copyright (C) 2006 Andrew Victor
- *
- * KS8695 Memory definitions
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-#include <asm/arch/hardware.h>
-
-/*
- * Physical SRAM offset.
- */
-#define PHYS_OFFSET             KS8695_SDRAM_PA
-
-#ifndef __ASSEMBLY__
-
-#ifdef CONFIG_PCI
-
-/* PCI mappings */
-#define __virt_to_bus(x)        ((x) - PAGE_OFFSET + KS8695_PCIMEM_PA)
-#define __bus_to_virt(x)        ((x) - KS8695_PCIMEM_PA + PAGE_OFFSET)
-
-/* Platform-bus mapping */
-extern struct bus_type platform_bus_type;
-#define is_lbus_device(dev)             (dev && dev->bus == &platform_bus_type)
-#define __arch_dma_to_virt(dev, x)      ({ is_lbus_device(dev) ? \
-                                        __phys_to_virt(x) : __bus_to_virt(x); })
-#define __arch_virt_to_dma(dev, x)      ({ is_lbus_device(dev) ? \
-                                        (dma_addr_t)__virt_to_phys(x) : (dma_addr_t)__virt_to_bus(x); })
-#define __arch_page_to_dma(dev, x)      __arch_virt_to_dma(dev, page_address(x))
-
-#else
-
-#define __virt_to_bus(x)        __virt_to_phys(x)
-#define __bus_to_virt(x)        __phys_to_virt(x)
-
-#endif
-
-#endif
-
-#endif
diff --git a/include/asm-arm/arch-ks8695/regs-gpio.h b/include/asm-arm/arch-ks8695/regs-gpio.h
deleted file mode 100644
index 6b95d77aea19..000000000000
--- a/include/asm-arm/arch-ks8695/regs-gpio.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * include/asm-arm/arch-ks8695/regs-gpio.h
- *
- * Copyright (C) 2007 Andrew Victor
- *
- * KS8695 - GPIO control registers and bit definitions.
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef KS8695_GPIO_H
-#define KS8695_GPIO_H
-
-#define KS8695_GPIO_OFFSET      (0xF0000 + 0xE600)
-#define KS8695_GPIO_VA          (KS8695_IO_VA + KS8695_GPIO_OFFSET)
-#define KS8695_GPIO_PA          (KS8695_IO_PA + KS8695_GPIO_OFFSET)
-
-
-#define KS8695_IOPM             (0x00)          /* I/O Port Mode Register */
-#define KS8695_IOPC             (0x04)          /* I/O Port Control Register */
-#define KS8695_IOPD             (0x08)          /* I/O Port Data Register */
-
-
-/* Port Mode Register */
-#define IOPM_(x)                (1 << (x))      /* Mode for GPIO Pin x */
-
-/* Port Control Register */
-#define IOPC_IOTIM1EN           (1 << 17)       /* GPIO Pin for Timer1 Enable */
-#define IOPC_IOTIM0EN           (1 << 16)       /* GPIO Pin for Timer0 Enable */
-#define IOPC_IOEINT3EN          (1 << 15)       /* GPIO Pin for External/Soft Interrupt 3 Enable */
-#define IOPC_IOEINT3TM          (7 << 12)       /* GPIO Pin for External/Soft Interrupt 3 Trigger Mode */
-#define IOPC_IOEINT3_MODE(x)    ((x) << 12)
-#define IOPC_IOEINT2EN          (1 << 11)       /* GPIO Pin for External/Soft Interrupt 2 Enable */
-#define IOPC_IOEINT2TM          (7 << 8)        /* GPIO Pin for External/Soft Interrupt 2 Trigger Mode */
-#define IOPC_IOEINT2_MODE(x)    ((x) << 8)
-#define IOPC_IOEINT1EN          (1 << 7)        /* GPIO Pin for External/Soft Interrupt 1 Enable */
-#define IOPC_IOEINT1TM          (7 << 4)        /* GPIO Pin for External/Soft Interrupt 1 Trigger Mode */
-#define IOPC_IOEINT1_MODE(x)    ((x) << 4)
-#define IOPC_IOEINT0EN          (1 << 3)        /* GPIO Pin for External/Soft Interrupt 0 Enable */
-#define IOPC_IOEINT0TM          (7 << 0)        /* GPIO Pin for External/Soft Interrupt 0 Trigger Mode */
-#define IOPC_IOEINT0_MODE(x)    ((x) << 0)
-
- /* Trigger Modes */
-#define IOPC_TM_LOW             (0)             /* Level Detection (Active Low) */
-#define IOPC_TM_HIGH            (1)             /* Level Detection (Active High) */
-#define IOPC_TM_RISING          (2)             /* Rising Edge Detection */
-#define IOPC_TM_FALLING         (4)             /* Falling Edge Detection */
-#define IOPC_TM_EDGE            (6)             /* Both Edge Detection */
-
-/* Port Data Register */
-#define IOPD_(x)                (1 << (x))      /* Signal Level of GPIO Pin x */
-
-#endif
diff --git a/include/asm-arm/arch-ks8695/regs-hpna.h b/include/asm-arm/arch-ks8695/regs-hpna.h
deleted file mode 100644
index 14091cdec103..000000000000
--- a/include/asm-arm/arch-ks8695/regs-hpna.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * include/asm-arm/arch-ks8695/regs-wan.h
- *
- * Copyright (C) 2006 Andrew Victor
- *
- * KS8695 - HPNA Registers and bit definitions.
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef KS8695_HPNA_H
-#define KS8695_HPNA_H
-
-#define KS8695_HPNA_OFFSET      (0xF0000 + 0xA000)
-#define KS8695_HPNA_VA          (KS8695_IO_VA + KS8695_HPNA_OFFSET)
-#define KS8695_HPNA_PA          (KS8695_IO_PA + KS8695_HPNA_OFFSET)
-
-
-/*
- * HPNA registers
- */
-
-#endif
diff --git a/include/asm-arm/arch-ks8695/regs-irq.h b/include/asm-arm/arch-ks8695/regs-irq.h
deleted file mode 100644
index 70b193f6b756..000000000000
--- a/include/asm-arm/arch-ks8695/regs-irq.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * include/asm-arm/arch-ks8695/regs-irq.h
- *
- * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
- * Copyright (C) 2006 Simtec Electronics
- *
- * KS8695 - IRQ registers and bit definitions
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef KS8695_IRQ_H
-#define KS8695_IRQ_H
-
-#define KS8695_IRQ_OFFSET       (0xF0000 + 0xE200)
-#define KS8695_IRQ_VA           (KS8695_IO_VA + KS8695_IRQ_OFFSET)
-#define KS8695_IRQ_PA           (KS8695_IO_PA + KS8695_IRQ_OFFSET)
-
-
-/*
- * Interrupt Controller registers
- */
-#define KS8695_INTMC            (0x00)          /* Mode Control Register */
-#define KS8695_INTEN            (0x04)          /* Interrupt Enable Register */
-#define KS8695_INTST            (0x08)          /* Interrupt Status Register */
-#define KS8695_INTPW            (0x0c)          /* Interrupt Priority (WAN MAC) */
-#define KS8695_INTPH            (0x10)          /* Interrupt Priority (HPNA) [KS8695 only] */
-#define KS8695_INTPL            (0x14)          /* Interrupt Priority (LAN MAC) */
-#define KS8695_INTPT            (0x18)          /* Interrupt Priority (Timer) */
-#define KS8695_INTPU            (0x1c)          /* Interrupt Priority (UART) */
-#define KS8695_INTPE            (0x20)          /* Interrupt Priority (External Interrupt) */
-#define KS8695_INTPC            (0x24)          /* Interrupt Priority (Communications Channel) */
-#define KS8695_INTPBE           (0x28)          /* Interrupt Priority (Bus Error Response) */
-#define KS8695_INTMS            (0x2c)          /* Interrupt Mask Status Register */
-#define KS8695_INTHPF           (0x30)          /* Interrupt Pending Highest Priority (FIQ) */
-#define KS8695_INTHPI           (0x34)          /* Interrupt Pending Highest Priority (IRQ) */
-
-
-#endif
diff --git a/include/asm-arm/arch-ks8695/regs-lan.h b/include/asm-arm/arch-ks8695/regs-lan.h
deleted file mode 100644
index a63bd61c64ed..000000000000
--- a/include/asm-arm/arch-ks8695/regs-lan.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * include/asm-arm/arch-ks8695/regs-lan.h
- *
- * Copyright (C) 2006 Andrew Victor
- *
- * KS8695 - LAN Registers and bit definitions.
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef KS8695_LAN_H
-#define KS8695_LAN_H
-
-#define KS8695_LAN_OFFSET       (0xF0000 + 0x8000)
-#define KS8695_LAN_VA           (KS8695_IO_VA + KS8695_LAN_OFFSET)
-#define KS8695_LAN_PA           (KS8695_IO_PA + KS8695_LAN_OFFSET)
-
-
-/*
- * LAN registers
- */
-#define KS8695_LMDTXC           (0x00)          /* DMA Transmit Control */
-#define KS8695_LMDRXC           (0x04)          /* DMA Receive Control */
-#define KS8695_LMDTSC           (0x08)          /* DMA Transmit Start Command */
-#define KS8695_LMDRSC           (0x0c)          /* DMA Receive Start Command */
-#define KS8695_LTDLB            (0x10)          /* Transmit Descriptor List Base Address */
-#define KS8695_LRDLB            (0x14)          /* Receive Descriptor List Base Address */
-#define KS8695_LMAL             (0x18)          /* MAC Station Address Low */
-#define KS8695_LMAH             (0x1c)          /* MAC Station Address High */
-#define KS8695_LMAAL_(n)        (0x80 + ((n)*8))        /* MAC Additional Station Address (0..15) Low */
-#define KS8695_LMAAH_(n)        (0x84 + ((n)*8))        /* MAC Additional Station Address (0..15) High */
-
-
-/* DMA Transmit Control Register */
-#define LMDTXC_LMTRST           (1    << 31)    /* Soft Reset */
-#define LMDTXC_LMTBS            (0x3f << 24)    /* Transmit Burst Size */
-#define LMDTXC_LMTUCG           (1    << 18)    /* Transmit UDP Checksum Generate */
-#define LMDTXC_LMTTCG           (1    << 17)    /* Transmit TCP Checksum Generate */
-#define LMDTXC_LMTICG           (1    << 16)    /* Transmit IP Checksum Generate */
-#define LMDTXC_LMTFCE           (1    <<  9)    /* Transmit Flow Control Enable */
-#define LMDTXC_LMTLB            (1    <<  8)    /* Loopback mode */
-#define LMDTXC_LMTEP            (1    <<  2)    /* Transmit Enable Padding */
-#define LMDTXC_LMTAC            (1    <<  1)    /* Transmit Add CRC */
-#define LMDTXC_LMTE             (1    <<  0)    /* TX Enable */
-
-/* DMA Receive Control Register */
-#define LMDRXC_LMRBS            (0x3f << 24)    /* Receive Burst Size */
-#define LMDRXC_LMRUCC           (1    << 18)    /* Receive UDP Checksum check */
-#define LMDRXC_LMRTCG           (1    << 17)    /* Receive TCP Checksum check */
-#define LMDRXC_LMRICG           (1    << 16)    /* Receive IP Checksum check */
-#define LMDRXC_LMRFCE           (1    <<  9)    /* Receive Flow Control Enable */
-#define LMDRXC_LMRB             (1    <<  6)    /* Receive Broadcast */
-#define LMDRXC_LMRM             (1    <<  5)    /* Receive Multicast */
-#define LMDRXC_LMRU             (1    <<  4)    /* Receive Unicast */
-#define LMDRXC_LMRERR           (1    <<  3)    /* Receive Error Frame */
-#define LMDRXC_LMRA             (1    <<  2)    /* Receive All */
-#define LMDRXC_LMRE             (1    <<  1)    /* RX Enable */
-
-/* Additional Station Address High */
-#define LMAAH_E                 (1    << 31)    /* Address Enabled */
-
-
-#endif
diff --git a/include/asm-arm/arch-ks8695/regs-mem.h b/include/asm-arm/arch-ks8695/regs-mem.h
deleted file mode 100644
index 76b38e0862e6..000000000000
--- a/include/asm-arm/arch-ks8695/regs-mem.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * include/asm-arm/arch-ks8695/regs-mem.h
- *
- * Copyright (C) 2006 Andrew Victor
- *
- * KS8695 - Memory Controller registers and bit definitions
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef KS8695_MEM_H
-#define KS8695_MEM_H
-
-#define KS8695_MEM_OFFSET       (0xF0000 + 0x4000)
-#define KS8695_MEM_VA           (KS8695_IO_VA + KS8695_MEM_OFFSET)
-#define KS8695_MEM_PA           (KS8695_IO_PA + KS8695_MEM_OFFSET)
-
-
-/*
- * Memory Controller Registers
- */
-#define KS8695_EXTACON0         (0x00)          /* External I/O 0 Access Control */
-#define KS8695_EXTACON1         (0x04)          /* External I/O 1 Access Control */
-#define KS8695_EXTACON2         (0x08)          /* External I/O 2 Access Control */
-#define KS8695_ROMCON0          (0x10)          /* ROM/SRAM/Flash 1 Control Register */
-#define KS8695_ROMCON1          (0x14)          /* ROM/SRAM/Flash 2 Control Register */
-#define KS8695_ERGCON           (0x20)          /* External I/O and ROM/SRAM/Flash General Register */
-#define KS8695_SDCON0           (0x30)          /* SDRAM Control Register 0 */
-#define KS8695_SDCON1           (0x34)          /* SDRAM Control Register 1 */
-#define KS8695_SDGCON           (0x38)          /* SDRAM General Control */
-#define KS8695_SDBCON           (0x3c)          /* SDRAM Buffer Control */
-#define KS8695_REFTIM           (0x40)          /* SDRAM Refresh Timer */
-
-
-/* External I/O Access Control Registers */
-#define EXTACON_EBNPTR          (0x3ff << 22)           /* Last Address Pointer */
-#define EXTACON_EBBPTR          (0x3ff << 12)           /* Base Pointer */
-#define EXTACON_EBTACT          (7     <<  9)           /* Write Enable/Output Enable Active Time */
-#define EXTACON_EBTCOH          (7     <<  6)           /* Chip Select Hold Time */
-#define EXTACON_EBTACS          (7     <<  3)           /* Address Setup Time before ECSN */
-#define EXTACON_EBTCOS          (7     <<  0)           /* Chip Select Time before OEN */
-
-/* ROM/SRAM/Flash Control Register */
-#define ROMCON_RBNPTR           (0x3ff << 22)           /* Next Pointer */
-#define ROMCON_RBBPTR           (0x3ff << 12)           /* Base Pointer */
-#define ROMCON_RBTACC           (7     <<  4)           /* Access Cycle Time */
-#define ROMCON_RBTPA            (3     <<  2)           /* Page Address Access Time */
-#define ROMCON_PMC              (3     <<  0)           /* Page Mode Configuration */
-#define         PMC_NORMAL              (0 << 0)
-#define         PMC_4WORD               (1 << 0)
-#define         PMC_8WORD               (2 << 0)
-#define         PMC_16WORD              (3 << 0)
-
-/* External I/O and ROM/SRAM/Flash General Register */
-#define ERGCON_TMULT            (3 << 28)               /* Time Multiplier */
-#define ERGCON_DSX2             (3 << 20)               /* Data Width (External I/O Bank 2) */
-#define ERGCON_DSX1             (3 << 18)               /* Data Width (External I/O Bank 1) */
-#define ERGCON_DSX0             (3 << 16)               /* Data Width (External I/O Bank 0) */
-#define ERGCON_DSR1             (3 <<  2)               /* Data Width (ROM/SRAM/Flash Bank 1) */
-#define ERGCON_DSR0             (3 <<  0)               /* Data Width (ROM/SRAM/Flash Bank 0) */
-
-/* SDRAM Control Register */
-#define SDCON_DBNPTR            (0x3ff << 22)           /* Last Address Pointer */
-#define SDCON_DBBPTR            (0x3ff << 12)           /* Base Pointer */
-#define SDCON_DBCAB             (3     <<  8)           /* Column Address Bits */
-#define SDCON_DBBNUM            (1     <<  3)           /* Number of Banks */
-#define SDCON_DBDBW             (3     <<  1)           /* Data Bus Width */
-
-/* SDRAM General Control Register */
-#define SDGCON_SDTRC            (3 << 2)                /* RAS to CAS latency */
-#define SDGCON_SDCAS            (3 << 0)                /* CAS latency */
-
-/* SDRAM Buffer Control Register */
-#define SDBCON_SDESTA           (1 << 31)               /* SDRAM Engine Status */
-#define SDBCON_RBUFBDIS         (1 << 24)               /* Read Buffer Burst Enable */
-#define SDBCON_WFIFOEN          (1 << 23)               /* Write FIFO Enable */
-#define SDBCON_RBUFEN           (1 << 22)               /* Read Buffer Enable */
-#define SDBCON_FLUSHWFIFO       (1 << 21)               /* Flush Write FIFO */
-#define SDBCON_RBUFINV          (1 << 20)               /* Read Buffer Invalidate */
-#define SDBCON_SDINI            (3 << 16)               /* SDRAM Initialization Control */
-#define SDBCON_SDMODE           (0x3fff << 0)           /* SDRAM Mode Register Value Program */
-
-/* SDRAM Refresh Timer Register */
-#define REFTIM_REFTIM           (0xffff << 0)           /* Refresh Timer Value */
-
-
-#endif
diff --git a/include/asm-arm/arch-ks8695/regs-misc.h b/include/asm-arm/arch-ks8695/regs-misc.h
deleted file mode 100644
index 632ca6601a94..000000000000
--- a/include/asm-arm/arch-ks8695/regs-misc.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * include/asm-arm/arch-ks8695/regs-misc.h
- *
- * Copyright (C) 2006 Andrew Victor
- *
- * KS8695 - Miscellaneous Registers
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef KS8695_MISC_H
-#define KS8695_MISC_H
-
-#define KS8695_MISC_OFFSET      (0xF0000 + 0xEA00)
-#define KS8695_MISC_VA          (KS8695_IO_VA + KS8695_MISC_OFFSET)
-#define KS8695_MISC_PA          (KS8695_IO_PA + KS8695_MISC_OFFSET)
-
-
-/*
- * Miscellaneous registers
- */
-#define KS8695_DID              (0x00)          /* Device ID */
-#define KS8695_RID              (0x04)          /* Revision ID */
-#define KS8695_HMC              (0x08)          /* HPNA Miscellaneous Control [KS8695 only] */
-#define KS8695_WMC              (0x0c)          /* WAN Miscellaneous Control */
-#define KS8695_WPPM             (0x10)          /* WAN PHY Power Management */
-#define KS8695_PPS              (0x1c)          /* PHY PowerSave */
-
-/* Device ID Register */
-#define DID_ID                  (0xffff << 0)   /* Device ID */
-
-/* Revision ID Register */
-#define RID_SUBID               (0xf << 4)      /* Sub-Device ID */
-#define RID_REVISION            (0xf << 0)      /* Revision ID */
-
-/* HPNA Miscellaneous Control Register */
-#define HMC_HSS                 (1 << 1)        /* Speed */
-#define HMC_HDS                 (1 << 0)        /* Duplex */
-
-/* WAN Miscellaneous Control Register */
-#define WMC_WANC                (1 << 30)       /* Auto-negotiation complete */
-#define WMC_WANR                (1 << 29)       /* Auto-negotiation restart */
-#define WMC_WANAP               (1 << 28)       /* Advertise Pause */
-#define WMC_WANA100F            (1 << 27)       /* Advertise 100 FDX */
-#define WMC_WANA100H            (1 << 26)       /* Advertise 100 HDX */
-#define WMC_WANA10F             (1 << 25)       /* Advertise 10 FDX */
-#define WMC_WANA10H             (1 << 24)       /* Advertise 10 HDX */
-#define WMC_WLS                 (1 << 23)       /* Link status */
-#define WMC_WDS                 (1 << 22)       /* Duplex status */
-#define WMC_WSS                 (1 << 21)       /* Speed status */
-#define WMC_WLPP                (1 << 20)       /* Link Partner Pause */
-#define WMC_WLP100F             (1 << 19)       /* Link Partner 100 FDX */
-#define WMC_WLP100H             (1 << 18)       /* Link Partner 100 HDX */
-#define WMC_WLP10F              (1 << 17)       /* Link Partner 10 FDX */
-#define WMC_WLP10H              (1 << 16)       /* Link Partner 10 HDX */
-#define WMC_WAND                (1 << 15)       /* Auto-negotiation disable */
-#define WMC_WANF100             (1 << 14)       /* Force 100 */
-#define WMC_WANFF               (1 << 13)       /* Force FDX */
-#define WMC_WLED1S              (7 <<  4)       /* LED1 Select */
-#define         WLED1S_SPEED            (0 << 4)
-#define         WLED1S_LINK             (1 << 4)
-#define         WLED1S_DUPLEX           (2 << 4)
-#define         WLED1S_COLLISION        (3 << 4)
-#define         WLED1S_ACTIVITY         (4 << 4)
-#define         WLED1S_FDX_COLLISION    (5 << 4)
-#define         WLED1S_LINK_ACTIVITY    (6 << 4)
-#define WMC_WLED0S              (7 << 0)        /* LED0 Select */
-#define         WLED0S_SPEED            (0 << 0)
-#define         WLED0S_LINK             (1 << 0)
-#define         WLED0S_DUPLEX           (2 << 0)
-#define         WLED0S_COLLISION        (3 << 0)
-#define         WLED0S_ACTIVITY         (4 << 0)
-#define         WLED0S_FDX_COLLISION    (5 << 0)
-#define         WLED0S_LINK_ACTIVITY    (6 << 0)
-
-/* WAN PHY Power Management Register */
-#define WPPM_WLPBK              (1 << 14)       /* Local Loopback */
-#define WPPM_WRLPKB             (1 << 13)       /* Remove Loopback */
-#define WPPM_WPI                (1 << 12)       /* PHY isolate */
-#define WPPM_WFL                (1 << 10)       /* Force link */
-#define WPPM_MDIXS              (1 << 9)        /* MDIX Status */
-#define WPPM_FEF                (1 << 8)        /* Far End Fault */
-#define WPPM_AMDIXP             (1 << 7)        /* Auto MDIX Parameter */
-#define WPPM_TXDIS              (1 << 6)        /* Disable transmitter */
-#define WPPM_DFEF               (1 << 5)        /* Disable Far End Fault */
-#define WPPM_PD                 (1 << 4)        /* Power Down */
-#define WPPM_DMDX               (1 << 3)        /* Disable Auto MDI/MDIX */
-#define WPPM_FMDX               (1 << 2)        /* Force MDIX */
-#define WPPM_LPBK               (1 << 1)        /* MAX Loopback */
-
-/* PHY Power Save Register */
-#define PPS_PPSM                (1 << 0)        /* PHY Power Save Mode */
-
-
-#endif
diff --git a/include/asm-arm/arch-ks8695/regs-pci.h b/include/asm-arm/arch-ks8695/regs-pci.h
deleted file mode 100644
index 286d6d488df8..000000000000
--- a/include/asm-arm/arch-ks8695/regs-pci.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * include/asm-arm/arch-ks8695/regs-pci.h
- *
- * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
- * Copyright (C) 2006 Simtec Electronics
- *
- * KS8695 - PCI bridge registers and bit definitions.
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#define KS8695_PCI_OFFSET       (0xF0000 + 0x2000)
-#define KS8695_PCI_VA           (KS8695_IO_VA + KS8695_PCI_OFFSET)
-#define KS8695_PCI_PA           (KS8695_IO_PA + KS8695_PCI_OFFSET)
-
-
-#define KS8695_CRCFID           (0x000)         /* Configuration: Identification */
-#define KS8695_CRCFCS           (0x004)         /* Configuration: Command and Status */
-#define KS8695_CRCFRV           (0x008)         /* Configuration: Revision */
-#define KS8695_CRCFLT           (0x00C)         /* Configuration: Latency Timer */
-#define KS8695_CRCBMA           (0x010)         /* Configuration: Base Memory Address */
-#define KS8695_CRCSID           (0x02C)         /* Configuration: Subsystem ID */
-#define KS8695_CRCFIT           (0x03C)         /* Configuration: Interrupt */
-#define KS8695_PBCA             (0x100)         /* Bridge Configuration Address */
-#define KS8695_PBCD             (0x104)         /* Bridge Configuration Data */
-#define KS8695_PBM              (0x200)         /* Bridge Mode */
-#define KS8695_PBCS             (0x204)         /* Bridge Control and Status */
-#define KS8695_PMBA             (0x208)         /* Bridge Memory Base Address */
-#define KS8695_PMBAC            (0x20C)         /* Bridge Memory Base Address Control */
-#define KS8695_PMBAM            (0x210)         /* Bridge Memory Base Address Mask */
-#define KS8695_PMBAT            (0x214)         /* Bridge Memory Base Address Translation */
-#define KS8695_PIOBA            (0x218)         /* Bridge I/O Base Address */
-#define KS8695_PIOBAC           (0x21C)         /* Bridge I/O Base Address Control */
-#define KS8695_PIOBAM           (0x220)         /* Bridge I/O Base Address Mask */
-#define KS8695_PIOBAT           (0x224)         /* Bridge I/O Base Address Translation */
-
-
-/* Configuration: Identification */
-
-/* Configuration: Command and Status */
-
-/* Configuration: Revision */
-
-
-
-#define CFRV_GUEST              (1 << 23)
-
-#define PBCA_TYPE1              (1)
-#define PBCA_ENABLE             (1 << 31)
-
-
diff --git a/include/asm-arm/arch-ks8695/regs-switch.h b/include/asm-arm/arch-ks8695/regs-switch.h
deleted file mode 100644
index 5f37be3f2f60..000000000000
--- a/include/asm-arm/arch-ks8695/regs-switch.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * include/asm-arm/arch-ks8695/regs-switch.h
- *
- * Copyright (C) 2006 Andrew Victor
- *
- * KS8695 - Switch Registers and bit definitions.
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef KS8695_SWITCH_H
-#define KS8695_SWITCH_H
-
-#define KS8695_SWITCH_OFFSET    (0xF0000 + 0xe800)
-#define KS8695_SWITCH_VA        (KS8695_IO_VA + KS8695_SWITCH_OFFSET)
-#define KS8695_SWITCH_PA        (KS8695_IO_PA + KS8695_SWITCH_OFFSET)
-
-
-/*
- * Switch registers
- */
-#define KS8695_SEC0             (0x00)          /* Switch Engine Control 0 */
-#define KS8695_SEC1             (0x04)          /* Switch Engine Control 1 */
-#define KS8695_SEC2             (0x08)          /* Switch Engine Control 2 */
-
-#define KS8695_P(x)_C(z)        (0xc0 + (((x)-1)*3 + ((z)-1))*4)        /* Port Configuration Registers */
-
-#define KS8695_SEP12AN          (0x48)          /* Port 1 & 2 Auto-Negotiation */
-#define KS8695_SEP34AN          (0x4c)          /* Port 3 & 4 Auto-Negotiation */
-#define KS8695_SEIAC            (0x50)          /* Indirect Access Control */
-#define KS8695_SEIADH2          (0x54)          /* Indirect Access Data High 2 */
-#define KS8695_SEIADH1          (0x58)          /* Indirect Access Data High 1 */
-#define KS8695_SEIADL           (0x5c)          /* Indirect Access Data Low */
-#define KS8695_SEAFC            (0x60)          /* Advance Feature Control */
-#define KS8695_SEDSCPH          (0x64)          /* TOS Priority High */
-#define KS8695_SEDSCPL          (0x68)          /* TOS Priority Low */
-#define KS8695_SEMAH            (0x6c)          /* Switch Engine MAC Address High */
-#define KS8695_SEMAL            (0x70)          /* Switch Engine MAC Address Low */
-#define KS8695_LPPM12           (0x74)          /* Port 1 & 2 PHY Power Management */
-#define KS8695_LPPM34           (0x78)          /* Port 3 & 4 PHY Power Management */
-
-
-/* Switch Engine Control 0 */
-#define SEC0_LLED1S             (7 << 25)       /* LED1 Select */
-#define         LLED1S_SPEED            (0 << 25)
-#define         LLED1S_LINK             (1 << 25)
-#define         LLED1S_DUPLEX           (2 << 25)
-#define         LLED1S_COLLISION        (3 << 25)
-#define         LLED1S_ACTIVITY         (4 << 25)
-#define         LLED1S_FDX_COLLISION    (5 << 25)
-#define         LLED1S_LINK_ACTIVITY    (6 << 25)
-#define SEC0_LLED0S             (7 << 22)       /* LED0 Select */
-#define         LLED0S_SPEED            (0 << 22)
-#define         LLED0S_LINK             (1 << 22)
-#define         LLED0S_DUPLEX           (2 << 22)
-#define         LLED0S_COLLISION        (3 << 22)
-#define         LLED0S_ACTIVITY         (4 << 22)
-#define         LLED0S_FDX_COLLISION    (5 << 22)
-#define         LLED0S_LINK_ACTIVITY    (6 << 22)
-#define SEC0_ENABLE             (1 << 0)        /* Enable Switch */
-
-
-
-#endif
diff --git a/include/asm-arm/arch-ks8695/regs-sys.h b/include/asm-arm/arch-ks8695/regs-sys.h
deleted file mode 100644
index f3179815b8ee..000000000000
--- a/include/asm-arm/arch-ks8695/regs-sys.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * include/asm-arm/arch-ks8695/regs-sys.h
- *
- * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
- * Copyright (C) 2006 Simtec Electronics
- *
- * KS8695 - System control registers and bit definitions
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef KS8695_SYS_H
-#define KS8695_SYS_H
-
-#define KS8695_SYS_OFFSET       (0xF0000 + 0x0000)
-#define KS8695_SYS_VA           (KS8695_IO_VA + KS8695_SYS_OFFSET)
-#define KS8695_SYS_PA           (KS8695_IO_PA + KS8695_SYS_OFFSET)
-
-
-#define KS8695_SYSCFG           (0x00)          /* System Configuration Register */
-#define KS8695_CLKCON           (0x04)          /* System Clock and Bus Control Register */
-
-
-/* System Configuration Register */
-#define SYSCFG_SPRBP            (0x3ff << 16)   /* Register Bank Base Pointer */
-
-/* System Clock and Bus Control Register */
-#define CLKCON_SFMODE           (1 << 8)        /* System Fast Mode for Simulation */
-#define CLKCON_SCDC             (7 << 0)        /* System Clock Divider Select */
-
-
-#endif
diff --git a/include/asm-arm/arch-ks8695/regs-timer.h b/include/asm-arm/arch-ks8695/regs-timer.h
deleted file mode 100644
index 0a9f7f99ec52..000000000000
--- a/include/asm-arm/arch-ks8695/regs-timer.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * include/asm-arm/arch-ks8695/regs-timer.h
- *
- * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
- * Copyright (C) 2006 Simtec Electronics
- *
- * KS8695 - Timer registers and bit definitions.
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef KS8695_TIMER_H
-#define KS8695_TIMER_H
-
-#define KS8695_TMR_OFFSET       (0xF0000 + 0xE400)
-#define KS8695_TMR_VA           (KS8695_IO_VA + KS8695_TMR_OFFSET)
-#define KS8695_TMR_PA           (KS8695_IO_PA + KS8695_TMR_OFFSET)
-
-
-/*
- * Timer registers
- */
-#define KS8695_TMCON            (0x00)          /* Timer Control Register */
-#define KS8695_T1TC             (0x04)          /* Timer 1 Timeout Count Register */
-#define KS8695_T0TC             (0x08)          /* Timer 0 Timeout Count Register */
-#define KS8695_T1PD             (0x0C)          /* Timer 1 Pulse Count Register */
-#define KS8695_T0PD             (0x10)          /* Timer 0 Pulse Count Register */
-
-
-/* Timer Control Register */
-#define TMCON_T1EN              (1 << 1)        /* Timer 1 Enable */
-#define TMCON_T0EN              (1 << 0)        /* Timer 0 Enable */
-
-/* Timer0 Timeout Counter Register */
-#define T0TC_WATCHDOG           (0xff)          /* Enable watchdog mode */
-
-
-#endif
diff --git a/include/asm-arm/arch-ks8695/regs-uart.h b/include/asm-arm/arch-ks8695/regs-uart.h
deleted file mode 100644
index a27cb20502a3..000000000000
--- a/include/asm-arm/arch-ks8695/regs-uart.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * linux/include/asm-arm/arch-ks8695/regs-uart.h
- *
- * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
- * Copyright (C) 2006 Simtec Electronics
- *
- * KS8695 - UART register and bit definitions.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef KS8695_UART_H
-#define KS8695_UART_H
-
-#define KS8695_UART_OFFSET      (0xF0000 + 0xE000)
-#define KS8695_UART_VA          (KS8695_IO_VA + KS8695_UART_OFFSET)
-#define KS8695_UART_PA          (KS8695_IO_PA + KS8695_UART_OFFSET)
-
-
-/*
- * UART registers
- */
-#define KS8695_URRB     (0x00)          /* Receive Buffer Register */
-#define KS8695_URTH     (0x04)          /* Transmit Holding Register */
-#define KS8695_URFC     (0x08)          /* FIFO Control Register */
-#define KS8695_URLC     (0x0C)          /* Line Control Register */
-#define KS8695_URMC     (0x10)          /* Modem Control Register */
-#define KS8695_URLS     (0x14)          /* Line Status Register */
-#define KS8695_URMS     (0x18)          /* Modem Status Register */
-#define KS8695_URBD     (0x1C)          /* Baud Rate Divisor Register */
-#define KS8695_USR      (0x20)          /* Status Register */
-
-
-/* FIFO Control Register */
-#define URFC_URFRT      (3 << 6)        /* Receive FIFO Trigger Level */
-#define         URFC_URFRT_1    (0 << 6)
-#define         URFC_URFRT_4    (1 << 6)
-#define         URFC_URFRT_8    (2 << 6)
-#define         URFC_URFRT_14   (3 << 6)
-#define URFC_URTFR      (1 << 2)        /* Transmit FIFO Reset */
-#define URFC_URRFR      (1 << 1)        /* Receive FIFO Reset */
-#define URFC_URFE       (1 << 0)        /* FIFO Enable */
-
-/* Line Control Register */
-#define URLC_URSBC      (1 << 6)        /* Set Break Condition */
-#define URLC_PARITY     (7 << 3)        /* Parity */
-#define         URPE_NONE       (0 << 3)
-#define         URPE_ODD        (1 << 3)
-#define         URPE_EVEN       (3 << 3)
-#define         URPE_MARK       (5 << 3)
-#define         URPE_SPACE      (7 << 3)
-#define URLC_URSB       (1 << 2)        /* Stop Bits */
-#define URLC_URCL       (3 << 0)        /* Character Length */
-#define         URCL_5          (0 << 0)
-#define         URCL_6          (1 << 0)
-#define         URCL_7          (2 << 0)
-#define         URCL_8          (3 << 0)
-
-/* Modem Control Register */
-#define URMC_URLB       (1 << 4)        /* Loop-back mode */
-#define URMC_UROUT2     (1 << 3)        /* OUT2 signal */
-#define URMC_UROUT1     (1 << 2)        /* OUT1 signal */
-#define URMC_URRTS      (1 << 1)        /* Request to Send */
-#define URMC_URDTR      (1 << 0)        /* Data Terminal Ready */
-
-/* Line Status Register */
-#define URLS_URRFE      (1 << 7)        /* Receive FIFO Error */
-#define URLS_URTE       (1 << 6)        /* Transmit Empty */
-#define URLS_URTHRE     (1 << 5)        /* Transmit Holding Register Empty */
-#define URLS_URBI       (1 << 4)        /* Break Interrupt */
-#define URLS_URFE       (1 << 3)        /* Framing Error */
-#define URLS_URPE       (1 << 2)        /* Parity Error */
-#define URLS_URROE      (1 << 1)        /* Receive Overrun Error */
-#define URLS_URDR       (1 << 0)        /* Receive Data Ready */
-
-/* Modem Status Register */
-#define URMS_URDCD      (1 << 7)        /* Data Carrier Detect */
-#define URMS_URRI       (1 << 6)        /* Ring Indicator */
-#define URMS_URDSR      (1 << 5)        /* Data Set Ready */
-#define URMS_URCTS      (1 << 4)        /* Clear to Send */
-#define URMS_URDDCD     (1 << 3)        /* Delta Data Carrier Detect */
-#define URMS_URTERI     (1 << 2)        /* Trailing Edge Ring Indicator */
-#define URMS_URDDST     (1 << 1)        /* Delta Data Set Ready */
-#define URMS_URDCTS     (1 << 0)        /* Delta Clear to Send */
-
-/* Status Register */
-#define USR_UTI         (1 << 0)        /* Timeout Indication */
-
-
-#endif
diff --git a/include/asm-arm/arch-ks8695/regs-wan.h b/include/asm-arm/arch-ks8695/regs-wan.h
deleted file mode 100644
index 52e35b0d65e4..000000000000
--- a/include/asm-arm/arch-ks8695/regs-wan.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * include/asm-arm/arch-ks8695/regs-wan.h
- *
- * Copyright (C) 2006 Andrew Victor
- *
- * KS8695 - WAN Registers and bit definitions.
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef KS8695_WAN_H
-#define KS8695_WAN_H
-
-#define KS8695_WAN_OFFSET       (0xF0000 + 0x6000)
-#define KS8695_WAN_VA           (KS8695_IO_VA + KS8695_WAN_OFFSET)
-#define KS8695_WAN_PA           (KS8695_IO_PA + KS8695_WAN_OFFSET)
-
-
-/*
- * WAN registers
- */
-#define KS8695_WMDTXC           (0x00)          /* DMA Transmit Control */
-#define KS8695_WMDRXC           (0x04)          /* DMA Receive Control */
-#define KS8695_WMDTSC           (0x08)          /* DMA Transmit Start Command */
-#define KS8695_WMDRSC           (0x0c)          /* DMA Receive Start Command */
-#define KS8695_WTDLB            (0x10)          /* Transmit Descriptor List Base Address */
-#define KS8695_WRDLB            (0x14)          /* Receive Descriptor List Base Address */
-#define KS8695_WMAL             (0x18)          /* MAC Station Address Low */
-#define KS8695_WMAH             (0x1c)          /* MAC Station Address High */
-#define KS8695_WMAAL_(n)        (0x80 + ((n)*8))        /* MAC Additional Station Address (0..15) Low */
-#define KS8695_WMAAH_(n)        (0x84 + ((n)*8))        /* MAC Additional Station Address (0..15) High */
-
-
-/* DMA Transmit Control Register */
-#define WMDTXC_WMTRST           (1    << 31)    /* Soft Reset */
-#define WMDTXC_WMTBS            (0x3f << 24)    /* Transmit Burst Size */
-#define WMDTXC_WMTUCG           (1    << 18)    /* Transmit UDP Checksum Generate */
-#define WMDTXC_WMTTCG           (1    << 17)    /* Transmit TCP Checksum Generate */
-#define WMDTXC_WMTICG           (1    << 16)    /* Transmit IP Checksum Generate */
-#define WMDTXC_WMTFCE           (1    <<  9)    /* Transmit Flow Control Enable */
-#define WMDTXC_WMTLB            (1    <<  8)    /* Loopback mode */
-#define WMDTXC_WMTEP            (1    <<  2)    /* Transmit Enable Padding */
-#define WMDTXC_WMTAC            (1    <<  1)    /* Transmit Add CRC */
-#define WMDTXC_WMTE             (1    <<  0)    /* TX Enable */
-
-/* DMA Receive Control Register */
-#define WMDRXC_WMRBS            (0x3f << 24)    /* Receive Burst Size */
-#define WMDRXC_WMRUCC           (1    << 18)    /* Receive UDP Checksum check */
-#define WMDRXC_WMRTCG           (1    << 17)    /* Receive TCP Checksum check */
-#define WMDRXC_WMRICG           (1    << 16)    /* Receive IP Checksum check */
-#define WMDRXC_WMRFCE           (1    <<  9)    /* Receive Flow Control Enable */
-#define WMDRXC_WMRB             (1    <<  6)    /* Receive Broadcast */
-#define WMDRXC_WMRM             (1    <<  5)    /* Receive Multicast */
-#define WMDRXC_WMRU             (1    <<  4)    /* Receive Unicast */
-#define WMDRXC_WMRERR           (1    <<  3)    /* Receive Error Frame */
-#define WMDRXC_WMRA             (1    <<  2)    /* Receive All */
-#define WMDRXC_WMRE             (1    <<  0)    /* RX Enable */
-
-/* Additional Station Address High */
-#define WMAAH_E                 (1    << 31)    /* Address Enabled */
-
-
-#endif
diff --git a/include/asm-arm/arch-ks8695/system.h b/include/asm-arm/arch-ks8695/system.h
deleted file mode 100644
index 3bc28106d937..000000000000
--- a/include/asm-arm/arch-ks8695/system.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * include/asm-arm/arch-s3c2410/system.h
- *
- * Copyright (C) 2006 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * KS8695 - System function defines and includes
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-#include <asm/io.h>
-#include <asm/arch/regs-timer.h>
-
-static void arch_idle(void)
-{
-        /*
-         * This should do all the clock switching
-         * and wait for interrupt tricks,
-         */
-        cpu_do_idle();
-
-}
-
-static void arch_reset(char mode)
-{
-        unsigned int reg;
-
-        if (mode == 's')
-                cpu_reset(0);
-
-        /* disable timer0 */
-        reg = __raw_readl(KS8695_TMR_VA + KS8695_TMCON);
-        __raw_writel(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
-
-        /* enable watchdog mode */
-        __raw_writel((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC);
-
-        /* re-enable timer0 */
-        __raw_writel(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
-}
-
-#endif
diff --git a/include/asm-arm/arch-ks8695/timex.h b/include/asm-arm/arch-ks8695/timex.h
deleted file mode 100644
index 8320d528b903..000000000000
--- a/include/asm-arm/arch-ks8695/timex.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * include/asm-arm/arch-ks8695/timex.h
- *
- * Copyright (C) 2006 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * KS8695 - Time Parameters
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_TIMEX_H
-#define __ASM_ARCH_TIMEX_H
-
-/* timers are derived from MCLK, which is 25MHz */
-#define CLOCK_TICK_RATE 25000000
-
-#endif
diff --git a/include/asm-arm/arch-ks8695/uncompress.h b/include/asm-arm/arch-ks8695/uncompress.h
deleted file mode 100644
index 733a50855b5d..000000000000
--- a/include/asm-arm/arch-ks8695/uncompress.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * include/asm-arm/arch-ks8695/uncompress.h
- *
- * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
- * Copyright (C) 2006 Simtec Electronics
- *
- * KS8695 - Kernel uncompressor
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-
-#include <asm/io.h>
-#include <asm/arch/regs-uart.h>
-
-static void putc(char c)
-{
-        while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTHRE))
-                barrier();
-
-        __raw_writel(c, KS8695_UART_PA + KS8695_URTH);
-}
-
-static inline void flush(void)
-{
-        while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTE))
-                barrier();
-}
-
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
-
-#endif
diff --git a/include/asm-arm/arch-ks8695/vmalloc.h b/include/asm-arm/arch-ks8695/vmalloc.h
deleted file mode 100644
index d1d88e58117d..000000000000
--- a/include/asm-arm/arch-ks8695/vmalloc.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * include/asm-arm/arch-ks8695/vmalloc.h
- *
- * Copyright (C) 2006 Ben Dooks
- * Copyright (C) 2006 Simtec Electronics <linux@simtec.co.uk>
- *
- * KS8695 vmalloc definition
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H
-
-#define VMALLOC_END       (KS8695_IO_VA & PGDIR_MASK)
-
-#endif
diff --git a/include/asm-arm/arch-l7200/aux_reg.h b/include/asm-arm/arch-l7200/aux_reg.h
deleted file mode 100644
index 762cbc76c501..000000000000
--- a/include/asm-arm/arch-l7200/aux_reg.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * linux/include/asm-arm/arch-l7200/aux_reg.h
- *
- * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
- *
- * Changelog:
- *   08-02-2000 SJH     Created file
- */
-#ifndef _ASM_ARCH_AUXREG_H
-#define _ASM_ARCH_AUXREG_H
-
-#include <asm/arch/hardware.h>
-
-#define l7200aux_reg    *((volatile unsigned int *) (AUX_BASE))
-
-/*
- * Auxillary register values
- */
-#define AUX_CLEAR               0x00000000
-#define AUX_DIAG_LED_ON         0x00000002
-#define AUX_RTS_UART1           0x00000004
-#define AUX_DTR_UART1           0x00000008
-#define AUX_KBD_COLUMN_12_HIGH  0x00000010
-#define AUX_KBD_COLUMN_12_OFF   0x00000020
-#define AUX_KBD_COLUMN_13_HIGH  0x00000040
-#define AUX_KBD_COLUMN_13_OFF   0x00000080
-
-#endif
diff --git a/include/asm-arm/arch-l7200/debug-macro.S b/include/asm-arm/arch-l7200/debug-macro.S
deleted file mode 100644
index 846473318e8b..000000000000
--- a/include/asm-arm/arch-l7200/debug-macro.S
+++ /dev/null
@@ -1,40 +0,0 @@
-/* linux/include/asm-arm/arch-l7200/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-                .equ    io_virt, IO_BASE
-                .equ    io_phys, IO_START
-
-                .macro  addruart,rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx, #io_phys           @ physical base address
-                movne   \rx, #io_virt           @ virtual address
-                add     \rx, \rx, #0x00044000   @ UART1
-@               add     \rx, \rx, #0x00045000   @ UART2
-                .endm
-
-                .macro  senduart,rd,rx
-                str     \rd, [\rx, #0x0]        @ UARTDR
-                .endm
-
-                .macro  waituart,rd,rx
-1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
-                tst     \rd, #1 << 5            @ UARTFLGUTXFF - 1 when full
-                bne     1001b
-                .endm
-
-                .macro  busyuart,rd,rx
-1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
-                tst     \rd, #1 << 3            @ UARTFLGUBUSY - 1 when busy
-                bne     1001b
-                .endm
diff --git a/include/asm-arm/arch-l7200/dma.h b/include/asm-arm/arch-l7200/dma.h
deleted file mode 100644
index 4c7eca63f035..000000000000
--- a/include/asm-arm/arch-l7200/dma.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * linux/include/asm-arm/arch-l7200/dma.h
- *
- * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
- *
- * Changelog:
- *  08-29-2000  SJH     Created
- */
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-
-/* DMA is not yet implemented! It should be the same as acorn, copy over.. */
-
-/*
- * This is the maximum DMA address that can be DMAd to.
- * There should not be more than (0xd0000000 - 0xc0000000)
- * bytes of RAM.
- */
-#define MAX_DMA_ADDRESS         0xd0000000
-
-#define DMA_S0                  0
-
-#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-l7200/entry-macro.S b/include/asm-arm/arch-l7200/entry-macro.S
deleted file mode 100644
index d5e7294df1d5..000000000000
--- a/include/asm-arm/arch-l7200/entry-macro.S
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * include/asm-arm/arch-l7200/entry-macro.S
- *
- * Low-level IRQ helper macros for L7200-based platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <asm/arch/hardware.h>
-
-                .equ    irq_base_addr,  IO_BASE_2
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                mov     \irqstat, #irq_base_addr                @ Virt addr IRQ regs
-                add     \irqstat, \irqstat, #0x00001000         @ Status reg
-                ldr     \irqstat, [\irqstat, #0]                @ get interrupts
-                mov     \irqnr, #0
-1001:           tst     \irqstat, #1
-                addeq   \irqnr, \irqnr, #1
-                moveq   \irqstat, \irqstat, lsr #1
-                tsteq   \irqnr, #32
-                beq     1001b
-                teq     \irqnr, #32
-                .endm
-
diff --git a/include/asm-arm/arch-l7200/gp_timers.h b/include/asm-arm/arch-l7200/gp_timers.h
deleted file mode 100644
index 6f20962df248..000000000000
--- a/include/asm-arm/arch-l7200/gp_timers.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * linux/include/asm-arm/arch-l7200/gp_timers.h
- *
- * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
- *
- * Changelog:
- *   07-28-2000 SJH     Created file
- *   08-02-2000 SJH     Used structure for registers
- */
-#ifndef _ASM_ARCH_GPTIMERS_H
-#define _ASM_ARCH_GPTIMERS_H
-
-#include <asm/arch/hardware.h>
-
-/*
- * Layout of L7200 general purpose timer registers
- */
-struct GPT_Regs {
-        unsigned int TIMERLOAD;
-        unsigned int TIMERVALUE;
-        unsigned int TIMERCONTROL;
-        unsigned int TIMERCLEAR;
-};
-
-#define GPT_BASE                (IO_BASE_2 + 0x3000)
-#define l7200_timer1_regs       ((volatile struct GPT_Regs *) (GPT_BASE))
-#define l7200_timer2_regs       ((volatile struct GPT_Regs *) (GPT_BASE + 0x20))
-
-/*
- * General register values
- */
-#define GPT_PRESCALE_1          0x00000000
-#define GPT_PRESCALE_16         0x00000004
-#define GPT_PRESCALE_256        0x00000008
-#define GPT_MODE_FREERUN        0x00000000
-#define GPT_MODE_PERIODIC       0x00000040
-#define GPT_ENABLE              0x00000080
-#define GPT_BZTOG               0x00000100
-#define GPT_BZMOD               0x00000200
-#define GPT_LOAD_MASK           0x0000ffff
-
-#endif
diff --git a/include/asm-arm/arch-l7200/gpio.h b/include/asm-arm/arch-l7200/gpio.h
deleted file mode 100644
index 0b63e4239bdd..000000000000
--- a/include/asm-arm/arch-l7200/gpio.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/****************************************************************************/
-/*
- *      linux/include/asm-arm/arch-l7200/gpio.h
- *
- *      Registers and  helper functions for the L7200 Link-Up Systems
- *      GPIO.
- *
- *      (C) Copyright 2000, S A McConnell  (samcconn@cotw.com)
- *
- *  This file is subject to the terms and conditions of the GNU General Public
- *  License. See the file COPYING in the main directory of this archive for
- *  more details.
- */
-
-/****************************************************************************/
-
-#define GPIO_OFF   0x00005000  /* Offset from IO_START to the GPIO reg's. */
-
-/* IO_START and IO_BASE are defined in hardware.h */
-
-#define GPIO_START (IO_START_2 + GPIO_OFF) /* Physical addr of the GPIO reg. */
-#define GPIO_BASE  (IO_BASE_2  + GPIO_OFF) /* Virtual addr of the GPIO reg. */
-
-/* Offsets from the start of the GPIO for all the registers. */
-#define PADR_OFF     0x000
-#define PADDR_OFF    0x004
-#define PASBSR_OFF   0x008
-#define PAEENR_OFF   0x00c
-#define PAESNR_OFF   0x010
-#define PAESTR_OFF   0x014
-#define PAIMR_OFF    0x018
-#define PAINT_OFF    0x01c
-
-#define PBDR_OFF     0x020
-#define PBDDR_OFF    0x024
-#define PBSBSR_OFF   0x028
-#define PBIMR_OFF    0x038
-#define PBINT_OFF    0x03c
-
-#define PCDR_OFF     0x040
-#define PCDDR_OFF    0x044
-#define PCSBSR_OFF   0x048
-#define PCIMR_OFF    0x058
-#define PCINT_OFF    0x05c
-
-#define PDDR_OFF     0x060
-#define PDDDR_OFF    0x064
-#define PDSBSR_OFF   0x068
-#define PDEENR_OFF   0x06c
-#define PDESNR_OFF   0x070
-#define PDESTR_OFF   0x074
-#define PDIMR_OFF    0x078
-#define PDINT_OFF    0x07c
-
-#define PEDR_OFF     0x080
-#define PEDDR_OFF    0x084
-#define PESBSR_OFF   0x088
-#define PEEENR_OFF   0x08c
-#define PEESNR_OFF   0x090
-#define PEESTR_OFF   0x094
-#define PEIMR_OFF    0x098
-#define PEINT_OFF    0x09c
-
-/* Define the GPIO registers for use by device drivers and the kernel. */
-#define PADR   (*(volatile unsigned long *)(GPIO_BASE+PADR_OFF))
-#define PADDR  (*(volatile unsigned long *)(GPIO_BASE+PADDR_OFF))
-#define PASBSR (*(volatile unsigned long *)(GPIO_BASE+PASBSR_OFF))
-#define PAEENR (*(volatile unsigned long *)(GPIO_BASE+PAEENR_OFF))
-#define PAESNR (*(volatile unsigned long *)(GPIO_BASE+PAESNR_OFF))
-#define PAESTR (*(volatile unsigned long *)(GPIO_BASE+PAESTR_OFF))
-#define PAIMR  (*(volatile unsigned long *)(GPIO_BASE+PAIMR_OFF))
-#define PAINT  (*(volatile unsigned long *)(GPIO_BASE+PAINT_OFF))
-
-#define PBDR   (*(volatile unsigned long *)(GPIO_BASE+PBDR_OFF))
-#define PBDDR  (*(volatile unsigned long *)(GPIO_BASE+PBDDR_OFF))
-#define PBSBSR (*(volatile unsigned long *)(GPIO_BASE+PBSBSR_OFF))
-#define PBIMR  (*(volatile unsigned long *)(GPIO_BASE+PBIMR_OFF))
-#define PBINT  (*(volatile unsigned long *)(GPIO_BASE+PBINT_OFF))
-
-#define PCDR   (*(volatile unsigned long *)(GPIO_BASE+PCDR_OFF))
-#define PCDDR  (*(volatile unsigned long *)(GPIO_BASE+PCDDR_OFF))
-#define PCSBSR (*(volatile unsigned long *)(GPIO_BASE+PCSBSR_OFF))
-#define PCIMR  (*(volatile unsigned long *)(GPIO_BASE+PCIMR_OFF))
-#define PCINT  (*(volatile unsigned long *)(GPIO_BASE+PCINT_OFF))
-
-#define PDDR   (*(volatile unsigned long *)(GPIO_BASE+PDDR_OFF))
-#define PDDDR  (*(volatile unsigned long *)(GPIO_BASE+PDDDR_OFF))
-#define PDSBSR (*(volatile unsigned long *)(GPIO_BASE+PDSBSR_OFF))
-#define PDEENR (*(volatile unsigned long *)(GPIO_BASE+PDEENR_OFF))
-#define PDESNR (*(volatile unsigned long *)(GPIO_BASE+PDESNR_OFF))
-#define PDESTR (*(volatile unsigned long *)(GPIO_BASE+PDESTR_OFF))
-#define PDIMR  (*(volatile unsigned long *)(GPIO_BASE+PDIMR_OFF))
-#define PDINT  (*(volatile unsigned long *)(GPIO_BASE+PDINT_OFF))
-
-#define PEDR   (*(volatile unsigned long *)(GPIO_BASE+PEDR_OFF))
-#define PEDDR  (*(volatile unsigned long *)(GPIO_BASE+PEDDR_OFF))
-#define PESBSR (*(volatile unsigned long *)(GPIO_BASE+PESBSR_OFF))
-#define PEEENR (*(volatile unsigned long *)(GPIO_BASE+PEEENR_OFF))
-#define PEESNR (*(volatile unsigned long *)(GPIO_BASE+PEESNR_OFF))
-#define PEESTR (*(volatile unsigned long *)(GPIO_BASE+PEESTR_OFF))
-#define PEIMR  (*(volatile unsigned long *)(GPIO_BASE+PEIMR_OFF))
-#define PEINT  (*(volatile unsigned long *)(GPIO_BASE+PEINT_OFF))
-
-#define VEE_EN         0x02
-#define BACKLIGHT_EN   0x04
diff --git a/include/asm-arm/arch-l7200/hardware.h b/include/asm-arm/arch-l7200/hardware.h
deleted file mode 100644
index 2ab43f3a4a8d..000000000000
--- a/include/asm-arm/arch-l7200/hardware.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * linux/include/asm-arm/arch-l7200/hardware.h
- *
- * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
- *                    Steve Hill (sjhill@cotw.com)
- *
- * This file contains the hardware definitions for the 
- * LinkUp Systems L7200 SOC development board.
- *
- * Changelog:
- *   02-01-2000  RS     Created L7200 version, derived from rpc code
- *   03-21-2000 SJH     Cleaned up file
- *   04-21-2000  RS     Changed mapping of I/O in virtual space
- *   04-25-2000 SJH     Removed unused symbols and such
- *   05-05-2000 SJH     Complete rewrite
- *   07-31-2000 SJH     Added undocumented debug auxillary port to
- *                      get at last two columns for keyboard driver
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-/* Hardware addresses of major areas.
- *  *_START is the physical address
- *  *_SIZE  is the size of the region
- *  *_BASE  is the virtual address
- */
-#define RAM_START               0xf0000000
-#define RAM_SIZE                0x02000000
-#define RAM_BASE                0xc0000000
-
-#define IO_START                0x80000000      /* I/O */
-#define IO_SIZE                 0x01000000
-#define IO_BASE                 0xd0000000
-
-#define IO_START_2              0x90000000      /* I/O */
-#define IO_SIZE_2               0x01000000
-#define IO_BASE_2               0xd1000000
-
-#define AUX_START               0x1a000000      /* AUX PORT */
-#define AUX_SIZE                0x01000000
-#define AUX_BASE                0xd2000000
-
-#define FLASH1_START            0x00000000      /* FLASH BANK 1 */
-#define FLASH1_SIZE             0x01000000
-#define FLASH1_BASE             0xd3000000
-
-#define FLASH2_START            0x10000000      /* FLASH BANK 2 */
-#define FLASH2_SIZE             0x01000000
-#define FLASH2_BASE             0xd4000000
-
-#define ISA_START               0x20000000      /* ISA */
-#define ISA_SIZE                0x20000000
-#define ISA_BASE                0xe0000000
-
-#define PCIO_BASE               IO_BASE
-
-#endif
diff --git a/include/asm-arm/arch-l7200/io.h b/include/asm-arm/arch-l7200/io.h
deleted file mode 100644
index e24a10a7ed8c..000000000000
--- a/include/asm-arm/arch-l7200/io.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * linux/include/asm-arm/arch-l7200/io.h
- *
- * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
- *
- * Changelog:
- *  03-21-2000  SJH     Created from linux/include/asm-arm/arch-nexuspci/io.h
- *  08-31-2000  SJH     Added in IO functions necessary for new drivers
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#include <asm/arch/hardware.h>
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/*
- * There are not real ISA nor PCI buses, so we fake it.
- */
-static inline void __iomem *__io(unsigned long addr)
-{
-        return (void __iomem *)addr;
-}
-#define __io(a) __io(a)
-#define __mem_pci(a)            (a)
-
-#endif
diff --git a/include/asm-arm/arch-l7200/irqs.h b/include/asm-arm/arch-l7200/irqs.h
deleted file mode 100644
index 7120c016e29e..000000000000
--- a/include/asm-arm/arch-l7200/irqs.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * include/asm-arm/arch-l7200/irqs.h
- *
- * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
- *                    Steve Hill (sjhill@cotw.com)
- *
- * Changelog:
- *   01-02-2000 RS      Create l7200 version
- *   03-28-2000 SJH     Removed unused interrupt
- *   07-28-2000 SJH     Added pseudo-keyboard interrupt
- */
-
-/*
- * NOTE: The second timer (Timer 2) is used as the keyboard
- *       interrupt when the keyboard driver is enabled.
- */
-
-#define NR_IRQS          32
-
-#define IRQ_STWDOG        0   /* Watchdog timer */
-#define IRQ_PROG          1   /* Programmable interrupt */
-#define IRQ_DEBUG_RX      2   /* Comm Rx debug */
-#define IRQ_DEBUG_TX      3   /* Comm Tx debug */
-#define IRQ_GCTC1         4   /* Timer 1 */
-#define IRQ_GCTC2         5   /* Timer 2 / Keyboard */
-#define IRQ_DMA           6   /* DMA controller */
-#define IRQ_CLCD          7   /* Color LCD controller */
-#define IRQ_SM_RX         8   /* Smart card */
-#define IRQ_SM_TX         9   /* Smart cart */
-#define IRQ_SM_RST       10   /* Smart card */
-#define IRQ_SIB          11   /* Serial Interface Bus */
-#define IRQ_MMC          12   /* MultiMediaCard */
-#define IRQ_SSP1         13   /* Synchronous Serial Port 1 */
-#define IRQ_SSP2         14   /* Synchronous Serial Port 1 */
-#define IRQ_SPI          15   /* SPI slave */
-#define IRQ_UART_1       16   /* UART 1 */
-#define IRQ_UART_2       17   /* UART 2 */
-#define IRQ_IRDA         18   /* IRDA */
-#define IRQ_RTC_TICK     19   /* Real Time Clock tick */
-#define IRQ_RTC_ALARM    20   /* Real Time Clock alarm */
-#define IRQ_GPIO         21   /* General Purpose IO */
-#define IRQ_GPIO_DMA     22   /* General Purpose IO, DMA */
-#define IRQ_M2M          23   /* Memory to memory DMA  */
-#define IRQ_RESERVED     24   /* RESERVED, don't use */
-#define IRQ_INTF         25   /* External active low interrupt */
-#define IRQ_INT0         26   /* External active low interrupt */
-#define IRQ_INT1         27   /* External active low interrupt */
-#define IRQ_INT2         28   /* External active low interrupt */
-#define IRQ_UCB1200      29   /* Interrupt generated by UCB1200*/
-#define IRQ_BAT_LO       30   /* Low batery or external power */
-#define IRQ_MEDIA_CHG    31   /* Media change interrupt */
-
-/*
- * This is the offset of the FIQ "IRQ" numbers
- */
-#define FIQ_START       64
diff --git a/include/asm-arm/arch-l7200/memory.h b/include/asm-arm/arch-l7200/memory.h
deleted file mode 100644
index 402df637e740..000000000000
--- a/include/asm-arm/arch-l7200/memory.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * linux/include/asm-arm/arch-l7200/memory.h
- *
- * Copyright (c) 2000 Steve Hill (sjhill@cotw.com)
- * Copyright (c) 2000 Rob Scott (rscott@mtrob.fdns.net)
- *
- * Changelog:
- *  03-13-2000  SJH     Created
- *  04-13-2000  RS      Changed bus macros for new addr
- *  05-03-2000  SJH     Removed bus macros and fixed virt_to_phys macro
- */
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-/*
- * Physical DRAM offset on the L7200 SDB.
- */
-#define PHYS_OFFSET     UL(0xf0000000)
-
-#define __virt_to_bus(x) __virt_to_phys(x)
-#define __bus_to_virt(x) __phys_to_virt(x)
-
-/*
- * Cache flushing area - ROM
- */
-#define FLUSH_BASE_PHYS         0x40000000
-#define FLUSH_BASE              0xdf000000
-
-#endif
diff --git a/include/asm-arm/arch-l7200/pmpcon.h b/include/asm-arm/arch-l7200/pmpcon.h
deleted file mode 100644
index 730056c194be..000000000000
--- a/include/asm-arm/arch-l7200/pmpcon.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/****************************************************************************/
-/*
- *  linux/include/asm-arm/arch-l7200/pmpcon.h
- *
- *   Registers and  helper functions for the L7200 Link-Up Systems
- *   DC/DC converter register.
- *
- *   (C) Copyright 2000, S A McConnell  (samcconn@cotw.com)
- *
- *  This file is subject to the terms and conditions of the GNU General Public
- *  License. See the file COPYING in the main directory of this archive for
- *  more details.
- */
-
-/****************************************************************************/
-
-#define PMPCON_OFF 0x00006000  /* Offset from IO_START_2. */
-
-/* IO_START_2 and IO_BASE_2 are defined in hardware.h */
-
-#define PMPCON_START (IO_START_2 + PMPCON_OFF)  /* Physical address of reg. */
-#define PMPCON_BASE  (IO_BASE_2  + PMPCON_OFF)  /* Virtual address of reg. */
-
-
-#define PMPCON (*(volatile unsigned int *)(PMPCON_BASE))
-
-#define PWM2_50CYCLE 0x800
-#define CONTRAST     0x9
-
-#define PWM1H (CONTRAST)
-#define PWM1L (CONTRAST << 4)
-
-#define PMPCON_VALUE  (PWM2_50CYCLE | PWM1L | PWM1H) 
-        
-/* PMPCON = 0x811;   // too light and fuzzy
- * PMPCON = 0x844;   
- * PMPCON = 0x866;   // better color poor depth
- * PMPCON = 0x888;   // Darker but better depth 
- * PMPCON = 0x899;   // Darker even better depth
- * PMPCON = 0x8aa;   // too dark even better depth
- * PMPCON = 0X8cc;   // Way too dark
- */
-
-/* As CONTRAST value increases the greater the depth perception and
- * the darker the colors.
- */
diff --git a/include/asm-arm/arch-l7200/pmu.h b/include/asm-arm/arch-l7200/pmu.h
deleted file mode 100644
index 57faea76d1b3..000000000000
--- a/include/asm-arm/arch-l7200/pmu.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/****************************************************************************/
-/*
- *  linux/include/asm-arm/arch-l7200/pmu.h
- *
- *   Registers and  helper functions for the L7200 Link-Up Systems
- *   Power Management Unit (PMU).
- *
- *   (C) Copyright 2000, S A McConnell  (samcconn@cotw.com)
- *
- *  This file is subject to the terms and conditions of the GNU General Public
- *  License. See the file COPYING in the main directory of this archive for
- *  more details.
- */
-
-/****************************************************************************/
-
-#define PMU_OFF   0x00050000  /* Offset from IO_START to the PMU registers. */
-
-/* IO_START and IO_BASE are defined in hardware.h */
-
-#define PMU_START (IO_START + PMU_OFF)  /* Physical addr. of the PMU reg. */
-#define PMU_BASE  (IO_BASE  + PMU_OFF)  /* Virtual addr. of the PMU reg. */
-
-
-/* Define the PMU registers for use by device drivers and the kernel. */
-
-typedef struct {
-     unsigned int CURRENT;  /* Current configuration register */
-     unsigned int NEXT;     /* Next configuration register */
-     unsigned int reserved;
-     unsigned int RUN;      /* Run configuration register */
-     unsigned int COMM;     /* Configuration command register */
-     unsigned int SDRAM;    /* SDRAM configuration bypass register */
-} pmu_interface;
-
-#define PMU ((volatile pmu_interface *)(PMU_BASE))
-
-
-/* Macro's for reading the common register fields. */
-
-#define GET_TRANSOP(reg)  ((reg >> 25) & 0x03) /* Bits 26-25 */
-#define GET_OSCEN(reg)    ((reg >> 16) & 0x01)
-#define GET_OSCMUX(reg)   ((reg >> 15) & 0x01)
-#define GET_PLLMUL(reg)   ((reg >>  9) & 0x3f) /* Bits 14-9 */
-#define GET_PLLEN(reg)    ((reg >>  8) & 0x01)
-#define GET_PLLMUX(reg)   ((reg >>  7) & 0x01)
-#define GET_BCLK_DIV(reg) ((reg >>  3) & 0x03) /* Bits 4-3 */
-#define GET_SDRB_SEL(reg) ((reg >>  2) & 0x01)
-#define GET_SDRF_SEL(reg) ((reg >>  1) & 0x01)
-#define GET_FASTBUS(reg)  (reg & 0x1)
-
-/* CFG_NEXT register */
-
-#define CFG_NEXT_CLOCKRECOVERY ((PMU->NEXT >> 18) & 0x7f)   /* Bits 24-18 */
-#define CFG_NEXT_INTRET        ((PMU->NEXT >> 17) & 0x01)
-#define CFG_NEXT_SDR_STOP      ((PMU->NEXT >>  6) & 0x01)
-#define CFG_NEXT_SYSCLKEN      ((PMU->NEXT >>  5) & 0x01)
-
-/* Useful field values that can be used to construct the
- * CFG_NEXT and CFG_RUN registers.
- */
-
-#define TRANSOP_NOP      0<<25  /* NOCHANGE_NOSTALL */
-#define NOCHANGE_STALL   1<<25
-#define CHANGE_NOSTALL   2<<25
-#define CHANGE_STALL     3<<25
-
-#define INTRET           1<<17
-#define OSCEN            1<<16
-#define OSCMUX           1<<15
-
-/* PLL frequencies */
-
-#define PLLMUL_0         0<<9         /*  3.6864 MHz */
-#define PLLMUL_1         1<<9         /*  ?????? MHz */
-#define PLLMUL_5         5<<9         /*  18.432 MHz */
-#define PLLMUL_10       10<<9         /*  36.864 MHz */
-#define PLLMUL_18       18<<9         /*  ?????? MHz */
-#define PLLMUL_20       20<<9         /*  73.728 MHz */
-#define PLLMUL_32       32<<9         /*  ?????? MHz */
-#define PLLMUL_35       35<<9         /* 129.024 MHz */
-#define PLLMUL_36       36<<9         /*  ?????? MHz */
-#define PLLMUL_39       39<<9         /*  ?????? MHz */
-#define PLLMUL_40       40<<9         /* 147.456 MHz */
-
-/* Clock recovery times */
-
-#define CRCLOCK_1        1<<18
-#define CRCLOCK_2        2<<18
-#define CRCLOCK_4        4<<18
-#define CRCLOCK_8        8<<18
-#define CRCLOCK_16      16<<18
-#define CRCLOCK_32      32<<18
-#define CRCLOCK_63      63<<18
-#define CRCLOCK_127    127<<18
-
-#define PLLEN            1<<8
-#define PLLMUX           1<<7
-#define SDR_STOP         1<<6
-#define SYSCLKEN         1<<5
-
-#define BCLK_DIV_4       2<<3
-#define BCLK_DIV_2       1<<3
-#define BCLK_DIV_1       0<<3
-
-#define SDRB_SEL         1<<2
-#define SDRF_SEL         1<<1
-#define FASTBUS          1<<0
-
-
-/* CFG_SDRAM */
-
-#define SDRREFFQ         1<<0  /* Only if SDRSTOPRQ is not set. */
-#define SDRREFACK        1<<1  /* Read-only */
-#define SDRSTOPRQ        1<<2  /* Only if SDRREFFQ is not set. */
-#define SDRSTOPACK       1<<3  /* Read-only */
-#define PICEN            1<<4  /* Enable Co-procesor */
-#define PICTEST          1<<5
-
-#define GET_SDRREFFQ    ((PMU->SDRAM >> 0) & 0x01)
-#define GET_SDRREFACK   ((PMU->SDRAM >> 1) & 0x01) /* Read-only */
-#define GET_SDRSTOPRQ   ((PMU->SDRAM >> 2) & 0x01)
-#define GET_SDRSTOPACK  ((PMU->SDRAM >> 3) & 0x01) /* Read-only */
-#define GET_PICEN       ((PMU->SDRAM >> 4) & 0x01)
-#define GET_PICTEST     ((PMU->SDRAM >> 5) & 0x01)
diff --git a/include/asm-arm/arch-l7200/serial.h b/include/asm-arm/arch-l7200/serial.h
deleted file mode 100644
index defb8b7fca73..000000000000
--- a/include/asm-arm/arch-l7200/serial.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * linux/include/asm-arm/arch-l7200/serial.h
- *
- * Copyright (c) 2000 Rob Scott (rscott@mtrob.fdns.net)
- *                    Steve Hill (sjhill@cotw.com)
- *
- * Changelog:
- *  03-20-2000  SJH     Created
- *  03-26-2000  SJH     Added flags for serial ports
- *  03-27-2000  SJH     Corrected BASE_BAUD value
- *  04-14-2000  RS      Made register addr dependent on IO_BASE
- *  05-03-2000  SJH     Complete rewrite
- *  05-09-2000  SJH     Stripped out architecture specific serial stuff
- *                      and placed it in a separate file
- *  07-28-2000  SJH     Moved base baud rate variable
- */
-#ifndef __ASM_ARCH_SERIAL_H
-#define __ASM_ARCH_SERIAL_H
-
-/*
- * This assumes you have a 3.6864 MHz clock for your UART.
- */
-#define BASE_BAUD       3686400
-
-/*
- * Standard COM flags
- */
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
-
-#define STD_SERIAL_PORT_DEFNS           \
-        /* MAGIC UART CLK   PORT       IRQ     FLAGS */                 \
-        { 0, BASE_BAUD, UART1_BASE, IRQ_UART_1, STD_COM_FLAGS },  /* ttyLU0 */ \
-        { 0, BASE_BAUD, UART2_BASE, IRQ_UART_2, STD_COM_FLAGS },  /* ttyLU1 */ \
-
-#define EXTRA_SERIAL_PORT_DEFNS
-
-#endif
diff --git a/include/asm-arm/arch-l7200/serial_l7200.h b/include/asm-arm/arch-l7200/serial_l7200.h
deleted file mode 100644
index b1008a9d23e5..000000000000
--- a/include/asm-arm/arch-l7200/serial_l7200.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * linux/include/asm-arm/arch-l7200/serial_l7200.h
- *
- * Copyright (c) 2000 Steven Hill (sjhill@cotw.com)
- *
- * Changelog:
- *  05-09-2000  SJH     Created
- */
-#ifndef __ASM_ARCH_SERIAL_L7200_H
-#define __ASM_ARCH_SERIAL_L7200_H
-
-#include <asm/arch/memory.h>
-
-/*
- * This assumes you have a 3.6864 MHz clock for your UART.
- */
-#define BASE_BAUD 3686400
-
-/*
- * UART base register addresses
- */
-#define UART1_BASE      (IO_BASE + 0x00044000)
-#define UART2_BASE      (IO_BASE + 0x00045000)
-
-/*
- * UART register offsets
- */
-#define UARTDR                  0x00    /* Tx/Rx data */
-#define RXSTAT                  0x04    /* Rx status */
-#define H_UBRLCR                0x08    /* mode register high */
-#define M_UBRLCR                0x0C    /* mode reg mid (MSB of baud)*/
-#define L_UBRLCR                0x10    /* mode reg low (LSB of baud)*/
-#define UARTCON                 0x14    /* control register */
-#define UARTFLG                 0x18    /* flag register */
-#define UARTINTSTAT             0x1C    /* FIFO IRQ status register */
-#define UARTINTMASK             0x20    /* FIFO IRQ mask register */
-
-/*
- * UART baud rate register values
- */
-#define BR_110                  0x827
-#define BR_1200                 0x06e
-#define BR_2400                 0x05f
-#define BR_4800                 0x02f
-#define BR_9600                 0x017
-#define BR_14400                0x00f
-#define BR_19200                0x00b
-#define BR_38400                0x005
-#define BR_57600                0x003
-#define BR_76800                0x002
-#define BR_115200               0x001
-
-/*
- * Receiver status register (RXSTAT) mask values
- */
-#define RXSTAT_NO_ERR           0x00    /* No error */
-#define RXSTAT_FRM_ERR          0x01    /* Framing error */
-#define RXSTAT_PAR_ERR          0x02    /* Parity error */
-#define RXSTAT_OVR_ERR          0x04    /* Overrun error */
-
-/*
- * High byte of UART bit rate and line control register (H_UBRLCR) values
- */
-#define UBRLCR_BRK              0x01    /* generate break on tx */
-#define UBRLCR_PEN              0x02    /* enable parity */
-#define UBRLCR_PDIS             0x00    /* disable parity */
-#define UBRLCR_EVEN             0x04    /* 1= even parity,0 = odd parity */
-#define UBRLCR_STP2             0x08    /* transmit 2 stop bits */
-#define UBRLCR_FIFO             0x10    /* enable FIFO */
-#define UBRLCR_LEN5             0x60    /* word length5 */
-#define UBRLCR_LEN6             0x40    /* word length6 */
-#define UBRLCR_LEN7             0x20    /* word length7 */
-#define UBRLCR_LEN8             0x00    /* word length8 */
-
-/*
- * UART control register (UARTCON) values
- */
-#define UARTCON_UARTEN          0x01    /* Enable UART */
-#define UARTCON_DMAONERR        0x08    /* Mask RxDmaRq when errors occur */
-
-/*
- * UART flag register (UARTFLG) mask values
- */
-#define UARTFLG_UTXFF           0x20    /* Transmit FIFO full */
-#define UARTFLG_URXFE           0x10    /* Receiver FIFO empty */
-#define UARTFLG_UBUSY           0x08    /* Transmitter busy */
-#define UARTFLG_DCD             0x04    /* Data carrier detect */
-#define UARTFLG_DSR             0x02    /* Data set ready */
-#define UARTFLG_CTS             0x01    /* Clear to send */
-
-/*
- * UART interrupt status/clear registers (UARTINTSTAT/CLR) values
- */
-#define UART_TXINT              0x01    /* TX interrupt */
-#define UART_RXINT              0x02    /* RX interrupt */
-#define UART_RXERRINT           0x04    /* RX error interrupt */
-#define UART_MSINT              0x08    /* Modem Status interrupt */
-#define UART_UDINT              0x10    /* UART Disabled interrupt */
-#define UART_ALLIRQS            0x1f    /* All interrupts */
-
-#endif
diff --git a/include/asm-arm/arch-l7200/sib.h b/include/asm-arm/arch-l7200/sib.h
deleted file mode 100644
index bf4364ee2535..000000000000
--- a/include/asm-arm/arch-l7200/sib.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/****************************************************************************/
-/*
- *  linux/include/asm-arm/arch-l7200/sib.h
- *
- *  Registers and helper functions for the Serial Interface Bus.
- *
- *  (C) Copyright 2000, S A McConnell  (samcconn@cotw.com)
- *
- *  This file is subject to the terms and conditions of the GNU General Public
- *  License. See the file COPYING in the main directory of this archive for
- *  more details.
- */
-
-/****************************************************************************/
-
-#define SIB_OFF   0x00040000  /* Offset from IO_START to the SIB reg's. */
-
-/* IO_START and IO_BASE are defined in hardware.h */
-
-#define SIB_START (IO_START + SIB_OFF) /* Physical addr of the SIB reg. */
-#define SIB_BASE  (IO_BASE  + SIB_OFF) /* Virtual addr of the SIB reg.  */
-
-/* Offsets from the start of the SIB for all the registers. */
-
-/* Define the SIB registers for use by device drivers and the kernel. */
-
-typedef struct
-{
-     unsigned int MCCR;    /* SIB Control Register           Offset: 0x00 */
-     unsigned int RES1;    /* Reserved                       Offset: 0x04 */
-     unsigned int MCDR0;   /* SIB Data Register 0            Offset: 0x08 */
-     unsigned int MCDR1;   /* SIB Data Register 1            Offset: 0x0c */
-     unsigned int MCDR2;   /* SIB Data Register 2 (UCB1x00)  Offset: 0x10 */
-     unsigned int RES2;    /* Reserved                       Offset: 0x14 */
-     unsigned int MCSR;    /* SIB Status Register            Offset: 0x18 */
-} SIB_Interface;
-
-#define SIB ((volatile SIB_Interface *) (SIB_BASE))
-
-/* MCCR */
-
-#define INTERNAL_FREQ   9216000  /* Hertz */
-#define AUDIO_FREQ         5000  /* Hertz */
-#define TELECOM_FREQ       5000  /* Hertz */
-
-#define AUDIO_DIVIDE    (INTERNAL_FREQ / (32 * AUDIO_FREQ))
-#define TELECOM_DIVIDE  (INTERNAL_FREQ / (32 * TELECOM_FREQ))
-
-#define MCCR_ASD57      AUDIO_DIVIDE
-#define MCCR_TSD57      (TELECOM_DIVIDE << 8)
-#define MCCR_MCE        (1 << 16)             /* SIB enable */
-#define MCCR_ECS        (1 << 17)             /* External Clock Select */
-#define MCCR_ADM        (1 << 18)             /* A/D Data Sampling */
-#define MCCR_PMC        (1 << 26)             /* PIN Multiplexer Control */
-
-
-#define GET_ASD ((SIB->MCCR >>  0) & 0x3f) /* Audio Sample Rate Div. */
-#define GET_TSD ((SIB->MCCR >>  8) & 0x3f) /* Telcom Sample Rate Div. */
-#define GET_MCE ((SIB->MCCR >> 16) & 0x01) /* SIB Enable */
-#define GET_ECS ((SIB->MCCR >> 17) & 0x01) /* External Clock Select */
-#define GET_ADM ((SIB->MCCR >> 18) & 0x01) /* A/D Data Sampling Mode */
-#define GET_TTM ((SIB->MCCR >> 19) & 0x01) /* Telco Trans. FIFO I mask */ 
-#define GET_TRM ((SIB->MCCR >> 20) & 0x01) /* Telco Recv. FIFO I mask */
-#define GET_ATM ((SIB->MCCR >> 21) & 0x01) /* Audio Trans. FIFO I mask */ 
-#define GET_ARM ((SIB->MCCR >> 22) & 0x01) /* Audio Recv. FIFO I mask */
-#define GET_LBM ((SIB->MCCR >> 23) & 0x01) /* Loop Back Mode */
-#define GET_ECP ((SIB->MCCR >> 24) & 0x03) /* Extern. Clck Prescale sel */
-#define GET_PMC ((SIB->MCCR >> 26) & 0x01) /* PIN Multiplexer Control */
-#define GET_ERI ((SIB->MCCR >> 27) & 0x01) /* External Read Interrupt */
-#define GET_EWI ((SIB->MCCR >> 28) & 0x01) /* External Write Interrupt */
-
-/* MCDR0 */
-
-#define AUDIO_RECV     ((SIB->MCDR0 >> 4) & 0xfff)
-#define AUDIO_WRITE(v) ((SIB->MCDR0 = (v & 0xfff) << 4))
-
-/* MCDR1 */
-
-#define TELECOM_RECV     ((SIB->MCDR1 >> 2) & 032fff)
-#define TELECOM_WRITE(v) ((SIB->MCDR1 = (v & 0x3fff) << 2))
-
-
-/* MCSR */
-
-#define MCSR_ATU (1 << 4)  /* Audio Transmit FIFO Underrun */
-#define MCSR_ARO (1 << 5)  /* Audio Receive  FIFO Underrun */
-#define MCSR_TTU (1 << 6)  /* TELECOM Transmit FIFO Underrun */
-#define MCSR_TRO (1 << 7)  /* TELECOM Receive  FIFO Underrun */
-
-#define MCSR_CLEAR_UNDERUN_BITS (MCSR_ATU | MCSR_ARO | MCSR_TTU | MCSR_TRO)
-
-
-#define GET_ATS ((SIB->MCSR >>  0) & 0x01) /* Audio Transmit FIFO Service Req*/
-#define GET_ARS ((SIB->MCSR >>  1) & 0x01) /* Audio Recv FIFO Service Request*/
-#define GET_TTS ((SIB->MCSR >>  2) & 0x01) /* TELECOM Transmit FIFO  Flag */
-#define GET_TRS ((SIB->MCSR >>  3) & 0x01) /* TELECOM Recv FIFO Service Req. */
-#define GET_ATU ((SIB->MCSR >>  4) & 0x01) /* Audio Transmit FIFO Underrun */
-#define GET_ARO ((SIB->MCSR >>  5) & 0x01) /* Audio Receive  FIFO Underrun */
-#define GET_TTU ((SIB->MCSR >>  6) & 0x01) /* TELECOM Transmit FIFO Underrun */
-#define GET_TRO ((SIB->MCSR >>  7) & 0x01) /* TELECOM Receive  FIFO Underrun */
-#define GET_ANF ((SIB->MCSR >>  8) & 0x01) /* Audio Transmit FIFO not full */
-#define GET_ANE ((SIB->MCSR >>  9) & 0x01) /* Audio Receive FIFO not empty */
-#define GET_TNF ((SIB->MCSR >> 10) & 0x01) /* Telecom Transmit FIFO not full */
-#define GET_TNE ((SIB->MCSR >> 11) & 0x01) /* Telecom Receive FIFO not empty */
-#define GET_CWC ((SIB->MCSR >> 12) & 0x01) /* Codec Write Complete */
-#define GET_CRC ((SIB->MCSR >> 13) & 0x01) /* Codec Read Complete */
-#define GET_ACE ((SIB->MCSR >> 14) & 0x01) /* Audio Codec Enabled */
-#define GET_TCE ((SIB->MCSR >> 15) & 0x01) /* Telecom Codec Enabled */
-
-/* MCDR2 */
-
-#define MCDR2_rW               (1 << 16)
-
-#define WRITE_MCDR2(reg, data) (SIB->MCDR2 =((reg<<17)|MCDR2_rW|(data&0xffff)))
-#define MCDR2_WRITE_COMPLETE   GET_CWC
-
-#define INITIATE_MCDR2_READ(reg) (SIB->MCDR2 = (reg << 17))
-#define MCDR2_READ_COMPLETE      GET_CRC
-#define MCDR2_READ               (SIB->MCDR2 & 0xffff)
diff --git a/include/asm-arm/arch-l7200/sys-clock.h b/include/asm-arm/arch-l7200/sys-clock.h
deleted file mode 100644
index 771c774f4815..000000000000
--- a/include/asm-arm/arch-l7200/sys-clock.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/****************************************************************************/
-/*
- *  linux/include/asm-arm/arch-l7200/sys-clock.h
- *
- *   Registers and  helper functions for the L7200 Link-Up Systems
- *   System clocks.
- *
- *   (C) Copyright 2000, S A McConnell  (samcconn@cotw.com)
- *
- *  This file is subject to the terms and conditions of the GNU General Public
- *  License. See the file COPYING in the main directory of this archive for
- *  more details.
- */
-
-/****************************************************************************/
-
-#define SYS_CLOCK_OFF   0x00050030  /* Offset from IO_START. */
-
-/* IO_START and IO_BASE are defined in hardware.h */
-
-#define SYS_CLOCK_START (IO_START + SYS_CLCOK_OFF)  /* Physical address */
-#define SYS_CLOCK_BASE  (IO_BASE  + SYS_CLOCK_OFF)  /* Virtual address  */
-
-/* Define the interface to the SYS_CLOCK */
-
-typedef struct
-{
-     unsigned int ENABLE;
-     unsigned int ESYNC;
-     unsigned int SELECT;
-} sys_clock_interface;
-
-#define SYS_CLOCK   ((volatile sys_clock_interface *)(SYS_CLOCK_BASE))
-
-//#define CLOCK_EN    (*(volatile unsigned long *)(PMU_BASE+CLOCK_EN_OFF))
-//#define CLOCK_ESYNC (*(volatile unsigned long *)(PMU_BASE+CLOCK_ESYNC_OFF))
-//#define CLOCK_SEL   (*(volatile unsigned long *)(PMU_BASE+CLOCK_SEL_OFF))
-
-/* SYS_CLOCK -> ENABLE */
-
-#define SYN_EN          1<<0
-#define B18M_EN         1<<1
-#define CLK3M6_EN       1<<2
-#define BUART_EN        1<<3
-#define CLK18MU_EN      1<<4
-#define FIR_EN          1<<5
-#define MIRN_EN         1<<6
-#define UARTM_EN        1<<7
-#define SIBADC_EN       1<<8
-#define ALTD_EN         1<<9
-#define CLCLK_EN        1<<10
-
-/* SYS_CLOCK -> SELECT */
-
-#define CLK18M_DIV      1<<0
-#define MIR_SEL         1<<1
-#define SSP_SEL         1<<4
-#define MM_DIV          1<<5
-#define MM_SEL          1<<6
-#define ADC_SEL_2       0<<7
-#define ADC_SEL_4       1<<7
-#define ADC_SEL_8       3<<7
-#define ADC_SEL_16      7<<7
-#define ADC_SEL_32      0x0f<<7
-#define ADC_SEL_64      0x1f<<7
-#define ADC_SEL_128     0x3f<<7
-#define ALTD_SEL        1<<13
diff --git a/include/asm-arm/arch-l7200/system.h b/include/asm-arm/arch-l7200/system.h
deleted file mode 100644
index efef950a5b5d..000000000000
--- a/include/asm-arm/arch-l7200/system.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * linux/include/asm-arm/arch-l7200/system.h
- *
- * Copyright (c) 2000 Steve Hill (sjhill@cotw.com)
- *
- * Changelog
- *  03-21-2000  SJH     Created
- *  04-26-2000  SJH     Fixed functions
- *  05-03-2000  SJH     Removed usage of obsolete 'iomd.h'
- *  05-31-2000  SJH     Properly implemented 'arch_idle'
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-#include <asm/arch/hardware.h>
-
-static inline void arch_idle(void)
-{
-        *(unsigned long *)(IO_BASE + 0x50004) = 1;      /* idle mode */
-}
-
-static inline void arch_reset(char mode)
-{
-        if (mode == 's') {
-                cpu_reset(0);
-        }
-}
-
-#endif
diff --git a/include/asm-arm/arch-l7200/time.h b/include/asm-arm/arch-l7200/time.h
deleted file mode 100644
index ea22f7fff9cd..000000000000
--- a/include/asm-arm/arch-l7200/time.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * linux/include/asm-arm/arch-l7200/time.h
- *
- * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
- *                    Steve Hill (sjhill@cotw.com)
- *
- * Changelog:
- *   01-02-2000 RS      Created l7200 version, derived from rpc code
- *   05-03-2000 SJH     Complete rewrite
- */
-#ifndef _ASM_ARCH_TIME_H
-#define _ASM_ARCH_TIME_H
-
-#include <asm/arch/irqs.h>
-
-/*
- * RTC base register address
- */
-#define RTC_BASE        (IO_BASE_2 + 0x2000)
-
-/*
- * RTC registers
- */
-#define RTC_RTCDR       (*(volatile unsigned char *) (RTC_BASE + 0x000))
-#define RTC_RTCMR       (*(volatile unsigned char *) (RTC_BASE + 0x004))
-#define RTC_RTCS        (*(volatile unsigned char *) (RTC_BASE + 0x008))
-#define RTC_RTCC        (*(volatile unsigned char *) (RTC_BASE + 0x008))
-#define RTC_RTCDV       (*(volatile unsigned char *) (RTC_BASE + 0x00c))
-#define RTC_RTCCR       (*(volatile unsigned char *) (RTC_BASE + 0x010))
-
-/*
- * RTCCR register values
- */
-#define RTC_RATE_32     0x00      /* 32 Hz tick */
-#define RTC_RATE_64     0x10      /* 64 Hz tick */
-#define RTC_RATE_128    0x20      /* 128 Hz tick */
-#define RTC_RATE_256    0x30      /* 256 Hz tick */
-#define RTC_EN_ALARM    0x01      /* Enable alarm */
-#define RTC_EN_TIC      0x04      /* Enable counter */
-#define RTC_EN_STWDOG   0x08      /* Enable watchdog */
-
-/*
- * Handler for RTC timer interrupt
- */
-static irqreturn_t
-timer_interrupt(int irq, void *dev_id)
-{
-        struct pt_regs *regs = get_irq_regs();
-        do_timer(1);
-#ifndef CONFIG_SMP
-        update_process_times(user_mode(regs));
-#endif
-        do_profile(regs);
-        RTC_RTCC = 0;                           /* Clear interrupt */
-
-        return IRQ_HANDLED;
-}
-
-/*
- * Set up RTC timer interrupt, and return the current time in seconds.
- */
-void __init time_init(void)
-{
-        RTC_RTCC = 0;                           /* Clear interrupt */
-
-        timer_irq.handler = timer_interrupt;
-
-        setup_irq(IRQ_RTC_TICK, &timer_irq);
-
-        RTC_RTCCR = RTC_RATE_128 | RTC_EN_TIC;  /* Set rate and enable timer */
-}
-
-#endif
diff --git a/include/asm-arm/arch-l7200/timex.h b/include/asm-arm/arch-l7200/timex.h
deleted file mode 100644
index 3c3202620f00..000000000000
--- a/include/asm-arm/arch-l7200/timex.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * linux/include/asm-arm/arch-l7200/timex.h
- *
- * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
- *                    Steve Hill (sjhill@cotw.com)
- *
- * 04-21-2000  RS Created file
- * 05-03-2000 SJH Tick rate was wrong
- *
- */
-
-/*
- * On the ARM720T, clock ticks are set to 128 Hz.
- *
- * NOTE: The actual RTC value is set in 'time.h' which
- *       must be changed when choosing a different tick
- *       rate. The value of HZ in 'param.h' must also
- *       be changed to match below.
- */
-#define CLOCK_TICK_RATE         128
diff --git a/include/asm-arm/arch-l7200/uncompress.h b/include/asm-arm/arch-l7200/uncompress.h
deleted file mode 100644
index c5ba0adf4a5d..000000000000
--- a/include/asm-arm/arch-l7200/uncompress.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * linux/include/asm-arm/arch-l7200/uncompress.h
- *
- * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
- *
- * Changelog:
- *  05-01-2000  SJH     Created
- *  05-13-2000  SJH     Filled in function bodies
- *  07-26-2000  SJH     Removed hard coded baud rate
- */
-
-#include <asm/arch/hardware.h>
-
-#define IO_UART  IO_START + 0x00044000
-
-#define __raw_writeb(v,p)       (*(volatile unsigned char *)(p) = (v))
-#define __raw_readb(p)          (*(volatile unsigned char *)(p))
-
-static inline void putc(int c)
-{
-        while(__raw_readb(IO_UART + 0x18) & 0x20 ||
-              __raw_readb(IO_UART + 0x18) & 0x08)
-                barrier();
-
-        __raw_writeb(c, IO_UART + 0x00);
-}
-
-static inline void flush(void)
-{
-}
-
-static __inline__ void arch_decomp_setup(void)
-{
-        __raw_writeb(0x00, IO_UART + 0x08);     /* Set HSB */
-        __raw_writeb(0x00, IO_UART + 0x20);     /* Disable IRQs */
-        __raw_writeb(0x01, IO_UART + 0x14);     /* Enable UART */
-}
-
-#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-l7200/vmalloc.h b/include/asm-arm/arch-l7200/vmalloc.h
deleted file mode 100644
index 816231eedaac..000000000000
--- a/include/asm-arm/arch-l7200/vmalloc.h
+++ /dev/null
@@ -1,4 +0,0 @@
-/*
- * linux/include/asm-arm/arch-l7200/vmalloc.h
- */
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
diff --git a/include/asm-arm/arch-lh7a40x/clocks.h b/include/asm-arm/arch-lh7a40x/clocks.h
deleted file mode 100644
index 7d0ba18ad578..000000000000
--- a/include/asm-arm/arch-lh7a40x/clocks.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* include/asm-arm/arch-lh7a40x/clocks.h
- *
- *  Copyright (C) 2004 Marc Singer
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  version 2 as published by the Free Software Foundation.
- *
- */
-
-#ifndef __ASM_ARCH_CLOCKS_H
-#define __ASM_ARCH_CLOCKS_H
-
-unsigned int fclkfreq_get (void);
-unsigned int hclkfreq_get (void);
-unsigned int pclkfreq_get (void);
-
-#endif  /* _ASM_ARCH_CLOCKS_H */
diff --git a/include/asm-arm/arch-lh7a40x/constants.h b/include/asm-arm/arch-lh7a40x/constants.h
deleted file mode 100644
index 51de96e87faf..000000000000
--- a/include/asm-arm/arch-lh7a40x/constants.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* include/asm-arm/arch-lh7a40x/constants.h
- *
- *  Copyright (C) 2004 Coastal Environmental Systems
- *  Copyright (C) 2004 Logic Product Development
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  version 2 as published by the Free Software Foundation.
- *
- */
-
-#ifndef __ASM_ARCH_CONSTANTS_H
-#define __ASM_ARCH_CONSTANTS_H
-
-
-/* Addressing constants */
-
-        /* SoC CPU IO addressing */
-#define IO_PHYS                 (0x80000000)
-#define IO_VIRT                 (0xf8000000)
-#define IO_SIZE                 (0x0000B000)
-
-#ifdef CONFIG_MACH_KEV7A400
-# define CPLD_PHYS              (0x20000000)
-# define CPLD_VIRT              (0xf2000000)
-# define CPLD_SIZE              PAGE_SIZE
-#endif
-
-#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
-
-# define IOBARRIER_PHYS         0x10000000 /* Second bank, fastest timing */
-# define IOBARRIER_VIRT         0xf0000000
-# define IOBARRIER_SIZE         PAGE_SIZE
-
-# define CF_PHYS                0x60200000
-# define CF_VIRT                0xf6020000
-# define CF_SIZE                (8*1024)
-
-        /* The IO mappings for the LPD CPLD are, unfortunately, sparse.  */
-# define CPLDX_PHYS(x)          (0x70000000 | ((x) << 20))
-# define CPLDX_VIRT(x)          (0xf7000000 | ((x) << 16))
-# define CPLD00_PHYS            CPLDX_PHYS (0x00) /* Wired LAN */
-# define CPLD00_VIRT            CPLDX_VIRT (0x00)
-# define CPLD00_SIZE            PAGE_SIZE
-# define CPLD02_PHYS            CPLDX_PHYS (0x02)
-# define CPLD02_VIRT            CPLDX_VIRT (0x02)
-# define CPLD02_SIZE            PAGE_SIZE
-# define CPLD06_PHYS            CPLDX_PHYS (0x06)
-# define CPLD06_VIRT            CPLDX_VIRT (0x06)
-# define CPLD06_SIZE            PAGE_SIZE
-# define CPLD08_PHYS            CPLDX_PHYS (0x08)
-# define CPLD08_VIRT            CPLDX_VIRT (0x08)
-# define CPLD08_SIZE            PAGE_SIZE
-# define CPLD0A_PHYS            CPLDX_PHYS (0x0a)
-# define CPLD0A_VIRT            CPLDX_VIRT (0x0a)
-# define CPLD0A_SIZE            PAGE_SIZE
-# define CPLD0C_PHYS            CPLDX_PHYS (0x0c)
-# define CPLD0C_VIRT            CPLDX_VIRT (0x0c)
-# define CPLD0C_SIZE            PAGE_SIZE
-# define CPLD0E_PHYS            CPLDX_PHYS (0x0e)
-# define CPLD0E_VIRT            CPLDX_VIRT (0x0e)
-# define CPLD0E_SIZE            PAGE_SIZE
-# define CPLD10_PHYS            CPLDX_PHYS (0x10)
-# define CPLD10_VIRT            CPLDX_VIRT (0x10)
-# define CPLD10_SIZE            PAGE_SIZE
-# define CPLD12_PHYS            CPLDX_PHYS (0x12)
-# define CPLD12_VIRT            CPLDX_VIRT (0x12)
-# define CPLD12_SIZE            PAGE_SIZE
-# define CPLD14_PHYS            CPLDX_PHYS (0x14)
-# define CPLD14_VIRT            CPLDX_VIRT (0x14)
-# define CPLD14_SIZE            PAGE_SIZE
-# define CPLD16_PHYS            CPLDX_PHYS (0x16)
-# define CPLD16_VIRT            CPLDX_VIRT (0x16)
-# define CPLD16_SIZE            PAGE_SIZE
-# define CPLD18_PHYS            CPLDX_PHYS (0x18)
-# define CPLD18_VIRT            CPLDX_VIRT (0x18)
-# define CPLD18_SIZE            PAGE_SIZE
-# define CPLD1A_PHYS            CPLDX_PHYS (0x1a)
-# define CPLD1A_VIRT            CPLDX_VIRT (0x1a)
-# define CPLD1A_SIZE            PAGE_SIZE
-#endif
-
-        /* Timing constants */
-
-#define XTAL_IN                 14745600        /* 14.7456 MHz crystal */
-#define PLL_CLOCK               (XTAL_IN * 21)  /* 309 MHz PLL clock */
-#define MAX_HCLK_KHZ            100000          /* HCLK max limit ~100MHz */
-#define HCLK                    (99993600)
-//#define HCLK                  (119808000)
-
-#endif /* __ASM_ARCH_CONSTANTS_H */
diff --git a/include/asm-arm/arch-lh7a40x/debug-macro.S b/include/asm-arm/arch-lh7a40x/debug-macro.S
deleted file mode 100644
index 421dcd6a8506..000000000000
--- a/include/asm-arm/arch-lh7a40x/debug-macro.S
+++ /dev/null
@@ -1,39 +0,0 @@
-/* linux/include/asm-arm/arch-lh7a40x/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-        @ It is not known if this will be appropriate for every 40x
-        @ board.
-
-                .macro  addruart,rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                mov     \rx, #0x00000700        @ offset from base
-                orreq   \rx, \rx, #0x80000000   @ physical base
-                orrne   \rx, \rx, #0xf8000000   @ virtual base
-                .endm
-
-                .macro  senduart,rd,rx
-                strb    \rd, [\rx]              @ DATA
-                .endm
-
-                .macro  busyuart,rd,rx          @ spin while busy
-1001:           ldr     \rd, [\rx, #0x10]       @ STATUS
-                tst     \rd, #1 << 3            @ BUSY (TX FIFO not empty)
-                bne     1001b                   @ yes, spin
-                .endm
-
-                .macro  waituart,rd,rx          @ wait for Tx FIFO room
-1001:           ldrb    \rd, [\rx, #0x10]       @ STATUS
-                tst     \rd, #1 << 5            @ TXFF (TX FIFO full)
-                bne     1001b                   @ yes, spin
-                .endm
diff --git a/include/asm-arm/arch-lh7a40x/dma.h b/include/asm-arm/arch-lh7a40x/dma.h
deleted file mode 100644
index a8cbd14bbf9d..000000000000
--- a/include/asm-arm/arch-lh7a40x/dma.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/* include/asm-arm/arch-lh7a40x/dma.h
- *
- *  Copyright (C) 2005 Marc Singer
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  version 2 as published by the Free Software Foundation.
- *
- */
-
-typedef enum {
-        DMA_M2M0        = 0,
-        DMA_M2M1        = 1,
-        DMA_M2P0        = 2,    /* Tx */
-        DMA_M2P1        = 3,    /* Rx */
-        DMA_M2P2        = 4,    /* Tx */
-        DMA_M2P3        = 5,    /* Rx */
-        DMA_M2P4        = 6,    /* Tx - AC97 */
-        DMA_M2P5        = 7,    /* Rx - AC97 */
-        DMA_M2P6        = 8,    /* Tx */
-        DMA_M2P7        = 9,    /* Rx */
-} dma_device_t;
-
-#define DMA_LENGTH_MAX          ((64*1024) - 4) /* bytes */
-
-#define DMAC_GCA                __REG(DMAC_PHYS + 0x2b80)
-#define DMAC_GIR                __REG(DMAC_PHYS + 0x2bc0)
-
-#define DMAC_GIR_MMI1           (1<<11)
-#define DMAC_GIR_MMI0           (1<<10)
-#define DMAC_GIR_MPI8           (1<<9)
-#define DMAC_GIR_MPI9           (1<<8)
-#define DMAC_GIR_MPI6           (1<<7)
-#define DMAC_GIR_MPI7           (1<<6)
-#define DMAC_GIR_MPI4           (1<<5)
-#define DMAC_GIR_MPI5           (1<<4)
-#define DMAC_GIR_MPI2           (1<<3)
-#define DMAC_GIR_MPI3           (1<<2)
-#define DMAC_GIR_MPI0           (1<<1)
-#define DMAC_GIR_MPI1           (1<<0)
-
-#define DMAC_M2P0               0x0000
-#define DMAC_M2P1               0x0040
-#define DMAC_M2P2               0x0080
-#define DMAC_M2P3               0x00c0
-#define DMAC_M2P4               0x0240
-#define DMAC_M2P5               0x0200
-#define DMAC_M2P6               0x02c0
-#define DMAC_M2P7               0x0280
-#define DMAC_M2P8               0x0340
-#define DMAC_M2P9               0x0300
-#define DMAC_M2M0               0x0100
-#define DMAC_M2M1               0x0140
-
-#define DMAC_P_PCONTROL(c)      __REG(DMAC_PHYS + (c) + 0x00)
-#define DMAC_P_PINTERRUPT(c)    __REG(DMAC_PHYS + (c) + 0x04)
-#define DMAC_P_PPALLOC(c)       __REG(DMAC_PHYS + (c) + 0x08)
-#define DMAC_P_PSTATUS(c)       __REG(DMAC_PHYS + (c) + 0x0c)
-#define DMAC_P_REMAIN(c)        __REG(DMAC_PHYS + (c) + 0x14)
-#define DMAC_P_MAXCNT0(c)       __REG(DMAC_PHYS + (c) + 0x20)
-#define DMAC_P_BASE0(c)         __REG(DMAC_PHYS + (c) + 0x24)
-#define DMAC_P_CURRENT0(c)      __REG(DMAC_PHYS + (c) + 0x28)
-#define DMAC_P_MAXCNT1(c)       __REG(DMAC_PHYS + (c) + 0x30)
-#define DMAC_P_BASE1(c)         __REG(DMAC_PHYS + (c) + 0x34)
-#define DMAC_P_CURRENT1(c)      __REG(DMAC_PHYS + (c) + 0x38)
-
-#define DMAC_PCONTROL_ENABLE    (1<<4)
-
-#define DMAC_PORT_USB           0
-#define DMAC_PORT_SDMMC         1
-#define DMAC_PORT_AC97_1        2
-#define DMAC_PORT_AC97_2        3
-#define DMAC_PORT_AC97_3        4
-#define DMAC_PORT_UART1         6
-#define DMAC_PORT_UART2         7
-#define DMAC_PORT_UART3         8
-
-#define DMAC_PSTATUS_CURRSTATE_SHIFT    4
-#define DMAC_PSTATUS_CURRSTATE_MASK     0x3
-
-#define DMAC_PSTATUS_NEXTBUF     (1<<6)
-#define DMAC_PSTATUS_STALLRINT   (1<<0)
-
-#define DMAC_INT_CHE             (1<<3)
-#define DMAC_INT_NFB             (1<<1)
-#define DMAC_INT_STALL           (1<<0)
diff --git a/include/asm-arm/arch-lh7a40x/entry-macro.S b/include/asm-arm/arch-lh7a40x/entry-macro.S
deleted file mode 100644
index 34468e064629..000000000000
--- a/include/asm-arm/arch-lh7a40x/entry-macro.S
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * include/asm-arm/arch-lh7a40x/entry-macro.S
- *
- * Low-level IRQ helper macros for LH7A40x platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <asm/arch/hardware.h>
-#include <asm/arch/irqs.h>
-
-/* In order to allow there to be support for both of the processor
-   classes at the same time, we make a hack here that isn't very
-   pretty.  At startup, the link pointed to with the
-   branch_irq_lh7a400 symbol is replaced with a NOP when the CPU is
-   detected as a lh7a404.
-
-   *** FIXME: we should clean this up so that there is only one
-              implementation for each CPU's design.
-
-*/
-
-#if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-
-branch_irq_lh7a400: b 1000f
-
-@ Implementation of the LH7A404 get_irqnr_and_base.
-
-                mov     \irqnr, #0                      @ VIC1 irq base
-                mov     \base, #io_p2v(0x80000000)      @ APB registers
-                add     \base, \base, #0x8000
-                ldr     \tmp, [\base, #0x0030]          @ VIC1_VECTADDR
-                tst     \tmp, #VA_VECTORED              @ Direct vectored
-                bne     1002f
-                tst     \tmp, #VA_VIC1DEFAULT           @ Default vectored VIC1
-                ldrne   \irqstat, [\base, #0]           @ VIC1_IRQSTATUS
-                bne     1001f
-                add     \base, \base, #(0xa000 - 0x8000)
-                ldr     \tmp, [\base, #0x0030]          @ VIC2_VECTADDR
-                tst     \tmp, #VA_VECTORED              @ Direct vectored
-                bne     1002f
-                ldr     \irqstat, [\base, #0]           @ VIC2_IRQSTATUS
-                mov     \irqnr, #32                     @ VIC2 irq base
-
-1001:           movs    \irqstat, \irqstat, lsr #1      @ Shift into carry
-                bcs     1008f                           @ Bit set; irq found
-                add     \irqnr, \irqnr, #1
-                bne     1001b                           @ Until no bits
-                b       1009f                           @ Nothing?  Hmm.
-1002:           and     \irqnr, \tmp, #0x3f             @ Mask for valid bits
-1008:           movs    \irqstat, #1                    @ Force !Z
-                str     \tmp, [\base, #0x0030]          @ Clear vector
-                b       1009f
-
-@ Implementation of the LH7A400 get_irqnr_and_base.
-
-1000:           mov     \irqnr, #0
-                mov     \base, #io_p2v(0x80000000)      @ APB registers
-                ldr     \irqstat, [\base, #0x500]       @ PIC INTSR
-
-1001:           movs    \irqstat, \irqstat, lsr #1      @ Shift into carry
-                bcs     1008f                           @ Bit set; irq found
-                add     \irqnr, \irqnr, #1
-                bne     1001b                           @ Until no bits
-                b       1009f                           @ Nothing?  Hmm.
-1008:           movs    \irqstat, #1                    @ Force !Z
-
-1009:
-               .endm
-
-
-
-#elif defined (CONFIG_ARCH_LH7A400)
-                .macro  disable_fiq
-                .endm
-
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                mov     \irqnr, #0
-                mov     \base, #io_p2v(0x80000000)      @ APB registers
-                ldr     \irqstat, [\base, #0x500]       @ PIC INTSR
-
-1001:           movs    \irqstat, \irqstat, lsr #1      @ Shift into carry
-                bcs     1008f                           @ Bit set; irq found
-                add     \irqnr, \irqnr, #1
-                bne     1001b                           @ Until no bits
-                b       1009f                           @ Nothing?  Hmm.
-1008:           movs    \irqstat, #1                    @ Force !Z
-1009:
-               .endm
-
-#elif defined(CONFIG_ARCH_LH7A404)
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                mov     \irqnr, #0                      @ VIC1 irq base
-                mov     \base, #io_p2v(0x80000000)      @ APB registers
-                add     \base, \base, #0x8000
-                ldr     \tmp, [\base, #0x0030]          @ VIC1_VECTADDR
-                tst     \tmp, #VA_VECTORED              @ Direct vectored
-                bne     1002f
-                tst     \tmp, #VA_VIC1DEFAULT           @ Default vectored VIC1
-                ldrne   \irqstat, [\base, #0]           @ VIC1_IRQSTATUS
-                bne     1001f
-                add     \base, \base, #(0xa000 - 0x8000)
-                ldr     \tmp, [\base, #0x0030]          @ VIC2_VECTADDR
-                tst     \tmp, #VA_VECTORED              @ Direct vectored
-                bne     1002f
-                ldr     \irqstat, [\base, #0]           @ VIC2_IRQSTATUS
-                mov     \irqnr, #32                     @ VIC2 irq base
-
-1001:           movs    \irqstat, \irqstat, lsr #1      @ Shift into carry
-                bcs     1008f                           @ Bit set; irq found
-                add     \irqnr, \irqnr, #1
-                bne     1001b                           @ Until no bits
-                b       1009f                           @ Nothing?  Hmm.
-1002:           and     \irqnr, \tmp, #0x3f             @ Mask for valid bits
-1008:           movs    \irqstat, #1                    @ Force !Z
-                str     \tmp, [\base, #0x0030]          @ Clear vector
-1009:
-               .endm
-#endif
-
-
diff --git a/include/asm-arm/arch-lh7a40x/hardware.h b/include/asm-arm/arch-lh7a40x/hardware.h
deleted file mode 100644
index e9ff74fd7939..000000000000
--- a/include/asm-arm/arch-lh7a40x/hardware.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* include/asm-arm/arch-lh7a40x/hardware.h
- *
- *  Copyright (C) 2004 Coastal Environmental Systems
- *
- *  [ Substantially cribbed from include/asm-arm/arch-pxa/hardware.h ]
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  version 2 as published by the Free Software Foundation.
- *
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <asm/sizes.h>          /* Added for the sake of amba-clcd driver */
-
-#define io_p2v(x) (0xf0000000 | (((x) & 0xfff00000) >> 4) | ((x) & 0x0000ffff))
-#define io_v2p(x) (             (((x) & 0x0fff0000) << 4) | ((x) & 0x0000ffff))
-
-#ifdef __ASSEMBLY__
-
-# define __REG(x)       io_p2v(x)
-# define __PREG(x)      io_v2p(x)
-
-#else
-
-# if 0
-#  define __REG(x)      (*((volatile u32 *)io_p2v(x)))
-# else
-/*
- * This __REG() version gives the same results as the one above,  except
- * that we are fooling gcc somehow so it generates far better and smaller
- * assembly code for access to contigous registers.  It's a shame that gcc
- * doesn't guess this by itself.
- */
-#include <asm/types.h>
-typedef struct { volatile u32 offset[4096]; } __regbase;
-# define __REGP(x)      ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
-# define __REG(x)       __REGP(io_p2v(x))
-typedef struct { volatile u16 offset[4096]; } __regbase16;
-# define __REGP16(x)    ((__regbase16 *)((x)&~4095))->offset[((x)&4095)>>1]
-# define __REG16(x)     __REGP16(io_p2v(x))
-typedef struct { volatile u8 offset[4096]; } __regbase8;
-# define __REGP8(x)     ((__regbase8 *)((x)&~4095))->offset[(x)&4095]
-# define __REG8(x)      __REGP8(io_p2v(x))
-#endif
-
-/* Let's kick gcc's ass again... */
-# define __REG2(x,y)    \
-        ( __builtin_constant_p(y) ? (__REG((x) + (y))) \
-                                  : (*(volatile u32 *)((u32)&__REG(x) + (y))) )
-
-# define __PREG(x)      (io_v2p((u32)&(x)))
-
-#endif
-
-#define MASK_AND_SET(v,m,s)     (v) = ((v)&~(m))|(s)
-
-#include "registers.h"
-
-#endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-lh7a40x/io.h b/include/asm-arm/arch-lh7a40x/io.h
deleted file mode 100644
index 8d591d0927c1..000000000000
--- a/include/asm-arm/arch-lh7a40x/io.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* include/asm-arm/arch-lh7a40x/io.h
- *
- *  Copyright (C) 2004 Coastal Environmental Systems
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  version 2 as published by the Free Software Foundation.
- *
- */
-
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#include <asm/arch/hardware.h>
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/* No ISA or PCI bus on this machine. */
-#define __io(a)                 ((void __iomem *)(a))
-#define __mem_pci(a)            (a)
-
-#endif /* __ASM_ARCH_IO_H */
diff --git a/include/asm-arm/arch-lh7a40x/irqs.h b/include/asm-arm/arch-lh7a40x/irqs.h
deleted file mode 100644
index afe8c7cbad6a..000000000000
--- a/include/asm-arm/arch-lh7a40x/irqs.h
+++ /dev/null
@@ -1,200 +0,0 @@
-/* include/asm-arm/arch-lh7a40x/irqs.h
- *
- *  Copyright (C) 2004 Coastal Environmental Systems
- *  Copyright (C) 2004 Logic Product Development
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  version 2 as published by the Free Software Foundation.
- *
- */
-
-/* It is to be seen whether or not we can build a kernel for more than
- * one board.  For the time being, these macros assume that we cannot.
- * Thus, it is OK to ifdef machine/board specific IRQ assignments.
- */
-
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H
-
-
-#define FIQ_START       80
-
-#if defined (CONFIG_ARCH_LH7A400)
-
-  /* FIQs */
-
-# define IRQ_GPIO0FIQ   0       /* GPIO External FIQ Interrupt on F0 */
-# define IRQ_BLINT      1       /* Battery Low */
-# define IRQ_WEINT      2       /* Watchdog Timer, WDT overflow */
-# define IRQ_MCINT      3       /* Media Change, MEDCHG pin rising */
-
-  /* IRQs */
-
-# define IRQ_CSINT      4       /* Audio Codec (ACI) */
-# define IRQ_GPIO1INTR  5       /* GPIO External IRQ Interrupt on F1 */
-# define IRQ_GPIO2INTR  6       /* GPIO External IRQ Interrupt on F2 */
-# define IRQ_GPIO3INTR  7       /* GPIO External IRQ Interrupt on F3 */
-# define IRQ_T1UI       8       /* Timer 1 underflow */
-# define IRQ_T2UI       9       /* Timer 2 underflow */
-# define IRQ_RTCMI      10
-# define IRQ_TINTR      11      /* Clock State Controller 64 Hz tick (CSC) */
-# define IRQ_UART1INTR  12
-# define IRQ_UART2INTR  13
-# define IRQ_LCDINTR    14
-# define IRQ_SSIEOT     15      /* Synchronous Serial Interface (SSI) */
-# define IRQ_UART3INTR  16
-# define IRQ_SCIINTR    17      /* Smart Card Interface (SCI) */
-# define IRQ_AACINTR    18      /* Advanced Audio Codec (AAC) */
-# define IRQ_MMCINTR    19      /* Multimedia Card (MMC) */
-# define IRQ_USBINTR    20
-# define IRQ_DMAINTR    21
-# define IRQ_T3UI       22      /* Timer 3 underflow */
-# define IRQ_GPIO4INTR  23      /* GPIO External IRQ Interrupt on F4 */
-# define IRQ_GPIO5INTR  24      /* GPIO External IRQ Interrupt on F5 */
-# define IRQ_GPIO6INTR  25      /* GPIO External IRQ Interrupt on F6 */
-# define IRQ_GPIO7INTR  26      /* GPIO External IRQ Interrupt on F7 */
-# define IRQ_BMIINTR    27      /* Battery Monitor Interface (BMI) */
-
-# define NR_IRQ_CPU     28      /* IRQs directly recognized by CPU */
-
-        /* Given IRQ, return GPIO interrupt number 0-7 */
-# define IRQ_TO_GPIO(i)  ((i) \
-        - (((i) > IRQ_GPIO3INTR) ? IRQ_GPIO4INTR - IRQ_GPIO3INTR - 1 : 0)\
-        - (((i) > IRQ_GPIO0INTR) ? IRQ_GPIO1INTR - IRQ_GPIO0INTR - 1 : 0))
-
-#endif
-
-#if defined (CONFIG_ARCH_LH7A404)
-
-# define IRQ_BROWN      0       /* Brownout */
-# define IRQ_WDTINTR    1       /* Watchdog Timer */
-# define IRQ_COMMRX     2       /* ARM Comm Rx for Debug */
-# define IRQ_COMMTX     3       /* ARM Comm Tx for Debug */
-# define IRQ_T1UI       4       /* Timer 1 underflow */
-# define IRQ_T2UI       5       /* Timer 2 underflow */
-# define IRQ_CSINT      6       /* Codec Interrupt (shared by AAC on 404) */
-# define IRQ_DMAM2P0    7       /* -- DMA Memory to Peripheral */
-# define IRQ_DMAM2P1    8
-# define IRQ_DMAM2P2    9
-# define IRQ_DMAM2P3    10
-# define IRQ_DMAM2P4    11
-# define IRQ_DMAM2P5    12
-# define IRQ_DMAM2P6    13
-# define IRQ_DMAM2P7    14
-# define IRQ_DMAM2P8    15
-# define IRQ_DMAM2P9    16
-# define IRQ_DMAM2M0    17      /* -- DMA Memory to Memory */
-# define IRQ_DMAM2M1    18
-# define IRQ_GPIO0INTR  19      /* -- GPIOF Interrupt */
-# define IRQ_GPIO1INTR  20
-# define IRQ_GPIO2INTR  21
-# define IRQ_GPIO3INTR  22
-# define IRQ_SOFT_V1_23 23      /* -- Unassigned */
-# define IRQ_SOFT_V1_24 24
-# define IRQ_SOFT_V1_25 25
-# define IRQ_SOFT_V1_26 26
-# define IRQ_SOFT_V1_27 27
-# define IRQ_SOFT_V1_28 28
-# define IRQ_SOFT_V1_29 29
-# define IRQ_SOFT_V1_30 30
-# define IRQ_SOFT_V1_31 31
-
-# define IRQ_BLINT      32      /* Battery Low */
-# define IRQ_BMIINTR    33      /* Battery Monitor */
-# define IRQ_MCINTR     34      /* Media Change */
-# define IRQ_TINTR      35      /* 64Hz Tick */
-# define IRQ_WEINT      36      /* Watchdog Expired */
-# define IRQ_RTCMI      37      /* Real-time Clock Match */
-# define IRQ_UART1INTR  38      /* UART1 Interrupt (including error) */
-# define IRQ_UART1ERR   39      /* UART1 Error */
-# define IRQ_UART2INTR  40      /* UART2 Interrupt (including error) */
-# define IRQ_UART2ERR   41      /* UART2 Error */
-# define IRQ_UART3INTR  42      /* UART3 Interrupt (including error) */
-# define IRQ_UART3ERR   43      /* UART3 Error */
-# define IRQ_SCIINTR    44      /* Smart Card */
-# define IRQ_TSCINTR    45      /* Touchscreen */
-# define IRQ_KMIINTR    46      /* Keyboard/Mouse (PS/2) */
-# define IRQ_GPIO4INTR  47      /* -- GPIOF Interrupt */
-# define IRQ_GPIO5INTR  48
-# define IRQ_GPIO6INTR  49
-# define IRQ_GPIO7INTR  50
-# define IRQ_T3UI       51      /* Timer 3 underflow */
-# define IRQ_LCDINTR    52      /* LCD Controller */
-# define IRQ_SSPINTR    53      /* Synchronous Serial Port */
-# define IRQ_SDINTR     54      /* Secure Digital Port (MMC) */
-# define IRQ_USBINTR    55      /* USB Device Port */
-# define IRQ_USHINTR    56      /* USB Host Port */
-# define IRQ_SOFT_V2_25 57      /* -- Unassigned */
-# define IRQ_SOFT_V2_26 58
-# define IRQ_SOFT_V2_27 59
-# define IRQ_SOFT_V2_28 60
-# define IRQ_SOFT_V2_29 61
-# define IRQ_SOFT_V2_30 62
-# define IRQ_SOFT_V2_31 63
-
-# define NR_IRQ_CPU     64      /* IRQs directly recognized by CPU */
-
-        /* Given IRQ, return GPIO interrupt number 0-7 */
-# define IRQ_TO_GPIO(i)  ((i) \
-        - (((i) > IRQ_GPIO3INTR) ? IRQ_GPIO4INTR - IRQ_GPIO3INTR - 1 : 0)\
-        - IRQ_GPIO0INTR)
-
-                        /* Vector Address constants */
-# define VA_VECTORED    0x100   /* Set for vectored interrupt */
-# define VA_VIC1DEFAULT 0x200   /* Set as default VECTADDR for VIC1 */
-# define VA_VIC2DEFAULT 0x400   /* Set as default VECTADDR for VIC2 */
-
-#endif
-
-  /* IRQ aliases */
-
-#if !defined (IRQ_GPIO0INTR)
-# define IRQ_GPIO0INTR  IRQ_GPIO0FIQ
-#endif
-#define IRQ_TICK        IRQ_TINTR
-#define IRQ_PCC1_RDY    IRQ_GPIO6INTR   /* PCCard 1 ready */
-#define IRQ_PCC2_RDY    IRQ_GPIO7INTR   /* PCCard 2 ready */
-#define IRQ_USB         IRQ_USBINTR     /* USB device */
-
-#ifdef CONFIG_MACH_KEV7A400
-# define IRQ_TS         IRQ_GPIOFIQ     /* Touchscreen */
-# define IRQ_CPLD       IRQ_GPIO1INTR   /* CPLD cascade */
-# define IRQ_PCC1_CD    IRQ_GPIO_F2     /* PCCard 1 card detect */
-# define IRQ_PCC2_CD    IRQ_GPIO_F3     /* PCCard 2 card detect */
-#endif
-
-#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
-# define IRQ_CPLD_V28   IRQ_GPIO7INTR   /* CPLD cascade through GPIO_PF7 */
-# define IRQ_CPLD_V34   IRQ_GPIO3INTR   /* CPLD cascade through GPIO_PF3 */
-#endif
-
-  /* System specific IRQs */
-
-#define IRQ_BOARD_START NR_IRQ_CPU
-
-#ifdef CONFIG_MACH_KEV7A400
-# define IRQ_KEV7A400_CPLD      IRQ_BOARD_START
-# define NR_IRQ_BOARD           5
-# define IRQ_KEV7A400_MMC_CD    IRQ_KEV7A400_CPLD + 0   /* MMC Card Detect */
-# define IRQ_KEV7A400_RI2       IRQ_KEV7A400_CPLD + 1   /* Ring Indicator 2 */
-# define IRQ_KEV7A400_IDE_CF    IRQ_KEV7A400_CPLD + 2   /* Compact Flash (?) */
-# define IRQ_KEV7A400_ETH_INT   IRQ_KEV7A400_CPLD + 3   /* Ethernet chip */
-# define IRQ_KEV7A400_INT       IRQ_KEV7A400_CPLD + 4
-#endif
-
-#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
-# define IRQ_LPD7A40X_CPLD      IRQ_BOARD_START
-# define NR_IRQ_BOARD           2
-# define IRQ_LPD7A40X_ETH_INT   IRQ_LPD7A40X_CPLD + 0   /* Ethernet chip */
-# define IRQ_LPD7A400_TS        IRQ_LPD7A40X_CPLD + 1   /* Touch screen */
-#endif
-
-#if defined (CONFIG_MACH_LPD7A400)
-# define IRQ_TOUCH              IRQ_LPD7A400_TS
-#endif
-
-#define NR_IRQS         (NR_IRQ_CPU + NR_IRQ_BOARD)
-
-#endif
diff --git a/include/asm-arm/arch-lh7a40x/memory.h b/include/asm-arm/arch-lh7a40x/memory.h
deleted file mode 100644
index 9b0c8012e713..000000000000
--- a/include/asm-arm/arch-lh7a40x/memory.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/* include/asm-arm/arch-lh7a40x/memory.h
- *
- *  Copyright (C) 2004 Coastal Environmental Systems
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  version 2 as published by the Free Software Foundation.
- *
- *
- *  Refer to <file:Documentation/arm/Sharp-LH/SDRAM> for more information.
- *
- */
-
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-/*
- * Physical DRAM offset.
- */
-#define PHYS_OFFSET     UL(0xc0000000)
-
-/*
- * Virtual view <-> DMA view memory address translations
- * virt_to_bus: Used to translate the virtual address to an
- *              address suitable to be passed to set_dma_addr
- * bus_to_virt: Used to convert an address for DMA operations
- *              to an address that the kernel can use.
- */
-#define __virt_to_bus(x)         __virt_to_phys(x)
-#define __bus_to_virt(x)         __phys_to_virt(x)
-
-#ifdef CONFIG_DISCONTIGMEM
-
-/*
- * Given a kernel address, find the home node of the underlying memory.
- */
-
-# ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE
-#  define KVADDR_TO_NID(addr) \
-  (  ((((unsigned long) (addr) - PAGE_OFFSET) >> 24) &  1)\
-   | ((((unsigned long) (addr) - PAGE_OFFSET) >> 25) & ~1))
-# else  /* 2 banks per node */
-#  define KVADDR_TO_NID(addr) \
-      (((unsigned long) (addr) - PAGE_OFFSET) >> 26)
-# endif
-
-/*
- * Given a page frame number, convert it to a node id.
- */
-
-# ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE
-#  define PFN_TO_NID(pfn) \
-  (((((pfn) - PHYS_PFN_OFFSET) >> (24 - PAGE_SHIFT)) &  1)\
- | ((((pfn) - PHYS_PFN_OFFSET) >> (25 - PAGE_SHIFT)) & ~1))
-# else  /* 2 banks per node */
-#  define PFN_TO_NID(pfn) \
-    (((pfn) - PHYS_PFN_OFFSET) >> (26 - PAGE_SHIFT))
-#endif
-
-/*
- * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
- * and returns the index corresponding to the appropriate page in the
- * node's mem_map.
- */
-
-# ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE
-#  define LOCAL_MAP_NR(addr) \
-       (((unsigned long)(addr) & 0x003fffff) >> PAGE_SHIFT)
-# else  /* 2 banks per node */
-#  define LOCAL_MAP_NR(addr) \
-       (((unsigned long)(addr) & 0x01ffffff) >> PAGE_SHIFT)
-# endif
-
-#endif
-
-#endif
diff --git a/include/asm-arm/arch-lh7a40x/registers.h b/include/asm-arm/arch-lh7a40x/registers.h
deleted file mode 100644
index b4f09b3e2d03..000000000000
--- a/include/asm-arm/arch-lh7a40x/registers.h
+++ /dev/null
@@ -1,224 +0,0 @@
-/* include/asm-arm/arch-lh7a40x/registers.h
- *
- *  Copyright (C) 2004 Coastal Environmental Systems
- *  Copyright (C) 2004 Logic Product Development
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  version 2 as published by the Free Software Foundation.
- *
- */
-
-#include <asm/arch/constants.h>
-
-#ifndef __ASM_ARCH_REGISTERS_H
-#define __ASM_ARCH_REGISTERS_H
-
-
-        /* Physical register base addresses */
-
-#define AC97C_PHYS      (0x80000000)    /* AC97 Controller */
-#define MMC_PHYS        (0x80000100)    /* Multimedia Card Controller */
-#define USB_PHYS        (0x80000200)    /* USB Client */
-#define SCI_PHYS        (0x80000300)    /* Secure Card Interface */
-#define CSC_PHYS        (0x80000400)    /* Clock/State Controller  */
-#define INTC_PHYS       (0x80000500)    /* Interrupt Controller */
-#define UART1_PHYS      (0x80000600)    /* UART1 Controller */
-#define SIR_PHYS        (0x80000600)    /* IR Controller, same are UART1 */
-#define UART2_PHYS      (0x80000700)    /* UART2 Controller */
-#define UART3_PHYS      (0x80000800)    /* UART3 Controller */
-#define DCDC_PHYS       (0x80000900)    /* DC to DC Controller */
-#define ACI_PHYS        (0x80000a00)    /* Audio Codec Interface */
-#define SSP_PHYS        (0x80000b00)    /* Synchronous ... */
-#define TIMER_PHYS      (0x80000c00)    /* Timer Controller */
-#define RTC_PHYS        (0x80000d00)    /* Real-time Clock */
-#define GPIO_PHYS       (0x80000e00)    /* General Purpose IO */
-#define BMI_PHYS        (0x80000f00)    /* Battery Monitor Interface */
-#define HRTFTC_PHYS     (0x80001000)    /* High-res TFT Controller (LH7A400) */
-#define ALI_PHYS        (0x80001000)    /* Advanced LCD Interface (LH7A404) */
-#define WDT_PHYS        (0x80001400)    /* Watchdog Timer */
-#define SMC_PHYS        (0x80002000)    /* Static Memory Controller */
-#define SDRC_PHYS       (0x80002400)    /* SDRAM Controller */
-#define DMAC_PHYS       (0x80002800)    /* DMA Controller */
-#define CLCDC_PHYS      (0x80003000)    /* Color LCD Controller */
-
-        /* Physical registers of the LH7A404 */
-
-#define ADC_PHYS        (0x80001300)    /* A/D & Touchscreen Controller */
-#define VIC1_PHYS       (0x80008000)    /* Vectored Interrupt Controller 1 */
-#define USBH_PHYS       (0x80009000)    /* USB OHCI host controller */
-#define VIC2_PHYS       (0x8000a000)    /* Vectored Interrupt Controller 2 */
-
-/*#define KBD_PHYS      (0x80000e00) */
-/*#define LCDICP_PHYS   (0x80001000) */
-
-
-        /* Clock/State Controller register */
-
-#define CSC_PWRSR       __REG(CSC_PHYS + 0x00) /* Reset register & ID */
-#define CSC_PWRCNT      __REG(CSC_PHYS + 0x04) /* Power control */
-#define CSC_CLKSET      __REG(CSC_PHYS + 0x20) /* Clock speed control */
-#define CSC_USBDRESET   __REG(CSC_PHYS + 0x4c) /* USB Device resets */
-
-#define CSC_PWRCNT_USBH_EN      (1<<28) /* USB Host power enable */
-#define CSC_PWRCNT_DMAC_M2M1_EN (1<<27)
-#define CSC_PWRCNT_DMAC_M2M0_EN (1<<26)
-#define CSC_PWRCNT_DMAC_M2P8_EN (1<<25)
-#define CSC_PWRCNT_DMAC_M2P9_EN (1<<24)
-#define CSC_PWRCNT_DMAC_M2P6_EN (1<<23)
-#define CSC_PWRCNT_DMAC_M2P7_EN (1<<22)
-#define CSC_PWRCNT_DMAC_M2P4_EN (1<<21)
-#define CSC_PWRCNT_DMAC_M2P5_EN (1<<20)
-#define CSC_PWRCNT_DMAC_M2P2_EN (1<<19)
-#define CSC_PWRCNT_DMAC_M2P3_EN (1<<18)
-#define CSC_PWRCNT_DMAC_M2P0_EN (1<<17)
-#define CSC_PWRCNT_DMAC_M2P1_EN (1<<16)
-
-#define CSC_PWRSR_CHIPMAN_SHIFT (24)
-#define CSC_PWRSR_CHIPMAN_MASK  (0xff)
-#define CSC_PWRSR_CHIPID_SHIFT  (16)
-#define CSC_PWRSR_CHIPID_MASK   (0xff)
-
-#define CSC_USBDRESET_APBRESETREG       (1<<1)
-#define CSC_USBDRESET_IORESETREG        (1<<0)
-
-        /* Interrupt Controller registers */
-
-#define INTC_INTSR      __REG(INTC_PHYS + 0x00) /* Status */
-#define INTC_INTRSR     __REG(INTC_PHYS + 0x04) /* Raw Status */
-#define INTC_INTENS     __REG(INTC_PHYS + 0x08) /* Enable Set */
-#define INTC_INTENC     __REG(INTC_PHYS + 0x0c) /* Enable Clear */
-
-
-        /* Vectored Interrupted Controller registers */
-
-#define VIC1_IRQSTATUS  __REG(VIC1_PHYS + 0x00)
-#define VIC1_FIQSTATUS  __REG(VIC1_PHYS + 0x04)
-#define VIC1_RAWINTR    __REG(VIC1_PHYS + 0x08)
-#define VIC1_INTSEL     __REG(VIC1_PHYS + 0x0c)
-#define VIC1_INTEN      __REG(VIC1_PHYS + 0x10)
-#define VIC1_INTENCLR   __REG(VIC1_PHYS + 0x14)
-#define VIC1_SOFTINT    __REG(VIC1_PHYS + 0x18)
-#define VIC1_SOFTINTCLR __REG(VIC1_PHYS + 0x1c)
-#define VIC1_PROTECT    __REG(VIC1_PHYS + 0x20)
-#define VIC1_VECTADDR   __REG(VIC1_PHYS + 0x30)
-#define VIC1_NVADDR     __REG(VIC1_PHYS + 0x34)
-#define VIC1_VAD0       __REG(VIC1_PHYS + 0x100)
-#define VIC1_VECTCNTL0  __REG(VIC1_PHYS + 0x200)
-#define VIC2_IRQSTATUS  __REG(VIC2_PHYS + 0x00)
-#define VIC2_FIQSTATUS  __REG(VIC2_PHYS + 0x04)
-#define VIC2_RAWINTR    __REG(VIC2_PHYS + 0x08)
-#define VIC2_INTSEL     __REG(VIC2_PHYS + 0x0c)
-#define VIC2_INTEN      __REG(VIC2_PHYS + 0x10)
-#define VIC2_INTENCLR   __REG(VIC2_PHYS + 0x14)
-#define VIC2_SOFTINT    __REG(VIC2_PHYS + 0x18)
-#define VIC2_SOFTINTCLR __REG(VIC2_PHYS + 0x1c)
-#define VIC2_PROTECT    __REG(VIC2_PHYS + 0x20)
-#define VIC2_VECTADDR   __REG(VIC2_PHYS + 0x30)
-#define VIC2_NVADDR     __REG(VIC2_PHYS + 0x34)
-#define VIC2_VAD0       __REG(VIC2_PHYS + 0x100)
-#define VIC2_VECTCNTL0  __REG(VIC2_PHYS + 0x200)
-
-#define VIC_CNTL_ENABLE (0x20)
-
-        /* USB Host registers (Open HCI compatible) */
-
-#define USBH_CMDSTATUS  __REG(USBH_PHYS + 0x08)
-
-
-        /* GPIO registers */
-
-#define GPIO_INTTYPE1   __REG(GPIO_PHYS + 0x4c) /* Interrupt Type 1 (Edge) */
-#define GPIO_INTTYPE2   __REG(GPIO_PHYS + 0x50) /* Interrupt Type 2 */
-#define GPIO_GPIOFEOI   __REG(GPIO_PHYS + 0x54) /* GPIO End-of-Interrupt */
-#define GPIO_GPIOINTEN  __REG(GPIO_PHYS + 0x58) /* GPIO Interrupt Enable */
-#define GPIO_INTSTATUS  __REG(GPIO_PHYS + 0x5c) /* GPIO Interrupt Status */
-#define GPIO_PINMUX     __REG(GPIO_PHYS + 0x2c)
-#define GPIO_PADD       __REG(GPIO_PHYS + 0x10)
-#define GPIO_PAD        __REG(GPIO_PHYS + 0x00)
-#define GPIO_PCD        __REG(GPIO_PHYS + 0x08)
-#define GPIO_PCDD       __REG(GPIO_PHYS + 0x18)
-#define GPIO_PEDD       __REG(GPIO_PHYS + 0x24)
-#define GPIO_PED        __REG(GPIO_PHYS + 0x20)
-
-
-        /* Static Memory Controller registers */
-
-#define SMC_BCR0        __REG(SMC_PHYS + 0x00)  /* Bank 0 Configuration */
-#define SMC_BCR1        __REG(SMC_PHYS + 0x04)  /* Bank 1 Configuration */
-#define SMC_BCR2        __REG(SMC_PHYS + 0x08)  /* Bank 2 Configuration */
-#define SMC_BCR3        __REG(SMC_PHYS + 0x0C)  /* Bank 3 Configuration */
-#define SMC_BCR6        __REG(SMC_PHYS + 0x18)  /* Bank 6 Configuration */
-#define SMC_BCR7        __REG(SMC_PHYS + 0x1c)  /* Bank 7 Configuration */
-
-
-#ifdef CONFIG_MACH_KEV7A400
-# define CPLD_RD_OPT_DIP_SW     __REG16(CPLD_PHYS + 0x00) /* Read Option SW */
-# define CPLD_WR_IO_BRD_CTL     __REG16(CPLD_PHYS + 0x00) /* Write Control */
-# define CPLD_RD_PB_KEYS        __REG16(CPLD_PHYS + 0x02) /* Read Btn Keys */
-# define CPLD_LATCHED_INTS      __REG16(CPLD_PHYS + 0x04) /* Read INTR stat. */
-# define CPLD_CL_INT            __REG16(CPLD_PHYS + 0x04) /* Clear INTR stat */
-# define CPLD_BOOT_MMC_STATUS   __REG16(CPLD_PHYS + 0x06) /* R/O */
-# define CPLD_RD_KPD_ROW_SENSE  __REG16(CPLD_PHYS + 0x08)
-# define CPLD_WR_PB_INT_MASK    __REG16(CPLD_PHYS + 0x08)
-# define CPLD_RD_BRD_DISP_SW    __REG16(CPLD_PHYS + 0x0a)
-# define CPLD_WR_EXT_INT_MASK   __REG16(CPLD_PHYS + 0x0a)
-# define CPLD_LCD_PWR_CNTL      __REG16(CPLD_PHYS + 0x0c)
-# define CPLD_SEVEN_SEG         __REG16(CPLD_PHYS + 0x0e) /* 7 seg. LED mask */
-
-#endif
-
-#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
-
-# define CPLD_CONTROL           __REG16(CPLD02_PHYS)
-# define CPLD_SPI_DATA          __REG16(CPLD06_PHYS)
-# define CPLD_SPI_CONTROL       __REG16(CPLD08_PHYS)
-# define CPLD_SPI_EEPROM        __REG16(CPLD0A_PHYS)
-# define CPLD_INTERRUPTS        __REG16(CPLD0C_PHYS) /* IRQ mask/status */
-# define CPLD_BOOT_MODE         __REG16(CPLD0E_PHYS)
-# define CPLD_FLASH             __REG16(CPLD10_PHYS)
-# define CPLD_POWER_MGMT        __REG16(CPLD12_PHYS)
-# define CPLD_REVISION          __REG16(CPLD14_PHYS)
-# define CPLD_GPIO_EXT          __REG16(CPLD16_PHYS)
-# define CPLD_GPIO_DATA         __REG16(CPLD18_PHYS)
-# define CPLD_GPIO_DIR          __REG16(CPLD1A_PHYS)
-
-#endif
-
-        /* Timer registers */
-
-#define TIMER_LOAD1     __REG(TIMER_PHYS + 0x00) /* Timer 1 initial value */
-#define TIMER_VALUE1    __REG(TIMER_PHYS + 0x04) /* Timer 1 current value */
-#define TIMER_CONTROL1  __REG(TIMER_PHYS + 0x08) /* Timer 1 control word */
-#define TIMER_EOI1      __REG(TIMER_PHYS + 0x0c) /* Timer 1 interrupt clear */
-
-#define TIMER_LOAD2     __REG(TIMER_PHYS + 0x20) /* Timer 2 initial value */
-#define TIMER_VALUE2    __REG(TIMER_PHYS + 0x24) /* Timer 2 current value */
-#define TIMER_CONTROL2  __REG(TIMER_PHYS + 0x28) /* Timer 2 control word */
-#define TIMER_EOI2      __REG(TIMER_PHYS + 0x2c) /* Timer 2 interrupt clear */
-
-#define TIMER_BUZZCON   __REG(TIMER_PHYS + 0x40) /* Buzzer configuration */
-
-#define TIMER_LOAD3     __REG(TIMER_PHYS + 0x80) /* Timer 3 initial value */
-#define TIMER_VALUE3    __REG(TIMER_PHYS + 0x84) /* Timer 3 current value */
-#define TIMER_CONTROL3  __REG(TIMER_PHYS + 0x88) /* Timer 3 control word */
-#define TIMER_EOI3      __REG(TIMER_PHYS + 0x8c) /* Timer 3 interrupt clear */
-
-#define TIMER_C_ENABLE          (1<<7)
-#define TIMER_C_PERIODIC        (1<<6)
-#define TIMER_C_FREERUNNING     (0)
-#define TIMER_C_2KHZ            (0x00)          /* 1.986 kHz */
-#define TIMER_C_508KHZ          (0x08)
-
-        /* GPIO registers */
-
-#define GPIO_PFDD               __REG(GPIO_PHYS + 0x34) /* PF direction */
-#define GPIO_INTTYPE1           __REG(GPIO_PHYS + 0x4c) /* IRQ edge or lvl  */
-#define GPIO_INTTYPE2           __REG(GPIO_PHYS + 0x50) /* IRQ activ hi/lo */
-#define GPIO_GPIOFEOI           __REG(GPIO_PHYS + 0x54) /* GPIOF end of IRQ */
-#define GPIO_GPIOFINTEN         __REG(GPIO_PHYS + 0x58) /* GPIOF IRQ enable */
-#define GPIO_INTSTATUS          __REG(GPIO_PHYS + 0x5c) /* GPIOF IRQ latch */
-#define GPIO_RAWINTSTATUS       __REG(GPIO_PHYS + 0x60) /* GPIOF IRQ raw */
-
-
-#endif  /* _ASM_ARCH_REGISTERS_H */
diff --git a/include/asm-arm/arch-lh7a40x/system.h b/include/asm-arm/arch-lh7a40x/system.h
deleted file mode 100644
index e1df8aa460f2..000000000000
--- a/include/asm-arm/arch-lh7a40x/system.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* include/asm-arm/arch-lh7a40x/system.h
- *
- *  Copyright (C) 2004 Coastal Environmental Systems
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  version 2 as published by the Free Software Foundation.
- *
- */
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle ();
-}
-
-static inline void arch_reset(char mode)
-{
-        cpu_reset (0);
-}
diff --git a/include/asm-arm/arch-lh7a40x/timex.h b/include/asm-arm/arch-lh7a40x/timex.h
deleted file mode 100644
index fa726b670829..000000000000
--- a/include/asm-arm/arch-lh7a40x/timex.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* include/asm-arm/arch-lh7a40x/timex.h
- *
- *  Copyright (C) 2004 Coastal Environmental Systems
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  version 2 as published by the Free Software Foundation.
- *
- */
-
-#include <asm/arch/constants.h>
-
-#define CLOCK_TICK_RATE         (PLL_CLOCK/6/16)
-
-/*
-#define CLOCK_TICK_RATE         3686400
-*/
diff --git a/include/asm-arm/arch-lh7a40x/uncompress.h b/include/asm-arm/arch-lh7a40x/uncompress.h
deleted file mode 100644
index 3d1ce0426a33..000000000000
--- a/include/asm-arm/arch-lh7a40x/uncompress.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* include/asm-arm/arch-lh7a40x/uncompress.h
- *
- *  Copyright (C) 2004 Coastal Environmental Systems
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  version 2 as published by the Free Software Foundation.
- *
- */
-
-#include <asm/arch/registers.h>
-
-#ifndef UART_R_DATA
-# define UART_R_DATA    (0x00)
-#endif
-#ifndef UART_R_STATUS
-# define UART_R_STATUS  (0x10)
-#endif
-#define nTxRdy          (0x20)  /* Not TxReady (literally Tx FIFO full) */
-
-        /* Access UART with physical addresses before MMU is setup */
-#define UART_STATUS (*(volatile unsigned long*) (UART2_PHYS + UART_R_STATUS))
-#define UART_DATA   (*(volatile unsigned long*) (UART2_PHYS + UART_R_DATA))
-
-static inline void putc(int ch)
-{
-        while (UART_STATUS & nTxRdy)
-                barrier();
-        UART_DATA = ch;
-}
-
-static inline void flush(void)
-{
-}
-
-        /* NULL functions; we don't presently need them */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-lh7a40x/vmalloc.h b/include/asm-arm/arch-lh7a40x/vmalloc.h
deleted file mode 100644
index 8163e45109b9..000000000000
--- a/include/asm-arm/arch-lh7a40x/vmalloc.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* include/asm-arm/arch-lh7a40x/vmalloc.h
- *
- *  Copyright (C) 2004 Coastal Environmental Systems
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  version 2 as published by the Free Software Foundation.
- *
- */
-#define VMALLOC_END       (0xe8000000)
diff --git a/include/asm-arm/arch-loki/debug-macro.S b/include/asm-arm/arch-loki/debug-macro.S
deleted file mode 100644
index 585502e96513..000000000000
--- a/include/asm-arm/arch-loki/debug-macro.S
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * include/asm-arm/arch-loki/debug-macro.S
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <asm/arch/loki.h>
-
-        .macro  addruart,rx
-        mrc     p15, 0, \rx, c1, c0
-        tst     \rx, #1                                 @ MMU enabled?
-        ldreq   \rx, =LOKI_REGS_PHYS_BASE
-        ldrne   \rx, =LOKI_REGS_VIRT_BASE
-        orr     \rx, \rx, #0x00012000
-        .endm
-
-#define UART_SHIFT      2
-#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-loki/entry-macro.S b/include/asm-arm/arch-loki/entry-macro.S
deleted file mode 100644
index 693257cdbeb8..000000000000
--- a/include/asm-arm/arch-loki/entry-macro.S
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * include/asm-arm/arch-loki/entry-macro.S
- *
- * Low-level IRQ helper macros for Marvell Loki (88RC8480) platforms
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/arch/loki.h>
-
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
-        .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =IRQ_VIRT_BASE
-        .endm
-
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        ldr     \irqstat, [\base, #IRQ_CAUSE_OFF]
-        ldr     \tmp, [\base, #IRQ_MASK_OFF]
-        mov     \irqnr, #0
-        ands    \irqstat, \irqstat, \tmp
-        clzne   \irqnr, \irqstat
-        rsbne   \irqnr, \irqnr, #31
-        .endm
diff --git a/include/asm-arm/arch-loki/hardware.h b/include/asm-arm/arch-loki/hardware.h
deleted file mode 100644
index f65b01c733b6..000000000000
--- a/include/asm-arm/arch-loki/hardware.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * include/asm-arm/arch-loki/hardware.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include "loki.h"
-
-
-#endif
diff --git a/include/asm-arm/arch-loki/io.h b/include/asm-arm/arch-loki/io.h
deleted file mode 100644
index e7418a915e75..000000000000
--- a/include/asm-arm/arch-loki/io.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * include/asm-arm/arch-loki/io.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#include "loki.h"
-
-#define IO_SPACE_LIMIT          0xffffffff
-
-static inline void __iomem *__io(unsigned long addr)
-{
-        return (void __iomem *)((addr - LOKI_PCIE0_IO_PHYS_BASE)
-                                        + LOKI_PCIE0_IO_VIRT_BASE);
-}
-
-#define __io(a)                 __io(a)
-#define __mem_pci(a)            (a)
-
-
-#endif
diff --git a/include/asm-arm/arch-loki/irqs.h b/include/asm-arm/arch-loki/irqs.h
deleted file mode 100644
index 7e4971438072..000000000000
--- a/include/asm-arm/arch-loki/irqs.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * include/asm-arm/arch-loki/irqs.h
- *
- * IRQ definitions for Marvell Loki (88RC8480) SoCs
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H
-
-#include "loki.h"       /* need GPIO_MAX */
-
-/*
- * Interrupt Controller
- */
-#define IRQ_LOKI_PCIE_A_CPU_DRBL        0
-#define IRQ_LOKI_CPU_PCIE_A_DRBL        1
-#define IRQ_LOKI_PCIE_B_CPU_DRBL        2
-#define IRQ_LOKI_CPU_PCIE_B_DRBL        3
-#define IRQ_LOKI_COM_A_ERR              6
-#define IRQ_LOKI_COM_A_IN               7
-#define IRQ_LOKI_COM_A_OUT              8
-#define IRQ_LOKI_COM_B_ERR              9
-#define IRQ_LOKI_COM_B_IN               10
-#define IRQ_LOKI_COM_B_OUT              11
-#define IRQ_LOKI_DMA_A                  12
-#define IRQ_LOKI_DMA_B                  13
-#define IRQ_LOKI_SAS_A                  14
-#define IRQ_LOKI_SAS_B                  15
-#define IRQ_LOKI_DDR                    16
-#define IRQ_LOKI_XOR                    17
-#define IRQ_LOKI_BRIDGE                 18
-#define IRQ_LOKI_PCIE_A_ERR             20
-#define IRQ_LOKI_PCIE_A_INT             21
-#define IRQ_LOKI_PCIE_B_ERR             22
-#define IRQ_LOKI_PCIE_B_INT             23
-#define IRQ_LOKI_GBE_A_INT              24
-#define IRQ_LOKI_GBE_B_INT              25
-#define IRQ_LOKI_DEV_ERR                26
-#define IRQ_LOKI_UART0                  27
-#define IRQ_LOKI_UART1                  28
-#define IRQ_LOKI_TWSI                   29
-#define IRQ_LOKI_GPIO_23_0              30
-#define IRQ_LOKI_GPIO_25_24             31
-
-/*
- * Loki General Purpose Pins
- */
-#define IRQ_LOKI_GPIO_START     32
-#define NR_GPIO_IRQS            GPIO_MAX
-
-#define NR_IRQS                 (IRQ_LOKI_GPIO_START + NR_GPIO_IRQS)
-
-
-#endif
diff --git a/include/asm-arm/arch-loki/loki.h b/include/asm-arm/arch-loki/loki.h
deleted file mode 100644
index 5dd05ee0a4e6..000000000000
--- a/include/asm-arm/arch-loki/loki.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * include/asm-arm/arch-loki/loki.h
- *
- * Generic definitions for Marvell Loki (88RC8480) SoC flavors
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_LOKI_H
-#define __ASM_ARCH_LOKI_H
-
-/*
- * Marvell Loki (88RC8480) address maps.
- *
- * phys
- * d0000000     on-chip peripheral registers
- * e0000000     PCIe 0 Memory space
- * e8000000     PCIe 1 Memory space
- * f0000000     PCIe 0 I/O space
- * f0100000     PCIe 1 I/O space
- *
- * virt         phys            size
- * fed00000     d0000000        1M      on-chip peripheral registers
- * fee00000     f0000000        64K     PCIe 0 I/O space
- * fef00000     f0100000        64K     PCIe 1 I/O space
- */
-
-#define LOKI_REGS_PHYS_BASE             0xd0000000
-#define LOKI_REGS_VIRT_BASE             0xfed00000
-#define LOKI_REGS_SIZE                  SZ_1M
-
-#define LOKI_PCIE0_IO_PHYS_BASE         0xf0000000
-#define LOKI_PCIE0_IO_VIRT_BASE         0xfee00000
-#define LOKI_PCIE0_IO_BUS_BASE          0x00000000
-#define LOKI_PCIE0_IO_SIZE              SZ_64K
-
-#define LOKI_PCIE1_IO_PHYS_BASE         0xf0100000
-#define LOKI_PCIE1_IO_VIRT_BASE         0xfef00000
-#define LOKI_PCIE1_IO_BUS_BASE          0x00000000
-#define LOKI_PCIE1_IO_SIZE              SZ_64K
-
-#define LOKI_PCIE0_MEM_PHYS_BASE        0xe0000000
-#define LOKI_PCIE0_MEM_SIZE             SZ_128M
-
-#define LOKI_PCIE1_MEM_PHYS_BASE        0xe8000000
-#define LOKI_PCIE1_MEM_SIZE             SZ_128M
-
-/*
- * Register Map
- */
-#define DEV_BUS_PHYS_BASE       (LOKI_REGS_PHYS_BASE | 0x10000)
-#define DEV_BUS_VIRT_BASE       (LOKI_REGS_VIRT_BASE | 0x10000)
-#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2000)
-#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2000)
-#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2100)
-#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2100)
-
-#define BRIDGE_VIRT_BASE        (LOKI_REGS_VIRT_BASE | 0x20000)
-#define  BRIDGE_REG(x)          (BRIDGE_VIRT_BASE | (x))
-#define  RSTOUTn_MASK           (BRIDGE_VIRT_BASE | 0x0108)
-#define   SOFT_RESET_OUT_EN     0x00000004
-#define  SYSTEM_SOFT_RESET      (BRIDGE_VIRT_BASE | 0x010c)
-#define   SOFT_RESET            0x00000001
-#define  BRIDGE_CAUSE           (BRIDGE_VIRT_BASE | 0x0110)
-#define  BRIDGE_MASK            (BRIDGE_VIRT_BASE | 0x0114)
-#define   BRIDGE_INT_TIMER0     0x0002
-#define   BRIDGE_INT_TIMER1     0x0004
-#define   BRIDGE_INT_TIMER1_CLR 0x0004
-#define  IRQ_VIRT_BASE          (BRIDGE_VIRT_BASE | 0x0200)
-#define   IRQ_CAUSE_OFF         0x0000
-#define   IRQ_MASK_OFF          0x0004
-#define  TIMER_VIRT_BASE        (BRIDGE_VIRT_BASE | 0x0300)
-
-#define PCIE0_VIRT_BASE         (LOKI_REGS_VIRT_BASE | 0x30000)
-
-#define PCIE1_VIRT_BASE         (LOKI_REGS_VIRT_BASE | 0x40000)
-
-#define SAS0_PHYS_BASE          (LOKI_REGS_PHYS_BASE | 0x80000)
-
-#define SAS1_PHYS_BASE          (LOKI_REGS_PHYS_BASE | 0x90000)
-
-#define GE0_PHYS_BASE           (LOKI_REGS_PHYS_BASE | 0xa0000)
-#define GE0_VIRT_BASE           (LOKI_REGS_VIRT_BASE | 0xa0000)
-
-#define GE1_PHYS_BASE           (LOKI_REGS_PHYS_BASE | 0xb0000)
-#define GE1_VIRT_BASE           (LOKI_REGS_VIRT_BASE | 0xb0000)
-
-#define DDR_VIRT_BASE           (LOKI_REGS_VIRT_BASE | 0xf0000)
-#define DDR_REG(x)              (DDR_VIRT_BASE | (x))
-
-
-#define GPIO_MAX                8
-
-
-#endif
diff --git a/include/asm-arm/arch-loki/memory.h b/include/asm-arm/arch-loki/memory.h
deleted file mode 100644
index 835101e49875..000000000000
--- a/include/asm-arm/arch-loki/memory.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * include/asm-arm/arch-loki/memory.h
- */
-
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-#define PHYS_OFFSET             UL(0x00000000)
-
-#define __virt_to_bus(x)        __virt_to_phys(x)
-#define __bus_to_virt(x)        __phys_to_virt(x)
-
-
-#endif
diff --git a/include/asm-arm/arch-loki/system.h b/include/asm-arm/arch-loki/system.h
deleted file mode 100644
index a3568ac8ec35..000000000000
--- a/include/asm-arm/arch-loki/system.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * include/asm-arm/arch-loki/system.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/loki.h>
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-static inline void arch_reset(char mode)
-{
-        /*
-         * Enable soft reset to assert RSTOUTn.
-         */
-        writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
-
-        /*
-         * Assert soft reset.
-         */
-        writel(SOFT_RESET, SYSTEM_SOFT_RESET);
-
-        while (1)
-                ;
-}
-
-
-#endif
diff --git a/include/asm-arm/arch-loki/timex.h b/include/asm-arm/arch-loki/timex.h
deleted file mode 100644
index 940014f97cae..000000000000
--- a/include/asm-arm/arch-loki/timex.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * include/asm-arm/arch-loki/timex.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#define CLOCK_TICK_RATE         (100 * HZ)
-
-#define LOKI_TCLK               180000000
diff --git a/include/asm-arm/arch-loki/uncompress.h b/include/asm-arm/arch-loki/uncompress.h
deleted file mode 100644
index 89a0cf88d3a5..000000000000
--- a/include/asm-arm/arch-loki/uncompress.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * include/asm-arm/arch-loki/uncompress.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/serial_reg.h>
-#include <asm/arch/loki.h>
-
-#define SERIAL_BASE     ((unsigned char *)UART0_PHYS_BASE)
-
-static void putc(const char c)
-{
-        unsigned char *base = SERIAL_BASE;
-        int i;
-
-        for (i = 0; i < 0x1000; i++) {
-                if (base[UART_LSR << 2] & UART_LSR_THRE)
-                        break;
-                barrier();
-        }
-
-        base[UART_TX << 2] = c;
-}
-
-static void flush(void)
-{
-        unsigned char *base = SERIAL_BASE;
-        unsigned char mask;
-        int i;
-
-        mask = UART_LSR_TEMT | UART_LSR_THRE;
-
-        for (i = 0; i < 0x1000; i++) {
-                if ((base[UART_LSR << 2] & mask) == mask)
-                        break;
-                barrier();
-        }
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-loki/vmalloc.h b/include/asm-arm/arch-loki/vmalloc.h
deleted file mode 100644
index f5be06220491..000000000000
--- a/include/asm-arm/arch-loki/vmalloc.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * include/asm-arm/arch-loki/vmalloc.h
- */
-
-#define VMALLOC_END     0xfe800000
diff --git a/include/asm-arm/arch-msm/board.h b/include/asm-arm/arch-msm/board.h
deleted file mode 100644
index 763051f8ba14..000000000000
--- a/include/asm-arm/arch-msm/board.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* linux/include/asm-arm/arch-msm/board.h
- *
- * Copyright (C) 2007 Google, Inc.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ASM_ARCH_MSM_BOARD_H
-#define __ASM_ARCH_MSM_BOARD_H
-
-#include <linux/types.h>
-
-/* platform device data structures */
-
-struct msm_mddi_platform_data
-{
-        void (*panel_power)(int on);
-        unsigned has_vsync_irq:1;
-};
-
-/* common init routines for use by arch/arm/mach-msm/board-*.c */
-
-void __init msm_add_devices(void);
-void __init msm_map_common_io(void);
-void __init msm_init_irq(void);
-void __init msm_init_gpio(void);
-
-#endif
diff --git a/include/asm-arm/arch-msm/debug-macro.S b/include/asm-arm/arch-msm/debug-macro.S
deleted file mode 100644
index e131b44b2107..000000000000
--- a/include/asm-arm/arch-msm/debug-macro.S
+++ /dev/null
@@ -1,40 +0,0 @@
-/* include/asm-arm/arch-msm7200/debug-macro.S
- *
- * Copyright (C) 2007 Google, Inc.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/msm_iomap.h>
-
-        .macro  addruart,rx
-        @ see if the MMU is enabled and select appropriate base address
-        mrc     p15, 0, \rx, c1, c0
-        tst     \rx, #1
-        ldreq   \rx, =MSM_UART1_PHYS
-        ldrne   \rx, =MSM_UART1_BASE
-        .endm
-
-        .macro  senduart,rd,rx
-        str     \rd, [\rx, #0x0C]
-        .endm
-
-        .macro  waituart,rd,rx
-        @ wait for TX_READY
-1:      ldr     \rd, [\rx, #0x08]
-        tst     \rd, #0x04
-        beq     1b
-        .endm
-
-        .macro  busyuart,rd,rx
-        .endm
diff --git a/include/asm-arm/arch-msm/dma.h b/include/asm-arm/arch-msm/dma.h
deleted file mode 100644
index e4b565b27b35..000000000000
--- a/include/asm-arm/arch-msm/dma.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/* linux/include/asm-arm/arch-msm/dma.h
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ASM_ARCH_MSM_DMA_H
-
-#include <linux/list.h>
-#include <asm/arch/msm_iomap.h>
-
-struct msm_dmov_cmd {
-        struct list_head list;
-        unsigned int cmdptr;
-        void (*complete_func)(struct msm_dmov_cmd *cmd, unsigned int result);
-/*      void (*user_result_func)(struct msm_dmov_cmd *cmd); */
-};
-
-void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd);
-void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd);
-int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr);
-/* int msm_dmov_exec_cmd_etc(unsigned id, unsigned int cmdptr, int timeout, int interruptible); */
-
-
-
-#define DMOV_SD0(off, ch) (MSM_DMOV_BASE + 0x0000 + (off) + ((ch) << 2))
-#define DMOV_SD1(off, ch) (MSM_DMOV_BASE + 0x0400 + (off) + ((ch) << 2))
-#define DMOV_SD2(off, ch) (MSM_DMOV_BASE + 0x0800 + (off) + ((ch) << 2))
-#define DMOV_SD3(off, ch) (MSM_DMOV_BASE + 0x0C00 + (off) + ((ch) << 2))
-
-/* only security domain 3 is available to the ARM11
- * SD0 -> mARM trusted, SD1 -> mARM nontrusted, SD2 -> aDSP, SD3 -> aARM
- */
-
-#define DMOV_CMD_PTR(ch)      DMOV_SD3(0x000, ch)
-#define DMOV_CMD_LIST         (0 << 29) /* does not work */
-#define DMOV_CMD_PTR_LIST     (1 << 29) /* works */
-#define DMOV_CMD_INPUT_CFG    (2 << 29) /* untested */
-#define DMOV_CMD_OUTPUT_CFG   (3 << 29) /* untested */
-#define DMOV_CMD_ADDR(addr)   ((addr) >> 3)
-
-#define DMOV_RSLT(ch)         DMOV_SD3(0x040, ch)
-#define DMOV_RSLT_VALID       (1 << 31) /* 0 == host has empties result fifo */
-#define DMOV_RSLT_ERROR       (1 << 3)
-#define DMOV_RSLT_FLUSH       (1 << 2)
-#define DMOV_RSLT_DONE        (1 << 1)  /* top pointer done */
-#define DMOV_RSLT_USER        (1 << 0)  /* command with FR force result */
-
-#define DMOV_FLUSH0(ch)       DMOV_SD3(0x080, ch)
-#define DMOV_FLUSH1(ch)       DMOV_SD3(0x0C0, ch)
-#define DMOV_FLUSH2(ch)       DMOV_SD3(0x100, ch)
-#define DMOV_FLUSH3(ch)       DMOV_SD3(0x140, ch)
-#define DMOV_FLUSH4(ch)       DMOV_SD3(0x180, ch)
-#define DMOV_FLUSH5(ch)       DMOV_SD3(0x1C0, ch)
-
-#define DMOV_STATUS(ch)       DMOV_SD3(0x200, ch)
-#define DMOV_STATUS_RSLT_COUNT(n)    (((n) >> 29))
-#define DMOV_STATUS_CMD_COUNT(n)     (((n) >> 27) & 3)
-#define DMOV_STATUS_RSLT_VALID       (1 << 1)
-#define DMOV_STATUS_CMD_PTR_RDY      (1 << 0)
-
-#define DMOV_ISR              DMOV_SD3(0x380, 0)
-
-#define DMOV_CONFIG(ch)       DMOV_SD3(0x300, ch)
-#define DMOV_CONFIG_FORCE_TOP_PTR_RSLT (1 << 2)
-#define DMOV_CONFIG_FORCE_FLUSH_RSLT   (1 << 1)
-#define DMOV_CONFIG_IRQ_EN             (1 << 0)
-
-/* channel assignments */
-
-#define DMOV_NAND_CHAN        7
-#define DMOV_NAND_CRCI_CMD    5
-#define DMOV_NAND_CRCI_DATA   4
-
-#define DMOV_SDC1_CHAN        8
-#define DMOV_SDC1_CRCI        6
-
-#define DMOV_SDC2_CHAN        8
-#define DMOV_SDC2_CRCI        7
-
-#define DMOV_TSIF_CHAN        10
-#define DMOV_TSIF_CRCI        10
-
-#define DMOV_USB_CHAN         11
-
-/* no client rate control ifc (eg, ram) */
-#define DMOV_NONE_CRCI        0
-
-
-/* If the CMD_PTR register has CMD_PTR_LIST selected, the data mover
- * is going to walk a list of 32bit pointers as described below.  Each
- * pointer points to a *array* of dmov_s, etc structs.  The last pointer
- * in the list is marked with CMD_PTR_LP.  The last struct in each array
- * is marked with CMD_LC (see below).
- */
-#define CMD_PTR_ADDR(addr)  ((addr) >> 3)
-#define CMD_PTR_LP          (1 << 31) /* last pointer */
-#define CMD_PTR_PT          (3 << 29) /* ? */
-
-/* Single Item Mode */
-typedef struct {
-        unsigned cmd;
-        unsigned src;
-        unsigned dst;
-        unsigned len;
-} dmov_s;
-
-/* Scatter/Gather Mode */
-typedef struct {
-        unsigned cmd;
-        unsigned src_dscr;
-        unsigned dst_dscr;
-        unsigned _reserved;
-} dmov_sg;
-
-/* bits for the cmd field of the above structures */
-
-#define CMD_LC      (1 << 31)  /* last command */
-#define CMD_FR      (1 << 22)  /* force result -- does not work? */
-#define CMD_OCU     (1 << 21)  /* other channel unblock */
-#define CMD_OCB     (1 << 20)  /* other channel block */
-#define CMD_TCB     (1 << 19)  /* ? */
-#define CMD_DAH     (1 << 18)  /* destination address hold -- does not work?*/
-#define CMD_SAH     (1 << 17)  /* source address hold -- does not work? */
-
-#define CMD_MODE_SINGLE     (0 << 0) /* dmov_s structure used */
-#define CMD_MODE_SG         (1 << 0) /* untested */
-#define CMD_MODE_IND_SG     (2 << 0) /* untested */
-#define CMD_MODE_BOX        (3 << 0) /* untested */
-
-#define CMD_DST_SWAP_BYTES  (1 << 14) /* exchange each byte n with byte n+1 */
-#define CMD_DST_SWAP_SHORTS (1 << 15) /* exchange each short n with short n+1 */
-#define CMD_DST_SWAP_WORDS  (1 << 16) /* exchange each word n with word n+1 */
-
-#define CMD_SRC_SWAP_BYTES  (1 << 11) /* exchange each byte n with byte n+1 */
-#define CMD_SRC_SWAP_SHORTS (1 << 12) /* exchange each short n with short n+1 */
-#define CMD_SRC_SWAP_WORDS  (1 << 13) /* exchange each word n with word n+1 */
-
-#define CMD_DST_CRCI(n)     (((n) & 15) << 7)
-#define CMD_SRC_CRCI(n)     (((n) & 15) << 3)
-
-#endif
diff --git a/include/asm-arm/arch-msm/entry-macro.S b/include/asm-arm/arch-msm/entry-macro.S
deleted file mode 100644
index ee24aece4cb0..000000000000
--- a/include/asm-arm/arch-msm/entry-macro.S
+++ /dev/null
@@ -1,38 +0,0 @@
-/* include/asm-arm/arch-msm7200/entry-macro.S
- *
- * Copyright (C) 2007 Google, Inc.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <asm/arch/msm_iomap.h>
-
-        .macro  disable_fiq
-        .endm
-
-        .macro  get_irqnr_preamble, base, tmp
-        @ enable imprecise aborts
-        cpsie   a
-        mov     \base, #MSM_VIC_BASE
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        @ 0xD0 has irq# or old irq# if the irq has been handled
-        @ 0xD4 has irq# or -1 if none pending *but* if you just
-        @ read 0xD4 you never get the first irq for some reason
-        ldr     \irqnr, [\base, #0xD0]
-        ldr     \irqnr, [\base, #0xD4]
-        cmp     \irqnr, #0xffffffff
-        .endm
diff --git a/include/asm-arm/arch-msm/hardware.h b/include/asm-arm/arch-msm/hardware.h
deleted file mode 100644
index 89af2b70182f..000000000000
--- a/include/asm-arm/arch-msm/hardware.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* linux/include/asm-arm/arch-msm/hardware.h
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ASM_ARCH_MSM_HARDWARE_H
-
-#endif
diff --git a/include/asm-arm/arch-msm/io.h b/include/asm-arm/arch-msm/io.h
deleted file mode 100644
index 4645ae26b62a..000000000000
--- a/include/asm-arm/arch-msm/io.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* include/asm-arm/arch-msm/io.h
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-#define __arch_ioremap __msm_ioremap
-#define __arch_iounmap __iounmap
-
-void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype);
-
-static inline void __iomem *__io(unsigned long addr)
-{
-        return (void __iomem *)addr;
-}
-#define __io(a)         __io(a)
-#define __mem_pci(a)    (a)
-
-#endif
diff --git a/include/asm-arm/arch-msm/irqs.h b/include/asm-arm/arch-msm/irqs.h
deleted file mode 100644
index e62a108b1857..000000000000
--- a/include/asm-arm/arch-msm/irqs.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/* linux/include/asm-arm/arch-msm/irqs.h
- *
- * Copyright (C) 2007 Google, Inc.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ASM_ARCH_MSM_IRQS_H
-#define __ASM_ARCH_MSM_IRQS_H
-
-/* MSM ARM11 Interrupt Numbers */
-/* See 80-VE113-1 A, pp219-221     */
-
-#define INT_A9_M2A_0         0
-#define INT_A9_M2A_1         1
-#define INT_A9_M2A_2         2
-#define INT_A9_M2A_3         3
-#define INT_A9_M2A_4         4
-#define INT_A9_M2A_5         5
-#define INT_A9_M2A_6         6
-#define INT_GP_TIMER_EXP     7
-#define INT_DEBUG_TIMER_EXP  8
-#define INT_UART1            9
-#define INT_UART2            10
-#define INT_UART3            11
-#define INT_UART1_RX         12
-#define INT_UART2_RX         13
-#define INT_UART3_RX         14
-#define INT_USB_OTG          15
-#define INT_MDDI_PRI         16
-#define INT_MDDI_EXT         17
-#define INT_MDDI_CLIENT      18
-#define INT_MDP              19
-#define INT_GRAPHICS         20
-#define INT_ADM_AARM         21
-#define INT_ADSP_A11         22
-#define INT_ADSP_A9_A11      23
-#define INT_SDC1_0           24
-#define INT_SDC1_1           25
-#define INT_SDC2_0           26
-#define INT_SDC2_1           27
-#define INT_KEYSENSE         28
-#define INT_TCHSCRN_SSBI     29
-#define INT_TCHSCRN1         30
-#define INT_TCHSCRN2         31
-
-#define INT_GPIO_GROUP1      (32 + 0)
-#define INT_GPIO_GROUP2      (32 + 1)
-#define INT_PWB_I2C          (32 + 2)
-#define INT_SOFTRESET        (32 + 3)
-#define INT_NAND_WR_ER_DONE  (32 + 4)
-#define INT_NAND_OP_DONE     (32 + 5)
-#define INT_PBUS_ARM11       (32 + 6)
-#define INT_AXI_MPU_SMI      (32 + 7)
-#define INT_AXI_MPU_EBI1     (32 + 8)
-#define INT_AD_HSSD          (32 + 9)
-#define INT_ARM11_PMU        (32 + 10)
-#define INT_ARM11_DMA        (32 + 11)
-#define INT_TSIF_IRQ         (32 + 12)
-#define INT_UART1DM_IRQ      (32 + 13)
-#define INT_UART1DM_RX       (32 + 14)
-#define INT_USB_HS           (32 + 15)
-#define INT_SDC3_0           (32 + 16)
-#define INT_SDC3_1           (32 + 17)
-#define INT_SDC4_0           (32 + 18)
-#define INT_SDC4_1           (32 + 19)
-#define INT_UART2DM_RX       (32 + 20)
-#define INT_UART2DM_IRQ      (32 + 21)
-
-/* 22-31 are reserved */
-
-#define MSM_IRQ_BIT(irq)     (1 << ((irq) & 31))
-
-#define NR_MSM_IRQS 64
-#define NR_GPIO_IRQS 122
-#define NR_BOARD_IRQS 64
-#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS)
-
-#define MSM_GPIO_TO_INT(n) (NR_MSM_IRQS + (n))
-
-#endif
diff --git a/include/asm-arm/arch-msm/memory.h b/include/asm-arm/arch-msm/memory.h
deleted file mode 100644
index b5ce0e9ac86d..000000000000
--- a/include/asm-arm/arch-msm/memory.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* linux/include/asm-arm/arch-msm/memory.h
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-/* physical offset of RAM */
-#define PHYS_OFFSET             UL(0x10000000)
-
-/* bus address and physical addresses are identical */
-#define __virt_to_bus(x)        __virt_to_phys(x)
-#define __bus_to_virt(x)        __phys_to_virt(x)
-
-#endif
-
diff --git a/include/asm-arm/arch-msm/msm_iomap.h b/include/asm-arm/arch-msm/msm_iomap.h
deleted file mode 100644
index b8955cc26fec..000000000000
--- a/include/asm-arm/arch-msm/msm_iomap.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/* linux/include/asm-arm/arch-msm/msm_iomap.h
- *
- * Copyright (C) 2007 Google, Inc.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- *
- * The MSM peripherals are spread all over across 768MB of physical
- * space, which makes just having a simple IO_ADDRESS macro to slide
- * them into the right virtual location rough.  Instead, we will
- * provide a master phys->virt mapping for peripherals here.
- *
- */
-
-#ifndef __ASM_ARCH_MSM_IOMAP_H
-#define __ASM_ARCH_MSM_IOMAP_H
-
-#include <asm/sizes.h>
-
-/* Physical base address and size of peripherals.
- * Ordered by the virtual base addresses they will be mapped at.
- *
- * MSM_VIC_BASE must be an value that can be loaded via a "mov"
- * instruction, otherwise entry-macro.S will not compile.
- *
- * If you add or remove entries here, you'll want to edit the
- * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
- * changes.
- *
- */
-
-#define MSM_VIC_BASE          0xE0000000
-#define MSM_VIC_PHYS          0xC0000000
-#define MSM_VIC_SIZE          SZ_4K
-
-#define MSM_CSR_BASE          0xE0001000
-#define MSM_CSR_PHYS          0xC0100000
-#define MSM_CSR_SIZE          SZ_4K
-
-#define MSM_GPT_PHYS          MSM_CSR_PHYS
-#define MSM_GPT_BASE          MSM_CSR_BASE
-#define MSM_GPT_SIZE          SZ_4K
-
-#define MSM_DMOV_BASE         0xE0002000
-#define MSM_DMOV_PHYS         0xA9700000
-#define MSM_DMOV_SIZE         SZ_4K
-
-#define MSM_UART1_BASE        0xE0003000
-#define MSM_UART1_PHYS        0xA9A00000
-#define MSM_UART1_SIZE        SZ_4K
-
-#define MSM_UART2_BASE        0xE0004000
-#define MSM_UART2_PHYS        0xA9B00000
-#define MSM_UART2_SIZE        SZ_4K
-
-#define MSM_UART3_BASE        0xE0005000
-#define MSM_UART3_PHYS        0xA9C00000
-#define MSM_UART3_SIZE        SZ_4K
-
-#define MSM_I2C_BASE          0xE0006000
-#define MSM_I2C_PHYS          0xA9900000
-#define MSM_I2C_SIZE          SZ_4K
-
-#define MSM_GPIO1_BASE        0xE0007000
-#define MSM_GPIO1_PHYS        0xA9200000
-#define MSM_GPIO1_SIZE        SZ_4K
-
-#define MSM_GPIO2_BASE        0xE0008000
-#define MSM_GPIO2_PHYS        0xA9300000
-#define MSM_GPIO2_SIZE        SZ_4K
-
-#define MSM_HSUSB_BASE        0xE0009000
-#define MSM_HSUSB_PHYS        0xA0800000
-#define MSM_HSUSB_SIZE        SZ_4K
-
-#define MSM_CLK_CTL_BASE      0xE000A000
-#define MSM_CLK_CTL_PHYS      0xA8600000
-#define MSM_CLK_CTL_SIZE      SZ_4K
-
-#define MSM_PMDH_BASE         0xE000B000
-#define MSM_PMDH_PHYS         0xAA600000
-#define MSM_PMDH_SIZE         SZ_4K
-
-#define MSM_EMDH_BASE         0xE000C000
-#define MSM_EMDH_PHYS         0xAA700000
-#define MSM_EMDH_SIZE         SZ_4K
-
-#define MSM_MDP_BASE          0xE0010000
-#define MSM_MDP_PHYS          0xAA200000
-#define MSM_MDP_SIZE          0x000F0000
-
-#define MSM_SHARED_RAM_BASE   0xE0100000
-#define MSM_SHARED_RAM_PHYS   0x01F00000
-#define MSM_SHARED_RAM_SIZE   SZ_1M
-
-#endif
diff --git a/include/asm-arm/arch-msm/system.h b/include/asm-arm/arch-msm/system.h
deleted file mode 100644
index fb31b3aa6750..000000000000
--- a/include/asm-arm/arch-msm/system.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* linux/include/asm-arm/arch-msm/system.h
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <asm/arch/hardware.h>
-
-void arch_idle(void);
-
-static inline void arch_reset(char mode)
-{
-        for (;;) ;  /* depends on IPC w/ other core */
-}
diff --git a/include/asm-arm/arch-msm/timex.h b/include/asm-arm/arch-msm/timex.h
deleted file mode 100644
index 8724487ab4c9..000000000000
--- a/include/asm-arm/arch-msm/timex.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* linux/include/asm-arm/arch-msm/timex.h
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ASM_ARCH_MSM_TIMEX_H
-#define __ASM_ARCH_MSM_TIMEX_H
-
-#define CLOCK_TICK_RATE         1000000
-
-#endif
diff --git a/include/asm-arm/arch-msm/uncompress.h b/include/asm-arm/arch-msm/uncompress.h
deleted file mode 100644
index e91ed786ffec..000000000000
--- a/include/asm-arm/arch-msm/uncompress.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* linux/include/asm-arm/arch-msm/uncompress.h
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ASM_ARCH_MSM_UNCOMPRESS_H
-
-#include "hardware.h"
-
-static void putc(int c)
-{
-}
-
-static inline void flush(void)
-{
-}
-
-static inline void arch_decomp_setup(void)
-{
-}
-
-static inline void arch_decomp_wdog(void)
-{
-}
-
-#endif
diff --git a/include/asm-arm/arch-msm/vmalloc.h b/include/asm-arm/arch-msm/vmalloc.h
deleted file mode 100644
index 60f8d910e825..000000000000
--- a/include/asm-arm/arch-msm/vmalloc.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* linux/include/asm-arm/arch-msm/vmalloc.h
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ASM_ARCH_MSM_VMALLOC_H
-#define __ASM_ARCH_MSM_VMALLOC_H
-
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
-
-#endif
-
diff --git a/include/asm-arm/arch-mv78xx0/debug-macro.S b/include/asm-arm/arch-mv78xx0/debug-macro.S
deleted file mode 100644
index d0595bd645e5..000000000000
--- a/include/asm-arm/arch-mv78xx0/debug-macro.S
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * include/asm-arm/arch-mv78xx0/debug-macro.S
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <asm/arch/mv78xx0.h>
-
-        .macro  addruart,rx
-        mrc     p15, 0, \rx, c1, c0
-        tst     \rx, #1                                 @ MMU enabled?
-        ldreq   \rx, =MV78XX0_REGS_PHYS_BASE
-        ldrne   \rx, =MV78XX0_REGS_VIRT_BASE
-        orr     \rx, \rx, #0x00012000
-        .endm
-
-#define UART_SHIFT      2
-#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-mv78xx0/entry-macro.S b/include/asm-arm/arch-mv78xx0/entry-macro.S
deleted file mode 100644
index e9a606b12669..000000000000
--- a/include/asm-arm/arch-mv78xx0/entry-macro.S
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * include/asm-arm/arch-mv78xx0/entry-macro.S
- *
- * Low-level IRQ helper macros for Marvell MV78xx0 platforms
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/arch/mv78xx0.h>
-
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
-        .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =IRQ_VIRT_BASE
-        .endm
-
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        @ check low interrupts
-        ldr     \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
-        ldr     \tmp, [\base, #IRQ_MASK_LOW_OFF]
-        mov     \irqnr, #31
-        ands    \irqstat, \irqstat, \tmp
-
-        @ if no low interrupts set, check high interrupts
-        ldreq   \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
-        ldreq   \tmp, [\base, #IRQ_MASK_HIGH_OFF]
-        moveq   \irqnr, #63
-        andeqs  \irqstat, \irqstat, \tmp
-
-        @ find first active interrupt source
-        clzne   \irqstat, \irqstat
-        subne   \irqnr, \irqnr, \irqstat
-        .endm
diff --git a/include/asm-arm/arch-mv78xx0/hardware.h b/include/asm-arm/arch-mv78xx0/hardware.h
deleted file mode 100644
index 8e17926086c6..000000000000
--- a/include/asm-arm/arch-mv78xx0/hardware.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * include/asm-arm/arch-mv78xx0/hardware.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include "mv78xx0.h"
-
-#define pcibios_assign_all_busses()     1
-
-#define PCIBIOS_MIN_IO                  0x00001000
-#define PCIBIOS_MIN_MEM                 0x01000000
-#define PCIMEM_BASE                     MV78XX0_PCIE_MEM_PHYS_BASE /* mem base for VGA */
-
-
-#endif
diff --git a/include/asm-arm/arch-mv78xx0/io.h b/include/asm-arm/arch-mv78xx0/io.h
deleted file mode 100644
index 415d4c98e3d1..000000000000
--- a/include/asm-arm/arch-mv78xx0/io.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * include/asm-arm/arch-mv78xx0/io.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#include "mv78xx0.h"
-
-#define IO_SPACE_LIMIT          0xffffffff
-
-static inline void __iomem *__io(unsigned long addr)
-{
-        return (void __iomem *)((addr - MV78XX0_PCIE_IO_PHYS_BASE(0))
-                                        + MV78XX0_PCIE_IO_VIRT_BASE(0));
-}
-
-#define __io(a)                 __io(a)
-#define __mem_pci(a)            (a)
-
-
-#endif
diff --git a/include/asm-arm/arch-mv78xx0/irqs.h b/include/asm-arm/arch-mv78xx0/irqs.h
deleted file mode 100644
index 75930450cd65..000000000000
--- a/include/asm-arm/arch-mv78xx0/irqs.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * include/asm-arm/arch-mv78xx0/irqs.h
- *
- * IRQ definitions for Marvell MV78xx0 SoCs
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H
-
-#include "mv78xx0.h"    /* need GPIO_MAX */
-
-/*
- * MV78xx0 Low Interrupt Controller
- */
-#define IRQ_MV78XX0_ERR         0
-#define IRQ_MV78XX0_SPI         1
-#define IRQ_MV78XX0_I2C_0       2
-#define IRQ_MV78XX0_I2C_1       3
-#define IRQ_MV78XX0_IDMA_0      4
-#define IRQ_MV78XX0_IDMA_1      5
-#define IRQ_MV78XX0_IDMA_2      6
-#define IRQ_MV78XX0_IDMA_3      7
-#define IRQ_MV78XX0_TIMER_0     8
-#define IRQ_MV78XX0_TIMER_1     9
-#define IRQ_MV78XX0_TIMER_2     10
-#define IRQ_MV78XX0_TIMER_3     11
-#define IRQ_MV78XX0_UART_0      12
-#define IRQ_MV78XX0_UART_1      13
-#define IRQ_MV78XX0_UART_2      14
-#define IRQ_MV78XX0_UART_3      15
-#define IRQ_MV78XX0_USB_0       16
-#define IRQ_MV78XX0_USB_1       17
-#define IRQ_MV78XX0_USB_2       18
-#define IRQ_MV78XX0_CRYPTO      19
-#define IRQ_MV78XX0_SDIO_0      20
-#define IRQ_MV78XX0_SDIO_1      21
-#define IRQ_MV78XX0_XOR_0       22
-#define IRQ_MV78XX0_XOR_1       23
-#define IRQ_MV78XX0_I2S_0       24
-#define IRQ_MV78XX0_I2S_1       25
-#define IRQ_MV78XX0_SATA        26
-#define IRQ_MV78XX0_TDMI        27
-
-/*
- * MV78xx0 High Interrupt Controller
- */
-#define IRQ_MV78XX0_PCIE_00     32
-#define IRQ_MV78XX0_PCIE_01     33
-#define IRQ_MV78XX0_PCIE_02     34
-#define IRQ_MV78XX0_PCIE_03     35
-#define IRQ_MV78XX0_PCIE_10     36
-#define IRQ_MV78XX0_PCIE_11     37
-#define IRQ_MV78XX0_PCIE_12     38
-#define IRQ_MV78XX0_PCIE_13     39
-#define IRQ_MV78XX0_GE00_SUM    40
-#define IRQ_MV78XX0_GE00_RX     41
-#define IRQ_MV78XX0_GE00_TX     42
-#define IRQ_MV78XX0_GE00_MISC   43
-#define IRQ_MV78XX0_GE01_SUM    44
-#define IRQ_MV78XX0_GE01_RX     45
-#define IRQ_MV78XX0_GE01_TX     46
-#define IRQ_MV78XX0_GE01_MISC   47
-#define IRQ_MV78XX0_GE10_SUM    48
-#define IRQ_MV78XX0_GE10_RX     49
-#define IRQ_MV78XX0_GE10_TX     50
-#define IRQ_MV78XX0_GE10_MISC   51
-#define IRQ_MV78XX0_GE11_SUM    52
-#define IRQ_MV78XX0_GE11_RX     53
-#define IRQ_MV78XX0_GE11_TX     54
-#define IRQ_MV78XX0_GE11_MISC   55
-#define IRQ_MV78XX0_GPIO_0_7    56
-#define IRQ_MV78XX0_GPIO_8_15   57
-#define IRQ_MV78XX0_GPIO_16_23  58
-#define IRQ_MV78XX0_GPIO_24_31  59
-#define IRQ_MV78XX0_DB_IN       60
-#define IRQ_MV78XX0_DB_OUT      61
-
-/*
- * MV78XX0 General Purpose Pins
- */
-#define IRQ_MV78XX0_GPIO_START  64
-#define NR_GPIO_IRQS            GPIO_MAX
-
-#define NR_IRQS                 (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS)
-
-
-#endif
diff --git a/include/asm-arm/arch-mv78xx0/memory.h b/include/asm-arm/arch-mv78xx0/memory.h
deleted file mode 100644
index 721a6b185b91..000000000000
--- a/include/asm-arm/arch-mv78xx0/memory.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * include/asm-arm/arch-mv78xx0/memory.h
- */
-
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-#define PHYS_OFFSET             UL(0x00000000)
-
-#define __virt_to_bus(x)        __virt_to_phys(x)
-#define __bus_to_virt(x)        __phys_to_virt(x)
-
-
-#endif
diff --git a/include/asm-arm/arch-mv78xx0/mv78xx0.h b/include/asm-arm/arch-mv78xx0/mv78xx0.h
deleted file mode 100644
index 9f5d83c73faa..000000000000
--- a/include/asm-arm/arch-mv78xx0/mv78xx0.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * include/asm-arm/arch-mv78xx0/mv78xx0.h
- *
- * Generic definitions for Marvell MV78xx0 SoC flavors:
- *  MV781x0 and MV782x0.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_MV78XX0_H
-#define __ASM_ARCH_MV78XX0_H
-
-/*
- * Marvell MV78xx0 address maps.
- *
- * phys
- * c0000000     PCIe Memory space
- * f0800000     PCIe #0 I/O space
- * f0900000     PCIe #1 I/O space
- * f0a00000     PCIe #2 I/O space
- * f0b00000     PCIe #3 I/O space
- * f0c00000     PCIe #4 I/O space
- * f0d00000     PCIe #5 I/O space
- * f0e00000     PCIe #6 I/O space
- * f0f00000     PCIe #7 I/O space
- * f1000000     on-chip peripheral registers
- *
- * virt         phys            size
- * fe400000     f102x000        16K     core-specific peripheral registers
- * fe700000     f0800000        1M      PCIe #0 I/O space
- * fe800000     f0900000        1M      PCIe #1 I/O space
- * fe900000     f0a00000        1M      PCIe #2 I/O space
- * fea00000     f0b00000        1M      PCIe #3 I/O space
- * feb00000     f0c00000        1M      PCIe #4 I/O space
- * fec00000     f0d00000        1M      PCIe #5 I/O space
- * fed00000     f0e00000        1M      PCIe #6 I/O space
- * fee00000     f0f00000        1M      PCIe #7 I/O space
- * fef00000     f1000000        1M      on-chip peripheral registers
- */
-#define MV78XX0_CORE0_REGS_PHYS_BASE    0xf1020000
-#define MV78XX0_CORE1_REGS_PHYS_BASE    0xf1024000
-#define MV78XX0_CORE_REGS_VIRT_BASE     0xfe400000
-#define MV78XX0_CORE_REGS_SIZE          SZ_16K
-
-#define MV78XX0_PCIE_IO_PHYS_BASE(i)    (0xf0800000 + ((i) << 20))
-#define MV78XX0_PCIE_IO_VIRT_BASE(i)    (0xfe700000 + ((i) << 20))
-#define MV78XX0_PCIE_IO_SIZE            SZ_1M
-
-#define MV78XX0_REGS_PHYS_BASE          0xf1000000
-#define MV78XX0_REGS_VIRT_BASE          0xfef00000
-#define MV78XX0_REGS_SIZE               SZ_1M
-
-#define MV78XX0_PCIE_MEM_PHYS_BASE      0xc0000000
-#define MV78XX0_PCIE_MEM_SIZE           0x30000000
-
-/*
- * Core-specific peripheral registers.
- */
-#define BRIDGE_VIRT_BASE        (MV78XX0_CORE_REGS_VIRT_BASE)
-#define  CPU_CONTROL            (BRIDGE_VIRT_BASE | 0x0104)
-#define   L2_WRITETHROUGH       0x00020000
-#define  RSTOUTn_MASK           (BRIDGE_VIRT_BASE | 0x0108)
-#define   SOFT_RESET_OUT_EN     0x00000004
-#define  SYSTEM_SOFT_RESET      (BRIDGE_VIRT_BASE | 0x010c)
-#define   SOFT_RESET            0x00000001
-#define  BRIDGE_CAUSE           (BRIDGE_VIRT_BASE | 0x0110)
-#define  BRIDGE_MASK            (BRIDGE_VIRT_BASE | 0x0114)
-#define   BRIDGE_INT_TIMER0     0x0002
-#define   BRIDGE_INT_TIMER1     0x0004
-#define   BRIDGE_INT_TIMER1_CLR (~0x0004)
-#define  IRQ_VIRT_BASE          (BRIDGE_VIRT_BASE | 0x0200)
-#define   IRQ_CAUSE_LOW_OFF     0x0004
-#define   IRQ_CAUSE_HIGH_OFF    0x0008
-#define   IRQ_MASK_LOW_OFF      0x0010
-#define   IRQ_MASK_HIGH_OFF     0x0014
-#define  TIMER_VIRT_BASE        (BRIDGE_VIRT_BASE | 0x0300)
-
-/*
- * Register Map
- */
-#define DDR_VIRT_BASE           (MV78XX0_REGS_VIRT_BASE | 0x00000)
-#define  DDR_WINDOW_CPU0_BASE   (DDR_VIRT_BASE | 0x1500)
-#define  DDR_WINDOW_CPU1_BASE   (DDR_VIRT_BASE | 0x1700)
-
-#define DEV_BUS_PHYS_BASE       (MV78XX0_REGS_PHYS_BASE | 0x10000)
-#define DEV_BUS_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE | 0x10000)
-#define  SAMPLE_AT_RESET_LOW    (DEV_BUS_VIRT_BASE | 0x0030)
-#define  SAMPLE_AT_RESET_HIGH   (DEV_BUS_VIRT_BASE | 0x0034)
-#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2000)
-#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2000)
-#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2100)
-#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2100)
-#define  UART2_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2200)
-#define  UART2_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2200)
-#define  UART3_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2300)
-#define  UART3_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2300)
-
-#define GE10_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x30000)
-#define GE11_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x34000)
-
-#define PCIE00_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x40000)
-#define PCIE01_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x44000)
-#define PCIE02_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x48000)
-#define PCIE03_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x4c000)
-
-#define USB0_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x50000)
-#define USB1_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x51000)
-#define USB2_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x52000)
-
-#define GE00_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x70000)
-#define GE01_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x74000)
-
-#define PCIE10_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x80000)
-#define PCIE11_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x84000)
-#define PCIE12_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x88000)
-#define PCIE13_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x8c000)
-
-#define SATA_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0xa0000)
-
-
-#define GPIO_MAX                32
-
-
-#endif
diff --git a/include/asm-arm/arch-mv78xx0/system.h b/include/asm-arm/arch-mv78xx0/system.h
deleted file mode 100644
index 7eb47d376db9..000000000000
--- a/include/asm-arm/arch-mv78xx0/system.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * include/asm-arm/arch-mv78xx0/system.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/mv78xx0.h>
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-static inline void arch_reset(char mode)
-{
-        /*
-         * Enable soft reset to assert RSTOUTn.
-         */
-        writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
-
-        /*
-         * Assert soft reset.
-         */
-        writel(SOFT_RESET, SYSTEM_SOFT_RESET);
-
-        while (1)
-                ;
-}
-
-
-#endif
diff --git a/include/asm-arm/arch-mv78xx0/timex.h b/include/asm-arm/arch-mv78xx0/timex.h
deleted file mode 100644
index a854b1ccbd01..000000000000
--- a/include/asm-arm/arch-mv78xx0/timex.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * include/asm-arm/arch-mv78xx0/timex.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#define CLOCK_TICK_RATE         (100 * HZ)
diff --git a/include/asm-arm/arch-mv78xx0/uncompress.h b/include/asm-arm/arch-mv78xx0/uncompress.h
deleted file mode 100644
index 3bfe0a293ef7..000000000000
--- a/include/asm-arm/arch-mv78xx0/uncompress.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * include/asm-arm/arch-mv78xx0/uncompress.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/serial_reg.h>
-#include <asm/arch/mv78xx0.h>
-
-#define SERIAL_BASE     ((unsigned char *)UART0_PHYS_BASE)
-
-static void putc(const char c)
-{
-        unsigned char *base = SERIAL_BASE;
-        int i;
-
-        for (i = 0; i < 0x1000; i++) {
-                if (base[UART_LSR << 2] & UART_LSR_THRE)
-                        break;
-                barrier();
-        }
-
-        base[UART_TX << 2] = c;
-}
-
-static void flush(void)
-{
-        unsigned char *base = SERIAL_BASE;
-        unsigned char mask;
-        int i;
-
-        mask = UART_LSR_TEMT | UART_LSR_THRE;
-
-        for (i = 0; i < 0x1000; i++) {
-                if ((base[UART_LSR << 2] & mask) == mask)
-                        break;
-                barrier();
-        }
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-mv78xx0/vmalloc.h b/include/asm-arm/arch-mv78xx0/vmalloc.h
deleted file mode 100644
index f2c512197579..000000000000
--- a/include/asm-arm/arch-mv78xx0/vmalloc.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * include/asm-arm/arch-mv78xx0/vmalloc.h
- */
-
-#define VMALLOC_END     0xfe000000
diff --git a/include/asm-arm/arch-mxc/debug-macro.S b/include/asm-arm/arch-mxc/debug-macro.S
deleted file mode 100644
index 575087f8561a..000000000000
--- a/include/asm-arm/arch-mxc/debug-macro.S
+++ /dev/null
@@ -1,49 +0,0 @@
-/* linux/include/asm-arm/arch-imx/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <asm/arch/hardware.h>
-
-#ifdef CONFIG_MACH_MX31ADS
-#include <asm/arch/board-mx31ads.h>
-#endif
-#ifdef CONFIG_MACH_PCM037
-#include <asm/arch/board-pcm037.h>
-#endif
-#ifdef CONFIG_MACH_MX31LITE
-#include <asm/arch/board-mx31lite.h>
-#endif
-#ifdef CONFIG_MACH_MX27ADS
-#include <asm/arch/board-mx27ads.h>
-#endif
-#ifdef CONFIG_MACH_PCM038
-#include <asm/arch/board-pcm038.h>
-#endif
-                .macro  addruart,rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                ldreq   \rx, =MXC_LL_UART_PADDR @ physical
-                ldrne   \rx, =MXC_LL_UART_VADDR @ virtual
-                .endm
-
-                .macro  senduart,rd,rx
-                str     \rd, [\rx, #0x40]       @ TXDATA
-                .endm
-
-                .macro  waituart,rd,rx
-                .endm
-
-                .macro  busyuart,rd,rx
-1002:           ldr     \rd, [\rx, #0x98]       @ SR2
-                tst     \rd, #1 << 3            @ TXDC
-                beq     1002b                   @ wait until transmit done
-                .endm
diff --git a/include/asm-arm/arch-mxc/gpio.h b/include/asm-arm/arch-mxc/gpio.h
deleted file mode 100644
index 5f13a65e4044..000000000000
--- a/include/asm-arm/arch-mxc/gpio.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- */
-
-#ifndef __ASM_ARCH_MXC_GPIO_H__
-#define __ASM_ARCH_MXC_GPIO_H__
-
-#include <asm/arch/hardware.h>
-#include <asm-generic/gpio.h>
-
-/* use gpiolib dispatchers */
-#define gpio_get_value          __gpio_get_value
-#define gpio_set_value          __gpio_set_value
-#define gpio_cansleep           __gpio_cansleep
-
-#define gpio_to_irq(gpio)       (MXC_MAX_INT_LINES + (gpio))
-#define irq_to_gpio(irq)        ((irq) - MXC_MAX_INT_LINES)
-
-struct mxc_gpio_port {
-        void __iomem *base;
-        int irq;
-        int virtual_irq_start;
-        struct gpio_chip chip;
-};
-
-int mxc_gpio_init(struct mxc_gpio_port*, int);
-
-#endif
diff --git a/include/asm-arm/arch-mxc/hardware.h b/include/asm-arm/arch-mxc/hardware.h
deleted file mode 100644
index 37cddbaaade7..000000000000
--- a/include/asm-arm/arch-mxc/hardware.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA  02110-1301, USA.
- */
-
-#ifndef __ASM_ARCH_MXC_HARDWARE_H__
-#define __ASM_ARCH_MXC_HARDWARE_H__
-
-#include <asm/sizes.h>
-
-#ifdef CONFIG_ARCH_MX3
-# include <asm/arch/mx31.h>
-#endif
-
-#ifdef CONFIG_ARCH_MX2
-# ifdef CONFIG_MACH_MX27
-#  include <asm/arch/mx27.h>
-# endif
-#endif
-
-#include <asm/arch/mxc.h>
-
-#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/include/asm-arm/arch-mxc/irqs.h b/include/asm-arm/arch-mxc/irqs.h
deleted file mode 100644
index 21411efc10fb..000000000000
--- a/include/asm-arm/arch-mxc/irqs.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MXC_IRQS_H__
-#define __ASM_ARCH_MXC_IRQS_H__
-
-#include <asm/arch/hardware.h>
-
-#endif /* __ASM_ARCH_MXC_IRQS_H__ */
diff --git a/include/asm-arm/arch-mxc/memory.h b/include/asm-arm/arch-mxc/memory.h
deleted file mode 100644
index 7e669ee0d634..000000000000
--- a/include/asm-arm/arch-mxc/memory.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MXC_MEMORY_H__
-#define __ASM_ARCH_MXC_MEMORY_H__
-
-#include <asm/arch/hardware.h>
-
-/*
- * Virtual view <-> DMA view memory address translations
- * This macro is used to translate the virtual address to an address
- * suitable to be passed to set_dma_addr()
- */
-#define __virt_to_bus(a)        __virt_to_phys(a)
-
-/*
- * Used to convert an address for DMA operations to an address that the
- * kernel can use.
- */
-#define __bus_to_virt(a)        __phys_to_virt(a)
-
-#endif /* __ASM_ARCH_MXC_MEMORY_H__ */
diff --git a/include/asm-arm/arch-mxc/mxc_timer.h b/include/asm-arm/arch-mxc/mxc_timer.h
deleted file mode 100644
index 5439fa6cf615..000000000000
--- a/include/asm-arm/arch-mxc/mxc_timer.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * mxc_timer.h
- *
- * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
- *
- * Platform independent (i.MX1, i.MX2, i.MX3) definition for timer handling.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor,
- * Boston, MA  02110-1301, USA.
- */
-
-#ifndef __PLAT_MXC_TIMER_H
-#define __PLAT_MXC_TIMER_H
-
-#include <linux/clk.h>
-#include <asm/arch/hardware.h>
-
-#ifdef CONFIG_ARCH_IMX
-#define TIMER_BASE              IO_ADDRESS(TIM1_BASE_ADDR)
-#define TIMER_INTERRUPT         TIM1_INT
-
-#define TCTL_VAL                TCTL_CLK_PCLK1
-#define TCTL_IRQEN              (1<<4)
-#define TCTL_FRR                (1<<8)
-#define TCTL_CLK_PCLK1          (1<<1)
-#define TCTL_CLK_PCLK1_4        (2<<1)
-#define TCTL_CLK_TIN            (3<<1)
-#define TCTL_CLK_32             (4<<1)
-
-#define MXC_TCTL   0x00
-#define MXC_TPRER  0x04
-#define MXC_TCMP   0x08
-#define MXC_TCR    0x0c
-#define MXC_TCN    0x10
-#define MXC_TSTAT  0x14
-#define TSTAT_CAPT              (1<<1)
-#define TSTAT_COMP              (1<<0)
-
-static inline void gpt_irq_disable(void)
-{
-        unsigned int tmp;
-
-        tmp = __raw_readl(TIMER_BASE + MXC_TCTL);
-        __raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL);
-}
-
-static inline void gpt_irq_enable(void)
-{
-        __raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN,
-                                TIMER_BASE + MXC_TCTL);
-}
-
-static void gpt_irq_acknowledge(void)
-{
-        __raw_writel(0, TIMER_BASE + MXC_TSTAT);
-}
-#endif /* CONFIG_ARCH_IMX */
-
-#ifdef CONFIG_ARCH_MX2
-#define TIMER_BASE              IO_ADDRESS(GPT1_BASE_ADDR)
-#define TIMER_INTERRUPT         MXC_INT_GPT1
-
-#define MXC_TCTL   0x00
-#define TCTL_VAL                TCTL_CLK_PCLK1
-#define TCTL_CLK_PCLK1          (1<<1)
-#define TCTL_CLK_PCLK1_4        (2<<1)
-#define TCTL_IRQEN              (1<<4)
-#define TCTL_FRR                (1<<8)
-#define MXC_TPRER  0x04
-#define MXC_TCMP   0x08
-#define MXC_TCR    0x0c
-#define MXC_TCN    0x10
-#define MXC_TSTAT  0x14
-#define TSTAT_CAPT              (1<<1)
-#define TSTAT_COMP              (1<<0)
-
-static inline void gpt_irq_disable(void)
-{
-        unsigned int tmp;
-
-        tmp = __raw_readl(TIMER_BASE + MXC_TCTL);
-        __raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL);
-}
-
-static inline void gpt_irq_enable(void)
-{
-        __raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN,
-                                TIMER_BASE + MXC_TCTL);
-}
-
-static void gpt_irq_acknowledge(void)
-{
-        __raw_writel(TSTAT_CAPT | TSTAT_COMP, TIMER_BASE + MXC_TSTAT);
-}
-#endif /* CONFIG_ARCH_MX2 */
-
-#ifdef CONFIG_ARCH_MX3
-#define TIMER_BASE              IO_ADDRESS(GPT1_BASE_ADDR)
-#define TIMER_INTERRUPT         MXC_INT_GPT
-
-#define MXC_TCTL   0x00
-#define TCTL_VAL                (TCTL_CLK_IPG | TCTL_WAITEN)
-#define TCTL_CLK_IPG            (1<<6)
-#define TCTL_FRR                (1<<9)
-#define TCTL_WAITEN             (1<<3)
-
-#define MXC_TPRER  0x04
-#define MXC_TSTAT  0x08
-#define TSTAT_OF1               (1<<0)
-#define TSTAT_OF2               (1<<1)
-#define TSTAT_OF3               (1<<2)
-#define TSTAT_IF1               (1<<3)
-#define TSTAT_IF2               (1<<4)
-#define TSTAT_ROV               (1<<5)
-#define MXC_IR     0x0c
-#define MXC_TCMP   0x10
-#define MXC_TCMP2  0x14
-#define MXC_TCMP3  0x18
-#define MXC_TCR    0x1c
-#define MXC_TCN    0x24
-
-static inline void gpt_irq_disable(void)
-{
-        __raw_writel(0, TIMER_BASE + MXC_IR);
-}
-
-static inline void gpt_irq_enable(void)
-{
-        __raw_writel(1<<0, TIMER_BASE + MXC_IR);
-}
-
-static inline void gpt_irq_acknowledge(void)
-{
-        __raw_writel(TSTAT_OF1, TIMER_BASE + MXC_TSTAT);
-}
-#endif /* CONFIG_ARCH_MX3 */
-
-#define TCTL_SWR                (1<<15)
-#define TCTL_CC                 (1<<10)
-#define TCTL_OM                 (1<<9)
-#define TCTL_CAP_RIS            (1<<6)
-#define TCTL_CAP_FAL            (2<<6)
-#define TCTL_CAP_RIS_FAL        (3<<6)
-#define TCTL_CAP_ENA            (1<<5)
-#define TCTL_TEN                (1<<0)
-
-#endif
diff --git a/include/asm-arm/arch-mxc/timex.h b/include/asm-arm/arch-mxc/timex.h
deleted file mode 100644
index 432e0c84c509..000000000000
--- a/include/asm-arm/arch-mxc/timex.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- *  Copyright (C) 1999 ARM Limited
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __ASM_ARCH_MXC_TIMEX_H__
-#define __ASM_ARCH_MXC_TIMEX_H__
-
-#include <asm/arch/hardware.h>  /* for CLOCK_TICK_RATE */
-
-#endif                          /* __ASM_ARCH_MXC_TIMEX_H__ */
diff --git a/include/asm-arm/arch-mxc/uncompress.h b/include/asm-arm/arch-mxc/uncompress.h
deleted file mode 100644
index 18f33b0cdeb2..000000000000
--- a/include/asm-arm/arch-mxc/uncompress.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- *  include/asm-arm/arch-mxc/uncompress.h
- *
- *
- *
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) Shane Nay (shane@minirl.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__
-#define __ASM_ARCH_MXC_UNCOMPRESS_H__
-
-#define __MXC_BOOT_UNCOMPRESS
-
-#include <asm/arch/hardware.h>
-
-#define UART(x) (*(volatile unsigned long *)(serial_port + (x)))
-
-#define USR2 0x98
-#define USR2_TXFE (1<<14)
-#define TXR  0x40
-#define UCR1 0x80
-#define UCR1_UARTEN 1
-
-/*
- * The following code assumes the serial port has already been
- * initialized by the bootloader.  We search for the first enabled
- * port in the most probable order.  If you didn't setup a port in
- * your bootloader then nothing will appear (which might be desired).
- *
- * This does not append a newline
- */
-
-static void putc(int ch)
-{
-        static unsigned long serial_port = 0;
-
-        if (unlikely(serial_port == 0)) {
-                do {
-                        serial_port = UART1_BASE_ADDR;
-                        if (UART(UCR1) & UCR1_UARTEN)
-                                break;
-                        serial_port = UART2_BASE_ADDR;
-                        if (UART(UCR1) & UCR1_UARTEN)
-                                break;
-                        return;
-                } while (0);
-        }
-
-        while (!(UART(USR2) & USR2_TXFE))
-                barrier();
-
-        UART(TXR) = ch;
-}
-
-#define flush() do { } while (0)
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-
-#define arch_decomp_wdog()
-
-#endif                          /* __ASM_ARCH_MXC_UNCOMPRESS_H__ */
diff --git a/include/asm-arm/arch-netx/debug-macro.S b/include/asm-arm/arch-netx/debug-macro.S
deleted file mode 100644
index a940d0e80cb2..000000000000
--- a/include/asm-arm/arch-netx/debug-macro.S
+++ /dev/null
@@ -1,38 +0,0 @@
-/* linux/include/asm-arm/arch-netx/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-#include "hardware.h"
-
-                .macro  addruart,rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx, #0x00100000                @ physical
-                movne   \rx, #io_p2v(0x00100000)        @ virtual
-                orr     \rx, \rx, #0x00000a00
-                .endm
-
-                .macro  senduart,rd,rx
-                str     \rd, [\rx, #0]
-                .endm
-
-                .macro  busyuart,rd,rx
-1002:           ldr     \rd, [\rx, #0x18]
-                tst     \rd, #(1 << 3)
-                bne     1002b
-                .endm
-
-                .macro  waituart,rd,rx
-1001:           ldr     \rd, [\rx, #0x18]
-                tst     \rd, #(1 << 3)
-                bne     1001b
-                .endm
diff --git a/include/asm-arm/arch-netx/dma.h b/include/asm-arm/arch-netx/dma.h
deleted file mode 100644
index 4eda5feed81c..000000000000
--- a/include/asm-arm/arch-netx/dma.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-netx/dma.h
- *
- * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#define MAX_DMA_CHANNELS 0
-#define MAX_DMA_ADDRESS ~0
diff --git a/include/asm-arm/arch-netx/entry-macro.S b/include/asm-arm/arch-netx/entry-macro.S
deleted file mode 100644
index 4115bbdf97ae..000000000000
--- a/include/asm-arm/arch-netx/entry-macro.S
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * include/asm-arm/arch-netx/entry-macro.S
- *
- * Low-level IRQ helper macros for Hilscher netX based platforms
- *
- * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <asm/arch/hardware.h>
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                mov     \base, #io_p2v(0x00100000)
-                add     \base, \base, #0x000ff000
-
-                ldr     \irqstat, [\base, #0]
-                clz     \irqnr, \irqstat
-                rsb     \irqnr, \irqnr, #31
-                cmp     \irqstat, #0
-                .endm
-
diff --git a/include/asm-arm/arch-netx/eth.h b/include/asm-arm/arch-netx/eth.h
deleted file mode 100644
index 643c90ef8b72..000000000000
--- a/include/asm-arm/arch-netx/eth.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * include/asm-arm/arch-netx/eth.h
- *
- * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef ASMARM_ARCH_ETH_H
-#define ASMARM_ARCH_ETH_H
-
-struct netxeth_platform_data {
-        unsigned int xcno;      /* number of xmac/xpec engine this eth uses */
-};
-
-#endif
diff --git a/include/asm-arm/arch-netx/hardware.h b/include/asm-arm/arch-netx/hardware.h
deleted file mode 100644
index 7786c45455cd..000000000000
--- a/include/asm-arm/arch-netx/hardware.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * include/asm-arm/arch-netx/hardware.h
- *
- * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#define NETX_IO_PHYS    0x00100000
-#define NETX_IO_VIRT    0xe0000000
-#define NETX_IO_SIZE    0x00100000
-
-#define SRAM_INTERNAL_PHYS_0 0x00000
-#define SRAM_INTERNAL_PHYS_1 0x08000
-#define SRAM_INTERNAL_PHYS_2 0x10000
-#define SRAM_INTERNAL_PHYS_3 0x18000
-#define SRAM_INTERNAL_PHYS(no) ((no) * 0x8000)
-
-#define XPEC_MEM_SIZE 0x4000
-#define XMAC_MEM_SIZE 0x1000
-#define SRAM_MEM_SIZE 0x8000
-
-#define io_p2v(x) ((x) - NETX_IO_PHYS + NETX_IO_VIRT)
-#define io_v2p(x) ((x) - NETX_IO_VIRT + NETX_IO_PHYS)
-
-#endif
diff --git a/include/asm-arm/arch-netx/io.h b/include/asm-arm/arch-netx/io.h
deleted file mode 100644
index a7a53f80165d..000000000000
--- a/include/asm-arm/arch-netx/io.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-netx/io.h
- *
- * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-#define __io(a)         ((void __iomem *)(a))
-#define __mem_pci(a)            (a)
-
-#endif
diff --git a/include/asm-arm/arch-netx/irqs.h b/include/asm-arm/arch-netx/irqs.h
deleted file mode 100644
index a487dc6e2661..000000000000
--- a/include/asm-arm/arch-netx/irqs.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * include/asm-arm/arch-netx/irqs.h
- *
- * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#define NETX_IRQ_VIC_START   0
-#define NETX_IRQ_SOFTINT     0
-#define NETX_IRQ_TIMER0      1
-#define NETX_IRQ_TIMER1      2
-#define NETX_IRQ_TIMER2      3
-#define NETX_IRQ_SYSTIME_NS  4
-#define NETX_IRQ_SYSTIME_S   5
-#define NETX_IRQ_GPIO_15     6
-#define NETX_IRQ_WATCHDOG    7
-#define NETX_IRQ_UART0       8
-#define NETX_IRQ_UART1       9
-#define NETX_IRQ_UART2      10
-#define NETX_IRQ_USB        11
-#define NETX_IRQ_SPI        12
-#define NETX_IRQ_I2C        13
-#define NETX_IRQ_LCD        14
-#define NETX_IRQ_HIF        15
-#define NETX_IRQ_GPIO_0_14  16
-#define NETX_IRQ_XPEC0      17
-#define NETX_IRQ_XPEC1      18
-#define NETX_IRQ_XPEC2      19
-#define NETX_IRQ_XPEC3      20
-#define NETX_IRQ_XPEC(no)   (17 + (no))
-#define NETX_IRQ_MSYNC0     21
-#define NETX_IRQ_MSYNC1     22
-#define NETX_IRQ_MSYNC2     23
-#define NETX_IRQ_MSYNC3     24
-#define NETX_IRQ_IRQ_PHY    25
-#define NETX_IRQ_ISO_AREA   26
-/* int 27 is reserved */
-/* int 28 is reserved */
-#define NETX_IRQ_TIMER3     29
-#define NETX_IRQ_TIMER4     30
-/* int 31 is reserved */
-
-#define NETX_IRQS 32
-
-/* for multiplexed irqs on gpio 0..14 */
-#define NETX_IRQ_GPIO(x) (NETX_IRQS + (x))
-#define NETX_IRQ_GPIO_LAST NETX_IRQ_GPIO(14)
-
-/* Host interface interrupts */
-#define NETX_IRQ_HIF_CHAINED(x)    (NETX_IRQ_GPIO_LAST + 1 + (x))
-#define NETX_IRQ_HIF_PIO35         NETX_IRQ_HIF_CHAINED(0)
-#define NETX_IRQ_HIF_PIO36         NETX_IRQ_HIF_CHAINED(1)
-#define NETX_IRQ_HIF_PIO40         NETX_IRQ_HIF_CHAINED(2)
-#define NETX_IRQ_HIF_PIO47         NETX_IRQ_HIF_CHAINED(3)
-#define NETX_IRQ_HIF_PIO72         NETX_IRQ_HIF_CHAINED(4)
-#define NETX_IRQ_HIF_LAST          NETX_IRQ_HIF_CHAINED(4)
-
-#define NR_IRQS (NETX_IRQ_HIF_LAST + 1)
diff --git a/include/asm-arm/arch-netx/memory.h b/include/asm-arm/arch-netx/memory.h
deleted file mode 100644
index 6d8d2df3e99d..000000000000
--- a/include/asm-arm/arch-netx/memory.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-netx/memory.h
- *
- * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-#define PHYS_OFFSET UL(0x80000000)
-
-/*
- * Virtual view <-> DMA view memory address translations
- * virt_to_bus: Used to translate the virtual address to an
- *              address suitable to be passed to set_dma_addr
- * bus_to_virt: Used to convert an address for DMA operations
- *              to an address that the kernel can use.
- */
-#define __virt_to_bus(x)         __virt_to_phys(x)
-#define __bus_to_virt(x)         __phys_to_virt(x)
-
-#endif
-
diff --git a/include/asm-arm/arch-netx/netx-regs.h b/include/asm-arm/arch-netx/netx-regs.h
deleted file mode 100644
index fc9aa21f360c..000000000000
--- a/include/asm-arm/arch-netx/netx-regs.h
+++ /dev/null
@@ -1,410 +0,0 @@
-/*
- * include/asm-arm/arch-netx/netx-regs.h
- *
- * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __ASM_ARCH_NETX_REGS_H
-#define __ASM_ARCH_NETX_REGS_H
-
-/* offsets relative to the beginning of the io space */
-#define NETX_OFS_SYSTEM  0x00000
-#define NETX_OFS_MEMCR   0x00100
-#define NETX_OFS_DPMAS   0x03000
-#define NETX_OFS_GPIO    0x00800
-#define NETX_OFS_PIO     0x00900
-#define NETX_OFS_UART0   0x00a00
-#define NETX_OFS_UART1   0x00a40
-#define NETX_OFS_UART2   0x00a80
-#define NETX_OF_MIIMU    0x00b00
-#define NETX_OFS_SPI     0x00c00
-#define NETX_OFS_I2C     0x00d00
-#define NETX_OFS_SYSTIME 0x01100
-#define NETX_OFS_RTC     0x01200
-#define NETX_OFS_EXTBUS  0x03600
-#define NETX_OFS_LCD     0x04000
-#define NETX_OFS_USB     0x20000
-#define NETX_OFS_XMAC0   0x60000
-#define NETX_OFS_XMAC1   0x61000
-#define NETX_OFS_XMAC2   0x62000
-#define NETX_OFS_XMAC3   0x63000
-#define NETX_OFS_XMAC(no) (0x60000 + (no) * 0x1000)
-#define NETX_OFS_PFIFO   0x64000
-#define NETX_OFS_XPEC0   0x70000
-#define NETX_OFS_XPEC1   0x74000
-#define NETX_OFS_XPEC2   0x78000
-#define NETX_OFS_XPEC3   0x7c000
-#define NETX_OFS_XPEC(no) (0x70000 + (no) * 0x4000)
-#define NETX_OFS_VIC     0xff000
-
-/* physical addresses */
-#define NETX_PA_SYSTEM   (NETX_IO_PHYS + NETX_OFS_SYSTEM)
-#define NETX_PA_MEMCR    (NETX_IO_PHYS + NETX_OFS_MEMCR)
-#define NETX_PA_DPMAS    (NETX_IO_PHYS + NETX_OFS_DPMAS)
-#define NETX_PA_GPIO     (NETX_IO_PHYS + NETX_OFS_GPIO)
-#define NETX_PA_PIO      (NETX_IO_PHYS + NETX_OFS_PIO)
-#define NETX_PA_UART0    (NETX_IO_PHYS + NETX_OFS_UART0)
-#define NETX_PA_UART1    (NETX_IO_PHYS + NETX_OFS_UART1)
-#define NETX_PA_UART2    (NETX_IO_PHYS + NETX_OFS_UART2)
-#define NETX_PA_MIIMU    (NETX_IO_PHYS + NETX_OF_MIIMU)
-#define NETX_PA_SPI      (NETX_IO_PHYS + NETX_OFS_SPI)
-#define NETX_PA_I2C      (NETX_IO_PHYS + NETX_OFS_I2C)
-#define NETX_PA_SYSTIME  (NETX_IO_PHYS + NETX_OFS_SYSTIME)
-#define NETX_PA_RTC      (NETX_IO_PHYS + NETX_OFS_RTC)
-#define NETX_PA_EXTBUS   (NETX_IO_PHYS + NETX_OFS_EXTBUS)
-#define NETX_PA_LCD      (NETX_IO_PHYS + NETX_OFS_LCD)
-#define NETX_PA_USB      (NETX_IO_PHYS + NETX_OFS_USB)
-#define NETX_PA_XMAC0    (NETX_IO_PHYS + NETX_OFS_XMAC0)
-#define NETX_PA_XMAC1    (NETX_IO_PHYS + NETX_OFS_XMAC1)
-#define NETX_PA_XMAC2    (NETX_IO_PHYS + NETX_OFS_XMAC2)
-#define NETX_PA_XMAC3    (NETX_IO_PHYS + NETX_OFS_XMAC3)
-#define NETX_PA_XMAC(no) (NETX_IO_PHYS + NETX_OFS_XMAC(no))
-#define NETX_PA_PFIFO    (NETX_IO_PHYS + NETX_OFS_PFIFO)
-#define NETX_PA_XPEC0    (NETX_IO_PHYS + NETX_OFS_XPEC0)
-#define NETX_PA_XPEC1    (NETX_IO_PHYS + NETX_OFS_XPEC1)
-#define NETX_PA_XPEC2    (NETX_IO_PHYS + NETX_OFS_XPEC2)
-#define NETX_PA_XPEC3    (NETX_IO_PHYS + NETX_OFS_XPEC3)
-#define NETX_PA_XPEC(no) (NETX_IO_PHYS + NETX_OFS_XPEC(no))
-#define NETX_PA_VIC      (NETX_IO_PHYS + NETX_OFS_VIC)
-
-/* virual addresses */
-#define NETX_VA_SYSTEM   (NETX_IO_VIRT + NETX_OFS_SYSTEM)
-#define NETX_VA_MEMCR    (NETX_IO_VIRT + NETX_OFS_MEMCR)
-#define NETX_VA_DPMAS    (NETX_IO_VIRT + NETX_OFS_DPMAS)
-#define NETX_VA_GPIO     (NETX_IO_VIRT + NETX_OFS_GPIO)
-#define NETX_VA_PIO      (NETX_IO_VIRT + NETX_OFS_PIO)
-#define NETX_VA_UART0    (NETX_IO_VIRT + NETX_OFS_UART0)
-#define NETX_VA_UART1    (NETX_IO_VIRT + NETX_OFS_UART1)
-#define NETX_VA_UART2    (NETX_IO_VIRT + NETX_OFS_UART2)
-#define NETX_VA_MIIMU    (NETX_IO_VIRT + NETX_OF_MIIMU)
-#define NETX_VA_SPI      (NETX_IO_VIRT + NETX_OFS_SPI)
-#define NETX_VA_I2C      (NETX_IO_VIRT + NETX_OFS_I2C)
-#define NETX_VA_SYSTIME  (NETX_IO_VIRT + NETX_OFS_SYSTIME)
-#define NETX_VA_RTC      (NETX_IO_VIRT + NETX_OFS_RTC)
-#define NETX_VA_EXTBUS   (NETX_IO_VIRT + NETX_OFS_EXTBUS)
-#define NETX_VA_LCD      (NETX_IO_VIRT + NETX_OFS_LCD)
-#define NETX_VA_USB      (NETX_IO_VIRT + NETX_OFS_USB)
-#define NETX_VA_XMAC0    (NETX_IO_VIRT + NETX_OFS_XMAC0)
-#define NETX_VA_XMAC1    (NETX_IO_VIRT + NETX_OFS_XMAC1)
-#define NETX_VA_XMAC2    (NETX_IO_VIRT + NETX_OFS_XMAC2)
-#define NETX_VA_XMAC3    (NETX_IO_VIRT + NETX_OFS_XMAC3)
-#define NETX_VA_XMAC(no) (NETX_IO_VIRT + NETX_OFS_XMAC(no))
-#define NETX_VA_PFIFO    (NETX_IO_VIRT + NETX_OFS_PFIFO)
-#define NETX_VA_XPEC0    (NETX_IO_VIRT + NETX_OFS_XPEC0)
-#define NETX_VA_XPEC1    (NETX_IO_VIRT + NETX_OFS_XPEC1)
-#define NETX_VA_XPEC2    (NETX_IO_VIRT + NETX_OFS_XPEC2)
-#define NETX_VA_XPEC3    (NETX_IO_VIRT + NETX_OFS_XPEC3)
-#define NETX_VA_XPEC(no) (NETX_IO_VIRT + NETX_OFS_XPEC(no))
-#define NETX_VA_VIC      (NETX_IO_VIRT + NETX_OFS_VIC)
-
-/*********************************
- * System functions              *
- *********************************/
-
-/* Registers */
-#define NETX_SYSTEM_REG(ofs)            __io(NETX_VA_SYSTEM + (ofs))
-#define NETX_SYSTEM_BOO_SR          NETX_SYSTEM_REG(0x00)
-#define NETX_SYSTEM_IOC_CR          NETX_SYSTEM_REG(0x04)
-#define NETX_SYSTEM_IOC_MR          NETX_SYSTEM_REG(0x08)
-
-/* FIXME: Docs are not consistent */
-/* #define NETX_SYSTEM_RES_CR          NETX_SYSTEM_REG(0x08) */
-#define NETX_SYSTEM_RES_CR          NETX_SYSTEM_REG(0x0c)
-
-#define NETX_SYSTEM_PHY_CONTROL     NETX_SYSTEM_REG(0x10)
-#define NETX_SYSTEM_REV             NETX_SYSTEM_REG(0x34)
-#define NETX_SYSTEM_IOC_ACCESS_KEY  NETX_SYSTEM_REG(0x70)
-#define NETX_SYSTEM_WDG_TR          NETX_SYSTEM_REG(0x200)
-#define NETX_SYSTEM_WDG_CTR         NETX_SYSTEM_REG(0x204)
-#define NETX_SYSTEM_WDG_IRQ_TIMEOUT NETX_SYSTEM_REG(0x208)
-#define NETX_SYSTEM_WDG_RES_TIMEOUT NETX_SYSTEM_REG(0x20c)
-
-/* Bits */
-#define NETX_SYSTEM_RES_CR_RSTIN         (1<<0)
-#define NETX_SYSTEM_RES_CR_WDG_RES       (1<<1)
-#define NETX_SYSTEM_RES_CR_HOST_RES      (1<<2)
-#define NETX_SYSTEM_RES_CR_FIRMW_RES     (1<<3)
-#define NETX_SYSTEM_RES_CR_XPEC0_RES     (1<<4)
-#define NETX_SYSTEM_RES_CR_XPEC1_RES     (1<<5)
-#define NETX_SYSTEM_RES_CR_XPEC2_RES     (1<<6)
-#define NETX_SYSTEM_RES_CR_XPEC3_RES     (1<<7)
-#define NETX_SYSTEM_RES_CR_DIS_XPEC0_RES (1<<16)
-#define NETX_SYSTEM_RES_CR_DIS_XPEC1_RES (1<<17)
-#define NETX_SYSTEM_RES_CR_DIS_XPEC2_RES (1<<18)
-#define NETX_SYSTEM_RES_CR_DIS_XPEC3_RES (1<<19)
-#define NETX_SYSTEM_RES_CR_FIRMW_FLG0    (1<<20)
-#define NETX_SYSTEM_RES_CR_FIRMW_FLG1    (1<<21)
-#define NETX_SYSTEM_RES_CR_FIRMW_FLG2    (1<<22)
-#define NETX_SYSTEM_RES_CR_FIRMW_FLG3    (1<<23)
-#define NETX_SYSTEM_RES_CR_FIRMW_RES_EN  (1<<24)
-#define NETX_SYSTEM_RES_CR_RSTOUT        (1<<25)
-#define NETX_SYSTEM_RES_CR_EN_RSTOUT     (1<<26)
-
-#define PHY_CONTROL_RESET            (1<<31)
-#define PHY_CONTROL_SIM_BYP          (1<<30)
-#define PHY_CONTROL_CLK_XLATIN       (1<<29)
-#define PHY_CONTROL_PHY1_EN          (1<<21)
-#define PHY_CONTROL_PHY1_NP_MSG_CODE
-#define PHY_CONTROL_PHY1_AUTOMDIX    (1<<17)
-#define PHY_CONTROL_PHY1_FIXMODE     (1<<16)
-#define PHY_CONTROL_PHY1_MODE(mode)  (((mode) & 0x7) << 13)
-#define PHY_CONTROL_PHY0_EN          (1<<12)
-#define PHY_CONTROL_PHY0_NP_MSG_CODE
-#define PHY_CONTROL_PHY0_AUTOMDIX    (1<<8)
-#define PHY_CONTROL_PHY0_FIXMODE     (1<<7)
-#define PHY_CONTROL_PHY0_MODE(mode)  (((mode) & 0x7) << 4)
-#define PHY_CONTROL_PHY_ADDRESS(adr) ((adr) & 0xf)
-
-#define PHY_MODE_10BASE_T_HALF      0
-#define PHY_MODE_10BASE_T_FULL      1
-#define PHY_MODE_100BASE_TX_FX_FULL 2
-#define PHY_MODE_100BASE_TX_FX_HALF 3
-#define PHY_MODE_100BASE_TX_HALF    4
-#define PHY_MODE_REPEATER           5
-#define PHY_MODE_POWER_DOWN         6
-#define PHY_MODE_ALL                7
-
-/* Bits */
-#define VECT_CNTL_ENABLE               (1 << 5)
-
-/*******************************
- * GPIO and timer module       *
- *******************************/
-
-/* Registers */
-#define NETX_GPIO_REG(ofs)                     __io(NETX_VA_GPIO + (ofs))
-#define NETX_GPIO_CFG(gpio)                NETX_GPIO_REG(0x0  + ((gpio)<<2))
-#define NETX_GPIO_THRESHOLD_CAPTURE(gpio)  NETX_GPIO_REG(0x40 + ((gpio)<<2))
-#define NETX_GPIO_COUNTER_CTRL(counter)    NETX_GPIO_REG(0x80 + ((counter)<<2))
-#define NETX_GPIO_COUNTER_MAX(counter)     NETX_GPIO_REG(0x94 + ((counter)<<2))
-#define NETX_GPIO_COUNTER_CURRENT(counter) NETX_GPIO_REG(0xa8 + ((counter)<<2))
-#define NETX_GPIO_IRQ_ENABLE               NETX_GPIO_REG(0xbc)
-#define NETX_GPIO_IRQ_DISABLE              NETX_GPIO_REG(0xc0)
-#define NETX_GPIO_SYSTIME_NS_CMP           NETX_GPIO_REG(0xc4)
-#define NETX_GPIO_LINE                     NETX_GPIO_REG(0xc8)
-#define NETX_GPIO_IRQ                      NETX_GPIO_REG(0xd0)
-
-/* Bits */
-#define NETX_GPIO_CFG_IOCFG_GP_INPUT                 (0x0)
-#define NETX_GPIO_CFG_IOCFG_GP_OUTPUT                (0x1)
-#define NETX_GPIO_CFG_IOCFG_GP_UART                  (0x2)
-#define NETX_GPIO_CFG_INV                            (1<<2)
-#define NETX_GPIO_CFG_MODE_INPUT_READ                (0<<3)
-#define NETX_GPIO_CFG_MODE_INPUT_CAPTURE_CONT_RISING (1<<3)
-#define NETX_GPIO_CFG_MODE_INPUT_CAPTURE_ONCE_RISING (2<<3)
-#define NETX_GPIO_CFG_MODE_INPUT_CAPTURE_HIGH_LEVEL  (3<<3)
-#define NETX_GPIO_CFG_COUNT_REF_COUNTER0             (0<<5)
-#define NETX_GPIO_CFG_COUNT_REF_COUNTER1             (1<<5)
-#define NETX_GPIO_CFG_COUNT_REF_COUNTER2             (2<<5)
-#define NETX_GPIO_CFG_COUNT_REF_COUNTER3             (3<<5)
-#define NETX_GPIO_CFG_COUNT_REF_COUNTER4             (4<<5)
-#define NETX_GPIO_CFG_COUNT_REF_SYSTIME              (7<<5)
-
-#define NETX_GPIO_COUNTER_CTRL_RUN                   (1<<0)
-#define NETX_GPIO_COUNTER_CTRL_SYM                   (1<<1)
-#define NETX_GPIO_COUNTER_CTRL_ONCE                  (1<<2)
-#define NETX_GPIO_COUNTER_CTRL_IRQ_EN                (1<<3)
-#define NETX_GPIO_COUNTER_CTRL_CNT_EVENT             (1<<4)
-#define NETX_GPIO_COUNTER_CTRL_RST_EN                (1<<5)
-#define NETX_GPIO_COUNTER_CTRL_SEL_EVENT             (1<<6)
-#define NETX_GPIO_COUNTER_CTRL_GPIO_REF /* FIXME */
-
-#define GPIO_BIT(gpio)                     (1<<(gpio))
-#define COUNTER_BIT(counter)               ((1<<16)<<(counter))
-
-/*******************************
- * PIO                         *
- *******************************/
-
-/* Registers */
-#define NETX_PIO_REG(ofs)        __io(NETX_VA_PIO + (ofs))
-#define NETX_PIO_INPIO       NETX_PIO_REG(0x0)
-#define NETX_PIO_OUTPIO      NETX_PIO_REG(0x4)
-#define NETX_PIO_OEPIO       NETX_PIO_REG(0x8)
-
-/*******************************
- * MII Unit                    *
- *******************************/
-
-/* Registers */
-#define NETX_MIIMU           __io(NETX_VA_MIIMU)
-
-/* Bits */
-#define MIIMU_SNRDY        (1<<0)
-#define MIIMU_PREAMBLE     (1<<1)
-#define MIIMU_OPMODE_WRITE (1<<2)
-#define MIIMU_MDC_PERIOD   (1<<3)
-#define MIIMU_PHY_NRES     (1<<4)
-#define MIIMU_RTA          (1<<5)
-#define MIIMU_REGADDR(adr) (((adr) & 0x1f) << 6)
-#define MIIMU_PHYADDR(adr) (((adr) & 0x1f) << 11)
-#define MIIMU_DATA(data)   (((data) & 0xffff) << 16)
-
-/*******************************
- * xmac / xpec                 *
- *******************************/
-
-/* XPEC register offsets relative to NETX_VA_XPEC(no) */
-#define NETX_XPEC_R0_OFS           0x00
-#define NETX_XPEC_R1_OFS           0x04
-#define NETX_XPEC_R2_OFS           0x08
-#define NETX_XPEC_R3_OFS           0x0c
-#define NETX_XPEC_R4_OFS           0x10
-#define NETX_XPEC_R5_OFS           0x14
-#define NETX_XPEC_R6_OFS           0x18
-#define NETX_XPEC_R7_OFS           0x1c
-#define NETX_XPEC_RANGE01_OFS      0x20
-#define NETX_XPEC_RANGE23_OFS      0x24
-#define NETX_XPEC_RANGE45_OFS      0x28
-#define NETX_XPEC_RANGE67_OFS      0x2c
-#define NETX_XPEC_PC_OFS           0x48
-#define NETX_XPEC_TIMER_OFS(timer) (0x30 + ((timer)<<2))
-#define NETX_XPEC_IRQ_OFS          0x8c
-#define NETX_XPEC_SYSTIME_NS_OFS   0x90
-#define NETX_XPEC_FIFO_DATA_OFS    0x94
-#define NETX_XPEC_SYSTIME_S_OFS    0x98
-#define NETX_XPEC_ADC_OFS          0x9c
-#define NETX_XPEC_URX_COUNT_OFS    0x40
-#define NETX_XPEC_UTX_COUNT_OFS    0x44
-#define NETX_XPEC_PC_OFS           0x48
-#define NETX_XPEC_ZERO_OFS         0x4c
-#define NETX_XPEC_STATCFG_OFS      0x50
-#define NETX_XPEC_EC_MASKA_OFS     0x54
-#define NETX_XPEC_EC_MASKB_OFS     0x58
-#define NETX_XPEC_EC_MASK0_OFS     0x5c
-#define NETX_XPEC_EC_MASK8_OFS     0x7c
-#define NETX_XPEC_EC_MASK9_OFS     0x80
-#define NETX_XPEC_XPU_HOLD_PC_OFS  0x100
-#define NETX_XPEC_RAM_START_OFS    0x2000
-
-/* Bits */
-#define XPU_HOLD_PC (1<<0)
-
-/* XMAC register offsets relative to NETX_VA_XMAC(no) */
-#define NETX_XMAC_RPU_PROGRAM_START_OFS       0x000
-#define NETX_XMAC_RPU_PROGRAM_END_OFS         0x3ff
-#define NETX_XMAC_TPU_PROGRAM_START_OFS       0x400
-#define NETX_XMAC_TPU_PROGRAM_END_OFS         0x7ff
-#define NETX_XMAC_RPU_HOLD_PC_OFS             0xa00
-#define NETX_XMAC_TPU_HOLD_PC_OFS             0xa04
-#define NETX_XMAC_STATUS_SHARED0_OFS          0x840
-#define NETX_XMAC_CONFIG_SHARED0_OFS          0x844
-#define NETX_XMAC_STATUS_SHARED1_OFS          0x848
-#define NETX_XMAC_CONFIG_SHARED1_OFS          0x84c
-#define NETX_XMAC_STATUS_SHARED2_OFS          0x850
-#define NETX_XMAC_CONFIG_SHARED2_OFS          0x854
-#define NETX_XMAC_STATUS_SHARED3_OFS          0x858
-#define NETX_XMAC_CONFIG_SHARED3_OFS          0x85c
-
-#define RPU_HOLD_PC            (1<<15)
-#define TPU_HOLD_PC            (1<<15)
-
-/*******************************
- * Pointer FIFO                *
- *******************************/
-
-/* Registers */
-#define NETX_PFIFO_REG(ofs)               __io(NETX_VA_PFIFO + (ofs))
-#define NETX_PFIFO_BASE(pfifo)        NETX_PFIFO_REG(0x00 + ((pfifo)<<2))
-#define NETX_PFIFO_BORDER_BASE(pfifo) NETX_PFIFO_REG(0x80 + ((pfifo)<<2))
-#define NETX_PFIFO_RESET              NETX_PFIFO_REG(0x100)
-#define NETX_PFIFO_FULL               NETX_PFIFO_REG(0x104)
-#define NETX_PFIFO_EMPTY              NETX_PFIFO_REG(0x108)
-#define NETX_PFIFO_OVEFLOW            NETX_PFIFO_REG(0x10c)
-#define NETX_PFIFO_UNDERRUN           NETX_PFIFO_REG(0x110)
-#define NETX_PFIFO_FILL_LEVEL(pfifo)  NETX_PFIFO_REG(0x180 + ((pfifo)<<2))
-#define NETX_PFIFO_XPEC_ISR(xpec)     NETX_PFIFO_REG(0x400 + ((xpec) << 2))
-
-/*******************************
- * Dual Port Memory            *
- *******************************/
-
-/* Registers */
-#define NETX_DPMAS_REG(ofs)               __io(NETX_VA_DPMAS + (ofs))
-#define NETX_DPMAS_SYS_STAT           NETX_DPMAS_REG(0x4d8)
-#define NETX_DPMAS_INT_STAT           NETX_DPMAS_REG(0x4e0)
-#define NETX_DPMAS_INT_EN             NETX_DPMAS_REG(0x4f0)
-#define NETX_DPMAS_IF_CONF0           NETX_DPMAS_REG(0x608)
-#define NETX_DPMAS_IF_CONF1           NETX_DPMAS_REG(0x60c)
-#define NETX_DPMAS_EXT_CONFIG(cs)     NETX_DPMAS_REG(0x610 + 4 * (cs))
-#define NETX_DPMAS_IO_MODE0           NETX_DPMAS_REG(0x620) /* I/O 32..63 */
-#define NETX_DPMAS_DRV_EN0            NETX_DPMAS_REG(0x624)
-#define NETX_DPMAS_DATA0              NETX_DPMAS_REG(0x628)
-#define NETX_DPMAS_IO_MODE1           NETX_DPMAS_REG(0x630) /* I/O 64..84 */
-#define NETX_DPMAS_DRV_EN1            NETX_DPMAS_REG(0x634)
-#define NETX_DPMAS_DATA1              NETX_DPMAS_REG(0x638)
-
-/* Bits */
-#define NETX_DPMAS_INT_EN_GLB_EN         (1<<31)
-#define NETX_DPMAS_INT_EN_MEM_LCK        (1<<30)
-#define NETX_DPMAS_INT_EN_WDG            (1<<29)
-#define NETX_DPMAS_INT_EN_PIO72          (1<<28)
-#define NETX_DPMAS_INT_EN_PIO47          (1<<27)
-#define NETX_DPMAS_INT_EN_PIO40          (1<<26)
-#define NETX_DPMAS_INT_EN_PIO36          (1<<25)
-#define NETX_DPMAS_INT_EN_PIO35          (1<<24)
-
-#define NETX_DPMAS_IF_CONF0_HIF_DISABLED (0<<28)
-#define NETX_DPMAS_IF_CONF0_HIF_EXT_BUS  (1<<28)
-#define NETX_DPMAS_IF_CONF0_HIF_UP_8BIT  (2<<28)
-#define NETX_DPMAS_IF_CONF0_HIF_UP_16BIT (3<<28)
-#define NETX_DPMAS_IF_CONF0_HIF_IO       (4<<28)
-#define NETX_DPMAS_IF_CONF0_WAIT_DRV_PP  (1<<14)
-#define NETX_DPMAS_IF_CONF0_WAIT_DRV_OD  (2<<14)
-#define NETX_DPMAS_IF_CONF0_WAIT_DRV_TRI (3<<14)
-
-#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO35 (1<<26)
-#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO36 (1<<27)
-#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO40 (1<<28)
-#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO47 (1<<29)
-#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO72 (1<<30)
-
-#define NETX_EXT_CONFIG_TALEWIDTH(x) (((x) & 0x7) << 29)
-#define NETX_EXT_CONFIG_TADRHOLD(x)  (((x) & 0x7) << 26)
-#define NETX_EXT_CONFIG_TCSON(x)     (((x) & 0x7) << 23)
-#define NETX_EXT_CONFIG_TRDON(x)     (((x) & 0x7) << 20)
-#define NETX_EXT_CONFIG_TWRON(x)     (((x) & 0x7)  << 17)
-#define NETX_EXT_CONFIG_TWROFF(x)    (((x) & 0x1f) << 12)
-#define NETX_EXT_CONFIG_TRDWRCYC(x)  (((x) & 0x1f) << 7)
-#define NETX_EXT_CONFIG_WAIT_POL     (1<<6)
-#define NETX_EXT_CONFIG_WAIT_EN      (1<<5)
-#define NETX_EXT_CONFIG_NRD_MODE     (1<<4)
-#define NETX_EXT_CONFIG_DS_MODE      (1<<3)
-#define NETX_EXT_CONFIG_NWR_MODE     (1<<2)
-#define NETX_EXT_CONFIG_16BIT        (1<<1)
-#define NETX_EXT_CONFIG_CS_ENABLE    (1<<0)
-
-#define NETX_DPMAS_IO_MODE0_WRL   (1<<13)
-#define NETX_DPMAS_IO_MODE0_WAIT  (1<<14)
-#define NETX_DPMAS_IO_MODE0_READY (1<<15)
-#define NETX_DPMAS_IO_MODE0_CS0   (1<<19)
-#define NETX_DPMAS_IO_MODE0_EXTRD (1<<20)
-
-#define NETX_DPMAS_IO_MODE1_CS2           (1<<15)
-#define NETX_DPMAS_IO_MODE1_CS1           (1<<16)
-#define NETX_DPMAS_IO_MODE1_SAMPLE_NPOR   (0<<30)
-#define NETX_DPMAS_IO_MODE1_SAMPLE_100MHZ (1<<30)
-#define NETX_DPMAS_IO_MODE1_SAMPLE_NPIO36 (2<<30)
-#define NETX_DPMAS_IO_MODE1_SAMPLE_PIO36  (3<<30)
-
-/*******************************
- * I2C                         *
- *******************************/
-#define NETX_I2C_REG(ofs)       __io(NETX_VA_I2C, (ofs))
-#define NETX_I2C_CTRL   NETX_I2C_REG(0x0)
-#define NETX_I2C_DATA   NETX_I2C_REG(0x4)
-
-#endif /* __ASM_ARCH_NETX_REGS_H */
diff --git a/include/asm-arm/arch-netx/param.h b/include/asm-arm/arch-netx/param.h
deleted file mode 100644
index 7a80c26178a8..000000000000
--- a/include/asm-arm/arch-netx/param.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-netx/param.h
- *
- * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
diff --git a/include/asm-arm/arch-netx/pfifo.h b/include/asm-arm/arch-netx/pfifo.h
deleted file mode 100644
index 4af2ee4a32c1..000000000000
--- a/include/asm-arm/arch-netx/pfifo.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * include/asm-arm/arch-netx/pfifo.h
- *
- * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-
-#ifndef ASM_ARCH_PFIFO_H
-#define ASM_ARCH_PFIFO_H
-
-static inline int pfifo_push(int no, unsigned int pointer)
-{
-        writel(pointer, NETX_PFIFO_BASE(no));
-        return 0;
-}
-
-static inline unsigned int pfifo_pop(int no)
-{
-        return readl(NETX_PFIFO_BASE(no));
-}
-
-static inline int pfifo_fill_level(int no)
-{
-
-        return readl(NETX_PFIFO_FILL_LEVEL(no));
-}
-
-static inline int pfifo_full(int no)
-{
-        return readl(NETX_PFIFO_FULL) & (1<<no) ? 1 : 0;
-}
-
-static inline int pfifo_empty(int no)
-{
-        return readl(NETX_PFIFO_EMPTY) & (1<<no) ? 1 : 0;
-}
-
-int pfifo_request(unsigned int pfifo_mask);
-void pfifo_free(unsigned int pfifo_mask);
-
-#endif /* ASM_ARCH_PFIFO_H */
diff --git a/include/asm-arm/arch-netx/system.h b/include/asm-arm/arch-netx/system.h
deleted file mode 100644
index 0624d87e1db8..000000000000
--- a/include/asm-arm/arch-netx/system.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * include/asm-arm/arch-netx/system.h
- *
- * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include "netx-regs.h"
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-static inline void arch_reset(char mode)
-{
-        writel(NETX_SYSTEM_RES_CR_FIRMW_RES_EN | NETX_SYSTEM_RES_CR_FIRMW_RES,
-               NETX_SYSTEM_RES_CR);
-}
-
-#endif
-
diff --git a/include/asm-arm/arch-netx/timex.h b/include/asm-arm/arch-netx/timex.h
deleted file mode 100644
index 7fdb42da0b40..000000000000
--- a/include/asm-arm/arch-netx/timex.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * include/asm-arm/arch-netx/timex.h
- *
- * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#define CLOCK_TICK_RATE 100000000
diff --git a/include/asm-arm/arch-netx/uncompress.h b/include/asm-arm/arch-netx/uncompress.h
deleted file mode 100644
index f89434547102..000000000000
--- a/include/asm-arm/arch-netx/uncompress.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * include/asm-arm/arch-netx/uncompress.h
- *
- * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-/*
- * The following code assumes the serial port has already been
- * initialized by the bootloader.  We search for the first enabled
- * port in the most probable order.  If you didn't setup a port in
- * your bootloader then nothing will appear (which might be desired).
- *
- * This does not append a newline
- */
-
-#define REG(x) (*(volatile unsigned long *)(x))
-
-#define UART1_BASE 0x100a00
-#define UART2_BASE 0x100a80
-
-#define UART_DR 0x0
-
-#define UART_CR 0x14
-#define CR_UART_EN (1<<0)
-
-#define UART_FR 0x18
-#define FR_BUSY (1<<3)
-#define FR_TXFF (1<<5)
-
-static void putc(char c)
-{
-        unsigned long base;
-
-        if (REG(UART1_BASE + UART_CR) & CR_UART_EN)
-                base = UART1_BASE;
-        else if (REG(UART2_BASE + UART_CR) & CR_UART_EN)
-                base = UART2_BASE;
-        else
-                return;
-
-        while (REG(base + UART_FR) & FR_TXFF);
-        REG(base + UART_DR) = c;
-}
-
-static inline void flush(void)
-{
-        unsigned long base;
-
-        if (REG(UART1_BASE + UART_CR) & CR_UART_EN)
-                base = UART1_BASE;
-        else if (REG(UART2_BASE + UART_CR) & CR_UART_EN)
-                base = UART2_BASE;
-        else
-                return;
-
-        while (REG(base + UART_FR) & FR_BUSY);
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-netx/vmalloc.h b/include/asm-arm/arch-netx/vmalloc.h
deleted file mode 100644
index da2da5a595da..000000000000
--- a/include/asm-arm/arch-netx/vmalloc.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-netx/vmalloc.h
- *
- * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
diff --git a/include/asm-arm/arch-netx/xc.h b/include/asm-arm/arch-netx/xc.h
deleted file mode 100644
index 659af19512a9..000000000000
--- a/include/asm-arm/arch-netx/xc.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-netx/xc.h
- *
- * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __ASM_ARCH_XC_H
-#define __ASM_ARCH_XC_H
-
-struct xc {
-        int no;
-        unsigned int type;
-        unsigned int version;
-        void __iomem *xpec_base;
-        void __iomem *xmac_base;
-        void __iomem *sram_base;
-        int irq;
-        struct device *dev;
-};
-
-int xc_reset(struct xc *x);
-int xc_stop(struct xc* x);
-int xc_start(struct xc *x);
-int xc_running(struct xc *x);
-int xc_request_firmware(struct xc* x);
-struct xc* request_xc(int xcno, struct device *dev);
-void free_xc(struct xc *x);
-
-#endif /* __ASM_ARCH_XC_H */
diff --git a/include/asm-arm/arch-ns9xxx/board.h b/include/asm-arm/arch-ns9xxx/board.h
deleted file mode 100644
index e57443bdbbd9..000000000000
--- a/include/asm-arm/arch-ns9xxx/board.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * include/asm-arm/arch-ns9xxx/board.h
- *
- * Copyright (C) 2006,2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_BOARD_H
-#define __ASM_ARCH_BOARD_H
-
-#include <asm/mach-types.h>
-
-#define board_is_a9m9750dev()   (0                      \
-                || machine_is_cc9p9360dev()             \
-                || machine_is_cc9p9750dev()             \
-                )
-
-#define board_is_a9mvali()      (0                      \
-                || machine_is_cc9p9360val()             \
-                || machine_is_cc9p9750val()             \
-                )
-
-#define board_is_jscc9p9210()   (0                      \
-                || machine_is_cc9p9210js()              \
-                )
-
-#define board_is_jscc9p9215()   (0                      \
-                || machine_is_cc9p9215js()              \
-                )
-
-#define board_is_jscc9p9360()   (0                      \
-                || machine_is_cc9p9360js()              \
-                )
-
-#define board_is_uncbas()       (0                      \
-                || machine_is_cc7ucamry()               \
-                )
-
-#endif /* ifndef __ASM_ARCH_BOARD_H */
diff --git a/include/asm-arm/arch-ns9xxx/debug-macro.S b/include/asm-arm/arch-ns9xxx/debug-macro.S
deleted file mode 100644
index c78908d7203d..000000000000
--- a/include/asm-arm/arch-ns9xxx/debug-macro.S
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * include/asm-arm/arch-ns9xxx/debug-macro.S
- * Copyright (C) 2006 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#include <asm/arch/hardware.h>
-
-#include <asm/arch/regs-board-a9m9750dev.h>
-
-                .macro  addruart,rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1
-                ldreq   \rx, =NS9XXX_CSxSTAT_PHYS(0)
-                ldrne   \rx, =io_p2v(NS9XXX_CSxSTAT_PHYS(0))
-                .endm
-
-#define UART_SHIFT      2
-#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-ns9xxx/dma.h b/include/asm-arm/arch-ns9xxx/dma.h
deleted file mode 100644
index a67cbbe009c4..000000000000
--- a/include/asm-arm/arch-ns9xxx/dma.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * include/asm-arm/arch-ns9xxx/dma.h
- *
- * Copyright (C) 2006 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-
-#endif /* ifndef __ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-ns9xxx/entry-macro.S b/include/asm-arm/arch-ns9xxx/entry-macro.S
deleted file mode 100644
index e9d9449d300a..000000000000
--- a/include/asm-arm/arch-ns9xxx/entry-macro.S
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * include/asm-arm/arch-ns9xxx/entry-macro.S
- *
- * Copyright (C) 2006,2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#include <asm/arch/hardware.h>
-#include <asm/arch/regs-sys-common.h>
-
-                .macro  get_irqnr_preamble, base, tmp
-                ldr     \base, =SYS_ISRADDR
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \irqstat, [\base, #(SYS_ISA - SYS_ISRADDR)]
-                cmp     \irqstat, #0
-                ldrne   \irqnr, [\base]
-                .endm
-
-                .macro  disable_fiq
-                .endm
diff --git a/include/asm-arm/arch-ns9xxx/gpio.h b/include/asm-arm/arch-ns9xxx/gpio.h
deleted file mode 100644
index adbca08583c0..000000000000
--- a/include/asm-arm/arch-ns9xxx/gpio.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * include/asm-arm/arch-ns9xxx/gpio.h
- *
- * Copyright (C) 2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H
-
-#include <asm/errno.h>
-
-int gpio_request(unsigned gpio, const char *label);
-
-void gpio_free(unsigned gpio);
-
-int ns9xxx_gpio_configure(unsigned gpio, int inv, int func);
-
-int gpio_direction_input(unsigned gpio);
-
-int gpio_direction_output(unsigned gpio, int value);
-
-int gpio_get_value(unsigned gpio);
-
-void gpio_set_value(unsigned gpio, int value);
-
-/*
- * ns9xxx can use gpio pins to trigger an irq, but it's not generic
- * enough to be supported by the gpio_to_irq/irq_to_gpio interface
- */
-static inline int gpio_to_irq(unsigned gpio)
-{
-        return -EINVAL;
-}
-
-static inline int irq_to_gpio(unsigned irq)
-{
-        return -EINVAL;
-}
-
-/* get the cansleep() stubs */
-#include <asm-generic/gpio.h>
-
-#endif /* ifndef __ASM_ARCH_GPIO_H */
diff --git a/include/asm-arm/arch-ns9xxx/hardware.h b/include/asm-arm/arch-ns9xxx/hardware.h
deleted file mode 100644
index 0dca11ce21fc..000000000000
--- a/include/asm-arm/arch-ns9xxx/hardware.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * include/asm-arm/arch-ns9xxx/hardware.h
- *
- * Copyright (C) 2006 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <asm/memory.h>
-
-/*
- * NetSilicon NS9xxx internal mapping:
- *
- * physical                <--> virtual
- * 0x90000000 - 0x906fffff <--> 0xf9000000 - 0xf96fffff
- * 0xa0100000 - 0xa0afffff <--> 0xfa100000 - 0xfaafffff
- */
-#define io_p2v(x)       (0xf0000000 \
-                         + (((x) & 0xf0000000) >> 4) \
-                         + ((x) & 0x00ffffff))
-
-#define io_v2p(x)       ((((x) & 0x0f000000) << 4) \
-                         + ((x) & 0x00ffffff))
-
-#define __REGSHIFT(mask)        ((mask) & (-(mask)))
-
-#define __REGBIT(bit)           ((u32)1 << (bit))
-#define __REGBITS(hbit, lbit)   ((((u32)1 << ((hbit) - (lbit) + 1)) - 1) << (lbit))
-#define __REGVAL(mask, value)   (((value) * __REGSHIFT(mask)) & (mask))
-
-#ifndef __ASSEMBLY__
-
-#  define __REG(x)      ((void __iomem __force *)io_p2v((x)))
-#  define __REG2(x, y)  ((void __iomem __force *)(io_p2v((x)) + 4 * (y)))
-
-#  define __REGSET(var, field, value)                                   \
-        ((var) = (((var) & ~((field) & ~(value))) | (value)))
-
-#  define REGSET(var, reg, field, value)                                \
-        __REGSET(var, reg ## _ ## field, reg ## _ ## field ## _ ## value)
-
-#  define REGSET_IDX(var, reg, field, idx, value)                       \
-        __REGSET(var, reg ## _ ## field((idx)), reg ## _ ## field ## _ ## value((idx)))
-
-#  define REGSETIM(var, reg, field, value)                              \
-        __REGSET(var, reg ## _ ## field, __REGVAL(reg ## _ ## field, (value)))
-
-#  define REGSETIM_IDX(var, reg, field, idx, value)                     \
-        __REGSET(var, reg ## _ ## field((idx)), __REGVAL(reg ## _ ## field((idx)), (value)))
-
-#  define __REGGET(var, field)                                          \
-        (((var) & (field)))
-
-#  define REGGET(var, reg, field)                                       \
-         __REGGET(var, reg ## _ ## field)
-
-#  define REGGET_IDX(var, reg, field, idx)                              \
-         __REGGET(var, reg ## _ ## field((idx)))
-
-#  define REGGETIM(var, reg, field)                                     \
-         __REGGET(var, reg ## _ ## field) / __REGSHIFT(reg ## _ ## field)
-
-#  define REGGETIM_IDX(var, reg, field, idx)                            \
-         __REGGET(var, reg ## _ ## field((idx))) /                      \
-         __REGSHIFT(reg ## _ ## field((idx)))
-
-#else
-
-#  define __REG(x)      io_p2v(x)
-#  define __REG2(x, y)  io_p2v((x) + 4 * (y))
-
-#endif
-
-#endif /* ifndef __ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-ns9xxx/io.h b/include/asm-arm/arch-ns9xxx/io.h
deleted file mode 100644
index 6f82d28af120..000000000000
--- a/include/asm-arm/arch-ns9xxx/io.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * include/asm-arm/arch-ns9xxx/io.h
- *
- * Copyright (C) 2006 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT  0xffffffff /* XXX */
-
-#define __io(a)         ((void __iomem *)(a))
-#define __mem_pci(a)    (a)
-#define __mem_isa(a)    (IO_BASE + (a))
-
-#endif /* ifndef __ASM_ARCH_IO_H */
diff --git a/include/asm-arm/arch-ns9xxx/irqs.h b/include/asm-arm/arch-ns9xxx/irqs.h
deleted file mode 100644
index e83d48ec42c9..000000000000
--- a/include/asm-arm/arch-ns9xxx/irqs.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * include/asm-arm/arch-ns9xxx/irqs.h
- *
- * Copyright (C) 2006,2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H
-
-/* NetSilicon 9360 */
-#define IRQ_NS9XXX_WATCHDOG     0
-#define IRQ_NS9XXX_AHBBUSERR    1
-#define IRQ_NS9360_BBUSAGG      2
-/* irq 3 is reserved for NS9360 */
-#define IRQ_NS9XXX_ETHRX        4
-#define IRQ_NS9XXX_ETHTX        5
-#define IRQ_NS9XXX_ETHPHY       6
-#define IRQ_NS9360_LCD          7
-#define IRQ_NS9360_SERBRX       8
-#define IRQ_NS9360_SERBTX       9
-#define IRQ_NS9360_SERARX       10
-#define IRQ_NS9360_SERATX       11
-#define IRQ_NS9360_SERCRX       12
-#define IRQ_NS9360_SERCTX       13
-#define IRQ_NS9360_I2C          14
-#define IRQ_NS9360_BBUSDMA      15
-#define IRQ_NS9360_TIMER0       16
-#define IRQ_NS9360_TIMER1       17
-#define IRQ_NS9360_TIMER2       18
-#define IRQ_NS9360_TIMER3       19
-#define IRQ_NS9360_TIMER4       20
-#define IRQ_NS9360_TIMER5       21
-#define IRQ_NS9360_TIMER6       22
-#define IRQ_NS9360_TIMER7       23
-#define IRQ_NS9360_RTC          24
-#define IRQ_NS9360_USBHOST      25
-#define IRQ_NS9360_USBDEVICE    26
-#define IRQ_NS9360_IEEE1284     27
-#define IRQ_NS9XXX_EXT0         28
-#define IRQ_NS9XXX_EXT1         29
-#define IRQ_NS9XXX_EXT2         30
-#define IRQ_NS9XXX_EXT3         31
-
-#define BBUS_IRQ(irq)   (32 + irq)
-
-#define IRQ_BBUS_DMA            BBUS_IRQ(0)
-#define IRQ_BBUS_SERBRX         BBUS_IRQ(2)
-#define IRQ_BBUS_SERBTX         BBUS_IRQ(3)
-#define IRQ_BBUS_SERARX         BBUS_IRQ(4)
-#define IRQ_BBUS_SERATX         BBUS_IRQ(5)
-#define IRQ_BBUS_SERCRX         BBUS_IRQ(6)
-#define IRQ_BBUS_SERCTX         BBUS_IRQ(7)
-#define IRQ_BBUS_SERDRX         BBUS_IRQ(8)
-#define IRQ_BBUS_SERDTX         BBUS_IRQ(9)
-#define IRQ_BBUS_I2C            BBUS_IRQ(10)
-#define IRQ_BBUS_1284           BBUS_IRQ(11)
-#define IRQ_BBUS_UTIL           BBUS_IRQ(12)
-#define IRQ_BBUS_RTC            BBUS_IRQ(13)
-#define IRQ_BBUS_USBHST         BBUS_IRQ(14)
-#define IRQ_BBUS_USBDEV         BBUS_IRQ(15)
-#define IRQ_BBUS_AHBDMA1        BBUS_IRQ(24)
-#define IRQ_BBUS_AHBDMA2        BBUS_IRQ(25)
-
-/*
- * these Interrupts are specific for the a9m9750dev board.
- * They are generated by an FPGA that interrupts the CPU on
- * IRQ_NS9360_EXT2
- */
-#define FPGA_IRQ(irq)   (64 + irq)
-
-#define IRQ_FPGA_UARTA          FPGA_IRQ(0)
-#define IRQ_FPGA_UARTB          FPGA_IRQ(1)
-#define IRQ_FPGA_UARTC          FPGA_IRQ(2)
-#define IRQ_FPGA_UARTD          FPGA_IRQ(3)
-#define IRQ_FPGA_TOUCH          FPGA_IRQ(4)
-#define IRQ_FPGA_CF             FPGA_IRQ(5)
-#define IRQ_FPGA_CAN0           FPGA_IRQ(6)
-#define IRQ_FPGA_CAN1           FPGA_IRQ(7)
-
-#define NR_IRQS 72
-
-#endif /* __ASM_ARCH_IRQS_H */
diff --git a/include/asm-arm/arch-ns9xxx/memory.h b/include/asm-arm/arch-ns9xxx/memory.h
deleted file mode 100644
index ce1343e593e1..000000000000
--- a/include/asm-arm/arch-ns9xxx/memory.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * include/asm-arm/arch-ns9xxx/memory.h
- *
- * Copyright (C) 2006 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-/* x in [0..3] */
-#define NS9XXX_CSxSTAT_PHYS(x)  UL(((x) + 4) << 28)
-
-#define NS9XXX_CS0STAT_LENGTH   UL(0x1000)
-#define NS9XXX_CS1STAT_LENGTH   UL(0x1000)
-#define NS9XXX_CS2STAT_LENGTH   UL(0x1000)
-#define NS9XXX_CS3STAT_LENGTH   UL(0x1000)
-
-#define PHYS_OFFSET     UL(0x00000000)
-
-#define __virt_to_bus(x) __virt_to_phys(x)
-#define __bus_to_virt(x) __phys_to_virt(x)
-
-#endif
diff --git a/include/asm-arm/arch-ns9xxx/module.h b/include/asm-arm/arch-ns9xxx/module.h
deleted file mode 100644
index ac08a31111e4..000000000000
--- a/include/asm-arm/arch-ns9xxx/module.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * include/asm-arm/arch-ns9xxx/module.h
- *
- * Copyright (C) 2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_MODULE_H
-#define __ASM_ARCH_MODULE_H
-
-#include <asm/mach-types.h>
-
-#define module_is_cc7ucamry()   (0                      \
-                || machine_is_cc7ucamry()               \
-                )
-
-#define module_is_cc9c()        (0                      \
-                || machine_is_cc9c()                    \
-                )
-
-#define module_is_cc9p9210()    (0                      \
-                || machine_is_cc9p9210()                \
-                || machine_is_cc9p9210js()              \
-                )
-
-#define module_is_cc9p9215()    (0                      \
-                || machine_is_cc9p9215()                \
-                || machine_is_cc9p9215js()              \
-                )
-
-#define module_is_cc9p9360()    (0                      \
-                || machine_is_a9m9360()                 \
-                || machine_is_cc9p9360dev()             \
-                || machine_is_cc9p9360js()              \
-                || machine_is_cc9p9360val()             \
-                )
-
-#define module_is_cc9p9750()    (0                      \
-                || machine_is_a9m9750()                 \
-                || machine_is_cc9p9750dev()             \
-                || machine_is_cc9p9750js()              \
-                || machine_is_cc9p9750val()             \
-                )
-
-#define module_is_ccw9c()       (0                      \
-                || machine_is_ccw9c()                   \
-                )
-
-#define module_is_inc20otter()  (0                      \
-                || machine_is_inc20otter()              \
-                )
-
-#define module_is_otter()       (0                      \
-                || machine_is_otter()                   \
-                )
-
-#endif /* ifndef __ASM_ARCH_MODULE_H */
diff --git a/include/asm-arm/arch-ns9xxx/processor-ns9360.h b/include/asm-arm/arch-ns9xxx/processor-ns9360.h
deleted file mode 100644
index f3aa6c50dbe5..000000000000
--- a/include/asm-arm/arch-ns9xxx/processor-ns9360.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * include/asm-arm/arch-ns9xxx/processor-ns9360.h
- *
- * Copyright (C) 2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_PROCESSORNS9360_H
-#define __ASM_ARCH_PROCESSORNS9360_H
-
-#include <linux/init.h>
-
-void ns9360_reset(char mode);
-
-unsigned long ns9360_systemclock(void) __attribute__((const));
-
-static inline unsigned long ns9360_cpuclock(void) __attribute__((const));
-static inline unsigned long ns9360_cpuclock(void)
-{
-        return ns9360_systemclock() / 2;
-}
-
-void __init ns9360_map_io(void);
-
-extern struct sys_timer ns9360_timer;
-
-int ns9360_gpio_configure(unsigned gpio, int inv, int func);
-
-#endif /* ifndef __ASM_ARCH_PROCESSORNS9360_H */
diff --git a/include/asm-arm/arch-ns9xxx/processor.h b/include/asm-arm/arch-ns9xxx/processor.h
deleted file mode 100644
index 3137e5ba01a9..000000000000
--- a/include/asm-arm/arch-ns9xxx/processor.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * include/asm-arm/arch-ns9xxx/processor.h
- *
- * Copyright (C) 2006,2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_PROCESSOR_H
-#define __ASM_ARCH_PROCESSOR_H
-
-#include <asm/arch/module.h>
-
-#define processor_is_ns9210()   (0                      \
-                || module_is_cc7ucamry()                \
-                || module_is_cc9p9210()                 \
-                || module_is_inc20otter()               \
-                || module_is_otter()                    \
-                )
-
-#define processor_is_ns9215()   (0                      \
-                || module_is_cc9p9215()                 \
-                )
-
-#define processor_is_ns9360()   (0                      \
-                || module_is_cc9p9360()                 \
-                || module_is_cc9c()                     \
-                || module_is_ccw9c()                    \
-                )
-
-#define processor_is_ns9750()   (0                      \
-                || module_is_cc9p9750()                 \
-                )
-
-#define processor_is_ns921x()   (0                      \
-                || processor_is_ns9210()                \
-                || processor_is_ns9215()                \
-                )
-
-#endif /* ifndef __ASM_ARCH_PROCESSOR_H */
diff --git a/include/asm-arm/arch-ns9xxx/regs-bbu.h b/include/asm-arm/arch-ns9xxx/regs-bbu.h
deleted file mode 100644
index b41b31d04f03..000000000000
--- a/include/asm-arm/arch-ns9xxx/regs-bbu.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * include/asm-arm/arch-ns9xxx/regs-bbu.h
- *
- * Copyright (C) 2006 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_REGSBBU_H
-#define __ASM_ARCH_REGSBBU_H
-
-#include <asm/arch/hardware.h>
-
-/* BBus Utility */
-
-/* GPIO Configuration Registers block 1 */
-/* NOTE: the HRM starts counting at 1 for the GPIO registers, here the start is
- * at 0 for each block.  That is, BBU_GCONFb1(0) is GPIO Configuration Register
- * #1, BBU_GCONFb2(0) is GPIO Configuration Register #8. */
-#define BBU_GCONFb1(x)  __REG2(0x90600010, (x))
-#define BBU_GCONFb2(x)  __REG2(0x90600100, (x))
-
-#define BBU_GCONFx_DIR(m)       __REGBIT(3 + (((m) & 7) << 2))
-#define BBU_GCONFx_DIR_INPUT(m) __REGVAL(BBU_GCONFx_DIR(m), 0)
-#define BBU_GCONFx_DIR_OUTPUT(m)        __REGVAL(BBU_GCONFx_DIR(m), 1)
-#define BBU_GCONFx_INV(m)       __REGBIT(2 + (((m) & 7) << 2))
-#define BBU_GCONFx_INV_NO(m)            __REGVAL(BBU_GCONFx_INV(m), 0)
-#define BBU_GCONFx_INV_YES(m)           __REGVAL(BBU_GCONFx_INV(m), 1)
-#define BBU_GCONFx_FUNC(m)      __REGBITS(1 + (((m) & 7) << 2), ((m) & 7) << 2)
-#define BBU_GCONFx_FUNC_0(m)            __REGVAL(BBU_GCONFx_FUNC(m), 0)
-#define BBU_GCONFx_FUNC_1(m)            __REGVAL(BBU_GCONFx_FUNC(m), 1)
-#define BBU_GCONFx_FUNC_2(m)            __REGVAL(BBU_GCONFx_FUNC(m), 2)
-#define BBU_GCONFx_FUNC_3(m)            __REGVAL(BBU_GCONFx_FUNC(m), 3)
-
-#define BBU_GCTRL1      __REG(0x90600030)
-#define BBU_GCTRL2      __REG(0x90600034)
-#define BBU_GCTRL3      __REG(0x90600120)
-
-#define BBU_GSTAT1      __REG(0x90600040)
-#define BBU_GSTAT2      __REG(0x90600044)
-#define BBU_GSTAT3      __REG(0x90600130)
-
-#endif /* ifndef __ASM_ARCH_REGSBBU_H */
diff --git a/include/asm-arm/arch-ns9xxx/regs-board-a9m9750dev.h b/include/asm-arm/arch-ns9xxx/regs-board-a9m9750dev.h
deleted file mode 100644
index 6bf1ed2ac3d2..000000000000
--- a/include/asm-arm/arch-ns9xxx/regs-board-a9m9750dev.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * include/asm-arm/arch-ns9xxx/regs-board-a9m9750dev.h
- *
- * Copyright (C) 2006 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_REGSBOARDA9M9750_H
-#define __ASM_ARCH_REGSBOARDA9M9750_H
-
-#include <asm/arch/hardware.h>
-
-#define FPGA_UARTA_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0))
-#define FPGA_UARTB_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x08)
-#define FPGA_UARTC_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x10)
-#define FPGA_UARTD_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x18)
-
-#define FPGA_IER        __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x50)
-#define FPGA_ISR        __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x60)
-
-#endif /* ifndef __ASM_ARCH_REGSBOARDA9M9750_H */
diff --git a/include/asm-arm/arch-ns9xxx/regs-mem.h b/include/asm-arm/arch-ns9xxx/regs-mem.h
deleted file mode 100644
index 023f7be6f4c6..000000000000
--- a/include/asm-arm/arch-ns9xxx/regs-mem.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * include/asm-arm/arch-ns9xxx/regs-mem.h
- *
- * Copyright (C) 2006 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_REGSMEM_H
-#define __ASM_ARCH_REGSMEM_H
-
-#include <asm/arch/hardware.h>
-
-/* Memory Module */
-
-/* Control register */
-#define MEM_CTRL        __REG(0xa0700000)
-
-/* Status register */
-#define MEM_STAT        __REG(0xa0700004)
-
-/* Configuration register */
-#define MEM_CONF        __REG(0xa0700008)
-
-/* Dynamic Memory Control register */
-#define MEM_DMCTRL      __REG(0xa0700020)
-
-/* Dynamic Memory Refresh Timer */
-#define MEM_DMRT        __REG(0xa0700024)
-
-/* Dynamic Memory Read Configuration register */
-#define MEM_DMRC        __REG(0xa0700028)
-
-/* Dynamic Memory Precharge Command Period (tRP) */
-#define MEM_DMPCP       __REG(0xa0700030)
-
-/* Dynamic Memory Active to Precharge Command Period (tRAS) */
-#define MEM_DMAPCP      __REG(0xa0700034)
-
-/* Dynamic Memory Self-Refresh Exit Time (tSREX) */
-#define MEM_DMSRET      __REG(0xa0700038)
-
-/* Dynamic Memory Last Data Out to Active Time (tAPR) */
-#define MEM_DMLDOAT     __REG(0xa070003c)
-
-/* Dynamic Memory Data-in to Active Command Time (tDAL or TAPW) */
-#define MEM_DMDIACT     __REG(0xa0700040)
-
-/* Dynamic Memory Write Recovery Time (tWR, tDPL, tRWL, tRDL) */
-#define MEM_DMWRT       __REG(0xa0700044)
-
-/* Dynamic Memory Active to Active Command Period (tRC) */
-#define MEM_DMAACP      __REG(0xa0700048)
-
-/* Dynamic Memory Auto Refresh Period, and Auto Refresh to Active Command Period (tRFC) */
-#define MEM_DMARP       __REG(0xa070004c)
-
-/* Dynamic Memory Exit Self-Refresh to Active Command (tXSR) */
-#define MEM_DMESRAC     __REG(0xa0700050)
-
-/* Dynamic Memory Active Bank A to Active B Time (tRRD) */
-#define MEM_DMABAABT    __REG(0xa0700054)
-
-/* Dynamic Memory Load Mode register to Active Command Time (tMRD) */
-#define MEM_DMLMACT     __REG(0xa0700058)
-
-/* Static Memory Extended Wait */
-#define MEM_SMEW        __REG(0xa0700080)
-
-/* Dynamic Memory Configuration Register x */
-#define MEM_DMCONF(x)   __REG2(0xa0700100, (x) << 3)
-
-/* Dynamic Memory RAS and CAS Delay x */
-#define MEM_DMRCD(x)    __REG2(0xa0700104, (x) << 3)
-
-/* Static Memory Configuration Register x */
-#define MEM_SMC(x)      __REG2(0xa0700200, (x) << 3)
-
-/* Static Memory Configuration Register x: Write protect */
-#define MEM_SMC_PSMC            __REGBIT(20)
-#define MEM_SMC_PSMC_OFF                __REGVAL(MEM_SMC_PSMC, 0)
-#define MEM_SMC_PSMC_ON                 __REGVAL(MEM_SMC_PSMC, 1)
-
-/* Static Memory Configuration Register x: Buffer enable */
-#define MEM_SMC_BSMC            __REGBIT(19)
-#define MEM_SMC_BSMC_OFF                __REGVAL(MEM_SMC_BSMC, 0)
-#define MEM_SMC_BSMC_ON                 __REGVAL(MEM_SMC_BSMC, 1)
-
-/* Static Memory Configuration Register x: Extended Wait */
-#define MEM_SMC_EW              __REGBIT(8)
-#define MEM_SMC_EW_OFF                  __REGVAL(MEM_SMC_EW, 0)
-#define MEM_SMC_EW_ON                   __REGVAL(MEM_SMC_EW, 1)
-
-/* Static Memory Configuration Register x: Byte lane state */
-#define MEM_SMC_PB              __REGBIT(7)
-#define MEM_SMC_PB_0                    __REGVAL(MEM_SMC_PB, 0)
-#define MEM_SMC_PB_1                    __REGVAL(MEM_SMC_PB, 1)
-
-/* Static Memory Configuration Register x: Chip select polarity */
-#define MEM_SMC_PC              __REGBIT(6)
-#define MEM_SMC_PC_AL                   __REGVAL(MEM_SMC_PC, 0)
-#define MEM_SMC_PC_AH                   __REGVAL(MEM_SMC_PC, 1)
-
-/* static memory configuration register x: page mode*/
-#define MEM_SMC_PM              __REGBIT(3)
-#define MEM_SMC_PM_DIS                  __REGVAL(MEM_SMC_PM, 0)
-#define MEM_SMC_PM_ASYNC                __REGVAL(MEM_SMC_PM, 1)
-
-/* static memory configuration register x: Memory width */
-#define MEM_SMC_MW              __REGBITS(1, 0)
-#define MEM_SMC_MW_8                    __REGVAL(MEM_SMC_MW, 0)
-#define MEM_SMC_MW_16                   __REGVAL(MEM_SMC_MW, 1)
-#define MEM_SMC_MW_32                   __REGVAL(MEM_SMC_MW, 2)
-
-/* Static Memory Write Enable Delay x */
-#define MEM_SMWED(x)    __REG2(0xa0700204, (x) << 3)
-
-/* Static Memory Output Enable Delay x */
-#define MEM_SMOED(x)    __REG2(0xa0700208, (x) << 3)
-
-/* Static Memory Read Delay x */
-#define MEM_SMRD(x)     __REG2(0xa070020c, (x) << 3)
-
-/* Static Memory Page Mode Read Delay 0 */
-#define MEM_SMPMRD(x)   __REG2(0xa0700210, (x) << 3)
-
-/* Static Memory Write Delay */
-#define MEM_SMWD(x)     __REG2(0xa0700214, (x) << 3)
-
-/* Static Memory Turn Round Delay x */
-#define MEM_SWT(x)      __REG2(0xa0700218, (x) << 3)
-
-#endif /* ifndef __ASM_ARCH_REGSMEM_H */
diff --git a/include/asm-arm/arch-ns9xxx/regs-sys-common.h b/include/asm-arm/arch-ns9xxx/regs-sys-common.h
deleted file mode 100644
index bc82d5ec2a88..000000000000
--- a/include/asm-arm/arch-ns9xxx/regs-sys-common.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * include/asm-arm/arch-ns9xxx/regs-sys-common.h
- *
- * Copyright (C) 2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_REGSSYSCOMMON_H
-#define __ASM_ARCH_REGSSYSCOMMON_H
-#include <asm/arch/hardware.h>
-
-/* Interrupt Vector Address Register Level x */
-#define SYS_IVA(x)      __REG2(0xa09000c4, (x))
-
-/* Interrupt Configuration registers */
-#define SYS_IC(x)       __REG2(0xa0900144, (x))
-
-/* ISRADDR */
-#define SYS_ISRADDR     __REG(0xa0900164)
-
-/* Interrupt Status Active */
-#define SYS_ISA         __REG(0xa0900168)
-
-/* Interrupt Status Raw */
-#define SYS_ISR         __REG(0xa090016c)
-
-#endif /* ifndef __ASM_ARCH_REGSSYSCOMMON_H */
diff --git a/include/asm-arm/arch-ns9xxx/regs-sys-ns9360.h b/include/asm-arm/arch-ns9xxx/regs-sys-ns9360.h
deleted file mode 100644
index 821275a88cb1..000000000000
--- a/include/asm-arm/arch-ns9xxx/regs-sys-ns9360.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * include/asm-arm/arch-ns9xxx/regs-sys-ns9360.h
- *
- * Copyright (C) 2006,2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_REGSSYSNS9360_H
-#define __ASM_ARCH_REGSSYSNS9360_H
-
-#include <asm/arch/hardware.h>
-
-/* System Control Module */
-
-/* AHB Arbiter Gen Configuration */
-#define SYS_AHBAGENCONF __REG(0xa0900000)
-
-/* BRC */
-#define SYS_BRC(x)      __REG2(0xa0900004, (x))
-
-/* Timer x Reload Count register */
-#define SYS_TRC(x)      __REG2(0xa0900044, (x))
-
-/* Timer x Read register */
-#define SYS_TR(x)       __REG2(0xa0900084, (x))
-
-/* Timer Interrupt Status register */
-#define SYS_TIS         __REG(0xa0900170)
-
-/* PLL Configuration register */
-#define SYS_PLL         __REG(0xa0900188)
-
-/* PLL FS status */
-#define SYS_PLL_FS              __REGBITS(24, 23)
-
-/* PLL ND status */
-#define SYS_PLL_ND              __REGBITS(20, 16)
-
-/* PLL Configuration register: PLL SW change */
-#define SYS_PLL_SWC             __REGBIT(15)
-#define SYS_PLL_SWC_NO                  __REGVAL(SYS_PLL_SWC, 0)
-#define SYS_PLL_SWC_YES                 __REGVAL(SYS_PLL_SWC, 1)
-
-/* Timer x Control register */
-#define SYS_TC(x)       __REG2(0xa0900190, (x))
-
-/* Timer x Control register: Timer enable */
-#define SYS_TCx_TEN             __REGBIT(15)
-#define SYS_TCx_TEN_DIS                 __REGVAL(SYS_TCx_TEN, 0)
-#define SYS_TCx_TEN_EN                  __REGVAL(SYS_TCx_TEN, 1)
-
-/* Timer x Control register: CPU debug mode */
-#define SYS_TCx_TDBG            __REGBIT(10)
-#define SYS_TCx_TDBG_CONT               __REGVAL(SYS_TCx_TDBG, 0)
-#define SYS_TCx_TDBG_STOP               __REGVAL(SYS_TCx_TDBG, 1)
-
-/* Timer x Control register: Interrupt clear */
-#define SYS_TCx_INTC            __REGBIT(9)
-#define SYS_TCx_INTC_UNSET              __REGVAL(SYS_TCx_INTC, 0)
-#define SYS_TCx_INTC_SET                __REGVAL(SYS_TCx_INTC, 1)
-
-/* Timer x Control register: Timer clock select */
-#define SYS_TCx_TLCS            __REGBITS(8, 6)
-#define SYS_TCx_TLCS_CPU                __REGVAL(SYS_TCx_TLCS, 0)       /* CPU clock */
-#define SYS_TCx_TLCS_DIV2               __REGVAL(SYS_TCx_TLCS, 1)       /* CPU clock / 2 */
-#define SYS_TCx_TLCS_DIV4               __REGVAL(SYS_TCx_TLCS, 2)       /* CPU clock / 4 */
-#define SYS_TCx_TLCS_DIV8               __REGVAL(SYS_TCx_TLCS, 3)       /* CPU clock / 8 */
-#define SYS_TCx_TLCS_DIV16              __REGVAL(SYS_TCx_TLCS, 4)       /* CPU clock / 16 */
-#define SYS_TCx_TLCS_DIV32              __REGVAL(SYS_TCx_TLCS, 5)       /* CPU clock / 32 */
-#define SYS_TCx_TLCS_DIV64              __REGVAL(SYS_TCx_TLCS, 6)       /* CPU clock / 64 */
-#define SYS_TCx_TLCS_EXT                __REGVAL(SYS_TCx_TLCS, 7)
-
-/* Timer x Control register: Timer mode */
-#define SYS_TCx_TM              __REGBITS(5, 4)
-#define SYS_TCx_TM_IEE                  __REGVAL(SYS_TCx_TM, 0)         /* Internal timer or external event */
-#define SYS_TCx_TM_ELL                  __REGVAL(SYS_TCx_TM, 1)         /* External low-level, gated timer */
-#define SYS_TCx_TM_EHL                  __REGVAL(SYS_TCx_TM, 2)         /* External high-level, gated timer */
-#define SYS_TCx_TM_CONCAT               __REGVAL(SYS_TCx_TM, 3)         /* Concatenate the lower timer. */
-
-/* Timer x Control register: Interrupt select */
-#define SYS_TCx_INTS            __REGBIT(3)
-#define SYS_TCx_INTS_DIS                __REGVAL(SYS_TCx_INTS, 0)
-#define SYS_TCx_INTS_EN                 __REGVAL(SYS_TCx_INTS, 1)
-
-/* Timer x Control register: Up/down select */
-#define SYS_TCx_UDS             __REGBIT(2)
-#define SYS_TCx_UDS_UP                  __REGVAL(SYS_TCx_UDS, 0)
-#define SYS_TCx_UDS_DOWN                __REGVAL(SYS_TCx_UDS, 1)
-
-/* Timer x Control register: 32- or 16-bit timer */
-#define SYS_TCx_TSZ             __REGBIT(1)
-#define SYS_TCx_TSZ_16                  __REGVAL(SYS_TCx_TSZ, 0)
-#define SYS_TCx_TSZ_32                  __REGVAL(SYS_TCx_TSZ, 1)
-
-/* Timer x Control register: Reload enable */
-#define SYS_TCx_REN             __REGBIT(0)
-#define SYS_TCx_REN_DIS                 __REGVAL(SYS_TCx_REN, 0)
-#define SYS_TCx_REN_EN                  __REGVAL(SYS_TCx_REN, 1)
-
-/* System Memory Chip Select x Dynamic Memory Base */
-#define SYS_SMCSDMB(x)  __REG2(0xa09001d0, (x) << 1)
-
-/* System Memory Chip Select x Dynamic Memory Mask */
-#define SYS_SMCSDMM(x)  __REG2(0xa09001d4, (x) << 1)
-
-/* System Memory Chip Select x Static Memory Base */
-#define SYS_SMCSSMB(x)  __REG2(0xa09001f0, (x) << 1)
-
-/* System Memory Chip Select x Static Memory Base: Chip select x base */
-#define SYS_SMCSSMB_CSxB        __REGBITS(31, 12)
-
-/* System Memory Chip Select x Static Memory Mask */
-#define SYS_SMCSSMM(x)  __REG2(0xa09001f4, (x) << 1)
-
-/* System Memory Chip Select x Static Memory Mask: Chip select x mask */
-#define SYS_SMCSSMM_CSxM        __REGBITS(31, 12)
-
-/* System Memory Chip Select x Static Memory Mask: Chip select x enable */
-#define SYS_SMCSSMM_CSEx        __REGBIT(0)
-#define SYS_SMCSSMM_CSEx_DIS            __REGVAL(SYS_SMCSSMM_CSEx, 0)
-#define SYS_SMCSSMM_CSEx_EN             __REGVAL(SYS_SMCSSMM_CSEx, 1)
-
-/* General purpose, user-defined ID register */
-#define SYS_GENID       __REG(0xa0900210)
-
-/* External Interrupt x Control register */
-#define SYS_EIC(x)      __REG2(0xa0900214, (x))
-
-/* External Interrupt x Control register: Status */
-#define SYS_EIC_STS             __REGBIT(3)
-
-/* External Interrupt x Control register: Clear */
-#define SYS_EIC_CLR             __REGBIT(2)
-
-/* External Interrupt x Control register: Polarity */
-#define SYS_EIC_PLTY            __REGBIT(1)
-#define SYS_EIC_PLTY_AH                 __REGVAL(SYS_EIC_PLTY, 0)
-#define SYS_EIC_PLTY_AL                 __REGVAL(SYS_EIC_PLTY, 1)
-
-/* External Interrupt x Control register: Level edge */
-#define SYS_EIC_LVEDG           __REGBIT(0)
-#define SYS_EIC_LVEDG_LEVEL             __REGVAL(SYS_EIC_LVEDG, 0)
-#define SYS_EIC_LVEDG_EDGE              __REGVAL(SYS_EIC_LVEDG, 1)
-
-#endif /* ifndef __ASM_ARCH_REGSSYSNS9360_H */
diff --git a/include/asm-arm/arch-ns9xxx/system.h b/include/asm-arm/arch-ns9xxx/system.h
deleted file mode 100644
index c2941684d667..000000000000
--- a/include/asm-arm/arch-ns9xxx/system.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * include/asm-arm/arch-ns9xxx/system.h
- *
- * Copyright (C) 2006,2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-#include <asm/proc-fns.h>
-#include <asm/arch/processor.h>
-#include <asm/arch/processor-ns9360.h>
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-static inline void arch_reset(char mode)
-{
-#ifdef CONFIG_PROCESSOR_NS9360
-        if (processor_is_ns9360())
-                ns9360_reset(mode);
-        else
-#endif
-                BUG();
-
-        BUG();
-}
-
-#endif /* ifndef __ASM_ARCH_SYSTEM_H */
diff --git a/include/asm-arm/arch-ns9xxx/timex.h b/include/asm-arm/arch-ns9xxx/timex.h
deleted file mode 100644
index f776cbd2622d..000000000000
--- a/include/asm-arm/arch-ns9xxx/timex.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * include/asm-arm/arch-ns9xxx/timex.h
- *
- * Copyright (C) 2005-2006 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_TIMEX_H
-#define __ASM_ARCH_TIMEX_H
-
-/*
- * value for CLOCK_TICK_RATE stolen from include/asm-arm/arch-s3c2410/timex.h.
- * See there for an explanation.
- */
-#define CLOCK_TICK_RATE         12000000
-
-#endif /* ifndef __ASM_ARCH_TIMEX_H */
diff --git a/include/asm-arm/arch-ns9xxx/uncompress.h b/include/asm-arm/arch-ns9xxx/uncompress.h
deleted file mode 100644
index 71066baceab7..000000000000
--- a/include/asm-arm/arch-ns9xxx/uncompress.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * include/asm-arm/arch-ns9xxx/uncompress.h
- *
- * Copyright (C) 2006 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-
-#include <asm/io.h>
-
-#define __REG(x)        ((void __iomem __force *)(x))
-
-static void putc_dummy(char c, void __iomem *base)
-{
-        /* nothing */
-}
-
-static void putc_ns9360(char c, void __iomem *base)
-{
-        static int t = 0x10000;
-        do {
-                if (t)
-                        --t;
-
-                if (__raw_readl(base + 8) & (1 << 3)) {
-                        __raw_writeb(c, base + 16);
-                        t = 0x10000;
-                        break;
-                }
-        } while (t);
-}
-
-static void putc_a9m9750dev(char c, void __iomem *base)
-{
-        static int t = 0x10000;
-        do {
-                if (t)
-                        --t;
-
-                if (__raw_readb(base + 5) & (1 << 5)) {
-                        __raw_writeb(c, base);
-                        t = 0x10000;
-                        break;
-                }
-        } while (t);
-
-}
-
-static void putc_ns921x(char c, void __iomem *base)
-{
-        static int t = 0x10000;
-        do {
-                if (t)
-                        --t;
-
-                if (!(__raw_readl(base) & (1 << 11))) {
-                        __raw_writeb(c, base + 0x0028);
-                        t = 0x10000;
-                        break;
-                }
-        } while (t);
-}
-
-#define MSCS __REG(0xA0900184)
-
-#define NS9360_UARTA    __REG(0x90200040)
-#define NS9360_UARTB    __REG(0x90200000)
-#define NS9360_UARTC    __REG(0x90300000)
-#define NS9360_UARTD    __REG(0x90300040)
-
-#define NS9360_UART_ENABLED(base)                                       \
-                (__raw_readl(NS9360_UARTA) & (1 << 31))
-
-#define A9M9750DEV_UARTA        __REG(0x40000000)
-
-#define NS921XSYS_CLOCK __REG(0xa090017c)
-#define NS921X_UARTA    __REG(0x90010000)
-#define NS921X_UARTB    __REG(0x90018000)
-#define NS921X_UARTC    __REG(0x90020000)
-#define NS921X_UARTD    __REG(0x90028000)
-
-#define NS921X_UART_ENABLED(base)                                       \
-                (__raw_readl((base) + 0x1000) & (1 << 29))
-
-static void autodetect(void (**putc)(char, void __iomem *), void __iomem **base)
-{
-        if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x00) {
-                /* ns9360 or ns9750 */
-                if (NS9360_UART_ENABLED(NS9360_UARTA)) {
-                        *putc = putc_ns9360;
-                        *base = NS9360_UARTA;
-                        return;
-                } else if (NS9360_UART_ENABLED(NS9360_UARTB)) {
-                        *putc = putc_ns9360;
-                        *base = NS9360_UARTB;
-                        return;
-                } else if (NS9360_UART_ENABLED(NS9360_UARTC)) {
-                        *putc = putc_ns9360;
-                        *base = NS9360_UARTC;
-                        return;
-                } else if (NS9360_UART_ENABLED(NS9360_UARTD)) {
-                        *putc = putc_ns9360;
-                        *base = NS9360_UARTD;
-                        return;
-                } else if (__raw_readl(__REG(0xa09001f4)) == 0xfffff001) {
-                        *putc = putc_a9m9750dev;
-                        *base = A9M9750DEV_UARTA;
-                        return;
-                }
-        } else if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x02) {
-                /* ns921x */
-                u32 clock = __raw_readl(NS921XSYS_CLOCK);
-
-                if ((clock & (1 << 1)) &&
-                                NS921X_UART_ENABLED(NS921X_UARTA)) {
-                        *putc = putc_ns921x;
-                        *base = NS921X_UARTA;
-                        return;
-                } else if ((clock & (1 << 2)) &&
-                                NS921X_UART_ENABLED(NS921X_UARTB)) {
-                        *putc = putc_ns921x;
-                        *base = NS921X_UARTB;
-                        return;
-                } else if ((clock & (1 << 3)) &&
-                                NS921X_UART_ENABLED(NS921X_UARTC)) {
-                        *putc = putc_ns921x;
-                        *base = NS921X_UARTC;
-                        return;
-                } else if ((clock & (1 << 4)) &&
-                                NS921X_UART_ENABLED(NS921X_UARTD)) {
-                        *putc = putc_ns921x;
-                        *base = NS921X_UARTD;
-                        return;
-                }
-        }
-
-        *putc = putc_dummy;
-}
-
-void (*myputc)(char, void __iomem *);
-void __iomem *base;
-
-static void putc(char c)
-{
-        myputc(c, base);
-}
-
-static void arch_decomp_setup(void)
-{
-        autodetect(&myputc, &base);
-}
-#define arch_decomp_wdog()
-
-static void flush(void)
-{
-        /* nothing */
-}
-
-#endif /* ifndef __ASM_ARCH_UNCOMPRESS_H */
diff --git a/include/asm-arm/arch-ns9xxx/vmalloc.h b/include/asm-arm/arch-ns9xxx/vmalloc.h
deleted file mode 100644
index 2f3cb6f6be24..000000000000
--- a/include/asm-arm/arch-ns9xxx/vmalloc.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * include/asm-arm/arch-ns9xxx/vmalloc.h
- *
- * Copyright (C) 2006 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H
-
-#define VMALLOC_END     (0xf0000000)
-
-#endif /* ifndef __ASM_ARCH_VMALLOC_H */
diff --git a/include/asm-arm/arch-omap/aic23.h b/include/asm-arm/arch-omap/aic23.h
deleted file mode 100644
index aec2d6563622..000000000000
--- a/include/asm-arm/arch-omap/aic23.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/aic23.h
- *
- * Hardware definitions for TI TLV320AIC23 audio codec
- *
- * Copyright (C) 2002 RidgeRun, Inc.
- * Author: Steve Johnson
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the  GNU General Public License along
- * with this program; if not, write  to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_AIC23_H
-#define __ASM_ARCH_AIC23_H
-
-// Codec TLV320AIC23
-#define LEFT_LINE_VOLUME_ADDR           0x00
-#define RIGHT_LINE_VOLUME_ADDR          0x01
-#define LEFT_CHANNEL_VOLUME_ADDR        0x02
-#define RIGHT_CHANNEL_VOLUME_ADDR       0x03
-#define ANALOG_AUDIO_CONTROL_ADDR       0x04
-#define DIGITAL_AUDIO_CONTROL_ADDR      0x05
-#define POWER_DOWN_CONTROL_ADDR         0x06
-#define DIGITAL_AUDIO_FORMAT_ADDR       0x07
-#define SAMPLE_RATE_CONTROL_ADDR        0x08
-#define DIGITAL_INTERFACE_ACT_ADDR      0x09
-#define RESET_CONTROL_ADDR              0x0F
-
-// Left (right) line input volume control register
-#define LRS_ENABLED                     0x0100
-#define LIM_MUTED                       0x0080
-#define LIV_DEFAULT                     0x0017
-#define LIV_MAX                         0x001f
-#define LIV_MIN                         0x0000
-
-// Left (right) channel headphone volume control register
-#define LZC_ON                          0x0080
-#define LHV_DEFAULT                     0x0079
-#define LHV_MAX                         0x007f
-#define LHV_MIN                         0x0000
-
-// Analog audio path control register
-#define STA_REG(x)                      ((x)<<6)
-#define STE_ENABLED                     0x0020
-#define DAC_SELECTED                    0x0010
-#define BYPASS_ON                       0x0008
-#define INSEL_MIC                       0x0004
-#define MICM_MUTED                      0x0002
-#define MICB_20DB                       0x0001
-
-// Digital audio path control register
-#define DACM_MUTE                       0x0008
-#define DEEMP_32K                       0x0002
-#define DEEMP_44K                       0x0004
-#define DEEMP_48K                       0x0006
-#define ADCHP_ON                        0x0001
-
-// Power control down register
-#define DEVICE_POWER_OFF                0x0080
-#define CLK_OFF                         0x0040
-#define OSC_OFF                         0x0020
-#define OUT_OFF                         0x0010
-#define DAC_OFF                         0x0008
-#define ADC_OFF                         0x0004
-#define MIC_OFF                         0x0002
-#define LINE_OFF                        0x0001
-
-// Digital audio interface register
-#define MS_MASTER                       0x0040
-#define LRSWAP_ON                       0x0020
-#define LRP_ON                          0x0010
-#define IWL_16                          0x0000
-#define IWL_20                          0x0004
-#define IWL_24                          0x0008
-#define IWL_32                          0x000C
-#define FOR_I2S                         0x0002
-#define FOR_DSP                         0x0003
-
-// Sample rate control register
-#define CLKOUT_HALF                     0x0080
-#define CLKIN_HALF                      0x0040
-#define BOSR_384fs                      0x0002 // BOSR_272fs when in USB mode
-#define USB_CLK_ON                      0x0001
-#define SR_MASK                         0xf
-#define CLKOUT_SHIFT                    7
-#define CLKIN_SHIFT                     6
-#define SR_SHIFT                        2
-#define BOSR_SHIFT                      1
-
-// Digital interface register
-#define ACT_ON                          0x0001
-
-#define TLV320AIC23ID1                  (0x1a)  // cs low
-#define TLV320AIC23ID2                  (0x1b)  // cs high
-
-void aic23_power_up(void);
-void aic23_power_down(void);
-
-#endif /* __ASM_ARCH_AIC23_H */
diff --git a/include/asm-arm/arch-omap/board-2430sdp.h b/include/asm-arm/arch-omap/board-2430sdp.h
deleted file mode 100644
index c7db9004ec31..000000000000
--- a/include/asm-arm/arch-omap/board-2430sdp.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/board-2430sdp.h
- *
- * Hardware definitions for TI OMAP2430 SDP board.
- *
- * Based on board-h4.h by Dirk Behme <dirk.behme@de.bosch.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_OMAP_2430SDP_H
-#define __ASM_ARCH_OMAP_2430SDP_H
-
-/* Placeholder for 2430SDP specific defines */
-#define OMAP24XX_ETHR_START              0x08000300
-#define OMAP24XX_ETHR_GPIO_IRQ          149
-#define SDP2430_CS0_BASE                0x04000000
-
-#define TWL4030_IRQNUM                  INT_24XX_SYS_NIRQ
-
-#endif /* __ASM_ARCH_OMAP_2430SDP_H */
diff --git a/include/asm-arm/arch-omap/board-ams-delta.h b/include/asm-arm/arch-omap/board-ams-delta.h
deleted file mode 100644
index 9aee15d97145..000000000000
--- a/include/asm-arm/arch-omap/board-ams-delta.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/board-ams-delta.h
- *
- * Copyright (C) 2006 Jonathan McDowell <noodles@earth.li>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#ifndef __ASM_ARCH_OMAP_AMS_DELTA_H
-#define __ASM_ARCH_OMAP_AMS_DELTA_H
-
-#if defined (CONFIG_MACH_AMS_DELTA)
-
-#define AMS_DELTA_LATCH1_PHYS           0x01000000
-#define AMS_DELTA_LATCH1_VIRT           0xEA000000
-#define AMS_DELTA_MODEM_PHYS            0x04000000
-#define AMS_DELTA_MODEM_VIRT            0xEB000000
-#define AMS_DELTA_LATCH2_PHYS           0x08000000
-#define AMS_DELTA_LATCH2_VIRT           0xEC000000
-
-#define AMS_DELTA_LATCH1_LED_CAMERA     0x01
-#define AMS_DELTA_LATCH1_LED_ADVERT     0x02
-#define AMS_DELTA_LATCH1_LED_EMAIL      0x04
-#define AMS_DELTA_LATCH1_LED_HANDSFREE  0x08
-#define AMS_DELTA_LATCH1_LED_VOICEMAIL  0x10
-#define AMS_DELTA_LATCH1_LED_VOICE      0x20
-
-#define AMS_DELTA_LATCH2_LCD_VBLEN      0x0001
-#define AMS_DELTA_LATCH2_LCD_NDISP      0x0002
-#define AMS_DELTA_LATCH2_NAND_NCE       0x0004
-#define AMS_DELTA_LATCH2_NAND_NRE       0x0008
-#define AMS_DELTA_LATCH2_NAND_NWP       0x0010
-#define AMS_DELTA_LATCH2_NAND_NWE       0x0020
-#define AMS_DELTA_LATCH2_NAND_ALE       0x0040
-#define AMS_DELTA_LATCH2_NAND_CLE       0x0080
-#define AMD_DELTA_LATCH2_KEYBRD_PWR     0x0100
-#define AMD_DELTA_LATCH2_KEYBRD_DATA    0x0200
-#define AMD_DELTA_LATCH2_SCARD_RSTIN    0x0400
-#define AMD_DELTA_LATCH2_SCARD_CMDVCC   0x0800
-#define AMS_DELTA_LATCH2_MODEM_NRESET   0x1000
-#define AMS_DELTA_LATCH2_MODEM_CODEC    0x2000
-
-#define AMS_DELTA_GPIO_PIN_KEYBRD_DATA  0
-#define AMS_DELTA_GPIO_PIN_KEYBRD_CLK   1
-#define AMS_DELTA_GPIO_PIN_MODEM_IRQ    2
-#define AMS_DELTA_GPIO_PIN_HOOK_SWITCH  4
-#define AMS_DELTA_GPIO_PIN_SCARD_NOFF   6
-#define AMS_DELTA_GPIO_PIN_SCARD_IO     7
-#define AMS_DELTA_GPIO_PIN_CONFIG       11
-#define AMS_DELTA_GPIO_PIN_NAND_RB      12
-
-#ifndef __ASSEMBLY__
-void ams_delta_latch1_write(u8 mask, u8 value);
-void ams_delta_latch2_write(u16 mask, u16 value);
-#endif
-
-#endif /* CONFIG_MACH_AMS_DELTA */
-
-#endif /* __ASM_ARCH_OMAP_AMS_DELTA_H */
diff --git a/include/asm-arm/arch-omap/board-apollon.h b/include/asm-arm/arch-omap/board-apollon.h
deleted file mode 100644
index 547125a4695e..000000000000
--- a/include/asm-arm/arch-omap/board-apollon.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/board-apollon.h
- *
- * Hardware definitions for Samsung OMAP24XX Apollon board.
- *
- * Initial creation by Kyungmin Park <kyungmin.park@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_OMAP_APOLLON_H
-#define __ASM_ARCH_OMAP_APOLLON_H
-
-extern void apollon_mmc_init(void);
-
-/* Placeholder for APOLLON specific defines */
-#define APOLLON_ETHR_GPIO_IRQ           74
-
-#endif /*  __ASM_ARCH_OMAP_APOLLON_H */
-
diff --git a/include/asm-arm/arch-omap/board-fsample.h b/include/asm-arm/arch-omap/board-fsample.h
deleted file mode 100644
index 89a1e529fb6f..000000000000
--- a/include/asm-arm/arch-omap/board-fsample.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/board-fsample.h
- *
- * Board-specific goodies for TI F-Sample.
- *
- * Copyright (C) 2006 Google, Inc.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_OMAP_FSAMPLE_H
-#define __ASM_ARCH_OMAP_FSAMPLE_H
-
-/* fsample is pretty close to p2-sample */
-#include <asm/arch/board-perseus2.h>
-
-#define fsample_cpld_read(reg) __raw_readb(reg)
-#define fsample_cpld_write(val, reg) __raw_writeb(val, reg)
-
-#define FSAMPLE_CPLD_BASE    0xE8100000
-#define FSAMPLE_CPLD_SIZE    SZ_4K
-#define FSAMPLE_CPLD_START   0x05080000
-
-#define FSAMPLE_CPLD_REG_A   (FSAMPLE_CPLD_BASE + 0x00)
-#define FSAMPLE_CPLD_SWITCH  (FSAMPLE_CPLD_BASE + 0x02)
-#define FSAMPLE_CPLD_UART    (FSAMPLE_CPLD_BASE + 0x02)
-#define FSAMPLE_CPLD_REG_B   (FSAMPLE_CPLD_BASE + 0x04)
-#define FSAMPLE_CPLD_VERSION (FSAMPLE_CPLD_BASE + 0x06)
-#define FSAMPLE_CPLD_SET_CLR (FSAMPLE_CPLD_BASE + 0x06)
-
-#define FSAMPLE_CPLD_BIT_BT_RESET         0
-#define FSAMPLE_CPLD_BIT_LCD_RESET        1
-#define FSAMPLE_CPLD_BIT_CAM_PWDN         2
-#define FSAMPLE_CPLD_BIT_CHARGER_ENABLE   3
-#define FSAMPLE_CPLD_BIT_SD_MMC_EN        4
-#define FSAMPLE_CPLD_BIT_aGPS_PWREN       5
-#define FSAMPLE_CPLD_BIT_BACKLIGHT        6
-#define FSAMPLE_CPLD_BIT_aGPS_EN_RESET    7
-#define FSAMPLE_CPLD_BIT_aGPS_SLEEPx_N    8
-#define FSAMPLE_CPLD_BIT_OTG_RESET        9
-
-#define fsample_cpld_set(bit) \
-    fsample_cpld_write((((bit) & 15) << 4) | 0x0f, FSAMPLE_CPLD_SET_CLR)
-
-#define fsample_cpld_clear(bit) \
-    fsample_cpld_write(0xf0 | ((bit) & 15), FSAMPLE_CPLD_SET_CLR)
-
-#endif
diff --git a/include/asm-arm/arch-omap/board-h2.h b/include/asm-arm/arch-omap/board-h2.h
deleted file mode 100644
index c322796d0d26..000000000000
--- a/include/asm-arm/arch-omap/board-h2.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/board-h2.h
- *
- * Hardware definitions for TI OMAP1610 H2 board.
- *
- * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_OMAP_H2_H
-#define __ASM_ARCH_OMAP_H2_H
-
-/* Placeholder for H2 specific defines */
-
-/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
-#define OMAP1610_ETHR_START             0x04000300
-
-extern void h2_mmc_init(void);
-extern void h2_mmc_slot_cover_handler(void *arg, int state);
-
-#endif /*  __ASM_ARCH_OMAP_H2_H */
-
diff --git a/include/asm-arm/arch-omap/board-h3.h b/include/asm-arm/arch-omap/board-h3.h
deleted file mode 100644
index c5d0f32a40ac..000000000000
--- a/include/asm-arm/arch-omap/board-h3.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/board-h3.h
- *
- * Copyright (C) 2001 RidgeRun, Inc.
- * Copyright (C) 2004 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the  GNU General Public License along
- * with this program; if not, write  to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#ifndef __ASM_ARCH_OMAP_H3_H
-#define __ASM_ARCH_OMAP_H3_H
-
-/* In OMAP1710 H3 the Ethernet is directly connected to CS1 */
-#define OMAP1710_ETHR_START             0x04000300
-
-extern void h3_mmc_init(void);
-extern void h3_mmc_slot_cover_handler(void *arg, int state);
-
-#endif /*  __ASM_ARCH_OMAP_H3_H */
diff --git a/include/asm-arm/arch-omap/board-h4.h b/include/asm-arm/arch-omap/board-h4.h
deleted file mode 100644
index 7e0efef4bb65..000000000000
--- a/include/asm-arm/arch-omap/board-h4.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/board-h4.h
- *
- * Hardware definitions for TI OMAP1610 H4 board.
- *
- * Initial creation by Dirk Behme <dirk.behme@de.bosch.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_OMAP_H4_H
-#define __ASM_ARCH_OMAP_H4_H
-
-/* Placeholder for H4 specific defines */
-#define OMAP24XX_ETHR_GPIO_IRQ          92
-#endif /*  __ASM_ARCH_OMAP_H4_H */
-
diff --git a/include/asm-arm/arch-omap/board-innovator.h b/include/asm-arm/arch-omap/board-innovator.h
deleted file mode 100644
index 9ca03dec9d36..000000000000
--- a/include/asm-arm/arch-omap/board-innovator.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/board-innovator.h
- *
- * Copyright (C) 2001 RidgeRun, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#ifndef __ASM_ARCH_OMAP_INNOVATOR_H
-#define __ASM_ARCH_OMAP_INNOVATOR_H
-
-#if defined (CONFIG_ARCH_OMAP15XX)
-
-#ifndef OMAP_SDRAM_DEVICE
-#define OMAP_SDRAM_DEVICE                       D256M_1X16_4B
-#endif
-
-#define OMAP1510P1_IMIF_PRI_VALUE               0x00
-#define OMAP1510P1_EMIFS_PRI_VALUE              0x00
-#define OMAP1510P1_EMIFF_PRI_VALUE              0x00
-
-#ifndef __ASSEMBLY__
-void fpga_write(unsigned char val, int reg);
-unsigned char fpga_read(int reg);
-#endif
-
-#endif /* CONFIG_ARCH_OMAP15XX */
-
-#if defined (CONFIG_ARCH_OMAP16XX)
-
-/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
-#define INNOVATOR1610_ETHR_START        0x04000300
-
-#endif /* CONFIG_ARCH_OMAP1610 */
-#endif /* __ASM_ARCH_OMAP_INNOVATOR_H */
diff --git a/include/asm-arm/arch-omap/board-nokia.h b/include/asm-arm/arch-omap/board-nokia.h
deleted file mode 100644
index 72deea203493..000000000000
--- a/include/asm-arm/arch-omap/board-nokia.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-omap/board-nokia.h
- *
- *  Information structures for Nokia-specific board config data
- *
- *  Copyright (C) 2005  Nokia Corporation
- */
-
-#ifndef _OMAP_BOARD_NOKIA_H
-#define _OMAP_BOARD_NOKIA_H
-
-#include <linux/types.h>
-
-#define OMAP_TAG_NOKIA_BT       0x4e01
-#define OMAP_TAG_WLAN_CX3110X   0x4e02
-#define OMAP_TAG_CBUS           0x4e03
-#define OMAP_TAG_EM_ASIC_BB5    0x4e04
-
-
-#define BT_CHIP_CSR             1
-#define BT_CHIP_TI              2
-
-#define BT_SYSCLK_12            1
-#define BT_SYSCLK_38_4          2
-
-struct omap_bluetooth_config {
-        u8    chip_type;
-        u8    bt_wakeup_gpio;
-        u8    host_wakeup_gpio;
-        u8    reset_gpio;
-        u8    bt_uart;
-        u8    bd_addr[6];
-        u8    bt_sysclk;
-};
-
-struct omap_wlan_cx3110x_config {
-        u8  chip_type;
-        s16 power_gpio;
-        s16 irq_gpio;
-        s16 spi_cs_gpio;
-};
-
-struct omap_cbus_config {
-        s16 clk_gpio;
-        s16 dat_gpio;
-        s16 sel_gpio;
-};
-
-struct omap_em_asic_bb5_config {
-        s16 retu_irq_gpio;
-        s16 tahvo_irq_gpio;
-};
-
-#endif
diff --git a/include/asm-arm/arch-omap/board-osk.h b/include/asm-arm/arch-omap/board-osk.h
deleted file mode 100644
index 94926090e475..000000000000
--- a/include/asm-arm/arch-omap/board-osk.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/board-osk.h
- *
- * Hardware definitions for TI OMAP5912 OSK board.
- *
- * Written by Dirk Behme <dirk.behme@de.bosch.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_OMAP_OSK_H
-#define __ASM_ARCH_OMAP_OSK_H
-
-/* At OMAP5912 OSK the Ethernet is directly connected to CS1 */
-#define OMAP_OSK_ETHR_START             0x04800300
-
-/* TPS65010 has four GPIOs.  nPG and LED2 can be treated like GPIOs with
- * alternate pin configurations for hardware-controlled blinking.
- */
-#define OSK_TPS_GPIO_BASE               (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */)
-#       define OSK_TPS_GPIO_USB_PWR_EN  (OSK_TPS_GPIO_BASE + 0)
-#       define OSK_TPS_GPIO_LED_D3      (OSK_TPS_GPIO_BASE + 1)
-#       define OSK_TPS_GPIO_LAN_RESET   (OSK_TPS_GPIO_BASE + 2)
-#       define OSK_TPS_GPIO_DSP_PWR_EN  (OSK_TPS_GPIO_BASE + 3)
-#       define OSK_TPS_GPIO_LED_D9      (OSK_TPS_GPIO_BASE + 4)
-#       define OSK_TPS_GPIO_LED_D2      (OSK_TPS_GPIO_BASE + 5)
-
-#endif /*  __ASM_ARCH_OMAP_OSK_H */
-
diff --git a/include/asm-arm/arch-omap/board-palmte.h b/include/asm-arm/arch-omap/board-palmte.h
deleted file mode 100644
index 6fac2c8935be..000000000000
--- a/include/asm-arm/arch-omap/board-palmte.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/board-palmte.h
- *
- * Hardware definitions for the Palm Tungsten E device.
- *
- * Maintainters :       http://palmtelinux.sf.net
- *                      palmtelinux-developpers@lists.sf.net
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __OMAP_BOARD_PALMTE_H
-#define __OMAP_BOARD_PALMTE_H
-
-#define PALMTE_USBDETECT_GPIO   0
-#define PALMTE_USB_OR_DC_GPIO   1
-#define PALMTE_TSC_GPIO         4
-#define PALMTE_PINTDAV_GPIO     6
-#define PALMTE_MMC_WP_GPIO      8
-#define PALMTE_MMC_POWER_GPIO   9
-#define PALMTE_HDQ_GPIO         11
-#define PALMTE_HEADPHONES_GPIO  14
-#define PALMTE_SPEAKER_GPIO     15
-#define PALMTE_DC_GPIO          OMAP_MPUIO(2)
-#define PALMTE_MMC_SWITCH_GPIO  OMAP_MPUIO(4)
-#define PALMTE_MMC1_GPIO        OMAP_MPUIO(6)
-#define PALMTE_MMC2_GPIO        OMAP_MPUIO(7)
-#define PALMTE_MMC3_GPIO        OMAP_MPUIO(11)
-
-#endif  /* __OMAP_BOARD_PALMTE_H */
diff --git a/include/asm-arm/arch-omap/board-palmtt.h b/include/asm-arm/arch-omap/board-palmtt.h
deleted file mode 100644
index d9590b0ec90e..000000000000
--- a/include/asm-arm/arch-omap/board-palmtt.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/board-palmte.h
- *
- * Hardware definitions for the Palm Tungsten|T device.
- *
- * Maintainters :       Marek Vasut <marek.vasut@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __OMAP_BOARD_PALMTT_H
-#define __OMAP_BOARD_PALMTT_H
-
-#define PALMTT_USBDETECT_GPIO   0
-#define PALMTT_CABLE_GPIO       1
-#define PALMTT_LED_GPIO         3
-#define PALMTT_PENIRQ_GPIO      6
-#define PALMTT_MMC_WP_GPIO      8
-#define PALMTT_HDQ_GPIO         11
-
-#endif  /* __OMAP_BOARD_PALMTT_H */
diff --git a/include/asm-arm/arch-omap/board-palmz71.h b/include/asm-arm/arch-omap/board-palmz71.h
deleted file mode 100644
index 1252a859787d..000000000000
--- a/include/asm-arm/arch-omap/board-palmz71.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/board-palmz71.h
- *
- * Hardware definitions for the Palm Zire71 device.
- *
- * Maintainters :       Marek Vasut <marek.vasut@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __OMAP_BOARD_PALMZ71_H
-#define __OMAP_BOARD_PALMZ71_H
-
-#define PALMZ71_USBDETECT_GPIO  0
-#define PALMZ71_PENIRQ_GPIO     6
-#define PALMZ71_MMC_WP_GPIO     8
-#define PALMZ71_HDQ_GPIO        11
-
-#define PALMZ71_HOTSYNC_GPIO    OMAP_MPUIO(1)
-#define PALMZ71_CABLE_GPIO      OMAP_MPUIO(2)
-#define PALMZ71_SLIDER_GPIO     OMAP_MPUIO(3)
-#define PALMZ71_MMC_IN_GPIO     OMAP_MPUIO(4)
-
-#endif  /* __OMAP_BOARD_PALMZ71_H */
diff --git a/include/asm-arm/arch-omap/board-perseus2.h b/include/asm-arm/arch-omap/board-perseus2.h
deleted file mode 100644
index d7429cb0f726..000000000000
--- a/include/asm-arm/arch-omap/board-perseus2.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-omap/board-perseus2.h
- *
- *  Copyright 2003 by Texas Instruments Incorporated
- *    OMAP730 / Perseus2 support by Jean Pihet
- *
- * Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com)
- * Author: RidgeRun, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#ifndef __ASM_ARCH_OMAP_PERSEUS2_H
-#define __ASM_ARCH_OMAP_PERSEUS2_H
-
-#include <asm/arch/fpga.h>
-
-#ifndef OMAP_SDRAM_DEVICE
-#define OMAP_SDRAM_DEVICE               D256M_1X16_4B
-#endif
-
-#endif
diff --git a/include/asm-arm/arch-omap/board.h b/include/asm-arm/arch-omap/board.h
deleted file mode 100644
index 99564c70f128..000000000000
--- a/include/asm-arm/arch-omap/board.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-omap/board.h
- *
- *  Information structures for board-specific data
- *
- *  Copyright (C) 2004  Nokia Corporation
- *  Written by Juha Yrjölä <juha.yrjola@nokia.com>
- */
-
-#ifndef _OMAP_BOARD_H
-#define _OMAP_BOARD_H
-
-#include <linux/types.h>
-
-#include <asm/arch/gpio-switch.h>
-
-/* Different peripheral ids */
-#define OMAP_TAG_CLOCK          0x4f01
-#define OMAP_TAG_MMC            0x4f02
-#define OMAP_TAG_SERIAL_CONSOLE 0x4f03
-#define OMAP_TAG_USB            0x4f04
-#define OMAP_TAG_LCD            0x4f05
-#define OMAP_TAG_GPIO_SWITCH    0x4f06
-#define OMAP_TAG_UART           0x4f07
-#define OMAP_TAG_FBMEM          0x4f08
-#define OMAP_TAG_STI_CONSOLE    0x4f09
-#define OMAP_TAG_CAMERA_SENSOR  0x4f0a
-
-#define OMAP_TAG_BOOT_REASON    0x4f80
-#define OMAP_TAG_FLASH_PART     0x4f81
-#define OMAP_TAG_VERSION_STR    0x4f82
-
-struct omap_clock_config {
-        /* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */
-        u8 system_clock_type;
-};
-
-struct omap_mmc_conf {
-        unsigned enabled:1;
-        /* nomux means "standard" muxing is wrong on this board, and that
-         * board-specific code handled it before common init logic.
-         */
-        unsigned nomux:1;
-        /* switch pin can be for card detect (default) or card cover */
-        unsigned cover:1;
-        /* 4 wire signaling is optional, and is only used for SD/SDIO */
-        unsigned wire4:1;
-        s16 power_pin;
-        s16 switch_pin;
-        s16 wp_pin;
-};
-
-struct omap_mmc_config {
-        struct omap_mmc_conf mmc[2];
-};
-
-struct omap_serial_console_config {
-        u8 console_uart;
-        u32 console_speed;
-};
-
-struct omap_sti_console_config {
-        unsigned enable:1;
-        u8 channel;
-};
-
-struct omap_camera_sensor_config {
-        u16 reset_gpio;
-        int (*power_on)(void * data);
-        int (*power_off)(void * data);
-};
-
-struct omap_usb_config {
-        /* Configure drivers according to the connectors on your board:
-         *  - "A" connector (rectagular)
-         *      ... for host/OHCI use, set "register_host".
-         *  - "B" connector (squarish) or "Mini-B"
-         *      ... for device/gadget use, set "register_dev".
-         *  - "Mini-AB" connector (very similar to Mini-B)
-         *      ... for OTG use as device OR host, initialize "otg"
-         */
-        unsigned        register_host:1;
-        unsigned        register_dev:1;
-        u8              otg;    /* port number, 1-based:  usb1 == 2 */
-
-        u8              hmc_mode;
-
-        /* implicitly true if otg:  host supports remote wakeup? */
-        u8              rwc;
-
-        /* signaling pins used to talk to transceiver on usbN:
-         *  0 == usbN unused
-         *  2 == usb0-only, using internal transceiver
-         *  3 == 3 wire bidirectional
-         *  4 == 4 wire bidirectional
-         *  6 == 6 wire unidirectional (or TLL)
-         */
-        u8              pins[3];
-};
-
-struct omap_lcd_config {
-        char panel_name[16];
-        char ctrl_name[16];
-        s16  nreset_gpio;
-        u8   data_lines;
-};
-
-struct device;
-struct fb_info;
-struct omap_backlight_config {
-        int default_intensity;
-        int (*set_power)(struct device *dev, int state);
-        int (*check_fb)(struct fb_info *fb);
-};
-
-struct omap_fbmem_config {
-        u32 start;
-        u32 size;
-};
-
-struct omap_pwm_led_platform_data {
-        const char *name;
-        int intensity_timer;
-        int blink_timer;
-        void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off);
-};
-
-/* See include/asm-arm/arch-omap/gpio-switch.h for definitions */
-struct omap_gpio_switch_config {
-        char name[12];
-        u16 gpio;
-        int flags:4;
-        int type:4;
-        int key_code:24; /* Linux key code */
-};
-
-struct omap_uart_config {
-        /* Bit field of UARTs present; bit 0 --> UART1 */
-        unsigned int enabled_uarts;
-};
-
-
-struct omap_flash_part_config {
-        char part_table[0];
-};
-
-struct omap_boot_reason_config {
-        char reason_str[12];
-};
-
-struct omap_version_config {
-        char component[12];
-        char version[12];
-};
-
-
-#include <asm/arch/board-nokia.h>
-
-struct omap_board_config_entry {
-        u16 tag;
-        u16 len;
-        u8  data[0];
-};
-
-struct omap_board_config_kernel {
-        u16 tag;
-        const void *data;
-};
-
-extern const void *__omap_get_config(u16 tag, size_t len, int nr);
-
-#define omap_get_config(tag, type) \
-        ((const type *) __omap_get_config((tag), sizeof(type), 0))
-#define omap_get_nr_config(tag, type, nr) \
-        ((const type *) __omap_get_config((tag), sizeof(type), (nr)))
-
-extern const void *omap_get_var_config(u16 tag, size_t *len);
-
-extern struct omap_board_config_kernel *omap_board_config;
-extern int omap_board_config_size;
-
-
-/* for TI reference platforms sharing the same debug card */
-extern int debug_card_init(u32 addr, unsigned gpio);
-
-#endif
diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h
deleted file mode 100644
index 4c7b3514f71a..000000000000
--- a/include/asm-arm/arch-omap/clock.h
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-omap/clock.h
- *
- *  Copyright (C) 2004 - 2005 Nokia corporation
- *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
- *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ARCH_ARM_OMAP_CLOCK_H
-#define __ARCH_ARM_OMAP_CLOCK_H
-
-struct module;
-struct clk;
-
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-
-struct clksel_rate {
-        u8                      div;
-        u32                     val;
-        u8                      flags;
-};
-
-struct clksel {
-        struct clk               *parent;
-        const struct clksel_rate *rates;
-};
-
-struct dpll_data {
-        void __iomem            *mult_div1_reg;
-        u32                     mult_mask;
-        u32                     div1_mask;
-        u16                     last_rounded_m;
-        u8                      last_rounded_n;
-        unsigned long           last_rounded_rate;
-        unsigned int            rate_tolerance;
-        u16                     max_multiplier;
-        u8                      max_divider;
-        u32                     max_tolerance;
-#  if defined(CONFIG_ARCH_OMAP3)
-        u8                      modes;
-        void __iomem            *control_reg;
-        u32                     enable_mask;
-        u8                      auto_recal_bit;
-        u8                      recal_en_bit;
-        u8                      recal_st_bit;
-        void __iomem            *autoidle_reg;
-        u32                     autoidle_mask;
-        void __iomem            *idlest_reg;
-        u8                      idlest_bit;
-#  endif
-};
-
-#endif
-
-struct clk {
-        struct list_head        node;
-        struct module           *owner;
-        const char              *name;
-        int                     id;
-        struct clk              *parent;
-        unsigned long           rate;
-        __u32                   flags;
-        void __iomem            *enable_reg;
-        __u8                    enable_bit;
-        __s8                    usecount;
-        void                    (*recalc)(struct clk *);
-        int                     (*set_rate)(struct clk *, unsigned long);
-        long                    (*round_rate)(struct clk *, unsigned long);
-        void                    (*init)(struct clk *);
-        int                     (*enable)(struct clk *);
-        void                    (*disable)(struct clk *);
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-        u8                      fixed_div;
-        void __iomem            *clksel_reg;
-        u32                     clksel_mask;
-        const struct clksel     *clksel;
-        struct dpll_data        *dpll_data;
-#else
-        __u8                    rate_offset;
-        __u8                    src_offset;
-#endif
-#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
-        struct dentry           *dent;  /* For visible tree hierarchy */
-#endif
-};
-
-struct cpufreq_frequency_table;
-
-struct clk_functions {
-        int             (*clk_enable)(struct clk *clk);
-        void            (*clk_disable)(struct clk *clk);
-        long            (*clk_round_rate)(struct clk *clk, unsigned long rate);
-        int             (*clk_set_rate)(struct clk *clk, unsigned long rate);
-        int             (*clk_set_parent)(struct clk *clk, struct clk *parent);
-        struct clk *    (*clk_get_parent)(struct clk *clk);
-        void            (*clk_allow_idle)(struct clk *clk);
-        void            (*clk_deny_idle)(struct clk *clk);
-        void            (*clk_disable_unused)(struct clk *clk);
-#ifdef CONFIG_CPU_FREQ
-        void            (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
-#endif
-};
-
-extern unsigned int mpurate;
-
-extern int clk_init(struct clk_functions * custom_clocks);
-extern int clk_register(struct clk *clk);
-extern void clk_unregister(struct clk *clk);
-extern void propagate_rate(struct clk *clk);
-extern void recalculate_root_clocks(void);
-extern void followparent_recalc(struct clk * clk);
-extern void clk_allow_idle(struct clk *clk);
-extern void clk_deny_idle(struct clk *clk);
-extern int clk_get_usecount(struct clk *clk);
-extern void clk_enable_init_clocks(void);
-
-/* Clock flags */
-#define RATE_CKCTL              (1 << 0)        /* Main fixed ratio clocks */
-#define RATE_FIXED              (1 << 1)        /* Fixed clock rate */
-#define RATE_PROPAGATES         (1 << 2)        /* Program children too */
-#define VIRTUAL_CLOCK           (1 << 3)        /* Composite clock from table */
-#define ALWAYS_ENABLED          (1 << 4)        /* Clock cannot be disabled */
-#define ENABLE_REG_32BIT        (1 << 5)        /* Use 32-bit access */
-#define VIRTUAL_IO_ADDRESS      (1 << 6)        /* Clock in virtual address */
-#define CLOCK_IDLE_CONTROL      (1 << 7)
-#define CLOCK_NO_IDLE_PARENT    (1 << 8)
-#define DELAYED_APP             (1 << 9)        /* Delay application of clock */
-#define CONFIG_PARTICIPANT      (1 << 10)       /* Fundamental clock */
-#define ENABLE_ON_INIT          (1 << 11)       /* Enable upon framework init */
-#define INVERT_ENABLE           (1 << 12)       /* 0 enables, 1 disables */
-/* bits 13-20 are currently free */
-#define CLOCK_IN_OMAP310        (1 << 21)
-#define CLOCK_IN_OMAP730        (1 << 22)
-#define CLOCK_IN_OMAP1510       (1 << 23)
-#define CLOCK_IN_OMAP16XX       (1 << 24)
-#define CLOCK_IN_OMAP242X       (1 << 25)
-#define CLOCK_IN_OMAP243X       (1 << 26)
-#define CLOCK_IN_OMAP343X       (1 << 27)       /* clocks common to all 343X */
-#define PARENT_CONTROLS_CLOCK   (1 << 28)
-#define CLOCK_IN_OMAP3430ES1    (1 << 29)       /* 3430ES1 clocks only */
-#define CLOCK_IN_OMAP3430ES2    (1 << 30)       /* 3430ES2 clocks only */
-
-/* Clksel_rate flags */
-#define DEFAULT_RATE            (1 << 0)
-#define RATE_IN_242X            (1 << 1)
-#define RATE_IN_243X            (1 << 2)
-#define RATE_IN_343X            (1 << 3)        /* rates common to all 343X */
-#define RATE_IN_3430ES2         (1 << 4)        /* 3430ES2 rates only */
-
-#define RATE_IN_24XX            (RATE_IN_242X | RATE_IN_243X)
-
-
-/* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */
-#define CORE_CLK_SRC_32K                0
-#define CORE_CLK_SRC_DPLL               1
-#define CORE_CLK_SRC_DPLL_X2            2
-
-#endif
diff --git a/include/asm-arm/arch-omap/common.h b/include/asm-arm/arch-omap/common.h
deleted file mode 100644
index 8ac03071f60c..000000000000
--- a/include/asm-arm/arch-omap/common.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/common.h
- *
- * Header for code common to all OMAP machines.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the  GNU General Public License along
- * with this program; if not, write  to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
-#define __ARCH_ARM_MACH_OMAP_COMMON_H
-
-#include <linux/i2c.h>
-
-struct sys_timer;
-
-extern void omap_map_common_io(void);
-extern struct sys_timer omap_timer;
-extern void omap_serial_init(void);
-#ifdef CONFIG_I2C_OMAP
-extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
-                                 struct i2c_board_info const *info,
-                                 unsigned len);
-#else
-static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
-                                 struct i2c_board_info const *info,
-                                 unsigned len)
-{
-        return 0;
-}
-#endif
-
-/* IO bases for various OMAP processors */
-struct omap_globals {
-        void __iomem    *tap;           /* Control module ID code */
-        void __iomem    *sdrc;          /* SDRAM Controller */
-        void __iomem    *sms;           /* SDRAM Memory Scheduler */
-        void __iomem    *ctrl;          /* System Control Module */
-        void __iomem    *prm;           /* Power and Reset Management */
-        void __iomem    *cm;            /* Clock Management */
-};
-
-void omap2_set_globals_242x(void);
-void omap2_set_globals_243x(void);
-void omap2_set_globals_343x(void);
-
-/* These get called from omap2_set_globals_xxxx(), do not call these */
-void omap2_set_globals_memory(struct omap_globals *);
-void omap2_set_globals_control(struct omap_globals *);
-void omap2_set_globals_prcm(struct omap_globals *);
-
-#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/include/asm-arm/arch-omap/control.h b/include/asm-arm/arch-omap/control.h
deleted file mode 100644
index 987553e3eeb9..000000000000
--- a/include/asm-arm/arch-omap/control.h
+++ /dev/null
@@ -1,189 +0,0 @@
-#ifndef __ASM_ARCH_CONTROL_H
-#define __ASM_ARCH_CONTROL_H
-
-/*
- * include/asm-arm/arch-omap/control.h
- *
- * OMAP2/3 System Control Module definitions
- *
- * Copyright (C) 2007 Texas Instruments, Inc.
- * Copyright (C) 2007 Nokia Corporation
- *
- * Written by Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation.
- */
-
-#include <asm/arch/io.h>
-
-#define OMAP242X_CTRL_REGADDR(reg)                                      \
-        (void __iomem *)IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
-#define OMAP243X_CTRL_REGADDR(reg)                                      \
-        (void __iomem *)IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
-#define OMAP343X_CTRL_REGADDR(reg)                                      \
-        (void __iomem *)IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
-
-/*
- * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
- * OMAP24XX and OMAP34XX.
- */
-
-/* Control submodule offsets */
-
-#define OMAP2_CONTROL_INTERFACE         0x000
-#define OMAP2_CONTROL_PADCONFS          0x030
-#define OMAP2_CONTROL_GENERAL           0x270
-#define OMAP343X_CONTROL_MEM_WKUP       0x600
-#define OMAP343X_CONTROL_PADCONFS_WKUP  0xa00
-#define OMAP343X_CONTROL_GENERAL_WKUP   0xa60
-
-/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
-
-#define OMAP2_CONTROL_SYSCONFIG         (OMAP2_CONTROL_INTERFACE + 0x10)
-
-/* CONTROL_GENERAL register offsets common to OMAP2 & 3 */
-#define OMAP2_CONTROL_DEVCONF0          (OMAP2_CONTROL_GENERAL + 0x0004)
-#define OMAP2_CONTROL_MSUSPENDMUX_0     (OMAP2_CONTROL_GENERAL + 0x0020)
-#define OMAP2_CONTROL_MSUSPENDMUX_1     (OMAP2_CONTROL_GENERAL + 0x0024)
-#define OMAP2_CONTROL_MSUSPENDMUX_2     (OMAP2_CONTROL_GENERAL + 0x0028)
-#define OMAP2_CONTROL_MSUSPENDMUX_3     (OMAP2_CONTROL_GENERAL + 0x002c)
-#define OMAP2_CONTROL_MSUSPENDMUX_4     (OMAP2_CONTROL_GENERAL + 0x0030)
-#define OMAP2_CONTROL_MSUSPENDMUX_5     (OMAP2_CONTROL_GENERAL + 0x0034)
-#define OMAP2_CONTROL_SEC_CTRL          (OMAP2_CONTROL_GENERAL + 0x0040)
-#define OMAP2_CONTROL_RPUB_KEY_H_0      (OMAP2_CONTROL_GENERAL + 0x0090)
-#define OMAP2_CONTROL_RPUB_KEY_H_1      (OMAP2_CONTROL_GENERAL + 0x0094)
-#define OMAP2_CONTROL_RPUB_KEY_H_2      (OMAP2_CONTROL_GENERAL + 0x0098)
-#define OMAP2_CONTROL_RPUB_KEY_H_3      (OMAP2_CONTROL_GENERAL + 0x009c)
-
-/* 242x-only CONTROL_GENERAL register offsets */
-#define OMAP242X_CONTROL_DEVCONF        OMAP2_CONTROL_DEVCONF0 /* match TRM */
-#define OMAP242X_CONTROL_OCM_RAM_PERM   (OMAP2_CONTROL_GENERAL + 0x0068)
-
-/* 243x-only CONTROL_GENERAL register offsets */
-/* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
-#define OMAP243X_CONTROL_DEVCONF1       (OMAP2_CONTROL_GENERAL + 0x0078)
-#define OMAP243X_CONTROL_CSIRXFE        (OMAP2_CONTROL_GENERAL + 0x007c)
-#define OMAP243X_CONTROL_IVA2_BOOTADDR  (OMAP2_CONTROL_GENERAL + 0x0190)
-#define OMAP243X_CONTROL_IVA2_BOOTMOD   (OMAP2_CONTROL_GENERAL + 0x0194)
-#define OMAP243X_CONTROL_IVA2_GEMCFG    (OMAP2_CONTROL_GENERAL + 0x0198)
-
-/* 24xx-only CONTROL_GENERAL register offsets */
-#define OMAP24XX_CONTROL_DEBOBS         (OMAP2_CONTROL_GENERAL + 0x0000)
-#define OMAP24XX_CONTROL_EMU_SUPPORT    (OMAP2_CONTROL_GENERAL + 0x0008)
-#define OMAP24XX_CONTROL_SEC_TEST       (OMAP2_CONTROL_GENERAL + 0x0044)
-#define OMAP24XX_CONTROL_PSA_CTRL       (OMAP2_CONTROL_GENERAL + 0x0048)
-#define OMAP24XX_CONTROL_PSA_CMD        (OMAP2_CONTROL_GENERAL + 0x004c)
-#define OMAP24XX_CONTROL_PSA_VALUE      (OMAP2_CONTROL_GENERAL + 0x0050)
-#define OMAP24XX_CONTROL_SEC_EMU        (OMAP2_CONTROL_GENERAL + 0x0060)
-#define OMAP24XX_CONTROL_SEC_TAP        (OMAP2_CONTROL_GENERAL + 0x0064)
-#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD        (OMAP2_CONTROL_GENERAL + 0x006c)
-#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD  (OMAP2_CONTROL_GENERAL + 0x0070)
-#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD   (OMAP2_CONTROL_GENERAL + 0x0074)
-#define OMAP24XX_CONTROL_SEC_STATUS             (OMAP2_CONTROL_GENERAL + 0x0080)
-#define OMAP24XX_CONTROL_SEC_ERR_STATUS         (OMAP2_CONTROL_GENERAL + 0x0084)
-#define OMAP24XX_CONTROL_STATUS                 (OMAP2_CONTROL_GENERAL + 0x0088)
-#define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c)
-#define OMAP24XX_CONTROL_RAND_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00a0)
-#define OMAP24XX_CONTROL_RAND_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00a4)
-#define OMAP24XX_CONTROL_RAND_KEY_2     (OMAP2_CONTROL_GENERAL + 0x00a8)
-#define OMAP24XX_CONTROL_RAND_KEY_3     (OMAP2_CONTROL_GENERAL + 0x00ac)
-#define OMAP24XX_CONTROL_CUST_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00b0)
-#define OMAP24XX_CONTROL_CUST_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00b4)
-#define OMAP24XX_CONTROL_TEST_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00c0)
-#define OMAP24XX_CONTROL_TEST_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00c4)
-#define OMAP24XX_CONTROL_TEST_KEY_2     (OMAP2_CONTROL_GENERAL + 0x00c8)
-#define OMAP24XX_CONTROL_TEST_KEY_3     (OMAP2_CONTROL_GENERAL + 0x00cc)
-#define OMAP24XX_CONTROL_TEST_KEY_4     (OMAP2_CONTROL_GENERAL + 0x00d0)
-#define OMAP24XX_CONTROL_TEST_KEY_5     (OMAP2_CONTROL_GENERAL + 0x00d4)
-#define OMAP24XX_CONTROL_TEST_KEY_6     (OMAP2_CONTROL_GENERAL + 0x00d8)
-#define OMAP24XX_CONTROL_TEST_KEY_7     (OMAP2_CONTROL_GENERAL + 0x00dc)
-#define OMAP24XX_CONTROL_TEST_KEY_8     (OMAP2_CONTROL_GENERAL + 0x00e0)
-#define OMAP24XX_CONTROL_TEST_KEY_9     (OMAP2_CONTROL_GENERAL + 0x00e4)
-
-/* 34xx-only CONTROL_GENERAL register offsets */
-#define OMAP343X_CONTROL_PADCONF_OFF    (OMAP2_CONTROL_GENERAL + 0x0000)
-#define OMAP343X_CONTROL_MEM_DFTRW0     (OMAP2_CONTROL_GENERAL + 0x0008)
-#define OMAP343X_CONTROL_MEM_DFTRW1     (OMAP2_CONTROL_GENERAL + 0x000c)
-#define OMAP343X_CONTROL_DEVCONF1       (OMAP2_CONTROL_GENERAL + 0x0068)
-#define OMAP343X_CONTROL_CSIRXFE                (OMAP2_CONTROL_GENERAL + 0x006c)
-#define OMAP343X_CONTROL_SEC_STATUS             (OMAP2_CONTROL_GENERAL + 0x0070)
-#define OMAP343X_CONTROL_SEC_ERR_STATUS         (OMAP2_CONTROL_GENERAL + 0x0074)
-#define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG   (OMAP2_CONTROL_GENERAL + 0x0078)
-#define OMAP343X_CONTROL_STATUS                 (OMAP2_CONTROL_GENERAL + 0x0080)
-#define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
-#define OMAP343X_CONTROL_RPUB_KEY_H_4   (OMAP2_CONTROL_GENERAL + 0x00a0)
-#define OMAP343X_CONTROL_RAND_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00a8)
-#define OMAP343X_CONTROL_RAND_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00ac)
-#define OMAP343X_CONTROL_RAND_KEY_2     (OMAP2_CONTROL_GENERAL + 0x00b0)
-#define OMAP343X_CONTROL_RAND_KEY_3     (OMAP2_CONTROL_GENERAL + 0x00b4)
-#define OMAP343X_CONTROL_TEST_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00c8)
-#define OMAP343X_CONTROL_TEST_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00cc)
-#define OMAP343X_CONTROL_TEST_KEY_2     (OMAP2_CONTROL_GENERAL + 0x00d0)
-#define OMAP343X_CONTROL_TEST_KEY_3     (OMAP2_CONTROL_GENERAL + 0x00d4)
-#define OMAP343X_CONTROL_TEST_KEY_4     (OMAP2_CONTROL_GENERAL + 0x00d8)
-#define OMAP343X_CONTROL_TEST_KEY_5     (OMAP2_CONTROL_GENERAL + 0x00dc)
-#define OMAP343X_CONTROL_TEST_KEY_6     (OMAP2_CONTROL_GENERAL + 0x00e0)
-#define OMAP343X_CONTROL_TEST_KEY_7     (OMAP2_CONTROL_GENERAL + 0x00e4)
-#define OMAP343X_CONTROL_TEST_KEY_8     (OMAP2_CONTROL_GENERAL + 0x00e8)
-#define OMAP343X_CONTROL_TEST_KEY_9     (OMAP2_CONTROL_GENERAL + 0x00ec)
-#define OMAP343X_CONTROL_TEST_KEY_10    (OMAP2_CONTROL_GENERAL + 0x00f0)
-#define OMAP343X_CONTROL_TEST_KEY_11    (OMAP2_CONTROL_GENERAL + 0x00f4)
-#define OMAP343X_CONTROL_TEST_KEY_12    (OMAP2_CONTROL_GENERAL + 0x00f8)
-#define OMAP343X_CONTROL_TEST_KEY_13    (OMAP2_CONTROL_GENERAL + 0x00fc)
-#define OMAP343X_CONTROL_IVA2_BOOTADDR  (OMAP2_CONTROL_GENERAL + 0x0190)
-#define OMAP343X_CONTROL_IVA2_BOOTMOD   (OMAP2_CONTROL_GENERAL + 0x0194)
-
-/*
- * REVISIT: This list of registers is not comprehensive - there are more
- * that should be added.
- */
-
-/*
- * Control module register bit defines - these should eventually go into
- * their own regbits file.  Some of these will be complicated, depending
- * on the device type (general-purpose, emulator, test, secure, bad, other)
- * and the security mode (secure, non-secure, don't care)
- */
-/* CONTROL_DEVCONF0 bits */
-#define OMAP24XX_USBSTANDBYCTRL         (1 << 15)
-#define OMAP2_MCBSP2_CLKS_MASK          (1 << 6)
-#define OMAP2_MCBSP1_CLKS_MASK          (1 << 2)
-
-/* CONTROL_DEVCONF1 bits */
-#define OMAP2_MCBSP5_CLKS_MASK          (1 << 4) /* > 242x */
-#define OMAP2_MCBSP4_CLKS_MASK          (1 << 2) /* > 242x */
-#define OMAP2_MCBSP3_CLKS_MASK          (1 << 0) /* > 242x */
-
-/* CONTROL_STATUS bits */
-#define OMAP2_DEVICETYPE_MASK           (0x7 << 8)
-#define OMAP2_SYSBOOT_5_MASK            (1 << 5)
-#define OMAP2_SYSBOOT_4_MASK            (1 << 4)
-#define OMAP2_SYSBOOT_3_MASK            (1 << 3)
-#define OMAP2_SYSBOOT_2_MASK            (1 << 2)
-#define OMAP2_SYSBOOT_1_MASK            (1 << 1)
-#define OMAP2_SYSBOOT_0_MASK            (1 << 0)
-
-#ifndef __ASSEMBLY__
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-extern void __iomem *omap_ctrl_base_get(void);
-extern u8 omap_ctrl_readb(u16 offset);
-extern u16 omap_ctrl_readw(u16 offset);
-extern u32 omap_ctrl_readl(u16 offset);
-extern void omap_ctrl_writeb(u8 val, u16 offset);
-extern void omap_ctrl_writew(u16 val, u16 offset);
-extern void omap_ctrl_writel(u32 val, u16 offset);
-#else
-#define omap_ctrl_base_get()            0
-#define omap_ctrl_readb(x)              0
-#define omap_ctrl_readw(x)              0
-#define omap_ctrl_readl(x)              0
-#define omap_ctrl_writeb(x, y)          WARN_ON(1)
-#define omap_ctrl_writew(x, y)          WARN_ON(1)
-#define omap_ctrl_writel(x, y)          WARN_ON(1)
-#endif
-#endif  /* __ASSEMBLY__ */
-
-#endif /* __ASM_ARCH_CONTROL_H */
-
diff --git a/include/asm-arm/arch-omap/cpu.h b/include/asm-arm/arch-omap/cpu.h
deleted file mode 100644
index 52db09f83281..000000000000
--- a/include/asm-arm/arch-omap/cpu.h
+++ /dev/null
@@ -1,402 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/cpu.h
- *
- * OMAP cpu type detection
- *
- * Copyright (C) 2004, 2008 Nokia Corporation
- *
- * Written by Tony Lindgren <tony.lindgren@nokia.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-#ifndef __ASM_ARCH_OMAP_CPU_H
-#define __ASM_ARCH_OMAP_CPU_H
-
-struct omap_chip_id {
-        u8 oc;
-};
-
-#define OMAP_CHIP_INIT(x)       { .oc = x }
-
-extern unsigned int system_rev;
-
-#define omap2_cpu_rev()         ((system_rev >> 12) & 0x0f)
-
-/*
- * Test if multicore OMAP support is needed
- */
-#undef MULTI_OMAP1
-#undef MULTI_OMAP2
-#undef OMAP_NAME
-
-#ifdef CONFIG_ARCH_OMAP730
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP1
-#  define MULTI_OMAP1
-# else
-#  define OMAP_NAME omap730
-# endif
-#endif
-#ifdef CONFIG_ARCH_OMAP15XX
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP1
-#  define MULTI_OMAP1
-# else
-#  define OMAP_NAME omap1510
-# endif
-#endif
-#ifdef CONFIG_ARCH_OMAP16XX
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP1
-#  define MULTI_OMAP1
-# else
-#  define OMAP_NAME omap16xx
-# endif
-#endif
-#if (defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX))
-# if (defined(OMAP_NAME) || defined(MULTI_OMAP1))
-#  error "OMAP1 and OMAP2 can't be selected at the same time"
-# endif
-#endif
-#ifdef CONFIG_ARCH_OMAP2420
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP2
-#  define MULTI_OMAP2
-# else
-#  define OMAP_NAME omap2420
-# endif
-#endif
-#ifdef CONFIG_ARCH_OMAP2430
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP2
-#  define MULTI_OMAP2
-# else
-#  define OMAP_NAME omap2430
-# endif
-#endif
-#ifdef CONFIG_ARCH_OMAP3430
-# ifdef OMAP_NAME
-#  undef  MULTI_OMAP2
-#  define MULTI_OMAP2
-# else
-#  define OMAP_NAME omap3430
-# endif
-#endif
-
-/*
- * Macros to group OMAP into cpu classes.
- * These can be used in most places.
- * cpu_is_omap7xx():    True for OMAP730
- * cpu_is_omap15xx():   True for OMAP1510, OMAP5910 and OMAP310
- * cpu_is_omap16xx():   True for OMAP1610, OMAP5912 and OMAP1710
- * cpu_is_omap24xx():   True for OMAP2420, OMAP2422, OMAP2423, OMAP2430
- * cpu_is_omap242x():   True for OMAP2420, OMAP2422, OMAP2423
- * cpu_is_omap243x():   True for OMAP2430
- * cpu_is_omap343x():   True for OMAP3430
- */
-#define GET_OMAP_CLASS  ((system_rev >> 24) & 0xff)
-
-#define IS_OMAP_CLASS(class, id)                        \
-static inline int is_omap ##class (void)                \
-{                                                       \
-        return (GET_OMAP_CLASS == (id)) ? 1 : 0;        \
-}
-
-#define GET_OMAP_SUBCLASS       ((system_rev >> 20) & 0x0fff)
-
-#define IS_OMAP_SUBCLASS(subclass, id)                  \
-static inline int is_omap ##subclass (void)             \
-{                                                       \
-        return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;     \
-}
-
-IS_OMAP_CLASS(7xx, 0x07)
-IS_OMAP_CLASS(15xx, 0x15)
-IS_OMAP_CLASS(16xx, 0x16)
-IS_OMAP_CLASS(24xx, 0x24)
-IS_OMAP_CLASS(34xx, 0x34)
-
-IS_OMAP_SUBCLASS(242x, 0x242)
-IS_OMAP_SUBCLASS(243x, 0x243)
-IS_OMAP_SUBCLASS(343x, 0x343)
-
-#define cpu_is_omap7xx()                0
-#define cpu_is_omap15xx()               0
-#define cpu_is_omap16xx()               0
-#define cpu_is_omap24xx()               0
-#define cpu_is_omap242x()               0
-#define cpu_is_omap243x()               0
-#define cpu_is_omap34xx()               0
-#define cpu_is_omap343x()               0
-
-#if defined(MULTI_OMAP1)
-# if defined(CONFIG_ARCH_OMAP730)
-#  undef  cpu_is_omap7xx
-#  define cpu_is_omap7xx()              is_omap7xx()
-# endif
-# if defined(CONFIG_ARCH_OMAP15XX)
-#  undef  cpu_is_omap15xx
-#  define cpu_is_omap15xx()             is_omap15xx()
-# endif
-# if defined(CONFIG_ARCH_OMAP16XX)
-#  undef  cpu_is_omap16xx
-#  define cpu_is_omap16xx()             is_omap16xx()
-# endif
-#else
-# if defined(CONFIG_ARCH_OMAP730)
-#  undef  cpu_is_omap7xx
-#  define cpu_is_omap7xx()              1
-# endif
-# if defined(CONFIG_ARCH_OMAP15XX)
-#  undef  cpu_is_omap15xx
-#  define cpu_is_omap15xx()             1
-# endif
-# if defined(CONFIG_ARCH_OMAP16XX)
-#  undef  cpu_is_omap16xx
-#  define cpu_is_omap16xx()             1
-# endif
-#endif
-
-#if defined(MULTI_OMAP2)
-# if defined(CONFIG_ARCH_OMAP24XX)
-#  undef  cpu_is_omap24xx
-#  undef  cpu_is_omap242x
-#  undef  cpu_is_omap243x
-#  define cpu_is_omap24xx()             is_omap24xx()
-#  define cpu_is_omap242x()             is_omap242x()
-#  define cpu_is_omap243x()             is_omap243x()
-# endif
-# if defined(CONFIG_ARCH_OMAP34XX)
-#  undef  cpu_is_omap34xx
-#  undef  cpu_is_omap343x
-#  define cpu_is_omap34xx()             is_omap34xx()
-#  define cpu_is_omap343x()             is_omap343x()
-# endif
-#else
-# if defined(CONFIG_ARCH_OMAP24XX)
-#  undef  cpu_is_omap24xx
-#  define cpu_is_omap24xx()             1
-# endif
-# if defined(CONFIG_ARCH_OMAP2420)
-#  undef  cpu_is_omap242x
-#  define cpu_is_omap242x()             1
-# endif
-# if defined(CONFIG_ARCH_OMAP2430)
-#  undef  cpu_is_omap243x
-#  define cpu_is_omap243x()             1
-# endif
-# if defined(CONFIG_ARCH_OMAP34XX)
-#  undef  cpu_is_omap34xx
-#  define cpu_is_omap34xx()             1
-# endif
-# if defined(CONFIG_ARCH_OMAP3430)
-#  undef  cpu_is_omap343x
-#  define cpu_is_omap343x()             1
-# endif
-#endif
-
-/*
- * Macros to detect individual cpu types.
- * These are only rarely needed.
- * cpu_is_omap330():    True for OMAP330
- * cpu_is_omap730():    True for OMAP730
- * cpu_is_omap1510():   True for OMAP1510
- * cpu_is_omap1610():   True for OMAP1610
- * cpu_is_omap1611():   True for OMAP1611
- * cpu_is_omap5912():   True for OMAP5912
- * cpu_is_omap1621():   True for OMAP1621
- * cpu_is_omap1710():   True for OMAP1710
- * cpu_is_omap2420():   True for OMAP2420
- * cpu_is_omap2422():   True for OMAP2422
- * cpu_is_omap2423():   True for OMAP2423
- * cpu_is_omap2430():   True for OMAP2430
- * cpu_is_omap3430():   True for OMAP3430
- */
-#define GET_OMAP_TYPE   ((system_rev >> 16) & 0xffff)
-
-#define IS_OMAP_TYPE(type, id)                          \
-static inline int is_omap ##type (void)                 \
-{                                                       \
-        return (GET_OMAP_TYPE == (id)) ? 1 : 0;         \
-}
-
-IS_OMAP_TYPE(310, 0x0310)
-IS_OMAP_TYPE(730, 0x0730)
-IS_OMAP_TYPE(1510, 0x1510)
-IS_OMAP_TYPE(1610, 0x1610)
-IS_OMAP_TYPE(1611, 0x1611)
-IS_OMAP_TYPE(5912, 0x1611)
-IS_OMAP_TYPE(1621, 0x1621)
-IS_OMAP_TYPE(1710, 0x1710)
-IS_OMAP_TYPE(2420, 0x2420)
-IS_OMAP_TYPE(2422, 0x2422)
-IS_OMAP_TYPE(2423, 0x2423)
-IS_OMAP_TYPE(2430, 0x2430)
-IS_OMAP_TYPE(3430, 0x3430)
-
-#define cpu_is_omap310()                0
-#define cpu_is_omap730()                0
-#define cpu_is_omap1510()               0
-#define cpu_is_omap1610()               0
-#define cpu_is_omap5912()               0
-#define cpu_is_omap1611()               0
-#define cpu_is_omap1621()               0
-#define cpu_is_omap1710()               0
-#define cpu_is_omap2420()               0
-#define cpu_is_omap2422()               0
-#define cpu_is_omap2423()               0
-#define cpu_is_omap2430()               0
-#define cpu_is_omap3430()               0
-
-#if defined(MULTI_OMAP1)
-# if defined(CONFIG_ARCH_OMAP730)
-#  undef  cpu_is_omap730
-#  define cpu_is_omap730()              is_omap730()
-# endif
-#else
-# if defined(CONFIG_ARCH_OMAP730)
-#  undef  cpu_is_omap730
-#  define cpu_is_omap730()              1
-# endif
-#endif
-
-/*
- * Whether we have MULTI_OMAP1 or not, we still need to distinguish
- * between 330 vs. 1510 and 1611B/5912 vs. 1710.
- */
-#if defined(CONFIG_ARCH_OMAP15XX)
-# undef  cpu_is_omap310
-# undef  cpu_is_omap1510
-# define cpu_is_omap310()               is_omap310()
-# define cpu_is_omap1510()              is_omap1510()
-#endif
-
-#if defined(CONFIG_ARCH_OMAP16XX)
-# undef  cpu_is_omap1610
-# undef  cpu_is_omap1611
-# undef  cpu_is_omap5912
-# undef  cpu_is_omap1621
-# undef  cpu_is_omap1710
-# define cpu_is_omap1610()              is_omap1610()
-# define cpu_is_omap1611()              is_omap1611()
-# define cpu_is_omap5912()              is_omap5912()
-# define cpu_is_omap1621()              is_omap1621()
-# define cpu_is_omap1710()              is_omap1710()
-#endif
-
-#if defined(CONFIG_ARCH_OMAP24XX)
-# undef  cpu_is_omap2420
-# undef  cpu_is_omap2422
-# undef  cpu_is_omap2423
-# undef  cpu_is_omap2430
-# define cpu_is_omap2420()              is_omap2420()
-# define cpu_is_omap2422()              is_omap2422()
-# define cpu_is_omap2423()              is_omap2423()
-# define cpu_is_omap2430()              is_omap2430()
-#endif
-
-#if defined(CONFIG_ARCH_OMAP34XX)
-# undef cpu_is_omap3430
-# define cpu_is_omap3430()              is_omap3430()
-#endif
-
-/* Macros to detect if we have OMAP1 or OMAP2 */
-#define cpu_class_is_omap1()    (cpu_is_omap730() || cpu_is_omap15xx() || \
-                                cpu_is_omap16xx())
-#define cpu_class_is_omap2()    (cpu_is_omap24xx() || cpu_is_omap34xx())
-
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-/*
- * Macros to detect silicon revision of OMAP2/3 processors.
- * is_sil_rev_greater_than:     true if passed cpu type & its rev is greater.
- * is_sil_rev_lesser_than:      true if passed cpu type & its rev is lesser.
- * is_sil_rev_equal_to:         true if passed cpu type & its rev is equal.
- * get_sil_rev:                 return the silicon rev value.
- */
-#define get_sil_omap_type(rev)  ((rev & 0xffff0000) >> 16)
-#define get_sil_revision(rev)   ((rev & 0x0000f000) >> 12)
-
-#define is_sil_rev_greater_than(rev) \
-                ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \
-                (get_sil_revision(system_rev) > get_sil_revision(rev)))
-
-#define is_sil_rev_less_than(rev) \
-                ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \
-                (get_sil_revision(system_rev) < get_sil_revision(rev)))
-
-#define is_sil_rev_equal_to(rev) \
-                ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \
-                (get_sil_revision(system_rev) == get_sil_revision(rev)))
-
-#define get_sil_rev() \
-                get_sil_revision(system_rev)
-
-/* Various silicon macros defined here */
-#define OMAP2420_REV_ES1_0      0x24200000
-#define OMAP2420_REV_ES2_0      0x24201000
-#define OMAP2430_REV_ES1_0      0x24300000
-#define OMAP3430_REV_ES1_0      0x34300000
-#define OMAP3430_REV_ES2_0      0x34301000
-#define OMAP3430_REV_ES2_1      0x34302000
-#define OMAP3430_REV_ES2_2      0x34303000
-
-/*
- * omap_chip bits
- *
- * CHIP_IS_OMAP{2420,2430,3430} indicate that a particular structure is
- * valid on all chips of that type.  CHIP_IS_OMAP3430ES{1,2} indicates
- * something that is only valid on that particular ES revision.
- *
- * These bits may be ORed together to indicate structures that are
- * available on multiple chip types.
- *
- * To test whether a particular structure matches the current OMAP chip type,
- * use omap_chip_is().
- *
- */
-#define CHIP_IS_OMAP2420       (1 << 0)
-#define CHIP_IS_OMAP2430       (1 << 1)
-#define CHIP_IS_OMAP3430       (1 << 2)
-#define CHIP_IS_OMAP3430ES1    (1 << 3)
-#define CHIP_IS_OMAP3430ES2    (1 << 4)
-
-#define CHIP_IS_OMAP24XX       (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
-
-int omap_chip_is(struct omap_chip_id oci);
-
-
-/*
- * Macro to detect device type i.e. EMU/HS/TST/GP/BAD
- */
-#define DEVICE_TYPE_TEST        0
-#define DEVICE_TYPE_EMU         1
-#define DEVICE_TYPE_SEC         2
-#define DEVICE_TYPE_GP          3
-#define DEVICE_TYPE_BAD         4
-
-#define get_device_type()       ((system_rev & 0x700) >> 8)
-#define is_device_type_test()   (get_device_type() == DEVICE_TYPE_TEST)
-#define is_device_type_emu()    (get_device_type() == DEVICE_TYPE_EMU)
-#define is_device_type_sec()    (get_device_type() == DEVICE_TYPE_SEC)
-#define is_device_type_gp()     (get_device_type() == DEVICE_TYPE_GP)
-#define is_device_type_bad()    (get_device_type() == DEVICE_TYPE_BAD)
-
-void omap2_check_revision(void);
-
-#endif    /* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */
-
-#endif
diff --git a/include/asm-arm/arch-omap/debug-macro.S b/include/asm-arm/arch-omap/debug-macro.S
deleted file mode 100644
index ca4f577f9675..000000000000
--- a/include/asm-arm/arch-omap/debug-macro.S
+++ /dev/null
@@ -1,58 +0,0 @@
-/* linux/include/asm-arm/arch-omap/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-                .macro  addruart,rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-#ifdef CONFIG_ARCH_OMAP1
-                moveq   \rx, #0xff000000        @ physical base address
-                movne   \rx, #0xfe000000        @ virtual base
-                orr     \rx, \rx, #0x00fb0000
-#ifdef CONFIG_OMAP_LL_DEBUG_UART3
-                orr     \rx, \rx, #0x00009000   @ UART 3
-#endif
-#if defined(CONFIG_OMAP_LL_DEBUG_UART2) || defined(CONFIG_OMAP_LL_DEBUG_UART3)
-                orr     \rx, \rx, #0x00000800   @ UART 2 & 3
-#endif
-
-#elif  CONFIG_ARCH_OMAP2
-                moveq   \rx, #0x48000000        @ physical base address
-                movne   \rx, #0xd8000000        @ virtual base
-                orr     \rx, \rx, #0x0006a000
-#ifdef CONFIG_OMAP_LL_DEBUG_UART2
-                add     \rx, \rx, #0x00002000   @ UART 2
-#endif
-#ifdef CONFIG_OMAP_LL_DEBUG_UART3
-                add     \rx, \rx, #0x00004000   @ UART 3
-#endif
-#endif
-                .endm
-
-                .macro  senduart,rd,rx
-                strb    \rd, [\rx]
-                .endm
-
-                .macro  busyuart,rd,rx
-1001:           ldrb    \rd, [\rx, #(0x5 << 2)] @ OMAP-1510 and friends
-                and     \rd, \rd, #0x60
-                teq     \rd, #0x60
-                beq     1002f
-                ldrb    \rd, [\rx, #(0x5 << 0)] @ OMAP-730 only
-                and     \rd, \rd, #0x60
-                teq     \rd, #0x60
-                bne     1001b
-1002:
-                .endm
-
-                .macro  waituart,rd,rx
-                .endm
diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h
deleted file mode 100644
index f4dcb9587869..000000000000
--- a/include/asm-arm/arch-omap/dma.h
+++ /dev/null
@@ -1,570 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-omap/dma.h
- *
- *  Copyright (C) 2003 Nokia Corporation
- *  Author: Juha Yrjölä <juha.yrjola@nokia.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-
-/* Hardware registers for omap1 */
-#define OMAP1_DMA_BASE                  (0xfffed800)
-
-#define OMAP1_DMA_GCR                   0x400
-#define OMAP1_DMA_GSCR                  0x404
-#define OMAP1_DMA_GRST                  0x408
-#define OMAP1_DMA_HW_ID                 0x442
-#define OMAP1_DMA_PCH2_ID               0x444
-#define OMAP1_DMA_PCH0_ID               0x446
-#define OMAP1_DMA_PCH1_ID               0x448
-#define OMAP1_DMA_PCHG_ID               0x44a
-#define OMAP1_DMA_PCHD_ID               0x44c
-#define OMAP1_DMA_CAPS_0_U              0x44e
-#define OMAP1_DMA_CAPS_0_L              0x450
-#define OMAP1_DMA_CAPS_1_U              0x452
-#define OMAP1_DMA_CAPS_1_L              0x454
-#define OMAP1_DMA_CAPS_2                0x456
-#define OMAP1_DMA_CAPS_3                0x458
-#define OMAP1_DMA_CAPS_4                0x45a
-#define OMAP1_DMA_PCH2_SR               0x460
-#define OMAP1_DMA_PCH0_SR               0x480
-#define OMAP1_DMA_PCH1_SR               0x482
-#define OMAP1_DMA_PCHD_SR               0x4c0
-
-/* Hardware registers for omap2 and omap3 */
-#define OMAP24XX_DMA4_BASE              (L4_24XX_BASE + 0x56000)
-#define OMAP34XX_DMA4_BASE              (L4_34XX_BASE + 0x56000)
-
-#define OMAP_DMA4_REVISION              0x00
-#define OMAP_DMA4_GCR                   0x78
-#define OMAP_DMA4_IRQSTATUS_L0          0x08
-#define OMAP_DMA4_IRQSTATUS_L1          0x0c
-#define OMAP_DMA4_IRQSTATUS_L2          0x10
-#define OMAP_DMA4_IRQSTATUS_L3          0x14
-#define OMAP_DMA4_IRQENABLE_L0          0x18
-#define OMAP_DMA4_IRQENABLE_L1          0x1c
-#define OMAP_DMA4_IRQENABLE_L2          0x20
-#define OMAP_DMA4_IRQENABLE_L3          0x24
-#define OMAP_DMA4_SYSSTATUS             0x28
-#define OMAP_DMA4_OCP_SYSCONFIG         0x2c
-#define OMAP_DMA4_CAPS_0                0x64
-#define OMAP_DMA4_CAPS_2                0x6c
-#define OMAP_DMA4_CAPS_3                0x70
-#define OMAP_DMA4_CAPS_4                0x74
-
-#define OMAP1_LOGICAL_DMA_CH_COUNT      17
-#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT  32      /* REVISIT: Is this 32 + 2? */
-
-/* Common channel specific registers for omap1 */
-#define OMAP1_DMA_CH_BASE(n)            (0x40 * (n) + 0x00)
-#define OMAP1_DMA_CSDP(n)               (0x40 * (n) + 0x00)
-#define OMAP1_DMA_CCR(n)                (0x40 * (n) + 0x02)
-#define OMAP1_DMA_CICR(n)               (0x40 * (n) + 0x04)
-#define OMAP1_DMA_CSR(n)                (0x40 * (n) + 0x06)
-#define OMAP1_DMA_CEN(n)                (0x40 * (n) + 0x10)
-#define OMAP1_DMA_CFN(n)                (0x40 * (n) + 0x12)
-#define OMAP1_DMA_CSFI(n)               (0x40 * (n) + 0x14)
-#define OMAP1_DMA_CSEI(n)               (0x40 * (n) + 0x16)
-#define OMAP1_DMA_CPC(n)                (0x40 * (n) + 0x18)     /* 15xx only */
-#define OMAP1_DMA_CSAC(n)               (0x40 * (n) + 0x18)
-#define OMAP1_DMA_CDAC(n)               (0x40 * (n) + 0x1a)
-#define OMAP1_DMA_CDEI(n)               (0x40 * (n) + 0x1c)
-#define OMAP1_DMA_CDFI(n)               (0x40 * (n) + 0x1e)
-#define OMAP1_DMA_CLNK_CTRL(n)          (0x40 * (n) + 0x28)
-
-/* Common channel specific registers for omap2 */
-#define OMAP_DMA4_CH_BASE(n)            (0x60 * (n) + 0x80)
-#define OMAP_DMA4_CCR(n)                (0x60 * (n) + 0x80)
-#define OMAP_DMA4_CLNK_CTRL(n)          (0x60 * (n) + 0x84)
-#define OMAP_DMA4_CICR(n)               (0x60 * (n) + 0x88)
-#define OMAP_DMA4_CSR(n)                (0x60 * (n) + 0x8c)
-#define OMAP_DMA4_CSDP(n)               (0x60 * (n) + 0x90)
-#define OMAP_DMA4_CEN(n)                (0x60 * (n) + 0x94)
-#define OMAP_DMA4_CFN(n)                (0x60 * (n) + 0x98)
-#define OMAP_DMA4_CSEI(n)               (0x60 * (n) + 0xa4)
-#define OMAP_DMA4_CSFI(n)               (0x60 * (n) + 0xa8)
-#define OMAP_DMA4_CDEI(n)               (0x60 * (n) + 0xac)
-#define OMAP_DMA4_CDFI(n)               (0x60 * (n) + 0xb0)
-#define OMAP_DMA4_CSAC(n)               (0x60 * (n) + 0xb4)
-#define OMAP_DMA4_CDAC(n)               (0x60 * (n) + 0xb8)
-
-/* Channel specific registers only on omap1 */
-#define OMAP1_DMA_CSSA_L(n)             (0x40 * (n) + 0x08)
-#define OMAP1_DMA_CSSA_U(n)             (0x40 * (n) + 0x0a)
-#define OMAP1_DMA_CDSA_L(n)             (0x40 * (n) + 0x0c)
-#define OMAP1_DMA_CDSA_U(n)             (0x40 * (n) + 0x0e)
-#define OMAP1_DMA_COLOR_L(n)            (0x40 * (n) + 0x20)
-#define OMAP1_DMA_COLOR_U(n)            (0x40 * (n) + 0x22)
-#define OMAP1_DMA_CCR2(n)               (0x40 * (n) + 0x24)
-#define OMAP1_DMA_LCH_CTRL(n)           (0x40 * (n) + 0x2a)     /* not on 15xx */
-#define OMAP1_DMA_CCEN(n)               0
-#define OMAP1_DMA_CCFN(n)               0
-
-/* Channel specific registers only on omap2 */
-#define OMAP_DMA4_CSSA(n)               (0x60 * (n) + 0x9c)
-#define OMAP_DMA4_CDSA(n)               (0x60 * (n) + 0xa0)
-#define OMAP_DMA4_CCEN(n)               (0x60 * (n) + 0xbc)
-#define OMAP_DMA4_CCFN(n)               (0x60 * (n) + 0xc0)
-#define OMAP_DMA4_COLOR(n)              (0x60 * (n) + 0xc4)
-
-/* Dummy defines to keep multi-omap compiles happy */
-#define OMAP1_DMA_REVISION              0
-#define OMAP1_DMA_IRQSTATUS_L0          0
-#define OMAP1_DMA_IRQENABLE_L0          0
-#define OMAP1_DMA_OCP_SYSCONFIG         0
-#define OMAP_DMA4_HW_ID                 0
-#define OMAP_DMA4_CAPS_0_L              0
-#define OMAP_DMA4_CAPS_0_U              0
-#define OMAP_DMA4_CAPS_1_L              0
-#define OMAP_DMA4_CAPS_1_U              0
-#define OMAP_DMA4_GSCR                  0
-#define OMAP_DMA4_CPC(n)                0
-
-#define OMAP_DMA4_LCH_CTRL(n)           0
-#define OMAP_DMA4_COLOR_L(n)            0
-#define OMAP_DMA4_COLOR_U(n)            0
-#define OMAP_DMA4_CCR2(n)               0
-#define OMAP1_DMA_CSSA(n)               0
-#define OMAP1_DMA_CDSA(n)               0
-#define OMAP_DMA4_CSSA_L(n)             0
-#define OMAP_DMA4_CSSA_U(n)             0
-#define OMAP_DMA4_CDSA_L(n)             0
-#define OMAP_DMA4_CDSA_U(n)             0
-
-/*----------------------------------------------------------------------------*/
-
-/* DMA channels for omap1 */
-#define OMAP_DMA_NO_DEVICE              0
-#define OMAP_DMA_MCSI1_TX               1
-#define OMAP_DMA_MCSI1_RX               2
-#define OMAP_DMA_I2C_RX                 3
-#define OMAP_DMA_I2C_TX                 4
-#define OMAP_DMA_EXT_NDMA_REQ           5
-#define OMAP_DMA_EXT_NDMA_REQ2          6
-#define OMAP_DMA_UWIRE_TX               7
-#define OMAP_DMA_MCBSP1_TX              8
-#define OMAP_DMA_MCBSP1_RX              9
-#define OMAP_DMA_MCBSP3_TX              10
-#define OMAP_DMA_MCBSP3_RX              11
-#define OMAP_DMA_UART1_TX               12
-#define OMAP_DMA_UART1_RX               13
-#define OMAP_DMA_UART2_TX               14
-#define OMAP_DMA_UART2_RX               15
-#define OMAP_DMA_MCBSP2_TX              16
-#define OMAP_DMA_MCBSP2_RX              17
-#define OMAP_DMA_UART3_TX               18
-#define OMAP_DMA_UART3_RX               19
-#define OMAP_DMA_CAMERA_IF_RX           20
-#define OMAP_DMA_MMC_TX                 21
-#define OMAP_DMA_MMC_RX                 22
-#define OMAP_DMA_NAND                   23
-#define OMAP_DMA_IRQ_LCD_LINE           24
-#define OMAP_DMA_MEMORY_STICK           25
-#define OMAP_DMA_USB_W2FC_RX0           26
-#define OMAP_DMA_USB_W2FC_RX1           27
-#define OMAP_DMA_USB_W2FC_RX2           28
-#define OMAP_DMA_USB_W2FC_TX0           29
-#define OMAP_DMA_USB_W2FC_TX1           30
-#define OMAP_DMA_USB_W2FC_TX2           31
-
-/* These are only for 1610 */
-#define OMAP_DMA_CRYPTO_DES_IN          32
-#define OMAP_DMA_SPI_TX                 33
-#define OMAP_DMA_SPI_RX                 34
-#define OMAP_DMA_CRYPTO_HASH            35
-#define OMAP_DMA_CCP_ATTN               36
-#define OMAP_DMA_CCP_FIFO_NOT_EMPTY     37
-#define OMAP_DMA_CMT_APE_TX_CHAN_0      38
-#define OMAP_DMA_CMT_APE_RV_CHAN_0      39
-#define OMAP_DMA_CMT_APE_TX_CHAN_1      40
-#define OMAP_DMA_CMT_APE_RV_CHAN_1      41
-#define OMAP_DMA_CMT_APE_TX_CHAN_2      42
-#define OMAP_DMA_CMT_APE_RV_CHAN_2      43
-#define OMAP_DMA_CMT_APE_TX_CHAN_3      44
-#define OMAP_DMA_CMT_APE_RV_CHAN_3      45
-#define OMAP_DMA_CMT_APE_TX_CHAN_4      46
-#define OMAP_DMA_CMT_APE_RV_CHAN_4      47
-#define OMAP_DMA_CMT_APE_TX_CHAN_5      48
-#define OMAP_DMA_CMT_APE_RV_CHAN_5      49
-#define OMAP_DMA_CMT_APE_TX_CHAN_6      50
-#define OMAP_DMA_CMT_APE_RV_CHAN_6      51
-#define OMAP_DMA_CMT_APE_TX_CHAN_7      52
-#define OMAP_DMA_CMT_APE_RV_CHAN_7      53
-#define OMAP_DMA_MMC2_TX                54
-#define OMAP_DMA_MMC2_RX                55
-#define OMAP_DMA_CRYPTO_DES_OUT         56
-
-/* DMA channels for 24xx */
-#define OMAP24XX_DMA_NO_DEVICE          0
-#define OMAP24XX_DMA_XTI_DMA            1       /* S_DMA_0 */
-#define OMAP24XX_DMA_EXT_DMAREQ0        2       /* S_DMA_1 */
-#define OMAP24XX_DMA_EXT_DMAREQ1        3       /* S_DMA_2 */
-#define OMAP24XX_DMA_GPMC               4       /* S_DMA_3 */
-#define OMAP24XX_DMA_GFX                5       /* S_DMA_4 */
-#define OMAP24XX_DMA_DSS                6       /* S_DMA_5 */
-#define OMAP242X_DMA_VLYNQ_TX           7       /* S_DMA_6 */
-#define OMAP24XX_DMA_EXT_DMAREQ2        7       /* S_DMA_6 */
-#define OMAP24XX_DMA_CWT                8       /* S_DMA_7 */
-#define OMAP24XX_DMA_AES_TX             9       /* S_DMA_8 */
-#define OMAP24XX_DMA_AES_RX             10      /* S_DMA_9 */
-#define OMAP24XX_DMA_DES_TX             11      /* S_DMA_10 */
-#define OMAP24XX_DMA_DES_RX             12      /* S_DMA_11 */
-#define OMAP24XX_DMA_SHA1MD5_RX         13      /* S_DMA_12 */
-#define OMAP34XX_DMA_SHA2MD5_RX         13      /* S_DMA_12 */
-#define OMAP242X_DMA_EXT_DMAREQ2        14      /* S_DMA_13 */
-#define OMAP242X_DMA_EXT_DMAREQ3        15      /* S_DMA_14 */
-#define OMAP242X_DMA_EXT_DMAREQ4        16      /* S_DMA_15 */
-#define OMAP242X_DMA_EAC_AC_RD          17      /* S_DMA_16 */
-#define OMAP242X_DMA_EAC_AC_WR          18      /* S_DMA_17 */
-#define OMAP242X_DMA_EAC_MD_UL_RD       19      /* S_DMA_18 */
-#define OMAP242X_DMA_EAC_MD_UL_WR       20      /* S_DMA_19 */
-#define OMAP242X_DMA_EAC_MD_DL_RD       21      /* S_DMA_20 */
-#define OMAP242X_DMA_EAC_MD_DL_WR       22      /* S_DMA_21 */
-#define OMAP242X_DMA_EAC_BT_UL_RD       23      /* S_DMA_22 */
-#define OMAP242X_DMA_EAC_BT_UL_WR       24      /* S_DMA_23 */
-#define OMAP242X_DMA_EAC_BT_DL_RD       25      /* S_DMA_24 */
-#define OMAP242X_DMA_EAC_BT_DL_WR       26      /* S_DMA_25 */
-#define OMAP243X_DMA_EXT_DMAREQ3        14      /* S_DMA_13 */
-#define OMAP24XX_DMA_SPI3_TX0           15      /* S_DMA_14 */
-#define OMAP24XX_DMA_SPI3_RX0           16      /* S_DMA_15 */
-#define OMAP24XX_DMA_MCBSP3_TX          17      /* S_DMA_16 */
-#define OMAP24XX_DMA_MCBSP3_RX          18      /* S_DMA_17 */
-#define OMAP24XX_DMA_MCBSP4_TX          19      /* S_DMA_18 */
-#define OMAP24XX_DMA_MCBSP4_RX          20      /* S_DMA_19 */
-#define OMAP24XX_DMA_MCBSP5_TX          21      /* S_DMA_20 */
-#define OMAP24XX_DMA_MCBSP5_RX          22      /* S_DMA_21 */
-#define OMAP24XX_DMA_SPI3_TX1           23      /* S_DMA_22 */
-#define OMAP24XX_DMA_SPI3_RX1           24      /* S_DMA_23 */
-#define OMAP243X_DMA_EXT_DMAREQ4        25      /* S_DMA_24 */
-#define OMAP243X_DMA_EXT_DMAREQ5        26      /* S_DMA_25 */
-#define OMAP34XX_DMA_I2C3_TX            25      /* S_DMA_24 */
-#define OMAP34XX_DMA_I2C3_RX            26      /* S_DMA_25 */
-#define OMAP24XX_DMA_I2C1_TX            27      /* S_DMA_26 */
-#define OMAP24XX_DMA_I2C1_RX            28      /* S_DMA_27 */
-#define OMAP24XX_DMA_I2C2_TX            29      /* S_DMA_28 */
-#define OMAP24XX_DMA_I2C2_RX            30      /* S_DMA_29 */
-#define OMAP24XX_DMA_MCBSP1_TX          31      /* S_DMA_30 */
-#define OMAP24XX_DMA_MCBSP1_RX          32      /* S_DMA_31 */
-#define OMAP24XX_DMA_MCBSP2_TX          33      /* S_DMA_32 */
-#define OMAP24XX_DMA_MCBSP2_RX          34      /* S_DMA_33 */
-#define OMAP24XX_DMA_SPI1_TX0           35      /* S_DMA_34 */
-#define OMAP24XX_DMA_SPI1_RX0           36      /* S_DMA_35 */
-#define OMAP24XX_DMA_SPI1_TX1           37      /* S_DMA_36 */
-#define OMAP24XX_DMA_SPI1_RX1           38      /* S_DMA_37 */
-#define OMAP24XX_DMA_SPI1_TX2           39      /* S_DMA_38 */
-#define OMAP24XX_DMA_SPI1_RX2           40      /* S_DMA_39 */
-#define OMAP24XX_DMA_SPI1_TX3           41      /* S_DMA_40 */
-#define OMAP24XX_DMA_SPI1_RX3           42      /* S_DMA_41 */
-#define OMAP24XX_DMA_SPI2_TX0           43      /* S_DMA_42 */
-#define OMAP24XX_DMA_SPI2_RX0           44      /* S_DMA_43 */
-#define OMAP24XX_DMA_SPI2_TX1           45      /* S_DMA_44 */
-#define OMAP24XX_DMA_SPI2_RX1           46      /* S_DMA_45 */
-#define OMAP24XX_DMA_MMC2_TX            47      /* S_DMA_46 */
-#define OMAP24XX_DMA_MMC2_RX            48      /* S_DMA_47 */
-#define OMAP24XX_DMA_UART1_TX           49      /* S_DMA_48 */
-#define OMAP24XX_DMA_UART1_RX           50      /* S_DMA_49 */
-#define OMAP24XX_DMA_UART2_TX           51      /* S_DMA_50 */
-#define OMAP24XX_DMA_UART2_RX           52      /* S_DMA_51 */
-#define OMAP24XX_DMA_UART3_TX           53      /* S_DMA_52 */
-#define OMAP24XX_DMA_UART3_RX           54      /* S_DMA_53 */
-#define OMAP24XX_DMA_USB_W2FC_TX0       55      /* S_DMA_54 */
-#define OMAP24XX_DMA_USB_W2FC_RX0       56      /* S_DMA_55 */
-#define OMAP24XX_DMA_USB_W2FC_TX1       57      /* S_DMA_56 */
-#define OMAP24XX_DMA_USB_W2FC_RX1       58      /* S_DMA_57 */
-#define OMAP24XX_DMA_USB_W2FC_TX2       59      /* S_DMA_58 */
-#define OMAP24XX_DMA_USB_W2FC_RX2       60      /* S_DMA_59 */
-#define OMAP24XX_DMA_MMC1_TX            61      /* S_DMA_60 */
-#define OMAP24XX_DMA_MMC1_RX            62      /* S_DMA_61 */
-#define OMAP24XX_DMA_MS                 63      /* S_DMA_62 */
-#define OMAP242X_DMA_EXT_DMAREQ5        64      /* S_DMA_63 */
-#define OMAP243X_DMA_EXT_DMAREQ6        64      /* S_DMA_63 */
-#define OMAP34XX_DMA_EXT_DMAREQ3        64      /* S_DMA_63 */
-#define OMAP34XX_DMA_AES2_TX            65      /* S_DMA_64 */
-#define OMAP34XX_DMA_AES2_RX            66      /* S_DMA_65 */
-#define OMAP34XX_DMA_DES2_TX            67      /* S_DMA_66 */
-#define OMAP34XX_DMA_DES2_RX            68      /* S_DMA_67 */
-#define OMAP34XX_DMA_SHA1MD5_RX         69      /* S_DMA_68 */
-#define OMAP34XX_DMA_SPI4_TX0           70      /* S_DMA_69 */
-#define OMAP34XX_DMA_SPI4_RX0           71      /* S_DMA_70 */
-#define OMAP34XX_DSS_DMA0               72      /* S_DMA_71 */
-#define OMAP34XX_DSS_DMA1               73      /* S_DMA_72 */
-#define OMAP34XX_DSS_DMA2               74      /* S_DMA_73 */
-#define OMAP34XX_DSS_DMA3               75      /* S_DMA_74 */
-#define OMAP34XX_DMA_MMC3_TX            77      /* S_DMA_76 */
-#define OMAP34XX_DMA_MMC3_RX            78      /* S_DMA_77 */
-#define OMAP34XX_DMA_USIM_TX            79      /* S_DMA_78 */
-#define OMAP34XX_DMA_USIM_RX            80      /* S_DMA_79 */
-
-/*----------------------------------------------------------------------------*/
-
-/* Hardware registers for LCD DMA */
-#define OMAP1510_DMA_LCD_BASE           (0xfffedb00)
-#define OMAP1510_DMA_LCD_CTRL           (OMAP1510_DMA_LCD_BASE + 0x00)
-#define OMAP1510_DMA_LCD_TOP_F1_L       (OMAP1510_DMA_LCD_BASE + 0x02)
-#define OMAP1510_DMA_LCD_TOP_F1_U       (OMAP1510_DMA_LCD_BASE + 0x04)
-#define OMAP1510_DMA_LCD_BOT_F1_L       (OMAP1510_DMA_LCD_BASE + 0x06)
-#define OMAP1510_DMA_LCD_BOT_F1_U       (OMAP1510_DMA_LCD_BASE + 0x08)
-
-#define OMAP1610_DMA_LCD_BASE           (0xfffee300)
-#define OMAP1610_DMA_LCD_CSDP           (OMAP1610_DMA_LCD_BASE + 0xc0)
-#define OMAP1610_DMA_LCD_CCR            (OMAP1610_DMA_LCD_BASE + 0xc2)
-#define OMAP1610_DMA_LCD_CTRL           (OMAP1610_DMA_LCD_BASE + 0xc4)
-#define OMAP1610_DMA_LCD_TOP_B1_L       (OMAP1610_DMA_LCD_BASE + 0xc8)
-#define OMAP1610_DMA_LCD_TOP_B1_U       (OMAP1610_DMA_LCD_BASE + 0xca)
-#define OMAP1610_DMA_LCD_BOT_B1_L       (OMAP1610_DMA_LCD_BASE + 0xcc)
-#define OMAP1610_DMA_LCD_BOT_B1_U       (OMAP1610_DMA_LCD_BASE + 0xce)
-#define OMAP1610_DMA_LCD_TOP_B2_L       (OMAP1610_DMA_LCD_BASE + 0xd0)
-#define OMAP1610_DMA_LCD_TOP_B2_U       (OMAP1610_DMA_LCD_BASE + 0xd2)
-#define OMAP1610_DMA_LCD_BOT_B2_L       (OMAP1610_DMA_LCD_BASE + 0xd4)
-#define OMAP1610_DMA_LCD_BOT_B2_U       (OMAP1610_DMA_LCD_BASE + 0xd6)
-#define OMAP1610_DMA_LCD_SRC_EI_B1      (OMAP1610_DMA_LCD_BASE + 0xd8)
-#define OMAP1610_DMA_LCD_SRC_FI_B1_L    (OMAP1610_DMA_LCD_BASE + 0xda)
-#define OMAP1610_DMA_LCD_SRC_EN_B1      (OMAP1610_DMA_LCD_BASE + 0xe0)
-#define OMAP1610_DMA_LCD_SRC_FN_B1      (OMAP1610_DMA_LCD_BASE + 0xe4)
-#define OMAP1610_DMA_LCD_LCH_CTRL       (OMAP1610_DMA_LCD_BASE + 0xea)
-#define OMAP1610_DMA_LCD_SRC_FI_B1_U    (OMAP1610_DMA_LCD_BASE + 0xf4)
-
-#define OMAP1_DMA_TOUT_IRQ              (1 << 0)
-#define OMAP_DMA_DROP_IRQ               (1 << 1)
-#define OMAP_DMA_HALF_IRQ               (1 << 2)
-#define OMAP_DMA_FRAME_IRQ              (1 << 3)
-#define OMAP_DMA_LAST_IRQ               (1 << 4)
-#define OMAP_DMA_BLOCK_IRQ              (1 << 5)
-#define OMAP1_DMA_SYNC_IRQ              (1 << 6)
-#define OMAP2_DMA_PKT_IRQ               (1 << 7)
-#define OMAP2_DMA_TRANS_ERR_IRQ         (1 << 8)
-#define OMAP2_DMA_SECURE_ERR_IRQ        (1 << 9)
-#define OMAP2_DMA_SUPERVISOR_ERR_IRQ    (1 << 10)
-#define OMAP2_DMA_MISALIGNED_ERR_IRQ    (1 << 11)
-
-#define OMAP_DMA_DATA_TYPE_S8           0x00
-#define OMAP_DMA_DATA_TYPE_S16          0x01
-#define OMAP_DMA_DATA_TYPE_S32          0x02
-
-#define OMAP_DMA_SYNC_ELEMENT           0x00
-#define OMAP_DMA_SYNC_FRAME             0x01
-#define OMAP_DMA_SYNC_BLOCK             0x02
-#define OMAP_DMA_SYNC_PACKET            0x03
-
-#define OMAP_DMA_SRC_SYNC               0x01
-#define OMAP_DMA_DST_SYNC               0x00
-
-#define OMAP_DMA_PORT_EMIFF             0x00
-#define OMAP_DMA_PORT_EMIFS             0x01
-#define OMAP_DMA_PORT_OCP_T1            0x02
-#define OMAP_DMA_PORT_TIPB              0x03
-#define OMAP_DMA_PORT_OCP_T2            0x04
-#define OMAP_DMA_PORT_MPUI              0x05
-
-#define OMAP_DMA_AMODE_CONSTANT         0x00
-#define OMAP_DMA_AMODE_POST_INC         0x01
-#define OMAP_DMA_AMODE_SINGLE_IDX       0x02
-#define OMAP_DMA_AMODE_DOUBLE_IDX       0x03
-
-#define DMA_DEFAULT_FIFO_DEPTH          0x10
-#define DMA_DEFAULT_ARB_RATE            0x01
-/* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
-#define DMA_THREAD_RESERVE_NORM         (0x00 << 12) /* Def */
-#define DMA_THREAD_RESERVE_ONET         (0x01 << 12)
-#define DMA_THREAD_RESERVE_TWOT         (0x02 << 12)
-#define DMA_THREAD_RESERVE_THREET       (0x03 << 12)
-#define DMA_THREAD_FIFO_NONE            (0x00 << 14) /* Def */
-#define DMA_THREAD_FIFO_75              (0x01 << 14)
-#define DMA_THREAD_FIFO_25              (0x02 << 14)
-#define DMA_THREAD_FIFO_50              (0x03 << 14)
-
-/* Chaining modes*/
-#ifndef CONFIG_ARCH_OMAP1
-#define OMAP_DMA_STATIC_CHAIN           0x1
-#define OMAP_DMA_DYNAMIC_CHAIN          0x2
-#define OMAP_DMA_CHAIN_ACTIVE           0x1
-#define OMAP_DMA_CHAIN_INACTIVE         0x0
-#endif
-
-#define DMA_CH_PRIO_HIGH                0x1
-#define DMA_CH_PRIO_LOW                 0x0 /* Def */
-
-/* LCD DMA block numbers */
-enum {
-        OMAP_LCD_DMA_B1_TOP,
-        OMAP_LCD_DMA_B1_BOTTOM,
-        OMAP_LCD_DMA_B2_TOP,
-        OMAP_LCD_DMA_B2_BOTTOM
-};
-
-enum omap_dma_burst_mode {
-        OMAP_DMA_DATA_BURST_DIS = 0,
-        OMAP_DMA_DATA_BURST_4,
-        OMAP_DMA_DATA_BURST_8,
-        OMAP_DMA_DATA_BURST_16,
-};
-
-enum end_type {
-        OMAP_DMA_LITTLE_ENDIAN = 0,
-        OMAP_DMA_BIG_ENDIAN
-};
-
-enum omap_dma_color_mode {
-        OMAP_DMA_COLOR_DIS = 0,
-        OMAP_DMA_CONSTANT_FILL,
-        OMAP_DMA_TRANSPARENT_COPY
-};
-
-enum omap_dma_write_mode {
-        OMAP_DMA_WRITE_NON_POSTED = 0,
-        OMAP_DMA_WRITE_POSTED,
-        OMAP_DMA_WRITE_LAST_NON_POSTED
-};
-
-enum omap_dma_channel_mode {
-        OMAP_DMA_LCH_2D = 0,
-        OMAP_DMA_LCH_G,
-        OMAP_DMA_LCH_P,
-        OMAP_DMA_LCH_PD
-};
-
-struct omap_dma_channel_params {
-        int data_type;          /* data type 8,16,32 */
-        int elem_count;         /* number of elements in a frame */
-        int frame_count;        /* number of frames in a element */
-
-        int src_port;           /* Only on OMAP1 REVISIT: Is this needed? */
-        int src_amode;          /* constant, post increment, indexed,
-                                        double indexed */
-        unsigned long src_start;        /* source address : physical */
-        int src_ei;             /* source element index */
-        int src_fi;             /* source frame index */
-
-        int dst_port;           /* Only on OMAP1 REVISIT: Is this needed? */
-        int dst_amode;          /* constant, post increment, indexed,
-                                        double indexed */
-        unsigned long dst_start;        /* source address : physical */
-        int dst_ei;             /* source element index */
-        int dst_fi;             /* source frame index */
-
-        int trigger;            /* trigger attached if the channel is
-                                        synchronized */
-        int sync_mode;          /* sycn on element, frame , block or packet */
-        int src_or_dst_synch;   /* source synch(1) or destination synch(0) */
-
-        int ie;                 /* interrupt enabled */
-
-        unsigned char read_prio;/* read priority */
-        unsigned char write_prio;/* write priority */
-
-#ifndef CONFIG_ARCH_OMAP1
-        enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
-#endif
-};
-
-
-extern void omap_set_dma_priority(int lch, int dst_port, int priority);
-extern int omap_request_dma(int dev_id, const char *dev_name,
-                        void (*callback)(int lch, u16 ch_status, void *data),
-                        void *data, int *dma_ch);
-extern void omap_enable_dma_irq(int ch, u16 irq_bits);
-extern void omap_disable_dma_irq(int ch, u16 irq_bits);
-extern void omap_free_dma(int ch);
-extern void omap_start_dma(int lch);
-extern void omap_stop_dma(int lch);
-extern void omap_set_dma_transfer_params(int lch, int data_type,
-                                         int elem_count, int frame_count,
-                                         int sync_mode,
-                                         int dma_trigger, int src_or_dst_synch);
-extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
-                                    u32 color);
-extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
-extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
-
-extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
-                                    unsigned long src_start,
-                                    int src_ei, int src_fi);
-extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
-extern void omap_set_dma_src_data_pack(int lch, int enable);
-extern void omap_set_dma_src_burst_mode(int lch,
-                                        enum omap_dma_burst_mode burst_mode);
-
-extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
-                                     unsigned long dest_start,
-                                     int dst_ei, int dst_fi);
-extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
-extern void omap_set_dma_dest_data_pack(int lch, int enable);
-extern void omap_set_dma_dest_burst_mode(int lch,
-                                         enum omap_dma_burst_mode burst_mode);
-
-extern void omap_set_dma_params(int lch,
-                                struct omap_dma_channel_params *params);
-
-extern void omap_dma_link_lch(int lch_head, int lch_queue);
-extern void omap_dma_unlink_lch(int lch_head, int lch_queue);
-
-extern int omap_set_dma_callback(int lch,
-                        void (*callback)(int lch, u16 ch_status, void *data),
-                        void *data);
-extern dma_addr_t omap_get_dma_src_pos(int lch);
-extern dma_addr_t omap_get_dma_dst_pos(int lch);
-extern void omap_clear_dma(int lch);
-extern int omap_get_dma_active_status(int lch);
-extern int omap_dma_running(void);
-extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
-                                       int tparams);
-extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
-                                 unsigned char write_prio);
-extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
-extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
-extern int omap_get_dma_index(int lch, int *ei, int *fi);
-
-/* Chaining APIs */
-#ifndef CONFIG_ARCH_OMAP1
-extern int omap_request_dma_chain(int dev_id, const char *dev_name,
-                                  void (*callback) (int chain_id, u16 ch_status,
-                                                    void *data),
-                                  int *chain_id, int no_of_chans,
-                                  int chain_mode,
-                                  struct omap_dma_channel_params params);
-extern int omap_free_dma_chain(int chain_id);
-extern int omap_dma_chain_a_transfer(int chain_id, int src_start,
-                                     int dest_start, int elem_count,
-                                     int frame_count, void *callbk_data);
-extern int omap_start_dma_chain_transfers(int chain_id);
-extern int omap_stop_dma_chain_transfers(int chain_id);
-extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi);
-extern int omap_get_dma_chain_dst_pos(int chain_id);
-extern int omap_get_dma_chain_src_pos(int chain_id);
-
-extern int omap_modify_dma_chain_params(int chain_id,
-                                        struct omap_dma_channel_params params);
-extern int omap_dma_chain_status(int chain_id);
-#endif
-
-/* LCD DMA functions */
-extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
-                                void *data);
-extern void omap_free_lcd_dma(void);
-extern void omap_setup_lcd_dma(void);
-extern void omap_enable_lcd_dma(void);
-extern void omap_stop_lcd_dma(void);
-extern void omap_set_lcd_dma_ext_controller(int external);
-extern void omap_set_lcd_dma_single_transfer(int single);
-extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
-                                int data_type);
-extern void omap_set_lcd_dma_b1_rotation(int rotate);
-extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres);
-extern void omap_set_lcd_dma_b1_mirror(int mirror);
-extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale);
-
-#endif /* __ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-omap/dmtimer.h b/include/asm-arm/arch-omap/dmtimer.h
deleted file mode 100644
index 02b29e8437ae..000000000000
--- a/include/asm-arm/arch-omap/dmtimer.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/dmtimer.h
- *
- * OMAP Dual-Mode Timers
- *
- * Copyright (C) 2005 Nokia Corporation
- * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
- * PWM and clock framwork support by Timo Teras.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the  GNU General Public License along
- * with this program; if not, write  to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_DMTIMER_H
-#define __ASM_ARCH_DMTIMER_H
-
-/* clock sources */
-#define OMAP_TIMER_SRC_SYS_CLK                  0x00
-#define OMAP_TIMER_SRC_32_KHZ                   0x01
-#define OMAP_TIMER_SRC_EXT_CLK                  0x02
-
-/* timer interrupt enable bits */
-#define OMAP_TIMER_INT_CAPTURE                  (1 << 2)
-#define OMAP_TIMER_INT_OVERFLOW                 (1 << 1)
-#define OMAP_TIMER_INT_MATCH                    (1 << 0)
-
-/* trigger types */
-#define OMAP_TIMER_TRIGGER_NONE                 0x00
-#define OMAP_TIMER_TRIGGER_OVERFLOW             0x01
-#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
-
-struct omap_dm_timer;
-struct clk;
-
-int omap_dm_timer_init(void);
-
-struct omap_dm_timer *omap_dm_timer_request(void);
-struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
-void omap_dm_timer_free(struct omap_dm_timer *timer);
-void omap_dm_timer_enable(struct omap_dm_timer *timer);
-void omap_dm_timer_disable(struct omap_dm_timer *timer);
-
-int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
-
-u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
-struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
-
-void omap_dm_timer_trigger(struct omap_dm_timer *timer);
-void omap_dm_timer_start(struct omap_dm_timer *timer);
-void omap_dm_timer_stop(struct omap_dm_timer *timer);
-
-void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
-void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
-void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
-void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
-void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
-void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
-
-void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
-
-unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
-void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
-unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
-void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
-
-int omap_dm_timers_active(void);
-
-
-#endif /* __ASM_ARCH_DMTIMER_H */
diff --git a/include/asm-arm/arch-omap/eac.h b/include/asm-arm/arch-omap/eac.h
deleted file mode 100644
index ccee3b0700b3..000000000000
--- a/include/asm-arm/arch-omap/eac.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap2/eac.h
- *
- * Defines for Enhanced Audio Controller
- *
- * Contact: Jarkko Nikula <jarkko.nikula@nokia.com>
- *
- * Copyright (C) 2006 Nokia Corporation
- * Copyright (C) 2004 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- */
-
-#ifndef __ASM_ARM_ARCH_OMAP2_EAC_H
-#define __ASM_ARM_ARCH_OMAP2_EAC_H
-
-#include <asm/arch/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/irq.h>
-
-#include <sound/core.h>
-
-/* master codec clock source */
-#define EAC_MCLK_EXT_MASK       0x100
-enum eac_mclk_src {
-        EAC_MCLK_INT_11290000, /* internal 96 MHz / 8.5 = 11.29 Mhz */
-        EAC_MCLK_EXT_11289600 = EAC_MCLK_EXT_MASK,
-        EAC_MCLK_EXT_12288000,
-        EAC_MCLK_EXT_2x11289600,
-        EAC_MCLK_EXT_2x12288000,
-};
-
-/* codec port interface mode */
-enum eac_codec_mode {
-        EAC_CODEC_PCM,
-        EAC_CODEC_AC97,
-        EAC_CODEC_I2S_MASTER, /* codec port, I.e. EAC is the master */
-        EAC_CODEC_I2S_SLAVE,
-};
-
-/* configuration structure for I2S mode */
-struct eac_i2s_conf {
-        /* if enabled, then first data slot (left channel) is signaled as
-         * positive level of frame sync EAC.AC_FS */
-        unsigned        polarity_changed_mode:1;
-        /* if enabled, then serial data starts one clock cycle after the
-         * of EAC.AC_FS for first audio slot */
-        unsigned        sync_delay_enable:1;
-};
-
-/* configuration structure for EAC codec port */
-struct eac_codec {
-        enum eac_mclk_src       mclk_src;
-
-        enum eac_codec_mode     codec_mode;
-        union {
-                struct eac_i2s_conf     i2s;
-        } codec_conf;
-
-        int             default_rate; /* audio sampling rate */
-
-        int             (* set_power)(void *private_data, int dac, int adc);
-        int             (* register_controls)(void *private_data,
-                                              struct snd_card *card);
-        const char      *short_name;
-
-        void            *private_data;
-};
-
-/* structure for passing platform dependent data to the EAC driver */
-struct eac_platform_data {
-        int     (* init)(struct device *eac_dev);
-        void    (* cleanup)(struct device *eac_dev);
-        /* these callbacks are used to configure & control external MCLK
-         * source. NULL if not used */
-        int     (* enable_ext_clocks)(struct device *eac_dev);
-        void    (* disable_ext_clocks)(struct device *eac_dev);
-};
-
-extern void omap_init_eac(struct eac_platform_data *pdata);
-
-extern int eac_register_codec(struct device *eac_dev, struct eac_codec *codec);
-extern void eac_unregister_codec(struct device *eac_dev);
-
-extern int eac_set_mode(struct device *eac_dev, int play, int rec);
-
-#endif /* __ASM_ARM_ARCH_OMAP2_EAC_H */
diff --git a/include/asm-arm/arch-omap/entry-macro.S b/include/asm-arm/arch-omap/entry-macro.S
deleted file mode 100644
index 67ed7839e782..000000000000
--- a/include/asm-arm/arch-omap/entry-macro.S
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * include/asm-arm/arch-omap/entry-macro.S
- *
- * Low-level IRQ helper macros for OMAP-based platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <asm/arch/hardware.h>
-#include <asm/arch/io.h>
-#include <asm/arch/irqs.h>
-
-#if defined(CONFIG_ARCH_OMAP1)
-
-#if defined(CONFIG_ARCH_OMAP730) && \
-        (defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX))
-#error "FIXME: OMAP730 doesn't support multiple-OMAP"
-#elif defined(CONFIG_ARCH_OMAP730)
-#define INT_IH2_IRQ             INT_730_IH2_IRQ
-#elif defined(CONFIG_ARCH_OMAP15XX)
-#define INT_IH2_IRQ             INT_1510_IH2_IRQ
-#elif defined(CONFIG_ARCH_OMAP16XX)
-#define INT_IH2_IRQ             INT_1610_IH2_IRQ
-#else
-#warning "IH2 IRQ defaulted"
-#define INT_IH2_IRQ             INT_1510_IH2_IRQ
-#endif
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \base, =IO_ADDRESS(OMAP_IH1_BASE)
-                ldr     \irqnr, [\base, #IRQ_ITR_REG_OFFSET]
-                ldr     \tmp, [\base, #IRQ_MIR_REG_OFFSET]
-                mov     \irqstat, #0xffffffff
-                bic     \tmp, \irqstat, \tmp
-                tst     \irqnr, \tmp
-                beq     1510f
-
-                ldr     \irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET]
-                cmp     \irqnr, #0
-                ldreq   \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
-                cmpeq   \irqnr, #INT_IH2_IRQ
-                ldreq   \base, =IO_ADDRESS(OMAP_IH2_BASE)
-                ldreq   \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
-                addeqs  \irqnr, \irqnr, #32
-1510:
-                .endm
-
-#elif defined(CONFIG_ARCH_OMAP24XX)
-
-#include <asm/arch/omap24xx.h>
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \base, =OMAP2_VA_IC_BASE
-                ldr     \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
-                cmp     \irqnr, #0x0
-                bne     2222f
-                ldr     \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
-                cmp     \irqnr, #0x0
-                bne     2222f
-                ldr     \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
-                cmp     \irqnr, #0x0
-2222:
-                ldrne   \irqnr, [\base, #IRQ_SIR_IRQ]
-
-                .endm
-
-                .macro  irq_prio_table
-                .endm
-
-#endif
diff --git a/include/asm-arm/arch-omap/fpga.h b/include/asm-arm/arch-omap/fpga.h
deleted file mode 100644
index f420881d2a3b..000000000000
--- a/include/asm-arm/arch-omap/fpga.h
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/fpga.h
- *
- * Interrupt handler for OMAP-1510 FPGA
- *
- * Copyright (C) 2001 RidgeRun, Inc.
- * Author: Greg Lonnon <glonnon@ridgerun.com>
- *
- * Copyright (C) 2002 MontaVista Software, Inc.
- *
- * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
- * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_OMAP_FPGA_H
-#define __ASM_ARCH_OMAP_FPGA_H
-
-#if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
-extern void omap1510_fpga_init_irq(void);
-#else
-#define omap1510_fpga_init_irq()        (0)
-#endif
-
-#define fpga_read(reg)                  __raw_readb(reg)
-#define fpga_write(val, reg)            __raw_writeb(val, reg)
-
-/*
- * ---------------------------------------------------------------------------
- *  H2/P2 Debug board FPGA
- * ---------------------------------------------------------------------------
- */
-/* maps in the FPGA registers and the ETHR registers */
-#define H2P2_DBG_FPGA_BASE              0xE8000000      /* VA */
-#define H2P2_DBG_FPGA_SIZE              SZ_4K           /* SIZE */
-#define H2P2_DBG_FPGA_START             0x04000000      /* PA */
-
-#define H2P2_DBG_FPGA_ETHR_START        (H2P2_DBG_FPGA_START + 0x300)
-#define H2P2_DBG_FPGA_FPGA_REV          (H2P2_DBG_FPGA_BASE + 0x10)     /* FPGA Revision */
-#define H2P2_DBG_FPGA_BOARD_REV         (H2P2_DBG_FPGA_BASE + 0x12)     /* Board Revision */
-#define H2P2_DBG_FPGA_GPIO              (H2P2_DBG_FPGA_BASE + 0x14)     /* GPIO outputs */
-#define H2P2_DBG_FPGA_LEDS              (H2P2_DBG_FPGA_BASE + 0x16)     /* LEDs outputs */
-#define H2P2_DBG_FPGA_MISC_INPUTS       (H2P2_DBG_FPGA_BASE + 0x18)     /* Misc inputs */
-#define H2P2_DBG_FPGA_LAN_STATUS        (H2P2_DBG_FPGA_BASE + 0x1A)     /* LAN Status line */
-#define H2P2_DBG_FPGA_LAN_RESET         (H2P2_DBG_FPGA_BASE + 0x1C)     /* LAN Reset line */
-
-/* NOTE:  most boards don't have a static mapping for the FPGA ... */
-struct h2p2_dbg_fpga {
-        /* offset 0x00 */
-        u16             smc91x[8];
-        /* offset 0x10 */
-        u16             fpga_rev;
-        u16             board_rev;
-        u16             gpio_outputs;
-        u16             leds;
-        /* offset 0x18 */
-        u16             misc_inputs;
-        u16             lan_status;
-        u16             lan_reset;
-        u16             reserved0;
-        /* offset 0x20 */
-        u16             ps2_data;
-        u16             ps2_ctrl;
-        /* plus also 4 rs232 ports ... */
-};
-
-/* LEDs definition on debug board (16 LEDs, all physically green) */
-#define H2P2_DBG_FPGA_LED_GREEN         (1 << 15)
-#define H2P2_DBG_FPGA_LED_AMBER         (1 << 14)
-#define H2P2_DBG_FPGA_LED_RED           (1 << 13)
-#define H2P2_DBG_FPGA_LED_BLUE          (1 << 12)
-/*  cpu0 load-meter LEDs */
-#define H2P2_DBG_FPGA_LOAD_METER        (1 << 0)        // A bit of fun on our board ...
-#define H2P2_DBG_FPGA_LOAD_METER_SIZE   11
-#define H2P2_DBG_FPGA_LOAD_METER_MASK   ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1)
-
-#define H2P2_DBG_FPGA_P2_LED_TIMER              (1 << 0)
-#define H2P2_DBG_FPGA_P2_LED_IDLE               (1 << 1)
-
-/*
- * ---------------------------------------------------------------------------
- *  OMAP-1510 FPGA
- * ---------------------------------------------------------------------------
- */
-#define OMAP1510_FPGA_BASE                      0xE8000000      /* Virtual */
-#define OMAP1510_FPGA_SIZE                      SZ_4K
-#define OMAP1510_FPGA_START                     0x08000000      /* Physical */
-
-/* Revision */
-#define OMAP1510_FPGA_REV_LOW                   (OMAP1510_FPGA_BASE + 0x0)
-#define OMAP1510_FPGA_REV_HIGH                  (OMAP1510_FPGA_BASE + 0x1)
-
-#define OMAP1510_FPGA_LCD_PANEL_CONTROL         (OMAP1510_FPGA_BASE + 0x2)
-#define OMAP1510_FPGA_LED_DIGIT                 (OMAP1510_FPGA_BASE + 0x3)
-#define INNOVATOR_FPGA_HID_SPI                  (OMAP1510_FPGA_BASE + 0x4)
-#define OMAP1510_FPGA_POWER                     (OMAP1510_FPGA_BASE + 0x5)
-
-/* Interrupt status */
-#define OMAP1510_FPGA_ISR_LO                    (OMAP1510_FPGA_BASE + 0x6)
-#define OMAP1510_FPGA_ISR_HI                    (OMAP1510_FPGA_BASE + 0x7)
-
-/* Interrupt mask */
-#define OMAP1510_FPGA_IMR_LO                    (OMAP1510_FPGA_BASE + 0x8)
-#define OMAP1510_FPGA_IMR_HI                    (OMAP1510_FPGA_BASE + 0x9)
-
-/* Reset registers */
-#define OMAP1510_FPGA_HOST_RESET                (OMAP1510_FPGA_BASE + 0xa)
-#define OMAP1510_FPGA_RST                       (OMAP1510_FPGA_BASE + 0xb)
-
-#define OMAP1510_FPGA_AUDIO                     (OMAP1510_FPGA_BASE + 0xc)
-#define OMAP1510_FPGA_DIP                       (OMAP1510_FPGA_BASE + 0xe)
-#define OMAP1510_FPGA_FPGA_IO                   (OMAP1510_FPGA_BASE + 0xf)
-#define OMAP1510_FPGA_UART1                     (OMAP1510_FPGA_BASE + 0x14)
-#define OMAP1510_FPGA_UART2                     (OMAP1510_FPGA_BASE + 0x15)
-#define OMAP1510_FPGA_OMAP1510_STATUS           (OMAP1510_FPGA_BASE + 0x16)
-#define OMAP1510_FPGA_BOARD_REV                 (OMAP1510_FPGA_BASE + 0x18)
-#define OMAP1510P1_PPT_DATA                     (OMAP1510_FPGA_BASE + 0x100)
-#define OMAP1510P1_PPT_STATUS                   (OMAP1510_FPGA_BASE + 0x101)
-#define OMAP1510P1_PPT_CONTROL                  (OMAP1510_FPGA_BASE + 0x102)
-
-#define OMAP1510_FPGA_TOUCHSCREEN               (OMAP1510_FPGA_BASE + 0x204)
-
-#define INNOVATOR_FPGA_INFO                     (OMAP1510_FPGA_BASE + 0x205)
-#define INNOVATOR_FPGA_LCD_BRIGHT_LO            (OMAP1510_FPGA_BASE + 0x206)
-#define INNOVATOR_FPGA_LCD_BRIGHT_HI            (OMAP1510_FPGA_BASE + 0x207)
-#define INNOVATOR_FPGA_LED_GRN_LO               (OMAP1510_FPGA_BASE + 0x208)
-#define INNOVATOR_FPGA_LED_GRN_HI               (OMAP1510_FPGA_BASE + 0x209)
-#define INNOVATOR_FPGA_LED_RED_LO               (OMAP1510_FPGA_BASE + 0x20a)
-#define INNOVATOR_FPGA_LED_RED_HI               (OMAP1510_FPGA_BASE + 0x20b)
-#define INNOVATOR_FPGA_CAM_USB_CONTROL          (OMAP1510_FPGA_BASE + 0x20c)
-#define INNOVATOR_FPGA_EXP_CONTROL              (OMAP1510_FPGA_BASE + 0x20d)
-#define INNOVATOR_FPGA_ISR2                     (OMAP1510_FPGA_BASE + 0x20e)
-#define INNOVATOR_FPGA_IMR2                     (OMAP1510_FPGA_BASE + 0x210)
-
-#define OMAP1510_FPGA_ETHR_START                (OMAP1510_FPGA_START + 0x300)
-
-/*
- * Power up Giga UART driver, turn on HID clock.
- * Turn off BT power, since we're not using it and it
- * draws power.
- */
-#define OMAP1510_FPGA_RESET_VALUE               0x42
-
-#define OMAP1510_FPGA_PCR_IF_PD0                (1 << 7)
-#define OMAP1510_FPGA_PCR_COM2_EN               (1 << 6)
-#define OMAP1510_FPGA_PCR_COM1_EN               (1 << 5)
-#define OMAP1510_FPGA_PCR_EXP_PD0               (1 << 4)
-#define OMAP1510_FPGA_PCR_EXP_PD1               (1 << 3)
-#define OMAP1510_FPGA_PCR_48MHZ_CLK             (1 << 2)
-#define OMAP1510_FPGA_PCR_4MHZ_CLK              (1 << 1)
-#define OMAP1510_FPGA_PCR_RSRVD_BIT0            (1 << 0)
-
-/*
- * Innovator/OMAP1510 FPGA HID register bit definitions
- */
-#define OMAP1510_FPGA_HID_SCLK  (1<<0)  /* output */
-#define OMAP1510_FPGA_HID_MOSI  (1<<1)  /* output */
-#define OMAP1510_FPGA_HID_nSS   (1<<2)  /* output 0/1 chip idle/select */
-#define OMAP1510_FPGA_HID_nHSUS (1<<3)  /* output 0/1 host active/suspended */
-#define OMAP1510_FPGA_HID_MISO  (1<<4)  /* input */
-#define OMAP1510_FPGA_HID_ATN   (1<<5)  /* input  0/1 chip idle/ATN */
-#define OMAP1510_FPGA_HID_rsrvd (1<<6)
-#define OMAP1510_FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */
-
-/* The FPGA IRQ is cascaded through GPIO_13 */
-#define OMAP1510_INT_FPGA               (IH_GPIO_BASE + 13)
-
-/* IRQ Numbers for interrupts muxed through the FPGA */
-#define OMAP1510_INT_FPGA_ATN           (OMAP_FPGA_IRQ_BASE + 0)
-#define OMAP1510_INT_FPGA_ACK           (OMAP_FPGA_IRQ_BASE + 1)
-#define OMAP1510_INT_FPGA2              (OMAP_FPGA_IRQ_BASE + 2)
-#define OMAP1510_INT_FPGA3              (OMAP_FPGA_IRQ_BASE + 3)
-#define OMAP1510_INT_FPGA4              (OMAP_FPGA_IRQ_BASE + 4)
-#define OMAP1510_INT_FPGA5              (OMAP_FPGA_IRQ_BASE + 5)
-#define OMAP1510_INT_FPGA6              (OMAP_FPGA_IRQ_BASE + 6)
-#define OMAP1510_INT_FPGA7              (OMAP_FPGA_IRQ_BASE + 7)
-#define OMAP1510_INT_FPGA8              (OMAP_FPGA_IRQ_BASE + 8)
-#define OMAP1510_INT_FPGA9              (OMAP_FPGA_IRQ_BASE + 9)
-#define OMAP1510_INT_FPGA10             (OMAP_FPGA_IRQ_BASE + 10)
-#define OMAP1510_INT_FPGA11             (OMAP_FPGA_IRQ_BASE + 11)
-#define OMAP1510_INT_FPGA12             (OMAP_FPGA_IRQ_BASE + 12)
-#define OMAP1510_INT_ETHER              (OMAP_FPGA_IRQ_BASE + 13)
-#define OMAP1510_INT_FPGAUART1          (OMAP_FPGA_IRQ_BASE + 14)
-#define OMAP1510_INT_FPGAUART2          (OMAP_FPGA_IRQ_BASE + 15)
-#define OMAP1510_INT_FPGA_TS            (OMAP_FPGA_IRQ_BASE + 16)
-#define OMAP1510_INT_FPGA17             (OMAP_FPGA_IRQ_BASE + 17)
-#define OMAP1510_INT_FPGA_CAM           (OMAP_FPGA_IRQ_BASE + 18)
-#define OMAP1510_INT_FPGA_RTC_A         (OMAP_FPGA_IRQ_BASE + 19)
-#define OMAP1510_INT_FPGA_RTC_B         (OMAP_FPGA_IRQ_BASE + 20)
-#define OMAP1510_INT_FPGA_CD            (OMAP_FPGA_IRQ_BASE + 21)
-#define OMAP1510_INT_FPGA22             (OMAP_FPGA_IRQ_BASE + 22)
-#define OMAP1510_INT_FPGA23             (OMAP_FPGA_IRQ_BASE + 23)
-
-#endif
diff --git a/include/asm-arm/arch-omap/gpio.h b/include/asm-arm/arch-omap/gpio.h
deleted file mode 100644
index 5ee6a49864c3..000000000000
--- a/include/asm-arm/arch-omap/gpio.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/gpio.h
- *
- * OMAP GPIO handling defines and functions
- *
- * Copyright (C) 2003-2005 Nokia Corporation
- *
- * Written by Juha Yrjölä <juha.yrjola@nokia.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-#ifndef __ASM_ARCH_OMAP_GPIO_H
-#define __ASM_ARCH_OMAP_GPIO_H
-
-#include <asm/arch/irqs.h>
-#include <asm/io.h>
-
-#define OMAP_MPUIO_BASE                 (void __iomem *)0xfffb5000
-
-#ifdef CONFIG_ARCH_OMAP730
-#define OMAP_MPUIO_INPUT_LATCH          0x00
-#define OMAP_MPUIO_OUTPUT               0x02
-#define OMAP_MPUIO_IO_CNTL              0x04
-#define OMAP_MPUIO_KBR_LATCH            0x08
-#define OMAP_MPUIO_KBC                  0x0a
-#define OMAP_MPUIO_GPIO_EVENT_MODE      0x0c
-#define OMAP_MPUIO_GPIO_INT_EDGE        0x0e
-#define OMAP_MPUIO_KBD_INT              0x10
-#define OMAP_MPUIO_GPIO_INT             0x12
-#define OMAP_MPUIO_KBD_MASKIT           0x14
-#define OMAP_MPUIO_GPIO_MASKIT          0x16
-#define OMAP_MPUIO_GPIO_DEBOUNCING      0x18
-#define OMAP_MPUIO_LATCH                0x1a
-#else
-#define OMAP_MPUIO_INPUT_LATCH          0x00
-#define OMAP_MPUIO_OUTPUT               0x04
-#define OMAP_MPUIO_IO_CNTL              0x08
-#define OMAP_MPUIO_KBR_LATCH            0x10
-#define OMAP_MPUIO_KBC                  0x14
-#define OMAP_MPUIO_GPIO_EVENT_MODE      0x18
-#define OMAP_MPUIO_GPIO_INT_EDGE        0x1c
-#define OMAP_MPUIO_KBD_INT              0x20
-#define OMAP_MPUIO_GPIO_INT             0x24
-#define OMAP_MPUIO_KBD_MASKIT           0x28
-#define OMAP_MPUIO_GPIO_MASKIT          0x2c
-#define OMAP_MPUIO_GPIO_DEBOUNCING      0x30
-#define OMAP_MPUIO_LATCH                0x34
-#endif
-
-#define OMAP34XX_NR_GPIOS               6
-
-#define OMAP_MPUIO(nr)          (OMAP_MAX_GPIO_LINES + (nr))
-#define OMAP_GPIO_IS_MPUIO(nr)  ((nr) >= OMAP_MAX_GPIO_LINES)
-
-#define OMAP_GPIO_IRQ(nr)       (OMAP_GPIO_IS_MPUIO(nr) ? \
-                                 IH_MPUIO_BASE + ((nr) & 0x0f) : \
-                                 IH_GPIO_BASE + (nr))
-
-extern int omap_gpio_init(void);        /* Call from board init only */
-extern int omap_request_gpio(int gpio);
-extern void omap_free_gpio(int gpio);
-extern void omap_set_gpio_direction(int gpio, int is_input);
-extern void omap_set_gpio_dataout(int gpio, int enable);
-extern int omap_get_gpio_datain(int gpio);
-extern void omap_set_gpio_debounce(int gpio, int enable);
-extern void omap_set_gpio_debounce_time(int gpio, int enable);
-
-/*-------------------------------------------------------------------------*/
-
-/* Wrappers for "new style" GPIO calls, using the new infrastructure
- * which lets us plug in FPGA, I2C, and other implementations.
- * *
- * The original OMAP-specfic calls should eventually be removed.
- */
-
-#include <linux/errno.h>
-#include <asm-generic/gpio.h>
-
-static inline int gpio_get_value(unsigned gpio)
-{
-        return __gpio_get_value(gpio);
-}
-
-static inline void gpio_set_value(unsigned gpio, int value)
-{
-        __gpio_set_value(gpio, value);
-}
-
-static inline int gpio_cansleep(unsigned gpio)
-{
-        return __gpio_cansleep(gpio);
-}
-
-static inline int gpio_to_irq(unsigned gpio)
-{
-        if (gpio < (OMAP_MAX_GPIO_LINES + 16))
-                return OMAP_GPIO_IRQ(gpio);
-        return -EINVAL;
-}
-
-static inline int irq_to_gpio(unsigned irq)
-{
-        if (cpu_class_is_omap1() && (irq < (IH_MPUIO_BASE + 16)))
-                return (irq - IH_MPUIO_BASE) + OMAP_MAX_GPIO_LINES;
-        return irq - IH_GPIO_BASE;
-}
-
-#endif
diff --git a/include/asm-arm/arch-omap/gpioexpander.h b/include/asm-arm/arch-omap/gpioexpander.h
deleted file mode 100644
index 4eed1f80e2fb..000000000000
--- a/include/asm-arm/arch-omap/gpioexpander.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/gpioexpander.h
- *
- *
- * Copyright (C) 2004 Texas Instruments, Inc.
- *
- * This package is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- */
-
-#ifndef __ASM_ARCH_OMAP_GPIOEXPANDER_H
-#define __ASM_ARCH_OMAP_GPIOEXPANDER_H
-
-/* Function Prototypes for GPIO Expander functions */
-
-#ifdef CONFIG_GPIOEXPANDER_OMAP
-int read_gpio_expa(u8 *, int);
-int write_gpio_expa(u8 , int);
-#else
-static inline int read_gpio_expa(u8 *val, int addr)
-{
-        return 0;
-}
-static inline int write_gpio_expa(u8 val, int addr)
-{
-        return 0;
-}
-#endif
-
-#endif /* __ASM_ARCH_OMAP_GPIOEXPANDER_H */
diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h
deleted file mode 100644
index 45fdfccbd5d4..000000000000
--- a/include/asm-arm/arch-omap/hardware.h
+++ /dev/null
@@ -1,355 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/hardware.h
- *
- * Hardware definitions for TI OMAP processors and boards
- *
- * NOTE: Please put device driver specific defines into a separate header
- *       file for each driver.
- *
- * Copyright (C) 2001 RidgeRun, Inc.
- * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
- *
- * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
- *                          and Dirk Behme <dirk.behme@de.bosch.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_OMAP_HARDWARE_H
-#define __ASM_ARCH_OMAP_HARDWARE_H
-
-#include <asm/sizes.h>
-#ifndef __ASSEMBLER__
-#include <asm/types.h>
-#include <asm/arch/cpu.h>
-#endif
-#include <asm/arch/serial.h>
-
-/*
- * ---------------------------------------------------------------------------
- * Common definitions for all OMAP processors
- * NOTE: Put all processor or board specific parts to the special header
- *       files.
- * ---------------------------------------------------------------------------
- */
-
-/*
- * ----------------------------------------------------------------------------
- * Timers
- * ----------------------------------------------------------------------------
- */
-#define OMAP_MPU_TIMER1_BASE    (0xfffec500)
-#define OMAP_MPU_TIMER2_BASE    (0xfffec600)
-#define OMAP_MPU_TIMER3_BASE    (0xfffec700)
-#define MPU_TIMER_FREE          (1 << 6)
-#define MPU_TIMER_CLOCK_ENABLE  (1 << 5)
-#define MPU_TIMER_AR            (1 << 1)
-#define MPU_TIMER_ST            (1 << 0)
-
-/*
- * ----------------------------------------------------------------------------
- * Clocks
- * ----------------------------------------------------------------------------
- */
-#define CLKGEN_REG_BASE         (0xfffece00)
-#define ARM_CKCTL               (CLKGEN_REG_BASE + 0x0)
-#define ARM_IDLECT1             (CLKGEN_REG_BASE + 0x4)
-#define ARM_IDLECT2             (CLKGEN_REG_BASE + 0x8)
-#define ARM_EWUPCT              (CLKGEN_REG_BASE + 0xC)
-#define ARM_RSTCT1              (CLKGEN_REG_BASE + 0x10)
-#define ARM_RSTCT2              (CLKGEN_REG_BASE + 0x14)
-#define ARM_SYSST               (CLKGEN_REG_BASE + 0x18)
-#define ARM_IDLECT3             (CLKGEN_REG_BASE + 0x24)
-
-#define CK_RATEF                1
-#define CK_IDLEF                2
-#define CK_ENABLEF              4
-#define CK_SELECTF              8
-#define SETARM_IDLE_SHIFT
-
-/* DPLL control registers */
-#define DPLL_CTL                (0xfffecf00)
-
-/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
-#define DSP_CONFIG_REG_BASE     (0xe1008000)
-#define DSP_CKCTL               (DSP_CONFIG_REG_BASE + 0x0)
-#define DSP_IDLECT1             (DSP_CONFIG_REG_BASE + 0x4)
-#define DSP_IDLECT2             (DSP_CONFIG_REG_BASE + 0x8)
-#define DSP_RSTCT2              (DSP_CONFIG_REG_BASE + 0x14)
-
-/*
- * ---------------------------------------------------------------------------
- * UPLD
- * ---------------------------------------------------------------------------
- */
-#define ULPD_REG_BASE           (0xfffe0800)
-#define ULPD_IT_STATUS          (ULPD_REG_BASE + 0x14)
-#define ULPD_SETUP_ANALOG_CELL_3        (ULPD_REG_BASE + 0x24)
-#define ULPD_CLOCK_CTRL         (ULPD_REG_BASE + 0x30)
-#       define DIS_USB_PVCI_CLK         (1 << 5)        /* no USB/FAC synch */
-#       define USB_MCLK_EN              (1 << 4)        /* enable W4_USB_CLKO */
-#define ULPD_SOFT_REQ           (ULPD_REG_BASE + 0x34)
-#       define SOFT_UDC_REQ             (1 << 4)
-#       define SOFT_USB_CLK_REQ         (1 << 3)
-#       define SOFT_DPLL_REQ            (1 << 0)
-#define ULPD_DPLL_CTRL          (ULPD_REG_BASE + 0x3c)
-#define ULPD_STATUS_REQ         (ULPD_REG_BASE + 0x40)
-#define ULPD_APLL_CTRL          (ULPD_REG_BASE + 0x4c)
-#define ULPD_POWER_CTRL         (ULPD_REG_BASE + 0x50)
-#define ULPD_SOFT_DISABLE_REQ_REG       (ULPD_REG_BASE + 0x68)
-#       define DIS_MMC2_DPLL_REQ        (1 << 11)
-#       define DIS_MMC1_DPLL_REQ        (1 << 10)
-#       define DIS_UART3_DPLL_REQ       (1 << 9)
-#       define DIS_UART2_DPLL_REQ       (1 << 8)
-#       define DIS_UART1_DPLL_REQ       (1 << 7)
-#       define DIS_USB_HOST_DPLL_REQ    (1 << 6)
-#define ULPD_SDW_CLK_DIV_CTRL_SEL       (ULPD_REG_BASE + 0x74)
-#define ULPD_CAM_CLK_CTRL       (ULPD_REG_BASE + 0x7c)
-
-/*
- * ---------------------------------------------------------------------------
- * Watchdog timer
- * ---------------------------------------------------------------------------
- */
-
-/* Watchdog timer within the OMAP3.2 gigacell */
-#define OMAP_MPU_WATCHDOG_BASE  (0xfffec800)
-#define OMAP_WDT_TIMER          (OMAP_MPU_WATCHDOG_BASE + 0x0)
-#define OMAP_WDT_LOAD_TIM       (OMAP_MPU_WATCHDOG_BASE + 0x4)
-#define OMAP_WDT_READ_TIM       (OMAP_MPU_WATCHDOG_BASE + 0x4)
-#define OMAP_WDT_TIMER_MODE     (OMAP_MPU_WATCHDOG_BASE + 0x8)
-
-/*
- * ---------------------------------------------------------------------------
- * Interrupts
- * ---------------------------------------------------------------------------
- */
-#ifdef CONFIG_ARCH_OMAP1
-
-/*
- * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c
- * or something similar.. -- PFM.
- */
-
-#define OMAP_IH1_BASE           0xfffecb00
-#define OMAP_IH2_BASE           0xfffe0000
-
-#define OMAP_IH1_ITR            (OMAP_IH1_BASE + 0x00)
-#define OMAP_IH1_MIR            (OMAP_IH1_BASE + 0x04)
-#define OMAP_IH1_SIR_IRQ        (OMAP_IH1_BASE + 0x10)
-#define OMAP_IH1_SIR_FIQ        (OMAP_IH1_BASE + 0x14)
-#define OMAP_IH1_CONTROL        (OMAP_IH1_BASE + 0x18)
-#define OMAP_IH1_ILR0           (OMAP_IH1_BASE + 0x1c)
-#define OMAP_IH1_ISR            (OMAP_IH1_BASE + 0x9c)
-
-#define OMAP_IH2_ITR            (OMAP_IH2_BASE + 0x00)
-#define OMAP_IH2_MIR            (OMAP_IH2_BASE + 0x04)
-#define OMAP_IH2_SIR_IRQ        (OMAP_IH2_BASE + 0x10)
-#define OMAP_IH2_SIR_FIQ        (OMAP_IH2_BASE + 0x14)
-#define OMAP_IH2_CONTROL        (OMAP_IH2_BASE + 0x18)
-#define OMAP_IH2_ILR0           (OMAP_IH2_BASE + 0x1c)
-#define OMAP_IH2_ISR            (OMAP_IH2_BASE + 0x9c)
-
-#define IRQ_ITR_REG_OFFSET      0x00
-#define IRQ_MIR_REG_OFFSET      0x04
-#define IRQ_SIR_IRQ_REG_OFFSET  0x10
-#define IRQ_SIR_FIQ_REG_OFFSET  0x14
-#define IRQ_CONTROL_REG_OFFSET  0x18
-#define IRQ_ISR_REG_OFFSET      0x9c
-#define IRQ_ILR0_REG_OFFSET     0x1c
-#define IRQ_GMR_REG_OFFSET      0xa0
-
-#endif
-
-/*
- * ----------------------------------------------------------------------------
- * System control registers
- * ----------------------------------------------------------------------------
- */
-#define MOD_CONF_CTRL_0         0xfffe1080
-#define MOD_CONF_CTRL_1         0xfffe1110
-
-/*
- * ----------------------------------------------------------------------------
- * Pin multiplexing registers
- * ----------------------------------------------------------------------------
- */
-#define FUNC_MUX_CTRL_0         0xfffe1000
-#define FUNC_MUX_CTRL_1         0xfffe1004
-#define FUNC_MUX_CTRL_2         0xfffe1008
-#define COMP_MODE_CTRL_0        0xfffe100c
-#define FUNC_MUX_CTRL_3         0xfffe1010
-#define FUNC_MUX_CTRL_4         0xfffe1014
-#define FUNC_MUX_CTRL_5         0xfffe1018
-#define FUNC_MUX_CTRL_6         0xfffe101C
-#define FUNC_MUX_CTRL_7         0xfffe1020
-#define FUNC_MUX_CTRL_8         0xfffe1024
-#define FUNC_MUX_CTRL_9         0xfffe1028
-#define FUNC_MUX_CTRL_A         0xfffe102C
-#define FUNC_MUX_CTRL_B         0xfffe1030
-#define FUNC_MUX_CTRL_C         0xfffe1034
-#define FUNC_MUX_CTRL_D         0xfffe1038
-#define PULL_DWN_CTRL_0         0xfffe1040
-#define PULL_DWN_CTRL_1         0xfffe1044
-#define PULL_DWN_CTRL_2         0xfffe1048
-#define PULL_DWN_CTRL_3         0xfffe104c
-#define PULL_DWN_CTRL_4         0xfffe10ac
-
-/* OMAP-1610 specific multiplexing registers */
-#define FUNC_MUX_CTRL_E         0xfffe1090
-#define FUNC_MUX_CTRL_F         0xfffe1094
-#define FUNC_MUX_CTRL_10        0xfffe1098
-#define FUNC_MUX_CTRL_11        0xfffe109c
-#define FUNC_MUX_CTRL_12        0xfffe10a0
-#define PU_PD_SEL_0             0xfffe10b4
-#define PU_PD_SEL_1             0xfffe10b8
-#define PU_PD_SEL_2             0xfffe10bc
-#define PU_PD_SEL_3             0xfffe10c0
-#define PU_PD_SEL_4             0xfffe10c4
-
-/* Timer32K for 1610 and 1710*/
-#define OMAP_TIMER32K_BASE      0xFFFBC400
-
-/*
- * ---------------------------------------------------------------------------
- * TIPB bus interface
- * ---------------------------------------------------------------------------
- */
-#define TIPB_PUBLIC_CNTL_BASE           0xfffed300
-#define MPU_PUBLIC_TIPB_CNTL            (TIPB_PUBLIC_CNTL_BASE + 0x8)
-#define TIPB_PRIVATE_CNTL_BASE          0xfffeca00
-#define MPU_PRIVATE_TIPB_CNTL           (TIPB_PRIVATE_CNTL_BASE + 0x8)
-
-/*
- * ----------------------------------------------------------------------------
- * MPUI interface
- * ----------------------------------------------------------------------------
- */
-#define MPUI_BASE                       (0xfffec900)
-#define MPUI_CTRL                       (MPUI_BASE + 0x0)
-#define MPUI_DEBUG_ADDR                 (MPUI_BASE + 0x4)
-#define MPUI_DEBUG_DATA                 (MPUI_BASE + 0x8)
-#define MPUI_DEBUG_FLAG                 (MPUI_BASE + 0xc)
-#define MPUI_STATUS_REG                 (MPUI_BASE + 0x10)
-#define MPUI_DSP_STATUS                 (MPUI_BASE + 0x14)
-#define MPUI_DSP_BOOT_CONFIG            (MPUI_BASE + 0x18)
-#define MPUI_DSP_API_CONFIG             (MPUI_BASE + 0x1c)
-
-/*
- * ----------------------------------------------------------------------------
- * LED Pulse Generator
- * ----------------------------------------------------------------------------
- */
-#define OMAP_LPG1_BASE                  0xfffbd000
-#define OMAP_LPG2_BASE                  0xfffbd800
-#define OMAP_LPG1_LCR                   (OMAP_LPG1_BASE + 0x00)
-#define OMAP_LPG1_PMR                   (OMAP_LPG1_BASE + 0x04)
-#define OMAP_LPG2_LCR                   (OMAP_LPG2_BASE + 0x00)
-#define OMAP_LPG2_PMR                   (OMAP_LPG2_BASE + 0x04)
-
-/*
- * ----------------------------------------------------------------------------
- * Pulse-Width Light
- * ----------------------------------------------------------------------------
- */
-#define OMAP_PWL_BASE                   0xfffb5800
-#define OMAP_PWL_ENABLE                 (OMAP_PWL_BASE + 0x00)
-#define OMAP_PWL_CLK_ENABLE             (OMAP_PWL_BASE + 0x04)
-
-/*
- * ---------------------------------------------------------------------------
- * Processor specific defines
- * ---------------------------------------------------------------------------
- */
-
-#include "omap730.h"
-#include "omap1510.h"
-#include "omap24xx.h"
-#include "omap16xx.h"
-#include "omap34xx.h"
-
-#ifndef __ASSEMBLER__
-
-/*
- * ---------------------------------------------------------------------------
- * Board specific defines
- * ---------------------------------------------------------------------------
- */
-
-#ifdef CONFIG_MACH_OMAP_INNOVATOR
-#include "board-innovator.h"
-#endif
-
-#ifdef CONFIG_MACH_OMAP_H2
-#include "board-h2.h"
-#endif
-
-#ifdef CONFIG_MACH_OMAP_PERSEUS2
-#include "board-perseus2.h"
-#endif
-
-#ifdef CONFIG_MACH_OMAP_FSAMPLE
-#include "board-fsample.h"
-#endif
-
-#ifdef CONFIG_MACH_OMAP_H3
-#include "board-h3.h"
-#endif
-
-#ifdef CONFIG_MACH_OMAP_H4
-#include "board-h4.h"
-#endif
-
-#ifdef CONFIG_MACH_OMAP_2430SDP
-#include "board-2430sdp.h"
-#endif
-
-#ifdef CONFIG_MACH_OMAP_APOLLON
-#include "board-apollon.h"
-#endif
-
-#ifdef CONFIG_MACH_OMAP_OSK
-#include "board-osk.h"
-#endif
-
-#ifdef CONFIG_MACH_VOICEBLUE
-#include "board-voiceblue.h"
-#endif
-
-#ifdef CONFIG_MACH_OMAP_PALMTE
-#include "board-palmte.h"
-#endif
-
-#ifdef CONFIG_MACH_OMAP_PALMZ71
-#include "board-palmz71.h"
-#endif
-
-#ifdef CONFIG_MACH_OMAP_PALMTT
-#include "board-palmtt.h"
-#endif
-
-#ifdef CONFIG_MACH_SX1
-#include "board-sx1.h"
-#endif
-
-#endif /* !__ASSEMBLER__ */
-
-#endif  /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h
deleted file mode 100644
index 449e3568baa6..000000000000
--- a/include/asm-arm/arch-omap/io.h
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/io.h
- *
- * IO definitions for TI OMAP processors and boards
- *
- * Copied from linux/include/asm-arm/arch-sa1100/io.h
- * Copyright (C) 1997-1999 Russell King
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * Modifications:
- *  06-12-1997  RMK     Created.
- *  07-04-1999  RMK     Major cleanup
- */
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#include <asm/arch/hardware.h>
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/*
- * We don't actually have real ISA nor PCI buses, but there is so many
- * drivers out there that might just work if we fake them...
- */
-#define __io(a)                 ((void __iomem *)(PCIO_BASE + (a)))
-#define __mem_pci(a)            (a)
-
-/*
- * ----------------------------------------------------------------------------
- * I/O mapping
- * ----------------------------------------------------------------------------
- */
-
-#define PCIO_BASE       0
-
-#if defined(CONFIG_ARCH_OMAP1)
-
-#define IO_PHYS         0xFFFB0000
-#define IO_OFFSET       0x01000000      /* Virtual IO = 0xfefb0000 */
-#define IO_SIZE         0x40000
-#define IO_VIRT         (IO_PHYS - IO_OFFSET)
-#define IO_ADDRESS(pa)  ((pa) - IO_OFFSET)
-#define OMAP1_IO_ADDRESS(pa)    ((pa) - IO_OFFSET)
-#define io_p2v(pa)      ((pa) - IO_OFFSET)
-#define io_v2p(va)      ((va) + IO_OFFSET)
-
-#elif defined(CONFIG_ARCH_OMAP2)
-
-/* We map both L3 and L4 on OMAP2 */
-#define L3_24XX_PHYS    L3_24XX_BASE    /* 0x68000000 */
-#define L3_24XX_VIRT    0xf8000000
-#define L3_24XX_SIZE    SZ_1M           /* 44kB of 128MB used, want 1MB sect */
-#define L4_24XX_PHYS    L4_24XX_BASE    /* 0x48000000 */
-#define L4_24XX_VIRT    0xd8000000
-#define L4_24XX_SIZE    SZ_1M           /* 1MB of 128MB used, want 1MB sect */
-
-#ifdef CONFIG_ARCH_OMAP2430
-#define L4_WK_243X_PHYS         L4_WK_243X_BASE         /* 0x49000000 */
-#define L4_WK_243X_VIRT         0xd9000000
-#define L4_WK_243X_SIZE         SZ_1M
-#define OMAP243X_GPMC_PHYS      OMAP243X_GPMC_BASE      /* 0x49000000 */
-#define OMAP243X_GPMC_VIRT      0xFE000000
-#define OMAP243X_GPMC_SIZE      SZ_1M
-#define OMAP243X_SDRC_PHYS      OMAP243X_SDRC_BASE
-#define OMAP243X_SDRC_VIRT      0xFD000000
-#define OMAP243X_SDRC_SIZE      SZ_1M
-#define OMAP243X_SMS_PHYS       OMAP243X_SMS_BASE
-#define OMAP243X_SMS_VIRT       0xFC000000
-#define OMAP243X_SMS_SIZE       SZ_1M
-
-#endif
-
-#define IO_OFFSET       0x90000000
-#define IO_ADDRESS(pa)  ((pa) + IO_OFFSET)      /* Works for L3 and L4 */
-#define OMAP2_IO_ADDRESS(pa)    ((pa) + IO_OFFSET)      /* Works for L3 and L4 */
-#define io_p2v(pa)      ((pa) + IO_OFFSET)      /* Works for L3 and L4 */
-#define io_v2p(va)      ((va) - IO_OFFSET)      /* Works for L3 and L4 */
-
-/* DSP */
-#define DSP_MEM_24XX_PHYS       OMAP2420_DSP_MEM_BASE   /* 0x58000000 */
-#define DSP_MEM_24XX_VIRT       0xe0000000
-#define DSP_MEM_24XX_SIZE       0x28000
-#define DSP_IPI_24XX_PHYS       OMAP2420_DSP_IPI_BASE   /* 0x59000000 */
-#define DSP_IPI_24XX_VIRT       0xe1000000
-#define DSP_IPI_24XX_SIZE       SZ_4K
-#define DSP_MMU_24XX_PHYS       OMAP2420_DSP_MMU_BASE   /* 0x5a000000 */
-#define DSP_MMU_24XX_VIRT       0xe2000000
-#define DSP_MMU_24XX_SIZE       SZ_4K
-
-#elif defined(CONFIG_ARCH_OMAP3)
-
-/* We map both L3 and L4 on OMAP3 */
-#define L3_34XX_PHYS            L3_34XX_BASE    /* 0x68000000 */
-#define L3_34XX_VIRT            0xf8000000
-#define L3_34XX_SIZE            SZ_1M   /* 44kB of 128MB used, want 1MB sect */
-
-#define L4_34XX_PHYS            L4_34XX_BASE    /* 0x48000000 */
-#define L4_34XX_VIRT            0xd8000000
-#define L4_34XX_SIZE            SZ_4M   /* 1MB of 128MB used, want 1MB sect */
-
-/*
- * Need to look at the Size 4M for L4.
- * VPOM3430 was not working for Int controller
- */
-
-#define L4_WK_34XX_PHYS         L4_WK_34XX_BASE /* 0x48300000 */
-#define L4_WK_34XX_VIRT         0xd8300000
-#define L4_WK_34XX_SIZE         SZ_1M
-
-#define L4_PER_34XX_PHYS        L4_PER_34XX_BASE /* 0x49000000 */
-#define L4_PER_34XX_VIRT        0xd9000000
-#define L4_PER_34XX_SIZE        SZ_1M
-
-#define L4_EMU_34XX_PHYS        L4_EMU_34XX_BASE /* 0x54000000 */
-#define L4_EMU_34XX_VIRT        0xe4000000
-#define L4_EMU_34XX_SIZE        SZ_64M
-
-#define OMAP34XX_GPMC_PHYS      OMAP34XX_GPMC_BASE /* 0x6E000000 */
-#define OMAP34XX_GPMC_VIRT      0xFE000000
-#define OMAP34XX_GPMC_SIZE      SZ_1M
-
-#define OMAP343X_SMS_PHYS       OMAP343X_SMS_BASE /* 0x6C000000 */
-#define OMAP343X_SMS_VIRT       0xFC000000
-#define OMAP343X_SMS_SIZE       SZ_1M
-
-#define OMAP343X_SDRC_PHYS      OMAP343X_SDRC_BASE /* 0x6D000000 */
-#define OMAP343X_SDRC_VIRT      0xFD000000
-#define OMAP343X_SDRC_SIZE      SZ_1M
-
-
-#define IO_OFFSET               0x90000000
-#define IO_ADDRESS(pa)          ((pa) + IO_OFFSET)/* Works for L3 and L4 */
-#define OMAP2_IO_ADDRESS(pa)    ((pa) + IO_OFFSET)/* Works for L3 and L4 */
-#define io_p2v(pa)              ((pa) + IO_OFFSET)/* Works for L3 and L4 */
-#define io_v2p(va)              ((va) - IO_OFFSET)/* Works for L3 and L4 */
-
-/* DSP */
-#define DSP_MEM_34XX_PHYS       OMAP34XX_DSP_MEM_BASE   /* 0x58000000 */
-#define DSP_MEM_34XX_VIRT       0xe0000000
-#define DSP_MEM_34XX_SIZE       0x28000
-#define DSP_IPI_34XX_PHYS       OMAP34XX_DSP_IPI_BASE   /* 0x59000000 */
-#define DSP_IPI_34XX_VIRT       0xe1000000
-#define DSP_IPI_34XX_SIZE       SZ_4K
-#define DSP_MMU_34XX_PHYS       OMAP34XX_DSP_MMU_BASE   /* 0x5a000000 */
-#define DSP_MMU_34XX_VIRT       0xe2000000
-#define DSP_MMU_34XX_SIZE       SZ_4K
-
-#endif
-
-#ifndef __ASSEMBLER__
-
-/*
- * Functions to access the OMAP IO region
- *
- * NOTE: - Use omap_read/write[bwl] for physical register addresses
- *       - Use __raw_read/write[bwl]() for virtual register addresses
- *       - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses
- *       - DO NOT use hardcoded virtual addresses to allow changing the
- *         IO address space again if needed
- */
-#define omap_readb(a)           (*(volatile unsigned char  *)IO_ADDRESS(a))
-#define omap_readw(a)           (*(volatile unsigned short *)IO_ADDRESS(a))
-#define omap_readl(a)           (*(volatile unsigned int   *)IO_ADDRESS(a))
-
-#define omap_writeb(v,a)        (*(volatile unsigned char  *)IO_ADDRESS(a) = (v))
-#define omap_writew(v,a)        (*(volatile unsigned short *)IO_ADDRESS(a) = (v))
-#define omap_writel(v,a)        (*(volatile unsigned int   *)IO_ADDRESS(a) = (v))
-
-extern void omap1_map_common_io(void);
-extern void omap1_init_common_hw(void);
-
-extern void omap2_map_common_io(void);
-extern void omap2_init_common_hw(void);
-
-#endif
-
-#endif
diff --git a/include/asm-arm/arch-omap/irda.h b/include/asm-arm/arch-omap/irda.h
deleted file mode 100644
index 96bb12fab438..000000000000
--- a/include/asm-arm/arch-omap/irda.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-omap/irda.h
- *
- *  Copyright (C) 2005-2006 Komal Shah <komal_shah802003@yahoo.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef ASMARM_ARCH_IRDA_H
-#define ASMARM_ARCH_IRDA_H
-
-/* board specific transceiver capabilities */
-
-#define IR_SEL          1       /* Selects IrDA */
-#define IR_SIRMODE      2
-#define IR_FIRMODE      4
-#define IR_MIRMODE      8
-
-struct omap_irda_config {
-        int transceiver_cap;
-        int (*transceiver_mode)(struct device *dev, int mode);
-        int (*select_irda)(struct device *dev, int state);
-        /* Very specific to the needs of some platforms (h3,h4)
-         * having calls which can sleep in irda_set_speed.
-         */
-        struct delayed_work gpio_expa;
-        int rx_channel;
-        int tx_channel;
-        unsigned long dest_start;
-        unsigned long src_start;
-        int tx_trigger;
-        int rx_trigger;
-        int mode;
-};
-
-#endif
diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h
deleted file mode 100644
index afbf1e846468..000000000000
--- a/include/asm-arm/arch-omap/irqs.h
+++ /dev/null
@@ -1,332 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-omap/irqs.h
- *
- *  Copyright (C) Greg Lonnon 2001
- *  Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
- *       are different.
- */
-
-#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
-#define __ASM_ARCH_OMAP15XX_IRQS_H
-
-/*
- * IRQ numbers for interrupt handler 1
- *
- * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
- *
- */
-#define INT_CAMERA              1
-#define INT_FIQ                 3
-#define INT_RTDX                6
-#define INT_DSP_MMU_ABORT       7
-#define INT_HOST                8
-#define INT_ABORT               9
-#define INT_BRIDGE_PRIV         13
-#define INT_GPIO_BANK1          14
-#define INT_UART3               15
-#define INT_TIMER3              16
-#define INT_DMA_CH0_6           19
-#define INT_DMA_CH1_7           20
-#define INT_DMA_CH2_8           21
-#define INT_DMA_CH3             22
-#define INT_DMA_CH4             23
-#define INT_DMA_CH5             24
-#define INT_DMA_LCD             25
-#define INT_TIMER1              26
-#define INT_WD_TIMER            27
-#define INT_BRIDGE_PUB          28
-#define INT_TIMER2              30
-#define INT_LCD_CTRL            31
-
-/*
- * OMAP-1510 specific IRQ numbers for interrupt handler 1
- */
-#define INT_1510_IH2_IRQ        0
-#define INT_1510_RES2           2
-#define INT_1510_SPI_TX         4
-#define INT_1510_SPI_RX         5
-#define INT_1510_DSP_MAILBOX1   10
-#define INT_1510_DSP_MAILBOX2   11
-#define INT_1510_RES12          12
-#define INT_1510_LB_MMU         17
-#define INT_1510_RES18          18
-#define INT_1510_LOCAL_BUS      29
-
-/*
- * OMAP-1610 specific IRQ numbers for interrupt handler 1
- */
-#define INT_1610_IH2_IRQ        0
-#define INT_1610_IH2_FIQ        2
-#define INT_1610_McBSP2_TX      4
-#define INT_1610_McBSP2_RX      5
-#define INT_1610_DSP_MAILBOX1   10
-#define INT_1610_DSP_MAILBOX2   11
-#define INT_1610_LCD_LINE       12
-#define INT_1610_GPTIMER1       17
-#define INT_1610_GPTIMER2       18
-#define INT_1610_SSR_FIFO_0     29
-
-/*
- * OMAP-730 specific IRQ numbers for interrupt handler 1
- */
-#define INT_730_IH2_FIQ         0
-#define INT_730_IH2_IRQ         1
-#define INT_730_USB_NON_ISO     2
-#define INT_730_USB_ISO         3
-#define INT_730_ICR             4
-#define INT_730_EAC             5
-#define INT_730_GPIO_BANK1      6
-#define INT_730_GPIO_BANK2      7
-#define INT_730_GPIO_BANK3      8
-#define INT_730_McBSP2TX        10
-#define INT_730_McBSP2RX        11
-#define INT_730_McBSP2RX_OVF    12
-#define INT_730_LCD_LINE        14
-#define INT_730_GSM_PROTECT     15
-#define INT_730_TIMER3          16
-#define INT_730_GPIO_BANK5      17
-#define INT_730_GPIO_BANK6      18
-#define INT_730_SPGIO_WR        29
-
-/*
- * IRQ numbers for interrupt handler 2
- *
- * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
- */
-#define IH2_BASE                32
-
-#define INT_KEYBOARD            (1 + IH2_BASE)
-#define INT_uWireTX             (2 + IH2_BASE)
-#define INT_uWireRX             (3 + IH2_BASE)
-#define INT_I2C                 (4 + IH2_BASE)
-#define INT_MPUIO               (5 + IH2_BASE)
-#define INT_USB_HHC_1           (6 + IH2_BASE)
-#define INT_McBSP3TX            (10 + IH2_BASE)
-#define INT_McBSP3RX            (11 + IH2_BASE)
-#define INT_McBSP1TX            (12 + IH2_BASE)
-#define INT_McBSP1RX            (13 + IH2_BASE)
-#define INT_UART1               (14 + IH2_BASE)
-#define INT_UART2               (15 + IH2_BASE)
-#define INT_BT_MCSI1TX          (16 + IH2_BASE)
-#define INT_BT_MCSI1RX          (17 + IH2_BASE)
-#define INT_USB_W2FC            (20 + IH2_BASE)
-#define INT_1WIRE               (21 + IH2_BASE)
-#define INT_OS_TIMER            (22 + IH2_BASE)
-#define INT_MMC                 (23 + IH2_BASE)
-#define INT_GAUGE_32K           (24 + IH2_BASE)
-#define INT_RTC_TIMER           (25 + IH2_BASE)
-#define INT_RTC_ALARM           (26 + IH2_BASE)
-#define INT_MEM_STICK           (27 + IH2_BASE)
-
-/*
- * OMAP-1510 specific IRQ numbers for interrupt handler 2
- */
-#define INT_1510_DSP_MMU        (28 + IH2_BASE)
-#define INT_1510_COM_SPI_RO     (31 + IH2_BASE)
-
-/*
- * OMAP-1610 specific IRQ numbers for interrupt handler 2
- */
-#define INT_1610_FAC            (0 + IH2_BASE)
-#define INT_1610_USB_HHC_2      (7 + IH2_BASE)
-#define INT_1610_USB_OTG        (8 + IH2_BASE)
-#define INT_1610_SoSSI          (9 + IH2_BASE)
-#define INT_1610_SoSSI_MATCH    (19 + IH2_BASE)
-#define INT_1610_DSP_MMU        (28 + IH2_BASE)
-#define INT_1610_McBSP2RX_OF    (31 + IH2_BASE)
-#define INT_1610_STI            (32 + IH2_BASE)
-#define INT_1610_STI_WAKEUP     (33 + IH2_BASE)
-#define INT_1610_GPTIMER3       (34 + IH2_BASE)
-#define INT_1610_GPTIMER4       (35 + IH2_BASE)
-#define INT_1610_GPTIMER5       (36 + IH2_BASE)
-#define INT_1610_GPTIMER6       (37 + IH2_BASE)
-#define INT_1610_GPTIMER7       (38 + IH2_BASE)
-#define INT_1610_GPTIMER8       (39 + IH2_BASE)
-#define INT_1610_GPIO_BANK2     (40 + IH2_BASE)
-#define INT_1610_GPIO_BANK3     (41 + IH2_BASE)
-#define INT_1610_MMC2           (42 + IH2_BASE)
-#define INT_1610_CF             (43 + IH2_BASE)
-#define INT_1610_WAKE_UP_REQ    (46 + IH2_BASE)
-#define INT_1610_GPIO_BANK4     (48 + IH2_BASE)
-#define INT_1610_SPI            (49 + IH2_BASE)
-#define INT_1610_DMA_CH6        (53 + IH2_BASE)
-#define INT_1610_DMA_CH7        (54 + IH2_BASE)
-#define INT_1610_DMA_CH8        (55 + IH2_BASE)
-#define INT_1610_DMA_CH9        (56 + IH2_BASE)
-#define INT_1610_DMA_CH10       (57 + IH2_BASE)
-#define INT_1610_DMA_CH11       (58 + IH2_BASE)
-#define INT_1610_DMA_CH12       (59 + IH2_BASE)
-#define INT_1610_DMA_CH13       (60 + IH2_BASE)
-#define INT_1610_DMA_CH14       (61 + IH2_BASE)
-#define INT_1610_DMA_CH15       (62 + IH2_BASE)
-#define INT_1610_NAND           (63 + IH2_BASE)
-
-/*
- * OMAP-730 specific IRQ numbers for interrupt handler 2
- */
-#define INT_730_HW_ERRORS       (0 + IH2_BASE)
-#define INT_730_NFIQ_PWR_FAIL   (1 + IH2_BASE)
-#define INT_730_CFCD            (2 + IH2_BASE)
-#define INT_730_CFIREQ          (3 + IH2_BASE)
-#define INT_730_I2C             (4 + IH2_BASE)
-#define INT_730_PCC             (5 + IH2_BASE)
-#define INT_730_MPU_EXT_NIRQ    (6 + IH2_BASE)
-#define INT_730_SPI_100K_1      (7 + IH2_BASE)
-#define INT_730_SYREN_SPI       (8 + IH2_BASE)
-#define INT_730_VLYNQ           (9 + IH2_BASE)
-#define INT_730_GPIO_BANK4      (10 + IH2_BASE)
-#define INT_730_McBSP1TX        (11 + IH2_BASE)
-#define INT_730_McBSP1RX        (12 + IH2_BASE)
-#define INT_730_McBSP1RX_OF     (13 + IH2_BASE)
-#define INT_730_UART_MODEM_IRDA_2 (14 + IH2_BASE)
-#define INT_730_UART_MODEM_1    (15 + IH2_BASE)
-#define INT_730_MCSI            (16 + IH2_BASE)
-#define INT_730_uWireTX         (17 + IH2_BASE)
-#define INT_730_uWireRX         (18 + IH2_BASE)
-#define INT_730_SMC_CD          (19 + IH2_BASE)
-#define INT_730_SMC_IREQ        (20 + IH2_BASE)
-#define INT_730_HDQ_1WIRE       (21 + IH2_BASE)
-#define INT_730_TIMER32K        (22 + IH2_BASE)
-#define INT_730_MMC_SDIO        (23 + IH2_BASE)
-#define INT_730_UPLD            (24 + IH2_BASE)
-#define INT_730_USB_HHC_1       (27 + IH2_BASE)
-#define INT_730_USB_HHC_2       (28 + IH2_BASE)
-#define INT_730_USB_GENI        (29 + IH2_BASE)
-#define INT_730_USB_OTG         (30 + IH2_BASE)
-#define INT_730_CAMERA_IF       (31 + IH2_BASE)
-#define INT_730_RNG             (32 + IH2_BASE)
-#define INT_730_DUAL_MODE_TIMER (33 + IH2_BASE)
-#define INT_730_DBB_RF_EN       (34 + IH2_BASE)
-#define INT_730_MPUIO_KEYPAD    (35 + IH2_BASE)
-#define INT_730_SHA1_MD5        (36 + IH2_BASE)
-#define INT_730_SPI_100K_2      (37 + IH2_BASE)
-#define INT_730_RNG_IDLE        (38 + IH2_BASE)
-#define INT_730_MPUIO           (39 + IH2_BASE)
-#define INT_730_LLPC_LCD_CTRL_CAN_BE_OFF        (40 + IH2_BASE)
-#define INT_730_LLPC_OE_FALLING (41 + IH2_BASE)
-#define INT_730_LLPC_OE_RISING  (42 + IH2_BASE)
-#define INT_730_LLPC_VSYNC      (43 + IH2_BASE)
-#define INT_730_WAKE_UP_REQ     (46 + IH2_BASE)
-#define INT_730_DMA_CH6         (53 + IH2_BASE)
-#define INT_730_DMA_CH7         (54 + IH2_BASE)
-#define INT_730_DMA_CH8         (55 + IH2_BASE)
-#define INT_730_DMA_CH9         (56 + IH2_BASE)
-#define INT_730_DMA_CH10        (57 + IH2_BASE)
-#define INT_730_DMA_CH11        (58 + IH2_BASE)
-#define INT_730_DMA_CH12        (59 + IH2_BASE)
-#define INT_730_DMA_CH13        (60 + IH2_BASE)
-#define INT_730_DMA_CH14        (61 + IH2_BASE)
-#define INT_730_DMA_CH15        (62 + IH2_BASE)
-#define INT_730_NAND            (63 + IH2_BASE)
-
-#define INT_24XX_SYS_NIRQ       7
-#define INT_24XX_SDMA_IRQ0      12
-#define INT_24XX_SDMA_IRQ1      13
-#define INT_24XX_SDMA_IRQ2      14
-#define INT_24XX_SDMA_IRQ3      15
-#define INT_24XX_CAM_IRQ        24
-#define INT_24XX_DSS_IRQ        25
-#define INT_24XX_MAIL_U0_MPU    26
-#define INT_24XX_DSP_UMA        27
-#define INT_24XX_DSP_MMU        28
-#define INT_24XX_GPIO_BANK1     29
-#define INT_24XX_GPIO_BANK2     30
-#define INT_24XX_GPIO_BANK3     31
-#define INT_24XX_GPIO_BANK4     32
-#define INT_24XX_GPIO_BANK5     33
-#define INT_24XX_MAIL_U3_MPU    34
-#define INT_24XX_GPTIMER1       37
-#define INT_24XX_GPTIMER2       38
-#define INT_24XX_GPTIMER3       39
-#define INT_24XX_GPTIMER4       40
-#define INT_24XX_GPTIMER5       41
-#define INT_24XX_GPTIMER6       42
-#define INT_24XX_GPTIMER7       43
-#define INT_24XX_GPTIMER8       44
-#define INT_24XX_GPTIMER9       45
-#define INT_24XX_GPTIMER10      46
-#define INT_24XX_GPTIMER11      47
-#define INT_24XX_GPTIMER12      48
-#define INT_24XX_I2C1_IRQ       56
-#define INT_24XX_I2C2_IRQ       57
-#define INT_24XX_MCBSP1_IRQ_TX  59
-#define INT_24XX_MCBSP1_IRQ_RX  60
-#define INT_24XX_MCBSP2_IRQ_TX  62
-#define INT_24XX_MCBSP2_IRQ_RX  63
-#define INT_24XX_UART1_IRQ      72
-#define INT_24XX_UART2_IRQ      73
-#define INT_24XX_UART3_IRQ      74
-#define INT_24XX_USB_IRQ_GEN    75
-#define INT_24XX_USB_IRQ_NISO   76
-#define INT_24XX_USB_IRQ_ISO    77
-#define INT_24XX_USB_IRQ_HGEN   78
-#define INT_24XX_USB_IRQ_HSOF   79
-#define INT_24XX_USB_IRQ_OTG    80
-#define INT_24XX_MMC_IRQ        83
-
-/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and
- * 16 MPUIO lines */
-#define OMAP_MAX_GPIO_LINES     192
-#define IH_GPIO_BASE            (128 + IH2_BASE)
-#define IH_MPUIO_BASE           (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
-#define OMAP_IRQ_END            (IH_MPUIO_BASE + 16)
-
-/* External FPGA handles interrupts on Innovator boards */
-#define OMAP_FPGA_IRQ_BASE      (OMAP_IRQ_END)
-#ifdef  CONFIG_MACH_OMAP_INNOVATOR
-#define OMAP_FPGA_NR_IRQS       24
-#else
-#define OMAP_FPGA_NR_IRQS       0
-#endif
-#define OMAP_FPGA_IRQ_END       (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
-
-/* External TWL4030 can handle interrupts on 2430 and 34xx boards */
-#define TWL4030_IRQ_BASE        (OMAP_FPGA_IRQ_END)
-#ifdef  CONFIG_TWL4030_CORE
-#define TWL4030_BASE_NR_IRQS    8
-#define TWL4030_PWR_NR_IRQS     8
-#else
-#define TWL4030_BASE_NR_IRQS    0
-#define TWL4030_PWR_NR_IRQS     0
-#endif
-#define TWL4030_IRQ_END         (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
-#define TWL4030_PWR_IRQ_BASE    TWL4030_IRQ_END
-#define TWL4030_PWR_IRQ_END     (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)
-
-/* External TWL4030 gpio interrupts are optional */
-#define TWL4030_GPIO_IRQ_BASE   TWL4030_PWR_IRQ_END
-#ifdef  CONFIG_TWL4030_GPIO
-#define TWL4030_GPIO_NR_IRQS    18
-#else
-#define TWL4030_GPIO_NR_IRQS    0
-#endif
-#define TWL4030_GPIO_IRQ_END    (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
-
-/* Total number of interrupts depends on the enabled blocks above */
-#define NR_IRQS                 TWL4030_GPIO_IRQ_END
-
-#define OMAP_IRQ_BIT(irq)       (1 << ((irq) % 32))
-
-#ifndef __ASSEMBLY__
-extern void omap_init_irq(void);
-#endif
-
-#include <asm/arch/hardware.h>
-
-#endif
diff --git a/include/asm-arm/arch-omap/keypad.h b/include/asm-arm/arch-omap/keypad.h
deleted file mode 100644
index b7f83075436e..000000000000
--- a/include/asm-arm/arch-omap/keypad.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-omap/keypad.h
- *
- *  Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef ASMARM_ARCH_KEYPAD_H
-#define ASMARM_ARCH_KEYPAD_H
-
-struct omap_kp_platform_data {
-        int rows;
-        int cols;
-        int *keymap;
-        unsigned int keymapsize;
-        unsigned int rep:1;
-        unsigned long delay;
-        unsigned int dbounce:1;
-        /* specific to OMAP242x*/
-        unsigned int *row_gpios;
-        unsigned int *col_gpios;
-};
-
-/* Group (0..3) -- when multiple keys are pressed, only the
- * keys pressed in the same group are considered as pressed. This is
- * in order to workaround certain crappy HW designs that produce ghost
- * keypresses. */
-#define GROUP_0         (0 << 16)
-#define GROUP_1         (1 << 16)
-#define GROUP_2         (2 << 16)
-#define GROUP_3         (3 << 16)
-#define GROUP_MASK      GROUP_3
-
-#define KEY(col, row, val) (((col) << 28) | ((row) << 24) | (val))
-
-#endif
-
diff --git a/include/asm-arm/arch-omap/led.h b/include/asm-arm/arch-omap/led.h
deleted file mode 100644
index f3acae28e2da..000000000000
--- a/include/asm-arm/arch-omap/led.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-omap/led.h
- *
- *  Copyright (C) 2006 Samsung Electronics
- *  Kyungmin Park <kyungmin.park@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef ASMARM_ARCH_LED_H
-#define ASMARM_ARCH_LED_H
-
-struct omap_led_config {
-        struct led_classdev     cdev;
-        s16                     gpio;
-};
-
-struct omap_led_platform_data {
-        s16                     nr_leds;
-        struct omap_led_config  *leds;
-};
-
-#endif
diff --git a/include/asm-arm/arch-omap/mcbsp.h b/include/asm-arm/arch-omap/mcbsp.h
deleted file mode 100644
index 3da459a282b9..000000000000
--- a/include/asm-arm/arch-omap/mcbsp.h
+++ /dev/null
@@ -1,380 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/mcbsp.h
- *
- * Defines for Multi-Channel Buffered Serial Port
- *
- * Copyright (C) 2002 RidgeRun, Inc.
- * Author: Steve Johnson
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-#ifndef __ASM_ARCH_OMAP_MCBSP_H
-#define __ASM_ARCH_OMAP_MCBSP_H
-
-#include <linux/completion.h>
-#include <linux/spinlock.h>
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/clock.h>
-
-#define OMAP730_MCBSP1_BASE     0xfffb1000
-#define OMAP730_MCBSP2_BASE     0xfffb1800
-
-#define OMAP1510_MCBSP1_BASE    0xe1011800
-#define OMAP1510_MCBSP2_BASE    0xfffb1000
-#define OMAP1510_MCBSP3_BASE    0xe1017000
-
-#define OMAP1610_MCBSP1_BASE    0xe1011800
-#define OMAP1610_MCBSP2_BASE    0xfffb1000
-#define OMAP1610_MCBSP3_BASE    0xe1017000
-
-#define OMAP24XX_MCBSP1_BASE    0x48074000
-#define OMAP24XX_MCBSP2_BASE    0x48076000
-
-#define OMAP34XX_MCBSP1_BASE    0x48074000
-#define OMAP34XX_MCBSP2_BASE    0x49022000
-
-#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)
-
-#define OMAP_MCBSP_REG_DRR2     0x00
-#define OMAP_MCBSP_REG_DRR1     0x02
-#define OMAP_MCBSP_REG_DXR2     0x04
-#define OMAP_MCBSP_REG_DXR1     0x06
-#define OMAP_MCBSP_REG_SPCR2    0x08
-#define OMAP_MCBSP_REG_SPCR1    0x0a
-#define OMAP_MCBSP_REG_RCR2     0x0c
-#define OMAP_MCBSP_REG_RCR1     0x0e
-#define OMAP_MCBSP_REG_XCR2     0x10
-#define OMAP_MCBSP_REG_XCR1     0x12
-#define OMAP_MCBSP_REG_SRGR2    0x14
-#define OMAP_MCBSP_REG_SRGR1    0x16
-#define OMAP_MCBSP_REG_MCR2     0x18
-#define OMAP_MCBSP_REG_MCR1     0x1a
-#define OMAP_MCBSP_REG_RCERA    0x1c
-#define OMAP_MCBSP_REG_RCERB    0x1e
-#define OMAP_MCBSP_REG_XCERA    0x20
-#define OMAP_MCBSP_REG_XCERB    0x22
-#define OMAP_MCBSP_REG_PCR0     0x24
-#define OMAP_MCBSP_REG_RCERC    0x26
-#define OMAP_MCBSP_REG_RCERD    0x28
-#define OMAP_MCBSP_REG_XCERC    0x2A
-#define OMAP_MCBSP_REG_XCERD    0x2C
-#define OMAP_MCBSP_REG_RCERE    0x2E
-#define OMAP_MCBSP_REG_RCERF    0x30
-#define OMAP_MCBSP_REG_XCERE    0x32
-#define OMAP_MCBSP_REG_XCERF    0x34
-#define OMAP_MCBSP_REG_RCERG    0x36
-#define OMAP_MCBSP_REG_RCERH    0x38
-#define OMAP_MCBSP_REG_XCERG    0x3A
-#define OMAP_MCBSP_REG_XCERH    0x3C
-
-#define OMAP_MAX_MCBSP_COUNT    3
-#define MAX_MCBSP_CLOCKS        3
-
-#define AUDIO_MCBSP_DATAWRITE   (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
-#define AUDIO_MCBSP_DATAREAD    (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
-
-#define AUDIO_MCBSP             OMAP_MCBSP1
-#define AUDIO_DMA_TX            OMAP_DMA_MCBSP1_TX
-#define AUDIO_DMA_RX            OMAP_DMA_MCBSP1_RX
-
-#elif defined(CONFIG_ARCH_OMAP24XX)
-
-#define OMAP_MCBSP_REG_DRR2     0x00
-#define OMAP_MCBSP_REG_DRR1     0x04
-#define OMAP_MCBSP_REG_DXR2     0x08
-#define OMAP_MCBSP_REG_DXR1     0x0C
-#define OMAP_MCBSP_REG_SPCR2    0x10
-#define OMAP_MCBSP_REG_SPCR1    0x14
-#define OMAP_MCBSP_REG_RCR2     0x18
-#define OMAP_MCBSP_REG_RCR1     0x1C
-#define OMAP_MCBSP_REG_XCR2     0x20
-#define OMAP_MCBSP_REG_XCR1     0x24
-#define OMAP_MCBSP_REG_SRGR2    0x28
-#define OMAP_MCBSP_REG_SRGR1    0x2C
-#define OMAP_MCBSP_REG_MCR2     0x30
-#define OMAP_MCBSP_REG_MCR1     0x34
-#define OMAP_MCBSP_REG_RCERA    0x38
-#define OMAP_MCBSP_REG_RCERB    0x3C
-#define OMAP_MCBSP_REG_XCERA    0x40
-#define OMAP_MCBSP_REG_XCERB    0x44
-#define OMAP_MCBSP_REG_PCR0     0x48
-#define OMAP_MCBSP_REG_RCERC    0x4C
-#define OMAP_MCBSP_REG_RCERD    0x50
-#define OMAP_MCBSP_REG_XCERC    0x54
-#define OMAP_MCBSP_REG_XCERD    0x58
-#define OMAP_MCBSP_REG_RCERE    0x5C
-#define OMAP_MCBSP_REG_RCERF    0x60
-#define OMAP_MCBSP_REG_XCERE    0x64
-#define OMAP_MCBSP_REG_XCERF    0x68
-#define OMAP_MCBSP_REG_RCERG    0x6C
-#define OMAP_MCBSP_REG_RCERH    0x70
-#define OMAP_MCBSP_REG_XCERG    0x74
-#define OMAP_MCBSP_REG_XCERH    0x78
-
-#define OMAP_MAX_MCBSP_COUNT    2
-#define MAX_MCBSP_CLOCKS        2
-
-#define AUDIO_MCBSP_DATAWRITE   (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
-#define AUDIO_MCBSP_DATAREAD    (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
-
-#define AUDIO_MCBSP             OMAP_MCBSP2
-#define AUDIO_DMA_TX            OMAP24XX_DMA_MCBSP2_TX
-#define AUDIO_DMA_RX            OMAP24XX_DMA_MCBSP2_RX
-
-#endif
-
-#define OMAP_MCBSP_READ(base, reg)              __raw_readw((base) + OMAP_MCBSP_REG_##reg)
-#define OMAP_MCBSP_WRITE(base, reg, val)        __raw_writew((val), (base) + OMAP_MCBSP_REG_##reg)
-
-
-/************************** McBSP SPCR1 bit definitions ***********************/
-#define RRST                    0x0001
-#define RRDY                    0x0002
-#define RFULL                   0x0004
-#define RSYNC_ERR               0x0008
-#define RINTM(value)            ((value)<<4)    /* bits 4:5 */
-#define ABIS                    0x0040
-#define DXENA                   0x0080
-#define CLKSTP(value)           ((value)<<11)   /* bits 11:12 */
-#define RJUST(value)            ((value)<<13)   /* bits 13:14 */
-#define DLB                     0x8000
-
-/************************** McBSP SPCR2 bit definitions ***********************/
-#define XRST            0x0001
-#define XRDY            0x0002
-#define XEMPTY          0x0004
-#define XSYNC_ERR       0x0008
-#define XINTM(value)    ((value)<<4)            /* bits 4:5 */
-#define GRST            0x0040
-#define FRST            0x0080
-#define SOFT            0x0100
-#define FREE            0x0200
-
-/************************** McBSP PCR bit definitions *************************/
-#define CLKRP           0x0001
-#define CLKXP           0x0002
-#define FSRP            0x0004
-#define FSXP            0x0008
-#define DR_STAT         0x0010
-#define DX_STAT         0x0020
-#define CLKS_STAT       0x0040
-#define SCLKME          0x0080
-#define CLKRM           0x0100
-#define CLKXM           0x0200
-#define FSRM            0x0400
-#define FSXM            0x0800
-#define RIOEN           0x1000
-#define XIOEN           0x2000
-#define IDLE_EN         0x4000
-
-/************************** McBSP RCR1 bit definitions ************************/
-#define RWDLEN1(value)          ((value)<<5)    /* Bits 5:7 */
-#define RFRLEN1(value)          ((value)<<8)    /* Bits 8:14 */
-
-/************************** McBSP XCR1 bit definitions ************************/
-#define XWDLEN1(value)          ((value)<<5)    /* Bits 5:7 */
-#define XFRLEN1(value)          ((value)<<8)    /* Bits 8:14 */
-
-/*************************** McBSP RCR2 bit definitions ***********************/
-#define RDATDLY(value)          (value)         /* Bits 0:1 */
-#define RFIG                    0x0004
-#define RCOMPAND(value)         ((value)<<3)    /* Bits 3:4 */
-#define RWDLEN2(value)          ((value)<<5)    /* Bits 5:7 */
-#define RFRLEN2(value)          ((value)<<8)    /* Bits 8:14 */
-#define RPHASE                  0x8000
-
-/*************************** McBSP XCR2 bit definitions ***********************/
-#define XDATDLY(value)          (value)         /* Bits 0:1 */
-#define XFIG                    0x0004
-#define XCOMPAND(value)         ((value)<<3)    /* Bits 3:4 */
-#define XWDLEN2(value)          ((value)<<5)    /* Bits 5:7 */
-#define XFRLEN2(value)          ((value)<<8)    /* Bits 8:14 */
-#define XPHASE                  0x8000
-
-/************************* McBSP SRGR1 bit definitions ************************/
-#define CLKGDV(value)           (value)         /* Bits 0:7 */
-#define FWID(value)             ((value)<<8)    /* Bits 8:15 */
-
-/************************* McBSP SRGR2 bit definitions ************************/
-#define FPER(value)             (value)         /* Bits 0:11 */
-#define FSGM                    0x1000
-#define CLKSM                   0x2000
-#define CLKSP                   0x4000
-#define GSYNC                   0x8000
-
-/************************* McBSP MCR1 bit definitions *************************/
-#define RMCM                    0x0001
-#define RCBLK(value)            ((value)<<2)    /* Bits 2:4 */
-#define RPABLK(value)           ((value)<<5)    /* Bits 5:6 */
-#define RPBBLK(value)           ((value)<<7)    /* Bits 7:8 */
-
-/************************* McBSP MCR2 bit definitions *************************/
-#define XMCM(value)             (value)         /* Bits 0:1 */
-#define XCBLK(value)            ((value)<<2)    /* Bits 2:4 */
-#define XPABLK(value)           ((value)<<5)    /* Bits 5:6 */
-#define XPBBLK(value)           ((value)<<7)    /* Bits 7:8 */
-
-
-/* we don't do multichannel for now */
-struct omap_mcbsp_reg_cfg {
-        u16 spcr2;
-        u16 spcr1;
-        u16 rcr2;
-        u16 rcr1;
-        u16 xcr2;
-        u16 xcr1;
-        u16 srgr2;
-        u16 srgr1;
-        u16 mcr2;
-        u16 mcr1;
-        u16 pcr0;
-        u16 rcerc;
-        u16 rcerd;
-        u16 xcerc;
-        u16 xcerd;
-        u16 rcere;
-        u16 rcerf;
-        u16 xcere;
-        u16 xcerf;
-        u16 rcerg;
-        u16 rcerh;
-        u16 xcerg;
-        u16 xcerh;
-};
-
-typedef enum {
-        OMAP_MCBSP1 = 0,
-        OMAP_MCBSP2,
-        OMAP_MCBSP3,
-} omap_mcbsp_id;
-
-typedef int __bitwise omap_mcbsp_io_type_t;
-#define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
-#define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)
-
-typedef enum {
-        OMAP_MCBSP_WORD_8 = 0,
-        OMAP_MCBSP_WORD_12,
-        OMAP_MCBSP_WORD_16,
-        OMAP_MCBSP_WORD_20,
-        OMAP_MCBSP_WORD_24,
-        OMAP_MCBSP_WORD_32,
-} omap_mcbsp_word_length;
-
-typedef enum {
-        OMAP_MCBSP_CLK_RISING = 0,
-        OMAP_MCBSP_CLK_FALLING,
-} omap_mcbsp_clk_polarity;
-
-typedef enum {
-        OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
-        OMAP_MCBSP_FS_ACTIVE_LOW,
-} omap_mcbsp_fs_polarity;
-
-typedef enum {
-        OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
-        OMAP_MCBSP_CLK_STP_MODE_DELAY,
-} omap_mcbsp_clk_stp_mode;
-
-
-/******* SPI specific mode **********/
-typedef enum {
-        OMAP_MCBSP_SPI_MASTER = 0,
-        OMAP_MCBSP_SPI_SLAVE,
-} omap_mcbsp_spi_mode;
-
-struct omap_mcbsp_spi_cfg {
-        omap_mcbsp_spi_mode             spi_mode;
-        omap_mcbsp_clk_polarity         rx_clock_polarity;
-        omap_mcbsp_clk_polarity         tx_clock_polarity;
-        omap_mcbsp_fs_polarity          fsx_polarity;
-        u8                              clk_div;
-        omap_mcbsp_clk_stp_mode         clk_stp_mode;
-        omap_mcbsp_word_length          word_length;
-};
-
-/* Platform specific configuration */
-struct omap_mcbsp_ops {
-        void (*request)(unsigned int);
-        void (*free)(unsigned int);
-        int (*check)(unsigned int);
-};
-
-struct omap_mcbsp_platform_data {
-        u32 virt_base;
-        u8 dma_rx_sync, dma_tx_sync;
-        u16 rx_irq, tx_irq;
-        struct omap_mcbsp_ops *ops;
-        char const *clk_name;
-};
-
-struct omap_mcbsp {
-        struct device *dev;
-        u32 io_base;
-        u8 id;
-        u8 free;
-        omap_mcbsp_word_length rx_word_length;
-        omap_mcbsp_word_length tx_word_length;
-
-        omap_mcbsp_io_type_t io_type; /* IRQ or poll */
-        /* IRQ based TX/RX */
-        int rx_irq;
-        int tx_irq;
-
-        /* DMA stuff */
-        u8 dma_rx_sync;
-        short dma_rx_lch;
-        u8 dma_tx_sync;
-        short dma_tx_lch;
-
-        /* Completion queues */
-        struct completion tx_irq_completion;
-        struct completion rx_irq_completion;
-        struct completion tx_dma_completion;
-        struct completion rx_dma_completion;
-
-        /* Protect the field .free, while checking if the mcbsp is in use */
-        spinlock_t lock;
-        struct omap_mcbsp_platform_data *pdata;
-        struct clk *clk;
-};
-
-int omap_mcbsp_init(void);
-void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
-                                        int size);
-void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
-int omap_mcbsp_request(unsigned int id);
-void omap_mcbsp_free(unsigned int id);
-void omap_mcbsp_start(unsigned int id);
-void omap_mcbsp_stop(unsigned int id);
-void omap_mcbsp_xmit_word(unsigned int id, u32 word);
-u32 omap_mcbsp_recv_word(unsigned int id);
-
-int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
-int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
-int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
-int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
-
-
-/* SPI specific API */
-void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
-
-/* Polled read/write functions */
-int omap_mcbsp_pollread(unsigned int id, u16 * buf);
-int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
-
-#endif
diff --git a/include/asm-arm/arch-omap/memory.h b/include/asm-arm/arch-omap/memory.h
deleted file mode 100644
index 14cba97c18ad..000000000000
--- a/include/asm-arm/arch-omap/memory.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/memory.h
- *
- * Memory map for OMAP-1510 and 1610
- *
- * Copyright (C) 2000 RidgeRun, Inc.
- * Author: Greg Lonnon <glonnon@ridgerun.com>
- *
- * This file was derived from linux/include/asm-arm/arch-intergrator/memory.h
- * Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-/*
- * Physical DRAM offset.
- */
-#if defined(CONFIG_ARCH_OMAP1)
-#define PHYS_OFFSET             UL(0x10000000)
-#elif defined(CONFIG_ARCH_OMAP2)
-#define PHYS_OFFSET             UL(0x80000000)
-#endif
-
-/*
- * Conversion between SDRAM and fake PCI bus, used by USB
- * NOTE: Physical address must be converted to Local Bus address
- *       on OMAP-1510 only
- */
-
-/*
- * Bus address is physical address, except for OMAP-1510 Local Bus.
- */
-#define __virt_to_bus(x)        __virt_to_phys(x)
-#define __bus_to_virt(x)        __phys_to_virt(x)
-
-/*
- * OMAP-1510 bus address is translated into a Local Bus address if the
- * OMAP bus type is lbus. We do the address translation based on the
- * device overriding the defaults used in the dma-mapping API.
- * Note that the is_lbus_device() test is not very efficient on 1510
- * because of the strncmp().
- */
-#ifdef CONFIG_ARCH_OMAP15XX
-
-/*
- * OMAP-1510 Local Bus address offset
- */
-#define OMAP1510_LB_OFFSET      UL(0x30000000)
-
-#define virt_to_lbus(x)         ((x) - PAGE_OFFSET + OMAP1510_LB_OFFSET)
-#define lbus_to_virt(x)         ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET)
-#define is_lbus_device(dev)     (cpu_is_omap15xx() && dev && (strncmp(dev->bus_id, "ohci", 4) == 0))
-
-#define __arch_page_to_dma(dev, page)   ({is_lbus_device(dev) ? \
-                                        (dma_addr_t)virt_to_lbus(page_address(page)) : \
-                                        (dma_addr_t)__virt_to_bus(page_address(page));})
-
-#define __arch_dma_to_virt(dev, addr)   ({is_lbus_device(dev) ? \
-                                        lbus_to_virt(addr) : \
-                                        __bus_to_virt(addr);})
-
-#define __arch_virt_to_dma(dev, addr)   ({is_lbus_device(dev) ? \
-                                        virt_to_lbus(addr) : \
-                                        __virt_to_bus(addr);})
-
-#endif  /* CONFIG_ARCH_OMAP15XX */
-
-/* Override the ARM default */
-#ifdef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
-
-#if (CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE == 0)
-#undef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
-#define CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE 2
-#endif
-
-#define CONSISTENT_DMA_SIZE \
-        (((CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE + 1) & ~1) * 1024 * 1024)
-
-#endif
-
-#endif
-
diff --git a/include/asm-arm/arch-omap/menelaus.h b/include/asm-arm/arch-omap/menelaus.h
deleted file mode 100644
index 69ed7ee40179..000000000000
--- a/include/asm-arm/arch-omap/menelaus.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/menelaus.h
- *
- * Functions to access Menelaus power management chip
- */
-
-#ifndef __ASM_ARCH_MENELAUS_H
-#define __ASM_ARCH_MENELAUS_H
-
-struct device;
-
-struct menelaus_platform_data {
-        int (* late_init)(struct device *dev);
-};
-
-extern int menelaus_register_mmc_callback(void (*callback)(void *data, u8 card_mask),
-                                          void *data);
-extern void menelaus_unregister_mmc_callback(void);
-extern int menelaus_set_mmc_opendrain(int slot, int enable);
-extern int menelaus_set_mmc_slot(int slot, int enable, int power, int cd_on);
-
-extern int menelaus_set_vmem(unsigned int mV);
-extern int menelaus_set_vio(unsigned int mV);
-extern int menelaus_set_vmmc(unsigned int mV);
-extern int menelaus_set_vaux(unsigned int mV);
-extern int menelaus_set_vdcdc(int dcdc, unsigned int mV);
-extern int menelaus_set_slot_sel(int enable);
-extern int menelaus_get_slot_pin_states(void);
-extern int menelaus_set_vcore_sw(unsigned int mV);
-extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV);
-
-#define EN_VPLL_SLEEP   (1 << 7)
-#define EN_VMMC_SLEEP   (1 << 6)
-#define EN_VAUX_SLEEP   (1 << 5)
-#define EN_VIO_SLEEP    (1 << 4)
-#define EN_VMEM_SLEEP   (1 << 3)
-#define EN_DC3_SLEEP    (1 << 2)
-#define EN_DC2_SLEEP    (1 << 1)
-#define EN_VC_SLEEP     (1 << 0)
-
-extern int menelaus_set_regulator_sleep(int enable, u32 val);
-
-#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_MENELAUS)
-#define omap_has_menelaus()     1
-#else
-#define omap_has_menelaus()     0
-#endif
-
-#endif
diff --git a/include/asm-arm/arch-omap/mmc.h b/include/asm-arm/arch-omap/mmc.h
deleted file mode 100644
index 7cfc5f258560..000000000000
--- a/include/asm-arm/arch-omap/mmc.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * MMC definitions for OMAP2
- *
- * Copyright (C) 2006 Nokia Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __OMAP2_MMC_H
-#define __OMAP2_MMC_H
-
-#include <linux/types.h>
-#include <linux/device.h>
-#include <linux/mmc/host.h>
-
-#include <asm/arch/board.h>
-
-#define OMAP_MMC_MAX_SLOTS      2
-
-struct omap_mmc_platform_data {
-        struct omap_mmc_conf    conf;
-
-        /* number of slots on board */
-        unsigned nr_slots:2;
-
-        /* set if your board has components or wiring that limits the
-         * maximum frequency on the MMC bus */
-        unsigned int max_freq;
-
-        /* switch the bus to a new slot */
-        int (* switch_slot)(struct device *dev, int slot);
-        /* initialize board-specific MMC functionality, can be NULL if
-         * not supported */
-        int (* init)(struct device *dev);
-        void (* cleanup)(struct device *dev);
-        void (* shutdown)(struct device *dev);
-
-        /* To handle board related suspend/resume functionality for MMC */
-        int (*suspend)(struct device *dev, int slot);
-        int (*resume)(struct device *dev, int slot);
-
-        struct omap_mmc_slot_data {
-                int (* set_bus_mode)(struct device *dev, int slot, int bus_mode);
-                int (* set_power)(struct device *dev, int slot, int power_on, int vdd);
-                int (* get_ro)(struct device *dev, int slot);
-
-                /* return MMC cover switch state, can be NULL if not supported.
-                 *
-                 * possible return values:
-                 *   0 - open
-                 *   1 - closed
-                 */
-                int (* get_cover_state)(struct device *dev, int slot);
-
-                const char *name;
-                u32 ocr_mask;
-
-                /* Card detection IRQs */
-                int card_detect_irq;
-                int (* card_detect)(int irq);
-
-                unsigned int ban_openended:1;
-
-        } slots[OMAP_MMC_MAX_SLOTS];
-};
-
-extern void omap_set_mmc_info(int host, const struct omap_mmc_platform_data *info);
-
-/* called from board-specific card detection service routine */
-extern void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed);
-
-#endif
diff --git a/include/asm-arm/arch-omap/mtd-xip.h b/include/asm-arm/arch-omap/mtd-xip.h
deleted file mode 100644
index f4714b5270d0..000000000000
--- a/include/asm-arm/arch-omap/mtd-xip.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * MTD primitives for XIP support. Architecture specific functions.
- *
- * Do not include this file directly. It's included from linux/mtd/xip.h
- *
- * Author: Vladimir Barinov <vbarinov@ru.mvista.com>
- *
- * (c) 2005 MontaVista Software, Inc.  This file is licensed under the
- * terms of the GNU General Public License version 2.  This program is
- * licensed "as is" without any warranty of any kind, whether express or
- * implied.
- */
-
-#ifndef __ARCH_OMAP_MTD_XIP_H__
-#define __ARCH_OMAP_MTD_XIP_H__
-
-#include <asm/arch/hardware.h>
-#define OMAP_MPU_TIMER_BASE     (0xfffec500)
-#define OMAP_MPU_TIMER_OFFSET   0x100
-
-typedef struct {
-        u32 cntl;                       /* CNTL_TIMER, R/W */
-        u32 load_tim;                   /* LOAD_TIM,   W */
-        u32 read_tim;                   /* READ_TIM,   R */
-} xip_omap_mpu_timer_regs_t;
-
-#define xip_omap_mpu_timer_base(n)                                      \
-((volatile xip_omap_mpu_timer_regs_t*)IO_ADDRESS(OMAP_MPU_TIMER_BASE +  \
-        (n)*OMAP_MPU_TIMER_OFFSET))
-
-static inline unsigned long xip_omap_mpu_timer_read(int nr)
-{
-        volatile xip_omap_mpu_timer_regs_t* timer = xip_omap_mpu_timer_base(nr);
-        return timer->read_tim;
-}
-
-#define xip_irqpending()        \
-        (omap_readl(OMAP_IH1_ITR) & ~omap_readl(OMAP_IH1_MIR))
-#define xip_currtime()          (~xip_omap_mpu_timer_read(0))
-
-/*
- * It's permitted to do approxmation for xip_elapsed_since macro
- * (see linux/mtd/xip.h)
- */
-
-#ifdef CONFIG_MACH_OMAP_PERSEUS2
-#define xip_elapsed_since(x)    (signed)((~xip_omap_mpu_timer_read(0) - (x)) / 7)
-#else
-#define xip_elapsed_since(x)    (signed)((~xip_omap_mpu_timer_read(0) - (x)) / 6)
-#endif
-
-/*
- * xip_cpu_idle() is used when waiting for a delay equal or larger than
- * the system timer tick period.  This should put the CPU into idle mode
- * to save power and to be woken up only when some interrupts are pending.
- * As above, this should not rely upon standard kernel code.
- */
-
-#define xip_cpu_idle()  asm volatile ("mcr p15, 0, %0, c7, c0, 4" :: "r" (1))
-
-#endif /* __ARCH_OMAP_MTD_XIP_H__ */
diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h
deleted file mode 100644
index ff9a5b5575fd..000000000000
--- a/include/asm-arm/arch-omap/mux.h
+++ /dev/null
@@ -1,615 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/mux.h
- *
- * Table of the Omap register configurations for the FUNC_MUX and
- * PULL_DWN combinations.
- *
- * Copyright (C) 2004 - 2008 Texas Instruments Inc.
- * Copyright (C) 2003 - 2008 Nokia Corporation
- *
- * Written by Tony Lindgren
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * NOTE: Please use the following naming style for new pin entries.
- *       For example, W8_1610_MMC2_DAT0, where:
- *       - W8        = ball
- *       - 1610      = 1510 or 1610, none if common for both 1510 and 1610
- *       - MMC2_DAT0 = function
- */
-
-#ifndef __ASM_ARCH_MUX_H
-#define __ASM_ARCH_MUX_H
-
-#define PU_PD_SEL_NA            0       /* No pu_pd reg available */
-#define PULL_DWN_CTRL_NA        0       /* No pull-down control needed */
-
-#ifdef  CONFIG_OMAP_MUX_DEBUG
-#define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
-                                        .mux_reg = FUNC_MUX_CTRL_##reg, \
-                                        .mask_offset = mode_offset, \
-                                        .mask = mode,
-
-#define PULL_REG(reg, bit, status)      .pull_name = "PULL_DWN_CTRL_"#reg, \
-                                        .pull_reg = PULL_DWN_CTRL_##reg, \
-                                        .pull_bit = bit, \
-                                        .pull_val = status,
-
-#define PU_PD_REG(reg, status)          .pu_pd_name = "PU_PD_SEL_"#reg, \
-                                        .pu_pd_reg = PU_PD_SEL_##reg, \
-                                        .pu_pd_val = status,
-
-#define MUX_REG_730(reg, mode_offset, mode) .mux_reg_name = "OMAP730_IO_CONF_"#reg, \
-                                        .mux_reg = OMAP730_IO_CONF_##reg, \
-                                        .mask_offset = mode_offset, \
-                                        .mask = mode,
-
-#define PULL_REG_730(reg, bit, status)  .pull_name = "OMAP730_IO_CONF_"#reg, \
-                                        .pull_reg = OMAP730_IO_CONF_##reg, \
-                                        .pull_bit = bit, \
-                                        .pull_val = status,
-
-#else
-
-#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
-                                        .mask_offset = mode_offset, \
-                                        .mask = mode,
-
-#define PULL_REG(reg, bit, status)      .pull_reg = PULL_DWN_CTRL_##reg, \
-                                        .pull_bit = bit, \
-                                        .pull_val = status,
-
-#define PU_PD_REG(reg, status)          .pu_pd_reg = PU_PD_SEL_##reg, \
-                                        .pu_pd_val = status,
-
-#define MUX_REG_730(reg, mode_offset, mode) \
-                                        .mux_reg = OMAP730_IO_CONF_##reg, \
-                                        .mask_offset = mode_offset, \
-                                        .mask = mode,
-
-#define PULL_REG_730(reg, bit, status)  .pull_reg = OMAP730_IO_CONF_##reg, \
-                                        .pull_bit = bit, \
-                                        .pull_val = status,
-
-#endif /* CONFIG_OMAP_MUX_DEBUG */
-
-#define MUX_CFG(desc, mux_reg, mode_offset, mode,       \
-                pull_reg, pull_bit, pull_status,        \
-                pu_pd_reg, pu_pd_status, debug_status)  \
-{                                                       \
-        .name =  desc,                                  \
-        .debug = debug_status,                          \
-        MUX_REG(mux_reg, mode_offset, mode)             \
-        PULL_REG(pull_reg, pull_bit, pull_status)       \
-        PU_PD_REG(pu_pd_reg, pu_pd_status)              \
-},
-
-
-/*
- * OMAP730 has a slightly different config for the pin mux.
- * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and
- *   not the FUNC_MUX_CTRL_x regs from hardware.h
- * - for pull-up/down, only has one enable bit which is is in the same register
- *   as mux config
- */
-#define MUX_CFG_730(desc, mux_reg, mode_offset, mode,   \
-                   pull_bit, pull_status, debug_status)\
-{                                                       \
-        .name =  desc,                                  \
-        .debug = debug_status,                          \
-        MUX_REG_730(mux_reg, mode_offset, mode)         \
-        PULL_REG_730(mux_reg, pull_bit, pull_status)    \
-        PU_PD_REG(NA, 0)                \
-},
-
-#define MUX_CFG_24XX(desc, reg_offset, mode,                    \
-                                pull_en, pull_mode, dbg)        \
-{                                                               \
-        .name           = desc,                                 \
-        .debug          = dbg,                                  \
-        .mux_reg        = reg_offset,                           \
-        .mask           = mode,                                 \
-        .pull_val       = pull_en,                              \
-        .pu_pd_val      = pull_mode,                            \
-},
-
-
-#define PULL_DISABLED   0
-#define PULL_ENABLED    1
-
-#define PULL_DOWN       0
-#define PULL_UP         1
-
-struct pin_config {
-        char *name;
-        unsigned char busy;
-        unsigned char debug;
-
-        const char *mux_reg_name;
-        const unsigned int mux_reg;
-        const unsigned char mask_offset;
-        const unsigned char mask;
-
-        const char *pull_name;
-        const unsigned int pull_reg;
-        const unsigned char pull_val;
-        const unsigned char pull_bit;
-
-        const char *pu_pd_name;
-        const unsigned int pu_pd_reg;
-        const unsigned char pu_pd_val;
-};
-
-enum omap730_index {
-        /* OMAP 730 keyboard */
-        E2_730_KBR0,
-        J7_730_KBR1,
-        E1_730_KBR2,
-        F3_730_KBR3,
-        D2_730_KBR4,
-        C2_730_KBC0,
-        D3_730_KBC1,
-        E4_730_KBC2,
-        F4_730_KBC3,
-        E3_730_KBC4,
-
-        /* USB */
-        AA17_730_USB_DM,
-        W16_730_USB_PU_EN,
-        W17_730_USB_VBUSI,
-};
-
-enum omap1xxx_index {
-        /* UART1 (BT_UART_GATING)*/
-        UART1_TX = 0,
-        UART1_RTS,
-
-        /* UART2 (COM_UART_GATING)*/
-        UART2_TX,
-        UART2_RX,
-        UART2_CTS,
-        UART2_RTS,
-
-        /* UART3 (GIGA_UART_GATING) */
-        UART3_TX,
-        UART3_RX,
-        UART3_CTS,
-        UART3_RTS,
-        UART3_CLKREQ,
-        UART3_BCLK,     /* 12MHz clock out */
-        Y15_1610_UART3_RTS,
-
-        /* PWT & PWL */
-        PWT,
-        PWL,
-
-        /* USB master generic */
-        R18_USB_VBUS,
-        R18_1510_USB_GPIO0,
-        W4_USB_PUEN,
-        W4_USB_CLKO,
-        W4_USB_HIGHZ,
-        W4_GPIO58,
-
-        /* USB1 master */
-        USB1_SUSP,
-        USB1_SEO,
-        W13_1610_USB1_SE0,
-        USB1_TXEN,
-        USB1_TXD,
-        USB1_VP,
-        USB1_VM,
-        USB1_RCV,
-        USB1_SPEED,
-        R13_1610_USB1_SPEED,
-        R13_1710_USB1_SE0,
-
-        /* USB2 master */
-        USB2_SUSP,
-        USB2_VP,
-        USB2_TXEN,
-        USB2_VM,
-        USB2_RCV,
-        USB2_SEO,
-        USB2_TXD,
-
-        /* OMAP-1510 GPIO */
-        R18_1510_GPIO0,
-        R19_1510_GPIO1,
-        M14_1510_GPIO2,
-
-        /* OMAP1610 GPIO */
-        P18_1610_GPIO3,
-        Y15_1610_GPIO17,
-
-        /* OMAP-1710 GPIO */
-        R18_1710_GPIO0,
-        V2_1710_GPIO10,
-        N21_1710_GPIO14,
-        W15_1710_GPIO40,
-
-        /* MPUIO */
-        MPUIO2,
-        N15_1610_MPUIO2,
-        MPUIO4,
-        MPUIO5,
-        T20_1610_MPUIO5,
-        W11_1610_MPUIO6,
-        V10_1610_MPUIO7,
-        W11_1610_MPUIO9,
-        V10_1610_MPUIO10,
-        W10_1610_MPUIO11,
-        E20_1610_MPUIO13,
-        U20_1610_MPUIO14,
-        E19_1610_MPUIO15,
-
-        /* MCBSP2 */
-        MCBSP2_CLKR,
-        MCBSP2_CLKX,
-        MCBSP2_DR,
-        MCBSP2_DX,
-        MCBSP2_FSR,
-        MCBSP2_FSX,
-
-        /* MCBSP3 */
-        MCBSP3_CLKX,
-
-        /* Misc ballouts */
-        BALLOUT_V8_ARMIO3,
-        N20_HDQ,
-
-        /* OMAP-1610 MMC2 */
-        W8_1610_MMC2_DAT0,
-        V8_1610_MMC2_DAT1,
-        W15_1610_MMC2_DAT2,
-        R10_1610_MMC2_DAT3,
-        Y10_1610_MMC2_CLK,
-        Y8_1610_MMC2_CMD,
-        V9_1610_MMC2_CMDDIR,
-        V5_1610_MMC2_DATDIR0,
-        W19_1610_MMC2_DATDIR1,
-        R18_1610_MMC2_CLKIN,
-
-        /* OMAP-1610 External Trace Interface */
-        M19_1610_ETM_PSTAT0,
-        L15_1610_ETM_PSTAT1,
-        L18_1610_ETM_PSTAT2,
-        L19_1610_ETM_D0,
-        J19_1610_ETM_D6,
-        J18_1610_ETM_D7,
-
-        /* OMAP16XX GPIO */
-        P20_1610_GPIO4,
-        V9_1610_GPIO7,
-        W8_1610_GPIO9,
-        N20_1610_GPIO11,
-        N19_1610_GPIO13,
-        P10_1610_GPIO22,
-        V5_1610_GPIO24,
-        AA20_1610_GPIO_41,
-        W19_1610_GPIO48,
-        M7_1610_GPIO62,
-        V14_16XX_GPIO37,
-        R9_16XX_GPIO18,
-        L14_16XX_GPIO49,
-
-        /* OMAP-1610 uWire */
-        V19_1610_UWIRE_SCLK,
-        U18_1610_UWIRE_SDI,
-        W21_1610_UWIRE_SDO,
-        N14_1610_UWIRE_CS0,
-        P15_1610_UWIRE_CS3,
-        N15_1610_UWIRE_CS1,
-
-        /* OMAP-1610 SPI */
-        U19_1610_SPIF_SCK,
-        U18_1610_SPIF_DIN,
-        P20_1610_SPIF_DIN,
-        W21_1610_SPIF_DOUT,
-        R18_1610_SPIF_DOUT,
-        N14_1610_SPIF_CS0,
-        N15_1610_SPIF_CS1,
-        T19_1610_SPIF_CS2,
-        P15_1610_SPIF_CS3,
-
-        /* OMAP-1610 Flash */
-        L3_1610_FLASH_CS2B_OE,
-        M8_1610_FLASH_CS2B_WE,
-
-        /* First MMC */
-        MMC_CMD,
-        MMC_DAT1,
-        MMC_DAT2,
-        MMC_DAT0,
-        MMC_CLK,
-        MMC_DAT3,
-
-        /* OMAP-1710 MMC CMDDIR and DATDIR0 */
-        M15_1710_MMC_CLKI,
-        P19_1710_MMC_CMDDIR,
-        P20_1710_MMC_DATDIR0,
-
-        /* OMAP-1610 USB0 alternate pin configuration */
-        W9_USB0_TXEN,
-        AA9_USB0_VP,
-        Y5_USB0_RCV,
-        R9_USB0_VM,
-        V6_USB0_TXD,
-        W5_USB0_SE0,
-        V9_USB0_SPEED,
-        V9_USB0_SUSP,
-
-        /* USB2 */
-        W9_USB2_TXEN,
-        AA9_USB2_VP,
-        Y5_USB2_RCV,
-        R9_USB2_VM,
-        V6_USB2_TXD,
-        W5_USB2_SE0,
-
-        /* 16XX UART */
-        R13_1610_UART1_TX,
-        V14_16XX_UART1_RX,
-        R14_1610_UART1_CTS,
-        AA15_1610_UART1_RTS,
-        R9_16XX_UART2_RX,
-        L14_16XX_UART3_RX,
-
-        /* I2C OMAP-1610 */
-        I2C_SCL,
-        I2C_SDA,
-
-        /* Keypad */
-        F18_1610_KBC0,
-        D20_1610_KBC1,
-        D19_1610_KBC2,
-        E18_1610_KBC3,
-        C21_1610_KBC4,
-        G18_1610_KBR0,
-        F19_1610_KBR1,
-        H14_1610_KBR2,
-        E20_1610_KBR3,
-        E19_1610_KBR4,
-        N19_1610_KBR5,
-
-        /* Power management */
-        T20_1610_LOW_PWR,
-
-        /* MCLK Settings */
-        V5_1710_MCLK_ON,
-        V5_1710_MCLK_OFF,
-        R10_1610_MCLK_ON,
-        R10_1610_MCLK_OFF,
-
-        /* CompactFlash controller */
-        P11_1610_CF_CD2,
-        R11_1610_CF_IOIS16,
-        V10_1610_CF_IREQ,
-        W10_1610_CF_RESET,
-        W11_1610_CF_CD1,
-
-        /* parallel camera */
-        J15_1610_CAM_LCLK,
-        J18_1610_CAM_D7,
-        J19_1610_CAM_D6,
-        J14_1610_CAM_D5,
-        K18_1610_CAM_D4,
-        K19_1610_CAM_D3,
-        K15_1610_CAM_D2,
-        K14_1610_CAM_D1,
-        L19_1610_CAM_D0,
-        L18_1610_CAM_VS,
-        L15_1610_CAM_HS,
-        M19_1610_CAM_RSTZ,
-        Y15_1610_CAM_OUTCLK,
-
-        /* serial camera */
-        H19_1610_CAM_EXCLK,
-        Y12_1610_CCP_CLKP,
-        W13_1610_CCP_CLKM,
-        W14_1610_CCP_DATAP,
-        Y14_1610_CCP_DATAM,
-
-};
-
-enum omap24xx_index {
-        /* 24xx I2C */
-        M19_24XX_I2C1_SCL,
-        L15_24XX_I2C1_SDA,
-        J15_24XX_I2C2_SCL,
-        H19_24XX_I2C2_SDA,
-
-        /* 24xx Menelaus interrupt */
-        W19_24XX_SYS_NIRQ,
-
-        /* 24xx clock */
-        W14_24XX_SYS_CLKOUT,
-
-        /* 24xx GPMC chipselects, wait pin monitoring */
-        E2_GPMC_NCS2,
-        L2_GPMC_NCS7,
-        L3_GPMC_WAIT0,
-        N7_GPMC_WAIT1,
-        M1_GPMC_WAIT2,
-        P1_GPMC_WAIT3,
-
-        /* 242X McBSP */
-        Y15_24XX_MCBSP2_CLKX,
-        R14_24XX_MCBSP2_FSX,
-        W15_24XX_MCBSP2_DR,
-        V15_24XX_MCBSP2_DX,
-
-        /* 24xx GPIO */
-        M21_242X_GPIO11,
-        P21_242X_GPIO12,
-        AA10_242X_GPIO13,
-        AA6_242X_GPIO14,
-        AA4_242X_GPIO15,
-        Y11_242X_GPIO16,
-        AA12_242X_GPIO17,
-        AA8_242X_GPIO58,
-        Y20_24XX_GPIO60,
-        W4__24XX_GPIO74,
-        N15_24XX_GPIO85,
-        M15_24XX_GPIO92,
-        P20_24XX_GPIO93,
-        P18_24XX_GPIO95,
-        M18_24XX_GPIO96,
-        L14_24XX_GPIO97,
-        J15_24XX_GPIO99,
-        V14_24XX_GPIO117,
-        P14_24XX_GPIO125,
-
-        /* 242x DBG GPIO */
-        V4_242X_GPIO49,
-        W2_242X_GPIO50,
-        U4_242X_GPIO51,
-        V3_242X_GPIO52,
-        V2_242X_GPIO53,
-        V6_242X_GPIO53,
-        T4_242X_GPIO54,
-        Y4_242X_GPIO54,
-        T3_242X_GPIO55,
-        U2_242X_GPIO56,
-
-        /* 24xx external DMA requests */
-        AA10_242X_DMAREQ0,
-        AA6_242X_DMAREQ1,
-        E4_242X_DMAREQ2,
-        G4_242X_DMAREQ3,
-        D3_242X_DMAREQ4,
-        E3_242X_DMAREQ5,
-
-        /* UART3 */
-        K15_24XX_UART3_TX,
-        K14_24XX_UART3_RX,
-
-        /* MMC/SDIO */
-        G19_24XX_MMC_CLKO,
-        H18_24XX_MMC_CMD,
-        F20_24XX_MMC_DAT0,
-        H14_24XX_MMC_DAT1,
-        E19_24XX_MMC_DAT2,
-        D19_24XX_MMC_DAT3,
-        F19_24XX_MMC_DAT_DIR0,
-        E20_24XX_MMC_DAT_DIR1,
-        F18_24XX_MMC_DAT_DIR2,
-        E18_24XX_MMC_DAT_DIR3,
-        G18_24XX_MMC_CMD_DIR,
-        H15_24XX_MMC_CLKI,
-
-        /* Full speed USB */
-        J20_24XX_USB0_PUEN,
-        J19_24XX_USB0_VP,
-        K20_24XX_USB0_VM,
-        J18_24XX_USB0_RCV,
-        K19_24XX_USB0_TXEN,
-        J14_24XX_USB0_SE0,
-        K18_24XX_USB0_DAT,
-
-        N14_24XX_USB1_SE0,
-        W12_24XX_USB1_SE0,
-        P15_24XX_USB1_DAT,
-        R13_24XX_USB1_DAT,
-        W20_24XX_USB1_TXEN,
-        P13_24XX_USB1_TXEN,
-        V19_24XX_USB1_RCV,
-        V12_24XX_USB1_RCV,
-
-        AA10_24XX_USB2_SE0,
-        Y11_24XX_USB2_DAT,
-        AA12_24XX_USB2_TXEN,
-        AA6_24XX_USB2_RCV,
-        AA4_24XX_USB2_TLLSE0,
-
-        /* Keypad GPIO*/
-        T19_24XX_KBR0,
-        R19_24XX_KBR1,
-        V18_24XX_KBR2,
-        M21_24XX_KBR3,
-        E5__24XX_KBR4,
-        M18_24XX_KBR5,
-        R20_24XX_KBC0,
-        M14_24XX_KBC1,
-        H19_24XX_KBC2,
-        V17_24XX_KBC3,
-        P21_24XX_KBC4,
-        L14_24XX_KBC5,
-        N19_24XX_KBC6,
-
-        /* 24xx Menelaus Keypad GPIO */
-        B3__24XX_KBR5,
-        AA4_24XX_KBC2,
-        B13_24XX_KBC6,
-
-        /* 2430 USB */
-        AD9_2430_USB0_PUEN,
-        Y11_2430_USB0_VP,
-        AD7_2430_USB0_VM,
-        AE7_2430_USB0_RCV,
-        AD4_2430_USB0_TXEN,
-        AF9_2430_USB0_SE0,
-        AE6_2430_USB0_DAT,
-        AD24_2430_USB1_SE0,
-        AB24_2430_USB1_RCV,
-        Y25_2430_USB1_TXEN,
-        AA26_2430_USB1_DAT,
-
-        /* 2430 HS-USB */
-        AD9_2430_USB0HS_DATA3,
-        Y11_2430_USB0HS_DATA4,
-        AD7_2430_USB0HS_DATA5,
-        AE7_2430_USB0HS_DATA6,
-        AD4_2430_USB0HS_DATA2,
-        AF9_2430_USB0HS_DATA0,
-        AE6_2430_USB0HS_DATA1,
-        AE8_2430_USB0HS_CLK,
-        AD8_2430_USB0HS_DIR,
-        AE5_2430_USB0HS_STP,
-        AE9_2430_USB0HS_NXT,
-        AC7_2430_USB0HS_DATA7,
-
-        /* 2430 McBSP */
-        AC10_2430_MCBSP2_FSX,
-        AD16_2430_MCBSP2_CLX,
-        AE13_2430_MCBSP2_DX,
-        AD13_2430_MCBSP2_DR,
-        AC10_2430_MCBSP2_FSX_OFF,
-        AD16_2430_MCBSP2_CLX_OFF,
-        AE13_2430_MCBSP2_DX_OFF,
-        AD13_2430_MCBSP2_DR_OFF,
-
-};
-
-struct omap_mux_cfg {
-        struct pin_config       *pins;
-        unsigned long           size;
-        int                     (*cfg_reg)(const struct pin_config *cfg);
-};
-
-#ifdef  CONFIG_OMAP_MUX
-/* setup pin muxing in Linux */
-extern int omap1_mux_init(void);
-extern int omap2_mux_init(void);
-extern int omap_mux_register(struct omap_mux_cfg *);
-extern int omap_cfg_reg(unsigned long reg_cfg);
-#else
-/* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
-static inline int omap1_mux_init(void) { return 0; }
-static inline int omap2_mux_init(void) { return 0; }
-static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
-#endif
-
-#endif
diff --git a/include/asm-arm/arch-omap/nand.h b/include/asm-arm/arch-omap/nand.h
deleted file mode 100644
index 17ae26e35353..000000000000
--- a/include/asm-arm/arch-omap/nand.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * include/asm-arm/arch-omap/nand.h
- *
- * Copyright (C) 2006 Micron Technology Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/mtd/partitions.h>
-
-struct omap_nand_platform_data {
-        unsigned int            options;
-        int                     cs;
-        int                     gpio_irq;
-        struct mtd_partition    *parts;
-        int                     nr_parts;
-        int                     (*nand_setup)(void __iomem *);
-        int                     (*dev_ready)(struct omap_nand_platform_data *);
-        int                     dma_channel;
-        void __iomem            *gpmc_cs_baseaddr;
-        void __iomem            *gpmc_baseaddr;
-};
diff --git a/include/asm-arm/arch-omap/omap-alsa.h b/include/asm-arm/arch-omap/omap-alsa.h
deleted file mode 100644
index faa0ed23d4ba..000000000000
--- a/include/asm-arm/arch-omap/omap-alsa.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/omap-alsa.h
- *
- * Alsa Driver for AIC23 and TSC2101 codecs on OMAP platform boards.
- *
- * Copyright (C) 2006 Mika Laitio <lamikr@cc.jyu.fi>
- *
- * Copyright (C) 2005 Instituto Nokia de Tecnologia - INdT - Manaus Brazil
- * Written by Daniel Petrini, David Cohen, Anderson Briglia
- *            {daniel.petrini, david.cohen, anderson.briglia}@indt.org.br
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the  GNU General Public License along
- * with this program; if not, write  to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- *  History
- *  -------
- *
- *  2005/07/25 INdT-10LE Kernel Team -  Alsa driver for omap osk,
- *                                      original version based in sa1100 driver
- *                                      and omap oss driver.
- */
-
-#ifndef __OMAP_ALSA_H
-#define __OMAP_ALSA_H
-
-#include <asm/arch/dma.h>
-#include <sound/core.h>
-#include <sound/pcm.h>
-#include <asm/arch/mcbsp.h>
-#include <linux/platform_device.h>
-
-#define DMA_BUF_SIZE    (1024 * 8)
-
-/*
- * Buffer management for alsa and dma
- */
-struct audio_stream {
-        char *id;               /* identification string */
-        int stream_id;          /* numeric identification */
-        int dma_dev;            /* dma number of that device */
-        int *lch;               /* Chain of channels this stream is linked to */
-        char started;           /* to store if the chain was started or not */
-        int dma_q_head;         /* DMA Channel Q Head */
-        int dma_q_tail;         /* DMA Channel Q Tail */
-        char dma_q_count;       /* DMA Channel Q Count */
-        int active:1;           /* we are using this stream for transfer now */
-        int period;             /* current transfer period */
-        int periods;            /* current count of periods registerd in the DMA engine */
-        spinlock_t dma_lock;    /* for locking in DMA operations */
-        struct snd_pcm_substream *stream;       /* the pcm stream */
-        unsigned linked:1;      /* dma channels linked */
-        int offset;             /* store start position of the last period in the alsa buffer */
-        int (*hw_start)(void);  /* interface to start HW interface, e.g. McBSP */
-        int (*hw_stop)(void);   /* interface to stop HW interface, e.g. McBSP */
-};
-
-/*
- * Alsa card structure for aic23
- */
-struct snd_card_omap_codec {
-        struct snd_card *card;
-        struct snd_pcm *pcm;
-        long samplerate;
-        struct audio_stream s[2];       /* playback & capture */
-};
-
-/* Codec specific information and function pointers.
- * Codec (omap-alsa-aic23.c and omap-alsa-tsc2101.c)
- * are responsible for defining the function pointers.
- */
-struct omap_alsa_codec_config {
-        char    *name;
-        struct  omap_mcbsp_reg_cfg *mcbsp_regs_alsa;
-        struct  snd_pcm_hw_constraint_list *hw_constraints_rates;
-        struct  snd_pcm_hardware *snd_omap_alsa_playback;
-        struct  snd_pcm_hardware *snd_omap_alsa_capture;
-        void    (*codec_configure_dev)(void);
-        void    (*codec_set_samplerate)(long);
-        void    (*codec_clock_setup)(void);
-        int     (*codec_clock_on)(void);
-        int     (*codec_clock_off)(void);
-        int     (*get_default_samplerate)(void);
-};
-
-/*********** Mixer function prototypes *************************/
-int snd_omap_mixer(struct snd_card_omap_codec *);
-void snd_omap_init_mixer(void);
-
-#ifdef CONFIG_PM
-void snd_omap_suspend_mixer(void);
-void snd_omap_resume_mixer(void);
-#endif
-
-int snd_omap_alsa_post_probe(struct platform_device *pdev, struct omap_alsa_codec_config *config);
-int snd_omap_alsa_remove(struct platform_device *pdev);
-#ifdef CONFIG_PM
-int snd_omap_alsa_suspend(struct platform_device *pdev, pm_message_t state);
-int snd_omap_alsa_resume(struct platform_device *pdev);
-#else
-#define snd_omap_alsa_suspend   NULL
-#define snd_omap_alsa_resume    NULL
-#endif
-
-void callback_omap_alsa_sound_dma(void *);
-
-#endif
diff --git a/include/asm-arm/arch-omap/omap1510.h b/include/asm-arm/arch-omap/omap1510.h
deleted file mode 100644
index c575d354850f..000000000000
--- a/include/asm-arm/arch-omap/omap1510.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* linux/include/asm-arm/arch-omap/omap1510.h
- *
- * Hardware definitions for TI OMAP1510 processor.
- *
- * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the  GNU General Public License along
- * with this program; if not, write  to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_OMAP15XX_H
-#define __ASM_ARCH_OMAP15XX_H
-
-/*
- * ----------------------------------------------------------------------------
- * Base addresses
- * ----------------------------------------------------------------------------
- */
-
-/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
-
-#define OMAP1510_DSP_BASE       0xE0000000
-#define OMAP1510_DSP_SIZE       0x28000
-#define OMAP1510_DSP_START      0xE0000000
-
-#define OMAP1510_DSPREG_BASE    0xE1000000
-#define OMAP1510_DSPREG_SIZE    SZ_128K
-#define OMAP1510_DSPREG_START   0xE1000000
-
-#endif /*  __ASM_ARCH_OMAP15XX_H */
-
diff --git a/include/asm-arm/arch-omap/omap16xx.h b/include/asm-arm/arch-omap/omap16xx.h
deleted file mode 100644
index f7f5cdfdccce..000000000000
--- a/include/asm-arm/arch-omap/omap16xx.h
+++ /dev/null
@@ -1,197 +0,0 @@
-/* linux/include/asm-arm/arch-omap/omap16xx.h
- *
- * Hardware definitions for TI OMAP1610/5912/1710 processors.
- *
- * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the  GNU General Public License along
- * with this program; if not, write  to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_OMAP16XX_H
-#define __ASM_ARCH_OMAP16XX_H
-
-/*
- * ----------------------------------------------------------------------------
- * Base addresses
- * ----------------------------------------------------------------------------
- */
-
-/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
-
-#define OMAP16XX_DSP_BASE       0xE0000000
-#define OMAP16XX_DSP_SIZE       0x28000
-#define OMAP16XX_DSP_START      0xE0000000
-
-#define OMAP16XX_DSPREG_BASE    0xE1000000
-#define OMAP16XX_DSPREG_SIZE    SZ_128K
-#define OMAP16XX_DSPREG_START   0xE1000000
-
-/*
- * ---------------------------------------------------------------------------
- * Interrupts
- * ---------------------------------------------------------------------------
- */
-#define OMAP_IH2_0_BASE         (0xfffe0000)
-#define OMAP_IH2_1_BASE         (0xfffe0100)
-#define OMAP_IH2_2_BASE         (0xfffe0200)
-#define OMAP_IH2_3_BASE         (0xfffe0300)
-
-#define OMAP_IH2_0_ITR          (OMAP_IH2_0_BASE + 0x00)
-#define OMAP_IH2_0_MIR          (OMAP_IH2_0_BASE + 0x04)
-#define OMAP_IH2_0_SIR_IRQ      (OMAP_IH2_0_BASE + 0x10)
-#define OMAP_IH2_0_SIR_FIQ      (OMAP_IH2_0_BASE + 0x14)
-#define OMAP_IH2_0_CONTROL      (OMAP_IH2_0_BASE + 0x18)
-#define OMAP_IH2_0_ILR0         (OMAP_IH2_0_BASE + 0x1c)
-#define OMAP_IH2_0_ISR          (OMAP_IH2_0_BASE + 0x9c)
-
-#define OMAP_IH2_1_ITR          (OMAP_IH2_1_BASE + 0x00)
-#define OMAP_IH2_1_MIR          (OMAP_IH2_1_BASE + 0x04)
-#define OMAP_IH2_1_SIR_IRQ      (OMAP_IH2_1_BASE + 0x10)
-#define OMAP_IH2_1_SIR_FIQ      (OMAP_IH2_1_BASE + 0x14)
-#define OMAP_IH2_1_CONTROL      (OMAP_IH2_1_BASE + 0x18)
-#define OMAP_IH2_1_ILR1         (OMAP_IH2_1_BASE + 0x1c)
-#define OMAP_IH2_1_ISR          (OMAP_IH2_1_BASE + 0x9c)
-
-#define OMAP_IH2_2_ITR          (OMAP_IH2_2_BASE + 0x00)
-#define OMAP_IH2_2_MIR          (OMAP_IH2_2_BASE + 0x04)
-#define OMAP_IH2_2_SIR_IRQ      (OMAP_IH2_2_BASE + 0x10)
-#define OMAP_IH2_2_SIR_FIQ      (OMAP_IH2_2_BASE + 0x14)
-#define OMAP_IH2_2_CONTROL      (OMAP_IH2_2_BASE + 0x18)
-#define OMAP_IH2_2_ILR2         (OMAP_IH2_2_BASE + 0x1c)
-#define OMAP_IH2_2_ISR          (OMAP_IH2_2_BASE + 0x9c)
-
-#define OMAP_IH2_3_ITR          (OMAP_IH2_3_BASE + 0x00)
-#define OMAP_IH2_3_MIR          (OMAP_IH2_3_BASE + 0x04)
-#define OMAP_IH2_3_SIR_IRQ      (OMAP_IH2_3_BASE + 0x10)
-#define OMAP_IH2_3_SIR_FIQ      (OMAP_IH2_3_BASE + 0x14)
-#define OMAP_IH2_3_CONTROL      (OMAP_IH2_3_BASE + 0x18)
-#define OMAP_IH2_3_ILR3         (OMAP_IH2_3_BASE + 0x1c)
-#define OMAP_IH2_3_ISR          (OMAP_IH2_3_BASE + 0x9c)
-
-/*
- * ----------------------------------------------------------------------------
- * Clocks
- * ----------------------------------------------------------------------------
- */
-#define OMAP16XX_ARM_IDLECT3    (CLKGEN_REG_BASE + 0x24)
-
-/*
- * ----------------------------------------------------------------------------
- * Pin configuration registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP16XX_CONF_VOLTAGE_VDDSHV6   (1 << 8)
-#define OMAP16XX_CONF_VOLTAGE_VDDSHV7   (1 << 9)
-#define OMAP16XX_CONF_VOLTAGE_VDDSHV8   (1 << 10)
-#define OMAP16XX_CONF_VOLTAGE_VDDSHV9   (1 << 11)
-#define OMAP16XX_SUBLVDS_CONF_VALID     (1 << 13)
-
-/*
- * ----------------------------------------------------------------------------
- * System control registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP1610_RESET_CONTROL  0xfffe1140
-
-/*
- * ---------------------------------------------------------------------------
- * TIPB bus interface
- * ---------------------------------------------------------------------------
- */
-#define TIPB_SWITCH_BASE                 (0xfffbc800)
-#define OMAP16XX_MMCSD2_SSW_MPU_CONF    (TIPB_SWITCH_BASE + 0x160)
-
-/* UART3 Registers Maping through MPU bus */
-#define UART3_RHR               (OMAP_UART3_BASE + 0)
-#define UART3_THR               (OMAP_UART3_BASE + 0)
-#define UART3_DLL               (OMAP_UART3_BASE + 0)
-#define UART3_IER               (OMAP_UART3_BASE + 4)
-#define UART3_DLH               (OMAP_UART3_BASE + 4)
-#define UART3_IIR               (OMAP_UART3_BASE + 8)
-#define UART3_FCR               (OMAP_UART3_BASE + 8)
-#define UART3_EFR               (OMAP_UART3_BASE + 8)
-#define UART3_LCR               (OMAP_UART3_BASE + 0x0C)
-#define UART3_MCR               (OMAP_UART3_BASE + 0x10)
-#define UART3_XON1_ADDR1        (OMAP_UART3_BASE + 0x10)
-#define UART3_XON2_ADDR2        (OMAP_UART3_BASE + 0x14)
-#define UART3_LSR               (OMAP_UART3_BASE + 0x14)
-#define UART3_TCR               (OMAP_UART3_BASE + 0x18)
-#define UART3_MSR               (OMAP_UART3_BASE + 0x18)
-#define UART3_XOFF1             (OMAP_UART3_BASE + 0x18)
-#define UART3_XOFF2             (OMAP_UART3_BASE + 0x1C)
-#define UART3_SPR               (OMAP_UART3_BASE + 0x1C)
-#define UART3_TLR               (OMAP_UART3_BASE + 0x1C)
-#define UART3_MDR1              (OMAP_UART3_BASE + 0x20)
-#define UART3_MDR2              (OMAP_UART3_BASE + 0x24)
-#define UART3_SFLSR             (OMAP_UART3_BASE + 0x28)
-#define UART3_TXFLL             (OMAP_UART3_BASE + 0x28)
-#define UART3_RESUME            (OMAP_UART3_BASE + 0x2C)
-#define UART3_TXFLH             (OMAP_UART3_BASE + 0x2C)
-#define UART3_SFREGL            (OMAP_UART3_BASE + 0x30)
-#define UART3_RXFLL             (OMAP_UART3_BASE + 0x30)
-#define UART3_SFREGH            (OMAP_UART3_BASE + 0x34)
-#define UART3_RXFLH             (OMAP_UART3_BASE + 0x34)
-#define UART3_BLR               (OMAP_UART3_BASE + 0x38)
-#define UART3_ACREG             (OMAP_UART3_BASE + 0x3C)
-#define UART3_DIV16             (OMAP_UART3_BASE + 0x3C)
-#define UART3_SCR               (OMAP_UART3_BASE + 0x40)
-#define UART3_SSR               (OMAP_UART3_BASE + 0x44)
-#define UART3_EBLR              (OMAP_UART3_BASE + 0x48)
-#define UART3_OSC_12M_SEL       (OMAP_UART3_BASE + 0x4C)
-#define UART3_MVR               (OMAP_UART3_BASE + 0x50)
-
-/*
- * ---------------------------------------------------------------------------
- * Watchdog timer
- * ---------------------------------------------------------------------------
- */
-
-/* 32-bit Watchdog timer in OMAP 16XX */
-#define OMAP_16XX_WATCHDOG_BASE        (0xfffeb000)
-#define OMAP_16XX_WIDR         (OMAP_16XX_WATCHDOG_BASE + 0x00)
-#define OMAP_16XX_WD_SYSCONFIG (OMAP_16XX_WATCHDOG_BASE + 0x10)
-#define OMAP_16XX_WD_SYSSTATUS (OMAP_16XX_WATCHDOG_BASE + 0x14)
-#define OMAP_16XX_WCLR         (OMAP_16XX_WATCHDOG_BASE + 0x24)
-#define OMAP_16XX_WCRR         (OMAP_16XX_WATCHDOG_BASE + 0x28)
-#define OMAP_16XX_WLDR         (OMAP_16XX_WATCHDOG_BASE + 0x2c)
-#define OMAP_16XX_WTGR         (OMAP_16XX_WATCHDOG_BASE + 0x30)
-#define OMAP_16XX_WWPS         (OMAP_16XX_WATCHDOG_BASE + 0x34)
-#define OMAP_16XX_WSPR         (OMAP_16XX_WATCHDOG_BASE + 0x48)
-
-#define WCLR_PRE_SHIFT         5
-#define WCLR_PTV_SHIFT         2
-
-#define WWPS_W_PEND_WSPR       (1 << 4)
-#define WWPS_W_PEND_WTGR       (1 << 3)
-#define WWPS_W_PEND_WLDR       (1 << 2)
-#define WWPS_W_PEND_WCRR       (1 << 1)
-#define WWPS_W_PEND_WCLR       (1 << 0)
-
-#define WSPR_ENABLE_0          (0x0000bbbb)
-#define WSPR_ENABLE_1          (0x00004444)
-#define WSPR_DISABLE_0         (0x0000aaaa)
-#define WSPR_DISABLE_1         (0x00005555)
-
-/* Mailbox */
-#define OMAP16XX_MAILBOX_BASE   (0xfffcf000)
-
-#endif /*  __ASM_ARCH_OMAP16XX_H */
-
diff --git a/include/asm-arm/arch-omap/omap24xx.h b/include/asm-arm/arch-omap/omap24xx.h
deleted file mode 100644
index b9fcaae287c8..000000000000
--- a/include/asm-arm/arch-omap/omap24xx.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * include/asm-arm/arch-omap/omap24xx.h
- *
- * This file contains the processor specific definitions
- * of the TI OMAP24XX.
- *
- * Copyright (C) 2007 Texas Instruments.
- * Copyright (C) 2007 Nokia Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-
-#ifndef __ASM_ARCH_OMAP24XX_H
-#define __ASM_ARCH_OMAP24XX_H
-
-/*
- * Please place only base defines here and put the rest in device
- * specific headers. Note also that some of these defines are needed
- * for omap1 to compile without adding ifdefs.
- */
-
-#define L4_24XX_BASE            0x48000000
-#define L4_WK_243X_BASE         0x49000000
-#define L3_24XX_BASE            0x68000000
-
-/* interrupt controller */
-#define OMAP24XX_IC_BASE        (L4_24XX_BASE + 0xfe000)
-#define OMAP24XX_IVA_INTC_BASE  0x40000000
-#define IRQ_SIR_IRQ             0x0040
-
-#define OMAP2420_CTRL_BASE      L4_24XX_BASE
-#define OMAP2420_32KSYNCT_BASE  (L4_24XX_BASE + 0x4000)
-#define OMAP2420_PRCM_BASE      (L4_24XX_BASE + 0x8000)
-#define OMAP2420_CM_BASE        (L4_24XX_BASE + 0x8000)
-#define OMAP2420_PRM_BASE       OMAP2420_CM_BASE
-#define OMAP2420_SDRC_BASE      (L3_24XX_BASE + 0x9000)
-#define OMAP2420_SMS_BASE       0x68008000
-
-#define OMAP2430_32KSYNCT_BASE  (L4_WK_243X_BASE + 0x20000)
-#define OMAP2430_PRCM_BASE      (L4_WK_243X_BASE + 0x6000)
-#define OMAP2430_CM_BASE        (L4_WK_243X_BASE + 0x6000)
-#define OMAP2430_PRM_BASE       OMAP2430_CM_BASE
-
-#define OMAP243X_SMS_BASE       0x6C000000
-#define OMAP243X_SDRC_BASE      0x6D000000
-#define OMAP243X_GPMC_BASE      0x6E000000
-#define OMAP243X_SCM_BASE       (L4_WK_243X_BASE + 0x2000)
-#define OMAP243X_CTRL_BASE      OMAP243X_SCM_BASE
-#define OMAP243X_HS_BASE        (L4_24XX_BASE + 0x000ac000)
-
-/* DSP SS */
-#define OMAP2420_DSP_BASE       0x58000000
-#define OMAP2420_DSP_MEM_BASE   (OMAP2420_DSP_BASE + 0x0)
-#define OMAP2420_DSP_IPI_BASE   (OMAP2420_DSP_BASE + 0x1000000)
-#define OMAP2420_DSP_MMU_BASE   (OMAP2420_DSP_BASE + 0x2000000)
-
-#define OMAP243X_DSP_BASE       0x5C000000
-#define OMAP243X_DSP_MEM_BASE   (OMAP243X_DSP_BASE + 0x0)
-#define OMAP243X_DSP_MMU_BASE   (OMAP243X_DSP_BASE + 0x1000000)
-
-/* Mailbox */
-#define OMAP24XX_MAILBOX_BASE   (L4_24XX_BASE + 0x94000)
-
-/* Camera */
-#define OMAP24XX_CAMERA_BASE    (L4_24XX_BASE + 0x52000)
-
-/* Security */
-#define OMAP24XX_SEC_BASE       (L4_24XX_BASE + 0xA0000)
-#define OMAP24XX_SEC_RNG_BASE   (OMAP24XX_SEC_BASE + 0x0000)
-#define OMAP24XX_SEC_DES_BASE   (OMAP24XX_SEC_BASE + 0x2000)
-#define OMAP24XX_SEC_SHA1MD5_BASE (OMAP24XX_SEC_BASE + 0x4000)
-#define OMAP24XX_SEC_AES_BASE   (OMAP24XX_SEC_BASE + 0x6000)
-#define OMAP24XX_SEC_PKA_BASE   (OMAP24XX_SEC_BASE + 0x8000)
-
-#if defined(CONFIG_ARCH_OMAP2420)
-
-#define OMAP2_32KSYNCT_BASE     OMAP2420_32KSYNCT_BASE
-#define OMAP2_PRCM_BASE         OMAP2420_PRCM_BASE
-#define OMAP2_CM_BASE           OMAP2420_CM_BASE
-#define OMAP2_PRM_BASE          OMAP2420_PRM_BASE
-#define OMAP2_VA_IC_BASE        IO_ADDRESS(OMAP24XX_IC_BASE)
-
-#elif defined(CONFIG_ARCH_OMAP2430)
-
-#define OMAP2_32KSYNCT_BASE     OMAP2430_32KSYNCT_BASE
-#define OMAP2_PRCM_BASE         OMAP2430_PRCM_BASE
-#define OMAP2_CM_BASE           OMAP2430_CM_BASE
-#define OMAP2_PRM_BASE          OMAP2430_PRM_BASE
-#define OMAP2_VA_IC_BASE        IO_ADDRESS(OMAP24XX_IC_BASE)
-
-#endif
-
-#endif /* __ASM_ARCH_OMAP24XX_H */
-
diff --git a/include/asm-arm/arch-omap/omap34xx.h b/include/asm-arm/arch-omap/omap34xx.h
deleted file mode 100644
index aa30c6d10abd..000000000000
--- a/include/asm-arm/arch-omap/omap34xx.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * include/asm-arm/arch-omap/omap34xx.h
- *
- * This file contains the processor specific definitions of the TI OMAP34XX.
- *
- * Copyright (C) 2007 Texas Instruments.
- * Copyright (C) 2007 Nokia Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __ASM_ARCH_OMAP34XX_H
-#define __ASM_ARCH_OMAP34XX_H
-
-/*
- * Please place only base defines here and put the rest in device
- * specific headers.
- */
-
-#define L4_34XX_BASE            0x48000000
-#define L4_WK_34XX_BASE         0x48300000
-#define L4_WK_OMAP_BASE         L4_WK_34XX_BASE
-#define L4_PER_34XX_BASE        0x49000000
-#define L4_PER_OMAP_BASE        L4_PER_34XX_BASE
-#define L4_EMU_34XX_BASE        0x54000000
-#define L4_EMU_BASE             L4_EMU_34XX_BASE
-#define L3_34XX_BASE            0x68000000
-#define L3_OMAP_BASE            L3_34XX_BASE
-
-#define OMAP3430_32KSYNCT_BASE  0x48320000
-#define OMAP3430_CM_BASE        0x48004800
-#define OMAP3430_PRM_BASE       0x48306800
-#define OMAP343X_SMS_BASE       0x6C000000
-#define OMAP343X_SDRC_BASE      0x6D000000
-#define OMAP34XX_GPMC_BASE      0x6E000000
-#define OMAP343X_SCM_BASE       0x48002000
-#define OMAP343X_CTRL_BASE      OMAP343X_SCM_BASE
-
-#define OMAP34XX_IC_BASE        0x48200000
-#define OMAP34XX_IVA_INTC_BASE  0x40000000
-#define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
-#define OMAP34XX_HSUSB_HOST_BASE        (L4_34XX_BASE + 0x64000)
-#define OMAP34XX_USBTLL_BASE    (L4_34XX_BASE + 0x62000)
-
-
-#if defined(CONFIG_ARCH_OMAP3430)
-
-#define OMAP2_32KSYNCT_BASE             OMAP3430_32KSYNCT_BASE
-#define OMAP2_CM_BASE                   OMAP3430_CM_BASE
-#define OMAP2_PRM_BASE                  OMAP3430_PRM_BASE
-#define OMAP2_VA_IC_BASE                IO_ADDRESS(OMAP34XX_IC_BASE)
-
-#endif
-
-#define OMAP34XX_DSP_BASE       0x58000000
-#define OMAP34XX_DSP_MEM_BASE   (OMAP34XX_DSP_BASE + 0x0)
-#define OMAP34XX_DSP_IPI_BASE   (OMAP34XX_DSP_BASE + 0x1000000)
-#define OMAP34XX_DSP_MMU_BASE   (OMAP34XX_DSP_BASE + 0x2000000)
-#endif /* __ASM_ARCH_OMAP34XX_H */
-
diff --git a/include/asm-arm/arch-omap/omap730.h b/include/asm-arm/arch-omap/omap730.h
deleted file mode 100644
index 755b64c5e9f0..000000000000
--- a/include/asm-arm/arch-omap/omap730.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* linux/include/asm-arm/arch-omap/omap730.h
- *
- * Hardware definitions for TI OMAP730 processor.
- *
- * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the  GNU General Public License along
- * with this program; if not, write  to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_OMAP730_H
-#define __ASM_ARCH_OMAP730_H
-
-/*
- * ----------------------------------------------------------------------------
- * Base addresses
- * ----------------------------------------------------------------------------
- */
-
-/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
-
-#define OMAP730_DSP_BASE        0xE0000000
-#define OMAP730_DSP_SIZE        0x50000
-#define OMAP730_DSP_START       0xE0000000
-
-#define OMAP730_DSPREG_BASE     0xE1000000
-#define OMAP730_DSPREG_SIZE     SZ_128K
-#define OMAP730_DSPREG_START    0xE1000000
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP730 specific configuration registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP730_CONFIG_BASE     0xfffe1000
-#define OMAP730_IO_CONF_0       0xfffe1070
-#define OMAP730_IO_CONF_1       0xfffe1074
-#define OMAP730_IO_CONF_2       0xfffe1078
-#define OMAP730_IO_CONF_3       0xfffe107c
-#define OMAP730_IO_CONF_4       0xfffe1080
-#define OMAP730_IO_CONF_5       0xfffe1084
-#define OMAP730_IO_CONF_6       0xfffe1088
-#define OMAP730_IO_CONF_7       0xfffe108c
-#define OMAP730_IO_CONF_8       0xfffe1090
-#define OMAP730_IO_CONF_9       0xfffe1094
-#define OMAP730_IO_CONF_10      0xfffe1098
-#define OMAP730_IO_CONF_11      0xfffe109c
-#define OMAP730_IO_CONF_12      0xfffe10a0
-#define OMAP730_IO_CONF_13      0xfffe10a4
-
-#define OMAP730_MODE_1          0xfffe1010
-#define OMAP730_MODE_2          0xfffe1014
-
-/* CSMI specials: in terms of base + offset */
-#define OMAP730_MODE2_OFFSET    0x14
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP730 traffic controller configuration registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP730_FLASH_CFG_0     0xfffecc10
-#define OMAP730_FLASH_ACFG_0    0xfffecc50
-#define OMAP730_FLASH_CFG_1     0xfffecc14
-#define OMAP730_FLASH_ACFG_1    0xfffecc54
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP730 DSP control registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP730_ICR_BASE        0xfffbb800
-#define OMAP730_DSP_M_CTL       0xfffbb804
-#define OMAP730_DSP_MMU_BASE    0xfffed200
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP730 PCC_UPLD configuration registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP730_PCC_UPLD_CTRL_BASE      (0xfffe0900)
-#define OMAP730_PCC_UPLD_CTRL           (OMAP730_PCC_UPLD_CTRL_BASE + 0x00)
-
-#endif /*  __ASM_ARCH_OMAP730_H */
-
diff --git a/include/asm-arm/arch-omap/omapfb.h b/include/asm-arm/arch-omap/omapfb.h
deleted file mode 100644
index 46d7a4f60854..000000000000
--- a/include/asm-arm/arch-omap/omapfb.h
+++ /dev/null
@@ -1,395 +0,0 @@
-/*
- * File: include/asm-arm/arch-omap/omapfb.h
- *
- * Framebuffer driver for TI OMAP boards
- *
- * Copyright (C) 2004 Nokia Corporation
- * Author: Imre Deak <imre.deak@nokia.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
- */
-
-#ifndef __OMAPFB_H
-#define __OMAPFB_H
-
-#include <asm/ioctl.h>
-#include <asm/types.h>
-
-/* IOCTL commands. */
-
-#define OMAP_IOW(num, dtype)    _IOW('O', num, dtype)
-#define OMAP_IOR(num, dtype)    _IOR('O', num, dtype)
-#define OMAP_IOWR(num, dtype)   _IOWR('O', num, dtype)
-#define OMAP_IO(num)            _IO('O', num)
-
-#define OMAPFB_MIRROR           OMAP_IOW(31, int)
-#define OMAPFB_SYNC_GFX         OMAP_IO(37)
-#define OMAPFB_VSYNC            OMAP_IO(38)
-#define OMAPFB_SET_UPDATE_MODE  OMAP_IOW(40, int)
-#define OMAPFB_GET_CAPS         OMAP_IOR(42, struct omapfb_caps)
-#define OMAPFB_GET_UPDATE_MODE  OMAP_IOW(43, int)
-#define OMAPFB_LCD_TEST         OMAP_IOW(45, int)
-#define OMAPFB_CTRL_TEST        OMAP_IOW(46, int)
-#define OMAPFB_UPDATE_WINDOW_OLD OMAP_IOW(47, struct omapfb_update_window_old)
-#define OMAPFB_SET_COLOR_KEY    OMAP_IOW(50, struct omapfb_color_key)
-#define OMAPFB_GET_COLOR_KEY    OMAP_IOW(51, struct omapfb_color_key)
-#define OMAPFB_SETUP_PLANE      OMAP_IOW(52, struct omapfb_plane_info)
-#define OMAPFB_QUERY_PLANE      OMAP_IOW(53, struct omapfb_plane_info)
-#define OMAPFB_UPDATE_WINDOW    OMAP_IOW(54, struct omapfb_update_window)
-#define OMAPFB_SETUP_MEM        OMAP_IOW(55, struct omapfb_mem_info)
-#define OMAPFB_QUERY_MEM        OMAP_IOW(56, struct omapfb_mem_info)
-
-#define OMAPFB_CAPS_GENERIC_MASK        0x00000fff
-#define OMAPFB_CAPS_LCDC_MASK           0x00fff000
-#define OMAPFB_CAPS_PANEL_MASK          0xff000000
-
-#define OMAPFB_CAPS_MANUAL_UPDATE       0x00001000
-#define OMAPFB_CAPS_TEARSYNC            0x00002000
-#define OMAPFB_CAPS_PLANE_RELOCATE_MEM  0x00004000
-#define OMAPFB_CAPS_PLANE_SCALE         0x00008000
-#define OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE 0x00010000
-#define OMAPFB_CAPS_WINDOW_SCALE        0x00020000
-#define OMAPFB_CAPS_WINDOW_OVERLAY      0x00040000
-#define OMAPFB_CAPS_SET_BACKLIGHT       0x01000000
-
-/* Values from DSP must map to lower 16-bits */
-#define OMAPFB_FORMAT_MASK              0x00ff
-#define OMAPFB_FORMAT_FLAG_DOUBLE       0x0100
-#define OMAPFB_FORMAT_FLAG_TEARSYNC     0x0200
-#define OMAPFB_FORMAT_FLAG_FORCE_VSYNC  0x0400
-#define OMAPFB_FORMAT_FLAG_ENABLE_OVERLAY       0x0800
-#define OMAPFB_FORMAT_FLAG_DISABLE_OVERLAY      0x1000
-
-#define OMAPFB_EVENT_READY      1
-#define OMAPFB_EVENT_DISABLED   2
-
-#define OMAPFB_MEMTYPE_SDRAM            0
-#define OMAPFB_MEMTYPE_SRAM             1
-#define OMAPFB_MEMTYPE_MAX              1
-
-enum omapfb_color_format {
-        OMAPFB_COLOR_RGB565 = 0,
-        OMAPFB_COLOR_YUV422,
-        OMAPFB_COLOR_YUV420,
-        OMAPFB_COLOR_CLUT_8BPP,
-        OMAPFB_COLOR_CLUT_4BPP,
-        OMAPFB_COLOR_CLUT_2BPP,
-        OMAPFB_COLOR_CLUT_1BPP,
-        OMAPFB_COLOR_RGB444,
-        OMAPFB_COLOR_YUY422,
-};
-
-struct omapfb_update_window {
-        __u32 x, y;
-        __u32 width, height;
-        __u32 format;
-        __u32 out_x, out_y;
-        __u32 out_width, out_height;
-        __u32 reserved[8];
-};
-
-struct omapfb_update_window_old {
-        __u32 x, y;
-        __u32 width, height;
-        __u32 format;
-};
-
-enum omapfb_plane {
-        OMAPFB_PLANE_GFX = 0,
-        OMAPFB_PLANE_VID1,
-        OMAPFB_PLANE_VID2,
-};
-
-enum omapfb_channel_out {
-        OMAPFB_CHANNEL_OUT_LCD = 0,
-        OMAPFB_CHANNEL_OUT_DIGIT,
-};
-
-struct omapfb_plane_info {
-        __u32 pos_x;
-        __u32 pos_y;
-        __u8  enabled;
-        __u8  channel_out;
-        __u8  mirror;
-        __u8  reserved1;
-        __u32 out_width;
-        __u32 out_height;
-        __u32 reserved2[12];
-};
-
-struct omapfb_mem_info {
-        __u32 size;
-        __u8  type;
-        __u8  reserved[3];
-};
-
-struct omapfb_caps {
-        __u32 ctrl;
-        __u32 plane_color;
-        __u32 wnd_color;
-};
-
-enum omapfb_color_key_type {
-        OMAPFB_COLOR_KEY_DISABLED = 0,
-        OMAPFB_COLOR_KEY_GFX_DST,
-        OMAPFB_COLOR_KEY_VID_SRC,
-};
-
-struct omapfb_color_key {
-        __u8  channel_out;
-        __u32 background;
-        __u32 trans_key;
-        __u8  key_type;
-};
-
-enum omapfb_update_mode {
-        OMAPFB_UPDATE_DISABLED = 0,
-        OMAPFB_AUTO_UPDATE,
-        OMAPFB_MANUAL_UPDATE
-};
-
-#ifdef __KERNEL__
-
-#include <linux/completion.h>
-#include <linux/interrupt.h>
-#include <linux/fb.h>
-#include <linux/mutex.h>
-
-#include <asm/arch/board.h>
-
-#define OMAP_LCDC_INV_VSYNC             0x0001
-#define OMAP_LCDC_INV_HSYNC             0x0002
-#define OMAP_LCDC_INV_PIX_CLOCK         0x0004
-#define OMAP_LCDC_INV_OUTPUT_EN         0x0008
-#define OMAP_LCDC_HSVS_RISING_EDGE      0x0010
-#define OMAP_LCDC_HSVS_OPPOSITE         0x0020
-
-#define OMAP_LCDC_SIGNAL_MASK           0x003f
-
-#define OMAP_LCDC_PANEL_TFT             0x0100
-
-#define OMAPFB_PLANE_XRES_MIN           8
-#define OMAPFB_PLANE_YRES_MIN           8
-
-#ifdef CONFIG_ARCH_OMAP1
-#define OMAPFB_PLANE_NUM                1
-#else
-#define OMAPFB_PLANE_NUM                3
-#endif
-
-struct omapfb_device;
-
-struct lcd_panel {
-        const char      *name;
-        int             config;         /* TFT/STN, signal inversion */
-        int             bpp;            /* Pixel format in fb mem */
-        int             data_lines;     /* Lines on LCD HW interface */
-
-        int             x_res, y_res;
-        int             pixel_clock;    /* In kHz */
-        int             hsw;            /* Horizontal synchronization
-                                           pulse width */
-        int             hfp;            /* Horizontal front porch */
-        int             hbp;            /* Horizontal back porch */
-        int             vsw;            /* Vertical synchronization
-                                           pulse width */
-        int             vfp;            /* Vertical front porch */
-        int             vbp;            /* Vertical back porch */
-        int             acb;            /* ac-bias pin frequency */
-        int             pcd;            /* pixel clock divider.
-                                           Obsolete use pixel_clock instead */
-
-        int             (*init)         (struct lcd_panel *panel,
-                                         struct omapfb_device *fbdev);
-        void            (*cleanup)      (struct lcd_panel *panel);
-        int             (*enable)       (struct lcd_panel *panel);
-        void            (*disable)      (struct lcd_panel *panel);
-        unsigned long   (*get_caps)     (struct lcd_panel *panel);
-        int             (*set_bklight_level)(struct lcd_panel *panel,
-                                             unsigned int level);
-        unsigned int    (*get_bklight_level)(struct lcd_panel *panel);
-        unsigned int    (*get_bklight_max)  (struct lcd_panel *panel);
-        int             (*run_test)     (struct lcd_panel *panel, int test_num);
-};
-
-struct extif_timings {
-        int cs_on_time;
-        int cs_off_time;
-        int we_on_time;
-        int we_off_time;
-        int re_on_time;
-        int re_off_time;
-        int we_cycle_time;
-        int re_cycle_time;
-        int cs_pulse_width;
-        int access_time;
-
-        int clk_div;
-
-        u32 tim[5];             /* set by extif->convert_timings */
-
-        int converted;
-};
-
-struct lcd_ctrl_extif {
-        int  (*init)            (struct omapfb_device *fbdev);
-        void (*cleanup)         (void);
-        void (*get_clk_info)    (u32 *clk_period, u32 *max_clk_div);
-        unsigned long (*get_max_tx_rate)(void);
-        int  (*convert_timings) (struct extif_timings *timings);
-        void (*set_timings)     (const struct extif_timings *timings);
-        void (*set_bits_per_cycle)(int bpc);
-        void (*write_command)   (const void *buf, unsigned int len);
-        void (*read_data)       (void *buf, unsigned int len);
-        void (*write_data)      (const void *buf, unsigned int len);
-        void (*transfer_area)   (int width, int height,
-                                 void (callback)(void * data), void *data);
-        int  (*setup_tearsync)  (unsigned pin_cnt,
-                                 unsigned hs_pulse_time, unsigned vs_pulse_time,
-                                 int hs_pol_inv, int vs_pol_inv, int div);
-        int  (*enable_tearsync) (int enable, unsigned line);
-
-        unsigned long           max_transmit_size;
-};
-
-struct omapfb_notifier_block {
-        struct notifier_block   nb;
-        void                    *data;
-        int                     plane_idx;
-};
-
-typedef int (*omapfb_notifier_callback_t)(struct notifier_block *,
-                                          unsigned long event,
-                                          void *fbi);
-
-struct omapfb_mem_region {
-        dma_addr_t      paddr;
-        void            *vaddr;
-        unsigned long   size;
-        u8              type;           /* OMAPFB_PLANE_MEM_* */
-        unsigned        alloc:1;        /* allocated by the driver */
-        unsigned        map:1;          /* kernel mapped by the driver */
-};
-
-struct omapfb_mem_desc {
-        int                             region_cnt;
-        struct omapfb_mem_region        region[OMAPFB_PLANE_NUM];
-};
-
-struct lcd_ctrl {
-        const char      *name;
-        void            *data;
-
-        int             (*init)           (struct omapfb_device *fbdev,
-                                           int ext_mode,
-                                           struct omapfb_mem_desc *req_md);
-        void            (*cleanup)        (void);
-        void            (*bind_client)    (struct omapfb_notifier_block *nb);
-        void            (*get_caps)       (int plane, struct omapfb_caps *caps);
-        int             (*set_update_mode)(enum omapfb_update_mode mode);
-        enum omapfb_update_mode (*get_update_mode)(void);
-        int             (*setup_plane)    (int plane, int channel_out,
-                                           unsigned long offset,
-                                           int screen_width,
-                                           int pos_x, int pos_y, int width,
-                                           int height, int color_mode);
-        int             (*setup_mem)      (int plane, size_t size,
-                                           int mem_type, unsigned long *paddr);
-        int             (*mmap)           (struct fb_info *info,
-                                           struct vm_area_struct *vma);
-        int             (*set_scale)      (int plane,
-                                           int orig_width, int orig_height,
-                                           int out_width, int out_height);
-        int             (*enable_plane)   (int plane, int enable);
-        int             (*update_window)  (struct fb_info *fbi,
-                                           struct omapfb_update_window *win,
-                                           void (*callback)(void *),
-                                           void *callback_data);
-        void            (*sync)           (void);
-        void            (*suspend)        (void);
-        void            (*resume)         (void);
-        int             (*run_test)       (int test_num);
-        int             (*setcolreg)      (u_int regno, u16 red, u16 green,
-                                           u16 blue, u16 transp,
-                                           int update_hw_mem);
-        int             (*set_color_key)  (struct omapfb_color_key *ck);
-        int             (*get_color_key)  (struct omapfb_color_key *ck);
-};
-
-enum omapfb_state {
-        OMAPFB_DISABLED = 0,
-        OMAPFB_SUSPENDED= 99,
-        OMAPFB_ACTIVE   = 100
-};
-
-struct omapfb_plane_struct {
-        int                             idx;
-        struct omapfb_plane_info        info;
-        enum omapfb_color_format        color_mode;
-        struct omapfb_device            *fbdev;
-};
-
-struct omapfb_device {
-        int                     state;
-        int                     ext_lcdc;               /* Using external
-                                                           LCD controller */
-        struct mutex            rqueue_mutex;
-
-        int                     palette_size;
-        u32                     pseudo_palette[17];
-
-        struct lcd_panel        *panel;                 /* LCD panel */
-        struct lcd_ctrl         *ctrl;                  /* LCD controller */
-        struct lcd_ctrl         *int_ctrl;              /* internal LCD ctrl */
-        struct lcd_ctrl_extif   *ext_if;                /* LCD ctrl external
-                                                           interface */
-        struct device           *dev;
-        struct fb_var_screeninfo        new_var;        /* for mode changes */
-
-        struct omapfb_mem_desc          mem_desc;
-        struct fb_info                  *fb_info[OMAPFB_PLANE_NUM];
-};
-
-struct omapfb_platform_data {
-        struct omap_lcd_config          lcd;
-        struct omapfb_mem_desc          mem_desc;
-        void                            *ctrl_platform_data;
-};
-
-#ifdef CONFIG_ARCH_OMAP1
-extern struct lcd_ctrl omap1_lcd_ctrl;
-#else
-extern struct lcd_ctrl omap2_disp_ctrl;
-#endif
-
-extern void omapfb_register_panel(struct lcd_panel *panel);
-extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval);
-extern void omapfb_notify_clients(struct omapfb_device *fbdev,
-                                  unsigned long event);
-extern int  omapfb_register_client(struct omapfb_notifier_block *nb,
-                                   omapfb_notifier_callback_t callback,
-                                   void *callback_data);
-extern int  omapfb_unregister_client(struct omapfb_notifier_block *nb);
-extern int  omapfb_update_window_async(struct fb_info *fbi,
-                                       struct omapfb_update_window *win,
-                                       void (*callback)(void *),
-                                       void *callback_data);
-
-/* in arch/arm/plat-omap/fb.c */
-extern void omapfb_set_ctrl_platform_data(void *pdata);
-
-#endif /* __KERNEL__ */
-
-#endif /* __OMAPFB_H */
diff --git a/include/asm-arm/arch-omap/onenand.h b/include/asm-arm/arch-omap/onenand.h
deleted file mode 100644
index 6c959d0ce470..000000000000
--- a/include/asm-arm/arch-omap/onenand.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * include/asm-arm/arch-omap/onenand.h
- *
- * Copyright (C) 2006 Nokia Corporation
- * Author: Juha Yrjola
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/mtd/partitions.h>
-
-struct omap_onenand_platform_data {
-        int                     cs;
-        int                     gpio_irq;
-        struct mtd_partition    *parts;
-        int                     nr_parts;
-        int                     (*onenand_setup)(void __iomem *);
-        int                     dma_channel;
-};
diff --git a/include/asm-arm/arch-omap/param.h b/include/asm-arm/arch-omap/param.h
deleted file mode 100644
index face9ad41e97..000000000000
--- a/include/asm-arm/arch-omap/param.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-omap/param.h
- *
- */
-
-#ifdef CONFIG_OMAP_32K_TIMER_HZ
-#define HZ      CONFIG_OMAP_32K_TIMER_HZ
-#endif
diff --git a/include/asm-arm/arch-omap/pm.h b/include/asm-arm/arch-omap/pm.h
deleted file mode 100644
index 14588059981f..000000000000
--- a/include/asm-arm/arch-omap/pm.h
+++ /dev/null
@@ -1,356 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/pm.h
- *
- * Header file for OMAP Power Management Routines
- *
- * Author: MontaVista Software, Inc.
- *         support@mvista.com
- *
- * Copyright 2002 MontaVista Software Inc.
- *
- * Cleanup 2004 for Linux 2.6 by Dirk Behme <dirk.behme@de.bosch.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_OMAP_PM_H
-#define __ASM_ARCH_OMAP_PM_H
-
-/*
- * ----------------------------------------------------------------------------
- * Register and offset definitions to be used in PM assembler code
- * ----------------------------------------------------------------------------
- */
-#define CLKGEN_REG_ASM_BASE             io_p2v(0xfffece00)
-#define ARM_IDLECT1_ASM_OFFSET          0x04
-#define ARM_IDLECT2_ASM_OFFSET          0x08
-
-#define TCMIF_ASM_BASE                  io_p2v(0xfffecc00)
-#define EMIFS_CONFIG_ASM_OFFSET         0x0c
-#define EMIFF_SDRAM_CONFIG_ASM_OFFSET   0x20
-
-/*
- * ----------------------------------------------------------------------------
- * Power management bitmasks
- * ----------------------------------------------------------------------------
- */
-#define IDLE_WAIT_CYCLES                0x00000fff
-#define PERIPHERAL_ENABLE               0x2
-
-#define SELF_REFRESH_MODE               0x0c000001
-#define IDLE_EMIFS_REQUEST              0xc
-#define MODEM_32K_EN                    0x1
-#define PER_EN                          0x1
-
-#define CPU_SUSPEND_SIZE                200
-#define ULPD_LOW_PWR_EN                 0x0001
-#define ULPD_DEEP_SLEEP_TRANSITION_EN   0x0010
-#define ULPD_SETUP_ANALOG_CELL_3_VAL    0
-#define ULPD_POWER_CTRL_REG_VAL         0x0219
-
-#define DSP_IDLE_DELAY                  10
-#define DSP_IDLE                        0x0040
-#define DSP_RST                         0x0004
-#define DSP_ENABLE                      0x0002
-#define SUFFICIENT_DSP_RESET_TIME       1000
-#define DEFAULT_MPUI_CONFIG             0x05cf
-#define ENABLE_XORCLK                   0x2
-#define DSP_CLOCK_ENABLE                0x2000
-#define DSP_IDLE_MODE                   0x2
-#define TC_IDLE_REQUEST                 (0x0000000c)
-
-#define IRQ_LEVEL2                      (1<<0)
-#define IRQ_KEYBOARD                    (1<<1)
-#define IRQ_UART2                       (1<<15)
-
-#define PDE_BIT                         0x08
-#define PWD_EN_BIT                      0x04
-#define EN_PERCK_BIT                    0x04
-
-#define OMAP1510_DEEP_SLEEP_REQUEST     0x0ec7
-#define OMAP1510_BIG_SLEEP_REQUEST      0x0cc5
-#define OMAP1510_IDLE_LOOP_REQUEST      0x0c00
-#define OMAP1510_IDLE_CLOCK_DOMAINS     0x2
-
-/* Both big sleep and deep sleep use same values. Difference is in ULPD. */
-#define OMAP1610_IDLECT1_SLEEP_VAL      0x13c7
-#define OMAP1610_IDLECT2_SLEEP_VAL      0x09c7
-#define OMAP1610_IDLECT3_VAL            0x3f
-#define OMAP1610_IDLECT3_SLEEP_ORMASK   0x2c
-#define OMAP1610_IDLECT3                0xfffece24
-#define OMAP1610_IDLE_LOOP_REQUEST      0x0400
-
-#define OMAP730_IDLECT1_SLEEP_VAL       0x16c7
-#define OMAP730_IDLECT2_SLEEP_VAL       0x09c7
-#define OMAP730_IDLECT3_VAL             0x3f
-#define OMAP730_IDLECT3         0xfffece24
-#define OMAP730_IDLE_LOOP_REQUEST       0x0C00
-
-#if     !defined(CONFIG_ARCH_OMAP730) && \
-        !defined(CONFIG_ARCH_OMAP15XX) && \
-        !defined(CONFIG_ARCH_OMAP16XX) && \
-        !defined(CONFIG_ARCH_OMAP24XX)
-#error "Power management for this processor not implemented yet"
-#endif
-
-#ifndef __ASSEMBLER__
-
-#include <linux/clk.h>
-
-extern void prevent_idle_sleep(void);
-extern void allow_idle_sleep(void);
-
-/**
- * clk_deny_idle - Prevents the clock from being idled during MPU idle
- * @clk: clock signal handle
- */
-void clk_deny_idle(struct clk *clk);
-
-/**
- * clk_allow_idle - Counters previous clk_deny_idle
- * @clk: clock signal handle
- */
-void clk_deny_idle(struct clk *clk);
-
-extern void omap_pm_idle(void);
-extern void omap_pm_suspend(void);
-extern void omap730_cpu_suspend(unsigned short, unsigned short);
-extern void omap1510_cpu_suspend(unsigned short, unsigned short);
-extern void omap1610_cpu_suspend(unsigned short, unsigned short);
-extern void omap24xx_cpu_suspend(u32 dll_ctrl, u32 cpu_revision);
-extern void omap730_idle_loop_suspend(void);
-extern void omap1510_idle_loop_suspend(void);
-extern void omap1610_idle_loop_suspend(void);
-extern void omap24xx_idle_loop_suspend(void);
-
-extern unsigned int omap730_cpu_suspend_sz;
-extern unsigned int omap1510_cpu_suspend_sz;
-extern unsigned int omap1610_cpu_suspend_sz;
-extern unsigned int omap24xx_cpu_suspend_sz;
-extern unsigned int omap730_idle_loop_suspend_sz;
-extern unsigned int omap1510_idle_loop_suspend_sz;
-extern unsigned int omap1610_idle_loop_suspend_sz;
-extern unsigned int omap24xx_idle_loop_suspend_sz;
-
-#ifdef CONFIG_OMAP_SERIAL_WAKE
-extern void omap_serial_wake_trigger(int enable);
-#else
-#define omap_serial_wakeup_init()       {}
-#define omap_serial_wake_trigger(x)     {}
-#endif  /* CONFIG_OMAP_SERIAL_WAKE */
-
-#define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = omap_readl(x)
-#define ARM_RESTORE(x) omap_writel((arm_sleep_save[ARM_SLEEP_SAVE_##x]), (x))
-#define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x]
-
-#define DSP_SAVE(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x] = __raw_readw(x)
-#define DSP_RESTORE(x) __raw_writew((dsp_sleep_save[DSP_SLEEP_SAVE_##x]), (x))
-#define DSP_SHOW(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x]
-
-#define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = omap_readw(x)
-#define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x))
-#define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
-
-#define MPUI730_SAVE(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x] = omap_readl(x)
-#define MPUI730_RESTORE(x) omap_writel((mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]), (x))
-#define MPUI730_SHOW(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]
-
-#define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x)
-#define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x))
-#define MPUI1510_SHOW(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]
-
-#define MPUI1610_SAVE(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] = omap_readl(x)
-#define MPUI1610_RESTORE(x) omap_writel((mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]), (x))
-#define MPUI1610_SHOW(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]
-
-#define OMAP24XX_SAVE(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x] = x
-#define OMAP24XX_RESTORE(x) x = omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x]
-#define OMAP24XX_SHOW(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x]
-
-/*
- * List of global OMAP registers to preserve.
- * More ones like CP and general purpose register values are preserved
- * with the stack pointer in sleep.S.
- */
-
-enum arm_save_state {
-        ARM_SLEEP_SAVE_START = 0,
-        /*
-         * MPU control registers 32 bits
-         */
-        ARM_SLEEP_SAVE_ARM_CKCTL,
-        ARM_SLEEP_SAVE_ARM_IDLECT1,
-        ARM_SLEEP_SAVE_ARM_IDLECT2,
-        ARM_SLEEP_SAVE_ARM_IDLECT3,
-        ARM_SLEEP_SAVE_ARM_EWUPCT,
-        ARM_SLEEP_SAVE_ARM_RSTCT1,
-        ARM_SLEEP_SAVE_ARM_RSTCT2,
-        ARM_SLEEP_SAVE_ARM_SYSST,
-        ARM_SLEEP_SAVE_SIZE
-};
-
-enum dsp_save_state {
-        DSP_SLEEP_SAVE_START = 0,
-        /*
-         * DSP registers 16 bits
-         */
-        DSP_SLEEP_SAVE_DSP_IDLECT2,
-        DSP_SLEEP_SAVE_SIZE
-};
-
-enum ulpd_save_state {
-        ULPD_SLEEP_SAVE_START = 0,
-        /*
-         * ULPD registers 16 bits
-         */
-        ULPD_SLEEP_SAVE_ULPD_IT_STATUS,
-        ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL,
-        ULPD_SLEEP_SAVE_ULPD_SOFT_REQ,
-        ULPD_SLEEP_SAVE_ULPD_STATUS_REQ,
-        ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL,
-        ULPD_SLEEP_SAVE_ULPD_POWER_CTRL,
-        ULPD_SLEEP_SAVE_SIZE
-};
-
-enum mpui1510_save_state {
-        MPUI1510_SLEEP_SAVE_START = 0,
-        /*
-         * MPUI registers 32 bits
-         */
-        MPUI1510_SLEEP_SAVE_MPUI_CTRL,
-        MPUI1510_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
-        MPUI1510_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
-        MPUI1510_SLEEP_SAVE_MPUI_DSP_STATUS,
-        MPUI1510_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
-        MPUI1510_SLEEP_SAVE_EMIFS_CONFIG,
-        MPUI1510_SLEEP_SAVE_OMAP_IH1_MIR,
-        MPUI1510_SLEEP_SAVE_OMAP_IH2_MIR,
-#if defined(CONFIG_ARCH_OMAP15XX)
-        MPUI1510_SLEEP_SAVE_SIZE
-#else
-        MPUI1510_SLEEP_SAVE_SIZE = 0
-#endif
-};
-
-enum mpui730_save_state {
-        MPUI730_SLEEP_SAVE_START = 0,
-        /*
-         * MPUI registers 32 bits
-         */
-        MPUI730_SLEEP_SAVE_MPUI_CTRL,
-        MPUI730_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
-        MPUI730_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
-        MPUI730_SLEEP_SAVE_MPUI_DSP_STATUS,
-        MPUI730_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
-        MPUI730_SLEEP_SAVE_EMIFS_CONFIG,
-        MPUI730_SLEEP_SAVE_OMAP_IH1_MIR,
-        MPUI730_SLEEP_SAVE_OMAP_IH2_0_MIR,
-        MPUI730_SLEEP_SAVE_OMAP_IH2_1_MIR,
-#if defined(CONFIG_ARCH_OMAP730)
-        MPUI730_SLEEP_SAVE_SIZE
-#else
-        MPUI730_SLEEP_SAVE_SIZE = 0
-#endif
-};
-
-enum mpui1610_save_state {
-        MPUI1610_SLEEP_SAVE_START = 0,
-        /*
-         * MPUI registers 32 bits
-         */
-        MPUI1610_SLEEP_SAVE_MPUI_CTRL,
-        MPUI1610_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
-        MPUI1610_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
-        MPUI1610_SLEEP_SAVE_MPUI_DSP_STATUS,
-        MPUI1610_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
-        MPUI1610_SLEEP_SAVE_EMIFS_CONFIG,
-        MPUI1610_SLEEP_SAVE_OMAP_IH1_MIR,
-        MPUI1610_SLEEP_SAVE_OMAP_IH2_0_MIR,
-        MPUI1610_SLEEP_SAVE_OMAP_IH2_1_MIR,
-        MPUI1610_SLEEP_SAVE_OMAP_IH2_2_MIR,
-        MPUI1610_SLEEP_SAVE_OMAP_IH2_3_MIR,
-#if defined(CONFIG_ARCH_OMAP16XX)
-        MPUI1610_SLEEP_SAVE_SIZE
-#else
-        MPUI1610_SLEEP_SAVE_SIZE = 0
-#endif
-};
-
-enum omap24xx_save_state {
-        OMAP24XX_SLEEP_SAVE_START = 0,
-        OMAP24XX_SLEEP_SAVE_INTC_MIR0,
-        OMAP24XX_SLEEP_SAVE_INTC_MIR1,
-        OMAP24XX_SLEEP_SAVE_INTC_MIR2,
-
-        OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_MPU,
-        OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_CORE,
-        OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_GFX,
-        OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_DSP,
-        OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_MDM,
-
-        OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_MPU,
-        OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_CORE,
-        OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_GFX,
-        OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_DSP,
-        OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_MDM,
-
-        OMAP24XX_SLEEP_SAVE_CM_IDLEST1_CORE,
-        OMAP24XX_SLEEP_SAVE_CM_IDLEST2_CORE,
-        OMAP24XX_SLEEP_SAVE_CM_IDLEST3_CORE,
-        OMAP24XX_SLEEP_SAVE_CM_IDLEST4_CORE,
-        OMAP24XX_SLEEP_SAVE_CM_IDLEST_GFX,
-        OMAP24XX_SLEEP_SAVE_CM_IDLEST_WKUP,
-        OMAP24XX_SLEEP_SAVE_CM_IDLEST_CKGEN,
-        OMAP24XX_SLEEP_SAVE_CM_IDLEST_DSP,
-        OMAP24XX_SLEEP_SAVE_CM_IDLEST_MDM,
-
-        OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE1_CORE,
-        OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE2_CORE,
-        OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE3_CORE,
-        OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE4_CORE,
-        OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_WKUP,
-        OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_PLL,
-        OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_DSP,
-        OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_MDM,
-
-        OMAP24XX_SLEEP_SAVE_CM_FCLKEN1_CORE,
-        OMAP24XX_SLEEP_SAVE_CM_FCLKEN2_CORE,
-        OMAP24XX_SLEEP_SAVE_CM_ICLKEN1_CORE,
-        OMAP24XX_SLEEP_SAVE_CM_ICLKEN2_CORE,
-        OMAP24XX_SLEEP_SAVE_CM_ICLKEN3_CORE,
-        OMAP24XX_SLEEP_SAVE_CM_ICLKEN4_CORE,
-        OMAP24XX_SLEEP_SAVE_GPIO1_IRQENABLE1,
-        OMAP24XX_SLEEP_SAVE_GPIO2_IRQENABLE1,
-        OMAP24XX_SLEEP_SAVE_GPIO3_IRQENABLE1,
-        OMAP24XX_SLEEP_SAVE_GPIO4_IRQENABLE1,
-        OMAP24XX_SLEEP_SAVE_GPIO3_OE,
-        OMAP24XX_SLEEP_SAVE_GPIO4_OE,
-        OMAP24XX_SLEEP_SAVE_GPIO3_RISINGDETECT,
-        OMAP24XX_SLEEP_SAVE_GPIO3_FALLINGDETECT,
-        OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SPI1_NCS2,
-        OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_MCBSP1_DX,
-        OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SSI1_FLAG_TX,
-        OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SYS_NIRQW0,
-        OMAP24XX_SLEEP_SAVE_SIZE
-};
-
-#endif /* ASSEMBLER */
-#endif /* __ASM_ARCH_OMAP_PM_H */
diff --git a/include/asm-arm/arch-omap/prcm.h b/include/asm-arm/arch-omap/prcm.h
deleted file mode 100644
index 7bcaf94bde9f..000000000000
--- a/include/asm-arm/arch-omap/prcm.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/prcm.h
- *
- * Access definations for use in OMAP24XX clock and power management
- *
- * Copyright (C) 2005 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARM_ARCH_DPM_PRCM_H
-#define __ASM_ARM_ARCH_DPM_PRCM_H
-
-u32 omap_prcm_get_reset_sources(void);
-
-#endif
-
-
-
-
-
diff --git a/include/asm-arm/arch-omap/sdrc.h b/include/asm-arm/arch-omap/sdrc.h
deleted file mode 100644
index 673b3965befc..000000000000
--- a/include/asm-arm/arch-omap/sdrc.h
+++ /dev/null
@@ -1,75 +0,0 @@
-#ifndef ____ASM_ARCH_SDRC_H
-#define ____ASM_ARCH_SDRC_H
-
-/*
- * OMAP2/3 SDRC/SMS register definitions
- *
- * Copyright (C) 2007 Texas Instruments, Inc.
- * Copyright (C) 2007 Nokia Corporation
- *
- * Written by Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <asm/arch/io.h>
-
-/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
-
-#define SDRC_SYSCONFIG          0x010
-#define SDRC_DLLA_CTRL          0x060
-#define SDRC_DLLA_STATUS        0x064
-#define SDRC_DLLB_CTRL          0x068
-#define SDRC_DLLB_STATUS        0x06C
-#define SDRC_POWER              0x070
-#define SDRC_MR_0               0x084
-#define SDRC_RFR_CTRL_0         0x0a4
-
-/*
- * These values represent the number of memory clock cycles between
- * autorefresh initiation.  They assume 1 refresh per 64 ms (JEDEC), 8192
- * rows per device, and include a subtraction of a 50 cycle window in the
- * event that the autorefresh command is delayed due to other SDRC activity.
- * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
- * counter reaches 0.
- *
- * These represent optimal values for common parts, it won't work for all.
- * As long as you scale down, most parameters are still work, they just
- * become sub-optimal. The RFR value goes in the opposite direction. If you
- * don't adjust it down as your clock period increases the refresh interval
- * will not be met. Setting all parameters for complete worst case may work,
- * but may cut memory performance by 2x. Due to errata the DLLs need to be
- * unlocked and their value needs run time calibration. A dynamic call is
- * need for that as no single right value exists acorss production samples.
- *
- * Only the FULL speed values are given. Current code is such that rate
- * changes must be made at DPLLoutx2. The actual value adjustment for low
- * frequency operation will be handled by omap_set_performance()
- *
- * By having the boot loader boot up in the fastest L4 speed available likely
- * will result in something which you can switch between.
- */
-#define SDRC_RFR_CTRL_165MHz    (0x00044c00 | 1)
-#define SDRC_RFR_CTRL_133MHz    (0x0003de00 | 1)
-#define SDRC_RFR_CTRL_100MHz    (0x0002da01 | 1)
-#define SDRC_RFR_CTRL_110MHz    (0x0002da01 | 1) /* Need to calc */
-#define SDRC_RFR_CTRL_BYPASS    (0x00005000 | 1) /* Need to calc */
-
-
-/*
- * SMS register access
- */
-
-
-#define OMAP242X_SMS_REGADDR(reg)       (void __iomem *)IO_ADDRESS(OMAP2420_SMS_BASE + reg)
-#define OMAP243X_SMS_REGADDR(reg)       (void __iomem *)IO_ADDRESS(OMAP243X_SMS_BASE + reg)
-#define OMAP343X_SMS_REGADDR(reg)       (void __iomem *)IO_ADDRESS(OMAP343X_SMS_BASE + reg)
-
-/* SMS register offsets - read/write with sms_{read,write}_reg() */
-
-#define SMS_SYSCONFIG           0x010
-/* REVISIT: fill in other SMS registers here */
-
-#endif
diff --git a/include/asm-arm/arch-omap/serial.h b/include/asm-arm/arch-omap/serial.h
deleted file mode 100644
index 79a5297af9fc..000000000000
--- a/include/asm-arm/arch-omap/serial.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-omap/serial.h
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ASM_ARCH_SERIAL_H
-#define __ASM_ARCH_SERIAL_H
-
-#if defined(CONFIG_ARCH_OMAP1)
-/* OMAP1 serial ports */
-#define OMAP_UART1_BASE         0xfffb0000
-#define OMAP_UART2_BASE         0xfffb0800
-#define OMAP_UART3_BASE         0xfffb9800
-#elif defined(CONFIG_ARCH_OMAP2)
-/* OMAP2 serial ports */
-#define OMAP_UART1_BASE         0x4806a000
-#define OMAP_UART2_BASE         0x4806c000
-#define OMAP_UART3_BASE         0x4806e000
-#endif
-
-#define OMAP_MAX_NR_PORTS       3
-#define OMAP1510_BASE_BAUD      (12000000/16)
-#define OMAP16XX_BASE_BAUD      (48000000/16)
-
-#define is_omap_port(p) ({int __ret = 0;                        \
-                        if (p == IO_ADDRESS(OMAP_UART1_BASE) || \
-                            p == IO_ADDRESS(OMAP_UART2_BASE) || \
-                            p == IO_ADDRESS(OMAP_UART3_BASE))   \
-                                __ret = 1;                      \
-                        __ret;                                  \
-                        })
-
-#endif
diff --git a/include/asm-arm/arch-omap/sram.h b/include/asm-arm/arch-omap/sram.h
deleted file mode 100644
index be59f4a9828b..000000000000
--- a/include/asm-arm/arch-omap/sram.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/sram.h
- *
- * Interface for functions that need to be run in internal SRAM
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ARCH_ARM_OMAP_SRAM_H
-#define __ARCH_ARM_OMAP_SRAM_H
-
-extern int __init omap_sram_init(void);
-extern void * omap_sram_push(void * start, unsigned long size);
-extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
-
-extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
-                                u32 base_cs, u32 force_unlock);
-extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
-                                      u32 mem_type);
-extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
-
-/* Do not use these */
-extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
-extern unsigned long omap1_sram_reprogram_clock_sz;
-
-extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
-extern unsigned long omap24xx_sram_reprogram_clock_sz;
-
-extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
-                                                u32 base_cs, u32 force_unlock);
-extern unsigned long omap242x_sram_ddr_init_sz;
-
-extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
-                                                int bypass);
-extern unsigned long omap242x_sram_set_prcm_sz;
-
-extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
-                                                u32 mem_type);
-extern unsigned long omap242x_sram_reprogram_sdrc_sz;
-
-
-extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
-                                                u32 base_cs, u32 force_unlock);
-extern unsigned long omap243x_sram_ddr_init_sz;
-
-extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
-                                                int bypass);
-extern unsigned long omap243x_sram_set_prcm_sz;
-
-extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
-                                                u32 mem_type);
-extern unsigned long omap243x_sram_reprogram_sdrc_sz;
-
-#endif
diff --git a/include/asm-arm/arch-omap/system.h b/include/asm-arm/arch-omap/system.h
deleted file mode 100644
index 176d9d6c258e..000000000000
--- a/include/asm-arm/arch-omap/system.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copied from linux/include/asm-arm/arch-sa1100/system.h
- * Copyright (c) 1999 Nicolas Pitre <nico@cam.org>
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-#include <linux/clk.h>
-
-#include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
-
-#ifndef CONFIG_MACH_VOICEBLUE
-#define voiceblue_reset()               do {} while (0)
-#endif
-
-extern void omap_prcm_arch_reset(char mode);
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-static inline void omap1_arch_reset(char mode)
-{
-        /*
-         * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
-         * "Global Software Reset Affects Traffic Controller Frequency".
-         */
-        if (cpu_is_omap5912()) {
-                omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4),
-                                 DPLL_CTL);
-                omap_writew(0x8, ARM_RSTCT1);
-        }
-
-        if (machine_is_voiceblue())
-                voiceblue_reset();
-        else
-                omap_writew(1, ARM_RSTCT1);
-}
-
-static inline void arch_reset(char mode)
-{
-        if (!cpu_is_omap24xx())
-                omap1_arch_reset(mode);
-        else
-                omap_prcm_arch_reset(mode);
-}
-
-#endif
diff --git a/include/asm-arm/arch-omap/tc.h b/include/asm-arm/arch-omap/tc.h
deleted file mode 100644
index 65a9c82d3bf7..000000000000
--- a/include/asm-arm/arch-omap/tc.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/tc.h
- *
- * OMAP Traffic Controller
- *
- * Copyright (C) 2004 Nokia Corporation
- * Author: Imre Deak <imre.deak@nokia.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
- */
-
-#ifndef __ASM_ARCH_TC_H
-#define __ASM_ARCH_TC_H
-
-#define TCMIF_BASE              0xfffecc00
-#define OMAP_TC_OCPT1_PRIOR     (TCMIF_BASE + 0x00)
-#define OMAP_TC_EMIFS_PRIOR     (TCMIF_BASE + 0x04)
-#define OMAP_TC_EMIFF_PRIOR     (TCMIF_BASE + 0x08)
-#define EMIFS_CONFIG            (TCMIF_BASE + 0x0c)
-#define EMIFS_CS0_CONFIG        (TCMIF_BASE + 0x10)
-#define EMIFS_CS1_CONFIG        (TCMIF_BASE + 0x14)
-#define EMIFS_CS2_CONFIG        (TCMIF_BASE + 0x18)
-#define EMIFS_CS3_CONFIG        (TCMIF_BASE + 0x1c)
-#define EMIFF_SDRAM_CONFIG      (TCMIF_BASE + 0x20)
-#define EMIFF_MRS               (TCMIF_BASE + 0x24)
-#define TC_TIMEOUT1             (TCMIF_BASE + 0x28)
-#define TC_TIMEOUT2             (TCMIF_BASE + 0x2c)
-#define TC_TIMEOUT3             (TCMIF_BASE + 0x30)
-#define TC_ENDIANISM            (TCMIF_BASE + 0x34)
-#define EMIFF_SDRAM_CONFIG_2    (TCMIF_BASE + 0x3c)
-#define EMIF_CFG_DYNAMIC_WS     (TCMIF_BASE + 0x40)
-#define EMIFS_ACS0              (TCMIF_BASE + 0x50)
-#define EMIFS_ACS1              (TCMIF_BASE + 0x54)
-#define EMIFS_ACS2              (TCMIF_BASE + 0x58)
-#define EMIFS_ACS3              (TCMIF_BASE + 0x5c)
-#define OMAP_TC_OCPT2_PRIOR     (TCMIF_BASE + 0xd0)
-
-/* external EMIFS chipselect regions */
-#define OMAP_CS0_PHYS           0x00000000
-#define OMAP_CS0_SIZE           SZ_64M
-
-#define OMAP_CS1_PHYS           0x04000000
-#define OMAP_CS1_SIZE           SZ_64M
-
-#define OMAP_CS1A_PHYS          OMAP_CS1_PHYS
-#define OMAP_CS1A_SIZE          SZ_32M
-
-#define OMAP_CS1B_PHYS          (OMAP_CS1A_PHYS + OMAP_CS1A_SIZE)
-#define OMAP_CS1B_SIZE          SZ_32M
-
-#define OMAP_CS2_PHYS           0x08000000
-#define OMAP_CS2_SIZE           SZ_64M
-
-#define OMAP_CS2A_PHYS          OMAP_CS2_PHYS
-#define OMAP_CS2A_SIZE          SZ_32M
-
-#define OMAP_CS2B_PHYS          (OMAP_CS2A_PHYS + OMAP_CS2A_SIZE)
-#define OMAP_CS2B_SIZE          SZ_32M
-
-#define OMAP_CS3_PHYS           0x0c000000
-#define OMAP_CS3_SIZE           SZ_64M
-
-#ifndef __ASSEMBLER__
-
-/* EMIF Slow Interface Configuration Register */
-#define OMAP_EMIFS_CONFIG_FR            (1 << 4)
-#define OMAP_EMIFS_CONFIG_PDE           (1 << 3)
-#define OMAP_EMIFS_CONFIG_PWD_EN        (1 << 2)
-#define OMAP_EMIFS_CONFIG_BM            (1 << 1)
-#define OMAP_EMIFS_CONFIG_WP            (1 << 0)
-
-#define EMIFS_CCS(n)            (EMIFS_CS0_CONFIG + (4 * (n)))
-#define EMIFS_ACS(n)            (EMIFS_ACS0 + (4 * (n)))
-
-/* Almost all documentation for chip and board memory maps assumes
- * BM is clear.  Most devel boards have a switch to control booting
- * from NOR flash (using external chipselect 3) rather than mask ROM,
- * which uses BM to interchange the physical CS0 and CS3 addresses.
- */
-static inline u32 omap_cs0_phys(void)
-{
-        return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
-                        ?  OMAP_CS3_PHYS : 0;
-}
-
-static inline u32 omap_cs3_phys(void)
-{
-        return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
-                        ? 0 : OMAP_CS3_PHYS;
-}
-
-#endif  /* __ASSEMBLER__ */
-
-#endif  /* __ASM_ARCH_TC_H */
diff --git a/include/asm-arm/arch-omap/timex.h b/include/asm-arm/arch-omap/timex.h
deleted file mode 100644
index 21f2e367185a..000000000000
--- a/include/asm-arm/arch-omap/timex.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/timex.h
- *
- * Copyright (C) 2000 RidgeRun, Inc.
- * Author:  Greg Lonnon <glonnon@ridgerun.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the  GNU General Public License along
- * with this program; if not, write  to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#if !defined(__ASM_ARCH_OMAP_TIMEX_H)
-#define __ASM_ARCH_OMAP_TIMEX_H
-
-/*
- * OMAP 32KHz timer updates time one jiffie at a time from a secondary timer,
- * and that's why the CLOCK_TICK_RATE is not 32768.
- */
-#ifdef CONFIG_OMAP_32K_TIMER
-#define CLOCK_TICK_RATE         (CONFIG_OMAP_32K_TIMER_HZ)
-#else
-#define CLOCK_TICK_RATE         (HZ * 100000UL)
-#endif
-
-#endif /* __ASM_ARCH_OMAP_TIMEX_H */
diff --git a/include/asm-arm/arch-omap/uncompress.h b/include/asm-arm/arch-omap/uncompress.h
deleted file mode 100644
index aca0adfef1b8..000000000000
--- a/include/asm-arm/arch-omap/uncompress.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/uncompress.h
- *
- * Serial port stubs for kernel decompress status messages
- *
- * Initially based on:
- * linux-2.4.15-rmk1-dsplinux1.6/include/asm-arm/arch-omap1510/uncompress.h
- * Copyright (C) 2000 RidgeRun, Inc.
- * Author: Greg Lonnon <glonnon@ridgerun.com>
- *
- * Rewritten by:
- * Author: <source@mvista.com>
- * 2004 (c) MontaVista Software, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <linux/types.h>
-#include <linux/serial_reg.h>
-#include <asm/arch/serial.h>
-
-unsigned int system_rev;
-
-#define UART_OMAP_MDR1          0x08    /* mode definition register */
-#define OMAP_ID_730             0x355F
-#define ID_MASK                 0x7fff
-#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0)
-#define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK
-
-static void putc(int c)
-{
-        volatile u8 * uart = 0;
-        int shift = 2;
-
-#ifdef CONFIG_MACH_OMAP_PALMTE
-        return;
-#endif
-
-#ifdef CONFIG_ARCH_OMAP
-#ifdef  CONFIG_OMAP_LL_DEBUG_UART3
-        uart = (volatile u8 *)(OMAP_UART3_BASE);
-#elif defined(CONFIG_OMAP_LL_DEBUG_UART2)
-        uart = (volatile u8 *)(OMAP_UART2_BASE);
-#else
-        uart = (volatile u8 *)(OMAP_UART1_BASE);
-#endif
-
-#ifdef CONFIG_ARCH_OMAP1
-        /* Determine which serial port to use */
-        do {
-                /* MMU is not on, so cpu_is_omapXXXX() won't work here */
-                unsigned int omap_id = omap_get_id();
-
-                if (omap_id == OMAP_ID_730)
-                        shift = 0;
-
-                if (check_port(uart, shift))
-                        break;
-                /* Silent boot if no serial ports are enabled. */
-                return;
-        } while (0);
-#endif /* CONFIG_ARCH_OMAP1 */
-#endif
-
-        /*
-         * Now, xmit each character
-         */
-        while (!(uart[UART_LSR << shift] & UART_LSR_THRE))
-                barrier();
-        uart[UART_TX << shift] = c;
-}
-
-static inline void flush(void)
-{
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-omap/usb.h b/include/asm-arm/arch-omap/usb.h
deleted file mode 100644
index ddf1861e6df9..000000000000
--- a/include/asm-arm/arch-omap/usb.h
+++ /dev/null
@@ -1,141 +0,0 @@
-// include/asm-arm/mach-omap/usb.h
-
-#ifndef __ASM_ARCH_OMAP_USB_H
-#define __ASM_ARCH_OMAP_USB_H
-
-#include <asm/arch/board.h>
-
-/*-------------------------------------------------------------------------*/
-
-#define OMAP1_OTG_BASE                  0xfffb0400
-#define OMAP1_UDC_BASE                  0xfffb4000
-#define OMAP1_OHCI_BASE                 0xfffba000
-
-#define OMAP2_OHCI_BASE                 0x4805e000
-#define OMAP2_UDC_BASE                  0x4805e200
-#define OMAP2_OTG_BASE                  0x4805e300
-
-#ifdef CONFIG_ARCH_OMAP1
-
-#define OTG_BASE                        OMAP1_OTG_BASE
-#define UDC_BASE                        OMAP1_UDC_BASE
-#define OMAP_OHCI_BASE                  OMAP1_OHCI_BASE
-
-#else
-
-#define OTG_BASE                        OMAP2_OTG_BASE
-#define UDC_BASE                        OMAP2_UDC_BASE
-#define OMAP_OHCI_BASE                  OMAP2_OHCI_BASE
-
-#endif
-
-/*-------------------------------------------------------------------------*/
-
-/*
- * OTG and transceiver registers, for OMAPs starting with ARM926
- */
-#define OTG_REV                         (OTG_BASE + 0x00)
-#define OTG_SYSCON_1                    (OTG_BASE + 0x04)
-#       define   USB2_TRX_MODE(w)       (((w)>>24)&0x07)
-#       define   USB1_TRX_MODE(w)       (((w)>>20)&0x07)
-#       define   USB0_TRX_MODE(w)       (((w)>>16)&0x07)
-#       define   OTG_IDLE_EN            (1 << 15)
-#       define   HST_IDLE_EN            (1 << 14)
-#       define   DEV_IDLE_EN            (1 << 13)
-#       define   OTG_RESET_DONE         (1 << 2)
-#       define   OTG_SOFT_RESET         (1 << 1)
-#define OTG_SYSCON_2                    (OTG_BASE + 0x08)
-#       define   OTG_EN                 (1 << 31)
-#       define   USBX_SYNCHRO           (1 << 30)
-#       define   OTG_MST16              (1 << 29)
-#       define   SRP_GPDATA             (1 << 28)
-#       define   SRP_GPDVBUS            (1 << 27)
-#       define   SRP_GPUVBUS(w)         (((w)>>24)&0x07)
-#       define   A_WAIT_VRISE(w)        (((w)>>20)&0x07)
-#       define   B_ASE_BRST(w)          (((w)>>16)&0x07)
-#       define   SRP_DPW                (1 << 14)
-#       define   SRP_DATA               (1 << 13)
-#       define   SRP_VBUS               (1 << 12)
-#       define   OTG_PADEN              (1 << 10)
-#       define   HMC_PADEN              (1 << 9)
-#       define   UHOST_EN               (1 << 8)
-#       define   HMC_TLLSPEED           (1 << 7)
-#       define   HMC_TLLATTACH          (1 << 6)
-#       define   OTG_HMC(w)             (((w)>>0)&0x3f)
-#define OTG_CTRL                        (OTG_BASE + 0x0c)
-#       define   OTG_USB2_EN            (1 << 29)
-#       define   OTG_USB2_DP            (1 << 28)
-#       define   OTG_USB2_DM            (1 << 27)
-#       define   OTG_USB1_EN            (1 << 26)
-#       define   OTG_USB1_DP            (1 << 25)
-#       define   OTG_USB1_DM            (1 << 24)
-#       define   OTG_USB0_EN            (1 << 23)
-#       define   OTG_USB0_DP            (1 << 22)
-#       define   OTG_USB0_DM            (1 << 21)
-#       define   OTG_ASESSVLD           (1 << 20)
-#       define   OTG_BSESSEND           (1 << 19)
-#       define   OTG_BSESSVLD           (1 << 18)
-#       define   OTG_VBUSVLD            (1 << 17)
-#       define   OTG_ID                 (1 << 16)
-#       define   OTG_DRIVER_SEL         (1 << 15)
-#       define   OTG_A_SETB_HNPEN       (1 << 12)
-#       define   OTG_A_BUSREQ           (1 << 11)
-#       define   OTG_B_HNPEN            (1 << 9)
-#       define   OTG_B_BUSREQ           (1 << 8)
-#       define   OTG_BUSDROP            (1 << 7)
-#       define   OTG_PULLDOWN           (1 << 5)
-#       define   OTG_PULLUP             (1 << 4)
-#       define   OTG_DRV_VBUS           (1 << 3)
-#       define   OTG_PD_VBUS            (1 << 2)
-#       define   OTG_PU_VBUS            (1 << 1)
-#       define   OTG_PU_ID              (1 << 0)
-#define OTG_IRQ_EN                      (OTG_BASE + 0x10)       /* 16-bit */
-#       define   DRIVER_SWITCH          (1 << 15)
-#       define   A_VBUS_ERR             (1 << 13)
-#       define   A_REQ_TMROUT           (1 << 12)
-#       define   A_SRP_DETECT           (1 << 11)
-#       define   B_HNP_FAIL             (1 << 10)
-#       define   B_SRP_TMROUT           (1 << 9)
-#       define   B_SRP_DONE             (1 << 8)
-#       define   B_SRP_STARTED          (1 << 7)
-#       define   OPRT_CHG               (1 << 0)
-#define OTG_IRQ_SRC                     (OTG_BASE + 0x14)       /* 16-bit */
-        // same bits as in IRQ_EN
-#define OTG_OUTCTRL                     (OTG_BASE + 0x18)       /* 16-bit */
-#       define   OTGVPD                 (1 << 14)
-#       define   OTGVPU                 (1 << 13)
-#       define   OTGPUID                (1 << 12)
-#       define   USB2VDR                (1 << 10)
-#       define   USB2PDEN               (1 << 9)
-#       define   USB2PUEN               (1 << 8)
-#       define   USB1VDR                (1 << 6)
-#       define   USB1PDEN               (1 << 5)
-#       define   USB1PUEN               (1 << 4)
-#       define   USB0VDR                (1 << 2)
-#       define   USB0PDEN               (1 << 1)
-#       define   USB0PUEN               (1 << 0)
-#define OTG_TEST                        (OTG_BASE + 0x20)       /* 16-bit */
-#define OTG_VENDOR_CODE                 (OTG_BASE + 0xfc)       /* 16-bit */
-
-/*-------------------------------------------------------------------------*/
-
-/* OMAP1 */
-#define USB_TRANSCEIVER_CTRL            (0xfffe1000 + 0x0064)
-#       define  CONF_USB2_UNI_R         (1 << 8)
-#       define  CONF_USB1_UNI_R         (1 << 7)
-#       define  CONF_USB_PORT0_R(x)     (((x)>>4)&0x7)
-#       define  CONF_USB0_ISOLATE_R     (1 << 3)
-#       define  CONF_USB_PWRDN_DM_R     (1 << 2)
-#       define  CONF_USB_PWRDN_DP_R     (1 << 1)
-
-/* OMAP2 */
-#       define  USB_UNIDIR                      0x0
-#       define  USB_UNIDIR_TLL                  0x1
-#       define  USB_BIDIR                       0x2
-#       define  USB_BIDIR_TLL                   0x3
-#       define  USBTXWRMODEI(port, x)   ((x) << (22 - (port * 2)))
-#       define  USBT2TLL5PI             (1 << 17)
-#       define  USB0PUENACTLOI          (1 << 16)
-#       define  USBSTANDBYCTRL          (1 << 15)
-
-#endif  /* __ASM_ARCH_OMAP_USB_H */
diff --git a/include/asm-arm/arch-omap/vmalloc.h b/include/asm-arm/arch-omap/vmalloc.h
deleted file mode 100644
index 5b8bd8dae8be..000000000000
--- a/include/asm-arm/arch-omap/vmalloc.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-omap/vmalloc.h
- *
- *  Copyright (C) 2000 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
-
diff --git a/include/asm-arm/arch-orion5x/debug-macro.S b/include/asm-arm/arch-orion5x/debug-macro.S
deleted file mode 100644
index 4f98f3ba2929..000000000000
--- a/include/asm-arm/arch-orion5x/debug-macro.S
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * include/asm-arm/arch-orion5x/debug-macro.S
- *
- * Debugging macro include header
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <asm/arch/orion5x.h>
-
-        .macro  addruart,rx
-        mrc     p15, 0, \rx, c1, c0
-        tst     \rx, #1                                 @ MMU enabled?
-        ldreq   \rx, =ORION5X_REGS_PHYS_BASE
-        ldrne   \rx, =ORION5X_REGS_VIRT_BASE
-        orr     \rx, \rx, #0x00012000
-        .endm
-
-#define UART_SHIFT      2
-#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-orion5x/entry-macro.S b/include/asm-arm/arch-orion5x/entry-macro.S
deleted file mode 100644
index d8ef54c0ee9a..000000000000
--- a/include/asm-arm/arch-orion5x/entry-macro.S
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * include/asm-arm/arch-orion5x/entry-macro.S
- *
- * Low-level IRQ helper macros for Orion platforms
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/arch/orion5x.h>
-
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
-        .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =MAIN_IRQ_CAUSE
-        .endm
-
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        ldr     \irqstat, [\base, #0]           @ main cause
-        ldr     \tmp, [\base, #(MAIN_IRQ_MASK - MAIN_IRQ_CAUSE)] @ main mask
-        mov     \irqnr, #0                      @ default irqnr
-        @ find cause bits that are unmasked
-        ands    \irqstat, \irqstat, \tmp        @ clear Z flag if any
-        clzne   \irqnr, \irqstat                @ calc irqnr
-        rsbne   \irqnr, \irqnr, #31
-        .endm
diff --git a/include/asm-arm/arch-orion5x/gpio.h b/include/asm-arm/arch-orion5x/gpio.h
deleted file mode 100644
index c85e498388b6..000000000000
--- a/include/asm-arm/arch-orion5x/gpio.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * include/asm-arm/arch-orion5x/gpio.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-extern int gpio_request(unsigned pin, const char *label);
-extern void gpio_free(unsigned pin);
-extern int gpio_direction_input(unsigned pin);
-extern int gpio_direction_output(unsigned pin, int value);
-extern int gpio_get_value(unsigned pin);
-extern void gpio_set_value(unsigned pin, int value);
-extern void orion5x_gpio_set_blink(unsigned pin, int blink);
-extern void gpio_display(void);         /* debug */
-
-static inline int gpio_to_irq(int pin)
-{
-        return pin + IRQ_ORION5X_GPIO_START;
-}
-
-static inline int irq_to_gpio(int irq)
-{
-        return irq - IRQ_ORION5X_GPIO_START;
-}
-
-#include <asm-generic/gpio.h>           /* cansleep wrappers */
diff --git a/include/asm-arm/arch-orion5x/hardware.h b/include/asm-arm/arch-orion5x/hardware.h
deleted file mode 100644
index 5d2d8e0b5630..000000000000
--- a/include/asm-arm/arch-orion5x/hardware.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * include/asm-arm/arch-orion5x/hardware.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include "orion5x.h"
-
-#define pcibios_assign_all_busses()     1
-
-#define PCIBIOS_MIN_IO          0x00001000
-#define PCIBIOS_MIN_MEM         0x01000000
-#define PCIMEM_BASE             ORION5X_PCIE_MEM_PHYS_BASE
-
-
-#endif
diff --git a/include/asm-arm/arch-orion5x/io.h b/include/asm-arm/arch-orion5x/io.h
deleted file mode 100644
index 59f1bc96a23b..000000000000
--- a/include/asm-arm/arch-orion5x/io.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * include/asm-arm/arch-orion5x/io.h
- *
- * Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#include "orion5x.h"
-
-#define IO_SPACE_LIMIT          0xffffffff
-
-static inline void __iomem *
-__arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype)
-{
-        void __iomem *retval;
-        unsigned long offs = paddr - ORION5X_REGS_PHYS_BASE;
-        if (mtype == MT_DEVICE && size && offs < ORION5X_REGS_SIZE &&
-            size <= ORION5X_REGS_SIZE && offs + size <= ORION5X_REGS_SIZE) {
-                retval = (void __iomem *)ORION5X_REGS_VIRT_BASE + offs;
-        } else {
-                retval = __arm_ioremap(paddr, size, mtype);
-        }
-
-        return retval;
-}
-
-static inline void
-__arch_iounmap(void __iomem *addr)
-{
-        if (addr < (void __iomem *)ORION5X_REGS_VIRT_BASE ||
-            addr >= (void __iomem *)(ORION5X_REGS_VIRT_BASE + ORION5X_REGS_SIZE))
-                __iounmap(addr);
-}
-
-static inline void __iomem *__io(unsigned long addr)
-{
-        return (void __iomem *)addr;
-}
-
-#define __arch_ioremap(p, s, m) __arch_ioremap(p, s, m)
-#define __arch_iounmap(a)       __arch_iounmap(a)
-#define __io(a)                 __io(a)
-#define __mem_pci(a)            (a)
-
-
-/*****************************************************************************
- * Helpers to access Orion registers
- ****************************************************************************/
-/*
- * These are not preempt-safe.  Locks, if needed, must be taken
- * care of by the caller.
- */
-#define orion5x_setbits(r, mask)        writel(readl(r) | (mask), (r))
-#define orion5x_clrbits(r, mask)        writel(readl(r) & ~(mask), (r))
-
-
-#endif
diff --git a/include/asm-arm/arch-orion5x/irqs.h b/include/asm-arm/arch-orion5x/irqs.h
deleted file mode 100644
index abdd61a4833a..000000000000
--- a/include/asm-arm/arch-orion5x/irqs.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * include/asm-arm/arch-orion5x/irqs.h
- *
- * IRQ definitions for Orion SoC
- *
- *  Maintainer: Tzachi Perelstein <tzachi@marvell.com>
- *
- *  This file is licensed under the terms of the GNU General Public
- *  License version 2. This program is licensed "as is" without any
- *  warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H
-
-#include "orion5x.h"    /* need GPIO_MAX */
-
-/*
- * Orion Main Interrupt Controller
- */
-#define IRQ_ORION5X_BRIDGE              0
-#define IRQ_ORION5X_DOORBELL_H2C        1
-#define IRQ_ORION5X_DOORBELL_C2H        2
-#define IRQ_ORION5X_UART0               3
-#define IRQ_ORION5X_UART1               4
-#define IRQ_ORION5X_I2C                 5
-#define IRQ_ORION5X_GPIO_0_7            6
-#define IRQ_ORION5X_GPIO_8_15           7
-#define IRQ_ORION5X_GPIO_16_23          8
-#define IRQ_ORION5X_GPIO_24_31          9
-#define IRQ_ORION5X_PCIE0_ERR           10
-#define IRQ_ORION5X_PCIE0_INT           11
-#define IRQ_ORION5X_USB1_CTRL           12
-#define IRQ_ORION5X_DEV_BUS_ERR         14
-#define IRQ_ORION5X_PCI_ERR             15
-#define IRQ_ORION5X_USB_BR_ERR          16
-#define IRQ_ORION5X_USB0_CTRL           17
-#define IRQ_ORION5X_ETH_RX              18
-#define IRQ_ORION5X_ETH_TX              19
-#define IRQ_ORION5X_ETH_MISC            20
-#define IRQ_ORION5X_ETH_SUM             21
-#define IRQ_ORION5X_ETH_ERR             22
-#define IRQ_ORION5X_IDMA_ERR            23
-#define IRQ_ORION5X_IDMA_0              24
-#define IRQ_ORION5X_IDMA_1              25
-#define IRQ_ORION5X_IDMA_2              26
-#define IRQ_ORION5X_IDMA_3              27
-#define IRQ_ORION5X_CESA                28
-#define IRQ_ORION5X_SATA                29
-#define IRQ_ORION5X_XOR0                30
-#define IRQ_ORION5X_XOR1                31
-
-/*
- * Orion General Purpose Pins
- */
-#define IRQ_ORION5X_GPIO_START  32
-#define NR_GPIO_IRQS            GPIO_MAX
-
-#define NR_IRQS                 (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS)
-
-
-#endif
diff --git a/include/asm-arm/arch-orion5x/memory.h b/include/asm-arm/arch-orion5x/memory.h
deleted file mode 100644
index 80053a7afc7a..000000000000
--- a/include/asm-arm/arch-orion5x/memory.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * include/asm-arm/arch-orion5x/memory.h
- *
- * Marvell Orion memory definitions
- */
-
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-#define PHYS_OFFSET     UL(0x00000000)
-
-#define __virt_to_bus(x)        __virt_to_phys(x)
-#define __bus_to_virt(x)        __phys_to_virt(x)
-
-
-#endif
diff --git a/include/asm-arm/arch-orion5x/orion5x.h b/include/asm-arm/arch-orion5x/orion5x.h
deleted file mode 100644
index 10257f5c5e9e..000000000000
--- a/include/asm-arm/arch-orion5x/orion5x.h
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * include/asm-arm/arch-orion5x/orion5x.h
- *
- * Generic definitions of Orion SoC flavors:
- *  Orion-1, Orion-VoIP, Orion-NAS, and Orion-2.
- *
- * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_ORION5X_H
-#define __ASM_ARCH_ORION5X_H
-
-/*****************************************************************************
- * Orion Address Maps
- *
- * phys
- * e0000000     PCIe MEM space
- * e8000000     PCI MEM space
- * f0000000     PCIe WA space (Orion-1/Orion-NAS only)
- * f1000000     on-chip peripheral registers
- * f2000000     PCIe I/O space
- * f2100000     PCI I/O space
- * f4000000     device bus mappings (boot)
- * fa000000     device bus mappings (cs0)
- * fa800000     device bus mappings (cs2)
- * fc000000     device bus mappings (cs0/cs1)
- *
- * virt         phys            size
- * fdd00000     f1000000        1M      on-chip peripheral registers
- * fde00000     f2000000        1M      PCIe I/O space
- * fdf00000     f2100000        1M      PCI I/O space
- * fe000000     f0000000        16M     PCIe WA space (Orion-1/Orion-NAS only)
- ****************************************************************************/
-#define ORION5X_REGS_PHYS_BASE          0xf1000000
-#define ORION5X_REGS_VIRT_BASE          0xfdd00000
-#define ORION5X_REGS_SIZE               SZ_1M
-
-#define ORION5X_PCIE_IO_PHYS_BASE       0xf2000000
-#define ORION5X_PCIE_IO_VIRT_BASE       0xfde00000
-#define ORION5X_PCIE_IO_BUS_BASE        0x00000000
-#define ORION5X_PCIE_IO_SIZE            SZ_1M
-
-#define ORION5X_PCI_IO_PHYS_BASE        0xf2100000
-#define ORION5X_PCI_IO_VIRT_BASE        0xfdf00000
-#define ORION5X_PCI_IO_BUS_BASE         0x00100000
-#define ORION5X_PCI_IO_SIZE             SZ_1M
-
-/* Relevant only for Orion-1/Orion-NAS */
-#define ORION5X_PCIE_WA_PHYS_BASE       0xf0000000
-#define ORION5X_PCIE_WA_VIRT_BASE       0xfe000000
-#define ORION5X_PCIE_WA_SIZE            SZ_16M
-
-#define ORION5X_PCIE_MEM_PHYS_BASE      0xe0000000
-#define ORION5X_PCIE_MEM_SIZE           SZ_128M
-
-#define ORION5X_PCI_MEM_PHYS_BASE       0xe8000000
-#define ORION5X_PCI_MEM_SIZE            SZ_128M
-
-/*******************************************************************************
- * Supported Devices & Revisions
- ******************************************************************************/
-/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
-#define MV88F5181_DEV_ID        0x5181
-#define MV88F5181_REV_B1        3
-#define MV88F5181L_REV_A0       8
-#define MV88F5181L_REV_A1       9
-/* Orion-NAS (88F5182) */
-#define MV88F5182_DEV_ID        0x5182
-#define MV88F5182_REV_A2        2
-/* Orion-2 (88F5281) */
-#define MV88F5281_DEV_ID        0x5281
-#define MV88F5281_REV_D1        5
-#define MV88F5281_REV_D2        6
-
-/*******************************************************************************
- * Orion Registers Map
- ******************************************************************************/
-#define ORION5X_DDR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x00000)
-#define ORION5X_DDR_REG(x)              (ORION5X_DDR_VIRT_BASE | (x))
-
-#define ORION5X_DEV_BUS_PHYS_BASE       (ORION5X_REGS_PHYS_BASE | 0x10000)
-#define ORION5X_DEV_BUS_VIRT_BASE       (ORION5X_REGS_VIRT_BASE | 0x10000)
-#define ORION5X_DEV_BUS_REG(x)          (ORION5X_DEV_BUS_VIRT_BASE | (x))
-#define  I2C_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE | 0x1000)
-#define  UART0_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE | 0x2000)
-#define  UART0_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE | 0x2000)
-#define  UART1_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE | 0x2100)
-#define  UART1_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE | 0x2100)
-
-#define ORION5X_BRIDGE_VIRT_BASE        (ORION5X_REGS_VIRT_BASE | 0x20000)
-#define ORION5X_BRIDGE_REG(x)           (ORION5X_BRIDGE_VIRT_BASE | (x))
-#define  TIMER_VIRT_BASE                (ORION5X_BRIDGE_VIRT_BASE | 0x300)
-
-#define ORION5X_PCI_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x30000)
-#define ORION5X_PCI_REG(x)              (ORION5X_PCI_VIRT_BASE | (x))
-
-#define ORION5X_PCIE_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x40000)
-#define ORION5X_PCIE_REG(x)             (ORION5X_PCIE_VIRT_BASE | (x))
-
-#define ORION5X_USB0_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0x50000)
-#define ORION5X_USB0_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x50000)
-#define ORION5X_USB0_REG(x)             (ORION5X_USB0_VIRT_BASE | (x))
-
-#define ORION5X_ETH_PHYS_BASE           (ORION5X_REGS_PHYS_BASE | 0x70000)
-#define ORION5X_ETH_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x70000)
-#define ORION5X_ETH_REG(x)              (ORION5X_ETH_VIRT_BASE | (x))
-
-#define ORION5X_SATA_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0x80000)
-#define ORION5X_SATA_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x80000)
-#define ORION5X_SATA_REG(x)             (ORION5X_SATA_VIRT_BASE | (x))
-
-#define ORION5X_USB1_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0xa0000)
-#define ORION5X_USB1_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0xa0000)
-#define ORION5X_USB1_REG(x)             (ORION5X_USB1_VIRT_BASE | (x))
-
-/*******************************************************************************
- * Device Bus Registers
- ******************************************************************************/
-#define MPP_0_7_CTRL            ORION5X_DEV_BUS_REG(0x000)
-#define MPP_8_15_CTRL           ORION5X_DEV_BUS_REG(0x004)
-#define MPP_16_19_CTRL          ORION5X_DEV_BUS_REG(0x050)
-#define MPP_DEV_CTRL            ORION5X_DEV_BUS_REG(0x008)
-#define MPP_RESET_SAMPLE        ORION5X_DEV_BUS_REG(0x010)
-#define GPIO_OUT                ORION5X_DEV_BUS_REG(0x100)
-#define GPIO_IO_CONF            ORION5X_DEV_BUS_REG(0x104)
-#define GPIO_BLINK_EN           ORION5X_DEV_BUS_REG(0x108)
-#define GPIO_IN_POL             ORION5X_DEV_BUS_REG(0x10c)
-#define GPIO_DATA_IN            ORION5X_DEV_BUS_REG(0x110)
-#define GPIO_EDGE_CAUSE         ORION5X_DEV_BUS_REG(0x114)
-#define GPIO_EDGE_MASK          ORION5X_DEV_BUS_REG(0x118)
-#define GPIO_LEVEL_MASK         ORION5X_DEV_BUS_REG(0x11c)
-#define DEV_BANK_0_PARAM        ORION5X_DEV_BUS_REG(0x45c)
-#define DEV_BANK_1_PARAM        ORION5X_DEV_BUS_REG(0x460)
-#define DEV_BANK_2_PARAM        ORION5X_DEV_BUS_REG(0x464)
-#define DEV_BANK_BOOT_PARAM     ORION5X_DEV_BUS_REG(0x46c)
-#define DEV_BUS_CTRL            ORION5X_DEV_BUS_REG(0x4c0)
-#define DEV_BUS_INT_CAUSE       ORION5X_DEV_BUS_REG(0x4d0)
-#define DEV_BUS_INT_MASK        ORION5X_DEV_BUS_REG(0x4d4)
-#define GPIO_MAX                32
-
-/***************************************************************************
- * Orion CPU Bridge Registers
- **************************************************************************/
-#define CPU_CONF                ORION5X_BRIDGE_REG(0x100)
-#define CPU_CTRL                ORION5X_BRIDGE_REG(0x104)
-#define CPU_RESET_MASK          ORION5X_BRIDGE_REG(0x108)
-#define CPU_SOFT_RESET          ORION5X_BRIDGE_REG(0x10c)
-#define POWER_MNG_CTRL_REG      ORION5X_BRIDGE_REG(0x11C)
-#define BRIDGE_CAUSE            ORION5X_BRIDGE_REG(0x110)
-#define BRIDGE_MASK             ORION5X_BRIDGE_REG(0x114)
-#define  BRIDGE_INT_TIMER0      0x0002
-#define  BRIDGE_INT_TIMER1      0x0004
-#define  BRIDGE_INT_TIMER1_CLR  (~0x0004)
-#define MAIN_IRQ_CAUSE          ORION5X_BRIDGE_REG(0x200)
-#define MAIN_IRQ_MASK           ORION5X_BRIDGE_REG(0x204)
-
-
-#endif
diff --git a/include/asm-arm/arch-orion5x/system.h b/include/asm-arm/arch-orion5x/system.h
deleted file mode 100644
index 3f1d1e2d38f8..000000000000
--- a/include/asm-arm/arch-orion5x/system.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * include/asm-arm/arch-orion5x/system.h
- *
- * Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/orion5x.h>
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-static inline void arch_reset(char mode)
-{
-        /*
-         * Enable and issue soft reset
-         */
-        orion5x_setbits(CPU_RESET_MASK, (1 << 2));
-        orion5x_setbits(CPU_SOFT_RESET, 1);
-}
-
-
-#endif
diff --git a/include/asm-arm/arch-orion5x/timex.h b/include/asm-arm/arch-orion5x/timex.h
deleted file mode 100644
index 31c568e28cc3..000000000000
--- a/include/asm-arm/arch-orion5x/timex.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * include/asm-arm/arch-orion5x/timex.h
- *
- * Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#define CLOCK_TICK_RATE         (100 * HZ)
-
-#define ORION5X_TCLK            166666667
diff --git a/include/asm-arm/arch-orion5x/uncompress.h b/include/asm-arm/arch-orion5x/uncompress.h
deleted file mode 100644
index 7548cedf2d76..000000000000
--- a/include/asm-arm/arch-orion5x/uncompress.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * include/asm-arm/arch-orion5x/uncompress.h
- *
- * Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/serial_reg.h>
-#include <asm/arch/orion5x.h>
-
-#define SERIAL_BASE     ((unsigned char *)UART0_PHYS_BASE)
-
-static void putc(const char c)
-{
-        unsigned char *base = SERIAL_BASE;
-        int i;
-
-        for (i = 0; i < 0x1000; i++) {
-                if (base[UART_LSR << 2] & UART_LSR_THRE)
-                        break;
-                barrier();
-        }
-
-        base[UART_TX << 2] = c;
-}
-
-static void flush(void)
-{
-        unsigned char *base = SERIAL_BASE;
-        unsigned char mask;
-        int i;
-
-        mask = UART_LSR_TEMT | UART_LSR_THRE;
-
-        for (i = 0; i < 0x1000; i++) {
-                if ((base[UART_LSR << 2] & mask) == mask)
-                        break;
-                barrier();
-        }
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-orion5x/vmalloc.h b/include/asm-arm/arch-orion5x/vmalloc.h
deleted file mode 100644
index 2b3061e90dc1..000000000000
--- a/include/asm-arm/arch-orion5x/vmalloc.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * include/asm-arm/arch-orion5x/vmalloc.h
- */
-
-#define VMALLOC_END       0xfd800000
diff --git a/include/asm-arm/arch-pnx4008/clock.h b/include/asm-arm/arch-pnx4008/clock.h
deleted file mode 100644
index ce155e161269..000000000000
--- a/include/asm-arm/arch-pnx4008/clock.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * include/asm-arm/arch-pnx4008/clock.h
- *
- * Clock control driver for PNX4008 - header file
- *
- * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __PNX4008_CLOCK_H__
-#define __PNX4008_CLOCK_H__
-
-struct module;
-struct clk;
-
-#define PWRMAN_VA_BASE          IO_ADDRESS(PNX4008_PWRMAN_BASE)
-#define HCLKDIVCTRL_REG         (PWRMAN_VA_BASE + 0x40)
-#define PWRCTRL_REG             (PWRMAN_VA_BASE + 0x44)
-#define PLLCTRL_REG             (PWRMAN_VA_BASE + 0x48)
-#define OSC13CTRL_REG           (PWRMAN_VA_BASE + 0x4c)
-#define SYSCLKCTRL_REG          (PWRMAN_VA_BASE + 0x50)
-#define HCLKPLLCTRL_REG         (PWRMAN_VA_BASE + 0x58)
-#define USBCTRL_REG             (PWRMAN_VA_BASE + 0x64)
-#define SDRAMCLKCTRL_REG        (PWRMAN_VA_BASE + 0x68)
-#define MSCTRL_REG              (PWRMAN_VA_BASE + 0x80)
-#define BTCLKCTRL               (PWRMAN_VA_BASE + 0x84)
-#define DUMCLKCTRL_REG          (PWRMAN_VA_BASE + 0x90)
-#define I2CCLKCTRL_REG          (PWRMAN_VA_BASE + 0xac)
-#define KEYCLKCTRL_REG          (PWRMAN_VA_BASE + 0xb0)
-#define TSCLKCTRL_REG           (PWRMAN_VA_BASE + 0xb4)
-#define PWMCLKCTRL_REG          (PWRMAN_VA_BASE + 0xb8)
-#define TIMCLKCTRL_REG          (PWRMAN_VA_BASE + 0xbc)
-#define SPICTRL_REG             (PWRMAN_VA_BASE + 0xc4)
-#define FLASHCLKCTRL_REG        (PWRMAN_VA_BASE + 0xc8)
-#define UART3CLK_REG            (PWRMAN_VA_BASE + 0xd0)
-#define UARTCLKCTRL_REG         (PWRMAN_VA_BASE + 0xe4)
-#define DMACLKCTRL_REG          (PWRMAN_VA_BASE + 0xe8)
-#define AUTOCLK_CTRL            (PWRMAN_VA_BASE + 0xec)
-#define JPEGCLKCTRL_REG         (PWRMAN_VA_BASE + 0xfc)
-
-#define AUDIOCONFIG_VA_BASE     IO_ADDRESS(PNX4008_AUDIOCONFIG_BASE)
-#define DSPPLLCTRL_REG          (AUDIOCONFIG_VA_BASE + 0x60)
-#define DSPCLKCTRL_REG          (AUDIOCONFIG_VA_BASE + 0x64)
-#define AUDIOCLKCTRL_REG        (AUDIOCONFIG_VA_BASE + 0x68)
-#define AUDIOPLLCTRL_REG        (AUDIOCONFIG_VA_BASE + 0x6C)
-
-#define USB_OTG_CLKCTRL_REG     IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xff4)
-
-#define VFP9CLKCTRL_REG         IO_ADDRESS(PNX4008_DEBUG_BASE)
-
-#define CLK_RATE_13MHZ 13000
-#define CLK_RATE_1MHZ 1000
-#define CLK_RATE_208MHZ 208000
-#define CLK_RATE_48MHZ 48000
-#define CLK_RATE_32KHZ 32
-
-#define PNX4008_UART_CLK CLK_RATE_13MHZ * 1000 /* in MHz */
-
-#endif
diff --git a/include/asm-arm/arch-pnx4008/debug-macro.S b/include/asm-arm/arch-pnx4008/debug-macro.S
deleted file mode 100644
index 67d18a203d23..000000000000
--- a/include/asm-arm/arch-pnx4008/debug-macro.S
+++ /dev/null
@@ -1,23 +0,0 @@
-/* linux/include/asm-arm/arch-pnx4008/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-                .macro  addruart,rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                mov     \rx, #0x00090000
-                addeq   \rx, \rx, #0x40000000
-                addne   \rx, \rx, #0xf4000000
-                .endm
-
-#define UART_SHIFT      2
-#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-pnx4008/dma.h b/include/asm-arm/arch-pnx4008/dma.h
deleted file mode 100644
index 418f15283ff1..000000000000
--- a/include/asm-arm/arch-pnx4008/dma.h
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-pnx4008/dma.h
- *
- *  PNX4008 DMA header file
- *
- *  Author:     Vitaly Wool
- *  Copyright:  MontaVista Software Inc. (c) 2005
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-
-#include "platform.h"
-
-#define MAX_DMA_ADDRESS         0xffffffff
-
-#define MAX_DMA_CHANNELS        8
-
-#define DMAC_BASE               IO_ADDRESS(PNX4008_DMA_CONFIG_BASE)
-#define DMAC_INT_STAT           (DMAC_BASE + 0x0000)
-#define DMAC_INT_TC_STAT        (DMAC_BASE + 0x0004)
-#define DMAC_INT_TC_CLEAR       (DMAC_BASE + 0x0008)
-#define DMAC_INT_ERR_STAT       (DMAC_BASE + 0x000c)
-#define DMAC_INT_ERR_CLEAR      (DMAC_BASE + 0x0010)
-#define DMAC_SOFT_SREQ          (DMAC_BASE + 0x0024)
-#define DMAC_CONFIG             (DMAC_BASE + 0x0030)
-#define DMAC_Cx_SRC_ADDR(c)     (DMAC_BASE + 0x0100 + (c) * 0x20)
-#define DMAC_Cx_DEST_ADDR(c)    (DMAC_BASE + 0x0104 + (c) * 0x20)
-#define DMAC_Cx_LLI(c)          (DMAC_BASE + 0x0108 + (c) * 0x20)
-#define DMAC_Cx_CONTROL(c)      (DMAC_BASE + 0x010c + (c) * 0x20)
-#define DMAC_Cx_CONFIG(c)       (DMAC_BASE + 0x0110 + (c) * 0x20)
-
-enum {
-        WIDTH_BYTE = 0,
-        WIDTH_HWORD,
-        WIDTH_WORD
-};
-
-enum {
-        FC_MEM2MEM_DMA,
-        FC_MEM2PER_DMA,
-        FC_PER2MEM_DMA,
-        FC_PER2PER_DMA,
-        FC_PER2PER_DPER,
-        FC_MEM2PER_PER,
-        FC_PER2MEM_PER,
-        FC_PER2PER_SPER
-};
-
-enum {
-        DMA_INT_UNKNOWN = 0,
-        DMA_ERR_INT = 1,
-        DMA_TC_INT = 2,
-};
-
-enum {
-        DMA_BUFFER_ALLOCATED = 1,
-        DMA_HAS_LL = 2,
-};
-
-enum {
-        PER_CAM_DMA_1 = 0,
-        PER_NDF_FLASH = 1,
-        PER_MBX_SLAVE_FIFO = 2,
-        PER_SPI2_REC_XMIT = 3,
-        PER_MS_SD_RX_XMIT = 4,
-        PER_HS_UART_1_XMIT = 5,
-        PER_HS_UART_1_RX = 6,
-        PER_HS_UART_2_XMIT = 7,
-        PER_HS_UART_2_RX = 8,
-        PER_HS_UART_7_XMIT = 9,
-        PER_HS_UART_7_RX = 10,
-        PER_SPI1_REC_XMIT = 11,
-        PER_MLC_NDF_SREC = 12,
-        PER_CAM_DMA_2 = 13,
-        PER_PRNG_INFIFO = 14,
-        PER_PRNG_OUTFIFO = 15,
-};
-
-struct pnx4008_dma_ch_ctrl {
-        int tc_mask;
-        int cacheable;
-        int bufferable;
-        int priv_mode;
-        int di;
-        int si;
-        int dest_ahb1;
-        int src_ahb1;
-        int dwidth;
-        int swidth;
-        int dbsize;
-        int sbsize;
-        int tr_size;
-};
-
-struct pnx4008_dma_ch_config {
-        int halt;
-        int active;
-        int lock;
-        int itc;
-        int ie;
-        int flow_cntrl;
-        int dest_per;
-        int src_per;
-};
-
-struct pnx4008_dma_ll {
-        unsigned long src_addr;
-        unsigned long dest_addr;
-        u32 next_dma;
-        unsigned long ch_ctrl;
-        struct pnx4008_dma_ll *next;
-        int flags;
-        void *alloc_data;
-        int (*free) (void *);
-};
-
-struct pnx4008_dma_config {
-        int is_ll;
-        unsigned long src_addr;
-        unsigned long dest_addr;
-        unsigned long ch_ctrl;
-        unsigned long ch_cfg;
-        struct pnx4008_dma_ll *ll;
-        u32 ll_dma;
-        int flags;
-        void *alloc_data;
-        int (*free) (void *);
-};
-
-extern struct pnx4008_dma_ll *pnx4008_alloc_ll_entry(dma_addr_t *);
-extern void pnx4008_free_ll_entry(struct pnx4008_dma_ll *, dma_addr_t);
-extern void pnx4008_free_ll(u32 ll_dma, struct pnx4008_dma_ll *);
-
-extern int pnx4008_request_channel(char *, int,
-                                   void (*)(int, int, void *),
-                                   void *);
-extern void pnx4008_free_channel(int);
-extern int pnx4008_config_dma(int, int, int);
-extern int pnx4008_dma_pack_control(const struct pnx4008_dma_ch_ctrl *,
-                                    unsigned long *);
-extern int pnx4008_dma_parse_control(unsigned long,
-                                     struct pnx4008_dma_ch_ctrl *);
-extern int pnx4008_dma_pack_config(const struct pnx4008_dma_ch_config *,
-                                   unsigned long *);
-extern int pnx4008_dma_parse_config(unsigned long,
-                                    struct pnx4008_dma_ch_config *);
-extern int pnx4008_config_channel(int, struct pnx4008_dma_config *);
-extern int pnx4008_channel_get_config(int, struct pnx4008_dma_config *);
-extern int pnx4008_dma_ch_enable(int);
-extern int pnx4008_dma_ch_disable(int);
-extern int pnx4008_dma_ch_enabled(int);
-extern void pnx4008_dma_split_head_entry(struct pnx4008_dma_config *,
-                                         struct pnx4008_dma_ch_ctrl *);
-extern void pnx4008_dma_split_ll_entry(struct pnx4008_dma_ll *,
-                                       struct pnx4008_dma_ch_ctrl *);
-
-#endif                          /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-pnx4008/entry-macro.S b/include/asm-arm/arch-pnx4008/entry-macro.S
deleted file mode 100644
index f11731974e5d..000000000000
--- a/include/asm-arm/arch-pnx4008/entry-macro.S
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * include/asm-arm/arch-pnx4008/entry-macro.S
- *
- * Low-level IRQ helper macros for PNX4008-based platforms
- *
- * 2005-2006 (c) MontaVista Software, Inc.
- * Author: Vitaly Wool <vwool@ru.mvista.com>
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include "platform.h"
-
-#define IO_BASE         0xF0000000
-#define IO_ADDRESS(x)  (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE)
-
-#define INTRC_MASK                      0x00
-#define INTRC_RAW_STAT                  0x04
-#define INTRC_STAT                      0x08
-#define INTRC_POLAR                     0x0C
-#define INTRC_ACT_TYPE                  0x10
-#define INTRC_TYPE                      0x14
-
-#define SIC1_BASE_INT   32
-#define SIC2_BASE_INT   64
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-/* decode the MIC interrupt numbers */
-                ldr     \base, =IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
-                ldr     \irqstat, [\base, #INTRC_STAT]
-
-                cmp     \irqstat,#1<<16
-                movhs   \irqnr,#16
-                movlo   \irqnr,#0
-                movhs   \irqstat,\irqstat,lsr#16
-                cmp     \irqstat,#1<<8
-                addhs   \irqnr,\irqnr,#8
-                movhs   \irqstat,\irqstat,lsr#8
-                cmp     \irqstat,#1<<4
-                addhs   \irqnr,\irqnr,#4
-                movhs   \irqstat,\irqstat,lsr#4
-                cmp     \irqstat,#1<<2
-                addhs   \irqnr,\irqnr,#2
-                movhs   \irqstat,\irqstat,lsr#2
-                cmp     \irqstat,#1<<1
-                addhs   \irqnr,\irqnr,#1
-
-/* was there an interrupt ? if not then drop out with EQ status */
-                teq     \irqstat,#0
-                beq     1003f
-
-/* and now check for extended IRQ reasons */
-                cmp     \irqnr,#1
-                bls     1003f
-                cmp     \irqnr,#30
-                blo     1002f
-
-/* IRQ 31,30  : High priority cascade IRQ handle */
-/* read the correct SIC */
-/* decoding status after compare : eq is 30 (SIC1) , ne is 31 (SIC2) */
-/* set the base IRQ number */
-                ldreq   \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
-                moveq  \irqnr,#SIC1_BASE_INT
-                ldrne   \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
-                movne   \irqnr,#SIC2_BASE_INT
-                ldr     \irqstat, [\base, #INTRC_STAT]
-                ldr     \tmp,     [\base, #INTRC_TYPE]
-/* and with inverted mask : low priority interrupts  */
-                and     \irqstat,\irqstat,\tmp
-                b       1004f
-
-1003:
-/* IRQ 1,0  : Low priority cascade IRQ handle */
-/* read the correct SIC */
-/* decoding status after compare : eq is 1 (SIC2) , ne is 0 (SIC1)*/
-/* read the correct SIC */
-/* set the base IRQ number  */
-                ldrne   \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
-                movne   \irqnr,#SIC1_BASE_INT
-                ldreq   \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
-                moveq   \irqnr,#SIC2_BASE_INT
-                ldr     \irqstat, [\base, #INTRC_STAT]
-                ldr     \tmp,     [\base, #INTRC_TYPE]
-/* and with inverted mask : low priority interrupts  */
-                bic     \irqstat,\irqstat,\tmp
-
-1004:
-
-                cmp     \irqstat,#1<<16
-                addhs   \irqnr,\irqnr,#16
-                movhs   \irqstat,\irqstat,lsr#16
-                cmp     \irqstat,#1<<8
-                addhs   \irqnr,\irqnr,#8
-                movhs   \irqstat,\irqstat,lsr#8
-                cmp     \irqstat,#1<<4
-                addhs   \irqnr,\irqnr,#4
-                movhs   \irqstat,\irqstat,lsr#4
-                cmp     \irqstat,#1<<2
-                addhs   \irqnr,\irqnr,#2
-                movhs   \irqstat,\irqstat,lsr#2
-                cmp     \irqstat,#1<<1
-                addhs   \irqnr,\irqnr,#1
-
-
-/* is irqstat not zero */
-
-1002:
-/* we assert that irqstat is not equal to zero and return ne status if true*/
-                teq     \irqstat,#0
-1003:
-                .endm
-
-
-                .macro  irq_prio_table
-                .endm
-
-
diff --git a/include/asm-arm/arch-pnx4008/gpio.h b/include/asm-arm/arch-pnx4008/gpio.h
deleted file mode 100644
index d01bf83d55c2..000000000000
--- a/include/asm-arm/arch-pnx4008/gpio.h
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * include/asm-arm/arch-pnx4008/gpio.h
- *
- * PNX4008 GPIO driver - header file
- *
- * Author: Dmitry Chigirev <source@mvista.com>
- *
- * Based on reference code by Iwo Mergler and Z.Tabaaloute from Philips:
- * Copyright (c) 2005 Koninklijke Philips Electronics N.V.
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef _PNX4008_GPIO_H_
-#define _PNX4008_GPIO_H_
-
-
-/* Block numbers */
-#define GPIO_IN         (0)
-#define GPIO_OUT                (0x100)
-#define GPIO_BID                (0x200)
-#define GPIO_RAM                (0x300)
-#define GPIO_MUX                (0x400)
-
-#define GPIO_TYPE_MASK(K) ((K) & 0x700)
-
-/* INPUT GPIOs */
-/* GPI */
-#define GPI_00          (GPIO_IN | 0)
-#define GPI_01          (GPIO_IN | 1)
-#define GPI_02          (GPIO_IN | 2)
-#define GPI_03          (GPIO_IN | 3)
-#define GPI_04          (GPIO_IN | 4)
-#define GPI_05          (GPIO_IN | 5)
-#define GPI_06          (GPIO_IN | 6)
-#define GPI_07          (GPIO_IN | 7)
-#define GPI_08          (GPIO_IN | 8)
-#define GPI_09          (GPIO_IN | 9)
-#define U1_RX           (GPIO_IN | 15)
-#define U2_HTCS         (GPIO_IN | 16)
-#define U2_RX           (GPIO_IN | 17)
-#define U3_RX           (GPIO_IN | 18)
-#define U4_RX           (GPIO_IN | 19)
-#define U5_RX           (GPIO_IN | 20)
-#define U6_IRRX         (GPIO_IN | 21)
-#define U7_HCTS         (GPIO_IN | 22)
-#define U7_RX           (GPIO_IN | 23)
-/* MISC IN */
-#define SPI1_DATIN      (GPIO_IN | 25)
-#define DISP_SYNC       (GPIO_IN | 26)
-#define SPI2_DATIN      (GPIO_IN | 27)
-#define GPI_11          (GPIO_IN | 28)
-
-#define GPIO_IN_MASK   0x1eff83ff
-
-/* OUTPUT GPIOs */
-/* GPO */
-#define GPO_00          (GPIO_OUT | 0)
-#define GPO_01          (GPIO_OUT | 1)
-#define GPO_02          (GPIO_OUT | 2)
-#define GPO_03          (GPIO_OUT | 3)
-#define GPO_04          (GPIO_OUT | 4)
-#define GPO_05          (GPIO_OUT | 5)
-#define GPO_06          (GPIO_OUT | 6)
-#define GPO_07          (GPIO_OUT | 7)
-#define GPO_08          (GPIO_OUT | 8)
-#define GPO_09          (GPIO_OUT | 9)
-#define GPO_10          (GPIO_OUT | 10)
-#define GPO_11          (GPIO_OUT | 11)
-#define GPO_12          (GPIO_OUT | 12)
-#define GPO_13          (GPIO_OUT | 13)
-#define GPO_14          (GPIO_OUT | 14)
-#define GPO_15          (GPIO_OUT | 15)
-#define GPO_16          (GPIO_OUT | 16)
-#define GPO_17          (GPIO_OUT | 17)
-#define GPO_18          (GPIO_OUT | 18)
-#define GPO_19          (GPIO_OUT | 19)
-#define GPO_20          (GPIO_OUT | 20)
-#define GPO_21          (GPIO_OUT | 21)
-#define GPO_22          (GPIO_OUT | 22)
-#define GPO_23          (GPIO_OUT | 23)
-
-#define GPIO_OUT_MASK   0xffffff
-
-/* BIDIRECTIONAL GPIOs */
-/* RAM pins */
-#define RAM_D19         (GPIO_RAM | 0)
-#define RAM_D20         (GPIO_RAM | 1)
-#define RAM_D21         (GPIO_RAM | 2)
-#define RAM_D22         (GPIO_RAM | 3)
-#define RAM_D23         (GPIO_RAM | 4)
-#define RAM_D24         (GPIO_RAM | 5)
-#define RAM_D25         (GPIO_RAM | 6)
-#define RAM_D26         (GPIO_RAM | 7)
-#define RAM_D27         (GPIO_RAM | 8)
-#define RAM_D28         (GPIO_RAM | 9)
-#define RAM_D29         (GPIO_RAM | 10)
-#define RAM_D30         (GPIO_RAM | 11)
-#define RAM_D31         (GPIO_RAM | 12)
-
-#define GPIO_RAM_MASK   0x1fff
-
-/* I/O pins */
-#define GPIO_00         (GPIO_BID | 25)
-#define GPIO_01         (GPIO_BID | 26)
-#define GPIO_02         (GPIO_BID | 27)
-#define GPIO_03         (GPIO_BID | 28)
-#define GPIO_04         (GPIO_BID | 29)
-#define GPIO_05         (GPIO_BID | 30)
-
-#define GPIO_BID_MASK   0x7e000000
-
-/* Non-GPIO multiplexed PIOs. For multiplexing with GPIO, please use GPIO macros */
-#define GPIO_SDRAM_SEL  (GPIO_MUX | 3)
-
-#define GPIO_MUX_MASK   0x8
-
-/* Extraction/assembly macros */
-#define GPIO_BIT_MASK(K) ((K) & 0x1F)
-#define GPIO_BIT(K) (1 << GPIO_BIT_MASK(K))
-#define GPIO_ISMUX(K) ((GPIO_TYPE_MASK(K) == GPIO_MUX) && (GPIO_BIT(K) & GPIO_MUX_MASK))
-#define GPIO_ISRAM(K) ((GPIO_TYPE_MASK(K) == GPIO_RAM) && (GPIO_BIT(K) & GPIO_RAM_MASK))
-#define GPIO_ISBID(K) ((GPIO_TYPE_MASK(K) == GPIO_BID) && (GPIO_BIT(K) & GPIO_BID_MASK))
-#define GPIO_ISOUT(K) ((GPIO_TYPE_MASK(K) == GPIO_OUT) && (GPIO_BIT(K) & GPIO_OUT_MASK))
-#define GPIO_ISIN(K)  ((GPIO_TYPE_MASK(K) == GPIO_IN) && (GPIO_BIT(K) & GPIO_IN_MASK))
-
-/* Start Enable Pin Interrupts - table 58 page 66 */
-
-#define SE_PIN_BASE_INT   32
-
-#define SE_U7_RX_INT            63
-#define SE_U7_HCTS_INT          62
-#define SE_BT_CLKREQ_INT        61
-#define SE_U6_IRRX_INT          60
-/*59 unused*/
-#define SE_U5_RX_INT            58
-#define SE_GPI_11_INT           57
-#define SE_U3_RX_INT            56
-#define SE_U2_HCTS_INT          55
-#define SE_U2_RX_INT            54
-#define SE_U1_RX_INT            53
-#define SE_DISP_SYNC_INT        52
-/*51 unused*/
-#define SE_SDIO_INT_N           50
-#define SE_MSDIO_START_INT      49
-#define SE_GPI_06_INT           48
-#define SE_GPI_05_INT           47
-#define SE_GPI_04_INT           46
-#define SE_GPI_03_INT           45
-#define SE_GPI_02_INT           44
-#define SE_GPI_01_INT           43
-#define SE_GPI_00_INT           42
-#define SE_SYSCLKEN_PIN_INT     41
-#define SE_SPI1_DATAIN_INT      40
-#define SE_GPI_07_INT           39
-#define SE_SPI2_DATAIN_INT      38
-#define SE_GPI_10_INT           37
-#define SE_GPI_09_INT           36
-#define SE_GPI_08_INT           35
-/*34-32 unused*/
-
-/* Start Enable Internal Interrupts - table 57 page 65 */
-
-#define SE_INT_BASE_INT   0
-
-#define SE_TS_IRQ               31
-#define SE_TS_P_INT             30
-#define SE_TS_AUX_INT           29
-/*27-28 unused*/
-#define SE_USB_AHB_NEED_CLK_INT 26
-#define SE_MSTIMER_INT          25
-#define SE_RTC_INT              24
-#define SE_USB_NEED_CLK_INT     23
-#define SE_USB_INT              22
-#define SE_USB_I2C_INT          21
-#define SE_USB_OTG_TIMER_INT    20
-#define SE_USB_OTG_ATX_INT_N    19
-/*18 unused*/
-#define SE_DSP_GPIO4_INT        17
-#define SE_KEY_IRQ              16
-#define SE_DSP_SLAVEPORT_INT    15
-#define SE_DSP_GPIO1_INT        14
-#define SE_DSP_GPIO0_INT        13
-#define SE_DSP_AHB_INT          12
-/*11-6 unused*/
-#define SE_GPIO_05_INT          5
-#define SE_GPIO_04_INT          4
-#define SE_GPIO_03_INT          3
-#define SE_GPIO_02_INT          2
-#define SE_GPIO_01_INT          1
-#define SE_GPIO_00_INT          0
-
-#define START_INT_REG_BIT(irq) (1<<((irq)&0x1F))
-
-#define START_INT_ER_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_RSR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_SR_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_APR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1)))
-
-extern int pnx4008_gpio_register_pin(unsigned short pin);
-extern int pnx4008_gpio_unregister_pin(unsigned short pin);
-extern unsigned long pnx4008_gpio_read_pin(unsigned short pin);
-extern int pnx4008_gpio_write_pin(unsigned short pin, int output);
-extern int pnx4008_gpio_set_pin_direction(unsigned short pin, int output);
-extern int pnx4008_gpio_read_pin_direction(unsigned short pin);
-extern int pnx4008_gpio_set_pin_mux(unsigned short pin, int output);
-extern int pnx4008_gpio_read_pin_mux(unsigned short pin);
-
-static inline void start_int_umask(u8 irq)
-{
-        __raw_writel(__raw_readl(START_INT_ER_REG(irq)) |
-                     START_INT_REG_BIT(irq), START_INT_ER_REG(irq));
-}
-
-static inline void start_int_mask(u8 irq)
-{
-        __raw_writel(__raw_readl(START_INT_ER_REG(irq)) &
-                     ~START_INT_REG_BIT(irq), START_INT_ER_REG(irq));
-}
-
-static inline void start_int_ack(u8 irq)
-{
-        __raw_writel(START_INT_REG_BIT(irq), START_INT_RSR_REG(irq));
-}
-
-static inline void start_int_set_falling_edge(u8 irq)
-{
-        __raw_writel(__raw_readl(START_INT_APR_REG(irq)) &
-                     ~START_INT_REG_BIT(irq), START_INT_APR_REG(irq));
-}
-
-static inline void start_int_set_rising_edge(u8 irq)
-{
-        __raw_writel(__raw_readl(START_INT_APR_REG(irq)) |
-                     START_INT_REG_BIT(irq), START_INT_APR_REG(irq));
-}
-
-#endif                          /* _PNX4008_GPIO_H_ */
diff --git a/include/asm-arm/arch-pnx4008/hardware.h b/include/asm-arm/arch-pnx4008/hardware.h
deleted file mode 100644
index a4410397a921..000000000000
--- a/include/asm-arm/arch-pnx4008/hardware.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * linux/include/asm-arm/arch-pnx4008/hardware.h
- *
- * Copyright (c) 2005 MontaVista Software, Inc. <source@mvista.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <asm/sizes.h>
-#include <asm/arch/platform.h>
-
-/* Start of virtual addresses for IO devices */
-#define IO_BASE         0xF0000000
-
-/* This macro relies on fact that for all HW i/o addresses bits 20-23 are 0 */
-#define IO_ADDRESS(x)  (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE)
-
-#endif
diff --git a/include/asm-arm/arch-pnx4008/io.h b/include/asm-arm/arch-pnx4008/io.h
deleted file mode 100644
index 29ee43955c52..000000000000
--- a/include/asm-arm/arch-pnx4008/io.h
+++ /dev/null
@@ -1,21 +0,0 @@
-
-/*
- *  include/asm-arm/arch-pnx4008/io.h
- *
- * Author: Dmitry Chigirev <chigirev@ru.mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-#define __io(a)                 ((void __iomem *)(a))
-#define __mem_pci(a)            (a)
-
-#endif
diff --git a/include/asm-arm/arch-pnx4008/irq.h b/include/asm-arm/arch-pnx4008/irq.h
deleted file mode 100644
index fabff5dc337f..000000000000
--- a/include/asm-arm/arch-pnx4008/irq.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * include/asm-arm/arch-pnx4008/irq.h
- *
- * PNX4008 IRQ controller driver - header file
- * this one is used in entry-arnv.S as well so it cannot contain C code
- *
- * Copyright (c) 2005 Philips Semiconductors
- * Copyright (c) 2005 MontaVista Software, Inc.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- */
-#ifndef __PNX4008_IRQ_H__
-#define __PNX4008_IRQ_H__
-
-#define MIC_VA_BASE             IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
-#define SIC1_VA_BASE            IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
-#define SIC2_VA_BASE            IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
-
-/* Manual: Chapter 20, page 195 */
-
-#define INTC_BIT(irq) (1<< ((irq) & 0x1F))
-
-#define INTC_ER(irq)    IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x0 + (((irq)&(0x3<<5))<<9)))
-#define INTC_RSR(irq)   IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x4 + (((irq)&(0x3<<5))<<9)))
-#define INTC_SR(irq)    IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x8 + (((irq)&(0x3<<5))<<9)))
-#define INTC_APR(irq)   IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0xC + (((irq)&(0x3<<5))<<9)))
-#define INTC_ATR(irq)   IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x10 + (((irq)&(0x3<<5))<<9)))
-#define INTC_ITR(irq)   IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x14 + (((irq)&(0x3<<5))<<9)))
-
-#define START_INT_REG_BIT(irq) (1<<((irq)&0x1F))
-
-#define START_INT_ER_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_RSR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_SR_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_APR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1)))
-
-extern void __init pnx4008_init_irq(void);
-
-#endif /* __PNX4008_IRQ_H__ */
diff --git a/include/asm-arm/arch-pnx4008/irqs.h b/include/asm-arm/arch-pnx4008/irqs.h
deleted file mode 100644
index a25d18f2d87a..000000000000
--- a/include/asm-arm/arch-pnx4008/irqs.h
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * include/asm-arm/arch-pnx4008/irqs.h
- *
- * PNX4008 IRQ controller driver - header file
- *
- * Author: Dmitry Chigirev <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __PNX4008_IRQS_h__
-#define __PNX4008_IRQS_h__
-
-#define NR_IRQS         96
-
-/*Manual: table 259, page 199*/
-
-/*SUB2 Interrupt Routing (SIC2)*/
-
-#define SIC2_BASE_INT   64
-
-#define CLK_SWITCH_ARM_INT 95   /*manual: Clkswitch ARM  */
-#define CLK_SWITCH_DSP_INT 94   /*manual: ClkSwitch DSP  */
-#define CLK_SWITCH_AUD_INT 93   /*manual: Clkswitch AUD  */
-#define GPI_06_INT         92
-#define GPI_05_INT         91
-#define GPI_04_INT         90
-#define GPI_03_INT         89
-#define GPI_02_INT         88
-#define GPI_01_INT         87
-#define GPI_00_INT         86
-#define BT_CLKREQ_INT      85
-#define SPI1_DATIN_INT     84
-#define U5_RX_INT          83
-#define SDIO_INT_N         82
-#define CAM_HS_INT         81
-#define CAM_VS_INT         80
-#define GPI_07_INT         79
-#define DISP_SYNC_INT      78
-#define DSP_INT8           77
-#define U7_HCTS_INT        76
-#define GPI_10_INT         75
-#define GPI_09_INT         74
-#define GPI_08_INT         73
-#define DSP_INT7           72
-#define U2_HCTS_INT        71
-#define SPI2_DATIN_INT     70
-#define GPIO_05_INT        69
-#define GPIO_04_INT        68
-#define GPIO_03_INT        67
-#define GPIO_02_INT        66
-#define GPIO_01_INT        65
-#define GPIO_00_INT        64
-
-/*Manual: table 258, page 198*/
-
-/*SUB1 Interrupt Routing (SIC1)*/
-
-#define SIC1_BASE_INT   32
-
-#define USB_I2C_INT        63
-#define USB_DEV_HP_INT     62
-#define USB_DEV_LP_INT     61
-#define USB_DEV_DMA_INT    60
-#define USB_HOST_INT       59
-#define USB_OTG_ATX_INT_N  58
-#define USB_OTG_TIMER_INT  57
-#define SW_INT             56
-#define SPI1_INT           55
-#define KEY_IRQ            54
-#define DSP_M_INT          53
-#define RTC_INT            52
-#define I2C_1_INT          51
-#define I2C_2_INT          50
-#define PLL1_LOCK_INT      49
-#define PLL2_LOCK_INT      48
-#define PLL3_LOCK_INT      47
-#define PLL4_LOCK_INT      46
-#define PLL5_LOCK_INT      45
-#define SPI2_INT           44
-#define DSP_INT1           43
-#define DSP_INT2           42
-#define DSP_TDM_INT2       41
-#define TS_AUX_INT         40
-#define TS_IRQ             39
-#define TS_P_INT           38
-#define UOUT1_TO_PAD_INT   37
-#define GPI_11_INT         36
-#define DSP_INT4           35
-#define JTAG_COMM_RX_INT   34
-#define JTAG_COMM_TX_INT   33
-#define DSP_INT3           32
-
-/*Manual: table 257, page 197*/
-
-/*MAIN Interrupt Routing*/
-
-#define MAIN_BASE_INT   0
-
-#define SUB2_FIQ_N         31   /*active low */
-#define SUB1_FIQ_N         30   /*active low */
-#define JPEG_INT           29
-#define DMA_INT            28
-#define MSTIMER_INT        27
-#define IIR1_INT           26
-#define IIR2_INT           25
-#define IIR7_INT           24
-#define DSP_TDM_INT0       23
-#define DSP_TDM_INT1       22
-#define DSP_P_INT          21
-#define DSP_INT0           20
-#define DUM_INT            19
-#define UOUT0_TO_PAD_INT   18
-#define MP4_ENC_INT        17
-#define MP4_DEC_INT        16
-#define SD0_INT            15
-#define MBX_INT            14
-#define SD1_INT            13
-#define MS_INT_N           12
-#define FLASH_INT          11 /*NAND*/
-#define IIR6_INT           10
-#define IIR5_INT           9
-#define IIR4_INT           8
-#define IIR3_INT           7
-#define WATCH_INT          6
-#define HSTIMER_INT        5
-#define ARCH_TIMER_IRQ     HSTIMER_INT
-#define CAM_INT            4
-#define PRNG_INT           3
-#define CRYPTO_INT         2
-#define SUB2_IRQ_N         1    /*active low */
-#define SUB1_IRQ_N         0    /*active low */
-
-#define PNX4008_IRQ_TYPES \
-{                                           /*IRQ #'s: */         \
-IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, /*  0, 1, 2, 3 */     \
-IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /*  4, 5, 6, 7 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /*  8, 9,10,11 */     \
-IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 12,13,14,15 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 16,17,18,19 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 20,21,22,23 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 24,25,26,27 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_LOW,  /* 28,29,30,31 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 32,33,34,35 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_FALLING, IRQ_TYPE_LEVEL_HIGH, /* 36,37,38,39 */  \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 40,41,42,43 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 44,45,46,47 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_LOW,  /* 48,49,50,51 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 52,53,54,55 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, /* 56,57,58,59 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 60,61,62,63 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 64,65,66,67 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 68,69,70,71 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 72,73,74,75 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 76,77,78,79 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 80,81,82,83 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 84,85,86,87 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 88,89,90,91 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 92,93,94,95 */     \
-}
-
-/* Start Enable Pin Interrupts - table 58 page 66 */
-
-#define SE_PIN_BASE_INT   32
-
-#define SE_U7_RX_INT            63
-#define SE_U7_HCTS_INT          62
-#define SE_BT_CLKREQ_INT        61
-#define SE_U6_IRRX_INT          60
-/*59 unused*/
-#define SE_U5_RX_INT            58
-#define SE_GPI_11_INT           57
-#define SE_U3_RX_INT            56
-#define SE_U2_HCTS_INT          55
-#define SE_U2_RX_INT            54
-#define SE_U1_RX_INT            53
-#define SE_DISP_SYNC_INT        52
-/*51 unused*/
-#define SE_SDIO_INT_N           50
-#define SE_MSDIO_START_INT      49
-#define SE_GPI_06_INT           48
-#define SE_GPI_05_INT           47
-#define SE_GPI_04_INT           46
-#define SE_GPI_03_INT           45
-#define SE_GPI_02_INT           44
-#define SE_GPI_01_INT           43
-#define SE_GPI_00_INT           42
-#define SE_SYSCLKEN_PIN_INT     41
-#define SE_SPI1_DATAIN_INT      40
-#define SE_GPI_07_INT           39
-#define SE_SPI2_DATAIN_INT      38
-#define SE_GPI_10_INT           37
-#define SE_GPI_09_INT           36
-#define SE_GPI_08_INT           35
-/*34-32 unused*/
-
-/* Start Enable Internal Interrupts - table 57 page 65 */
-
-#define SE_INT_BASE_INT   0
-
-#define SE_TS_IRQ               31
-#define SE_TS_P_INT             30
-#define SE_TS_AUX_INT           29
-/*27-28 unused*/
-#define SE_USB_AHB_NEED_CLK_INT 26
-#define SE_MSTIMER_INT          25
-#define SE_RTC_INT              24
-#define SE_USB_NEED_CLK_INT     23
-#define SE_USB_INT              22
-#define SE_USB_I2C_INT          21
-#define SE_USB_OTG_TIMER_INT    20
-
-#endif /* __PNX4008_IRQS_h__ */
diff --git a/include/asm-arm/arch-pnx4008/memory.h b/include/asm-arm/arch-pnx4008/memory.h
deleted file mode 100644
index 0d8268a95261..000000000000
--- a/include/asm-arm/arch-pnx4008/memory.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * linux/include/asm-arm/arch-pnx4008/memory.h
- *
- * Copyright (c) 2005 Philips Semiconductors
- * Copyright (c) 2005 MontaVista Software, Inc.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- */
-
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-/*
- * Physical DRAM offset.
- */
-#define PHYS_OFFSET     (0x80000000)
-
-#define __virt_to_bus(x) ((x) - PAGE_OFFSET + PHYS_OFFSET)
-#define __bus_to_virt(x) ((x) + PAGE_OFFSET - PHYS_OFFSET)
-
-#endif
diff --git a/include/asm-arm/arch-pnx4008/param.h b/include/asm-arm/arch-pnx4008/param.h
deleted file mode 100644
index 95d5f547b416..000000000000
--- a/include/asm-arm/arch-pnx4008/param.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-pnx4008/param.h
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#define HZ 100
diff --git a/include/asm-arm/arch-pnx4008/platform.h b/include/asm-arm/arch-pnx4008/platform.h
deleted file mode 100644
index 2613c7c669b1..000000000000
--- a/include/asm-arm/arch-pnx4008/platform.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * include/asm-arm/arch-pnx4008/platform.h
- *
- * PNX4008 Base addresses - header file
- *
- * Author: Dmitry Chigirev <source@mvista.com>
- *
- * Based on reference code received from Philips:
- * Copyright (C) 2003 Philips Semiconductors
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-
-#ifndef __ASM_ARCH_PLATFORM_H__
-#define __ASM_ARCH_PLATFORM_H__
-
-#define PNX4008_IRAM_BASE               0x08000000
-#define PNX4008_IRAM_SIZE               0x00010000
-#define PNX4008_YUV_SLAVE_BASE          0x10000000
-#define PNX4008_DUM_SLAVE_BASE          0x18000000
-#define PNX4008_NDF_FLASH_BASE          0x20020000
-#define PNX4008_SPI1_BASE               0x20088000
-#define PNX4008_SPI2_BASE               0x20090000
-#define PNX4008_SD_CONFIG_BASE          0x20098000
-#define PNX4008_FLASH_DATA              0x200B0000
-#define PNX4008_MLC_FLASH_BASE          0x200B8000
-#define PNX4008_JPEG_CONFIG_BASE        0x300A0000
-#define PNX4008_DMA_CONFIG_BASE         0x31000000
-#define PNX4008_USB_CONFIG_BASE         0x31020000
-#define PNX4008_SDRAM_CFG_BASE          0x31080000
-#define PNX4008_AHB2FAB_BASE            0x40000000
-#define PNX4008_PWRMAN_BASE             0x40004000
-#define PNX4008_INTCTRLMIC_BASE         0x40008000
-#define PNX4008_INTCTRLSIC1_BASE        0x4000C000
-#define PNX4008_INTCTRLSIC2_BASE        0x40010000
-#define PNX4008_HSUART1_BASE            0x40014000
-#define PNX4008_HSUART2_BASE            0x40018000
-#define PNX4008_HSUART7_BASE            0x4001C000
-#define PNX4008_RTC_BASE                0x40024000
-#define PNX4008_PIO_BASE                0x40028000
-#define PNX4008_MSTIMER_BASE            0x40034000
-#define PNX4008_HSTIMER_BASE            0x40038000
-#define PNX4008_WDOG_BASE               0x4003C000
-#define PNX4008_DEBUG_BASE              0x40040000
-#define PNX4008_TOUCH1_BASE             0x40048000
-#define PNX4008_KEYSCAN_BASE            0x40050000
-#define PNX4008_UARTCTRL_BASE           0x40054000
-#define PNX4008_PWM_BASE                0x4005C000
-#define PNX4008_UART3_BASE              0x40080000
-#define PNX4008_UART4_BASE              0x40088000
-#define PNX4008_UART5_BASE              0x40090000
-#define PNX4008_UART6_BASE              0x40098000
-#define PNX4008_I2C1_BASE               0x400A0000
-#define PNX4008_I2C2_BASE               0x400A8000
-#define PNX4008_MAGICGATE_BASE          0x400B0000
-#define PNX4008_DUMCONF_BASE            0x400B8000
-#define PNX4008_DUM_MAINCFG_BASE        0x400BC000
-#define PNX4008_DSP_BASE                0x400C0000
-#define PNX4008_PROFCOUNTER_BASE        0x400C8000
-#define PNX4008_CRYPTO_BASE             0x400D0000
-#define PNX4008_CAMIFCONF_BASE          0x400D8000
-#define PNX4008_YUV2RGB_BASE            0x400E0000
-#define PNX4008_AUDIOCONFIG_BASE        0x400E8000
-
-#endif
diff --git a/include/asm-arm/arch-pnx4008/pm.h b/include/asm-arm/arch-pnx4008/pm.h
deleted file mode 100644
index bac1634cb3e0..000000000000
--- a/include/asm-arm/arch-pnx4008/pm.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * include/asm-arm/arch-pnx4008/pm.h
- *
- * PNX4008 Power Management Routiness - header file
- *
- * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __ASM_ARCH_PNX4008_PM_H
-#define __ASM_ARCH_PNX4008_PM_H
-
-#ifndef __ASSEMBLER__
-#include "irq.h"
-#include "irqs.h"
-#include "clock.h"
-
-extern void pnx4008_pm_idle(void);
-extern void pnx4008_pm_suspend(void);
-extern unsigned int pnx4008_cpu_suspend_sz;
-extern void pnx4008_cpu_suspend(void);
-extern unsigned int pnx4008_cpu_standby_sz;
-extern void pnx4008_cpu_standby(void);
-
-extern int pnx4008_startup_pll(struct clk *);
-extern int pnx4008_shutdown_pll(struct clk *);
-
-#endif                          /* ASSEMBLER */
-#endif                          /* __ASM_ARCH_PNX4008_PM_H */
diff --git a/include/asm-arm/arch-pnx4008/system.h b/include/asm-arm/arch-pnx4008/system.h
deleted file mode 100644
index 17f9d7f9e5a1..000000000000
--- a/include/asm-arm/arch-pnx4008/system.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * linux/include/asm-arm/arch-pnx4008/system.h
- *
- * Copyright (C) 2003 Philips Semiconductors
- * Copyright (C) 2005 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-#include <asm/arch/platform.h>
-
-static void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-static inline void arch_reset(char mode)
-{
-        cpu_reset(0);
-}
-
-#endif
diff --git a/include/asm-arm/arch-pnx4008/timex.h b/include/asm-arm/arch-pnx4008/timex.h
deleted file mode 100644
index f22ee24a0219..000000000000
--- a/include/asm-arm/arch-pnx4008/timex.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * include/asm-arm/arch-pnx4008/timex.h
- *
- * PNX4008 timers header file
- *
- * Author: Dmitry Chigirev <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __PNX4008_TIMEX_H
-#define __PNX4008_TIMEX_H
-
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-
-#define CLOCK_TICK_RATE         1000000
-
-#define TICKS2USECS(x)  (x)
-
-/* MilliSecond Timer - Chapter 21 Page 202 */
-
-#define MSTIM_INT     IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x0))
-#define MSTIM_CTRL    IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x4))
-#define MSTIM_COUNTER IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x8))
-#define MSTIM_MCTRL   IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x14))
-#define MSTIM_MATCH0  IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x18))
-#define MSTIM_MATCH1  IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x1c))
-
-/* High Speed Timer - Chpater 22, Page 205 */
-
-#define HSTIM_INT     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x0))
-#define HSTIM_CTRL    IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x4))
-#define HSTIM_COUNTER IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x8))
-#define HSTIM_PMATCH  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0xC))
-#define HSTIM_PCOUNT  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x10))
-#define HSTIM_MCTRL   IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x14))
-#define HSTIM_MATCH0  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x18))
-#define HSTIM_MATCH1  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x1c))
-#define HSTIM_MATCH2  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x20))
-#define HSTIM_CCR     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x28))
-#define HSTIM_CR0     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x2C))
-#define HSTIM_CR1     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x30))
-
-/* IMPORTANT: both timers are UPCOUNTING */
-
-/* xSTIM_MCTRL bit definitions */
-#define MR0_INT        1
-#define RESET_COUNT0   (1<<1)
-#define STOP_COUNT0    (1<<2)
-#define MR1_INT        (1<<3)
-#define RESET_COUNT1   (1<<4)
-#define STOP_COUNT1    (1<<5)
-#define MR2_INT        (1<<6)
-#define RESET_COUNT2   (1<<7)
-#define STOP_COUNT2    (1<<8)
-
-/* xSTIM_CTRL bit definitions */
-#define COUNT_ENAB     1
-#define RESET_COUNT    (1<<1)
-#define DEBUG_EN       (1<<2)
-
-/* xSTIM_INT bit definitions */
-#define MATCH0_INT     1
-#define MATCH1_INT     (1<<1)
-#define MATCH2_INT     (1<<2)
-#define RTC_TICK0      (1<<4)
-#define RTC_TICK1      (1<<5)
-
-#endif
diff --git a/include/asm-arm/arch-pnx4008/uncompress.h b/include/asm-arm/arch-pnx4008/uncompress.h
deleted file mode 100644
index 8fa4d24b72b4..000000000000
--- a/include/asm-arm/arch-pnx4008/uncompress.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-pnx4008/uncompress.h
- *
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) 2006 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#define UART5_BASE 0x40090000
-
-#define UART5_DR    (*(volatile unsigned char *) (UART5_BASE))
-#define UART5_FR    (*(volatile unsigned char *) (UART5_BASE + 18))
-
-static __inline__ void putc(char c)
-{
-        while (UART5_FR & (1 << 5))
-                barrier();
-
-        UART5_DR = c;
-}
-
-/*
- * This does not append a newline
- */
-static inline void flush(void)
-{
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-pnx4008/vmalloc.h b/include/asm-arm/arch-pnx4008/vmalloc.h
deleted file mode 100644
index 140d925f6f37..000000000000
--- a/include/asm-arm/arch-pnx4008/vmalloc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * include/asm-arm/arch-pnx4008/vmalloc.h
- *
- * Author: Vitaly Wool <source@mvista.com>
- *
- * 2006 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-/*
- * Just any arbitrary offset to the start of the vmalloc VM area: the
- * current 8MB value just means that there will be a 8MB "hole" after the
- * physical memory until the kernel virtual memory starts.  That means that
- * any out-of-bounds memory accesses will hopefully be caught.
- * The vmalloc() routines leaves a hole of 4kB between each vmalloced
- * area for the same reason. ;)
- */
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
diff --git a/include/asm-arm/arch-pxa/debug-macro.S b/include/asm-arm/arch-pxa/debug-macro.S
deleted file mode 100644
index 9012cbc0ad8b..000000000000
--- a/include/asm-arm/arch-pxa/debug-macro.S
+++ /dev/null
@@ -1,25 +0,0 @@
-/* linux/include/asm-arm/arch-pxa/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-#include "hardware.h"
-
-                .macro  addruart,rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx, #0x40000000                @ physical
-                movne   \rx, #io_p2v(0x40000000)        @ virtual
-                orr     \rx, \rx, #0x00100000
-                .endm
-
-#define UART_SHIFT      2
-#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-pxa/dma.h b/include/asm-arm/arch-pxa/dma.h
deleted file mode 100644
index dbe110ee2666..000000000000
--- a/include/asm-arm/arch-pxa/dma.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-pxa/dma.h
- *
- *  Author:     Nicolas Pitre
- *  Created:    Jun 15, 2001
- *  Copyright:  MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-
-/*
- * Descriptor structure for PXA's DMA engine
- * Note: this structure must always be aligned to a 16-byte boundary.
- */
-
-typedef struct pxa_dma_desc {
-        volatile u32 ddadr;     /* Points to the next descriptor + flags */
-        volatile u32 dsadr;     /* DSADR value for the current transfer */
-        volatile u32 dtadr;     /* DTADR value for the current transfer */
-        volatile u32 dcmd;      /* DCMD value for the current transfer */
-} pxa_dma_desc;
-
-typedef enum {
-        DMA_PRIO_HIGH = 0,
-        DMA_PRIO_MEDIUM = 1,
-        DMA_PRIO_LOW = 2
-} pxa_dma_prio;
-
-#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
-#define HAVE_ARCH_PCI_SET_DMA_MASK      1
-#endif
-
-/*
- * DMA registration
- */
-
-int __init pxa_init_dma(int num_ch);
-
-int pxa_request_dma (char *name,
-                         pxa_dma_prio prio,
-                         void (*irq_handler)(int, void *),
-                         void *data);
-
-void pxa_free_dma (int dma_ch);
-
-#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-pxa/entry-macro.S b/include/asm-arm/arch-pxa/entry-macro.S
deleted file mode 100644
index 897d164da223..000000000000
--- a/include/asm-arm/arch-pxa/entry-macro.S
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * include/asm-arm/arch-pxa/entry-macro.S
- *
- * Low-level IRQ helper macros for PXA-based platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <asm/arch/hardware.h>
-#include <asm/arch/irqs.h>
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                mrc     p15, 0, \tmp, c0, c0, 0         @ CPUID
-                mov     \tmp, \tmp, lsr #13
-                and     \tmp, \tmp, #0x7                @ Core G
-                cmp     \tmp, #1
-                bhi     1004f
-
-                mov     \base, #io_p2v(0x40000000)      @ IIR Ctl = 0x40d00000
-                add     \base, \base, #0x00d00000
-                ldr     \irqstat, [\base, #0]           @ ICIP
-                ldr     \irqnr, [\base, #4]             @ ICMR
-                b       1002f
-
-1004:
-                mrc     p6, 0, \irqstat, c6, c0, 0      @ ICIP2
-                mrc     p6, 0, \irqnr, c7, c0, 0        @ ICMR2
-                ands    \irqnr, \irqstat, \irqnr
-                beq     1003f
-                rsb     \irqstat, \irqnr, #0
-                and     \irqstat, \irqstat, \irqnr
-                clz     \irqnr, \irqstat
-                rsb     \irqnr, \irqnr, #31
-                add     \irqnr, \irqnr, #32
-                b       1001f
-1003:
-                mrc     p6, 0, \irqstat, c0, c0, 0      @ ICIP
-                mrc     p6, 0, \irqnr, c1, c0, 0        @ ICMR
-1002:
-                ands    \irqnr, \irqstat, \irqnr
-                beq     1001f
-                rsb     \irqstat, \irqnr, #0
-                and     \irqstat, \irqstat, \irqnr
-                clz     \irqnr, \irqstat
-                rsb     \irqnr, \irqnr, #31
-1001:
-                .endm
diff --git a/include/asm-arm/arch-pxa/gpio.h b/include/asm-arm/arch-pxa/gpio.h
deleted file mode 100644
index 2c1e3d8ad7a2..000000000000
--- a/include/asm-arm/arch-pxa/gpio.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * linux/include/asm-arm/arch-pxa/gpio.h
- *
- * PXA GPIO wrappers for arch-neutral GPIO calls
- *
- * Written by Philipp Zabel <philipp.zabel@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-#ifndef __ASM_ARCH_PXA_GPIO_H
-#define __ASM_ARCH_PXA_GPIO_H
-
-#include <asm/arch/pxa-regs.h>
-#include <asm/irq.h>
-#include <asm/arch/hardware.h>
-
-#include <asm-generic/gpio.h>
-
-
-/* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85).
- * Those cases currently cause holes in the GPIO number space.
- */
-#define NR_BUILTIN_GPIO 128
-
-static inline int gpio_get_value(unsigned gpio)
-{
-        if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO))
-                return GPLR(gpio) & GPIO_bit(gpio);
-        else
-                return __gpio_get_value(gpio);
-}
-
-static inline void gpio_set_value(unsigned gpio, int value)
-{
-        if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) {
-                if (value)
-                        GPSR(gpio) = GPIO_bit(gpio);
-                else
-                        GPCR(gpio) = GPIO_bit(gpio);
-        } else {
-                __gpio_set_value(gpio, value);
-        }
-}
-
-#define gpio_cansleep __gpio_cansleep
-
-#define gpio_to_irq(gpio)       IRQ_GPIO(gpio)
-#define irq_to_gpio(irq)        IRQ_TO_GPIO(irq)
-
-
-#endif
diff --git a/include/asm-arm/arch-pxa/gumstix.h b/include/asm-arm/arch-pxa/gumstix.h
deleted file mode 100644
index 6fa85c4f94f8..000000000000
--- a/include/asm-arm/arch-pxa/gumstix.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-pxa/gumstix.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-
-/* BTRESET - Reset line to Bluetooth module, active low signal. */
-#define GPIO_GUMSTIX_BTRESET          7
-#define GPIO_GUMSTIX_BTRESET_MD         (GPIO_GUMSTIX_BTRESET | GPIO_OUT)
-
-
-/*
-GPIOn - Input from MAX823 (or equiv), normalizing USB +5V into a clean
-interrupt signal for determining cable presence. On the original gumstix,
-this is GPIO81, and GPIO83 needs to be defined as well. On the gumstix F,
-this moves to GPIO17 and GPIO37. */
-
-/* GPIOx - Connects to USB D+ and used as a pull-up after GPIOn
-has detected a cable insertion; driven low otherwise. */
-
-#ifdef CONFIG_ARCH_GUMSTIX_ORIG
-
-#define GPIO_GUMSTIX_USB_GPIOn          81
-#define GPIO_GUMSTIX_USB_GPIOx          83
-
-#else
-
-#define GPIO_GUMSTIX_USB_GPIOn          35
-#define GPIO_GUMSTIX_USB_GPIOx          41
-
-#endif
-
-/* usb state change */
-#define GUMSTIX_USB_INTR_IRQ            IRQ_GPIO(GPIO_GUMSTIX_USB_GPIOn)
-
-#define GPIO_GUMSTIX_USB_GPIOn_MD       (GPIO_GUMSTIX_USB_GPIOn | GPIO_IN)
-#define GPIO_GUMSTIX_USB_GPIOx_CON_MD   (GPIO_GUMSTIX_USB_GPIOx | GPIO_OUT)
-#define GPIO_GUMSTIX_USB_GPIOx_DIS_MD   (GPIO_GUMSTIX_USB_GPIOx | GPIO_IN)
-
-/*
- * SD/MMC definitions
- */
-#define GUMSTIX_GPIO_nSD_WP             22 /* SD Write Protect */
-#define GUMSTIX_GPIO_nSD_DETECT         11 /* MMC/SD Card Detect */
-#define GUMSTIX_IRQ_GPIO_nSD_DETECT     IRQ_GPIO(GUMSTIX_GPIO_nSD_DETECT)
-
-/*
- * SMC Ethernet definitions
- * ETH_RST provides a hardware reset line to the ethernet chip
- * ETH is the IRQ line in from the ethernet chip to the PXA
- */
-#define GPIO_GUMSTIX_ETH0_RST           80
-#define GPIO_GUMSTIX_ETH0_RST_MD        (GPIO_GUMSTIX_ETH0_RST | GPIO_OUT)
-#define GPIO_GUMSTIX_ETH1_RST           52
-#define GPIO_GUMSTIX_ETH1_RST_MD        (GPIO_GUMSTIX_ETH1_RST | GPIO_OUT)
-
-#define GPIO_GUMSTIX_ETH0               36
-#define GPIO_GUMSTIX_ETH0_MD            (GPIO_GUMSTIX_ETH0 | GPIO_IN)
-#define GUMSTIX_ETH0_IRQ                IRQ_GPIO(GPIO_GUMSTIX_ETH0)
-#define GPIO_GUMSTIX_ETH1               27
-#define GPIO_GUMSTIX_ETH1_MD            (GPIO_GUMSTIX_ETH1 | GPIO_IN)
-#define GUMSTIX_ETH1_IRQ                IRQ_GPIO(GPIO_GUMSTIX_ETH1)
-
-
-/* CF reset line */
-#define GPIO8_RESET                     8
-
-/* CF slot 0 */
-#define GPIO4_nBVD1                     4
-#define GPIO4_nSTSCHG                   GPIO4_nBVD1
-#define GPIO11_nCD                      11
-#define GPIO26_PRDY_nBSY                26
-#define GUMSTIX_S0_nSTSCHG_IRQ          IRQ_GPIO(GPIO4_nSTSCHG)
-#define GUMSTIX_S0_nCD_IRQ              IRQ_GPIO(GPIO11_nCD)
-#define GUMSTIX_S0_PRDY_nBSY_IRQ        IRQ_GPIO(GPIO26_PRDY_nBSY)
-
-/* CF slot 1 */
-#define GPIO18_nBVD1                    18
-#define GPIO18_nSTSCHG                  GPIO18_nBVD1
-#define GPIO36_nCD                      36
-#define GPIO27_PRDY_nBSY                27
-#define GUMSTIX_S1_nSTSCHG_IRQ          IRQ_GPIO(GPIO18_nSTSCHG)
-#define GUMSTIX_S1_nCD_IRQ              IRQ_GPIO(GPIO36_nCD)
-#define GUMSTIX_S1_PRDY_nBSY_IRQ        IRQ_GPIO(GPIO27_PRDY_nBSY)
-
-/* CF GPIO line modes */
-#define GPIO4_nSTSCHG_MD                (GPIO4_nSTSCHG | GPIO_IN)
-#define GPIO8_RESET_MD                  (GPIO8_RESET | GPIO_OUT)
-#define GPIO11_nCD_MD                   (GPIO11_nCD | GPIO_IN)
-#define GPIO18_nSTSCHG_MD               (GPIO18_nSTSCHG | GPIO_IN)
-#define GPIO26_PRDY_nBSY_MD             (GPIO26_PRDY_nBSY | GPIO_IN)
-#define GPIO27_PRDY_nBSY_MD             (GPIO27_PRDY_nBSY | GPIO_IN)
-#define GPIO36_nCD_MD                   (GPIO36_nCD | GPIO_IN)
diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h
deleted file mode 100644
index 979a45695d7d..000000000000
--- a/include/asm-arm/arch-pxa/hardware.h
+++ /dev/null
@@ -1,240 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-pxa/hardware.h
- *
- *  Author:     Nicolas Pitre
- *  Created:    Jun 15, 2001
- *  Copyright:  MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-/*
- * We requires absolute addresses.
- */
-#define PCIO_BASE               0
-
-/*
- * Workarounds for at least 2 errata so far require this.
- * The mapping is set in mach-pxa/generic.c.
- */
-#define UNCACHED_PHYS_0         0xff000000
-#define UNCACHED_ADDR           UNCACHED_PHYS_0
-
-/*
- * Intel PXA2xx internal register mapping:
- *
- * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
- * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
- * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
- * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
- * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
- * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
- * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
- *
- * Note that not all PXA2xx chips implement all those addresses, and the
- * kernel only maps the minimum needed range of this mapping.
- */
-#define io_p2v(x) (0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
-#define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
-
-#ifndef __ASSEMBLY__
-
-# define __REG(x)       (*((volatile u32 *)io_p2v(x)))
-
-/* With indexed regs we don't want to feed the index through io_p2v()
-   especially if it is a variable, otherwise horrible code will result. */
-# define __REG2(x,y)    \
-        (*(volatile u32 *)((u32)&__REG(x) + (y)))
-
-# define __PREG(x)      (io_v2p((u32)&(x)))
-
-#else
-
-# define __REG(x)       io_p2v(x)
-# define __PREG(x)      io_v2p(x)
-
-#endif
-
-#ifndef __ASSEMBLY__
-
-#ifdef CONFIG_PXA25x
-#define __cpu_is_pxa21x(id)                             \
-        ({                                              \
-                unsigned int _id = (id) >> 4 & 0xf3f;   \
-                _id == 0x212;                           \
-        })
-
-#define __cpu_is_pxa255(id)                             \
-        ({                                              \
-                unsigned int _id = (id) >> 4 & 0xfff;   \
-                _id == 0x2d0;                           \
-         })
-
-#define __cpu_is_pxa25x(id)                             \
-        ({                                              \
-                unsigned int _id = (id) >> 4 & 0xfff;   \
-                _id == 0x2d0 || _id == 0x290;           \
-        })
-#else
-#define __cpu_is_pxa21x(id)     (0)
-#define __cpu_is_pxa255(id)     (0)
-#define __cpu_is_pxa25x(id)     (0)
-#endif
-
-#ifdef CONFIG_PXA27x
-#define __cpu_is_pxa27x(id)                             \
-        ({                                              \
-                unsigned int _id = (id) >> 4 & 0xfff;   \
-                _id == 0x411;                           \
-        })
-#else
-#define __cpu_is_pxa27x(id)     (0)
-#endif
-
-#ifdef CONFIG_CPU_PXA300
-#define __cpu_is_pxa300(id)                             \
-        ({                                              \
-                unsigned int _id = (id) >> 4 & 0xfff;   \
-                _id == 0x688;                           \
-         })
-#else
-#define __cpu_is_pxa300(id)     (0)
-#endif
-
-#ifdef CONFIG_CPU_PXA310
-#define __cpu_is_pxa310(id)                             \
-        ({                                              \
-                unsigned int _id = (id) >> 4 & 0xfff;   \
-                _id == 0x689;                           \
-         })
-#else
-#define __cpu_is_pxa310(id)     (0)
-#endif
-
-#ifdef CONFIG_CPU_PXA320
-#define __cpu_is_pxa320(id)                             \
-        ({                                              \
-                unsigned int _id = (id) >> 4 & 0xfff;   \
-                _id == 0x603 || _id == 0x682;           \
-         })
-#else
-#define __cpu_is_pxa320(id)     (0)
-#endif
-
-#ifdef CONFIG_CPU_PXA930
-#define __cpu_is_pxa930(id)                             \
-        ({                                              \
-                unsigned int _id = (id) >> 4 & 0xfff;   \
-                _id == 0x683;           \
-         })
-#else
-#define __cpu_is_pxa930(id)     (0)
-#endif
-
-#define cpu_is_pxa21x()                                 \
-        ({                                              \
-                __cpu_is_pxa21x(read_cpuid_id());       \
-        })
-
-#define cpu_is_pxa255()                                 \
-        ({                                              \
-                __cpu_is_pxa255(read_cpuid_id());       \
-        })
-
-#define cpu_is_pxa25x()                                 \
-        ({                                              \
-                __cpu_is_pxa25x(read_cpuid_id());       \
-        })
-
-#define cpu_is_pxa27x()                                 \
-        ({                                              \
-                __cpu_is_pxa27x(read_cpuid_id());       \
-        })
-
-#define cpu_is_pxa300()                                 \
-        ({                                              \
-                __cpu_is_pxa300(read_cpuid_id());       \
-         })
-
-#define cpu_is_pxa310()                                 \
-        ({                                              \
-                __cpu_is_pxa310(read_cpuid_id());       \
-         })
-
-#define cpu_is_pxa320()                                 \
-        ({                                              \
-                __cpu_is_pxa320(read_cpuid_id());       \
-         })
-
-#define cpu_is_pxa930()                                 \
-        ({                                              \
-                unsigned int id = read_cpuid(CPUID_ID); \
-                __cpu_is_pxa930(id);                    \
-         })
-
-/*
- * CPUID Core Generation Bit
- * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
- * == 0x3 for pxa300/pxa310/pxa320
- */
-#define __cpu_is_pxa2xx(id)                             \
-        ({                                              \
-                unsigned int _id = (id) >> 13 & 0x7;    \
-                _id <= 0x2;                             \
-         })
-
-#define __cpu_is_pxa3xx(id)                             \
-        ({                                              \
-                unsigned int _id = (id) >> 13 & 0x7;    \
-                _id == 0x3;                             \
-         })
-
-#define cpu_is_pxa2xx()                                 \
-        ({                                              \
-                __cpu_is_pxa2xx(read_cpuid_id());       \
-         })
-
-#define cpu_is_pxa3xx()                                 \
-        ({                                              \
-                __cpu_is_pxa3xx(read_cpuid_id());       \
-         })
-
-/*
- * Handy routine to set GPIO alternate functions
- */
-extern int pxa_gpio_mode( int gpio_mode );
-
-/*
- * Return GPIO level, nonzero means high, zero is low
- */
-extern int pxa_gpio_get_value(unsigned gpio);
-
-/*
- * Set output GPIO level
- */
-extern void pxa_gpio_set_value(unsigned gpio, int value);
-
-/*
- * return current memory and LCD clock frequency in units of 10kHz
- */
-extern unsigned int get_memclk_frequency_10khz(void);
-
-/*
- * register GPIO as reset generator
- */
-extern int init_gpio_reset(int gpio);
-
-#endif
-
-#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
-#define PCIBIOS_MIN_IO          0
-#define PCIBIOS_MIN_MEM         0
-#define pcibios_assign_all_busses()     1
-#endif
-
-#endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-pxa/idp.h b/include/asm-arm/arch-pxa/idp.h
deleted file mode 100644
index 21aa8ac35c1c..000000000000
--- a/include/asm-arm/arch-pxa/idp.h
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-pxa/idp.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Copyright (c) 2001 Cliff Brake, Accelent Systems Inc.
- *
- * 2001-09-13: Cliff Brake <cbrake@accelent.com>
- *             Initial code
- *
- * 2005-02-15: Cliff Brake <cliff.brake@gmail.com>
- *             <http://www.vibren.com> <http://bec-systems.com>
- *             Changes for 2.6 kernel.
- */
-
-
-/*
- * Note: this file must be safe to include in assembly files
- *
- * Support for the Vibren PXA255 IDP requires rev04 or later
- * IDP hardware.
- */
-
-
-#define IDP_FLASH_PHYS          (PXA_CS0_PHYS)
-#define IDP_ALT_FLASH_PHYS      (PXA_CS1_PHYS)
-#define IDP_MEDIAQ_PHYS         (PXA_CS3_PHYS)
-#define IDP_IDE_PHYS            (PXA_CS5_PHYS + 0x03000000)
-#define IDP_ETH_PHYS            (PXA_CS5_PHYS + 0x03400000)
-#define IDP_COREVOLT_PHYS       (PXA_CS5_PHYS + 0x03800000)
-#define IDP_CPLD_PHYS           (PXA_CS5_PHYS + 0x03C00000)
-
-
-/*
- * virtual memory map
- */
-
-#define IDP_COREVOLT_VIRT       (0xf0000000)
-#define IDP_COREVOLT_SIZE       (1*1024*1024)
-
-#define IDP_CPLD_VIRT           (IDP_COREVOLT_VIRT + IDP_COREVOLT_SIZE)
-#define IDP_CPLD_SIZE           (1*1024*1024)
-
-#if (IDP_CPLD_VIRT + IDP_CPLD_SIZE) > 0xfc000000
-#error Your custom IO space is getting a bit large !!
-#endif
-
-#define CPLD_P2V(x)             ((x) - IDP_CPLD_PHYS + IDP_CPLD_VIRT)
-#define CPLD_V2P(x)             ((x) - IDP_CPLD_VIRT + IDP_CPLD_PHYS)
-
-#ifndef __ASSEMBLY__
-#  define __CPLD_REG(x)         (*((volatile unsigned long *)CPLD_P2V(x)))
-#else
-#  define __CPLD_REG(x)         CPLD_P2V(x)
-#endif
-
-/* board level registers in the CPLD: (offsets from CPLD_VIRT) */
-
-#define _IDP_CPLD_REV                   (IDP_CPLD_PHYS + 0x00)
-#define _IDP_CPLD_PERIPH_PWR            (IDP_CPLD_PHYS + 0x04)
-#define _IDP_CPLD_LED_CONTROL           (IDP_CPLD_PHYS + 0x08)
-#define _IDP_CPLD_KB_COL_HIGH           (IDP_CPLD_PHYS + 0x0C)
-#define _IDP_CPLD_KB_COL_LOW            (IDP_CPLD_PHYS + 0x10)
-#define _IDP_CPLD_PCCARD_EN             (IDP_CPLD_PHYS + 0x14)
-#define _IDP_CPLD_GPIOH_DIR             (IDP_CPLD_PHYS + 0x18)
-#define _IDP_CPLD_GPIOH_VALUE           (IDP_CPLD_PHYS + 0x1C)
-#define _IDP_CPLD_GPIOL_DIR             (IDP_CPLD_PHYS + 0x20)
-#define _IDP_CPLD_GPIOL_VALUE           (IDP_CPLD_PHYS + 0x24)
-#define _IDP_CPLD_PCCARD_PWR            (IDP_CPLD_PHYS + 0x28)
-#define _IDP_CPLD_MISC_CTRL             (IDP_CPLD_PHYS + 0x2C)
-#define _IDP_CPLD_LCD                   (IDP_CPLD_PHYS + 0x30)
-#define _IDP_CPLD_FLASH_WE              (IDP_CPLD_PHYS + 0x34)
-
-#define _IDP_CPLD_KB_ROW                (IDP_CPLD_PHYS + 0x50)
-#define _IDP_CPLD_PCCARD0_STATUS        (IDP_CPLD_PHYS + 0x54)
-#define _IDP_CPLD_PCCARD1_STATUS        (IDP_CPLD_PHYS + 0x58)
-#define _IDP_CPLD_MISC_STATUS           (IDP_CPLD_PHYS + 0x5C)
-
-/* FPGA register virtual addresses */
-
-#define IDP_CPLD_REV                    __CPLD_REG(_IDP_CPLD_REV)
-#define IDP_CPLD_PERIPH_PWR             __CPLD_REG(_IDP_CPLD_PERIPH_PWR)
-#define IDP_CPLD_LED_CONTROL            __CPLD_REG(_IDP_CPLD_LED_CONTROL)
-#define IDP_CPLD_KB_COL_HIGH            __CPLD_REG(_IDP_CPLD_KB_COL_HIGH)
-#define IDP_CPLD_KB_COL_LOW             __CPLD_REG(_IDP_CPLD_KB_COL_LOW)
-#define IDP_CPLD_PCCARD_EN              __CPLD_REG(_IDP_CPLD_PCCARD_EN)
-#define IDP_CPLD_GPIOH_DIR              __CPLD_REG(_IDP_CPLD_GPIOH_DIR)
-#define IDP_CPLD_GPIOH_VALUE            __CPLD_REG(_IDP_CPLD_GPIOH_VALUE)
-#define IDP_CPLD_GPIOL_DIR              __CPLD_REG(_IDP_CPLD_GPIOL_DIR)
-#define IDP_CPLD_GPIOL_VALUE            __CPLD_REG(_IDP_CPLD_GPIOL_VALUE)
-#define IDP_CPLD_PCCARD_PWR             __CPLD_REG(_IDP_CPLD_PCCARD_PWR)
-#define IDP_CPLD_MISC_CTRL              __CPLD_REG(_IDP_CPLD_MISC_CTRL)
-#define IDP_CPLD_LCD                    __CPLD_REG(_IDP_CPLD_LCD)
-#define IDP_CPLD_FLASH_WE               __CPLD_REG(_IDP_CPLD_FLASH_WE)
-
-#define IDP_CPLD_KB_ROW                 __CPLD_REG(_IDP_CPLD_KB_ROW)
-#define IDP_CPLD_PCCARD0_STATUS         __CPLD_REG(_IDP_CPLD_PCCARD0_STATUS)
-#define IDP_CPLD_PCCARD1_STATUS         __CPLD_REG(_IDP_CPLD_PCCARD1_STATUS)
-#define IDP_CPLD_MISC_STATUS            __CPLD_REG(_IDP_CPLD_MISC_STATUS)
-
-
-/*
- * Bit masks for various registers
- */
-
-// IDP_CPLD_PCCARD_PWR
-#define PCC0_PWR0       (1 << 0)
-#define PCC0_PWR1       (1 << 1)
-#define PCC0_PWR2       (1 << 2)
-#define PCC0_PWR3       (1 << 3)
-#define PCC1_PWR0       (1 << 4)
-#define PCC1_PWR1       (1 << 5)
-#define PCC1_PWR2       (1 << 6)
-#define PCC1_PWR3       (1 << 7)
-
-// IDP_CPLD_PCCARD_EN
-#define PCC0_RESET      (1 << 6)
-#define PCC1_RESET      (1 << 7)
-#define PCC0_ENABLE     (1 << 0)
-#define PCC1_ENABLE     (1 << 1)
-
-// IDP_CPLD_PCCARDx_STATUS
-#define _PCC_WRPROT     (1 << 7) // 7-4 read as low true
-#define _PCC_RESET      (1 << 6)
-#define _PCC_IRQ        (1 << 5)
-#define _PCC_INPACK     (1 << 4)
-#define PCC_BVD2        (1 << 3)
-#define PCC_BVD1        (1 << 2)
-#define PCC_VS2         (1 << 1)
-#define PCC_VS1         (1 << 0)
-
-#define PCC_DETECT(x)   (GPLR(7 + (x)) & GPIO_bit(7 + (x)))
-
-/* A listing of interrupts used by external hardware devices */
-
-#define TOUCH_PANEL_IRQ                 IRQ_GPIO(5)
-#define IDE_IRQ                         IRQ_GPIO(21)
-
-#define TOUCH_PANEL_IRQ_EDGE            IRQ_TYPE_EDGE_FALLING
-
-#define ETHERNET_IRQ                    IRQ_GPIO(4)
-#define ETHERNET_IRQ_EDGE               IRQ_TYPE_EDGE_RISING
-
-#define IDE_IRQ_EDGE                    IRQ_TYPE_EDGE_RISING
-
-#define PCMCIA_S0_CD_VALID              IRQ_GPIO(7)
-#define PCMCIA_S0_CD_VALID_EDGE         IRQ_TYPE_EDGE_BOTH
-
-#define PCMCIA_S1_CD_VALID              IRQ_GPIO(8)
-#define PCMCIA_S1_CD_VALID_EDGE         IRQ_TYPE_EDGE_BOTH
-
-#define PCMCIA_S0_RDYINT                IRQ_GPIO(19)
-#define PCMCIA_S1_RDYINT                IRQ_GPIO(22)
-
-
-/*
- * Macros for LED Driver
- */
-
-/* leds 0 = ON */
-#define IDP_HB_LED      (1<<5)
-#define IDP_BUSY_LED    (1<<6)
-
-#define IDP_LEDS_MASK   (IDP_HB_LED | IDP_BUSY_LED)
-
-/*
- * macros for MTD driver
- */
-
-#define FLASH_WRITE_PROTECT_DISABLE()   ((IDP_CPLD_FLASH_WE) &= ~(0x1))
-#define FLASH_WRITE_PROTECT_ENABLE()    ((IDP_CPLD_FLASH_WE) |= (0x1))
-
-/*
- * macros for matrix keyboard driver
- */
-
-#define KEYBD_MATRIX_NUMBER_INPUTS      7
-#define KEYBD_MATRIX_NUMBER_OUTPUTS     14
-
-#define KEYBD_MATRIX_INVERT_OUTPUT_LOGIC        FALSE
-#define KEYBD_MATRIX_INVERT_INPUT_LOGIC         FALSE
-
-#define KEYBD_MATRIX_SETTLING_TIME_US                   100
-#define KEYBD_MATRIX_KEYSTATE_DEBOUNCE_CONSTANT         2
-
-#define KEYBD_MATRIX_SET_OUTPUTS(outputs) \
-{\
-        IDP_CPLD_KB_COL_LOW = outputs;\
-        IDP_CPLD_KB_COL_HIGH = outputs >> 7;\
-}
-
-#define KEYBD_MATRIX_GET_INPUTS(inputs) \
-{\
-        inputs = (IDP_CPLD_KB_ROW & 0x7f);\
-}
-
-
diff --git a/include/asm-arm/arch-pxa/io.h b/include/asm-arm/arch-pxa/io.h
deleted file mode 100644
index af34e0f2f7dc..000000000000
--- a/include/asm-arm/arch-pxa/io.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * linux/include/asm-arm/arch-pxa/io.h
- *
- * Copied from asm/arch/sa1100/io.h
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#include <asm/arch/hardware.h>
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/*
- * We don't actually have real ISA nor PCI buses, but there is so many
- * drivers out there that might just work if we fake them...
- */
-#define __io(a)                 ((void __iomem *)(a))
-#define __mem_pci(a)            (a)
-
-#endif
diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h
deleted file mode 100644
index 9413121b0ed9..000000000000
--- a/include/asm-arm/arch-pxa/irqs.h
+++ /dev/null
@@ -1,264 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-pxa/irqs.h
- *
- *  Author:     Nicolas Pitre
- *  Created:    Jun 15, 2001
- *  Copyright:  MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-
-#define PXA_IRQ(x)      (x)
-
-#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
-#define IRQ_SSP3        PXA_IRQ(0)      /* SSP3 service request */
-#define IRQ_MSL         PXA_IRQ(1)      /* MSL Interface interrupt */
-#define IRQ_USBH2       PXA_IRQ(2)      /* USB Host interrupt 1 (OHCI) */
-#define IRQ_USBH1       PXA_IRQ(3)      /* USB Host interrupt 2 (non-OHCI) */
-#define IRQ_KEYPAD      PXA_IRQ(4)      /* Key pad controller */
-#define IRQ_MEMSTK      PXA_IRQ(5)      /* Memory Stick interrupt */
-#define IRQ_PWRI2C      PXA_IRQ(6)      /* Power I2C interrupt */
-#endif
-
-#define IRQ_HWUART      PXA_IRQ(7)      /* HWUART Transmit/Receive/Error (PXA26x) */
-#define IRQ_OST_4_11    PXA_IRQ(7)      /* OS timer 4-11 matches (PXA27x) */
-#define IRQ_GPIO0       PXA_IRQ(8)      /* GPIO0 Edge Detect */
-#define IRQ_GPIO1       PXA_IRQ(9)      /* GPIO1 Edge Detect */
-#define IRQ_GPIO_2_x    PXA_IRQ(10)     /* GPIO[2-x] Edge Detect */
-#define IRQ_USB         PXA_IRQ(11)     /* USB Service */
-#define IRQ_PMU         PXA_IRQ(12)     /* Performance Monitoring Unit */
-#define IRQ_I2S         PXA_IRQ(13)     /* I2S Interrupt */
-#define IRQ_AC97        PXA_IRQ(14)     /* AC97 Interrupt */
-#define IRQ_ASSP        PXA_IRQ(15)     /* Audio SSP Service Request (PXA25x) */
-#define IRQ_USIM        PXA_IRQ(15)     /* Smart Card interface interrupt (PXA27x) */
-#define IRQ_NSSP        PXA_IRQ(16)     /* Network SSP Service Request (PXA25x) */
-#define IRQ_SSP2        PXA_IRQ(16)     /* SSP2 interrupt (PXA27x) */
-#define IRQ_LCD         PXA_IRQ(17)     /* LCD Controller Service Request */
-#define IRQ_I2C         PXA_IRQ(18)     /* I2C Service Request */
-#define IRQ_ICP         PXA_IRQ(19)     /* ICP Transmit/Receive/Error */
-#define IRQ_STUART      PXA_IRQ(20)     /* STUART Transmit/Receive/Error */
-#define IRQ_BTUART      PXA_IRQ(21)     /* BTUART Transmit/Receive/Error */
-#define IRQ_FFUART      PXA_IRQ(22)     /* FFUART Transmit/Receive/Error*/
-#define IRQ_MMC         PXA_IRQ(23)     /* MMC Status/Error Detection */
-#define IRQ_SSP         PXA_IRQ(24)     /* SSP Service Request */
-#define IRQ_DMA         PXA_IRQ(25)     /* DMA Channel Service Request */
-#define IRQ_OST0        PXA_IRQ(26)     /* OS Timer match 0 */
-#define IRQ_OST1        PXA_IRQ(27)     /* OS Timer match 1 */
-#define IRQ_OST2        PXA_IRQ(28)     /* OS Timer match 2 */
-#define IRQ_OST3        PXA_IRQ(29)     /* OS Timer match 3 */
-#define IRQ_RTC1Hz      PXA_IRQ(30)     /* RTC HZ Clock Tick */
-#define IRQ_RTCAlrm     PXA_IRQ(31)     /* RTC Alarm */
-
-#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
-#define IRQ_TPM         PXA_IRQ(32)     /* TPM interrupt */
-#define IRQ_CAMERA      PXA_IRQ(33)     /* Camera Interface */
-#endif
-
-#ifdef CONFIG_PXA3xx
-#define IRQ_SSP4        PXA_IRQ(13)     /* SSP4 service request */
-#define IRQ_CIR         PXA_IRQ(34)     /* Consumer IR */
-#define IRQ_TSI         PXA_IRQ(36)     /* Touch Screen Interface (PXA320) */
-#define IRQ_USIM2       PXA_IRQ(38)     /* USIM2 Controller */
-#define IRQ_GRPHICS     PXA_IRQ(39)     /* Graphics Controller */
-#define IRQ_MMC2        PXA_IRQ(41)     /* MMC2 Controller */
-#define IRQ_1WIRE       PXA_IRQ(44)     /* 1-Wire Controller */
-#define IRQ_NAND        PXA_IRQ(45)     /* NAND Controller */
-#define IRQ_USB2        PXA_IRQ(46)     /* USB 2.0 Device Controller */
-#define IRQ_WAKEUP0     PXA_IRQ(49)     /* EXT_WAKEUP0 */
-#define IRQ_WAKEUP1     PXA_IRQ(50)     /* EXT_WAKEUP1 */
-#define IRQ_DMEMC       PXA_IRQ(51)     /* Dynamic Memory Controller */
-#define IRQ_MMC3        PXA_IRQ(55)     /* MMC3 Controller (PXA310) */
-#endif
-
-#define PXA_GPIO_IRQ_BASE       (64)
-#define PXA_GPIO_IRQ_NUM        (128)
-
-#define GPIO_2_x_TO_IRQ(x)      (PXA_GPIO_IRQ_BASE + (x))
-#define IRQ_GPIO(x)     (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x))
-
-#define IRQ_TO_GPIO_2_x(i)      ((i) - PXA_GPIO_IRQ_BASE)
-#define IRQ_TO_GPIO(i)  (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i))
-
-/*
- * The next 16 interrupts are for board specific purposes.  Since
- * the kernel can only run on one machine at a time, we can re-use
- * these.  If you need more, increase IRQ_BOARD_END, but keep it
- * within sensible limits.
- */
-#define IRQ_BOARD_START         (PXA_GPIO_IRQ_BASE + PXA_GPIO_IRQ_NUM)
-#define IRQ_BOARD_END           (IRQ_BOARD_START + 16)
-
-#define IRQ_SA1111_START        (IRQ_BOARD_END)
-#define IRQ_GPAIN0              (IRQ_BOARD_END + 0)
-#define IRQ_GPAIN1              (IRQ_BOARD_END + 1)
-#define IRQ_GPAIN2              (IRQ_BOARD_END + 2)
-#define IRQ_GPAIN3              (IRQ_BOARD_END + 3)
-#define IRQ_GPBIN0              (IRQ_BOARD_END + 4)
-#define IRQ_GPBIN1              (IRQ_BOARD_END + 5)
-#define IRQ_GPBIN2              (IRQ_BOARD_END + 6)
-#define IRQ_GPBIN3              (IRQ_BOARD_END + 7)
-#define IRQ_GPBIN4              (IRQ_BOARD_END + 8)
-#define IRQ_GPBIN5              (IRQ_BOARD_END + 9)
-#define IRQ_GPCIN0              (IRQ_BOARD_END + 10)
-#define IRQ_GPCIN1              (IRQ_BOARD_END + 11)
-#define IRQ_GPCIN2              (IRQ_BOARD_END + 12)
-#define IRQ_GPCIN3              (IRQ_BOARD_END + 13)
-#define IRQ_GPCIN4              (IRQ_BOARD_END + 14)
-#define IRQ_GPCIN5              (IRQ_BOARD_END + 15)
-#define IRQ_GPCIN6              (IRQ_BOARD_END + 16)
-#define IRQ_GPCIN7              (IRQ_BOARD_END + 17)
-#define IRQ_MSTXINT             (IRQ_BOARD_END + 18)
-#define IRQ_MSRXINT             (IRQ_BOARD_END + 19)
-#define IRQ_MSSTOPERRINT        (IRQ_BOARD_END + 20)
-#define IRQ_TPTXINT             (IRQ_BOARD_END + 21)
-#define IRQ_TPRXINT             (IRQ_BOARD_END + 22)
-#define IRQ_TPSTOPERRINT        (IRQ_BOARD_END + 23)
-#define SSPXMTINT               (IRQ_BOARD_END + 24)
-#define SSPRCVINT               (IRQ_BOARD_END + 25)
-#define SSPROR                  (IRQ_BOARD_END + 26)
-#define AUDXMTDMADONEA          (IRQ_BOARD_END + 32)
-#define AUDRCVDMADONEA          (IRQ_BOARD_END + 33)
-#define AUDXMTDMADONEB          (IRQ_BOARD_END + 34)
-#define AUDRCVDMADONEB          (IRQ_BOARD_END + 35)
-#define AUDTFSR                 (IRQ_BOARD_END + 36)
-#define AUDRFSR                 (IRQ_BOARD_END + 37)
-#define AUDTUR                  (IRQ_BOARD_END + 38)
-#define AUDROR                  (IRQ_BOARD_END + 39)
-#define AUDDTS                  (IRQ_BOARD_END + 40)
-#define AUDRDD                  (IRQ_BOARD_END + 41)
-#define AUDSTO                  (IRQ_BOARD_END + 42)
-#define IRQ_USBPWR              (IRQ_BOARD_END + 43)
-#define IRQ_HCIM                (IRQ_BOARD_END + 44)
-#define IRQ_HCIBUFFACC          (IRQ_BOARD_END + 45)
-#define IRQ_HCIRMTWKP           (IRQ_BOARD_END + 46)
-#define IRQ_NHCIMFCIR           (IRQ_BOARD_END + 47)
-#define IRQ_USB_PORT_RESUME     (IRQ_BOARD_END + 48)
-#define IRQ_S0_READY_NINT       (IRQ_BOARD_END + 49)
-#define IRQ_S1_READY_NINT       (IRQ_BOARD_END + 50)
-#define IRQ_S0_CD_VALID         (IRQ_BOARD_END + 51)
-#define IRQ_S1_CD_VALID         (IRQ_BOARD_END + 52)
-#define IRQ_S0_BVD1_STSCHG      (IRQ_BOARD_END + 53)
-#define IRQ_S1_BVD1_STSCHG      (IRQ_BOARD_END + 54)
-
-#define IRQ_LOCOMO_START        (IRQ_BOARD_END)
-#define IRQ_LOCOMO_KEY          (IRQ_BOARD_END + 0)
-#define IRQ_LOCOMO_GPIO0        (IRQ_BOARD_END + 1)
-#define IRQ_LOCOMO_GPIO1        (IRQ_BOARD_END + 2)
-#define IRQ_LOCOMO_GPIO2        (IRQ_BOARD_END + 3)
-#define IRQ_LOCOMO_GPIO3        (IRQ_BOARD_END + 4)
-#define IRQ_LOCOMO_GPIO4        (IRQ_BOARD_END + 5)
-#define IRQ_LOCOMO_GPIO5        (IRQ_BOARD_END + 6)
-#define IRQ_LOCOMO_GPIO6        (IRQ_BOARD_END + 7)
-#define IRQ_LOCOMO_GPIO7        (IRQ_BOARD_END + 8)
-#define IRQ_LOCOMO_GPIO8        (IRQ_BOARD_END + 9)
-#define IRQ_LOCOMO_GPIO9        (IRQ_BOARD_END + 10)
-#define IRQ_LOCOMO_GPIO10       (IRQ_BOARD_END + 11)
-#define IRQ_LOCOMO_GPIO11       (IRQ_BOARD_END + 12)
-#define IRQ_LOCOMO_GPIO12       (IRQ_BOARD_END + 13)
-#define IRQ_LOCOMO_GPIO13       (IRQ_BOARD_END + 14)
-#define IRQ_LOCOMO_GPIO14       (IRQ_BOARD_END + 15)
-#define IRQ_LOCOMO_GPIO15       (IRQ_BOARD_END + 16)
-#define IRQ_LOCOMO_LT           (IRQ_BOARD_END + 17)
-#define IRQ_LOCOMO_SPI_RFR      (IRQ_BOARD_END + 18)
-#define IRQ_LOCOMO_SPI_RFW      (IRQ_BOARD_END + 19)
-#define IRQ_LOCOMO_SPI_OVRN     (IRQ_BOARD_END + 20)
-#define IRQ_LOCOMO_SPI_TEND     (IRQ_BOARD_END + 21)
-
-/*
- * Figure out the MAX IRQ number.
- *
- * If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1.
- * If we have an LoCoMo, the max IRQ is IRQ_LOCOMO_SPI_TEND+1
- * Otherwise, we have the standard IRQs only.
- */
-#ifdef CONFIG_SA1111
-#define NR_IRQS                 (IRQ_S1_BVD1_STSCHG + 1)
-#elif defined(CONFIG_SHARP_LOCOMO)
-#define NR_IRQS                 (IRQ_LOCOMO_SPI_TEND + 1)
-#elif defined(CONFIG_ARCH_LUBBOCK) || \
-      defined(CONFIG_MACH_LOGICPD_PXA270) || \
-      defined(CONFIG_MACH_TOSA) || \
-      defined(CONFIG_MACH_MAINSTONE) || \
-      defined(CONFIG_MACH_PCM027) || \
-      defined(CONFIG_MACH_MAGICIAN)
-#define NR_IRQS                 (IRQ_BOARD_END)
-#elif defined(CONFIG_MACH_ZYLONITE)
-#define NR_IRQS                 (IRQ_BOARD_START + 32)
-#else
-#define NR_IRQS                 (IRQ_BOARD_START)
-#endif
-
-/*
- * Board specific IRQs.  Define them here.
- * Do not surround them with ifdefs.
- */
-#define LUBBOCK_IRQ(x)          (IRQ_BOARD_START + (x))
-#define LUBBOCK_SD_IRQ          LUBBOCK_IRQ(0)
-#define LUBBOCK_SA1111_IRQ      LUBBOCK_IRQ(1)
-#define LUBBOCK_USB_IRQ         LUBBOCK_IRQ(2)  /* usb connect */
-#define LUBBOCK_ETH_IRQ         LUBBOCK_IRQ(3)
-#define LUBBOCK_UCB1400_IRQ     LUBBOCK_IRQ(4)
-#define LUBBOCK_BB_IRQ          LUBBOCK_IRQ(5)
-#define LUBBOCK_USB_DISC_IRQ    LUBBOCK_IRQ(6)  /* usb disconnect */
-#define LUBBOCK_LAST_IRQ        LUBBOCK_IRQ(6)
-
-#define LPD270_IRQ(x)           (IRQ_BOARD_START + (x))
-#define LPD270_USBC_IRQ         LPD270_IRQ(2)
-#define LPD270_ETHERNET_IRQ     LPD270_IRQ(3)
-#define LPD270_AC97_IRQ         LPD270_IRQ(4)
-
-#define MAINSTONE_IRQ(x)        (IRQ_BOARD_START + (x))
-#define MAINSTONE_MMC_IRQ       MAINSTONE_IRQ(0)
-#define MAINSTONE_USIM_IRQ      MAINSTONE_IRQ(1)
-#define MAINSTONE_USBC_IRQ      MAINSTONE_IRQ(2)
-#define MAINSTONE_ETHERNET_IRQ  MAINSTONE_IRQ(3)
-#define MAINSTONE_AC97_IRQ      MAINSTONE_IRQ(4)
-#define MAINSTONE_PEN_IRQ       MAINSTONE_IRQ(5)
-#define MAINSTONE_MSINS_IRQ     MAINSTONE_IRQ(6)
-#define MAINSTONE_EXBRD_IRQ     MAINSTONE_IRQ(7)
-#define MAINSTONE_S0_CD_IRQ     MAINSTONE_IRQ(9)
-#define MAINSTONE_S0_STSCHG_IRQ MAINSTONE_IRQ(10)
-#define MAINSTONE_S0_IRQ        MAINSTONE_IRQ(11)
-#define MAINSTONE_S1_CD_IRQ     MAINSTONE_IRQ(13)
-#define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14)
-#define MAINSTONE_S1_IRQ        MAINSTONE_IRQ(15)
-
-/* LoCoMo Interrupts (CONFIG_SHARP_LOCOMO) */
-#define IRQ_LOCOMO_KEY_BASE     (IRQ_BOARD_START + 0)
-#define IRQ_LOCOMO_GPIO_BASE    (IRQ_BOARD_START + 1)
-#define IRQ_LOCOMO_LT_BASE      (IRQ_BOARD_START + 2)
-#define IRQ_LOCOMO_SPI_BASE     (IRQ_BOARD_START + 3)
-
-/* phyCORE-PXA270 (PCM027) Interrupts */
-#define PCM027_IRQ(x)          (IRQ_BOARD_START + (x))
-#define PCM027_BTDET_IRQ       PCM027_IRQ(0)
-#define PCM027_FF_RI_IRQ       PCM027_IRQ(1)
-#define PCM027_MMCDET_IRQ      PCM027_IRQ(2)
-#define PCM027_PM_5V_IRQ       PCM027_IRQ(3)
-
-/* ITE8152 irqs */
-/* add IT8152 IRQs beyond BOARD_END */
-#ifdef CONFIG_PCI_HOST_ITE8152
-#define IT8152_IRQ(x)   (IRQ_BOARD_END + (x))
-
-/* IRQ-sources in 3 groups - local devices, LPC (serial), and external PCI */
-#define IT8152_LD_IRQ_COUNT     9
-#define IT8152_LP_IRQ_COUNT     16
-#define IT8152_PD_IRQ_COUNT     15
-
-/* Priorities: */
-#define IT8152_PD_IRQ(i)        IT8152_IRQ(i)
-#define IT8152_LP_IRQ(i)        (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT)
-#define IT8152_LD_IRQ(i)        (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT + IT8152_LP_IRQ_COUNT)
-
-#define IT8152_LAST_IRQ         IT8152_LD_IRQ(IT8152_LD_IRQ_COUNT - 1)
-
-#if NR_IRQS < (IT8152_LAST_IRQ+1)
-#undef NR_IRQS
-#define NR_IRQS (IT8152_LAST_IRQ+1)
-#endif
-
-#endif /* CONFIG_PCI_HOST_ITE8152 */
diff --git a/include/asm-arm/arch-pxa/lpd270.h b/include/asm-arm/arch-pxa/lpd270.h
deleted file mode 100644
index 501d240ac120..000000000000
--- a/include/asm-arm/arch-pxa/lpd270.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * include/asm-arm/arch-pxa/lpd270.h
- *
- * Author:      Lennert Buytenhek
- * Created:     Feb 10, 2006
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_LPD270_H
-#define __ASM_ARCH_LPD270_H
-
-#define LPD270_CPLD_PHYS        PXA_CS2_PHYS
-#define LPD270_CPLD_VIRT        0xf0000000
-#define LPD270_CPLD_SIZE        0x00100000
-
-#define LPD270_ETH_PHYS         (PXA_CS2_PHYS + 0x01000000)
-
-/* CPLD registers  */
-#define LPD270_CPLD_REG(x)      ((unsigned long)(LPD270_CPLD_VIRT + (x)))
-#define LPD270_CONTROL          LPD270_CPLD_REG(0x00)
-#define LPD270_PERIPHERAL0      LPD270_CPLD_REG(0x04)
-#define LPD270_PERIPHERAL1      LPD270_CPLD_REG(0x08)
-#define LPD270_CPLD_REVISION    LPD270_CPLD_REG(0x14)
-#define LPD270_EEPROM_SPI_ITF   LPD270_CPLD_REG(0x20)
-#define LPD270_MODE_PINS        LPD270_CPLD_REG(0x24)
-#define LPD270_EGPIO            LPD270_CPLD_REG(0x30)
-#define LPD270_INT_MASK         LPD270_CPLD_REG(0x40)
-#define LPD270_INT_STATUS       LPD270_CPLD_REG(0x50)
-
-#define LPD270_INT_AC97         (1 << 4)  /* AC'97 CODEC IRQ */
-#define LPD270_INT_ETHERNET     (1 << 3)  /* Ethernet controller IRQ */
-#define LPD270_INT_USBC         (1 << 2)  /* USB client cable detection IRQ */
-
-
-#endif
diff --git a/include/asm-arm/arch-pxa/lubbock.h b/include/asm-arm/arch-pxa/lubbock.h
deleted file mode 100644
index 11ee73593fc3..000000000000
--- a/include/asm-arm/arch-pxa/lubbock.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-pxa/lubbock.h
- *
- *  Author:     Nicolas Pitre
- *  Created:    Jun 15, 2001
- *  Copyright:  MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#define LUBBOCK_ETH_PHYS        PXA_CS3_PHYS
-
-#define LUBBOCK_FPGA_PHYS       PXA_CS2_PHYS
-#define LUBBOCK_FPGA_VIRT       (0xf0000000)
-#define LUB_P2V(x)              ((x) - LUBBOCK_FPGA_PHYS + LUBBOCK_FPGA_VIRT)
-#define LUB_V2P(x)              ((x) - LUBBOCK_FPGA_VIRT + LUBBOCK_FPGA_PHYS)
-
-#ifndef __ASSEMBLY__
-#  define __LUB_REG(x)          (*((volatile unsigned long *)LUB_P2V(x)))
-#else
-#  define __LUB_REG(x)          LUB_P2V(x)
-#endif
-
-/* FPGA register virtual addresses */
-#define LUB_WHOAMI              __LUB_REG(LUBBOCK_FPGA_PHYS + 0x000)
-#define LUB_HEXLED              __LUB_REG(LUBBOCK_FPGA_PHYS + 0x010)
-#define LUB_DISC_BLNK_LED       __LUB_REG(LUBBOCK_FPGA_PHYS + 0x040)
-#define LUB_CONF_SWITCHES       __LUB_REG(LUBBOCK_FPGA_PHYS + 0x050)
-#define LUB_USER_SWITCHES       __LUB_REG(LUBBOCK_FPGA_PHYS + 0x060)
-#define LUB_MISC_WR             __LUB_REG(LUBBOCK_FPGA_PHYS + 0x080)
-#define LUB_MISC_RD             __LUB_REG(LUBBOCK_FPGA_PHYS + 0x090)
-#define LUB_IRQ_MASK_EN         __LUB_REG(LUBBOCK_FPGA_PHYS + 0x0c0)
-#define LUB_IRQ_SET_CLR         __LUB_REG(LUBBOCK_FPGA_PHYS + 0x0d0)
-#define LUB_GP                  __LUB_REG(LUBBOCK_FPGA_PHYS + 0x100)
-
-#ifndef __ASSEMBLY__
-extern void lubbock_set_misc_wr(unsigned int mask, unsigned int set);
-#endif
diff --git a/include/asm-arm/arch-pxa/magician.h b/include/asm-arm/arch-pxa/magician.h
deleted file mode 100644
index 169b374f9921..000000000000
--- a/include/asm-arm/arch-pxa/magician.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * GPIO and IRQ definitions for HTC Magician PDA phones
- *
- * Copyright (c) 2007 Philipp Zabel
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef _MAGICIAN_H_
-#define _MAGICIAN_H_
-
-#include <asm/arch/irqs.h>
-
-/*
- * PXA GPIOs
- */
-
-#define GPIO0_MAGICIAN_KEY_POWER                0
-#define GPIO9_MAGICIAN_UNKNOWN                  9
-#define GPIO10_MAGICIAN_GSM_IRQ                 10
-#define GPIO11_MAGICIAN_GSM_OUT1                11
-#define GPIO13_MAGICIAN_CPLD_IRQ                13
-#define GPIO18_MAGICIAN_UNKNOWN                 18
-#define GPIO22_MAGICIAN_VIBRA_EN                22
-#define GPIO26_MAGICIAN_GSM_POWER               26
-#define GPIO27_MAGICIAN_USBC_PUEN               27
-#define GPIO30_MAGICIAN_nCHARGE_EN              30
-#define GPIO37_MAGICIAN_KEY_HANGUP              37
-#define GPIO38_MAGICIAN_KEY_CONTACTS            38
-#define GPIO40_MAGICIAN_GSM_OUT2                40
-#define GPIO48_MAGICIAN_UNKNOWN                 48
-#define GPIO56_MAGICIAN_UNKNOWN                 56
-#define GPIO57_MAGICIAN_CAM_RESET               57
-#define GPIO75_MAGICIAN_SAMSUNG_POWER           75
-#define GPIO83_MAGICIAN_nIR_EN                  83
-#define GPIO86_MAGICIAN_GSM_RESET               86
-#define GPIO87_MAGICIAN_GSM_SELECT              87
-#define GPIO90_MAGICIAN_KEY_CALENDAR            90
-#define GPIO91_MAGICIAN_KEY_CAMERA              91
-#define GPIO93_MAGICIAN_KEY_UP                  93
-#define GPIO94_MAGICIAN_KEY_DOWN                94
-#define GPIO95_MAGICIAN_KEY_LEFT                95
-#define GPIO96_MAGICIAN_KEY_RIGHT               96
-#define GPIO97_MAGICIAN_KEY_ENTER               97
-#define GPIO98_MAGICIAN_KEY_RECORD              98
-#define GPIO99_MAGICIAN_HEADPHONE_IN            99
-#define GPIO100_MAGICIAN_KEY_VOL_UP             100
-#define GPIO101_MAGICIAN_KEY_VOL_DOWN           101
-#define GPIO102_MAGICIAN_KEY_PHONE              102
-#define GPIO103_MAGICIAN_LED_KP                 103
-#define GPIO104_MAGICIAN_LCD_POWER_1            104
-#define GPIO105_MAGICIAN_LCD_POWER_2            105
-#define GPIO106_MAGICIAN_LCD_POWER_3            106
-#define GPIO107_MAGICIAN_DS1WM_IRQ              107
-#define GPIO108_MAGICIAN_GSM_READY              108
-#define GPIO114_MAGICIAN_UNKNOWN                114
-#define GPIO115_MAGICIAN_nPEN_IRQ               115
-#define GPIO116_MAGICIAN_nCAM_EN                116
-#define GPIO119_MAGICIAN_UNKNOWN                119
-#define GPIO120_MAGICIAN_UNKNOWN                120
-
-/*
- * CPLD IRQs
- */
-
-#define IRQ_MAGICIAN_SD         (IRQ_BOARD_START + 0)
-#define IRQ_MAGICIAN_EP         (IRQ_BOARD_START + 1)
-#define IRQ_MAGICIAN_BT         (IRQ_BOARD_START + 2)
-#define IRQ_MAGICIAN_AC         (IRQ_BOARD_START + 3)
-
-/*
- * CPLD EGPIOs
- */
-
-#define MAGICIAN_EGPIO_BASE                     0x80 /* GPIO_BOARD_START */
-#define MAGICIAN_EGPIO(reg,bit) \
-        (MAGICIAN_EGPIO_BASE + 8*reg + bit)
-
-/* output */
-
-#define EGPIO_MAGICIAN_TOPPOLY_POWER            MAGICIAN_EGPIO(0, 2)
-#define EGPIO_MAGICIAN_LED_POWER                MAGICIAN_EGPIO(0, 5)
-#define EGPIO_MAGICIAN_GSM_RESET                MAGICIAN_EGPIO(0, 6)
-#define EGPIO_MAGICIAN_LCD_POWER                MAGICIAN_EGPIO(0, 7)
-#define EGPIO_MAGICIAN_SPK_POWER                MAGICIAN_EGPIO(1, 0)
-#define EGPIO_MAGICIAN_EP_POWER                 MAGICIAN_EGPIO(1, 1)
-#define EGPIO_MAGICIAN_IN_SEL0                  MAGICIAN_EGPIO(1, 2)
-#define EGPIO_MAGICIAN_IN_SEL1                  MAGICIAN_EGPIO(1, 3)
-#define EGPIO_MAGICIAN_MIC_POWER                MAGICIAN_EGPIO(1, 4)
-#define EGPIO_MAGICIAN_CODEC_RESET              MAGICIAN_EGPIO(1, 5)
-#define EGPIO_MAGICIAN_CODEC_POWER              MAGICIAN_EGPIO(1, 6)
-#define EGPIO_MAGICIAN_BL_POWER                 MAGICIAN_EGPIO(1, 7)
-#define EGPIO_MAGICIAN_SD_POWER                 MAGICIAN_EGPIO(2, 0)
-#define EGPIO_MAGICIAN_CARKIT_MIC               MAGICIAN_EGPIO(2, 1)
-#define EGPIO_MAGICIAN_UNKNOWN_WAVEDEV_DLL      MAGICIAN_EGPIO(2, 2)
-#define EGPIO_MAGICIAN_FLASH_VPP                MAGICIAN_EGPIO(2, 3)
-#define EGPIO_MAGICIAN_BL_POWER2                MAGICIAN_EGPIO(2, 4)
-#define EGPIO_MAGICIAN_CHARGE_EN                MAGICIAN_EGPIO(2, 5)
-#define EGPIO_MAGICIAN_GSM_POWER                MAGICIAN_EGPIO(2, 7)
-
-/* input */
-
-#define EGPIO_MAGICIAN_CABLE_STATE_AC           MAGICIAN_EGPIO(4, 0)
-#define EGPIO_MAGICIAN_CABLE_STATE_USB          MAGICIAN_EGPIO(4, 1)
-
-#define EGPIO_MAGICIAN_BOARD_ID0                MAGICIAN_EGPIO(5, 0)
-#define EGPIO_MAGICIAN_BOARD_ID1                MAGICIAN_EGPIO(5, 1)
-#define EGPIO_MAGICIAN_BOARD_ID2                MAGICIAN_EGPIO(5, 2)
-#define EGPIO_MAGICIAN_LCD_SELECT               MAGICIAN_EGPIO(5, 3)
-#define EGPIO_MAGICIAN_nSD_READONLY             MAGICIAN_EGPIO(5, 4)
-
-#define EGPIO_MAGICIAN_EP_INSERT                MAGICIAN_EGPIO(6, 1)
-
-#endif /* _MAGICIAN_H_ */
diff --git a/include/asm-arm/arch-pxa/mainstone.h b/include/asm-arm/arch-pxa/mainstone.h
deleted file mode 100644
index 14c862adcaa1..000000000000
--- a/include/asm-arm/arch-pxa/mainstone.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-pxa/mainstone.h
- *
- *  Author:     Nicolas Pitre
- *  Created:    Nov 14, 2002
- *  Copyright:  MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef ASM_ARCH_MAINSTONE_H
-#define ASM_ARCH_MAINSTONE_H
-
-#define MST_ETH_PHYS            PXA_CS4_PHYS
-
-#define MST_FPGA_PHYS           PXA_CS2_PHYS
-#define MST_FPGA_VIRT           (0xf0000000)
-#define MST_P2V(x)              ((x) - MST_FPGA_PHYS + MST_FPGA_VIRT)
-#define MST_V2P(x)              ((x) - MST_FPGA_VIRT + MST_FPGA_PHYS)
-
-#ifndef __ASSEMBLY__
-# define __MST_REG(x)           (*((volatile unsigned long *)MST_P2V(x)))
-#else
-# define __MST_REG(x)           MST_P2V(x)
-#endif
-
-/* board level registers in the FPGA */
-
-#define MST_LEDDAT1             __MST_REG(0x08000010)
-#define MST_LEDDAT2             __MST_REG(0x08000014)
-#define MST_LEDCTRL             __MST_REG(0x08000040)
-#define MST_GPSWR               __MST_REG(0x08000060)
-#define MST_MSCWR1              __MST_REG(0x08000080)
-#define MST_MSCWR2              __MST_REG(0x08000084)
-#define MST_MSCWR3              __MST_REG(0x08000088)
-#define MST_MSCRD               __MST_REG(0x08000090)
-#define MST_INTMSKENA           __MST_REG(0x080000c0)
-#define MST_INTSETCLR           __MST_REG(0x080000d0)
-#define MST_PCMCIA0             __MST_REG(0x080000e0)
-#define MST_PCMCIA1             __MST_REG(0x080000e4)
-
-#define MST_MSCWR1_CAMERA_ON    (1 << 15)  /* Camera interface power control */
-#define MST_MSCWR1_CAMERA_SEL   (1 << 14)  /* Camera interface mux control */
-#define MST_MSCWR1_LCD_CTL      (1 << 13)  /* General-purpose LCD control */
-#define MST_MSCWR1_MS_ON        (1 << 12)  /* Memory Stick power control */
-#define MST_MSCWR1_MMC_ON       (1 << 11)  /* MultiMediaCard* power control */
-#define MST_MSCWR1_MS_SEL       (1 << 10)  /* SD/MS multiplexer control */
-#define MST_MSCWR1_BB_SEL       (1 << 9)   /* PCMCIA/Baseband multiplexer */
-#define MST_MSCWR1_BT_ON        (1 << 8)   /* Bluetooth UART transceiver */
-#define MST_MSCWR1_BTDTR        (1 << 7)   /* Bluetooth UART DTR */
-
-#define MST_MSCWR1_IRDA_MASK    (3 << 5)   /* IrDA transceiver mode */
-#define MST_MSCWR1_IRDA_FULL    (0 << 5)   /* full distance power */
-#define MST_MSCWR1_IRDA_OFF     (1 << 5)   /* shutdown */
-#define MST_MSCWR1_IRDA_MED     (2 << 5)   /* 2/3 distance power */
-#define MST_MSCWR1_IRDA_LOW     (3 << 5)   /* 1/3 distance power */
-
-#define MST_MSCWR1_IRDA_FIR     (1 << 4)   /* IrDA transceiver SIR/FIR */
-#define MST_MSCWR1_GREENLED     (1 << 3)   /* LED D1 control */
-#define MST_MSCWR1_PDC_CTL      (1 << 2)   /* reserved */
-#define MST_MSCWR1_MTR_ON       (1 << 1)   /* Silent alert motor */
-#define MST_MSCWR1_SYSRESET     (1 << 0)   /* System reset */
-
-#define MST_MSCWR2_USB_OTG_RST  (1 << 6)   /* USB On The Go reset */
-#define MST_MSCWR2_USB_OTG_SEL  (1 << 5)   /* USB On The Go control */
-#define MST_MSCWR2_nUSBC_SC     (1 << 4)   /* USB client soft connect control */
-#define MST_MSCWR2_I2S_SPKROFF  (1 << 3)   /* I2S CODEC amplifier control */
-#define MST_MSCWR2_AC97_SPKROFF (1 << 2)   /* AC97 CODEC amplifier control */
-#define MST_MSCWR2_RADIO_PWR    (1 << 1)   /* Radio module power control */
-#define MST_MSCWR2_RADIO_WAKE   (1 << 0)   /* Radio module wake-up signal */
-
-#define MST_MSCWR3_GPIO_RESET_EN        (1 << 2) /* Enable GPIO Reset */
-#define MST_MSCWR3_GPIO_RESET           (1 << 1) /* Initiate a GPIO Reset */
-#define MST_MSCWR3_COMMS_SW_RESET       (1 << 0) /* Communications Processor Reset Control */
-
-#define MST_MSCRD_nPENIRQ       (1 << 9)   /* ADI7873* nPENIRQ signal */
-#define MST_MSCRD_nMEMSTK_CD    (1 << 8)   /* Memory Stick detection signal */
-#define MST_MSCRD_nMMC_CD       (1 << 7)   /* SD/MMC card detection signal */
-#define MST_MSCRD_nUSIM_CD      (1 << 6)   /* USIM card detection signal */
-#define MST_MSCRD_USB_CBL       (1 << 5)   /* USB client cable status */
-#define MST_MSCRD_TS_BUSY       (1 << 4)   /* ADI7873 busy */
-#define MST_MSCRD_BTDSR         (1 << 3)   /* Bluetooth UART DSR */
-#define MST_MSCRD_BTRI          (1 << 2)   /* Bluetooth UART Ring Indicator */
-#define MST_MSCRD_BTDCD         (1 << 1)   /* Bluetooth UART DCD */
-#define MST_MSCRD_nMMC_WP       (1 << 0)   /* SD/MMC write-protect status */
-
-#define MST_INT_S1_IRQ          (1 << 15)  /* PCMCIA socket 1 IRQ */
-#define MST_INT_S1_STSCHG       (1 << 14)  /* PCMCIA socket 1 status changed */
-#define MST_INT_S1_CD           (1 << 13)  /* PCMCIA socket 1 card detection */
-#define MST_INT_S0_IRQ          (1 << 11)  /* PCMCIA socket 0 IRQ */
-#define MST_INT_S0_STSCHG       (1 << 10)  /* PCMCIA socket 0 status changed */
-#define MST_INT_S0_CD           (1 << 9)   /* PCMCIA socket 0 card detection */
-#define MST_INT_nEXBRD_INT      (1 << 7)   /* Expansion board IRQ */
-#define MST_INT_MSINS           (1 << 6)   /* Memory Stick* detection */
-#define MST_INT_PENIRQ          (1 << 5)   /* ADI7873* touch-screen IRQ */
-#define MST_INT_AC97            (1 << 4)   /* AC'97 CODEC IRQ */
-#define MST_INT_ETHERNET        (1 << 3)   /* Ethernet controller IRQ */
-#define MST_INT_USBC            (1 << 2)   /* USB client cable detection IRQ */
-#define MST_INT_USIM            (1 << 1)   /* USIM card detection IRQ */
-#define MST_INT_MMC             (1 << 0)   /* MMC/SD card detection IRQ */
-
-#define MST_PCMCIA_nIRQ         (1 << 10)  /* IRQ / ready signal */
-#define MST_PCMCIA_nSPKR_BVD2   (1 << 9)   /* VDD sense / digital speaker */
-#define MST_PCMCIA_nSTSCHG_BVD1 (1 << 8)   /* VDD sense / card status changed */
-#define MST_PCMCIA_nVS2         (1 << 7)   /* VSS voltage sense */
-#define MST_PCMCIA_nVS1         (1 << 6)   /* VSS voltage sense */
-#define MST_PCMCIA_nCD          (1 << 5)   /* Card detection signal */
-#define MST_PCMCIA_RESET        (1 << 4)   /* Card reset signal */
-#define MST_PCMCIA_PWR_MASK     (0x000f)   /* MAX1602 power-supply controls */
-
-#define MST_PCMCIA_PWR_VPP_0    0x0        /* voltage VPP = 0V */
-#define MST_PCMCIA_PWR_VPP_120  0x2        /* voltage VPP = 12V*/
-#define MST_PCMCIA_PWR_VPP_VCC  0x1        /* voltage VPP = VCC */
-#define MST_PCMCIA_PWR_VCC_0    0x0        /* voltage VCC = 0V */
-#define MST_PCMCIA_PWR_VCC_33   0x8        /* voltage VCC = 3.3V */
-#define MST_PCMCIA_PWR_VCC_50   0x4        /* voltage VCC = 5.0V */
-
-#endif
diff --git a/include/asm-arm/arch-pxa/memory.h b/include/asm-arm/arch-pxa/memory.h
deleted file mode 100644
index bee81d66c184..000000000000
--- a/include/asm-arm/arch-pxa/memory.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-pxa/memory.h
- *
- * Author:      Nicolas Pitre
- * Copyright:   (C) 2001 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-/*
- * Physical DRAM offset.
- */
-#define PHYS_OFFSET     UL(0xa0000000)
-
-/*
- * Virtual view <-> DMA view memory address translations
- * virt_to_bus: Used to translate the virtual address to an
- *              address suitable to be passed to set_dma_addr
- * bus_to_virt: Used to convert an address for DMA operations
- *              to an address that the kernel can use.
- */
-#define __virt_to_bus(x)         __virt_to_phys(x)
-#define __bus_to_virt(x)         __phys_to_virt(x)
-
-/*
- * The nodes are matched with the physical SDRAM banks as follows:
- *
- *      node 0:  0xa0000000-0xa3ffffff  -->  0xc0000000-0xc3ffffff
- *      node 1:  0xa4000000-0xa7ffffff  -->  0xc4000000-0xc7ffffff
- *      node 2:  0xa8000000-0xabffffff  -->  0xc8000000-0xcbffffff
- *      node 3:  0xac000000-0xafffffff  -->  0xcc000000-0xcfffffff
- *
- * This needs a node mem size of 26 bits.
- */
-#define NODE_MEM_SIZE_BITS      26
-
-#if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
-void cmx270_pci_adjust_zones(int node, unsigned long *size,
-                             unsigned long *holes);
-
-#define arch_adjust_zones(node, size, holes) \
-        cmx270_pci_adjust_zones(node, size, holes)
-
-#define ISA_DMA_THRESHOLD       (PHYS_OFFSET + SZ_64M - 1)
-#endif
-
-#endif
diff --git a/include/asm-arm/arch-pxa/mfp-pxa25x.h b/include/asm-arm/arch-pxa/mfp-pxa25x.h
deleted file mode 100644
index 0499323010ba..000000000000
--- a/include/asm-arm/arch-pxa/mfp-pxa25x.h
+++ /dev/null
@@ -1,161 +0,0 @@
-#ifndef __ASM_ARCH_MFP_PXA25X_H
-#define __ASM_ARCH_MFP_PXA25X_H
-
-#include <asm/arch/mfp.h>
-#include <asm/arch/mfp-pxa2xx.h>
-
-/* GPIO */
-#define GPIO2_GPIO              MFP_CFG_IN(GPIO2, AF0)
-#define GPIO3_GPIO              MFP_CFG_IN(GPIO3, AF0)
-#define GPIO4_GPIO              MFP_CFG_IN(GPIO4, AF0)
-#define GPIO5_GPIO              MFP_CFG_IN(GPIO5, AF0)
-#define GPIO6_GPIO              MFP_CFG_IN(GPIO6, AF0)
-#define GPIO7_GPIO              MFP_CFG_IN(GPIO7, AF0)
-#define GPIO8_GPIO              MFP_CFG_IN(GPIO8, AF0)
-
-#define GPIO1_RST               MFP_CFG_IN(GPIO1, AF1)
-
-/* Crystal and Clock Signals */
-#define GPIO10_RTCCLK           MFP_CFG_OUT(GPIO10, AF1, DRIVE_LOW)
-#define GPIO70_RTC_CLK          MFP_CFG_OUT(GPIO70, AF1, DRIVE_LOW)
-#define GPIO7_48MHz             MFP_CFG_OUT(GPIO7,  AF1, DRIVE_LOW)
-#define GPIO11_3_6MHz           MFP_CFG_OUT(GPIO11, AF1, DRIVE_LOW)
-#define GPIO71_3_6MHz           MFP_CFG_OUT(GPIO71, AF1, DRIVE_LOW)
-#define GPIO12_32KHz            MFP_CFG_OUT(GPIO12, AF1, DRIVE_LOW)
-#define GPIO72_32kHz            MFP_CFG_OUT(GPIO72, AF1, DRIVE_LOW)
-
-/* SDRAM and Static Memory I/O Signals */
-#define GPIO15_nCS_1            MFP_CFG_OUT(GPIO15, AF2, DRIVE_HIGH)
-#define GPIO78_nCS_2            MFP_CFG_OUT(GPIO78, AF2, DRIVE_HIGH)
-#define GPIO79_nCS_3            MFP_CFG_OUT(GPIO79, AF2, DRIVE_HIGH)
-#define GPIO80_nCS_4            MFP_CFG_OUT(GPIO80, AF2, DRIVE_HIGH)
-#define GPIO33_nCS_5            MFP_CFG_OUT(GPIO33, AF2, DRIVE_HIGH)
-
-/* Miscellaneous I/O and DMA Signals */
-#define GPIO18_RDY              MFP_CFG_IN(GPIO18, AF1)
-#define GPIO20_DREQ_0           MFP_CFG_IN(GPIO20, AF1)
-#define GPIO19_DREQ_1           MFP_CFG_IN(GPIO19, AF1)
-
-/* Alternate Bus Master Mode I/O Signals */
-#define GPIO13_MBGNT            MFP_CFG_OUT(GPIO13, AF2, DRIVE_LOW)
-#define GPIO73_MBGNT            MFP_CFG_OUT(GPIO73, AF1, DRIVE_LOW)
-#define GPIO14_MBREQ            MFP_CFG_IN(GPIO14, AF1)
-#define GPIO66_MBREQ            MFP_CFG_IN(GPIO66, AF1)
-
-/* PC CARD */
-#define GPIO52_nPCE_1           MFP_CFG_OUT(GPIO52, AF2, DRIVE_HIGH)
-#define GPIO53_nPCE_2           MFP_CFG_OUT(GPIO53, AF2, DRIVE_HIGH)
-#define GPIO55_nPREG            MFP_CFG_OUT(GPIO55, AF2, DRIVE_HIGH)
-#define GPIO50_nPIOR            MFP_CFG_OUT(GPIO50, AF2, DRIVE_HIGH)
-#define GPIO51_nPIOW            MFP_CFG_OUT(GPIO51, AF2, DRIVE_HIGH)
-#define GPIO49_nPWE             MFP_CFG_OUT(GPIO49, AF2, DRIVE_HIGH)
-#define GPIO48_nPOE             MFP_CFG_OUT(GPIO48, AF2, DRIVE_HIGH)
-#define GPIO57_nIOIS16          MFP_CFG_IN(GPIO57, AF1)
-#define GPIO56_nPWAIT           MFP_CFG_IN(GPIO56, AF1)
-#define GPIO54_nPSKTSEL         MFP_CFG_OUT(GPIO54, AF2, DRIVE_HIGH)
-
-/* FFUART */
-#define GPIO34_FFUART_RXD       MFP_CFG_IN(GPIO34, AF1)
-#define GPIO35_FFUART_CTS       MFP_CFG_IN(GPIO35, AF1)
-#define GPIO36_FFUART_DCD       MFP_CFG_IN(GPIO36, AF1)
-#define GPIO37_FFUART_DSR       MFP_CFG_IN(GPIO37, AF1)
-#define GPIO38_FFUART_RI        MFP_CFG_IN(GPIO38, AF1)
-#define GPIO39_FFUART_TXD       MFP_CFG_OUT(GPIO39, AF2, DRIVE_HIGH)
-#define GPIO40_FFUART_DTR       MFP_CFG_OUT(GPIO40, AF2, DRIVE_HIGH)
-#define GPIO41_FFUART_RTS       MFP_CFG_OUT(GPIO41, AF2, DRIVE_HIGH)
-
-/* BTUART */
-#define GPIO42_BTUART_RXD       MFP_CFG_IN(GPIO42, AF1)
-#define GPIO43_BTUART_TXD       MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH)
-#define GPIO44_BTUART_CTS       MFP_CFG_IN(GPIO44, AF1)
-#define GPIO45_BTUART_RTS       MFP_CFG_OUT(GPIO45, AF2, DRIVE_HIGH)
-
-/* STUART */
-#define GPIO46_STUART_RXD       MFP_CFG_IN(GPIO46, AF2)
-#define GPIO47_STUART_TXD       MFP_CFG_OUT(GPIO47, AF1, DRIVE_HIGH)
-
-/* HWUART */
-#define GPIO42_HWUART_RXD       MFP_CFG_IN(GPIO42, AF3)
-#define GPIO43_HWUART_TXD       MFP_CFG_OUT(GPIO43, AF3, DRIVE_HIGH)
-#define GPIO44_HWUART_CTS       MFP_CFG_IN(GPIO44, AF3)
-#define GPIO45_HWUART_RTS       MFP_CFG_OUT(GPIO45, AF3, DRIVE_HIGH)
-#define GPIO48_HWUART_TXD       MFP_CFG_OUT(GPIO48, AF1, DRIVE_HIGH)
-#define GPIO49_HWUART_RXD       MFP_CFG_IN(GPIO49, AF1)
-#define GPIO50_HWUART_CTS       MFP_CFG_IN(GPIO50, AF1)
-#define GPIO51_HWUART_RTS       MFP_CFG_OUT(GPIO51, AF1, DRIVE_HIGH)
-
-/* FICP */
-#define GPIO46_FICP_RXD         MFP_CFG_IN(GPIO46, AF1)
-#define GPIO47_FICP_TXD         MFP_CFG_OUT(GPIO47, AF2, DRIVE_HIGH)
-
-/* PWM 0/1 */
-#define GPIO16_PWM0_OUT         MFP_CFG_OUT(GPIO16, AF2, DRIVE_LOW)
-#define GPIO17_PWM1_OUT         MFP_CFG_OUT(GPIO17, AF2, DRIVE_LOW)
-
-/* AC97 */
-#define GPIO28_AC97_BITCLK      MFP_CFG_IN(GPIO28, AF1)
-#define GPIO29_AC97_SDATA_IN_0  MFP_CFG_IN(GPIO29, AF1)
-#define GPIO30_AC97_SDATA_OUT   MFP_CFG_OUT(GPIO30, AF2, DRIVE_LOW)
-#define GPIO31_AC97_SYNC        MFP_CFG_OUT(GPIO31, AF2, DRIVE_LOW)
-#define GPIO32_AC97_SDATA_IN_1  MFP_CFG_IN(GPIO32, AF1)
-
-/* I2S */
-#define GPIO28_I2S_BITCLK_IN    MFP_CFG_IN(GPIO28, AF2)
-#define GPIO28_I2S_BITCLK_OUT   MFP_CFG_OUT(GPIO28, AF1, DRIVE_LOW)
-#define GPIO29_I2S_SDATA_IN     MFP_CFG_IN(GPIO29, AF2)
-#define GPIO30_I2S_SDATA_OUT    MFP_CFG_OUT(GPIO30, AF1, DRIVE_LOW)
-#define GPIO31_I2S_SYNC         MFP_CFG_OUT(GPIO31, AF1, DRIVE_LOW)
-#define GPIO32_I2S_SYSCLK       MFP_CFG_OUT(GPIO32, AF1, DRIVE_LOW)
-
-/* SSP 1 */
-#define GPIO23_SSP1_SCLK        MFP_CFG_OUT(GPIO23, AF2, DRIVE_LOW)
-#define GPIO24_SSP1_SFRM        MFP_CFG_OUT(GPIO24, AF2, DRIVE_LOW)
-#define GPIO25_SSP1_TXD         MFP_CFG_OUT(GPIO25, AF2, DRIVE_LOW)
-#define GPIO26_SSP1_RXD         MFP_CFG_IN(GPIO26, AF1)
-#define GPIO27_SSP1_EXTCLK      MFP_CFG_IN(GPIO27, AF1)
-
-/* SSP 2 - NSSP */
-#define GPIO81_SSP2_CLK_OUT     MFP_CFG_OUT(GPIO81, AF1, DRIVE_LOW)
-#define GPIO81_SSP2_CLK_IN      MFP_CFG_IN(GPIO81, AF1)
-#define GPIO82_SSP2_FRM_OUT     MFP_CFG_OUT(GPIO82, AF1, DRIVE_LOW)
-#define GPIO82_SSP2_FRM_IN      MFP_CFG_IN(GPIO82, AF1)
-#define GPIO83_SSP2_TXD         MFP_CFG_OUT(GPIO83, AF1, DRIVE_LOW)
-#define GPIO83_SSP2_RXD         MFP_CFG_IN(GPIO83, AF2)
-#define GPIO84_SSP2_TXD         MFP_CFG_OUT(GPIO84, AF1, DRIVE_LOW)
-#define GPIO84_SSP2_RXD         MFP_CFG_IN(GPIO84, AF2)
-
-/* MMC */
-#define GPIO6_MMC_CLK           MFP_CFG_OUT(GPIO6, AF1, DRIVE_LOW)
-#define GPIO8_MMC_CS0           MFP_CFG_OUT(GPIO8, AF1, DRIVE_LOW)
-#define GPIO9_MMC_CS1           MFP_CFG_OUT(GPIO9, AF1, DRIVE_LOW)
-#define GPIO34_MMC_CS0          MFP_CFG_OUT(GPIO34, AF2, DRIVE_LOW)
-#define GPIO39_MMC_CS1          MFP_CFG_OUT(GPIO39, AF1, DRIVE_LOW)
-#define GPIO53_MMC_CLK          MFP_CFG_OUT(GPIO53, AF1, DRIVE_LOW)
-#define GPIO54_MMC_CLK          MFP_CFG_OUT(GPIO54, AF1, DRIVE_LOW)
-#define GPIO69_MMC_CLK          MFP_CFG_OUT(GPIO69, AF1, DRIVE_LOW)
-#define GPIO67_MMC_CS0          MFP_CFG_OUT(GPIO67, AF1, DRIVE_LOW)
-#define GPIO68_MMC_CS1          MFP_CFG_OUT(GPIO68, AF1, DRIVE_LOW)
-
-/* LCD */
-#define GPIO58_LCD_LDD_0        MFP_CFG_OUT(GPIO58, AF2, DRIVE_LOW)
-#define GPIO59_LCD_LDD_1        MFP_CFG_OUT(GPIO59, AF2, DRIVE_LOW)
-#define GPIO60_LCD_LDD_2        MFP_CFG_OUT(GPIO60, AF2, DRIVE_LOW)
-#define GPIO61_LCD_LDD_3        MFP_CFG_OUT(GPIO61, AF2, DRIVE_LOW)
-#define GPIO62_LCD_LDD_4        MFP_CFG_OUT(GPIO62, AF2, DRIVE_LOW)
-#define GPIO63_LCD_LDD_5        MFP_CFG_OUT(GPIO63, AF2, DRIVE_LOW)
-#define GPIO64_LCD_LDD_6        MFP_CFG_OUT(GPIO64, AF2, DRIVE_LOW)
-#define GPIO65_LCD_LDD_7        MFP_CFG_OUT(GPIO65, AF2, DRIVE_LOW)
-#define GPIO66_LCD_LDD_8        MFP_CFG_OUT(GPIO66, AF2, DRIVE_LOW)
-#define GPIO67_LCD_LDD_9        MFP_CFG_OUT(GPIO67, AF2, DRIVE_LOW)
-#define GPIO68_LCD_LDD_10       MFP_CFG_OUT(GPIO68, AF2, DRIVE_LOW)
-#define GPIO69_LCD_LDD_11       MFP_CFG_OUT(GPIO69, AF2, DRIVE_LOW)
-#define GPIO70_LCD_LDD_12       MFP_CFG_OUT(GPIO70, AF2, DRIVE_LOW)
-#define GPIO71_LCD_LDD_13       MFP_CFG_OUT(GPIO71, AF2, DRIVE_LOW)
-#define GPIO72_LCD_LDD_14       MFP_CFG_OUT(GPIO72, AF2, DRIVE_LOW)
-#define GPIO73_LCD_LDD_15       MFP_CFG_OUT(GPIO73, AF2, DRIVE_LOW)
-#define GPIO74_LCD_FCLK         MFP_CFG_OUT(GPIO74, AF2, DRIVE_LOW)
-#define GPIO75_LCD_LCLK         MFP_CFG_OUT(GPIO75, AF2, DRIVE_LOW)
-#define GPIO76_LCD_PCLK         MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW)
-#define GPIO77_LCD_ACBIAS       MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW)
-
-#endif /* __ASM_ARCH_MFP_PXA25X_H */
diff --git a/include/asm-arm/arch-pxa/mfp-pxa27x.h b/include/asm-arm/arch-pxa/mfp-pxa27x.h
deleted file mode 100644
index bc73ab84167c..000000000000
--- a/include/asm-arm/arch-pxa/mfp-pxa27x.h
+++ /dev/null
@@ -1,433 +0,0 @@
-#ifndef __ASM_ARCH_MFP_PXA27X_H
-#define __ASM_ARCH_MFP_PXA27X_H
-
-/*
- * NOTE:  for those special-function bidirectional GPIOs, as described
- * in the "PXA27x Developer's Manual" Section 24.4.2.1, only its input
- * alternative is preserved, the direction is actually selected by the
- * specific controller, and this should work in most cases.
- */
-
-#include <asm/arch/mfp.h>
-#include <asm/arch/mfp-pxa2xx.h>
-
-/* GPIO */
-#define GPIO85_GPIO             MFP_CFG_IN(GPIO85, AF0)
-#define GPIO86_GPIO             MFP_CFG_IN(GPIO86, AF0)
-#define GPIO87_GPIO             MFP_CFG_IN(GPIO87, AF0)
-#define GPIO88_GPIO             MFP_CFG_IN(GPIO88, AF0)
-#define GPIO89_GPIO             MFP_CFG_IN(GPIO89, AF0)
-#define GPIO90_GPIO             MFP_CFG_IN(GPIO90, AF0)
-#define GPIO91_GPIO             MFP_CFG_IN(GPIO91, AF0)
-#define GPIO92_GPIO             MFP_CFG_IN(GPIO92, AF0)
-#define GPIO93_GPIO             MFP_CFG_IN(GPIO93, AF0)
-#define GPIO94_GPIO             MFP_CFG_IN(GPIO94, AF0)
-#define GPIO95_GPIO             MFP_CFG_IN(GPIO95, AF0)
-#define GPIO96_GPIO             MFP_CFG_IN(GPIO96, AF0)
-#define GPIO97_GPIO             MFP_CFG_IN(GPIO97, AF0)
-#define GPIO98_GPIO             MFP_CFG_IN(GPIO98, AF0)
-#define GPIO99_GPIO             MFP_CFG_IN(GPIO99, AF0)
-#define GPIO100_GPIO            MFP_CFG_IN(GPIO100, AF0)
-#define GPIO101_GPIO            MFP_CFG_IN(GPIO101, AF0)
-#define GPIO102_GPIO            MFP_CFG_IN(GPIO102, AF0)
-#define GPIO103_GPIO            MFP_CFG_IN(GPIO103, AF0)
-#define GPIO104_GPIO            MFP_CFG_IN(GPIO104, AF0)
-#define GPIO105_GPIO            MFP_CFG_IN(GPIO105, AF0)
-#define GPIO106_GPIO            MFP_CFG_IN(GPIO106, AF0)
-#define GPIO107_GPIO            MFP_CFG_IN(GPIO107, AF0)
-#define GPIO108_GPIO            MFP_CFG_IN(GPIO108, AF0)
-#define GPIO109_GPIO            MFP_CFG_IN(GPIO109, AF0)
-#define GPIO110_GPIO            MFP_CFG_IN(GPIO110, AF0)
-#define GPIO111_GPIO            MFP_CFG_IN(GPIO111, AF0)
-#define GPIO112_GPIO            MFP_CFG_IN(GPIO112, AF0)
-#define GPIO113_GPIO            MFP_CFG_IN(GPIO113, AF0)
-#define GPIO114_GPIO            MFP_CFG_IN(GPIO114, AF0)
-#define GPIO115_GPIO            MFP_CFG_IN(GPIO115, AF0)
-#define GPIO116_GPIO            MFP_CFG_IN(GPIO116, AF0)
-#define GPIO117_GPIO            MFP_CFG_IN(GPIO117, AF0)
-#define GPIO118_GPIO            MFP_CFG_IN(GPIO118, AF0)
-#define GPIO119_GPIO            MFP_CFG_IN(GPIO119, AF0)
-#define GPIO120_GPIO            MFP_CFG_IN(GPIO120, AF0)
-
-/* Crystal and Clock Signals */
-#define GPIO9_HZ_CLK            MFP_CFG_OUT(GPIO9,  AF1, DRIVE_LOW)
-#define GPIO10_HZ_CLK           MFP_CFG_OUT(GPIO10, AF1, DRIVE_LOW)
-#define GPIO11_48_MHz           MFP_CFG_OUT(GPIO11, AF3, DRIVE_LOW)
-#define GPIO12_48_MHz           MFP_CFG_OUT(GPIO12, AF3, DRIVE_LOW)
-#define GPIO13_CLK_EXT          MFP_CFG_IN(GPIO13, AF1)
-
-/* OS Timer Signals */
-#define GPIO11_EXT_SYNC_0       MFP_CFG_IN(GPIO11, AF1)
-#define GPIO12_EXT_SYNC_1       MFP_CFG_IN(GPIO12, AF1)
-#define GPIO9_CHOUT_0           MFP_CFG_OUT(GPIO9,  AF3, DRIVE_LOW)
-#define GPIO10_CHOUT_1          MFP_CFG_OUT(GPIO10, AF3, DRIVE_LOW)
-#define GPIO11_CHOUT_0          MFP_CFG_OUT(GPIO11, AF1, DRIVE_LOW)
-#define GPIO12_CHOUT_1          MFP_CFG_OUT(GPIO12, AF1, DRIVE_LOW)
-
-/* SDRAM and Static Memory I/O Signals */
-#define GPIO20_nSDCS_2          MFP_CFG_OUT(GPIO20, AF1, DRIVE_HIGH)
-#define GPIO21_nSDCS_3          MFP_CFG_OUT(GPIO21, AF1, DRIVE_HIGH)
-#define GPIO15_nCS_1            MFP_CFG_OUT(GPIO15, AF2, DRIVE_HIGH)
-#define GPIO78_nCS_2            MFP_CFG_OUT(GPIO78, AF2, DRIVE_HIGH)
-#define GPIO79_nCS_3            MFP_CFG_OUT(GPIO79, AF2, DRIVE_HIGH)
-#define GPIO80_nCS_4            MFP_CFG_OUT(GPIO80, AF2, DRIVE_HIGH)
-#define GPIO33_nCS_5            MFP_CFG_OUT(GPIO33, AF2, DRIVE_HIGH)
-
-/* Miscellaneous I/O and DMA Signals */
-#define GPIO21_DVAL_0           MFP_CFG_OUT(GPIO21, AF2, DRIVE_HIGH)
-#define GPIO116_DVAL_0          MFP_CFG_OUT(GPIO116, AF1, DRIVE_HIGH)
-#define GPIO33_DVAL_1           MFP_CFG_OUT(GPIO33, AF1, DRIVE_HIGH)
-#define GPIO96_DVAL_1           MFP_CFG_OUT(GPIO96, AF2, DRIVE_HIGH)
-#define GPIO18_RDY              MFP_CFG_IN(GPIO18, AF1)
-#define GPIO20_DREQ_0           MFP_CFG_IN(GPIO20, AF1)
-#define GPIO115_DREQ_0          MFP_CFG_IN(GPIO115, AF1)
-#define GPIO80_DREQ_1           MFP_CFG_IN(GPIO80, AF1)
-#define GPIO97_DREQ_1           MFP_CFG_IN(GPIO97, AF2)
-#define GPIO85_DREQ_2           MFP_CFG_IN(GPIO85, AF2)
-#define GPIO100_DREQ_2          MFP_CFG_IN(GPIO100, AF2)
-
-/* Alternate Bus Master Mode I/O Signals */
-#define GPIO20_MBREQ            MFP_CFG_IN(GPIO20, AF2)
-#define GPIO80_MBREQ            MFP_CFG_IN(GPIO80, AF2)
-#define GPIO96_MBREQ            MFP_CFG_IN(GPIO96, AF2)
-#define GPIO115_MBREQ           MFP_CFG_IN(GPIO115, AF3)
-#define GPIO21_MBGNT            MFP_CFG_OUT(GPIO21, AF3, DRIVE_LOW)
-#define GPIO33_MBGNT            MFP_CFG_OUT(GPIO33, AF3, DRIVE_LOW)
-#define GPIO97_MBGNT            MFP_CFG_OUT(GPIO97, AF2, DRIVE_LOW)
-#define GPIO116_MBGNT           MFP_CFG_OUT(GPIO116, AF3, DRIVE_LOW)
-
-/* PC CARD */
-#define GPIO15_nPCE_1           MFP_CFG_OUT(GPIO15, AF1, DRIVE_HIGH)
-#define GPIO85_nPCE_1           MFP_CFG_OUT(GPIO85, AF1, DRIVE_HIGH)
-#define GPIO86_nPCE_1           MFP_CFG_OUT(GPIO86, AF1, DRIVE_HIGH)
-#define GPIO102_nPCE_1          MFP_CFG_OUT(GPIO102, AF1, DRIVE_HIGH)
-#define GPIO54_nPCE_2           MFP_CFG_OUT(GPIO54, AF2, DRIVE_HIGH)
-#define GPIO78_nPCE_2           MFP_CFG_OUT(GPIO78, AF1, DRIVE_HIGH)
-#define GPIO87_nPCE_2           MFP_CFG_IN(GPIO87, AF1)
-#define GPIO55_nPREG            MFP_CFG_OUT(GPIO55, AF2, DRIVE_HIGH)
-#define GPIO50_nPIOR            MFP_CFG_OUT(GPIO50, AF2, DRIVE_HIGH)
-#define GPIO51_nPIOW            MFP_CFG_OUT(GPIO51, AF2, DRIVE_HIGH)
-#define GPIO49_nPWE             MFP_CFG_OUT(GPIO49, AF2, DRIVE_HIGH)
-#define GPIO48_nPOE             MFP_CFG_OUT(GPIO48, AF2, DRIVE_HIGH)
-#define GPIO57_nIOIS16          MFP_CFG_IN(GPIO57, AF1)
-#define GPIO56_nPWAIT           MFP_CFG_IN(GPIO56, AF1)
-#define GPIO79_PSKTSEL          MFP_CFG_OUT(GPIO79, AF1, DRIVE_HIGH)
-#define GPIO104_PSKTSEL         MFP_CFG_OUT(GPIO104, AF1, DRIVE_HIGH)
-
-/* I2C */
-#define GPIO117_I2C_SCL         MFP_CFG_IN(GPIO117, AF1)
-#define GPIO118_I2C_SDA         MFP_CFG_IN(GPIO118, AF1)
-
-/* FFUART */
-#define GPIO9_FFUART_CTS        MFP_CFG_IN(GPIO9, AF3)
-#define GPIO26_FFUART_CTS       MFP_CFG_IN(GPIO26, AF3)
-#define GPIO35_FFUART_CTS       MFP_CFG_IN(GPIO35, AF1)
-#define GPIO100_FFUART_CTS      MFP_CFG_IN(GPIO100, AF3)
-#define GPIO10_FFUART_DCD       MFP_CFG_IN(GPIO10, AF1)
-#define GPIO36_FFUART_DCD       MFP_CFG_IN(GPIO36, AF1)
-#define GPIO33_FFUART_DSR       MFP_CFG_IN(GPIO33, AF2)
-#define GPIO37_FFUART_DSR       MFP_CFG_IN(GPIO37, AF1)
-#define GPIO38_FFUART_RI        MFP_CFG_IN(GPIO38, AF1)
-#define GPIO89_FFUART_RI        MFP_CFG_IN(GPIO89, AF3)
-#define GPIO19_FFUART_RXD       MFP_CFG_IN(GPIO19, AF3)
-#define GPIO33_FFUART_RXD       MFP_CFG_IN(GPIO33, AF1)
-#define GPIO34_FFUART_RXD       MFP_CFG_IN(GPIO34, AF1)
-#define GPIO41_FFUART_RXD       MFP_CFG_IN(GPIO41, AF1)
-#define GPIO53_FFUART_RXD       MFP_CFG_IN(GPIO53, AF1)
-#define GPIO85_FFUART_RXD       MFP_CFG_IN(GPIO85, AF1)
-#define GPIO96_FFUART_RXD       MFP_CFG_IN(GPIO96, AF3)
-#define GPIO102_FFUART_RXD      MFP_CFG_IN(GPIO102, AF3)
-#define GPIO16_FFUART_TXD       MFP_CFG_OUT(GPIO16, AF3, DRIVE_HIGH)
-#define GPIO37_FFUART_TXD       MFP_CFG_OUT(GPIO37, AF3, DRIVE_HIGH)
-#define GPIO39_FFUART_TXD       MFP_CFG_OUT(GPIO39, AF2, DRIVE_HIGH)
-#define GPIO83_FFUART_TXD       MFP_CFG_OUT(GPIO83, AF2, DRIVE_HIGH)
-#define GPIO99_FFUART_TXD       MFP_CFG_OUT(GPIO99, AF3, DRIVE_HIGH)
-#define GPIO27_FFUART_RTS       MFP_CFG_OUT(GPIO27, AF3, DRIVE_HIGH)
-#define GPIO41_FFUART_RTS       MFP_CFG_OUT(GPIO41, AF2, DRIVE_HIGH)
-#define GPIO83_FFUART_RTS       MFP_CFG_OUT(GPIO83, AF3, DRIVE_HIGH)
-#define GPIO98_FFUART_RTS       MFP_CFG_OUT(GPIO98, AF3, DRIVE_HIGH)
-#define GPIO40_FFUART_DTR       MFP_CFG_OUT(GPIO40, AF2, DRIVE_HIGH)
-#define GPIO82_FFUART_DTR       MFP_CFG_OUT(GPIO82, AF3, DRIVE_HIGH)
-
-/* BTUART */
-#define GPIO44_BTUART_CTS       MFP_CFG_IN(GPIO44, AF1)
-#define GPIO42_BTUART_RXD       MFP_CFG_IN(GPIO42, AF1)
-#define GPIO45_BTUART_RTS       MFP_CFG_OUT(GPIO45, AF2, DRIVE_HIGH)
-#define GPIO43_BTUART_TXD       MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH)
-
-/* STUART */
-#define GPIO46_STUART_RXD       MFP_CFG_IN(GPIO46, AF2)
-#define GPIO47_STUART_TXD       MFP_CFG_OUT(GPIO47, AF1, DRIVE_HIGH)
-
-/* FICP */
-#define GPIO42_FICP_RXD         MFP_CFG_IN(GPIO42, AF2)
-#define GPIO46_FICP_RXD         MFP_CFG_IN(GPIO46, AF1)
-#define GPIO43_FICP_TXD         MFP_CFG_OUT(GPIO43, AF1, DRIVE_HIGH)
-#define GPIO47_FICP_TXD         MFP_CFG_OUT(GPIO47, AF2, DRIVE_HIGH)
-
-/* PWM 0/1/2/3 */
-#define GPIO11_PWM2_OUT         MFP_CFG_OUT(GPIO11, AF2, DRIVE_LOW)
-#define GPIO12_PWM3_OUT         MFP_CFG_OUT(GPIO12, AF2, DRIVE_LOW)
-#define GPIO16_PWM0_OUT         MFP_CFG_OUT(GPIO16, AF2, DRIVE_LOW)
-#define GPIO17_PWM1_OUT         MFP_CFG_OUT(GPIO17, AF2, DRIVE_LOW)
-#define GPIO38_PWM1_OUT         MFP_CFG_OUT(GPIO38, AF3, DRIVE_LOW)
-#define GPIO46_PWM2_OUT         MFP_CFG_OUT(GPIO46, AF2, DRIVE_LOW)
-#define GPIO47_PWM3_OUT         MFP_CFG_OUT(GPIO47, AF3, DRIVE_LOW)
-#define GPIO79_PWM2_OUT         MFP_CFG_OUT(GPIO79, AF3, DRIVE_LOW)
-#define GPIO80_PWM3_OUT         MFP_CFG_OUT(GPIO80, AF3, DRIVE_LOW)
-#define GPIO115_PWM1_OUT        MFP_CFG_OUT(GPIO115, AF3, DRIVE_LOW)
-
-/* AC97 */
-#define GPIO31_AC97_SYNC        MFP_CFG_OUT(GPIO31, AF2, DRIVE_LOW)
-#define GPIO94_AC97_SYNC        MFP_CFG_OUT(GPIO94, AF1, DRIVE_LOW)
-#define GPIO30_AC97_SDATA_OUT   MFP_CFG_OUT(GPIO30, AF2, DRIVE_LOW)
-#define GPIO93_AC97_SDATA_OUT   MFP_CFG_OUT(GPIO93, AF1, DRIVE_LOW)
-#define GPIO45_AC97_SYSCLK      MFP_CFG_OUT(GPIO45, AF1, DRIVE_LOW)
-#define GPIO89_AC97_SYSCLK      MFP_CFG_OUT(GPIO89, AF1, DRIVE_LOW)
-#define GPIO98_AC97_SYSCLK      MFP_CFG_OUT(GPIO98, AF1, DRIVE_LOW)
-#define GPIO95_AC97_nRESET      MFP_CFG_OUT(GPIO95, AF1, DRIVE_LOW)
-#define GPIO113_AC97_nRESET     MFP_CFG_OUT(GPIO113, AF2, DRIVE_LOW)
-#define GPIO28_AC97_BITCLK      MFP_CFG_IN(GPIO28, AF1)
-#define GPIO29_AC97_SDATA_IN_0  MFP_CFG_IN(GPIO29, AF1)
-#define GPIO116_AC97_SDATA_IN_0 MFP_CFG_IN(GPIO116, AF2)
-#define GPIO99_AC97_SDATA_IN_1  MFP_CFG_IN(GPIO99, AF2)
-
-/* I2S */
-#define GPIO28_I2S_BITCLK_IN    MFP_CFG_IN(GPIO28, AF2)
-#define GPIO28_I2S_BITCLK_OUT   MFP_CFG_OUT(GPIO28, AF1, DRIVE_LOW)
-#define GPIO29_I2S_SDATA_IN     MFP_CFG_IN(GPIO29, AF2)
-#define GPIO30_I2S_SDATA_OUT    MFP_CFG_OUT(GPIO30, AF1, DRIVE_LOW)
-#define GPIO31_I2S_SYNC         MFP_CFG_OUT(GPIO31, AF1, DRIVE_LOW)
-#define GPIO113_I2S_SYSCLK      MFP_CFG_OUT(GPIO113, AF1, DRIVE_LOW)
-
-/* SSP 1 */
-#define GPIO23_SSP1_SCLK        MFP_CFG_OUT(GPIO23, AF2, DRIVE_LOW)
-#define GPIO29_SSP1_SCLK        MFP_CFG_IN(GPIO29, AF3)
-#define GPIO27_SSP1_SYSCLK      MFP_CFG_OUT(GPIO27, AF1, DRIVE_LOW)
-#define GPIO53_SSP1_SYSCLK      MFP_CFG_OUT(GPIO53, AF3, DRIVE_LOW)
-#define GPIO24_SSP1_SFRM        MFP_CFG_IN(GPIO24, AF2)
-#define GPIO28_SSP1_SFRM        MFP_CFG_IN(GPIO28, AF3)
-#define GPIO25_SSP1_TXD         MFP_CFG_OUT(GPIO25, AF2, DRIVE_LOW)
-#define GPIO57_SSP1_TXD         MFP_CFG_OUT(GPIO57, AF3, DRIVE_LOW)
-#define GPIO26_SSP1_RXD         MFP_CFG_IN(GPIO26, AF1)
-#define GPIO27_SSP1_SCLKEN      MFP_CFG_IN(GPIO27, AF2)
-
-/* SSP 2 */
-#define GPIO19_SSP2_SCLK        MFP_CFG_IN(GPIO19, AF1)
-#define GPIO22_SSP2_SCLK        MFP_CFG_IN(GPIO22, AF3)
-#define GPIO29_SSP2_SCLK        MFP_CFG_OUT(GPIO29, AF3, DRIVE_LOW)
-#define GPIO36_SSP2_SCLK        MFP_CFG_IN(GPIO36, AF2)
-#define GPIO50_SSP2_SCLK        MFP_CFG_IN(GPIO50, AF3)
-#define GPIO22_SSP2_SYSCLK      MFP_CFG_OUT(GPIO22, AF2, DRIVE_LOW)
-#define GPIO14_SSP2_SFRM        MFP_CFG_IN(GPIO14, AF2)
-#define GPIO37_SSP2_SFRM        MFP_CFG_IN(GPIO37, AF2)
-#define GPIO87_SSP2_SFRM        MFP_CFG_OUT(GPIO87, AF3, DRIVE_LOW)
-#define GPIO88_SSP2_SFRM        MFP_CFG_IN(GPIO88, AF3)
-#define GPIO13_SSP2_TXD         MFP_CFG_OUT(GPIO13, AF1, DRIVE_LOW)
-#define GPIO38_SSP2_TXD         MFP_CFG_OUT(GPIO38, AF2, DRIVE_LOW)
-#define GPIO87_SSP2_TXD         MFP_CFG_OUT(GPIO87, AF1, DRIVE_LOW)
-#define GPIO89_SSP2_TXD         MFP_CFG_OUT(GPIO89, AF3, DRIVE_LOW)
-#define GPIO11_SSP2_RXD         MFP_CFG_IN(GPIO11, AF2)
-#define GPIO29_SSP2_RXD         MFP_CFG_OUT(GPIO29, AF1, DRIVE_LOW)
-#define GPIO40_SSP2_RXD         MFP_CFG_IN(GPIO40, AF1)
-#define GPIO86_SSP2_RXD         MFP_CFG_IN(GPIO86, AF1)
-#define GPIO88_SSP2_RXD         MFP_CFG_IN(GPIO88, AF2)
-#define GPIO22_SSP2_EXTCLK      MFP_CFG_IN(GPIO22, AF1)
-#define GPIO27_SSP2_EXTCLK      MFP_CFG_IN(GPIO27, AF1)
-#define GPIO22_SSP2_SCLKEN      MFP_CFG_IN(GPIO22, AF2)
-#define GPIO23_SSP2_SCLKEN      MFP_CFG_IN(GPIO23, AF2)
-
-/* SSP 3 */
-#define GPIO34_SSP3_SCLK        MFP_CFG_IN(GPIO34, AF3)
-#define GPIO40_SSP3_SCLK        MFP_CFG_OUT(GPIO40, AF3, DRIVE_LOW)
-#define GPIO52_SSP3_SCLK        MFP_CFG_IN(GPIO52, AF2)
-#define GPIO84_SSP3_SCLK        MFP_CFG_IN(GPIO84, AF1)
-#define GPIO45_SSP3_SYSCLK      MFP_CFG_OUT(GPIO45, AF3, DRIVE_LOW)
-#define GPIO35_SSP3_SFRM        MFP_CFG_IN(GPIO35, AF3)
-#define GPIO39_SSP3_SFRM        MFP_CFG_IN(GPIO39, AF3)
-#define GPIO83_SSP3_SFRM        MFP_CFG_IN(GPIO83, AF1)
-#define GPIO35_SSP3_TXD         MFP_CFG_OUT(GPIO35, AF3, DRIVE_LOW)
-#define GPIO38_SSP3_TXD         MFP_CFG_OUT(GPIO38, AF1, DRIVE_LOW)
-#define GPIO81_SSP3_TXD         MFP_CFG_OUT(GPIO81, AF1, DRIVE_LOW)
-#define GPIO41_SSP3_RXD         MFP_CFG_IN(GPIO41, AF3)
-#define GPIO82_SSP3_RXD         MFP_CFG_IN(GPIO82, AF1)
-#define GPIO89_SSP3_RXD         MFP_CFG_IN(GPIO89, AF1)
-
-/* MMC */
-#define GPIO32_MMC_CLK          MFP_CFG_OUT(GPIO32, AF2, DRIVE_LOW)
-#define GPIO92_MMC_DAT_0        MFP_CFG_IN(GPIO92, AF1)
-#define GPIO109_MMC_DAT_1       MFP_CFG_IN(GPIO109, AF1)
-#define GPIO110_MMC_DAT_2       MFP_CFG_IN(GPIO110, AF1)
-#define GPIO111_MMC_DAT_3       MFP_CFG_IN(GPIO111, AF1)
-#define GPIO112_MMC_CMD         MFP_CFG_IN(GPIO112, AF1)
-
-/* LCD */
-#define GPIO58_LCD_LDD_0        MFP_CFG_OUT(GPIO58, AF2, DRIVE_LOW)
-#define GPIO59_LCD_LDD_1        MFP_CFG_OUT(GPIO59, AF2, DRIVE_LOW)
-#define GPIO60_LCD_LDD_2        MFP_CFG_OUT(GPIO60, AF2, DRIVE_LOW)
-#define GPIO61_LCD_LDD_3        MFP_CFG_OUT(GPIO61, AF2, DRIVE_LOW)
-#define GPIO62_LCD_LDD_4        MFP_CFG_OUT(GPIO62, AF2, DRIVE_LOW)
-#define GPIO63_LCD_LDD_5        MFP_CFG_OUT(GPIO63, AF2, DRIVE_LOW)
-#define GPIO64_LCD_LDD_6        MFP_CFG_OUT(GPIO64, AF2, DRIVE_LOW)
-#define GPIO65_LCD_LDD_7        MFP_CFG_OUT(GPIO65, AF2, DRIVE_LOW)
-#define GPIO66_LCD_LDD_8        MFP_CFG_OUT(GPIO66, AF2, DRIVE_LOW)
-#define GPIO67_LCD_LDD_9        MFP_CFG_OUT(GPIO67, AF2, DRIVE_LOW)
-#define GPIO68_LCD_LDD_10       MFP_CFG_OUT(GPIO68, AF2, DRIVE_LOW)
-#define GPIO69_LCD_LDD_11       MFP_CFG_OUT(GPIO69, AF2, DRIVE_LOW)
-#define GPIO70_LCD_LDD_12       MFP_CFG_OUT(GPIO70, AF2, DRIVE_LOW)
-#define GPIO71_LCD_LDD_13       MFP_CFG_OUT(GPIO71, AF2, DRIVE_LOW)
-#define GPIO72_LCD_LDD_14       MFP_CFG_OUT(GPIO72, AF2, DRIVE_LOW)
-#define GPIO73_LCD_LDD_15       MFP_CFG_OUT(GPIO73, AF2, DRIVE_LOW)
-#define GPIO86_LCD_LDD_16       MFP_CFG_OUT(GPIO86, AF2, DRIVE_LOW)
-#define GPIO87_LCD_LDD_17       MFP_CFG_OUT(GPIO87, AF2, DRIVE_LOW)
-#define GPIO74_LCD_FCLK         MFP_CFG_OUT(GPIO74, AF2, DRIVE_LOW)
-#define GPIO75_LCD_LCLK         MFP_CFG_OUT(GPIO75, AF2, DRIVE_LOW)
-#define GPIO76_LCD_PCLK         MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW)
-#define GPIO77_LCD_BIAS         MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW)
-#define GPIO14_LCD_VSYNC        MFP_CFG_IN(GPIO14, AF1)
-#define GPIO19_LCD_CS           MFP_CFG_OUT(GPIO19, AF2, DRIVE_LOW)
-
-/* Keypad */
-#define GPIO93_KP_DKIN_0        MFP_CFG_IN(GPIO93, AF1)
-#define GPIO94_KP_DKIN_1        MFP_CFG_IN(GPIO94, AF1)
-#define GPIO95_KP_DKIN_2        MFP_CFG_IN(GPIO95, AF1)
-#define GPIO96_KP_DKIN_3        MFP_CFG_IN(GPIO96, AF1)
-#define GPIO97_KP_DKIN_4        MFP_CFG_IN(GPIO97, AF1)
-#define GPIO98_KP_DKIN_5        MFP_CFG_IN(GPIO98, AF1)
-#define GPIO99_KP_DKIN_6        MFP_CFG_IN(GPIO99, AF1)
-#define GPIO13_KP_KDIN_7        MFP_CFG_IN(GPIO13, AF2)
-#define GPIO100_KP_MKIN_0       MFP_CFG_IN(GPIO100, AF1)
-#define GPIO101_KP_MKIN_1       MFP_CFG_IN(GPIO101, AF1)
-#define GPIO102_KP_MKIN_2       MFP_CFG_IN(GPIO102, AF1)
-#define GPIO34_KP_MKIN_3        MFP_CFG_IN(GPIO34, AF2)
-#define GPIO37_KP_MKIN_3        MFP_CFG_IN(GPIO37, AF3)
-#define GPIO97_KP_MKIN_3        MFP_CFG_IN(GPIO97, AF3)
-#define GPIO98_KP_MKIN_4        MFP_CFG_IN(GPIO98, AF3)
-#define GPIO38_KP_MKIN_4        MFP_CFG_IN(GPIO38, AF2)
-#define GPIO39_KP_MKIN_4        MFP_CFG_IN(GPIO39, AF1)
-#define GPIO16_KP_MKIN_5        MFP_CFG_IN(GPIO16, AF1)
-#define GPIO90_KP_MKIN_5        MFP_CFG_IN(GPIO90, AF1)
-#define GPIO99_KP_MKIN_5        MFP_CFG_IN(GPIO99, AF3)
-#define GPIO17_KP_MKIN_6        MFP_CFG_IN(GPIO17, AF1)
-#define GPIO91_KP_MKIN_6        MFP_CFG_IN(GPIO91, AF1)
-#define GPIO95_KP_MKIN_6        MFP_CFG_IN(GPIO95, AF3)
-#define GPIO13_KP_MKIN_7        MFP_CFG_IN(GPIO13, AF3)
-#define GPIO36_KP_MKIN_7        MFP_CFG_IN(GPIO36, AF3)
-#define GPIO103_KP_MKOUT_0      MFP_CFG_OUT(GPIO103, AF2, DRIVE_HIGH)
-#define GPIO104_KP_MKOUT_1      MFP_CFG_OUT(GPIO104, AF2, DRIVE_HIGH)
-#define GPIO105_KP_MKOUT_2      MFP_CFG_OUT(GPIO105, AF2, DRIVE_HIGH)
-#define GPIO106_KP_MKOUT_3      MFP_CFG_OUT(GPIO106, AF2, DRIVE_HIGH)
-#define GPIO107_KP_MKOUT_4      MFP_CFG_OUT(GPIO107, AF2, DRIVE_HIGH)
-#define GPIO108_KP_MKOUT_5      MFP_CFG_OUT(GPIO108, AF2, DRIVE_HIGH)
-#define GPIO35_KP_MKOUT_6       MFP_CFG_OUT(GPIO35, AF2, DRIVE_HIGH)
-#define GPIO22_KP_MKOUT_7       MFP_CFG_OUT(GPIO22, AF1, DRIVE_HIGH)
-#define GPIO40_KP_MKOUT_6       MFP_CFG_OUT(GPIO40, AF1, DRIVE_HIGH)
-#define GPIO41_KP_MKOUT_7       MFP_CFG_OUT(GPIO41, AF1, DRIVE_HIGH)
-#define GPIO96_KP_MKOUT_6       MFP_CFG_OUT(GPIO96, AF3, DRIVE_HIGH)
-
-/* USB P3 */
-#define GPIO10_USB_P3_5         MFP_CFG_IN(GPIO10, AF3)
-#define GPIO11_USB_P3_1         MFP_CFG_IN(GPIO11, AF3)
-#define GPIO30_USB_P3_2         MFP_CFG_OUT(GPIO30, AF3, DRIVE_LOW)
-#define GPIO31_USB_P3_6         MFP_CFG_OUT(GPIO31, AF3, DRIVE_LOW)
-#define GPIO56_USB_P3_4         MFP_CFG_OUT(GPIO56, AF1, DRIVE_LOW)
-#define GPIO86_USB_P3_5         MFP_CFG_IN(GPIO86, AF3)
-#define GPIO87_USB_P3_1         MFP_CFG_IN(GPIO87, AF3)
-#define GPIO90_USB_P3_5         MFP_CFG_IN(GPIO90, AF2)
-#define GPIO91_USB_P3_1         MFP_CFG_IN(GPIO91, AF2)
-#define GPIO113_USB_P3_3        MFP_CFG_IN(GPIO113, AF3)
-
-/* USB P2 */
-#define GPIO34_USB_P2_2         MFP_CFG_OUT(GPIO34, AF1, DRIVE_LOW)
-#define GPIO35_USB_P2_1         MFP_CFG_IN(GPIO35, AF2)
-#define GPIO36_USB_P2_4         MFP_CFG_OUT(GPIO36, AF1, DRIVE_LOW)
-#define GPIO37_USB_P2_8         MFP_CFG_OUT(GPIO37, AF1, DRIVE_LOW)
-#define GPIO38_USB_P2_3         MFP_CFG_IN(GPIO38, AF3)
-#define GPIO39_USB_P2_6         MFP_CFG_OUT(GPIO39, AF1, DRIVE_LOW)
-#define GPIO40_USB_P2_5         MFP_CFG_IN(GPIO40, AF3)
-#define GPIO41_USB_P2_7         MFP_CFG_IN(GPIO41, AF2)
-#define GPIO53_USB_P2_3         MFP_CFG_IN(GPIO53, AF2)
-
-/* USB Host Port 1/2 */
-#define GPIO88_USBH1_PWR        MFP_CFG_IN(GPIO88, AF1)
-#define GPIO89_USBH1_PEN        MFP_CFG_OUT(GPIO89, AF2, DRIVE_LOW)
-#define GPIO119_USBH2_PWR       MFP_CFG_IN(GPIO119, AF1)
-#define GPIO120_USBH2_PEN       MFP_CFG_OUT(GPIO120, AF2, DRIVE_LOW)
-
-/* QCI - default to Master Mode: CIF_FV/CIF_LV Direction In */
-#define GPIO115_CIF_DD_3        MFP_CFG_IN(GPIO115, AF2)
-#define GPIO116_CIF_DD_2        MFP_CFG_IN(GPIO116, AF1)
-#define GPIO12_CIF_DD_7         MFP_CFG_IN(GPIO12, AF2)
-#define GPIO17_CIF_DD_6         MFP_CFG_IN(GPIO17, AF2)
-#define GPIO23_CIF_MCLK         MFP_CFG_OUT(GPIO23, AF1, DRIVE_LOW)
-#define GPIO24_CIF_FV           MFP_CFG_IN(GPIO24, AF1)
-#define GPIO25_CIF_LV           MFP_CFG_IN(GPIO25, AF1)
-#define GPIO26_CIF_PCLK         MFP_CFG_IN(GPIO26, AF2)
-#define GPIO27_CIF_DD_0         MFP_CFG_IN(GPIO27, AF3)
-#define GPIO42_CIF_MCLK         MFP_CFG_OUT(GPIO42, AF3, DRIVE_LOW)
-#define GPIO43_CIF_FV           MFP_CFG_IN(GPIO43, AF3)
-#define GPIO44_CIF_LV           MFP_CFG_IN(GPIO44, AF3)
-#define GPIO45_CIF_PCLK         MFP_CFG_IN(GPIO45, AF3)
-#define GPIO47_CIF_DD_0         MFP_CFG_IN(GPIO47, AF1)
-#define GPIO48_CIF_DD_5         MFP_CFG_IN(GPIO48, AF1)
-#define GPIO50_CIF_DD_3         MFP_CFG_IN(GPIO50, AF1)
-#define GPIO51_CIF_DD_2         MFP_CFG_IN(GPIO51, AF1)
-#define GPIO52_CIF_DD_4         MFP_CFG_IN(GPIO52, AF1)
-#define GPIO53_CIF_MCLK         MFP_CFG_OUT(GPIO53, AF2, DRIVE_LOW)
-#define GPIO54_CIF_PCLK         MFP_CFG_IN(GPIO54, AF3)
-#define GPIO55_CIF_DD_1         MFP_CFG_IN(GPIO55, AF1)
-#define GPIO81_CIF_DD_0         MFP_CFG_IN(GPIO81, AF2)
-#define GPIO82_CIF_DD_5         MFP_CFG_IN(GPIO82, AF3)
-#define GPIO83_CIF_DD_4         MFP_CFG_IN(GPIO83, AF3)
-#define GPIO84_CIF_FV           MFP_CFG_IN(GPIO84, AF3)
-#define GPIO85_CIF_LV           MFP_CFG_IN(GPIO85, AF3)
-#define GPIO90_CIF_DD_4         MFP_CFG_IN(GPIO90, AF3)
-#define GPIO91_CIF_DD_5         MFP_CFG_IN(GPIO91, AF3)
-#define GPIO93_CIF_DD_6         MFP_CFG_IN(GPIO93, AF2)
-#define GPIO94_CIF_DD_5         MFP_CFG_IN(GPIO94, AF2)
-#define GPIO95_CIF_DD_4         MFP_CFG_IN(GPIO95, AF2)
-#define GPIO98_CIF_DD_0         MFP_CFG_IN(GPIO98, AF2)
-#define GPIO103_CIF_DD_3        MFP_CFG_IN(GPIO103, AF1)
-#define GPIO104_CIF_DD_2        MFP_CFG_IN(GPIO104, AF1)
-#define GPIO105_CIF_DD_1        MFP_CFG_IN(GPIO105, AF1)
-#define GPIO106_CIF_DD_9        MFP_CFG_IN(GPIO106, AF1)
-#define GPIO107_CIF_DD_8        MFP_CFG_IN(GPIO107, AF1)
-#define GPIO108_CIF_DD_7        MFP_CFG_IN(GPIO108, AF1)
-#define GPIO114_CIF_DD_1        MFP_CFG_IN(GPIO114, AF1)
-
-/* Universal Subscriber ID Interface */
-#define GPIO114_UVS0            MFP_CFG_OUT(GPIO114, AF2, DRIVE_LOW)
-#define GPIO115_nUVS1           MFP_CFG_OUT(GPIO115, AF2, DRIVE_LOW)
-#define GPIO116_nUVS2           MFP_CFG_OUT(GPIO116, AF2, DRIVE_LOW)
-#define GPIO14_UCLK             MFP_CFG_OUT(GPIO14, AF3, DRIVE_LOW)
-#define GPIO91_UCLK             MFP_CFG_OUT(GPIO91, AF2, DRIVE_LOW)
-#define GPIO19_nURST            MFP_CFG_OUT(GPIO19, AF3, DRIVE_LOW)
-#define GPIO90_nURST            MFP_CFG_OUT(GPIO90, AF2, DRIVE_LOW)
-#define GPIO116_UDET            MFP_CFG_IN(GPIO116, AF3)
-#define GPIO114_UEN             MFP_CFG_OUT(GPIO114, AF1, DRIVE_LOW)
-#define GPIO115_UEN             MFP_CFG_OUT(GPIO115, AF1, DRIVE_LOW)
-
-/* Mobile Scalable Link (MSL) Interface */
-#define GPIO81_BB_OB_DAT_0      MFP_CFG_OUT(GPIO81, AF2, DRIVE_LOW)
-#define GPIO48_BB_OB_DAT_1      MFP_CFG_OUT(GPIO48, AF1, DRIVE_LOW)
-#define GPIO50_BB_OB_DAT_2      MFP_CFG_OUT(GPIO50, AF1, DRIVE_LOW)
-#define GPIO51_BB_OB_DAT_3      MFP_CFG_OUT(GPIO51, AF1, DRIVE_LOW)
-#define GPIO52_BB_OB_CLK        MFP_CFG_OUT(GPIO52, AF1, DRIVE_LOW)
-#define GPIO53_BB_OB_STB        MFP_CFG_OUT(GPIO53, AF1, DRIVE_LOW)
-#define GPIO54_BB_OB_WAIT       MFP_CFG_IN(GPIO54, AF2)
-#define GPIO82_BB_IB_DAT_0      MFP_CFG_IN(GPIO82, AF2)
-#define GPIO55_BB_IB_DAT_1      MFP_CFG_IN(GPIO55, AF2)
-#define GPIO56_BB_IB_DAT_2      MFP_CFG_IN(GPIO56, AF2)
-#define GPIO57_BB_IB_DAT_3      MFP_CFG_IN(GPIO57, AF2)
-#define GPIO83_BB_IB_CLK        MFP_CFG_IN(GPIO83, AF2)
-#define GPIO84_BB_IB_STB        MFP_CFG_IN(GPIO84, AF2)
-#define GPIO85_BB_IB_WAIT       MFP_CFG_OUT(GPIO85, AF2, DRIVE_LOW)
-
-/* Memory Stick Host Controller */
-#define GPIO92_MSBS             MFP_CFG_OUT(GPIO92, AF2, DRIVE_LOW)
-#define GPIO109_MSSDIO          MFP_CFG_IN(GPIO109, AF2)
-#define GPIO112_nMSINS          MFP_CFG_IN(GPIO112, AF2)
-#define GPIO32_MSSCLK           MFP_CFG_OUT(GPIO32, AF1, DRIVE_LOW)
-
-extern int keypad_set_wake(unsigned int on);
-#endif /* __ASM_ARCH_MFP_PXA27X_H */
diff --git a/include/asm-arm/arch-pxa/mfp-pxa2xx.h b/include/asm-arm/arch-pxa/mfp-pxa2xx.h
deleted file mode 100644
index 8de1c0dae624..000000000000
--- a/include/asm-arm/arch-pxa/mfp-pxa2xx.h
+++ /dev/null
@@ -1,133 +0,0 @@
-#ifndef __ASM_ARCH_MFP_PXA2XX_H
-#define __ASM_ARCH_MFP_PXA2XX_H
-
-#include <asm/arch/mfp.h>
-
-/*
- * the following MFP_xxx bit definitions in mfp.h are re-used for pxa2xx:
- *
- *  MFP_PIN(x)
- *  MFP_AFx
- *  MFP_LPM_DRIVE_{LOW, HIGH}
- *  MFP_LPM_EDGE_x
- *
- * other MFP_x bit definitions will be ignored
- *
- * and adds the below two bits specifically for pxa2xx:
- *
- * bit     23 - Input/Output (PXA2xx specific)
- * bit     24 - Wakeup Enable(PXA2xx specific)
- */
-
-#define MFP_DIR_IN              (0x0 << 23)
-#define MFP_DIR_OUT             (0x1 << 23)
-#define MFP_DIR_MASK            (0x1 << 23)
-#define MFP_DIR(x)              (((x) >> 23) & 0x1)
-
-#define MFP_LPM_CAN_WAKEUP      (0x1 << 24)
-#define WAKEUP_ON_EDGE_RISE     (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE)
-#define WAKEUP_ON_EDGE_FALL     (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_FALL)
-#define WAKEUP_ON_EDGE_BOTH     (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_BOTH)
-
-/* specifically for enabling wakeup on keypad GPIOs */
-#define WAKEUP_ON_LEVEL_HIGH    (MFP_LPM_CAN_WAKEUP)
-
-#define MFP_CFG_IN(pin, af)             \
-        ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK)) |\
-         (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DIR_IN))
-
-/* NOTE:  pins configured as output _must_ provide a low power state,
- * and this state should help to minimize the power dissipation.
- */
-#define MFP_CFG_OUT(pin, af, state)     \
-        ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK | MFP_LPM_STATE_MASK)) |\
-         (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state))
-
-/* Common configurations for pxa25x and pxa27x
- *
- * Note: pins configured as GPIO are always initialized to input
- * so not to cause any side effect
- */
-#define GPIO0_GPIO      MFP_CFG_IN(GPIO0, AF0)
-#define GPIO1_GPIO      MFP_CFG_IN(GPIO1, AF0)
-#define GPIO9_GPIO      MFP_CFG_IN(GPIO9, AF0)
-#define GPIO10_GPIO     MFP_CFG_IN(GPIO10, AF0)
-#define GPIO11_GPIO     MFP_CFG_IN(GPIO11, AF0)
-#define GPIO12_GPIO     MFP_CFG_IN(GPIO12, AF0)
-#define GPIO13_GPIO     MFP_CFG_IN(GPIO13, AF0)
-#define GPIO14_GPIO     MFP_CFG_IN(GPIO14, AF0)
-#define GPIO15_GPIO     MFP_CFG_IN(GPIO15, AF0)
-#define GPIO16_GPIO     MFP_CFG_IN(GPIO16, AF0)
-#define GPIO17_GPIO     MFP_CFG_IN(GPIO17, AF0)
-#define GPIO18_GPIO     MFP_CFG_IN(GPIO18, AF0)
-#define GPIO19_GPIO     MFP_CFG_IN(GPIO19, AF0)
-#define GPIO20_GPIO     MFP_CFG_IN(GPIO20, AF0)
-#define GPIO21_GPIO     MFP_CFG_IN(GPIO21, AF0)
-#define GPIO22_GPIO     MFP_CFG_IN(GPIO22, AF0)
-#define GPIO23_GPIO     MFP_CFG_IN(GPIO23, AF0)
-#define GPIO24_GPIO     MFP_CFG_IN(GPIO24, AF0)
-#define GPIO25_GPIO     MFP_CFG_IN(GPIO25, AF0)
-#define GPIO26_GPIO     MFP_CFG_IN(GPIO26, AF0)
-#define GPIO27_GPIO     MFP_CFG_IN(GPIO27, AF0)
-#define GPIO28_GPIO     MFP_CFG_IN(GPIO28, AF0)
-#define GPIO29_GPIO     MFP_CFG_IN(GPIO29, AF0)
-#define GPIO30_GPIO     MFP_CFG_IN(GPIO30, AF0)
-#define GPIO31_GPIO     MFP_CFG_IN(GPIO31, AF0)
-#define GPIO32_GPIO     MFP_CFG_IN(GPIO32, AF0)
-#define GPIO33_GPIO     MFP_CFG_IN(GPIO33, AF0)
-#define GPIO34_GPIO     MFP_CFG_IN(GPIO34, AF0)
-#define GPIO35_GPIO     MFP_CFG_IN(GPIO35, AF0)
-#define GPIO36_GPIO     MFP_CFG_IN(GPIO36, AF0)
-#define GPIO37_GPIO     MFP_CFG_IN(GPIO37, AF0)
-#define GPIO38_GPIO     MFP_CFG_IN(GPIO38, AF0)
-#define GPIO39_GPIO     MFP_CFG_IN(GPIO39, AF0)
-#define GPIO40_GPIO     MFP_CFG_IN(GPIO40, AF0)
-#define GPIO41_GPIO     MFP_CFG_IN(GPIO41, AF0)
-#define GPIO42_GPIO     MFP_CFG_IN(GPIO42, AF0)
-#define GPIO43_GPIO     MFP_CFG_IN(GPIO43, AF0)
-#define GPIO44_GPIO     MFP_CFG_IN(GPIO44, AF0)
-#define GPIO45_GPIO     MFP_CFG_IN(GPIO45, AF0)
-#define GPIO46_GPIO     MFP_CFG_IN(GPIO46, AF0)
-#define GPIO47_GPIO     MFP_CFG_IN(GPIO47, AF0)
-#define GPIO48_GPIO     MFP_CFG_IN(GPIO48, AF0)
-#define GPIO49_GPIO     MFP_CFG_IN(GPIO49, AF0)
-#define GPIO50_GPIO     MFP_CFG_IN(GPIO50, AF0)
-#define GPIO51_GPIO     MFP_CFG_IN(GPIO51, AF0)
-#define GPIO52_GPIO     MFP_CFG_IN(GPIO52, AF0)
-#define GPIO53_GPIO     MFP_CFG_IN(GPIO53, AF0)
-#define GPIO54_GPIO     MFP_CFG_IN(GPIO54, AF0)
-#define GPIO55_GPIO     MFP_CFG_IN(GPIO55, AF0)
-#define GPIO56_GPIO     MFP_CFG_IN(GPIO56, AF0)
-#define GPIO57_GPIO     MFP_CFG_IN(GPIO57, AF0)
-#define GPIO58_GPIO     MFP_CFG_IN(GPIO58, AF0)
-#define GPIO59_GPIO     MFP_CFG_IN(GPIO59, AF0)
-#define GPIO60_GPIO     MFP_CFG_IN(GPIO60, AF0)
-#define GPIO61_GPIO     MFP_CFG_IN(GPIO61, AF0)
-#define GPIO62_GPIO     MFP_CFG_IN(GPIO62, AF0)
-#define GPIO63_GPIO     MFP_CFG_IN(GPIO63, AF0)
-#define GPIO64_GPIO     MFP_CFG_IN(GPIO64, AF0)
-#define GPIO65_GPIO     MFP_CFG_IN(GPIO65, AF0)
-#define GPIO66_GPIO     MFP_CFG_IN(GPIO66, AF0)
-#define GPIO67_GPIO     MFP_CFG_IN(GPIO67, AF0)
-#define GPIO68_GPIO     MFP_CFG_IN(GPIO68, AF0)
-#define GPIO69_GPIO     MFP_CFG_IN(GPIO69, AF0)
-#define GPIO70_GPIO     MFP_CFG_IN(GPIO70, AF0)
-#define GPIO71_GPIO     MFP_CFG_IN(GPIO71, AF0)
-#define GPIO72_GPIO     MFP_CFG_IN(GPIO72, AF0)
-#define GPIO73_GPIO     MFP_CFG_IN(GPIO73, AF0)
-#define GPIO74_GPIO     MFP_CFG_IN(GPIO74, AF0)
-#define GPIO75_GPIO     MFP_CFG_IN(GPIO75, AF0)
-#define GPIO76_GPIO     MFP_CFG_IN(GPIO76, AF0)
-#define GPIO77_GPIO     MFP_CFG_IN(GPIO77, AF0)
-#define GPIO78_GPIO     MFP_CFG_IN(GPIO78, AF0)
-#define GPIO79_GPIO     MFP_CFG_IN(GPIO79, AF0)
-#define GPIO80_GPIO     MFP_CFG_IN(GPIO80, AF0)
-#define GPIO81_GPIO     MFP_CFG_IN(GPIO81, AF0)
-#define GPIO82_GPIO     MFP_CFG_IN(GPIO82, AF0)
-#define GPIO83_GPIO     MFP_CFG_IN(GPIO83, AF0)
-#define GPIO84_GPIO     MFP_CFG_IN(GPIO84, AF0)
-
-extern void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num);
-extern void pxa2xx_mfp_set_lpm(int mfp, unsigned long lpm);
-extern int gpio_set_wake(unsigned int gpio, unsigned int on);
-#endif /* __ASM_ARCH_MFP_PXA2XX_H */
diff --git a/include/asm-arm/arch-pxa/mfp-pxa300.h b/include/asm-arm/arch-pxa/mfp-pxa300.h
deleted file mode 100644
index bb410313556f..000000000000
--- a/include/asm-arm/arch-pxa/mfp-pxa300.h
+++ /dev/null
@@ -1,575 +0,0 @@
-/*
- * linux/include/asm-arm/arch-pxa/mfp-pxa300.h
- *
- * PXA300/PXA310 specific MFP configuration definitions
- *
- * Copyright (C) 2007 Marvell International Ltd.
- * 2007-08-21: eric miao <eric.miao@marvell.com>
- *             initial version
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MFP_PXA300_H
-#define __ASM_ARCH_MFP_PXA300_H
-
-#include <asm/arch/mfp.h>
-#include <asm/arch/mfp-pxa3xx.h>
-
-/* GPIO */
-#define GPIO46_GPIO             MFP_CFG(GPIO46, AF1)
-#define GPIO49_GPIO             MFP_CFG(GPIO49, AF3)
-#define GPIO50_GPIO             MFP_CFG(GPIO50, AF2)
-#define GPIO51_GPIO             MFP_CFG(GPIO51, AF3)
-#define GPIO52_GPIO             MFP_CFG(GPIO52, AF3)
-#define GPIO56_GPIO             MFP_CFG(GPIO56, AF0)
-#define GPIO58_GPIO             MFP_CFG(GPIO58, AF0)
-#define GPIO59_GPIO             MFP_CFG(GPIO59, AF0)
-#define GPIO60_GPIO             MFP_CFG(GPIO60, AF0)
-#define GPIO61_GPIO             MFP_CFG(GPIO61, AF0)
-#define GPIO62_GPIO             MFP_CFG(GPIO62, AF0)
-
-#ifdef CONFIG_CPU_PXA310
-#define GPIO7_2_GPIO            MFP_CFG(GPIO7_2, AF0)
-#define GPIO8_2_GPIO            MFP_CFG(GPIO8_2, AF0)
-#define GPIO9_2_GPIO            MFP_CFG(GPIO9_2, AF0)
-#define GPIO10_2_GPIO           MFP_CFG(GPIO10_2, AF0)
-#define GPIO11_2_GPIO           MFP_CFG(GPIO11_2, AF0)
-#define GPIO12_2_GPIO           MFP_CFG(GPIO12_2, AF0)
-#endif
-
-/* Chip Select */
-#define GPIO2_nCS3              MFP_CFG(GPIO2,  AF1)
-
-/* AC97 */
-#define GPIO23_AC97_nACRESET    MFP_CFG(GPIO23, AF1)
-#define GPIO24_AC97_SYSCLK      MFP_CFG(GPIO24, AF1)
-#define GPIO29_AC97_BITCLK      MFP_CFG(GPIO29, AF1)
-#define GPIO25_AC97_SDATA_IN_0  MFP_CFG(GPIO25, AF1)
-#define GPIO26_AC97_SDATA_IN_1  MFP_CFG(GPIO26, AF1)
-#define GPIO17_AC97_SDATA_IN_2  MFP_CFG(GPIO17, AF3)
-#define GPIO21_AC97_SDATA_IN_2  MFP_CFG(GPIO21, AF2)
-#define GPIO18_AC97_SDATA_IN_3  MFP_CFG(GPIO18, AF3)
-#define GPIO22_AC97_SDATA_IN_3  MFP_CFG(GPIO22, AF2)
-#define GPIO27_AC97_SDATA_OUT   MFP_CFG(GPIO27, AF1)
-#define GPIO28_AC97_SYNC        MFP_CFG(GPIO28, AF1)
-
-/* I2C */
-#define GPIO21_I2C_SCL          MFP_CFG_LPM(GPIO21, AF1, PULL_HIGH)
-#define GPIO22_I2C_SDA          MFP_CFG_LPM(GPIO22, AF1, PULL_HIGH)
-
-/* QCI */
-#define GPIO39_CI_DD_0          MFP_CFG_DRV(GPIO39, AF1, DS04X)
-#define GPIO40_CI_DD_1          MFP_CFG_DRV(GPIO40, AF1, DS04X)
-#define GPIO41_CI_DD_2          MFP_CFG_DRV(GPIO41, AF1, DS04X)
-#define GPIO42_CI_DD_3          MFP_CFG_DRV(GPIO42, AF1, DS04X)
-#define GPIO43_CI_DD_4          MFP_CFG_DRV(GPIO43, AF1, DS04X)
-#define GPIO44_CI_DD_5          MFP_CFG_DRV(GPIO44, AF1, DS04X)
-#define GPIO45_CI_DD_6          MFP_CFG_DRV(GPIO45, AF1, DS04X)
-#define GPIO46_CI_DD_7          MFP_CFG_DRV(GPIO46, AF0, DS04X)
-#define GPIO47_CI_DD_8          MFP_CFG_DRV(GPIO47, AF1, DS04X)
-#define GPIO48_CI_DD_9          MFP_CFG_DRV(GPIO48, AF1, DS04X)
-#define GPIO52_CI_HSYNC         MFP_CFG_DRV(GPIO52, AF0, DS04X)
-#define GPIO51_CI_VSYNC         MFP_CFG_DRV(GPIO51, AF0, DS04X)
-#define GPIO49_CI_MCLK          MFP_CFG_DRV(GPIO49, AF0, DS04X)
-#define GPIO50_CI_PCLK          MFP_CFG_DRV(GPIO50, AF0, DS04X)
-
-/* KEYPAD */
-#define GPIO3_KP_DKIN_6         MFP_CFG_LPM(GPIO3,   AF2, FLOAT)
-#define GPIO4_KP_DKIN_7         MFP_CFG_LPM(GPIO4,   AF2, FLOAT)
-#define GPIO16_KP_DKIN_6        MFP_CFG_LPM(GPIO16,  AF6, FLOAT)
-#define GPIO83_KP_DKIN_2        MFP_CFG_LPM(GPIO83,  AF5, FLOAT)
-#define GPIO84_KP_DKIN_1        MFP_CFG_LPM(GPIO84,  AF5, FLOAT)
-#define GPIO85_KP_DKIN_0        MFP_CFG_LPM(GPIO85,  AF3, FLOAT)
-#define GPIO86_KP_DKIN_1        MFP_CFG_LPM(GPIO86,  AF3, FLOAT)
-#define GPIO87_KP_DKIN_2        MFP_CFG_LPM(GPIO87,  AF3, FLOAT)
-#define GPIO88_KP_DKIN_3        MFP_CFG_LPM(GPIO88,  AF3, FLOAT)
-#define GPIO89_KP_DKIN_3        MFP_CFG_LPM(GPIO89,  AF3, FLOAT)
-#define GPIO107_KP_DKIN_0       MFP_CFG_LPM(GPIO107, AF2, FLOAT)
-#define GPIO108_KP_DKIN_1       MFP_CFG_LPM(GPIO108, AF2, FLOAT)
-#define GPIO109_KP_DKIN_2       MFP_CFG_LPM(GPIO109, AF2, FLOAT)
-#define GPIO110_KP_DKIN_3       MFP_CFG_LPM(GPIO110, AF2, FLOAT)
-#define GPIO111_KP_DKIN_4       MFP_CFG_LPM(GPIO111, AF2, FLOAT)
-#define GPIO112_KP_DKIN_5       MFP_CFG_LPM(GPIO112, AF2, FLOAT)
-#define GPIO113_KP_DKIN_6       MFP_CFG_LPM(GPIO113, AF2, FLOAT)
-#define GPIO114_KP_DKIN_7       MFP_CFG_LPM(GPIO114, AF2, FLOAT)
-#define GPIO115_KP_DKIN_0       MFP_CFG_LPM(GPIO115, AF2, FLOAT)
-#define GPIO116_KP_DKIN_1       MFP_CFG_LPM(GPIO116, AF2, FLOAT)
-#define GPIO117_KP_DKIN_2       MFP_CFG_LPM(GPIO117, AF2, FLOAT)
-#define GPIO118_KP_DKIN_3       MFP_CFG_LPM(GPIO118, AF2, FLOAT)
-#define GPIO119_KP_DKIN_4       MFP_CFG_LPM(GPIO119, AF2, FLOAT)
-#define GPIO120_KP_DKIN_5       MFP_CFG_LPM(GPIO120, AF2, FLOAT)
-#define GPIO121_KP_DKIN_6       MFP_CFG_LPM(GPIO121, AF2, FLOAT)
-#define GPIO122_KP_DKIN_5       MFP_CFG_LPM(GPIO122, AF2, FLOAT)
-#define GPIO123_KP_DKIN_4       MFP_CFG_LPM(GPIO123, AF2, FLOAT)
-#define GPIO124_KP_DKIN_3       MFP_CFG_LPM(GPIO124, AF2, FLOAT)
-#define GPIO127_KP_DKIN_0       MFP_CFG_LPM(GPIO127, AF5, FLOAT)
-#define GPIO0_2_KP_DKIN_0       MFP_CFG_LPM(GPIO0_2, AF2, FLOAT)
-#define GPIO1_2_KP_DKIN_1       MFP_CFG_LPM(GPIO1_2, AF2, FLOAT)
-#define GPIO2_2_KP_DKIN_6       MFP_CFG_LPM(GPIO2_2, AF2, FLOAT)
-#define GPIO3_2_KP_DKIN_7       MFP_CFG_LPM(GPIO3_2, AF2, FLOAT)
-#define GPIO4_2_KP_DKIN_1       MFP_CFG_LPM(GPIO4_2, AF2, FLOAT)
-#define GPIO5_2_KP_DKIN_0       MFP_CFG_LPM(GPIO5_2, AF2, FLOAT)
-
-#define GPIO5_KP_MKIN_0         MFP_CFG_LPM(GPIO5,   AF2, FLOAT)
-#define GPIO6_KP_MKIN_1         MFP_CFG_LPM(GPIO6,   AF2, FLOAT)
-#define GPIO9_KP_MKIN_6         MFP_CFG_LPM(GPIO9,   AF3, FLOAT)
-#define GPIO10_KP_MKIN_7        MFP_CFG_LPM(GPIO10,  AF3, FLOAT)
-#define GPIO70_KP_MKIN_6        MFP_CFG_LPM(GPIO70,  AF3, FLOAT)
-#define GPIO71_KP_MKIN_7        MFP_CFG_LPM(GPIO71,  AF3, FLOAT)
-#define GPIO100_KP_MKIN_6       MFP_CFG_LPM(GPIO100, AF7, FLOAT)
-#define GPIO101_KP_MKIN_7       MFP_CFG_LPM(GPIO101, AF7, FLOAT)
-#define GPIO112_KP_MKIN_6       MFP_CFG_LPM(GPIO112, AF4, FLOAT)
-#define GPIO113_KP_MKIN_7       MFP_CFG_LPM(GPIO113, AF4, FLOAT)
-#define GPIO115_KP_MKIN_0       MFP_CFG_LPM(GPIO115, AF1, FLOAT)
-#define GPIO116_KP_MKIN_1       MFP_CFG_LPM(GPIO116, AF1, FLOAT)
-#define GPIO117_KP_MKIN_2       MFP_CFG_LPM(GPIO117, AF1, FLOAT)
-#define GPIO118_KP_MKIN_3       MFP_CFG_LPM(GPIO118, AF1, FLOAT)
-#define GPIO119_KP_MKIN_4       MFP_CFG_LPM(GPIO119, AF1, FLOAT)
-#define GPIO120_KP_MKIN_5       MFP_CFG_LPM(GPIO120, AF1, FLOAT)
-#define GPIO125_KP_MKIN_2       MFP_CFG_LPM(GPIO125, AF2, FLOAT)
-#define GPIO2_2_KP_MKIN_6       MFP_CFG_LPM(GPIO2_2, AF1, FLOAT)
-#define GPIO3_2_KP_MKIN_7       MFP_CFG_LPM(GPIO3_2, AF1, FLOAT)
-
-#define GPIO7_KP_MKOUT_5        MFP_CFG_LPM(GPIO7,   AF1, DRIVE_HIGH)
-#define GPIO11_KP_MKOUT_5       MFP_CFG_LPM(GPIO11,  AF3, DRIVE_HIGH)
-#define GPIO12_KP_MKOUT_6       MFP_CFG_LPM(GPIO12,  AF3, DRIVE_HIGH)
-#define GPIO13_KP_MKOUT_7       MFP_CFG_LPM(GPIO13,  AF3, DRIVE_HIGH)
-#define GPIO19_KP_MKOUT_4       MFP_CFG_LPM(GPIO19,  AF3, DRIVE_HIGH)
-#define GPIO20_KP_MKOUT_5       MFP_CFG_LPM(GPIO20,  AF3, DRIVE_HIGH)
-#define GPIO38_KP_MKOUT_5       MFP_CFG_LPM(GPIO38,  AF5, DRIVE_HIGH)
-#define GPIO53_KP_MKOUT_6       MFP_CFG_LPM(GPIO53,  AF5, DRIVE_HIGH)
-#define GPIO78_KP_MKOUT_7       MFP_CFG_LPM(GPIO78,  AF5, DRIVE_HIGH)
-#define GPIO85_KP_MKOUT_0       MFP_CFG_LPM(GPIO85,  AF2, DRIVE_HIGH)
-#define GPIO86_KP_MKOUT_1       MFP_CFG_LPM(GPIO86,  AF2, DRIVE_HIGH)
-#define GPIO87_KP_MKOUT_2       MFP_CFG_LPM(GPIO87,  AF2, DRIVE_HIGH)
-#define GPIO88_KP_MKOUT_3       MFP_CFG_LPM(GPIO88,  AF2, DRIVE_HIGH)
-#define GPIO104_KP_MKOUT_6      MFP_CFG_LPM(GPIO104, AF5, DRIVE_HIGH)
-#define GPIO105_KP_MKOUT_7      MFP_CFG_LPM(GPIO105, AF5, DRIVE_HIGH)
-#define GPIO121_KP_MKOUT_0      MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH)
-#define GPIO122_KP_MKOUT_1      MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH)
-#define GPIO123_KP_MKOUT_2      MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH)
-#define GPIO124_KP_MKOUT_3      MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH)
-#define GPIO125_KP_MKOUT_4      MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH)
-#define GPIO126_KP_MKOUT_7      MFP_CFG_LPM(GPIO126, AF4, DRIVE_HIGH)
-#define GPIO5_2_KP_MKOUT_6      MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH)
-#define GPIO4_2_KP_MKOUT_5      MFP_CFG_LPM(GPIO4_2, AF1, DRIVE_HIGH)
-#define GPIO6_2_KP_MKOUT_7      MFP_CFG_LPM(GPIO6_2, AF1, DRIVE_HIGH)
-
-/* LCD */
-#define GPIO54_LCD_LDD_0        MFP_CFG_DRV(GPIO54, AF1, DS01X)
-#define GPIO55_LCD_LDD_1        MFP_CFG_DRV(GPIO55, AF1, DS01X)
-#define GPIO56_LCD_LDD_2        MFP_CFG_DRV(GPIO56, AF1, DS01X)
-#define GPIO57_LCD_LDD_3        MFP_CFG_DRV(GPIO57, AF1, DS01X)
-#define GPIO58_LCD_LDD_4        MFP_CFG_DRV(GPIO58, AF1, DS01X)
-#define GPIO59_LCD_LDD_5        MFP_CFG_DRV(GPIO59, AF1, DS01X)
-#define GPIO60_LCD_LDD_6        MFP_CFG_DRV(GPIO60, AF1, DS01X)
-#define GPIO61_LCD_LDD_7        MFP_CFG_DRV(GPIO61, AF1, DS01X)
-#define GPIO62_LCD_LDD_8        MFP_CFG_DRV(GPIO62, AF1, DS01X)
-#define GPIO63_LCD_LDD_9        MFP_CFG_DRV(GPIO63, AF1, DS01X)
-#define GPIO64_LCD_LDD_10       MFP_CFG_DRV(GPIO64, AF1, DS01X)
-#define GPIO65_LCD_LDD_11       MFP_CFG_DRV(GPIO65, AF1, DS01X)
-#define GPIO66_LCD_LDD_12       MFP_CFG_DRV(GPIO66, AF1, DS01X)
-#define GPIO67_LCD_LDD_13       MFP_CFG_DRV(GPIO67, AF1, DS01X)
-#define GPIO68_LCD_LDD_14       MFP_CFG_DRV(GPIO68, AF1, DS01X)
-#define GPIO69_LCD_LDD_15       MFP_CFG_DRV(GPIO69, AF1, DS01X)
-#define GPIO70_LCD_LDD_16       MFP_CFG_DRV(GPIO70, AF1, DS01X)
-#define GPIO71_LCD_LDD_17       MFP_CFG_DRV(GPIO71, AF1, DS01X)
-#define GPIO62_LCD_CS_N         MFP_CFG_DRV(GPIO62, AF2, DS01X)
-#define GPIO72_LCD_FCLK         MFP_CFG_DRV(GPIO72, AF1, DS01X)
-#define GPIO73_LCD_LCLK         MFP_CFG_DRV(GPIO73, AF1, DS01X)
-#define GPIO74_LCD_PCLK         MFP_CFG_DRV(GPIO74, AF1, DS02X)
-#define GPIO75_LCD_BIAS         MFP_CFG_DRV(GPIO75, AF1, DS01X)
-#define GPIO76_LCD_VSYNC        MFP_CFG_DRV(GPIO76, AF2, DS01X)
-
-#define GPIO15_LCD_CS_N         MFP_CFG_DRV(GPIO15,  AF2, DS01X)
-#define GPIO127_LCD_CS_N        MFP_CFG_DRV(GPIO127, AF1, DS01X)
-#define GPIO63_LCD_VSYNC        MFP_CFG_DRV(GPIO63,  AF2, DS01X)
-
-/* Mini-LCD */
-#define GPIO72_MLCD_FCLK        MFP_CFG_DRV(GPIO72, AF7, DS08X)
-#define GPIO73_MLCD_LCLK        MFP_CFG_DRV(GPIO73, AF7, DS08X)
-#define GPIO54_MLCD_LDD_0       MFP_CFG_DRV(GPIO54, AF7, DS08X)
-#define GPIO55_MLCD_LDD_1       MFP_CFG_DRV(GPIO55, AF7, DS08X)
-#define GPIO56_MLCD_LDD_2       MFP_CFG_DRV(GPIO56, AF7, DS08X)
-#define GPIO57_MLCD_LDD_3       MFP_CFG_DRV(GPIO57, AF7, DS08X)
-#define GPIO58_MLCD_LDD_4       MFP_CFG_DRV(GPIO58, AF7, DS08X)
-#define GPIO59_MLCD_LDD_5       MFP_CFG_DRV(GPIO59, AF7, DS08X)
-#define GPIO60_MLCD_LDD_6       MFP_CFG_DRV(GPIO60, AF7, DS08X)
-#define GPIO61_MLCD_LDD_7       MFP_CFG_DRV(GPIO61, AF7, DS08X)
-#define GPIO62_MLCD_LDD_8       MFP_CFG_DRV(GPIO62, AF7, DS08X)
-#define GPIO63_MLCD_LDD_9       MFP_CFG_DRV(GPIO63, AF7, DS08X)
-#define GPIO64_MLCD_LDD_10      MFP_CFG_DRV(GPIO64, AF7, DS08X)
-#define GPIO65_MLCD_LDD_11      MFP_CFG_DRV(GPIO65, AF7, DS08X)
-#define GPIO66_MLCD_LDD_12      MFP_CFG_DRV(GPIO66, AF7, DS08X)
-#define GPIO67_MLCD_LDD_13      MFP_CFG_DRV(GPIO67, AF7, DS08X)
-#define GPIO68_MLCD_LDD_14      MFP_CFG_DRV(GPIO68, AF7, DS08X)
-#define GPIO69_MLCD_LDD_15      MFP_CFG_DRV(GPIO69, AF7, DS08X)
-#define GPIO74_MLCD_PCLK        MFP_CFG_DRV(GPIO74, AF7, DS08X)
-#define GPIO75_MLCD_BIAS        MFP_CFG_DRV(GPIO75, AF2, DS08X)
-
-/* MMC1 */
-#define GPIO7_MMC1_CLK          MFP_CFG_LPM(GPIO7,  AF4, DRIVE_HIGH)
-#define GPIO8_MMC1_CMD          MFP_CFG_LPM(GPIO8,  AF4, DRIVE_HIGH)
-#define GPIO14_MMC1_CMD         MFP_CFG_LPM(GPIO14, AF5, DRIVE_HIGH)
-#define GPIO15_MMC1_CMD         MFP_CFG_LPM(GPIO15, AF5, DRIVE_HIGH)
-#define GPIO3_MMC1_DAT0         MFP_CFG_LPM(GPIO3,  AF4, DRIVE_HIGH)
-#define GPIO4_MMC1_DAT1         MFP_CFG_LPM(GPIO4,  AF4, DRIVE_HIGH)
-#define GPIO5_MMC1_DAT2         MFP_CFG_LPM(GPIO5,  AF4, DRIVE_HIGH)
-#define GPIO6_MMC1_DAT3         MFP_CFG_LPM(GPIO6,  AF4, DRIVE_HIGH)
-
-/* MMC2 */
-#define GPIO9_MMC2_DAT0         MFP_CFG_LPM(GPIO9,  AF4, PULL_HIGH)
-#define GPIO10_MMC2_DAT1        MFP_CFG_LPM(GPIO10, AF4, PULL_HIGH)
-#define GPIO11_MMC2_DAT2        MFP_CFG_LPM(GPIO11, AF4, PULL_HIGH)
-#define GPIO12_MMC2_DAT3        MFP_CFG_LPM(GPIO12, AF4, PULL_HIGH)
-#define GPIO13_MMC2_CLK         MFP_CFG_LPM(GPIO13, AF4, PULL_HIGH)
-#define GPIO14_MMC2_CMD         MFP_CFG_LPM(GPIO14, AF4, PULL_HIGH)
-#define GPIO77_MMC2_DAT0        MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH)
-#define GPIO78_MMC2_DAT1        MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH)
-#define GPIO79_MMC2_DAT2        MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH)
-#define GPIO80_MMC2_DAT3        MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH)
-#define GPIO81_MMC2_CLK         MFP_CFG_LPM(GPIO81, AF4, PULL_HIGH)
-#define GPIO82_MMC2_CMD         MFP_CFG_LPM(GPIO82, AF4, PULL_HIGH)
-
-/* SSP1 */
-#define GPIO89_SSP1_EXTCLK      MFP_CFG(GPIO89, AF1)
-#define GPIO90_SSP1_SYSCLK      MFP_CFG(GPIO90, AF1)
-#define GPIO15_SSP1_SCLK        MFP_CFG(GPIO15, AF6)
-#define GPIO16_SSP1_FRM         MFP_CFG(GPIO16, AF2)
-#define GPIO33_SSP1_SCLK        MFP_CFG(GPIO33, AF5)
-#define GPIO34_SSP1_FRM         MFP_CFG(GPIO34, AF5)
-#define GPIO85_SSP1_SCLK        MFP_CFG(GPIO85, AF1)
-#define GPIO86_SSP1_FRM         MFP_CFG(GPIO86, AF1)
-#define GPIO18_SSP1_TXD         MFP_CFG(GPIO18, AF7)
-#define GPIO18_SSP1_RXD         MFP_CFG(GPIO18, AF2)
-#define GPIO20_SSP1_TXD         MFP_CFG(GPIO20, AF2)
-#define GPIO20_SSP1_RXD         MFP_CFG(GPIO20, AF7)
-#define GPIO35_SSP1_TXD         MFP_CFG(GPIO35, AF5)
-#define GPIO35_SSP1_RXD         MFP_CFG(GPIO35, AF4)
-#define GPIO36_SSP1_TXD         MFP_CFG(GPIO36, AF5)
-#define GPIO36_SSP1_RXD         MFP_CFG(GPIO36, AF6)
-#define GPIO87_SSP1_TXD         MFP_CFG(GPIO87, AF1)
-#define GPIO87_SSP1_RXD         MFP_CFG(GPIO87, AF6)
-#define GPIO88_SSP1_TXD         MFP_CFG(GPIO88, AF6)
-#define GPIO88_SSP1_RXD         MFP_CFG(GPIO88, AF1)
-
-/* SSP2 */
-#define GPIO29_SSP2_EXTCLK      MFP_CFG(GPIO29, AF2)
-#define GPIO23_SSP2_SCLK        MFP_CFG(GPIO23, AF2)
-#define GPIO17_SSP2_FRM         MFP_CFG(GPIO17, AF2)
-#define GPIO25_SSP2_SCLK        MFP_CFG(GPIO25, AF2)
-#define GPIO26_SSP2_FRM         MFP_CFG(GPIO26, AF2)
-#define GPIO33_SSP2_SCLK        MFP_CFG(GPIO33, AF6)
-#define GPIO34_SSP2_FRM         MFP_CFG(GPIO34, AF6)
-#define GPIO64_SSP2_SCLK        MFP_CFG(GPIO64, AF2)
-#define GPIO65_SSP2_FRM         MFP_CFG(GPIO65, AF2)
-#define GPIO19_SSP2_TXD         MFP_CFG(GPIO19, AF2)
-#define GPIO19_SSP2_RXD         MFP_CFG(GPIO19, AF7)
-#define GPIO24_SSP2_TXD         MFP_CFG(GPIO24, AF5)
-#define GPIO24_SSP2_RXD         MFP_CFG(GPIO24, AF4)
-#define GPIO27_SSP2_TXD         MFP_CFG(GPIO27, AF2)
-#define GPIO27_SSP2_RXD         MFP_CFG(GPIO27, AF5)
-#define GPIO28_SSP2_TXD         MFP_CFG(GPIO28, AF5)
-#define GPIO28_SSP2_RXD         MFP_CFG(GPIO28, AF2)
-#define GPIO35_SSP2_TXD         MFP_CFG(GPIO35, AF7)
-#define GPIO35_SSP2_RXD         MFP_CFG(GPIO35, AF6)
-#define GPIO66_SSP2_TXD         MFP_CFG(GPIO66, AF4)
-#define GPIO66_SSP2_RXD         MFP_CFG(GPIO66, AF2)
-#define GPIO67_SSP2_TXD         MFP_CFG(GPIO67, AF2)
-#define GPIO67_SSP2_RXD         MFP_CFG(GPIO67, AF4)
-#define GPIO36_SSP2_TXD         MFP_CFG(GPIO36, AF7)
-
-/* SSP3 */
-#define GPIO69_SSP3_FRM         MFP_CFG_X(GPIO69, AF2, DS08X, DRIVE_LOW)
-#define GPIO68_SSP3_SCLK        MFP_CFG_X(GPIO68, AF2, DS08X, FLOAT)
-#define GPIO92_SSP3_FRM         MFP_CFG_X(GPIO92, AF1, DS08X, DRIVE_LOW)
-#define GPIO91_SSP3_SCLK        MFP_CFG_X(GPIO91, AF1, DS08X, FLOAT)
-#define GPIO70_SSP3_TXD         MFP_CFG_X(GPIO70, AF2, DS08X, DRIVE_LOW)
-#define GPIO70_SSP3_RXD         MFP_CFG_X(GPIO70, AF5, DS08X, FLOAT)
-#define GPIO71_SSP3_TXD         MFP_CFG_X(GPIO71, AF5, DS08X, DRIVE_LOW)
-#define GPIO71_SSP3_RXD         MFP_CFG_X(GPIO71, AF2, DS08X, FLOAT)
-#define GPIO93_SSP3_TXD         MFP_CFG_X(GPIO93, AF1, DS08X, DRIVE_LOW)
-#define GPIO93_SSP3_RXD         MFP_CFG_X(GPIO93, AF5, DS08X, FLOAT)
-#define GPIO94_SSP3_TXD         MFP_CFG_X(GPIO94, AF5, DS08X, DRIVE_LOW)
-#define GPIO94_SSP3_RXD         MFP_CFG_X(GPIO94, AF1, DS08X, FLOAT)
-
-/* SSP4 */
-#define GPIO95_SSP4_SCLK        MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH)
-#define GPIO96_SSP4_FRM         MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH)
-#define GPIO97_SSP4_TXD         MFP_CFG_LPM(GPIO97, AF1, PULL_HIGH)
-#define GPIO97_SSP4_RXD         MFP_CFG_LPM(GPIO97, AF5, PULL_HIGH)
-#define GPIO98_SSP4_TXD         MFP_CFG_LPM(GPIO98, AF5, PULL_HIGH)
-#define GPIO98_SSP4_RXD         MFP_CFG_LPM(GPIO98, AF1, PULL_HIGH)
-
-/* UART1 */
-#define GPIO32_UART1_CTS        MFP_CFG_LPM(GPIO32,  AF2, FLOAT)
-#define GPIO37_UART1_CTS        MFP_CFG_LPM(GPIO37,  AF4, FLOAT)
-#define GPIO79_UART1_CTS        MFP_CFG_LPM(GPIO79,  AF1, FLOAT)
-#define GPIO84_UART1_CTS        MFP_CFG_LPM(GPIO84,  AF3, FLOAT)
-#define GPIO101_UART1_CTS       MFP_CFG_LPM(GPIO101, AF1, FLOAT)
-#define GPIO106_UART1_CTS       MFP_CFG_LPM(GPIO106, AF6, FLOAT)
-
-#define GPIO32_UART1_RTS        MFP_CFG_LPM(GPIO32,  AF4, FLOAT)
-#define GPIO37_UART1_RTS        MFP_CFG_LPM(GPIO37,  AF2, FLOAT)
-#define GPIO79_UART1_RTS        MFP_CFG_LPM(GPIO79,  AF3, FLOAT)
-#define GPIO84_UART1_RTS        MFP_CFG_LPM(GPIO84,  AF1, FLOAT)
-#define GPIO101_UART1_RTS       MFP_CFG_LPM(GPIO101, AF6, FLOAT)
-#define GPIO106_UART1_RTS       MFP_CFG_LPM(GPIO106, AF1, FLOAT)
-
-#define GPIO34_UART1_DSR        MFP_CFG_LPM(GPIO34,  AF2, FLOAT)
-#define GPIO36_UART1_DSR        MFP_CFG_LPM(GPIO36,  AF4, FLOAT)
-#define GPIO81_UART1_DSR        MFP_CFG_LPM(GPIO81,  AF1, FLOAT)
-#define GPIO83_UART1_DSR        MFP_CFG_LPM(GPIO83,  AF3, FLOAT)
-#define GPIO103_UART1_DSR       MFP_CFG_LPM(GPIO103, AF1, FLOAT)
-#define GPIO105_UART1_DSR       MFP_CFG_LPM(GPIO105, AF6, FLOAT)
-
-#define GPIO34_UART1_DTR        MFP_CFG_LPM(GPIO34,  AF4, FLOAT)
-#define GPIO36_UART1_DTR        MFP_CFG_LPM(GPIO36,  AF2, FLOAT)
-#define GPIO81_UART1_DTR        MFP_CFG_LPM(GPIO81,  AF3, FLOAT)
-#define GPIO83_UART1_DTR        MFP_CFG_LPM(GPIO83,  AF1, FLOAT)
-#define GPIO103_UART1_DTR       MFP_CFG_LPM(GPIO103, AF6, FLOAT)
-#define GPIO105_UART1_DTR       MFP_CFG_LPM(GPIO105, AF1, FLOAT)
-
-#define GPIO35_UART1_RI         MFP_CFG_LPM(GPIO35,  AF2, FLOAT)
-#define GPIO82_UART1_RI         MFP_CFG_LPM(GPIO82,  AF1, FLOAT)
-#define GPIO104_UART1_RI        MFP_CFG_LPM(GPIO104, AF1, FLOAT)
-
-#define GPIO33_UART1_DCD        MFP_CFG_LPM(GPIO33,  AF2, FLOAT)
-#define GPIO80_UART1_DCD        MFP_CFG_LPM(GPIO80,  AF1, FLOAT)
-#define GPIO102_UART1_DCD       MFP_CFG_LPM(GPIO102, AF1, FLOAT)
-
-#define GPIO30_UART1_RXD        MFP_CFG_LPM(GPIO30,  AF2, FLOAT)
-#define GPIO31_UART1_RXD        MFP_CFG_LPM(GPIO31,  AF4, FLOAT)
-#define GPIO77_UART1_RXD        MFP_CFG_LPM(GPIO77,  AF1, FLOAT)
-#define GPIO78_UART1_RXD        MFP_CFG_LPM(GPIO78,  AF3, FLOAT)
-#define GPIO99_UART1_RXD        MFP_CFG_LPM(GPIO99,  AF1, FLOAT)
-#define GPIO100_UART1_RXD       MFP_CFG_LPM(GPIO100, AF6, FLOAT)
-#define GPIO102_UART1_RXD       MFP_CFG_LPM(GPIO102, AF6, FLOAT)
-#define GPIO104_UART1_RXD       MFP_CFG_LPM(GPIO104, AF4, FLOAT)
-
-#define GPIO30_UART1_TXD        MFP_CFG_LPM(GPIO30,  AF4, FLOAT)
-#define GPIO31_UART1_TXD        MFP_CFG_LPM(GPIO31,  AF2, FLOAT)
-#define GPIO77_UART1_TXD        MFP_CFG_LPM(GPIO77,  AF3, FLOAT)
-#define GPIO78_UART1_TXD        MFP_CFG_LPM(GPIO78,  AF1, FLOAT)
-#define GPIO99_UART1_TXD        MFP_CFG_LPM(GPIO99,  AF6, FLOAT)
-#define GPIO100_UART1_TXD       MFP_CFG_LPM(GPIO100, AF1, FLOAT)
-#define GPIO102_UART1_TXD       MFP_CFG_LPM(GPIO102, AF4, FLOAT)
-
-/* UART2 */
-#define GPIO15_UART2_CTS        MFP_CFG_LPM(GPIO15,  AF3, FLOAT)
-#define GPIO16_UART2_CTS        MFP_CFG_LPM(GPIO16,  AF5, FLOAT)
-#define GPIO111_UART2_CTS       MFP_CFG_LPM(GPIO111, AF3, FLOAT)
-#define GPIO114_UART2_CTS       MFP_CFG_LPM(GPIO114, AF1, FLOAT)
-
-#define GPIO15_UART2_RTS        MFP_CFG_LPM(GPIO15,  AF4, FLOAT)
-#define GPIO16_UART2_RTS        MFP_CFG_LPM(GPIO16,  AF4, FLOAT)
-#define GPIO114_UART2_RTS       MFP_CFG_LPM(GPIO114, AF3, FLOAT)
-#define GPIO111_UART2_RTS       MFP_CFG_LPM(GPIO111, AF1, FLOAT)
-
-#define GPIO18_UART2_RXD        MFP_CFG_LPM(GPIO18,  AF5, FLOAT)
-#define GPIO19_UART2_RXD        MFP_CFG_LPM(GPIO19,  AF4, FLOAT)
-#define GPIO112_UART2_RXD       MFP_CFG_LPM(GPIO112, AF1, FLOAT)
-#define GPIO113_UART2_RXD       MFP_CFG_LPM(GPIO113, AF3, FLOAT)
-
-#define GPIO18_UART2_TXD        MFP_CFG_LPM(GPIO18,  AF4, FLOAT)
-#define GPIO19_UART2_TXD        MFP_CFG_LPM(GPIO19,  AF5, FLOAT)
-#define GPIO112_UART2_TXD       MFP_CFG_LPM(GPIO112, AF3, FLOAT)
-#define GPIO113_UART2_TXD       MFP_CFG_LPM(GPIO113, AF1, FLOAT)
-
-/* UART3 */
-#define GPIO91_UART3_CTS        MFP_CFG_LPM(GPIO91,  AF2, FLOAT)
-#define GPIO92_UART3_CTS        MFP_CFG_LPM(GPIO92,  AF4, FLOAT)
-#define GPIO107_UART3_CTS       MFP_CFG_LPM(GPIO107, AF1, FLOAT)
-#define GPIO108_UART3_CTS       MFP_CFG_LPM(GPIO108, AF3, FLOAT)
-
-#define GPIO91_UART3_RTS        MFP_CFG_LPM(GPIO91,  AF4, FLOAT)
-#define GPIO92_UART3_RTS        MFP_CFG_LPM(GPIO92,  AF2, FLOAT)
-#define GPIO107_UART3_RTS       MFP_CFG_LPM(GPIO107, AF3, FLOAT)
-#define GPIO108_UART3_RTS       MFP_CFG_LPM(GPIO108, AF1, FLOAT)
-
-#define GPIO7_UART3_RXD         MFP_CFG_LPM(GPIO7,   AF2, FLOAT)
-#define GPIO8_UART3_RXD         MFP_CFG_LPM(GPIO8,   AF6, FLOAT)
-#define GPIO93_UART3_RXD        MFP_CFG_LPM(GPIO93,  AF4, FLOAT)
-#define GPIO94_UART3_RXD        MFP_CFG_LPM(GPIO94,  AF2, FLOAT)
-#define GPIO109_UART3_RXD       MFP_CFG_LPM(GPIO109, AF3, FLOAT)
-#define GPIO110_UART3_RXD       MFP_CFG_LPM(GPIO110, AF1, FLOAT)
-
-#define GPIO7_UART3_TXD         MFP_CFG_LPM(GPIO7,   AF6, FLOAT)
-#define GPIO8_UART3_TXD         MFP_CFG_LPM(GPIO8,   AF2, FLOAT)
-#define GPIO93_UART3_TXD        MFP_CFG_LPM(GPIO93,  AF2, FLOAT)
-#define GPIO94_UART3_TXD        MFP_CFG_LPM(GPIO94,  AF4, FLOAT)
-#define GPIO109_UART3_TXD       MFP_CFG_LPM(GPIO109, AF1, FLOAT)
-#define GPIO110_UART3_TXD       MFP_CFG_LPM(GPIO110, AF3, FLOAT)
-
-/* USB Host */
-#define GPIO0_2_USBH_PEN        MFP_CFG(GPIO0_2, AF1)
-#define GPIO1_2_USBH_PWR        MFP_CFG(GPIO1_2, AF1)
-
-/* USB P3 */
-#define GPIO77_USB_P3_1         MFP_CFG(GPIO77,  AF2)
-#define GPIO78_USB_P3_2         MFP_CFG(GPIO78,  AF2)
-#define GPIO79_USB_P3_3         MFP_CFG(GPIO79,  AF2)
-#define GPIO80_USB_P3_4         MFP_CFG(GPIO80,  AF2)
-#define GPIO81_USB_P3_5         MFP_CFG(GPIO81,  AF2)
-#define GPIO82_USB_P3_6         MFP_CFG(GPIO82,  AF2)
-
-/* PWM */
-#define GPIO17_PWM0_OUT         MFP_CFG(GPIO17, AF1)
-#define GPIO18_PWM1_OUT         MFP_CFG(GPIO18, AF1)
-#define GPIO19_PWM2_OUT         MFP_CFG(GPIO19, AF1)
-#define GPIO20_PWM3_OUT         MFP_CFG(GPIO20, AF1)
-
-/* CIR */
-#define GPIO8_CIR_OUT           MFP_CFG(GPIO8, AF5)
-#define GPIO16_CIR_OUT          MFP_CFG(GPIO16, AF3)
-
-#define GPIO20_OW_DQ_IN         MFP_CFG(GPIO20, AF5)
-#define GPIO126_OW_DQ           MFP_CFG(GPIO126, AF2)
-
-#define GPIO0_DF_RDY            MFP_CFG(GPIO0, AF1)
-#define GPIO7_CLK_BYPASS_XSC    MFP_CFG(GPIO7, AF7)
-#define GPIO17_EXT_SYNC_MVT_0   MFP_CFG(GPIO17, AF6)
-#define GPIO18_EXT_SYNC_MVT_1   MFP_CFG(GPIO18, AF6)
-#define GPIO19_OST_CHOUT_MVT_0  MFP_CFG(GPIO19, AF6)
-#define GPIO20_OST_CHOUT_MVT_1  MFP_CFG(GPIO20, AF6)
-#define GPIO49_48M_CLK          MFP_CFG(GPIO49, AF2)
-#define GPIO126_EXT_CLK         MFP_CFG(GPIO126, AF3)
-#define GPIO127_CLK_BYPASS_GB   MFP_CFG(GPIO127, AF7)
-#define GPIO71_EXT_MATCH_MVT    MFP_CFG(GPIO71, AF6)
-
-#define GPIO3_uIO_IN            MFP_CFG(GPIO3, AF1)
-
-#define GPIO4_uSIM_CARD_STATE   MFP_CFG(GPIO4, AF1)
-#define GPIO5_uSIM_uCLK         MFP_CFG(GPIO5, AF1)
-#define GPIO6_uSIM_uRST         MFP_CFG(GPIO6, AF1)
-#define GPIO16_uSIM_UVS_0       MFP_CFG(GPIO16, AF1)
-
-#define GPIO9_SCIO              MFP_CFG(GPIO9, AF1)
-#define GPIO20_RTC_MVT          MFP_CFG(GPIO20, AF4)
-#define GPIO126_RTC_MVT         MFP_CFG(GPIO126, AF1)
-
-/*
- * PXA300 specific MFP configurations
- */
-#ifdef CONFIG_CPU_PXA300
-#define GPIO99_USB_P2_2         MFP_CFG(GPIO99, AF2)
-#define GPIO99_USB_P2_5         MFP_CFG(GPIO99, AF3)
-#define GPIO99_USB_P2_6         MFP_CFG(GPIO99, AF4)
-#define GPIO100_USB_P2_2        MFP_CFG(GPIO100, AF4)
-#define GPIO100_USB_P2_5        MFP_CFG(GPIO100, AF5)
-#define GPIO101_USB_P2_1        MFP_CFG(GPIO101, AF2)
-#define GPIO102_USB_P2_4        MFP_CFG(GPIO102, AF2)
-#define GPIO104_USB_P2_3        MFP_CFG(GPIO104, AF2)
-#define GPIO105_USB_P2_5        MFP_CFG(GPIO105, AF2)
-#define GPIO100_USB_P2_6        MFP_CFG(GPIO100, AF2)
-#define GPIO106_USB_P2_7        MFP_CFG(GPIO106, AF2)
-#define GPIO103_USB_P2_8        MFP_CFG(GPIO103, AF2)
-
-/* U2D UTMI */
-#define GPIO38_UTM_CLK          MFP_CFG(GPIO38,  AF1)
-#define GPIO26_U2D_RXERROR      MFP_CFG(GPIO26,  AF3)
-#define GPIO50_U2D_RXERROR      MFP_CFG(GPIO50,  AF1)
-#define GPIO89_U2D_RXERROR      MFP_CFG(GPIO89,  AF5)
-#define GPIO24_UTM_RXVALID      MFP_CFG(GPIO24,  AF3)
-#define GPIO48_UTM_RXVALID      MFP_CFG(GPIO48,  AF2)
-#define GPIO87_UTM_RXVALID      MFP_CFG(GPIO87,  AF5)
-#define GPIO25_UTM_RXACTIVE     MFP_CFG(GPIO25,  AF3)
-#define GPIO47_UTM_RXACTIVE     MFP_CFG(GPIO47,  AF2)
-#define GPIO49_UTM_RXACTIVE     MFP_CFG(GPIO49,  AF1)
-#define GPIO88_UTM_RXACTIVE     MFP_CFG(GPIO88,  AF5)
-#define GPIO53_UTM_TXREADY      MFP_CFG(GPIO53,  AF1)
-#define GPIO67_UTM_LINESTATE_0  MFP_CFG(GPIO67,  AF3)
-#define GPIO92_UTM_LINESTATE_0  MFP_CFG(GPIO92,  AF3)
-#define GPIO104_UTM_LINESTATE_0 MFP_CFG(GPIO104, AF3)
-#define GPIO109_UTM_LINESTATE_0 MFP_CFG(GPIO109, AF4)
-#define GPIO68_UTM_LINESTATE_1  MFP_CFG(GPIO68,  AF3)
-#define GPIO93_UTM_LINESTATE_1  MFP_CFG(GPIO93,  AF3)
-#define GPIO105_UTM_LINESTATE_1 MFP_CFG(GPIO105, AF3)
-#define GPIO27_U2D_OPMODE_0     MFP_CFG(GPIO27,  AF4)
-#define GPIO51_U2D_OPMODE_0     MFP_CFG(GPIO51,  AF2)
-#define GPIO90_U2D_OPMODE_0     MFP_CFG(GPIO90,  AF7)
-#define GPIO28_U2D_OPMODE_1     MFP_CFG(GPIO28,  AF4)
-#define GPIO52_U2D_OPMODE_1     MFP_CFG(GPIO52,  AF2)
-#define GPIO106_U2D_OPMODE_1    MFP_CFG(GPIO106, AF3)
-#define GPIO110_U2D_OPMODE_1    MFP_CFG(GPIO110, AF5)
-#define GPIO76_U2D_RESET        MFP_CFG(GPIO76,  AF1)
-#define GPIO95_U2D_RESET        MFP_CFG(GPIO95,  AF2)
-#define GPIO100_U2D_RESET       MFP_CFG(GPIO100, AF3)
-#define GPIO66_U2D_SUSPEND      MFP_CFG(GPIO66,  AF3)
-#define GPIO98_U2D_SUSPEND      MFP_CFG(GPIO98,  AF2)
-#define GPIO103_U2D_SUSPEND     MFP_CFG(GPIO103, AF3)
-#define GPIO65_U2D_TERM_SEL     MFP_CFG(GPIO65,  AF5)
-#define GPIO97_U2D_TERM_SEL     MFP_CFG(GPIO97,  AF3)
-#define GPIO102_U2D_TERM_SEL    MFP_CFG(GPIO102, AF5)
-#define GPIO29_U2D_TXVALID      MFP_CFG(GPIO29,  AF3)
-#define GPIO52_U2D_TXVALID      MFP_CFG(GPIO52,  AF4)
-#define GPIO69_U2D_TXVALID      MFP_CFG(GPIO69,  AF3)
-#define GPIO85_U2D_TXVALID      MFP_CFG(GPIO85,  AF7)
-#define GPIO64_U2D_XCVR_SEL     MFP_CFG(GPIO64,  AF5)
-#define GPIO96_U2D_XCVR_SEL     MFP_CFG(GPIO96,  AF3)
-#define GPIO101_U2D_XCVR_SEL    MFP_CFG(GPIO101, AF5)
-#define GPIO30_UTM_PHYDATA_0    MFP_CFG(GPIO30,  AF3)
-#define GPIO31_UTM_PHYDATA_1    MFP_CFG(GPIO31,  AF3)
-#define GPIO32_UTM_PHYDATA_2    MFP_CFG(GPIO32,  AF3)
-#define GPIO33_UTM_PHYDATA_3    MFP_CFG(GPIO33,  AF3)
-#define GPIO34_UTM_PHYDATA_4    MFP_CFG(GPIO34,  AF3)
-#define GPIO35_UTM_PHYDATA_5    MFP_CFG(GPIO35,  AF3)
-#define GPIO36_UTM_PHYDATA_6    MFP_CFG(GPIO36,  AF3)
-#define GPIO37_UTM_PHYDATA_7    MFP_CFG(GPIO37,  AF3)
-#define GPIO39_UTM_PHYDATA_0    MFP_CFG(GPIO39,  AF3)
-#define GPIO40_UTM_PHYDATA_1    MFP_CFG(GPIO40,  AF3)
-#define GPIO41_UTM_PHYDATA_2    MFP_CFG(GPIO41,  AF3)
-#define GPIO42_UTM_PHYDATA_3    MFP_CFG(GPIO42,  AF3)
-#define GPIO43_UTM_PHYDATA_4    MFP_CFG(GPIO43,  AF3)
-#define GPIO44_UTM_PHYDATA_5    MFP_CFG(GPIO44,  AF3)
-#define GPIO45_UTM_PHYDATA_6    MFP_CFG(GPIO45,  AF3)
-#define GPIO46_UTM_PHYDATA_7    MFP_CFG(GPIO46,  AF3)
-#endif /* CONFIG_CPU_PXA300 */
-
-/*
- * PXA310 specific MFP configurations
- */
-#ifdef CONFIG_CPU_PXA310
-/* USB P2 */
-#define GPIO36_USB_P2_1         MFP_CFG(GPIO36, AF1)
-#define GPIO30_USB_P2_2         MFP_CFG(GPIO30, AF1)
-#define GPIO35_USB_P2_3         MFP_CFG(GPIO35, AF1)
-#define GPIO32_USB_P2_4         MFP_CFG(GPIO32, AF1)
-#define GPIO34_USB_P2_5         MFP_CFG(GPIO34, AF1)
-#define GPIO31_USB_P2_6         MFP_CFG(GPIO31, AF1)
-
-/* MMC1 */
-#define GPIO24_MMC1_CMD         MFP_CFG(GPIO24, AF3)
-#define GPIO29_MMC1_DAT0        MFP_CFG(GPIO29, AF3)
-
-/* MMC3 */
-#define GPIO103_MMC3_CLK        MFP_CFG(GPIO103, AF2)
-#define GPIO105_MMC3_CMD        MFP_CFG(GPIO105, AF2)
-#define GPIO11_2_MMC3_CLK       MFP_CFG(GPIO11_2, AF1)
-#define GPIO12_2_MMC3_CMD       MFP_CFG(GPIO12_2, AF1)
-#define GPIO7_2_MMC3_DAT0       MFP_CFG(GPIO7_2, AF1)
-#define GPIO8_2_MMC3_DAT1       MFP_CFG(GPIO8_2, AF1)
-#define GPIO9_2_MMC3_DAT2       MFP_CFG(GPIO9_2, AF1)
-#define GPIO10_2_MMC3_DAT3      MFP_CFG(GPIO10_2, AF1)
-
-/* ULPI */
-#define GPIO38_ULPI_CLK         MFP_CFG(GPIO38, AF1)
-#define GPIO30_ULPI_DATA_OUT_0  MFP_CFG(GPIO30, AF3)
-#define GPIO31_ULPI_DATA_OUT_1  MFP_CFG(GPIO31, AF3)
-#define GPIO32_ULPI_DATA_OUT_2  MFP_CFG(GPIO32, AF3)
-#define GPIO33_ULPI_DATA_OUT_3  MFP_CFG(GPIO33, AF3)
-#define GPIO34_ULPI_DATA_OUT_4  MFP_CFG(GPIO34, AF3)
-#define GPIO35_ULPI_DATA_OUT_5  MFP_CFG(GPIO35, AF3)
-#define GPIO36_ULPI_DATA_OUT_6  MFP_CFG(GPIO36, AF3)
-#define GPIO37_ULPI_DATA_OUT_7  MFP_CFG(GPIO37, AF3)
-#define GPIO33_ULPI_OTG_INTR    MFP_CFG(GPIO33, AF1)
-
-#define ULPI_DIR        MFP_CFG_DRV(ULPI_DIR, MFP_AF0, MFP_DS01X)
-#define ULPI_NXT        MFP_CFG_DRV(ULPI_NXT, MFP_AF0, MFP_DS01X)
-#define ULPI_STP        MFP_CFG_DRV(ULPI_STP, MFP_AF0, MFP_DS01X)
-#endif /* CONFIG_CPU_PXA310 */
-
-#endif /* __ASM_ARCH_MFP_PXA300_H */
diff --git a/include/asm-arm/arch-pxa/mfp-pxa320.h b/include/asm-arm/arch-pxa/mfp-pxa320.h
deleted file mode 100644
index 576aa46d90fc..000000000000
--- a/include/asm-arm/arch-pxa/mfp-pxa320.h
+++ /dev/null
@@ -1,447 +0,0 @@
-/*
- * linux/include/asm-arm/arch-pxa/mfp-pxa320.h
- *
- * PXA320 specific MFP configuration definitions
- *
- * Copyright (C) 2007 Marvell International Ltd.
- * 2007-08-21: eric miao <eric.miao@marvell.com>
- *             initial version
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MFP_PXA320_H
-#define __ASM_ARCH_MFP_PXA320_H
-
-#include <asm/arch/mfp.h>
-#include <asm/arch/mfp-pxa3xx.h>
-
-/* GPIO */
-#define GPIO46_GPIO             MFP_CFG(GPIO46, AF0)
-#define GPIO49_GPIO             MFP_CFG(GPIO49, AF0)
-#define GPIO50_GPIO             MFP_CFG(GPIO50, AF0)
-#define GPIO51_GPIO             MFP_CFG(GPIO51, AF0)
-#define GPIO52_GPIO             MFP_CFG(GPIO52, AF0)
-
-#define GPIO7_2_GPIO            MFP_CFG(GPIO7_2, AF0)
-#define GPIO8_2_GPIO            MFP_CFG(GPIO8_2, AF0)
-#define GPIO9_2_GPIO            MFP_CFG(GPIO9_2, AF0)
-#define GPIO10_2_GPIO           MFP_CFG(GPIO10_2, AF0)
-#define GPIO11_2_GPIO           MFP_CFG(GPIO11_2, AF0)
-#define GPIO12_2_GPIO           MFP_CFG(GPIO12_2, AF0)
-#define GPIO13_2_GPIO           MFP_CFG(GPIO13_2, AF0)
-#define GPIO14_2_GPIO           MFP_CFG(GPIO14_2, AF0)
-#define GPIO15_2_GPIO           MFP_CFG(GPIO15_2, AF0)
-#define GPIO16_2_GPIO           MFP_CFG(GPIO16_2, AF0)
-#define GPIO17_2_GPIO           MFP_CFG(GPIO17_2, AF0)
-
-/* Chip Select */
-#define GPIO4_nCS3              MFP_CFG(GPIO4, AF1)
-
-/* AC97 */
-#define GPIO34_AC97_SYSCLK      MFP_CFG(GPIO34, AF1)
-#define GPIO39_AC97_BITCLK      MFP_CFG(GPIO39, AF1)
-#define GPIO40_AC97_nACRESET    MFP_CFG(GPIO40, AF1)
-#define GPIO35_AC97_SDATA_IN_0  MFP_CFG(GPIO35, AF1)
-#define GPIO36_AC97_SDATA_IN_1  MFP_CFG(GPIO36, AF1)
-#define GPIO32_AC97_SDATA_IN_2  MFP_CFG(GPIO32, AF2)
-#define GPIO33_AC97_SDATA_IN_3  MFP_CFG(GPIO33, AF2)
-#define GPIO11_AC97_SDATA_IN_2  MFP_CFG(GPIO11, AF3)
-#define GPIO12_AC97_SDATA_IN_3  MFP_CFG(GPIO12, AF3)
-#define GPIO37_AC97_SDATA_OUT   MFP_CFG(GPIO37, AF1)
-#define GPIO38_AC97_SYNC        MFP_CFG(GPIO38, AF1)
-
-/* I2C */
-#define GPIO32_I2C_SCL          MFP_CFG_LPM(GPIO32, AF1, PULL_HIGH)
-#define GPIO33_I2C_SDA          MFP_CFG_LPM(GPIO33, AF1, PULL_HIGH)
-
-/* QCI */
-#define GPIO49_CI_DD_0          MFP_CFG_DRV(GPIO49, AF1, DS04X)
-#define GPIO50_CI_DD_1          MFP_CFG_DRV(GPIO50, AF1, DS04X)
-#define GPIO51_CI_DD_2          MFP_CFG_DRV(GPIO51, AF1, DS04X)
-#define GPIO52_CI_DD_3          MFP_CFG_DRV(GPIO52, AF1, DS04X)
-#define GPIO53_CI_DD_4          MFP_CFG_DRV(GPIO53, AF1, DS04X)
-#define GPIO54_CI_DD_5          MFP_CFG_DRV(GPIO54, AF1, DS04X)
-#define GPIO55_CI_DD_6          MFP_CFG_DRV(GPIO55, AF1, DS04X)
-#define GPIO56_CI_DD_7          MFP_CFG_DRV(GPIO56, AF0, DS04X)
-#define GPIO57_CI_DD_8          MFP_CFG_DRV(GPIO57, AF1, DS04X)
-#define GPIO58_CI_DD_9          MFP_CFG_DRV(GPIO58, AF1, DS04X)
-#define GPIO59_CI_MCLK          MFP_CFG_DRV(GPIO59, AF0, DS04X)
-#define GPIO60_CI_PCLK          MFP_CFG_DRV(GPIO60, AF0, DS04X)
-#define GPIO61_CI_HSYNC         MFP_CFG_DRV(GPIO61, AF0, DS04X)
-#define GPIO62_CI_VSYNC         MFP_CFG_DRV(GPIO62, AF0, DS04X)
-
-#define GPIO31_CIR_OUT          MFP_CFG(GPIO31, AF5)
-
-#define GPIO0_2_CLK_EXT         MFP_CFG(GPIO0_2, AF3)
-#define GPIO0_DRQ               MFP_CFG(GPIO0, AF2)
-#define GPIO11_EXT_SYNC0        MFP_CFG(GPIO11, AF5)
-#define GPIO12_EXT_SYNC1        MFP_CFG(GPIO12, AF6)
-#define GPIO0_2_HZ_CLK          MFP_CFG(GPIO0_2, AF1)
-#define GPIO14_HZ_CLK           MFP_CFG(GPIO14, AF4)
-#define GPIO30_ICP_RXD          MFP_CFG(GPIO30, AF1)
-#define GPIO31_ICP_TXD          MFP_CFG(GPIO31, AF1)
-
-#define GPIO83_KP_DKIN_0        MFP_CFG_LPM(GPIO83, AF3, FLOAT)
-#define GPIO84_KP_DKIN_1        MFP_CFG_LPM(GPIO84, AF3, FLOAT)
-#define GPIO85_KP_DKIN_2        MFP_CFG_LPM(GPIO85, AF3, FLOAT)
-#define GPIO86_KP_DKIN_3        MFP_CFG_LPM(GPIO86, AF3, FLOAT)
-
-#define GPIO105_KP_DKIN_0       MFP_CFG_LPM(GPIO105, AF2, FLOAT)
-#define GPIO106_KP_DKIN_1       MFP_CFG_LPM(GPIO106, AF2, FLOAT)
-#define GPIO107_KP_DKIN_2       MFP_CFG_LPM(GPIO107, AF2, FLOAT)
-#define GPIO108_KP_DKIN_3       MFP_CFG_LPM(GPIO108, AF2, FLOAT)
-#define GPIO109_KP_DKIN_4       MFP_CFG_LPM(GPIO109, AF2, FLOAT)
-#define GPIO110_KP_DKIN_5       MFP_CFG_LPM(GPIO110, AF2, FLOAT)
-#define GPIO111_KP_DKIN_6       MFP_CFG_LPM(GPIO111, AF2, FLOAT)
-#define GPIO112_KP_DKIN_7       MFP_CFG_LPM(GPIO112, AF2, FLOAT)
-
-#define GPIO113_KP_DKIN_0       MFP_CFG_LPM(GPIO113, AF2, FLOAT)
-#define GPIO114_KP_DKIN_1       MFP_CFG_LPM(GPIO114, AF2, FLOAT)
-#define GPIO115_KP_DKIN_2       MFP_CFG_LPM(GPIO115, AF2, FLOAT)
-#define GPIO116_KP_DKIN_3       MFP_CFG_LPM(GPIO116, AF2, FLOAT)
-#define GPIO117_KP_DKIN_4       MFP_CFG_LPM(GPIO117, AF2, FLOAT)
-#define GPIO118_KP_DKIN_5       MFP_CFG_LPM(GPIO118, AF2, FLOAT)
-#define GPIO119_KP_DKIN_6       MFP_CFG_LPM(GPIO119, AF2, FLOAT)
-#define GPIO120_KP_DKIN_7       MFP_CFG_LPM(GPIO120, AF2, FLOAT)
-
-#define GPIO127_KP_DKIN_0       MFP_CFG_LPM(GPIO127, AF2, FLOAT)
-#define GPIO126_KP_DKIN_1       MFP_CFG_LPM(GPIO126, AF2, FLOAT)
-
-#define GPIO2_2_KP_DKIN_0       MFP_CFG_LPM(GPIO2_2, AF2, FLOAT)
-#define GPIO3_2_KP_DKIN_1       MFP_CFG_LPM(GPIO3_2, AF2, FLOAT)
-#define GPIO125_KP_DKIN_2       MFP_CFG_LPM(GPIO125, AF2, FLOAT)
-#define GPIO124_KP_DKIN_3       MFP_CFG_LPM(GPIO124, AF2, FLOAT)
-#define GPIO123_KP_DKIN_4       MFP_CFG_LPM(GPIO123, AF2, FLOAT)
-#define GPIO122_KP_DKIN_5       MFP_CFG_LPM(GPIO122, AF2, FLOAT)
-#define GPIO121_KP_DKIN_6       MFP_CFG_LPM(GPIO121, AF2, FLOAT)
-#define GPIO4_2_KP_DKIN_7       MFP_CFG_LPM(GPIO4_2, AF2, FLOAT)
-
-#define GPIO113_KP_MKIN_0       MFP_CFG_LPM(GPIO113, AF1, FLOAT)
-#define GPIO114_KP_MKIN_1       MFP_CFG_LPM(GPIO114, AF1, FLOAT)
-#define GPIO115_KP_MKIN_2       MFP_CFG_LPM(GPIO115, AF1, FLOAT)
-#define GPIO116_KP_MKIN_3       MFP_CFG_LPM(GPIO116, AF1, FLOAT)
-#define GPIO117_KP_MKIN_4       MFP_CFG_LPM(GPIO117, AF1, FLOAT)
-#define GPIO118_KP_MKIN_5       MFP_CFG_LPM(GPIO118, AF1, FLOAT)
-#define GPIO119_KP_MKIN_6       MFP_CFG_LPM(GPIO119, AF1, FLOAT)
-#define GPIO120_KP_MKIN_7       MFP_CFG_LPM(GPIO120, AF1, FLOAT)
-
-#define GPIO83_KP_MKOUT_0       MFP_CFG_LPM(GPIO83, AF2, DRIVE_HIGH)
-#define GPIO84_KP_MKOUT_1       MFP_CFG_LPM(GPIO84, AF2, DRIVE_HIGH)
-#define GPIO85_KP_MKOUT_2       MFP_CFG_LPM(GPIO85, AF2, DRIVE_HIGH)
-#define GPIO86_KP_MKOUT_3       MFP_CFG_LPM(GPIO86, AF2, DRIVE_HIGH)
-#define GPIO13_KP_MKOUT_4       MFP_CFG_LPM(GPIO13, AF3, DRIVE_HIGH)
-#define GPIO14_KP_MKOUT_5       MFP_CFG_LPM(GPIO14, AF3, DRIVE_HIGH)
-
-#define GPIO121_KP_MKOUT_0      MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH)
-#define GPIO122_KP_MKOUT_1      MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH)
-#define GPIO123_KP_MKOUT_2      MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH)
-#define GPIO124_KP_MKOUT_3      MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH)
-#define GPIO125_KP_MKOUT_4      MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH)
-#define GPIO126_KP_MKOUT_5      MFP_CFG_LPM(GPIO126, AF1, DRIVE_HIGH)
-#define GPIO127_KP_MKOUT_6      MFP_CFG_LPM(GPIO127, AF1, DRIVE_HIGH)
-#define GPIO5_2_KP_MKOUT_7      MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH)
-
-/* LCD */
-#define GPIO6_2_LCD_LDD_0       MFP_CFG_DRV(GPIO6_2, AF1, DS01X)
-#define GPIO7_2_LCD_LDD_1       MFP_CFG_DRV(GPIO7_2, AF1, DS01X)
-#define GPIO8_2_LCD_LDD_2       MFP_CFG_DRV(GPIO8_2, AF1, DS01X)
-#define GPIO9_2_LCD_LDD_3       MFP_CFG_DRV(GPIO9_2, AF1, DS01X)
-#define GPIO10_2_LCD_LDD_4      MFP_CFG_DRV(GPIO10_2, AF1, DS01X)
-#define GPIO11_2_LCD_LDD_5      MFP_CFG_DRV(GPIO11_2, AF1, DS01X)
-#define GPIO12_2_LCD_LDD_6      MFP_CFG_DRV(GPIO12_2, AF1, DS01X)
-#define GPIO13_2_LCD_LDD_7      MFP_CFG_DRV(GPIO13_2, AF1, DS01X)
-#define GPIO63_LCD_LDD_8        MFP_CFG_DRV(GPIO63, AF1, DS01X)
-#define GPIO64_LCD_LDD_9        MFP_CFG_DRV(GPIO64, AF1, DS01X)
-#define GPIO65_LCD_LDD_10       MFP_CFG_DRV(GPIO65, AF1, DS01X)
-#define GPIO66_LCD_LDD_11       MFP_CFG_DRV(GPIO66, AF1, DS01X)
-#define GPIO67_LCD_LDD_12       MFP_CFG_DRV(GPIO67, AF1, DS01X)
-#define GPIO68_LCD_LDD_13       MFP_CFG_DRV(GPIO68, AF1, DS01X)
-#define GPIO69_LCD_LDD_14       MFP_CFG_DRV(GPIO69, AF1, DS01X)
-#define GPIO70_LCD_LDD_15       MFP_CFG_DRV(GPIO70, AF1, DS01X)
-#define GPIO71_LCD_LDD_16       MFP_CFG_DRV(GPIO71, AF1, DS01X)
-#define GPIO72_LCD_LDD_17       MFP_CFG_DRV(GPIO72, AF1, DS01X)
-#define GPIO73_LCD_CS_N         MFP_CFG_DRV(GPIO73, AF2, DS01X)
-#define GPIO74_LCD_VSYNC        MFP_CFG_DRV(GPIO74, AF2, DS01X)
-#define GPIO14_2_LCD_FCLK       MFP_CFG_DRV(GPIO14_2, AF1, DS01X)
-#define GPIO15_2_LCD_LCLK       MFP_CFG_DRV(GPIO15_2, AF1, DS01X)
-#define GPIO16_2_LCD_PCLK       MFP_CFG_DRV(GPIO16_2, AF1, DS01X)
-#define GPIO17_2_LCD_BIAS       MFP_CFG_DRV(GPIO17_2, AF1, DS01X)
-#define GPIO64_LCD_VSYNC        MFP_CFG_DRV(GPIO64, AF2, DS01X)
-#define GPIO63_LCD_CS_N         MFP_CFG_DRV(GPIO63, AF2, DS01X)
-
-#define GPIO6_2_MLCD_DD_0       MFP_CFG_DRV(GPIO6_2, AF7, DS08X)
-#define GPIO7_2_MLCD_DD_1       MFP_CFG_DRV(GPIO7_2, AF7, DS08X)
-#define GPIO8_2_MLCD_DD_2       MFP_CFG_DRV(GPIO8_2, AF7, DS08X)
-#define GPIO9_2_MLCD_DD_3       MFP_CFG_DRV(GPIO9_2, AF7, DS08X)
-#define GPIO10_2_MLCD_DD_4      MFP_CFG_DRV(GPIO10_2, AF7, DS08X)
-#define GPIO11_2_MLCD_DD_5      MFP_CFG_DRV(GPIO11_2, AF7, DS08X)
-#define GPIO12_2_MLCD_DD_6      MFP_CFG_DRV(GPIO12_2, AF7, DS08X)
-#define GPIO13_2_MLCD_DD_7      MFP_CFG_DRV(GPIO13_2, AF7, DS08X)
-#define GPIO63_MLCD_DD_8        MFP_CFG_DRV(GPIO63, AF7, DS08X)
-#define GPIO64_MLCD_DD_9        MFP_CFG_DRV(GPIO64, AF7, DS08X)
-#define GPIO65_MLCD_DD_10       MFP_CFG_DRV(GPIO65, AF7, DS08X)
-#define GPIO66_MLCD_DD_11       MFP_CFG_DRV(GPIO66, AF7, DS08X)
-#define GPIO67_MLCD_DD_12       MFP_CFG_DRV(GPIO67, AF7, DS08X)
-#define GPIO68_MLCD_DD_13       MFP_CFG_DRV(GPIO68, AF7, DS08X)
-#define GPIO69_MLCD_DD_14       MFP_CFG_DRV(GPIO69, AF7, DS08X)
-#define GPIO70_MLCD_DD_15       MFP_CFG_DRV(GPIO70, AF7, DS08X)
-#define GPIO71_MLCD_DD_16       MFP_CFG_DRV(GPIO71, AF7, DS08X)
-#define GPIO72_MLCD_DD_17       MFP_CFG_DRV(GPIO72, AF7, DS08X)
-#define GPIO73_MLCD_CS          MFP_CFG_DRV(GPIO73, AF7, DS08X)
-#define GPIO74_MLCD_VSYNC       MFP_CFG_DRV(GPIO74, AF7, DS08X)
-#define GPIO14_2_MLCD_FCLK      MFP_CFG_DRV(GPIO14_2, AF7, DS08X)
-#define GPIO15_2_MLCD_LCLK      MFP_CFG_DRV(GPIO15_2, AF7, DS08X)
-#define GPIO16_2_MLCD_PCLK      MFP_CFG_DRV(GPIO16_2, AF7, DS08X)
-#define GPIO17_2_MLCD_BIAS      MFP_CFG_DRV(GPIO17_2, AF7, DS08X)
-
-/* MMC1 */
-#define GPIO9_MMC1_CMD          MFP_CFG_LPM(GPIO9,  AF4, DRIVE_HIGH)
-#define GPIO22_MMC1_CLK         MFP_CFG_LPM(GPIO22, AF4, DRIVE_HIGH)
-#define GPIO23_MMC1_CMD         MFP_CFG_LPM(GPIO23, AF4, DRIVE_HIGH)
-#define GPIO30_MMC1_CLK         MFP_CFG_LPM(GPIO30, AF4, DRIVE_HIGH)
-#define GPIO31_MMC1_CMD         MFP_CFG_LPM(GPIO31, AF4, DRIVE_HIGH)
-#define GPIO5_MMC1_DAT0         MFP_CFG_LPM(GPIO5,  AF4, DRIVE_HIGH)
-#define GPIO6_MMC1_DAT1         MFP_CFG_LPM(GPIO6,  AF4, DRIVE_HIGH)
-#define GPIO7_MMC1_DAT2         MFP_CFG_LPM(GPIO7,  AF4, DRIVE_HIGH)
-#define GPIO8_MMC1_DAT3         MFP_CFG_LPM(GPIO8,  AF4, DRIVE_HIGH)
-#define GPIO18_MMC1_DAT0        MFP_CFG_LPM(GPIO18, AF4, DRIVE_HIGH)
-#define GPIO19_MMC1_DAT1        MFP_CFG_LPM(GPIO19, AF4, DRIVE_HIGH)
-#define GPIO20_MMC1_DAT2        MFP_CFG_LPM(GPIO20, AF4, DRIVE_HIGH)
-#define GPIO21_MMC1_DAT3        MFP_CFG_LPM(GPIO21, AF4, DRIVE_HIGH)
-
-#define GPIO28_MMC2_CLK         MFP_CFG_LPM(GPIO28, AF4, PULL_HIGH)
-#define GPIO29_MMC2_CMD         MFP_CFG_LPM(GPIO29, AF4, PULL_HIGH)
-#define GPIO30_MMC2_CLK         MFP_CFG_LPM(GPIO30, AF3, PULL_HIGH)
-#define GPIO31_MMC2_CMD         MFP_CFG_LPM(GPIO31, AF3, PULL_HIGH)
-#define GPIO79_MMC2_CLK         MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH)
-#define GPIO80_MMC2_CMD         MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH)
-
-#define GPIO5_MMC2_DAT0         MFP_CFG_LPM(GPIO5, AF2, PULL_HIGH)
-#define GPIO6_MMC2_DAT1         MFP_CFG_LPM(GPIO6, AF2, PULL_HIGH)
-#define GPIO7_MMC2_DAT2         MFP_CFG_LPM(GPIO7, AF2, PULL_HIGH)
-#define GPIO8_MMC2_DAT3         MFP_CFG_LPM(GPIO8, AF2, PULL_HIGH)
-#define GPIO24_MMC2_DAT0        MFP_CFG_LPM(GPIO24, AF4, PULL_HIGH)
-#define GPIO75_MMC2_DAT0        MFP_CFG_LPM(GPIO75, AF4, PULL_HIGH)
-#define GPIO25_MMC2_DAT1        MFP_CFG_LPM(GPIO25, AF4, PULL_HIGH)
-#define GPIO76_MMC2_DAT1        MFP_CFG_LPM(GPIO76, AF4, PULL_HIGH)
-#define GPIO26_MMC2_DAT2        MFP_CFG_LPM(GPIO26, AF4, PULL_HIGH)
-#define GPIO77_MMC2_DAT2        MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH)
-#define GPIO27_MMC2_DAT3        MFP_CFG_LPM(GPIO27, AF4, PULL_HIGH)
-#define GPIO78_MMC2_DAT3        MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH)
-
-/* 1-Wire */
-#define GPIO14_ONE_WIRE         MFP_CFG_LPM(GPIO14,  AF5, FLOAT)
-#define GPIO0_2_ONE_WIRE        MFP_CFG_LPM(GPIO0_2, AF2, FLOAT)
-
-/* SSP1 */
-#define GPIO87_SSP1_EXTCLK      MFP_CFG(GPIO87, AF1)
-#define GPIO88_SSP1_SYSCLK      MFP_CFG(GPIO88, AF1)
-#define GPIO83_SSP1_SCLK        MFP_CFG(GPIO83, AF1)
-#define GPIO84_SSP1_SFRM        MFP_CFG(GPIO84, AF1)
-#define GPIO85_SSP1_RXD         MFP_CFG(GPIO85, AF6)
-#define GPIO85_SSP1_TXD         MFP_CFG(GPIO85, AF1)
-#define GPIO86_SSP1_RXD         MFP_CFG(GPIO86, AF1)
-#define GPIO86_SSP1_TXD         MFP_CFG(GPIO86, AF6)
-
-/* SSP2 */
-#define GPIO39_SSP2_EXTCLK      MFP_CFG(GPIO39, AF2)
-#define GPIO40_SSP2_SYSCLK      MFP_CFG(GPIO40, AF2)
-#define GPIO12_SSP2_SCLK        MFP_CFG(GPIO12, AF2)
-#define GPIO35_SSP2_SCLK        MFP_CFG(GPIO35, AF2)
-#define GPIO36_SSP2_SFRM        MFP_CFG(GPIO36, AF2)
-#define GPIO37_SSP2_RXD         MFP_CFG(GPIO37, AF5)
-#define GPIO37_SSP2_TXD         MFP_CFG(GPIO37, AF2)
-#define GPIO38_SSP2_RXD         MFP_CFG(GPIO38, AF2)
-#define GPIO38_SSP2_TXD         MFP_CFG(GPIO38, AF5)
-
-#define GPIO69_SSP3_SCLK        MFP_CFG(GPIO69, AF2, DS08X, FLOAT)
-#define GPIO70_SSP3_FRM         MFP_CFG(GPIO70, AF2, DS08X, DRIVE_LOW)
-#define GPIO89_SSP3_SCLK        MFP_CFG(GPIO89, AF1, DS08X, FLOAT)
-#define GPIO90_SSP3_FRM         MFP_CFG(GPIO90, AF1, DS08X, DRIVE_LOW)
-#define GPIO71_SSP3_RXD         MFP_CFG_X(GPIO71, AF5, DS08X, FLOAT)
-#define GPIO71_SSP3_TXD         MFP_CFG_X(GPIO71, AF2, DS08X, DRIVE_LOW)
-#define GPIO72_SSP3_RXD         MFP_CFG_X(GPIO72, AF2, DS08X, FLOAT)
-#define GPIO72_SSP3_TXD         MFP_CFG_X(GPIO72, AF5, DS08X, DRIVE_LOW)
-#define GPIO91_SSP3_RXD         MFP_CFG_X(GPIO91, AF5, DS08X, FLOAT)
-#define GPIO91_SSP3_TXD         MFP_CFG_X(GPIO91, AF1, DS08X, DRIVE_LOW)
-#define GPIO92_SSP3_RXD         MFP_CFG_X(GPIO92, AF1, DS08X, FLOAT)
-#define GPIO92_SSP3_TXD         MFP_CFG_X(GPIO92, AF5, DS08X, DRIVE_LOW)
-
-#define GPIO93_SSP4_SCLK        MFP_CFG_LPM(GPIO93, AF1, PULL_HIGH)
-#define GPIO94_SSP4_FRM         MFP_CFG_LPM(GPIO94, AF1, PULL_HIGH)
-#define GPIO94_SSP4_RXD         MFP_CFG_LPM(GPIO94, AF5, PULL_HIGH)
-#define GPIO95_SSP4_RXD         MFP_CFG_LPM(GPIO95, AF5, PULL_HIGH)
-#define GPIO95_SSP4_TXD         MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH)
-#define GPIO96_SSP4_RXD         MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH)
-#define GPIO96_SSP4_TXD         MFP_CFG_LPM(GPIO96, AF5, PULL_HIGH)
-
-/* UART1 */
-#define GPIO41_UART1_RXD        MFP_CFG_LPM(GPIO41, AF2, FLOAT)
-#define GPIO41_UART1_TXD        MFP_CFG_LPM(GPIO41, AF4, FLOAT)
-#define GPIO42_UART1_RXD        MFP_CFG_LPM(GPIO42, AF4, FLOAT)
-#define GPIO42_UART1_TXD        MFP_CFG_LPM(GPIO42, AF2, FLOAT)
-#define GPIO97_UART1_RXD        MFP_CFG_LPM(GPIO97, AF1, FLOAT)
-#define GPIO97_UART1_TXD        MFP_CFG_LPM(GPIO97, AF6, FLOAT)
-#define GPIO98_UART1_RXD        MFP_CFG_LPM(GPIO98, AF6, FLOAT)
-#define GPIO98_UART1_TXD        MFP_CFG_LPM(GPIO98, AF1, FLOAT)
-#define GPIO43_UART1_CTS        MFP_CFG_LPM(GPIO43, AF2, FLOAT)
-#define GPIO43_UART1_RTS        MFP_CFG_LPM(GPIO43, AF4, FLOAT)
-#define GPIO48_UART1_CTS        MFP_CFG_LPM(GPIO48, AF4, FLOAT)
-#define GPIO48_UART1_RTS        MFP_CFG_LPM(GPIO48, AF2, FLOAT)
-#define GPIO99_UART1_CTS        MFP_CFG_LPM(GPIO99, AF1, FLOAT)
-#define GPIO99_UART1_RTS        MFP_CFG_LPM(GPIO99, AF6, FLOAT)
-#define GPIO104_UART1_CTS       MFP_CFG_LPM(GPIO104, AF6, FLOAT)
-#define GPIO104_UART1_RTS       MFP_CFG_LPM(GPIO104, AF1, FLOAT)
-#define GPIO45_UART1_DTR        MFP_CFG_LPM(GPIO45, AF4, FLOAT)
-#define GPIO45_UART1_DSR        MFP_CFG_LPM(GPIO45, AF2, FLOAT)
-#define GPIO47_UART1_DTR        MFP_CFG_LPM(GPIO47, AF2, FLOAT)
-#define GPIO47_UART1_DSR        MFP_CFG_LPM(GPIO47, AF4, FLOAT)
-#define GPIO101_UART1_DTR       MFP_CFG_LPM(GPIO101, AF6, FLOAT)
-#define GPIO101_UART1_DSR       MFP_CFG_LPM(GPIO101, AF1, FLOAT)
-#define GPIO103_UART1_DTR       MFP_CFG_LPM(GPIO103, AF1, FLOAT)
-#define GPIO103_UART1_DSR       MFP_CFG_LPM(GPIO103, AF6, FLOAT)
-#define GPIO44_UART1_DCD        MFP_CFG_LPM(GPIO44, AF2, FLOAT)
-#define GPIO100_UART1_DCD       MFP_CFG_LPM(GPIO100, AF1, FLOAT)
-#define GPIO46_UART1_RI         MFP_CFG_LPM(GPIO46, AF2, FLOAT)
-#define GPIO102_UART1_RI        MFP_CFG_LPM(GPIO102, AF1, FLOAT)
-
-/* UART2 */
-#define GPIO109_UART2_CTS       MFP_CFG_LPM(GPIO109, AF3, FLOAT)
-#define GPIO109_UART2_RTS       MFP_CFG_LPM(GPIO109, AF1, FLOAT)
-#define GPIO112_UART2_CTS       MFP_CFG_LPM(GPIO112, AF1, FLOAT)
-#define GPIO112_UART2_RTS       MFP_CFG_LPM(GPIO112, AF3, FLOAT)
-#define GPIO110_UART2_RXD       MFP_CFG_LPM(GPIO110, AF1, FLOAT)
-#define GPIO110_UART2_TXD       MFP_CFG_LPM(GPIO110, AF3, FLOAT)
-#define GPIO111_UART2_RXD       MFP_CFG_LPM(GPIO111, AF3, FLOAT)
-#define GPIO111_UART2_TXD       MFP_CFG_LPM(GPIO111, AF1, FLOAT)
-
-/* UART3 */
-#define GPIO89_UART3_CTS        MFP_CFG_LPM(GPIO89, AF2, FLOAT)
-#define GPIO89_UART3_RTS        MFP_CFG_LPM(GPIO89, AF4, FLOAT)
-#define GPIO90_UART3_CTS        MFP_CFG_LPM(GPIO90, AF4, FLOAT)
-#define GPIO90_UART3_RTS        MFP_CFG_LPM(GPIO90, AF2, FLOAT)
-#define GPIO105_UART3_CTS       MFP_CFG_LPM(GPIO105, AF1, FLOAT)
-#define GPIO105_UART3_RTS       MFP_CFG_LPM(GPIO105, AF3, FLOAT)
-#define GPIO106_UART3_CTS       MFP_CFG_LPM(GPIO106, AF3, FLOAT)
-#define GPIO106_UART3_RTS       MFP_CFG_LPM(GPIO106, AF1, FLOAT)
-#define GPIO30_UART3_RXD        MFP_CFG_LPM(GPIO30, AF2, FLOAT)
-#define GPIO30_UART3_TXD        MFP_CFG_LPM(GPIO30, AF6, FLOAT)
-#define GPIO31_UART3_RXD        MFP_CFG_LPM(GPIO31, AF6, FLOAT)
-#define GPIO31_UART3_TXD        MFP_CFG_LPM(GPIO31, AF2, FLOAT)
-#define GPIO91_UART3_RXD        MFP_CFG_LPM(GPIO91, AF4, FLOAT)
-#define GPIO91_UART3_TXD        MFP_CFG_LPM(GPIO91, AF2, FLOAT)
-#define GPIO92_UART3_RXD        MFP_CFG_LPM(GPIO92, AF2, FLOAT)
-#define GPIO92_UART3_TXD        MFP_CFG_LPM(GPIO92, AF4, FLOAT)
-#define GPIO107_UART3_RXD       MFP_CFG_LPM(GPIO107, AF3, FLOAT)
-#define GPIO107_UART3_TXD       MFP_CFG_LPM(GPIO107, AF1, FLOAT)
-#define GPIO108_UART3_RXD       MFP_CFG_LPM(GPIO108, AF1, FLOAT)
-#define GPIO108_UART3_TXD       MFP_CFG_LPM(GPIO108, AF3, FLOAT)
-
-
-/* USB 2.0 UTMI */
-#define GPIO10_UTM_CLK          MFP_CFG(GPIO10, AF1)
-#define GPIO36_U2D_RXERROR      MFP_CFG(GPIO36, AF3)
-#define GPIO60_U2D_RXERROR      MFP_CFG(GPIO60, AF1)
-#define GPIO87_U2D_RXERROR      MFP_CFG(GPIO87, AF5)
-#define GPIO34_UTM_RXVALID      MFP_CFG(GPIO34, AF3)
-#define GPIO58_UTM_RXVALID      MFP_CFG(GPIO58, AF2)
-#define GPIO85_UTM_RXVALID      MFP_CFG(GPIO85, AF5)
-#define GPIO35_UTM_RXACTIVE     MFP_CFG(GPIO35, AF3)
-#define GPIO59_UTM_RXACTIVE     MFP_CFG(GPIO59, AF1)
-#define GPIO86_UTM_RXACTIVE     MFP_CFG(GPIO86, AF5)
-#define GPIO73_UTM_TXREADY      MFP_CFG(GPIO73, AF1)
-#define GPIO68_UTM_LINESTATE_0  MFP_CFG(GPIO68, AF3)
-#define GPIO90_UTM_LINESTATE_0  MFP_CFG(GPIO90, AF3)
-#define GPIO102_UTM_LINESTATE_0 MFP_CFG(GPIO102, AF3)
-#define GPIO107_UTM_LINESTATE_0 MFP_CFG(GPIO107, AF4)
-#define GPIO69_UTM_LINESTATE_1  MFP_CFG(GPIO69, AF3)
-#define GPIO91_UTM_LINESTATE_1  MFP_CFG(GPIO91, AF3)
-#define GPIO103_UTM_LINESTATE_1 MFP_CFG(GPIO103, AF3)
-
-#define GPIO41_U2D_PHYDATA_0    MFP_CFG(GPIO41, AF3)
-#define GPIO42_U2D_PHYDATA_1    MFP_CFG(GPIO42, AF3)
-#define GPIO43_U2D_PHYDATA_2    MFP_CFG(GPIO43, AF3)
-#define GPIO44_U2D_PHYDATA_3    MFP_CFG(GPIO44, AF3)
-#define GPIO45_U2D_PHYDATA_4    MFP_CFG(GPIO45, AF3)
-#define GPIO46_U2D_PHYDATA_5    MFP_CFG(GPIO46, AF3)
-#define GPIO47_U2D_PHYDATA_6    MFP_CFG(GPIO47, AF3)
-#define GPIO48_U2D_PHYDATA_7    MFP_CFG(GPIO48, AF3)
-
-#define GPIO49_U2D_PHYDATA_0    MFP_CFG(GPIO49, AF3)
-#define GPIO50_U2D_PHYDATA_1    MFP_CFG(GPIO50, AF3)
-#define GPIO51_U2D_PHYDATA_2    MFP_CFG(GPIO51, AF3)
-#define GPIO52_U2D_PHYDATA_3    MFP_CFG(GPIO52, AF3)
-#define GPIO53_U2D_PHYDATA_4    MFP_CFG(GPIO53, AF3)
-#define GPIO54_U2D_PHYDATA_5    MFP_CFG(GPIO54, AF3)
-#define GPIO55_U2D_PHYDATA_6    MFP_CFG(GPIO55, AF3)
-#define GPIO56_U2D_PHYDATA_7    MFP_CFG(GPIO56, AF3)
-
-#define GPIO37_U2D_OPMODE0      MFP_CFG(GPIO37, AF4)
-#define GPIO61_U2D_OPMODE0      MFP_CFG(GPIO61, AF2)
-#define GPIO88_U2D_OPMODE0      MFP_CFG(GPIO88, AF7)
-
-#define GPIO38_U2D_OPMODE1      MFP_CFG(GPIO38, AF4)
-#define GPIO62_U2D_OPMODE1      MFP_CFG(GPIO62, AF2)
-#define GPIO104_U2D_OPMODE1     MFP_CFG(GPIO104, AF4)
-#define GPIO108_U2D_OPMODE1     MFP_CFG(GPIO108, AF5)
-
-#define GPIO74_U2D_RESET        MFP_CFG(GPIO74, AF1)
-#define GPIO93_U2D_RESET        MFP_CFG(GPIO93, AF2)
-#define GPIO98_U2D_RESET        MFP_CFG(GPIO98, AF3)
-
-#define GPIO67_U2D_SUSPEND      MFP_CFG(GPIO67, AF3)
-#define GPIO96_U2D_SUSPEND      MFP_CFG(GPIO96, AF2)
-#define GPIO101_U2D_SUSPEND     MFP_CFG(GPIO101, AF3)
-
-#define GPIO66_U2D_TERM_SEL     MFP_CFG(GPIO66, AF5)
-#define GPIO95_U2D_TERM_SEL     MFP_CFG(GPIO95, AF3)
-#define GPIO97_U2D_TERM_SEL     MFP_CFG(GPIO97, AF7)
-#define GPIO100_U2D_TERM_SEL    MFP_CFG(GPIO100, AF5)
-
-#define GPIO39_U2D_TXVALID      MFP_CFG(GPIO39, AF4)
-#define GPIO70_U2D_TXVALID      MFP_CFG(GPIO70, AF5)
-#define GPIO83_U2D_TXVALID      MFP_CFG(GPIO83, AF7)
-
-#define GPIO65_U2D_XCVR_SEL     MFP_CFG(GPIO65, AF5)
-#define GPIO94_U2D_XCVR_SEL     MFP_CFG(GPIO94, AF3)
-#define GPIO99_U2D_XCVR_SEL     MFP_CFG(GPIO99, AF5)
-
-/* USB Host 1.1 */
-#define GPIO2_2_USBH_PEN        MFP_CFG(GPIO2_2, AF1)
-#define GPIO3_2_USBH_PWR        MFP_CFG(GPIO3_2, AF1)
-
-/* USB P2 */
-#define GPIO97_USB_P2_2         MFP_CFG(GPIO97, AF2)
-#define GPIO97_USB_P2_6         MFP_CFG(GPIO97, AF4)
-#define GPIO98_USB_P2_2         MFP_CFG(GPIO98, AF4)
-#define GPIO98_USB_P2_6         MFP_CFG(GPIO98, AF2)
-#define GPIO99_USB_P2_1         MFP_CFG(GPIO99, AF2)
-#define GPIO100_USB_P2_4        MFP_CFG(GPIO100, AF2)
-#define GPIO101_USB_P2_8        MFP_CFG(GPIO101, AF2)
-#define GPIO102_USB_P2_3        MFP_CFG(GPIO102, AF2)
-#define GPIO103_USB_P2_5        MFP_CFG(GPIO103, AF2)
-#define GPIO104_USB_P2_7        MFP_CFG(GPIO104, AF2)
-
-/* USB P3 */
-#define GPIO75_USB_P3_1         MFP_CFG(GPIO75, AF2)
-#define GPIO76_USB_P3_2         MFP_CFG(GPIO76, AF2)
-#define GPIO77_USB_P3_3         MFP_CFG(GPIO77, AF2)
-#define GPIO78_USB_P3_4         MFP_CFG(GPIO78, AF2)
-#define GPIO79_USB_P3_5         MFP_CFG(GPIO79, AF2)
-#define GPIO80_USB_P3_6         MFP_CFG(GPIO80, AF2)
-
-#define GPIO13_CHOUT0           MFP_CFG(GPIO13, AF6)
-#define GPIO14_CHOUT1           MFP_CFG(GPIO14, AF6)
-
-#define GPIO2_RDY               MFP_CFG(GPIO2, AF1)
-#define GPIO5_NPIOR             MFP_CFG(GPIO5, AF3)
-
-#define GPIO11_PWM0_OUT         MFP_CFG(GPIO11, AF1)
-#define GPIO12_PWM1_OUT         MFP_CFG(GPIO12, AF1)
-#define GPIO13_PWM2_OUT         MFP_CFG(GPIO13, AF1)
-#define GPIO14_PWM3_OUT         MFP_CFG(GPIO14, AF1)
-
-#endif /* __ASM_ARCH_MFP_PXA320_H */
diff --git a/include/asm-arm/arch-pxa/mfp-pxa930.h b/include/asm-arm/arch-pxa/mfp-pxa930.h
deleted file mode 100644
index c4e945ab1923..000000000000
--- a/include/asm-arm/arch-pxa/mfp-pxa930.h
+++ /dev/null
@@ -1,491 +0,0 @@
-/*
- * linux/include/asm-arm/arch-pxa/mfp-pxa930.h
- *
- * PXA930 specific MFP configuration definitions
- *
- * Copyright (C) 2007-2008 Marvell International Ltd.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MFP_PXA9xx_H
-#define __ASM_ARCH_MFP_PXA9xx_H
-
-#include <asm/arch/mfp.h>
-#include <asm/arch/mfp-pxa3xx.h>
-
-/* GPIO */
-#define GPIO46_GPIO             MFP_CFG(GPIO46, AF0)
-#define GPIO49_GPIO             MFP_CFG(GPIO49, AF0)
-#define GPIO50_GPIO             MFP_CFG(GPIO50, AF0)
-#define GPIO51_GPIO             MFP_CFG(GPIO51, AF0)
-#define GPIO52_GPIO             MFP_CFG(GPIO52, AF0)
-#define GPIO56_GPIO             MFP_CFG(GPIO56, AF0)
-#define GPIO58_GPIO             MFP_CFG(GPIO58, AF0)
-#define GPIO59_GPIO             MFP_CFG(GPIO59, AF0)
-#define GPIO60_GPIO             MFP_CFG(GPIO60, AF0)
-#define GPIO61_GPIO             MFP_CFG(GPIO61, AF0)
-#define GPIO62_GPIO             MFP_CFG(GPIO62, AF0)
-
-#define GSIM_UCLK_GPIO_79       MFP_CFG(GSIM_UCLK, AF0)
-#define GSIM_UIO_GPIO_80        MFP_CFG(GSIM_UIO, AF0)
-#define GSIM_nURST_GPIO_81      MFP_CFG(GSIM_nURST, AF0)
-#define GSIM_UDET_GPIO_82       MFP_CFG(GSIM_UDET, AF0)
-
-#define DF_IO15_GPIO_28         MFP_CFG(DF_IO15, AF0)
-#define DF_IO14_GPIO_29         MFP_CFG(DF_IO14, AF0)
-#define DF_IO13_GPIO_30         MFP_CFG(DF_IO13, AF0)
-#define DF_IO12_GPIO_31         MFP_CFG(DF_IO12, AF0)
-#define DF_IO11_GPIO_32         MFP_CFG(DF_IO11, AF0)
-#define DF_IO10_GPIO_33         MFP_CFG(DF_IO10, AF0)
-#define DF_IO9_GPIO_34          MFP_CFG(DF_IO9, AF0)
-#define DF_IO8_GPIO_35          MFP_CFG(DF_IO8, AF0)
-#define DF_IO7_GPIO_36          MFP_CFG(DF_IO7, AF0)
-#define DF_IO6_GPIO_37          MFP_CFG(DF_IO6, AF0)
-#define DF_IO5_GPIO_38          MFP_CFG(DF_IO5, AF0)
-#define DF_IO4_GPIO_39          MFP_CFG(DF_IO4, AF0)
-#define DF_IO3_GPIO_40          MFP_CFG(DF_IO3, AF0)
-#define DF_IO2_GPIO_41          MFP_CFG(DF_IO2, AF0)
-#define DF_IO1_GPIO_42          MFP_CFG(DF_IO1, AF0)
-#define DF_IO0_GPIO_43          MFP_CFG(DF_IO0, AF0)
-#define DF_nCS0_GPIO_44         MFP_CFG(DF_nCS0, AF0)
-#define DF_nCS1_GPIO_45         MFP_CFG(DF_nCS1, AF0)
-#define DF_nWE_GPIO_46          MFP_CFG(DF_nWE, AF0)
-#define DF_nRE_nOE_GPIO_47      MFP_CFG(DF_nRE_nOE, AF0)
-#define DF_CLE_nOE_GPIO_48      MFP_CFG(DF_CLE_nOE, AF0)
-#define DF_nADV1_ALE_GPIO_49    MFP_CFG(DF_nADV1_ALE, AF0)
-#define DF_nADV2_ALE_GPIO_50    MFP_CFG(DF_nADV2_ALE, AF0)
-#define DF_INT_RnB_GPIO_51      MFP_CFG(DF_INT_RnB, AF0)
-#define DF_SCLK_E_GPIO_52       MFP_CFG(DF_SCLK_E, AF0)
-
-#define DF_ADDR0_GPIO_53        MFP_CFG(DF_ADDR0, AF0)
-#define DF_ADDR1_GPIO_54        MFP_CFG(DF_ADDR1, AF0)
-#define DF_ADDR2_GPIO_55        MFP_CFG(DF_ADDR2, AF0)
-#define DF_ADDR3_GPIO_56        MFP_CFG(DF_ADDR3, AF0)
-#define nXCVREN_GPIO_57         MFP_CFG(nXCVREN, AF0)
-#define nLUA_GPIO_58            MFP_CFG(nLUA, AF0)
-#define nLLA_GPIO_59            MFP_CFG(nLLA, AF0)
-#define nBE0_GPIO_60            MFP_CFG(nBE0, AF0)
-#define nBE1_GPIO_61            MFP_CFG(nBE1, AF0)
-#define RDY_GPIO_62             MFP_CFG(RDY, AF0)
-
-/* Chip Select */
-#define DF_nCS0_nCS2            MFP_CFG_LPM(DF_nCS0, AF3, PULL_HIGH)
-#define DF_nCS1_nCS3            MFP_CFG_LPM(DF_nCS1, AF3, PULL_HIGH)
-
-/* AC97 */
-#define GPIO83_BAC97_SYSCLK     MFP_CFG(GPIO83, AF3)
-#define GPIO84_BAC97_SDATA_IN0  MFP_CFG(GPIO84, AF3)
-#define GPIO85_BAC97_BITCLK     MFP_CFG(GPIO85, AF3)
-#define GPIO86_BAC97_nRESET     MFP_CFG(GPIO86, AF3)
-#define GPIO87_BAC97_SYNC       MFP_CFG(GPIO87, AF3)
-#define GPIO88_BAC97_SDATA_OUT  MFP_CFG(GPIO88, AF3)
-
-/* I2C */
-#define GPIO39_CI2C_SCL         MFP_CFG_LPM(GPIO39, AF3, PULL_HIGH)
-#define GPIO40_CI2C_SDA         MFP_CFG_LPM(GPIO40, AF3, PULL_HIGH)
-
-#define GPIO51_CI2C_SCL         MFP_CFG_LPM(GPIO51, AF3, PULL_HIGH)
-#define GPIO52_CI2C_SDA         MFP_CFG_LPM(GPIO52, AF3, PULL_HIGH)
-
-#define GPIO63_CI2C_SCL         MFP_CFG_LPM(GPIO63, AF4, PULL_HIGH)
-#define GPIO64_CI2C_SDA         MFP_CFG_LPM(GPIO64, AF4, PULL_HIGH)
-
-#define GPIO77_CI2C_SCL         MFP_CFG_LPM(GPIO77, AF2, PULL_HIGH)
-#define GPIO78_CI2C_SDA         MFP_CFG_LPM(GPIO78, AF2, PULL_HIGH)
-
-#define GPIO89_CI2C_SCL         MFP_CFG_LPM(GPIO89, AF1, PULL_HIGH)
-#define GPIO90_CI2C_SDA         MFP_CFG_LPM(GPIO90, AF1, PULL_HIGH)
-
-#define GPIO95_CI2C_SCL         MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH)
-#define GPIO96_CI2C_SDA         MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH)
-
-#define GPIO97_CI2C_SCL         MFP_CFG_LPM(GPIO97, AF3, PULL_HIGH)
-#define GPIO98_CI2C_SDA         MFP_CFG_LPM(GPIO98, AF3, PULL_HIGH)
-
-/* QCI */
-#define GPIO63_CI_DD_9          MFP_CFG_LPM(GPIO63, AF1, PULL_LOW)
-#define GPIO64_CI_DD_8          MFP_CFG_LPM(GPIO64, AF1, PULL_LOW)
-#define GPIO65_CI_DD_7          MFP_CFG_LPM(GPIO65, AF1, PULL_LOW)
-#define GPIO66_CI_DD_6          MFP_CFG_LPM(GPIO66, AF1, PULL_LOW)
-#define GPIO67_CI_DD_5          MFP_CFG_LPM(GPIO67, AF1, PULL_LOW)
-#define GPIO68_CI_DD_4          MFP_CFG_LPM(GPIO68, AF1, PULL_LOW)
-#define GPIO69_CI_DD_3          MFP_CFG_LPM(GPIO69, AF1, PULL_LOW)
-#define GPIO70_CI_DD_2          MFP_CFG_LPM(GPIO70, AF1, PULL_LOW)
-#define GPIO71_CI_DD_1          MFP_CFG_LPM(GPIO71, AF1, PULL_LOW)
-#define GPIO72_CI_DD_0          MFP_CFG_LPM(GPIO72, AF1, PULL_LOW)
-#define GPIO73_CI_HSYNC         MFP_CFG_LPM(GPIO73, AF1, PULL_LOW)
-#define GPIO74_CI_VSYNC         MFP_CFG_LPM(GPIO74, AF1, PULL_LOW)
-#define GPIO75_CI_MCLK          MFP_CFG_LPM(GPIO75, AF1, PULL_LOW)
-#define GPIO76_CI_PCLK          MFP_CFG_LPM(GPIO76, AF1, PULL_LOW)
-
-/* KEYPAD */
-#define GPIO4_KP_DKIN_4         MFP_CFG_LPM(GPIO4, AF3, FLOAT)
-#define GPIO5_KP_DKIN_5         MFP_CFG_LPM(GPIO5, AF3, FLOAT)
-#define GPIO6_KP_DKIN_6         MFP_CFG_LPM(GPIO6, AF3, FLOAT)
-#define GPIO7_KP_DKIN_7         MFP_CFG_LPM(GPIO7, AF3, FLOAT)
-#define GPIO8_KP_DKIN_4         MFP_CFG_LPM(GPIO8, AF3, FLOAT)
-#define GPIO9_KP_DKIN_5         MFP_CFG_LPM(GPIO9, AF3, FLOAT)
-#define GPIO10_KP_DKIN_6        MFP_CFG_LPM(GPIO10, AF3, FLOAT)
-#define GPIO11_KP_DKIN_7        MFP_CFG_LPM(GPIO11, AF3, FLOAT)
-
-#define GPIO12_KP_DKIN_0        MFP_CFG_LPM(GPIO12, AF2, FLOAT)
-#define GPIO13_KP_DKIN_1        MFP_CFG_LPM(GPIO13, AF2, FLOAT)
-#define GPIO14_KP_DKIN_2        MFP_CFG_LPM(GPIO14, AF2, FLOAT)
-#define GPIO15_KP_DKIN_3        MFP_CFG_LPM(GPIO15, AF2, FLOAT)
-
-#define GPIO41_KP_DKIN_0        MFP_CFG_LPM(GPIO41, AF2, FLOAT)
-#define GPIO42_KP_DKIN_1        MFP_CFG_LPM(GPIO42, AF2, FLOAT)
-#define GPIO43_KP_DKIN_2        MFP_CFG_LPM(GPIO43, AF2, FLOAT)
-#define GPIO44_KP_DKIN_3        MFP_CFG_LPM(GPIO44, AF2, FLOAT)
-#define GPIO41_KP_DKIN_4        MFP_CFG_LPM(GPIO41, AF4, FLOAT)
-#define GPIO42_KP_DKIN_5        MFP_CFG_LPM(GPIO42, AF4, FLOAT)
-
-#define GPIO0_KP_MKIN_0         MFP_CFG_LPM(GPIO0, AF1, FLOAT)
-#define GPIO2_KP_MKIN_1         MFP_CFG_LPM(GPIO2, AF1, FLOAT)
-#define GPIO4_KP_MKIN_2         MFP_CFG_LPM(GPIO4, AF1, FLOAT)
-#define GPIO6_KP_MKIN_3         MFP_CFG_LPM(GPIO6, AF1, FLOAT)
-#define GPIO8_KP_MKIN_4         MFP_CFG_LPM(GPIO8, AF1, FLOAT)
-#define GPIO10_KP_MKIN_5        MFP_CFG_LPM(GPIO10, AF1, FLOAT)
-#define GPIO12_KP_MKIN_6        MFP_CFG_LPM(GPIO12, AF1, FLOAT)
-#define GPIO14_KP_MKIN_7        MFP_CFG(GPIO14, AF1)
-#define GPIO35_KP_MKIN_5        MFP_CFG(GPIO35, AF4)
-
-#define GPIO1_KP_MKOUT_0        MFP_CFG_LPM(GPIO1, AF1, DRIVE_HIGH)
-#define GPIO3_KP_MKOUT_1        MFP_CFG_LPM(GPIO3, AF1, DRIVE_HIGH)
-#define GPIO5_KP_MKOUT_2        MFP_CFG_LPM(GPIO5, AF1, DRIVE_HIGH)
-#define GPIO7_KP_MKOUT_3        MFP_CFG_LPM(GPIO7, AF1, DRIVE_HIGH)
-#define GPIO9_KP_MKOUT_4        MFP_CFG_LPM(GPIO9, AF1, DRIVE_HIGH)
-#define GPIO11_KP_MKOUT_5       MFP_CFG_LPM(GPIO11, AF1, DRIVE_HIGH)
-#define GPIO13_KP_MKOUT_6       MFP_CFG_LPM(GPIO13, AF1, DRIVE_HIGH)
-#define GPIO15_KP_MKOUT_7       MFP_CFG_LPM(GPIO15, AF1, DRIVE_HIGH)
-#define GPIO36_KP_MKOUT_5       MFP_CFG_LPM(GPIO36, AF4, DRIVE_HIGH)
-
-/* LCD */
-#define GPIO17_LCD_FCLK_RD      MFP_CFG(GPIO17, AF1)
-#define GPIO18_LCD_LCLK_A0      MFP_CFG(GPIO18, AF1)
-#define GPIO19_LCD_PCLK_WR      MFP_CFG(GPIO19, AF1)
-#define GPIO20_LCD_BIAS         MFP_CFG(GPIO20, AF1)
-#define GPIO21_LCD_CS           MFP_CFG(GPIO21, AF1)
-#define GPIO22_LCD_CS2          MFP_CFG(GPIO22, AF2)
-#define GPIO22_LCD_VSYNC        MFP_CFG(GPIO22, AF1)
-#define GPIO23_LCD_DD0          MFP_CFG(GPIO23, AF1)
-#define GPIO24_LCD_DD1          MFP_CFG(GPIO24, AF1)
-#define GPIO25_LCD_DD2          MFP_CFG(GPIO25, AF1)
-#define GPIO26_LCD_DD3          MFP_CFG(GPIO26, AF1)
-#define GPIO27_LCD_DD4          MFP_CFG(GPIO27, AF1)
-#define GPIO28_LCD_DD5          MFP_CFG(GPIO28, AF1)
-#define GPIO29_LCD_DD6          MFP_CFG(GPIO29, AF1)
-#define GPIO30_LCD_DD7          MFP_CFG(GPIO30, AF1)
-#define GPIO31_LCD_DD8          MFP_CFG(GPIO31, AF1)
-#define GPIO32_LCD_DD9          MFP_CFG(GPIO32, AF1)
-#define GPIO33_LCD_DD10         MFP_CFG(GPIO33, AF1)
-#define GPIO34_LCD_DD11         MFP_CFG(GPIO34, AF1)
-#define GPIO35_LCD_DD12         MFP_CFG(GPIO35, AF1)
-#define GPIO36_LCD_DD13         MFP_CFG(GPIO36, AF1)
-#define GPIO37_LCD_DD14         MFP_CFG(GPIO37, AF1)
-#define GPIO38_LCD_DD15         MFP_CFG(GPIO38, AF1)
-#define GPIO39_LCD_DD16         MFP_CFG(GPIO39, AF1)
-#define GPIO40_LCD_DD17         MFP_CFG(GPIO40, AF1)
-#define GPIO41_LCD_CS2          MFP_CFG(GPIO41, AF3)
-#define GPIO42_LCD_VSYNC2       MFP_CFG(GPIO42, AF3)
-#define GPIO44_LCD_DD7          MFP_CFG(GPIO44, AF1)
-
-/* Mini-LCD */
-#define GPIO17_MLCD_FCLK        MFP_CFG(GPIO17, AF3)
-#define GPIO18_MLCD_LCLK        MFP_CFG(GPIO18, AF3)
-#define GPIO19_MLCD_PCLK        MFP_CFG(GPIO19, AF3)
-#define GPIO20_MLCD_BIAS        MFP_CFG(GPIO20, AF3)
-#define GPIO23_MLCD_DD0         MFP_CFG(GPIO23, AF3)
-#define GPIO24_MLCD_DD1         MFP_CFG(GPIO24, AF3)
-#define GPIO25_MLCD_DD2         MFP_CFG(GPIO25, AF3)
-#define GPIO26_MLCD_DD3         MFP_CFG(GPIO26, AF3)
-#define GPIO27_MLCD_DD4         MFP_CFG(GPIO27, AF3)
-#define GPIO28_MLCD_DD5         MFP_CFG(GPIO28, AF3)
-#define GPIO29_MLCD_DD6         MFP_CFG(GPIO29, AF3)
-#define GPIO30_MLCD_DD7         MFP_CFG(GPIO30, AF3)
-#define GPIO31_MLCD_DD8         MFP_CFG(GPIO31, AF3)
-#define GPIO32_MLCD_DD9         MFP_CFG(GPIO32, AF3)
-#define GPIO33_MLCD_DD10        MFP_CFG(GPIO33, AF3)
-#define GPIO34_MLCD_DD11        MFP_CFG(GPIO34, AF3)
-#define GPIO35_MLCD_DD12        MFP_CFG(GPIO35, AF3)
-#define GPIO36_MLCD_DD13        MFP_CFG(GPIO36, AF3)
-#define GPIO37_MLCD_DD14        MFP_CFG(GPIO37, AF3)
-#define GPIO38_MLCD_DD15        MFP_CFG(GPIO38, AF3)
-#define GPIO44_MLCD_DD7         MFP_CFG(GPIO44, AF5)
-
-/* MMC1 */
-#define GPIO10_MMC1_DAT3        MFP_CFG(GPIO10, AF4)
-#define GPIO11_MMC1_DAT2        MFP_CFG(GPIO11, AF4)
-#define GPIO12_MMC1_DAT1        MFP_CFG(GPIO12, AF4)
-#define GPIO13_MMC1_DAT0        MFP_CFG(GPIO13, AF4)
-#define GPIO14_MMC1_CMD         MFP_CFG(GPIO14, AF4)
-#define GPIO15_MMC1_CLK         MFP_CFG(GPIO15, AF4)
-#define GPIO55_MMC1_CMD         MFP_CFG(GPIO55, AF3)
-#define GPIO56_MMC1_CLK         MFP_CFG(GPIO56, AF3)
-#define GPIO57_MMC1_DAT0        MFP_CFG(GPIO57, AF3)
-#define GPIO58_MMC1_DAT1        MFP_CFG(GPIO58, AF3)
-#define GPIO59_MMC1_DAT2        MFP_CFG(GPIO59, AF3)
-#define GPIO60_MMC1_DAT3        MFP_CFG(GPIO60, AF3)
-
-#define DF_ADDR0_MMC1_CLK       MFP_CFG(DF_ADDR0, AF2)
-#define DF_ADDR1_MMC1_CMD       MFP_CFG(DF_ADDR1, AF2)
-#define DF_ADDR2_MMC1_DAT0      MFP_CFG(DF_ADDR2, AF2)
-#define DF_ADDR3_MMC1_DAT1      MFP_CFG(DF_ADDR3, AF3)
-#define nXCVREN_MMC1_DAT2       MFP_CFG(nXCVREN, AF2)
-
-/* MMC2 */
-#define GPIO31_MMC2_CMD         MFP_CFG(GPIO31, AF7)
-#define GPIO32_MMC2_CLK         MFP_CFG(GPIO32, AF7)
-#define GPIO33_MMC2_DAT0        MFP_CFG(GPIO33, AF7)
-#define GPIO34_MMC2_DAT1        MFP_CFG(GPIO34, AF7)
-#define GPIO35_MMC2_DAT2        MFP_CFG(GPIO35, AF7)
-#define GPIO36_MMC2_DAT3        MFP_CFG(GPIO36, AF7)
-
-#define GPIO101_MMC2_DAT3       MFP_CFG(GPIO101, AF1)
-#define GPIO102_MMC2_DAT2       MFP_CFG(GPIO102, AF1)
-#define GPIO103_MMC2_DAT1       MFP_CFG(GPIO103, AF1)
-#define GPIO104_MMC2_DAT0       MFP_CFG(GPIO104, AF1)
-#define GPIO105_MMC2_CMD        MFP_CFG(GPIO105, AF1)
-#define GPIO106_MMC2_CLK        MFP_CFG(GPIO106, AF1)
-
-#define DF_IO10_MMC2_DAT3       MFP_CFG(DF_IO10, AF3)
-#define DF_IO11_MMC2_DAT2       MFP_CFG(DF_IO11, AF3)
-#define DF_IO12_MMC2_DAT1       MFP_CFG(DF_IO12, AF3)
-#define DF_IO13_MMC2_DAT0       MFP_CFG(DF_IO13, AF3)
-#define DF_IO14_MMC2_CLK        MFP_CFG(DF_IO14, AF3)
-#define DF_IO15_MMC2_CMD        MFP_CFG(DF_IO15, AF3)
-
-/* BSSP1 */
-#define GPIO12_BSSP1_CLK        MFP_CFG(GPIO12, AF3)
-#define GPIO13_BSSP1_FRM        MFP_CFG(GPIO13, AF3)
-#define GPIO14_BSSP1_RXD        MFP_CFG(GPIO14, AF3)
-#define GPIO15_BSSP1_TXD        MFP_CFG(GPIO15, AF3)
-#define GPIO97_BSSP1_CLK        MFP_CFG(GPIO97, AF5)
-#define GPIO98_BSSP1_FRM        MFP_CFG(GPIO98, AF5)
-
-/* BSSP2 */
-#define GPIO84_BSSP2_SDATA_IN   MFP_CFG(GPIO84, AF1)
-#define GPIO85_BSSP2_BITCLK     MFP_CFG(GPIO85, AF1)
-#define GPIO86_BSSP2_SYSCLK     MFP_CFG(GPIO86, AF1)
-#define GPIO87_BSSP2_SYNC       MFP_CFG(GPIO87, AF1)
-#define GPIO88_BSSP2_DATA_OUT   MFP_CFG(GPIO88, AF1)
-#define GPIO86_BSSP2_SDATA_IN   MFP_CFG(GPIO86, AF4)
-
-/* BSSP3 */
-#define GPIO79_BSSP3_CLK        MFP_CFG(GPIO79, AF1)
-#define GPIO80_BSSP3_FRM        MFP_CFG(GPIO80, AF1)
-#define GPIO81_BSSP3_TXD        MFP_CFG(GPIO81, AF1)
-#define GPIO82_BSSP3_RXD        MFP_CFG(GPIO82, AF1)
-#define GPIO83_BSSP3_SYSCLK     MFP_CFG(GPIO83, AF1)
-
-/* BSSP4 */
-#define GPIO43_BSSP4_CLK        MFP_CFG(GPIO43, AF4)
-#define GPIO44_BSSP4_FRM        MFP_CFG(GPIO44, AF4)
-#define GPIO45_BSSP4_TXD        MFP_CFG(GPIO45, AF4)
-#define GPIO46_BSSP4_RXD        MFP_CFG(GPIO46, AF4)
-
-#define GPIO51_BSSP4_CLK        MFP_CFG(GPIO51, AF4)
-#define GPIO52_BSSP4_FRM        MFP_CFG(GPIO52, AF4)
-#define GPIO53_BSSP4_TXD        MFP_CFG(GPIO53, AF4)
-#define GPIO54_BSSP4_RXD        MFP_CFG(GPIO54, AF4)
-
-/* GSSP1 */
-#define GPIO79_GSSP1_CLK        MFP_CFG(GPIO79, AF2)
-#define GPIO80_GSSP1_FRM        MFP_CFG(GPIO80, AF2)
-#define GPIO81_GSSP1_TXD        MFP_CFG(GPIO81, AF2)
-#define GPIO82_GSSP1_RXD        MFP_CFG(GPIO82, AF2)
-#define GPIO83_GSSP1_SYSCLK     MFP_CFG(GPIO83, AF2)
-
-#define GPIO93_GSSP1_CLK        MFP_CFG(GPIO93, AF4)
-#define GPIO94_GSSP1_FRM        MFP_CFG(GPIO94, AF4)
-#define GPIO95_GSSP1_TXD        MFP_CFG(GPIO95, AF4)
-#define GPIO96_GSSP1_RXD        MFP_CFG(GPIO96, AF4)
-
-/* GSSP2 */
-#define GPIO47_GSSP2_CLK        MFP_CFG(GPIO47, AF4)
-#define GPIO48_GSSP2_FRM        MFP_CFG(GPIO48, AF4)
-#define GPIO49_GSSP2_RXD        MFP_CFG(GPIO49, AF4)
-#define GPIO50_GSSP2_TXD        MFP_CFG(GPIO50, AF4)
-
-#define GPIO69_GSSP2_CLK        MFP_CFG(GPIO69, AF4)
-#define GPIO70_GSSP2_FRM        MFP_CFG(GPIO70, AF4)
-#define GPIO71_GSSP2_RXD        MFP_CFG(GPIO71, AF4)
-#define GPIO72_GSSP2_TXD        MFP_CFG(GPIO72, AF4)
-
-#define GPIO84_GSSP2_RXD        MFP_CFG(GPIO84, AF2)
-#define GPIO85_GSSP2_CLK        MFP_CFG(GPIO85, AF2)
-#define GPIO86_GSSP2_SYSCLK     MFP_CFG(GPIO86, AF2)
-#define GPIO87_GSSP2_FRM        MFP_CFG(GPIO87, AF2)
-#define GPIO88_GSSP2_TXD        MFP_CFG(GPIO88, AF2)
-#define GPIO86_GSSP2_RXD        MFP_CFG(GPIO86, AF5)
-
-#define GPIO103_GSSP2_CLK       MFP_CFG(GPIO103, AF2)
-#define GPIO104_GSSP2_FRM       MFP_CFG(GPIO104, AF2)
-#define GPIO105_GSSP2_RXD       MFP_CFG(GPIO105, AF2)
-#define GPIO106_GSSP2_TXD       MFP_CFG(GPIO106, AF2)
-
-/* UART1 - FFUART */
-#define GPIO47_UART1_DSR_N      MFP_CFG(GPIO47, AF1)
-#define GPIO48_UART1_DTR_N      MFP_CFG(GPIO48, AF1)
-#define GPIO49_UART1_RI         MFP_CFG(GPIO49, AF1)
-#define GPIO50_UART1_DCD        MFP_CFG(GPIO50, AF1)
-#define GPIO51_UART1_CTS        MFP_CFG(GPIO51, AF1)
-#define GPIO52_UART1_RTS        MFP_CFG(GPIO52, AF1)
-#define GPIO53_UART1_RXD        MFP_CFG(GPIO53, AF1)
-#define GPIO54_UART1_TXD        MFP_CFG(GPIO54, AF1)
-
-#define GPIO63_UART1_TXD        MFP_CFG(GPIO63, AF2)
-#define GPIO64_UART1_RXD        MFP_CFG(GPIO64, AF2)
-#define GPIO65_UART1_DSR        MFP_CFG(GPIO65, AF2)
-#define GPIO66_UART1_DTR        MFP_CFG(GPIO66, AF2)
-#define GPIO67_UART1_RI         MFP_CFG(GPIO67, AF2)
-#define GPIO68_UART1_DCD        MFP_CFG(GPIO68, AF2)
-#define GPIO69_UART1_CTS        MFP_CFG(GPIO69, AF2)
-#define GPIO70_UART1_RTS        MFP_CFG(GPIO70, AF2)
-
-/* UART2 - BTUART */
-#define GPIO91_UART2_RXD        MFP_CFG(GPIO91, AF1)
-#define GPIO92_UART2_TXD        MFP_CFG(GPIO92, AF1)
-#define GPIO93_UART2_CTS        MFP_CFG(GPIO93, AF1)
-#define GPIO94_UART2_RTS        MFP_CFG(GPIO94, AF1)
-
-/* UART3 - STUART */
-#define GPIO43_UART3_RTS        MFP_CFG(GPIO43, AF3)
-#define GPIO44_UART3_CTS        MFP_CFG(GPIO44, AF3)
-#define GPIO45_UART3_RXD        MFP_CFG(GPIO45, AF3)
-#define GPIO46_UART3_TXD        MFP_CFG(GPIO46, AF3)
-
-#define GPIO75_UART3_RTS        MFP_CFG(GPIO75, AF5)
-#define GPIO76_UART3_CTS        MFP_CFG(GPIO76, AF5)
-#define GPIO77_UART3_TXD        MFP_CFG(GPIO77, AF5)
-#define GPIO78_UART3_RXD        MFP_CFG(GPIO78, AF5)
-
-/* DFI */
-#define DF_IO0_DF_IO0           MFP_CFG(DF_IO0, AF2)
-#define DF_IO1_DF_IO1           MFP_CFG(DF_IO1, AF2)
-#define DF_IO2_DF_IO2           MFP_CFG(DF_IO2, AF2)
-#define DF_IO3_DF_IO3           MFP_CFG(DF_IO3, AF2)
-#define DF_IO4_DF_IO4           MFP_CFG(DF_IO4, AF2)
-#define DF_IO5_DF_IO5           MFP_CFG(DF_IO5, AF2)
-#define DF_IO6_DF_IO6           MFP_CFG(DF_IO6, AF2)
-#define DF_IO7_DF_IO7           MFP_CFG(DF_IO7, AF2)
-#define DF_IO8_DF_IO8           MFP_CFG(DF_IO8, AF2)
-#define DF_IO9_DF_IO9           MFP_CFG(DF_IO9, AF2)
-#define DF_IO10_DF_IO10         MFP_CFG(DF_IO10, AF2)
-#define DF_IO11_DF_IO11         MFP_CFG(DF_IO11, AF2)
-#define DF_IO12_DF_IO12         MFP_CFG(DF_IO12, AF2)
-#define DF_IO13_DF_IO13         MFP_CFG(DF_IO13, AF2)
-#define DF_IO14_DF_IO14         MFP_CFG(DF_IO14, AF2)
-#define DF_IO15_DF_IO15         MFP_CFG(DF_IO15, AF2)
-#define DF_nADV1_ALE_DF_nADV1   MFP_CFG(DF_nADV1_ALE, AF2)
-#define DF_nADV2_ALE_DF_nADV2   MFP_CFG(DF_nADV2_ALE, AF2)
-#define DF_nCS0_DF_nCS0         MFP_CFG(DF_nCS0, AF2)
-#define DF_nCS1_DF_nCS1         MFP_CFG(DF_nCS1, AF2)
-#define DF_nRE_nOE_DF_nOE       MFP_CFG(DF_nRE_nOE, AF2)
-#define DF_nWE_DF_nWE           MFP_CFG(DF_nWE, AF2)
-
-/* DFI - NAND */
-#define DF_CLE_nOE_ND_CLE       MFP_CFG_LPM(DF_CLE_nOE, AF1, PULL_HIGH)
-#define DF_INT_RnB_ND_INT_RnB   MFP_CFG_LPM(DF_INT_RnB, AF1, PULL_LOW)
-#define DF_IO0_ND_IO0           MFP_CFG_LPM(DF_IO0, AF1, PULL_LOW)
-#define DF_IO1_ND_IO1           MFP_CFG_LPM(DF_IO1, AF1, PULL_LOW)
-#define DF_IO2_ND_IO2           MFP_CFG_LPM(DF_IO2, AF1, PULL_LOW)
-#define DF_IO3_ND_IO3           MFP_CFG_LPM(DF_IO3, AF1, PULL_LOW)
-#define DF_IO4_ND_IO4           MFP_CFG_LPM(DF_IO4, AF1, PULL_LOW)
-#define DF_IO5_ND_IO5           MFP_CFG_LPM(DF_IO5, AF1, PULL_LOW)
-#define DF_IO6_ND_IO6           MFP_CFG_LPM(DF_IO6, AF1, PULL_LOW)
-#define DF_IO7_ND_IO7           MFP_CFG_LPM(DF_IO7, AF1, PULL_LOW)
-#define DF_IO8_ND_IO8           MFP_CFG_LPM(DF_IO8, AF1, PULL_LOW)
-#define DF_IO9_ND_IO9           MFP_CFG_LPM(DF_IO9, AF1, PULL_LOW)
-#define DF_IO10_ND_IO10         MFP_CFG_LPM(DF_IO10, AF1, PULL_LOW)
-#define DF_IO11_ND_IO11         MFP_CFG_LPM(DF_IO11, AF1, PULL_LOW)
-#define DF_IO12_ND_IO12         MFP_CFG_LPM(DF_IO12, AF1, PULL_LOW)
-#define DF_IO13_ND_IO13         MFP_CFG_LPM(DF_IO13, AF1, PULL_LOW)
-#define DF_IO14_ND_IO14         MFP_CFG_LPM(DF_IO14, AF1, PULL_LOW)
-#define DF_IO15_ND_IO15         MFP_CFG_LPM(DF_IO15, AF1, PULL_LOW)
-#define DF_nADV1_ALE_ND_ALE     MFP_CFG_LPM(DF_nADV1_ALE, AF1, PULL_HIGH)
-#define DF_nADV2_ALE_ND_ALE     MFP_CFG_LPM(DF_nADV2_ALE, AF1, PULL_HIGH)
-#define DF_nADV2_ALE_nCS3       MFP_CFG_LPM(DF_nADV2_ALE, AF3, PULL_HIGH)
-#define DF_nCS0_ND_nCS0         MFP_CFG_LPM(DF_nCS0, AF1, PULL_HIGH)
-#define DF_nCS1_ND_nCS1         MFP_CFG_LPM(DF_nCS1, AF1, PULL_HIGH)
-#define DF_nRE_nOE_ND_nRE       MFP_CFG_LPM(DF_nRE_nOE, AF1, PULL_HIGH)
-#define DF_nWE_ND_nWE           MFP_CFG_LPM(DF_nWE, AF1, PULL_HIGH)
-
-/* PWM */
-#define GPIO41_PWM0             MFP_CFG_LPM(GPIO41, AF1, PULL_LOW)
-#define GPIO42_PWM1             MFP_CFG_LPM(GPIO42, AF1, PULL_LOW)
-#define GPIO43_PWM3             MFP_CFG_LPM(GPIO43, AF1, PULL_LOW)
-#define GPIO20_PWM0             MFP_CFG_LPM(GPIO20, AF2, PULL_LOW)
-#define GPIO21_PWM2             MFP_CFG_LPM(GPIO21, AF3, PULL_LOW)
-#define GPIO22_PWM3             MFP_CFG_LPM(GPIO22, AF3, PULL_LOW)
-
-/* CIR */
-#define GPIO46_CIR_OUT          MFP_CFG(GPIO46, AF1)
-#define GPIO77_CIR_OUT          MFP_CFG(GPIO77, AF3)
-
-/* USB P2 */
-#define GPIO0_USB_P2_7          MFP_CFG(GPIO0, AF3)
-#define GPIO15_USB_P2_7         MFP_CFG(GPIO15, AF5)
-#define GPIO16_USB_P2_7         MFP_CFG(GPIO16, AF2)
-#define GPIO48_USB_P2_7         MFP_CFG(GPIO48, AF7)
-#define GPIO49_USB_P2_7         MFP_CFG(GPIO49, AF6)
-#define DF_IO9_USB_P2_7         MFP_CFG(DF_IO9, AF3)
-
-#define GPIO48_USB_P2_8         MFP_CFG(GPIO48, AF2)
-#define GPIO50_USB_P2_7         MFP_CFG_X(GPIO50, AF2, DS02X, FLOAT)
-#define GPIO51_USB_P2_5         MFP_CFG(GPIO51, AF2)
-#define GPIO47_USB_P2_4         MFP_CFG(GPIO47, AF2)
-#define GPIO53_USB_P2_3         MFP_CFG(GPIO53, AF2)
-#define GPIO54_USB_P2_6         MFP_CFG(GPIO54, AF2)
-#define GPIO49_USB_P2_2         MFP_CFG(GPIO49, AF2)
-#define GPIO52_USB_P2_1         MFP_CFG(GPIO52, AF2)
-
-#define GPIO63_USB_P2_8         MFP_CFG(GPIO63, AF3)
-#define GPIO64_USB_P2_7         MFP_CFG(GPIO64, AF3)
-#define GPIO65_USB_P2_6         MFP_CFG(GPIO65, AF3)
-#define GPIO66_USG_P2_5         MFP_CFG(GPIO66, AF3)
-#define GPIO67_USB_P2_4         MFP_CFG(GPIO67, AF3)
-#define GPIO68_USB_P2_3         MFP_CFG(GPIO68, AF3)
-#define GPIO69_USB_P2_2         MFP_CFG(GPIO69, AF3)
-#define GPIO70_USB_P2_1         MFP_CFG(GPIO70, AF3)
-
-/* ULPI */
-#define GPIO31_USB_ULPI_D0      MFP_CFG(GPIO31, AF4)
-#define GPIO30_USB_ULPI_D1      MFP_CFG(GPIO30, AF7)
-#define GPIO33_USB_ULPI_D2      MFP_CFG(GPIO33, AF5)
-#define GPIO34_USB_ULPI_D3      MFP_CFG(GPIO34, AF5)
-#define GPIO35_USB_ULPI_D4      MFP_CFG(GPIO35, AF5)
-#define GPIO36_USB_ULPI_D5      MFP_CFG(GPIO36, AF5)
-#define GPIO41_USB_ULPI_D6      MFP_CFG(GPIO41, AF5)
-#define GPIO42_USB_ULPI_D7      MFP_CFG(GPIO42, AF5)
-#define GPIO37_USB_ULPI_DIR     MFP_CFG(GPIO37, AF4)
-#define GPIO38_USB_ULPI_CLK     MFP_CFG(GPIO38, AF4)
-#define GPIO39_USB_ULPI_STP     MFP_CFG(GPIO39, AF4)
-#define GPIO40_USB_ULPI_NXT     MFP_CFG(GPIO40, AF4)
-
-#define GPIO3_CLK26MOUTDMD      MFP_CFG(GPIO3, AF3)
-#define GPIO40_CLK26MOUTDMD     MFP_CFG(GPIO40, AF7)
-#define GPIO94_CLK26MOUTDMD     MFP_CFG(GPIO94, AF5)
-#define GPIO104_CLK26MOUTDMD    MFP_CFG(GPIO104, AF4)
-#define DF_ADDR1_CLK26MOUTDMD   MFP_CFG(DF_ADDR2, AF3)
-#define DF_ADDR3_CLK26MOUTDMD   MFP_CFG(DF_ADDR3, AF3)
-
-#define GPIO14_CLK26MOUT        MFP_CFG(GPIO14, AF5)
-#define GPIO38_CLK26MOUT        MFP_CFG(GPIO38, AF7)
-#define GPIO92_CLK26MOUT        MFP_CFG(GPIO92, AF5)
-#define GPIO105_CLK26MOUT       MFP_CFG(GPIO105, AF4)
-
-#define GPIO2_CLK13MOUTDMD      MFP_CFG(GPIO2, AF3)
-#define GPIO39_CLK13MOUTDMD     MFP_CFG(GPIO39, AF7)
-#define GPIO50_CLK13MOUTDMD     MFP_CFG(GPIO50, AF3)
-#define GPIO93_CLK13MOUTDMD     MFP_CFG(GPIO93, AF5)
-#define GPIO103_CLK13MOUTDMD    MFP_CFG(GPIO103, AF4)
-#define DF_ADDR2_CLK13MOUTDMD   MFP_CFG(DF_ADDR2, AF3)
-
-/* 1 wire */
-#define GPIO95_OW_DQ_IN         MFP_CFG(GPIO95, AF5)
-
-#endif /* __ASM_ARCH_MFP_PXA9xx_H */
diff --git a/include/asm-arm/arch-pxa/mfp.h b/include/asm-arm/arch-pxa/mfp.h
deleted file mode 100644
index e7d58798da67..000000000000
--- a/include/asm-arm/arch-pxa/mfp.h
+++ /dev/null
@@ -1,319 +0,0 @@
-/*
- * linux/include/asm-arm/arch-pxa/mfp.h
- *
- * Multi-Function Pin Definitions
- *
- * Copyright (C) 2007 Marvell International Ltd.
- *
- * 2007-8-21: eric miao <eric.miao@marvell.com>
- *            initial version
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MFP_H
-#define __ASM_ARCH_MFP_H
-
-#define mfp_to_gpio(m)  ((m) % 128)
-
-/* list of all the configurable MFP pins */
-enum {
-        MFP_PIN_INVALID = -1,
-
-        MFP_PIN_GPIO0 = 0,
-        MFP_PIN_GPIO1,
-        MFP_PIN_GPIO2,
-        MFP_PIN_GPIO3,
-        MFP_PIN_GPIO4,
-        MFP_PIN_GPIO5,
-        MFP_PIN_GPIO6,
-        MFP_PIN_GPIO7,
-        MFP_PIN_GPIO8,
-        MFP_PIN_GPIO9,
-        MFP_PIN_GPIO10,
-        MFP_PIN_GPIO11,
-        MFP_PIN_GPIO12,
-        MFP_PIN_GPIO13,
-        MFP_PIN_GPIO14,
-        MFP_PIN_GPIO15,
-        MFP_PIN_GPIO16,
-        MFP_PIN_GPIO17,
-        MFP_PIN_GPIO18,
-        MFP_PIN_GPIO19,
-        MFP_PIN_GPIO20,
-        MFP_PIN_GPIO21,
-        MFP_PIN_GPIO22,
-        MFP_PIN_GPIO23,
-        MFP_PIN_GPIO24,
-        MFP_PIN_GPIO25,
-        MFP_PIN_GPIO26,
-        MFP_PIN_GPIO27,
-        MFP_PIN_GPIO28,
-        MFP_PIN_GPIO29,
-        MFP_PIN_GPIO30,
-        MFP_PIN_GPIO31,
-        MFP_PIN_GPIO32,
-        MFP_PIN_GPIO33,
-        MFP_PIN_GPIO34,
-        MFP_PIN_GPIO35,
-        MFP_PIN_GPIO36,
-        MFP_PIN_GPIO37,
-        MFP_PIN_GPIO38,
-        MFP_PIN_GPIO39,
-        MFP_PIN_GPIO40,
-        MFP_PIN_GPIO41,
-        MFP_PIN_GPIO42,
-        MFP_PIN_GPIO43,
-        MFP_PIN_GPIO44,
-        MFP_PIN_GPIO45,
-        MFP_PIN_GPIO46,
-        MFP_PIN_GPIO47,
-        MFP_PIN_GPIO48,
-        MFP_PIN_GPIO49,
-        MFP_PIN_GPIO50,
-        MFP_PIN_GPIO51,
-        MFP_PIN_GPIO52,
-        MFP_PIN_GPIO53,
-        MFP_PIN_GPIO54,
-        MFP_PIN_GPIO55,
-        MFP_PIN_GPIO56,
-        MFP_PIN_GPIO57,
-        MFP_PIN_GPIO58,
-        MFP_PIN_GPIO59,
-        MFP_PIN_GPIO60,
-        MFP_PIN_GPIO61,
-        MFP_PIN_GPIO62,
-        MFP_PIN_GPIO63,
-        MFP_PIN_GPIO64,
-        MFP_PIN_GPIO65,
-        MFP_PIN_GPIO66,
-        MFP_PIN_GPIO67,
-        MFP_PIN_GPIO68,
-        MFP_PIN_GPIO69,
-        MFP_PIN_GPIO70,
-        MFP_PIN_GPIO71,
-        MFP_PIN_GPIO72,
-        MFP_PIN_GPIO73,
-        MFP_PIN_GPIO74,
-        MFP_PIN_GPIO75,
-        MFP_PIN_GPIO76,
-        MFP_PIN_GPIO77,
-        MFP_PIN_GPIO78,
-        MFP_PIN_GPIO79,
-        MFP_PIN_GPIO80,
-        MFP_PIN_GPIO81,
-        MFP_PIN_GPIO82,
-        MFP_PIN_GPIO83,
-        MFP_PIN_GPIO84,
-        MFP_PIN_GPIO85,
-        MFP_PIN_GPIO86,
-        MFP_PIN_GPIO87,
-        MFP_PIN_GPIO88,
-        MFP_PIN_GPIO89,
-        MFP_PIN_GPIO90,
-        MFP_PIN_GPIO91,
-        MFP_PIN_GPIO92,
-        MFP_PIN_GPIO93,
-        MFP_PIN_GPIO94,
-        MFP_PIN_GPIO95,
-        MFP_PIN_GPIO96,
-        MFP_PIN_GPIO97,
-        MFP_PIN_GPIO98,
-        MFP_PIN_GPIO99,
-        MFP_PIN_GPIO100,
-        MFP_PIN_GPIO101,
-        MFP_PIN_GPIO102,
-        MFP_PIN_GPIO103,
-        MFP_PIN_GPIO104,
-        MFP_PIN_GPIO105,
-        MFP_PIN_GPIO106,
-        MFP_PIN_GPIO107,
-        MFP_PIN_GPIO108,
-        MFP_PIN_GPIO109,
-        MFP_PIN_GPIO110,
-        MFP_PIN_GPIO111,
-        MFP_PIN_GPIO112,
-        MFP_PIN_GPIO113,
-        MFP_PIN_GPIO114,
-        MFP_PIN_GPIO115,
-        MFP_PIN_GPIO116,
-        MFP_PIN_GPIO117,
-        MFP_PIN_GPIO118,
-        MFP_PIN_GPIO119,
-        MFP_PIN_GPIO120,
-        MFP_PIN_GPIO121,
-        MFP_PIN_GPIO122,
-        MFP_PIN_GPIO123,
-        MFP_PIN_GPIO124,
-        MFP_PIN_GPIO125,
-        MFP_PIN_GPIO126,
-        MFP_PIN_GPIO127,
-        MFP_PIN_GPIO0_2,
-        MFP_PIN_GPIO1_2,
-        MFP_PIN_GPIO2_2,
-        MFP_PIN_GPIO3_2,
-        MFP_PIN_GPIO4_2,
-        MFP_PIN_GPIO5_2,
-        MFP_PIN_GPIO6_2,
-        MFP_PIN_GPIO7_2,
-        MFP_PIN_GPIO8_2,
-        MFP_PIN_GPIO9_2,
-        MFP_PIN_GPIO10_2,
-        MFP_PIN_GPIO11_2,
-        MFP_PIN_GPIO12_2,
-        MFP_PIN_GPIO13_2,
-        MFP_PIN_GPIO14_2,
-        MFP_PIN_GPIO15_2,
-        MFP_PIN_GPIO16_2,
-        MFP_PIN_GPIO17_2,
-
-        MFP_PIN_ULPI_STP,
-        MFP_PIN_ULPI_NXT,
-        MFP_PIN_ULPI_DIR,
-
-        MFP_PIN_nXCVREN,
-        MFP_PIN_DF_CLE_nOE,
-        MFP_PIN_DF_nADV1_ALE,
-        MFP_PIN_DF_SCLK_E,
-        MFP_PIN_DF_SCLK_S,
-        MFP_PIN_nBE0,
-        MFP_PIN_nBE1,
-        MFP_PIN_DF_nADV2_ALE,
-        MFP_PIN_DF_INT_RnB,
-        MFP_PIN_DF_nCS0,
-        MFP_PIN_DF_nCS1,
-        MFP_PIN_nLUA,
-        MFP_PIN_nLLA,
-        MFP_PIN_DF_nWE,
-        MFP_PIN_DF_ALE_nWE,
-        MFP_PIN_DF_nRE_nOE,
-        MFP_PIN_DF_ADDR0,
-        MFP_PIN_DF_ADDR1,
-        MFP_PIN_DF_ADDR2,
-        MFP_PIN_DF_ADDR3,
-        MFP_PIN_DF_IO0,
-        MFP_PIN_DF_IO1,
-        MFP_PIN_DF_IO2,
-        MFP_PIN_DF_IO3,
-        MFP_PIN_DF_IO4,
-        MFP_PIN_DF_IO5,
-        MFP_PIN_DF_IO6,
-        MFP_PIN_DF_IO7,
-        MFP_PIN_DF_IO8,
-        MFP_PIN_DF_IO9,
-        MFP_PIN_DF_IO10,
-        MFP_PIN_DF_IO11,
-        MFP_PIN_DF_IO12,
-        MFP_PIN_DF_IO13,
-        MFP_PIN_DF_IO14,
-        MFP_PIN_DF_IO15,
-
-        /* additional pins on PXA930 */
-        MFP_PIN_GSIM_UIO,
-        MFP_PIN_GSIM_UCLK,
-        MFP_PIN_GSIM_UDET,
-        MFP_PIN_GSIM_nURST,
-        MFP_PIN_PMIC_INT,
-        MFP_PIN_RDY,
-
-        MFP_PIN_MAX,
-};
-
-/*
- * a possible MFP configuration is represented by a 32-bit integer
- *
- * bit  0.. 9 - MFP Pin Number (1024 Pins Maximum)
- * bit 10..12 - Alternate Function Selection
- * bit 13..15 - Drive Strength
- * bit 16..18 - Low Power Mode State
- * bit 19..20 - Low Power Mode Edge Detection
- * bit 21..22 - Run Mode Pull State
- *
- * to facilitate the definition, the following macros are provided
- *
- * MFP_CFG_DEFAULT - default MFP configuration value, with
- *                alternate function = 0,
- *                drive strength = fast 3mA (MFP_DS03X)
- *                low power mode = default
- *                edge detection = none
- *
- * MFP_CFG      - default MFPR value with alternate function
- * MFP_CFG_DRV  - default MFPR value with alternate function and
- *                pin drive strength
- * MFP_CFG_LPM  - default MFPR value with alternate function and
- *                low power mode
- * MFP_CFG_X    - default MFPR value with alternate function,
- *                pin drive strength and low power mode
- */
-
-typedef unsigned long mfp_cfg_t;
-
-#define MFP_PIN(x)              ((x) & 0x3ff)
-
-#define MFP_AF0                 (0x0 << 10)
-#define MFP_AF1                 (0x1 << 10)
-#define MFP_AF2                 (0x2 << 10)
-#define MFP_AF3                 (0x3 << 10)
-#define MFP_AF4                 (0x4 << 10)
-#define MFP_AF5                 (0x5 << 10)
-#define MFP_AF6                 (0x6 << 10)
-#define MFP_AF7                 (0x7 << 10)
-#define MFP_AF_MASK             (0x7 << 10)
-#define MFP_AF(x)               (((x) >> 10) & 0x7)
-
-#define MFP_DS01X               (0x0 << 13)
-#define MFP_DS02X               (0x1 << 13)
-#define MFP_DS03X               (0x2 << 13)
-#define MFP_DS04X               (0x3 << 13)
-#define MFP_DS06X               (0x4 << 13)
-#define MFP_DS08X               (0x5 << 13)
-#define MFP_DS10X               (0x6 << 13)
-#define MFP_DS13X               (0x7 << 13)
-#define MFP_DS_MASK             (0x7 << 13)
-#define MFP_DS(x)               (((x) >> 13) & 0x7)
-
-#define MFP_LPM_INPUT           (0x0 << 16)
-#define MFP_LPM_DRIVE_LOW       (0x1 << 16)
-#define MFP_LPM_DRIVE_HIGH      (0x2 << 16)
-#define MFP_LPM_PULL_LOW        (0x3 << 16)
-#define MFP_LPM_PULL_HIGH       (0x4 << 16)
-#define MFP_LPM_FLOAT           (0x5 << 16)
-#define MFP_LPM_STATE_MASK      (0x7 << 16)
-#define MFP_LPM_STATE(x)        (((x) >> 16) & 0x7)
-
-#define MFP_LPM_EDGE_NONE       (0x0 << 19)
-#define MFP_LPM_EDGE_RISE       (0x1 << 19)
-#define MFP_LPM_EDGE_FALL       (0x2 << 19)
-#define MFP_LPM_EDGE_BOTH       (0x3 << 19)
-#define MFP_LPM_EDGE_MASK       (0x3 << 19)
-#define MFP_LPM_EDGE(x)         (((x) >> 19) & 0x3)
-
-#define MFP_PULL_NONE           (0x0 << 21)
-#define MFP_PULL_LOW            (0x1 << 21)
-#define MFP_PULL_HIGH           (0x2 << 21)
-#define MFP_PULL_BOTH           (0x3 << 21)
-#define MFP_PULL_MASK           (0x3 << 21)
-#define MFP_PULL(x)             (((x) >> 21) & 0x3)
-
-#define MFP_CFG_DEFAULT         (MFP_AF0 | MFP_DS03X | MFP_LPM_INPUT |\
-                                 MFP_LPM_EDGE_NONE | MFP_PULL_NONE)
-
-#define MFP_CFG(pin, af)                \
-        ((MFP_CFG_DEFAULT & ~MFP_AF_MASK) |\
-         (MFP_PIN(MFP_PIN_##pin) | MFP_##af))
-
-#define MFP_CFG_DRV(pin, af, drv)       \
-        ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK)) |\
-         (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv))
-
-#define MFP_CFG_LPM(pin, af, lpm)       \
-        ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_LPM_STATE_MASK)) |\
-         (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_LPM_##lpm))
-
-#define MFP_CFG_X(pin, af, drv, lpm)    \
-        ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\
-         (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm))
-
-#endif /* __ASM_ARCH_MFP_H */
diff --git a/include/asm-arm/arch-pxa/mtd-xip.h b/include/asm-arm/arch-pxa/mtd-xip.h
deleted file mode 100644
index 8704dbceb432..000000000000
--- a/include/asm-arm/arch-pxa/mtd-xip.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * MTD primitives for XIP support. Architecture specific functions
- *
- * Do not include this file directly. It's included from linux/mtd/xip.h
- * 
- * Author:      Nicolas Pitre
- * Created:     Nov 2, 2004
- * Copyright:   (C) 2004 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * $Id: xip.h,v 1.2 2004/12/01 15:49:10 nico Exp $
- */
-
-#ifndef __ARCH_PXA_MTD_XIP_H__
-#define __ARCH_PXA_MTD_XIP_H__
-
-#include <asm/arch/pxa-regs.h>
-
-#define xip_irqpending()        (ICIP & ICMR)
-
-/* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */
-#define xip_currtime()          (OSCR)
-#define xip_elapsed_since(x)    (signed)((OSCR - (x)) / 4)
-
-/*
- * xip_cpu_idle() is used when waiting for a delay equal or larger than
- * the system timer tick period.  This should put the CPU into idle mode
- * to save power and to be woken up only when some interrupts are pending.
- * As above, this should not rely upon standard kernel code.
- */
-
-#define xip_cpu_idle()  asm volatile ("mcr p14, 0, %0, c7, c0, 0" :: "r" (1))
-
-#endif /* __ARCH_PXA_MTD_XIP_H__ */
diff --git a/include/asm-arm/arch-pxa/pcm027.h b/include/asm-arm/arch-pxa/pcm027.h
deleted file mode 100644
index 7beae1472c3e..000000000000
--- a/include/asm-arm/arch-pxa/pcm027.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * linux/include/asm-arm/arch-pxa/pcm027.h
- *
- * (c) 2003 Phytec Messtechnik GmbH <armlinux@phytec.de>
- * (c) 2007 Juergen Beisert <j.beisert@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-/*
- * Definitions of CPU card resources only
- */
-
-/* I2C RTC */
-#define PCM027_RTC_IRQ_GPIO     0
-#define PCM027_RTC_IRQ          IRQ_GPIO(PCM027_RTC_IRQ_GPIO)
-#define PCM027_RTC_IRQ_EDGE     IRQ_TYPE_EDGE_FALLING
-#define ADR_PCM027_RTC          0x51    /* I2C address */
-
-/* I2C EEPROM */
-#define ADR_PCM027_EEPROM       0x54    /* I2C address */
-
-/* Ethernet chip (SMSC91C111) */
-#define PCM027_ETH_IRQ_GPIO     52
-#define PCM027_ETH_IRQ          IRQ_GPIO(PCM027_ETH_IRQ_GPIO)
-#define PCM027_ETH_IRQ_EDGE     IRQ_TYPE_EDGE_RISING
-#define PCM027_ETH_PHYS         PXA_CS5_PHYS
-#define PCM027_ETH_SIZE         (1*1024*1024)
-
-/* CAN controller SJA1000 (unsupported yet) */
-#define PCM027_CAN_IRQ_GPIO     114
-#define PCM027_CAN_IRQ          IRQ_GPIO(PCM027_CAN_IRQ_GPIO)
-#define PCM027_CAN_IRQ_EDGE     IRQ_TYPE_EDGE_FALLING
-#define PCM027_CAN_PHYS         0x22000000
-#define PCM027_CAN_SIZE         0x100
-
-/* SPI GPIO expander (unsupported yet) */
-#define PCM027_EGPIO_IRQ_GPIO   27
-#define PCM027_EGPIO_IRQ        IRQ_GPIO(PCM027_EGPIO_IRQ_GPIO)
-#define PCM027_EGPIO_IRQ_EDGE   IRQ_TYPE_EDGE_FALLING
-#define PCM027_EGPIO_CS         24
-/*
- * TODO: Switch this pin from dedicated usage to GPIO if
- * more than the MAX7301 device is connected to this SPI bus
- */
-#define PCM027_EGPIO_CS_MODE    GPIO24_SFRM_MD
-
-/* Flash memory */
-#define PCM027_FLASH_PHYS       0x00000000
-#define PCM027_FLASH_SIZE       0x02000000
-
-/* onboard LEDs connected to GPIO */
-#define PCM027_LED_CPU          90
-#define PCM027_LED_HEARD_BEAT   91
-
-/*
- * This CPU module needs a baseboard to work. After basic initializing
- * its own devices, it calls baseboard's init function.
- * TODO: Add your own basebaord init function and call it from
- * inside pcm027_init(). This example here is for the developmen board.
- * Refer pcm990-baseboard.c
- */
-extern void pcm990_baseboard_init(void);
diff --git a/include/asm-arm/arch-pxa/pcm990_baseboard.h b/include/asm-arm/arch-pxa/pcm990_baseboard.h
deleted file mode 100644
index 2e2013179063..000000000000
--- a/include/asm-arm/arch-pxa/pcm990_baseboard.h
+++ /dev/null
@@ -1,275 +0,0 @@
-/*
- * include/asm-arm/arch-pxa/pcm990_baseboard.h
- *
- * (c) 2003 Phytec Messtechnik GmbH <armlinux@phytec.de>
- * (c) 2007 Juergen Beisert <j.beisert@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <asm/arch/pcm027.h>
-
-/*
- * definitions relevant only when the PCM-990
- * development base board is in use
- */
-
-/* CPLD's interrupt controller is connected to PCM-027 GPIO 9 */
-#define PCM990_CTRL_INT_IRQ_GPIO        9
-#define PCM990_CTRL_INT_IRQ             IRQ_GPIO(PCM990_CTRL_INT_IRQ_GPIO)
-#define PCM990_CTRL_INT_IRQ_EDGE        IRQ_TYPE_EDGE_RISING
-#define PCM990_CTRL_PHYS                PXA_CS1_PHYS    /* 16-Bit */
-#define PCM990_CTRL_BASE                0xea000000
-#define PCM990_CTRL_SIZE                (1*1024*1024)
-
-#define PCM990_CTRL_PWR_IRQ_GPIO        14
-#define PCM990_CTRL_PWR_IRQ             IRQ_GPIO(PCM990_CTRL_PWR_IRQ_GPIO)
-#define PCM990_CTRL_PWR_IRQ_EDGE        IRQ_TYPE_EDGE_RISING
-
-/* visible CPLD (U7) registers */
-#define PCM990_CTRL_REG0        0x0000  /* RESET REGISTER */
-#define PCM990_CTRL_SYSRES      0x0001  /* System RESET REGISTER */
-#define PCM990_CTRL_RESOUT      0x0002  /* RESETOUT Enable REGISTER */
-#define PCM990_CTRL_RESGPIO     0x0004  /* RESETGPIO Enable REGISTER */
-
-#define PCM990_CTRL_REG1        0x0002  /* Power REGISTER */
-#define PCM990_CTRL_5VOFF       0x0001  /* Disable  5V Regulators */
-#define PCM990_CTRL_CANPWR      0x0004  /* Enable CANPWR ADUM */
-#define PCM990_CTRL_PM_5V       0x0008  /* Read 5V OK */
-
-#define PCM990_CTRL_REG2        0x0004  /* LED REGISTER */
-#define PCM990_CTRL_LEDPWR      0x0001  /* POWER LED enable */
-#define PCM990_CTRL_LEDBAS      0x0002  /* BASIS LED enable */
-#define PCM990_CTRL_LEDUSR      0x0004  /* USER LED enable */
-
-#define PCM990_CTRL_REG3        0x0006  /* LCD CTRL REGISTER 3 */
-#define PCM990_CTRL_LCDPWR      0x0001  /* RW LCD Power on */
-#define PCM990_CTRL_LCDON       0x0002  /* RW LCD Latch on */
-#define PCM990_CTRL_LCDPOS1     0x0004  /* RW POS 1 */
-#define PCM990_CTRL_LCDPOS2     0x0008  /* RW POS 2 */
-
-#define PCM990_CTRL_REG4        0x0008  /* MMC1 CTRL REGISTER 4 */
-#define PCM990_CTRL_MMC1PWR     0x0001 /* RW MMC1 Power on */
-
-#define PCM990_CTRL_REG5        0x000A  /* MMC2 CTRL REGISTER 5 */
-#define PCM990_CTRL_MMC2PWR     0x0001  /* RW MMC2 Power on */
-#define PCM990_CTRL_MMC2LED     0x0002  /* RW MMC2 LED */
-#define PCM990_CTRL_MMC2DE      0x0004  /* R MMC2 Card detect */
-#define PCM990_CTRL_MMC2WP      0x0008  /* R MMC2 Card write protect */
-
-#define PCM990_CTRL_REG6        0x000C  /* Interrupt Clear REGISTER */
-#define PCM990_CTRL_INTC0       0x0001  /* Clear Reg BT Detect */
-#define PCM990_CTRL_INTC1       0x0002  /* Clear Reg FR RI */
-#define PCM990_CTRL_INTC2       0x0004  /* Clear Reg MMC1 Detect */
-#define PCM990_CTRL_INTC3       0x0008  /* Clear Reg PM_5V off */
-
-#define PCM990_CTRL_REG7        0x000E  /* Interrupt Enable REGISTER */
-#define PCM990_CTRL_ENAINT0     0x0001  /* Enable Int BT Detect */
-#define PCM990_CTRL_ENAINT1     0x0002  /* Enable Int FR RI */
-#define PCM990_CTRL_ENAINT2     0x0004  /* Enable Int MMC1 Detect */
-#define PCM990_CTRL_ENAINT3     0x0008  /* Enable Int PM_5V off */
-
-#define PCM990_CTRL_REG8        0x0014  /* Uart REGISTER */
-#define PCM990_CTRL_FFSD        0x0001  /* BT Uart Enable */
-#define PCM990_CTRL_BTSD        0x0002  /* FF Uart Enable */
-#define PCM990_CTRL_FFRI        0x0004  /* FF Uart RI detect */
-#define PCM990_CTRL_BTRX        0x0008  /* BT Uart Rx detect */
-
-#define PCM990_CTRL_REG9        0x0010  /* AC97 Flash REGISTER */
-#define PCM990_CTRL_FLWP        0x0001  /* pC Flash Write Protect */
-#define PCM990_CTRL_FLDIS       0x0002  /* pC Flash Disable */
-#define PCM990_CTRL_AC97ENA     0x0004  /* Enable AC97 Expansion */
-
-#define PCM990_CTRL_REG10       0x0012  /* GPS-REGISTER */
-#define PCM990_CTRL_GPSPWR      0x0004  /* GPS-Modul Power on */
-#define PCM990_CTRL_GPSENA      0x0008  /* GPS-Modul Enable */
-
-#define PCM990_CTRL_REG11       0x0014  /* Accu REGISTER */
-#define PCM990_CTRL_ACENA       0x0001  /* Charge Enable */
-#define PCM990_CTRL_ACSEL       0x0002  /* Charge Akku -> DC Enable */
-#define PCM990_CTRL_ACPRES      0x0004  /* DC Present */
-#define PCM990_CTRL_ACALARM     0x0008  /* Error Akku */
-
-#define PCM990_CTRL_P2V(x)      ((x) - PCM990_CTRL_PHYS + PCM990_CTRL_BASE)
-#define PCM990_CTRL_V2P(x)      ((x) - PCM990_CTRL_BASE + PCM990_CTRL_PHYS)
-
-#ifndef __ASSEMBLY__
-#  define __PCM990_CTRL_REG(x) \
-                (*((volatile unsigned char *)PCM990_CTRL_P2V(x)))
-#else
-#  define __PCM990_CTRL_REG(x)  PCM990_CTRL_P2V(x)
-#endif
-
-#define PCM990_INTMSKENA __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG7)
-#define PCM990_INTSETCLR __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG6)
-#define PCM990_CTRL0    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG0)
-#define PCM990_CTRL1    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG1)
-#define PCM990_CTRL2    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG2)
-#define PCM990_CTRL3    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG3)
-#define PCM990_CTRL4    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG4)
-#define PCM990_CTRL5    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG5)
-#define PCM990_CTRL6    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG6)
-#define PCM990_CTRL7    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG7)
-#define PCM990_CTRL8    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG8)
-#define PCM990_CTRL9    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG9)
-#define PCM990_CTRL10   __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG10)
-#define PCM990_CTRL11   __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG11)
-
-
-/*
- * IDE
- */
-#define PCM990_IDE_IRQ_GPIO     13
-#define PCM990_IDE_IRQ          IRQ_GPIO(PCM990_IDE_IRQ_GPIO)
-#define PCM990_IDE_IRQ_EDGE     IRQ_TYPE_EDGE_RISING
-#define PCM990_IDE_PLD_PHYS     0x20000000      /* 16 bit wide */
-#define PCM990_IDE_PLD_BASE     0xee000000
-#define PCM990_IDE_PLD_SIZE     (1*1024*1024)
-
-/* visible CPLD (U6) registers */
-#define PCM990_IDE_PLD_REG0     0x1000  /* OFFSET IDE REGISTER 0 */
-#define PCM990_IDE_PM5V         0x0004  /* R System VCC_5V */
-#define PCM990_IDE_STBY         0x0008  /* R System StandBy */
-
-#define PCM990_IDE_PLD_REG1     0x1002  /* OFFSET IDE REGISTER 1 */
-#define PCM990_IDE_IDEMODE      0x0001  /* R TrueIDE Mode */
-#define PCM990_IDE_DMAENA       0x0004  /* RW DMA Enable */
-#define PCM990_IDE_DMA1_0       0x0008  /* RW 1=DREQ1 0=DREQ0 */
-
-#define PCM990_IDE_PLD_REG2     0x1004  /* OFFSET IDE REGISTER 2 */
-#define PCM990_IDE_RESENA       0x0001  /* RW IDE Reset Bit enable */
-#define PCM990_IDE_RES          0x0002  /* RW IDE Reset Bit */
-#define PCM990_IDE_RDY          0x0008  /* RDY */
-
-#define PCM990_IDE_PLD_REG3     0x1006  /* OFFSET IDE REGISTER 3 */
-#define PCM990_IDE_IDEOE        0x0001  /* RW Latch on Databus */
-#define PCM990_IDE_IDEON        0x0002  /* RW Latch on Control Address */
-#define PCM990_IDE_IDEIN        0x0004  /* RW Latch on Interrupt usw. */
-
-#define PCM990_IDE_PLD_REG4     0x1008  /* OFFSET IDE REGISTER 4 */
-#define PCM990_IDE_PWRENA       0x0001  /* RW IDE Power enable */
-#define PCM990_IDE_5V           0x0002  /* R IDE Power 5V */
-#define PCM990_IDE_PWG          0x0008  /* R IDE Power is on */
-
-#define PCM990_IDE_PLD_P2V(x) ((x) - PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_BASE)
-#define PCM990_IDE_PLD_V2P(x) ((x) - PCM990_IDE_PLD_BASE + PCM990_IDE_PLD_PHYS)
-
-#ifndef __ASSEMBLY__
-# define  __PCM990_IDE_PLD_REG(x) \
-        (*((volatile unsigned char *)PCM990_IDE_PLD_P2V(x)))
-#else
-# define  __PCM990_IDE_PLD_REG(x)       PCM990_IDE_PLD_P2V(x)
-#endif
-
-#define PCM990_IDE0 \
-        __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG0)
-#define PCM990_IDE1 \
-        __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG1)
-#define PCM990_IDE2 \
-        __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG2)
-#define PCM990_IDE3 \
-        __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG3)
-#define PCM990_IDE4 \
-        __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG4)
-
-/*
- * Compact Flash
- */
-#define PCM990_CF_IRQ_GPIO      11
-#define PCM990_CF_IRQ           IRQ_GPIO(PCM990_CF_IRQ_GPIO)
-#define PCM990_CF_IRQ_EDGE      IRQ_TYPE_EDGE_RISING
-
-#define PCM990_CF_CD_GPIO       12
-#define PCM990_CF_CD            IRQ_GPIO(PCM990_CF_CD_GPIO)
-#define PCM990_CF_CD_EDGE       IRQ_TYPE_EDGE_RISING
-
-#define PCM990_CF_PLD_PHYS      0x30000000      /* 16 bit wide */
-#define PCM990_CF_PLD_BASE      0xef000000
-#define PCM990_CF_PLD_SIZE      (1*1024*1024)
-#define PCM990_CF_PLD_P2V(x)    ((x) - PCM990_CF_PLD_PHYS + PCM990_CF_PLD_BASE)
-#define PCM990_CF_PLD_V2P(x)    ((x) - PCM990_CF_PLD_BASE + PCM990_CF_PLD_PHYS)
-
-/* visible CPLD (U6) registers */
-#define PCM990_CF_PLD_REG0      0x1000  /* OFFSET CF REGISTER 0 */
-#define PCM990_CF_REG0_LED      0x0001  /* RW LED on */
-#define PCM990_CF_REG0_BLK      0x0002  /* RW LED flash when access */
-#define PCM990_CF_REG0_PM5V     0x0004  /* R System VCC_5V enable */
-#define PCM990_CF_REG0_STBY     0x0008  /* R System StandBy */
-
-#define PCM990_CF_PLD_REG1      0x1002  /* OFFSET CF REGISTER 1 */
-#define PCM990_CF_REG1_IDEMODE  0x0001  /* RW CF card run as TrueIDE */
-#define PCM990_CF_REG1_CF0      0x0002  /* RW CF card at ADDR 0x28000000 */
-
-#define PCM990_CF_PLD_REG2      0x1004  /* OFFSET CF REGISTER 2 */
-#define PCM990_CF_REG2_RES      0x0002  /* RW CF RESET BIT */
-#define PCM990_CF_REG2_RDYENA   0x0004  /* RW Enable CF_RDY */
-#define PCM990_CF_REG2_RDY      0x0008  /* R CF_RDY auf PWAIT */
-
-#define PCM990_CF_PLD_REG3      0x1006  /* OFFSET CF REGISTER 3 */
-#define PCM990_CF_REG3_CFOE     0x0001  /* RW Latch on Databus */
-#define PCM990_CF_REG3_CFON     0x0002  /* RW Latch on Control Address */
-#define PCM990_CF_REG3_CFIN     0x0004  /* RW Latch on Interrupt usw. */
-#define PCM990_CF_REG3_CFCD     0x0008  /* RW Latch on CD1/2 VS1/2 usw */
-
-#define PCM990_CF_PLD_REG4      0x1008  /* OFFSET CF REGISTER 4 */
-#define PCM990_CF_REG4_PWRENA   0x0001  /* RW CF Power on (CD1/2 = "00") */
-#define PCM990_CF_REG4_5_3V     0x0002  /* RW 1 = 5V CF_VCC 0 = 3 V CF_VCC */
-#define PCM990_CF_REG4_3B       0x0004  /* RW 3.0V Backup from VCC (5_3V=0) */
-#define PCM990_CF_REG4_PWG      0x0008  /* R CF-Power is on */
-
-#define PCM990_CF_PLD_REG5      0x100A  /* OFFSET CF REGISTER 5 */
-#define PCM990_CF_REG5_BVD1     0x0001  /* R CF /BVD1 */
-#define PCM990_CF_REG5_BVD2     0x0002  /* R CF /BVD2 */
-#define PCM990_CF_REG5_VS1      0x0004  /* R CF /VS1 */
-#define PCM990_CF_REG5_VS2      0x0008  /* R CF /VS2 */
-
-#define PCM990_CF_PLD_REG6      0x100C  /* OFFSET CF REGISTER 6 */
-#define PCM990_CF_REG6_CD1      0x0001  /* R CF Card_Detect1 */
-#define PCM990_CF_REG6_CD2      0x0002  /* R CF Card_Detect2 */
-
-#ifndef __ASSEMBLY__
-#  define  __PCM990_CF_PLD_REG(x) \
-        (*((volatile unsigned char *)PCM990_CF_PLD_P2V(x)))
-#else
-#  define  __PCM990_CF_PLD_REG(x)       PCM990_CF_PLD_P2V(x)
-#endif
-
-#define PCM990_CF0 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG0)
-#define PCM990_CF1 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG1)
-#define PCM990_CF2 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG2)
-#define PCM990_CF3 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG3)
-#define PCM990_CF4 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG4)
-#define PCM990_CF5 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG5)
-#define PCM990_CF6 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG6)
-
-/*
- * Wolfson AC97 Touch
- */
-#define PCM990_AC97_IRQ_GPIO    10
-#define PCM990_AC97_IRQ         IRQ_GPIO(PCM990_AC97_IRQ_GPIO)
-#define PCM990_AC97_IRQ_EDGE    IRQ_TYPE_EDGE_RISING
-
-/*
- * MMC phyCORE
- */
-#define PCM990_MMC0_IRQ_GPIO    9
-#define PCM990_MMC0_IRQ         IRQ_GPIO(PCM990_MMC0_IRQ_GPIO)
-#define PCM990_MMC0_IRQ_EDGE    IRQ_TYPE_EDGE_FALLING
-
-/*
- * USB phyCore
- */
-#define PCM990_USB_OVERCURRENT (88 | GPIO_ALT_FN_1_IN)
-#define PCM990_USB_PWR_EN (89 | GPIO_ALT_FN_2_OUT)
diff --git a/include/asm-arm/arch-pxa/poodle.h b/include/asm-arm/arch-pxa/poodle.h
deleted file mode 100644
index 4d6a40315764..000000000000
--- a/include/asm-arm/arch-pxa/poodle.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * linux/include/asm-arm/arch-pxa/poodle.h
- *
- * May be copied or modified under the terms of the GNU General Public
- * License.  See linux/COPYING for more information.
- *
- * Based on:
- *   linux/include/asm-arm/arch-sa1100/collie.h
- *
- * ChangeLog:
- *   04-06-2001 Lineo Japan, Inc.
- *   04-16-2001 SHARP Corporation
- *   Update to 2.6 John Lenz
- */
-#ifndef __ASM_ARCH_POODLE_H
-#define __ASM_ARCH_POODLE_H  1
-
-/*
- * GPIOs
- */
-/* PXA GPIOs */
-#define POODLE_GPIO_ON_KEY              (0)
-#define POODLE_GPIO_AC_IN               (1)
-#define POODLE_GPIO_CO                  16
-#define POODLE_GPIO_TP_INT              (5)
-#define POODLE_GPIO_WAKEUP              (11)    /* change battery */
-#define POODLE_GPIO_GA_INT              (10)
-#define POODLE_GPIO_IR_ON               (22)
-#define POODLE_GPIO_HP_IN               (4)
-#define POODLE_GPIO_CF_IRQ              (17)
-#define POODLE_GPIO_CF_CD               (14)
-#define POODLE_GPIO_CF_STSCHG           (14)
-#define POODLE_GPIO_SD_PWR              (33)
-#define POODLE_GPIO_SD_PWR1             (3)
-#define POODLE_GPIO_nSD_CLK             (6)
-#define POODLE_GPIO_nSD_WP              (7)
-#define POODLE_GPIO_nSD_INT             (8)
-#define POODLE_GPIO_nSD_DETECT          (9)
-#define POODLE_GPIO_MAIN_BAT_LOW        (13)
-#define POODLE_GPIO_BAT_COVER           (13)
-#define POODLE_GPIO_USB_PULLUP          (20)
-#define POODLE_GPIO_ADC_TEMP_ON         (21)
-#define POODLE_GPIO_BYPASS_ON           (36)
-#define POODLE_GPIO_CHRG_ON             (38)
-#define POODLE_GPIO_CHRG_FULL           (16)
-#define POODLE_GPIO_DISCHARGE_ON        (42) /* Enable battery discharge */
-
-/* PXA GPIOs */
-#define POODLE_IRQ_GPIO_ON_KEY          IRQ_GPIO(0)
-#define POODLE_IRQ_GPIO_AC_IN           IRQ_GPIO(1)
-#define POODLE_IRQ_GPIO_HP_IN           IRQ_GPIO(4)
-#define POODLE_IRQ_GPIO_CO              IRQ_GPIO(16)
-#define POODLE_IRQ_GPIO_TP_INT          IRQ_GPIO(5)
-#define POODLE_IRQ_GPIO_WAKEUP          IRQ_GPIO(11)
-#define POODLE_IRQ_GPIO_GA_INT          IRQ_GPIO(10)
-#define POODLE_IRQ_GPIO_CF_IRQ          IRQ_GPIO(17)
-#define POODLE_IRQ_GPIO_CF_CD           IRQ_GPIO(14)
-#define POODLE_IRQ_GPIO_nSD_INT         IRQ_GPIO(8)
-#define POODLE_IRQ_GPIO_nSD_DETECT      IRQ_GPIO(9)
-#define POODLE_IRQ_GPIO_MAIN_BAT_LOW    IRQ_GPIO(13)
-
-/* SCOOP GPIOs */
-#define POODLE_SCOOP_CHARGE_ON  SCOOP_GPCR_PA11
-#define POODLE_SCOOP_CP401      SCOOP_GPCR_PA13
-#define POODLE_SCOOP_VPEN       SCOOP_GPCR_PA18
-#define POODLE_SCOOP_L_PCLK     SCOOP_GPCR_PA20
-#define POODLE_SCOOP_L_LCLK     SCOOP_GPCR_PA21
-#define POODLE_SCOOP_HS_OUT     SCOOP_GPCR_PA22
-
-#define POODLE_SCOOP_IO_DIR     ( POODLE_SCOOP_VPEN | POODLE_SCOOP_HS_OUT )
-#define POODLE_SCOOP_IO_OUT     ( 0 )
-
-extern struct platform_device poodle_locomo_device;
-
-#endif /* __ASM_ARCH_POODLE_H  */
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
deleted file mode 100644
index dce9308626b7..000000000000
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ /dev/null
@@ -1,1070 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-pxa/pxa-regs.h
- *
- *  Author:     Nicolas Pitre
- *  Created:    Jun 15, 2001
- *  Copyright:  MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __PXA_REGS_H
-#define __PXA_REGS_H
-
-
-/*
- * PXA Chip selects
- */
-
-#define PXA_CS0_PHYS    0x00000000
-#define PXA_CS1_PHYS    0x04000000
-#define PXA_CS2_PHYS    0x08000000
-#define PXA_CS3_PHYS    0x0C000000
-#define PXA_CS4_PHYS    0x10000000
-#define PXA_CS5_PHYS    0x14000000
-
-
-/*
- * Personal Computer Memory Card International Association (PCMCIA) sockets
- */
-
-#define PCMCIAPrtSp     0x04000000      /* PCMCIA Partition Space [byte]   */
-#define PCMCIASp        (4*PCMCIAPrtSp) /* PCMCIA Space [byte]             */
-#define PCMCIAIOSp      PCMCIAPrtSp     /* PCMCIA I/O Space [byte]         */
-#define PCMCIAAttrSp    PCMCIAPrtSp     /* PCMCIA Attribute Space [byte]   */
-#define PCMCIAMemSp     PCMCIAPrtSp     /* PCMCIA Memory Space [byte]      */
-
-#define PCMCIA0Sp       PCMCIASp        /* PCMCIA 0 Space [byte]           */
-#define PCMCIA0IOSp     PCMCIAIOSp      /* PCMCIA 0 I/O Space [byte]       */
-#define PCMCIA0AttrSp   PCMCIAAttrSp    /* PCMCIA 0 Attribute Space [byte] */
-#define PCMCIA0MemSp    PCMCIAMemSp     /* PCMCIA 0 Memory Space [byte]    */
-
-#define PCMCIA1Sp       PCMCIASp        /* PCMCIA 1 Space [byte]           */
-#define PCMCIA1IOSp     PCMCIAIOSp      /* PCMCIA 1 I/O Space [byte]       */
-#define PCMCIA1AttrSp   PCMCIAAttrSp    /* PCMCIA 1 Attribute Space [byte] */
-#define PCMCIA1MemSp    PCMCIAMemSp     /* PCMCIA 1 Memory Space [byte]    */
-
-#define _PCMCIA(Nb)                     /* PCMCIA [0..1]                   */ \
-                        (0x20000000 + (Nb)*PCMCIASp)
-#define _PCMCIAIO(Nb)   _PCMCIA (Nb)    /* PCMCIA I/O [0..1]               */
-#define _PCMCIAAttr(Nb)                 /* PCMCIA Attribute [0..1]         */ \
-                        (_PCMCIA (Nb) + 2*PCMCIAPrtSp)
-#define _PCMCIAMem(Nb)                  /* PCMCIA Memory [0..1]            */ \
-                        (_PCMCIA (Nb) + 3*PCMCIAPrtSp)
-
-#define _PCMCIA0        _PCMCIA (0)     /* PCMCIA 0                        */
-#define _PCMCIA0IO      _PCMCIAIO (0)   /* PCMCIA 0 I/O                    */
-#define _PCMCIA0Attr    _PCMCIAAttr (0) /* PCMCIA 0 Attribute              */
-#define _PCMCIA0Mem     _PCMCIAMem (0)  /* PCMCIA 0 Memory                 */
-
-#define _PCMCIA1        _PCMCIA (1)     /* PCMCIA 1                        */
-#define _PCMCIA1IO      _PCMCIAIO (1)   /* PCMCIA 1 I/O                    */
-#define _PCMCIA1Attr    _PCMCIAAttr (1) /* PCMCIA 1 Attribute              */
-#define _PCMCIA1Mem     _PCMCIAMem (1)  /* PCMCIA 1 Memory                 */
-
-
-
-/*
- * DMA Controller
- */
-
-#define DCSR0           __REG(0x40000000)  /* DMA Control / Status Register for Channel 0 */
-#define DCSR1           __REG(0x40000004)  /* DMA Control / Status Register for Channel 1 */
-#define DCSR2           __REG(0x40000008)  /* DMA Control / Status Register for Channel 2 */
-#define DCSR3           __REG(0x4000000c)  /* DMA Control / Status Register for Channel 3 */
-#define DCSR4           __REG(0x40000010)  /* DMA Control / Status Register for Channel 4 */
-#define DCSR5           __REG(0x40000014)  /* DMA Control / Status Register for Channel 5 */
-#define DCSR6           __REG(0x40000018)  /* DMA Control / Status Register for Channel 6 */
-#define DCSR7           __REG(0x4000001c)  /* DMA Control / Status Register for Channel 7 */
-#define DCSR8           __REG(0x40000020)  /* DMA Control / Status Register for Channel 8 */
-#define DCSR9           __REG(0x40000024)  /* DMA Control / Status Register for Channel 9 */
-#define DCSR10          __REG(0x40000028)  /* DMA Control / Status Register for Channel 10 */
-#define DCSR11          __REG(0x4000002c)  /* DMA Control / Status Register for Channel 11 */
-#define DCSR12          __REG(0x40000030)  /* DMA Control / Status Register for Channel 12 */
-#define DCSR13          __REG(0x40000034)  /* DMA Control / Status Register for Channel 13 */
-#define DCSR14          __REG(0x40000038)  /* DMA Control / Status Register for Channel 14 */
-#define DCSR15          __REG(0x4000003c)  /* DMA Control / Status Register for Channel 15 */
-
-#define DCSR(x)         __REG2(0x40000000, (x) << 2)
-
-#define DCSR_RUN        (1 << 31)       /* Run Bit (read / write) */
-#define DCSR_NODESC     (1 << 30)       /* No-Descriptor Fetch (read / write) */
-#define DCSR_STOPIRQEN  (1 << 29)       /* Stop Interrupt Enable (read / write) */
-#ifdef CONFIG_PXA27x
-#define DCSR_EORIRQEN   (1 << 28)       /* End of Receive Interrupt Enable (R/W) */
-#define DCSR_EORJMPEN   (1 << 27)       /* Jump to next descriptor on EOR */
-#define DCSR_EORSTOPEN  (1 << 26)       /* STOP on an EOR */
-#define DCSR_SETCMPST   (1 << 25)       /* Set Descriptor Compare Status */
-#define DCSR_CLRCMPST   (1 << 24)       /* Clear Descriptor Compare Status */
-#define DCSR_CMPST      (1 << 10)       /* The Descriptor Compare Status */
-#define DCSR_EORINTR    (1 << 9)        /* The end of Receive */
-#endif
-#define DCSR_REQPEND    (1 << 8)        /* Request Pending (read-only) */
-#define DCSR_STOPSTATE  (1 << 3)        /* Stop State (read-only) */
-#define DCSR_ENDINTR    (1 << 2)        /* End Interrupt (read / write) */
-#define DCSR_STARTINTR  (1 << 1)        /* Start Interrupt (read / write) */
-#define DCSR_BUSERR     (1 << 0)        /* Bus Error Interrupt (read / write) */
-
-#define DALGN           __REG(0x400000a0)  /* DMA Alignment Register */
-#define DINT            __REG(0x400000f0)  /* DMA Interrupt Register */
-
-#define DRCMR(n)        (*(((n) < 64) ? \
-                        &__REG2(0x40000100, ((n) & 0x3f) << 2) : \
-                        &__REG2(0x40001100, ((n) & 0x3f) << 2)))
-
-#define DRCMR0          __REG(0x40000100)  /* Request to Channel Map Register for DREQ 0 */
-#define DRCMR1          __REG(0x40000104)  /* Request to Channel Map Register for DREQ 1 */
-#define DRCMR2          __REG(0x40000108)  /* Request to Channel Map Register for I2S receive Request */
-#define DRCMR3          __REG(0x4000010c)  /* Request to Channel Map Register for I2S transmit Request */
-#define DRCMR4          __REG(0x40000110)  /* Request to Channel Map Register for BTUART receive Request */
-#define DRCMR5          __REG(0x40000114)  /* Request to Channel Map Register for BTUART transmit Request. */
-#define DRCMR6          __REG(0x40000118)  /* Request to Channel Map Register for FFUART receive Request */
-#define DRCMR7          __REG(0x4000011c)  /* Request to Channel Map Register for FFUART transmit Request */
-#define DRCMR8          __REG(0x40000120)  /* Request to Channel Map Register for AC97 microphone Request */
-#define DRCMR9          __REG(0x40000124)  /* Request to Channel Map Register for AC97 modem receive Request */
-#define DRCMR10         __REG(0x40000128)  /* Request to Channel Map Register for AC97 modem transmit Request */
-#define DRCMR11         __REG(0x4000012c)  /* Request to Channel Map Register for AC97 audio receive Request */
-#define DRCMR12         __REG(0x40000130)  /* Request to Channel Map Register for AC97 audio transmit Request */
-#define DRCMR13         __REG(0x40000134)  /* Request to Channel Map Register for SSP receive Request */
-#define DRCMR14         __REG(0x40000138)  /* Request to Channel Map Register for SSP transmit Request */
-#define DRCMR15         __REG(0x4000013c)  /* Request to Channel Map Register for SSP2 receive Request */
-#define DRCMR16         __REG(0x40000140)  /* Request to Channel Map Register for SSP2 transmit Request */
-#define DRCMR17         __REG(0x40000144)  /* Request to Channel Map Register for ICP receive Request */
-#define DRCMR18         __REG(0x40000148)  /* Request to Channel Map Register for ICP transmit Request */
-#define DRCMR19         __REG(0x4000014c)  /* Request to Channel Map Register for STUART receive Request */
-#define DRCMR20         __REG(0x40000150)  /* Request to Channel Map Register for STUART transmit Request */
-#define DRCMR21         __REG(0x40000154)  /* Request to Channel Map Register for MMC receive Request */
-#define DRCMR22         __REG(0x40000158)  /* Request to Channel Map Register for MMC transmit Request */
-#define DRCMR23         __REG(0x4000015c)  /* Reserved */
-#define DRCMR24         __REG(0x40000160)  /* Reserved */
-#define DRCMR25         __REG(0x40000164)  /* Request to Channel Map Register for USB endpoint 1 Request */
-#define DRCMR26         __REG(0x40000168)  /* Request to Channel Map Register for USB endpoint 2 Request */
-#define DRCMR27         __REG(0x4000016C)  /* Request to Channel Map Register for USB endpoint 3 Request */
-#define DRCMR28         __REG(0x40000170)  /* Request to Channel Map Register for USB endpoint 4 Request */
-#define DRCMR29         __REG(0x40000174)  /* Reserved */
-#define DRCMR30         __REG(0x40000178)  /* Request to Channel Map Register for USB endpoint 6 Request */
-#define DRCMR31         __REG(0x4000017C)  /* Request to Channel Map Register for USB endpoint 7 Request */
-#define DRCMR32         __REG(0x40000180)  /* Request to Channel Map Register for USB endpoint 8 Request */
-#define DRCMR33         __REG(0x40000184)  /* Request to Channel Map Register for USB endpoint 9 Request */
-#define DRCMR34         __REG(0x40000188)  /* Reserved */
-#define DRCMR35         __REG(0x4000018C)  /* Request to Channel Map Register for USB endpoint 11 Request */
-#define DRCMR36         __REG(0x40000190)  /* Request to Channel Map Register for USB endpoint 12 Request */
-#define DRCMR37         __REG(0x40000194)  /* Request to Channel Map Register for USB endpoint 13 Request */
-#define DRCMR38         __REG(0x40000198)  /* Request to Channel Map Register for USB endpoint 14 Request */
-#define DRCMR39         __REG(0x4000019C)  /* Reserved */
-#define DRCMR66         __REG(0x40001108)  /* Request to Channel Map Register for SSP3 receive Request */
-#define DRCMR67         __REG(0x4000110C)  /* Request to Channel Map Register for SSP3 transmit Request */
-#define DRCMR68         __REG(0x40001110)  /* Request to Channel Map Register for Camera FIFO 0 Request */
-#define DRCMR69         __REG(0x40001114)  /* Request to Channel Map Register for Camera FIFO 1 Request */
-#define DRCMR70         __REG(0x40001118)  /* Request to Channel Map Register for Camera FIFO 2 Request */
-
-#define DRCMRRXSADR     DRCMR2
-#define DRCMRTXSADR     DRCMR3
-#define DRCMRRXBTRBR    DRCMR4
-#define DRCMRTXBTTHR    DRCMR5
-#define DRCMRRXFFRBR    DRCMR6
-#define DRCMRTXFFTHR    DRCMR7
-#define DRCMRRXMCDR     DRCMR8
-#define DRCMRRXMODR     DRCMR9
-#define DRCMRTXMODR     DRCMR10
-#define DRCMRRXPCDR     DRCMR11
-#define DRCMRTXPCDR     DRCMR12
-#define DRCMRRXSSDR     DRCMR13
-#define DRCMRTXSSDR     DRCMR14
-#define DRCMRRXSS2DR   DRCMR15
-#define DRCMRTXSS2DR   DRCMR16
-#define DRCMRRXICDR     DRCMR17
-#define DRCMRTXICDR     DRCMR18
-#define DRCMRRXSTRBR    DRCMR19
-#define DRCMRTXSTTHR    DRCMR20
-#define DRCMRRXMMC      DRCMR21
-#define DRCMRTXMMC      DRCMR22
-#define DRCMRRXSS3DR   DRCMR66
-#define DRCMRTXSS3DR   DRCMR67
-#define DRCMRUDC(x)     DRCMR((x) + 24)
-
-#define DRCMR_MAPVLD    (1 << 7)        /* Map Valid (read / write) */
-#define DRCMR_CHLNUM    0x1f            /* mask for Channel Number (read / write) */
-
-#define DDADR0          __REG(0x40000200)  /* DMA Descriptor Address Register Channel 0 */
-#define DSADR0          __REG(0x40000204)  /* DMA Source Address Register Channel 0 */
-#define DTADR0          __REG(0x40000208)  /* DMA Target Address Register Channel 0 */
-#define DCMD0           __REG(0x4000020c)  /* DMA Command Address Register Channel 0 */
-#define DDADR1          __REG(0x40000210)  /* DMA Descriptor Address Register Channel 1 */
-#define DSADR1          __REG(0x40000214)  /* DMA Source Address Register Channel 1 */
-#define DTADR1          __REG(0x40000218)  /* DMA Target Address Register Channel 1 */
-#define DCMD1           __REG(0x4000021c)  /* DMA Command Address Register Channel 1 */
-#define DDADR2          __REG(0x40000220)  /* DMA Descriptor Address Register Channel 2 */
-#define DSADR2          __REG(0x40000224)  /* DMA Source Address Register Channel 2 */
-#define DTADR2          __REG(0x40000228)  /* DMA Target Address Register Channel 2 */
-#define DCMD2           __REG(0x4000022c)  /* DMA Command Address Register Channel 2 */
-#define DDADR3          __REG(0x40000230)  /* DMA Descriptor Address Register Channel 3 */
-#define DSADR3          __REG(0x40000234)  /* DMA Source Address Register Channel 3 */
-#define DTADR3          __REG(0x40000238)  /* DMA Target Address Register Channel 3 */
-#define DCMD3           __REG(0x4000023c)  /* DMA Command Address Register Channel 3 */
-#define DDADR4          __REG(0x40000240)  /* DMA Descriptor Address Register Channel 4 */
-#define DSADR4          __REG(0x40000244)  /* DMA Source Address Register Channel 4 */
-#define DTADR4          __REG(0x40000248)  /* DMA Target Address Register Channel 4 */
-#define DCMD4           __REG(0x4000024c)  /* DMA Command Address Register Channel 4 */
-#define DDADR5          __REG(0x40000250)  /* DMA Descriptor Address Register Channel 5 */
-#define DSADR5          __REG(0x40000254)  /* DMA Source Address Register Channel 5 */
-#define DTADR5          __REG(0x40000258)  /* DMA Target Address Register Channel 5 */
-#define DCMD5           __REG(0x4000025c)  /* DMA Command Address Register Channel 5 */
-#define DDADR6          __REG(0x40000260)  /* DMA Descriptor Address Register Channel 6 */
-#define DSADR6          __REG(0x40000264)  /* DMA Source Address Register Channel 6 */
-#define DTADR6          __REG(0x40000268)  /* DMA Target Address Register Channel 6 */
-#define DCMD6           __REG(0x4000026c)  /* DMA Command Address Register Channel 6 */
-#define DDADR7          __REG(0x40000270)  /* DMA Descriptor Address Register Channel 7 */
-#define DSADR7          __REG(0x40000274)  /* DMA Source Address Register Channel 7 */
-#define DTADR7          __REG(0x40000278)  /* DMA Target Address Register Channel 7 */
-#define DCMD7           __REG(0x4000027c)  /* DMA Command Address Register Channel 7 */
-#define DDADR8          __REG(0x40000280)  /* DMA Descriptor Address Register Channel 8 */
-#define DSADR8          __REG(0x40000284)  /* DMA Source Address Register Channel 8 */
-#define DTADR8          __REG(0x40000288)  /* DMA Target Address Register Channel 8 */
-#define DCMD8           __REG(0x4000028c)  /* DMA Command Address Register Channel 8 */
-#define DDADR9          __REG(0x40000290)  /* DMA Descriptor Address Register Channel 9 */
-#define DSADR9          __REG(0x40000294)  /* DMA Source Address Register Channel 9 */
-#define DTADR9          __REG(0x40000298)  /* DMA Target Address Register Channel 9 */
-#define DCMD9           __REG(0x4000029c)  /* DMA Command Address Register Channel 9 */
-#define DDADR10         __REG(0x400002a0)  /* DMA Descriptor Address Register Channel 10 */
-#define DSADR10         __REG(0x400002a4)  /* DMA Source Address Register Channel 10 */
-#define DTADR10         __REG(0x400002a8)  /* DMA Target Address Register Channel 10 */
-#define DCMD10          __REG(0x400002ac)  /* DMA Command Address Register Channel 10 */
-#define DDADR11         __REG(0x400002b0)  /* DMA Descriptor Address Register Channel 11 */
-#define DSADR11         __REG(0x400002b4)  /* DMA Source Address Register Channel 11 */
-#define DTADR11         __REG(0x400002b8)  /* DMA Target Address Register Channel 11 */
-#define DCMD11          __REG(0x400002bc)  /* DMA Command Address Register Channel 11 */
-#define DDADR12         __REG(0x400002c0)  /* DMA Descriptor Address Register Channel 12 */
-#define DSADR12         __REG(0x400002c4)  /* DMA Source Address Register Channel 12 */
-#define DTADR12         __REG(0x400002c8)  /* DMA Target Address Register Channel 12 */
-#define DCMD12          __REG(0x400002cc)  /* DMA Command Address Register Channel 12 */
-#define DDADR13         __REG(0x400002d0)  /* DMA Descriptor Address Register Channel 13 */
-#define DSADR13         __REG(0x400002d4)  /* DMA Source Address Register Channel 13 */
-#define DTADR13         __REG(0x400002d8)  /* DMA Target Address Register Channel 13 */
-#define DCMD13          __REG(0x400002dc)  /* DMA Command Address Register Channel 13 */
-#define DDADR14         __REG(0x400002e0)  /* DMA Descriptor Address Register Channel 14 */
-#define DSADR14         __REG(0x400002e4)  /* DMA Source Address Register Channel 14 */
-#define DTADR14         __REG(0x400002e8)  /* DMA Target Address Register Channel 14 */
-#define DCMD14          __REG(0x400002ec)  /* DMA Command Address Register Channel 14 */
-#define DDADR15         __REG(0x400002f0)  /* DMA Descriptor Address Register Channel 15 */
-#define DSADR15         __REG(0x400002f4)  /* DMA Source Address Register Channel 15 */
-#define DTADR15         __REG(0x400002f8)  /* DMA Target Address Register Channel 15 */
-#define DCMD15          __REG(0x400002fc)  /* DMA Command Address Register Channel 15 */
-
-#define DDADR(x)        __REG2(0x40000200, (x) << 4)
-#define DSADR(x)        __REG2(0x40000204, (x) << 4)
-#define DTADR(x)        __REG2(0x40000208, (x) << 4)
-#define DCMD(x)         __REG2(0x4000020c, (x) << 4)
-
-#define DDADR_DESCADDR  0xfffffff0      /* Address of next descriptor (mask) */
-#define DDADR_STOP      (1 << 0)        /* Stop (read / write) */
-
-#define DCMD_INCSRCADDR (1 << 31)       /* Source Address Increment Setting. */
-#define DCMD_INCTRGADDR (1 << 30)       /* Target Address Increment Setting. */
-#define DCMD_FLOWSRC    (1 << 29)       /* Flow Control by the source. */
-#define DCMD_FLOWTRG    (1 << 28)       /* Flow Control by the target. */
-#define DCMD_STARTIRQEN (1 << 22)       /* Start Interrupt Enable */
-#define DCMD_ENDIRQEN   (1 << 21)       /* End Interrupt Enable */
-#define DCMD_ENDIAN     (1 << 18)       /* Device Endian-ness. */
-#define DCMD_BURST8     (1 << 16)       /* 8 byte burst */
-#define DCMD_BURST16    (2 << 16)       /* 16 byte burst */
-#define DCMD_BURST32    (3 << 16)       /* 32 byte burst */
-#define DCMD_WIDTH1     (1 << 14)       /* 1 byte width */
-#define DCMD_WIDTH2     (2 << 14)       /* 2 byte width (HalfWord) */
-#define DCMD_WIDTH4     (3 << 14)       /* 4 byte width (Word) */
-#define DCMD_LENGTH     0x01fff         /* length mask (max = 8K - 1) */
-
-
-/*
- * UARTs
- */
-
-/* Full Function UART (FFUART) */
-#define FFUART          FFRBR
-#define FFRBR           __REG(0x40100000)  /* Receive Buffer Register (read only) */
-#define FFTHR           __REG(0x40100000)  /* Transmit Holding Register (write only) */
-#define FFIER           __REG(0x40100004)  /* Interrupt Enable Register (read/write) */
-#define FFIIR           __REG(0x40100008)  /* Interrupt ID Register (read only) */
-#define FFFCR           __REG(0x40100008)  /* FIFO Control Register (write only) */
-#define FFLCR           __REG(0x4010000C)  /* Line Control Register (read/write) */
-#define FFMCR           __REG(0x40100010)  /* Modem Control Register (read/write) */
-#define FFLSR           __REG(0x40100014)  /* Line Status Register (read only) */
-#define FFMSR           __REG(0x40100018)  /* Modem Status Register (read only) */
-#define FFSPR           __REG(0x4010001C)  /* Scratch Pad Register (read/write) */
-#define FFISR           __REG(0x40100020)  /* Infrared Selection Register (read/write) */
-#define FFDLL           __REG(0x40100000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
-#define FFDLH           __REG(0x40100004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
-
-/* Bluetooth UART (BTUART) */
-#define BTUART          BTRBR
-#define BTRBR           __REG(0x40200000)  /* Receive Buffer Register (read only) */
-#define BTTHR           __REG(0x40200000)  /* Transmit Holding Register (write only) */
-#define BTIER           __REG(0x40200004)  /* Interrupt Enable Register (read/write) */
-#define BTIIR           __REG(0x40200008)  /* Interrupt ID Register (read only) */
-#define BTFCR           __REG(0x40200008)  /* FIFO Control Register (write only) */
-#define BTLCR           __REG(0x4020000C)  /* Line Control Register (read/write) */
-#define BTMCR           __REG(0x40200010)  /* Modem Control Register (read/write) */
-#define BTLSR           __REG(0x40200014)  /* Line Status Register (read only) */
-#define BTMSR           __REG(0x40200018)  /* Modem Status Register (read only) */
-#define BTSPR           __REG(0x4020001C)  /* Scratch Pad Register (read/write) */
-#define BTISR           __REG(0x40200020)  /* Infrared Selection Register (read/write) */
-#define BTDLL           __REG(0x40200000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
-#define BTDLH           __REG(0x40200004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
-
-/* Standard UART (STUART) */
-#define STUART          STRBR
-#define STRBR           __REG(0x40700000)  /* Receive Buffer Register (read only) */
-#define STTHR           __REG(0x40700000)  /* Transmit Holding Register (write only) */
-#define STIER           __REG(0x40700004)  /* Interrupt Enable Register (read/write) */
-#define STIIR           __REG(0x40700008)  /* Interrupt ID Register (read only) */
-#define STFCR           __REG(0x40700008)  /* FIFO Control Register (write only) */
-#define STLCR           __REG(0x4070000C)  /* Line Control Register (read/write) */
-#define STMCR           __REG(0x40700010)  /* Modem Control Register (read/write) */
-#define STLSR           __REG(0x40700014)  /* Line Status Register (read only) */
-#define STMSR           __REG(0x40700018)  /* Reserved */
-#define STSPR           __REG(0x4070001C)  /* Scratch Pad Register (read/write) */
-#define STISR           __REG(0x40700020)  /* Infrared Selection Register (read/write) */
-#define STDLL           __REG(0x40700000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
-#define STDLH           __REG(0x40700004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
-
-/* Hardware UART (HWUART) */
-#define HWUART          HWRBR
-#define HWRBR           __REG(0x41600000)  /* Receive Buffer Register (read only) */
-#define HWTHR           __REG(0x41600000)  /* Transmit Holding Register (write only) */
-#define HWIER           __REG(0x41600004)  /* Interrupt Enable Register (read/write) */
-#define HWIIR           __REG(0x41600008)  /* Interrupt ID Register (read only) */
-#define HWFCR           __REG(0x41600008)  /* FIFO Control Register (write only) */
-#define HWLCR           __REG(0x4160000C)  /* Line Control Register (read/write) */
-#define HWMCR           __REG(0x41600010)  /* Modem Control Register (read/write) */
-#define HWLSR           __REG(0x41600014)  /* Line Status Register (read only) */
-#define HWMSR           __REG(0x41600018)  /* Modem Status Register (read only) */
-#define HWSPR           __REG(0x4160001C)  /* Scratch Pad Register (read/write) */
-#define HWISR           __REG(0x41600020)  /* Infrared Selection Register (read/write) */
-#define HWFOR           __REG(0x41600024)  /* Receive FIFO Occupancy Register (read only) */
-#define HWABR           __REG(0x41600028)  /* Auto-Baud Control Register (read/write) */
-#define HWACR           __REG(0x4160002C)  /* Auto-Baud Count Register (read only) */
-#define HWDLL           __REG(0x41600000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
-#define HWDLH           __REG(0x41600004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
-
-#define IER_DMAE        (1 << 7)        /* DMA Requests Enable */
-#define IER_UUE         (1 << 6)        /* UART Unit Enable */
-#define IER_NRZE        (1 << 5)        /* NRZ coding Enable */
-#define IER_RTIOE       (1 << 4)        /* Receiver Time Out Interrupt Enable */
-#define IER_MIE         (1 << 3)        /* Modem Interrupt Enable */
-#define IER_RLSE        (1 << 2)        /* Receiver Line Status Interrupt Enable */
-#define IER_TIE         (1 << 1)        /* Transmit Data request Interrupt Enable */
-#define IER_RAVIE       (1 << 0)        /* Receiver Data Available Interrupt Enable */
-
-#define IIR_FIFOES1     (1 << 7)        /* FIFO Mode Enable Status */
-#define IIR_FIFOES0     (1 << 6)        /* FIFO Mode Enable Status */
-#define IIR_TOD         (1 << 3)        /* Time Out Detected */
-#define IIR_IID2        (1 << 2)        /* Interrupt Source Encoded */
-#define IIR_IID1        (1 << 1)        /* Interrupt Source Encoded */
-#define IIR_IP          (1 << 0)        /* Interrupt Pending (active low) */
-
-#define FCR_ITL2        (1 << 7)        /* Interrupt Trigger Level */
-#define FCR_ITL1        (1 << 6)        /* Interrupt Trigger Level */
-#define FCR_RESETTF     (1 << 2)        /* Reset Transmitter FIFO */
-#define FCR_RESETRF     (1 << 1)        /* Reset Receiver FIFO */
-#define FCR_TRFIFOE     (1 << 0)        /* Transmit and Receive FIFO Enable */
-#define FCR_ITL_1       (0)
-#define FCR_ITL_8       (FCR_ITL1)
-#define FCR_ITL_16      (FCR_ITL2)
-#define FCR_ITL_32      (FCR_ITL2|FCR_ITL1)
-
-#define LCR_DLAB        (1 << 7)        /* Divisor Latch Access Bit */
-#define LCR_SB          (1 << 6)        /* Set Break */
-#define LCR_STKYP       (1 << 5)        /* Sticky Parity */
-#define LCR_EPS         (1 << 4)        /* Even Parity Select */
-#define LCR_PEN         (1 << 3)        /* Parity Enable */
-#define LCR_STB         (1 << 2)        /* Stop Bit */
-#define LCR_WLS1        (1 << 1)        /* Word Length Select */
-#define LCR_WLS0        (1 << 0)        /* Word Length Select */
-
-#define LSR_FIFOE       (1 << 7)        /* FIFO Error Status */
-#define LSR_TEMT        (1 << 6)        /* Transmitter Empty */
-#define LSR_TDRQ        (1 << 5)        /* Transmit Data Request */
-#define LSR_BI          (1 << 4)        /* Break Interrupt */
-#define LSR_FE          (1 << 3)        /* Framing Error */
-#define LSR_PE          (1 << 2)        /* Parity Error */
-#define LSR_OE          (1 << 1)        /* Overrun Error */
-#define LSR_DR          (1 << 0)        /* Data Ready */
-
-#define MCR_LOOP        (1 << 4)
-#define MCR_OUT2        (1 << 3)        /* force MSR_DCD in loopback mode */
-#define MCR_OUT1        (1 << 2)        /* force MSR_RI in loopback mode */
-#define MCR_RTS         (1 << 1)        /* Request to Send */
-#define MCR_DTR         (1 << 0)        /* Data Terminal Ready */
-
-#define MSR_DCD         (1 << 7)        /* Data Carrier Detect */
-#define MSR_RI          (1 << 6)        /* Ring Indicator */
-#define MSR_DSR         (1 << 5)        /* Data Set Ready */
-#define MSR_CTS         (1 << 4)        /* Clear To Send */
-#define MSR_DDCD        (1 << 3)        /* Delta Data Carrier Detect */
-#define MSR_TERI        (1 << 2)        /* Trailing Edge Ring Indicator */
-#define MSR_DDSR        (1 << 1)        /* Delta Data Set Ready */
-#define MSR_DCTS        (1 << 0)        /* Delta Clear To Send */
-
-/*
- * IrSR (Infrared Selection Register)
- */
-#define STISR_RXPL      (1 << 4)        /* Receive Data Polarity */
-#define STISR_TXPL      (1 << 3)        /* Transmit Data Polarity */
-#define STISR_XMODE     (1 << 2)        /* Transmit Pulse Width Select */
-#define STISR_RCVEIR    (1 << 1)        /* Receiver SIR Enable */
-#define STISR_XMITIR    (1 << 0)        /* Transmitter SIR Enable */
-
-
-/*
- * I2C registers
- */
-
-#define IBMR            __REG(0x40301680)  /* I2C Bus Monitor Register - IBMR */
-#define IDBR            __REG(0x40301688)  /* I2C Data Buffer Register - IDBR */
-#define ICR             __REG(0x40301690)  /* I2C Control Register - ICR */
-#define ISR             __REG(0x40301698)  /* I2C Status Register - ISR */
-#define ISAR            __REG(0x403016A0)  /* I2C Slave Address Register - ISAR */
-
-#define PWRIBMR    __REG(0x40f00180)  /* Power I2C Bus Monitor Register-IBMR */
-#define PWRIDBR    __REG(0x40f00188)  /* Power I2C Data Buffer Register-IDBR */
-#define PWRICR __REG(0x40f00190)  /* Power I2C Control Register - ICR */
-#define PWRISR __REG(0x40f00198)  /* Power I2C Status Register - ISR */
-#define PWRISAR    __REG(0x40f001A0)  /*Power I2C Slave Address Register-ISAR */
-
-#define ICR_START       (1 << 0)           /* start bit */
-#define ICR_STOP        (1 << 1)           /* stop bit */
-#define ICR_ACKNAK      (1 << 2)           /* send ACK(0) or NAK(1) */
-#define ICR_TB          (1 << 3)           /* transfer byte bit */
-#define ICR_MA          (1 << 4)           /* master abort */
-#define ICR_SCLE        (1 << 5)           /* master clock enable */
-#define ICR_IUE         (1 << 6)           /* unit enable */
-#define ICR_GCD         (1 << 7)           /* general call disable */
-#define ICR_ITEIE       (1 << 8)           /* enable tx interrupts */
-#define ICR_IRFIE       (1 << 9)           /* enable rx interrupts */
-#define ICR_BEIE        (1 << 10)          /* enable bus error ints */
-#define ICR_SSDIE       (1 << 11)          /* slave STOP detected int enable */
-#define ICR_ALDIE       (1 << 12)          /* enable arbitration interrupt */
-#define ICR_SADIE       (1 << 13)          /* slave address detected int enable */
-#define ICR_UR          (1 << 14)          /* unit reset */
-
-#define ISR_RWM         (1 << 0)           /* read/write mode */
-#define ISR_ACKNAK      (1 << 1)           /* ack/nak status */
-#define ISR_UB          (1 << 2)           /* unit busy */
-#define ISR_IBB         (1 << 3)           /* bus busy */
-#define ISR_SSD         (1 << 4)           /* slave stop detected */
-#define ISR_ALD         (1 << 5)           /* arbitration loss detected */
-#define ISR_ITE         (1 << 6)           /* tx buffer empty */
-#define ISR_IRF         (1 << 7)           /* rx buffer full */
-#define ISR_GCAD        (1 << 8)           /* general call address detected */
-#define ISR_SAD         (1 << 9)           /* slave address detected */
-#define ISR_BED         (1 << 10)          /* bus error no ACK/NAK */
-
-
-/*
- * Serial Audio Controller
- */
-
-#define SACR0           __REG(0x40400000)  /* Global Control Register */
-#define SACR1           __REG(0x40400004)  /* Serial Audio I 2 S/MSB-Justified Control Register */
-#define SASR0           __REG(0x4040000C)  /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
-#define SAIMR           __REG(0x40400014)  /* Serial Audio Interrupt Mask Register */
-#define SAICR           __REG(0x40400018)  /* Serial Audio Interrupt Clear Register */
-#define SADIV           __REG(0x40400060)  /* Audio Clock Divider Register. */
-#define SADR            __REG(0x40400080)  /* Serial Audio Data Register (TX and RX FIFO access Register). */
-
-#define SACR0_RFTH(x)   ((x) << 12)     /* Rx FIFO Interrupt or DMA Trigger Threshold */
-#define SACR0_TFTH(x)   ((x) << 8)      /* Tx FIFO Interrupt or DMA Trigger Threshold */
-#define SACR0_STRF      (1 << 5)        /* FIFO Select for EFWR Special Function */
-#define SACR0_EFWR      (1 << 4)        /* Enable EFWR Function  */
-#define SACR0_RST       (1 << 3)        /* FIFO, i2s Register Reset */
-#define SACR0_BCKD      (1 << 2)        /* Bit Clock Direction */
-#define SACR0_ENB       (1 << 0)        /* Enable I2S Link */
-#define SACR1_ENLBF     (1 << 5)        /* Enable Loopback */
-#define SACR1_DRPL      (1 << 4)        /* Disable Replaying Function */
-#define SACR1_DREC      (1 << 3)        /* Disable Recording Function */
-#define SACR1_AMSL      (1 << 0)        /* Specify Alternate Mode */
-
-#define SASR0_I2SOFF    (1 << 7)        /* Controller Status */
-#define SASR0_ROR       (1 << 6)        /* Rx FIFO Overrun */
-#define SASR0_TUR       (1 << 5)        /* Tx FIFO Underrun */
-#define SASR0_RFS       (1 << 4)        /* Rx FIFO Service Request */
-#define SASR0_TFS       (1 << 3)        /* Tx FIFO Service Request */
-#define SASR0_BSY       (1 << 2)        /* I2S Busy */
-#define SASR0_RNE       (1 << 1)        /* Rx FIFO Not Empty */
-#define SASR0_TNF       (1 << 0)        /* Tx FIFO Not Empty */
-
-#define SAICR_ROR       (1 << 6)        /* Clear Rx FIFO Overrun Interrupt */
-#define SAICR_TUR       (1 << 5)        /* Clear Tx FIFO Underrun Interrupt */
-
-#define SAIMR_ROR       (1 << 6)        /* Enable Rx FIFO Overrun Condition Interrupt */
-#define SAIMR_TUR       (1 << 5)        /* Enable Tx FIFO Underrun Condition Interrupt */
-#define SAIMR_RFS       (1 << 4)        /* Enable Rx FIFO Service Interrupt */
-#define SAIMR_TFS       (1 << 3)        /* Enable Tx FIFO Service Interrupt */
-
-/*
- * AC97 Controller registers
- */
-
-#define POCR            __REG(0x40500000)  /* PCM Out Control Register */
-#define POCR_FEIE       (1 << 3)        /* FIFO Error Interrupt Enable */
-#define POCR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
-
-#define PICR            __REG(0x40500004)  /* PCM In Control Register */
-#define PICR_FEIE       (1 << 3)        /* FIFO Error Interrupt Enable */
-#define PICR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
-
-#define MCCR            __REG(0x40500008)  /* Mic In Control Register */
-#define MCCR_FEIE       (1 << 3)        /* FIFO Error Interrupt Enable */
-#define MCCR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
-
-#define GCR             __REG(0x4050000C)  /* Global Control Register */
-#ifdef CONFIG_PXA3xx
-#define GCR_CLKBPB      (1 << 31)       /* Internal clock enable */
-#endif
-#define GCR_nDMAEN      (1 << 24)       /* non DMA Enable */
-#define GCR_CDONE_IE    (1 << 19)       /* Command Done Interrupt Enable */
-#define GCR_SDONE_IE    (1 << 18)       /* Status Done Interrupt Enable */
-#define GCR_SECRDY_IEN  (1 << 9)        /* Secondary Ready Interrupt Enable */
-#define GCR_PRIRDY_IEN  (1 << 8)        /* Primary Ready Interrupt Enable */
-#define GCR_SECRES_IEN  (1 << 5)        /* Secondary Resume Interrupt Enable */
-#define GCR_PRIRES_IEN  (1 << 4)        /* Primary Resume Interrupt Enable */
-#define GCR_ACLINK_OFF  (1 << 3)        /* AC-link Shut Off */
-#define GCR_WARM_RST    (1 << 2)        /* AC97 Warm Reset */
-#define GCR_COLD_RST    (1 << 1)        /* AC'97 Cold Reset (0 = active) */
-#define GCR_GIE         (1 << 0)        /* Codec GPI Interrupt Enable */
-
-#define POSR            __REG(0x40500010)  /* PCM Out Status Register */
-#define POSR_FIFOE      (1 << 4)        /* FIFO error */
-#define POSR_FSR        (1 << 2)        /* FIFO Service Request */
-
-#define PISR            __REG(0x40500014)  /* PCM In Status Register */
-#define PISR_FIFOE      (1 << 4)        /* FIFO error */
-#define PISR_EOC        (1 << 3)        /* DMA End-of-Chain (exclusive clear) */
-#define PISR_FSR        (1 << 2)        /* FIFO Service Request */
-
-#define MCSR            __REG(0x40500018)  /* Mic In Status Register */
-#define MCSR_FIFOE      (1 << 4)        /* FIFO error */
-#define MCSR_EOC        (1 << 3)        /* DMA End-of-Chain (exclusive clear) */
-#define MCSR_FSR        (1 << 2)        /* FIFO Service Request */
-
-#define GSR             __REG(0x4050001C)  /* Global Status Register */
-#define GSR_CDONE       (1 << 19)       /* Command Done */
-#define GSR_SDONE       (1 << 18)       /* Status Done */
-#define GSR_RDCS        (1 << 15)       /* Read Completion Status */
-#define GSR_BIT3SLT12   (1 << 14)       /* Bit 3 of slot 12 */
-#define GSR_BIT2SLT12   (1 << 13)       /* Bit 2 of slot 12 */
-#define GSR_BIT1SLT12   (1 << 12)       /* Bit 1 of slot 12 */
-#define GSR_SECRES      (1 << 11)       /* Secondary Resume Interrupt */
-#define GSR_PRIRES      (1 << 10)       /* Primary Resume Interrupt */
-#define GSR_SCR         (1 << 9)        /* Secondary Codec Ready */
-#define GSR_PCR         (1 << 8)        /*  Primary Codec Ready */
-#define GSR_MCINT       (1 << 7)        /* Mic In Interrupt */
-#define GSR_POINT       (1 << 6)        /* PCM Out Interrupt */
-#define GSR_PIINT       (1 << 5)        /* PCM In Interrupt */
-#define GSR_ACOFFD      (1 << 3)        /* AC-link Shut Off Done */
-#define GSR_MOINT       (1 << 2)        /* Modem Out Interrupt */
-#define GSR_MIINT       (1 << 1)        /* Modem In Interrupt */
-#define GSR_GSCI        (1 << 0)        /* Codec GPI Status Change Interrupt */
-
-#define CAR             __REG(0x40500020)  /* CODEC Access Register */
-#define CAR_CAIP        (1 << 0)        /* Codec Access In Progress */
-
-#define PCDR            __REG(0x40500040)  /* PCM FIFO Data Register */
-#define MCDR            __REG(0x40500060)  /* Mic-in FIFO Data Register */
-
-#define MOCR            __REG(0x40500100)  /* Modem Out Control Register */
-#define MOCR_FEIE       (1 << 3)        /* FIFO Error */
-#define MOCR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
-
-#define MICR            __REG(0x40500108)  /* Modem In Control Register */
-#define MICR_FEIE       (1 << 3)        /* FIFO Error */
-#define MICR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
-
-#define MOSR            __REG(0x40500110)  /* Modem Out Status Register */
-#define MOSR_FIFOE      (1 << 4)        /* FIFO error */
-#define MOSR_FSR        (1 << 2)        /* FIFO Service Request */
-
-#define MISR            __REG(0x40500118)  /* Modem In Status Register */
-#define MISR_FIFOE      (1 << 4)        /* FIFO error */
-#define MISR_EOC        (1 << 3)        /* DMA End-of-Chain (exclusive clear) */
-#define MISR_FSR        (1 << 2)        /* FIFO Service Request */
-
-#define MODR            __REG(0x40500140)  /* Modem FIFO Data Register */
-
-#define PAC_REG_BASE    __REG(0x40500200)  /* Primary Audio Codec */
-#define SAC_REG_BASE    __REG(0x40500300)  /* Secondary Audio Codec */
-#define PMC_REG_BASE    __REG(0x40500400)  /* Primary Modem Codec */
-#define SMC_REG_BASE    __REG(0x40500500)  /* Secondary Modem Codec */
-
-
-/*
- * Fast Infrared Communication Port
- */
-
-#define FICP            __REG(0x40800000)  /* Start of FICP area */
-#define ICCR0           __REG(0x40800000)  /* ICP Control Register 0 */
-#define ICCR1           __REG(0x40800004)  /* ICP Control Register 1 */
-#define ICCR2           __REG(0x40800008)  /* ICP Control Register 2 */
-#define ICDR            __REG(0x4080000c)  /* ICP Data Register */
-#define ICSR0           __REG(0x40800014)  /* ICP Status Register 0 */
-#define ICSR1           __REG(0x40800018)  /* ICP Status Register 1 */
-
-#define ICCR0_AME       (1 << 7)        /* Address match enable */
-#define ICCR0_TIE       (1 << 6)        /* Transmit FIFO interrupt enable */
-#define ICCR0_RIE       (1 << 5)        /* Recieve FIFO interrupt enable */
-#define ICCR0_RXE       (1 << 4)        /* Receive enable */
-#define ICCR0_TXE       (1 << 3)        /* Transmit enable */
-#define ICCR0_TUS       (1 << 2)        /* Transmit FIFO underrun select */
-#define ICCR0_LBM       (1 << 1)        /* Loopback mode */
-#define ICCR0_ITR       (1 << 0)        /* IrDA transmission */
-
-#define ICCR2_RXP       (1 << 3)        /* Receive Pin Polarity select */
-#define ICCR2_TXP       (1 << 2)        /* Transmit Pin Polarity select */
-#define ICCR2_TRIG      (3 << 0)        /* Receive FIFO Trigger threshold */
-#define ICCR2_TRIG_8    (0 << 0)        /*      >= 8 bytes */
-#define ICCR2_TRIG_16   (1 << 0)        /*      >= 16 bytes */
-#define ICCR2_TRIG_32   (2 << 0)        /*      >= 32 bytes */
-
-#ifdef CONFIG_PXA27x
-#define ICSR0_EOC       (1 << 6)        /* DMA End of Descriptor Chain */
-#endif
-#define ICSR0_FRE       (1 << 5)        /* Framing error */
-#define ICSR0_RFS       (1 << 4)        /* Receive FIFO service request */
-#define ICSR0_TFS       (1 << 3)        /* Transnit FIFO service request */
-#define ICSR0_RAB       (1 << 2)        /* Receiver abort */
-#define ICSR0_TUR       (1 << 1)        /* Trunsmit FIFO underun */
-#define ICSR0_EIF       (1 << 0)        /* End/Error in FIFO */
-
-#define ICSR1_ROR       (1 << 6)        /* Receiver FIFO underrun  */
-#define ICSR1_CRE       (1 << 5)        /* CRC error */
-#define ICSR1_EOF       (1 << 4)        /* End of frame */
-#define ICSR1_TNF       (1 << 3)        /* Transmit FIFO not full */
-#define ICSR1_RNE       (1 << 2)        /* Receive FIFO not empty */
-#define ICSR1_TBY       (1 << 1)        /* Tramsmiter busy flag */
-#define ICSR1_RSY       (1 << 0)        /* Recevier synchronized flag */
-
-
-/*
- * Real Time Clock
- */
-
-#define RCNR            __REG(0x40900000)  /* RTC Count Register */
-#define RTAR            __REG(0x40900004)  /* RTC Alarm Register */
-#define RTSR            __REG(0x40900008)  /* RTC Status Register */
-#define RTTR            __REG(0x4090000C)  /* RTC Timer Trim Register */
-#define PIAR            __REG(0x40900038)  /* Periodic Interrupt Alarm Register */
-
-#define RTSR_PICE       (1 << 15)       /* Periodic interrupt count enable */
-#define RTSR_PIALE      (1 << 14)       /* Periodic interrupt Alarm enable */
-#define RTSR_HZE        (1 << 3)        /* HZ interrupt enable */
-#define RTSR_ALE        (1 << 2)        /* RTC alarm interrupt enable */
-#define RTSR_HZ         (1 << 1)        /* HZ rising-edge detected */
-#define RTSR_AL         (1 << 0)        /* RTC alarm detected */
-
-
-/*
- * OS Timer & Match Registers
- */
-
-#define OSMR0           __REG(0x40A00000)  /* */
-#define OSMR1           __REG(0x40A00004)  /* */
-#define OSMR2           __REG(0x40A00008)  /* */
-#define OSMR3           __REG(0x40A0000C)  /* */
-#define OSMR4           __REG(0x40A00080)  /* */
-#define OSCR            __REG(0x40A00010)  /* OS Timer Counter Register */
-#define OSCR4           __REG(0x40A00040)  /* OS Timer Counter Register */
-#define OMCR4           __REG(0x40A000C0)  /* */
-#define OSSR            __REG(0x40A00014)  /* OS Timer Status Register */
-#define OWER            __REG(0x40A00018)  /* OS Timer Watchdog Enable Register */
-#define OIER            __REG(0x40A0001C)  /* OS Timer Interrupt Enable Register */
-
-#define OSSR_M3         (1 << 3)        /* Match status channel 3 */
-#define OSSR_M2         (1 << 2)        /* Match status channel 2 */
-#define OSSR_M1         (1 << 1)        /* Match status channel 1 */
-#define OSSR_M0         (1 << 0)        /* Match status channel 0 */
-
-#define OWER_WME        (1 << 0)        /* Watchdog Match Enable */
-
-#define OIER_E3         (1 << 3)        /* Interrupt enable channel 3 */
-#define OIER_E2         (1 << 2)        /* Interrupt enable channel 2 */
-#define OIER_E1         (1 << 1)        /* Interrupt enable channel 1 */
-#define OIER_E0         (1 << 0)        /* Interrupt enable channel 0 */
-
-
-/*
- * Pulse Width Modulator
- */
-
-#define PWM_CTRL0       __REG(0x40B00000)  /* PWM 0 Control Register */
-#define PWM_PWDUTY0     __REG(0x40B00004)  /* PWM 0 Duty Cycle Register */
-#define PWM_PERVAL0     __REG(0x40B00008)  /* PWM 0 Period Control Register */
-
-#define PWM_CTRL1       __REG(0x40C00000)  /* PWM 1Control Register */
-#define PWM_PWDUTY1     __REG(0x40C00004)  /* PWM 1 Duty Cycle Register */
-#define PWM_PERVAL1     __REG(0x40C00008)  /* PWM 1 Period Control Register */
-
-
-/*
- * Interrupt Controller
- */
-
-#define ICIP            __REG(0x40D00000)  /* Interrupt Controller IRQ Pending Register */
-#define ICMR            __REG(0x40D00004)  /* Interrupt Controller Mask Register */
-#define ICLR            __REG(0x40D00008)  /* Interrupt Controller Level Register */
-#define ICFP            __REG(0x40D0000C)  /* Interrupt Controller FIQ Pending Register */
-#define ICPR            __REG(0x40D00010)  /* Interrupt Controller Pending Register */
-#define ICCR            __REG(0x40D00014)  /* Interrupt Controller Control Register */
-
-#define ICIP2           __REG(0x40D0009C)  /* Interrupt Controller IRQ Pending Register 2 */
-#define ICMR2           __REG(0x40D000A0)  /* Interrupt Controller Mask Register 2 */
-#define ICLR2           __REG(0x40D000A4)  /* Interrupt Controller Level Register 2 */
-#define ICFP2           __REG(0x40D000A8)  /* Interrupt Controller FIQ Pending Register 2 */
-#define ICPR2           __REG(0x40D000AC)  /* Interrupt Controller Pending Register 2 */
-
-/*
- * General Purpose I/O
- */
-
-#define GPIO0_BASE      ((void __iomem *)io_p2v(0x40E00000))
-#define GPIO1_BASE      ((void __iomem *)io_p2v(0x40E00004))
-#define GPIO2_BASE      ((void __iomem *)io_p2v(0x40E00008))
-#define GPIO3_BASE      ((void __iomem *)io_p2v(0x40E00100))
-
-#define GPLR_OFFSET     0x00
-#define GPDR_OFFSET     0x0C
-#define GPSR_OFFSET     0x18
-#define GPCR_OFFSET     0x24
-#define GRER_OFFSET     0x30
-#define GFER_OFFSET     0x3C
-#define GEDR_OFFSET     0x48
-
-#define GPLR0           __REG(0x40E00000)  /* GPIO Pin-Level Register GPIO<31:0> */
-#define GPLR1           __REG(0x40E00004)  /* GPIO Pin-Level Register GPIO<63:32> */
-#define GPLR2           __REG(0x40E00008)  /* GPIO Pin-Level Register GPIO<80:64> */
-
-#define GPDR0           __REG(0x40E0000C)  /* GPIO Pin Direction Register GPIO<31:0> */
-#define GPDR1           __REG(0x40E00010)  /* GPIO Pin Direction Register GPIO<63:32> */
-#define GPDR2           __REG(0x40E00014)  /* GPIO Pin Direction Register GPIO<80:64> */
-
-#define GPSR0           __REG(0x40E00018)  /* GPIO Pin Output Set Register GPIO<31:0> */
-#define GPSR1           __REG(0x40E0001C)  /* GPIO Pin Output Set Register GPIO<63:32> */
-#define GPSR2           __REG(0x40E00020)  /* GPIO Pin Output Set Register GPIO<80:64> */
-
-#define GPCR0           __REG(0x40E00024)  /* GPIO Pin Output Clear Register GPIO<31:0> */
-#define GPCR1           __REG(0x40E00028)  /* GPIO Pin Output Clear Register GPIO <63:32> */
-#define GPCR2           __REG(0x40E0002C)  /* GPIO Pin Output Clear Register GPIO <80:64> */
-
-#define GRER0           __REG(0x40E00030)  /* GPIO Rising-Edge Detect Register GPIO<31:0> */
-#define GRER1           __REG(0x40E00034)  /* GPIO Rising-Edge Detect Register GPIO<63:32> */
-#define GRER2           __REG(0x40E00038)  /* GPIO Rising-Edge Detect Register GPIO<80:64> */
-
-#define GFER0           __REG(0x40E0003C)  /* GPIO Falling-Edge Detect Register GPIO<31:0> */
-#define GFER1           __REG(0x40E00040)  /* GPIO Falling-Edge Detect Register GPIO<63:32> */
-#define GFER2           __REG(0x40E00044)  /* GPIO Falling-Edge Detect Register GPIO<80:64> */
-
-#define GEDR0           __REG(0x40E00048)  /* GPIO Edge Detect Status Register GPIO<31:0> */
-#define GEDR1           __REG(0x40E0004C)  /* GPIO Edge Detect Status Register GPIO<63:32> */
-#define GEDR2           __REG(0x40E00050)  /* GPIO Edge Detect Status Register GPIO<80:64> */
-
-#define GAFR0_L         __REG(0x40E00054)  /* GPIO Alternate Function Select Register GPIO<15:0> */
-#define GAFR0_U         __REG(0x40E00058)  /* GPIO Alternate Function Select Register GPIO<31:16> */
-#define GAFR1_L         __REG(0x40E0005C)  /* GPIO Alternate Function Select Register GPIO<47:32> */
-#define GAFR1_U         __REG(0x40E00060)  /* GPIO Alternate Function Select Register GPIO<63:48> */
-#define GAFR2_L         __REG(0x40E00064)  /* GPIO Alternate Function Select Register GPIO<79:64> */
-#define GAFR2_U         __REG(0x40E00068)  /* GPIO Alternate Function Select Register GPIO<95-80> */
-#define GAFR3_L         __REG(0x40E0006C)  /* GPIO Alternate Function Select Register GPIO<111:96> */
-#define GAFR3_U         __REG(0x40E00070)  /* GPIO Alternate Function Select Register GPIO<127:112> */
-
-#define GPLR3           __REG(0x40E00100)  /* GPIO Pin-Level Register GPIO<127:96> */
-#define GPDR3           __REG(0x40E0010C)  /* GPIO Pin Direction Register GPIO<127:96> */
-#define GPSR3           __REG(0x40E00118)  /* GPIO Pin Output Set Register GPIO<127:96> */
-#define GPCR3           __REG(0x40E00124)  /* GPIO Pin Output Clear Register GPIO<127:96> */
-#define GRER3           __REG(0x40E00130)  /* GPIO Rising-Edge Detect Register GPIO<127:96> */
-#define GFER3           __REG(0x40E0013C)  /* GPIO Falling-Edge Detect Register GPIO<127:96> */
-#define GEDR3           __REG(0x40E00148)  /* GPIO Edge Detect Status Register GPIO<127:96> */
-
-/* More handy macros.  The argument is a literal GPIO number. */
-
-#define GPIO_bit(x)     (1 << ((x) & 0x1f))
-
-#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
-
-/* Interrupt Controller */
-
-#define _GPLR(x)        __REG2(0x40E00000, ((x) & 0x60) >> 3)
-#define _GPDR(x)        __REG2(0x40E0000C, ((x) & 0x60) >> 3)
-#define _GPSR(x)        __REG2(0x40E00018, ((x) & 0x60) >> 3)
-#define _GPCR(x)        __REG2(0x40E00024, ((x) & 0x60) >> 3)
-#define _GRER(x)        __REG2(0x40E00030, ((x) & 0x60) >> 3)
-#define _GFER(x)        __REG2(0x40E0003C, ((x) & 0x60) >> 3)
-#define _GEDR(x)        __REG2(0x40E00048, ((x) & 0x60) >> 3)
-#define _GAFR(x)        __REG2(0x40E00054, ((x) & 0x70) >> 2)
-
-#define GPLR(x)         (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3))
-#define GPDR(x)         (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3))
-#define GPSR(x)         (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3))
-#define GPCR(x)         (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3))
-#define GRER(x)         (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3))
-#define GFER(x)         (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3))
-#define GEDR(x)         (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3))
-#define GAFR(x)         (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \
-                         ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U)))
-#else
-
-#define GPLR(x)         __REG2(0x40E00000, ((x) & 0x60) >> 3)
-#define GPDR(x)         __REG2(0x40E0000C, ((x) & 0x60) >> 3)
-#define GPSR(x)         __REG2(0x40E00018, ((x) & 0x60) >> 3)
-#define GPCR(x)         __REG2(0x40E00024, ((x) & 0x60) >> 3)
-#define GRER(x)         __REG2(0x40E00030, ((x) & 0x60) >> 3)
-#define GFER(x)         __REG2(0x40E0003C, ((x) & 0x60) >> 3)
-#define GEDR(x)         __REG2(0x40E00048, ((x) & 0x60) >> 3)
-#define GAFR(x)         __REG2(0x40E00054, ((x) & 0x70) >> 2)
-
-#endif
-
-/*
- * Power Manager - see pxa2xx-regs.h
- */
-
-/*
- * SSP Serial Port Registers - see include/asm-arm/arch-pxa/regs-ssp.h
- */
-
-/*
- * MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h
- */
-
-/*
- * Core Clock - see include/asm-arm/arch-pxa/pxa2xx-regs.h
- */
-
-#ifdef CONFIG_PXA27x
-
-/* Camera Interface */
-#define CICR0           __REG(0x50000000)
-#define CICR1           __REG(0x50000004)
-#define CICR2           __REG(0x50000008)
-#define CICR3           __REG(0x5000000C)
-#define CICR4           __REG(0x50000010)
-#define CISR            __REG(0x50000014)
-#define CIFR            __REG(0x50000018)
-#define CITOR           __REG(0x5000001C)
-#define CIBR0           __REG(0x50000028)
-#define CIBR1           __REG(0x50000030)
-#define CIBR2           __REG(0x50000038)
-
-#define CICR0_DMAEN     (1 << 31)       /* DMA request enable */
-#define CICR0_PAR_EN    (1 << 30)       /* Parity enable */
-#define CICR0_SL_CAP_EN (1 << 29)       /* Capture enable for slave mode */
-#define CICR0_ENB       (1 << 28)       /* Camera interface enable */
-#define CICR0_DIS       (1 << 27)       /* Camera interface disable */
-#define CICR0_SIM       (0x7 << 24)     /* Sensor interface mode mask */
-#define CICR0_TOM       (1 << 9)        /* Time-out mask */
-#define CICR0_RDAVM     (1 << 8)        /* Receive-data-available mask */
-#define CICR0_FEM       (1 << 7)        /* FIFO-empty mask */
-#define CICR0_EOLM      (1 << 6)        /* End-of-line mask */
-#define CICR0_PERRM     (1 << 5)        /* Parity-error mask */
-#define CICR0_QDM       (1 << 4)        /* Quick-disable mask */
-#define CICR0_CDM       (1 << 3)        /* Disable-done mask */
-#define CICR0_SOFM      (1 << 2)        /* Start-of-frame mask */
-#define CICR0_EOFM      (1 << 1)        /* End-of-frame mask */
-#define CICR0_FOM       (1 << 0)        /* FIFO-overrun mask */
-
-#define CICR1_TBIT      (1 << 31)       /* Transparency bit */
-#define CICR1_RGBT_CONV (0x3 << 29)     /* RGBT conversion mask */
-#define CICR1_PPL       (0x7ff << 15)   /* Pixels per line mask */
-#define CICR1_RGB_CONV  (0x7 << 12)     /* RGB conversion mask */
-#define CICR1_RGB_F     (1 << 11)       /* RGB format */
-#define CICR1_YCBCR_F   (1 << 10)       /* YCbCr format */
-#define CICR1_RGB_BPP   (0x7 << 7)      /* RGB bis per pixel mask */
-#define CICR1_RAW_BPP   (0x3 << 5)      /* Raw bis per pixel mask */
-#define CICR1_COLOR_SP  (0x3 << 3)      /* Color space mask */
-#define CICR1_DW        (0x7 << 0)      /* Data width mask */
-
-#define CICR2_BLW       (0xff << 24)    /* Beginning-of-line pixel clock
-                                           wait count mask */
-#define CICR2_ELW       (0xff << 16)    /* End-of-line pixel clock
-                                           wait count mask */
-#define CICR2_HSW       (0x3f << 10)    /* Horizontal sync pulse width mask */
-#define CICR2_BFPW      (0x3f << 3)     /* Beginning-of-frame pixel clock
-                                           wait count mask */
-#define CICR2_FSW       (0x7 << 0)      /* Frame stabilization
-                                           wait count mask */
-
-#define CICR3_BFW       (0xff << 24)    /* Beginning-of-frame line clock
-                                           wait count mask */
-#define CICR3_EFW       (0xff << 16)    /* End-of-frame line clock
-                                           wait count mask */
-#define CICR3_VSW       (0x3f << 10)    /* Vertical sync pulse width mask */
-#define CICR3_BFPW      (0x3f << 3)     /* Beginning-of-frame pixel clock
-                                           wait count mask */
-#define CICR3_LPF       (0x7ff << 0)    /* Lines per frame mask */
-
-#define CICR4_MCLK_DLY  (0x3 << 24)     /* MCLK Data Capture Delay mask */
-#define CICR4_PCLK_EN   (1 << 23)       /* Pixel clock enable */
-#define CICR4_PCP       (1 << 22)       /* Pixel clock polarity */
-#define CICR4_HSP       (1 << 21)       /* Horizontal sync polarity */
-#define CICR4_VSP       (1 << 20)       /* Vertical sync polarity */
-#define CICR4_MCLK_EN   (1 << 19)       /* MCLK enable */
-#define CICR4_FR_RATE   (0x7 << 8)      /* Frame rate mask */
-#define CICR4_DIV       (0xff << 0)     /* Clock divisor mask */
-
-#define CISR_FTO        (1 << 15)       /* FIFO time-out */
-#define CISR_RDAV_2     (1 << 14)       /* Channel 2 receive data available */
-#define CISR_RDAV_1     (1 << 13)       /* Channel 1 receive data available */
-#define CISR_RDAV_0     (1 << 12)       /* Channel 0 receive data available */
-#define CISR_FEMPTY_2   (1 << 11)       /* Channel 2 FIFO empty */
-#define CISR_FEMPTY_1   (1 << 10)       /* Channel 1 FIFO empty */
-#define CISR_FEMPTY_0   (1 << 9)        /* Channel 0 FIFO empty */
-#define CISR_EOL        (1 << 8)        /* End of line */
-#define CISR_PAR_ERR    (1 << 7)        /* Parity error */
-#define CISR_CQD        (1 << 6)        /* Camera interface quick disable */
-#define CISR_CDD        (1 << 5)        /* Camera interface disable done */
-#define CISR_SOF        (1 << 4)        /* Start of frame */
-#define CISR_EOF        (1 << 3)        /* End of frame */
-#define CISR_IFO_2      (1 << 2)        /* FIFO overrun for Channel 2 */
-#define CISR_IFO_1      (1 << 1)        /* FIFO overrun for Channel 1 */
-#define CISR_IFO_0      (1 << 0)        /* FIFO overrun for Channel 0 */
-
-#define CIFR_FLVL2      (0x7f << 23)    /* FIFO 2 level mask */
-#define CIFR_FLVL1      (0x7f << 16)    /* FIFO 1 level mask */
-#define CIFR_FLVL0      (0xff << 8)     /* FIFO 0 level mask */
-#define CIFR_THL_0      (0x3 << 4)      /* Threshold Level for Channel 0 FIFO */
-#define CIFR_RESET_F    (1 << 3)        /* Reset input FIFOs */
-#define CIFR_FEN2       (1 << 2)        /* FIFO enable for channel 2 */
-#define CIFR_FEN1       (1 << 1)        /* FIFO enable for channel 1 */
-#define CIFR_FEN0       (1 << 0)        /* FIFO enable for channel 0 */
-
-#define SRAM_SIZE               0x40000 /* 4x64K  */
-
-#define SRAM_MEM_PHYS           0x5C000000
-
-#define IMPMCR          __REG(0x58000000) /* IM Power Management Control Reg */
-#define IMPMSR          __REG(0x58000008) /* IM Power Management Status Reg */
-
-#define IMPMCR_PC3              (0x3 << 22) /* Bank 3 Power Control */
-#define IMPMCR_PC3_RUN_MODE     (0x0 << 22) /*   Run mode */
-#define IMPMCR_PC3_STANDBY_MODE (0x1 << 22) /*   Standby mode */
-#define IMPMCR_PC3_AUTO_MODE    (0x3 << 22) /*   Automatically controlled */
-
-#define IMPMCR_PC2              (0x3 << 20) /* Bank 2 Power Control */
-#define IMPMCR_PC2_RUN_MODE     (0x0 << 20) /*   Run mode */
-#define IMPMCR_PC2_STANDBY_MODE (0x1 << 20) /*   Standby mode */
-#define IMPMCR_PC2_AUTO_MODE    (0x3 << 20) /*   Automatically controlled */
-
-#define IMPMCR_PC1              (0x3 << 18) /* Bank 1 Power Control */
-#define IMPMCR_PC1_RUN_MODE     (0x0 << 18) /*   Run mode */
-#define IMPMCR_PC1_STANDBY_MODE (0x1 << 18) /*   Standby mode */
-#define IMPMCR_PC1_AUTO_MODE    (0x3 << 18) /*   Automatically controlled */
-
-#define IMPMCR_PC0              (0x3 << 16) /* Bank 0 Power Control */
-#define IMPMCR_PC0_RUN_MODE     (0x0 << 16) /*   Run mode */
-#define IMPMCR_PC0_STANDBY_MODE (0x1 << 16) /*   Standby mode */
-#define IMPMCR_PC0_AUTO_MODE    (0x3 << 16) /*   Automatically controlled */
-
-#define IMPMCR_AW3              (1 << 11) /* Bank 3 Automatic Wake-up enable */
-#define IMPMCR_AW2              (1 << 10) /* Bank 2 Automatic Wake-up enable */
-#define IMPMCR_AW1              (1 << 9)  /* Bank 1 Automatic Wake-up enable */
-#define IMPMCR_AW0              (1 << 8)  /* Bank 0 Automatic Wake-up enable */
-
-#define IMPMCR_DST              (0xFF << 0) /* Delay Standby Time, ms */
-
-#define IMPMSR_PS3              (0x3 << 6) /* Bank 3 Power Status: */
-#define IMPMSR_PS3_RUN_MODE     (0x0 << 6) /*    Run mode */
-#define IMPMSR_PS3_STANDBY_MODE (0x1 << 6) /*    Standby mode */
-
-#define IMPMSR_PS2              (0x3 << 4) /* Bank 2 Power Status: */
-#define IMPMSR_PS2_RUN_MODE     (0x0 << 4) /*    Run mode */
-#define IMPMSR_PS2_STANDBY_MODE (0x1 << 4) /*    Standby mode */
-
-#define IMPMSR_PS1              (0x3 << 2) /* Bank 1 Power Status: */
-#define IMPMSR_PS1_RUN_MODE     (0x0 << 2) /*    Run mode */
-#define IMPMSR_PS1_STANDBY_MODE (0x1 << 2) /*    Standby mode */
-
-#define IMPMSR_PS0              (0x3 << 0) /* Bank 0 Power Status: */
-#define IMPMSR_PS0_RUN_MODE     (0x0 << 0) /*    Run mode */
-#define IMPMSR_PS0_STANDBY_MODE (0x1 << 0) /*    Standby mode */
-
-#endif
-
-#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
-/*
- * UHC: USB Host Controller (OHCI-like) register definitions
- */
-#define UHC_BASE_PHYS   (0x4C000000)
-#define UHCREV          __REG(0x4C000000) /* UHC HCI Spec Revision */
-#define UHCHCON         __REG(0x4C000004) /* UHC Host Control Register */
-#define UHCCOMS         __REG(0x4C000008) /* UHC Command Status Register */
-#define UHCINTS         __REG(0x4C00000C) /* UHC Interrupt Status Register */
-#define UHCINTE         __REG(0x4C000010) /* UHC Interrupt Enable */
-#define UHCINTD         __REG(0x4C000014) /* UHC Interrupt Disable */
-#define UHCHCCA         __REG(0x4C000018) /* UHC Host Controller Comm. Area */
-#define UHCPCED         __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
-#define UHCCHED         __REG(0x4C000020) /* UHC Control Head Endpt Descr */
-#define UHCCCED         __REG(0x4C000024) /* UHC Control Current Endpt Descr */
-#define UHCBHED         __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
-#define UHCBCED         __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
-#define UHCDHEAD        __REG(0x4C000030) /* UHC Done Head */
-#define UHCFMI          __REG(0x4C000034) /* UHC Frame Interval */
-#define UHCFMR          __REG(0x4C000038) /* UHC Frame Remaining */
-#define UHCFMN          __REG(0x4C00003C) /* UHC Frame Number */
-#define UHCPERS         __REG(0x4C000040) /* UHC Periodic Start */
-#define UHCLS           __REG(0x4C000044) /* UHC Low Speed Threshold */
-
-#define UHCRHDA         __REG(0x4C000048) /* UHC Root Hub Descriptor A */
-#define UHCRHDA_NOCP    (1 << 12)       /* No over current protection */
-
-#define UHCRHDB         __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
-#define UHCRHS          __REG(0x4C000050) /* UHC Root Hub Status */
-#define UHCRHPS1        __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
-#define UHCRHPS2        __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
-#define UHCRHPS3        __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
-
-#define UHCSTAT         __REG(0x4C000060) /* UHC Status Register */
-#define UHCSTAT_UPS3    (1 << 16)       /* USB Power Sense Port3 */
-#define UHCSTAT_SBMAI   (1 << 15)       /* System Bus Master Abort Interrupt*/
-#define UHCSTAT_SBTAI   (1 << 14)       /* System Bus Target Abort Interrupt*/
-#define UHCSTAT_UPRI    (1 << 13)       /* USB Port Resume Interrupt */
-#define UHCSTAT_UPS2    (1 << 12)       /* USB Power Sense Port 2 */
-#define UHCSTAT_UPS1    (1 << 11)       /* USB Power Sense Port 1 */
-#define UHCSTAT_HTA     (1 << 10)       /* HCI Target Abort */
-#define UHCSTAT_HBA     (1 << 8)        /* HCI Buffer Active */
-#define UHCSTAT_RWUE    (1 << 7)        /* HCI Remote Wake Up Event */
-
-#define UHCHR           __REG(0x4C000064) /* UHC Reset Register */
-#define UHCHR_SSEP3     (1 << 11)       /* Sleep Standby Enable for Port3 */
-#define UHCHR_SSEP2     (1 << 10)       /* Sleep Standby Enable for Port2 */
-#define UHCHR_SSEP1     (1 << 9)        /* Sleep Standby Enable for Port1 */
-#define UHCHR_PCPL      (1 << 7)        /* Power control polarity low */
-#define UHCHR_PSPL      (1 << 6)        /* Power sense polarity low */
-#define UHCHR_SSE       (1 << 5)        /* Sleep Standby Enable */
-#define UHCHR_UIT       (1 << 4)        /* USB Interrupt Test */
-#define UHCHR_SSDC      (1 << 3)        /* Simulation Scale Down Clock */
-#define UHCHR_CGR       (1 << 2)        /* Clock Generation Reset */
-#define UHCHR_FHR       (1 << 1)        /* Force Host Controller Reset */
-#define UHCHR_FSBIR     (1 << 0)        /* Force System Bus Iface Reset */
-
-#define UHCHIE          __REG(0x4C000068) /* UHC Interrupt Enable Register*/
-#define UHCHIE_UPS3IE   (1 << 14)       /* Power Sense Port3 IntEn */
-#define UHCHIE_UPRIE    (1 << 13)       /* Port Resume IntEn */
-#define UHCHIE_UPS2IE   (1 << 12)       /* Power Sense Port2 IntEn */
-#define UHCHIE_UPS1IE   (1 << 11)       /* Power Sense Port1 IntEn */
-#define UHCHIE_TAIE     (1 << 10)       /* HCI Interface Transfer Abort
-                                           Interrupt Enable*/
-#define UHCHIE_HBAIE    (1 << 8)        /* HCI Buffer Active IntEn */
-#define UHCHIE_RWIE     (1 << 7)        /* Remote Wake-up IntEn */
-
-#define UHCHIT          __REG(0x4C00006C) /* UHC Interrupt Test register */
-
-#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
-
-/* PWRMODE register M field values */
-
-#define PWRMODE_IDLE            0x1
-#define PWRMODE_STANDBY         0x2
-#define PWRMODE_SLEEP           0x3
-#define PWRMODE_DEEPSLEEP       0x7
-
-#endif
diff --git a/include/asm-arm/arch-pxa/pxa2xx-regs.h b/include/asm-arm/arch-pxa/pxa2xx-regs.h
deleted file mode 100644
index 73e0a329cf7f..000000000000
--- a/include/asm-arm/arch-pxa/pxa2xx-regs.h
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-pxa/pxa2xx-regs.h
- *
- *  Taken from pxa-regs.h by Russell King
- *
- *  Author:     Nicolas Pitre
- *  Copyright:  MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __PXA2XX_REGS_H
-#define __PXA2XX_REGS_H
-
-/*
- * Memory controller
- */
-
-#define MDCNFG          __REG(0x48000000)  /* SDRAM Configuration Register 0 */
-#define MDREFR          __REG(0x48000004)  /* SDRAM Refresh Control Register */
-#define MSC0            __REG(0x48000008)  /* Static Memory Control Register 0 */
-#define MSC1            __REG(0x4800000C)  /* Static Memory Control Register 1 */
-#define MSC2            __REG(0x48000010)  /* Static Memory Control Register 2 */
-#define MECR            __REG(0x48000014)  /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
-#define SXLCR           __REG(0x48000018)  /* LCR value to be written to SDRAM-Timing Synchronous Flash */
-#define SXCNFG          __REG(0x4800001C)  /* Synchronous Static Memory Control Register */
-#define SXMRS           __REG(0x48000024)  /* MRS value to be written to Synchronous Flash or SMROM */
-#define MCMEM0          __REG(0x48000028)  /* Card interface Common Memory Space Socket 0 Timing */
-#define MCMEM1          __REG(0x4800002C)  /* Card interface Common Memory Space Socket 1 Timing */
-#define MCATT0          __REG(0x48000030)  /* Card interface Attribute Space Socket 0 Timing Configuration */
-#define MCATT1          __REG(0x48000034)  /* Card interface Attribute Space Socket 1 Timing Configuration */
-#define MCIO0           __REG(0x48000038)  /* Card interface I/O Space Socket 0 Timing Configuration */
-#define MCIO1           __REG(0x4800003C)  /* Card interface I/O Space Socket 1 Timing Configuration */
-#define MDMRS           __REG(0x48000040)  /* MRS value to be written to SDRAM */
-#define BOOT_DEF        __REG(0x48000044)  /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
-
-/*
- * More handy macros for PCMCIA
- *
- * Arg is socket number
- */
-#define MCMEM(s)        __REG2(0x48000028, (s)<<2 )  /* Card interface Common Memory Space Socket s Timing */
-#define MCATT(s)        __REG2(0x48000030, (s)<<2 )  /* Card interface Attribute Space Socket s Timing Configuration */
-#define MCIO(s)         __REG2(0x48000038, (s)<<2 )  /* Card interface I/O Space Socket s Timing Configuration */
-
-/* MECR register defines */
-#define MECR_NOS        (1 << 0)        /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
-#define MECR_CIT        (1 << 1)        /* Card Is There: 0 -> no card, 1 -> card inserted */
-
-#define MDREFR_K0DB4    (1 << 29)       /* SDCLK0 Divide by 4 Control/Status */
-#define MDREFR_K2FREE   (1 << 25)       /* SDRAM Free-Running Control */
-#define MDREFR_K1FREE   (1 << 24)       /* SDRAM Free-Running Control */
-#define MDREFR_K0FREE   (1 << 23)       /* SDRAM Free-Running Control */
-#define MDREFR_SLFRSH   (1 << 22)       /* SDRAM Self-Refresh Control/Status */
-#define MDREFR_APD      (1 << 20)       /* SDRAM/SSRAM Auto-Power-Down Enable */
-#define MDREFR_K2DB2    (1 << 19)       /* SDCLK2 Divide by 2 Control/Status */
-#define MDREFR_K2RUN    (1 << 18)       /* SDCLK2 Run Control/Status */
-#define MDREFR_K1DB2    (1 << 17)       /* SDCLK1 Divide by 2 Control/Status */
-#define MDREFR_K1RUN    (1 << 16)       /* SDCLK1 Run Control/Status */
-#define MDREFR_E1PIN    (1 << 15)       /* SDCKE1 Level Control/Status */
-#define MDREFR_K0DB2    (1 << 14)       /* SDCLK0 Divide by 2 Control/Status */
-#define MDREFR_K0RUN    (1 << 13)       /* SDCLK0 Run Control/Status */
-#define MDREFR_E0PIN    (1 << 12)       /* SDCKE0 Level Control/Status */
-
-
-#ifdef CONFIG_PXA27x
-
-#define ARB_CNTRL       __REG(0x48000048)  /* Arbiter Control Register */
-
-#define ARB_DMA_SLV_PARK        (1<<31)    /* Be parked with DMA slave when idle */
-#define ARB_CI_PARK             (1<<30)    /* Be parked with Camera Interface when idle */
-#define ARB_EX_MEM_PARK         (1<<29)    /* Be parked with external MEMC when idle */
-#define ARB_INT_MEM_PARK        (1<<28)    /* Be parked with internal MEMC when idle */
-#define ARB_USB_PARK            (1<<27)    /* Be parked with USB when idle */
-#define ARB_LCD_PARK            (1<<26)    /* Be parked with LCD when idle */
-#define ARB_DMA_PARK            (1<<25)    /* Be parked with DMA when idle */
-#define ARB_CORE_PARK           (1<<24)    /* Be parked with core when idle */
-#define ARB_LOCK_FLAG           (1<<23)    /* Only Locking masters gain access to the bus */
-
-#endif
-
-
-/*
- * Power Manager
- */
-
-#define PMCR            __REG(0x40F00000)  /* Power Manager Control Register */
-#define PSSR            __REG(0x40F00004)  /* Power Manager Sleep Status Register */
-#define PSPR            __REG(0x40F00008)  /* Power Manager Scratch Pad Register */
-#define PWER            __REG(0x40F0000C)  /* Power Manager Wake-up Enable Register */
-#define PRER            __REG(0x40F00010)  /* Power Manager GPIO Rising-Edge Detect Enable Register */
-#define PFER            __REG(0x40F00014)  /* Power Manager GPIO Falling-Edge Detect Enable Register */
-#define PEDR            __REG(0x40F00018)  /* Power Manager GPIO Edge Detect Status Register */
-#define PCFR            __REG(0x40F0001C)  /* Power Manager General Configuration Register */
-#define PGSR0           __REG(0x40F00020)  /* Power Manager GPIO Sleep State Register for GP[31-0] */
-#define PGSR1           __REG(0x40F00024)  /* Power Manager GPIO Sleep State Register for GP[63-32] */
-#define PGSR2           __REG(0x40F00028)  /* Power Manager GPIO Sleep State Register for GP[84-64] */
-#define PGSR3           __REG(0x40F0002C)  /* Power Manager GPIO Sleep State Register for GP[118-96] */
-#define RCSR            __REG(0x40F00030)  /* Reset Controller Status Register */
-
-#define PSLR            __REG(0x40F00034)       /* Power Manager Sleep Config Register */
-#define PSTR            __REG(0x40F00038)       /* Power Manager Standby Config Register */
-#define PSNR            __REG(0x40F0003C)       /* Power Manager Sense Config Register */
-#define PVCR            __REG(0x40F00040)       /* Power Manager VoltageControl Register */
-#define PKWR            __REG(0x40F00050)       /* Power Manager KB Wake-up Enable Reg */
-#define PKSR            __REG(0x40F00054)       /* Power Manager KB Level-Detect Register */
-#define PCMD(x) __REG2(0x40F00080, (x)<<2)
-#define PCMD0   __REG(0x40F00080 + 0 * 4)
-#define PCMD1   __REG(0x40F00080 + 1 * 4)
-#define PCMD2   __REG(0x40F00080 + 2 * 4)
-#define PCMD3   __REG(0x40F00080 + 3 * 4)
-#define PCMD4   __REG(0x40F00080 + 4 * 4)
-#define PCMD5   __REG(0x40F00080 + 5 * 4)
-#define PCMD6   __REG(0x40F00080 + 6 * 4)
-#define PCMD7   __REG(0x40F00080 + 7 * 4)
-#define PCMD8   __REG(0x40F00080 + 8 * 4)
-#define PCMD9   __REG(0x40F00080 + 9 * 4)
-#define PCMD10  __REG(0x40F00080 + 10 * 4)
-#define PCMD11  __REG(0x40F00080 + 11 * 4)
-#define PCMD12  __REG(0x40F00080 + 12 * 4)
-#define PCMD13  __REG(0x40F00080 + 13 * 4)
-#define PCMD14  __REG(0x40F00080 + 14 * 4)
-#define PCMD15  __REG(0x40F00080 + 15 * 4)
-#define PCMD16  __REG(0x40F00080 + 16 * 4)
-#define PCMD17  __REG(0x40F00080 + 17 * 4)
-#define PCMD18  __REG(0x40F00080 + 18 * 4)
-#define PCMD19  __REG(0x40F00080 + 19 * 4)
-#define PCMD20  __REG(0x40F00080 + 20 * 4)
-#define PCMD21  __REG(0x40F00080 + 21 * 4)
-#define PCMD22  __REG(0x40F00080 + 22 * 4)
-#define PCMD23  __REG(0x40F00080 + 23 * 4)
-#define PCMD24  __REG(0x40F00080 + 24 * 4)
-#define PCMD25  __REG(0x40F00080 + 25 * 4)
-#define PCMD26  __REG(0x40F00080 + 26 * 4)
-#define PCMD27  __REG(0x40F00080 + 27 * 4)
-#define PCMD28  __REG(0x40F00080 + 28 * 4)
-#define PCMD29  __REG(0x40F00080 + 29 * 4)
-#define PCMD30  __REG(0x40F00080 + 30 * 4)
-#define PCMD31  __REG(0x40F00080 + 31 * 4)
-
-#define PCMD_MBC        (1<<12)
-#define PCMD_DCE        (1<<11)
-#define PCMD_LC (1<<10)
-/* FIXME:  PCMD_SQC need be checked.   */
-#define PCMD_SQC        (3<<8)  /* currently only bit 8 is changeable,
-                                   bit 9 should be 0 all day. */
-#define PVCR_VCSA       (0x1<<14)
-#define PVCR_CommandDelay (0xf80)
-#define PCFR_PI2C_EN    (0x1 << 6)
-
-#define PSSR_OTGPH      (1 << 6)        /* OTG Peripheral control Hold */
-#define PSSR_RDH        (1 << 5)        /* Read Disable Hold */
-#define PSSR_PH         (1 << 4)        /* Peripheral Control Hold */
-#define PSSR_STS        (1 << 3)        /* Standby Mode Status */
-#define PSSR_VFS        (1 << 2)        /* VDD Fault Status */
-#define PSSR_BFS        (1 << 1)        /* Battery Fault Status */
-#define PSSR_SSS        (1 << 0)        /* Software Sleep Status */
-
-#define PSLR_SL_ROD     (1 << 20)       /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
-
-#define PCFR_RO         (1 << 15)       /* RDH Override */
-#define PCFR_PO         (1 << 14)       /* PH Override */
-#define PCFR_GPROD      (1 << 12)       /* GPIO nRESET_OUT Disable */
-#define PCFR_L1_EN      (1 << 11)       /* Sleep Mode L1 converter Enable */
-#define PCFR_FVC        (1 << 10)       /* Frequency/Voltage Change */
-#define PCFR_DC_EN      (1 << 7)        /* Sleep/deep-sleep DC-DC Converter Enable */
-#define PCFR_PI2CEN     (1 << 6)        /* Enable PI2C controller */
-#define PCFR_GPR_EN     (1 << 4)        /* nRESET_GPIO Pin Enable */
-#define PCFR_DS         (1 << 3)        /* Deep Sleep Mode */
-#define PCFR_FS         (1 << 2)        /* Float Static Chip Selects */
-#define PCFR_FP         (1 << 1)        /* Float PCMCIA controls */
-#define PCFR_OPDE       (1 << 0)        /* 3.6864 MHz oscillator power-down enable */
-
-#define RCSR_GPR        (1 << 3)        /* GPIO Reset */
-#define RCSR_SMR        (1 << 2)        /* Sleep Mode */
-#define RCSR_WDR        (1 << 1)        /* Watchdog Reset */
-#define RCSR_HWR        (1 << 0)        /* Hardware Reset */
-
-#define PWER_GPIO(Nb)   (1 << Nb)       /* GPIO [0..15] wake-up enable     */
-#define PWER_GPIO0      PWER_GPIO (0)   /* GPIO  [0] wake-up enable        */
-#define PWER_GPIO1      PWER_GPIO (1)   /* GPIO  [1] wake-up enable        */
-#define PWER_GPIO2      PWER_GPIO (2)   /* GPIO  [2] wake-up enable        */
-#define PWER_GPIO3      PWER_GPIO (3)   /* GPIO  [3] wake-up enable        */
-#define PWER_GPIO4      PWER_GPIO (4)   /* GPIO  [4] wake-up enable        */
-#define PWER_GPIO5      PWER_GPIO (5)   /* GPIO  [5] wake-up enable        */
-#define PWER_GPIO6      PWER_GPIO (6)   /* GPIO  [6] wake-up enable        */
-#define PWER_GPIO7      PWER_GPIO (7)   /* GPIO  [7] wake-up enable        */
-#define PWER_GPIO8      PWER_GPIO (8)   /* GPIO  [8] wake-up enable        */
-#define PWER_GPIO9      PWER_GPIO (9)   /* GPIO  [9] wake-up enable        */
-#define PWER_GPIO10     PWER_GPIO (10)  /* GPIO [10] wake-up enable        */
-#define PWER_GPIO11     PWER_GPIO (11)  /* GPIO [11] wake-up enable        */
-#define PWER_GPIO12     PWER_GPIO (12)  /* GPIO [12] wake-up enable        */
-#define PWER_GPIO13     PWER_GPIO (13)  /* GPIO [13] wake-up enable        */
-#define PWER_GPIO14     PWER_GPIO (14)  /* GPIO [14] wake-up enable        */
-#define PWER_GPIO15     PWER_GPIO (15)  /* GPIO [15] wake-up enable        */
-#define PWER_RTC        0x80000000      /* RTC alarm wake-up enable        */
-
-/*
- * PXA2xx specific Core clock definitions
- */
-#define CCCR            __REG(0x41300000)  /* Core Clock Configuration Register */
-#define CCSR            __REG(0x4130000C)  /* Core Clock Status Register */
-#define CKEN            __REG(0x41300004)  /* Clock Enable Register */
-#define OSCC            __REG(0x41300008)  /* Oscillator Configuration Register */
-
-#define CCCR_N_MASK     0x0380  /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
-#define CCCR_M_MASK     0x0060  /* Memory Frequency to Run Mode Frequency Multiplier */
-#define CCCR_L_MASK     0x001f  /* Crystal Frequency to Memory Frequency Multiplier */
-
-#define CKEN_AC97CONF   (31)    /* AC97 Controller Configuration */
-#define CKEN_CAMERA     (24)    /* Camera Interface Clock Enable */
-#define CKEN_SSP1       (23)    /* SSP1 Unit Clock Enable */
-#define CKEN_MEMC       (22)    /* Memory Controller Clock Enable */
-#define CKEN_MEMSTK     (21)    /* Memory Stick Host Controller */
-#define CKEN_IM         (20)    /* Internal Memory Clock Enable */
-#define CKEN_KEYPAD     (19)    /* Keypad Interface Clock Enable */
-#define CKEN_USIM       (18)    /* USIM Unit Clock Enable */
-#define CKEN_MSL        (17)    /* MSL Unit Clock Enable */
-#define CKEN_LCD        (16)    /* LCD Unit Clock Enable */
-#define CKEN_PWRI2C     (15)    /* PWR I2C Unit Clock Enable */
-#define CKEN_I2C        (14)    /* I2C Unit Clock Enable */
-#define CKEN_FICP       (13)    /* FICP Unit Clock Enable */
-#define CKEN_MMC        (12)    /* MMC Unit Clock Enable */
-#define CKEN_USB        (11)    /* USB Unit Clock Enable */
-#define CKEN_ASSP       (10)    /* ASSP (SSP3) Clock Enable */
-#define CKEN_USBHOST    (10)    /* USB Host Unit Clock Enable */
-#define CKEN_OSTIMER    (9)     /* OS Timer Unit Clock Enable */
-#define CKEN_NSSP       (9)     /* NSSP (SSP2) Clock Enable */
-#define CKEN_I2S        (8)     /* I2S Unit Clock Enable */
-#define CKEN_BTUART     (7)     /* BTUART Unit Clock Enable */
-#define CKEN_FFUART     (6)     /* FFUART Unit Clock Enable */
-#define CKEN_STUART     (5)     /* STUART Unit Clock Enable */
-#define CKEN_HWUART     (4)     /* HWUART Unit Clock Enable */
-#define CKEN_SSP3       (4)     /* SSP3 Unit Clock Enable */
-#define CKEN_SSP        (3)     /* SSP Unit Clock Enable */
-#define CKEN_SSP2       (3)     /* SSP2 Unit Clock Enable */
-#define CKEN_AC97       (2)     /* AC97 Unit Clock Enable */
-#define CKEN_PWM1       (1)     /* PWM1 Clock Enable */
-#define CKEN_PWM0       (0)     /* PWM0 Clock Enable */
-
-#define OSCC_OON        (1 << 1)        /* 32.768kHz OON (write-once only bit) */
-#define OSCC_OOK        (1 << 0)        /* 32.768kHz OOK (read-only bit) */
-
-#endif
diff --git a/include/asm-arm/arch-pxa/pxa3xx-regs.h b/include/asm-arm/arch-pxa/pxa3xx-regs.h
deleted file mode 100644
index fe9364c83a28..000000000000
--- a/include/asm-arm/arch-pxa/pxa3xx-regs.h
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * linux/include/asm-arm/arch-pxa/pxa3xx-regs.h
- *
- * PXA3xx specific register definitions
- *
- * Copyright (C) 2007 Marvell International Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_PXA3XX_REGS_H
-#define __ASM_ARCH_PXA3XX_REGS_H
-
-/*
- * Oscillator Configuration Register (OSCC)
- */
-#define OSCC           __REG(0x41350000)  /* Oscillator Configuration Register */
-
-#define OSCC_PEN       (1 << 11)       /* 13MHz POUT */
-
-
-/*
- * Service Power Management Unit (MPMU)
- */
-#define PMCR            __REG(0x40F50000)       /* Power Manager Control Register */
-#define PSR             __REG(0x40F50004)       /* Power Manager S2 Status Register */
-#define PSPR            __REG(0x40F50008)       /* Power Manager Scratch Pad Register */
-#define PCFR            __REG(0x40F5000C)       /* Power Manager General Configuration Register */
-#define PWER            __REG(0x40F50010)       /* Power Manager Wake-up Enable Register */
-#define PWSR            __REG(0x40F50014)       /* Power Manager Wake-up Status Register */
-#define PECR            __REG(0x40F50018)       /* Power Manager EXT_WAKEUP[1:0] Control Register */
-#define DCDCSR          __REG(0x40F50080)       /* DC-DC Controller Status Register */
-#define PVCR            __REG(0x40F50100)       /* Power Manager Voltage Change Control Register */
-#define PCMD(x)         __REG(0x40F50110 + ((x) << 2))
-
-/*
- * Slave Power Managment Unit
- */
-#define ASCR            __REG(0x40f40000)       /* Application Subsystem Power Status/Configuration */
-#define ARSR            __REG(0x40f40004)       /* Application Subsystem Reset Status */
-#define AD3ER           __REG(0x40f40008)       /* Application Subsystem Wake-Up from D3 Enable */
-#define AD3SR           __REG(0x40f4000c)       /* Application Subsystem Wake-Up from D3 Status */
-#define AD2D0ER         __REG(0x40f40010)       /* Application Subsystem Wake-Up from D2 to D0 Enable */
-#define AD2D0SR         __REG(0x40f40014)       /* Application Subsystem Wake-Up from D2 to D0 Status */
-#define AD2D1ER         __REG(0x40f40018)       /* Application Subsystem Wake-Up from D2 to D1 Enable */
-#define AD2D1SR         __REG(0x40f4001c)       /* Application Subsystem Wake-Up from D2 to D1 Status */
-#define AD1D0ER         __REG(0x40f40020)       /* Application Subsystem Wake-Up from D1 to D0 Enable */
-#define AD1D0SR         __REG(0x40f40024)       /* Application Subsystem Wake-Up from D1 to D0 Status */
-#define AGENP           __REG(0x40f4002c)       /* Application Subsystem General Purpose */
-#define AD3R            __REG(0x40f40030)       /* Application Subsystem D3 Configuration */
-#define AD2R            __REG(0x40f40034)       /* Application Subsystem D2 Configuration */
-#define AD1R            __REG(0x40f40038)       /* Application Subsystem D1 Configuration */
-
-/*
- * Application Subsystem Configuration bits.
- */
-#define ASCR_RDH                (1 << 31)
-#define ASCR_D1S                (1 << 2)
-#define ASCR_D2S                (1 << 1)
-#define ASCR_D3S                (1 << 0)
-
-/*
- * Application Reset Status bits.
- */
-#define ARSR_GPR                (1 << 3)
-#define ARSR_LPMR               (1 << 2)
-#define ARSR_WDT                (1 << 1)
-#define ARSR_HWR                (1 << 0)
-
-/*
- * Application Subsystem Wake-Up bits.
- */
-#define ADXER_WRTC              (1 << 31)       /* RTC */
-#define ADXER_WOST              (1 << 30)       /* OS Timer */
-#define ADXER_WTSI              (1 << 29)       /* Touchscreen */
-#define ADXER_WUSBH             (1 << 28)       /* USB host */
-#define ADXER_WUSB2             (1 << 26)       /* USB client 2.0 */
-#define ADXER_WMSL0             (1 << 24)       /* MSL port 0*/
-#define ADXER_WDMUX3            (1 << 23)       /* USB EDMUX3 */
-#define ADXER_WDMUX2            (1 << 22)       /* USB EDMUX2 */
-#define ADXER_WKP               (1 << 21)       /* Keypad */
-#define ADXER_WUSIM1            (1 << 20)       /* USIM Port 1 */
-#define ADXER_WUSIM0            (1 << 19)       /* USIM Port 0 */
-#define ADXER_WOTG              (1 << 16)       /* USBOTG input */
-#define ADXER_MFP_WFLASH        (1 << 15)       /* MFP: Data flash busy */
-#define ADXER_MFP_GEN12         (1 << 14)       /* MFP: MMC3/GPIO/OST inputs */
-#define ADXER_MFP_WMMC2         (1 << 13)       /* MFP: MMC2 */
-#define ADXER_MFP_WMMC1         (1 << 12)       /* MFP: MMC1 */
-#define ADXER_MFP_WI2C          (1 << 11)       /* MFP: I2C */
-#define ADXER_MFP_WSSP4         (1 << 10)       /* MFP: SSP4 */
-#define ADXER_MFP_WSSP3         (1 << 9)        /* MFP: SSP3 */
-#define ADXER_MFP_WMAXTRIX      (1 << 8)        /* MFP: matrix keypad */
-#define ADXER_MFP_WUART3        (1 << 7)        /* MFP: UART3 */
-#define ADXER_MFP_WUART2        (1 << 6)        /* MFP: UART2 */
-#define ADXER_MFP_WUART1        (1 << 5)        /* MFP: UART1 */
-#define ADXER_MFP_WSSP2         (1 << 4)        /* MFP: SSP2 */
-#define ADXER_MFP_WSSP1         (1 << 3)        /* MFP: SSP1 */
-#define ADXER_MFP_WAC97         (1 << 2)        /* MFP: AC97 */
-#define ADXER_WEXTWAKE1         (1 << 1)        /* External Wake 1 */
-#define ADXER_WEXTWAKE0         (1 << 0)        /* External Wake 0 */
-
-/*
- * AD3R/AD2R/AD1R bits.  R2-R5 are only defined for PXA320.
- */
-#define ADXR_L2                 (1 << 8)
-#define ADXR_R5                 (1 << 5)
-#define ADXR_R4                 (1 << 4)
-#define ADXR_R3                 (1 << 3)
-#define ADXR_R2                 (1 << 2)
-#define ADXR_R1                 (1 << 1)
-#define ADXR_R0                 (1 << 0)
-
-/*
- * Values for PWRMODE CP15 register
- */
-#define PXA3xx_PM_S3D4C4        0x07    /* aka deep sleep */
-#define PXA3xx_PM_S2D3C4        0x06    /* aka sleep */
-#define PXA3xx_PM_S0D2C2        0x03    /* aka standby */
-#define PXA3xx_PM_S0D1C2        0x02    /* aka LCD refresh */
-#define PXA3xx_PM_S0D0C1        0x01
-
-/*
- * Application Subsystem Clock
- */
-#define ACCR            __REG(0x41340000)       /* Application Subsystem Clock Configuration Register */
-#define ACSR            __REG(0x41340004)       /* Application Subsystem Clock Status Register */
-#define AICSR           __REG(0x41340008)       /* Application Subsystem Interrupt Control/Status Register */
-#define CKENA           __REG(0x4134000C)       /* A Clock Enable Register */
-#define CKENB           __REG(0x41340010)       /* B Clock Enable Register */
-#define AC97_DIV        __REG(0x41340014)       /* AC97 clock divisor value register */
-
-/*
- * Clock Enable Bit
- */
-#define CKEN_LCD        1       /* < LCD Clock Enable */
-#define CKEN_USBH       2       /* < USB host clock enable */
-#define CKEN_CAMERA     3       /* < Camera interface clock enable */
-#define CKEN_NAND       4       /* < NAND Flash Controller Clock Enable */
-#define CKEN_USB2       6       /* < USB 2.0 client clock enable. */
-#define CKEN_DMC        8       /* < Dynamic Memory Controller clock enable */
-#define CKEN_SMC        9       /* < Static Memory Controller clock enable */
-#define CKEN_ISC        10      /* < Internal SRAM Controller clock enable */
-#define CKEN_BOOT       11      /* < Boot rom clock enable */
-#define CKEN_MMC1       12      /* < MMC1 Clock enable */
-#define CKEN_MMC2       13      /* < MMC2 clock enable */
-#define CKEN_KEYPAD     14      /* < Keypand Controller Clock Enable */
-#define CKEN_CIR        15      /* < Consumer IR Clock Enable */
-#define CKEN_USIM0      17      /* < USIM[0] Clock Enable */
-#define CKEN_USIM1      18      /* < USIM[1] Clock Enable */
-#define CKEN_TPM        19      /* < TPM clock enable */
-#define CKEN_UDC        20      /* < UDC clock enable */
-#define CKEN_BTUART     21      /* < BTUART clock enable */
-#define CKEN_FFUART     22      /* < FFUART clock enable */
-#define CKEN_STUART     23      /* < STUART clock enable */
-#define CKEN_AC97       24      /* < AC97 clock enable */
-#define CKEN_TOUCH      25      /* < Touch screen Interface Clock Enable */
-#define CKEN_SSP1       26      /* < SSP1 clock enable */
-#define CKEN_SSP2       27      /* < SSP2 clock enable */
-#define CKEN_SSP3       28      /* < SSP3 clock enable */
-#define CKEN_SSP4       29      /* < SSP4 clock enable */
-#define CKEN_MSL0       30      /* < MSL0 clock enable */
-#define CKEN_PWM0       32      /* < PWM[0] clock enable */
-#define CKEN_PWM1       33      /* < PWM[1] clock enable */
-#define CKEN_I2C        36      /* < I2C clock enable */
-#define CKEN_INTC       38      /* < Interrupt controller clock enable */
-#define CKEN_GPIO       39      /* < GPIO clock enable */
-#define CKEN_1WIRE      40      /* < 1-wire clock enable */
-#define CKEN_HSIO2      41      /* < HSIO2 clock enable */
-#define CKEN_MINI_IM    48      /* < Mini-IM */
-#define CKEN_MINI_LCD   49      /* < Mini LCD */
-
-#if defined(CONFIG_CPU_PXA310)
-#define CKEN_MMC3       5       /* < MMC3 Clock Enable */
-#define CKEN_MVED       43      /* < MVED clock enable */
-#endif
-
-/* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */
-#define PXA300_CKEN_GRAPHICS    42      /* Graphics controller clock enable */
-#define PXA320_CKEN_GRAPHICS    7       /* Graphics controller clock enable */
-
-#endif /* __ASM_ARCH_PXA3XX_REGS_H */
diff --git a/include/asm-arm/arch-pxa/pxafb.h b/include/asm-arm/arch-pxa/pxafb.h
deleted file mode 100644
index daf018d0c604..000000000000
--- a/include/asm-arm/arch-pxa/pxafb.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-pxa/pxafb.h
- *
- *  Support for the xscale frame buffer.
- *
- *  Author:     Jean-Frederic Clere
- *  Created:    Sep 22, 2003
- *  Copyright:  jfclere@sinix.net
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-
-#include <linux/fb.h>
-#include <asm/arch/regs-lcd.h>
-
-/*
- * Supported LCD connections
- *
- * bits 0 - 3: for LCD panel type:
- *
- *   STN  - for passive matrix
- *   DSTN - for dual scan passive matrix
- *   TFT  - for active matrix
- *
- * bits 4 - 9 : for bus width
- * bits 10-17 : for AC Bias Pin Frequency
- * bit     18 : for output enable polarity
- * bit     19 : for pixel clock edge
- */
-#define LCD_CONN_TYPE(_x)       ((_x) & 0x0f)
-#define LCD_CONN_WIDTH(_x)      (((_x) >> 4) & 0x1f)
-
-#define LCD_TYPE_UNKNOWN        0
-#define LCD_TYPE_MONO_STN       1
-#define LCD_TYPE_MONO_DSTN      2
-#define LCD_TYPE_COLOR_STN      3
-#define LCD_TYPE_COLOR_DSTN     4
-#define LCD_TYPE_COLOR_TFT      5
-#define LCD_TYPE_SMART_PANEL    6
-#define LCD_TYPE_MAX            7
-
-#define LCD_MONO_STN_4BPP       ((4  << 4) | LCD_TYPE_MONO_STN)
-#define LCD_MONO_STN_8BPP       ((8  << 4) | LCD_TYPE_MONO_STN)
-#define LCD_MONO_DSTN_8BPP      ((8  << 4) | LCD_TYPE_MONO_DSTN)
-#define LCD_COLOR_STN_8BPP      ((8  << 4) | LCD_TYPE_COLOR_STN)
-#define LCD_COLOR_DSTN_16BPP    ((16 << 4) | LCD_TYPE_COLOR_DSTN)
-#define LCD_COLOR_TFT_16BPP     ((16 << 4) | LCD_TYPE_COLOR_TFT)
-#define LCD_COLOR_TFT_18BPP     ((18 << 4) | LCD_TYPE_COLOR_TFT)
-#define LCD_SMART_PANEL_8BPP    ((8  << 4) | LCD_TYPE_SMART_PANEL)
-#define LCD_SMART_PANEL_16BPP   ((16 << 4) | LCD_TYPE_SMART_PANEL)
-#define LCD_SMART_PANEL_18BPP   ((18 << 4) | LCD_TYPE_SMART_PANEL)
-
-#define LCD_AC_BIAS_FREQ(x)     (((x) & 0xff) << 10)
-#define LCD_BIAS_ACTIVE_HIGH    (0 << 17)
-#define LCD_BIAS_ACTIVE_LOW     (1 << 17)
-#define LCD_PCLK_EDGE_RISE      (0 << 18)
-#define LCD_PCLK_EDGE_FALL      (1 << 18)
-
-/*
- * This structure describes the machine which we are running on.
- * It is set in linux/arch/arm/mach-pxa/machine_name.c and used in the probe routine
- * of linux/drivers/video/pxafb.c
- */
-struct pxafb_mode_info {
-        u_long          pixclock;
-
-        u_short         xres;
-        u_short         yres;
-
-        u_char          bpp;
-        u_int           cmap_greyscale:1,
-                        depth:8,
-                        unused:23;
-
-        /* Parallel Mode Timing */
-        u_char          hsync_len;
-        u_char          left_margin;
-        u_char          right_margin;
-
-        u_char          vsync_len;
-        u_char          upper_margin;
-        u_char          lower_margin;
-        u_char          sync;
-
-        /* Smart Panel Mode Timing - see PXA27x DM 7.4.15.0.3 for details
-         * Note:
-         * 1. all parameters in nanosecond (ns)
-         * 2. a0cs{rd,wr}_set_hld are controlled by the same register bits
-         *    in pxa27x and pxa3xx, initialize them to the same value or
-         *    the larger one will be used
-         * 3. same to {rd,wr}_pulse_width
-         */
-        unsigned        a0csrd_set_hld; /* A0 and CS Setup/Hold Time before/after L_FCLK_RD */
-        unsigned        a0cswr_set_hld; /* A0 and CS Setup/Hold Time before/after L_PCLK_WR */
-        unsigned        wr_pulse_width; /* L_PCLK_WR pulse width */
-        unsigned        rd_pulse_width; /* L_FCLK_RD pulse width */
-        unsigned        cmd_inh_time;   /* Command Inhibit time between two writes */
-        unsigned        op_hold_time;   /* Output Hold time from L_FCLK_RD negation */
-};
-
-struct pxafb_mach_info {
-        struct pxafb_mode_info *modes;
-        unsigned int num_modes;
-
-        unsigned int    lcd_conn;
-
-        u_int           fixed_modes:1,
-                        cmap_inverse:1,
-                        cmap_static:1,
-                        unused:29;
-
-        /* The following should be defined in LCCR0
-         *      LCCR0_Act or LCCR0_Pas          Active or Passive
-         *      LCCR0_Sngl or LCCR0_Dual        Single/Dual panel
-         *      LCCR0_Mono or LCCR0_Color       Mono/Color
-         *      LCCR0_4PixMono or LCCR0_8PixMono (in mono single mode)
-         *      LCCR0_DMADel(Tcpu) (optional)   DMA request delay
-         *
-         * The following should not be defined in LCCR0:
-         *      LCCR0_OUM, LCCR0_BM, LCCR0_QDM, LCCR0_DIS, LCCR0_EFM
-         *      LCCR0_IUM, LCCR0_SFM, LCCR0_LDM, LCCR0_ENB
-         */
-        u_int           lccr0;
-        /* The following should be defined in LCCR3
-         *      LCCR3_OutEnH or LCCR3_OutEnL    Output enable polarity
-         *      LCCR3_PixRsEdg or LCCR3_PixFlEdg Pixel clock edge type
-         *      LCCR3_Acb(X)                    AB Bias pin frequency
-         *      LCCR3_DPC (optional)            Double Pixel Clock mode (untested)
-         *
-         * The following should not be defined in LCCR3
-         *      LCCR3_HSP, LCCR3_VSP, LCCR0_Pcd(x), LCCR3_Bpp
-         */
-        u_int           lccr3;
-        /* The following should be defined in LCCR4
-         *      LCCR4_PAL_FOR_0 or LCCR4_PAL_FOR_1 or LCCR4_PAL_FOR_2
-         *
-         * All other bits in LCCR4 should be left alone.
-         */
-        u_int           lccr4;
-        void (*pxafb_backlight_power)(int);
-        void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
-        void (*smart_update)(struct fb_info *);
-};
-void set_pxa_fb_info(struct pxafb_mach_info *hard_pxa_fb_info);
-void set_pxa_fb_parent(struct device *parent_dev);
-unsigned long pxafb_get_hsync_time(struct device *dev);
-
-extern int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int);
-extern int pxafb_smart_flush(struct fb_info *info);
diff --git a/include/asm-arm/arch-pxa/regs-lcd.h b/include/asm-arm/arch-pxa/regs-lcd.h
deleted file mode 100644
index 820a189684a9..000000000000
--- a/include/asm-arm/arch-pxa/regs-lcd.h
+++ /dev/null
@@ -1,180 +0,0 @@
-#ifndef __ASM_ARCH_REGS_LCD_H
-#define __ASM_ARCH_REGS_LCD_H
-
-#include <asm/arch/bitfield.h>
-
-/*
- * LCD Controller Registers and Bits Definitions
- */
-#define LCCR0           (0x000) /* LCD Controller Control Register 0 */
-#define LCCR1           (0x004) /* LCD Controller Control Register 1 */
-#define LCCR2           (0x008) /* LCD Controller Control Register 2 */
-#define LCCR3           (0x00C) /* LCD Controller Control Register 3 */
-#define LCCR4           (0x010) /* LCD Controller Control Register 4 */
-#define LCCR5           (0x014) /* LCD Controller Control Register 5 */
-#define DFBR0           (0x020) /* DMA Channel 0 Frame Branch Register */
-#define DFBR1           (0x024) /* DMA Channel 1 Frame Branch Register */
-#define LCSR            (0x038) /* LCD Controller Status Register */
-#define LIIDR           (0x03C) /* LCD Controller Interrupt ID Register */
-#define TMEDRGBR        (0x040) /* TMED RGB Seed Register */
-#define TMEDCR          (0x044) /* TMED Control Register */
-
-#define CMDCR           (0x100) /* Command Control Register */
-#define PRSR            (0x104) /* Panel Read Status Register */
-
-#define LCCR3_1BPP      (0 << 24)
-#define LCCR3_2BPP      (1 << 24)
-#define LCCR3_4BPP      (2 << 24)
-#define LCCR3_8BPP      (3 << 24)
-#define LCCR3_16BPP     (4 << 24)
-#define LCCR3_18BPP     (5 << 24)
-#define LCCR3_18BPP_P   (6 << 24)
-#define LCCR3_19BPP     (7 << 24)
-#define LCCR3_19BPP_P   (1 << 29)
-#define LCCR3_24BPP     ((1 << 29) | (1 << 24))
-#define LCCR3_25BPP     ((1 << 29) | (2 << 24))
-
-#define LCCR3_PDFOR_0   (0 << 30)
-#define LCCR3_PDFOR_1   (1 << 30)
-#define LCCR3_PDFOR_2   (2 << 30)
-#define LCCR3_PDFOR_3   (3 << 30)
-
-#define LCCR4_PAL_FOR_0 (0 << 15)
-#define LCCR4_PAL_FOR_1 (1 << 15)
-#define LCCR4_PAL_FOR_2 (2 << 15)
-#define LCCR4_PAL_FOR_MASK      (3 << 15)
-
-#define FDADR0          (0x200) /* DMA Channel 0 Frame Descriptor Address Register */
-#define FSADR0          (0x204) /* DMA Channel 0 Frame Source Address Register */
-#define FIDR0           (0x208) /* DMA Channel 0 Frame ID Register */
-#define LDCMD0          (0x20C) /* DMA Channel 0 Command Register */
-#define FDADR1          (0x210) /* DMA Channel 1 Frame Descriptor Address Register */
-#define FSADR1          (0x214) /* DMA Channel 1 Frame Source Address Register */
-#define FIDR1           (0x218) /* DMA Channel 1 Frame ID Register */
-#define LDCMD1          (0x21C) /* DMA Channel 1 Command Register */
-#define FDADR6          (0x260) /* DMA Channel 6 Frame Descriptor Address Register */
-#define FSADR6          (0x264) /* DMA Channel 6 Frame Source Address Register */
-#define FIDR6           (0x268) /* DMA Channel 6 Frame ID Register */
-
-#define LCCR0_ENB       (1 << 0)        /* LCD Controller enable */
-#define LCCR0_CMS       (1 << 1)        /* Color/Monochrome Display Select */
-#define LCCR0_Color     (LCCR0_CMS*0)   /*  Color display */
-#define LCCR0_Mono      (LCCR0_CMS*1)   /*  Monochrome display */
-#define LCCR0_SDS       (1 << 2)        /* Single/Dual Panel Display Select */
-#define LCCR0_Sngl      (LCCR0_SDS*0)   /*  Single panel display */
-#define LCCR0_Dual      (LCCR0_SDS*1)   /*  Dual panel display */
-
-#define LCCR0_LDM       (1 << 3)        /* LCD Disable Done Mask */
-#define LCCR0_SFM       (1 << 4)        /* Start of frame mask */
-#define LCCR0_IUM       (1 << 5)        /* Input FIFO underrun mask */
-#define LCCR0_EFM       (1 << 6)        /* End of Frame mask */
-#define LCCR0_PAS       (1 << 7)        /* Passive/Active display Select */
-#define LCCR0_Pas       (LCCR0_PAS*0)   /*  Passive display (STN) */
-#define LCCR0_Act       (LCCR0_PAS*1)   /*  Active display (TFT) */
-#define LCCR0_DPD       (1 << 9)        /* Double Pixel Data (monochrome) */
-#define LCCR0_4PixMono  (LCCR0_DPD*0)   /*  4-Pixel/clock Monochrome display */
-#define LCCR0_8PixMono  (LCCR0_DPD*1)   /*  8-Pixel/clock Monochrome display */
-#define LCCR0_DIS       (1 << 10)       /* LCD Disable */
-#define LCCR0_QDM       (1 << 11)       /* LCD Quick Disable mask */
-#define LCCR0_PDD       (0xff << 12)    /* Palette DMA request delay */
-#define LCCR0_PDD_S     12
-#define LCCR0_BM        (1 << 20)       /* Branch mask */
-#define LCCR0_OUM       (1 << 21)       /* Output FIFO underrun mask */
-#define LCCR0_LCDT      (1 << 22)       /* LCD panel type */
-#define LCCR0_RDSTM     (1 << 23)       /* Read status interrupt mask */
-#define LCCR0_CMDIM     (1 << 24)       /* Command interrupt mask */
-#define LCCR0_OUC       (1 << 25)       /* Overlay Underlay control bit */
-#define LCCR0_LDDALT    (1 << 26)       /* LDD alternate mapping control */
-
-#define LCCR1_PPL       Fld (10, 0)     /* Pixels Per Line - 1 */
-#define LCCR1_DisWdth(Pixel)    (((Pixel) - 1) << FShft (LCCR1_PPL))
-
-#define LCCR1_HSW       Fld (6, 10)     /* Horizontal Synchronization */
-#define LCCR1_HorSnchWdth(Tpix) (((Tpix) - 1) << FShft (LCCR1_HSW))
-
-#define LCCR1_ELW       Fld (8, 16)     /* End-of-Line pixel clock Wait - 1 */
-#define LCCR1_EndLnDel(Tpix)    (((Tpix) - 1) << FShft (LCCR1_ELW))
-
-#define LCCR1_BLW       Fld (8, 24)     /* Beginning-of-Line pixel clock */
-#define LCCR1_BegLnDel(Tpix)    (((Tpix) - 1) << FShft (LCCR1_BLW))
-
-#define LCCR2_LPP       Fld (10, 0)     /* Line Per Panel - 1 */
-#define LCCR2_DisHght(Line)     (((Line) - 1) << FShft (LCCR2_LPP))
-
-#define LCCR2_VSW       Fld (6, 10)     /* Vertical Synchronization pulse - 1 */
-#define LCCR2_VrtSnchWdth(Tln)  (((Tln) - 1) << FShft (LCCR2_VSW))
-
-#define LCCR2_EFW       Fld (8, 16)     /* End-of-Frame line clock Wait */
-#define LCCR2_EndFrmDel(Tln)    ((Tln) << FShft (LCCR2_EFW))
-
-#define LCCR2_BFW       Fld (8, 24)     /* Beginning-of-Frame line clock */
-#define LCCR2_BegFrmDel(Tln)    ((Tln) << FShft (LCCR2_BFW))
-
-#define LCCR3_API       (0xf << 16)     /* AC Bias pin trasitions per interrupt */
-#define LCCR3_API_S     16
-#define LCCR3_VSP       (1 << 20)       /* vertical sync polarity */
-#define LCCR3_HSP       (1 << 21)       /* horizontal sync polarity */
-#define LCCR3_PCP       (1 << 22)       /* Pixel Clock Polarity (L_PCLK) */
-#define LCCR3_PixRsEdg  (LCCR3_PCP*0)   /*  Pixel clock Rising-Edge */
-#define LCCR3_PixFlEdg  (LCCR3_PCP*1)   /*  Pixel clock Falling-Edge */
-
-#define LCCR3_OEP       (1 << 23)       /* Output Enable Polarity */
-#define LCCR3_OutEnH    (LCCR3_OEP*0)   /*  Output Enable active High */
-#define LCCR3_OutEnL    (LCCR3_OEP*1)   /*  Output Enable active Low */
-
-#define LCCR3_DPC       (1 << 27)       /* double pixel clock mode */
-#define LCCR3_PCD       Fld (8, 0)      /* Pixel Clock Divisor */
-#define LCCR3_PixClkDiv(Div)    (((Div) << FShft (LCCR3_PCD)))
-
-#define LCCR3_BPP       Fld (3, 24)     /* Bit Per Pixel */
-#define LCCR3_Bpp(Bpp)  (((Bpp) << FShft (LCCR3_BPP)))
-
-#define LCCR3_ACB       Fld (8, 8)      /* AC Bias */
-#define LCCR3_Acb(Acb)  (((Acb) << FShft (LCCR3_ACB)))
-
-#define LCCR3_HorSnchH  (LCCR3_HSP*0)   /*  HSP Active High */
-#define LCCR3_HorSnchL  (LCCR3_HSP*1)   /*  HSP Active Low */
-
-#define LCCR3_VrtSnchH  (LCCR3_VSP*0)   /*  VSP Active High */
-#define LCCR3_VrtSnchL  (LCCR3_VSP*1)   /*  VSP Active Low */
-
-#define LCCR5_IUM(x)    (1 << ((x) + 23)) /* input underrun mask */
-#define LCCR5_BSM(x)    (1 << ((x) + 15)) /* branch mask */
-#define LCCR5_EOFM(x)   (1 << ((x) + 7))  /* end of frame mask */
-#define LCCR5_SOFM(x)   (1 << ((x) + 0))  /* start of frame mask */
-
-#define LCSR_LDD        (1 << 0)        /* LCD Disable Done */
-#define LCSR_SOF        (1 << 1)        /* Start of frame */
-#define LCSR_BER        (1 << 2)        /* Bus error */
-#define LCSR_ABC        (1 << 3)        /* AC Bias count */
-#define LCSR_IUL        (1 << 4)        /* input FIFO underrun Lower panel */
-#define LCSR_IUU        (1 << 5)        /* input FIFO underrun Upper panel */
-#define LCSR_OU         (1 << 6)        /* output FIFO underrun */
-#define LCSR_QD         (1 << 7)        /* quick disable */
-#define LCSR_EOF        (1 << 8)        /* end of frame */
-#define LCSR_BS         (1 << 9)        /* branch status */
-#define LCSR_SINT       (1 << 10)       /* subsequent interrupt */
-#define LCSR_RD_ST      (1 << 11)       /* read status */
-#define LCSR_CMD_INT    (1 << 12)       /* command interrupt */
-
-#define LDCMD_PAL       (1 << 26)       /* instructs DMA to load palette buffer */
-
-/* smartpanel related */
-#define PRSR_DATA(x)    ((x) & 0xff)    /* Panel Data */
-#define PRSR_A0         (1 << 8)        /* Read Data Source */
-#define PRSR_ST_OK      (1 << 9)        /* Status OK */
-#define PRSR_CON_NT     (1 << 10)       /* Continue to Next Command */
-
-#define SMART_CMD_A0                     (0x1 << 8)
-#define SMART_CMD_READ_STATUS_REG        (0x0 << 9)
-#define SMART_CMD_READ_FRAME_BUFFER     ((0x0 << 9) | SMART_CMD_A0)
-#define SMART_CMD_WRITE_COMMAND          (0x1 << 9)
-#define SMART_CMD_WRITE_DATA            ((0x1 << 9) | SMART_CMD_A0)
-#define SMART_CMD_WRITE_FRAME           ((0x2 << 9) | SMART_CMD_A0)
-#define SMART_CMD_WAIT_FOR_VSYNC         (0x3 << 9)
-#define SMART_CMD_NOOP                   (0x4 << 9)
-#define SMART_CMD_INTERRUPT              (0x5 << 9)
-
-#define SMART_CMD(x)    (SMART_CMD_WRITE_COMMAND | ((x) & 0xff))
-#define SMART_DAT(x)    (SMART_CMD_WRITE_DATA | ((x) & 0xff))
-#endif /* __ASM_ARCH_REGS_LCD_H */
diff --git a/include/asm-arm/arch-pxa/system.h b/include/asm-arm/arch-pxa/system.h
deleted file mode 100644
index 6956fc5235f8..000000000000
--- a/include/asm-arm/arch-pxa/system.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * linux/include/asm-arm/arch-pxa/system.h
- *
- * Author:      Nicolas Pitre
- * Created:     Jun 15, 2001
- * Copyright:   MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <asm/proc-fns.h>
-#include "hardware.h"
-#include "pxa2xx-regs.h"
-#include "pxa-regs.h"
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-
-void arch_reset(char mode);
diff --git a/include/asm-arm/arch-pxa/timex.h b/include/asm-arm/arch-pxa/timex.h
deleted file mode 100644
index 8d882f0b6a16..000000000000
--- a/include/asm-arm/arch-pxa/timex.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * linux/include/asm-arm/arch-pxa/timex.h
- *
- * Author:      Nicolas Pitre
- * Created:     Jun 15, 2001
- * Copyright:   MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-
-#if defined(CONFIG_PXA25x)
-/* PXA250/210 timer base */
-#define CLOCK_TICK_RATE 3686400
-#elif defined(CONFIG_PXA27x)
-/* PXA27x timer base */
-#ifdef CONFIG_MACH_MAINSTONE
-#define CLOCK_TICK_RATE 3249600
-#else
-#define CLOCK_TICK_RATE 3250000
-#endif
-#else
-#define CLOCK_TICK_RATE 3250000
-#endif
diff --git a/include/asm-arm/arch-pxa/udc.h b/include/asm-arm/arch-pxa/udc.h
deleted file mode 100644
index 27aa3a91012f..000000000000
--- a/include/asm-arm/arch-pxa/udc.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/*
- * linux/include/asm-arm/arch-pxa/udc.h
- *
- */
-#include <asm/mach/udc_pxa2xx.h>
-
-extern void pxa_set_udc_info(struct pxa2xx_udc_mach_info *info);
-
diff --git a/include/asm-arm/arch-pxa/uncompress.h b/include/asm-arm/arch-pxa/uncompress.h
deleted file mode 100644
index f4551269aaf2..000000000000
--- a/include/asm-arm/arch-pxa/uncompress.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * linux/include/asm-arm/arch-pxa/uncompress.h
- *
- * Author:      Nicolas Pitre
- * Copyright:   (C) 2001 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/serial_reg.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/mach-types.h>
-
-#define __REG(x)       ((volatile unsigned long *)x)
-
-static volatile unsigned long *UART = FFUART;
-
-static inline void putc(char c)
-{
-        if (!(UART[UART_IER] & IER_UUE))
-                return;
-        while (!(UART[UART_LSR] & LSR_TDRQ))
-                barrier();
-        UART[UART_TX] = c;
-}
-
-/*
- * This does not append a newline
- */
-static inline void flush(void)
-{
-}
-
-static inline void arch_decomp_setup(void)
-{
-        if (machine_is_littleton())
-                UART = STUART;
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-pxa/vmalloc.h b/include/asm-arm/arch-pxa/vmalloc.h
deleted file mode 100644
index 5bb450c7aa2c..000000000000
--- a/include/asm-arm/arch-pxa/vmalloc.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * linux/include/asm-arm/arch-pxa/vmalloc.h
- *
- * Author:      Nicolas Pitre
- * Copyright:   (C) 2001 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#define VMALLOC_END       (0xe8000000)
diff --git a/include/asm-arm/arch-realview/board-eb.h b/include/asm-arm/arch-realview/board-eb.h
deleted file mode 100644
index 206f7a752882..000000000000
--- a/include/asm-arm/arch-realview/board-eb.h
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
- * include/asm-arm/arch-realview/board-eb.h
- *
- * Copyright (C) 2007 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __ASM_ARCH_BOARD_EB_H
-#define __ASM_ARCH_BOARD_EB_H
-
-#include <asm/arch/platform.h>
-
-/*
- * RealView EB + ARM11MPCore peripheral addresses
- */
-#define REALVIEW_EB_UART0_BASE          0x10009000      /* UART 0 */
-#define REALVIEW_EB_UART1_BASE          0x1000A000      /* UART 1 */
-#define REALVIEW_EB_UART2_BASE          0x1000B000      /* UART 2 */
-#define REALVIEW_EB_UART3_BASE          0x1000C000      /* UART 3 */
-#define REALVIEW_EB_SSP_BASE            0x1000D000      /* Synchronous Serial Port */
-#define REALVIEW_EB_WATCHDOG_BASE       0x10010000      /* watchdog interface */
-#define REALVIEW_EB_TIMER0_1_BASE       0x10011000      /* Timer 0 and 1 */
-#define REALVIEW_EB_TIMER2_3_BASE       0x10012000      /* Timer 2 and 3 */
-#define REALVIEW_EB_GPIO0_BASE          0x10013000      /* GPIO port 0 */
-#define REALVIEW_EB_RTC_BASE            0x10017000      /* Real Time Clock */
-#define REALVIEW_EB_CLCD_BASE           0x10020000      /* CLCD */
-#define REALVIEW_EB_GIC_CPU_BASE        0x10040000      /* Generic interrupt controller CPU interface */
-#define REALVIEW_EB_GIC_DIST_BASE       0x10041000      /* Generic interrupt controller distributor */
-#define REALVIEW_EB_SMC_BASE            0x10080000      /* Static memory controller */
-
-#define REALVIEW_EB_FLASH_BASE          0x40000000
-#define REALVIEW_EB_FLASH_SIZE          SZ_64M
-#define REALVIEW_EB_ETH_BASE            0x4E000000      /* Ethernet */
-#define REALVIEW_EB_USB_BASE            0x4F000000      /* USB */
-
-#ifdef CONFIG_REALVIEW_EB_ARM11MP_REVB
-#define REALVIEW_EB11MP_SCU_BASE        0x10100000      /* SCU registers */
-#define REALVIEW_EB11MP_GIC_CPU_BASE    0x10100100      /* Generic interrupt controller CPU interface */
-#define REALVIEW_EB11MP_TWD_BASE        0x10100700
-#define REALVIEW_EB11MP_TWD_SIZE        0x00000100
-#define REALVIEW_EB11MP_GIC_DIST_BASE   0x10101000      /* Generic interrupt controller distributor */
-#define REALVIEW_EB11MP_L220_BASE       0x10102000      /* L220 registers */
-#define REALVIEW_EB11MP_SYS_PLD_CTRL1   0xD8            /* Register offset for MPCore sysctl */
-#else
-#define REALVIEW_EB11MP_SCU_BASE        0x1F000000      /* SCU registers */
-#define REALVIEW_EB11MP_GIC_CPU_BASE    0x1F000100      /* Generic interrupt controller CPU interface */
-#define REALVIEW_EB11MP_TWD_BASE        0x1F000700
-#define REALVIEW_EB11MP_TWD_SIZE        0x00000100
-#define REALVIEW_EB11MP_GIC_DIST_BASE   0x1F001000      /* Generic interrupt controller distributor */
-#define REALVIEW_EB11MP_L220_BASE       0x1F002000      /* L220 registers */
-#define REALVIEW_EB11MP_SYS_PLD_CTRL1   0x74            /* Register offset for MPCore sysctl */
-#endif
-
-#define IRQ_EB_GIC_START        32
-
-/*
- * RealView EB interrupt sources
- */
-#define IRQ_EB_WDOG             (IRQ_EB_GIC_START + 0)          /* Watchdog timer */
-#define IRQ_EB_SOFT             (IRQ_EB_GIC_START + 1)          /* Software interrupt */
-#define IRQ_EB_COMMRx           (IRQ_EB_GIC_START + 2)          /* Debug Comm Rx interrupt */
-#define IRQ_EB_COMMTx           (IRQ_EB_GIC_START + 3)          /* Debug Comm Tx interrupt */
-#define IRQ_EB_TIMER0_1         (IRQ_EB_GIC_START + 4)          /* Timer 0 and 1 */
-#define IRQ_EB_TIMER2_3         (IRQ_EB_GIC_START + 5)          /* Timer 2 and 3 */
-#define IRQ_EB_GPIO0            (IRQ_EB_GIC_START + 6)          /* GPIO 0 */
-#define IRQ_EB_GPIO1            (IRQ_EB_GIC_START + 7)          /* GPIO 1 */
-#define IRQ_EB_GPIO2            (IRQ_EB_GIC_START + 8)          /* GPIO 2 */
-                                                                /* 9 reserved */
-#define IRQ_EB_RTC              (IRQ_EB_GIC_START + 10)         /* Real Time Clock */
-#define IRQ_EB_SSP              (IRQ_EB_GIC_START + 11)         /* Synchronous Serial Port */
-#define IRQ_EB_UART0            (IRQ_EB_GIC_START + 12)         /* UART 0 on development chip */
-#define IRQ_EB_UART1            (IRQ_EB_GIC_START + 13)         /* UART 1 on development chip */
-#define IRQ_EB_UART2            (IRQ_EB_GIC_START + 14)         /* UART 2 on development chip */
-#define IRQ_EB_UART3            (IRQ_EB_GIC_START + 15)         /* UART 3 on development chip */
-#define IRQ_EB_SCI              (IRQ_EB_GIC_START + 16)         /* Smart Card Interface */
-#define IRQ_EB_MMCI0A           (IRQ_EB_GIC_START + 17)         /* Multimedia Card 0A */
-#define IRQ_EB_MMCI0B           (IRQ_EB_GIC_START + 18)         /* Multimedia Card 0B */
-#define IRQ_EB_AACI             (IRQ_EB_GIC_START + 19)         /* Audio Codec */
-#define IRQ_EB_KMI0             (IRQ_EB_GIC_START + 20)         /* Keyboard/Mouse port 0 */
-#define IRQ_EB_KMI1             (IRQ_EB_GIC_START + 21)         /* Keyboard/Mouse port 1 */
-#define IRQ_EB_CHARLCD          (IRQ_EB_GIC_START + 22)         /* Character LCD */
-#define IRQ_EB_CLCD             (IRQ_EB_GIC_START + 23)         /* CLCD controller */
-#define IRQ_EB_DMA              (IRQ_EB_GIC_START + 24)         /* DMA controller */
-#define IRQ_EB_PWRFAIL          (IRQ_EB_GIC_START + 25)         /* Power failure */
-#define IRQ_EB_PISMO            (IRQ_EB_GIC_START + 26)         /* PISMO interface */
-#define IRQ_EB_DoC              (IRQ_EB_GIC_START + 27)         /* Disk on Chip memory controller */
-#define IRQ_EB_ETH              (IRQ_EB_GIC_START + 28)         /* Ethernet controller */
-#define IRQ_EB_USB              (IRQ_EB_GIC_START + 29)         /* USB controller */
-#define IRQ_EB_TSPEN            (IRQ_EB_GIC_START + 30)         /* Touchscreen pen */
-#define IRQ_EB_TSKPAD           (IRQ_EB_GIC_START + 31)         /* Touchscreen keypad */
-
-/*
- * RealView EB + ARM11MPCore interrupt sources (primary GIC on the core tile)
- */
-#define IRQ_EB11MP_AACI         (IRQ_EB_GIC_START + 0)
-#define IRQ_EB11MP_TIMER0_1     (IRQ_EB_GIC_START + 1)
-#define IRQ_EB11MP_TIMER2_3     (IRQ_EB_GIC_START + 2)
-#define IRQ_EB11MP_USB          (IRQ_EB_GIC_START + 3)
-#define IRQ_EB11MP_UART0        (IRQ_EB_GIC_START + 4)
-#define IRQ_EB11MP_UART1        (IRQ_EB_GIC_START + 5)
-#define IRQ_EB11MP_RTC          (IRQ_EB_GIC_START + 6)
-#define IRQ_EB11MP_KMI0         (IRQ_EB_GIC_START + 7)
-#define IRQ_EB11MP_KMI1         (IRQ_EB_GIC_START + 8)
-#define IRQ_EB11MP_ETH          (IRQ_EB_GIC_START + 9)
-#define IRQ_EB11MP_EB_IRQ1      (IRQ_EB_GIC_START + 10)         /* main GIC */
-#define IRQ_EB11MP_EB_IRQ2      (IRQ_EB_GIC_START + 11)         /* tile GIC */
-#define IRQ_EB11MP_EB_FIQ1      (IRQ_EB_GIC_START + 12)         /* main GIC */
-#define IRQ_EB11MP_EB_FIQ2      (IRQ_EB_GIC_START + 13)         /* tile GIC */
-#define IRQ_EB11MP_MMCI0A       (IRQ_EB_GIC_START + 14)
-#define IRQ_EB11MP_MMCI0B       (IRQ_EB_GIC_START + 15)
-
-#define IRQ_EB11MP_PMU_CPU0     (IRQ_EB_GIC_START + 17)
-#define IRQ_EB11MP_PMU_CPU1     (IRQ_EB_GIC_START + 18)
-#define IRQ_EB11MP_PMU_CPU2     (IRQ_EB_GIC_START + 19)
-#define IRQ_EB11MP_PMU_CPU3     (IRQ_EB_GIC_START + 20)
-#define IRQ_EB11MP_PMU_SCU0     (IRQ_EB_GIC_START + 21)
-#define IRQ_EB11MP_PMU_SCU1     (IRQ_EB_GIC_START + 22)
-#define IRQ_EB11MP_PMU_SCU2     (IRQ_EB_GIC_START + 23)
-#define IRQ_EB11MP_PMU_SCU3     (IRQ_EB_GIC_START + 24)
-#define IRQ_EB11MP_PMU_SCU4     (IRQ_EB_GIC_START + 25)
-#define IRQ_EB11MP_PMU_SCU5     (IRQ_EB_GIC_START + 26)
-#define IRQ_EB11MP_PMU_SCU6     (IRQ_EB_GIC_START + 27)
-#define IRQ_EB11MP_PMU_SCU7     (IRQ_EB_GIC_START + 28)
-
-#define IRQ_EB11MP_L220_EVENT   (IRQ_EB_GIC_START + 29)
-#define IRQ_EB11MP_L220_SLAVE   (IRQ_EB_GIC_START + 30)
-#define IRQ_EB11MP_L220_DECODE  (IRQ_EB_GIC_START + 31)
-
-#define IRQ_EB11MP_UART2        -1
-#define IRQ_EB11MP_UART3        -1
-#define IRQ_EB11MP_CLCD         -1
-#define IRQ_EB11MP_DMA          -1
-#define IRQ_EB11MP_WDOG         -1
-#define IRQ_EB11MP_GPIO0        -1
-#define IRQ_EB11MP_GPIO1        -1
-#define IRQ_EB11MP_GPIO2        -1
-#define IRQ_EB11MP_SCI          -1
-#define IRQ_EB11MP_SSP          -1
-
-#define NR_GIC_EB11MP           2
-
-/*
- * Only define NR_IRQS if less than NR_IRQS_EB
- */
-#define NR_IRQS_EB              (IRQ_EB_GIC_START + 96)
-
-#if defined(CONFIG_MACH_REALVIEW_EB) \
-        && (!defined(NR_IRQS) || (NR_IRQS < NR_IRQS_EB))
-#undef NR_IRQS
-#define NR_IRQS                 NR_IRQS_EB
-#endif
-
-#if defined(CONFIG_REALVIEW_EB_ARM11MP) \
-        && (!defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_EB11MP))
-#undef MAX_GIC_NR
-#define MAX_GIC_NR              NR_GIC_EB11MP
-#endif
-
-/*
- * Core tile identification (REALVIEW_SYS_PROCID)
- */
-#define REALVIEW_EB_PROC_MASK           0xFF000000
-#define REALVIEW_EB_PROC_ARM7TDMI       0x00000000
-#define REALVIEW_EB_PROC_ARM9           0x02000000
-#define REALVIEW_EB_PROC_ARM11          0x04000000
-#define REALVIEW_EB_PROC_ARM11MP        0x06000000
-
-#define check_eb_proc(proc_type)                                                \
-        ((readl(__io_address(REALVIEW_SYS_PROCID)) & REALVIEW_EB_PROC_MASK)     \
-         == proc_type)
-
-#ifdef CONFIG_REALVIEW_EB_ARM11MP
-#define core_tile_eb11mp()      check_eb_proc(REALVIEW_EB_PROC_ARM11MP)
-#else
-#define core_tile_eb11mp()      0
-#endif
-
-#endif  /* __ASM_ARCH_BOARD_EB_H */
diff --git a/include/asm-arm/arch-realview/board-pb1176.h b/include/asm-arm/arch-realview/board-pb1176.h
deleted file mode 100644
index 48ce9c833705..000000000000
--- a/include/asm-arm/arch-realview/board-pb1176.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * include/asm-arm/arch-realview/board-pb1176.h
- *
- * Copyright (C) 2008 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __ASM_ARCH_BOARD_PB1176_H
-#define __ASM_ARCH_BOARD_PB1176_H
-
-#include <asm/arch/platform.h>
-
-/*
- * Peripheral addresses
- */
-#define REALVIEW_PB1176_SCTL_BASE               0x10100000 /* System controller */
-#define REALVIEW_PB1176_SMC_BASE                0x10111000 /* SMC */
-#define REALVIEW_PB1176_DMC_BASE                0x10109000 /* DMC configuration */
-#define REALVIEW_PB1176_SDRAM67_BASE            0x70000000 /* SDRAM banks 6 and 7 */
-#define REALVIEW_PB1176_FLASH_BASE              0x30000000
-#define REALVIEW_PB1176_FLASH_SIZE              SZ_64M
-
-#define REALVIEW_PB1176_TIMER0_1_BASE           0x10104000 /* Timer 0 and 1 */
-#define REALVIEW_PB1176_TIMER2_3_BASE           0x10105000 /* Timer 2 and 3 */
-#define REALVIEW_PB1176_TIMER4_5_BASE           0x10106000 /* Timer 4 and 5 */
-#define REALVIEW_PB1176_WATCHDOG_BASE           0x10107000 /* watchdog interface */
-#define REALVIEW_PB1176_RTC_BASE                0x10108000 /* Real Time Clock */
-#define REALVIEW_PB1176_GPIO0_BASE              0x1010A000 /* GPIO port 0 */
-#define REALVIEW_PB1176_SSP_BASE                0x1010B000 /* Synchronous Serial Port */
-#define REALVIEW_PB1176_UART0_BASE              0x1010C000 /* UART 0 */
-#define REALVIEW_PB1176_UART1_BASE              0x1010D000 /* UART 1 */
-#define REALVIEW_PB1176_UART2_BASE              0x1010E000 /* UART 2 */
-#define REALVIEW_PB1176_UART3_BASE              0x1010F000 /* UART 3 */
-#define REALVIEW_PB1176_CLCD_BASE               0x10112000 /* CLCD */
-#define REALVIEW_PB1176_ETH_BASE                0x3A000000 /* Ethernet */
-#define REALVIEW_PB1176_USB_BASE                0x3B000000 /* USB */
-
-/*
- * PCI regions
- */
-#define REALVIEW_PB1176_PCI_BASE                0x60000000 /* PCI self config */
-#define REALVIEW_PB1176_PCI_CFG_BASE            0x61000000 /* PCI config */
-#define REALVIEW_PB1176_PCI_IO_BASE0            0x62000000 /* PCI IO region */
-#define REALVIEW_PB1176_PCI_MEM_BASE0           0x63000000 /* Memory region 1 */
-#define REALVIEW_PB1176_PCI_MEM_BASE1           0x64000000 /* Memory region 2 */
-#define REALVIEW_PB1176_PCI_MEM_BASE2           0x68000000 /* Memory region 3 */
-
-#define REALVIEW_PB1176_PCI_BASE_SIZE           0x01000000 /* 16MB */
-#define REALVIEW_PB1176_PCI_CFG_BASE_SIZE       0x01000000 /* 16MB */
-#define REALVIEW_PB1176_PCI_IO_BASE0_SIZE       0x01000000 /* 16MB */
-#define REALVIEW_PB1176_PCI_MEM_BASE0_SIZE      0x01000000 /* 16MB */
-#define REALVIEW_PB1176_PCI_MEM_BASE1_SIZE      0x04000000 /* 64MB */
-#define REALVIEW_PB1176_PCI_MEM_BASE2_SIZE      0x08000000 /* 128MB */
-
-#define REALVIEW_DC1176_GIC_CPU_BASE            0x10120000 /* GIC CPU interface, on devchip */
-#define REALVIEW_DC1176_GIC_DIST_BASE           0x10121000 /* GIC distributor, on devchip */
-#define REALVIEW_PB1176_GIC_CPU_BASE            0x10040000 /* GIC CPU interface, on FPGA */
-#define REALVIEW_PB1176_GIC_DIST_BASE           0x10041000 /* GIC distributor, on FPGA */
-#define REALVIEW_PB1176_L220_BASE               0x10110000 /* L220 registers */
-
-/*
- * Irqs
- */
-#define IRQ_DC1176_GIC_START                    32
-#define IRQ_PB1176_GIC_START                    64
-
-/*
- * ARM1176 DevChip interrupt sources (primary GIC)
- */
-#define IRQ_DC1176_WATCHDOG     (IRQ_DC1176_GIC_START + 0)      /* Watchdog timer */
-#define IRQ_DC1176_SOFTINT      (IRQ_DC1176_GIC_START + 1)      /* Software interrupt */
-#define IRQ_DC1176_COMMRx       (IRQ_DC1176_GIC_START + 2)      /* Debug Comm Rx interrupt */
-#define IRQ_DC1176_COMMTx       (IRQ_DC1176_GIC_START + 3)      /* Debug Comm Tx interrupt */
-#define IRQ_DC1176_TIMER0       (IRQ_DC1176_GIC_START + 8)      /* Timer 0 */
-#define IRQ_DC1176_TIMER1       (IRQ_DC1176_GIC_START + 9)      /* Timer 1 */
-#define IRQ_DC1176_TIMER2       (IRQ_DC1176_GIC_START + 10)     /* Timer 2 */
-#define IRQ_DC1176_APC          (IRQ_DC1176_GIC_START + 11)
-#define IRQ_DC1176_IEC          (IRQ_DC1176_GIC_START + 12)
-#define IRQ_DC1176_L2CC         (IRQ_DC1176_GIC_START + 13)
-#define IRQ_DC1176_RTC          (IRQ_DC1176_GIC_START + 14)
-#define IRQ_DC1176_CLCD         (IRQ_DC1176_GIC_START + 15)     /* CLCD controller */
-#define IRQ_DC1176_UART0        (IRQ_DC1176_GIC_START + 18)     /* UART 0 on development chip */
-#define IRQ_DC1176_UART1        (IRQ_DC1176_GIC_START + 19)     /* UART 1 on development chip */
-#define IRQ_DC1176_UART2        (IRQ_DC1176_GIC_START + 20)     /* UART 2 on development chip */
-#define IRQ_DC1176_UART3        (IRQ_DC1176_GIC_START + 21)     /* UART 3 on development chip */
-
-#define IRQ_DC1176_PB_IRQ2      (IRQ_DC1176_GIC_START + 30)     /* tile GIC */
-#define IRQ_DC1176_PB_IRQ1      (IRQ_DC1176_GIC_START + 31)     /* main GIC */
-
-/*
- * RealView PB1176 interrupt sources (secondary GIC)
- */
-#define IRQ_PB1176_MMCI0A       (IRQ_PB1176_GIC_START + 1)      /* Multimedia Card 0A */
-#define IRQ_PB1176_MMCI0B       (IRQ_PB1176_GIC_START + 2)      /* Multimedia Card 0A */
-#define IRQ_PB1176_KMI0         (IRQ_PB1176_GIC_START + 3)      /* Keyboard/Mouse port 0 */
-#define IRQ_PB1176_KMI1         (IRQ_PB1176_GIC_START + 4)      /* Keyboard/Mouse port 1 */
-#define IRQ_PB1176_SCI          (IRQ_PB1176_GIC_START + 5)
-#define IRQ_PB1176_UART4        (IRQ_PB1176_GIC_START + 6)      /* UART 4 on baseboard */
-#define IRQ_PB1176_CHARLCD      (IRQ_PB1176_GIC_START + 7)      /* Character LCD */
-#define IRQ_PB1176_GPIO1        (IRQ_PB1176_GIC_START + 8)
-#define IRQ_PB1176_GPIO2        (IRQ_PB1176_GIC_START + 9)
-#define IRQ_PB1176_ETH          (IRQ_PB1176_GIC_START + 10)     /* Ethernet controller */
-#define IRQ_PB1176_USB          (IRQ_PB1176_GIC_START + 11)     /* USB controller */
-
-#define IRQ_PB1176_PISMO        (IRQ_PB1176_GIC_START + 16)
-
-#define IRQ_PB1176_AACI         (IRQ_PB1176_GIC_START + 19)     /* Audio Codec */
-
-#define IRQ_PB1176_TIMER0_1     (IRQ_PB1176_GIC_START + 22)
-#define IRQ_PB1176_TIMER2_3     (IRQ_PB1176_GIC_START + 23)
-#define IRQ_PB1176_DMAC         (IRQ_PB1176_GIC_START + 24)     /* DMA controller */
-#define IRQ_PB1176_RTC          (IRQ_PB1176_GIC_START + 25)     /* Real Time Clock */
-
-#define IRQ_PB1176_GPIO0        -1
-#define IRQ_PB1176_SSP          -1
-#define IRQ_PB1176_SCTL         -1
-
-#define NR_GIC_PB1176           2
-
-/*
- * Only define NR_IRQS if less than NR_IRQS_PB1176
- */
-#define NR_IRQS_PB1176          (IRQ_DC1176_GIC_START + 96)
-
-#if defined(CONFIG_MACH_REALVIEW_PB1176)
-
-#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PB1176)
-#undef NR_IRQS
-#define NR_IRQS                 NR_IRQS_PB1176
-#endif
-
-#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PB1176)
-#undef MAX_GIC_NR
-#define MAX_GIC_NR              NR_GIC_PB1176
-#endif
-
-#endif  /* CONFIG_MACH_REALVIEW_PB1176 */
-
-#endif  /* __ASM_ARCH_BOARD_PB1176_H */
diff --git a/include/asm-arm/arch-realview/board-pb11mp.h b/include/asm-arm/arch-realview/board-pb11mp.h
deleted file mode 100644
index a1294d915fa8..000000000000
--- a/include/asm-arm/arch-realview/board-pb11mp.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * include/asm-arm/arch-realview/board-pb11mp.h
- *
- * Copyright (C) 2008 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __ASM_ARCH_BOARD_PB11MP_H
-#define __ASM_ARCH_BOARD_PB11MP_H
-
-#include <asm/arch/platform.h>
-
-/*
- * Peripheral addresses
- */
-#define REALVIEW_PB11MP_UART0_BASE              0x10009000      /* UART 0 */
-#define REALVIEW_PB11MP_UART1_BASE              0x1000A000      /* UART 1 */
-#define REALVIEW_PB11MP_UART2_BASE              0x1000B000      /* UART 2 */
-#define REALVIEW_PB11MP_UART3_BASE              0x1000C000      /* UART 3 */
-#define REALVIEW_PB11MP_SSP_BASE                0x1000D000      /* Synchronous Serial Port */
-#define REALVIEW_PB11MP_WATCHDOG0_BASE          0x1000F000      /* Watchdog 0 */
-#define REALVIEW_PB11MP_WATCHDOG_BASE           0x10010000      /* watchdog interface */
-#define REALVIEW_PB11MP_TIMER0_1_BASE           0x10011000      /* Timer 0 and 1 */
-#define REALVIEW_PB11MP_TIMER2_3_BASE           0x10012000      /* Timer 2 and 3 */
-#define REALVIEW_PB11MP_GPIO0_BASE              0x10013000      /* GPIO port 0 */
-#define REALVIEW_PB11MP_RTC_BASE                0x10017000      /* Real Time Clock */
-#define REALVIEW_PB11MP_TIMER4_5_BASE           0x10018000      /* Timer 4/5 */
-#define REALVIEW_PB11MP_TIMER6_7_BASE           0x10019000      /* Timer 6/7 */
-#define REALVIEW_PB11MP_SCTL_BASE               0x1001A000      /* System Controller */
-#define REALVIEW_PB11MP_CLCD_BASE               0x10020000      /* CLCD */
-#define REALVIEW_PB11MP_ONB_SRAM_BASE           0x10060000      /* On-board SRAM */
-#define REALVIEW_PB11MP_DMC_BASE                0x100E0000      /* DMC configuration */
-#define REALVIEW_PB11MP_SMC_BASE                0x100E1000      /* SMC configuration */
-#define REALVIEW_PB11MP_CAN_BASE                0x100E2000      /* CAN bus */
-#define REALVIEW_PB11MP_CF_BASE                 0x18000000      /* Compact flash */
-#define REALVIEW_PB11MP_CF_MEM_BASE             0x18003000      /* SMC for Compact flash */
-#define REALVIEW_PB11MP_GIC_CPU_BASE            0x1E000000      /* Generic interrupt controller CPU interface */
-#define REALVIEW_PB11MP_FLASH0_BASE             0x40000000
-#define REALVIEW_PB11MP_FLASH0_SIZE             SZ_64M
-#define REALVIEW_PB11MP_FLASH1_BASE             0x44000000
-#define REALVIEW_PB11MP_FLASH1_SIZE             SZ_64M
-#define REALVIEW_PB11MP_ETH_BASE                0x4E000000      /* Ethernet */
-#define REALVIEW_PB11MP_USB_BASE                0x4F000000      /* USB */
-#define REALVIEW_PB11MP_GIC_DIST_BASE           0x1E001000      /* Generic interrupt controller distributor */
-#define REALVIEW_PB11MP_LT_BASE                 0xC0000000      /* Logic Tile expansion */
-#define REALVIEW_PB11MP_SDRAM6_BASE             0x70000000      /* SDRAM bank 6 256MB */
-#define REALVIEW_PB11MP_SDRAM7_BASE             0x80000000      /* SDRAM bank 7 256MB */
-
-#define REALVIEW_PB11MP_SYS_PLD_CTRL1           0x74
-
-/*
- * PB11MPCore PCI regions
- */
-#define REALVIEW_PB11MP_PCI_BASE                0x90040000      /* PCI-X Unit base */
-#define REALVIEW_PB11MP_PCI_IO_BASE             0x90050000      /* IO Region on AHB */
-#define REALVIEW_PB11MP_PCI_MEM_BASE            0xA0000000      /* MEM Region on AHB */
-
-#define REALVIEW_PB11MP_PCI_BASE_SIZE           0x10000         /* 16 Kb */
-#define REALVIEW_PB11MP_PCI_IO_SIZE             0x1000          /* 4 Kb */
-#define REALVIEW_PB11MP_PCI_MEM_SIZE            0x20000000      /* 512 MB */
-
-/*
- * Testchip peripheral and fpga gic regions
- */
-#define REALVIEW_TC11MP_SCU_BASE                0x1F000000      /* IRQ, Test chip */
-#define REALVIEW_TC11MP_GIC_CPU_BASE            0x1F000100      /* Test chip interrupt controller CPU interface */
-#define REALVIEW_TC11MP_TWD_BASE                0x1F000700
-#define REALVIEW_TC11MP_TWD_SIZE                0x00000100
-#define REALVIEW_TC11MP_GIC_DIST_BASE           0x1F001000      /* Test chip interrupt controller distributor */
-#define REALVIEW_TC11MP_L220_BASE               0x1F002000      /* L220 registers */
-
-/*
- * Irqs
- */
-#define IRQ_TC11MP_GIC_START                    32
-#define IRQ_PB11MP_GIC_START                    64
-
-/*
- * ARM11MPCore test chip interrupt sources (primary GIC on the test chip)
- */
-#define IRQ_TC11MP_AACI         (IRQ_TC11MP_GIC_START + 0)
-#define IRQ_TC11MP_TIMER0_1     (IRQ_TC11MP_GIC_START + 1)
-#define IRQ_TC11MP_TIMER2_3     (IRQ_TC11MP_GIC_START + 2)
-#define IRQ_TC11MP_USB          (IRQ_TC11MP_GIC_START + 3)
-#define IRQ_TC11MP_UART0        (IRQ_TC11MP_GIC_START + 4)
-#define IRQ_TC11MP_UART1        (IRQ_TC11MP_GIC_START + 5)
-#define IRQ_TC11MP_RTC          (IRQ_TC11MP_GIC_START + 6)
-#define IRQ_TC11MP_KMI0         (IRQ_TC11MP_GIC_START + 7)
-#define IRQ_TC11MP_KMI1         (IRQ_TC11MP_GIC_START + 8)
-#define IRQ_TC11MP_ETH          (IRQ_TC11MP_GIC_START + 9)
-#define IRQ_TC11MP_PB_IRQ1      (IRQ_TC11MP_GIC_START + 10)             /* main GIC */
-#define IRQ_TC11MP_PB_IRQ2      (IRQ_TC11MP_GIC_START + 11)             /* tile GIC */
-#define IRQ_TC11MP_PB_FIQ1      (IRQ_TC11MP_GIC_START + 12)             /* main GIC */
-#define IRQ_TC11MP_PB_FIQ2      (IRQ_TC11MP_GIC_START + 13)             /* tile GIC */
-#define IRQ_TC11MP_MMCI0A       (IRQ_TC11MP_GIC_START + 14)
-#define IRQ_TC11MP_MMCI0B       (IRQ_TC11MP_GIC_START + 15)
-
-#define IRQ_TC11MP_PMU_CPU0     (IRQ_TC11MP_GIC_START + 17)
-#define IRQ_TC11MP_PMU_CPU1     (IRQ_TC11MP_GIC_START + 18)
-#define IRQ_TC11MP_PMU_CPU2     (IRQ_TC11MP_GIC_START + 19)
-#define IRQ_TC11MP_PMU_CPU3     (IRQ_TC11MP_GIC_START + 20)
-#define IRQ_TC11MP_PMU_SCU0     (IRQ_TC11MP_GIC_START + 21)
-#define IRQ_TC11MP_PMU_SCU1     (IRQ_TC11MP_GIC_START + 22)
-#define IRQ_TC11MP_PMU_SCU2     (IRQ_TC11MP_GIC_START + 23)
-#define IRQ_TC11MP_PMU_SCU3     (IRQ_TC11MP_GIC_START + 24)
-#define IRQ_TC11MP_PMU_SCU4     (IRQ_TC11MP_GIC_START + 25)
-#define IRQ_TC11MP_PMU_SCU5     (IRQ_TC11MP_GIC_START + 26)
-#define IRQ_TC11MP_PMU_SCU6     (IRQ_TC11MP_GIC_START + 27)
-#define IRQ_TC11MP_PMU_SCU7     (IRQ_TC11MP_GIC_START + 28)
-
-#define IRQ_TC11MP_L220_EVENT   (IRQ_TC11MP_GIC_START + 29)
-#define IRQ_TC11MP_L220_SLAVE   (IRQ_TC11MP_GIC_START + 30)
-#define IRQ_TC11MP_L220_DECODE  (IRQ_TC11MP_GIC_START + 31)
-
-/*
- * RealView PB11MPCore GIC interrupt sources (secondary GIC on the board)
- */
-#define IRQ_PB11MP_WATCHDOG     (IRQ_PB11MP_GIC_START + 0)      /* Watchdog timer */
-#define IRQ_PB11MP_SOFT         (IRQ_PB11MP_GIC_START + 1)      /* Software interrupt */
-#define IRQ_PB11MP_COMMRx       (IRQ_PB11MP_GIC_START + 2)      /* Debug Comm Rx interrupt */
-#define IRQ_PB11MP_COMMTx       (IRQ_PB11MP_GIC_START + 3)      /* Debug Comm Tx interrupt */
-#define IRQ_PB11MP_GPIO0        (IRQ_PB11MP_GIC_START + 6)      /* GPIO 0 */
-#define IRQ_PB11MP_GPIO1        (IRQ_PB11MP_GIC_START + 7)      /* GPIO 1 */
-#define IRQ_PB11MP_GPIO2        (IRQ_PB11MP_GIC_START + 8)      /* GPIO 2 */
-                                                                /* 9 reserved */
-#define IRQ_PB11MP_RTC_GIC1     (IRQ_PB11MP_GIC_START + 10)     /* Real Time Clock */
-#define IRQ_PB11MP_SSP          (IRQ_PB11MP_GIC_START + 11)     /* Synchronous Serial Port */
-#define IRQ_PB11MP_UART0_GIC1   (IRQ_PB11MP_GIC_START + 12)     /* UART 0 on development chip */
-#define IRQ_PB11MP_UART1_GIC1   (IRQ_PB11MP_GIC_START + 13)     /* UART 1 on development chip */
-#define IRQ_PB11MP_UART2        (IRQ_PB11MP_GIC_START + 14)     /* UART 2 on development chip */
-#define IRQ_PB11MP_UART3        (IRQ_PB11MP_GIC_START + 15)     /* UART 3 on development chip */
-#define IRQ_PB11MP_SCI          (IRQ_PB11MP_GIC_START + 16)     /* Smart Card Interface */
-#define IRQ_PB11MP_MMCI0A_GIC1  (IRQ_PB11MP_GIC_START + 17)     /* Multimedia Card 0A */
-#define IRQ_PB11MP_MMCI0B_GIC1  (IRQ_PB11MP_GIC_START + 18)     /* Multimedia Card 0B */
-#define IRQ_PB11MP_AACI_GIC1    (IRQ_PB11MP_GIC_START + 19)     /* Audio Codec */
-#define IRQ_PB11MP_KMI0_GIC1    (IRQ_PB11MP_GIC_START + 20)     /* Keyboard/Mouse port 0 */
-#define IRQ_PB11MP_KMI1_GIC1    (IRQ_PB11MP_GIC_START + 21)     /* Keyboard/Mouse port 1 */
-#define IRQ_PB11MP_CHARLCD      (IRQ_PB11MP_GIC_START + 22)     /* Character LCD */
-#define IRQ_PB11MP_CLCD         (IRQ_PB11MP_GIC_START + 23)     /* CLCD controller */
-#define IRQ_PB11MP_DMAC         (IRQ_PB11MP_GIC_START + 24)     /* DMA controller */
-#define IRQ_PB11MP_PWRFAIL      (IRQ_PB11MP_GIC_START + 25)     /* Power failure */
-#define IRQ_PB11MP_PISMO        (IRQ_PB11MP_GIC_START + 26)     /* PISMO interface */
-#define IRQ_PB11MP_DoC          (IRQ_PB11MP_GIC_START + 27)     /* Disk on Chip memory controller */
-#define IRQ_PB11MP_ETH_GIC1     (IRQ_PB11MP_GIC_START + 28)     /* Ethernet controller */
-#define IRQ_PB11MP_USB_GIC1     (IRQ_PB11MP_GIC_START + 29)     /* USB controller */
-#define IRQ_PB11MP_TSPEN        (IRQ_PB11MP_GIC_START + 30)     /* Touchscreen pen */
-#define IRQ_PB11MP_TSKPAD       (IRQ_PB11MP_GIC_START + 31)     /* Touchscreen keypad */
-
-#define IRQ_PB11MP_SMC          -1
-#define IRQ_PB11MP_SCTL         -1
-
-#define NR_GIC_PB11MP           2
-
-/*
- * Only define NR_IRQS if less than NR_IRQS_PB11MP
- */
-#define NR_IRQS_PB11MP          (IRQ_TC11MP_GIC_START + 96)
-
-#if defined(CONFIG_MACH_REALVIEW_PB11MP)
-
-#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PB11MP)
-#undef NR_IRQS
-#define NR_IRQS                 NR_IRQS_PB11MP
-#endif
-
-#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PB11MP)
-#undef MAX_GIC_NR
-#define MAX_GIC_NR              NR_GIC_PB11MP
-#endif
-
-#endif  /* CONFIG_MACH_REALVIEW_PB11MP */
-
-#endif  /* __ASM_ARCH_BOARD_PB11MP_H */
diff --git a/include/asm-arm/arch-realview/debug-macro.S b/include/asm-arm/arch-realview/debug-macro.S
deleted file mode 100644
index c8c860c3c26e..000000000000
--- a/include/asm-arm/arch-realview/debug-macro.S
+++ /dev/null
@@ -1,22 +0,0 @@
-/* linux/include/asm-arm/arch-realview/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-                .macro  addruart,rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx,      #0x10000000
-                movne   \rx,      #0xf0000000   @ virtual base
-                orr     \rx, \rx, #0x00009000
-                .endm
-
-#include <asm/hardware/debug-pl01x.S>
diff --git a/include/asm-arm/arch-realview/dma.h b/include/asm-arm/arch-realview/dma.h
deleted file mode 100644
index 8342e3f9d6ec..000000000000
--- a/include/asm-arm/arch-realview/dma.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-realview/dma.h
- *
- *  Copyright (C) 2003 ARM Limited.
- *  Copyright (C) 1997,1998 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
diff --git a/include/asm-arm/arch-realview/entry-macro.S b/include/asm-arm/arch-realview/entry-macro.S
deleted file mode 100644
index 31a39a7cdaa9..000000000000
--- a/include/asm-arm/arch-realview/entry-macro.S
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * include/asm-arm/arch-realview/entry-macro.S
- *
- * Low-level IRQ helper macros for RealView platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <asm/arch/hardware.h>
-#include <asm/hardware/gic.h>
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  get_irqnr_preamble, base, tmp
-                ldr     \base, =gic_cpu_base_addr
-                ldr     \base, [\base]
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
-                /*
-                 * The interrupt numbering scheme is defined in the
-                 * interrupt controller spec.  To wit:
-                 *
-                 * Interrupts 0-15 are IPI
-                 * 16-28 are reserved
-                 * 29-31 are local.  We allow 30 to be used for the watchdog.
-                 * 32-1020 are global
-                 * 1021-1022 are reserved
-                 * 1023 is "spurious" (no interrupt)
-                 *
-                 * For now, we ignore all local interrupts so only return an interrupt if it's
-                 * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
-                 *
-                 * A simple read from the controller will tell us the number of the highest
-                 * priority enabled interrupt.  We then just need to check whether it is in the
-                 * valid range for an IRQ (30-1020 inclusive).
-                 */
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-
-                ldr     \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
-
-                ldr     \tmp, =1021
-
-                bic     \irqnr, \irqstat, #0x1c00
-
-                cmp     \irqnr, #29
-                cmpcc   \irqnr, \irqnr
-                cmpne   \irqnr, \tmp
-                cmpcs   \irqnr, \irqnr
-
-                .endm
-
-                /* We assume that irqstat (the raw value of the IRQ acknowledge
-                 * register) is preserved from the macro above.
-                 * If there is an IPI, we immediately signal end of interrupt on the
-                 * controller, since this requires the original irqstat value which
-                 * we won't easily be able to recreate later.
-                 */
-
-                .macro test_for_ipi, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                cmp     \irqnr, #16
-                strcc   \irqstat, [\base, #GIC_CPU_EOI]
-                cmpcs   \irqnr, \irqnr
-                .endm
-
-                /* As above, this assumes that irqstat and base are preserved.. */
-
-                .macro test_for_ltirq, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                mov     \tmp, #0
-                cmp     \irqnr, #29
-                moveq   \tmp, #1
-                streq   \irqstat, [\base, #GIC_CPU_EOI]
-                cmp     \tmp, #0
-                .endm
diff --git a/include/asm-arm/arch-realview/hardware.h b/include/asm-arm/arch-realview/hardware.h
deleted file mode 100644
index 1ee8313ceb6a..000000000000
--- a/include/asm-arm/arch-realview/hardware.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-realview/hardware.h
- *
- *  This file contains the hardware definitions of the RealView boards.
- *
- *  Copyright (C) 2003 ARM Limited.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <asm/sizes.h>
-
-/* macro to get at IO space when running virtually */
-#define IO_ADDRESS(x)           (((x) & 0x0fffffff) + 0xf0000000)
-#define __io_address(n)         __io(IO_ADDRESS(n))
-
-#endif
diff --git a/include/asm-arm/arch-realview/io.h b/include/asm-arm/arch-realview/io.h
deleted file mode 100644
index c70f1dfbe135..000000000000
--- a/include/asm-arm/arch-realview/io.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-realview/io.h
- *
- *  Copyright (C) 2003 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-static inline void __iomem *__io(unsigned long addr)
-{
-        return (void __iomem *)addr;
-}
-
-#define __io(a)                 __io(a)
-#define __mem_pci(a)            (a)
-
-#endif
diff --git a/include/asm-arm/arch-realview/irqs.h b/include/asm-arm/arch-realview/irqs.h
deleted file mode 100644
index ccbac59235c6..000000000000
--- a/include/asm-arm/arch-realview/irqs.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-realview/irqs.h
- *
- *  Copyright (C) 2003 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H
-
-#include <asm/arch/board-eb.h>
-#include <asm/arch/board-pb11mp.h>
-#include <asm/arch/board-pb1176.h>
-
-#define IRQ_LOCALTIMER          29
-#define IRQ_LOCALWDOG           30
-
-#define IRQ_GIC_START           32
-
-#ifndef NR_IRQS
-#error "NR_IRQS not defined by the board-specific files"
-#endif
-
-#endif
diff --git a/include/asm-arm/arch-realview/memory.h b/include/asm-arm/arch-realview/memory.h
deleted file mode 100644
index ed370abb638f..000000000000
--- a/include/asm-arm/arch-realview/memory.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-realview/memory.h
- *
- *  Copyright (C) 2003 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-/*
- * Physical DRAM offset.
- */
-#define PHYS_OFFSET             UL(0x00000000)
-
-/*
- * Virtual view <-> DMA view memory address translations
- * virt_to_bus: Used to translate the virtual address to an
- *              address suitable to be passed to set_dma_addr
- * bus_to_virt: Used to convert an address for DMA operations
- *              to an address that the kernel can use.
- */
-#define __virt_to_bus(x)        ((x) - PAGE_OFFSET)
-#define __bus_to_virt(x)        ((x) + PAGE_OFFSET)
-
-#endif
diff --git a/include/asm-arm/arch-realview/platform.h b/include/asm-arm/arch-realview/platform.h
deleted file mode 100644
index 424c0aaf46a0..000000000000
--- a/include/asm-arm/arch-realview/platform.h
+++ /dev/null
@@ -1,293 +0,0 @@
-/*
- * linux/include/asm-arm/arch-realview/platform.h
- *
- * Copyright (c) ARM Limited 2003.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __ASM_ARCH_PLATFORM_H
-#define __ASM_ARCH_PLATFORM_H
-
-/*
- * Memory definitions
- */
-#define REALVIEW_BOOT_ROM_LO          0x30000000                /* DoC Base (64Mb)...*/
-#define REALVIEW_BOOT_ROM_HI          0x30000000
-#define REALVIEW_BOOT_ROM_BASE        REALVIEW_BOOT_ROM_HI       /*  Normal position */
-#define REALVIEW_BOOT_ROM_SIZE        SZ_64M
-
-#define REALVIEW_SSRAM_BASE           /* REALVIEW_SSMC_BASE ? */
-#define REALVIEW_SSRAM_SIZE           SZ_2M
-
-/* 
- *  SDRAM
- */
-#define REALVIEW_SDRAM_BASE           0x00000000
-
-/* 
- *  Logic expansion modules
- * 
- */
-
-
-/* ------------------------------------------------------------------------
- *  RealView Registers
- * ------------------------------------------------------------------------
- * 
- */
-#define REALVIEW_SYS_ID_OFFSET               0x00
-#define REALVIEW_SYS_SW_OFFSET               0x04
-#define REALVIEW_SYS_LED_OFFSET              0x08
-#define REALVIEW_SYS_OSC0_OFFSET             0x0C
-
-#define REALVIEW_SYS_OSC1_OFFSET             0x10
-#define REALVIEW_SYS_OSC2_OFFSET             0x14
-#define REALVIEW_SYS_OSC3_OFFSET             0x18
-#define REALVIEW_SYS_OSC4_OFFSET             0x1C       /* OSC1 for RealView/AB */
-
-#define REALVIEW_SYS_LOCK_OFFSET             0x20
-#define REALVIEW_SYS_100HZ_OFFSET            0x24
-#define REALVIEW_SYS_CFGDATA1_OFFSET         0x28
-#define REALVIEW_SYS_CFGDATA2_OFFSET         0x2C
-#define REALVIEW_SYS_FLAGS_OFFSET            0x30
-#define REALVIEW_SYS_FLAGSSET_OFFSET         0x30
-#define REALVIEW_SYS_FLAGSCLR_OFFSET         0x34
-#define REALVIEW_SYS_NVFLAGS_OFFSET          0x38
-#define REALVIEW_SYS_NVFLAGSSET_OFFSET       0x38
-#define REALVIEW_SYS_NVFLAGSCLR_OFFSET       0x3C
-#define REALVIEW_SYS_RESETCTL_OFFSET         0x40
-#define REALVIEW_SYS_PCICTL_OFFSET           0x44
-#define REALVIEW_SYS_MCI_OFFSET              0x48
-#define REALVIEW_SYS_FLASH_OFFSET            0x4C
-#define REALVIEW_SYS_CLCD_OFFSET             0x50
-#define REALVIEW_SYS_CLCDSER_OFFSET          0x54
-#define REALVIEW_SYS_BOOTCS_OFFSET           0x58
-#define REALVIEW_SYS_24MHz_OFFSET            0x5C
-#define REALVIEW_SYS_MISC_OFFSET             0x60
-#define REALVIEW_SYS_IOSEL_OFFSET            0x70
-#define REALVIEW_SYS_PROCID_OFFSET           0x84
-#define REALVIEW_SYS_TEST_OSC0_OFFSET        0xC0
-#define REALVIEW_SYS_TEST_OSC1_OFFSET        0xC4
-#define REALVIEW_SYS_TEST_OSC2_OFFSET        0xC8
-#define REALVIEW_SYS_TEST_OSC3_OFFSET        0xCC
-#define REALVIEW_SYS_TEST_OSC4_OFFSET        0xD0
-
-#define REALVIEW_SYS_BASE                    0x10000000
-#define REALVIEW_SYS_ID                      (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET)
-#define REALVIEW_SYS_SW                      (REALVIEW_SYS_BASE + REALVIEW_SYS_SW_OFFSET)
-#define REALVIEW_SYS_LED                     (REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET)
-#define REALVIEW_SYS_OSC0                    (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC0_OFFSET)
-#define REALVIEW_SYS_OSC1                    (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC1_OFFSET)
-
-#define REALVIEW_SYS_LOCK                    (REALVIEW_SYS_BASE + REALVIEW_SYS_LOCK_OFFSET)
-#define REALVIEW_SYS_100HZ                   (REALVIEW_SYS_BASE + REALVIEW_SYS_100HZ_OFFSET)
-#define REALVIEW_SYS_CFGDATA1                (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA1_OFFSET)
-#define REALVIEW_SYS_CFGDATA2                (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA2_OFFSET)
-#define REALVIEW_SYS_FLAGS                   (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGS_OFFSET)
-#define REALVIEW_SYS_FLAGSSET                (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSSET_OFFSET)
-#define REALVIEW_SYS_FLAGSCLR                (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSCLR_OFFSET)
-#define REALVIEW_SYS_NVFLAGS                 (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGS_OFFSET)
-#define REALVIEW_SYS_NVFLAGSSET              (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSSET_OFFSET)
-#define REALVIEW_SYS_NVFLAGSCLR              (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSCLR_OFFSET)
-#define REALVIEW_SYS_RESETCTL                (REALVIEW_SYS_BASE + REALVIEW_SYS_RESETCTL_OFFSET)
-#define REALVIEW_SYS_PCICTL                  (REALVIEW_SYS_BASE + REALVIEW_SYS_PCICTL_OFFSET)
-#define REALVIEW_SYS_MCI                     (REALVIEW_SYS_BASE + REALVIEW_SYS_MCI_OFFSET)
-#define REALVIEW_SYS_FLASH                   (REALVIEW_SYS_BASE + REALVIEW_SYS_FLASH_OFFSET)
-#define REALVIEW_SYS_CLCD                    (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCD_OFFSET)
-#define REALVIEW_SYS_CLCDSER                 (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCDSER_OFFSET)
-#define REALVIEW_SYS_BOOTCS                  (REALVIEW_SYS_BASE + REALVIEW_SYS_BOOTCS_OFFSET)
-#define REALVIEW_SYS_24MHz                   (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET)
-#define REALVIEW_SYS_MISC                    (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET)
-#define REALVIEW_SYS_IOSEL                   (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET)
-#define REALVIEW_SYS_PROCID                  (REALVIEW_SYS_BASE + REALVIEW_SYS_PROCID_OFFSET)
-#define REALVIEW_SYS_TEST_OSC0               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET)
-#define REALVIEW_SYS_TEST_OSC1               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET)
-#define REALVIEW_SYS_TEST_OSC2               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET)
-#define REALVIEW_SYS_TEST_OSC3               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC3_OFFSET)
-#define REALVIEW_SYS_TEST_OSC4               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC4_OFFSET)
-
-/* 
- * Values for REALVIEW_SYS_RESET_CTRL
- */
-#define REALVIEW_SYS_CTRL_RESET_CONFIGCLR    0x01
-#define REALVIEW_SYS_CTRL_RESET_CONFIGINIT   0x02
-#define REALVIEW_SYS_CTRL_RESET_DLLRESET     0x03
-#define REALVIEW_SYS_CTRL_RESET_PLLRESET     0x04
-#define REALVIEW_SYS_CTRL_RESET_POR          0x05
-#define REALVIEW_SYS_CTRL_RESET_DoC          0x06
-
-#define REALVIEW_SYS_CTRL_LED         (1 << 0)
-
-
-/* ------------------------------------------------------------------------
- *  RealView control registers
- * ------------------------------------------------------------------------
- */
-
-/* 
- * REALVIEW_IDFIELD
- *
- * 31:24 = manufacturer (0x41 = ARM)
- * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus)
- * 15:12 = FPGA (0x3 = XVC600 or XVC600E)
- * 11:4  = build value
- * 3:0   = revision number (0x1 = rev B (AHB))
- */
-
-/*
- * REALVIEW_SYS_LOCK
- *     control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL, 
- *     SYS_CLD, SYS_BOOTCS
- */
-#define REALVIEW_SYS_LOCK_LOCKED    (1 << 16)
-#define REALVIEW_SYS_LOCKVAL_MASK       0xFFFF          /* write 0xA05F to enable write access */
-
-/*
- * REALVIEW_SYS_FLASH
- */
-#define REALVIEW_FLASHPROG_FLVPPEN      (1 << 0)        /* Enable writing to flash */
-
-/*
- * REALVIEW_INTREG
- *     - used to acknowledge and control MMCI and UART interrupts 
- */
-#define REALVIEW_INTREG_WPROT        0x00    /* MMC protection status (no interrupt generated) */
-#define REALVIEW_INTREG_RI0          0x01    /* Ring indicator UART0 is asserted,              */
-#define REALVIEW_INTREG_CARDIN       0x08    /* MMCI card in detect                            */
-                                                /* write 1 to acknowledge and clear               */
-#define REALVIEW_INTREG_RI1          0x02    /* Ring indicator UART1 is asserted,              */
-#define REALVIEW_INTREG_CARDINSERT   0x03    /* Signal insertion of MMC card                   */
-
-/*
- * RealView common peripheral addresses
- */
-#define REALVIEW_SCTL_BASE            0x10001000        /* System controller */
-#define REALVIEW_I2C_BASE             0x10002000        /* I2C control */
-#define REALVIEW_AACI_BASE            0x10004000        /* Audio */
-#define REALVIEW_MMCI0_BASE           0x10005000        /* MMC interface */
-#define REALVIEW_KMI0_BASE            0x10006000        /* KMI interface */
-#define REALVIEW_KMI1_BASE            0x10007000        /* KMI 2nd interface */
-#define REALVIEW_CHAR_LCD_BASE        0x10008000        /* Character LCD */
-#define REALVIEW_SCI_BASE             0x1000E000        /* Smart card controller */
-#define REALVIEW_GPIO1_BASE           0x10014000        /* GPIO port 1 */
-#define REALVIEW_GPIO2_BASE           0x10015000        /* GPIO port 2 */
-#define REALVIEW_DMC_BASE             0x10018000        /* DMC configuration */
-#define REALVIEW_DMAC_BASE            0x10030000        /* DMA controller */
-
-/* PCI space */
-#define REALVIEW_PCI_BASE             0x41000000        /* PCI Interface */
-#define REALVIEW_PCI_CFG_BASE         0x42000000
-#define REALVIEW_PCI_MEM_BASE0        0x44000000
-#define REALVIEW_PCI_MEM_BASE1        0x50000000
-#define REALVIEW_PCI_MEM_BASE2        0x60000000
-/* Sizes of above maps */
-#define REALVIEW_PCI_BASE_SIZE         0x01000000
-#define REALVIEW_PCI_CFG_BASE_SIZE    0x02000000
-#define REALVIEW_PCI_MEM_BASE0_SIZE   0x0c000000        /* 32Mb */
-#define REALVIEW_PCI_MEM_BASE1_SIZE   0x10000000        /* 256Mb */
-#define REALVIEW_PCI_MEM_BASE2_SIZE   0x10000000        /* 256Mb */
-
-#define REALVIEW_SDRAM67_BASE         0x70000000        /* SDRAM banks 6 and 7 */
-#define REALVIEW_LT_BASE              0x80000000        /* Logic Tile expansion */
-
-/*
- * Disk on Chip
- */
-#define REALVIEW_DOC_BASE             0x2C000000
-#define REALVIEW_DOC_SIZE             (16 << 20)
-#define REALVIEW_DOC_PAGE_SIZE        512
-#define REALVIEW_DOC_TOTAL_PAGES     (DOC_SIZE / PAGE_SIZE)
-
-#define ERASE_UNIT_PAGES    32
-#define START_PAGE          0x80
-
-/* 
- *  LED settings, bits [7:0]
- */
-#define REALVIEW_SYS_LED0             (1 << 0)
-#define REALVIEW_SYS_LED1             (1 << 1)
-#define REALVIEW_SYS_LED2             (1 << 2)
-#define REALVIEW_SYS_LED3             (1 << 3)
-#define REALVIEW_SYS_LED4             (1 << 4)
-#define REALVIEW_SYS_LED5             (1 << 5)
-#define REALVIEW_SYS_LED6             (1 << 6)
-#define REALVIEW_SYS_LED7             (1 << 7)
-
-#define ALL_LEDS                  0xFF
-
-#define LED_BANK                  REALVIEW_SYS_LED
-
-/* 
- * Control registers
- */
-#define REALVIEW_IDFIELD_OFFSET 0x0     /* RealView build information */
-#define REALVIEW_FLASHPROG_OFFSET       0x4     /* Flash devices */
-#define REALVIEW_INTREG_OFFSET          0x8     /* Interrupt control */
-#define REALVIEW_DECODE_OFFSET          0xC     /* Fitted logic modules */
-
-/* 
- *  Application Flash
- * 
- */
-#define FLASH_BASE                      REALVIEW_FLASH_BASE
-#define FLASH_SIZE                      REALVIEW_FLASH_SIZE
-#define FLASH_END                       (FLASH_BASE + FLASH_SIZE - 1)
-#define FLASH_BLOCK_SIZE                SZ_128K
-
-/* 
- *  Boot Flash
- * 
- */
-#define EPROM_BASE                      REALVIEW_BOOT_ROM_HI
-#define EPROM_SIZE                      REALVIEW_BOOT_ROM_SIZE
-#define EPROM_END                       (EPROM_BASE + EPROM_SIZE - 1)
-
-/* 
- *  Clean base - dummy
- * 
- */
-#define CLEAN_BASE                      EPROM_BASE
-
-/*
- * System controller bit assignment
- */
-#define REALVIEW_REFCLK 0
-#define REALVIEW_TIMCLK 1
-
-#define REALVIEW_TIMER1_EnSel   15
-#define REALVIEW_TIMER2_EnSel   17
-#define REALVIEW_TIMER3_EnSel   19
-#define REALVIEW_TIMER4_EnSel   21
-
-
-#define MAX_TIMER                       2
-#define MAX_PERIOD                      699050
-#define TICKS_PER_uSEC                  1
-
-/* 
- *  These are useconds NOT ticks.  
- * 
- */
-#define mSEC_1                          1000
-#define mSEC_5                          (mSEC_1 * 5)
-#define mSEC_10                         (mSEC_1 * 10)
-#define mSEC_25                         (mSEC_1 * 25)
-#define SEC_1                           (mSEC_1 * 1000)
-
-#define REALVIEW_CSR_BASE             0x10000000
-#define REALVIEW_CSR_SIZE             0x10000000
-
-#endif  /* __ASM_ARCH_PLATFORM_H */
diff --git a/include/asm-arm/arch-realview/system.h b/include/asm-arm/arch-realview/system.h
deleted file mode 100644
index bff3d3fcf846..000000000000
--- a/include/asm-arm/arch-realview/system.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-realview/system.h
- *
- *  Copyright (C) 2003 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-#include <asm/arch/platform.h>
-
-static inline void arch_idle(void)
-{
-        /*
-         * This should do all the clock switching
-         * and wait for interrupt tricks
-         */
-        cpu_do_idle();
-}
-
-static inline void arch_reset(char mode)
-{
-        void __iomem *hdr_ctrl = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_RESETCTL_OFFSET;
-        unsigned int val;
-
-        /*
-         * To reset, we hit the on-board reset register
-         * in the system FPGA
-         */
-        val = __raw_readl(hdr_ctrl);
-        val |= REALVIEW_SYS_CTRL_RESET_CONFIGCLR;
-        __raw_writel(val, hdr_ctrl);
-}
-
-#endif
diff --git a/include/asm-arm/arch-realview/timex.h b/include/asm-arm/arch-realview/timex.h
deleted file mode 100644
index 5b9d82d0a5e0..000000000000
--- a/include/asm-arm/arch-realview/timex.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-realview/timex.h
- *
- *  RealView architecture timex specifications
- *
- *  Copyright (C) 2003 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#define CLOCK_TICK_RATE         (50000000 / 16)
diff --git a/include/asm-arm/arch-realview/uncompress.h b/include/asm-arm/arch-realview/uncompress.h
deleted file mode 100644
index 3f7ae2e0260d..000000000000
--- a/include/asm-arm/arch-realview/uncompress.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-realview/uncompress.h
- *
- *  Copyright (C) 2003 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <asm/arch/hardware.h>
-#include <asm/mach-types.h>
-
-#include <asm/arch/board-eb.h>
-#include <asm/arch/board-pb11mp.h>
-#include <asm/arch/board-pb1176.h>
-
-#define AMBA_UART_DR(base)      (*(volatile unsigned char *)((base) + 0x00))
-#define AMBA_UART_LCRH(base)    (*(volatile unsigned char *)((base) + 0x2c))
-#define AMBA_UART_CR(base)      (*(volatile unsigned char *)((base) + 0x30))
-#define AMBA_UART_FR(base)      (*(volatile unsigned char *)((base) + 0x18))
-
-/*
- * Return the UART base address
- */
-static inline unsigned long get_uart_base(void)
-{
-        if (machine_is_realview_eb())
-                return REALVIEW_EB_UART0_BASE;
-        else if (machine_is_realview_pb11mp())
-                return REALVIEW_PB11MP_UART0_BASE;
-        else if (machine_is_realview_pb1176())
-                return REALVIEW_PB1176_UART0_BASE;
-        else
-                return 0;
-}
-
-/*
- * This does not append a newline
- */
-static inline void putc(int c)
-{
-        unsigned long base = get_uart_base();
-
-        while (AMBA_UART_FR(base) & (1 << 5))
-                barrier();
-
-        AMBA_UART_DR(base) = c;
-}
-
-static inline void flush(void)
-{
-        unsigned long base = get_uart_base();
-
-        while (AMBA_UART_FR(base) & (1 << 3))
-                barrier();
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-realview/vmalloc.h b/include/asm-arm/arch-realview/vmalloc.h
deleted file mode 100644
index 0ad49af186af..000000000000
--- a/include/asm-arm/arch-realview/vmalloc.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-realview/vmalloc.h
- *
- *  Copyright (C) 2003 ARM Limited
- *  Copyright (C) 2000 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define VMALLOC_END             (PAGE_OFFSET + 0x18000000)
diff --git a/include/asm-arm/arch-rpc/acornfb.h b/include/asm-arm/arch-rpc/acornfb.h
deleted file mode 100644
index ecb7733a0949..000000000000
--- a/include/asm-arm/arch-rpc/acornfb.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-rpc/acornfb.h
- *
- *  Copyright (C) 1999 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  AcornFB architecture specific code
- */
-
-#define acornfb_bandwidth(var) ((var)->pixclock * 8 / (var)->bits_per_pixel)
-
-static inline int
-acornfb_valid_pixrate(struct fb_var_screeninfo *var)
-{
-        u_long limit;
-
-        if (!var->pixclock)
-                return 0;
-
-        /*
-         * Limits below are taken from RISC OS bandwidthlimit file
-         */
-        if (current_par.using_vram) {
-                if (current_par.vram_half_sam == 2048)
-                        limit = 6578;
-                else
-                        limit = 13157;
-        } else {
-                limit = 26315;
-        }
-
-        return acornfb_bandwidth(var) >= limit;
-}
-
-/*
- * Try to find the best PLL parameters for the pixel clock.
- * This algorithm seems to give best predictable results,
- * and produces the same values as detailed in the VIDC20
- * data sheet.
- */
-static inline u_int
-acornfb_vidc20_find_pll(u_int pixclk)
-{
-        u_int r, best_r = 2, best_v = 2;
-        int best_d = 0x7fffffff;
-
-        for (r = 2; r <= 32; r++) {
-                u_int rr, v, p;
-                int d;
-
-                rr = 41667 * r;
-
-                v = (rr + pixclk / 2) / pixclk;
-
-                if (v > 32 || v < 2)
-                        continue;
-
-                p = (rr + v / 2) / v;
-
-                d = pixclk - p;
-
-                if (d < 0)
-                        d = -d;
-
-                if (d < best_d) {
-                        best_d = d;
-                        best_v = v - 1;
-                        best_r = r - 1;
-                }
-
-                if (d == 0)
-                        break;
-        }
-
-        return best_v << 8 | best_r;
-}
-
-static inline void
-acornfb_vidc20_find_rates(struct vidc_timing *vidc,
-                          struct fb_var_screeninfo *var)
-{
-        u_int div;
-
-        /* Select pixel-clock divisor to keep PLL in range */
-        div = var->pixclock / 9090; /*9921*/
-
-        /* Limit divisor */
-        if (div == 0)
-                div = 1;
-        if (div > 8)
-                div = 8;
-
-        /* Encode divisor to VIDC20 setting */
-        switch (div) {
-        case 1: vidc->control |= VIDC20_CTRL_PIX_CK;  break;
-        case 2: vidc->control |= VIDC20_CTRL_PIX_CK2; break;
-        case 3: vidc->control |= VIDC20_CTRL_PIX_CK3; break;
-        case 4: vidc->control |= VIDC20_CTRL_PIX_CK4; break;
-        case 5: vidc->control |= VIDC20_CTRL_PIX_CK5; break;
-        case 6: vidc->control |= VIDC20_CTRL_PIX_CK6; break;
-        case 7: vidc->control |= VIDC20_CTRL_PIX_CK7; break;
-        case 8: vidc->control |= VIDC20_CTRL_PIX_CK8; break;
-        }
-
-        /*
-         * With VRAM, the FIFO can be set to the highest possible setting
-         * because there are no latency considerations for other memory
-         * accesses. However, in 64 bit bus mode the FIFO preload value
-         * must not be set to VIDC20_CTRL_FIFO_28 because this will let
-         * the FIFO overflow. See VIDC20 manual page 33 (6.0 Setting the
-         * FIFO preload value).
-         */
-        if (current_par.using_vram) {
-                if (current_par.vram_half_sam == 2048)
-                        vidc->control |= VIDC20_CTRL_FIFO_24;
-                else
-                        vidc->control |= VIDC20_CTRL_FIFO_28;
-        } else {
-                unsigned long bandwidth = acornfb_bandwidth(var);
-
-                /* Encode bandwidth as VIDC20 setting */
-                if (bandwidth > 33334)          /* < 30.0MB/s */
-                        vidc->control |= VIDC20_CTRL_FIFO_16;
-                else if (bandwidth > 26666)     /* < 37.5MB/s */
-                        vidc->control |= VIDC20_CTRL_FIFO_20;
-                else if (bandwidth > 22222)     /* < 45.0MB/s */
-                        vidc->control |= VIDC20_CTRL_FIFO_24;
-                else                            /* > 45.0MB/s */
-                        vidc->control |= VIDC20_CTRL_FIFO_28;
-        }
-
-        /* Find the PLL values */
-        vidc->pll_ctl = acornfb_vidc20_find_pll(var->pixclock / div);
-}
-
-#define acornfb_default_control()       (VIDC20_CTRL_PIX_VCLK)
-#define acornfb_default_econtrol()      (VIDC20_ECTL_DAC | VIDC20_ECTL_REG(3))
diff --git a/include/asm-arm/arch-rpc/debug-macro.S b/include/asm-arm/arch-rpc/debug-macro.S
deleted file mode 100644
index c634c8d8f4a1..000000000000
--- a/include/asm-arm/arch-rpc/debug-macro.S
+++ /dev/null
@@ -1,25 +0,0 @@
-/* linux/include/asm-arm/arch-rpc/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-                .macro  addruart,rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx, #0x03000000
-                movne   \rx, #0xe0000000
-                orr     \rx, \rx, #0x00010000
-                orr     \rx, \rx, #0x00000fe0
-                .endm
-
-#define UART_SHIFT      2
-#define FLOW_CONTROL
-#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-rpc/dma.h b/include/asm-arm/arch-rpc/dma.h
deleted file mode 100644
index d24a27e30b93..000000000000
--- a/include/asm-arm/arch-rpc/dma.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-rpc/dma.h
- *
- *  Copyright (C) 1997 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-
-/*
- * This is the maximum DMA address that can be DMAd to.
- * There should not be more than (0xd0000000 - 0xc0000000)
- * bytes of RAM.
- */
-#define MAX_DMA_ADDRESS         0xd0000000
-#define MAX_DMA_CHANNELS        8
-
-#define DMA_0                   0
-#define DMA_1                   1
-#define DMA_2                   2
-#define DMA_3                   3
-#define DMA_S0                  4
-#define DMA_S1                  5
-#define DMA_VIRTUAL_FLOPPY      6
-#define DMA_VIRTUAL_SOUND       7
-
-#define DMA_FLOPPY              DMA_VIRTUAL_FLOPPY
-
-#endif /* _ASM_ARCH_DMA_H */
-
diff --git a/include/asm-arm/arch-rpc/entry-macro.S b/include/asm-arm/arch-rpc/entry-macro.S
deleted file mode 100644
index 5bd55557ccca..000000000000
--- a/include/asm-arm/arch-rpc/entry-macro.S
+++ /dev/null
@@ -1,16 +0,0 @@
-#include <asm/arch/hardware.h>
-#include <asm/hardware/entry-macro-iomd.S>
-
-        .equ    ioc_base_high, IOC_BASE & 0xff000000
-        .equ    ioc_base_low, IOC_BASE & 0x00ff0000
-
-        .macro  get_irqnr_preamble, base, tmp
-        mov     \base, #ioc_base_high           @ point at IOC
-        .if     ioc_base_low
-        orr     \base, \base, #ioc_base_low
-        .endif
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
diff --git a/include/asm-arm/arch-rpc/hardware.h b/include/asm-arm/arch-rpc/hardware.h
deleted file mode 100644
index 7480f4e8d974..000000000000
--- a/include/asm-arm/arch-rpc/hardware.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-rpc/hardware.h
- *
- *  Copyright (C) 1996-1999 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  This file contains the hardware definitions of the RiscPC series machines.
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <asm/arch/memory.h>
-
-#ifndef __ASSEMBLY__
-#define IOMEM(x) ((void __iomem *)(unsigned long)(x))
-#else
-#define IOMEM(x) x
-#endif /* __ASSEMBLY__ */
-
-/*
- * What hardware must be present
- */
-#define HAS_IOMD
-#define HAS_VIDC20
-
-/* Hardware addresses of major areas.
- *  *_START is the physical address
- *  *_SIZE  is the size of the region
- *  *_BASE  is the virtual address
- */
-#define RAM_SIZE                0x10000000
-#define RAM_START               0x10000000
-
-#define EASI_SIZE               0x08000000      /* EASI I/O */
-#define EASI_START              0x08000000
-#define EASI_BASE               0xe5000000
-
-#define IO_START                0x03000000      /* I/O */
-#define IO_SIZE                 0x01000000
-#define IO_BASE                 IOMEM(0xe0000000)
-
-#define SCREEN_START            0x02000000      /* VRAM */
-#define SCREEN_END              0xdfc00000
-#define SCREEN_BASE             0xdf800000
-
-#define UNCACHEABLE_ADDR        0xdf010000
-
-/*
- * IO Addresses
- */
-#define VIDC_BASE               IOMEM(0xe0400000)
-#define EXPMASK_BASE            0xe0360000
-#define IOMD_BASE               IOMEM(0xe0200000)
-#define IOC_BASE                IOMEM(0xe0200000)
-#define PCIO_BASE               IOMEM(0xe0010000)
-#define FLOPPYDMA_BASE          IOMEM(0xe002a000)
-
-#define vidc_writel(val)        __raw_writel(val, VIDC_BASE)
-
-#define IO_EC_EASI_BASE         0x81400000
-#define IO_EC_IOC4_BASE         0x8009c000
-#define IO_EC_IOC_BASE          0x80090000
-#define IO_EC_MEMC8_BASE        0x8000ac00
-#define IO_EC_MEMC_BASE         0x80000000
-
-#define NETSLOT_BASE            0x0302b000
-#define NETSLOT_SIZE            0x00001000
-
-#define PODSLOT_IOC0_BASE       0x03240000
-#define PODSLOT_IOC4_BASE       0x03270000
-#define PODSLOT_IOC_SIZE        (1 << 14)
-#define PODSLOT_MEMC_BASE       0x03000000
-#define PODSLOT_MEMC_SIZE       (1 << 14)
-#define PODSLOT_EASI_BASE       0x08000000
-#define PODSLOT_EASI_SIZE       (1 << 24)
-
-#define EXPMASK_STATUS          (EXPMASK_BASE + 0x00)
-#define EXPMASK_ENABLE          (EXPMASK_BASE + 0x04)
-
-#endif
diff --git a/include/asm-arm/arch-rpc/io.h b/include/asm-arm/arch-rpc/io.h
deleted file mode 100644
index 0d10d4591a45..000000000000
--- a/include/asm-arm/arch-rpc/io.h
+++ /dev/null
@@ -1,258 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-rpc/io.h
- *
- *  Copyright (C) 1997 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Modifications:
- *  06-Dec-1997 RMK     Created.
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#include <asm/arch/hardware.h>
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/*
- * GCC is totally crap at loading/storing data.  We try to persuade it
- * to do the right thing by using these whereever possible instead of
- * the above.
- */
-#define __arch_base_getb(b,o)                   \
- ({                                             \
-        unsigned int __v, __r = (b);            \
-        __asm__ __volatile__(                   \
-                "ldrb   %0, [%1, %2]"           \
-                : "=r" (__v)                    \
-                : "r" (__r), "Ir" (o));         \
-        __v;                                    \
- })
-
-#define __arch_base_getl(b,o)                   \
- ({                                             \
-        unsigned int __v, __r = (b);            \
-        __asm__ __volatile__(                   \
-                "ldr    %0, [%1, %2]"           \
-                : "=r" (__v)                    \
-                : "r" (__r), "Ir" (o));         \
-        __v;                                    \
- })
-
-#define __arch_base_putb(v,b,o)                 \
- ({                                             \
-        unsigned int __r = (b);                 \
-        __asm__ __volatile__(                   \
-                "strb   %0, [%1, %2]"           \
-                :                               \
-                : "r" (v), "r" (__r), "Ir" (o));\
- })
-
-#define __arch_base_putl(v,b,o)                 \
- ({                                             \
-        unsigned int __r = (b);                 \
-        __asm__ __volatile__(                   \
-                "str    %0, [%1, %2]"           \
-                :                               \
-                : "r" (v), "r" (__r), "Ir" (o));\
- })
-
-/*
- * We use two different types of addressing - PC style addresses, and ARM
- * addresses.  PC style accesses the PC hardware with the normal PC IO
- * addresses, eg 0x3f8 for serial#1.  ARM addresses are 0x80000000+
- * and are translated to the start of IO.  Note that all addresses are
- * shifted left!
- */
-#define __PORT_PCIO(x)  (!((x) & 0x80000000))
-
-/*
- * Dynamic IO functions.
- */
-static inline void __outb (unsigned int value, unsigned int port)
-{
-        unsigned long temp;
-        __asm__ __volatile__(
-        "tst    %2, #0x80000000\n\t"
-        "mov    %0, %4\n\t"
-        "addeq  %0, %0, %3\n\t"
-        "strb   %1, [%0, %2, lsl #2]    @ outb"
-        : "=&r" (temp)
-        : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
-        : "cc");
-}
-
-static inline void __outw (unsigned int value, unsigned int port)
-{
-        unsigned long temp;
-        __asm__ __volatile__(
-        "tst    %2, #0x80000000\n\t"
-        "mov    %0, %4\n\t"
-        "addeq  %0, %0, %3\n\t"
-        "str    %1, [%0, %2, lsl #2]    @ outw"
-        : "=&r" (temp)
-        : "r" (value|value<<16), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
-        : "cc");
-}
-
-static inline void __outl (unsigned int value, unsigned int port)
-{
-        unsigned long temp;
-        __asm__ __volatile__(
-        "tst    %2, #0x80000000\n\t"
-        "mov    %0, %4\n\t"
-        "addeq  %0, %0, %3\n\t"
-        "str    %1, [%0, %2, lsl #2]    @ outl"
-        : "=&r" (temp)
-        : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
-        : "cc");
-}
-
-#define DECLARE_DYN_IN(sz,fnsuffix,instr)                                       \
-static inline unsigned sz __in##fnsuffix (unsigned int port)            \
-{                                                                               \
-        unsigned long temp, value;                                              \
-        __asm__ __volatile__(                                                   \
-        "tst    %2, #0x80000000\n\t"                                            \
-        "mov    %0, %4\n\t"                                                     \
-        "addeq  %0, %0, %3\n\t"                                                 \
-        "ldr" instr "   %1, [%0, %2, lsl #2]    @ in" #fnsuffix                 \
-        : "=&r" (temp), "=r" (value)                                            \
-        : "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)                \
-        : "cc");                                                                \
-        return (unsigned sz)value;                                              \
-}
-
-static inline void __iomem *__deprecated __ioaddr(unsigned int port)
-{
-        void __iomem *ret;
-        if (__PORT_PCIO(port))
-                ret = PCIO_BASE;
-        else
-                ret = IO_BASE;
-        return ret + (port << 2);
-}
-
-#define DECLARE_IO(sz,fnsuffix,instr)   \
-        DECLARE_DYN_IN(sz,fnsuffix,instr)
-
-DECLARE_IO(char,b,"b")
-DECLARE_IO(short,w,"")
-DECLARE_IO(int,l,"")
-
-#undef DECLARE_IO
-#undef DECLARE_DYN_IN
-
-/*
- * Constant address IO functions
- *
- * These have to be macros for the 'J' constraint to work -
- * +/-4096 immediate operand.
- */
-#define __outbc(value,port)                                                     \
-({                                                                              \
-        if (__PORT_PCIO((port)))                                                \
-                __asm__ __volatile__(                                           \
-                "strb   %0, [%1, %2]    @ outbc"                                \
-                : : "r" (value), "r" (PCIO_BASE), "Jr" ((port) << 2));          \
-        else                                                                    \
-                __asm__ __volatile__(                                           \
-                "strb   %0, [%1, %2]    @ outbc"                                \
-                : : "r" (value), "r" (IO_BASE), "r" ((port) << 2));             \
-})
-
-#define __inbc(port)                                                            \
-({                                                                              \
-        unsigned char result;                                                   \
-        if (__PORT_PCIO((port)))                                                \
-                __asm__ __volatile__(                                           \
-                "ldrb   %0, [%1, %2]    @ inbc"                                 \
-                : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2));         \
-        else                                                                    \
-                __asm__ __volatile__(                                           \
-                "ldrb   %0, [%1, %2]    @ inbc"                                 \
-                : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2));            \
-        result;                                                                 \
-})
-
-#define __outwc(value,port)                                                     \
-({                                                                              \
-        unsigned long __v = value;                                              \
-        if (__PORT_PCIO((port)))                                                \
-                __asm__ __volatile__(                                           \
-                "str    %0, [%1, %2]    @ outwc"                                \
-                : : "r" (__v|__v<<16), "r" (PCIO_BASE), "Jr" ((port) << 2));    \
-        else                                                                    \
-                __asm__ __volatile__(                                           \
-                "str    %0, [%1, %2]    @ outwc"                                \
-                : : "r" (__v|__v<<16), "r" (IO_BASE), "r" ((port) << 2));               \
-})
-
-#define __inwc(port)                                                            \
-({                                                                              \
-        unsigned short result;                                                  \
-        if (__PORT_PCIO((port)))                                                \
-                __asm__ __volatile__(                                           \
-                "ldr    %0, [%1, %2]    @ inwc"                                 \
-                : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2));         \
-        else                                                                    \
-                __asm__ __volatile__(                                           \
-                "ldr    %0, [%1, %2]    @ inwc"                                 \
-                : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2));            \
-        result & 0xffff;                                                        \
-})
-
-#define __outlc(value,port)                                                     \
-({                                                                              \
-        unsigned long __v = value;                                              \
-        if (__PORT_PCIO((port)))                                                \
-                __asm__ __volatile__(                                           \
-                "str    %0, [%1, %2]    @ outlc"                                \
-                : : "r" (__v), "r" (PCIO_BASE), "Jr" ((port) << 2));            \
-        else                                                                    \
-                __asm__ __volatile__(                                           \
-                "str    %0, [%1, %2]    @ outlc"                                \
-                : : "r" (__v), "r" (IO_BASE), "r" ((port) << 2));               \
-})
-
-#define __inlc(port)                                                            \
-({                                                                              \
-        unsigned long result;                                                   \
-        if (__PORT_PCIO((port)))                                                \
-                __asm__ __volatile__(                                           \
-                "ldr    %0, [%1, %2]    @ inlc"                                 \
-                : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2));         \
-        else                                                                    \
-                __asm__ __volatile__(                                           \
-                "ldr    %0, [%1, %2]    @ inlc"                                 \
-                : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2));            \
-        result;                                                                 \
-})
-
-#define __ioaddrc(port)         __ioaddr(port)
-
-#define inb(p)          (__builtin_constant_p((p)) ? __inbc(p)    : __inb(p))
-#define inw(p)          (__builtin_constant_p((p)) ? __inwc(p)    : __inw(p))
-#define inl(p)          (__builtin_constant_p((p)) ? __inlc(p)    : __inl(p))
-#define outb(v,p)       (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p))
-#define outw(v,p)       (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p))
-#define outl(v,p)       (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p))
-#define __ioaddr(p)     (__builtin_constant_p((p)) ? __ioaddr(p)  : __ioaddrc(p))
-/* the following macro is deprecated */
-#define ioaddr(port)    ((unsigned long)__ioaddr((port)))
-
-#define insb(p,d,l)     __raw_readsb(__ioaddr(p),d,l)
-#define insw(p,d,l)     __raw_readsw(__ioaddr(p),d,l)
-
-#define outsb(p,d,l)    __raw_writesb(__ioaddr(p),d,l)
-#define outsw(p,d,l)    __raw_writesw(__ioaddr(p),d,l)
-
-/*
- * 1:1 mapping for ioremapped regions.
- */
-#define __mem_pci(x)    (x)
-
-#endif
diff --git a/include/asm-arm/arch-rpc/irqs.h b/include/asm-arm/arch-rpc/irqs.h
deleted file mode 100644
index 27c35b05b27d..000000000000
--- a/include/asm-arm/arch-rpc/irqs.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-rpc/irqs.h
- *
- *  Copyright (C) 1996 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#define IRQ_PRINTER             0
-#define IRQ_BATLOW              1
-#define IRQ_FLOPPYINDEX         2
-#define IRQ_VSYNCPULSE          3
-#define IRQ_POWERON             4
-#define IRQ_TIMER0              5
-#define IRQ_TIMER1              6
-#define IRQ_IMMEDIATE           7
-#define IRQ_EXPCARDFIQ          8
-#define IRQ_HARDDISK            9
-#define IRQ_SERIALPORT          10
-#define IRQ_FLOPPYDISK          12
-#define IRQ_EXPANSIONCARD       13
-#define IRQ_KEYBOARDTX          14
-#define IRQ_KEYBOARDRX          15
-
-#define IRQ_DMA0                16
-#define IRQ_DMA1                17
-#define IRQ_DMA2                18
-#define IRQ_DMA3                19
-#define IRQ_DMAS0               20
-#define IRQ_DMAS1               21
-
-#define FIQ_FLOPPYDATA          0
-#define FIQ_ECONET              2
-#define FIQ_SERIALPORT          4
-#define FIQ_EXPANSIONCARD       6
-#define FIQ_FORCE               7
-
-/*
- * This is the offset of the FIQ "IRQ" numbers
- */
-#define FIQ_START               64
-
-#define IRQ_TIMER               IRQ_TIMER0
-
diff --git a/include/asm-arm/arch-rpc/memory.h b/include/asm-arm/arch-rpc/memory.h
deleted file mode 100644
index 303c424ce673..000000000000
--- a/include/asm-arm/arch-rpc/memory.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-rpc/memory.h
- *
- *  Copyright (C) 1996,1997,1998 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  Changelog:
- *   20-Oct-1996 RMK    Created
- *   31-Dec-1997 RMK    Fixed definitions to reduce warnings
- *   11-Jan-1998 RMK    Uninlined to reduce hits on cache
- *   08-Feb-1998 RMK    Added __virt_to_bus and __bus_to_virt
- *   21-Mar-1999 RMK    Renamed to memory.h
- *               RMK    Added TASK_SIZE and PAGE_OFFSET
- */
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-/*
- * Physical DRAM offset.
- */
-#define PHYS_OFFSET     UL(0x10000000)
-
-/*
- * These are exactly the same on the RiscPC as the
- * physical memory view.
- */
-#define __virt_to_bus(x) __virt_to_phys(x)
-#define __bus_to_virt(x) __phys_to_virt(x)
-
-/*
- * Cache flushing area - ROM
- */
-#define FLUSH_BASE_PHYS         0x00000000
-#define FLUSH_BASE              0xdf000000
-
-#endif
diff --git a/include/asm-arm/arch-rpc/system.h b/include/asm-arm/arch-rpc/system.h
deleted file mode 100644
index ca3277d1d5ea..000000000000
--- a/include/asm-arm/arch-rpc/system.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-rpc/system.h
- *
- *  Copyright (C) 1996-1999 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <asm/arch/hardware.h>
-#include <asm/hardware/iomd.h>
-#include <asm/io.h>
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-static inline void arch_reset(char mode)
-{
-        iomd_writeb(0, IOMD_ROMCR0);
-
-        /*
-         * Jump into the ROM
-         */
-        cpu_reset(0);
-}
diff --git a/include/asm-arm/arch-rpc/timex.h b/include/asm-arm/arch-rpc/timex.h
deleted file mode 100644
index ed7df64d960b..000000000000
--- a/include/asm-arm/arch-rpc/timex.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-rpc/timex.h
- *
- *  Copyright (C) 1997, 1998 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  RiscPC architecture timex specifications
- */
-
-/*
- * On the RiscPC, the clock ticks at 2MHz.
- */
-#define CLOCK_TICK_RATE         2000000
-
diff --git a/include/asm-arm/arch-rpc/uncompress.h b/include/asm-arm/arch-rpc/uncompress.h
deleted file mode 100644
index 844e4d469fb2..000000000000
--- a/include/asm-arm/arch-rpc/uncompress.h
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-rpc/uncompress.h
- *
- *  Copyright (C) 1996 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#define VIDMEM ((char *)SCREEN_START)
- 
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-#include <asm/setup.h>
-#include <asm/page.h>
-
-int video_size_row;
-unsigned char bytes_per_char_h;
-extern unsigned long con_charconvtable[256];
-
-struct param_struct {
-        unsigned long page_size;
-        unsigned long nr_pages;
-        unsigned long ramdisk_size;
-        unsigned long mountrootrdonly;
-        unsigned long rootdev;
-        unsigned long video_num_cols;
-        unsigned long video_num_rows;
-        unsigned long video_x;
-        unsigned long video_y;
-        unsigned long memc_control_reg;
-        unsigned char sounddefault;
-        unsigned char adfsdrives;
-        unsigned char bytes_per_char_h;
-        unsigned char bytes_per_char_v;
-        unsigned long unused[256/4-11];
-};
-
-static const unsigned long palette_4[16] = {
-        0x00000000,
-        0x000000cc,
-        0x0000cc00,             /* Green   */
-        0x0000cccc,             /* Yellow  */
-        0x00cc0000,             /* Blue    */
-        0x00cc00cc,             /* Magenta */
-        0x00cccc00,             /* Cyan    */
-        0x00cccccc,             /* White   */
-        0x00000000,
-        0x000000ff,
-        0x0000ff00,
-        0x0000ffff,
-        0x00ff0000,
-        0x00ff00ff,
-        0x00ffff00,
-        0x00ffffff
-};
-
-#define palette_setpixel(p)     *(unsigned long *)(IO_START+0x00400000) = 0x10000000|((p) & 255)
-#define palette_write(v)        *(unsigned long *)(IO_START+0x00400000) = 0x00000000|((v) & 0x00ffffff)
-
-/*
- * params_phys is a linker defined symbol - see
- * arch/arm/boot/compressed/Makefile
- */
-extern __attribute__((pure)) struct param_struct *params(void);
-#define params (params())
-
-#ifndef STANDALONE_DEBUG 
-static unsigned long video_num_cols;
-static unsigned long video_num_rows;
-static unsigned long video_x;
-static unsigned long video_y;
-static unsigned char bytes_per_char_v;
-static int white;
-
-/*
- * This does not append a newline
- */
-static void putc(int c)
-{
-        extern void ll_write_char(char *, char c, char white);
-        int x,y;
-        char *ptr;
-
-        x = video_x;
-        y = video_y;
-
-        if (c == '\n') {
-                if (++y >= video_num_rows)
-                        y--;
-        } else if (c == '\r') {
-                x = 0;
-        } else {
-                ptr = VIDMEM + ((y*video_num_cols*bytes_per_char_v+x)*bytes_per_char_h);
-                ll_write_char(ptr, c, white);
-                if (++x >= video_num_cols) {
-                        x = 0;
-                        if ( ++y >= video_num_rows ) {
-                                y--;
-                        }
-                }
-        }
-
-        video_x = x;
-        video_y = y;
-}
-
-static inline void flush(void)
-{
-}
-
-static void error(char *x);
-
-/*
- * Setup for decompression
- */
-static void arch_decomp_setup(void)
-{
-        int i;
-        struct tag *t = (struct tag *)params;
-        unsigned int nr_pages = 0, page_size = PAGE_SIZE;
-
-        if (t->hdr.tag == ATAG_CORE)
-        {
-                for (; t->hdr.size; t = tag_next(t))
-                {
-                        if (t->hdr.tag == ATAG_VIDEOTEXT)
-                        {
-                                video_num_rows = t->u.videotext.video_lines;
-                                video_num_cols = t->u.videotext.video_cols;
-                                bytes_per_char_h = t->u.videotext.video_points;
-                                bytes_per_char_v = t->u.videotext.video_points;
-                                video_x = t->u.videotext.x;
-                                video_y = t->u.videotext.y;
-                        }
-
-                        if (t->hdr.tag == ATAG_MEM)
-                        {
-                                page_size = PAGE_SIZE;
-                                nr_pages += (t->u.mem.size / PAGE_SIZE);
-                        }
-                }
-        }
-        else
-        {
-                nr_pages = params->nr_pages;
-                page_size = params->page_size;
-                video_num_rows = params->video_num_rows;
-                video_num_cols = params->video_num_cols;
-                video_x = params->video_x;
-                video_y = params->video_y;
-                bytes_per_char_h = params->bytes_per_char_h;
-                bytes_per_char_v = params->bytes_per_char_v;
-        }
-
-        video_size_row = video_num_cols * bytes_per_char_h;
-        
-        if (bytes_per_char_h == 4)
-                for (i = 0; i < 256; i++)
-                        con_charconvtable[i] =
-                                (i & 128 ? 1 << 0  : 0) |
-                                (i & 64  ? 1 << 4  : 0) |
-                                (i & 32  ? 1 << 8  : 0) |
-                                (i & 16  ? 1 << 12 : 0) |
-                                (i & 8   ? 1 << 16 : 0) |
-                                (i & 4   ? 1 << 20 : 0) |
-                                (i & 2   ? 1 << 24 : 0) |
-                                (i & 1   ? 1 << 28 : 0);
-        else
-                for (i = 0; i < 16; i++)
-                        con_charconvtable[i] =
-                                (i & 8   ? 1 << 0  : 0) |
-                                (i & 4   ? 1 << 8  : 0) |
-                                (i & 2   ? 1 << 16 : 0) |
-                                (i & 1   ? 1 << 24 : 0);
-
-
-        palette_setpixel(0);
-        if (bytes_per_char_h == 1) {
-                palette_write (0);
-                palette_write (0x00ffffff);
-                for (i = 2; i < 256; i++)
-                        palette_write (0);
-                white = 1;
-        } else {
-                for (i = 0; i < 256; i++)
-                        palette_write (i < 16 ? palette_4[i] : 0);
-                white = 7;
-        }
-
-        if (nr_pages * page_size < 4096*1024) error("<4M of mem\n");
-}
-#endif
-
-/*
- * nothing to do
- */
-#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-rpc/vmalloc.h b/include/asm-arm/arch-rpc/vmalloc.h
deleted file mode 100644
index 077046bb2f36..000000000000
--- a/include/asm-arm/arch-rpc/vmalloc.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-rpc/vmalloc.h
- *
- *  Copyright (C) 1997 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#define VMALLOC_END       (PAGE_OFFSET + 0x1c000000)
diff --git a/include/asm-arm/arch-s3c2400/map.h b/include/asm-arm/arch-s3c2400/map.h
deleted file mode 100644
index 1184d907b31e..000000000000
--- a/include/asm-arm/arch-s3c2400/map.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2400/map.h
- *
- * Copyright 2003,2007  Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Copyright 2003, Lucas Correia Villa Real
- *
- * S3C2400 - Memory map definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#define S3C2400_PA_MEMCTRL      (0x14000000)
-#define S3C2400_PA_USBHOST      (0x14200000)
-#define S3C2400_PA_IRQ          (0x14400000)
-#define S3C2400_PA_DMA          (0x14600000)
-#define S3C2400_PA_CLKPWR       (0x14800000)
-#define S3C2400_PA_LCD          (0x14A00000)
-#define S3C2400_PA_UART         (0x15000000)
-#define S3C2400_PA_TIMER        (0x15100000)
-#define S3C2400_PA_USBDEV       (0x15200140)
-#define S3C2400_PA_WATCHDOG     (0x15300000)
-#define S3C2400_PA_IIC          (0x15400000)
-#define S3C2400_PA_IIS          (0x15508000)
-#define S3C2400_PA_GPIO         (0x15600000)
-#define S3C2400_PA_RTC          (0x15700040)
-#define S3C2400_PA_ADC          (0x15800000)
-#define S3C2400_PA_SPI          (0x15900000)
-
-#define S3C2400_PA_MMC          (0x15A00000)
-#define S3C2400_SZ_MMC          SZ_1M
-
-/* physical addresses of all the chip-select areas */
-
-#define S3C2400_CS0     (0x00000000)
-#define S3C2400_CS1     (0x02000000)
-#define S3C2400_CS2     (0x04000000)
-#define S3C2400_CS3     (0x06000000)
-#define S3C2400_CS4     (0x08000000)
-#define S3C2400_CS5     (0x0A000000)
-#define S3C2400_CS6     (0x0C000000)
-#define S3C2400_CS7     (0x0E000000)
-
-#define S3C2400_SDRAM_PA    (S3C2400_CS6)
-
-/* Use a single interface for common resources between S3C24XX cpus */
-
-#define S3C24XX_PA_IRQ          S3C2400_PA_IRQ
-#define S3C24XX_PA_MEMCTRL      S3C2400_PA_MEMCTRL
-#define S3C24XX_PA_USBHOST      S3C2400_PA_USBHOST
-#define S3C24XX_PA_DMA          S3C2400_PA_DMA
-#define S3C24XX_PA_CLKPWR       S3C2400_PA_CLKPWR
-#define S3C24XX_PA_LCD          S3C2400_PA_LCD
-#define S3C24XX_PA_UART         S3C2400_PA_UART
-#define S3C24XX_PA_TIMER        S3C2400_PA_TIMER
-#define S3C24XX_PA_USBDEV       S3C2400_PA_USBDEV
-#define S3C24XX_PA_WATCHDOG     S3C2400_PA_WATCHDOG
-#define S3C24XX_PA_IIC          S3C2400_PA_IIC
-#define S3C24XX_PA_IIS          S3C2400_PA_IIS
-#define S3C24XX_PA_GPIO         S3C2400_PA_GPIO
-#define S3C24XX_PA_RTC          S3C2400_PA_RTC
-#define S3C24XX_PA_ADC          S3C2400_PA_ADC
-#define S3C24XX_PA_SPI          S3C2400_PA_SPI
diff --git a/include/asm-arm/arch-s3c2400/memory.h b/include/asm-arm/arch-s3c2400/memory.h
deleted file mode 100644
index fb0381dde704..000000000000
--- a/include/asm-arm/arch-s3c2400/memory.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2400/memory.h
- *  from linux/include/asm-arm/arch-rpc/memory.h
- *
- *  Copyright 2007 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- *  Copyright (C) 1996,1997,1998 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-#define PHYS_OFFSET     UL(0x0C000000)
-
-#define __virt_to_bus(x) __virt_to_phys(x)
-#define __bus_to_virt(x) __phys_to_virt(x)
-
-#endif
diff --git a/include/asm-arm/arch-s3c2410/anubis-cpld.h b/include/asm-arm/arch-s3c2410/anubis-cpld.h
deleted file mode 100644
index 168b93fee529..000000000000
--- a/include/asm-arm/arch-s3c2410/anubis-cpld.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/anubis-cpld.h
- *
- * Copyright (c) 2005 Simtec Electronics
- *      http://www.simtec.co.uk/products/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * ANUBIS - CPLD control constants
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_ANUBISCPLD_H
-#define __ASM_ARCH_ANUBISCPLD_H
-
-/* CTRL2 - NAND WP control, IDE Reset assert/check */
-
-#define ANUBIS_CTRL1_NANDSEL            (0x3)
-
-/* IDREG - revision */
-
-#define ANUBIS_IDREG_REVMASK            (0x7)
-
-#endif /* __ASM_ARCH_ANUBISCPLD_H */
diff --git a/include/asm-arm/arch-s3c2410/anubis-irq.h b/include/asm-arm/arch-s3c2410/anubis-irq.h
deleted file mode 100644
index cd77a70d45c0..000000000000
--- a/include/asm-arm/arch-s3c2410/anubis-irq.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/anubis-irq.h
- *
- * Copyright (c) 2005 Simtec Electronics
- *      http://www.simtec.co.uk/products/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- *  ANUBIS - IRQ Number definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_ANUBISIRQ_H
-#define __ASM_ARCH_ANUBISIRQ_H
-
-#define IRQ_IDE0       IRQ_EINT2
-#define IRQ_IDE1       IRQ_EINT3
-#define IRQ_ASIX       IRQ_EINT1
-
-#endif /* __ASM_ARCH_ANUBISIRQ_H */
diff --git a/include/asm-arm/arch-s3c2410/anubis-map.h b/include/asm-arm/arch-s3c2410/anubis-map.h
deleted file mode 100644
index 830d114261da..000000000000
--- a/include/asm-arm/arch-s3c2410/anubis-map.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/anubis-map.h
- *
- * Copyright (c) 2005 Simtec Electronics
- *      http://www.simtec.co.uk/products/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * ANUBIS - Memory map definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* needs arch/map.h including with this */
-
-#ifndef __ASM_ARCH_ANUBISMAP_H
-#define __ASM_ARCH_ANUBISMAP_H
-
-/* start peripherals off after the S3C2410 */
-
-#define ANUBIS_IOADDR(x)        (S3C2410_ADDR((x) + 0x01800000))
-
-#define ANUBIS_PA_CPLD          (S3C2410_CS1 | (1<<26))
-
-/* we put the CPLD registers next, to get them out of the way */
-
-#define ANUBIS_VA_CTRL1     ANUBIS_IOADDR(0x00000000)    /* 0x01800000 */
-#define ANUBIS_PA_CTRL1     (ANUBIS_PA_CPLD)
-
-#define ANUBIS_VA_IDREG     ANUBIS_IOADDR(0x00300000)    /* 0x01B00000 */
-#define ANUBIS_PA_IDREG     (ANUBIS_PA_CPLD + (3<<23))
-
-#define ANUBIS_IDEPRI       ANUBIS_IOADDR(0x01000000)
-#define ANUBIS_IDEPRIAUX    ANUBIS_IOADDR(0x01100000)
-#define ANUBIS_IDESEC       ANUBIS_IOADDR(0x01200000)
-#define ANUBIS_IDESECAUX    ANUBIS_IOADDR(0x01300000)
-
-#endif /* __ASM_ARCH_ANUBISMAP_H */
diff --git a/include/asm-arm/arch-s3c2410/audio.h b/include/asm-arm/arch-s3c2410/audio.h
deleted file mode 100644
index 0a6977fb5770..000000000000
--- a/include/asm-arm/arch-s3c2410/audio.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/audio.h
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- *      http://www.simtec.co.uk/products/SWLINUX/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C24XX - Audio platfrom_device info
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_AUDIO_H
-#define __ASM_ARCH_AUDIO_H __FILE__
-
-/* struct s3c24xx_iis_ops
- *
- * called from the s3c24xx audio core to deal with the architecture
- * or the codec's setup and control.
- *
- * the pointer to itself is passed through in case the caller wants to
- * embed this in an larger structure for easy reference to it's context.
-*/
-
-struct s3c24xx_iis_ops {
-        struct module *owner;
-
-        int     (*startup)(struct s3c24xx_iis_ops *me);
-        void    (*shutdown)(struct s3c24xx_iis_ops *me);
-        int     (*suspend)(struct s3c24xx_iis_ops *me);
-        int     (*resume)(struct s3c24xx_iis_ops *me);
-
-        int     (*open)(struct s3c24xx_iis_ops *me, struct snd_pcm_substream *strm);
-        int     (*close)(struct s3c24xx_iis_ops *me, struct snd_pcm_substream *strm);
-        int     (*prepare)(struct s3c24xx_iis_ops *me, struct snd_pcm_substream *strm, struct snd_pcm_runtime *rt);
-};
-
-struct s3c24xx_platdata_iis {
-        const char              *codec_clk;
-        struct s3c24xx_iis_ops  *ops;
-        int                     (*match_dev)(struct device *dev);
-};
-
-#endif /* __ASM_ARCH_AUDIO_H */
diff --git a/include/asm-arm/arch-s3c2410/bast-cpld.h b/include/asm-arm/arch-s3c2410/bast-cpld.h
deleted file mode 100644
index 034d2c5a47c4..000000000000
--- a/include/asm-arm/arch-s3c2410/bast-cpld.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/bast-cpld.h
- *
- * Copyright (c) 2003,2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * BAST - CPLD control constants
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_BASTCPLD_H
-#define __ASM_ARCH_BASTCPLD_H
-
-/* CTRL1 - Audio LR routing */
-
-#define BAST_CPLD_CTRL1_LRCOFF      (0x00)
-#define BAST_CPLD_CTRL1_LRCADC      (0x01)
-#define BAST_CPLD_CTRL1_LRCDAC      (0x02)
-#define BAST_CPLD_CTRL1_LRCARM      (0x03)
-#define BAST_CPLD_CTRL1_LRMASK      (0x03)
-
-/* CTRL2 - NAND WP control, IDE Reset assert/check */
-
-#define BAST_CPLD_CTRL2_WNAND       (0x04)
-#define BAST_CPLD_CTLR2_IDERST      (0x08)
-
-/* CTRL3 - rom write control, CPLD identity */
-
-#define BAST_CPLD_CTRL3_IDMASK      (0x0e)
-#define BAST_CPLD_CTRL3_ROMWEN      (0x01)
-
-/* CTRL4 - 8bit LCD interface control/status */
-
-#define BAST_CPLD_CTRL4_LLAT        (0x01)
-#define BAST_CPLD_CTRL4_LCDRW       (0x02)
-#define BAST_CPLD_CTRL4_LCDCMD      (0x04)
-#define BAST_CPLD_CTRL4_LCDE2       (0x01)
-
-/* CTRL5 - DMA routing */
-
-#define BAST_CPLD_DMA0_PRIIDE      (0<<0)
-#define BAST_CPLD_DMA0_SECIDE      (1<<0)
-#define BAST_CPLD_DMA0_ISA15       (2<<0)
-#define BAST_CPLD_DMA0_ISA36       (3<<0)
-
-#define BAST_CPLD_DMA1_PRIIDE      (0<<2)
-#define BAST_CPLD_DMA1_SECIDE      (1<<2)
-#define BAST_CPLD_DMA1_ISA15       (2<<2)
-#define BAST_CPLD_DMA1_ISA36       (3<<2)
-
-#endif /* __ASM_ARCH_BASTCPLD_H */
diff --git a/include/asm-arm/arch-s3c2410/bast-irq.h b/include/asm-arm/arch-s3c2410/bast-irq.h
deleted file mode 100644
index 726c0466f85a..000000000000
--- a/include/asm-arm/arch-s3c2410/bast-irq.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/bast-irq.h
- *
- * Copyright (c) 2003,2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Machine BAST - IRQ Number definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_BASTIRQ_H
-#define __ASM_ARCH_BASTIRQ_H
-
-/* irq numbers to onboard peripherals */
-
-#define IRQ_USBOC      IRQ_EINT18
-#define IRQ_IDE0       IRQ_EINT16
-#define IRQ_IDE1       IRQ_EINT17
-#define IRQ_PCSERIAL1  IRQ_EINT15
-#define IRQ_PCSERIAL2  IRQ_EINT14
-#define IRQ_PCPARALLEL IRQ_EINT13
-#define IRQ_ASIX       IRQ_EINT11
-#define IRQ_DM9000     IRQ_EINT10
-#define IRQ_ISA        IRQ_EINT9
-#define IRQ_SMALERT    IRQ_EINT8
-
-#endif /* __ASM_ARCH_BASTIRQ_H */
diff --git a/include/asm-arm/arch-s3c2410/bast-map.h b/include/asm-arm/arch-s3c2410/bast-map.h
deleted file mode 100644
index 86ac1c108db8..000000000000
--- a/include/asm-arm/arch-s3c2410/bast-map.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/bast-map.h
- *
- * Copyright (c) 2003,2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Machine BAST - Memory map definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* needs arch/map.h including with this */
-
-/* ok, we've used up to 0x13000000, now we need to find space for the
- * peripherals that live in the nGCS[x] areas, which are quite numerous
- * in their space. We also have the board's CPLD to find register space
- * for.
- */
-
-#ifndef __ASM_ARCH_BASTMAP_H
-#define __ASM_ARCH_BASTMAP_H
-
-#define BAST_IOADDR(x)     (S3C2410_ADDR((x) + 0x01300000))
-
-/* we put the CPLD registers next, to get them out of the way */
-
-#define BAST_VA_CTRL1       BAST_IOADDR(0x00000000)      /* 0x01300000 */
-#define BAST_PA_CTRL1       (S3C2410_CS5 | 0x7800000)
-
-#define BAST_VA_CTRL2       BAST_IOADDR(0x00100000)      /* 0x01400000 */
-#define BAST_PA_CTRL2       (S3C2410_CS1 | 0x6000000)
-
-#define BAST_VA_CTRL3       BAST_IOADDR(0x00200000)      /* 0x01500000 */
-#define BAST_PA_CTRL3       (S3C2410_CS1 | 0x6800000)
-
-#define BAST_VA_CTRL4       BAST_IOADDR(0x00300000)      /* 0x01600000 */
-#define BAST_PA_CTRL4       (S3C2410_CS1 | 0x7000000)
-
-/* next, we have the PC104 ISA interrupt registers */
-
-#define BAST_PA_PC104_IRQREQ  (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
-#define BAST_VA_PC104_IRQREQ  BAST_IOADDR(0x00400000)
-
-#define BAST_PA_PC104_IRQRAW  (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
-#define BAST_VA_PC104_IRQRAW  BAST_IOADDR(0x00500000)
-
-#define BAST_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
-#define BAST_VA_PC104_IRQMASK BAST_IOADDR(0x00600000)
-
-#define BAST_PA_LCD_RCMD1     (0x8800000)
-#define BAST_VA_LCD_RCMD1     BAST_IOADDR(0x00700000)
-
-#define BAST_PA_LCD_WCMD1     (0x8000000)
-#define BAST_VA_LCD_WCMD1     BAST_IOADDR(0x00800000)
-
-#define BAST_PA_LCD_RDATA1    (0x9800000)
-#define BAST_VA_LCD_RDATA1    BAST_IOADDR(0x00900000)
-
-#define BAST_PA_LCD_WDATA1    (0x9000000)
-#define BAST_VA_LCD_WDATA1    BAST_IOADDR(0x00A00000)
-
-#define BAST_PA_LCD_RCMD2     (0xA800000)
-#define BAST_VA_LCD_RCMD2     BAST_IOADDR(0x00B00000)
-
-#define BAST_PA_LCD_WCMD2     (0xA000000)
-#define BAST_VA_LCD_WCMD2     BAST_IOADDR(0x00C00000)
-
-#define BAST_PA_LCD_RDATA2    (0xB800000)
-#define BAST_VA_LCD_RDATA2    BAST_IOADDR(0x00D00000)
-
-#define BAST_PA_LCD_WDATA2    (0xB000000)
-#define BAST_VA_LCD_WDATA2    BAST_IOADDR(0x00E00000)
-
-
-/* 0xE0000000 contains the IO space that is split by speed and
- * wether the access is for 8 or 16bit IO... this ensures that
- * the correct access is made
- *
- * 0x10000000 of space, partitioned as so:
- *
- * 0x00000000 to 0x04000000  8bit,  slow
- * 0x04000000 to 0x08000000  16bit, slow
- * 0x08000000 to 0x0C000000  16bit, net
- * 0x0C000000 to 0x10000000  16bit, fast
- *
- * each of these spaces has the following in:
- *
- * 0x00000000 to 0x01000000 16MB ISA IO space
- * 0x01000000 to 0x02000000 16MB ISA memory space
- * 0x02000000 to 0x02100000 1MB  IDE primary channel
- * 0x02100000 to 0x02200000 1MB  IDE primary channel aux
- * 0x02200000 to 0x02400000 1MB  IDE secondary channel
- * 0x02300000 to 0x02400000 1MB  IDE secondary channel aux
- * 0x02400000 to 0x02500000 1MB  ASIX ethernet controller
- * 0x02500000 to 0x02600000 1MB  Davicom DM9000 ethernet controller
- * 0x02600000 to 0x02700000 1MB  PC SuperIO controller
- *
- * the phyiscal layout of the zones are:
- *  nGCS2 - 8bit, slow
- *  nGCS3 - 16bit, slow
- *  nGCS4 - 16bit, net
- *  nGCS5 - 16bit, fast
- */
-
-#define BAST_VA_MULTISPACE (0xE0000000)
-
-#define BAST_VA_ISAIO      (BAST_VA_MULTISPACE + 0x00000000)
-#define BAST_VA_ISAMEM     (BAST_VA_MULTISPACE + 0x01000000)
-#define BAST_VA_IDEPRI     (BAST_VA_MULTISPACE + 0x02000000)
-#define BAST_VA_IDEPRIAUX  (BAST_VA_MULTISPACE + 0x02100000)
-#define BAST_VA_IDESEC     (BAST_VA_MULTISPACE + 0x02200000)
-#define BAST_VA_IDESECAUX  (BAST_VA_MULTISPACE + 0x02300000)
-#define BAST_VA_ASIXNET    (BAST_VA_MULTISPACE + 0x02400000)
-#define BAST_VA_DM9000     (BAST_VA_MULTISPACE + 0x02500000)
-#define BAST_VA_SUPERIO    (BAST_VA_MULTISPACE + 0x02600000)
-
-#define BAST_VA_MULTISPACE (0xE0000000)
-
-#define BAST_VAM_CS2 (0x00000000)
-#define BAST_VAM_CS3 (0x04000000)
-#define BAST_VAM_CS4 (0x08000000)
-#define BAST_VAM_CS5 (0x0C000000)
-
-/* physical offset addresses for the peripherals */
-
-#define BAST_PA_ISAIO     (0x00000000)
-#define BAST_PA_ASIXNET   (0x01000000)
-#define BAST_PA_SUPERIO   (0x01800000)
-#define BAST_PA_IDEPRI    (0x02000000)
-#define BAST_PA_IDEPRIAUX (0x02800000)
-#define BAST_PA_IDESEC    (0x03000000)
-#define BAST_PA_IDESECAUX (0x03800000)
-#define BAST_PA_ISAMEM    (0x04000000)
-#define BAST_PA_DM9000    (0x05000000)
-
-/* some configurations for the peripherals */
-
-#define BAST_PCSIO (BAST_VA_SUPERIO + BAST_VAM_CS2)
-/*  */
-
-#define BAST_ASIXNET_CS  BAST_VAM_CS5
-#define BAST_IDE_CS      BAST_VAM_CS5
-#define BAST_DM9000_CS   BAST_VAM_CS4
-
-#endif /* __ASM_ARCH_BASTMAP_H */
diff --git a/include/asm-arm/arch-s3c2410/bast-pmu.h b/include/asm-arm/arch-s3c2410/bast-pmu.h
deleted file mode 100644
index 37a11fe54a78..000000000000
--- a/include/asm-arm/arch-s3c2410/bast-pmu.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/bast-pmu.h
- *
- * Copyright (c) 2003,2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      Vincent Sanders <vince@simtec.co.uk>
- *
- * Machine BAST - Power Management chip
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_BASTPMU_H
-#define __ASM_ARCH_BASTPMU_H "08_OCT_2004"
-
-#define BASTPMU_REG_IDENT       (0x00)
-#define BASTPMU_REG_VERSION     (0x01)
-#define BASTPMU_REG_DDCCTRL     (0x02)
-#define BASTPMU_REG_POWER       (0x03)
-#define BASTPMU_REG_RESET       (0x04)
-#define BASTPMU_REG_GWO         (0x05)
-#define BASTPMU_REG_WOL         (0x06)
-#define BASTPMU_REG_WOR         (0x07)
-#define BASTPMU_REG_UID         (0x09)
-
-#define BASTPMU_EEPROM          (0xC0)
-
-#define BASTPMU_EEP_UID         (BASTPMU_EEPROM + 0)
-#define BASTPMU_EEP_WOL         (BASTPMU_EEPROM + 8)
-#define BASTPMU_EEP_WOR         (BASTPMU_EEPROM + 9)
-
-#define BASTPMU_IDENT_0         0x53
-#define BASTPMU_IDENT_1         0x42
-#define BASTPMU_IDENT_2         0x50
-#define BASTPMU_IDENT_3         0x4d
-
-#define BASTPMU_RESET_GUARD     (0x55)
-
-#endif /* __ASM_ARCH_BASTPMU_H */
diff --git a/include/asm-arm/arch-s3c2410/debug-macro.S b/include/asm-arm/arch-s3c2410/debug-macro.S
deleted file mode 100644
index 89076c322726..000000000000
--- a/include/asm-arm/arch-s3c2410/debug-macro.S
+++ /dev/null
@@ -1,102 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Copyright (C) 2005 Simtec Electronics
- *
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <asm/arch/map.h>
-#include <asm/arch/regs-gpio.h>
-#include <asm/plat-s3c/regs-serial.h>
-
-#define S3C2410_UART1_OFF (0x4000)
-#define SHIFT_2440TXF (14-9)
-
-        .macro addruart, rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1
-                ldreq   \rx, = S3C24XX_PA_UART
-                ldrne   \rx, = S3C24XX_VA_UART
-#if CONFIG_DEBUG_S3C_UART != 0
-                add     \rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
-#endif
-        .endm
-
-        .macro fifo_full_s3c24xx rd, rx
-                @ check for arm920 vs arm926. currently assume all arm926
-                @ devices have an 64 byte FIFO identical to the s3c2440
-                mrc     p15, 0, \rd, c0, c0
-                and     \rd, \rd, #0xff0
-                teq     \rd, #0x260
-                beq     1004f
-                mrc     p15, 0, \rd, c1, c0
-                tst     \rd, #1
-                addeq   \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
-                addne   \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART)
-                bic     \rd, \rd, #0xff000
-                ldr     \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ]
-                and     \rd, \rd, #0x00ff0000
-                teq     \rd, #0x00440000                @ is it 2440?
-1004:
-                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
-                moveq   \rd, \rd, lsr #SHIFT_2440TXF
-                tst     \rd, #S3C2410_UFSTAT_TXFULL
-        .endm
-
-        .macro  fifo_full_s3c2410 rd, rx
-                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
-                tst     \rd, #S3C2410_UFSTAT_TXFULL
-        .endm
-
-/* fifo level reading */
-
-        .macro fifo_level_s3c24xx rd, rx
-                @ check for arm920 vs arm926. currently assume all arm926
-                @ devices have an 64 byte FIFO identical to the s3c2440
-                mrc     p15, 0, \rd, c0, c0
-                and     \rd, \rd, #0xff0
-                teq     \rd, #0x260
-                beq     10000f
-                mrc     p15, 0, \rd, c1, c0
-                tst     \rd, #1
-                addeq   \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
-                addne   \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART)
-                bic     \rd, \rd, #0xff000
-                ldr     \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ]
-                and     \rd, \rd, #0x00ff0000
-                teq     \rd, #0x00440000                @ is it 2440?
-
-10000:
-                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
-                andne   \rd, \rd, #S3C2410_UFSTAT_TXMASK
-                andeq   \rd, \rd, #S3C2440_UFSTAT_TXMASK
-        .endm
-
-        .macro fifo_level_s3c2410 rd, rx
-                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
-                and     \rd, \rd, #S3C2410_UFSTAT_TXMASK
-        .endm
-
-/* Select the correct implementation depending on the configuration. The
- * S3C2440 will get selected by default, as these are the most widely
- * used variants of these
-*/
-
-#if defined(CONFIG_CPU_LLSERIAL_S3C2410_ONLY)
-#define fifo_full  fifo_full_s3c2410
-#define fifo_level fifo_level_s3c2410
-#elif !defined(CONFIG_CPU_LLSERIAL_S3C2440_ONLY)
-#define fifo_full  fifo_full_s3c24xx
-#define fifo_level fifo_level_s3c24xx
-#endif
-
-/* include the reset of the code which will do the work */
-
-#include <asm/plat-s3c/debug-macro.S>
diff --git a/include/asm-arm/arch-s3c2410/dma.h b/include/asm-arm/arch-s3c2410/dma.h
deleted file mode 100644
index 86eaa0c2dc1e..000000000000
--- a/include/asm-arm/arch-s3c2410/dma.h
+++ /dev/null
@@ -1,453 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/dma.h
- *
- * Copyright (C) 2003,2004,2006 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Samsung S3C241XX DMA support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H __FILE__
-
-#include <linux/sysdev.h>
-#include <asm/arch/hardware.h>
-
-/*
- * This is the maximum DMA address(physical address) that can be DMAd to.
- *
- */
-#define MAX_DMA_ADDRESS         0x40000000
-#define MAX_DMA_TRANSFER_SIZE   0x100000 /* Data Unit is half word  */
-
-/* We use `virtual` dma channels to hide the fact we have only a limited
- * number of DMA channels, and not of all of them (dependant on the device)
- * can be attached to any DMA source. We therefore let the DMA core handle
- * the allocation of hardware channels to clients.
-*/
-
-enum dma_ch {
-        DMACH_XD0,
-        DMACH_XD1,
-        DMACH_SDI,
-        DMACH_SPI0,
-        DMACH_SPI1,
-        DMACH_UART0,
-        DMACH_UART1,
-        DMACH_UART2,
-        DMACH_TIMER,
-        DMACH_I2S_IN,
-        DMACH_I2S_OUT,
-        DMACH_PCM_IN,
-        DMACH_PCM_OUT,
-        DMACH_MIC_IN,
-        DMACH_USB_EP1,
-        DMACH_USB_EP2,
-        DMACH_USB_EP3,
-        DMACH_USB_EP4,
-        DMACH_UART0_SRC2,       /* s3c2412 second uart sources */
-        DMACH_UART1_SRC2,
-        DMACH_UART2_SRC2,
-        DMACH_UART3,            /* s3c2443 has extra uart */
-        DMACH_UART3_SRC2,
-        DMACH_MAX,              /* the end entry */
-};
-
-#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
-
-/* we have 4 dma channels */
-#ifndef CONFIG_CPU_S3C2443
-#define S3C2410_DMA_CHANNELS            (4)
-#else
-#define S3C2410_DMA_CHANNELS            (6)
-#endif
-
-/* types */
-
-enum s3c2410_dma_state {
-        S3C2410_DMA_IDLE,
-        S3C2410_DMA_RUNNING,
-        S3C2410_DMA_PAUSED
-};
-
-
-/* enum s3c2410_dma_loadst
- *
- * This represents the state of the DMA engine, wrt to the loaded / running
- * transfers. Since we don't have any way of knowing exactly the state of
- * the DMA transfers, we need to know the state to make decisions on wether
- * we can
- *
- * S3C2410_DMA_NONE
- *
- * There are no buffers loaded (the channel should be inactive)
- *
- * S3C2410_DMA_1LOADED
- *
- * There is one buffer loaded, however it has not been confirmed to be
- * loaded by the DMA engine. This may be because the channel is not
- * yet running, or the DMA driver decided that it was too costly to
- * sit and wait for it to happen.
- *
- * S3C2410_DMA_1RUNNING
- *
- * The buffer has been confirmed running, and not finisged
- *
- * S3C2410_DMA_1LOADED_1RUNNING
- *
- * There is a buffer waiting to be loaded by the DMA engine, and one
- * currently running.
-*/
-
-enum s3c2410_dma_loadst {
-        S3C2410_DMALOAD_NONE,
-        S3C2410_DMALOAD_1LOADED,
-        S3C2410_DMALOAD_1RUNNING,
-        S3C2410_DMALOAD_1LOADED_1RUNNING,
-};
-
-enum s3c2410_dma_buffresult {
-        S3C2410_RES_OK,
-        S3C2410_RES_ERR,
-        S3C2410_RES_ABORT
-};
-
-enum s3c2410_dmasrc {
-        S3C2410_DMASRC_HW,              /* source is memory */
-        S3C2410_DMASRC_MEM              /* source is hardware */
-};
-
-/* enum s3c2410_chan_op
- *
- * operation codes passed to the DMA code by the user, and also used
- * to inform the current channel owner of any changes to the system state
-*/
-
-enum s3c2410_chan_op {
-        S3C2410_DMAOP_START,
-        S3C2410_DMAOP_STOP,
-        S3C2410_DMAOP_PAUSE,
-        S3C2410_DMAOP_RESUME,
-        S3C2410_DMAOP_FLUSH,
-        S3C2410_DMAOP_TIMEOUT,          /* internal signal to handler */
-        S3C2410_DMAOP_STARTED,          /* indicate channel started */
-};
-
-/* flags */
-
-#define S3C2410_DMAF_SLOW         (1<<0)   /* slow, so don't worry about
-                                            * waiting for reloads */
-#define S3C2410_DMAF_AUTOSTART    (1<<1)   /* auto-start if buffer queued */
-
-/* dma buffer */
-
-struct s3c2410_dma_client {
-        char                *name;
-};
-
-/* s3c2410_dma_buf_s
- *
- * internally used buffer structure to describe a queued or running
- * buffer.
-*/
-
-struct s3c2410_dma_buf;
-struct s3c2410_dma_buf {
-        struct s3c2410_dma_buf  *next;
-        int                      magic;         /* magic */
-        int                      size;          /* buffer size in bytes */
-        dma_addr_t               data;          /* start of DMA data */
-        dma_addr_t               ptr;           /* where the DMA got to [1] */
-        void                    *id;            /* client's id */
-};
-
-/* [1] is this updated for both recv/send modes? */
-
-struct s3c2410_dma_chan;
-
-/* s3c2410_dma_cbfn_t
- *
- * buffer callback routine type
-*/
-
-typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
-                                   void *buf, int size,
-                                   enum s3c2410_dma_buffresult result);
-
-typedef int  (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
-                                   enum s3c2410_chan_op );
-
-struct s3c2410_dma_stats {
-        unsigned long           loads;
-        unsigned long           timeout_longest;
-        unsigned long           timeout_shortest;
-        unsigned long           timeout_avg;
-        unsigned long           timeout_failed;
-};
-
-struct s3c2410_dma_map;
-
-/* struct s3c2410_dma_chan
- *
- * full state information for each DMA channel
-*/
-
-struct s3c2410_dma_chan {
-        /* channel state flags and information */
-        unsigned char            number;      /* number of this dma channel */
-        unsigned char            in_use;      /* channel allocated */
-        unsigned char            irq_claimed; /* irq claimed for channel */
-        unsigned char            irq_enabled; /* irq enabled for channel */
-        unsigned char            xfer_unit;   /* size of an transfer */
-
-        /* channel state */
-
-        enum s3c2410_dma_state   state;
-        enum s3c2410_dma_loadst  load_state;
-        struct s3c2410_dma_client *client;
-
-        /* channel configuration */
-        enum s3c2410_dmasrc      source;
-        unsigned long            dev_addr;
-        unsigned long            load_timeout;
-        unsigned int             flags;         /* channel flags */
-        unsigned int             hw_cfg;        /* last hw config */
-
-        struct s3c24xx_dma_map  *map;           /* channel hw maps */
-
-        /* channel's hardware position and configuration */
-        void __iomem            *regs;          /* channels registers */
-        void __iomem            *addr_reg;      /* data address register */
-        unsigned int             irq;           /* channel irq */
-        unsigned long            dcon;          /* default value of DCON */
-
-        /* driver handles */
-        s3c2410_dma_cbfn_t       callback_fn;   /* buffer done callback */
-        s3c2410_dma_opfn_t       op_fn;         /* channel op callback */
-
-        /* stats gathering */
-        struct s3c2410_dma_stats *stats;
-        struct s3c2410_dma_stats  stats_store;
-
-        /* buffer list and information */
-        struct s3c2410_dma_buf  *curr;          /* current dma buffer */
-        struct s3c2410_dma_buf  *next;          /* next buffer to load */
-        struct s3c2410_dma_buf  *end;           /* end of queue */
-
-        /* system device */
-        struct sys_device       dev;
-};
-
-/* the currently allocated channel information */
-extern struct s3c2410_dma_chan s3c2410_chans[];
-
-/* note, we don't really use dma_device_t at the moment */
-typedef unsigned long dma_device_t;
-
-/* functions --------------------------------------------------------------- */
-
-/* s3c2410_dma_request
- *
- * request a dma channel exclusivley
-*/
-
-extern int s3c2410_dma_request(dmach_t channel,
-                               struct s3c2410_dma_client *, void *dev);
-
-
-/* s3c2410_dma_ctrl
- *
- * change the state of the dma channel
-*/
-
-extern int s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op);
-
-/* s3c2410_dma_setflags
- *
- * set the channel's flags to a given state
-*/
-
-extern int s3c2410_dma_setflags(dmach_t channel,
-                                unsigned int flags);
-
-/* s3c2410_dma_free
- *
- * free the dma channel (will also abort any outstanding operations)
-*/
-
-extern int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *);
-
-/* s3c2410_dma_enqueue
- *
- * place the given buffer onto the queue of operations for the channel.
- * The buffer must be allocated from dma coherent memory, or the Dcache/WB
- * drained before the buffer is given to the DMA system.
-*/
-
-extern int s3c2410_dma_enqueue(dmach_t channel, void *id,
-                               dma_addr_t data, int size);
-
-/* s3c2410_dma_config
- *
- * configure the dma channel
-*/
-
-extern int s3c2410_dma_config(dmach_t channel, int xferunit, int dcon);
-
-/* s3c2410_dma_devconfig
- *
- * configure the device we're talking to
-*/
-
-extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
-                                 int hwcfg, unsigned long devaddr);
-
-/* s3c2410_dma_getposition
- *
- * get the position that the dma transfer is currently at
-*/
-
-extern int s3c2410_dma_getposition(dmach_t channel,
-                                   dma_addr_t *src, dma_addr_t *dest);
-
-extern int s3c2410_dma_set_opfn(dmach_t, s3c2410_dma_opfn_t rtn);
-extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn);
-
-/* DMA Register definitions */
-
-#define S3C2410_DMA_DISRC       (0x00)
-#define S3C2410_DMA_DISRCC      (0x04)
-#define S3C2410_DMA_DIDST       (0x08)
-#define S3C2410_DMA_DIDSTC      (0x0C)
-#define S3C2410_DMA_DCON        (0x10)
-#define S3C2410_DMA_DSTAT       (0x14)
-#define S3C2410_DMA_DCSRC       (0x18)
-#define S3C2410_DMA_DCDST       (0x1C)
-#define S3C2410_DMA_DMASKTRIG   (0x20)
-#define S3C2412_DMA_DMAREQSEL   (0x24)
-#define S3C2443_DMA_DMAREQSEL   (0x24)
-
-#define S3C2410_DISRCC_INC      (1<<0)
-#define S3C2410_DISRCC_APB      (1<<1)
-
-#define S3C2410_DMASKTRIG_STOP   (1<<2)
-#define S3C2410_DMASKTRIG_ON     (1<<1)
-#define S3C2410_DMASKTRIG_SWTRIG (1<<0)
-
-#define S3C2410_DCON_DEMAND     (0<<31)
-#define S3C2410_DCON_HANDSHAKE  (1<<31)
-#define S3C2410_DCON_SYNC_PCLK  (0<<30)
-#define S3C2410_DCON_SYNC_HCLK  (1<<30)
-
-#define S3C2410_DCON_INTREQ     (1<<29)
-
-#define S3C2410_DCON_CH0_XDREQ0 (0<<24)
-#define S3C2410_DCON_CH0_UART0  (1<<24)
-#define S3C2410_DCON_CH0_SDI    (2<<24)
-#define S3C2410_DCON_CH0_TIMER  (3<<24)
-#define S3C2410_DCON_CH0_USBEP1 (4<<24)
-
-#define S3C2410_DCON_CH1_XDREQ1 (0<<24)
-#define S3C2410_DCON_CH1_UART1  (1<<24)
-#define S3C2410_DCON_CH1_I2SSDI (2<<24)
-#define S3C2410_DCON_CH1_SPI    (3<<24)
-#define S3C2410_DCON_CH1_USBEP2 (4<<24)
-
-#define S3C2410_DCON_CH2_I2SSDO (0<<24)
-#define S3C2410_DCON_CH2_I2SSDI (1<<24)
-#define S3C2410_DCON_CH2_SDI    (2<<24)
-#define S3C2410_DCON_CH2_TIMER  (3<<24)
-#define S3C2410_DCON_CH2_USBEP3 (4<<24)
-
-#define S3C2410_DCON_CH3_UART2  (0<<24)
-#define S3C2410_DCON_CH3_SDI    (1<<24)
-#define S3C2410_DCON_CH3_SPI    (2<<24)
-#define S3C2410_DCON_CH3_TIMER  (3<<24)
-#define S3C2410_DCON_CH3_USBEP4 (4<<24)
-
-#define S3C2410_DCON_SRCSHIFT   (24)
-#define S3C2410_DCON_SRCMASK    (7<<24)
-
-#define S3C2410_DCON_BYTE       (0<<20)
-#define S3C2410_DCON_HALFWORD   (1<<20)
-#define S3C2410_DCON_WORD       (2<<20)
-
-#define S3C2410_DCON_AUTORELOAD (0<<22)
-#define S3C2410_DCON_NORELOAD   (1<<22)
-#define S3C2410_DCON_HWTRIG     (1<<23)
-
-#ifdef CONFIG_CPU_S3C2440
-#define S3C2440_DIDSTC_CHKINT   (1<<2)
-
-#define S3C2440_DCON_CH0_I2SSDO (5<<24)
-#define S3C2440_DCON_CH0_PCMIN  (6<<24)
-
-#define S3C2440_DCON_CH1_PCMOUT (5<<24)
-#define S3C2440_DCON_CH1_SDI    (6<<24)
-
-#define S3C2440_DCON_CH2_PCMIN  (5<<24)
-#define S3C2440_DCON_CH2_MICIN  (6<<24)
-
-#define S3C2440_DCON_CH3_MICIN  (5<<24)
-#define S3C2440_DCON_CH3_PCMOUT (6<<24)
-#endif
-
-#ifdef CONFIG_CPU_S3C2412
-
-#define S3C2412_DMAREQSEL_SRC(x)        ((x)<<1)
-
-#define S3C2412_DMAREQSEL_HW            (1)
-
-#define S3C2412_DMAREQSEL_SPI0TX        S3C2412_DMAREQSEL_SRC(0)
-#define S3C2412_DMAREQSEL_SPI0RX        S3C2412_DMAREQSEL_SRC(1)
-#define S3C2412_DMAREQSEL_SPI1TX        S3C2412_DMAREQSEL_SRC(2)
-#define S3C2412_DMAREQSEL_SPI1RX        S3C2412_DMAREQSEL_SRC(3)
-#define S3C2412_DMAREQSEL_I2STX         S3C2412_DMAREQSEL_SRC(4)
-#define S3C2412_DMAREQSEL_I2SRX         S3C2412_DMAREQSEL_SRC(5)
-#define S3C2412_DMAREQSEL_TIMER         S3C2412_DMAREQSEL_SRC(9)
-#define S3C2412_DMAREQSEL_SDI           S3C2412_DMAREQSEL_SRC(10)
-#define S3C2412_DMAREQSEL_USBEP1        S3C2412_DMAREQSEL_SRC(13)
-#define S3C2412_DMAREQSEL_USBEP2        S3C2412_DMAREQSEL_SRC(14)
-#define S3C2412_DMAREQSEL_USBEP3        S3C2412_DMAREQSEL_SRC(15)
-#define S3C2412_DMAREQSEL_USBEP4        S3C2412_DMAREQSEL_SRC(16)
-#define S3C2412_DMAREQSEL_XDREQ0        S3C2412_DMAREQSEL_SRC(17)
-#define S3C2412_DMAREQSEL_XDREQ1        S3C2412_DMAREQSEL_SRC(18)
-#define S3C2412_DMAREQSEL_UART0_0       S3C2412_DMAREQSEL_SRC(19)
-#define S3C2412_DMAREQSEL_UART0_1       S3C2412_DMAREQSEL_SRC(20)
-#define S3C2412_DMAREQSEL_UART1_0       S3C2412_DMAREQSEL_SRC(21)
-#define S3C2412_DMAREQSEL_UART1_1       S3C2412_DMAREQSEL_SRC(22)
-#define S3C2412_DMAREQSEL_UART2_0       S3C2412_DMAREQSEL_SRC(23)
-#define S3C2412_DMAREQSEL_UART2_1       S3C2412_DMAREQSEL_SRC(24)
-
-#endif
-
-#define S3C2443_DMAREQSEL_SRC(x)        ((x)<<1)
-
-#define S3C2443_DMAREQSEL_HW            (1)
-
-#define S3C2443_DMAREQSEL_SPI0TX        S3C2443_DMAREQSEL_SRC(0)
-#define S3C2443_DMAREQSEL_SPI0RX        S3C2443_DMAREQSEL_SRC(1)
-#define S3C2443_DMAREQSEL_SPI1TX        S3C2443_DMAREQSEL_SRC(2)
-#define S3C2443_DMAREQSEL_SPI1RX        S3C2443_DMAREQSEL_SRC(3)
-#define S3C2443_DMAREQSEL_I2STX         S3C2443_DMAREQSEL_SRC(4)
-#define S3C2443_DMAREQSEL_I2SRX         S3C2443_DMAREQSEL_SRC(5)
-#define S3C2443_DMAREQSEL_TIMER         S3C2443_DMAREQSEL_SRC(9)
-#define S3C2443_DMAREQSEL_SDI           S3C2443_DMAREQSEL_SRC(10)
-#define S3C2443_DMAREQSEL_XDREQ0        S3C2443_DMAREQSEL_SRC(17)
-#define S3C2443_DMAREQSEL_XDREQ1        S3C2443_DMAREQSEL_SRC(18)
-#define S3C2443_DMAREQSEL_UART0_0       S3C2443_DMAREQSEL_SRC(19)
-#define S3C2443_DMAREQSEL_UART0_1       S3C2443_DMAREQSEL_SRC(20)
-#define S3C2443_DMAREQSEL_UART1_0       S3C2443_DMAREQSEL_SRC(21)
-#define S3C2443_DMAREQSEL_UART1_1       S3C2443_DMAREQSEL_SRC(22)
-#define S3C2443_DMAREQSEL_UART2_0       S3C2443_DMAREQSEL_SRC(23)
-#define S3C2443_DMAREQSEL_UART2_1       S3C2443_DMAREQSEL_SRC(24)
-#define S3C2443_DMAREQSEL_UART3_0       S3C2443_DMAREQSEL_SRC(25)
-#define S3C2443_DMAREQSEL_UART3_1       S3C2443_DMAREQSEL_SRC(26)
-#define S3C2443_DMAREQSEL_PCMOUT        S3C2443_DMAREQSEL_SRC(27)
-#define S3C2443_DMAREQSEL_PCMIN         S3C2443_DMAREQSEL_SRC(28)
-#define S3C2443_DMAREQSEL_MICIN         S3C2443_DMAREQSEL_SRC(29)
-
-#endif /* __ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-s3c2410/entry-macro.S b/include/asm-arm/arch-s3c2410/entry-macro.S
deleted file mode 100644
index f70d051b267b..000000000000
--- a/include/asm-arm/arch-s3c2410/entry-macro.S
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * include/asm-arm/arch-s3c2410/entry-macro.S
- *
- * Low-level IRQ helper macros for S3C2410-based platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
-*/
-
-/* We have a problem that the INTOFFSET register does not always
- * show one interrupt. Occasionally we get two interrupts through
- * the prioritiser, and this causes the INTOFFSET register to show
- * what looks like the logical-or of the two interrupt numbers.
- *
- * Thanks to Klaus, Shannon, et al for helping to debug this problem
-*/
-
-#define INTPND          (0x10)
-#define INTOFFSET       (0x14)
-
-#include <asm/arch/hardware.h>
-#include <asm/irq.h>
-
-        .macro  get_irqnr_preamble, base, tmp
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-
-                mov     \base, #S3C24XX_VA_IRQ
-
-                @@ try the interrupt offset register, since it is there
-
-                ldr     \irqstat, [ \base, #INTPND ]
-                teq     \irqstat, #0
-                beq     1002f
-                ldr     \irqnr, [ \base, #INTOFFSET ]
-                mov     \tmp, #1
-                tst     \irqstat, \tmp, lsl \irqnr
-                bne     1001f
-
-                @@ the number specified is not a valid irq, so try
-                @@ and work it out for ourselves
-
-                mov     \irqnr, #0              @@ start here
-
-                @@ work out which irq (if any) we got
-
-                movs    \tmp, \irqstat, lsl#16
-                addeq   \irqnr, \irqnr, #16
-                moveq   \irqstat, \irqstat, lsr#16
-                tst     \irqstat, #0xff
-                addeq   \irqnr, \irqnr, #8
-                moveq   \irqstat, \irqstat, lsr#8
-                tst     \irqstat, #0xf
-                addeq   \irqnr, \irqnr, #4
-                moveq   \irqstat, \irqstat, lsr#4
-                tst     \irqstat, #0x3
-                addeq   \irqnr, \irqnr, #2
-                moveq   \irqstat, \irqstat, lsr#2
-                tst     \irqstat, #0x1
-                addeq   \irqnr, \irqnr, #1
-
-                @@ we have the value
-1001:
-                adds    \irqnr, \irqnr, #IRQ_EINT0
-1002:
-                @@ exit here, Z flag unset if IRQ
-
-        .endm
-
-                /* currently don't need an disable_fiq macro */
-
-                .macro  disable_fiq
-                .endm
diff --git a/include/asm-arm/arch-s3c2410/fb.h b/include/asm-arm/arch-s3c2410/fb.h
deleted file mode 100644
index 5d0262601a7e..000000000000
--- a/include/asm-arm/arch-s3c2410/fb.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/fb.h
- *
- * Copyright (c) 2004 Arnaud Patard <arnaud.patard@rtp-net.org>
- *
- * Inspired by pxafb.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARM_FB_H
-#define __ASM_ARM_FB_H
-
-#include <asm/arch/regs-lcd.h>
-
-struct s3c2410fb_hw {
-        unsigned long   lcdcon1;
-        unsigned long   lcdcon2;
-        unsigned long   lcdcon3;
-        unsigned long   lcdcon4;
-        unsigned long   lcdcon5;
-};
-
-/* LCD description */
-struct s3c2410fb_display {
-        /* LCD type */
-        unsigned type;
-
-        /* Screen size */
-        unsigned short width;
-        unsigned short height;
-
-        /* Screen info */
-        unsigned short xres;
-        unsigned short yres;
-        unsigned short bpp;
-
-        unsigned pixclock;              /* pixclock in picoseconds */
-        unsigned short left_margin;  /* value in pixels (TFT) or HCLKs (STN) */
-        unsigned short right_margin; /* value in pixels (TFT) or HCLKs (STN) */
-        unsigned short hsync_len;    /* value in pixels (TFT) or HCLKs (STN) */
-        unsigned short upper_margin;    /* value in lines (TFT) or 0 (STN) */
-        unsigned short lower_margin;    /* value in lines (TFT) or 0 (STN) */
-        unsigned short vsync_len;       /* value in lines (TFT) or 0 (STN) */
-
-        /* lcd configuration registers */
-        unsigned long   lcdcon5;
-};
-
-struct s3c2410fb_mach_info {
-
-        struct s3c2410fb_display *displays;     /* attached diplays info */
-        unsigned num_displays;                  /* number of defined displays */
-        unsigned default_display;
-
-        /* GPIOs */
-
-        unsigned long   gpcup;
-        unsigned long   gpcup_mask;
-        unsigned long   gpccon;
-        unsigned long   gpccon_mask;
-        unsigned long   gpdup;
-        unsigned long   gpdup_mask;
-        unsigned long   gpdcon;
-        unsigned long   gpdcon_mask;
-
-        /* lpc3600 control register */
-        unsigned long   lpcsel;
-};
-
-extern void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *);
-
-#endif /* __ASM_ARM_FB_H */
diff --git a/include/asm-arm/arch-s3c2410/gpio.h b/include/asm-arm/arch-s3c2410/gpio.h
deleted file mode 100644
index 18e10d2c35ea..000000000000
--- a/include/asm-arm/arch-s3c2410/gpio.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/gpio.h
- *
- * Copyright (c) 2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - GPIO lib support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#define gpio_get_value  __gpio_get_value
-#define gpio_set_value  __gpio_set_value
-#define gpio_cansleep   __gpio_cansleep
-
-#include <asm-generic/gpio.h>
diff --git a/include/asm-arm/arch-s3c2410/h1940-latch.h b/include/asm-arm/arch-s3c2410/h1940-latch.h
deleted file mode 100644
index c3de5ab102eb..000000000000
--- a/include/asm-arm/arch-s3c2410/h1940-latch.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/h1940-latch.h
- *
- * Copyright (c) 2005 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- *  iPAQ H1940 series - latch definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_H1940_LATCH_H
-#define __ASM_ARCH_H1940_LATCH_H
-
-
-#ifndef __ASSEMBLY__
-#define H1940_LATCH             ((void __force __iomem *)0xF8000000)
-#else
-#define H1940_LATCH             0xF8000000
-#endif
-
-#define H1940_PA_LATCH          (S3C2410_CS2)
-
-/* SD layer latch */
-
-#define H1940_LATCH_SDQ1                (1<<16)
-#define H1940_LATCH_LCD_P1              (1<<17)
-#define H1940_LATCH_LCD_P2              (1<<18)
-#define H1940_LATCH_LCD_P3              (1<<19)
-#define H1940_LATCH_MAX1698_nSHUTDOWN   (1<<20)         /* LCD backlight */
-#define H1940_LATCH_LED_RED             (1<<21)
-#define H1940_LATCH_SDQ7                (1<<22)
-#define H1940_LATCH_USB_DP              (1<<23)
-
-/* CPU layer latch */
-
-#define H1940_LATCH_UDA_POWER           (1<<24)
-#define H1940_LATCH_AUDIO_POWER         (1<<25)
-#define H1940_LATCH_SM803_ENABLE        (1<<26)
-#define H1940_LATCH_LCD_P4              (1<<27)
-#define H1940_LATCH_CPUQ5               (1<<28)         /* untraced */
-#define H1940_LATCH_BLUETOOTH_POWER     (1<<29)         /* active high */
-#define H1940_LATCH_LED_GREEN           (1<<30)
-#define H1940_LATCH_LED_FLASH           (1<<31)
-
-/* default settings */
-
-#define H1940_LATCH_DEFAULT             \
-        H1940_LATCH_LCD_P4              | \
-        H1940_LATCH_SM803_ENABLE        | \
-        H1940_LATCH_SDQ1                | \
-        H1940_LATCH_LCD_P1              | \
-        H1940_LATCH_LCD_P2              | \
-        H1940_LATCH_LCD_P3              | \
-        H1940_LATCH_MAX1698_nSHUTDOWN   | \
-        H1940_LATCH_CPUQ5
-
-/* control functions */
-
-extern void h1940_latch_control(unsigned int clear, unsigned int set);
-
-#endif /* __ASM_ARCH_H1940_LATCH_H */
diff --git a/include/asm-arm/arch-s3c2410/h1940.h b/include/asm-arm/arch-s3c2410/h1940.h
deleted file mode 100644
index 6135592e60f2..000000000000
--- a/include/asm-arm/arch-s3c2410/h1940.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/h1940.h
- *
- * Copyright 2006 Ben Dooks <ben-linux@fluff.org>
- *
- * H1940 definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_H1940_H
-#define __ASM_ARCH_H1940_H
-
-#define H1940_SUSPEND_CHECKSUM          (0x30003ff8)
-#define H1940_SUSPEND_RESUMEAT          (0x30081000)
-#define H1940_SUSPEND_CHECK             (0x30080000)
-
-extern void h1940_pm_return(void);
-
-#endif /* __ASM_ARCH_H1940_H */
diff --git a/include/asm-arm/arch-s3c2410/hardware.h b/include/asm-arm/arch-s3c2410/hardware.h
deleted file mode 100644
index 6dd10be43145..000000000000
--- a/include/asm-arm/arch-s3c2410/hardware.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/hardware.h
- *
- * Copyright (c) 2003 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - hardware
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#ifndef __ASSEMBLY__
-
-/* external functions for GPIO support
- *
- * These allow various different clients to access the same GPIO
- * registers without conflicting. If your driver only owns the entire
- * GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
-*/
-
-/* s3c2410_gpio_cfgpin
- *
- * set the configuration of the given pin to the value passed.
- *
- * eg:
- *    s3c2410_gpio_cfgpin(S3C2410_GPA0, S3C2410_GPA0_ADDR0);
- *    s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1);
-*/
-
-extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function);
-
-extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
-
-/* s3c2410_gpio_getirq
- *
- * turn the given pin number into the corresponding IRQ number
- *
- * returns:
- *      < 0 = no interrupt for this pin
- *      >=0 = interrupt number for the pin
-*/
-
-extern int s3c2410_gpio_getirq(unsigned int pin);
-
-/* s3c2410_gpio_irq2pin
- *
- * turn the given irq number into the corresponding GPIO number
- *
- * returns:
- *      < 0 = no pin
- *      >=0 = gpio pin number
-*/
-
-extern int s3c2410_gpio_irq2pin(unsigned int irq);
-
-#ifdef CONFIG_CPU_S3C2400
-
-extern int s3c2400_gpio_getirq(unsigned int pin);
-
-#endif /* CONFIG_CPU_S3C2400 */
-
-/* s3c2410_gpio_irqfilter
- *
- * set the irq filtering on the given pin
- *
- * on = 0 => disable filtering
- *      1 => enable filtering
- *
- * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with
- *          width of filter (0 through 63)
- *
- *
-*/
-
-extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
-                                  unsigned int config);
-
-/* s3c2410_gpio_pullup
- *
- * configure the pull-up control on the given pin
- *
- * to = 1 => disable the pull-up
- *      0 => enable the pull-up
- *
- * eg;
- *
- *   s3c2410_gpio_pullup(S3C2410_GPB0, 0);
- *   s3c2410_gpio_pullup(S3C2410_GPE8, 0);
-*/
-
-extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
-
-/* s3c2410_gpio_getpull
- *
- * Read the state of the pull-up on a given pin
- *
- * return:
- *      < 0 => error code
- *        0 => enabled
- *        1 => disabled
-*/
-
-extern int s3c2410_gpio_getpull(unsigned int pin);
-
-extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
-
-extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
-
-extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg);
-
-#ifdef CONFIG_CPU_S3C2440
-
-extern int s3c2440_set_dsc(unsigned int pin, unsigned int value);
-
-#endif /* CONFIG_CPU_S3C2440 */
-
-#ifdef CONFIG_CPU_S3C2412
-
-extern int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state);
-
-#endif /* CONFIG_CPU_S3C2412 */
-
-#endif /* __ASSEMBLY__ */
-
-#include <asm/sizes.h>
-#include <asm/arch/map.h>
-
-/* machine specific hardware definitions should go after this */
-
-/* currently here until moved into config (todo) */
-#define CONFIG_NO_MULTIWORD_IO
-
-#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-s3c2410/idle.h b/include/asm-arm/arch-s3c2410/idle.h
deleted file mode 100644
index eed450608f9c..000000000000
--- a/include/asm-arm/arch-s3c2410/idle.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/idle.h
- *
- * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
- *              http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 CPU Idle controls
-*/
-
-#ifndef __ASM_ARCH_IDLE_H
-#define __ASM_ARCH_IDLE_H __FILE__
-
-/* This allows the over-ride of the default idle code, in case there
- * is any other things to be done over idle (like DVS)
-*/
-
-extern void (*s3c24xx_idle)(void);
-
-extern void s3c24xx_default_idle(void);
-
-#endif /* __ASM_ARCH_IDLE_H */
diff --git a/include/asm-arm/arch-s3c2410/io.h b/include/asm-arm/arch-s3c2410/io.h
deleted file mode 100644
index 3756c993776c..000000000000
--- a/include/asm-arm/arch-s3c2410/io.h
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
- * linux/include/asm-arm/arch-s3c2410/io.h
- *  from linux/include/asm-arm/arch-rpc/io.h
- *
- * Copyright (C) 1997 Russell King
- *           (C) 2003 Simtec Electronics
-*/
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#include <asm/arch/hardware.h>
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/*
- * We use two different types of addressing - PC style addresses, and ARM
- * addresses.  PC style accesses the PC hardware with the normal PC IO
- * addresses, eg 0x3f8 for serial#1.  ARM addresses are above A28
- * and are translated to the start of IO.  Note that all addresses are
- * not shifted left!
- */
-
-#define __PORT_PCIO(x)  ((x) < (1<<28))
-
-#define PCIO_BASE        (S3C24XX_VA_ISA_WORD)
-#define PCIO_BASE_b      (S3C24XX_VA_ISA_BYTE)
-#define PCIO_BASE_w      (S3C24XX_VA_ISA_WORD)
-#define PCIO_BASE_l      (S3C24XX_VA_ISA_WORD)
-/*
- * Dynamic IO functions - let the compiler
- * optimize the expressions
- */
-
-#define DECLARE_DYN_OUT(sz,fnsuffix,instr) \
-static inline void __out##fnsuffix (unsigned int val, unsigned int port) \
-{ \
-        unsigned long temp;                                   \
-        __asm__ __volatile__(                                 \
-        "cmp    %2, #(1<<28)\n\t"                             \
-        "mov    %0, %2\n\t"                                   \
-        "addcc  %0, %0, %3\n\t"                               \
-        "str" instr " %1, [%0, #0 ]     @ out" #fnsuffix      \
-        : "=&r" (temp)                                        \
-        : "r" (val), "r" (port), "Ir" (PCIO_BASE_##fnsuffix)  \
-        : "cc");                                              \
-}
-
-
-#define DECLARE_DYN_IN(sz,fnsuffix,instr)                               \
-static inline unsigned sz __in##fnsuffix (unsigned int port)            \
-{                                                                       \
-        unsigned long temp, value;                                      \
-        __asm__ __volatile__(                                           \
-        "cmp    %2, #(1<<28)\n\t"                                       \
-        "mov    %0, %2\n\t"                                             \
-        "addcc  %0, %0, %3\n\t"                                         \
-        "ldr" instr "   %1, [%0, #0 ]   @ in" #fnsuffix         \
-        : "=&r" (temp), "=r" (value)                                    \
-        : "r" (port), "Ir" (PCIO_BASE_##fnsuffix)       \
-        : "cc");                                                        \
-        return (unsigned sz)value;                                      \
-}
-
-static inline void __iomem *__ioaddr (unsigned long port)
-{
-        return __PORT_PCIO(port) ? (PCIO_BASE + port) : (void __iomem *)port;
-}
-
-#define DECLARE_IO(sz,fnsuffix,instr)   \
-        DECLARE_DYN_IN(sz,fnsuffix,instr) \
-        DECLARE_DYN_OUT(sz,fnsuffix,instr)
-
-DECLARE_IO(char,b,"b")
-DECLARE_IO(short,w,"h")
-DECLARE_IO(int,l,"")
-
-#undef DECLARE_IO
-#undef DECLARE_DYN_IN
-
-/*
- * Constant address IO functions
- *
- * These have to be macros for the 'J' constraint to work -
- * +/-4096 immediate operand.
- */
-#define __outbc(value,port)                                             \
-({                                                                      \
-        if (__PORT_PCIO((port)))                                        \
-                __asm__ __volatile__(                                   \
-                "strb   %0, [%1, %2]    @ outbc"                        \
-                : : "r" (value), "r" (PCIO_BASE), "Jr" ((port)));       \
-        else                                                            \
-                __asm__ __volatile__(                                   \
-                "strb   %0, [%1, #0]    @ outbc"                        \
-                : : "r" (value), "r" ((port)));                         \
-})
-
-#define __inbc(port)                                                    \
-({                                                                      \
-        unsigned char result;                                           \
-        if (__PORT_PCIO((port)))                                        \
-                __asm__ __volatile__(                                   \
-                "ldrb   %0, [%1, %2]    @ inbc"                         \
-                : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port)));      \
-        else                                                            \
-                __asm__ __volatile__(                                   \
-                "ldrb   %0, [%1, #0]    @ inbc"                         \
-                : "=r" (result) : "r" ((port)));                        \
-        result;                                                         \
-})
-
-#define __outwc(value,port)                                             \
-({                                                                      \
-        unsigned long v = value;                                        \
-        if (__PORT_PCIO((port))) {                                      \
-                if ((port) < 256 && (port) > -256)                      \
-                        __asm__ __volatile__(                           \
-                        "strh   %0, [%1, %2]    @ outwc"                \
-                        : : "r" (v), "r" (PCIO_BASE), "Jr" ((port)));   \
-                else if ((port) > 0)                                    \
-                        __asm__ __volatile__(                           \
-                        "strh   %0, [%1, %2]    @ outwc"                \
-                        : : "r" (v),                                    \
-                            "r" (PCIO_BASE + ((port) & ~0xff)),         \
-                             "Jr" (((port) & 0xff)));                   \
-                else                                                    \
-                        __asm__ __volatile__(                           \
-                        "strh   %0, [%1, #0]    @ outwc"                \
-                        : : "r" (v),                                    \
-                            "r" (PCIO_BASE + (port)));                  \
-        } else                                                          \
-                __asm__ __volatile__(                                   \
-                "strh   %0, [%1, #0]    @ outwc"                        \
-                : : "r" (v), "r" ((port)));                             \
-})
-
-#define __inwc(port)                                                    \
-({                                                                      \
-        unsigned short result;                                          \
-        if (__PORT_PCIO((port))) {                                      \
-                if ((port) < 256 && (port) > -256 )                     \
-                        __asm__ __volatile__(                           \
-                        "ldrh   %0, [%1, %2]    @ inwc"                 \
-                        : "=r" (result)                                 \
-                        : "r" (PCIO_BASE),                              \
-                          "Jr" ((port)));                               \
-                else if ((port) > 0)                                    \
-                        __asm__ __volatile__(                           \
-                        "ldrh   %0, [%1, %2]    @ inwc"                 \
-                        : "=r" (result)                                 \
-                        : "r" (PCIO_BASE + ((port) & ~0xff)),           \
-                          "Jr" (((port) & 0xff)));                      \
-                else                                                    \
-                        __asm__ __volatile__(                           \
-                        "ldrh   %0, [%1, #0]    @ inwc"                 \
-                        : "=r" (result)                                 \
-                        : "r" (PCIO_BASE + ((port))));                  \
-        } else                                                          \
-                __asm__ __volatile__(                                   \
-                "ldrh   %0, [%1, #0]    @ inwc"                         \
-                : "=r" (result) : "r" ((port)));                        \
-        result;                                                         \
-})
-
-#define __outlc(value,port)                                             \
-({                                                                      \
-        unsigned long v = value;                                        \
-        if (__PORT_PCIO((port)))                                        \
-                __asm__ __volatile__(                                   \
-                "str    %0, [%1, %2]    @ outlc"                        \
-                : : "r" (v), "r" (PCIO_BASE), "Jr" ((port)));   \
-        else                                                            \
-                __asm__ __volatile__(                                   \
-                "str    %0, [%1, #0]    @ outlc"                        \
-                : : "r" (v), "r" ((port)));             \
-})
-
-#define __inlc(port)                                                    \
-({                                                                      \
-        unsigned long result;                                           \
-        if (__PORT_PCIO((port)))                                        \
-                __asm__ __volatile__(                                   \
-                "ldr    %0, [%1, %2]    @ inlc"                         \
-                : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port)));      \
-        else                                                            \
-                __asm__ __volatile__(                                   \
-                "ldr    %0, [%1, #0]    @ inlc"                         \
-                : "=r" (result) : "r" ((port)));                \
-        result;                                                         \
-})
-
-#define __ioaddrc(port) ((__PORT_PCIO(port) ? PCIO_BASE + (port) : (void __iomem *)(port)))
-
-#define inb(p)          (__builtin_constant_p((p)) ? __inbc(p)     : __inb(p))
-#define inw(p)          (__builtin_constant_p((p)) ? __inwc(p)     : __inw(p))
-#define inl(p)          (__builtin_constant_p((p)) ? __inlc(p)     : __inl(p))
-#define outb(v,p)       (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p))
-#define outw(v,p)       (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p))
-#define outl(v,p)       (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p))
-#define __ioaddr(p)     (__builtin_constant_p((p)) ? __ioaddr(p)  : __ioaddrc(p))
-/* the following macro is deprecated */
-#define ioaddr(port)    __ioaddr((port))
-
-#define insb(p,d,l)     __raw_readsb(__ioaddr(p),d,l)
-#define insw(p,d,l)     __raw_readsw(__ioaddr(p),d,l)
-#define insl(p,d,l)     __raw_readsl(__ioaddr(p),d,l)
-
-#define outsb(p,d,l)    __raw_writesb(__ioaddr(p),d,l)
-#define outsw(p,d,l)    __raw_writesw(__ioaddr(p),d,l)
-#define outsl(p,d,l)    __raw_writesl(__ioaddr(p),d,l)
-
-/*
- * 1:1 mapping for ioremapped regions.
- */
-#define __mem_pci(x)    (x)
-
-#endif
diff --git a/include/asm-arm/arch-s3c2410/irqs.h b/include/asm-arm/arch-s3c2410/irqs.h
deleted file mode 100644
index f5435d8c3769..000000000000
--- a/include/asm-arm/arch-s3c2410/irqs.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/irqs.h
- *
- * Copyright (c) 2003-2005 Simtec Electronics
- *   Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H __FILE__
-
-#ifndef __ASM_ARM_IRQ_H
-#error "Do not include this directly, instead #include <asm/irq.h>"
-#endif
-
-/* we keep the first set of CPU IRQs out of the range of
- * the ISA space, so that the PC104 has them to itself
- * and we don't end up having to do horrible things to the
- * standard ISA drivers....
- */
-
-#define S3C2410_CPUIRQ_OFFSET    (16)
-
-#define S3C2410_IRQ(x) ((x) + S3C2410_CPUIRQ_OFFSET)
-
-/* main cpu interrupts */
-#define IRQ_EINT0      S3C2410_IRQ(0)       /* 16 */
-#define IRQ_EINT1      S3C2410_IRQ(1)
-#define IRQ_EINT2      S3C2410_IRQ(2)
-#define IRQ_EINT3      S3C2410_IRQ(3)
-#define IRQ_EINT4t7    S3C2410_IRQ(4)       /* 20 */
-#define IRQ_EINT8t23   S3C2410_IRQ(5)
-#define IRQ_RESERVED6  S3C2410_IRQ(6)       /* for s3c2410 */
-#define IRQ_CAM        S3C2410_IRQ(6)       /* for s3c2440,s3c2443 */
-#define IRQ_BATT_FLT   S3C2410_IRQ(7)
-#define IRQ_TICK       S3C2410_IRQ(8)       /* 24 */
-#define IRQ_WDT        S3C2410_IRQ(9)       /* WDT/AC97 for s3c2443 */
-#define IRQ_TIMER0     S3C2410_IRQ(10)
-#define IRQ_TIMER1     S3C2410_IRQ(11)
-#define IRQ_TIMER2     S3C2410_IRQ(12)
-#define IRQ_TIMER3     S3C2410_IRQ(13)
-#define IRQ_TIMER4     S3C2410_IRQ(14)
-#define IRQ_UART2      S3C2410_IRQ(15)
-#define IRQ_LCD        S3C2410_IRQ(16)      /* 32 */
-#define IRQ_DMA0       S3C2410_IRQ(17)      /* IRQ_DMA for s3c2443 */
-#define IRQ_DMA1       S3C2410_IRQ(18)
-#define IRQ_DMA2       S3C2410_IRQ(19)
-#define IRQ_DMA3       S3C2410_IRQ(20)
-#define IRQ_SDI        S3C2410_IRQ(21)
-#define IRQ_SPI0       S3C2410_IRQ(22)
-#define IRQ_UART1      S3C2410_IRQ(23)
-#define IRQ_RESERVED24 S3C2410_IRQ(24)      /* 40 */
-#define IRQ_NFCON      S3C2410_IRQ(24)      /* for s3c2440 */
-#define IRQ_USBD       S3C2410_IRQ(25)
-#define IRQ_USBH       S3C2410_IRQ(26)
-#define IRQ_IIC        S3C2410_IRQ(27)
-#define IRQ_UART0      S3C2410_IRQ(28)      /* 44 */
-#define IRQ_SPI1       S3C2410_IRQ(29)
-#define IRQ_RTC        S3C2410_IRQ(30)
-#define IRQ_ADCPARENT  S3C2410_IRQ(31)
-
-/* interrupts generated from the external interrupts sources */
-#define IRQ_EINT4      S3C2410_IRQ(32)     /* 48 */
-#define IRQ_EINT5      S3C2410_IRQ(33)
-#define IRQ_EINT6      S3C2410_IRQ(34)
-#define IRQ_EINT7      S3C2410_IRQ(35)
-#define IRQ_EINT8      S3C2410_IRQ(36)
-#define IRQ_EINT9      S3C2410_IRQ(37)
-#define IRQ_EINT10     S3C2410_IRQ(38)
-#define IRQ_EINT11     S3C2410_IRQ(39)
-#define IRQ_EINT12     S3C2410_IRQ(40)
-#define IRQ_EINT13     S3C2410_IRQ(41)
-#define IRQ_EINT14     S3C2410_IRQ(42)
-#define IRQ_EINT15     S3C2410_IRQ(43)
-#define IRQ_EINT16     S3C2410_IRQ(44)
-#define IRQ_EINT17     S3C2410_IRQ(45)
-#define IRQ_EINT18     S3C2410_IRQ(46)
-#define IRQ_EINT19     S3C2410_IRQ(47)
-#define IRQ_EINT20     S3C2410_IRQ(48)     /* 64 */
-#define IRQ_EINT21     S3C2410_IRQ(49)
-#define IRQ_EINT22     S3C2410_IRQ(50)
-#define IRQ_EINT23     S3C2410_IRQ(51)
-
-
-#define IRQ_EINT(x)    (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x)))
-
-#define IRQ_LCD_FIFO   S3C2410_IRQ(52)
-#define IRQ_LCD_FRAME  S3C2410_IRQ(53)
-
-/* IRQs for the interal UARTs, and ADC
- * these need to be ordered in number of appearance in the
- * SUBSRC mask register
-*/
-
-#define S3C2410_IRQSUB(x)       S3C2410_IRQ((x)+54)
-
-#define IRQ_S3CUART_RX0         S3C2410_IRQSUB(0)       /* 70 */
-#define IRQ_S3CUART_TX0         S3C2410_IRQSUB(1)
-#define IRQ_S3CUART_ERR0        S3C2410_IRQSUB(2)
-
-#define IRQ_S3CUART_RX1         S3C2410_IRQSUB(3)       /* 73 */
-#define IRQ_S3CUART_TX1         S3C2410_IRQSUB(4)
-#define IRQ_S3CUART_ERR1        S3C2410_IRQSUB(5)
-
-#define IRQ_S3CUART_RX2         S3C2410_IRQSUB(6)       /* 76 */
-#define IRQ_S3CUART_TX2         S3C2410_IRQSUB(7)
-#define IRQ_S3CUART_ERR2        S3C2410_IRQSUB(8)
-
-#define IRQ_TC                  S3C2410_IRQSUB(9)
-#define IRQ_ADC                 S3C2410_IRQSUB(10)
-
-/* extra irqs for s3c2412 */
-
-#define IRQ_S3C2412_CFSDI       S3C2410_IRQ(21)
-
-#define IRQ_S3C2412_SDI         S3C2410_IRQSUB(13)
-#define IRQ_S3C2412_CF          S3C2410_IRQSUB(14)
-
-/* extra irqs for s3c2440 */
-
-#define IRQ_S3C2440_CAM_C       S3C2410_IRQSUB(11)      /* S3C2443 too */
-#define IRQ_S3C2440_CAM_P       S3C2410_IRQSUB(12)      /* S3C2443 too */
-#define IRQ_S3C2440_WDT         S3C2410_IRQSUB(13)
-#define IRQ_S3C2440_AC97        S3C2410_IRQSUB(14)
-
-/* irqs for s3c2443 */
-
-#define IRQ_S3C2443_DMA         S3C2410_IRQ(17)         /* IRQ_DMA1 */
-#define IRQ_S3C2443_UART3       S3C2410_IRQ(18)         /* IRQ_DMA2 */
-#define IRQ_S3C2443_CFCON       S3C2410_IRQ(19)         /* IRQ_DMA3 */
-#define IRQ_S3C2443_HSMMC       S3C2410_IRQ(20)         /* IRQ_SDI */
-#define IRQ_S3C2443_NAND        S3C2410_IRQ(24)         /* reserved */
-
-#define IRQ_S3C2443_LCD1        S3C2410_IRQSUB(14)
-#define IRQ_S3C2443_LCD2        S3C2410_IRQSUB(15)
-#define IRQ_S3C2443_LCD3        S3C2410_IRQSUB(16)
-#define IRQ_S3C2443_LCD4        S3C2410_IRQSUB(17)
-
-#define IRQ_S3C2443_DMA0        S3C2410_IRQSUB(18)
-#define IRQ_S3C2443_DMA1        S3C2410_IRQSUB(19)
-#define IRQ_S3C2443_DMA2        S3C2410_IRQSUB(20)
-#define IRQ_S3C2443_DMA3        S3C2410_IRQSUB(21)
-#define IRQ_S3C2443_DMA4        S3C2410_IRQSUB(22)
-#define IRQ_S3C2443_DMA5        S3C2410_IRQSUB(23)
-
-/* UART3 */
-#define IRQ_S3C2443_RX3         S3C2410_IRQSUB(24)
-#define IRQ_S3C2443_TX3         S3C2410_IRQSUB(25)
-#define IRQ_S3C2443_ERR3        S3C2410_IRQSUB(26)
-
-#define IRQ_S3C2443_WDT         S3C2410_IRQSUB(27)
-#define IRQ_S3C2443_AC97        S3C2410_IRQSUB(28)
-
-#ifdef CONFIG_CPU_S3C2443
-#define NR_IRQS (IRQ_S3C2443_AC97+1)
-#else
-#define NR_IRQS (IRQ_S3C2440_AC97+1)
-#endif
-
-/* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */
-#define FIQ_START               IRQ_EINT0
-
-#endif /* __ASM_ARCH_IRQ_H */
diff --git a/include/asm-arm/arch-s3c2410/leds-gpio.h b/include/asm-arm/arch-s3c2410/leds-gpio.h
deleted file mode 100644
index 800846ebddba..000000000000
--- a/include/asm-arm/arch-s3c2410/leds-gpio.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/leds-gpio.h
- *
- * Copyright (c) 2006 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C24XX - LEDs GPIO connector
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_LEDSGPIO_H
-#define __ASM_ARCH_LEDSGPIO_H "leds-gpio.h"
-
-#define S3C24XX_LEDF_ACTLOW     (1<<0)          /* LED is on when GPIO low */
-#define S3C24XX_LEDF_TRISTATE   (1<<1)          /* tristate to turn off */
-
-struct s3c24xx_led_platdata {
-        unsigned int             gpio;
-        unsigned int             flags;
-
-        char                    *name;
-        char                    *def_trigger;
-};
-
-#endif /* __ASM_ARCH_LEDSGPIO_H */
diff --git a/include/asm-arm/arch-s3c2410/map.h b/include/asm-arm/arch-s3c2410/map.h
deleted file mode 100644
index b33ed3b05ef5..000000000000
--- a/include/asm-arm/arch-s3c2410/map.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/map.h
- *
- * Copyright (c) 2003 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - Memory map definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_MAP_H
-#define __ASM_ARCH_MAP_H
-
-#include <asm/plat-s3c/map.h>
-
-#define S3C2410_ADDR(x)         S3C_ADDR(x)
-
-/* interrupt controller is the first thing we put in, to make
- * the assembly code for the irq detection easier
- */
-#define S3C24XX_VA_IRQ     S3C_VA_IRQ
-#define S3C2410_PA_IRQ     (0x4A000000)
-#define S3C24XX_SZ_IRQ     SZ_1M
-
-/* memory controller registers */
-#define S3C24XX_VA_MEMCTRL S3C_VA_MEM
-#define S3C2410_PA_MEMCTRL (0x48000000)
-#define S3C24XX_SZ_MEMCTRL SZ_1M
-
-/* USB host controller */
-#define S3C2410_PA_USBHOST (0x49000000)
-#define S3C24XX_SZ_USBHOST SZ_1M
-
-/* DMA controller */
-#define S3C2410_PA_DMA     (0x4B000000)
-#define S3C24XX_SZ_DMA     SZ_1M
-
-/* Clock and Power management */
-#define S3C24XX_VA_CLKPWR  S3C_VA_SYS
-#define S3C2410_PA_CLKPWR  (0x4C000000)
-#define S3C24XX_SZ_CLKPWR  SZ_1M
-
-/* LCD controller */
-#define S3C2410_PA_LCD     (0x4D000000)
-#define S3C24XX_SZ_LCD     SZ_1M
-
-/* NAND flash controller */
-#define S3C2410_PA_NAND    (0x4E000000)
-#define S3C24XX_SZ_NAND    SZ_1M
-
-/* UARTs */
-#define S3C24XX_VA_UART    S3C_VA_UART
-#define S3C2410_PA_UART    (0x50000000)
-#define S3C24XX_SZ_UART    SZ_1M
-
-/* Timers */
-#define S3C24XX_VA_TIMER   S3C_VA_TIMER
-#define S3C2410_PA_TIMER   (0x51000000)
-#define S3C24XX_SZ_TIMER   SZ_1M
-
-/* USB Device port */
-#define S3C2410_PA_USBDEV  (0x52000000)
-#define S3C24XX_SZ_USBDEV  SZ_1M
-
-/* Watchdog */
-#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG
-#define S3C2410_PA_WATCHDOG (0x53000000)
-#define S3C24XX_SZ_WATCHDOG SZ_1M
-
-/* IIC hardware controller */
-#define S3C2410_PA_IIC     (0x54000000)
-#define S3C24XX_SZ_IIC     SZ_1M
-
-/* IIS controller */
-#define S3C2410_PA_IIS     (0x55000000)
-#define S3C24XX_SZ_IIS     SZ_1M
-
-/* GPIO ports */
-
-/* the calculation for the VA of this must ensure that
- * it is the same distance apart from the UART in the
- * phsyical address space, as the initial mapping for the IO
- * is done as a 1:1 maping. This puts it (currently) at
- * 0xFA800000, which is not in the way of any current mapping
- * by the base system.
-*/
-
-#define S3C2410_PA_GPIO    (0x56000000)
-#define S3C24XX_VA_GPIO    ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
-#define S3C24XX_SZ_GPIO    SZ_1M
-
-/* RTC */
-#define S3C2410_PA_RTC     (0x57000000)
-#define S3C24XX_SZ_RTC     SZ_1M
-
-/* ADC */
-#define S3C2410_PA_ADC     (0x58000000)
-#define S3C24XX_SZ_ADC     SZ_1M
-
-/* SPI */
-#define S3C2410_PA_SPI     (0x59000000)
-#define S3C24XX_SZ_SPI     SZ_1M
-
-/* SDI */
-#define S3C2410_PA_SDI     (0x5A000000)
-#define S3C24XX_SZ_SDI     SZ_1M
-
-/* CAMIF */
-#define S3C2440_PA_CAMIF   (0x4F000000)
-#define S3C2440_SZ_CAMIF   SZ_1M
-
-/* AC97 */
-
-#define S3C2440_PA_AC97    (0x5B000000)
-#define S3C2440_SZ_AC97    SZ_1M
-
-/* S3C2443 High-speed SD/MMC */
-#define S3C2443_PA_HSMMC   (0x4A800000)
-#define S3C2443_SZ_HSMMC   (256)
-
-/* ISA style IO, for each machine to sort out mappings for, if it
- * implements it. We reserve two 16M regions for ISA.
- */
-
-#define S3C24XX_VA_ISA_WORD  S3C2410_ADDR(0x02000000)
-#define S3C24XX_VA_ISA_BYTE  S3C2410_ADDR(0x03000000)
-
-/* physical addresses of all the chip-select areas */
-
-#define S3C2410_CS0 (0x00000000)
-#define S3C2410_CS1 (0x08000000)
-#define S3C2410_CS2 (0x10000000)
-#define S3C2410_CS3 (0x18000000)
-#define S3C2410_CS4 (0x20000000)
-#define S3C2410_CS5 (0x28000000)
-#define S3C2410_CS6 (0x30000000)
-#define S3C2410_CS7 (0x38000000)
-
-#define S3C2410_SDRAM_PA    (S3C2410_CS6)
-
-/* Use a single interface for common resources between S3C24XX cpus */
-
-#define S3C24XX_PA_IRQ      S3C2410_PA_IRQ
-#define S3C24XX_PA_MEMCTRL  S3C2410_PA_MEMCTRL
-#define S3C24XX_PA_USBHOST  S3C2410_PA_USBHOST
-#define S3C24XX_PA_DMA      S3C2410_PA_DMA
-#define S3C24XX_PA_CLKPWR   S3C2410_PA_CLKPWR
-#define S3C24XX_PA_LCD      S3C2410_PA_LCD
-#define S3C24XX_PA_UART     S3C2410_PA_UART
-#define S3C24XX_PA_TIMER    S3C2410_PA_TIMER
-#define S3C24XX_PA_USBDEV   S3C2410_PA_USBDEV
-#define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
-#define S3C24XX_PA_IIC      S3C2410_PA_IIC
-#define S3C24XX_PA_IIS      S3C2410_PA_IIS
-#define S3C24XX_PA_GPIO     S3C2410_PA_GPIO
-#define S3C24XX_PA_RTC      S3C2410_PA_RTC
-#define S3C24XX_PA_ADC      S3C2410_PA_ADC
-#define S3C24XX_PA_SPI      S3C2410_PA_SPI
-
-/* deal with the registers that move under the 2412/2413 */
-
-#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
-#ifndef __ASSEMBLY__
-extern void __iomem *s3c24xx_va_gpio2;
-#endif
-#ifdef CONFIG_CPU_S3C2412_ONLY
-#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
-#else
-#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
-#endif
-#else
-#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
-#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
-#endif
-
-#endif /* __ASM_ARCH_MAP_H */
diff --git a/include/asm-arm/arch-s3c2410/memory.h b/include/asm-arm/arch-s3c2410/memory.h
deleted file mode 100644
index 533e2436e707..000000000000
--- a/include/asm-arm/arch-s3c2410/memory.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/memory.h
- *  from linux/include/asm-arm/arch-rpc/memory.h
- *
- *  Copyright (C) 1996,1997,1998 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-#define PHYS_OFFSET     UL(0x30000000)
-
-#define __virt_to_bus(x) __virt_to_phys(x)
-#define __bus_to_virt(x) __phys_to_virt(x)
-
-#endif
diff --git a/include/asm-arm/arch-s3c2410/osiris-cpld.h b/include/asm-arm/arch-s3c2410/osiris-cpld.h
deleted file mode 100644
index 229ab2351db6..000000000000
--- a/include/asm-arm/arch-s3c2410/osiris-cpld.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/osiris-cpld.h
- *
- * Copyright 2005 Simtec Electronics
- *      http://www.simtec.co.uk/products/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * OSIRIS - CPLD control constants
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_OSIRISCPLD_H
-#define __ASM_ARCH_OSIRISCPLD_H
-
-/* CTRL0 - NAND WP control */
-
-#define OSIRIS_CTRL0_NANDSEL            (0x3)
-#define OSIRIS_CTRL0_BOOT_INT           (1<<3)
-#define OSIRIS_CTRL0_PCMCIA             (1<<4)
-#define OSIRIS_CTRL0_FIX8               (1<<5)
-#define OSIRIS_CTRL0_PCMCIA_nWAIT       (1<<6)
-#define OSIRIS_CTRL0_PCMCIA_nIOIS16     (1<<7)
-
-#define OSIRIS_CTRL1_FIX8               (1<<0)
-
-#define OSIRIS_ID_REVMASK               (0x7)
-
-#endif /* __ASM_ARCH_OSIRISCPLD_H */
diff --git a/include/asm-arm/arch-s3c2410/osiris-map.h b/include/asm-arm/arch-s3c2410/osiris-map.h
deleted file mode 100644
index b5c74d2b9aaa..000000000000
--- a/include/asm-arm/arch-s3c2410/osiris-map.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/osiris-map.h
- *
- * (c) 2005 Simtec Electronics
- *      http://www.simtec.co.uk/products/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * OSIRIS - Memory map definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* needs arch/map.h including with this */
-
-#ifndef __ASM_ARCH_OSIRISMAP_H
-#define __ASM_ARCH_OSIRISMAP_H
-
-/* start peripherals off after the S3C2410 */
-
-#define OSIRIS_IOADDR(x)        (S3C2410_ADDR((x) + 0x04000000))
-
-#define OSIRIS_PA_CPLD          (S3C2410_CS1 | (1<<26))
-
-/* we put the CPLD registers next, to get them out of the way */
-
-#define OSIRIS_VA_CTRL0         OSIRIS_IOADDR(0x00000000)
-#define OSIRIS_PA_CTRL0         (OSIRIS_PA_CPLD)
-
-#define OSIRIS_VA_CTRL1         OSIRIS_IOADDR(0x00100000)
-#define OSIRIS_PA_CTRL1         (OSIRIS_PA_CPLD + (1<<23))
-
-#define OSIRIS_VA_CTRL2         OSIRIS_IOADDR(0x00200000)
-#define OSIRIS_PA_CTRL2         (OSIRIS_PA_CPLD + (2<<23))
-
-#define OSIRIS_VA_CTRL3         OSIRIS_IOADDR(0x00300000)
-#define OSIRIS_PA_CTRL3         (OSIRIS_PA_CPLD + (2<<23))
-
-#define OSIRIS_VA_IDREG         OSIRIS_IOADDR(0x00700000)
-#define OSIRIS_PA_IDREG         (OSIRIS_PA_CPLD + (7<<23))
-
-#endif /* __ASM_ARCH_OSIRISMAP_H */
diff --git a/include/asm-arm/arch-s3c2410/otom-map.h b/include/asm-arm/arch-s3c2410/otom-map.h
deleted file mode 100644
index e40c93429854..000000000000
--- a/include/asm-arm/arch-s3c2410/otom-map.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/otom-map.h
- *
- * (c) 2005 Guillaume GOURAT / NexVision
- *          guillaume.gourat@nexvision.fr
- *
- * NexVision OTOM board memory map definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* needs arch/map.h including with this */
-
-/* ok, we've used up to 0x01300000, now we need to find space for the
- * peripherals that live in the nGCS[x] areas, which are quite numerous
- * in their space.
- */
-
-#ifndef __ASM_ARCH_OTOMMAP_H
-#define __ASM_ARCH_OTOMMAP_H
-
-#define OTOM_PA_CS8900A_BASE       (S3C2410_CS3 + 0x01000000)   /* nGCS3 +0x01000000 */
-#define OTOM_VA_CS8900A_BASE       S3C2410_ADDR(0x04000000)             /* 0xF4000000 */
-
-/* physical offset addresses for the peripherals */
-
-#define OTOM_PA_FLASH0_BASE        (S3C2410_CS0)                                /* Bank 0 */
-
-#endif /* __ASM_ARCH_OTOMMAP_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h
deleted file mode 100644
index 37661358b42b..000000000000
--- a/include/asm-arm/arch-s3c2410/regs-clock.h
+++ /dev/null
@@ -1,197 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-clock.h
- *
- * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk>
- *                    http://armlinux.simtec.co.uk/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 clock register definitions
-*/
-
-#ifndef __ASM_ARM_REGS_CLOCK
-#define __ASM_ARM_REGS_CLOCK "$Id: clock.h,v 1.4 2003/04/30 14:50:51 ben Exp $"
-
-#define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
-
-#define S3C2410_PLLVAL(_m,_p,_s) ((_m) << 12 | ((_p) << 4) | ((_s)))
-
-#define S3C2410_LOCKTIME    S3C2410_CLKREG(0x00)
-#define S3C2410_MPLLCON     S3C2410_CLKREG(0x04)
-#define S3C2410_UPLLCON     S3C2410_CLKREG(0x08)
-#define S3C2410_CLKCON      S3C2410_CLKREG(0x0C)
-#define S3C2410_CLKSLOW     S3C2410_CLKREG(0x10)
-#define S3C2410_CLKDIVN     S3C2410_CLKREG(0x14)
-
-#define S3C2410_CLKCON_IDLE          (1<<2)
-#define S3C2410_CLKCON_POWER         (1<<3)
-#define S3C2410_CLKCON_NAND          (1<<4)
-#define S3C2410_CLKCON_LCDC          (1<<5)
-#define S3C2410_CLKCON_USBH          (1<<6)
-#define S3C2410_CLKCON_USBD          (1<<7)
-#define S3C2410_CLKCON_PWMT          (1<<8)
-#define S3C2410_CLKCON_SDI           (1<<9)
-#define S3C2410_CLKCON_UART0         (1<<10)
-#define S3C2410_CLKCON_UART1         (1<<11)
-#define S3C2410_CLKCON_UART2         (1<<12)
-#define S3C2410_CLKCON_GPIO          (1<<13)
-#define S3C2410_CLKCON_RTC           (1<<14)
-#define S3C2410_CLKCON_ADC           (1<<15)
-#define S3C2410_CLKCON_IIC           (1<<16)
-#define S3C2410_CLKCON_IIS           (1<<17)
-#define S3C2410_CLKCON_SPI           (1<<18)
-
-#define S3C2410_PLLCON_MDIVSHIFT     12
-#define S3C2410_PLLCON_PDIVSHIFT     4
-#define S3C2410_PLLCON_SDIVSHIFT     0
-#define S3C2410_PLLCON_MDIVMASK      ((1<<(1+(19-12)))-1)
-#define S3C2410_PLLCON_PDIVMASK      ((1<<5)-1)
-#define S3C2410_PLLCON_SDIVMASK      3
-
-/* DCLKCON register addresses in gpio.h */
-
-#define S3C2410_DCLKCON_DCLK0EN      (1<<0)
-#define S3C2410_DCLKCON_DCLK0_PCLK   (0<<1)
-#define S3C2410_DCLKCON_DCLK0_UCLK   (1<<1)
-#define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4)
-#define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8)
-#define S3C2410_DCLKCON_DCLK0_DIV_MASK ((0xf)<<4)
-#define S3C2410_DCLKCON_DCLK0_CMP_MASK ((0xf)<<8)
-
-#define S3C2410_DCLKCON_DCLK1EN      (1<<16)
-#define S3C2410_DCLKCON_DCLK1_PCLK   (0<<17)
-#define S3C2410_DCLKCON_DCLK1_UCLK   (1<<17)
-#define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20)
-#define S3C2410_DCLKCON_DCLK1_CMP(x) (((x) - 1) <<24)
-#define S3C2410_DCLKCON_DCLK1_DIV_MASK ((0xf) <<20)
-#define S3C2410_DCLKCON_DCLK1_CMP_MASK ((0xf) <<24)
-
-#define S3C2410_CLKDIVN_PDIVN        (1<<0)
-#define S3C2410_CLKDIVN_HDIVN        (1<<1)
-
-#define S3C2410_CLKSLOW_UCLK_OFF        (1<<7)
-#define S3C2410_CLKSLOW_MPLL_OFF        (1<<5)
-#define S3C2410_CLKSLOW_SLOW            (1<<4)
-#define S3C2410_CLKSLOW_SLOWVAL(x)      (x)
-#define S3C2410_CLKSLOW_GET_SLOWVAL(x)  ((x) & 7)
-
-#ifndef __ASSEMBLY__
-
-#include <asm/div64.h>
-
-static inline unsigned int
-s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
-{
-        unsigned int mdiv, pdiv, sdiv;
-        uint64_t fvco;
-
-        mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT;
-        pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT;
-        sdiv = pllval >> S3C2410_PLLCON_SDIVSHIFT;
-
-        mdiv &= S3C2410_PLLCON_MDIVMASK;
-        pdiv &= S3C2410_PLLCON_PDIVMASK;
-        sdiv &= S3C2410_PLLCON_SDIVMASK;
-
-        fvco = (uint64_t)baseclk * (mdiv + 8);
-        do_div(fvco, (pdiv + 2) << sdiv);
-
-        return (unsigned int)fvco;
-}
-
-#endif /* __ASSEMBLY__ */
-
-#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
-
-/* extra registers */
-#define S3C2440_CAMDIVN     S3C2410_CLKREG(0x18)
-
-#define S3C2440_CLKCON_CAMERA        (1<<19)
-#define S3C2440_CLKCON_AC97          (1<<20)
-
-#define S3C2440_CLKDIVN_PDIVN        (1<<0)
-#define S3C2440_CLKDIVN_HDIVN_MASK   (3<<1)
-#define S3C2440_CLKDIVN_HDIVN_1      (0<<1)
-#define S3C2440_CLKDIVN_HDIVN_2      (1<<1)
-#define S3C2440_CLKDIVN_HDIVN_4_8    (2<<1)
-#define S3C2440_CLKDIVN_HDIVN_3_6    (3<<1)
-#define S3C2440_CLKDIVN_UCLK         (1<<3)
-
-#define S3C2440_CAMDIVN_CAMCLK_MASK  (0xf<<0)
-#define S3C2440_CAMDIVN_CAMCLK_SEL   (1<<4)
-#define S3C2440_CAMDIVN_HCLK3_HALF   (1<<8)
-#define S3C2440_CAMDIVN_HCLK4_HALF   (1<<9)
-#define S3C2440_CAMDIVN_DVSEN        (1<<12)
-
-#define S3C2442_CAMDIVN_CAMCLK_DIV3  (1<<5)
-
-#endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */
-
-#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
-
-#define S3C2412_OSCSET          S3C2410_CLKREG(0x18)
-#define S3C2412_CLKSRC          S3C2410_CLKREG(0x1C)
-
-#define S3C2412_PLLCON_OFF              (1<<20)
-
-#define S3C2412_CLKDIVN_PDIVN           (1<<2)
-#define S3C2412_CLKDIVN_HDIVN_MASK      (3<<0)
-#define S3C2412_CLKDIVN_ARMDIVN         (1<<3)
-#define S3C2412_CLKDIVN_DVSEN           (1<<4)
-#define S3C2412_CLKDIVN_HALFHCLK        (1<<5)
-#define S3C2412_CLKDIVN_USB48DIV        (1<<6)
-#define S3C2412_CLKDIVN_UARTDIV_MASK    (15<<8)
-#define S3C2412_CLKDIVN_UARTDIV_SHIFT   (8)
-#define S3C2412_CLKDIVN_I2SDIV_MASK     (15<<12)
-#define S3C2412_CLKDIVN_I2SDIV_SHIFT    (12)
-#define S3C2412_CLKDIVN_CAMDIV_MASK     (15<<16)
-#define S3C2412_CLKDIVN_CAMDIV_SHIFT    (16)
-
-#define S3C2412_CLKCON_WDT              (1<<28)
-#define S3C2412_CLKCON_SPI              (1<<27)
-#define S3C2412_CLKCON_IIS              (1<<26)
-#define S3C2412_CLKCON_IIC              (1<<25)
-#define S3C2412_CLKCON_ADC              (1<<24)
-#define S3C2412_CLKCON_RTC              (1<<23)
-#define S3C2412_CLKCON_GPIO             (1<<22)
-#define S3C2412_CLKCON_UART2            (1<<21)
-#define S3C2412_CLKCON_UART1            (1<<20)
-#define S3C2412_CLKCON_UART0            (1<<19)
-#define S3C2412_CLKCON_SDI              (1<<18)
-#define S3C2412_CLKCON_PWMT             (1<<17)
-#define S3C2412_CLKCON_USBD             (1<<16)
-#define S3C2412_CLKCON_CAMCLK           (1<<15)
-#define S3C2412_CLKCON_UARTCLK          (1<<14)
-/* missing 13 */
-#define S3C2412_CLKCON_USB_HOST48       (1<<12)
-#define S3C2412_CLKCON_USB_DEV48        (1<<11)
-#define S3C2412_CLKCON_HCLKdiv2         (1<<10)
-#define S3C2412_CLKCON_HCLKx2           (1<<9)
-#define S3C2412_CLKCON_SDRAM            (1<<8)
-/* missing 7 */
-#define S3C2412_CLKCON_USBH             S3C2410_CLKCON_USBH
-#define S3C2412_CLKCON_LCDC             S3C2410_CLKCON_LCDC
-#define S3C2412_CLKCON_NAND             S3C2410_CLKCON_NAND
-#define S3C2412_CLKCON_DMA3             (1<<3)
-#define S3C2412_CLKCON_DMA2             (1<<2)
-#define S3C2412_CLKCON_DMA1             (1<<1)
-#define S3C2412_CLKCON_DMA0             (1<<0)
-
-/* clock sourec controls */
-
-#define S3C2412_CLKSRC_EXTCLKDIV_MASK           (7 << 0)
-#define S3C2412_CLKSRC_EXTCLKDIV_SHIFT          (0)
-#define S3C2412_CLKSRC_MDIVCLK_EXTCLKDIV        (1<<3)
-#define S3C2412_CLKSRC_MSYSCLK_MPLL             (1<<4)
-#define S3C2412_CLKSRC_USYSCLK_UPLL             (1<<5)
-#define S3C2412_CLKSRC_UARTCLK_MPLL             (1<<8)
-#define S3C2412_CLKSRC_I2SCLK_MPLL              (1<<9)
-#define S3C2412_CLKSRC_USBCLK_HCLK              (1<<10)
-#define S3C2412_CLKSRC_CAMCLK_HCLK              (1<<11)
-#define S3C2412_CLKSRC_UREFCLK_EXTCLK   (1<<12)
-#define S3C2412_CLKSRC_EREFCLK_EXTCLK   (1<<14)
-
-#endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */
-
-#endif /* __ASM_ARM_REGS_CLOCK */
diff --git a/include/asm-arm/arch-s3c2410/regs-dsc.h b/include/asm-arm/arch-s3c2410/regs-dsc.h
deleted file mode 100644
index 1235df70f34e..000000000000
--- a/include/asm-arm/arch-s3c2410/regs-dsc.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-dsc.h
- *
- * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
- *                    http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2440/S3C2412 Signal Drive Strength Control
-*/
-
-
-#ifndef __ASM_ARCH_REGS_DSC_H
-#define __ASM_ARCH_REGS_DSC_H "2440-dsc"
-
-#if defined(CONFIG_CPU_S3C2412)
-#define S3C2412_DSC0       S3C2410_GPIOREG(0xdc)
-#define S3C2412_DSC1       S3C2410_GPIOREG(0xe0)
-#endif
-
-#if defined(CONFIG_CPU_S3C244X)
-
-#define S3C2440_DSC0       S3C2410_GPIOREG(0xc4)
-#define S3C2440_DSC1       S3C2410_GPIOREG(0xc8)
-
-#define S3C2440_SELECT_DSC0 (0)
-#define S3C2440_SELECT_DSC1 (1<<31)
-
-#define S3C2440_DSC_GETSHIFT(x) ((x) & 31)
-
-#define S3C2440_DSC0_DISABLE    (1<<31)
-
-#define S3C2440_DSC0_ADDR       (S3C2440_SELECT_DSC0 | 8)
-#define S3C2440_DSC0_ADDR_12mA  (0<<8)
-#define S3C2440_DSC0_ADDR_10mA  (1<<8)
-#define S3C2440_DSC0_ADDR_8mA   (2<<8)
-#define S3C2440_DSC0_ADDR_6mA   (3<<8)
-#define S3C2440_DSC0_ADDR_MASK  (3<<8)
-
-/* D24..D31 */
-#define S3C2440_DSC0_DATA3      (S3C2440_SELECT_DSC0 | 6)
-#define S3C2440_DSC0_DATA3_12mA (0<<6)
-#define S3C2440_DSC0_DATA3_10mA (1<<6)
-#define S3C2440_DSC0_DATA3_8mA  (2<<6)
-#define S3C2440_DSC0_DATA3_6mA  (3<<6)
-#define S3C2440_DSC0_DATA3_MASK (3<<6)
-
-/* D16..D23 */
-#define S3C2440_DSC0_DATA2      (S3C2440_SELECT_DSC0 | 4)
-#define S3C2440_DSC0_DATA2_12mA (0<<4)
-#define S3C2440_DSC0_DATA2_10mA (1<<4)
-#define S3C2440_DSC0_DATA2_8mA  (2<<4)
-#define S3C2440_DSC0_DATA2_6mA  (3<<4)
-#define S3C2440_DSC0_DATA2_MASK (3<<4)
-
-/* D8..D15 */
-#define S3C2440_DSC0_DATA1      (S3C2440_SELECT_DSC0 | 2)
-#define S3C2440_DSC0_DATA1_12mA (0<<2)
-#define S3C2440_DSC0_DATA1_10mA (1<<2)
-#define S3C2440_DSC0_DATA1_8mA  (2<<2)
-#define S3C2440_DSC0_DATA1_6mA  (3<<2)
-#define S3C2440_DSC0_DATA1_MASK (3<<2)
-
-/* D0..D7 */
-#define S3C2440_DSC0_DATA0      (S3C2440_SELECT_DSC0 | 0)
-#define S3C2440_DSC0_DATA0_12mA (0<<0)
-#define S3C2440_DSC0_DATA0_10mA (1<<0)
-#define S3C2440_DSC0_DATA0_8mA  (2<<0)
-#define S3C2440_DSC0_DATA0_6mA  (3<<0)
-#define S3C2440_DSC0_DATA0_MASK (3<<0)
-
-#define S3C2440_DSC1_SCK1       (S3C2440_SELECT_DSC1 | 28)
-#define S3C2440_DSC1_SCK1_12mA  (0<<28)
-#define S3C2440_DSC1_SCK1_10mA  (1<<28)
-#define S3C2440_DSC1_SCK1_8mA   (2<<28)
-#define S3C2440_DSC1_SCK1_6mA   (3<<28)
-#define S3C2440_DSC1_SCK1_MASK  (3<<28)
-
-#define S3C2440_DSC1_SCK0       (S3C2440_SELECT_DSC1 | 26)
-#define S3C2440_DSC1_SCK0_12mA  (0<<26)
-#define S3C2440_DSC1_SCK0_10mA  (1<<26)
-#define S3C2440_DSC1_SCK0_8mA   (2<<26)
-#define S3C2440_DSC1_SCK0_6mA   (3<<26)
-#define S3C2440_DSC1_SCK0_MASK  (3<<26)
-
-#define S3C2440_DSC1_SCKE       (S3C2440_SELECT_DSC1 | 24)
-#define S3C2440_DSC1_SCKE_10mA  (0<<24)
-#define S3C2440_DSC1_SCKE_8mA   (1<<24)
-#define S3C2440_DSC1_SCKE_6mA   (2<<24)
-#define S3C2440_DSC1_SCKE_4mA   (3<<24)
-#define S3C2440_DSC1_SCKE_MASK  (3<<24)
-
-/* SDRAM nRAS/nCAS */
-#define S3C2440_DSC1_SDR        (S3C2440_SELECT_DSC1 | 22)
-#define S3C2440_DSC1_SDR_10mA   (0<<22)
-#define S3C2440_DSC1_SDR_8mA    (1<<22)
-#define S3C2440_DSC1_SDR_6mA    (2<<22)
-#define S3C2440_DSC1_SDR_4mA    (3<<22)
-#define S3C2440_DSC1_SDR_MASK   (3<<22)
-
-/* NAND Flash Controller */
-#define S3C2440_DSC1_NFC        (S3C2440_SELECT_DSC1 | 20)
-#define S3C2440_DSC1_NFC_10mA   (0<<20)
-#define S3C2440_DSC1_NFC_8mA    (1<<20)
-#define S3C2440_DSC1_NFC_6mA    (2<<20)
-#define S3C2440_DSC1_NFC_4mA    (3<<20)
-#define S3C2440_DSC1_NFC_MASK   (3<<20)
-
-/* nBE[0..3] */
-#define S3C2440_DSC1_nBE        (S3C2440_SELECT_DSC1 | 18)
-#define S3C2440_DSC1_nBE_10mA   (0<<18)
-#define S3C2440_DSC1_nBE_8mA    (1<<18)
-#define S3C2440_DSC1_nBE_6mA    (2<<18)
-#define S3C2440_DSC1_nBE_4mA    (3<<18)
-#define S3C2440_DSC1_nBE_MASK   (3<<18)
-
-#define S3C2440_DSC1_WOE        (S3C2440_SELECT_DSC1 | 16)
-#define S3C2440_DSC1_WOE_10mA   (0<<16)
-#define S3C2440_DSC1_WOE_8mA    (1<<16)
-#define S3C2440_DSC1_WOE_6mA    (2<<16)
-#define S3C2440_DSC1_WOE_4mA    (3<<16)
-#define S3C2440_DSC1_WOE_MASK   (3<<16)
-
-#define S3C2440_DSC1_CS7        (S3C2440_SELECT_DSC1 | 14)
-#define S3C2440_DSC1_CS7_10mA   (0<<14)
-#define S3C2440_DSC1_CS7_8mA    (1<<14)
-#define S3C2440_DSC1_CS7_6mA    (2<<14)
-#define S3C2440_DSC1_CS7_4mA    (3<<14)
-#define S3C2440_DSC1_CS7_MASK   (3<<14)
-
-#define S3C2440_DSC1_CS6        (S3C2440_SELECT_DSC1 | 12)
-#define S3C2440_DSC1_CS6_10mA   (0<<12)
-#define S3C2440_DSC1_CS6_8mA    (1<<12)
-#define S3C2440_DSC1_CS6_6mA    (2<<12)
-#define S3C2440_DSC1_CS6_4mA    (3<<12)
-#define S3C2440_DSC1_CS6_MASK   (3<<12)
-
-#define S3C2440_DSC1_CS5        (S3C2440_SELECT_DSC1 | 10)
-#define S3C2440_DSC1_CS5_10mA   (0<<10)
-#define S3C2440_DSC1_CS5_8mA    (1<<10)
-#define S3C2440_DSC1_CS5_6mA    (2<<10)
-#define S3C2440_DSC1_CS5_4mA    (3<<10)
-#define S3C2440_DSC1_CS5_MASK   (3<<10)
-
-#define S3C2440_DSC1_CS4        (S3C2440_SELECT_DSC1 | 8)
-#define S3C2440_DSC1_CS4_10mA   (0<<8)
-#define S3C2440_DSC1_CS4_8mA    (1<<8)
-#define S3C2440_DSC1_CS4_6mA    (2<<8)
-#define S3C2440_DSC1_CS4_4mA    (3<<8)
-#define S3C2440_DSC1_CS4_MASK   (3<<8)
-
-#define S3C2440_DSC1_CS3        (S3C2440_SELECT_DSC1 | 6)
-#define S3C2440_DSC1_CS3_10mA   (0<<6)
-#define S3C2440_DSC1_CS3_8mA    (1<<6)
-#define S3C2440_DSC1_CS3_6mA    (2<<6)
-#define S3C2440_DSC1_CS3_4mA    (3<<6)
-#define S3C2440_DSC1_CS3_MASK   (3<<6)
-
-#define S3C2440_DSC1_CS2        (S3C2440_SELECT_DSC1 | 4)
-#define S3C2440_DSC1_CS2_10mA   (0<<4)
-#define S3C2440_DSC1_CS2_8mA    (1<<4)
-#define S3C2440_DSC1_CS2_6mA    (2<<4)
-#define S3C2440_DSC1_CS2_4mA    (3<<4)
-#define S3C2440_DSC1_CS2_MASK   (3<<4)
-
-#define S3C2440_DSC1_CS1        (S3C2440_SELECT_DSC1 | 2)
-#define S3C2440_DSC1_CS1_10mA   (0<<2)
-#define S3C2440_DSC1_CS1_8mA    (1<<2)
-#define S3C2440_DSC1_CS1_6mA    (2<<2)
-#define S3C2440_DSC1_CS1_4mA    (3<<2)
-#define S3C2440_DSC1_CS1_MASK   (3<<2)
-
-#define S3C2440_DSC1_CS0        (S3C2440_SELECT_DSC1 | 0)
-#define S3C2440_DSC1_CS0_10mA   (0<<0)
-#define S3C2440_DSC1_CS0_8mA    (1<<0)
-#define S3C2440_DSC1_CS0_6mA    (2<<0)
-#define S3C2440_DSC1_CS0_4mA    (3<<0)
-#define S3C2440_DSC1_CS0_MASK   (3<<0)
-
-#endif /* CONFIG_CPU_S3C2440 */
-
-#endif  /* __ASM_ARCH_REGS_DSC_H */
-
diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h
deleted file mode 100644
index 497dd06e2c99..000000000000
--- a/include/asm-arm/arch-s3c2410/regs-gpio.h
+++ /dev/null
@@ -1,1163 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-gpio.h
- *
- * Copyright (c) 2003,2004 Simtec Electronics <linux@simtec.co.uk>
- *                         http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 GPIO register definitions
-*/
-
-
-#ifndef __ASM_ARCH_REGS_GPIO_H
-#define __ASM_ARCH_REGS_GPIO_H "$Id: gpio.h,v 1.5 2003/05/19 12:51:08 ben Exp $"
-
-#define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
-
-#define S3C2410_GPIO_BANKA   (32*0)
-#define S3C2410_GPIO_BANKB   (32*1)
-#define S3C2410_GPIO_BANKC   (32*2)
-#define S3C2410_GPIO_BANKD   (32*3)
-#define S3C2410_GPIO_BANKE   (32*4)
-#define S3C2410_GPIO_BANKF   (32*5)
-#define S3C2410_GPIO_BANKG   (32*6)
-#define S3C2410_GPIO_BANKH   (32*7)
-
-#ifdef CONFIG_CPU_S3C2400
-#define S3C24XX_GPIO_BASE(x)  S3C2400_GPIO_BASE(x)
-#define S3C24XX_MISCCR        S3C2400_MISCCR
-#else
-#define S3C24XX_GPIO_BASE(x)  S3C2410_GPIO_BASE(x)
-#define S3C24XX_MISCCR        S3C24XX_GPIOREG2(0x80)
-#endif /* CONFIG_CPU_S3C2400 */
-
-
-/* S3C2400 doesn't have a 1:1 mapping to S3C2410 gpio base pins */
-
-#define S3C2400_BANKNUM(pin)     (((pin) & ~31) / 32)
-#define S3C2400_BASEA2B(pin)     ((((pin) & ~31) >> 2))
-#define S3C2400_BASEC2H(pin)     ((S3C2400_BANKNUM(pin) * 10) + \
-                                 (2 * (S3C2400_BANKNUM(pin)-2)))
-
-#define S3C2400_GPIO_BASE(pin)   (pin < S3C2410_GPIO_BANKC ? \
-                                 S3C2400_BASEA2B(pin)+S3C24XX_VA_GPIO : \
-                                 S3C2400_BASEC2H(pin)+S3C24XX_VA_GPIO)
-
-
-#define S3C2410_GPIO_BASE(pin)   ((((pin) & ~31) >> 1) + S3C24XX_VA_GPIO)
-#define S3C2410_GPIO_OFFSET(pin) ((pin) & 31)
-
-/* general configuration options */
-
-#define S3C2410_GPIO_LEAVE   (0xFFFFFFFF)
-#define S3C2410_GPIO_INPUT   (0xFFFFFFF0)       /* not available on A */
-#define S3C2410_GPIO_OUTPUT  (0xFFFFFFF1)
-#define S3C2410_GPIO_IRQ     (0xFFFFFFF2)       /* not available for all */
-#define S3C2410_GPIO_SFN2    (0xFFFFFFF2)       /* bank A => addr/cs/nand */
-#define S3C2410_GPIO_SFN3    (0xFFFFFFF3)       /* not available on A */
-
-/* register address for the GPIO registers.
- * S3C24XX_GPIOREG2 is for the second set of registers in the
- * GPIO which move between s3c2410 and s3c2412 type systems */
-
-#define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO)
-#define S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2)
-
-
-/* configure GPIO ports A..G */
-
-/* port A - S3C2410: 22bits, zero in bit X makes pin X output
- *          S3C2400: 18bits, zero in bit X makes pin X output
- * 1 makes port special function, this is default
-*/
-#define S3C2410_GPACON     S3C2410_GPIOREG(0x00)
-#define S3C2410_GPADAT     S3C2410_GPIOREG(0x04)
-
-#define S3C2400_GPACON     S3C2410_GPIOREG(0x00)
-#define S3C2400_GPADAT     S3C2410_GPIOREG(0x04)
-
-#define S3C2410_GPA0         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0)
-#define S3C2410_GPA0_OUT     (0<<0)
-#define S3C2410_GPA0_ADDR0   (1<<0)
-
-#define S3C2410_GPA1         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 1)
-#define S3C2410_GPA1_OUT     (0<<1)
-#define S3C2410_GPA1_ADDR16  (1<<1)
-
-#define S3C2410_GPA2         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 2)
-#define S3C2410_GPA2_OUT     (0<<2)
-#define S3C2410_GPA2_ADDR17  (1<<2)
-
-#define S3C2410_GPA3         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 3)
-#define S3C2410_GPA3_OUT     (0<<3)
-#define S3C2410_GPA3_ADDR18  (1<<3)
-
-#define S3C2410_GPA4         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 4)
-#define S3C2410_GPA4_OUT     (0<<4)
-#define S3C2410_GPA4_ADDR19  (1<<4)
-
-#define S3C2410_GPA5         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 5)
-#define S3C2410_GPA5_OUT     (0<<5)
-#define S3C2410_GPA5_ADDR20  (1<<5)
-
-#define S3C2410_GPA6         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 6)
-#define S3C2410_GPA6_OUT     (0<<6)
-#define S3C2410_GPA6_ADDR21  (1<<6)
-
-#define S3C2410_GPA7         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 7)
-#define S3C2410_GPA7_OUT     (0<<7)
-#define S3C2410_GPA7_ADDR22  (1<<7)
-
-#define S3C2410_GPA8         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 8)
-#define S3C2410_GPA8_OUT     (0<<8)
-#define S3C2410_GPA8_ADDR23  (1<<8)
-
-#define S3C2410_GPA9         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 9)
-#define S3C2410_GPA9_OUT     (0<<9)
-#define S3C2410_GPA9_ADDR24  (1<<9)
-
-#define S3C2410_GPA10        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10)
-#define S3C2410_GPA10_OUT    (0<<10)
-#define S3C2410_GPA10_ADDR25 (1<<10)
-#define S3C2400_GPA10_SCKE   (1<<10)
-
-#define S3C2410_GPA11        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11)
-#define S3C2410_GPA11_OUT    (0<<11)
-#define S3C2410_GPA11_ADDR26 (1<<11)
-#define S3C2400_GPA11_nCAS0  (1<<11)
-
-#define S3C2410_GPA12        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12)
-#define S3C2410_GPA12_OUT    (0<<12)
-#define S3C2410_GPA12_nGCS1  (1<<12)
-#define S3C2400_GPA12_nCAS1  (1<<12)
-
-#define S3C2410_GPA13        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13)
-#define S3C2410_GPA13_OUT    (0<<13)
-#define S3C2410_GPA13_nGCS2  (1<<13)
-#define S3C2400_GPA13_nGCS1  (1<<13)
-
-#define S3C2410_GPA14        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14)
-#define S3C2410_GPA14_OUT    (0<<14)
-#define S3C2410_GPA14_nGCS3  (1<<14)
-#define S3C2400_GPA14_nGCS2  (1<<14)
-
-#define S3C2410_GPA15        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15)
-#define S3C2410_GPA15_OUT    (0<<15)
-#define S3C2410_GPA15_nGCS4  (1<<15)
-#define S3C2400_GPA15_nGCS3  (1<<15)
-
-#define S3C2410_GPA16        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16)
-#define S3C2410_GPA16_OUT    (0<<16)
-#define S3C2410_GPA16_nGCS5  (1<<16)
-#define S3C2400_GPA16_nGCS4  (1<<16)
-
-#define S3C2410_GPA17        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17)
-#define S3C2410_GPA17_OUT    (0<<17)
-#define S3C2410_GPA17_CLE    (1<<17)
-#define S3C2400_GPA17_nGCS5  (1<<17)
-
-#define S3C2410_GPA18        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18)
-#define S3C2410_GPA18_OUT    (0<<18)
-#define S3C2410_GPA18_ALE    (1<<18)
-
-#define S3C2410_GPA19        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 19)
-#define S3C2410_GPA19_OUT    (0<<19)
-#define S3C2410_GPA19_nFWE   (1<<19)
-
-#define S3C2410_GPA20        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 20)
-#define S3C2410_GPA20_OUT    (0<<20)
-#define S3C2410_GPA20_nFRE   (1<<20)
-
-#define S3C2410_GPA21        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 21)
-#define S3C2410_GPA21_OUT    (0<<21)
-#define S3C2410_GPA21_nRSTOUT (1<<21)
-
-#define S3C2410_GPA22        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 22)
-#define S3C2410_GPA22_OUT    (0<<22)
-#define S3C2410_GPA22_nFCE   (1<<22)
-
-/* 0x08 and 0x0c are reserved on S3C2410 */
-
-/* S3C2410:
- * GPB is 10 IO pins, each configured by 2 bits each in GPBCON.
- *   00 = input, 01 = output, 10=special function, 11=reserved
-
- * S3C2400:
- * GPB is 16 IO pins, each configured by 2 bits each in GPBCON.
- *   00 = input, 01 = output, 10=data, 11=special function
-
- * bit 0,1 = pin 0, 2,3= pin 1...
- *
- * CPBUP = pull up resistor control, 1=disabled, 0=enabled
-*/
-
-#define S3C2410_GPBCON     S3C2410_GPIOREG(0x10)
-#define S3C2410_GPBDAT     S3C2410_GPIOREG(0x14)
-#define S3C2410_GPBUP      S3C2410_GPIOREG(0x18)
-
-#define S3C2400_GPBCON     S3C2410_GPIOREG(0x08)
-#define S3C2400_GPBDAT     S3C2410_GPIOREG(0x0C)
-#define S3C2400_GPBUP      S3C2410_GPIOREG(0x10)
-
-/* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */
-
-#define S3C2410_GPB0         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0)
-#define S3C2410_GPB0_INP     (0x00 << 0)
-#define S3C2410_GPB0_OUTP    (0x01 << 0)
-#define S3C2410_GPB0_TOUT0   (0x02 << 0)
-#define S3C2400_GPB0_DATA16  (0x02 << 0)
-
-#define S3C2410_GPB1         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1)
-#define S3C2410_GPB1_INP     (0x00 << 2)
-#define S3C2410_GPB1_OUTP    (0x01 << 2)
-#define S3C2410_GPB1_TOUT1   (0x02 << 2)
-#define S3C2400_GPB1_DATA17  (0x02 << 2)
-
-#define S3C2410_GPB2         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2)
-#define S3C2410_GPB2_INP     (0x00 << 4)
-#define S3C2410_GPB2_OUTP    (0x01 << 4)
-#define S3C2410_GPB2_TOUT2   (0x02 << 4)
-#define S3C2400_GPB2_DATA18  (0x02 << 4)
-#define S3C2400_GPB2_TCLK1   (0x03 << 4)
-
-#define S3C2410_GPB3         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3)
-#define S3C2410_GPB3_INP     (0x00 << 6)
-#define S3C2410_GPB3_OUTP    (0x01 << 6)
-#define S3C2410_GPB3_TOUT3   (0x02 << 6)
-#define S3C2400_GPB3_DATA19  (0x02 << 6)
-#define S3C2400_GPB3_TXD1    (0x03 << 6)
-
-#define S3C2410_GPB4         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4)
-#define S3C2410_GPB4_INP     (0x00 << 8)
-#define S3C2410_GPB4_OUTP    (0x01 << 8)
-#define S3C2410_GPB4_TCLK0   (0x02 << 8)
-#define S3C2400_GPB4_DATA20  (0x02 << 8)
-#define S3C2410_GPB4_MASK    (0x03 << 8)
-#define S3C2400_GPB4_RXD1    (0x03 << 8)
-#define S3C2400_GPB4_MASK    (0x03 << 8)
-
-#define S3C2410_GPB5         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5)
-#define S3C2410_GPB5_INP     (0x00 << 10)
-#define S3C2410_GPB5_OUTP    (0x01 << 10)
-#define S3C2410_GPB5_nXBACK  (0x02 << 10)
-#define S3C2443_GPB5_XBACK   (0x03 << 10)
-#define S3C2400_GPB5_DATA21  (0x02 << 10)
-#define S3C2400_GPB5_nCTS1   (0x03 << 10)
-
-#define S3C2410_GPB6         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6)
-#define S3C2410_GPB6_INP     (0x00 << 12)
-#define S3C2410_GPB6_OUTP    (0x01 << 12)
-#define S3C2410_GPB6_nXBREQ  (0x02 << 12)
-#define S3C2443_GPB6_XBREQ   (0x03 << 12)
-#define S3C2400_GPB6_DATA22  (0x02 << 12)
-#define S3C2400_GPB6_nRTS1   (0x03 << 12)
-
-#define S3C2410_GPB7         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7)
-#define S3C2410_GPB7_INP     (0x00 << 14)
-#define S3C2410_GPB7_OUTP    (0x01 << 14)
-#define S3C2410_GPB7_nXDACK1 (0x02 << 14)
-#define S3C2443_GPB7_XDACK1  (0x03 << 14)
-#define S3C2400_GPB7_DATA23  (0x02 << 14)
-
-#define S3C2410_GPB8         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8)
-#define S3C2410_GPB8_INP     (0x00 << 16)
-#define S3C2410_GPB8_OUTP    (0x01 << 16)
-#define S3C2410_GPB8_nXDREQ1 (0x02 << 16)
-#define S3C2400_GPB8_DATA24  (0x02 << 16)
-
-#define S3C2410_GPB9         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9)
-#define S3C2410_GPB9_INP     (0x00 << 18)
-#define S3C2410_GPB9_OUTP    (0x01 << 18)
-#define S3C2410_GPB9_nXDACK0 (0x02 << 18)
-#define S3C2443_GPB9_XDACK0  (0x03 << 18)
-#define S3C2400_GPB9_DATA25  (0x02 << 18)
-#define S3C2400_GPB9_I2SSDI  (0x03 << 18)
-
-#define S3C2410_GPB10        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10)
-#define S3C2410_GPB10_INP    (0x00 << 20)
-#define S3C2410_GPB10_OUTP   (0x01 << 20)
-#define S3C2410_GPB10_nXDRE0 (0x02 << 20)
-#define S3C2443_GPB10_XDREQ0 (0x03 << 20)
-#define S3C2400_GPB10_DATA26 (0x02 << 20)
-#define S3C2400_GPB10_nSS    (0x03 << 20)
-
-#define S3C2400_GPB11        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 11)
-#define S3C2400_GPB11_INP    (0x00 << 22)
-#define S3C2400_GPB11_OUTP   (0x01 << 22)
-#define S3C2400_GPB11_DATA27 (0x02 << 22)
-
-#define S3C2400_GPB12        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 12)
-#define S3C2400_GPB12_INP    (0x00 << 24)
-#define S3C2400_GPB12_OUTP   (0x01 << 24)
-#define S3C2400_GPB12_DATA28 (0x02 << 24)
-
-#define S3C2400_GPB13        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 13)
-#define S3C2400_GPB13_INP    (0x00 << 26)
-#define S3C2400_GPB13_OUTP   (0x01 << 26)
-#define S3C2400_GPB13_DATA29 (0x02 << 26)
-
-#define S3C2400_GPB14        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 14)
-#define S3C2400_GPB14_INP    (0x00 << 28)
-#define S3C2400_GPB14_OUTP   (0x01 << 28)
-#define S3C2400_GPB14_DATA30 (0x02 << 28)
-
-#define S3C2400_GPB15        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 15)
-#define S3C2400_GPB15_INP    (0x00 << 30)
-#define S3C2400_GPB15_OUTP   (0x01 << 30)
-#define S3C2400_GPB15_DATA31 (0x02 << 30)
-
-#define S3C2410_GPB_PUPDIS(x)  (1<<(x))
-
-/* Port C consits of 16 GPIO/Special function
- *
- * almost identical setup to port b, but the special functions are mostly
- * to do with the video system's sync/etc.
-*/
-
-#define S3C2410_GPCCON     S3C2410_GPIOREG(0x20)
-#define S3C2410_GPCDAT     S3C2410_GPIOREG(0x24)
-#define S3C2410_GPCUP      S3C2410_GPIOREG(0x28)
-
-#define S3C2400_GPCCON     S3C2410_GPIOREG(0x14)
-#define S3C2400_GPCDAT     S3C2410_GPIOREG(0x18)
-#define S3C2400_GPCUP      S3C2410_GPIOREG(0x1C)
-
-#define S3C2410_GPC0            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0)
-#define S3C2410_GPC0_INP        (0x00 << 0)
-#define S3C2410_GPC0_OUTP       (0x01 << 0)
-#define S3C2410_GPC0_LEND       (0x02 << 0)
-#define S3C2400_GPC0_VD0        (0x02 << 0)
-
-#define S3C2410_GPC1            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1)
-#define S3C2410_GPC1_INP        (0x00 << 2)
-#define S3C2410_GPC1_OUTP       (0x01 << 2)
-#define S3C2410_GPC1_VCLK       (0x02 << 2)
-#define S3C2400_GPC1_VD1        (0x02 << 2)
-
-#define S3C2410_GPC2            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2)
-#define S3C2410_GPC2_INP        (0x00 << 4)
-#define S3C2410_GPC2_OUTP       (0x01 << 4)
-#define S3C2410_GPC2_VLINE      (0x02 << 4)
-#define S3C2400_GPC2_VD2        (0x02 << 4)
-
-#define S3C2410_GPC3            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3)
-#define S3C2410_GPC3_INP        (0x00 << 6)
-#define S3C2410_GPC3_OUTP       (0x01 << 6)
-#define S3C2410_GPC3_VFRAME     (0x02 << 6)
-#define S3C2400_GPC3_VD3        (0x02 << 6)
-
-#define S3C2410_GPC4            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4)
-#define S3C2410_GPC4_INP        (0x00 << 8)
-#define S3C2410_GPC4_OUTP       (0x01 << 8)
-#define S3C2410_GPC4_VM         (0x02 << 8)
-#define S3C2400_GPC4_VD4        (0x02 << 8)
-
-#define S3C2410_GPC5            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5)
-#define S3C2410_GPC5_INP        (0x00 << 10)
-#define S3C2410_GPC5_OUTP       (0x01 << 10)
-#define S3C2410_GPC5_LCDVF0     (0x02 << 10)
-#define S3C2400_GPC5_VD5        (0x02 << 10)
-
-#define S3C2410_GPC6            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6)
-#define S3C2410_GPC6_INP        (0x00 << 12)
-#define S3C2410_GPC6_OUTP       (0x01 << 12)
-#define S3C2410_GPC6_LCDVF1     (0x02 << 12)
-#define S3C2400_GPC6_VD6        (0x02 << 12)
-
-#define S3C2410_GPC7            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7)
-#define S3C2410_GPC7_INP        (0x00 << 14)
-#define S3C2410_GPC7_OUTP       (0x01 << 14)
-#define S3C2410_GPC7_LCDVF2     (0x02 << 14)
-#define S3C2400_GPC7_VD7        (0x02 << 14)
-
-#define S3C2410_GPC8            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8)
-#define S3C2410_GPC8_INP        (0x00 << 16)
-#define S3C2410_GPC8_OUTP       (0x01 << 16)
-#define S3C2410_GPC8_VD0        (0x02 << 16)
-#define S3C2400_GPC8_VD8        (0x02 << 16)
-
-#define S3C2410_GPC9            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9)
-#define S3C2410_GPC9_INP        (0x00 << 18)
-#define S3C2410_GPC9_OUTP       (0x01 << 18)
-#define S3C2410_GPC9_VD1        (0x02 << 18)
-#define S3C2400_GPC9_VD9        (0x02 << 18)
-
-#define S3C2410_GPC10           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10)
-#define S3C2410_GPC10_INP       (0x00 << 20)
-#define S3C2410_GPC10_OUTP      (0x01 << 20)
-#define S3C2410_GPC10_VD2       (0x02 << 20)
-#define S3C2400_GPC10_VD10      (0x02 << 20)
-
-#define S3C2410_GPC11           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11)
-#define S3C2410_GPC11_INP       (0x00 << 22)
-#define S3C2410_GPC11_OUTP      (0x01 << 22)
-#define S3C2410_GPC11_VD3       (0x02 << 22)
-#define S3C2400_GPC11_VD11      (0x02 << 22)
-
-#define S3C2410_GPC12           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12)
-#define S3C2410_GPC12_INP       (0x00 << 24)
-#define S3C2410_GPC12_OUTP      (0x01 << 24)
-#define S3C2410_GPC12_VD4       (0x02 << 24)
-#define S3C2400_GPC12_VD12      (0x02 << 24)
-
-#define S3C2410_GPC13           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13)
-#define S3C2410_GPC13_INP       (0x00 << 26)
-#define S3C2410_GPC13_OUTP      (0x01 << 26)
-#define S3C2410_GPC13_VD5       (0x02 << 26)
-#define S3C2400_GPC13_VD13      (0x02 << 26)
-
-#define S3C2410_GPC14           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14)
-#define S3C2410_GPC14_INP       (0x00 << 28)
-#define S3C2410_GPC14_OUTP      (0x01 << 28)
-#define S3C2410_GPC14_VD6       (0x02 << 28)
-#define S3C2400_GPC14_VD14      (0x02 << 28)
-
-#define S3C2410_GPC15           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15)
-#define S3C2410_GPC15_INP       (0x00 << 30)
-#define S3C2410_GPC15_OUTP      (0x01 << 30)
-#define S3C2410_GPC15_VD7       (0x02 << 30)
-#define S3C2400_GPC15_VD15      (0x02 << 30)
-
-#define S3C2410_GPC_PUPDIS(x)  (1<<(x))
-
-/*
- * S3C2410: Port D consists of 16 GPIO/Special function
- *
- * almost identical setup to port b, but the special functions are mostly
- * to do with the video system's data.
- *
- * S3C2400: Port D consists of 11 GPIO/Special function
- *
- * almost identical setup to port c
-*/
-
-#define S3C2410_GPDCON     S3C2410_GPIOREG(0x30)
-#define S3C2410_GPDDAT     S3C2410_GPIOREG(0x34)
-#define S3C2410_GPDUP      S3C2410_GPIOREG(0x38)
-
-#define S3C2400_GPDCON     S3C2410_GPIOREG(0x20)
-#define S3C2400_GPDDAT     S3C2410_GPIOREG(0x24)
-#define S3C2400_GPDUP      S3C2410_GPIOREG(0x28)
-
-#define S3C2410_GPD0            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0)
-#define S3C2410_GPD0_INP        (0x00 << 0)
-#define S3C2410_GPD0_OUTP       (0x01 << 0)
-#define S3C2410_GPD0_VD8        (0x02 << 0)
-#define S3C2400_GPD0_VFRAME     (0x02 << 0)
-#define S3C2442_GPD0_nSPICS1    (0x03 << 0)
-
-#define S3C2410_GPD1            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1)
-#define S3C2410_GPD1_INP        (0x00 << 2)
-#define S3C2410_GPD1_OUTP       (0x01 << 2)
-#define S3C2410_GPD1_VD9        (0x02 << 2)
-#define S3C2400_GPD1_VM         (0x02 << 2)
-#define S3C2442_GPD1_SPICLK1    (0x03 << 2)
-
-#define S3C2410_GPD2            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2)
-#define S3C2410_GPD2_INP        (0x00 << 4)
-#define S3C2410_GPD2_OUTP       (0x01 << 4)
-#define S3C2410_GPD2_VD10       (0x02 << 4)
-#define S3C2400_GPD2_VLINE      (0x02 << 4)
-
-#define S3C2410_GPD3            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3)
-#define S3C2410_GPD3_INP        (0x00 << 6)
-#define S3C2410_GPD3_OUTP       (0x01 << 6)
-#define S3C2410_GPD3_VD11       (0x02 << 6)
-#define S3C2400_GPD3_VCLK       (0x02 << 6)
-
-#define S3C2410_GPD4            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4)
-#define S3C2410_GPD4_INP        (0x00 << 8)
-#define S3C2410_GPD4_OUTP       (0x01 << 8)
-#define S3C2410_GPD4_VD12       (0x02 << 8)
-#define S3C2400_GPD4_LEND       (0x02 << 8)
-
-#define S3C2410_GPD5            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5)
-#define S3C2410_GPD5_INP        (0x00 << 10)
-#define S3C2410_GPD5_OUTP       (0x01 << 10)
-#define S3C2410_GPD5_VD13       (0x02 << 10)
-#define S3C2400_GPD5_TOUT0      (0x02 << 10)
-
-#define S3C2410_GPD6            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6)
-#define S3C2410_GPD6_INP        (0x00 << 12)
-#define S3C2410_GPD6_OUTP       (0x01 << 12)
-#define S3C2410_GPD6_VD14       (0x02 << 12)
-#define S3C2400_GPD6_TOUT1      (0x02 << 12)
-
-#define S3C2410_GPD7            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7)
-#define S3C2410_GPD7_INP        (0x00 << 14)
-#define S3C2410_GPD7_OUTP       (0x01 << 14)
-#define S3C2410_GPD7_VD15       (0x02 << 14)
-#define S3C2400_GPD7_TOUT2      (0x02 << 14)
-
-#define S3C2410_GPD8            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8)
-#define S3C2410_GPD8_INP        (0x00 << 16)
-#define S3C2410_GPD8_OUTP       (0x01 << 16)
-#define S3C2410_GPD8_VD16       (0x02 << 16)
-#define S3C2400_GPD8_TOUT3      (0x02 << 16)
-
-#define S3C2410_GPD9            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9)
-#define S3C2410_GPD9_INP        (0x00 << 18)
-#define S3C2410_GPD9_OUTP       (0x01 << 18)
-#define S3C2410_GPD9_VD17       (0x02 << 18)
-#define S3C2400_GPD9_TCLK0      (0x02 << 18)
-#define S3C2410_GPD9_MASK       (0x03 << 18)
-
-#define S3C2410_GPD10           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10)
-#define S3C2410_GPD10_INP       (0x00 << 20)
-#define S3C2410_GPD10_OUTP      (0x01 << 20)
-#define S3C2410_GPD10_VD18      (0x02 << 20)
-#define S3C2400_GPD10_nWAIT     (0x02 << 20)
-
-#define S3C2410_GPD11           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11)
-#define S3C2410_GPD11_INP       (0x00 << 22)
-#define S3C2410_GPD11_OUTP      (0x01 << 22)
-#define S3C2410_GPD11_VD19      (0x02 << 22)
-
-#define S3C2410_GPD12           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 12)
-#define S3C2410_GPD12_INP       (0x00 << 24)
-#define S3C2410_GPD12_OUTP      (0x01 << 24)
-#define S3C2410_GPD12_VD20      (0x02 << 24)
-
-#define S3C2410_GPD13           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 13)
-#define S3C2410_GPD13_INP       (0x00 << 26)
-#define S3C2410_GPD13_OUTP      (0x01 << 26)
-#define S3C2410_GPD13_VD21      (0x02 << 26)
-
-#define S3C2410_GPD14           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 14)
-#define S3C2410_GPD14_INP       (0x00 << 28)
-#define S3C2410_GPD14_OUTP      (0x01 << 28)
-#define S3C2410_GPD14_VD22      (0x02 << 28)
-#define S3C2410_GPD14_nSS1      (0x03 << 28)
-
-#define S3C2410_GPD15           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15)
-#define S3C2410_GPD15_INP       (0x00 << 30)
-#define S3C2410_GPD15_OUTP      (0x01 << 30)
-#define S3C2410_GPD15_VD23      (0x02 << 30)
-#define S3C2410_GPD15_nSS0      (0x03 << 30)
-
-#define S3C2410_GPD_PUPDIS(x)  (1<<(x))
-
-/* S3C2410:
- * Port E consists of 16 GPIO/Special function
- *
- * again, the same as port B, but dealing with I2S, SDI, and
- * more miscellaneous functions
- *
- * S3C2400:
- * Port E consists of 12 GPIO/Special function
- *
- * GPIO / interrupt inputs
-*/
-
-#define S3C2410_GPECON     S3C2410_GPIOREG(0x40)
-#define S3C2410_GPEDAT     S3C2410_GPIOREG(0x44)
-#define S3C2410_GPEUP      S3C2410_GPIOREG(0x48)
-
-#define S3C2400_GPECON     S3C2410_GPIOREG(0x2C)
-#define S3C2400_GPEDAT     S3C2410_GPIOREG(0x30)
-#define S3C2400_GPEUP      S3C2410_GPIOREG(0x34)
-
-#define S3C2410_GPE0           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0)
-#define S3C2410_GPE0_INP       (0x00 << 0)
-#define S3C2410_GPE0_OUTP      (0x01 << 0)
-#define S3C2410_GPE0_I2SLRCK   (0x02 << 0)
-#define S3C2443_GPE0_AC_nRESET (0x03 << 0)
-#define S3C2400_GPE0_EINT0     (0x02 << 0)
-#define S3C2410_GPE0_MASK      (0x03 << 0)
-
-#define S3C2410_GPE1           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1)
-#define S3C2410_GPE1_INP       (0x00 << 2)
-#define S3C2410_GPE1_OUTP      (0x01 << 2)
-#define S3C2410_GPE1_I2SSCLK   (0x02 << 2)
-#define S3C2443_GPE1_AC_SYNC   (0x03 << 2)
-#define S3C2400_GPE1_EINT1     (0x02 << 2)
-#define S3C2400_GPE1_nSS       (0x03 << 2)
-#define S3C2410_GPE1_MASK      (0x03 << 2)
-
-#define S3C2410_GPE2           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2)
-#define S3C2410_GPE2_INP       (0x00 << 4)
-#define S3C2410_GPE2_OUTP      (0x01 << 4)
-#define S3C2410_GPE2_CDCLK     (0x02 << 4)
-#define S3C2443_GPE2_AC_BITCLK (0x03 << 4)
-#define S3C2400_GPE2_EINT2     (0x02 << 4)
-#define S3C2400_GPE2_I2SSDI    (0x03 << 4)
-
-#define S3C2410_GPE3           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3)
-#define S3C2410_GPE3_INP       (0x00 << 6)
-#define S3C2410_GPE3_OUTP      (0x01 << 6)
-#define S3C2410_GPE3_I2SSDI    (0x02 << 6)
-#define S3C2443_GPE3_AC_SDI    (0x03 << 6)
-#define S3C2400_GPE3_EINT3     (0x02 << 6)
-#define S3C2400_GPE3_nCTS1     (0x03 << 6)
-#define S3C2410_GPE3_nSS0      (0x03 << 6)
-#define S3C2410_GPE3_MASK      (0x03 << 6)
-
-#define S3C2410_GPE4           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 4)
-#define S3C2410_GPE4_INP       (0x00 << 8)
-#define S3C2410_GPE4_OUTP      (0x01 << 8)
-#define S3C2410_GPE4_I2SSDO    (0x02 << 8)
-#define S3C2443_GPE4_AC_SDO    (0x03 << 8)
-#define S3C2400_GPE4_EINT4     (0x02 << 8)
-#define S3C2400_GPE4_nRTS1     (0x03 << 8)
-#define S3C2410_GPE4_I2SSDI    (0x03 << 8)
-#define S3C2410_GPE4_MASK      (0x03 << 8)
-
-#define S3C2410_GPE5           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 5)
-#define S3C2410_GPE5_INP       (0x00 << 10)
-#define S3C2410_GPE5_OUTP      (0x01 << 10)
-#define S3C2410_GPE5_SDCLK     (0x02 << 10)
-#define S3C2443_GPE5_SD1_CLK   (0x02 << 10)
-#define S3C2400_GPE5_EINT5     (0x02 << 10)
-#define S3C2400_GPE5_TCLK1     (0x03 << 10)
-
-#define S3C2410_GPE6           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6)
-#define S3C2410_GPE6_INP       (0x00 << 12)
-#define S3C2410_GPE6_OUTP      (0x01 << 12)
-#define S3C2410_GPE6_SDCMD     (0x02 << 12)
-#define S3C2443_GPE6_SD1_CMD   (0x02 << 12)
-#define S3C2443_GPE6_AC_BITCLK (0x03 << 12)
-#define S3C2400_GPE6_EINT6     (0x02 << 12)
-
-#define S3C2410_GPE7           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7)
-#define S3C2410_GPE7_INP       (0x00 << 14)
-#define S3C2410_GPE7_OUTP      (0x01 << 14)
-#define S3C2410_GPE7_SDDAT0    (0x02 << 14)
-#define S3C2443_GPE5_SD1_DAT0  (0x02 << 14)
-#define S3C2443_GPE7_AC_SDI    (0x03 << 14)
-#define S3C2400_GPE7_EINT7     (0x02 << 14)
-
-#define S3C2410_GPE8           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8)
-#define S3C2410_GPE8_INP       (0x00 << 16)
-#define S3C2410_GPE8_OUTP      (0x01 << 16)
-#define S3C2410_GPE8_SDDAT1    (0x02 << 16)
-#define S3C2443_GPE8_SD1_DAT1  (0x02 << 16)
-#define S3C2443_GPE8_AC_SDO    (0x03 << 16)
-#define S3C2400_GPE8_nXDACK0   (0x02 << 16)
-
-#define S3C2410_GPE9           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9)
-#define S3C2410_GPE9_INP       (0x00 << 18)
-#define S3C2410_GPE9_OUTP      (0x01 << 18)
-#define S3C2410_GPE9_SDDAT2    (0x02 << 18)
-#define S3C2443_GPE9_SD1_DAT2  (0x02 << 18)
-#define S3C2443_GPE9_AC_SYNC   (0x03 << 18)
-#define S3C2400_GPE9_nXDACK1   (0x02 << 18)
-#define S3C2400_GPE9_nXBACK    (0x03 << 18)
-
-#define S3C2410_GPE10          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10)
-#define S3C2410_GPE10_INP      (0x00 << 20)
-#define S3C2410_GPE10_OUTP     (0x01 << 20)
-#define S3C2410_GPE10_SDDAT3   (0x02 << 20)
-#define S3C2443_GPE10_SD1_DAT3 (0x02 << 20)
-#define S3C2443_GPE10_AC_nRESET (0x03 << 20)
-#define S3C2400_GPE10_nXDREQ0  (0x02 << 20)
-
-#define S3C2410_GPE11          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11)
-#define S3C2410_GPE11_INP      (0x00 << 22)
-#define S3C2410_GPE11_OUTP     (0x01 << 22)
-#define S3C2410_GPE11_SPIMISO0 (0x02 << 22)
-#define S3C2400_GPE11_nXDREQ1  (0x02 << 22)
-#define S3C2400_GPE11_nXBREQ   (0x03 << 22)
-
-#define S3C2410_GPE12          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12)
-#define S3C2410_GPE12_INP      (0x00 << 24)
-#define S3C2410_GPE12_OUTP     (0x01 << 24)
-#define S3C2410_GPE12_SPIMOSI0 (0x02 << 24)
-
-#define S3C2410_GPE13          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 13)
-#define S3C2410_GPE13_INP      (0x00 << 26)
-#define S3C2410_GPE13_OUTP     (0x01 << 26)
-#define S3C2410_GPE13_SPICLK0  (0x02 << 26)
-
-#define S3C2410_GPE14          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 14)
-#define S3C2410_GPE14_INP      (0x00 << 28)
-#define S3C2410_GPE14_OUTP     (0x01 << 28)
-#define S3C2410_GPE14_IICSCL   (0x02 << 28)
-#define S3C2410_GPE14_MASK     (0x03 << 28)
-
-#define S3C2410_GPE15          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 15)
-#define S3C2410_GPE15_INP      (0x00 << 30)
-#define S3C2410_GPE15_OUTP     (0x01 << 30)
-#define S3C2410_GPE15_IICSDA   (0x02 << 30)
-#define S3C2410_GPE15_MASK     (0x03 << 30)
-
-#define S3C2440_GPE0_ACSYNC    (0x03 << 0)
-#define S3C2440_GPE1_ACBITCLK  (0x03 << 2)
-#define S3C2440_GPE2_ACRESET   (0x03 << 4)
-#define S3C2440_GPE3_ACIN      (0x03 << 6)
-#define S3C2440_GPE4_ACOUT     (0x03 << 8)
-
-#define S3C2410_GPE_PUPDIS(x)  (1<<(x))
-
-/* S3C2410:
- * Port F consists of 8 GPIO/Special function
- *
- * GPIO / interrupt inputs
- *
- * GPFCON has 2 bits for each of the input pins on port F
- *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined
- *
- * pull up works like all other ports.
- *
- * S3C2400:
- * Port F consists of 7 GPIO/Special function
- *
- * GPIO/serial/misc pins
-*/
-
-#define S3C2410_GPFCON     S3C2410_GPIOREG(0x50)
-#define S3C2410_GPFDAT     S3C2410_GPIOREG(0x54)
-#define S3C2410_GPFUP      S3C2410_GPIOREG(0x58)
-
-#define S3C2400_GPFCON     S3C2410_GPIOREG(0x38)
-#define S3C2400_GPFDAT     S3C2410_GPIOREG(0x3C)
-#define S3C2400_GPFUP      S3C2410_GPIOREG(0x40)
-
-#define S3C2410_GPF0        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0)
-#define S3C2410_GPF0_INP    (0x00 << 0)
-#define S3C2410_GPF0_OUTP   (0x01 << 0)
-#define S3C2410_GPF0_EINT0  (0x02 << 0)
-#define S3C2400_GPF0_RXD0   (0x02 << 0)
-
-#define S3C2410_GPF1        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1)
-#define S3C2410_GPF1_INP    (0x00 << 2)
-#define S3C2410_GPF1_OUTP   (0x01 << 2)
-#define S3C2410_GPF1_EINT1  (0x02 << 2)
-#define S3C2400_GPF1_RXD1   (0x02 << 2)
-#define S3C2400_GPF1_IICSDA (0x03 << 2)
-
-#define S3C2410_GPF2        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2)
-#define S3C2410_GPF2_INP    (0x00 << 4)
-#define S3C2410_GPF2_OUTP   (0x01 << 4)
-#define S3C2410_GPF2_EINT2  (0x02 << 4)
-#define S3C2400_GPF2_TXD0   (0x02 << 4)
-
-#define S3C2410_GPF3        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3)
-#define S3C2410_GPF3_INP    (0x00 << 6)
-#define S3C2410_GPF3_OUTP   (0x01 << 6)
-#define S3C2410_GPF3_EINT3  (0x02 << 6)
-#define S3C2400_GPF3_TXD1   (0x02 << 6)
-#define S3C2400_GPF3_IICSCL (0x03 << 6)
-
-#define S3C2410_GPF4        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4)
-#define S3C2410_GPF4_INP    (0x00 << 8)
-#define S3C2410_GPF4_OUTP   (0x01 << 8)
-#define S3C2410_GPF4_EINT4  (0x02 << 8)
-#define S3C2400_GPF4_nRTS0  (0x02 << 8)
-#define S3C2400_GPF4_nXBACK (0x03 << 8)
-
-#define S3C2410_GPF5        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5)
-#define S3C2410_GPF5_INP    (0x00 << 10)
-#define S3C2410_GPF5_OUTP   (0x01 << 10)
-#define S3C2410_GPF5_EINT5  (0x02 << 10)
-#define S3C2400_GPF5_nCTS0  (0x02 << 10)
-#define S3C2400_GPF5_nXBREQ (0x03 << 10)
-
-#define S3C2410_GPF6        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6)
-#define S3C2410_GPF6_INP    (0x00 << 12)
-#define S3C2410_GPF6_OUTP   (0x01 << 12)
-#define S3C2410_GPF6_EINT6  (0x02 << 12)
-#define S3C2400_GPF6_CLKOUT (0x02 << 12)
-
-#define S3C2410_GPF7        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7)
-#define S3C2410_GPF7_INP    (0x00 << 14)
-#define S3C2410_GPF7_OUTP   (0x01 << 14)
-#define S3C2410_GPF7_EINT7  (0x02 << 14)
-
-#define S3C2410_GPF_PUPDIS(x)  (1<<(x))
-
-/* S3C2410:
- * Port G consists of 8 GPIO/IRQ/Special function
- *
- * GPGCON has 2 bits for each of the input pins on port F
- *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
- *
- * pull up works like all other ports.
- *
- * S3C2400:
- * Port G consists of 10 GPIO/Special function
-*/
-
-#define S3C2410_GPGCON     S3C2410_GPIOREG(0x60)
-#define S3C2410_GPGDAT     S3C2410_GPIOREG(0x64)
-#define S3C2410_GPGUP      S3C2410_GPIOREG(0x68)
-
-#define S3C2400_GPGCON     S3C2410_GPIOREG(0x44)
-#define S3C2400_GPGDAT     S3C2410_GPIOREG(0x48)
-#define S3C2400_GPGUP      S3C2410_GPIOREG(0x4C)
-
-#define S3C2410_GPG0          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0)
-#define S3C2410_GPG0_INP      (0x00 << 0)
-#define S3C2410_GPG0_OUTP     (0x01 << 0)
-#define S3C2410_GPG0_EINT8    (0x02 << 0)
-#define S3C2400_GPG0_I2SLRCK  (0x02 << 0)
-
-#define S3C2410_GPG1          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1)
-#define S3C2410_GPG1_INP      (0x00 << 2)
-#define S3C2410_GPG1_OUTP     (0x01 << 2)
-#define S3C2410_GPG1_EINT9    (0x02 << 2)
-#define S3C2400_GPG1_I2SSCLK  (0x02 << 2)
-
-#define S3C2410_GPG2          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2)
-#define S3C2410_GPG2_INP      (0x00 << 4)
-#define S3C2410_GPG2_OUTP     (0x01 << 4)
-#define S3C2410_GPG2_EINT10   (0x02 << 4)
-#define S3C2410_GPG2_nSS0     (0x03 << 4)
-#define S3C2400_GPG2_CDCLK    (0x02 << 4)
-
-#define S3C2410_GPG3          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3)
-#define S3C2410_GPG3_INP      (0x00 << 6)
-#define S3C2410_GPG3_OUTP     (0x01 << 6)
-#define S3C2410_GPG3_EINT11   (0x02 << 6)
-#define S3C2410_GPG3_nSS1     (0x03 << 6)
-#define S3C2400_GPG3_I2SSDO   (0x02 << 6)
-#define S3C2400_GPG3_I2SSDI   (0x03 << 6)
-
-#define S3C2410_GPG4          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4)
-#define S3C2410_GPG4_INP      (0x00 << 8)
-#define S3C2410_GPG4_OUTP     (0x01 << 8)
-#define S3C2410_GPG4_EINT12   (0x02 << 8)
-#define S3C2400_GPG4_MMCCLK   (0x02 << 8)
-#define S3C2400_GPG4_I2SSDI   (0x03 << 8)
-#define S3C2410_GPG4_LCDPWREN (0x03 << 8)
-#define S3C2443_GPG4_LCDPWRDN (0x03 << 8)
-
-#define S3C2410_GPG5          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5)
-#define S3C2410_GPG5_INP      (0x00 << 10)
-#define S3C2410_GPG5_OUTP     (0x01 << 10)
-#define S3C2410_GPG5_EINT13   (0x02 << 10)
-#define S3C2400_GPG5_MMCCMD   (0x02 << 10)
-#define S3C2400_GPG5_IICSDA   (0x03 << 10)
-#define S3C2410_GPG5_SPIMISO1 (0x03 << 10)      /* not s3c2443 */
-
-#define S3C2410_GPG6          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6)
-#define S3C2410_GPG6_INP      (0x00 << 12)
-#define S3C2410_GPG6_OUTP     (0x01 << 12)
-#define S3C2410_GPG6_EINT14   (0x02 << 12)
-#define S3C2400_GPG6_MMCDAT   (0x02 << 12)
-#define S3C2400_GPG6_IICSCL   (0x03 << 12)
-#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)
-
-#define S3C2410_GPG7          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7)
-#define S3C2410_GPG7_INP      (0x00 << 14)
-#define S3C2410_GPG7_OUTP     (0x01 << 14)
-#define S3C2410_GPG7_EINT15   (0x02 << 14)
-#define S3C2410_GPG7_SPICLK1  (0x03 << 14)
-#define S3C2400_GPG7_SPIMISO  (0x02 << 14)
-#define S3C2400_GPG7_IICSDA   (0x03 << 14)
-
-#define S3C2410_GPG8          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8)
-#define S3C2410_GPG8_INP      (0x00 << 16)
-#define S3C2410_GPG8_OUTP     (0x01 << 16)
-#define S3C2410_GPG8_EINT16   (0x02 << 16)
-#define S3C2400_GPG8_SPIMOSI  (0x02 << 16)
-#define S3C2400_GPG8_IICSCL   (0x03 << 16)
-
-#define S3C2410_GPG9          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9)
-#define S3C2410_GPG9_INP      (0x00 << 18)
-#define S3C2410_GPG9_OUTP     (0x01 << 18)
-#define S3C2410_GPG9_EINT17   (0x02 << 18)
-#define S3C2400_GPG9_SPICLK   (0x02 << 18)
-#define S3C2400_GPG9_MMCCLK   (0x03 << 18)
-
-#define S3C2410_GPG10         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
-#define S3C2410_GPG10_INP     (0x00 << 20)
-#define S3C2410_GPG10_OUTP    (0x01 << 20)
-#define S3C2410_GPG10_EINT18  (0x02 << 20)
-
-#define S3C2410_GPG11         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 11)
-#define S3C2410_GPG11_INP     (0x00 << 22)
-#define S3C2410_GPG11_OUTP    (0x01 << 22)
-#define S3C2410_GPG11_EINT19  (0x02 << 22)
-#define S3C2410_GPG11_TCLK1   (0x03 << 22)
-#define S3C2443_GPG11_CF_nIREQ (0x03 << 22)
-
-#define S3C2410_GPG12         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 12)
-#define S3C2410_GPG12_INP     (0x00 << 24)
-#define S3C2410_GPG12_OUTP    (0x01 << 24)
-#define S3C2410_GPG12_EINT20  (0x02 << 24)
-#define S3C2410_GPG12_XMON    (0x03 << 24)
-#define S3C2442_GPG12_nSPICS0 (0x03 << 24)
-#define S3C2443_GPG12_nINPACK (0x03 << 24)
-
-#define S3C2410_GPG13         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13)
-#define S3C2410_GPG13_INP     (0x00 << 26)
-#define S3C2410_GPG13_OUTP    (0x01 << 26)
-#define S3C2410_GPG13_EINT21  (0x02 << 26)
-#define S3C2410_GPG13_nXPON   (0x03 << 26)
-#define S3C2443_GPG13_CF_nREG (0x03 << 26)
-
-#define S3C2410_GPG14         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 14)
-#define S3C2410_GPG14_INP     (0x00 << 28)
-#define S3C2410_GPG14_OUTP    (0x01 << 28)
-#define S3C2410_GPG14_EINT22  (0x02 << 28)
-#define S3C2410_GPG14_YMON    (0x03 << 28)
-#define S3C2443_GPG14_CF_RESET (0x03 << 28)
-
-#define S3C2410_GPG15         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 15)
-#define S3C2410_GPG15_INP     (0x00 << 30)
-#define S3C2410_GPG15_OUTP    (0x01 << 30)
-#define S3C2410_GPG15_EINT23  (0x02 << 30)
-#define S3C2410_GPG15_nYPON   (0x03 << 30)
-#define S3C2443_GPG15_CF_PWR  (0x03 << 30)
-
-#define S3C2410_GPG_PUPDIS(x)  (1<<(x))
-
-/* Port H consists of11 GPIO/serial/Misc pins
- *
- * GPGCON has 2 bits for each of the input pins on port F
- *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
- *
- * pull up works like all other ports.
-*/
-
-#define S3C2410_GPHCON     S3C2410_GPIOREG(0x70)
-#define S3C2410_GPHDAT     S3C2410_GPIOREG(0x74)
-#define S3C2410_GPHUP      S3C2410_GPIOREG(0x78)
-
-#define S3C2410_GPH0        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 0)
-#define S3C2410_GPH0_INP    (0x00 << 0)
-#define S3C2410_GPH0_OUTP   (0x01 << 0)
-#define S3C2410_GPH0_nCTS0  (0x02 << 0)
-
-#define S3C2410_GPH1        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 1)
-#define S3C2410_GPH1_INP    (0x00 << 2)
-#define S3C2410_GPH1_OUTP   (0x01 << 2)
-#define S3C2410_GPH1_nRTS0  (0x02 << 2)
-
-#define S3C2410_GPH2        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 2)
-#define S3C2410_GPH2_INP    (0x00 << 4)
-#define S3C2410_GPH2_OUTP   (0x01 << 4)
-#define S3C2410_GPH2_TXD0   (0x02 << 4)
-
-#define S3C2410_GPH3        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 3)
-#define S3C2410_GPH3_INP    (0x00 << 6)
-#define S3C2410_GPH3_OUTP   (0x01 << 6)
-#define S3C2410_GPH3_RXD0   (0x02 << 6)
-
-#define S3C2410_GPH4        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 4)
-#define S3C2410_GPH4_INP    (0x00 << 8)
-#define S3C2410_GPH4_OUTP   (0x01 << 8)
-#define S3C2410_GPH4_TXD1   (0x02 << 8)
-
-#define S3C2410_GPH5        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 5)
-#define S3C2410_GPH5_INP    (0x00 << 10)
-#define S3C2410_GPH5_OUTP   (0x01 << 10)
-#define S3C2410_GPH5_RXD1   (0x02 << 10)
-
-#define S3C2410_GPH6        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 6)
-#define S3C2410_GPH6_INP    (0x00 << 12)
-#define S3C2410_GPH6_OUTP   (0x01 << 12)
-#define S3C2410_GPH6_TXD2   (0x02 << 12)
-#define S3C2410_GPH6_nRTS1  (0x03 << 12)
-
-#define S3C2410_GPH7        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 7)
-#define S3C2410_GPH7_INP    (0x00 << 14)
-#define S3C2410_GPH7_OUTP   (0x01 << 14)
-#define S3C2410_GPH7_RXD2   (0x02 << 14)
-#define S3C2410_GPH7_nCTS1  (0x03 << 14)
-
-#define S3C2410_GPH8        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 8)
-#define S3C2410_GPH8_INP    (0x00 << 16)
-#define S3C2410_GPH8_OUTP   (0x01 << 16)
-#define S3C2410_GPH8_UCLK   (0x02 << 16)
-
-#define S3C2410_GPH9          S3C2410_GPIONO(S3C2410_GPIO_BANKH, 9)
-#define S3C2410_GPH9_INP      (0x00 << 18)
-#define S3C2410_GPH9_OUTP     (0x01 << 18)
-#define S3C2410_GPH9_CLKOUT0  (0x02 << 18)
-#define S3C2442_GPH9_nSPICS0  (0x03 << 18)
-
-#define S3C2410_GPH10         S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10)
-#define S3C2410_GPH10_INP     (0x00 << 20)
-#define S3C2410_GPH10_OUTP    (0x01 << 20)
-#define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
-
-/* The S3C2412 and S3C2413 move the GPJ register set to after
- * GPH, which means all registers after 0x80 are now offset by 0x10
- * for the 2412/2413 from the 2410/2440/2442
-*/
-
-/* miscellaneous control */
-#define S3C2400_MISCCR     S3C2410_GPIOREG(0x54)
-#define S3C2410_MISCCR     S3C2410_GPIOREG(0x80)
-#define S3C2410_DCLKCON    S3C2410_GPIOREG(0x84)
-
-#define S3C24XX_DCLKCON    S3C24XX_GPIOREG2(0x84)
-
-/* see clock.h for dclk definitions */
-
-/* pullup control on databus */
-#define S3C2410_MISCCR_SPUCR_HEN    (0<<0)
-#define S3C2410_MISCCR_SPUCR_HDIS   (1<<0)
-#define S3C2410_MISCCR_SPUCR_LEN    (0<<1)
-#define S3C2410_MISCCR_SPUCR_LDIS   (1<<1)
-
-#define S3C2400_MISCCR_SPUCR_LEN    (0<<0)
-#define S3C2400_MISCCR_SPUCR_LDIS   (1<<0)
-#define S3C2400_MISCCR_SPUCR_HEN    (0<<1)
-#define S3C2400_MISCCR_SPUCR_HDIS   (1<<1)
-
-#define S3C2400_MISCCR_HZ_STOPEN    (0<<2)
-#define S3C2400_MISCCR_HZ_STOPPREV  (1<<2)
-
-#define S3C2410_MISCCR_USBDEV       (0<<3)
-#define S3C2410_MISCCR_USBHOST      (1<<3)
-
-#define S3C2410_MISCCR_CLK0_MPLL    (0<<4)
-#define S3C2410_MISCCR_CLK0_UPLL    (1<<4)
-#define S3C2410_MISCCR_CLK0_FCLK    (2<<4)
-#define S3C2410_MISCCR_CLK0_HCLK    (3<<4)
-#define S3C2410_MISCCR_CLK0_PCLK    (4<<4)
-#define S3C2410_MISCCR_CLK0_DCLK0   (5<<4)
-#define S3C2410_MISCCR_CLK0_MASK    (7<<4)
-
-#define S3C2412_MISCCR_CLK0_RTC     (2<<4)
-
-#define S3C2410_MISCCR_CLK1_MPLL    (0<<8)
-#define S3C2410_MISCCR_CLK1_UPLL    (1<<8)
-#define S3C2410_MISCCR_CLK1_FCLK    (2<<8)
-#define S3C2410_MISCCR_CLK1_HCLK    (3<<8)
-#define S3C2410_MISCCR_CLK1_PCLK    (4<<8)
-#define S3C2410_MISCCR_CLK1_DCLK1   (5<<8)
-#define S3C2410_MISCCR_CLK1_MASK    (7<<8)
-
-#define S3C2412_MISCCR_CLK1_CLKsrc  (0<<8)
-
-#define S3C2410_MISCCR_USBSUSPND0   (1<<12)
-#define S3C2410_MISCCR_USBSUSPND1   (1<<13)
-
-#define S3C2410_MISCCR_nRSTCON      (1<<16)
-
-#define S3C2410_MISCCR_nEN_SCLK0    (1<<17)
-#define S3C2410_MISCCR_nEN_SCLK1    (1<<18)
-#define S3C2410_MISCCR_nEN_SCLKE    (1<<19)     /* not 2412 */
-#define S3C2410_MISCCR_SDSLEEP      (7<<17)
-
-/* external interrupt control... */
-/* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7
- * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15
- * S3C2410_EXTINT2 -> irq sense control for EINT16..EINT23
- *
- * note S3C2410_EXTINT2 has filtering options for EINT16..EINT23
- *
- * Samsung datasheet p9-25
-*/
-#define S3C2400_EXTINT0    S3C2410_GPIOREG(0x58)
-#define S3C2410_EXTINT0    S3C2410_GPIOREG(0x88)
-#define S3C2410_EXTINT1    S3C2410_GPIOREG(0x8C)
-#define S3C2410_EXTINT2    S3C2410_GPIOREG(0x90)
-
-#define S3C24XX_EXTINT0    S3C24XX_GPIOREG2(0x88)
-#define S3C24XX_EXTINT1    S3C24XX_GPIOREG2(0x8C)
-#define S3C24XX_EXTINT2    S3C24XX_GPIOREG2(0x90)
-
-/* values for S3C2410_EXTINT0/1/2 */
-#define S3C2410_EXTINT_LOWLEV    (0x00)
-#define S3C2410_EXTINT_HILEV     (0x01)
-#define S3C2410_EXTINT_FALLEDGE  (0x02)
-#define S3C2410_EXTINT_RISEEDGE  (0x04)
-#define S3C2410_EXTINT_BOTHEDGE  (0x06)
-
-/* interrupt filtering conrrol for EINT16..EINT23 */
-#define S3C2410_EINFLT0    S3C2410_GPIOREG(0x94)
-#define S3C2410_EINFLT1    S3C2410_GPIOREG(0x98)
-#define S3C2410_EINFLT2    S3C2410_GPIOREG(0x9C)
-#define S3C2410_EINFLT3    S3C2410_GPIOREG(0xA0)
-
-#define S3C24XX_EINFLT0    S3C24XX_GPIOREG2(0x94)
-#define S3C24XX_EINFLT1    S3C24XX_GPIOREG2(0x98)
-#define S3C24XX_EINFLT2    S3C24XX_GPIOREG2(0x9C)
-#define S3C24XX_EINFLT3    S3C24XX_GPIOREG2(0xA0)
-
-/* values for interrupt filtering */
-#define S3C2410_EINTFLT_PCLK            (0x00)
-#define S3C2410_EINTFLT_EXTCLK          (1<<7)
-#define S3C2410_EINTFLT_WIDTHMSK(x)     ((x) & 0x3f)
-
-/* removed EINTxxxx defs from here, not meant for this */
-
-/* GSTATUS have miscellaneous information in them
- *
- * These move between s3c2410 and s3c2412 style systems.
- */
-
-#define S3C2410_GSTATUS0   S3C2410_GPIOREG(0x0AC)
-#define S3C2410_GSTATUS1   S3C2410_GPIOREG(0x0B0)
-#define S3C2410_GSTATUS2   S3C2410_GPIOREG(0x0B4)
-#define S3C2410_GSTATUS3   S3C2410_GPIOREG(0x0B8)
-#define S3C2410_GSTATUS4   S3C2410_GPIOREG(0x0BC)
-
-#define S3C2412_GSTATUS0   S3C2410_GPIOREG(0x0BC)
-#define S3C2412_GSTATUS1   S3C2410_GPIOREG(0x0C0)
-#define S3C2412_GSTATUS2   S3C2410_GPIOREG(0x0C4)
-#define S3C2412_GSTATUS3   S3C2410_GPIOREG(0x0C8)
-#define S3C2412_GSTATUS4   S3C2410_GPIOREG(0x0CC)
-
-#define S3C24XX_GSTATUS0   S3C24XX_GPIOREG2(0x0AC)
-#define S3C24XX_GSTATUS1   S3C24XX_GPIOREG2(0x0B0)
-#define S3C24XX_GSTATUS2   S3C24XX_GPIOREG2(0x0B4)
-#define S3C24XX_GSTATUS3   S3C24XX_GPIOREG2(0x0B8)
-#define S3C24XX_GSTATUS4   S3C24XX_GPIOREG2(0x0BC)
-
-#define S3C2410_GSTATUS0_nWAIT     (1<<3)
-#define S3C2410_GSTATUS0_NCON      (1<<2)
-#define S3C2410_GSTATUS0_RnB       (1<<1)
-#define S3C2410_GSTATUS0_nBATTFLT  (1<<0)
-
-#define S3C2410_GSTATUS1_IDMASK    (0xffff0000)
-#define S3C2410_GSTATUS1_2410      (0x32410000)
-#define S3C2410_GSTATUS1_2412      (0x32412001)
-#define S3C2410_GSTATUS1_2440      (0x32440000)
-#define S3C2410_GSTATUS1_2442      (0x32440aaa)
-
-#define S3C2410_GSTATUS2_WTRESET   (1<<2)
-#define S3C2410_GSTATUS2_OFFRESET  (1<<1)
-#define S3C2410_GSTATUS2_PONRESET  (1<<0)
-
-/* open drain control register */
-#define S3C2400_OPENCR     S3C2410_GPIOREG(0x50)
-
-#define S3C2400_OPENCR_OPC_RXD1DIS  (0<<0)
-#define S3C2400_OPENCR_OPC_RXD1EN   (1<<0)
-#define S3C2400_OPENCR_OPC_TXD1DIS  (0<<1)
-#define S3C2400_OPENCR_OPC_TXD1EN   (1<<1)
-#define S3C2400_OPENCR_OPC_CMDDIS   (0<<2)
-#define S3C2400_OPENCR_OPC_CMDEN    (1<<2)
-#define S3C2400_OPENCR_OPC_DATDIS   (0<<3)
-#define S3C2400_OPENCR_OPC_DATEN    (1<<3)
-#define S3C2400_OPENCR_OPC_MISODIS  (0<<4)
-#define S3C2400_OPENCR_OPC_MISOEN   (1<<4)
-#define S3C2400_OPENCR_OPC_MOSIDIS  (0<<5)
-#define S3C2400_OPENCR_OPC_MOSIEN   (1<<5)
-
-/* 2412/2413 sleep configuration registers */
-
-#define S3C2412_GPBSLPCON       S3C2410_GPIOREG(0x1C)
-#define S3C2412_GPCSLPCON       S3C2410_GPIOREG(0x2C)
-#define S3C2412_GPDSLPCON       S3C2410_GPIOREG(0x3C)
-#define S3C2412_GPFSLPCON       S3C2410_GPIOREG(0x5C)
-#define S3C2412_GPGSLPCON       S3C2410_GPIOREG(0x6C)
-#define S3C2412_GPHSLPCON       S3C2410_GPIOREG(0x7C)
-
-/* definitions for each pin bit */
-#define S3C2412_GPIO_SLPCON_LOW  ( 0x00 )
-#define S3C2412_GPIO_SLPCON_HIGH ( 0x01 )
-#define S3C2412_GPIO_SLPCON_IN   ( 0x02 )
-#define S3C2412_GPIO_SLPCON_PULL ( 0x03 )
-
-#define S3C2412_SLPCON_LOW(x)   ( 0x00 << ((x) * 2))
-#define S3C2412_SLPCON_HIGH(x)  ( 0x01 << ((x) * 2))
-#define S3C2412_SLPCON_IN(x)    ( 0x02 << ((x) * 2))
-#define S3C2412_SLPCON_PULL(x)  ( 0x03 << ((x) * 2))
-#define S3C2412_SLPCON_EINT(x)  ( 0x02 << ((x) * 2))  /* only IRQ pins */
-#define S3C2412_SLPCON_MASK(x)  ( 0x03 << ((x) * 2))
-
-#define S3C2412_SLPCON_ALL_LOW  (0x0)
-#define S3C2412_SLPCON_ALL_HIGH (0x11111111 | 0x44444444)
-#define S3C2412_SLPCON_ALL_IN   (0x22222222 | 0x88888888)
-#define S3C2412_SLPCON_ALL_PULL (0x33333333)
-
-#endif  /* __ASM_ARCH_REGS_GPIO_H */
-
diff --git a/include/asm-arm/arch-s3c2410/regs-gpioj.h b/include/asm-arm/arch-s3c2410/regs-gpioj.h
deleted file mode 100644
index 0362332faaf0..000000000000
--- a/include/asm-arm/arch-s3c2410/regs-gpioj.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-gpioj.h
- *
- * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
- *                    http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2440 GPIO J register definitions
-*/
-
-
-#ifndef __ASM_ARCH_REGS_GPIOJ_H
-#define __ASM_ARCH_REGS_GPIOJ_H "gpioj"
-
-/* Port J consists of 13 GPIO/Camera pins
- *
- * GPJCON has 2 bits for each of the input pins on port F
- *   00 = 0 input, 1 output, 2 Camera
- *
- * pull up works like all other ports.
-*/
-
-#define S3C2440_GPIO_BANKJ  (416)
-
-#define S3C2440_GPJCON      S3C2410_GPIOREG(0xd0)
-#define S3C2440_GPJDAT      S3C2410_GPIOREG(0xd4)
-#define S3C2440_GPJUP       S3C2410_GPIOREG(0xd8)
-
-#define S3C2413_GPJCON          S3C2410_GPIOREG(0x80)
-#define S3C2413_GPJDAT          S3C2410_GPIOREG(0x84)
-#define S3C2413_GPJUP           S3C2410_GPIOREG(0x88)
-#define S3C2413_GPJSLPCON       S3C2410_GPIOREG(0x8C)
-
-#define S3C2440_GPJ0            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 0)
-#define S3C2440_GPJ0_INP        (0x00 << 0)
-#define S3C2440_GPJ0_OUTP       (0x01 << 0)
-#define S3C2440_GPJ0_CAMDATA0   (0x02 << 0)
-
-#define S3C2440_GPJ1            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 1)
-#define S3C2440_GPJ1_INP        (0x00 << 2)
-#define S3C2440_GPJ1_OUTP       (0x01 << 2)
-#define S3C2440_GPJ1_CAMDATA1   (0x02 << 2)
-
-#define S3C2440_GPJ2            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 2)
-#define S3C2440_GPJ2_INP        (0x00 << 4)
-#define S3C2440_GPJ2_OUTP       (0x01 << 4)
-#define S3C2440_GPJ2_CAMDATA2   (0x02 << 4)
-
-#define S3C2440_GPJ3            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 3)
-#define S3C2440_GPJ3_INP        (0x00 << 6)
-#define S3C2440_GPJ3_OUTP       (0x01 << 6)
-#define S3C2440_GPJ3_CAMDATA3   (0x02 << 6)
-
-#define S3C2440_GPJ4            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 4)
-#define S3C2440_GPJ4_INP        (0x00 << 8)
-#define S3C2440_GPJ4_OUTP       (0x01 << 8)
-#define S3C2440_GPJ4_CAMDATA4   (0x02 << 8)
-
-#define S3C2440_GPJ5            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 5)
-#define S3C2440_GPJ5_INP        (0x00 << 10)
-#define S3C2440_GPJ5_OUTP       (0x01 << 10)
-#define S3C2440_GPJ5_CAMDATA5   (0x02 << 10)
-
-#define S3C2440_GPJ6            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 6)
-#define S3C2440_GPJ6_INP        (0x00 << 12)
-#define S3C2440_GPJ6_OUTP       (0x01 << 12)
-#define S3C2440_GPJ6_CAMDATA6   (0x02 << 12)
-
-#define S3C2440_GPJ7            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 7)
-#define S3C2440_GPJ7_INP        (0x00 << 14)
-#define S3C2440_GPJ7_OUTP       (0x01 << 14)
-#define S3C2440_GPJ7_CAMDATA7   (0x02 << 14)
-
-#define S3C2440_GPJ8            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 8)
-#define S3C2440_GPJ8_INP        (0x00 << 16)
-#define S3C2440_GPJ8_OUTP       (0x01 << 16)
-#define S3C2440_GPJ8_CAMPCLK    (0x02 << 16)
-
-#define S3C2440_GPJ9            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 9)
-#define S3C2440_GPJ9_INP        (0x00 << 18)
-#define S3C2440_GPJ9_OUTP       (0x01 << 18)
-#define S3C2440_GPJ9_CAMVSYNC   (0x02 << 18)
-
-#define S3C2440_GPJ10           S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 10)
-#define S3C2440_GPJ10_INP       (0x00 << 20)
-#define S3C2440_GPJ10_OUTP      (0x01 << 20)
-#define S3C2440_GPJ10_CAMHREF   (0x02 << 20)
-
-#define S3C2440_GPJ11           S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 11)
-#define S3C2440_GPJ11_INP       (0x00 << 22)
-#define S3C2440_GPJ11_OUTP      (0x01 << 22)
-#define S3C2440_GPJ11_CAMCLKOUT (0x02 << 22)
-
-#define S3C2440_GPJ12           S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 12)
-#define S3C2440_GPJ12_INP       (0x00 << 24)
-#define S3C2440_GPJ12_OUTP      (0x01 << 24)
-#define S3C2440_GPJ12_CAMRESET  (0x02 << 24)
-
-#define S3C2443_GPJ13           S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 13)
-#define S3C2443_GPJ14           S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 14)
-#define S3C2443_GPJ15           S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 15)
-
-#endif  /* __ASM_ARCH_REGS_GPIOJ_H */
-
diff --git a/include/asm-arm/arch-s3c2410/regs-irq.h b/include/asm-arm/arch-s3c2410/regs-irq.h
deleted file mode 100644
index 498184cb8adc..000000000000
--- a/include/asm-arm/arch-s3c2410/regs-irq.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-irq.h
- *
- * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
- *                    http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-
-#ifndef ___ASM_ARCH_REGS_IRQ_H
-#define ___ASM_ARCH_REGS_IRQ_H "$Id: irq.h,v 1.3 2003/03/25 21:29:06 ben Exp $"
-
-/* interrupt controller */
-
-#define S3C2410_IRQREG(x)   ((x) + S3C24XX_VA_IRQ)
-#define S3C2410_EINTREG(x)  ((x) + S3C24XX_VA_GPIO)
-#define S3C24XX_EINTREG(x)  ((x) + S3C24XX_VA_GPIO2)
-
-#define S3C2410_SRCPND         S3C2410_IRQREG(0x000)
-#define S3C2410_INTMOD         S3C2410_IRQREG(0x004)
-#define S3C2410_INTMSK         S3C2410_IRQREG(0x008)
-#define S3C2410_PRIORITY       S3C2410_IRQREG(0x00C)
-#define S3C2410_INTPND         S3C2410_IRQREG(0x010)
-#define S3C2410_INTOFFSET      S3C2410_IRQREG(0x014)
-#define S3C2410_SUBSRCPND      S3C2410_IRQREG(0x018)
-#define S3C2410_INTSUBMSK      S3C2410_IRQREG(0x01C)
-
-/* mask: 0=enable, 1=disable
- * 1 bit EINT, 4=EINT4, 23=EINT23
- * EINT0,1,2,3 are not handled here.
-*/
-
-#define S3C2410_EINTMASK       S3C2410_EINTREG(0x0A4)
-#define S3C2410_EINTPEND       S3C2410_EINTREG(0X0A8)
-#define S3C2412_EINTMASK       S3C2410_EINTREG(0x0B4)
-#define S3C2412_EINTPEND       S3C2410_EINTREG(0X0B8)
-
-#define S3C24XX_EINTMASK       S3C24XX_EINTREG(0x0A4)
-#define S3C24XX_EINTPEND       S3C24XX_EINTREG(0X0A8)
-
-#endif /* ___ASM_ARCH_REGS_IRQ_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-lcd.h b/include/asm-arm/arch-s3c2410/regs-lcd.h
deleted file mode 100644
index bd854845697f..000000000000
--- a/include/asm-arm/arch-s3c2410/regs-lcd.h
+++ /dev/null
@@ -1,162 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-lcd.h
- *
- * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
- *                    http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-
-#ifndef ___ASM_ARCH_REGS_LCD_H
-#define ___ASM_ARCH_REGS_LCD_H "$Id: lcd.h,v 1.3 2003/06/26 13:25:06 ben Exp $"
-
-#define S3C2410_LCDREG(x)       (x)
-
-/* LCD control registers */
-#define S3C2410_LCDCON1     S3C2410_LCDREG(0x00)
-#define S3C2410_LCDCON2     S3C2410_LCDREG(0x04)
-#define S3C2410_LCDCON3     S3C2410_LCDREG(0x08)
-#define S3C2410_LCDCON4     S3C2410_LCDREG(0x0C)
-#define S3C2410_LCDCON5     S3C2410_LCDREG(0x10)
-
-#define S3C2410_LCDCON1_CLKVAL(x)  ((x) << 8)
-#define S3C2410_LCDCON1_MMODE      (1<<7)
-#define S3C2410_LCDCON1_DSCAN4     (0<<5)
-#define S3C2410_LCDCON1_STN4       (1<<5)
-#define S3C2410_LCDCON1_STN8       (2<<5)
-#define S3C2410_LCDCON1_TFT        (3<<5)
-
-#define S3C2410_LCDCON1_STN1BPP    (0<<1)
-#define S3C2410_LCDCON1_STN2GREY   (1<<1)
-#define S3C2410_LCDCON1_STN4GREY   (2<<1)
-#define S3C2410_LCDCON1_STN8BPP    (3<<1)
-#define S3C2410_LCDCON1_STN12BPP   (4<<1)
-
-#define S3C2410_LCDCON1_TFT1BPP    (8<<1)
-#define S3C2410_LCDCON1_TFT2BPP    (9<<1)
-#define S3C2410_LCDCON1_TFT4BPP    (10<<1)
-#define S3C2410_LCDCON1_TFT8BPP    (11<<1)
-#define S3C2410_LCDCON1_TFT16BPP   (12<<1)
-#define S3C2410_LCDCON1_TFT24BPP   (13<<1)
-
-#define S3C2410_LCDCON1_ENVID      (1)
-
-#define S3C2410_LCDCON1_MODEMASK    0x1E
-
-#define S3C2410_LCDCON2_VBPD(x)     ((x) << 24)
-#define S3C2410_LCDCON2_LINEVAL(x)  ((x) << 14)
-#define S3C2410_LCDCON2_VFPD(x)     ((x) << 6)
-#define S3C2410_LCDCON2_VSPW(x)     ((x) << 0)
-
-#define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF)
-#define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >>  6) & 0xFF)
-#define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >>  0) & 0x3F)
-
-#define S3C2410_LCDCON3_HBPD(x)     ((x) << 19)
-#define S3C2410_LCDCON3_WDLY(x)     ((x) << 19)
-#define S3C2410_LCDCON3_HOZVAL(x)   ((x) << 8)
-#define S3C2410_LCDCON3_HFPD(x)     ((x) << 0)
-#define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0)
-
-#define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F)
-#define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >>  0) & 0xFF)
-
-/* LDCCON4 changes for STN mode on the S3C2412 */
-
-#define S3C2410_LCDCON4_MVAL(x)     ((x) << 8)
-#define S3C2410_LCDCON4_HSPW(x)     ((x) << 0)
-#define S3C2410_LCDCON4_WLH(x)      ((x) << 0)
-
-#define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >>  0) & 0xFF)
-
-#define S3C2410_LCDCON5_BPP24BL     (1<<12)
-#define S3C2410_LCDCON5_FRM565      (1<<11)
-#define S3C2410_LCDCON5_INVVCLK     (1<<10)
-#define S3C2410_LCDCON5_INVVLINE    (1<<9)
-#define S3C2410_LCDCON5_INVVFRAME   (1<<8)
-#define S3C2410_LCDCON5_INVVD       (1<<7)
-#define S3C2410_LCDCON5_INVVDEN     (1<<6)
-#define S3C2410_LCDCON5_INVPWREN    (1<<5)
-#define S3C2410_LCDCON5_INVLEND     (1<<4)
-#define S3C2410_LCDCON5_PWREN       (1<<3)
-#define S3C2410_LCDCON5_ENLEND      (1<<2)
-#define S3C2410_LCDCON5_BSWP        (1<<1)
-#define S3C2410_LCDCON5_HWSWP       (1<<0)
-
-/* framebuffer start addressed */
-#define S3C2410_LCDSADDR1   S3C2410_LCDREG(0x14)
-#define S3C2410_LCDSADDR2   S3C2410_LCDREG(0x18)
-#define S3C2410_LCDSADDR3   S3C2410_LCDREG(0x1C)
-
-#define S3C2410_LCDBANK(x)      ((x) << 21)
-#define S3C2410_LCDBASEU(x)     (x)
-
-#define S3C2410_OFFSIZE(x)      ((x) << 11)
-#define S3C2410_PAGEWIDTH(x)    (x)
-
-/* colour lookup and miscellaneous controls */
-
-#define S3C2410_REDLUT     S3C2410_LCDREG(0x20)
-#define S3C2410_GREENLUT   S3C2410_LCDREG(0x24)
-#define S3C2410_BLUELUT    S3C2410_LCDREG(0x28)
-
-#define S3C2410_DITHMODE   S3C2410_LCDREG(0x4C)
-#define S3C2410_TPAL       S3C2410_LCDREG(0x50)
-
-#define S3C2410_TPAL_EN         (1<<24)
-
-/* interrupt info */
-#define S3C2410_LCDINTPND  S3C2410_LCDREG(0x54)
-#define S3C2410_LCDSRCPND  S3C2410_LCDREG(0x58)
-#define S3C2410_LCDINTMSK  S3C2410_LCDREG(0x5C)
-#define S3C2410_LCDINT_FIWSEL   (1<<2)
-#define S3C2410_LCDINT_FRSYNC   (1<<1)
-#define S3C2410_LCDINT_FICNT    (1<<0)
-
-/* s3c2442 extra stn registers */
-
-#define S3C2442_REDLUT          S3C2410_LCDREG(0x20)
-#define S3C2442_GREENLUT        S3C2410_LCDREG(0x24)
-#define S3C2442_BLUELUT         S3C2410_LCDREG(0x28)
-#define S3C2442_DITHMODE        S3C2410_LCDREG(0x20)
-
-#define S3C2410_LPCSEL     S3C2410_LCDREG(0x60)
-
-#define S3C2410_TFTPAL(x)  S3C2410_LCDREG((0x400 + (x)*4))
-
-/* S3C2412 registers */
-
-#define S3C2412_TPAL            S3C2410_LCDREG(0x20)
-
-#define S3C2412_LCDINTPND       S3C2410_LCDREG(0x24)
-#define S3C2412_LCDSRCPND       S3C2410_LCDREG(0x28)
-#define S3C2412_LCDINTMSK       S3C2410_LCDREG(0x2C)
-
-#define S3C2412_TCONSEL         S3C2410_LCDREG(0x30)
-
-#define S3C2412_LCDCON6         S3C2410_LCDREG(0x34)
-#define S3C2412_LCDCON7         S3C2410_LCDREG(0x38)
-#define S3C2412_LCDCON8         S3C2410_LCDREG(0x3C)
-#define S3C2412_LCDCON9         S3C2410_LCDREG(0x40)
-
-#define S3C2412_REDLUT(x)       S3C2410_LCDREG(0x44 + ((x)*4))
-#define S3C2412_GREENLUT(x)     S3C2410_LCDREG(0x60 + ((x)*4))
-#define S3C2412_BLUELUT(x)      S3C2410_LCDREG(0x98 + ((x)*4))
-
-#define S3C2412_FRCPAT(x)       S3C2410_LCDREG(0xB4 + ((x)*4))
-
-/* general registers */
-
-/* base of the LCD registers, where INTPND, INTSRC and then INTMSK
- * are available. */
-
-#define S3C2410_LCDINTBASE      S3C2410_LCDREG(0x54)
-#define S3C2412_LCDINTBASE      S3C2410_LCDREG(0x24)
-
-#define S3C24XX_LCDINTPND       (0x00)
-#define S3C24XX_LCDSRCPND       (0x04)
-#define S3C24XX_LCDINTMSK       (0x08)
-
-#endif /* ___ASM_ARCH_REGS_LCD_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-mem.h b/include/asm-arm/arch-s3c2410/regs-mem.h
deleted file mode 100644
index 312ff93b63c6..000000000000
--- a/include/asm-arm/arch-s3c2410/regs-mem.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-mem.h
- *
- * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
- *              http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 Memory Control register definitions
-*/
-
-#ifndef __ASM_ARM_MEMREGS_H
-#define __ASM_ARM_MEMREGS_H "$Id: regs.h,v 1.8 2003/05/01 15:55:41 ben Exp $"
-
-#ifndef S3C2410_MEMREG
-#define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
-#endif
-
-/* bus width, and wait state control */
-#define S3C2410_BWSCON                  S3C2410_MEMREG(0x0000)
-
-/* bank zero config - note, pinstrapped from OM pins! */
-#define S3C2410_BWSCON_DW0_16           (1<<1)
-#define S3C2410_BWSCON_DW0_32           (2<<1)
-
-/* bank one configs */
-#define S3C2410_BWSCON_DW1_8            (0<<4)
-#define S3C2410_BWSCON_DW1_16           (1<<4)
-#define S3C2410_BWSCON_DW1_32           (2<<4)
-#define S3C2410_BWSCON_WS1              (1<<6)
-#define S3C2410_BWSCON_ST1              (1<<7)
-
-/* bank 2 configurations */
-#define S3C2410_BWSCON_DW2_8            (0<<8)
-#define S3C2410_BWSCON_DW2_16           (1<<8)
-#define S3C2410_BWSCON_DW2_32           (2<<8)
-#define S3C2410_BWSCON_WS2              (1<<10)
-#define S3C2410_BWSCON_ST2              (1<<11)
-
-/* bank 3 configurations */
-#define S3C2410_BWSCON_DW3_8            (0<<12)
-#define S3C2410_BWSCON_DW3_16           (1<<12)
-#define S3C2410_BWSCON_DW3_32           (2<<12)
-#define S3C2410_BWSCON_WS3              (1<<14)
-#define S3C2410_BWSCON_ST3              (1<<15)
-
-/* bank 4 configurations */
-#define S3C2410_BWSCON_DW4_8            (0<<16)
-#define S3C2410_BWSCON_DW4_16           (1<<16)
-#define S3C2410_BWSCON_DW4_32           (2<<16)
-#define S3C2410_BWSCON_WS4              (1<<18)
-#define S3C2410_BWSCON_ST4              (1<<19)
-
-/* bank 5 configurations */
-#define S3C2410_BWSCON_DW5_8            (0<<20)
-#define S3C2410_BWSCON_DW5_16           (1<<20)
-#define S3C2410_BWSCON_DW5_32           (2<<20)
-#define S3C2410_BWSCON_WS5              (1<<22)
-#define S3C2410_BWSCON_ST5              (1<<23)
-
-/* bank 6 configurations */
-#define S3C2410_BWSCON_DW6_8            (0<<24)
-#define S3C2410_BWSCON_DW6_16           (1<<24)
-#define S3C2410_BWSCON_DW6_32           (2<<24)
-#define S3C2410_BWSCON_WS6              (1<<26)
-#define S3C2410_BWSCON_ST6              (1<<27)
-
-/* bank 7 configurations */
-#define S3C2410_BWSCON_DW7_8            (0<<28)
-#define S3C2410_BWSCON_DW7_16           (1<<28)
-#define S3C2410_BWSCON_DW7_32           (2<<28)
-#define S3C2410_BWSCON_WS7              (1<<30)
-#define S3C2410_BWSCON_ST7              (1<<31)
-
-/* memory set (rom, ram) */
-#define S3C2410_BANKCON0                S3C2410_MEMREG(0x0004)
-#define S3C2410_BANKCON1                S3C2410_MEMREG(0x0008)
-#define S3C2410_BANKCON2                S3C2410_MEMREG(0x000C)
-#define S3C2410_BANKCON3                S3C2410_MEMREG(0x0010)
-#define S3C2410_BANKCON4                S3C2410_MEMREG(0x0014)
-#define S3C2410_BANKCON5                S3C2410_MEMREG(0x0018)
-#define S3C2410_BANKCON6                S3C2410_MEMREG(0x001C)
-#define S3C2410_BANKCON7                S3C2410_MEMREG(0x0020)
-
-/* bank configuration registers */
-
-#define S3C2410_BANKCON_PMCnorm         (0x00)
-#define S3C2410_BANKCON_PMC4            (0x01)
-#define S3C2410_BANKCON_PMC8            (0x02)
-#define S3C2410_BANKCON_PMC16           (0x03)
-
-/* bank configurations for banks 0..7, note banks
- * 6 and 7 have differnt configurations depending on
- * the memory type bits */
-
-#define S3C2410_BANKCON_Tacp2           (0x0 << 2)
-#define S3C2410_BANKCON_Tacp3           (0x1 << 2)
-#define S3C2410_BANKCON_Tacp4           (0x2 << 2)
-#define S3C2410_BANKCON_Tacp6           (0x3 << 2)
-#define S3C2410_BANKCON_Tacp_SHIFT      (2)
-
-#define S3C2410_BANKCON_Tcah0           (0x0 << 4)
-#define S3C2410_BANKCON_Tcah1           (0x1 << 4)
-#define S3C2410_BANKCON_Tcah2           (0x2 << 4)
-#define S3C2410_BANKCON_Tcah4           (0x3 << 4)
-#define S3C2410_BANKCON_Tcah_SHIFT      (4)
-
-#define S3C2410_BANKCON_Tcoh0           (0x0 << 6)
-#define S3C2410_BANKCON_Tcoh1           (0x1 << 6)
-#define S3C2410_BANKCON_Tcoh2           (0x2 << 6)
-#define S3C2410_BANKCON_Tcoh4           (0x3 << 6)
-#define S3C2410_BANKCON_Tcoh_SHIFT      (6)
-
-#define S3C2410_BANKCON_Tacc1           (0x0 << 8)
-#define S3C2410_BANKCON_Tacc2           (0x1 << 8)
-#define S3C2410_BANKCON_Tacc3           (0x2 << 8)
-#define S3C2410_BANKCON_Tacc4           (0x3 << 8)
-#define S3C2410_BANKCON_Tacc6           (0x4 << 8)
-#define S3C2410_BANKCON_Tacc8           (0x5 << 8)
-#define S3C2410_BANKCON_Tacc10          (0x6 << 8)
-#define S3C2410_BANKCON_Tacc14          (0x7 << 8)
-#define S3C2410_BANKCON_Tacc_SHIFT      (8)
-
-#define S3C2410_BANKCON_Tcos0           (0x0 << 11)
-#define S3C2410_BANKCON_Tcos1           (0x1 << 11)
-#define S3C2410_BANKCON_Tcos2           (0x2 << 11)
-#define S3C2410_BANKCON_Tcos4           (0x3 << 11)
-#define S3C2410_BANKCON_Tcos_SHIFT      (11)
-
-#define S3C2410_BANKCON_Tacs0           (0x0 << 13)
-#define S3C2410_BANKCON_Tacs1           (0x1 << 13)
-#define S3C2410_BANKCON_Tacs2           (0x2 << 13)
-#define S3C2410_BANKCON_Tacs4           (0x3 << 13)
-#define S3C2410_BANKCON_Tacs_SHIFT      (13)
-
-#define S3C2410_BANKCON_SRAM            (0x0 << 15)
-#define S3C2400_BANKCON_EDODRAM         (0x2 << 15)
-#define S3C2410_BANKCON_SDRAM           (0x3 << 15)
-
-/* next bits only for EDO DRAM in 6,7 */
-#define S3C2400_BANKCON_EDO_Trcd1      (0x00 << 4)
-#define S3C2400_BANKCON_EDO_Trcd2      (0x01 << 4)
-#define S3C2400_BANKCON_EDO_Trcd3      (0x02 << 4)
-#define S3C2400_BANKCON_EDO_Trcd4      (0x03 << 4)
-
-/* CAS pulse width */
-#define S3C2400_BANKCON_EDO_PULSE1     (0x00 << 3)
-#define S3C2400_BANKCON_EDO_PULSE2     (0x01 << 3)
-
-/* CAS pre-charge */
-#define S3C2400_BANKCON_EDO_TCP1       (0x00 << 2)
-#define S3C2400_BANKCON_EDO_TCP2       (0x01 << 2)
-
-/* control column address select */
-#define S3C2400_BANKCON_EDO_SCANb8     (0x00 << 0)
-#define S3C2400_BANKCON_EDO_SCANb9     (0x01 << 0)
-#define S3C2400_BANKCON_EDO_SCANb10    (0x02 << 0)
-#define S3C2400_BANKCON_EDO_SCANb11    (0x03 << 0)
-
-/* next bits only for SDRAM in 6,7 */
-#define S3C2410_BANKCON_Trcd2           (0x00 << 2)
-#define S3C2410_BANKCON_Trcd3           (0x01 << 2)
-#define S3C2410_BANKCON_Trcd4           (0x02 << 2)
-
-/* control column address select */
-#define S3C2410_BANKCON_SCANb8          (0x00 << 0)
-#define S3C2410_BANKCON_SCANb9          (0x01 << 0)
-#define S3C2410_BANKCON_SCANb10         (0x02 << 0)
-
-#define S3C2410_REFRESH                 S3C2410_MEMREG(0x0024)
-#define S3C2410_BANKSIZE                S3C2410_MEMREG(0x0028)
-#define S3C2410_MRSRB6                  S3C2410_MEMREG(0x002C)
-#define S3C2410_MRSRB7                  S3C2410_MEMREG(0x0030)
-
-/* refresh control */
-
-#define S3C2410_REFRESH_REFEN           (1<<23)
-#define S3C2410_REFRESH_SELF            (1<<22)
-#define S3C2410_REFRESH_REFCOUNTER      ((1<<11)-1)
-
-#define S3C2410_REFRESH_TRP_MASK        (3<<20)
-#define S3C2410_REFRESH_TRP_2clk        (0<<20)
-#define S3C2410_REFRESH_TRP_3clk        (1<<20)
-#define S3C2410_REFRESH_TRP_4clk        (2<<20)
-
-#define S3C2400_REFRESH_DRAM_TRP_MASK   (3<<20)
-#define S3C2400_REFRESH_DRAM_TRP_1_5clk (0<<20)
-#define S3C2400_REFRESH_DRAM_TRP_2_5clk (1<<20)
-#define S3C2400_REFRESH_DRAM_TRP_3_5clk (2<<20)
-#define S3C2400_REFRESH_DRAM_TRP_4_5clk (3<<20)
-
-#define S3C2410_REFRESH_TSRC_MASK       (3<<18)
-#define S3C2410_REFRESH_TSRC_4clk       (0<<18)
-#define S3C2410_REFRESH_TSRC_5clk       (1<<18)
-#define S3C2410_REFRESH_TSRC_6clk       (2<<18)
-#define S3C2410_REFRESH_TSRC_7clk       (3<<18)
-
-
-/* mode select register(s) */
-
-#define  S3C2410_MRSRB_CL1              (0x00 << 4)
-#define  S3C2410_MRSRB_CL2              (0x02 << 4)
-#define  S3C2410_MRSRB_CL3              (0x03 << 4)
-
-/* bank size register */
-#define S3C2410_BANKSIZE_128M           (0x2 << 0)
-#define S3C2410_BANKSIZE_64M            (0x1 << 0)
-#define S3C2410_BANKSIZE_32M            (0x0 << 0)
-#define S3C2410_BANKSIZE_16M            (0x7 << 0)
-#define S3C2410_BANKSIZE_8M             (0x6 << 0)
-#define S3C2410_BANKSIZE_4M             (0x5 << 0)
-#define S3C2410_BANKSIZE_2M             (0x4 << 0)
-#define S3C2410_BANKSIZE_MASK           (0x7 << 0)
-#define S3C2400_BANKSIZE_MASK           (0x4 << 0)
-#define S3C2410_BANKSIZE_SCLK_EN        (1<<4)
-#define S3C2410_BANKSIZE_SCKE_EN        (1<<5)
-#define S3C2410_BANKSIZE_BURST          (1<<7)
-
-#endif /* __ASM_ARM_MEMREGS_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-power.h b/include/asm-arm/arch-s3c2410/regs-power.h
deleted file mode 100644
index 13d13b7cfe98..000000000000
--- a/include/asm-arm/arch-s3c2410/regs-power.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-power.h
- *
- * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk>
- *                    http://armlinux.simtec.co.uk/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C24XX power control register definitions
-*/
-
-#ifndef __ASM_ARM_REGS_PWR
-#define __ASM_ARM_REGS_PWR __FILE__
-
-#define S3C24XX_PWRREG(x) ((x) + S3C24XX_VA_CLKPWR)
-
-#define S3C2412_PWRMODECON      S3C24XX_PWRREG(0x20)
-#define S3C2412_PWRCFG          S3C24XX_PWRREG(0x24)
-
-#define S3C2412_INFORM0         S3C24XX_PWRREG(0x70)
-#define S3C2412_INFORM1         S3C24XX_PWRREG(0x74)
-#define S3C2412_INFORM2         S3C24XX_PWRREG(0x78)
-#define S3C2412_INFORM3         S3C24XX_PWRREG(0x7C)
-
-#define S3C2412_PWRCFG_BATF_IRQ                 (1<<0)
-#define S3C2412_PWRCFG_BATF_IGNORE              (2<<0)
-#define S3C2412_PWRCFG_BATF_SLEEP               (3<<0)
-#define S3C2412_PWRCFG_BATF_MASK                (3<<0)
-
-#define S3C2412_PWRCFG_STANDBYWFI_IGNORE        (0<<6)
-#define S3C2412_PWRCFG_STANDBYWFI_IDLE          (1<<6)
-#define S3C2412_PWRCFG_STANDBYWFI_STOP          (2<<6)
-#define S3C2412_PWRCFG_STANDBYWFI_SLEEP         (3<<6)
-#define S3C2412_PWRCFG_STANDBYWFI_MASK          (3<<6)
-
-#define S3C2412_PWRCFG_RTC_MASKIRQ              (1<<8)
-#define S3C2412_PWRCFG_NAND_NORST               (1<<9)
-
-#endif /* __ASM_ARM_REGS_PWR */
diff --git a/include/asm-arm/arch-s3c2410/regs-s3c2412-mem.h b/include/asm-arm/arch-s3c2410/regs-s3c2412-mem.h
deleted file mode 100644
index c8c793e78936..000000000000
--- a/include/asm-arm/arch-s3c2410/regs-s3c2412-mem.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-s3c2412-mem.h
- *
- * Copyright (c) 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2412 memory register definitions
-*/
-
-#ifndef __ASM_ARM_REGS_S3C2412_MEM
-#define __ASM_ARM_REGS_S3C2412_MEM
-
-#ifndef S3C2412_MEMREG
-#define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
-#endif
-
-#define S3C2412_BANKCFG                 S3C2412_MEMREG(0x00)
-#define S3C2412_BANKCON1                S3C2412_MEMREG(0x04)
-#define S3C2412_BANKCON2                S3C2412_MEMREG(0x08)
-#define S3C2412_BANKCON3                S3C2412_MEMREG(0x0C)
-
-#define S3C2412_REFRESH                 S3C2412_MEMREG(0x10)
-#define S3C2412_TIMEOUT                 S3C2412_MEMREG(0x14)
-
-#endif /*  __ASM_ARM_REGS_S3C2412_MEM */
diff --git a/include/asm-arm/arch-s3c2410/regs-s3c2412.h b/include/asm-arm/arch-s3c2410/regs-s3c2412.h
deleted file mode 100644
index 783b18f5bcea..000000000000
--- a/include/asm-arm/arch-s3c2410/regs-s3c2412.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-s3c2412.h
- *
- * Copyright 2007 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2412 specific register definitions
-*/
-
-#ifndef __ASM_ARCH_REGS_S3C2412_H
-#define __ASM_ARCH_REGS_S3C2412_H "s3c2412"
-
-#define S3C2412_SWRST           (S3C24XX_VA_CLKPWR + 0x30)
-#define S3C2412_SWRST_RESET     (0x533C2412)
-
-/* see regs-power.h for the other registers in the power block. */
-
-#endif  /* __ASM_ARCH_REGS_S3C2412_H */
-
diff --git a/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h b/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h
deleted file mode 100644
index c1414658d1c5..000000000000
--- a/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h
+++ /dev/null
@@ -1,195 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h
- *
- * Copyright (c) 2007 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2443 clock register definitions
-*/
-
-#ifndef __ASM_ARM_REGS_S3C2443_CLOCK
-#define __ASM_ARM_REGS_S3C2443_CLOCK
-
-#define S3C2443_CLKREG(x)               ((x) + S3C24XX_VA_CLKPWR)
-
-#define S3C2443_PLLCON_MDIVSHIFT        16
-#define S3C2443_PLLCON_PDIVSHIFT        8
-#define S3C2443_PLLCON_SDIVSHIFT        0
-#define S3C2443_PLLCON_MDIVMASK         ((1<<(1+(23-16)))-1)
-#define S3C2443_PLLCON_PDIVMASK         ((1<<(1+(9-8)))-1)
-#define S3C2443_PLLCON_SDIVMASK         (3)
-
-#define S3C2443_MPLLCON                 S3C2443_CLKREG(0x10)
-#define S3C2443_EPLLCON                 S3C2443_CLKREG(0x18)
-#define S3C2443_CLKSRC                  S3C2443_CLKREG(0x20)
-#define S3C2443_CLKDIV0                 S3C2443_CLKREG(0x24)
-#define S3C2443_CLKDIV1                 S3C2443_CLKREG(0x28)
-#define S3C2443_HCLKCON                 S3C2443_CLKREG(0x30)
-#define S3C2443_PCLKCON                 S3C2443_CLKREG(0x34)
-#define S3C2443_SCLKCON                 S3C2443_CLKREG(0x38)
-#define S3C2443_PWRMODE                 S3C2443_CLKREG(0x40)
-#define S3C2443_SWRST                   S3C2443_CLKREG(0x44)
-#define S3C2443_BUSPRI0                 S3C2443_CLKREG(0x50)
-#define S3C2443_SYSID                   S3C2443_CLKREG(0x5C)
-#define S3C2443_PWRCFG                  S3C2443_CLKREG(0x60)
-#define S3C2443_RSTCON                  S3C2443_CLKREG(0x64)
-
-#define S3C2443_SWRST_RESET             (0x533c2443)
-
-#define S3C2443_PLLCON_OFF              (1<<24)
-
-#define S3C2443_CLKSRC_I2S_EXT          (1<<14)
-#define S3C2443_CLKSRC_I2S_EPLLDIV      (0<<14)
-#define S3C2443_CLKSRC_I2S_EPLLREF      (2<<14)
-#define S3C2443_CLKSRC_I2S_EPLLREF3     (3<<14)
-#define S3C2443_CLKSRC_I2S_MASK         (3<<14)
-
-#define S3C2443_CLKSRC_EPLLREF_XTAL     (2<<8)
-#define S3C2443_CLKSRC_EPLLREF_EXTCLK   (3<<8)
-#define S3C2443_CLKSRC_EPLLREF_MPLLREF  (0<<8)
-#define S3C2443_CLKSRC_EPLLREF_MPLLREF2 (1<<8)
-#define S3C2443_CLKSRC_EPLLREF_MASK     (3<<8)
-
-#define S3C2443_CLKSRC_ESYSCLK_EPLL     (1<<6)
-#define S3C2443_CLKSRC_MSYSCLK_MPLL     (1<<4)
-#define S3C2443_CLKSRC_EXTCLK_DIV       (1<<3)
-
-#define S3C2443_CLKDIV0_DVS             (1<<13)
-#define S3C2443_CLKDIV0_HALF_HCLK       (1<<3)
-#define S3C2443_CLKDIV0_HALF_PCLK       (1<<2)
-
-#define S3C2443_CLKDIV0_HCLKDIV_MASK    (3<<0)
-
-#define S3C2443_CLKDIV0_EXTDIV_MASK     (3<<6)
-#define S3C2443_CLKDIV0_EXTDIV_SHIFT    (6)
-
-#define S3C2443_CLKDIV0_PREDIV_MASK     (3<<4)
-#define S3C2443_CLKDIV0_PREDIV_SHIFT    (4)
-
-#define S3C2443_CLKDIV0_ARMDIV_MASK     (15<<9)
-#define S3C2443_CLKDIV0_ARMDIV_SHIFT    (9)
-#define S3C2443_CLKDIV0_ARMDIV_1        (0<<9)
-#define S3C2443_CLKDIV0_ARMDIV_2        (8<<9)
-#define S3C2443_CLKDIV0_ARMDIV_3        (2<<9)
-#define S3C2443_CLKDIV0_ARMDIV_4        (9<<9)
-#define S3C2443_CLKDIV0_ARMDIV_6        (10<<9)
-#define S3C2443_CLKDIV0_ARMDIV_8        (11<<9)
-#define S3C2443_CLKDIV0_ARMDIV_12       (13<<9)
-#define S3C2443_CLKDIV0_ARMDIV_16       (15<<9)
-
-/* S3C2443_CLKDIV1 */
-
-#define S3C2443_CLKDIV1_CAMDIV_MASK     (15<<26)
-#define S3C2443_CLKDIV1_CAMDIV_SHIFT    (26)
-
-#define S3C2443_CLKDIV1_HSSPIDIV_MASK   (3<<24)
-#define S3C2443_CLKDIV1_HSSPIDIV_SHIFT  (24)
-
-#define S3C2443_CLKDIV1_DISPDIV_MASK    (0xff<<16)
-#define S3C2443_CLKDIV1_DISPDIV_SHIFT   (16)
-
-#define S3C2443_CLKDIV1_I2SDIV_MASK     (15<<12)
-#define S3C2443_CLKDIV1_I2SDIV_SHIFT    (12)
-
-#define S3C2443_CLKDIV1_UARTDIV_MASK    (15<<8)
-#define S3C2443_CLKDIV1_UARTDIV_SHIFT   (8)
-
-#define S3C2443_CLKDIV1_HSMMCDIV_MASK   (3<<6)
-#define S3C2443_CLKDIV1_HSMMCDIV_SHIFT  (6)
-
-#define S3C2443_CLKDIV1_USBHOSTDIV_MASK (3<<4)
-#define S3C2443_CLKDIV1_USBHOSTDIV_SHIFT (4)
-
-#define S3C2443_CLKCON_NAND
-
-#define S3C2443_HCLKCON_DMA0            (1<<0)
-#define S3C2443_HCLKCON_DMA1            (1<<1)
-#define S3C2443_HCLKCON_DMA2            (1<<2)
-#define S3C2443_HCLKCON_DMA3            (1<<3)
-#define S3C2443_HCLKCON_DMA4            (1<<4)
-#define S3C2443_HCLKCON_DMA5            (1<<5)
-#define S3C2443_HCLKCON_CAMIF           (1<<8)
-#define S3C2443_HCLKCON_DISP            (1<<9)
-#define S3C2443_HCLKCON_LCDC            (1<<10)
-#define S3C2443_HCLKCON_USBH            (1<<11)
-#define S3C2443_HCLKCON_USBD            (1<<12)
-#define S3C2443_HCLKCON_HSMMC           (1<<16)
-#define S3C2443_HCLKCON_CFC             (1<<17)
-#define S3C2443_HCLKCON_SSMC            (1<<18)
-#define S3C2443_HCLKCON_DRAMC           (1<<19)
-
-#define S3C2443_PCLKCON_UART0           (1<<0)
-#define S3C2443_PCLKCON_UART1           (1<<1)
-#define S3C2443_PCLKCON_UART2           (1<<2)
-#define S3C2443_PCLKCON_UART3           (1<<3)
-#define S3C2443_PCLKCON_IIC             (1<<4)
-#define S3C2443_PCLKCON_SDI             (1<<5)
-#define S3C2443_PCLKCON_ADC             (1<<7)
-#define S3C2443_PCLKCON_AC97            (1<<8)
-#define S3C2443_PCLKCON_IIS             (1<<9)
-#define S3C2443_PCLKCON_PWMT            (1<<10)
-#define S3C2443_PCLKCON_WDT             (1<<11)
-#define S3C2443_PCLKCON_RTC             (1<<12)
-#define S3C2443_PCLKCON_GPIO            (1<<13)
-#define S3C2443_PCLKCON_SPI0            (1<<14)
-#define S3C2443_PCLKCON_SPI1            (1<<15)
-
-#define S3C2443_SCLKCON_DDRCLK          (1<<16)
-#define S3C2443_SCLKCON_SSMCCLK         (1<<15)
-#define S3C2443_SCLKCON_HSSPICLK        (1<<14)
-#define S3C2443_SCLKCON_HSMMCCLK_EXT    (1<<13)
-#define S3C2443_SCLKCON_HSMMCCLK_EPLL   (1<<12)
-#define S3C2443_SCLKCON_CAMCLK          (1<<11)
-#define S3C2443_SCLKCON_DISPCLK         (1<<10)
-#define S3C2443_SCLKCON_I2SCLK          (1<<9)
-#define S3C2443_SCLKCON_UARTCLK         (1<<8)
-#define S3C2443_SCLKCON_USBHOST         (1<<1)
-
-#include <asm/div64.h>
-
-static inline unsigned int
-s3c2443_get_mpll(unsigned int pllval, unsigned int baseclk)
-{
-        unsigned int mdiv, pdiv, sdiv;
-        uint64_t fvco;
-
-        mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT;
-        pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT;
-        sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT;
-
-        mdiv &= S3C2443_PLLCON_MDIVMASK;
-        pdiv &= S3C2443_PLLCON_PDIVMASK;
-        sdiv &= S3C2443_PLLCON_SDIVMASK;
-
-        fvco = (uint64_t)baseclk * (2 * (mdiv + 8));
-        do_div(fvco, pdiv << sdiv);
-
-        return (unsigned int)fvco;
-}
-
-static inline unsigned int
-s3c2443_get_epll(unsigned int pllval, unsigned int baseclk)
-{
-        unsigned int mdiv, pdiv, sdiv;
-        uint64_t fvco;
-
-        mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT;
-        pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT;
-        sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT;
-
-        mdiv &= S3C2443_PLLCON_MDIVMASK;
-        pdiv &= S3C2443_PLLCON_PDIVMASK;
-        sdiv &= S3C2443_PLLCON_SDIVMASK;
-
-        fvco = (uint64_t)baseclk * (mdiv + 8);
-        do_div(fvco, (pdiv + 2) << sdiv);
-
-        return (unsigned int)fvco;
-}
-
-#endif /*  __ASM_ARM_REGS_S3C2443_CLOCK */
-
diff --git a/include/asm-arm/arch-s3c2410/regs-sdi.h b/include/asm-arm/arch-s3c2410/regs-sdi.h
deleted file mode 100644
index bfb222fa4abb..000000000000
--- a/include/asm-arm/arch-s3c2410/regs-sdi.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-sdi.h
- *
- * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
- *                    http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 MMC/SDIO register definitions
-*/
-
-#ifndef __ASM_ARM_REGS_SDI
-#define __ASM_ARM_REGS_SDI "regs-sdi.h"
-
-#define S3C2410_SDICON                (0x00)
-#define S3C2410_SDIPRE                (0x04)
-#define S3C2410_SDICMDARG             (0x08)
-#define S3C2410_SDICMDCON             (0x0C)
-#define S3C2410_SDICMDSTAT            (0x10)
-#define S3C2410_SDIRSP0               (0x14)
-#define S3C2410_SDIRSP1               (0x18)
-#define S3C2410_SDIRSP2               (0x1C)
-#define S3C2410_SDIRSP3               (0x20)
-#define S3C2410_SDITIMER              (0x24)
-#define S3C2410_SDIBSIZE              (0x28)
-#define S3C2410_SDIDCON               (0x2C)
-#define S3C2410_SDIDCNT               (0x30)
-#define S3C2410_SDIDSTA               (0x34)
-#define S3C2410_SDIFSTA               (0x38)
-
-#define S3C2410_SDIDATA               (0x3C)
-#define S3C2410_SDIIMSK               (0x40)
-
-#define S3C2440_SDIDATA               (0x40)
-#define S3C2440_SDIIMSK               (0x3C)
-
-#define S3C2440_SDICON_SDRESET        (1<<8)
-#define S3C2440_SDICON_MMCCLOCK       (1<<5)
-#define S3C2410_SDICON_BYTEORDER      (1<<4)
-#define S3C2410_SDICON_SDIOIRQ        (1<<3)
-#define S3C2410_SDICON_RWAITEN        (1<<2)
-#define S3C2410_SDICON_FIFORESET      (1<<1)
-#define S3C2410_SDICON_CLOCKTYPE      (1<<0)
-
-#define S3C2410_SDICMDCON_ABORT       (1<<12)
-#define S3C2410_SDICMDCON_WITHDATA    (1<<11)
-#define S3C2410_SDICMDCON_LONGRSP     (1<<10)
-#define S3C2410_SDICMDCON_WAITRSP     (1<<9)
-#define S3C2410_SDICMDCON_CMDSTART    (1<<8)
-#define S3C2410_SDICMDCON_SENDERHOST  (1<<6)
-#define S3C2410_SDICMDCON_INDEX       (0x3f)
-
-#define S3C2410_SDICMDSTAT_CRCFAIL    (1<<12)
-#define S3C2410_SDICMDSTAT_CMDSENT    (1<<11)
-#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1<<10)
-#define S3C2410_SDICMDSTAT_RSPFIN     (1<<9)
-#define S3C2410_SDICMDSTAT_XFERING    (1<<8)
-#define S3C2410_SDICMDSTAT_INDEX      (0xff)
-
-#define S3C2440_SDIDCON_DS_BYTE       (0<<22)
-#define S3C2440_SDIDCON_DS_HALFWORD   (1<<22)
-#define S3C2440_SDIDCON_DS_WORD       (2<<22)
-#define S3C2410_SDIDCON_IRQPERIOD     (1<<21)
-#define S3C2410_SDIDCON_TXAFTERRESP   (1<<20)
-#define S3C2410_SDIDCON_RXAFTERCMD    (1<<19)
-#define S3C2410_SDIDCON_BUSYAFTERCMD  (1<<18)
-#define S3C2410_SDIDCON_BLOCKMODE     (1<<17)
-#define S3C2410_SDIDCON_WIDEBUS       (1<<16)
-#define S3C2410_SDIDCON_DMAEN         (1<<15)
-#define S3C2410_SDIDCON_STOP          (1<<14)
-#define S3C2440_SDIDCON_DATSTART      (1<<14)
-#define S3C2410_SDIDCON_DATMODE       (3<<12)
-#define S3C2410_SDIDCON_BLKNUM        (0x7ff)
-
-/* constants for S3C2410_SDIDCON_DATMODE */
-#define S3C2410_SDIDCON_XFER_READY    (0<<12)
-#define S3C2410_SDIDCON_XFER_CHKSTART (1<<12)
-#define S3C2410_SDIDCON_XFER_RXSTART  (2<<12)
-#define S3C2410_SDIDCON_XFER_TXSTART  (3<<12)
-
-#define S3C2410_SDIDCON_BLKNUM_MASK   (0xFFF)
-#define S3C2410_SDIDCNT_BLKNUM_SHIFT  (12)
-
-#define S3C2410_SDIDSTA_RDYWAITREQ    (1<<10)
-#define S3C2410_SDIDSTA_SDIOIRQDETECT (1<<9)
-#define S3C2410_SDIDSTA_FIFOFAIL      (1<<8)    /* reserved on 2440 */
-#define S3C2410_SDIDSTA_CRCFAIL       (1<<7)
-#define S3C2410_SDIDSTA_RXCRCFAIL     (1<<6)
-#define S3C2410_SDIDSTA_DATATIMEOUT   (1<<5)
-#define S3C2410_SDIDSTA_XFERFINISH    (1<<4)
-#define S3C2410_SDIDSTA_BUSYFINISH    (1<<3)
-#define S3C2410_SDIDSTA_SBITERR       (1<<2)    /* reserved on 2410a/2440 */
-#define S3C2410_SDIDSTA_TXDATAON      (1<<1)
-#define S3C2410_SDIDSTA_RXDATAON      (1<<0)
-
-#define S3C2440_SDIFSTA_FIFORESET      (1<<16)
-#define S3C2440_SDIFSTA_FIFOFAIL       (3<<14)  /* 3 is correct (2 bits) */
-#define S3C2410_SDIFSTA_TFDET          (1<<13)
-#define S3C2410_SDIFSTA_RFDET          (1<<12)
-#define S3C2410_SDIFSTA_TFHALF         (1<<11)
-#define S3C2410_SDIFSTA_TFEMPTY        (1<<10)
-#define S3C2410_SDIFSTA_RFLAST         (1<<9)
-#define S3C2410_SDIFSTA_RFFULL         (1<<8)
-#define S3C2410_SDIFSTA_RFHALF         (1<<7)
-#define S3C2410_SDIFSTA_COUNTMASK      (0x7f)
-
-#define S3C2410_SDIIMSK_RESPONSECRC    (1<<17)
-#define S3C2410_SDIIMSK_CMDSENT        (1<<16)
-#define S3C2410_SDIIMSK_CMDTIMEOUT     (1<<15)
-#define S3C2410_SDIIMSK_RESPONSEND     (1<<14)
-#define S3C2410_SDIIMSK_READWAIT       (1<<13)
-#define S3C2410_SDIIMSK_SDIOIRQ        (1<<12)
-#define S3C2410_SDIIMSK_FIFOFAIL       (1<<11)
-#define S3C2410_SDIIMSK_CRCSTATUS      (1<<10)
-#define S3C2410_SDIIMSK_DATACRC        (1<<9)
-#define S3C2410_SDIIMSK_DATATIMEOUT    (1<<8)
-#define S3C2410_SDIIMSK_DATAFINISH     (1<<7)
-#define S3C2410_SDIIMSK_BUSYFINISH     (1<<6)
-#define S3C2410_SDIIMSK_SBITERR        (1<<5)   /* reserved 2440/2410a */
-#define S3C2410_SDIIMSK_TXFIFOHALF     (1<<4)
-#define S3C2410_SDIIMSK_TXFIFOEMPTY    (1<<3)
-#define S3C2410_SDIIMSK_RXFIFOLAST     (1<<2)
-#define S3C2410_SDIIMSK_RXFIFOFULL     (1<<1)
-#define S3C2410_SDIIMSK_RXFIFOHALF     (1<<0)
-
-#endif /* __ASM_ARM_REGS_SDI */
diff --git a/include/asm-arm/arch-s3c2410/reset.h b/include/asm-arm/arch-s3c2410/reset.h
deleted file mode 100644
index 4f866cdecab0..000000000000
--- a/include/asm-arm/arch-s3c2410/reset.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/reset.h
- *
- * Copyright (c) 2007 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 CPU reset controls
-*/
-
-#ifndef __ASM_ARCH_RESET_H
-#define __ASM_ARCH_RESET_H __FILE__
-
-/* This allows the over-ride of the default reset code
-*/
-
-extern void (*s3c24xx_reset_hook)(void);
-
-#endif /* __ASM_ARCH_RESET_H */
diff --git a/include/asm-arm/arch-s3c2410/spi-gpio.h b/include/asm-arm/arch-s3c2410/spi-gpio.h
deleted file mode 100644
index 73803731142a..000000000000
--- a/include/asm-arm/arch-s3c2410/spi-gpio.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/spi-gpio.h
- *
- * Copyright (c) 2006 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - SPI Controller platfrom_device info
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_SPIGPIO_H
-#define __ASM_ARCH_SPIGPIO_H __FILE__
-
-struct s3c2410_spigpio_info {
-        unsigned long            pin_clk;
-        unsigned long            pin_mosi;
-        unsigned long            pin_miso;
-
-        int                      bus_num;
-
-        void (*chip_select)(struct s3c2410_spigpio_info *spi, int cs);
-};
-
-
-#endif /* __ASM_ARCH_SPIGPIO_H */
diff --git a/include/asm-arm/arch-s3c2410/spi.h b/include/asm-arm/arch-s3c2410/spi.h
deleted file mode 100644
index 442169887d3b..000000000000
--- a/include/asm-arm/arch-s3c2410/spi.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/spi.h
- *
- * Copyright (c) 2006 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - SPI Controller platform_device info
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_SPI_H
-#define __ASM_ARCH_SPI_H __FILE__
-
-struct s3c2410_spi_info {
-        unsigned long            pin_cs;        /* simple gpio cs */
-        unsigned int             num_cs;        /* total chipselects */
-        int                      bus_num;       /* bus number to use. */
-
-        void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol);
-};
-
-
-#endif /* __ASM_ARCH_SPI_H */
diff --git a/include/asm-arm/arch-s3c2410/system-reset.h b/include/asm-arm/arch-s3c2410/system-reset.h
deleted file mode 100644
index beeec770dcf7..000000000000
--- a/include/asm-arm/arch-s3c2410/system-reset.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/system-reset.h
- *
- * Copyright (c) 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - System define for arch_reset() function
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-
-#include <asm/plat-s3c/regs-watchdog.h>
-#include <asm/arch/regs-clock.h>
-
-#include <linux/clk.h>
-#include <linux/err.h>
-
-extern void (*s3c24xx_reset_hook)(void);
-
-static void
-arch_reset(char mode)
-{
-        struct clk *wdtclk;
-
-        if (mode == 's') {
-                cpu_reset(0);
-        }
-
-        if (s3c24xx_reset_hook)
-                s3c24xx_reset_hook();
-
-        printk("arch_reset: attempting watchdog reset\n");
-
-        __raw_writel(0, S3C2410_WTCON);   /* disable watchdog, to be safe  */
-
-        wdtclk = clk_get(NULL, "watchdog");
-        if (!IS_ERR(wdtclk)) {
-                clk_enable(wdtclk);
-        } else
-                printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
-
-        /* put initial values into count and data */
-        __raw_writel(0x80, S3C2410_WTCNT);
-        __raw_writel(0x80, S3C2410_WTDAT);
-
-        /* set the watchdog to go and reset... */
-        __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
-                     S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON);
-
-        /* wait for reset to assert... */
-        mdelay(500);
-
-        printk(KERN_ERR "Watchdog reset failed to assert reset\n");
-
-        /* delay to allow the serial port to show the message */
-        mdelay(50);
-
-        /* we'll take a jump through zero as a poor second */
-        cpu_reset(0);
-}
diff --git a/include/asm-arm/arch-s3c2410/system.h b/include/asm-arm/arch-s3c2410/system.h
deleted file mode 100644
index 98f690e7d33e..000000000000
--- a/include/asm-arm/arch-s3c2410/system.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/system.h
- *
- * Copyright (c) 2003 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - System function defines and includes
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-
-#include <asm/arch/map.h>
-#include <asm/arch/idle.h>
-#include <asm/arch/reset.h>
-
-#include <asm/arch/regs-clock.h>
-
-void (*s3c24xx_idle)(void);
-void (*s3c24xx_reset_hook)(void);
-
-void s3c24xx_default_idle(void)
-{
-        unsigned long tmp;
-        int i;
-
-        /* idle the system by using the idle mode which will wait for an
-         * interrupt to happen before restarting the system.
-         */
-
-        /* Warning: going into idle state upsets jtag scanning */
-
-        __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
-                     S3C2410_CLKCON);
-
-        /* the samsung port seems to do a loop and then unset idle.. */
-        for (i = 0; i < 50; i++) {
-                tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
-        }
-
-        /* this bit is not cleared on re-start... */
-
-        __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
-                     S3C2410_CLKCON);
-}
-
-static void arch_idle(void)
-{
-        if (s3c24xx_idle != NULL)
-                (s3c24xx_idle)();
-        else
-                s3c24xx_default_idle();
-}
-
-#include <asm/arch/system-reset.h>
diff --git a/include/asm-arm/arch-s3c2410/timex.h b/include/asm-arm/arch-s3c2410/timex.h
deleted file mode 100644
index c16a99c5a59a..000000000000
--- a/include/asm-arm/arch-s3c2410/timex.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/timex.h
- *
- * Copyright (c) 2003-2005 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - time parameters
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_TIMEX_H
-#define __ASM_ARCH_TIMEX_H
-
-/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
- * a variable is useless. It seems as long as we make our timers an
- * exact multiple of HZ, any value that makes a 1->1 correspondence
- * for the time conversion functions to/from jiffies is acceptable.
-*/
-
-
-#define CLOCK_TICK_RATE 12000000
-
-
-#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/include/asm-arm/arch-s3c2410/uncompress.h b/include/asm-arm/arch-s3c2410/uncompress.h
deleted file mode 100644
index 48a5731ee988..000000000000
--- a/include/asm-arm/arch-s3c2410/uncompress.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/uncompress.h
- *
- * Copyright (c) 2003, 2007 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - uncompress code
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/map.h>
-
-/* working in physical space... */
-#undef S3C2410_GPIOREG
-#define S3C2410_GPIOREG(x) ((S3C24XX_PA_GPIO + (x)))
-
-#include <asm/plat-s3c/uncompress.h>
-
-static inline int is_arm926(void)
-{
-        unsigned int cpuid;
-
-        asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (cpuid));
-
-        return ((cpuid & 0xff0) == 0x260);
-}
-
-static void arch_detect_cpu(void)
-{
-        unsigned int cpuid;
-
-        cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1);
-        cpuid &= S3C2410_GSTATUS1_IDMASK;
-
-        if (is_arm926() || cpuid == S3C2410_GSTATUS1_2440 ||
-            cpuid == S3C2410_GSTATUS1_2442) {
-                fifo_mask = S3C2440_UFSTAT_TXMASK;
-                fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
-        } else {
-                fifo_mask = S3C2410_UFSTAT_TXMASK;
-                fifo_max = 15 << S3C2410_UFSTAT_TXSHIFT;
-        }
-}
-
-#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/include/asm-arm/arch-s3c2410/usb-control.h b/include/asm-arm/arch-s3c2410/usb-control.h
deleted file mode 100644
index 5bfa376e33dc..000000000000
--- a/include/asm-arm/arch-s3c2410/usb-control.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/usb-control.h
- *
- * Copyright (c) 2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - usb port information
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_USBCONTROL_H
-#define __ASM_ARCH_USBCONTROL_H "include/asm-arm/arch-s3c2410/usb-control.h"
-
-#define S3C_HCDFLG_USED (1)
-
-struct s3c2410_hcd_port {
-        unsigned char   flags;
-        unsigned char   power;
-        unsigned char   oc_status;
-        unsigned char   oc_changed;
-};
-
-struct s3c2410_hcd_info {
-        struct usb_hcd          *hcd;
-        struct s3c2410_hcd_port port[2];
-
-        void            (*power_control)(int port, int to);
-        void            (*enable_oc)(struct s3c2410_hcd_info *, int on);
-        void            (*report_oc)(struct s3c2410_hcd_info *, int ports);
-};
-
-static void inline s3c2410_usb_report_oc(struct s3c2410_hcd_info *info, int ports)
-{
-        if (info->report_oc != NULL) {
-                (info->report_oc)(info, ports);
-        }
-}
-
-#endif /*__ASM_ARCH_USBCONTROL_H */
diff --git a/include/asm-arm/arch-s3c2410/vmalloc.h b/include/asm-arm/arch-s3c2410/vmalloc.h
deleted file mode 100644
index 0ae3bdb7e03b..000000000000
--- a/include/asm-arm/arch-s3c2410/vmalloc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/vmalloc.h
- *
- * from linux/include/asm-arm/arch-iop3xx/vmalloc.h
- *
- * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
- *                    http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 vmalloc definition
-*/
-
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H
-
-#define VMALLOC_END       (0xE0000000)
-
-#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/include/asm-arm/arch-s3c2410/vr1000-cpld.h b/include/asm-arm/arch-s3c2410/vr1000-cpld.h
deleted file mode 100644
index 0557b0a5ab1d..000000000000
--- a/include/asm-arm/arch-s3c2410/vr1000-cpld.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/vr1000-cpld.h
- *
- * Copyright (c) 2003 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * VR1000 - CPLD control constants
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_VR1000CPLD_H
-#define __ASM_ARCH_VR1000CPLD_H
-
-#define VR1000_CPLD_CTRL2_RAMWEN     (0x04)   /* SRAM Write Enable */
-
-#endif /* __ASM_ARCH_VR1000CPLD_H */
diff --git a/include/asm-arm/arch-s3c2410/vr1000-irq.h b/include/asm-arm/arch-s3c2410/vr1000-irq.h
deleted file mode 100644
index 890937083c61..000000000000
--- a/include/asm-arm/arch-s3c2410/vr1000-irq.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/vr1000-irq.h
- *
- * Copyright (c) 2003,2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Machine VR1000 - IRQ Number definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_VR1000IRQ_H
-#define __ASM_ARCH_VR1000IRQ_H
-
-/* irq numbers to onboard peripherals */
-
-#define IRQ_USBOC            IRQ_EINT19
-#define IRQ_IDE0             IRQ_EINT16
-#define IRQ_IDE1             IRQ_EINT17
-#define IRQ_VR1000_SERIAL    IRQ_EINT12
-#define IRQ_VR1000_DM9000A   IRQ_EINT10
-#define IRQ_VR1000_DM9000N   IRQ_EINT9
-#define IRQ_SMALERT          IRQ_EINT8
-
-#endif /* __ASM_ARCH_VR1000IRQ_H */
diff --git a/include/asm-arm/arch-s3c2410/vr1000-map.h b/include/asm-arm/arch-s3c2410/vr1000-map.h
deleted file mode 100644
index 92a56a724a8c..000000000000
--- a/include/asm-arm/arch-s3c2410/vr1000-map.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/vr1000-map.h
- *
- * Copyright (c) 2003-2005 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Machine VR1000 - Memory map definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* needs arch/map.h including with this */
-
-/* ok, we've used up to 0x13000000, now we need to find space for the
- * peripherals that live in the nGCS[x] areas, which are quite numerous
- * in their space. We also have the board's CPLD to find register space
- * for.
- */
-
-#ifndef __ASM_ARCH_VR1000MAP_H
-#define __ASM_ARCH_VR1000MAP_H
-
-#include <asm/arch/bast-map.h>
-
-#define VR1000_IOADDR(x) BAST_IOADDR(x)
-
-/* we put the CPLD registers next, to get them out of the way */
-
-#define VR1000_VA_CTRL1     VR1000_IOADDR(0x00000000)    /* 0x01300000 */
-#define VR1000_PA_CTRL1     (S3C2410_CS5 | 0x7800000)
-
-#define VR1000_VA_CTRL2     VR1000_IOADDR(0x00100000)    /* 0x01400000 */
-#define VR1000_PA_CTRL2     (S3C2410_CS1 | 0x6000000)
-
-#define VR1000_VA_CTRL3     VR1000_IOADDR(0x00200000)    /* 0x01500000 */
-#define VR1000_PA_CTRL3     (S3C2410_CS1 | 0x6800000)
-
-#define VR1000_VA_CTRL4     VR1000_IOADDR(0x00300000)    /* 0x01600000 */
-#define VR1000_PA_CTRL4     (S3C2410_CS1 | 0x7000000)
-
-/* next, we have the PC104 ISA interrupt registers */
-
-#define VR1000_PA_PC104_IRQREQ  (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
-#define VR1000_VA_PC104_IRQREQ  VR1000_IOADDR(0x00400000)
-
-#define VR1000_PA_PC104_IRQRAW  (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
-#define VR1000_VA_PC104_IRQRAW  VR1000_IOADDR(0x00500000)
-
-#define VR1000_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
-#define VR1000_VA_PC104_IRQMASK VR1000_IOADDR(0x00600000)
-
-/* 0xE0000000 contains the IO space that is split by speed and
- * wether the access is for 8 or 16bit IO... this ensures that
- * the correct access is made
- *
- * 0x10000000 of space, partitioned as so:
- *
- * 0x00000000 to 0x04000000  8bit,  slow
- * 0x04000000 to 0x08000000  16bit, slow
- * 0x08000000 to 0x0C000000  16bit, net
- * 0x0C000000 to 0x10000000  16bit, fast
- *
- * each of these spaces has the following in:
- *
- * 0x02000000 to 0x02100000 1MB  IDE primary channel
- * 0x02100000 to 0x02200000 1MB  IDE primary channel aux
- * 0x02200000 to 0x02400000 1MB  IDE secondary channel
- * 0x02300000 to 0x02400000 1MB  IDE secondary channel aux
- * 0x02500000 to 0x02600000 1MB  Davicom DM9000 ethernet controllers
- * 0x02600000 to 0x02700000 1MB
- *
- * the phyiscal layout of the zones are:
- *  nGCS2 - 8bit, slow
- *  nGCS3 - 16bit, slow
- *  nGCS4 - 16bit, net
- *  nGCS5 - 16bit, fast
- */
-
-#define VR1000_VA_MULTISPACE (0xE0000000)
-
-#define VR1000_VA_ISAIO            (VR1000_VA_MULTISPACE + 0x00000000)
-#define VR1000_VA_ISAMEM           (VR1000_VA_MULTISPACE + 0x01000000)
-#define VR1000_VA_IDEPRI           (VR1000_VA_MULTISPACE + 0x02000000)
-#define VR1000_VA_IDEPRIAUX        (VR1000_VA_MULTISPACE + 0x02100000)
-#define VR1000_VA_IDESEC           (VR1000_VA_MULTISPACE + 0x02200000)
-#define VR1000_VA_IDESECAUX        (VR1000_VA_MULTISPACE + 0x02300000)
-#define VR1000_VA_ASIXNET          (VR1000_VA_MULTISPACE + 0x02400000)
-#define VR1000_VA_DM9000           (VR1000_VA_MULTISPACE + 0x02500000)
-#define VR1000_VA_SUPERIO          (VR1000_VA_MULTISPACE + 0x02600000)
-
-/* physical offset addresses for the peripherals */
-
-#define VR1000_PA_IDEPRI           (0x02000000)
-#define VR1000_PA_IDEPRIAUX        (0x02800000)
-#define VR1000_PA_IDESEC           (0x03000000)
-#define VR1000_PA_IDESECAUX        (0x03800000)
-#define VR1000_PA_DM9000           (0x05000000)
-
-#define VR1000_PA_SERIAL           (0x11800000)
-#define VR1000_VA_SERIAL           (VR1000_IOADDR(0x00700000))
-
-/* VR1000 ram is in CS1, with A26..A24 = 2_101 */
-#define VR1000_PA_SRAM             (S3C2410_CS1 | 0x05000000)
-
-/* some configurations for the peripherals */
-
-#define VR1000_DM9000_CS         VR1000_VAM_CS4
-
-#endif /* __ASM_ARCH_VR1000MAP_H */
diff --git a/include/asm-arm/arch-sa1100/SA-1101.h b/include/asm-arm/arch-sa1100/SA-1101.h
deleted file mode 100644
index 65ca8c79e6d2..000000000000
--- a/include/asm-arm/arch-sa1100/SA-1101.h
+++ /dev/null
@@ -1,925 +0,0 @@
-/*
- * SA-1101.h
- *
- * Copyright (c) Peter Danielsson 1999
- *
- * Definition of constants related to the sa1101
- * support chip for the sa1100
- *
- */
-
-
-/* Be sure that virtual mapping is defined right */
-#ifndef __ASM_ARCH_HARDWARE_H
-#error You must include hardware.h not SA-1101.h
-#endif
-
-#ifndef SA1101_BASE
-#error You must define SA-1101 physical base address
-#endif
-
-#ifndef LANGUAGE
-# ifdef __ASSEMBLY__
-#  define LANGUAGE Assembly
-# else
-#  define LANGUAGE C
-# endif
-#endif
-
-/*
- * We have mapped the sa1101 depending on the value of SA1101_BASE.
- * It then appears from 0xf4000000.
- */
-
-#define SA1101_p2v( x )         ((x) - SA1101_BASE + 0xf4000000)
-#define SA1101_v2p( x )         ((x) - 0xf4000000  + SA1101_BASE)
-
-#ifndef SA1101_p2v
-#define SA1101_p2v(PhAdd)  (PhAdd)
-#endif
-
-#include <asm/arch/bitfield.h>
-
-#define C               0
-#define Assembly        1
-
-
-/*
- * Memory map
- */
-
-#define __SHMEM_CONTROL0        0x00000000
-#define __SYSTEM_CONTROL1       0x00000400
-#define __ARBITER               0x00020000
-#define __SYSTEM_CONTROL2       0x00040000
-#define __SYSTEM_CONTROL3       0x00060000
-#define __PARALLEL_PORT         0x00080000
-#define __VIDMEM_CONTROL        0x00100000
-#define __UPDATE_FIFO           0x00120000
-#define __SHMEM_CONTROL1        0x00140000
-#define __INTERRUPT_CONTROL     0x00160000
-#define __USB_CONTROL           0x00180000
-#define __TRACK_INTERFACE       0x001a0000
-#define __MOUSE_INTERFACE       0x001b0000
-#define __KEYPAD_INTERFACE      0x001c0000
-#define __PCMCIA_INTERFACE      0x001e0000
-#define __VGA_CONTROL           0x00200000
-#define __GPIO_INTERFACE        0x00300000
-
-/*
- * Macro that calculates real address for registers in the SA-1101
- */
-
-#define _SA1101( x )    ((x) + SA1101_BASE)
-
-/*
- * Interface and shared memory controller registers
- *
- * Registers
- *      SKCR            SA-1101 control register (read/write)
- *      SMCR            Shared Memory Controller Register
- *      SNPR            Snoop Register
- */
-
-#define _SKCR           _SA1101( 0x00000000 ) /* SA-1101 Control Reg. */
-#define _SMCR           _SA1101( 0x00140000 ) /* Shared Mem. Control Reg. */
-#define _SNPR           _SA1101( 0x00140400 ) /* Snoop Reg. */
-
-#if LANGUAGE == C
-#define SKCR            (*((volatile Word *) SA1101_p2v (_SKCR)))
-#define SMCR            (*((volatile Word *) SA1101_p2v (_SMCR)))
-#define SNPR            (*((volatile Word *) SA1101_p2v (_SNPR)))
-
-#define SKCR_PLLEn        0x0001          /* Enable On-Chip PLL */
-#define SKCR_BCLKEn       0x0002          /* Enables BCLK */
-#define SKCR_Sleep        0x0004          /* Sleep Mode */
-#define SKCR_IRefEn       0x0008          /* DAC Iref input enable */
-#define SKCR_VCOON        0x0010          /* VCO bias */
-#define SKCR_ScanTestEn   0x0020          /* Enables scan test */
-#define SKCR_ClockTestEn  0x0040          /* Enables clock test */
-
-#define SMCR_DCAC         Fld(2,0)        /* Number of column address bits */
-#define SMCR_DRAC         Fld(2,2)        /* Number of row address bits */
-#define SMCR_ArbiterBias  0x0008          /* favor video or USB */
-#define SMCR_TopVidMem    Fld(4,5)        /* Top 4 bits of vidmem addr. */
-
-#define SMCR_ColAdrBits( x )              /* col. addr bits 8..11 */ \
-        (( (x) - 8 ) << FShft (SMCR_DCAC))
-#define SMCR_RowAdrBits( x )              /* row addr bits 9..12 */\
-        (( (x) - 9 ) << FShft (SMCR_DRAC))
-
-#define SNPR_VFBstart     Fld(12,0)     /* Video frame buffer addr */
-#define SNPR_VFBsize      Fld(11,12)    /* Video frame buffer size */
-#define SNPR_WholeBank    (1 << 23)     /* Whole bank bit */
-#define SNPR_BankSelect   Fld(2,27)     /* Bank select */
-#define SNPR_SnoopEn      (1 << 31)     /* Enable snoop operation */
-
-#define SNPR_Set_VFBsize( x )   /* set frame buffer size (in kb) */ \
-        ( (x) << FShft (SNPR_VFBsize))
-#define SNPR_Select_Bank(x)     /* select bank 0 or 1 */  \
-        (( (x) + 1 ) << FShft (SNPR_BankSelect ))
-
-#endif /* LANGUAGE == C */
-
-/*
- * Video Memory Controller
- *
- * Registers
- *    VMCCR     Configuration register
- *    VMCAR     VMC address register
- *    VMCDR     VMC data register
- *
- */
-
-#define _VMCCR          _SA1101( 0x00100000 )   /* Configuration register */
-#define _VMCAR          _SA1101( 0x00101000 )   /* VMC address register */
-#define _VMCDR          _SA1101( 0x00101400 )   /* VMC data register */
-
-#if LANGUAGE == C
-#define VMCCR           (*((volatile Word *) SA1101_p2v (_VMCCR)))
-#define VMCAR           (*((volatile Word *) SA1101_p2v (_VMCAR)))
-#define VMCDR           (*((volatile Word *) SA1101_p2v (_VMCDR)))
-
-#define VMCCR_RefreshEn     0x0000        /* Enable memory refresh */
-#define VMCCR_Config        0x0001        /* DRAM size */
-#define VMCCR_RefPeriod     Fld(2,3)      /* Refresh period */
-#define VMCCR_StaleDataWait Fld(4,5)      /* Stale FIFO data timeout counter */
-#define VMCCR_SleepState    (1<<9)        /* State of interface pins in sleep*/
-#define VMCCR_RefTest       (1<<10)       /* refresh test */
-#define VMCCR_RefLow        Fld(6,11)     /* refresh low counter */
-#define VMCCR_RefHigh       Fld(7,17)     /* refresh high counter */
-#define VMCCR_SDTCTest      Fld(7,24)     /* stale data timeout counter */
-#define VMCCR_ForceSelfRef  (1<<31)       /* Force self refresh */
-
-#endif LANGUAGE == C
-
-
-/* Update FIFO
- *
- * Registers
- *    UFCR      Update FIFO Control Register
- *    UFSR      Update FIFO Status Register
- *    UFLVLR    update FIFO level register
- *    UFDR      update FIFO data register
- */
-
-#define _UFCR   _SA1101(0x00120000)   /* Update FIFO Control Reg. */
-#define _UFSR   _SA1101(0x00120400)   /* Update FIFO Status Reg. */     
-#define _UFLVLR _SA1101(0x00120800)   /* Update FIFO level reg. */
-#define _UFDR   _SA1101(0x00120c00)   /* Update FIFO data reg. */
-
-#if LANGUAGE == C
-
-#define UFCR    (*((volatile Word *) SA1101_p2v (_UFCR)))
-#define UFSR    (*((volatile Word *) SA1101_p2v (_UFSR)))
-#define UFLVLR  (*((volatile Word *) SA1101_p2v (_UFLVLR))) 
-#define UFDR    (*((volatile Word *) SA1101_p2v (_UFDR)))
-
-
-#define UFCR_FifoThreshhold     Fld(7,0)        /* Level for FifoGTn flag */
-
-#define UFSR_FifoGTnFlag        0x01            /* FifoGTn flag */#define UFSR_FifoEmpty                0x80            /* FIFO is empty */
-
-#endif /* LANGUAGE == C */
-
-/* System Controller
- *
- * Registers
- *    SKPCR     Power Control Register
- *    SKCDR     Clock Divider Register
- *    DACDR1    DAC1 Data register
- *    DACDR2    DAC2 Data register
- */
-
-#define _SKPCR          _SA1101(0x00000400)
-#define _SKCDR          _SA1101(0x00040000)
-#define _DACDR1         _SA1101(0x00060000)
-#define _DACDR2         _SA1101(0x00060400)
-
-#if LANGUAGE == C
-#define SKPCR   (*((volatile Word *) SA1101_p2v (_SKPCR)))
-#define SKCDR   (*((volatile Word *) SA1101_p2v (_SKCDR)))
-#define DACDR1  (*((volatile Word *) SA1101_p2v (_DACDR1)))
-#define DACDR2  (*((volatile Word *) SA1101_p2v (_DACDR2)))
-
-#define SKPCR_UCLKEn         0x01    /* USB Enable */
-#define SKPCR_PCLKEn         0x02    /* PS/2 Enable */
-#define SKPCR_ICLKEn         0x04    /* Interrupt Controller Enable */
-#define SKPCR_VCLKEn         0x08    /* Video Controller Enable */
-#define SKPCR_PICLKEn        0x10    /* parallel port Enable */
-#define SKPCR_DCLKEn         0x20    /* DACs Enable */
-#define SKPCR_nKPADEn        0x40    /* Multiplexer */
-
-#define SKCDR_PLLMul         Fld(7,0)   /* PLL Multiplier */
-#define SKCDR_VCLKEn         Fld(2,7)   /* Video controller clock divider */
-#define SKDCR_BCLKEn         (1<<9)     /* BCLK Divider */
-#define SKDCR_UTESTCLKEn     (1<<10)    /* Route USB clock during test mode */
-#define SKDCR_DivRValue      Fld(6,11)  /* Input clock divider for PLL */
-#define SKDCR_DivNValue      Fld(5,17)  /* Output clock divider for PLL */
-#define SKDCR_PLLRSH         Fld(3,22)  /* PLL bandwidth control */
-#define SKDCR_ChargePump     (1<<25)    /* Charge pump control */
-#define SKDCR_ClkTestMode    (1<<26)    /* Clock output test mode */
-#define SKDCR_ClkTestEn      (1<<27)    /* Test clock generator */
-#define SKDCR_ClkJitterCntl  Fld(3,28)  /* video clock jitter compensation */
-
-#define DACDR_DACCount       Fld(8,0)   /* Count value */
-#define DACDR1_DACCount      DACDR_DACCount
-#define DACDR2_DACCount      DACDR_DACCount
-
-#endif /* LANGUAGE == C */
-
-/*
- * Parallel Port Interface
- *
- * Registers
- *    IEEE_Config       IEEE mode selection and programmable attributes
- *    IEEE_Control      Controls the states of IEEE port control outputs
- *    IEEE_Data         Forward transfer data register
- *    IEEE_Addr         Forward transfer address register
- *    IEEE_Status       Port IO signal status register
- *    IEEE_IntStatus    Port interrupts status register
- *    IEEE_FifoLevels   Rx and Tx FIFO interrupt generation levels
- *    IEEE_InitTime     Forward timeout counter initial value
- *    IEEE_TimerStatus  Forward timeout counter current value
- *    IEEE_FifoReset    Reset forward transfer FIFO
- *    IEEE_ReloadValue  Counter reload value
- *    IEEE_TestControl  Control testmode
- *    IEEE_TestDataIn   Test data register
- *    IEEE_TestDataInEn Enable test data
- *    IEEE_TestCtrlIn   Test control signals
- *    IEEE_TestCtrlInEn Enable test control signals
- *    IEEE_TestDataStat Current data bus value
- *
- */
-
-/*
- * The control registers are defined as offsets from a base address 
- */
- 
-#define _IEEE( x ) _SA1101( (x) + __PARALLEL_PORT )
-
-#define _IEEE_Config        _IEEE( 0x0000 )
-#define _IEEE_Control       _IEEE( 0x0400 )
-#define _IEEE_Data          _IEEE( 0x4000 )
-#define _IEEE_Addr          _IEEE( 0x0800 )
-#define _IEEE_Status        _IEEE( 0x0c00 )
-#define _IEEE_IntStatus     _IEEE( 0x1000 )
-#define _IEEE_FifoLevels    _IEEE( 0x1400 )
-#define _IEEE_InitTime      _IEEE( 0x1800 )
-#define _IEEE_TimerStatus   _IEEE( 0x1c00 )
-#define _IEEE_FifoReset     _IEEE( 0x2000 )
-#define _IEEE_ReloadValue   _IEEE( 0x3c00 )
-#define _IEEE_TestControl   _IEEE( 0x2400 )
-#define _IEEE_TestDataIn    _IEEE( 0x2800 )
-#define _IEEE_TestDataInEn  _IEEE( 0x2c00 )
-#define _IEEE_TestCtrlIn    _IEEE( 0x3000 )
-#define _IEEE_TestCtrlInEn  _IEEE( 0x3400 )
-#define _IEEE_TestDataStat  _IEEE( 0x3800 )
- 
-
-#if LANGUAGE == C
-#define IEEE_Config         (*((volatile Word *) SA1101_p2v (_IEEE_Config)))
-#define IEEE_Control        (*((volatile Word *) SA1101_p2v (_IEEE_Control)))
-#define IEEE_Data           (*((volatile Word *) SA1101_p2v (_IEEE_Data)))
-#define IEEE_Addr           (*((volatile Word *) SA1101_p2v (_IEEE_Addr)))
-#define IEEE_Status         (*((volatile Word *) SA1101_p2v (_IEEE_Status)))
-#define IEEE_IntStatus      (*((volatile Word *) SA1101_p2v (_IEEE_IntStatus)))
-#define IEEE_FifoLevels     (*((volatile Word *) SA1101_p2v (_IEEE_FifoLevels)))
-#define IEEE_InitTime       (*((volatile Word *) SA1101_p2v (_IEEE_InitTime)))
-#define IEEE_TimerStatus    (*((volatile Word *) SA1101_p2v (_IEEE_TimerStatus)))
-#define IEEE_FifoReset      (*((volatile Word *) SA1101_p2v (_IEEE_FifoReset)))
-#define IEEE_ReloadValue    (*((volatile Word *) SA1101_p2v (_IEEE_ReloadValue)))
-#define IEEE_TestControl    (*((volatile Word *) SA1101_p2v (_IEEE_TestControl)))
-#define IEEE_TestDataIn     (*((volatile Word *) SA1101_p2v (_IEEE_TestDataIn)))
-#define IEEE_TestDataInEn   (*((volatile Word *) SA1101_p2v (_IEEE_TestDataInEn)))
-#define IEEE_TestCtrlIn     (*((volatile Word *) SA1101_p2v (_IEEE_TestCtrlIn)))
-#define IEEE_TestCtrlInEn   (*((volatile Word *) SA1101_p2v (_IEEE_TestCtrlInEn)))
-#define IEEE_TestDataStat   (*((volatile Word *) SA1101_p2v (_IEEE_TestDataStat)))
-
-
-#define IEEE_Config_M       Fld(3,0)     /* Mode select */
-#define IEEE_Config_D       0x04         /* FIFO access enable */
-#define IEEE_Config_B       0x08         /* 9-bit word enable */
-#define IEEE_Config_T       0x10         /* Data transfer enable */
-#define IEEE_Config_A       0x20         /* Data transfer direction */
-#define IEEE_Config_E       0x40         /* Timer enable */
-#define IEEE_Control_A      0x08         /* AutoFd output */
-#define IEEE_Control_E      0x04         /* Selectin output */
-#define IEEE_Control_T      0x02         /* Strobe output */
-#define IEEE_Control_I      0x01         /* Port init output */
-#define IEEE_Data_C         (1<<31)      /* Byte count */
-#define IEEE_Data_Db        Fld(9,16)    /* Data byte 2 */
-#define IEEE_Data_Da        Fld(9,0)     /* Data byte 1 */
-#define IEEE_Addr_A         Fld(8,0)     /* forward address transfer byte */
-#define IEEE_Status_A       0x0100       /* nAutoFd port output status */
-#define IEEE_Status_E       0x0080       /* nSelectIn port output status */
-#define IEEE_Status_T       0x0040       /* nStrobe port output status */
-#define IEEE_Status_I       0x0020       /* nInit port output status */
-#define IEEE_Status_B       0x0010       /* Busy port inout status */
-#define IEEE_Status_S       0x0008       /* Select port input status */
-#define IEEE_Status_K       0x0004       /* nAck port input status */
-#define IEEE_Status_F       0x0002       /* nFault port input status */
-#define IEEE_Status_R       0x0001       /* pError port input status */
-
-#define IEEE_IntStatus_IntReqDat         0x0100
-#define IEEE_IntStatus_IntReqEmp         0x0080
-#define IEEE_IntStatus_IntReqInt         0x0040
-#define IEEE_IntStatus_IntReqRav         0x0020
-#define IEEE_IntStatus_IntReqTim         0x0010
-#define IEEE_IntStatus_RevAddrComp       0x0008
-#define IEEE_IntStatus_RevDataComp       0x0004
-#define IEEE_IntStatus_FwdAddrComp       0x0002
-#define IEEE_IntStatus_FwdDataComp       0x0001
-#define IEEE_FifoLevels_RevFifoLevel     2
-#define IEEE_FifoLevels_FwdFifoLevel     1
-#define IEEE_InitTime_TimValInit         Fld(22,0)
-#define IEEE_TimerStatus_TimValStat      Fld(22,0)
-#define IEEE_ReloadValue_Reload          Fld(4,0)
-
-#define IEEE_TestControl_RegClk          0x04
-#define IEEE_TestControl_ClockSelect     Fld(2,1)
-#define IEEE_TestControl_TimerTestModeEn 0x01
-#define IEEE_TestCtrlIn_PError           0x10
-#define IEEE_TestCtrlIn_nFault           0x08
-#define IEEE_TestCtrlIn_nAck             0x04
-#define IEEE_TestCtrlIn_PSel             0x02
-#define IEEE_TestCtrlIn_Busy             0x01
-
-#endif /* LANGUAGE == C */
-
-/*
- * VGA Controller
- *
- * Registers
- *    VideoControl      Video Control Register
- *    VgaTiming0        VGA Timing Register 0
- *    VgaTiming1        VGA Timing Register 1
- *    VgaTiming2        VGA Timing Register 2
- *    VgaTiming3        VGA Timing Register 3
- *    VgaBorder         VGA Border Color Register
- *    VgaDBAR           VGADMA Base Address Register
- *    VgaDCAR           VGADMA Channel Current Address Register
- *    VgaStatus         VGA Status Register
- *    VgaInterruptMask  VGA Interrupt Mask Register
- *    VgaPalette        VGA Palette Registers
- *    DacControl        DAC Control Register
- *    VgaTest           VGA Controller Test Register
- */
-
-#define _VGA( x )       _SA1101( ( x ) + __VGA_CONTROL )
-
-#define _VideoControl       _VGA( 0x0000 )
-#define _VgaTiming0         _VGA( 0x0400 )
-#define _VgaTiming1         _VGA( 0x0800 )
-#define _VgaTiming2         _VGA( 0x0c00 )
-#define _VgaTiming3         _VGA( 0x1000 )
-#define _VgaBorder          _VGA( 0x1400 )
-#define _VgaDBAR            _VGA( 0x1800 )
-#define _VgaDCAR            _VGA( 0x1c00 )
-#define _VgaStatus          _VGA( 0x2000 )
-#define _VgaInterruptMask   _VGA( 0x2400 )
-#define _VgaPalette         _VGA( 0x40000 )
-#define _DacControl         _VGA( 0x3000 )
-#define _VgaTest            _VGA( 0x2c00 )
-
-#if (LANGUAGE == C)
-#define VideoControl   (*((volatile Word *) SA1101_p2v (_VideoControl)))
-#define VgaTiming0     (*((volatile Word *) SA1101_p2v (_VgaTiming0)))
-#define VgaTiming1     (*((volatile Word *) SA1101_p2v (_VgaTiming1)))
-#define VgaTiming2     (*((volatile Word *) SA1101_p2v (_VgaTiming2)))
-#define VgaTiming3     (*((volatile Word *) SA1101_p2v (_VgaTiming3)))
-#define VgaBorder      (*((volatile Word *) SA1101_p2v (_VgaBorder)))
-#define VgaDBAR        (*((volatile Word *) SA1101_p2v (_VgaDBAR)))
-#define VgaDCAR        (*((volatile Word *) SA1101_p2v (_VgaDCAR)))
-#define VgaStatus      (*((volatile Word *) SA1101_p2v (_VgaStatus)))
-#define VgaInterruptMask (*((volatile Word *) SA1101_p2v (_VgaInterruptMask)))
-#define VgaPalette     (*((volatile Word *) SA1101_p2v (_VgaPalette)))
-#define DacControl     (*((volatile Word *) SA1101_p2v (_DacControl)))
-#define VgaTest        (*((volatile Word *) SA1101_p2v (_VgaTest)))
-
-#define VideoControl_VgaEn    0x00000000
-#define VideoControl_BGR      0x00000001
-#define VideoControl_VCompVal Fld(2,2)
-#define VideoControl_VgaReq   Fld(4,4)
-#define VideoControl_VBurstL  Fld(4,8)
-#define VideoControl_VMode    (1<<12)
-#define VideoControl_PalRead  (1<<13)
-
-#define VgaTiming0_PPL        Fld(6,2)
-#define VgaTiming0_HSW        Fld(8,8)
-#define VgaTiming0_HFP        Fld(8,16)
-#define VgaTiming0_HBP        Fld(8,24)
-
-#define VgaTiming1_LPS        Fld(10,0)
-#define VgaTiming1_VSW        Fld(6,10)
-#define VgaTiming1_VFP        Fld(8,16)
-#define VgaTiming1_VBP        Fld(8,24)
-
-#define VgaTiming2_IVS        0x01
-#define VgaTiming2_IHS        0x02
-#define VgaTiming2_CVS        0x04
-#define VgaTiming2_CHS        0x08
-
-#define VgaTiming3_HBS        Fld(8,0)
-#define VgaTiming3_HBE        Fld(8,8)
-#define VgaTiming3_VBS        Fld(8,16)
-#define VgaTiming3_VBE        Fld(8,24)
-
-#define VgaBorder_BCOL        Fld(24,0)
-
-#define VgaStatus_VFUF        0x01
-#define VgaStatus_VNext       0x02
-#define VgaStatus_VComp       0x04
-
-#define VgaInterruptMask_VFUFMask   0x00
-#define VgaInterruptMask_VNextMask  0x01
-#define VgaInterruptMask_VCompMask  0x02
-
-#define VgaPalette_R          Fld(8,0)
-#define VgaPalette_G          Fld(8,8)
-#define VgaPalette_B          Fld(8,16)
-
-#define DacControl_DACON      0x0001
-#define DacControl_COMPON     0x0002
-#define DacControl_PEDON      0x0004
-#define DacControl_RTrim      Fld(5,4)
-#define DacControl_GTrim      Fld(5,9)
-#define DacControl_BTrim      Fld(5,14)
-
-#define VgaTest_TDAC          0x00
-#define VgaTest_Datatest      Fld(4,1)
-#define VgaTest_DACTESTDAC    0x10
-#define VgaTest_DACTESTOUT    Fld(3,5)
-
-#endif /* LANGUAGE == C */
-
-/*
- * USB Host Interface Controller
- *
- * Registers
- *    Revision
- *    Control
- *    CommandStatus
- *    InterruptStatus
- *    InterruptEnable
- *    HCCA
- *    PeriodCurrentED
- *    ControlHeadED
- *    BulkHeadED
- *    BulkCurrentED
- *    DoneHead
- *    FmInterval
- *    FmRemaining
- *    FmNumber
- *    PeriodicStart
- *    LSThreshold
- *    RhDescriptorA
- *    RhDescriptorB
- *    RhStatus
- *    RhPortStatus
- *    USBStatus
- *    USBReset
- *    USTAR
- *    USWER
- *    USRFR
- *    USNFR
- *    USTCSR
- *    USSR
- *    
- */
-
-#define _USB( x )       _SA1101( ( x ) + __USB_CONTROL )
-
-
-#define _Revision         _USB( 0x0000 )
-#define _Control          _USB( 0x0888 )
-#define _CommandStatus    _USB( 0x0c00 )
-#define _InterruptStatus  _USB( 0x1000 )
-#define _InterruptEnable  _USB( 0x1400 )
-#define _HCCA             _USB( 0x1800 )
-#define _PeriodCurrentED  _USB( 0x1c00 )
-#define _ControlHeadED    _USB( 0x2000 )
-#define _BulkHeadED       _USB( 0x2800 )
-#define _BulkCurrentED    _USB( 0x2c00 )
-#define _DoneHead         _USB( 0x3000 )
-#define _FmInterval       _USB( 0x3400 )
-#define _FmRemaining      _USB( 0x3800 )
-#define _FmNumber         _USB( 0x3c00 )
-#define _PeriodicStart    _USB( 0x4000 )
-#define _LSThreshold      _USB( 0x4400 )
-#define _RhDescriptorA    _USB( 0x4800 )
-#define _RhDescriptorB    _USB( 0x4c00 )
-#define _RhStatus         _USB( 0x5000 )
-#define _RhPortStatus     _USB( 0x5400 )
-#define _USBStatus        _USB( 0x11800 )
-#define _USBReset         _USB( 0x11c00 )
-
-#define _USTAR            _USB( 0x10400 )
-#define _USWER            _USB( 0x10800 )
-#define _USRFR            _USB( 0x10c00 )
-#define _USNFR            _USB( 0x11000 )
-#define _USTCSR           _USB( 0x11400 )
-#define _USSR             _USB( 0x11800 )
-
-
-#if (LANGUAGE == C)
-
-#define Revision        (*((volatile Word *) SA1101_p2v (_Revision)))
-#define Control         (*((volatile Word *) SA1101_p2v (_Control)))
-#define CommandStatus   (*((volatile Word *) SA1101_p2v (_CommandStatus)))
-#define InterruptStatus (*((volatile Word *) SA1101_p2v (_InterruptStatus)))
-#define InterruptEnable (*((volatile Word *) SA1101_p2v (_InterruptEnable)))
-#define HCCA            (*((volatile Word *) SA1101_p2v (_HCCA)))
-#define PeriodCurrentED (*((volatile Word *) SA1101_p2v (_PeriodCurrentED)))
-#define ControlHeadED   (*((volatile Word *) SA1101_p2v (_ControlHeadED)))
-#define BulkHeadED      (*((volatile Word *) SA1101_p2v (_BulkHeadED)))
-#define BulkCurrentED   (*((volatile Word *) SA1101_p2v (_BulkCurrentED)))
-#define DoneHead        (*((volatile Word *) SA1101_p2v (_DoneHead)))
-#define FmInterval      (*((volatile Word *) SA1101_p2v (_FmInterval)))
-#define FmRemaining     (*((volatile Word *) SA1101_p2v (_FmRemaining)))
-#define FmNumber        (*((volatile Word *) SA1101_p2v (_FmNumber)))
-#define PeriodicStart   (*((volatile Word *) SA1101_p2v (_PeriodicStart)))
-#define LSThreshold     (*((volatile Word *) SA1101_p2v (_LSThreshold)))
-#define RhDescriptorA   (*((volatile Word *) SA1101_p2v (_RhDescriptorA)))
-#define RhDescriptorB   (*((volatile Word *) SA1101_p2v (_RhDescriptorB)))
-#define RhStatus        (*((volatile Word *) SA1101_p2v (_RhStatus)))
-#define RhPortStatus    (*((volatile Word *) SA1101_p2v (_RhPortStatus)))
-#define USBStatus       (*((volatile Word *) SA1101_p2v (_USBStatus)))
-#define USBReset        (*((volatile Word *) SA1101_p2v (_USBReset)))
-#define USTAR           (*((volatile Word *) SA1101_p2v (_USTAR)))
-#define USWER           (*((volatile Word *) SA1101_p2v (_USWER)))
-#define USRFR           (*((volatile Word *) SA1101_p2v (_USRFR)))
-#define USNFR           (*((volatile Word *) SA1101_p2v (_USNFR)))
-#define USTCSR          (*((volatile Word *) SA1101_p2v (_USTCSR)))
-#define USSR            (*((volatile Word *) SA1101_p2v (_USSR)))
-
-
-#define USBStatus_IrqHciRmtWkp       (1<<7)
-#define USBStatus_IrqHciBuffAcc      (1<<8)
-#define USBStatus_nIrqHciM           (1<<9)
-#define USBStatus_nHciMFClr          (1<<10)
-
-#define USBReset_ForceIfReset        0x01
-#define USBReset_ForceHcReset        0x02
-#define USBReset_ClkGenReset         0x04
-
-#define USTCR_RdBstCntrl             Fld(3,0)
-#define USTCR_ByteEnable             Fld(4,3)
-#define USTCR_WriteEn                (1<<7)
-#define USTCR_FifoCir                (1<<8)
-#define USTCR_TestXferSel            (1<<9)
-#define USTCR_FifoCirAtEnd           (1<<10)
-#define USTCR_nSimScaleDownClk       (1<<11)
-
-#define USSR_nAppMDEmpty             0x01
-#define USSR_nAppMDFirst             0x02
-#define USSR_nAppMDLast              0x04
-#define USSR_nAppMDFull              0x08
-#define USSR_nAppMAFull              0x10
-#define USSR_XferReq                 0x20
-#define USSR_XferEnd                 0x40
-
-#endif /* LANGUAGE == C */
-
-
-/*
- * Interrupt Controller
- *
- * Registers
- *    INTTEST0          Test register 0
- *    INTTEST1          Test register 1
- *    INTENABLE0        Interrupt Enable register 0
- *    INTENABLE1        Interrupt Enable register 1
- *    INTPOL0           Interrupt Polarity selection 0
- *    INTPOL1           Interrupt Polarity selection 1
- *    INTTSTSEL         Interrupt source selection
- *    INTSTATCLR0       Interrupt Status 0
- *    INTSTATCLR1       Interrupt Status 1
- *    INTSET0           Interrupt Set 0
- *    INTSET1           Interrupt Set 1
- */
-
-#define _INT( x )       _SA1101( ( x ) + __INTERRUPT_CONTROL)
-
-#define _INTTEST0       _INT( 0x1000 )
-#define _INTTEST1       _INT( 0x1400 )
-#define _INTENABLE0     _INT( 0x2000 )
-#define _INTENABLE1     _INT( 0x2400 )
-#define _INTPOL0        _INT( 0x3000 )
-#define _INTPOL1        _INT( 0x3400 )
-#define _INTTSTSEL      _INT( 0x5000 )
-#define _INTSTATCLR0    _INT( 0x6000 )
-#define _INTSTATCLR1    _INT( 0x6400 )
-#define _INTSET0        _INT( 0x7000 )
-#define _INTSET1        _INT( 0x7400 )
-
-#if ( LANGUAGE == C )
-#define INTTEST0        (*((volatile Word *) SA1101_p2v (_INTTEST0)))
-#define INTTEST1        (*((volatile Word *) SA1101_p2v (_INTTEST1)))
-#define INTENABLE0      (*((volatile Word *) SA1101_p2v (_INTENABLE0)))
-#define INTENABLE1      (*((volatile Word *) SA1101_p2v (_INTENABLE1)))
-#define INTPOL0         (*((volatile Word *) SA1101_p2v (_INTPOL0)))
-#define INTPOL1         (*((volatile Word *) SA1101_p2v (_INTPOL1)))
-#define INTTSTSEL       (*((volatile Word *) SA1101_p2v (_INTTSTSEL)))
-#define INTSTATCLR0     (*((volatile Word *) SA1101_p2v (_INTSTATCLR0)))
-#define INTSTATCLR1     (*((volatile Word *) SA1101_p2v (_INTSTATCLR1)))
-#define INTSET0         (*((volatile Word *) SA1101_p2v (_INTSET0)))
-#define INTSET1         (*((volatile Word *) SA1101_p2v (_INTSET1)))
-
-#endif /* LANGUAGE == C */
-
-/*
- * PS/2 Trackpad and Mouse Interfaces
- *
- * Registers   (prefix kbd applies to trackpad interface, mse to mouse)
- *    KBDCR             Control Register
- *    KBDSTAT           Status Register
- *    KBDDATA           Transmit/Receive Data register
- *    KBDCLKDIV         Clock Division Register
- *    KBDPRECNT         Clock Precount Register
- *    KBDTEST1          Test register 1
- *    KBDTEST2          Test register 2
- *    KBDTEST3          Test register 3
- *    KBDTEST4          Test register 4
- *    MSECR     
- *    MSESTAT
- *    MSEDATA
- *    MSECLKDIV
- *    MSEPRECNT
- *    MSETEST1
- *    MSETEST2
- *    MSETEST3
- *    MSETEST4
- *     
- */
-
-#define _KBD( x )       _SA1101( ( x ) + __TRACK_INTERFACE )
-#define _MSE( x )       _SA1101( ( x ) + __MOUSE_INTERFACE )
-
-#define _KBDCR          _KBD( 0x0000 )
-#define _KBDSTAT        _KBD( 0x0400 )
-#define _KBDDATA        _KBD( 0x0800 )
-#define _KBDCLKDIV      _KBD( 0x0c00 )
-#define _KBDPRECNT      _KBD( 0x1000 )
-#define _KBDTEST1       _KBD( 0x2000 )
-#define _KBDTEST2       _KBD( 0x2400 )
-#define _KBDTEST3       _KBD( 0x2800 )
-#define _KBDTEST4       _KBD( 0x2c00 )
-#define _MSECR          _MSE( 0x0000 )
-#define _MSESTAT        _MSE( 0x0400 )
-#define _MSEDATA        _MSE( 0x0800 )
-#define _MSECLKDIV      _MSE( 0x0c00 )
-#define _MSEPRECNT      _MSE( 0x1000 )
-#define _MSETEST1       _MSE( 0x2000 )
-#define _MSETEST2       _MSE( 0x2400 )
-#define _MSETEST3       _MSE( 0x2800 )
-#define _MSETEST4       _MSE( 0x2c00 )
-
-#if ( LANGUAGE == C )
-
-#define KBDCR       (*((volatile Word *) SA1101_p2v (_KBDCR)))
-#define KBDSTAT     (*((volatile Word *) SA1101_p2v (_KBDSTAT)))
-#define KBDDATA     (*((volatile Word *) SA1101_p2v (_KBDDATA)))
-#define KBDCLKDIV   (*((volatile Word *) SA1101_p2v (_KBDCLKDIV)))
-#define KBDPRECNT   (*((volatile Word *) SA1101_p2v (_KBDPRECNT)))
-#define KBDTEST1    (*((volatile Word *) SA1101_p2v (_KBDTEST1)))
-#define KBDTEST2    (*((volatile Word *) SA1101_p2v (_KBDTEST2)))
-#define KBDTEST3    (*((volatile Word *) SA1101_p2v (_KBDTEST3)))
-#define KBDTEST4    (*((volatile Word *) SA1101_p2v (_KBDTEST4)))
-#define MSECR       (*((volatile Word *) SA1101_p2v (_MSECR)))
-#define MSESTAT     (*((volatile Word *) SA1101_p2v (_MSESTAT)))
-#define MSEDATA     (*((volatile Word *) SA1101_p2v (_MSEDATA)))
-#define MSECLKDIV   (*((volatile Word *) SA1101_p2v (_MSECLKDIV)))
-#define MSEPRECNT   (*((volatile Word *) SA1101_p2v (_MSEPRECNT)))
-#define MSETEST1    (*((volatile Word *) SA1101_p2v (_MSETEST1)))
-#define MSETEST2    (*((volatile Word *) SA1101_p2v (_MSETEST2)))
-#define MSETEST3    (*((volatile Word *) SA1101_p2v (_MSETEST3)))
-#define MSETEST4    (*((volatile Word *) SA1101_p2v (_MSETEST4)))
-
-
-#define KBDCR_ENA                0x08
-#define KBDCR_FKD                0x02
-#define KBDCR_FKC                0x01
-
-#define KBDSTAT_TXE              0x80
-#define KBDSTAT_TXB              0x40
-#define KBDSTAT_RXF              0x20
-#define KBDSTAT_RXB              0x10
-#define KBDSTAT_ENA              0x08
-#define KBDSTAT_RXP              0x04
-#define KBDSTAT_KBD              0x02
-#define KBDSTAT_KBC              0x01
-
-#define KBDCLKDIV_DivVal         Fld(4,0)
-
-#define MSECR_ENA                0x08
-#define MSECR_FKD                0x02
-#define MSECR_FKC                0x01
-
-#define MSESTAT_TXE              0x80
-#define MSESTAT_TXB              0x40
-#define MSESTAT_RXF              0x20
-#define MSESTAT_RXB              0x10
-#define MSESTAT_ENA              0x08
-#define MSESTAT_RXP              0x04   
-#define MSESTAT_MSD              0x02
-#define MSESTAT_MSC              0x01
-
-#define MSECLKDIV_DivVal         Fld(4,0)
-
-#define KBDTEST1_CD              0x80
-#define KBDTEST1_RC1             0x40
-#define KBDTEST1_MC              0x20
-#define KBDTEST1_C               Fld(2,3)
-#define KBDTEST1_T2              0x40
-#define KBDTEST1_T1              0x20
-#define KBDTEST1_T0              0x10
-#define KBDTEST2_TICBnRES        0x08
-#define KBDTEST2_RKC             0x04
-#define KBDTEST2_RKD             0x02
-#define KBDTEST2_SEL             0x01
-#define KBDTEST3_ms_16           0x80
-#define KBDTEST3_us_64           0x40
-#define KBDTEST3_us_16           0x20
-#define KBDTEST3_DIV8            0x10
-#define KBDTEST3_DIn             0x08
-#define KBDTEST3_CIn             0x04
-#define KBDTEST3_KD              0x02
-#define KBDTEST3_KC              0x01
-#define KBDTEST4_BC12            0x80
-#define KBDTEST4_BC11            0x40
-#define KBDTEST4_TRES            0x20
-#define KBDTEST4_CLKOE           0x10
-#define KBDTEST4_CRES            0x08
-#define KBDTEST4_RXB             0x04
-#define KBDTEST4_TXB             0x02
-#define KBDTEST4_SRX             0x01
-
-#define MSETEST1_CD              0x80
-#define MSETEST1_RC1             0x40
-#define MSETEST1_MC              0x20
-#define MSETEST1_C               Fld(2,3)
-#define MSETEST1_T2              0x40
-#define MSETEST1_T1              0x20
-#define MSETEST1_T0              0x10
-#define MSETEST2_TICBnRES        0x08
-#define MSETEST2_RKC             0x04
-#define MSETEST2_RKD             0x02
-#define MSETEST2_SEL             0x01
-#define MSETEST3_ms_16           0x80
-#define MSETEST3_us_64           0x40
-#define MSETEST3_us_16           0x20
-#define MSETEST3_DIV8            0x10
-#define MSETEST3_DIn             0x08
-#define MSETEST3_CIn             0x04
-#define MSETEST3_KD              0x02
-#define MSETEST3_KC              0x01
-#define MSETEST4_BC12            0x80
-#define MSETEST4_BC11            0x40
-#define MSETEST4_TRES            0x20
-#define MSETEST4_CLKOE           0x10
-#define MSETEST4_CRES            0x08
-#define MSETEST4_RXB             0x04
-#define MSETEST4_TXB             0x02
-#define MSETEST4_SRX             0x01
-
-#endif  /* LANGUAGE == C */
-
-
-/*
- * General-Purpose I/O Interface
- *
- * Registers
- *    PADWR     Port A Data Write Register
- *    PBDWR     Port B Data Write Register
- *    PADRR     Port A Data Read Register
- *    PBDRR     Port B Data Read Register
- *    PADDR     Port A Data Direction Register
- *    PBDDR     Port B Data Direction Register
- *    PASSR     Port A Sleep State Register
- *    PBSSR     Port B Sleep State Register
- *
- */
-
-#define _PIO( x )      _SA1101( ( x ) + __GPIO_INTERFACE )
-
-#define _PADWR         _PIO( 0x0000 )
-#define _PBDWR         _PIO( 0x0400 )
-#define _PADRR         _PIO( 0x0000 )
-#define _PBDRR         _PIO( 0x0400 )
-#define _PADDR         _PIO( 0x0800 )
-#define _PBDDR         _PIO( 0x0c00 )
-#define _PASSR         _PIO( 0x1000 )
-#define _PBSSR         _PIO( 0x1400 )
-
-
-#if ( LANGUAGE == C )
-
-
-#define PADWR       (*((volatile Word *) SA1101_p2v (_PADWR)))
-#define PBDWR       (*((volatile Word *) SA1101_p2v (_PBDWR)))
-#define PADRR       (*((volatile Word *) SA1101_p2v (_PADRR)))
-#define PBDRR       (*((volatile Word *) SA1101_p2v (_PBDRR)))
-#define PADDR       (*((volatile Word *) SA1101_p2v (_PADDR)))
-#define PBDDR       (*((volatile Word *) SA1101_p2v (_PBDDR)))
-#define PASSR       (*((volatile Word *) SA1101_p2v (_PASSR)))
-#define PBSSR       (*((volatile Word *) SA1101_p2v (_PBSSR)))
-
-#endif
-
-
-
-/*
- * Keypad Interface
- *
- * Registers
- *    PXDWR
- *    PXDRR
- *    PYDWR
- *    PYDRR
- *
- */
-
-#define _KEYPAD( x )    _SA1101( ( x ) + __KEYPAD_INTERFACE ) 
-
-#define _PXDWR     _KEYPAD( 0x0000 )
-#define _PXDRR     _KEYPAD( 0x0000 )
-#define _PYDWR     _KEYPAD( 0x0400 )
-#define _PYDRR     _KEYPAD( 0x0400 )
-
-#if ( LANGUAGE == C )
-
-
-#define PXDWR       (*((volatile Word *) SA1101_p2v (_PXDWR)))
-#define PXDRR       (*((volatile Word *) SA1101_p2v (_PXDRR)))
-#define PYDWR       (*((volatile Word *) SA1101_p2v (_PYDWR)))
-#define PYDRR       (*((volatile Word *) SA1101_p2v (_PYDRR)))
-
-#endif
-
-
-
-/*
- * PCMCIA Interface
- *
- * Registers
- *    PCSR      Status Register
- *    PCCR      Control Register
- *    PCSSR     Sleep State Register
- *
- */
-
-#define _CARD( x )      _SA1101( ( x ) + __PCMCIA_INTERFACE )
-
-#define _PCSR      _CARD( 0x0000 )
-#define _PCCR      _CARD( 0x0400 )
-#define _PCSSR     _CARD( 0x0800 )
-
-#if ( LANGUAGE == C )
-#define PCSR    (*((volatile Word *) SA1101_p2v (_PCSR)))
-#define PCCR    (*((volatile Word *) SA1101_p2v (_PCCR)))
-#define PCSSR   (*((volatile Word *) SA1101_p2v (_PCSSR)))
-
-#define PCSR_S0_ready           0x0001
-#define PCSR_S1_ready           0x0002
-#define PCSR_S0_detected        0x0004
-#define PCSR_S1_detected        0x0008
-#define PCSR_S0_VS1             0x0010
-#define PCSR_S0_VS2             0x0020
-#define PCSR_S1_VS1             0x0040
-#define PCSR_S1_VS2             0x0080
-#define PCSR_S0_WP              0x0100
-#define PCSR_S1_WP              0x0200
-#define PCSR_S0_BVD1_nSTSCHG    0x0400
-#define PCSR_S0_BVD2_nSPKR      0x0800
-#define PCSR_S1_BVD1_nSTSCHG    0x1000
-#define PCSR_S1_BVD2_nSPKR      0x2000
-
-#define PCCR_S0_VPP0            0x0001
-#define PCCR_S0_VPP1            0x0002
-#define PCCR_S0_VCC0            0x0004
-#define PCCR_S0_VCC1            0x0008
-#define PCCR_S1_VPP0            0x0010
-#define PCCR_S1_VPP1            0x0020
-#define PCCR_S1_VCC0            0x0040
-#define PCCR_S1_VCC1            0x0080
-#define PCCR_S0_reset           0x0100
-#define PCCR_S1_reset           0x0200
-#define PCCR_S0_float           0x0400
-#define PCCR_S1_float           0x0800
-
-#define PCSSR_S0_VCC0           0x0001
-#define PCSSR_S0_VCC1           0x0002
-#define PCSSR_S0_VPP0           0x0004
-#define PCSSR_S0_VPP1           0x0008
-#define PCSSR_S0_control        0x0010
-#define PCSSR_S1_VCC0           0x0020
-#define PCSSR_S1_VCC1           0x0040
-#define PCSSR_S1_VPP0           0x0080
-#define PCSSR_S1_VPP1           0x0100
-#define PCSSR_S1_control        0x0200
-
-#endif
-
-#undef C
-#undef Assembly
diff --git a/include/asm-arm/arch-sa1100/assabet.h b/include/asm-arm/arch-sa1100/assabet.h
deleted file mode 100644
index d6a1bb5b4944..000000000000
--- a/include/asm-arm/arch-sa1100/assabet.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * linux/include/asm-arm/arch-sa1100/assabet.h
- *
- * Created 2000/06/05 by Nicolas Pitre <nico@cam.org>
- *
- * This file contains the hardware specific definitions for Assabet
- * Only include this file from SA1100-specific files.
- *
- * 2000/05/23 John Dorsey <john+@cs.cmu.edu>
- *      Definitions for Neponset added.
- */
-#ifndef __ASM_ARCH_ASSABET_H
-#define __ASM_ARCH_ASSABET_H
-
-
-/* System Configuration Register flags */
-
-#define ASSABET_SCR_SDRAM_LOW   (1<<2)  /* SDRAM size (low bit) */
-#define ASSABET_SCR_SDRAM_HIGH  (1<<3)  /* SDRAM size (high bit) */
-#define ASSABET_SCR_FLASH_LOW   (1<<4)  /* Flash size (low bit) */
-#define ASSABET_SCR_FLASH_HIGH  (1<<5)  /* Flash size (high bit) */
-#define ASSABET_SCR_GFX         (1<<8)  /* Graphics Accelerator (0 = present) */
-#define ASSABET_SCR_SA1111      (1<<9)  /* Neponset (0 = present) */
-
-#define ASSABET_SCR_INIT        -1
-
-extern unsigned long SCR_value;
-
-#ifdef CONFIG_ASSABET_NEPONSET
-#define machine_has_neponset()  ((SCR_value & ASSABET_SCR_SA1111) == 0)
-#else
-#define machine_has_neponset()  (0)
-#endif
-
-/* Board Control Register */
-
-#define ASSABET_BCR_BASE  0xf1000000
-#define ASSABET_BCR (*(volatile unsigned int *)(ASSABET_BCR_BASE))
-
-#define ASSABET_BCR_CF_PWR      (1<<0)  /* Compact Flash Power (1 = 3.3v, 0 = off) */
-#define ASSABET_BCR_CF_RST      (1<<1)  /* Compact Flash Reset (1 = power up reset) */
-#define ASSABET_BCR_GFX_RST     (1<<1)  /* Graphics Accelerator Reset (0 = hold reset) */
-#define ASSABET_BCR_CODEC_RST   (1<<2)  /* 0 = Holds UCB1300, ADI7171, and UDA1341 in reset */
-#define ASSABET_BCR_IRDA_FSEL   (1<<3)  /* IRDA Frequency select (0 = SIR, 1 = MIR/ FIR) */
-#define ASSABET_BCR_IRDA_MD0    (1<<4)  /* Range/Power select */
-#define ASSABET_BCR_IRDA_MD1    (1<<5)  /* Range/Power select */
-#define ASSABET_BCR_STEREO_LB   (1<<6)  /* Stereo Loopback */
-#define ASSABET_BCR_CF_BUS_OFF  (1<<7)  /* Compact Flash bus (0 = on, 1 = off (float)) */
-#define ASSABET_BCR_AUDIO_ON    (1<<8)  /* Audio power on */
-#define ASSABET_BCR_LIGHT_ON    (1<<9)  /* Backlight */
-#define ASSABET_BCR_LCD_12RGB   (1<<10) /* 0 = 16RGB, 1 = 12RGB */
-#define ASSABET_BCR_LCD_ON      (1<<11) /* LCD power on */
-#define ASSABET_BCR_RS232EN     (1<<12) /* RS232 transceiver enable */
-#define ASSABET_BCR_LED_RED     (1<<13) /* D9 (0 = on, 1 = off) */
-#define ASSABET_BCR_LED_GREEN   (1<<14) /* D8 (0 = on, 1 = off) */
-#define ASSABET_BCR_VIB_ON      (1<<15) /* Vibration motor (quiet alert) */
-#define ASSABET_BCR_COM_DTR     (1<<16) /* COMport Data Terminal Ready */
-#define ASSABET_BCR_COM_RTS     (1<<17) /* COMport Request To Send */
-#define ASSABET_BCR_RAD_WU      (1<<18) /* Radio wake up interrupt */
-#define ASSABET_BCR_SMB_EN      (1<<19) /* System management bus enable */
-#define ASSABET_BCR_TV_IR_DEC   (1<<20) /* TV IR Decode Enable (not implemented) */
-#define ASSABET_BCR_QMUTE       (1<<21) /* Quick Mute */
-#define ASSABET_BCR_RAD_ON      (1<<22) /* Radio Power On */
-#define ASSABET_BCR_SPK_OFF     (1<<23) /* 1 = Speaker amplifier power off */
-
-#ifdef CONFIG_SA1100_ASSABET
-extern void ASSABET_BCR_frob(unsigned int mask, unsigned int set);
-#else
-#define ASSABET_BCR_frob(x,y)   do { } while (0)
-#endif
-
-#define ASSABET_BCR_set(x)      ASSABET_BCR_frob((x), (x))
-#define ASSABET_BCR_clear(x)    ASSABET_BCR_frob((x), 0)
-
-#define ASSABET_BSR_BASE        0xf1000000
-#define ASSABET_BSR (*(volatile unsigned int*)(ASSABET_BSR_BASE))
-
-#define ASSABET_BSR_RS232_VALID (1 << 24)
-#define ASSABET_BSR_COM_DCD     (1 << 25)
-#define ASSABET_BSR_COM_CTS     (1 << 26)
-#define ASSABET_BSR_COM_DSR     (1 << 27)
-#define ASSABET_BSR_RAD_CTS     (1 << 28)
-#define ASSABET_BSR_RAD_DSR     (1 << 29)
-#define ASSABET_BSR_RAD_DCD     (1 << 30)
-#define ASSABET_BSR_RAD_RI      (1 << 31)
-
-
-/* GPIOs for which the generic definition doesn't say much */
-#define ASSABET_GPIO_RADIO_IRQ          GPIO_GPIO (14)  /* Radio interrupt request  */
-#define ASSABET_GPIO_PS_MODE_SYNC       GPIO_GPIO (16)  /* Power supply mode/sync   */
-#define ASSABET_GPIO_STEREO_64FS_CLK    GPIO_GPIO (19)  /* SSP UDA1341 clock input  */
-#define ASSABET_GPIO_CF_IRQ             GPIO_GPIO (21)  /* CF IRQ   */
-#define ASSABET_GPIO_CF_CD              GPIO_GPIO (22)  /* CF CD */
-#define ASSABET_GPIO_CF_BVD2            GPIO_GPIO (24)  /* CF BVD */
-#define ASSABET_GPIO_GFX_IRQ            GPIO_GPIO (24)  /* Graphics IRQ */
-#define ASSABET_GPIO_CF_BVD1            GPIO_GPIO (25)  /* CF BVD */
-#define ASSABET_GPIO_BATT_LOW           GPIO_GPIO (26)  /* Low battery */
-#define ASSABET_GPIO_RCLK               GPIO_GPIO (26)  /* CCLK/2  */
-
-#define ASSABET_IRQ_GPIO_CF_IRQ         IRQ_GPIO21
-#define ASSABET_IRQ_GPIO_CF_CD          IRQ_GPIO22
-#define ASSABET_IRQ_GPIO_CF_BVD2        IRQ_GPIO24
-#define ASSABET_IRQ_GPIO_CF_BVD1        IRQ_GPIO25
-
-#endif
diff --git a/include/asm-arm/arch-sa1100/badge4.h b/include/asm-arm/arch-sa1100/badge4.h
deleted file mode 100644
index d93a9a83b25d..000000000000
--- a/include/asm-arm/arch-sa1100/badge4.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * linux/include/asm-arm/arch-sa1100/badge4.h
- *
- *   Tim Connors <connors@hpl.hp.com>
- *   Christopher Hoover <ch@hpl.hp.com>
- *
- * Copyright (C) 2002 Hewlett-Packard Company
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#error "include <asm/arch/hardware.h> instead"
-#endif
-
-#define BADGE4_SA1111_BASE              (0x48000000)
-
-/* GPIOs on the BadgePAD 4 */
-#define BADGE4_GPIO_INT_1111            GPIO_GPIO0   /* SA-1111 IRQ */
-
-#define BADGE4_GPIO_INT_VID             GPIO_GPIO1   /* Video expansion */
-#define BADGE4_GPIO_LGP2                GPIO_GPIO2   /* GPIO_LDD8 */
-#define BADGE4_GPIO_LGP3                GPIO_GPIO3   /* GPIO_LDD9 */
-#define BADGE4_GPIO_LGP4                GPIO_GPIO4   /* GPIO_LDD10 */
-#define BADGE4_GPIO_LGP5                GPIO_GPIO5   /* GPIO_LDD11 */
-#define BADGE4_GPIO_LGP6                GPIO_GPIO6   /* GPIO_LDD12 */
-#define BADGE4_GPIO_LGP7                GPIO_GPIO7   /* GPIO_LDD13 */
-#define BADGE4_GPIO_LGP8                GPIO_GPIO8   /* GPIO_LDD14 */
-#define BADGE4_GPIO_LGP9                GPIO_GPIO9   /* GPIO_LDD15 */
-#define BADGE4_GPIO_GPA_VID             GPIO_GPIO10  /* Video expansion */
-#define BADGE4_GPIO_GPB_VID             GPIO_GPIO11  /* Video expansion */
-#define BADGE4_GPIO_GPC_VID             GPIO_GPIO12  /* Video expansion */
-
-#define BADGE4_GPIO_UART_HS1            GPIO_GPIO13
-#define BADGE4_GPIO_UART_HS2            GPIO_GPIO14
-
-#define BADGE4_GPIO_MUXSEL0             GPIO_GPIO15
-#define BADGE4_GPIO_TESTPT_J7           GPIO_GPIO16
-
-#define BADGE4_GPIO_SDSDA               GPIO_GPIO17  /* SDRAM SPD Data */
-#define BADGE4_GPIO_SDSCL               GPIO_GPIO18  /* SDRAM SPD Clock */
-#define BADGE4_GPIO_SDTYP0              GPIO_GPIO19  /* SDRAM Type Control */
-#define BADGE4_GPIO_SDTYP1              GPIO_GPIO20  /* SDRAM Type Control */
-
-#define BADGE4_GPIO_BGNT_1111           GPIO_GPIO21  /* GPIO_MBGNT */
-#define BADGE4_GPIO_BREQ_1111           GPIO_GPIO22  /* GPIO_TREQA */
-
-#define BADGE4_GPIO_TESTPT_J6           GPIO_GPIO23
-
-#define BADGE4_GPIO_PCMEN5V             GPIO_GPIO24  /* 5V power */
-
-#define BADGE4_GPIO_SA1111_NRST         GPIO_GPIO25  /* SA-1111 nRESET */
-
-#define BADGE4_GPIO_TESTPT_J5           GPIO_GPIO26
-
-#define BADGE4_GPIO_CLK_1111            GPIO_GPIO27  /* GPIO_32_768kHz */
-
-/* Interrupts on the BadgePAD 4 */
-#define BADGE4_IRQ_GPIO_SA1111          IRQ_GPIO0    /* SA-1111 interrupt */
-
-
-/* PCM5ENV Usage tracking */
-
-#define BADGE4_5V_PCMCIA_SOCK0          (1<<0)
-#define BADGE4_5V_PCMCIA_SOCK1          (1<<1)
-#define BADGE4_5V_PCMCIA_SOCK(n)        (1<<(n))
-#define BADGE4_5V_USB                   (1<<2)
-#define BADGE4_5V_INITIALLY             (1<<3)
-
-#ifndef __ASSEMBLY__
-extern void badge4_set_5V(unsigned subsystem, int on);
-#endif
diff --git a/include/asm-arm/arch-sa1100/cerf.h b/include/asm-arm/arch-sa1100/cerf.h
deleted file mode 100644
index 9a19c3d07c1e..000000000000
--- a/include/asm-arm/arch-sa1100/cerf.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * include/asm-arm/arch-sa1100/cerf.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Apr-2003 : Removed some old PDA crud [FB]
- */
-#ifndef _INCLUDE_CERF_H_
-#define _INCLUDE_CERF_H_
-
-
-#define CERF_ETH_IO                     0xf0000000
-#define CERF_ETH_IRQ IRQ_GPIO26
-
-#define CERF_GPIO_CF_BVD2               GPIO_GPIO (19)
-#define CERF_GPIO_CF_BVD1               GPIO_GPIO (20)
-#define CERF_GPIO_CF_RESET              GPIO_GPIO (21)
-#define CERF_GPIO_CF_IRQ                GPIO_GPIO (22)
-#define CERF_GPIO_CF_CD                 GPIO_GPIO (23)
-
-#define CERF_IRQ_GPIO_CF_BVD2           IRQ_GPIO19
-#define CERF_IRQ_GPIO_CF_BVD1           IRQ_GPIO20
-#define CERF_IRQ_GPIO_CF_IRQ            IRQ_GPIO22
-#define CERF_IRQ_GPIO_CF_CD             IRQ_GPIO23
-
-#endif // _INCLUDE_CERF_H_
diff --git a/include/asm-arm/arch-sa1100/collie.h b/include/asm-arm/arch-sa1100/collie.h
deleted file mode 100644
index 762eba535813..000000000000
--- a/include/asm-arm/arch-sa1100/collie.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * linux/include/asm-arm/arch-sa1100/collie.h
- *
- * This file contains the hardware specific definitions for Assabet
- * Only include this file from SA1100-specific files.
- *
- * ChangeLog:
- *   04-06-2001 Lineo Japan, Inc.
- *   04-16-2001 SHARP Corporation
- *   07-07-2002 Chris Larson <clarson@digi.com>
- *
- */
-#ifndef __ASM_ARCH_COLLIE_H
-#define __ASM_ARCH_COLLIE_H
-
-
-#define COLLIE_SCP_CHARGE_ON    SCOOP_GPCR_PA11
-#define COLLIE_SCP_DIAG_BOOT1   SCOOP_GPCR_PA12
-#define COLLIE_SCP_DIAG_BOOT2   SCOOP_GPCR_PA13
-#define COLLIE_SCP_MUTE_L       SCOOP_GPCR_PA14
-#define COLLIE_SCP_MUTE_R       SCOOP_GPCR_PA15
-#define COLLIE_SCP_5VON         SCOOP_GPCR_PA16
-#define COLLIE_SCP_AMP_ON       SCOOP_GPCR_PA17
-#define COLLIE_SCP_VPEN         SCOOP_GPCR_PA18
-#define COLLIE_SCP_LB_VOL_CHG   SCOOP_GPCR_PA19
-
-#define COLLIE_SCOOP_IO_DIR     ( COLLIE_SCP_CHARGE_ON | COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | \
-                                COLLIE_SCP_5VON | COLLIE_SCP_AMP_ON | COLLIE_SCP_VPEN | \
-                                COLLIE_SCP_LB_VOL_CHG )
-#define COLLIE_SCOOP_IO_OUT     ( COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | COLLIE_SCP_VPEN | \
-                                COLLIE_SCP_CHARGE_ON )
-
-/* GPIOs for which the generic definition doesn't say much */
-
-#define COLLIE_GPIO_ON_KEY              GPIO_GPIO (0)
-#define COLLIE_GPIO_AC_IN               GPIO_GPIO (1)
-#define COLLIE_GPIO_SDIO_INT            GPIO_GPIO (11)
-#define COLLIE_GPIO_CF_IRQ              GPIO_GPIO (14)
-#define COLLIE_GPIO_nREMOCON_INT        GPIO_GPIO (15)
-#define COLLIE_GPIO_UCB1x00_RESET       GPIO_GPIO (16)
-#define COLLIE_GPIO_nMIC_ON             GPIO_GPIO (17)
-#define COLLIE_GPIO_nREMOCON_ON         GPIO_GPIO (18)
-#define COLLIE_GPIO_CO                  GPIO_GPIO (20)
-#define COLLIE_GPIO_MCP_CLK             GPIO_GPIO (21)
-#define COLLIE_GPIO_CF_CD               GPIO_GPIO (22)
-#define COLLIE_GPIO_UCB1x00_IRQ         GPIO_GPIO (23)
-#define COLLIE_GPIO_WAKEUP              GPIO_GPIO (24)
-#define COLLIE_GPIO_GA_INT              GPIO_GPIO (25)
-#define COLLIE_GPIO_MAIN_BAT_LOW        GPIO_GPIO (26)
-
-/* Interrupts */
-
-#define COLLIE_IRQ_GPIO_ON_KEY          IRQ_GPIO0
-#define COLLIE_IRQ_GPIO_AC_IN           IRQ_GPIO1
-#define COLLIE_IRQ_GPIO_SDIO_IRQ        IRQ_GPIO11
-#define COLLIE_IRQ_GPIO_CF_IRQ          IRQ_GPIO14
-#define COLLIE_IRQ_GPIO_nREMOCON_INT    IRQ_GPIO15
-#define COLLIE_IRQ_GPIO_CO              IRQ_GPIO20
-#define COLLIE_IRQ_GPIO_CF_CD           IRQ_GPIO22
-#define COLLIE_IRQ_GPIO_UCB1x00_IRQ     IRQ_GPIO23
-#define COLLIE_IRQ_GPIO_WAKEUP          IRQ_GPIO24
-#define COLLIE_IRQ_GPIO_GA_INT          IRQ_GPIO25
-#define COLLIE_IRQ_GPIO_MAIN_BAT_LOW    IRQ_GPIO26
-
-#define COLLIE_LCM_IRQ_GPIO_RTS         IRQ_LOCOMO_GPIO0
-#define COLLIE_LCM_IRQ_GPIO_CTS         IRQ_LOCOMO_GPIO1
-#define COLLIE_LCM_IRQ_GPIO_DSR         IRQ_LOCOMO_GPIO2
-#define COLLIE_LCM_IRQ_GPIO_DTR         IRQ_LOCOMO_GPIO3
-#define COLLIE_LCM_IRQ_GPIO_nSD_DETECT  IRQ_LOCOMO_GPIO13
-#define COLLIE_LCM_IRQ_GPIO_nSD_WP      IRQ_LOCOMO_GPIO14
-
-/* GPIO's on the TC35143AF (Toshiba Analog Frontend) */
-#define COLLIE_TC35143_GPIO_VERSION0    UCB_IO_0        /* GPIO0=Version                 */
-#define COLLIE_TC35143_GPIO_TBL_CHK     UCB_IO_1        /* GPIO1=TBL_CHK                 */
-#define COLLIE_TC35143_GPIO_VPEN_ON     UCB_IO_2        /* GPIO2=VPNE_ON                 */
-#define COLLIE_TC35143_GPIO_IR_ON       UCB_IO_3        /* GPIO3=IR_ON                   */
-#define COLLIE_TC35143_GPIO_AMP_ON      UCB_IO_4        /* GPIO4=AMP_ON                  */
-#define COLLIE_TC35143_GPIO_VERSION1    UCB_IO_5        /* GPIO5=Version                 */
-#define COLLIE_TC35143_GPIO_FS8KLPF     UCB_IO_5        /* GPIO5=fs 8k LPF               */
-#define COLLIE_TC35143_GPIO_BUZZER_BIAS UCB_IO_6        /* GPIO6=BUZZER BIAS             */
-#define COLLIE_TC35143_GPIO_MBAT_ON     UCB_IO_7        /* GPIO7=MBAT_ON                 */
-#define COLLIE_TC35143_GPIO_BBAT_ON     UCB_IO_8        /* GPIO8=BBAT_ON                 */
-#define COLLIE_TC35143_GPIO_TMP_ON      UCB_IO_9        /* GPIO9=TMP_ON                  */
-#define COLLIE_TC35143_GPIO_IN          ( UCB_IO_0 | UCB_IO_2 | UCB_IO_5 )
-#define COLLIE_TC35143_GPIO_OUT         ( UCB_IO_1 | UCB_IO_3 | UCB_IO_4 | UCB_IO_6 | \
-                                        UCB_IO_7 | UCB_IO_8 | UCB_IO_9 )
-
-#endif
diff --git a/include/asm-arm/arch-sa1100/debug-macro.S b/include/asm-arm/arch-sa1100/debug-macro.S
deleted file mode 100644
index 1b7753654bd4..000000000000
--- a/include/asm-arm/arch-sa1100/debug-macro.S
+++ /dev/null
@@ -1,58 +0,0 @@
-/* linux/include/asm-arm/arch-sa1100/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-#include <asm/arch/hardware.h>
-
-                .macro  addruart,rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx, #0x80000000        @ physical base address
-                movne   \rx, #0xf8000000        @ virtual address
-
-                @ We probe for the active serial port here, coherently with
-                @ the comment in include/asm-arm/arch-sa1100/uncompress.h.
-                @ We assume r1 can be clobbered.
-
-                @ see if Ser3 is active
-                add     \rx, \rx, #0x00050000
-                ldr     r1, [\rx, #UTCR3]
-                tst     r1, #UTCR3_TXE
-
-                @ if Ser3 is inactive, then try Ser1
-                addeq   \rx, \rx, #(0x00010000 - 0x00050000)
-                ldreq   r1, [\rx, #UTCR3]
-                tsteq   r1, #UTCR3_TXE
-
-                @ if Ser1 is inactive, then try Ser2
-                addeq   \rx, \rx, #(0x00030000 - 0x00010000)
-                ldreq   r1, [\rx, #UTCR3]
-                tsteq   r1, #UTCR3_TXE
-
-                @ if all ports are inactive, then there is nothing we can do
-                moveq   pc, lr
-                .endm
-
-                .macro  senduart,rd,rx
-                str     \rd, [\rx, #UTDR]
-                .endm
-
-                .macro  waituart,rd,rx
-1001:           ldr     \rd, [\rx, #UTSR1]
-                tst     \rd, #UTSR1_TNF
-                beq     1001b
-                .endm
-
-                .macro  busyuart,rd,rx
-1001:           ldr     \rd, [\rx, #UTSR1]
-                tst     \rd, #UTSR1_TBY
-                bne     1001b
-                .endm
diff --git a/include/asm-arm/arch-sa1100/dma.h b/include/asm-arm/arch-sa1100/dma.h
deleted file mode 100644
index 6b7917a2e77a..000000000000
--- a/include/asm-arm/arch-sa1100/dma.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * linux/include/asm-arm/arch-sa1100/dma.h
- *
- * Generic SA1100 DMA support
- *
- * Copyright (C) 2000 Nicolas Pitre
- *
- */
-
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-
-#include "hardware.h"
-
-
-/*
- * The SA1100 has six internal DMA channels.
- */
-#define SA1100_DMA_CHANNELS     6
-
-/*
- * Maximum physical DMA buffer size
- */
-#define MAX_DMA_SIZE            0x1fff
-#define CUT_DMA_SIZE            0x1000
-
-/*
- * All possible SA1100 devices a DMA channel can be attached to.
- */
-typedef enum {
-        DMA_Ser0UDCWr  = DDAR_Ser0UDCWr,   /* Ser. port 0 UDC Write */
-        DMA_Ser0UDCRd  = DDAR_Ser0UDCRd,   /* Ser. port 0 UDC Read */
-        DMA_Ser1UARTWr = DDAR_Ser1UARTWr,  /* Ser. port 1 UART Write */
-        DMA_Ser1UARTRd = DDAR_Ser1UARTRd,  /* Ser. port 1 UART Read */
-        DMA_Ser1SDLCWr = DDAR_Ser1SDLCWr,  /* Ser. port 1 SDLC Write */
-        DMA_Ser1SDLCRd = DDAR_Ser1SDLCRd,  /* Ser. port 1 SDLC Read */
-        DMA_Ser2UARTWr = DDAR_Ser2UARTWr,  /* Ser. port 2 UART Write */
-        DMA_Ser2UARTRd = DDAR_Ser2UARTRd,  /* Ser. port 2 UART Read */
-        DMA_Ser2HSSPWr = DDAR_Ser2HSSPWr,  /* Ser. port 2 HSSP Write */
-        DMA_Ser2HSSPRd = DDAR_Ser2HSSPRd,  /* Ser. port 2 HSSP Read */
-        DMA_Ser3UARTWr = DDAR_Ser3UARTWr,  /* Ser. port 3 UART Write */
-        DMA_Ser3UARTRd = DDAR_Ser3UARTRd,  /* Ser. port 3 UART Read */
-        DMA_Ser4MCP0Wr = DDAR_Ser4MCP0Wr,  /* Ser. port 4 MCP 0 Write (audio) */
-        DMA_Ser4MCP0Rd = DDAR_Ser4MCP0Rd,  /* Ser. port 4 MCP 0 Read (audio) */
-        DMA_Ser4MCP1Wr = DDAR_Ser4MCP1Wr,  /* Ser. port 4 MCP 1 Write */
-        DMA_Ser4MCP1Rd = DDAR_Ser4MCP1Rd,  /* Ser. port 4 MCP 1 Read */
-        DMA_Ser4SSPWr  = DDAR_Ser4SSPWr,   /* Ser. port 4 SSP Write (16 bits) */
-        DMA_Ser4SSPRd  = DDAR_Ser4SSPRd    /* Ser. port 4 SSP Read (16 bits) */
-} dma_device_t;
-
-typedef struct {
-        volatile u_long DDAR;
-        volatile u_long SetDCSR;
-        volatile u_long ClrDCSR;
-        volatile u_long RdDCSR;
-        volatile dma_addr_t DBSA;
-        volatile u_long DBTA;
-        volatile dma_addr_t DBSB;
-        volatile u_long DBTB;
-} dma_regs_t;
-
-typedef void (*dma_callback_t)(void *data);
-
-/*
- * DMA function prototypes
- */
-
-extern int sa1100_request_dma( dma_device_t device, const char *device_id,
-                               dma_callback_t callback, void *data,
-                               dma_regs_t **regs );
-extern void sa1100_free_dma( dma_regs_t *regs );
-extern int sa1100_start_dma( dma_regs_t *regs, dma_addr_t dma_ptr, u_int size );
-extern dma_addr_t sa1100_get_dma_pos(dma_regs_t *regs);
-extern void sa1100_reset_dma(dma_regs_t *regs);
-
-/**
- *      sa1100_stop_dma - stop DMA in progress
- *      @regs: identifier for the channel to use
- *
- *      This stops DMA without clearing buffer pointers. Unlike
- *      sa1100_clear_dma() this allows subsequent use of sa1100_resume_dma()
- *      or sa1100_get_dma_pos().
- *
- *      The @regs identifier is provided by a successful call to
- *      sa1100_request_dma().
- **/
-
-#define sa1100_stop_dma(regs)   ((regs)->ClrDCSR = DCSR_IE|DCSR_RUN)
-
-/**
- *      sa1100_resume_dma - resume DMA on a stopped channel
- *      @regs: identifier for the channel to use
- *
- *      This resumes DMA on a channel previously stopped with
- *      sa1100_stop_dma().
- *
- *      The @regs identifier is provided by a successful call to
- *      sa1100_request_dma().
- **/
-
-#define sa1100_resume_dma(regs) ((regs)->SetDCSR = DCSR_IE|DCSR_RUN)
-
-/**
- *      sa1100_clear_dma - clear DMA pointers
- *      @regs: identifier for the channel to use
- *
- *      This clear any DMA state so the DMA engine is ready to restart
- *      with new buffers through sa1100_start_dma(). Any buffers in flight
- *      are discarded.
- *
- *      The @regs identifier is provided by a successful call to
- *      sa1100_request_dma().
- **/
-
-#define sa1100_clear_dma(regs)  ((regs)->ClrDCSR = DCSR_IE|DCSR_RUN|DCSR_STRTA|DCSR_STRTB)
-
-#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-sa1100/entry-macro.S b/include/asm-arm/arch-sa1100/entry-macro.S
deleted file mode 100644
index 127db4aaf4f2..000000000000
--- a/include/asm-arm/arch-sa1100/entry-macro.S
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * include/asm-arm/arch-sa1100/entry-macro.S
- *
- * Low-level IRQ helper macros for SA1100-based platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  get_irqnr_preamble, base, tmp
-                mov     \base, #0xfa000000              @ ICIP = 0xfa050000
-                add     \base, \base, #0x00050000
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \irqstat, [\base]               @ get irqs
-                ldr     \irqnr, [\base, #4]             @ ICMR = 0xfa050004
-                ands    \irqstat, \irqstat, \irqnr
-                mov     \irqnr, #0
-                beq     1001f
-                tst     \irqstat, #0xff
-                moveq   \irqstat, \irqstat, lsr #8
-                addeq   \irqnr, \irqnr, #8
-                tsteq   \irqstat, #0xff
-                moveq   \irqstat, \irqstat, lsr #8
-                addeq   \irqnr, \irqnr, #8
-                tsteq   \irqstat, #0xff
-                moveq   \irqstat, \irqstat, lsr #8
-                addeq   \irqnr, \irqnr, #8
-                tst     \irqstat, #0x0f
-                moveq   \irqstat, \irqstat, lsr #4
-                addeq   \irqnr, \irqnr, #4
-                tst     \irqstat, #0x03
-                moveq   \irqstat, \irqstat, lsr #2
-                addeq   \irqnr, \irqnr, #2
-                tst     \irqstat, #0x01
-                addeqs  \irqnr, \irqnr, #1
-1001:
-                .endm
-
diff --git a/include/asm-arm/arch-sa1100/gpio.h b/include/asm-arm/arch-sa1100/gpio.h
deleted file mode 100644
index e66ecf74e807..000000000000
--- a/include/asm-arm/arch-sa1100/gpio.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * linux/include/asm-arm/arch-sa1100/gpio.h
- *
- * SA1100 GPIO wrappers for arch-neutral GPIO calls
- *
- * Written by Philipp Zabel <philipp.zabel@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-#ifndef __ASM_ARCH_SA1100_GPIO_H
-#define __ASM_ARCH_SA1100_GPIO_H
-
-#include <asm/arch/hardware.h>
-#include <asm/irq.h>
-#include <asm-generic/gpio.h>
-
-static inline int gpio_get_value(unsigned gpio)
-{
-        if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX))
-                return GPLR & GPIO_GPIO(gpio);
-        else
-                return __gpio_get_value(gpio);
-}
-
-static inline void gpio_set_value(unsigned gpio, int value)
-{
-        if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX))
-                if (value)
-                        GPSR = GPIO_GPIO(gpio);
-                else
-                        GPCR = GPIO_GPIO(gpio);
-        else
-                __gpio_set_value(gpio, value);
-}
-
-#define gpio_cansleep   __gpio_cansleep
-
-static inline unsigned gpio_to_irq(unsigned gpio)
-{
-        if (gpio < 11)
-                return IRQ_GPIO0 + gpio;
-        else
-                return IRQ_GPIO11 - 11 + gpio;
-}
-
-static inline unsigned irq_to_gpio(unsigned irq)
-{
-        if (irq < IRQ_GPIO11_27)
-                return irq - IRQ_GPIO0;
-        else
-                return irq - IRQ_GPIO11 + 11;
-}
-
-#endif
diff --git a/include/asm-arm/arch-sa1100/hardware.h b/include/asm-arm/arch-sa1100/hardware.h
deleted file mode 100644
index 1abd7cfc8bce..000000000000
--- a/include/asm-arm/arch-sa1100/hardware.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * linux/include/asm-arm/arch-sa1100/hardware.h
- *
- * Copyright (C) 1998 Nicolas Pitre <nico@cam.org>
- *
- * This file contains the hardware definitions for SA1100 architecture
- *
- * 2000/05/23 John Dorsey <john+@cs.cmu.edu>
- *      Definitions for SA1111 added.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-
-#define UNCACHEABLE_ADDR        0xfa050000
-
-
-/*
- * SA1100 internal I/O mappings
- *
- * We have the following mapping:
- *      phys            virt
- *      80000000        f8000000
- *      90000000        fa000000
- *      a0000000        fc000000
- *      b0000000        fe000000
- */
-
-#define VIO_BASE        0xf8000000      /* virtual start of IO space */
-#define VIO_SHIFT       3               /* x = IO space shrink power */
-#define PIO_START       0x80000000      /* physical start of IO space */
-
-#define io_p2v( x )             \
-   ( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE )
-#define io_v2p( x )             \
-   ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START )
-
-#ifndef __ASSEMBLY__
-
-# define __REG(x)       (*((volatile unsigned long *)io_p2v(x)))
-# define __PREG(x)      (io_v2p((unsigned long)&(x)))
-
-#else
-
-# define __REG(x)       io_p2v(x)
-# define __PREG(x)      io_v2p(x)
-
-#endif
-
-#include "SA-1100.h"
-
-#ifdef CONFIG_SA1101
-#include "SA-1101.h"
-#endif
-
-#endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-sa1100/ide.h b/include/asm-arm/arch-sa1100/ide.h
deleted file mode 100644
index 24972f30195a..000000000000
--- a/include/asm-arm/arch-sa1100/ide.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * linux/include/asm-arm/arch-sa1100/ide.h
- *
- * Copyright (c) 1998 Hugo Fiennes & Nicolas Pitre
- *
- * 18-aug-2000: Cleanup by Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
- *              Get rid of the special ide_init_hwif_ports() functions
- *              and make a generalised function that can be used by all
- *              architectures.
- */
-
-#include <asm/irq.h>
-#include <asm/arch/hardware.h>
-#include <asm/mach-types.h>
-
-#error "This code is broken and needs update to match with current ide support"
-
-
-/*
- * Set up a hw structure for a specified data port, control port and IRQ.
- * This should follow whatever the default interface uses.
- */
-static inline void ide_init_hwif_ports(hw_regs_t *hw, unsigned long data_port,
-                                       unsigned long ctrl_port, int *irq)
-{
-        unsigned long reg = data_port;
-        int i;
-        int regincr = 1;
-
-        /* The Empeg board has the first two address lines unused */
-        if (machine_is_empeg())
-                regincr = 1 << 2;
-
-        /* The LART doesn't use A0 for IDE */
-        if (machine_is_lart())
-                regincr = 1 << 1;
-
-        memset(hw, 0, sizeof(*hw));
-
-        for (i = 0; i <= 7; i++) {
-                hw->io_ports_array[i] = reg;
-                reg += regincr;
-        }
-
-        hw->io_ports.ctl_addr = ctrl_port;
-
-        if (irq)
-                *irq = 0;
-}
-
-/*
- * This registers the standard ports for this architecture with the IDE
- * driver.
- */
-static __inline__ void
-ide_init_default_hwifs(void)
-{
-    if (machine_is_lart()) {
-#ifdef CONFIG_SA1100_LART
-        hw_regs_t hw;
-
-        /* Enable GPIO as interrupt line */
-        GPDR &= ~LART_GPIO_IDE;
-        set_irq_type(LART_IRQ_IDE, IRQ_TYPE_EDGE_RISING);
-
-        /* set PCMCIA interface timing */
-        MECR = 0x00060006;
-
-        /* init the interface */
-        ide_init_hwif_ports(&hw, PCMCIA_IO_0_BASE + 0x0000, PCMCIA_IO_0_BASE + 0x1000, NULL);
-        hw.irq = LART_IRQ_IDE;
-        ide_register_hw(&hw);
-#endif
-    }
-}
diff --git a/include/asm-arm/arch-sa1100/io.h b/include/asm-arm/arch-sa1100/io.h
deleted file mode 100644
index 0756269404b1..000000000000
--- a/include/asm-arm/arch-sa1100/io.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * linux/include/asm-arm/arch-sa1100/io.h
- *
- * Copyright (C) 1997-1999 Russell King
- *
- * Modifications:
- *  06-12-1997  RMK     Created.
- *  07-04-1999  RMK     Major cleanup
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/*
- * We don't actually have real ISA nor PCI buses, but there is so many 
- * drivers out there that might just work if we fake them...
- */
-static inline void __iomem *__io(unsigned long addr)
-{
-        return (void __iomem *)addr;
-}
-#define __io(a)                 __io(a)
-#define __mem_pci(a)            (a)
-
-#endif
diff --git a/include/asm-arm/arch-sa1100/irqs.h b/include/asm-arm/arch-sa1100/irqs.h
deleted file mode 100644
index 7bf80484bb77..000000000000
--- a/include/asm-arm/arch-sa1100/irqs.h
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * linux/include/asm-arm/arch-sa1100/irqs.h
- *
- * Copyright (C) 1996 Russell King
- * Copyright (C) 1998 Deborah Wallach (updates for SA1100/Brutus).
- * Copyright (C) 1999 Nicolas Pitre (full GPIO irq isolation)
- *
- * 2001/11/14   RMK     Cleaned up and standardised a lot of the IRQs.
- */
-
-#define IRQ_GPIO0               0
-#define IRQ_GPIO1               1
-#define IRQ_GPIO2               2
-#define IRQ_GPIO3               3
-#define IRQ_GPIO4               4
-#define IRQ_GPIO5               5
-#define IRQ_GPIO6               6
-#define IRQ_GPIO7               7
-#define IRQ_GPIO8               8
-#define IRQ_GPIO9               9
-#define IRQ_GPIO10              10
-#define IRQ_GPIO11_27           11
-#define IRQ_LCD                 12      /* LCD controller           */
-#define IRQ_Ser0UDC             13      /* Ser. port 0 UDC          */
-#define IRQ_Ser1SDLC            14      /* Ser. port 1 SDLC         */
-#define IRQ_Ser1UART            15      /* Ser. port 1 UART         */
-#define IRQ_Ser2ICP             16      /* Ser. port 2 ICP          */
-#define IRQ_Ser3UART            17      /* Ser. port 3 UART         */
-#define IRQ_Ser4MCP             18      /* Ser. port 4 MCP          */
-#define IRQ_Ser4SSP             19      /* Ser. port 4 SSP          */
-#define IRQ_DMA0                20      /* DMA controller channel 0 */
-#define IRQ_DMA1                21      /* DMA controller channel 1 */
-#define IRQ_DMA2                22      /* DMA controller channel 2 */
-#define IRQ_DMA3                23      /* DMA controller channel 3 */
-#define IRQ_DMA4                24      /* DMA controller channel 4 */
-#define IRQ_DMA5                25      /* DMA controller channel 5 */
-#define IRQ_OST0                26      /* OS Timer match 0         */
-#define IRQ_OST1                27      /* OS Timer match 1         */
-#define IRQ_OST2                28      /* OS Timer match 2         */
-#define IRQ_OST3                29      /* OS Timer match 3         */
-#define IRQ_RTC1Hz              30      /* RTC 1 Hz clock           */
-#define IRQ_RTCAlrm             31      /* RTC Alarm                */
-
-#define IRQ_GPIO11              32
-#define IRQ_GPIO12              33
-#define IRQ_GPIO13              34
-#define IRQ_GPIO14              35
-#define IRQ_GPIO15              36
-#define IRQ_GPIO16              37
-#define IRQ_GPIO17              38
-#define IRQ_GPIO18              39
-#define IRQ_GPIO19              40
-#define IRQ_GPIO20              41
-#define IRQ_GPIO21              42
-#define IRQ_GPIO22              43
-#define IRQ_GPIO23              44
-#define IRQ_GPIO24              45
-#define IRQ_GPIO25              46
-#define IRQ_GPIO26              47
-#define IRQ_GPIO27              48
-
-/*
- * The next 16 interrupts are for board specific purposes.  Since
- * the kernel can only run on one machine at a time, we can re-use
- * these.  If you need more, increase IRQ_BOARD_END, but keep it
- * within sensible limits.  IRQs 49 to 64 are available.
- */
-#define IRQ_BOARD_START         49
-#define IRQ_BOARD_END           65
-
-#define IRQ_SA1111_START        (IRQ_BOARD_END)
-#define IRQ_GPAIN0              (IRQ_BOARD_END + 0)
-#define IRQ_GPAIN1              (IRQ_BOARD_END + 1)
-#define IRQ_GPAIN2              (IRQ_BOARD_END + 2)
-#define IRQ_GPAIN3              (IRQ_BOARD_END + 3)
-#define IRQ_GPBIN0              (IRQ_BOARD_END + 4)
-#define IRQ_GPBIN1              (IRQ_BOARD_END + 5)
-#define IRQ_GPBIN2              (IRQ_BOARD_END + 6)
-#define IRQ_GPBIN3              (IRQ_BOARD_END + 7)
-#define IRQ_GPBIN4              (IRQ_BOARD_END + 8)
-#define IRQ_GPBIN5              (IRQ_BOARD_END + 9)
-#define IRQ_GPCIN0              (IRQ_BOARD_END + 10)
-#define IRQ_GPCIN1              (IRQ_BOARD_END + 11)
-#define IRQ_GPCIN2              (IRQ_BOARD_END + 12)
-#define IRQ_GPCIN3              (IRQ_BOARD_END + 13)
-#define IRQ_GPCIN4              (IRQ_BOARD_END + 14)
-#define IRQ_GPCIN5              (IRQ_BOARD_END + 15)
-#define IRQ_GPCIN6              (IRQ_BOARD_END + 16)
-#define IRQ_GPCIN7              (IRQ_BOARD_END + 17)
-#define IRQ_MSTXINT             (IRQ_BOARD_END + 18)
-#define IRQ_MSRXINT             (IRQ_BOARD_END + 19)
-#define IRQ_MSSTOPERRINT        (IRQ_BOARD_END + 20)
-#define IRQ_TPTXINT             (IRQ_BOARD_END + 21)
-#define IRQ_TPRXINT             (IRQ_BOARD_END + 22)
-#define IRQ_TPSTOPERRINT        (IRQ_BOARD_END + 23)
-#define SSPXMTINT               (IRQ_BOARD_END + 24)
-#define SSPRCVINT               (IRQ_BOARD_END + 25)
-#define SSPROR                  (IRQ_BOARD_END + 26)
-#define AUDXMTDMADONEA          (IRQ_BOARD_END + 32)
-#define AUDRCVDMADONEA          (IRQ_BOARD_END + 33)
-#define AUDXMTDMADONEB          (IRQ_BOARD_END + 34)
-#define AUDRCVDMADONEB          (IRQ_BOARD_END + 35)
-#define AUDTFSR                 (IRQ_BOARD_END + 36)
-#define AUDRFSR                 (IRQ_BOARD_END + 37)
-#define AUDTUR                  (IRQ_BOARD_END + 38)
-#define AUDROR                  (IRQ_BOARD_END + 39)
-#define AUDDTS                  (IRQ_BOARD_END + 40)
-#define AUDRDD                  (IRQ_BOARD_END + 41)
-#define AUDSTO                  (IRQ_BOARD_END + 42)
-#define IRQ_USBPWR              (IRQ_BOARD_END + 43)
-#define IRQ_HCIM                (IRQ_BOARD_END + 44)
-#define IRQ_HCIBUFFACC          (IRQ_BOARD_END + 45)
-#define IRQ_HCIRMTWKP           (IRQ_BOARD_END + 46)
-#define IRQ_NHCIMFCIR           (IRQ_BOARD_END + 47)
-#define IRQ_USB_PORT_RESUME     (IRQ_BOARD_END + 48)
-#define IRQ_S0_READY_NINT       (IRQ_BOARD_END + 49)
-#define IRQ_S1_READY_NINT       (IRQ_BOARD_END + 50)
-#define IRQ_S0_CD_VALID         (IRQ_BOARD_END + 51)
-#define IRQ_S1_CD_VALID         (IRQ_BOARD_END + 52)
-#define IRQ_S0_BVD1_STSCHG      (IRQ_BOARD_END + 53)
-#define IRQ_S1_BVD1_STSCHG      (IRQ_BOARD_END + 54)
-
-#define IRQ_LOCOMO_START        (IRQ_BOARD_END)
-#define IRQ_LOCOMO_KEY          (IRQ_BOARD_END + 0)
-#define IRQ_LOCOMO_GPIO0        (IRQ_BOARD_END + 1)
-#define IRQ_LOCOMO_GPIO1        (IRQ_BOARD_END + 2)
-#define IRQ_LOCOMO_GPIO2        (IRQ_BOARD_END + 3)
-#define IRQ_LOCOMO_GPIO3        (IRQ_BOARD_END + 4)
-#define IRQ_LOCOMO_GPIO4        (IRQ_BOARD_END + 5)
-#define IRQ_LOCOMO_GPIO5        (IRQ_BOARD_END + 6)
-#define IRQ_LOCOMO_GPIO6        (IRQ_BOARD_END + 7)
-#define IRQ_LOCOMO_GPIO7        (IRQ_BOARD_END + 8)
-#define IRQ_LOCOMO_GPIO8        (IRQ_BOARD_END + 9)
-#define IRQ_LOCOMO_GPIO9        (IRQ_BOARD_END + 10)
-#define IRQ_LOCOMO_GPIO10       (IRQ_BOARD_END + 11)
-#define IRQ_LOCOMO_GPIO11       (IRQ_BOARD_END + 12)
-#define IRQ_LOCOMO_GPIO12       (IRQ_BOARD_END + 13)
-#define IRQ_LOCOMO_GPIO13       (IRQ_BOARD_END + 14)
-#define IRQ_LOCOMO_GPIO14       (IRQ_BOARD_END + 15)
-#define IRQ_LOCOMO_GPIO15       (IRQ_BOARD_END + 16)
-#define IRQ_LOCOMO_LT           (IRQ_BOARD_END + 17)
-#define IRQ_LOCOMO_SPI_RFR      (IRQ_BOARD_END + 18)
-#define IRQ_LOCOMO_SPI_RFW      (IRQ_BOARD_END + 19)
-#define IRQ_LOCOMO_SPI_REND     (IRQ_BOARD_END + 20)
-#define IRQ_LOCOMO_SPI_TEND     (IRQ_BOARD_END + 21)
-
-/*
- * Figure out the MAX IRQ number.
- *
- * If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1.
- * If we have an LoCoMo, the max IRQ is IRQ_LOCOMO_SPI_TEND+1
- * Otherwise, we have the standard IRQs only.
- */
-#ifdef CONFIG_SA1111
-#define NR_IRQS                 (IRQ_S1_BVD1_STSCHG + 1)
-#elif defined(CONFIG_SA1100_H3800)
-#define NR_IRQS                 (IRQ_BOARD_END)
-#elif defined(CONFIG_SHARP_LOCOMO)
-#define NR_IRQS                 (IRQ_LOCOMO_SPI_TEND + 1)
-#else
-#define NR_IRQS                 (IRQ_BOARD_START)
-#endif
-
-/*
- * Board specific IRQs.  Define them here.
- * Do not surround them with ifdefs.
- */
-#define IRQ_NEPONSET_SMC9196    (IRQ_BOARD_START + 0)
-#define IRQ_NEPONSET_USAR       (IRQ_BOARD_START + 1)
-#define IRQ_NEPONSET_SA1111     (IRQ_BOARD_START + 2)
-
-/* LoCoMo Interrupts (CONFIG_SHARP_LOCOMO) */
-#define IRQ_LOCOMO_KEY_BASE     (IRQ_BOARD_START + 0)
-#define IRQ_LOCOMO_GPIO_BASE    (IRQ_BOARD_START + 1)
-#define IRQ_LOCOMO_LT_BASE      (IRQ_BOARD_START + 2)
-#define IRQ_LOCOMO_SPI_BASE     (IRQ_BOARD_START + 3)
-
-/* H3800-specific IRQs (CONFIG_SA1100_H3800) */
-#define H3800_KPIO_IRQ_START    (IRQ_BOARD_START)
-#define IRQ_H3800_KEY           (IRQ_BOARD_START + 0)
-#define IRQ_H3800_SPI           (IRQ_BOARD_START + 1)
-#define IRQ_H3800_OWM           (IRQ_BOARD_START + 2)
-#define IRQ_H3800_ADC           (IRQ_BOARD_START + 3)
-#define IRQ_H3800_UART_0        (IRQ_BOARD_START + 4)
-#define IRQ_H3800_UART_1        (IRQ_BOARD_START + 5)
-#define IRQ_H3800_TIMER_0       (IRQ_BOARD_START + 6)
-#define IRQ_H3800_TIMER_1       (IRQ_BOARD_START + 7)
-#define IRQ_H3800_TIMER_2       (IRQ_BOARD_START + 8)
-#define H3800_KPIO_IRQ_COUNT    9
-
-#define H3800_GPIO_IRQ_START    (IRQ_BOARD_START + 9)
-#define IRQ_H3800_PEN           (IRQ_BOARD_START + 9)
-#define IRQ_H3800_SD_DETECT     (IRQ_BOARD_START + 10)
-#define IRQ_H3800_EAR_IN        (IRQ_BOARD_START + 11)
-#define IRQ_H3800_USB_DETECT    (IRQ_BOARD_START + 12)
-#define IRQ_H3800_SD_CON_SLT    (IRQ_BOARD_START + 13)
-#define H3800_GPIO_IRQ_COUNT    5
diff --git a/include/asm-arm/arch-sa1100/jornada720.h b/include/asm-arm/arch-sa1100/jornada720.h
deleted file mode 100644
index 45d2bb59f9d0..000000000000
--- a/include/asm-arm/arch-sa1100/jornada720.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * include/asm-arm/arch-sa1100/jornada720.h
- *
- * This file contains SSP/MCU communication definitions for HP Jornada 710/720/728
- *
- * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
- *  Copyright (C) 2000 John Ankcorn <jca@lcs.mit.edu>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
- /* HP Jornada 7xx microprocessor commands */
-#define GETBATTERYDATA          0xc0
-#define GETSCANKEYCODE          0x90
-#define GETTOUCHSAMPLES         0xa0
-#define GETCONTRAST             0xD0
-#define SETCONTRAST             0xD1
-#define GETBRIGHTNESS           0xD2
-#define SETBRIGHTNESS           0xD3
-#define CONTRASTOFF             0xD8
-#define BRIGHTNESSOFF           0xD9
-#define PWMOFF                  0xDF
-#define TXDUMMY                 0x11
-#define ERRORCODE               0x00
diff --git a/include/asm-arm/arch-sa1100/mcp.h b/include/asm-arm/arch-sa1100/mcp.h
deleted file mode 100644
index f58a22755c61..000000000000
--- a/include/asm-arm/arch-sa1100/mcp.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-sa1100/mcp.h
- *
- *  Copyright (C) 2005 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_ARM_ARCH_MCP_H
-#define __ASM_ARM_ARCH_MCP_H
-
-#include <linux/types.h>
-
-struct mcp_plat_data {
-        u32 mccr0;
-        u32 mccr1;
-        unsigned int sclk_rate;
-};
-
-#endif
diff --git a/include/asm-arm/arch-sa1100/memory.h b/include/asm-arm/arch-sa1100/memory.h
deleted file mode 100644
index 0e907fc6d42a..000000000000
--- a/include/asm-arm/arch-sa1100/memory.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * linux/include/asm-arm/arch-sa1100/memory.h
- *
- * Copyright (C) 1999-2000 Nicolas Pitre <nico@cam.org>
- */
-
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-#include <asm/sizes.h>
-
-/*
- * Physical DRAM offset is 0xc0000000 on the SA1100
- */
-#define PHYS_OFFSET     UL(0xc0000000)
-
-#ifndef __ASSEMBLY__
-
-#ifdef CONFIG_SA1111
-void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes);
-
-#define arch_adjust_zones(node, size, holes) \
-        sa1111_adjust_zones(node, size, holes)
-
-#define ISA_DMA_THRESHOLD       (PHYS_OFFSET + SZ_1M - 1)
-
-#endif
-#endif
-
-/*
- * Virtual view <-> DMA view memory address translations
- * virt_to_bus: Used to translate the virtual address to an
- *              address suitable to be passed to set_dma_addr
- * bus_to_virt: Used to convert an address for DMA operations
- *              to an address that the kernel can use.
- *
- * On the SA1100, bus addresses are equivalent to physical addresses.
- */
-#define __virt_to_bus(x)         __virt_to_phys(x)
-#define __bus_to_virt(x)         __phys_to_virt(x)
-
-/*
- * Because of the wide memory address space between physical RAM banks on the 
- * SA1100, it's much convenient to use Linux's NUMA support to implement our 
- * memory map representation.  Assuming all memory nodes have equal access 
- * characteristics, we then have generic discontiguous memory support.
- *
- * Of course, all this isn't mandatory for SA1100 implementations with only
- * one used memory bank.  For those, simply undefine CONFIG_DISCONTIGMEM.
- *
- * The nodes are matched with the physical memory bank addresses which are 
- * incidentally the same as virtual addresses.
- * 
- *      node 0:  0xc0000000 - 0xc7ffffff
- *      node 1:  0xc8000000 - 0xcfffffff
- *      node 2:  0xd0000000 - 0xd7ffffff
- *      node 3:  0xd8000000 - 0xdfffffff
- */
-#define NODE_MEM_SIZE_BITS      27
-
-/*
- * Cache flushing area - SA1100 zero bank
- */
-#define FLUSH_BASE_PHYS         0xe0000000
-#define FLUSH_BASE              0xf5000000
-#define FLUSH_BASE_MINICACHE    0xf5100000
-
-#endif
diff --git a/include/asm-arm/arch-sa1100/neponset.h b/include/asm-arm/arch-sa1100/neponset.h
deleted file mode 100644
index 09ec9e2bd182..000000000000
--- a/include/asm-arm/arch-sa1100/neponset.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * linux/include/asm-arm/arch-sa1100/neponset.h
- *
- * Created 2000/06/05 by Nicolas Pitre <nico@cam.org>
- *
- * This file contains the hardware specific definitions for Assabet
- * Only include this file from SA1100-specific files.
- *
- * 2000/05/23 John Dorsey <john+@cs.cmu.edu>
- *      Definitions for Neponset added.
- */
-#ifndef __ASM_ARCH_NEPONSET_H
-#define __ASM_ARCH_NEPONSET_H
-
-/*
- * Neponset definitions: 
- */
-
-#define NEPONSET_CPLD_BASE      (0x10000000)
-#define Nep_p2v( x )            ((x) - NEPONSET_CPLD_BASE + 0xf3000000)
-#define Nep_v2p( x )            ((x) - 0xf3000000 + NEPONSET_CPLD_BASE)
-
-#define _IRR                    0x10000024      /* Interrupt Reason Register */
-#define _AUD_CTL                0x100000c0      /* Audio controls (RW)       */
-#define _MDM_CTL_0              0x100000b0      /* Modem control 0 (RW)      */
-#define _MDM_CTL_1              0x100000b4      /* Modem control 1 (RW)      */
-#define _NCR_0                  0x100000a0      /* Control Register (RW)     */
-#define _KP_X_OUT               0x10000090      /* Keypad row write (RW)     */
-#define _KP_Y_IN                0x10000080      /* Keypad column read (RO)   */
-#define _SWPK                   0x10000020      /* Switch pack (RO)          */
-#define _WHOAMI                 0x10000000      /* System ID Register (RO)   */
-
-#define _LEDS                   0x10000010      /* LEDs [31:0] (WO)          */
-
-#define IRR                     (*((volatile u_char *) Nep_p2v(_IRR)))
-#define AUD_CTL                 (*((volatile u_char *) Nep_p2v(_AUD_CTL)))
-#define MDM_CTL_0               (*((volatile u_char *) Nep_p2v(_MDM_CTL_0)))
-#define MDM_CTL_1               (*((volatile u_char *) Nep_p2v(_MDM_CTL_1)))
-#define NCR_0                   (*((volatile u_char *) Nep_p2v(_NCR_0)))
-#define KP_X_OUT                (*((volatile u_char *) Nep_p2v(_KP_X_OUT)))
-#define KP_Y_IN                 (*((volatile u_char *) Nep_p2v(_KP_Y_IN)))
-#define SWPK                    (*((volatile u_char *) Nep_p2v(_SWPK)))
-#define WHOAMI                  (*((volatile u_char *) Nep_p2v(_WHOAMI)))
-
-#define LEDS                    (*((volatile Word   *) Nep_p2v(_LEDS)))
-
-#define IRR_ETHERNET            (1<<0)
-#define IRR_USAR                (1<<1)
-#define IRR_SA1111              (1<<2)
-
-#define AUD_SEL_1341            (1<<0)
-#define AUD_MUTE_1341           (1<<1)
-
-#define MDM_CTL0_RTS1           (1 << 0)
-#define MDM_CTL0_DTR1           (1 << 1)
-#define MDM_CTL0_RTS2           (1 << 2)
-#define MDM_CTL0_DTR2           (1 << 3)
-
-#define MDM_CTL1_CTS1           (1 << 0)
-#define MDM_CTL1_DSR1           (1 << 1)
-#define MDM_CTL1_DCD1           (1 << 2)
-#define MDM_CTL1_CTS2           (1 << 3)
-#define MDM_CTL1_DSR2           (1 << 4)
-#define MDM_CTL1_DCD2           (1 << 5)
-
-#define NCR_GP01_OFF            (1<<0)
-#define NCR_TP_PWR_EN           (1<<1)
-#define NCR_MS_PWR_EN           (1<<2)
-#define NCR_ENET_OSC_EN         (1<<3)
-#define NCR_SPI_KB_WK_UP        (1<<4)
-#define NCR_A0VPP               (1<<5)
-#define NCR_A1VPP               (1<<6)
-
-#endif
diff --git a/include/asm-arm/arch-sa1100/simpad.h b/include/asm-arm/arch-sa1100/simpad.h
deleted file mode 100644
index 034301d23f60..000000000000
--- a/include/asm-arm/arch-sa1100/simpad.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * linux/include/asm-arm/arch-sa1100/simpad.h
- *
- * based of assabet.h same as HUW_Webpanel
- *
- * This file contains the hardware specific definitions for SIMpad
- *
- * 2001/05/14 Juergen Messerer <juergen.messerer@freesurf.ch>
- */
-
-#ifndef __ASM_ARCH_SIMPAD_H
-#define __ASM_ARCH_SIMPAD_H
-
-
-#define GPIO_UART1_RTS  GPIO_GPIO14
-#define GPIO_UART1_DTR  GPIO_GPIO7
-#define GPIO_UART1_CTS  GPIO_GPIO8
-#define GPIO_UART1_DCD  GPIO_GPIO23
-#define GPIO_UART1_DSR  GPIO_GPIO6
-
-#define GPIO_UART3_RTS  GPIO_GPIO12
-#define GPIO_UART3_DTR  GPIO_GPIO16
-#define GPIO_UART3_CTS  GPIO_GPIO13
-#define GPIO_UART3_DCD  GPIO_GPIO18
-#define GPIO_UART3_DSR  GPIO_GPIO17
-
-#define GPIO_POWER_BUTTON       GPIO_GPIO0
-#define GPIO_UCB1300_IRQ        GPIO_GPIO22     /* UCB GPIO and touchscreen */
-
-#define IRQ_UART1_CTS   IRQ_GPIO15
-#define IRQ_UART1_DCD   GPIO_GPIO23
-#define IRQ_UART1_DSR   GPIO_GPIO6
-#define IRQ_UART3_CTS   GPIO_GPIO13
-#define IRQ_UART3_DCD   GPIO_GPIO18
-#define IRQ_UART3_DSR   GPIO_GPIO17
-
-#define IRQ_GPIO_UCB1300_IRQ IRQ_GPIO22
-#define IRQ_GPIO_POWER_BUTTON IRQ_GPIO0
-
-
-/*---  PCMCIA  ---*/
-#define GPIO_CF_CD              GPIO_GPIO24
-#define GPIO_CF_IRQ             GPIO_GPIO1
-#define IRQ_GPIO_CF_IRQ         IRQ_GPIO1
-#define IRQ_GPIO_CF_CD          IRQ_GPIO24
-
-/*--- SmartCard ---*/
-#define GPIO_SMART_CARD         GPIO_GPIO10
-#define IRQ_GPIO_SMARD_CARD     IRQ_GPIO10
-
-// CS3 Latch is write only, a shadow is necessary
-
-#define CS3BUSTYPE unsigned volatile long
-#define CS3_BASE        0xf1000000
-
-#define VCC_5V_EN       0x0001 // For 5V PCMCIA
-#define VCC_3V_EN       0x0002 // FOR 3.3V PCMCIA
-#define EN1             0x0004 // This is only for EPROM's
-#define EN0             0x0008 // Both should be enable for 3.3V or 5V
-#define DISPLAY_ON      0x0010
-#define PCMCIA_BUFF_DIS 0x0020
-#define MQ_RESET        0x0040
-#define PCMCIA_RESET    0x0080
-#define DECT_POWER_ON   0x0100
-#define IRDA_SD         0x0200 // Shutdown for powersave
-#define RS232_ON        0x0400
-#define SD_MEDIAQ       0x0800 // Shutdown for powersave
-#define LED2_ON         0x1000
-#define IRDA_MODE       0x2000 // Fast/Slow IrDA mode
-#define ENABLE_5V       0x4000 // Enable 5V circuit
-#define RESET_SIMCARD   0x8000
-
-#define RS232_ENABLE    0x0440
-#define PCMCIAMASK      0x402f
-
-
-struct simpad_battery {
-        unsigned char ac_status;        /* line connected yes/no */
-        unsigned char status;           /* battery loading yes/no */
-        unsigned char percentage;       /* percentage loaded */
-        unsigned short life;            /* life till empty */
-};
-
-/* These should match the apm_bios.h definitions */
-#define SIMPAD_AC_STATUS_AC_OFFLINE      0x00
-#define SIMPAD_AC_STATUS_AC_ONLINE       0x01
-#define SIMPAD_AC_STATUS_AC_BACKUP       0x02   /* What does this mean? */
-#define SIMPAD_AC_STATUS_AC_UNKNOWN      0xff
-
-/* These bitfields are rarely "or'd" together */
-#define SIMPAD_BATT_STATUS_HIGH          0x01
-#define SIMPAD_BATT_STATUS_LOW           0x02
-#define SIMPAD_BATT_STATUS_CRITICAL      0x04
-#define SIMPAD_BATT_STATUS_CHARGING      0x08
-#define SIMPAD_BATT_STATUS_CHARGE_MAIN   0x10
-#define SIMPAD_BATT_STATUS_DEAD          0x20   /* Battery will not charge */
-#define SIMPAD_BATT_NOT_INSTALLED        0x20   /* For expansion pack batteries */
-#define SIMPAD_BATT_STATUS_FULL          0x40   /* Battery fully charged (and connected to AC) */
-#define SIMPAD_BATT_STATUS_NOBATT        0x80
-#define SIMPAD_BATT_STATUS_UNKNOWN       0xff
-
-extern int simpad_get_battery(struct simpad_battery* );
-
-#endif // __ASM_ARCH_SIMPAD_H
-
-
-
-
-
-
-
-
diff --git a/include/asm-arm/arch-sa1100/system.h b/include/asm-arm/arch-sa1100/system.h
deleted file mode 100644
index 63375a0c0145..000000000000
--- a/include/asm-arm/arch-sa1100/system.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * linux/include/asm-arm/arch-sa1100/system.h
- *
- * Copyright (c) 1999 Nicolas Pitre <nico@cam.org>
- */
-#include <asm/arch/hardware.h>
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-static inline void arch_reset(char mode)
-{
-        if (mode == 's') {
-                /* Jump into ROM at address 0 */
-                cpu_reset(0);
-        } else {
-                /* Use on-chip reset capability */
-                RSRR = RSRR_SWR;
-        }
-}
diff --git a/include/asm-arm/arch-sa1100/timex.h b/include/asm-arm/arch-sa1100/timex.h
deleted file mode 100644
index 837be9b797dd..000000000000
--- a/include/asm-arm/arch-sa1100/timex.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * linux/include/asm-arm/arch-sa1100/timex.h
- *
- * SA1100 architecture timex specifications
- *
- * Copyright (C) 1998 
- */
-
-/*
- * SA1100 timer
- */
-#define CLOCK_TICK_RATE         3686400
diff --git a/include/asm-arm/arch-sa1100/uncompress.h b/include/asm-arm/arch-sa1100/uncompress.h
deleted file mode 100644
index 17e64d232e7d..000000000000
--- a/include/asm-arm/arch-sa1100/uncompress.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * linux/include/asm-arm/arch-sa1100/uncompress.h
- *
- * (C) 1999 Nicolas Pitre <nico@cam.org>
- *
- * Reorganised to be machine independent.
- */
-
-#include "hardware.h"
-
-/*
- * The following code assumes the serial port has already been
- * initialized by the bootloader.  We search for the first enabled
- * port in the most probable order.  If you didn't setup a port in
- * your bootloader then nothing will appear (which might be desired).
- */
-
-#define UART(x)         (*(volatile unsigned long *)(serial_port + (x)))
-
-static void putc(int c)
-{
-        unsigned long serial_port;
-
-        do {
-                serial_port = _Ser3UTCR0;
-                if (UART(UTCR3) & UTCR3_TXE) break;
-                serial_port = _Ser1UTCR0;
-                if (UART(UTCR3) & UTCR3_TXE) break;
-                serial_port = _Ser2UTCR0;
-                if (UART(UTCR3) & UTCR3_TXE) break;
-                return;
-        } while (0);
-
-        /* wait for space in the UART's transmitter */
-        while (!(UART(UTSR1) & UTSR1_TNF))
-                barrier();
-
-        /* send the character out. */
-        UART(UTDR) = c;
-}
-
-static inline void flush(void)
-{
-}
-
-/*
- * Nothing to do for these
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-sa1100/vmalloc.h b/include/asm-arm/arch-sa1100/vmalloc.h
deleted file mode 100644
index 2fb1c6f3aa1b..000000000000
--- a/include/asm-arm/arch-sa1100/vmalloc.h
+++ /dev/null
@@ -1,4 +0,0 @@
-/*
- * linux/include/asm-arm/arch-sa1100/vmalloc.h
- */
-#define VMALLOC_END       (0xe8000000)
diff --git a/include/asm-arm/arch-shark/debug-macro.S b/include/asm-arm/arch-shark/debug-macro.S
deleted file mode 100644
index 7cb37f78825e..000000000000
--- a/include/asm-arm/arch-shark/debug-macro.S
+++ /dev/null
@@ -1,31 +0,0 @@
-/* linux/include/asm-arm/arch-shark/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-                .macro  addruart,rx
-                mov     \rx, #0xe0000000
-                orr     \rx, \rx, #0x000003f8
-                .endm
-
-                .macro  senduart,rd,rx
-                strb    \rd, [\rx]
-                .endm
-
-                .macro  busyuart,rd,rx
-                mov     \rd, #0
-1001:           add     \rd, \rd, #1
-                teq     \rd, #0x10000
-                bne     1001b
-                .endm
-
-                .macro  waituart,rd,rx
-                .endm
diff --git a/include/asm-arm/arch-shark/dma.h b/include/asm-arm/arch-shark/dma.h
deleted file mode 100644
index fc985d5e62af..000000000000
--- a/include/asm-arm/arch-shark/dma.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * linux/include/asm-arm/arch-shark/dma.h
- *
- * by Alexander Schulz
- */
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-
-/* Use only the lowest 4MB, nothing else works.
- * The rest is not DMAable. See dev /  .properties
- * in OpenFirmware.
- */
-#define MAX_DMA_ADDRESS         0xC0400000
-#define MAX_DMA_CHANNELS        8
-#define DMA_ISA_CASCADE         4
-
-#endif /* _ASM_ARCH_DMA_H */
-
diff --git a/include/asm-arm/arch-shark/entry-macro.S b/include/asm-arm/arch-shark/entry-macro.S
deleted file mode 100644
index 82463f30f3df..000000000000
--- a/include/asm-arm/arch-shark/entry-macro.S
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * include/asm-arm/arch-shark/entry-macro.S
- *
- * Low-level IRQ helper macros for Shark platform
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-                .macro  disable_fiq
-                .endm
-
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                mov     r4, #0xe0000000
-
-                mov     \irqstat, #0x0C
-                strb    \irqstat, [r4, #0x20]           @outb(0x0C, 0x20) /* Poll command */
-                ldrb    \irqnr, [r4, #0x20]             @irq = inb(0x20) & 7
-                and     \irqstat, \irqnr, #0x80
-                teq     \irqstat, #0
-                beq     43f
-                and     \irqnr, \irqnr, #7
-                teq     \irqnr, #2
-                bne     44f
-43:             mov     \irqstat, #0x0C
-                strb    \irqstat, [r4, #0xa0]           @outb(0x0C, 0xA0) /* Poll command */
-                ldrb    \irqnr, [r4, #0xa0]             @irq = (inb(0xA0) & 7) + 8
-                and     \irqstat, \irqnr, #0x80
-                teq     \irqstat, #0
-                beq     44f
-                and     \irqnr, \irqnr, #7
-                add     \irqnr, \irqnr, #8
-44:             teq     \irqstat, #0
-                .endm
-
diff --git a/include/asm-arm/arch-shark/hardware.h b/include/asm-arm/arch-shark/hardware.h
deleted file mode 100644
index ecba45260898..000000000000
--- a/include/asm-arm/arch-shark/hardware.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * linux/include/asm-arm/arch-shark/hardware.h
- *
- * by Alexander Schulz
- *
- * derived from:
- * linux/include/asm-arm/arch-ebsa110/hardware.h
- * Copyright (C) 1996-1999 Russell King.
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#ifndef __ASSEMBLY__
-
-/*
- * Mapping areas
- */
-#define IO_BASE                 0xe0000000
-
-#else
-
-#define IO_BASE                 0
-
-#endif
-
-#define IO_SIZE                 0x08000000
-#define IO_START                0x40000000
-#define ROMCARD_SIZE            0x08000000
-#define ROMCARD_START           0x10000000
-
-#define PCIO_BASE               0xe0000000
-
-
-/* defines for the Framebuffer */
-#define FB_START                0x06000000
-#define FB_SIZE                 0x01000000
-
-#define UNCACHEABLE_ADDR        0xdf010000
-
-#define SEQUOIA_LED_GREEN       (1<<6)
-#define SEQUOIA_LED_AMBER       (1<<5)
-#define SEQUOIA_LED_BACK        (1<<7)
-
-#define pcibios_assign_all_busses()     1
-
-#define PCIBIOS_MIN_IO          0x6000
-#define PCIBIOS_MIN_MEM         0x50000000
-#define PCIMEM_BASE             0xe8000000
-
-#endif
-
diff --git a/include/asm-arm/arch-shark/io.h b/include/asm-arm/arch-shark/io.h
deleted file mode 100644
index b11d7860a9d3..000000000000
--- a/include/asm-arm/arch-shark/io.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * linux/include/asm-arm/arch-shark/io.h
- *
- * by Alexander Schulz
- *
- * derived from:
- * linux/include/asm-arm/arch-ebsa110/io.h
- * Copyright (C) 1997,1998 Russell King
- */
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#include <asm/arch/hardware.h>
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/*
- * We use two different types of addressing - PC style addresses, and ARM
- * addresses.  PC style accesses the PC hardware with the normal PC IO
- * addresses, eg 0x3f8 for serial#1.  ARM addresses are 0x80000000+
- * and are translated to the start of IO.
- */
-#define __PORT_PCIO(x)  (!((x) & 0x80000000))
-
-#define __io(a)                 ((void __iomem *)(PCIO_BASE + (a)))
-
-
-static inline unsigned int __ioaddr (unsigned int port)                 \
-{                                                                               \
-        if (__PORT_PCIO(port))                                                  \
-                return (unsigned int)(PCIO_BASE + (port));                      \
-        else                                                                    \
-                return (unsigned int)(IO_BASE + (port));                        \
-}
-
-#define __mem_pci(addr) (addr)
-
-/*
- * Translated address IO functions
- *
- * IO address has already been translated to a virtual address
- */
-#define outb_t(v,p)                                                             \
-        (*(volatile unsigned char *)(p) = (v))
-
-#define inb_t(p)                                                                \
-        (*(volatile unsigned char *)(p))
-
-#define outl_t(v,p)                                                             \
-        (*(volatile unsigned long *)(p) = (v))
-
-#define inl_t(p)                                                                \
-        (*(volatile unsigned long *)(p))
-
-#endif
diff --git a/include/asm-arm/arch-shark/irqs.h b/include/asm-arm/arch-shark/irqs.h
deleted file mode 100644
index b36cc975b290..000000000000
--- a/include/asm-arm/arch-shark/irqs.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * linux/include/asm-arm/arch-shark/irqs.h
- *
- * by Alexander Schulz
- */
-
-#define NR_IRQS                 16
-
-#define IRQ_ISA_KEYBOARD         1
-#define RTC_IRQ                  8
-#define I8042_KBD_IRQ            1
-#define I8042_AUX_IRQ           12
-#define IRQ_HARDDISK            14
diff --git a/include/asm-arm/arch-shark/memory.h b/include/asm-arm/arch-shark/memory.h
deleted file mode 100644
index 6968d6103ea0..000000000000
--- a/include/asm-arm/arch-shark/memory.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * linux/include/asm-arm/arch-shark/memory.h
- *
- * by Alexander Schulz
- *
- * derived from:
- * linux/include/asm-arm/arch-ebsa110/memory.h
- * Copyright (c) 1996-1999 Russell King.
- */
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-#include <asm/sizes.h>
-
-/*
- * Physical DRAM offset.
- */
-#define PHYS_OFFSET     UL(0x08000000)
-
-#ifndef __ASSEMBLY__
-
-static inline void __arch_adjust_zones(int node, unsigned long *zone_size, unsigned long *zhole_size) 
-{
-  if (node != 0) return;
-  /* Only the first 4 MB (=1024 Pages) are usable for DMA */
-  zone_size[1] = zone_size[0] - 1024;
-  zone_size[0] = 1024;
-  zhole_size[1] = zhole_size[0];
-  zhole_size[0] = 0;
-}
-
-#define arch_adjust_zones(node, size, holes) \
-        __arch_adjust_zones(node, size, holes)
-
-#define ISA_DMA_THRESHOLD       (PHYS_OFFSET + SZ_4M - 1)
-
-#endif
-
-#define __virt_to_bus(x)        __virt_to_phys(x)
-#define __bus_to_virt(x)        __phys_to_virt(x)
-
-/*
- * Cache flushing area
- */
-#define FLUSH_BASE_PHYS         0x80000000
-#define FLUSH_BASE              0xdf000000
-
-#endif
diff --git a/include/asm-arm/arch-shark/system.h b/include/asm-arm/arch-shark/system.h
deleted file mode 100644
index f12d771ab4ce..000000000000
--- a/include/asm-arm/arch-shark/system.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * linux/include/asm-arm/arch-shark/system.h
- *
- * by Alexander Schulz
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-#include <asm/io.h>
-
-static void arch_reset(char mode)
-{
-        short temp;
-        local_irq_disable();
-        /* Reset the Machine via pc[3] of the sequoia chipset */
-        outw(0x09,0x24);
-        temp=inw(0x26);
-        temp = temp | (1<<3) | (1<<10);
-        outw(0x09,0x24);
-        outw(temp,0x26);
-
-}
-
-static inline void arch_idle(void)
-{
-}
-
-#endif
diff --git a/include/asm-arm/arch-shark/timex.h b/include/asm-arm/arch-shark/timex.h
deleted file mode 100644
index 0d02d255513b..000000000000
--- a/include/asm-arm/arch-shark/timex.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * linux/include/asm-arm/arch-shark/timex.h
- *
- * by Alexander Schulz
- */
-
-#define CLOCK_TICK_RATE 1193180
diff --git a/include/asm-arm/arch-shark/uncompress.h b/include/asm-arm/arch-shark/uncompress.h
deleted file mode 100644
index 7eca6534f1bb..000000000000
--- a/include/asm-arm/arch-shark/uncompress.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * linux/include/asm-arm/arch-shark/uncompress.h
- * by Alexander Schulz
- *
- * derived from:
- * linux/include/asm-arm/arch-ebsa285/uncompress.h
- * Copyright (C) 1996,1997,1998 Russell King
- */
-
-#define SERIAL_BASE ((volatile unsigned char *)0x400003f8)
-
-static inline void putc(int c)
-{
-        int t;
-
-        SERIAL_BASE[0] = c;
-        t=0x10000;
-        while (t--);
-}
-
-static inline void flush(void)
-{
-}
-
-#ifdef DEBUG
-static void putn(unsigned long z)
-{
-        int i;
-        char x;
-
-        putc('0');
-        putc('x');
-        for (i=0;i<8;i++) {
-                x='0'+((z>>((7-i)*4))&0xf);
-                if (x>'9') x=x-'0'+'A'-10;
-                putc(x);
-        }
-}
-
-static void putr()
-{
-        putc('\n');
-        putc('\r');
-}
-#endif
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-shark/vmalloc.h b/include/asm-arm/arch-shark/vmalloc.h
deleted file mode 100644
index fac37c636b38..000000000000
--- a/include/asm-arm/arch-shark/vmalloc.h
+++ /dev/null
@@ -1,4 +0,0 @@
-/*
- * linux/include/asm-arm/arch-shark/vmalloc.h
- */
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
diff --git a/include/asm-arm/arch-versatile/debug-macro.S b/include/asm-arm/arch-versatile/debug-macro.S
deleted file mode 100644
index fe106d184e62..000000000000
--- a/include/asm-arm/arch-versatile/debug-macro.S
+++ /dev/null
@@ -1,23 +0,0 @@
-/* linux/include/asm-arm/arch-versatile/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-                .macro  addruart,rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx,      #0x10000000
-                movne   \rx,      #0xf1000000   @ virtual base
-                orr     \rx, \rx, #0x001F0000
-                orr     \rx, \rx, #0x00001000
-                .endm
-
-#include <asm/hardware/debug-pl01x.S>
diff --git a/include/asm-arm/arch-versatile/dma.h b/include/asm-arm/arch-versatile/dma.h
deleted file mode 100644
index 642577348623..000000000000
--- a/include/asm-arm/arch-versatile/dma.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-versatile/dma.h
- *
- *  Copyright (C) 2003 ARM Limited.
- *  Copyright (C) 1997,1998 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
diff --git a/include/asm-arm/arch-versatile/entry-macro.S b/include/asm-arm/arch-versatile/entry-macro.S
deleted file mode 100644
index cd114169c3e6..000000000000
--- a/include/asm-arm/arch-versatile/entry-macro.S
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * include/asm-arm/arch-versatile/entry-macro.S
- *
- * Low-level IRQ helper macros for Versatile platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <asm/arch/hardware.h>
-#include <asm/hardware/vic.h>
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  get_irqnr_preamble, base, tmp
-                ldr     \base, =IO_ADDRESS(VERSATILE_VIC_BASE)
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \irqstat, [\base, #VIC_IRQ_STATUS]      @ get masked status
-                mov     \irqnr, #0
-                teq     \irqstat, #0
-                beq     1003f
-
-1001:           tst     \irqstat, #15
-                bne     1002f
-                add     \irqnr, \irqnr, #4
-                movs    \irqstat, \irqstat, lsr #4
-                bne     1001b
-1002:           tst     \irqstat, #1
-                bne     1003f
-                add     \irqnr, \irqnr, #1
-                movs    \irqstat, \irqstat, lsr #1
-                bne     1002b
-1003:           /* EQ will be set if no irqs pending */
-
-@               clz     \irqnr, \irqstat
-@1003:          /* EQ will be set if we reach MAXIRQNUM */
-                .endm
-
diff --git a/include/asm-arm/arch-versatile/hardware.h b/include/asm-arm/arch-versatile/hardware.h
deleted file mode 100644
index edc06598d187..000000000000
--- a/include/asm-arm/arch-versatile/hardware.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-versatile/hardware.h
- *
- *  This file contains the hardware definitions of the Versatile boards.
- *
- *  Copyright (C) 2003 ARM Limited.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <asm/sizes.h>
-#include <asm/arch/platform.h>
-
-/*
- * PCI space virtual addresses
- */
-#define VERSATILE_PCI_VIRT_BASE         (void __iomem *)0xe8000000ul
-#define VERSATILE_PCI_CFG_VIRT_BASE     (void __iomem *)0xe9000000ul
-
-#if 0
-#define VERSATILE_PCI_VIRT_MEM_BASE0    0xf4000000
-#define VERSATILE_PCI_VIRT_MEM_BASE1    0xf5000000
-#define VERSATILE_PCI_VIRT_MEM_BASE2    0xf6000000
-
-#define PCIO_BASE                       VERSATILE_PCI_VIRT_MEM_BASE0
-#define PCIMEM_BASE                     VERSATILE_PCI_VIRT_MEM_BASE1
-#endif
-
-/* CIK guesswork */
-#define PCIBIOS_MIN_IO                  0x44000000
-#define PCIBIOS_MIN_MEM                 0x50000000
-
-#define pcibios_assign_all_busses()     1
-
-/* macro to get at IO space when running virtually */
-#define IO_ADDRESS(x)           (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
-
-#endif
diff --git a/include/asm-arm/arch-versatile/io.h b/include/asm-arm/arch-versatile/io.h
deleted file mode 100644
index c4d01948e00b..000000000000
--- a/include/asm-arm/arch-versatile/io.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-versatile/io.h
- *
- *  Copyright (C) 2003 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-static inline void __iomem *__io(unsigned long addr)
-{
-        return (void __iomem *)addr;
-}
-#define __io(a) __io(a)
-#define __mem_pci(a)            (a)
-
-#endif
diff --git a/include/asm-arm/arch-versatile/irqs.h b/include/asm-arm/arch-versatile/irqs.h
deleted file mode 100644
index f7263b99403b..000000000000
--- a/include/asm-arm/arch-versatile/irqs.h
+++ /dev/null
@@ -1,211 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-versatile/irqs.h
- *
- *  Copyright (C) 2003 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <asm/arch/platform.h>
-
-/* 
- *  IRQ interrupts definitions are the same as the INT definitions
- *  held within platform.h
- */
-#define IRQ_VIC_START           0
-#define IRQ_WDOGINT             (IRQ_VIC_START + INT_WDOGINT)
-#define IRQ_SOFTINT             (IRQ_VIC_START + INT_SOFTINT)
-#define IRQ_COMMRx              (IRQ_VIC_START + INT_COMMRx)
-#define IRQ_COMMTx              (IRQ_VIC_START + INT_COMMTx)
-#define IRQ_TIMERINT0_1         (IRQ_VIC_START + INT_TIMERINT0_1)
-#define IRQ_TIMERINT2_3         (IRQ_VIC_START + INT_TIMERINT2_3)
-#define IRQ_GPIOINT0            (IRQ_VIC_START + INT_GPIOINT0)
-#define IRQ_GPIOINT1            (IRQ_VIC_START + INT_GPIOINT1)
-#define IRQ_GPIOINT2            (IRQ_VIC_START + INT_GPIOINT2)
-#define IRQ_GPIOINT3            (IRQ_VIC_START + INT_GPIOINT3)
-#define IRQ_RTCINT              (IRQ_VIC_START + INT_RTCINT)
-#define IRQ_SSPINT              (IRQ_VIC_START + INT_SSPINT)
-#define IRQ_UARTINT0            (IRQ_VIC_START + INT_UARTINT0)
-#define IRQ_UARTINT1            (IRQ_VIC_START + INT_UARTINT1)
-#define IRQ_UARTINT2            (IRQ_VIC_START + INT_UARTINT2)
-#define IRQ_SCIINT              (IRQ_VIC_START + INT_SCIINT)
-#define IRQ_CLCDINT             (IRQ_VIC_START + INT_CLCDINT)
-#define IRQ_DMAINT              (IRQ_VIC_START + INT_DMAINT)
-#define IRQ_PWRFAILINT          (IRQ_VIC_START + INT_PWRFAILINT)
-#define IRQ_MBXINT              (IRQ_VIC_START + INT_MBXINT)
-#define IRQ_GNDINT              (IRQ_VIC_START + INT_GNDINT)
-#define IRQ_VICSOURCE21         (IRQ_VIC_START + INT_VICSOURCE21)
-#define IRQ_VICSOURCE22         (IRQ_VIC_START + INT_VICSOURCE22)
-#define IRQ_VICSOURCE23         (IRQ_VIC_START + INT_VICSOURCE23)
-#define IRQ_VICSOURCE24         (IRQ_VIC_START + INT_VICSOURCE24)
-#define IRQ_VICSOURCE25         (IRQ_VIC_START + INT_VICSOURCE25)
-#define IRQ_VICSOURCE26         (IRQ_VIC_START + INT_VICSOURCE26)
-#define IRQ_VICSOURCE27         (IRQ_VIC_START + INT_VICSOURCE27)
-#define IRQ_VICSOURCE28         (IRQ_VIC_START + INT_VICSOURCE28)
-#define IRQ_VICSOURCE29         (IRQ_VIC_START + INT_VICSOURCE29)
-#define IRQ_VICSOURCE30         (IRQ_VIC_START + INT_VICSOURCE30)
-#define IRQ_VICSOURCE31         (IRQ_VIC_START + INT_VICSOURCE31)
-#define IRQ_VIC_END             (IRQ_VIC_START + 31)
-
-#define IRQMASK_WDOGINT         INTMASK_WDOGINT
-#define IRQMASK_SOFTINT         INTMASK_SOFTINT
-#define IRQMASK_COMMRx          INTMASK_COMMRx
-#define IRQMASK_COMMTx          INTMASK_COMMTx
-#define IRQMASK_TIMERINT0_1     INTMASK_TIMERINT0_1
-#define IRQMASK_TIMERINT2_3     INTMASK_TIMERINT2_3
-#define IRQMASK_GPIOINT0        INTMASK_GPIOINT0
-#define IRQMASK_GPIOINT1        INTMASK_GPIOINT1
-#define IRQMASK_GPIOINT2        INTMASK_GPIOINT2
-#define IRQMASK_GPIOINT3        INTMASK_GPIOINT3
-#define IRQMASK_RTCINT          INTMASK_RTCINT
-#define IRQMASK_SSPINT          INTMASK_SSPINT
-#define IRQMASK_UARTINT0        INTMASK_UARTINT0
-#define IRQMASK_UARTINT1        INTMASK_UARTINT1
-#define IRQMASK_UARTINT2        INTMASK_UARTINT2
-#define IRQMASK_SCIINT          INTMASK_SCIINT
-#define IRQMASK_CLCDINT         INTMASK_CLCDINT
-#define IRQMASK_DMAINT          INTMASK_DMAINT
-#define IRQMASK_PWRFAILINT      INTMASK_PWRFAILINT
-#define IRQMASK_MBXINT          INTMASK_MBXINT
-#define IRQMASK_GNDINT          INTMASK_GNDINT
-#define IRQMASK_VICSOURCE21     INTMASK_VICSOURCE21
-#define IRQMASK_VICSOURCE22     INTMASK_VICSOURCE22
-#define IRQMASK_VICSOURCE23     INTMASK_VICSOURCE23
-#define IRQMASK_VICSOURCE24     INTMASK_VICSOURCE24
-#define IRQMASK_VICSOURCE25     INTMASK_VICSOURCE25
-#define IRQMASK_VICSOURCE26     INTMASK_VICSOURCE26
-#define IRQMASK_VICSOURCE27     INTMASK_VICSOURCE27
-#define IRQMASK_VICSOURCE28     INTMASK_VICSOURCE28
-#define IRQMASK_VICSOURCE29     INTMASK_VICSOURCE29
-#define IRQMASK_VICSOURCE30     INTMASK_VICSOURCE30
-#define IRQMASK_VICSOURCE31     INTMASK_VICSOURCE31
-
-/* 
- *  FIQ interrupts definitions are the same as the INT definitions.
- */
-#define FIQ_WDOGINT             INT_WDOGINT
-#define FIQ_SOFTINT             INT_SOFTINT
-#define FIQ_COMMRx              INT_COMMRx
-#define FIQ_COMMTx              INT_COMMTx
-#define FIQ_TIMERINT0_1         INT_TIMERINT0_1
-#define FIQ_TIMERINT2_3         INT_TIMERINT2_3
-#define FIQ_GPIOINT0            INT_GPIOINT0
-#define FIQ_GPIOINT1            INT_GPIOINT1
-#define FIQ_GPIOINT2            INT_GPIOINT2
-#define FIQ_GPIOINT3            INT_GPIOINT3
-#define FIQ_RTCINT              INT_RTCINT
-#define FIQ_SSPINT              INT_SSPINT
-#define FIQ_UARTINT0            INT_UARTINT0
-#define FIQ_UARTINT1            INT_UARTINT1
-#define FIQ_UARTINT2            INT_UARTINT2
-#define FIQ_SCIINT              INT_SCIINT
-#define FIQ_CLCDINT             INT_CLCDINT
-#define FIQ_DMAINT              INT_DMAINT
-#define FIQ_PWRFAILINT          INT_PWRFAILINT
-#define FIQ_MBXINT              INT_MBXINT
-#define FIQ_GNDINT              INT_GNDINT
-#define FIQ_VICSOURCE21         INT_VICSOURCE21
-#define FIQ_VICSOURCE22         INT_VICSOURCE22
-#define FIQ_VICSOURCE23         INT_VICSOURCE23
-#define FIQ_VICSOURCE24         INT_VICSOURCE24
-#define FIQ_VICSOURCE25         INT_VICSOURCE25
-#define FIQ_VICSOURCE26         INT_VICSOURCE26
-#define FIQ_VICSOURCE27         INT_VICSOURCE27
-#define FIQ_VICSOURCE28         INT_VICSOURCE28
-#define FIQ_VICSOURCE29         INT_VICSOURCE29
-#define FIQ_VICSOURCE30         INT_VICSOURCE30
-#define FIQ_VICSOURCE31         INT_VICSOURCE31
-
-
-#define FIQMASK_WDOGINT         INTMASK_WDOGINT
-#define FIQMASK_SOFTINT         INTMASK_SOFTINT
-#define FIQMASK_COMMRx          INTMASK_COMMRx
-#define FIQMASK_COMMTx          INTMASK_COMMTx
-#define FIQMASK_TIMERINT0_1     INTMASK_TIMERINT0_1
-#define FIQMASK_TIMERINT2_3     INTMASK_TIMERINT2_3
-#define FIQMASK_GPIOINT0        INTMASK_GPIOINT0
-#define FIQMASK_GPIOINT1        INTMASK_GPIOINT1
-#define FIQMASK_GPIOINT2        INTMASK_GPIOINT2
-#define FIQMASK_GPIOINT3        INTMASK_GPIOINT3
-#define FIQMASK_RTCINT          INTMASK_RTCINT
-#define FIQMASK_SSPINT          INTMASK_SSPINT
-#define FIQMASK_UARTINT0        INTMASK_UARTINT0
-#define FIQMASK_UARTINT1        INTMASK_UARTINT1
-#define FIQMASK_UARTINT2        INTMASK_UARTINT2
-#define FIQMASK_SCIINT          INTMASK_SCIINT
-#define FIQMASK_CLCDINT         INTMASK_CLCDINT
-#define FIQMASK_DMAINT          INTMASK_DMAINT
-#define FIQMASK_PWRFAILINT      INTMASK_PWRFAILINT
-#define FIQMASK_MBXINT          INTMASK_MBXINT
-#define FIQMASK_GNDINT          INTMASK_GNDINT
-#define FIQMASK_VICSOURCE21     INTMASK_VICSOURCE21
-#define FIQMASK_VICSOURCE22     INTMASK_VICSOURCE22
-#define FIQMASK_VICSOURCE23     INTMASK_VICSOURCE23
-#define FIQMASK_VICSOURCE24     INTMASK_VICSOURCE24
-#define FIQMASK_VICSOURCE25     INTMASK_VICSOURCE25
-#define FIQMASK_VICSOURCE26     INTMASK_VICSOURCE26
-#define FIQMASK_VICSOURCE27     INTMASK_VICSOURCE27
-#define FIQMASK_VICSOURCE28     INTMASK_VICSOURCE28
-#define FIQMASK_VICSOURCE29     INTMASK_VICSOURCE29
-#define FIQMASK_VICSOURCE30     INTMASK_VICSOURCE30
-#define FIQMASK_VICSOURCE31     INTMASK_VICSOURCE31
-
-/*
- * Secondary interrupt controller
- */
-#define IRQ_SIC_START           32
-#define IRQ_SIC_MMCI0B          (IRQ_SIC_START + SIC_INT_MMCI0B)
-#define IRQ_SIC_MMCI1B          (IRQ_SIC_START + SIC_INT_MMCI1B)
-#define IRQ_SIC_KMI0            (IRQ_SIC_START + SIC_INT_KMI0)
-#define IRQ_SIC_KMI1            (IRQ_SIC_START + SIC_INT_KMI1)
-#define IRQ_SIC_SCI3            (IRQ_SIC_START + SIC_INT_SCI3)
-#define IRQ_SIC_UART3           (IRQ_SIC_START + SIC_INT_UART3)
-#define IRQ_SIC_CLCD            (IRQ_SIC_START + SIC_INT_CLCD)
-#define IRQ_SIC_TOUCH           (IRQ_SIC_START + SIC_INT_TOUCH)
-#define IRQ_SIC_KEYPAD          (IRQ_SIC_START + SIC_INT_KEYPAD)
-#define IRQ_SIC_DoC             (IRQ_SIC_START + SIC_INT_DoC)
-#define IRQ_SIC_MMCI0A          (IRQ_SIC_START + SIC_INT_MMCI0A)
-#define IRQ_SIC_MMCI1A          (IRQ_SIC_START + SIC_INT_MMCI1A)
-#define IRQ_SIC_AACI            (IRQ_SIC_START + SIC_INT_AACI)
-#define IRQ_SIC_ETH             (IRQ_SIC_START + SIC_INT_ETH)
-#define IRQ_SIC_USB             (IRQ_SIC_START + SIC_INT_USB)
-#define IRQ_SIC_PCI0            (IRQ_SIC_START + SIC_INT_PCI0)
-#define IRQ_SIC_PCI1            (IRQ_SIC_START + SIC_INT_PCI1)
-#define IRQ_SIC_PCI2            (IRQ_SIC_START + SIC_INT_PCI2)
-#define IRQ_SIC_PCI3            (IRQ_SIC_START + SIC_INT_PCI3)
-#define IRQ_SIC_END             63
-
-#define SIC_IRQMASK_MMCI0B      SIC_INTMASK_MMCI0B
-#define SIC_IRQMASK_MMCI1B      SIC_INTMASK_MMCI1B
-#define SIC_IRQMASK_KMI0        SIC_INTMASK_KMI0
-#define SIC_IRQMASK_KMI1        SIC_INTMASK_KMI1
-#define SIC_IRQMASK_SCI3        SIC_INTMASK_SCI3
-#define SIC_IRQMASK_UART3       SIC_INTMASK_UART3
-#define SIC_IRQMASK_CLCD        SIC_INTMASK_CLCD
-#define SIC_IRQMASK_TOUCH       SIC_INTMASK_TOUCH
-#define SIC_IRQMASK_KEYPAD      SIC_INTMASK_KEYPAD
-#define SIC_IRQMASK_DoC         SIC_INTMASK_DoC
-#define SIC_IRQMASK_MMCI0A      SIC_INTMASK_MMCI0A
-#define SIC_IRQMASK_MMCI1A      SIC_INTMASK_MMCI1A
-#define SIC_IRQMASK_AACI        SIC_INTMASK_AACI
-#define SIC_IRQMASK_ETH         SIC_INTMASK_ETH
-#define SIC_IRQMASK_USB         SIC_INTMASK_USB
-#define SIC_IRQMASK_PCI0        SIC_INTMASK_PCI0
-#define SIC_IRQMASK_PCI1        SIC_INTMASK_PCI1
-#define SIC_IRQMASK_PCI2        SIC_INTMASK_PCI2
-#define SIC_IRQMASK_PCI3        SIC_INTMASK_PCI3
-
-#define NR_IRQS                 64
diff --git a/include/asm-arm/arch-versatile/memory.h b/include/asm-arm/arch-versatile/memory.h
deleted file mode 100644
index a9370976cc5e..000000000000
--- a/include/asm-arm/arch-versatile/memory.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-versatile/memory.h
- *
- *  Copyright (C) 2003 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-/*
- * Physical DRAM offset.
- */
-#define PHYS_OFFSET     UL(0x00000000)
-
-/*
- * Virtual view <-> DMA view memory address translations
- * virt_to_bus: Used to translate the virtual address to an
- *              address suitable to be passed to set_dma_addr
- * bus_to_virt: Used to convert an address for DMA operations
- *              to an address that the kernel can use.
- */
-#define __virt_to_bus(x)        ((x) - PAGE_OFFSET)
-#define __bus_to_virt(x)        ((x) + PAGE_OFFSET)
-
-#endif
diff --git a/include/asm-arm/arch-versatile/platform.h b/include/asm-arm/arch-versatile/platform.h
deleted file mode 100644
index 2af9d7c9c63c..000000000000
--- a/include/asm-arm/arch-versatile/platform.h
+++ /dev/null
@@ -1,510 +0,0 @@
-/*
- * linux/include/asm-arm/arch-versatile/platform.h
- *
- * Copyright (c) ARM Limited 2003.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __address_h
-#define __address_h                     1
-
-/*
- * Memory definitions
- */
-#define VERSATILE_BOOT_ROM_LO          0x30000000               /* DoC Base (64Mb)...*/
-#define VERSATILE_BOOT_ROM_HI          0x30000000
-#define VERSATILE_BOOT_ROM_BASE        VERSATILE_BOOT_ROM_HI     /*  Normal position */
-#define VERSATILE_BOOT_ROM_SIZE        SZ_64M
-
-#define VERSATILE_SSRAM_BASE           /* VERSATILE_SSMC_BASE ? */
-#define VERSATILE_SSRAM_SIZE           SZ_2M
-
-#define VERSATILE_FLASH_BASE           0x34000000
-#define VERSATILE_FLASH_SIZE           SZ_64M
-
-/* 
- *  SDRAM
- */
-#define VERSATILE_SDRAM_BASE           0x00000000
-
-/* 
- *  Logic expansion modules
- * 
- */
-
-
-/* ------------------------------------------------------------------------
- *  Versatile Registers
- * ------------------------------------------------------------------------
- * 
- */
-#define VERSATILE_SYS_ID_OFFSET               0x00
-#define VERSATILE_SYS_SW_OFFSET               0x04
-#define VERSATILE_SYS_LED_OFFSET              0x08
-#define VERSATILE_SYS_OSC0_OFFSET             0x0C
-
-#if defined(CONFIG_ARCH_VERSATILE_PB)
-#define VERSATILE_SYS_OSC1_OFFSET             0x10
-#define VERSATILE_SYS_OSC2_OFFSET             0x14
-#define VERSATILE_SYS_OSC3_OFFSET             0x18
-#define VERSATILE_SYS_OSC4_OFFSET             0x1C
-#elif defined(CONFIG_MACH_VERSATILE_AB)
-#define VERSATILE_SYS_OSC1_OFFSET             0x1C
-#endif
-
-#define VERSATILE_SYS_OSCCLCD_OFFSET          0x1c
-
-#define VERSATILE_SYS_LOCK_OFFSET             0x20
-#define VERSATILE_SYS_100HZ_OFFSET            0x24
-#define VERSATILE_SYS_CFGDATA1_OFFSET         0x28
-#define VERSATILE_SYS_CFGDATA2_OFFSET         0x2C
-#define VERSATILE_SYS_FLAGS_OFFSET            0x30
-#define VERSATILE_SYS_FLAGSSET_OFFSET         0x30
-#define VERSATILE_SYS_FLAGSCLR_OFFSET         0x34
-#define VERSATILE_SYS_NVFLAGS_OFFSET          0x38
-#define VERSATILE_SYS_NVFLAGSSET_OFFSET       0x38
-#define VERSATILE_SYS_NVFLAGSCLR_OFFSET       0x3C
-#define VERSATILE_SYS_RESETCTL_OFFSET         0x40
-#define VERSATILE_SYS_PCICTL_OFFSET           0x44
-#define VERSATILE_SYS_MCI_OFFSET              0x48
-#define VERSATILE_SYS_FLASH_OFFSET            0x4C
-#define VERSATILE_SYS_CLCD_OFFSET             0x50
-#define VERSATILE_SYS_CLCDSER_OFFSET          0x54
-#define VERSATILE_SYS_BOOTCS_OFFSET           0x58
-#define VERSATILE_SYS_24MHz_OFFSET            0x5C
-#define VERSATILE_SYS_MISC_OFFSET             0x60
-#define VERSATILE_SYS_TEST_OSC0_OFFSET        0x80
-#define VERSATILE_SYS_TEST_OSC1_OFFSET        0x84
-#define VERSATILE_SYS_TEST_OSC2_OFFSET        0x88
-#define VERSATILE_SYS_TEST_OSC3_OFFSET        0x8C
-#define VERSATILE_SYS_TEST_OSC4_OFFSET        0x90
-
-#define VERSATILE_SYS_BASE                    0x10000000
-#define VERSATILE_SYS_ID                      (VERSATILE_SYS_BASE + VERSATILE_SYS_ID_OFFSET)
-#define VERSATILE_SYS_SW                      (VERSATILE_SYS_BASE + VERSATILE_SYS_SW_OFFSET)
-#define VERSATILE_SYS_LED                     (VERSATILE_SYS_BASE + VERSATILE_SYS_LED_OFFSET)
-#define VERSATILE_SYS_OSC0                    (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC0_OFFSET)
-#define VERSATILE_SYS_OSC1                    (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC1_OFFSET)
-
-#if defined(CONFIG_ARCH_VERSATILE_PB)
-#define VERSATILE_SYS_OSC2                    (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC2_OFFSET)
-#define VERSATILE_SYS_OSC3                    (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC3_OFFSET)
-#define VERSATILE_SYS_OSC4                    (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC4_OFFSET)
-#endif
-
-#define VERSATILE_SYS_LOCK                    (VERSATILE_SYS_BASE + VERSATILE_SYS_LOCK_OFFSET)
-#define VERSATILE_SYS_100HZ                   (VERSATILE_SYS_BASE + VERSATILE_SYS_100HZ_OFFSET)
-#define VERSATILE_SYS_CFGDATA1                (VERSATILE_SYS_BASE + VERSATILE_SYS_CFGDATA1_OFFSET)
-#define VERSATILE_SYS_CFGDATA2                (VERSATILE_SYS_BASE + VERSATILE_SYS_CFGDATA2_OFFSET)
-#define VERSATILE_SYS_FLAGS                   (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGS_OFFSET)
-#define VERSATILE_SYS_FLAGSSET                (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGSSET_OFFSET)
-#define VERSATILE_SYS_FLAGSCLR                (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGSCLR_OFFSET)
-#define VERSATILE_SYS_NVFLAGS                 (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGS_OFFSET)
-#define VERSATILE_SYS_NVFLAGSSET              (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSSET_OFFSET)
-#define VERSATILE_SYS_NVFLAGSCLR              (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSCLR_OFFSET)
-#define VERSATILE_SYS_RESETCTL                (VERSATILE_SYS_BASE + VERSATILE_SYS_RESETCTL_OFFSET)
-#define VERSATILE_SYS_PCICTL                  (VERSATILE_SYS_BASE + VERSATILE_SYS_PCICTL_OFFSET)
-#define VERSATILE_SYS_MCI                     (VERSATILE_SYS_BASE + VERSATILE_SYS_MCI_OFFSET)
-#define VERSATILE_SYS_FLASH                   (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET)
-#define VERSATILE_SYS_CLCD                    (VERSATILE_SYS_BASE + VERSATILE_SYS_CLCD_OFFSET)
-#define VERSATILE_SYS_CLCDSER                 (VERSATILE_SYS_BASE + VERSATILE_SYS_CLCDSER_OFFSET)
-#define VERSATILE_SYS_BOOTCS                  (VERSATILE_SYS_BASE + VERSATILE_SYS_BOOTCS_OFFSET)
-#define VERSATILE_SYS_24MHz                   (VERSATILE_SYS_BASE + VERSATILE_SYS_24MHz_OFFSET)
-#define VERSATILE_SYS_MISC                    (VERSATILE_SYS_BASE + VERSATILE_SYS_MISC_OFFSET)
-#define VERSATILE_SYS_TEST_OSC0               (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC0_OFFSET)
-#define VERSATILE_SYS_TEST_OSC1               (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC1_OFFSET)
-#define VERSATILE_SYS_TEST_OSC2               (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC2_OFFSET)
-#define VERSATILE_SYS_TEST_OSC3               (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC3_OFFSET)
-#define VERSATILE_SYS_TEST_OSC4               (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC4_OFFSET)
-
-/* 
- * Values for VERSATILE_SYS_RESET_CTRL
- */
-#define VERSATILE_SYS_CTRL_RESET_CONFIGCLR    0x01
-#define VERSATILE_SYS_CTRL_RESET_CONFIGINIT   0x02
-#define VERSATILE_SYS_CTRL_RESET_DLLRESET     0x03
-#define VERSATILE_SYS_CTRL_RESET_PLLRESET     0x04
-#define VERSATILE_SYS_CTRL_RESET_POR          0x05
-#define VERSATILE_SYS_CTRL_RESET_DoC          0x06
-
-#define VERSATILE_SYS_CTRL_LED         (1 << 0)
-
-
-/* ------------------------------------------------------------------------
- *  Versatile control registers
- * ------------------------------------------------------------------------
- */
-
-/* 
- * VERSATILE_IDFIELD
- *
- * 31:24 = manufacturer (0x41 = ARM)
- * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus)
- * 15:12 = FPGA (0x3 = XVC600 or XVC600E)
- * 11:4  = build value
- * 3:0   = revision number (0x1 = rev B (AHB))
- */
-
-/*
- * VERSATILE_SYS_LOCK
- *     control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL, 
- *     SYS_CLD, SYS_BOOTCS
- */
-#define VERSATILE_SYS_LOCK_LOCKED    (1 << 16)
-#define VERSATILE_SYS_LOCKVAL_MASK      0xFFFF          /* write 0xA05F to enable write access */
-
-/*
- * VERSATILE_SYS_FLASH
- */
-#define VERSATILE_FLASHPROG_FLVPPEN     (1 << 0)        /* Enable writing to flash */
-
-/*
- * VERSATILE_INTREG
- *     - used to acknowledge and control MMCI and UART interrupts 
- */
-#define VERSATILE_INTREG_WPROT        0x00    /* MMC protection status (no interrupt generated) */
-#define VERSATILE_INTREG_RI0          0x01    /* Ring indicator UART0 is asserted,              */
-#define VERSATILE_INTREG_CARDIN       0x08    /* MMCI card in detect                            */
-                                                /* write 1 to acknowledge and clear               */
-#define VERSATILE_INTREG_RI1          0x02    /* Ring indicator UART1 is asserted,              */
-#define VERSATILE_INTREG_CARDINSERT   0x03    /* Signal insertion of MMC card                   */
-
-/*
- * VERSATILE peripheral addresses
- */
-#define VERSATILE_PCI_CORE_BASE        0x10001000       /* PCI core control */
-#define VERSATILE_I2C_BASE             0x10002000       /* I2C control */
-#define VERSATILE_SIC_BASE             0x10003000       /* Secondary interrupt controller */
-#define VERSATILE_AACI_BASE            0x10004000       /* Audio */
-#define VERSATILE_MMCI0_BASE           0x10005000       /* MMC interface */
-#define VERSATILE_KMI0_BASE            0x10006000       /* KMI interface */
-#define VERSATILE_KMI1_BASE            0x10007000       /* KMI 2nd interface */
-#define VERSATILE_CHAR_LCD_BASE        0x10008000       /* Character LCD */
-#define VERSATILE_UART3_BASE           0x10009000       /* UART 3 */
-#define VERSATILE_SCI1_BASE            0x1000A000
-#define VERSATILE_MMCI1_BASE           0x1000B000    /* MMC Interface */
-        /* 0x1000C000 - 0x1000CFFF = reserved */
-#define VERSATILE_ETH_BASE             0x10010000       /* Ethernet */
-#define VERSATILE_USB_BASE             0x10020000       /* USB */
-        /* 0x10030000 - 0x100FFFFF = reserved */
-#define VERSATILE_SMC_BASE             0x10100000       /* SMC */
-#define VERSATILE_MPMC_BASE            0x10110000       /* MPMC */
-#define VERSATILE_CLCD_BASE            0x10120000       /* CLCD */
-#define VERSATILE_DMAC_BASE            0x10130000       /* DMA controller */
-#define VERSATILE_VIC_BASE             0x10140000       /* Vectored interrupt controller */
-#define VERSATILE_PERIPH_BASE          0x10150000    /* off-chip peripherals alias from */
-                                                /* 0x10000000 - 0x100FFFFF */
-#define VERSATILE_AHBM_BASE            0x101D0000       /* AHB monitor */
-#define VERSATILE_SCTL_BASE            0x101E0000       /* System controller */
-#define VERSATILE_WATCHDOG_BASE        0x101E1000       /* Watchdog */
-#define VERSATILE_TIMER0_1_BASE        0x101E2000       /* Timer 0 and 1 */
-#define VERSATILE_TIMER2_3_BASE        0x101E3000       /* Timer 2 and 3 */
-#define VERSATILE_GPIO0_BASE           0x101E4000       /* GPIO port 0 */
-#define VERSATILE_GPIO1_BASE           0x101E5000    /* GPIO port 1 */
-#define VERSATILE_GPIO2_BASE           0x101E6000       /* GPIO port 2 */
-#define VERSATILE_GPIO3_BASE           0x101E7000       /* GPIO port 3 */
-#define VERSATILE_RTC_BASE             0x101E8000       /* Real Time Clock */
-        /* 0x101E9000 - reserved */
-#define VERSATILE_SCI_BASE             0x101F0000       /* Smart card controller */
-#define VERSATILE_UART0_BASE           0x101F1000       /* Uart 0 */
-#define VERSATILE_UART1_BASE           0x101F2000       /* Uart 1 */
-#define VERSATILE_UART2_BASE           0x101F3000       /* Uart 2 */
-#define VERSATILE_SSP_BASE             0x101F4000       /* Synchronous Serial Port */
-
-#define VERSATILE_SSMC_BASE            0x20000000       /* SSMC */
-#define VERSATILE_IB2_BASE             0x24000000       /* IB2 module */
-#define VERSATILE_MBX_BASE             0x40000000       /* MBX */
-
-/* PCI space */
-#define VERSATILE_PCI_BASE             0x41000000       /* PCI Interface */
-#define VERSATILE_PCI_CFG_BASE         0x42000000
-#define VERSATILE_PCI_MEM_BASE0        0x44000000
-#define VERSATILE_PCI_MEM_BASE1        0x50000000
-#define VERSATILE_PCI_MEM_BASE2        0x60000000
-/* Sizes of above maps */
-#define VERSATILE_PCI_BASE_SIZE        0x01000000
-#define VERSATILE_PCI_CFG_BASE_SIZE    0x02000000
-#define VERSATILE_PCI_MEM_BASE0_SIZE   0x0c000000       /* 32Mb */
-#define VERSATILE_PCI_MEM_BASE1_SIZE   0x10000000       /* 256Mb */
-#define VERSATILE_PCI_MEM_BASE2_SIZE   0x10000000       /* 256Mb */
-
-#define VERSATILE_SDRAM67_BASE         0x70000000       /* SDRAM banks 6 and 7 */
-#define VERSATILE_LT_BASE              0x80000000       /* Logic Tile expansion */
-
-/*
- * Disk on Chip
- */
-#define VERSATILE_DOC_BASE             0x2C000000
-#define VERSATILE_DOC_SIZE             (16 << 20)
-#define VERSATILE_DOC_PAGE_SIZE        512
-#define VERSATILE_DOC_TOTAL_PAGES     (DOC_SIZE / PAGE_SIZE)
-
-#define ERASE_UNIT_PAGES    32
-#define START_PAGE          0x80
-
-/* 
- *  LED settings, bits [7:0]
- */
-#define VERSATILE_SYS_LED0             (1 << 0)
-#define VERSATILE_SYS_LED1             (1 << 1)
-#define VERSATILE_SYS_LED2             (1 << 2)
-#define VERSATILE_SYS_LED3             (1 << 3)
-#define VERSATILE_SYS_LED4             (1 << 4)
-#define VERSATILE_SYS_LED5             (1 << 5)
-#define VERSATILE_SYS_LED6             (1 << 6)
-#define VERSATILE_SYS_LED7             (1 << 7)
-
-#define ALL_LEDS                  0xFF
-
-#define LED_BANK                  VERSATILE_SYS_LED
-
-/* 
- * Control registers
- */
-#define VERSATILE_IDFIELD_OFFSET        0x0     /* Versatile build information */
-#define VERSATILE_FLASHPROG_OFFSET      0x4     /* Flash devices */
-#define VERSATILE_INTREG_OFFSET         0x8     /* Interrupt control */
-#define VERSATILE_DECODE_OFFSET         0xC     /* Fitted logic modules */
-
-
-/* ------------------------------------------------------------------------
- *  Versatile Interrupt Controller - control registers
- * ------------------------------------------------------------------------
- * 
- *  Offsets from interrupt controller base 
- * 
- *  System Controller interrupt controller base is
- * 
- *      VERSATILE_IC_BASE
- * 
- *  Core Module interrupt controller base is
- * 
- *      VERSATILE_SYS_IC 
- * 
- */
-/* VIC definitions in include/asm-arm/hardware/vic.h */
-
-#define SIC_IRQ_STATUS                  0
-#define SIC_IRQ_RAW_STATUS              0x04
-#define SIC_IRQ_ENABLE                  0x08
-#define SIC_IRQ_ENABLE_SET              0x08
-#define SIC_IRQ_ENABLE_CLEAR            0x0C
-#define SIC_INT_SOFT_SET                0x10
-#define SIC_INT_SOFT_CLEAR              0x14
-#define SIC_INT_PIC_ENABLE              0x20    /* read status of pass through mask */
-#define SIC_INT_PIC_ENABLES             0x20    /* set interrupt pass through bits */
-#define SIC_INT_PIC_ENABLEC             0x24    /* Clear interrupt pass through bits */
-
-/* ------------------------------------------------------------------------
- *  Interrupts - bit assignment (primary)
- * ------------------------------------------------------------------------
- */
-
-#define INT_WDOGINT                     0       /* Watchdog timer */
-#define INT_SOFTINT                     1       /* Software interrupt */
-#define INT_COMMRx                      2       /* Debug Comm Rx interrupt */
-#define INT_COMMTx                      3       /* Debug Comm Tx interrupt */
-#define INT_TIMERINT0_1                 4       /* Timer 0 and 1 */
-#define INT_TIMERINT2_3                 5       /* Timer 2 and 3 */
-#define INT_GPIOINT0                    6       /* GPIO 0 */
-#define INT_GPIOINT1                    7       /* GPIO 1 */
-#define INT_GPIOINT2                    8       /* GPIO 2 */
-#define INT_GPIOINT3                    9       /* GPIO 3 */
-#define INT_RTCINT                      10      /* Real Time Clock */
-#define INT_SSPINT                      11      /* Synchronous Serial Port */
-#define INT_UARTINT0                    12      /* UART 0 on development chip */
-#define INT_UARTINT1                    13      /* UART 1 on development chip */
-#define INT_UARTINT2                    14      /* UART 2 on development chip */
-#define INT_SCIINT                      15      /* Smart Card Interface */
-#define INT_CLCDINT                     16      /* CLCD controller */
-#define INT_DMAINT                      17      /* DMA controller */
-#define INT_PWRFAILINT                  18      /* Power failure */
-#define INT_MBXINT                      19      /* Graphics processor */
-#define INT_GNDINT                      20      /* Reserved */
-        /* External interrupt signals from logic tiles or secondary controller */
-#define INT_VICSOURCE21                 21      /* Disk on Chip */
-#define INT_VICSOURCE22                 22      /* MCI0A */
-#define INT_VICSOURCE23                 23      /* MCI1A */
-#define INT_VICSOURCE24                 24      /* AACI */
-#define INT_VICSOURCE25                 25      /* Ethernet */
-#define INT_VICSOURCE26                 26      /* USB */
-#define INT_VICSOURCE27                 27      /* PCI 0 */
-#define INT_VICSOURCE28                 28      /* PCI 1 */
-#define INT_VICSOURCE29                 29      /* PCI 2 */
-#define INT_VICSOURCE30                 30      /* PCI 3 */
-#define INT_VICSOURCE31                 31      /* SIC source */
-
-/* 
- *  Interrupt bit positions
- * 
- */
-#define INTMASK_WDOGINT                 (1 << INT_WDOGINT)
-#define INTMASK_SOFTINT                 (1 << INT_SOFTINT)
-#define INTMASK_COMMRx                  (1 << INT_COMMRx)
-#define INTMASK_COMMTx                  (1 << INT_COMMTx)
-#define INTMASK_TIMERINT0_1             (1 << INT_TIMERINT0_1)
-#define INTMASK_TIMERINT2_3             (1 << INT_TIMERINT2_3)
-#define INTMASK_GPIOINT0                (1 << INT_GPIOINT0)
-#define INTMASK_GPIOINT1                (1 << INT_GPIOINT1)
-#define INTMASK_GPIOINT2                (1 << INT_GPIOINT2)
-#define INTMASK_GPIOINT3                (1 << INT_GPIOINT3)
-#define INTMASK_RTCINT                  (1 << INT_RTCINT)
-#define INTMASK_SSPINT                  (1 << INT_SSPINT)
-#define INTMASK_UARTINT0                (1 << INT_UARTINT0)
-#define INTMASK_UARTINT1                (1 << INT_UARTINT1)
-#define INTMASK_UARTINT2                (1 << INT_UARTINT2)
-#define INTMASK_SCIINT                  (1 << INT_SCIINT)
-#define INTMASK_CLCDINT                 (1 << INT_CLCDINT)
-#define INTMASK_DMAINT                  (1 << INT_DMAINT)
-#define INTMASK_PWRFAILINT              (1 << INT_PWRFAILINT)
-#define INTMASK_MBXINT                  (1 << INT_MBXINT)
-#define INTMASK_GNDINT                  (1 << INT_GNDINT)
-#define INTMASK_VICSOURCE21             (1 << INT_VICSOURCE21)
-#define INTMASK_VICSOURCE22             (1 << INT_VICSOURCE22)
-#define INTMASK_VICSOURCE23             (1 << INT_VICSOURCE23)
-#define INTMASK_VICSOURCE24             (1 << INT_VICSOURCE24)
-#define INTMASK_VICSOURCE25             (1 << INT_VICSOURCE25)
-#define INTMASK_VICSOURCE26             (1 << INT_VICSOURCE26)
-#define INTMASK_VICSOURCE27             (1 << INT_VICSOURCE27)
-#define INTMASK_VICSOURCE28             (1 << INT_VICSOURCE28)
-#define INTMASK_VICSOURCE29             (1 << INT_VICSOURCE29)
-#define INTMASK_VICSOURCE30             (1 << INT_VICSOURCE30)
-#define INTMASK_VICSOURCE31             (1 << INT_VICSOURCE31)
-
-
-#define VERSATILE_SC_VALID_INT               0x003FFFFF
-
-#define MAXIRQNUM                       31
-#define MAXFIQNUM                       31
-#define MAXSWINUM                       31
-
-/* ------------------------------------------------------------------------
- *  Interrupts - bit assignment (secondary)
- * ------------------------------------------------------------------------
- */
-#define SIC_INT_MMCI0B                  1       /* Multimedia Card 0B */
-#define SIC_INT_MMCI1B                  2       /* Multimedia Card 1B */
-#define SIC_INT_KMI0                    3       /* Keyboard/Mouse port 0 */
-#define SIC_INT_KMI1                    4       /* Keyboard/Mouse port 1 */
-#define SIC_INT_SCI3                    5       /* Smart Card interface */
-#define SIC_INT_UART3                   6       /* UART 3 empty or data available */
-#define SIC_INT_CLCD                    7       /* Character LCD */
-#define SIC_INT_TOUCH                   8       /* Touchscreen */
-#define SIC_INT_KEYPAD                  9       /* Key pressed on display keypad */
-        /* 10:20 - reserved */
-#define SIC_INT_DoC                     21      /* Disk on Chip memory controller */
-#define SIC_INT_MMCI0A                  22      /* MMC 0A */
-#define SIC_INT_MMCI1A                  23      /* MMC 1A */
-#define SIC_INT_AACI                    24      /* Audio Codec */
-#define SIC_INT_ETH                     25      /* Ethernet controller */
-#define SIC_INT_USB                     26      /* USB controller */
-#define SIC_INT_PCI0                    27
-#define SIC_INT_PCI1                    28
-#define SIC_INT_PCI2                    29
-#define SIC_INT_PCI3                    30
-
-
-#define SIC_INTMASK_MMCI0B              (1 << SIC_INT_MMCI0B)
-#define SIC_INTMASK_MMCI1B              (1 << SIC_INT_MMCI1B)
-#define SIC_INTMASK_KMI0                (1 << SIC_INT_KMI0)
-#define SIC_INTMASK_KMI1                (1 << SIC_INT_KMI1)
-#define SIC_INTMASK_SCI3                (1 << SIC_INT_SCI3)
-#define SIC_INTMASK_UART3               (1 << SIC_INT_UART3)
-#define SIC_INTMASK_CLCD                (1 << SIC_INT_CLCD)
-#define SIC_INTMASK_TOUCH               (1 << SIC_INT_TOUCH)
-#define SIC_INTMASK_KEYPAD              (1 << SIC_INT_KEYPAD)
-#define SIC_INTMASK_DoC                 (1 << SIC_INT_DoC)
-#define SIC_INTMASK_MMCI0A              (1 << SIC_INT_MMCI0A)
-#define SIC_INTMASK_MMCI1A              (1 << SIC_INT_MMCI1A)
-#define SIC_INTMASK_AACI                (1 << SIC_INT_AACI)
-#define SIC_INTMASK_ETH                 (1 << SIC_INT_ETH)
-#define SIC_INTMASK_USB                 (1 << SIC_INT_USB)
-#define SIC_INTMASK_PCI0                (1 << SIC_INT_PCI0)
-#define SIC_INTMASK_PCI1                (1 << SIC_INT_PCI1)
-#define SIC_INTMASK_PCI2                (1 << SIC_INT_PCI2)
-#define SIC_INTMASK_PCI3                (1 << SIC_INT_PCI3)
-/* 
- *  Application Flash
- * 
- */
-#define FLASH_BASE                      VERSATILE_FLASH_BASE
-#define FLASH_SIZE                      VERSATILE_FLASH_SIZE
-#define FLASH_END                       (FLASH_BASE + FLASH_SIZE - 1)
-#define FLASH_BLOCK_SIZE                SZ_128K
-
-/* 
- *  Boot Flash
- * 
- */
-#define EPROM_BASE                      VERSATILE_BOOT_ROM_HI
-#define EPROM_SIZE                      VERSATILE_BOOT_ROM_SIZE
-#define EPROM_END                       (EPROM_BASE + EPROM_SIZE - 1)
-
-/* 
- *  Clean base - dummy
- * 
- */
-#define CLEAN_BASE                      EPROM_BASE
-
-/*
- * System controller bit assignment
- */
-#define VERSATILE_REFCLK        0
-#define VERSATILE_TIMCLK        1
-
-#define VERSATILE_TIMER1_EnSel  15
-#define VERSATILE_TIMER2_EnSel  17
-#define VERSATILE_TIMER3_EnSel  19
-#define VERSATILE_TIMER4_EnSel  21
-
-
-#define MAX_TIMER                       2
-#define MAX_PERIOD                      699050
-#define TICKS_PER_uSEC                  1
-
-/* 
- *  These are useconds NOT ticks.  
- * 
- */
-#define mSEC_1                          1000
-#define mSEC_5                          (mSEC_1 * 5)
-#define mSEC_10                         (mSEC_1 * 10)
-#define mSEC_25                         (mSEC_1 * 25)
-#define SEC_1                           (mSEC_1 * 1000)
-
-#define VERSATILE_CSR_BASE             0x10000000
-#define VERSATILE_CSR_SIZE             0x10000000
-
-#ifdef CONFIG_MACH_VERSATILE_AB
-/*
- * IB2 Versatile/AB expansion board definitions
- */
-#define VERSATILE_IB2_CAMERA_BANK       VERSATILE_IB2_BASE
-#define VERSATILE_IB2_KBD_DATAREG       (VERSATILE_IB2_BASE + 0x01000000)
-
-/* VICINTSOURCE27 */
-#define VERSATILE_IB2_INT_BASE          (VERSATILE_IB2_BASE + 0x02000000)
-#define VERSATILE_IB2_IER               (VERSATILE_IB2_INT_BASE + 0)
-#define VERSATILE_IB2_ISR               (VERSATILE_IB2_INT_BASE + 4)
-
-#define VERSATILE_IB2_CTL_BASE          (VERSATILE_IB2_BASE + 0x03000000)
-#define VERSATILE_IB2_CTRL              (VERSATILE_IB2_CTL_BASE + 0)
-#define VERSATILE_IB2_STAT              (VERSATILE_IB2_CTL_BASE + 4)
-#endif
-
-#endif
-
-/*      END */
diff --git a/include/asm-arm/arch-versatile/system.h b/include/asm-arm/arch-versatile/system.h
deleted file mode 100644
index 3ea4e07b58c8..000000000000
--- a/include/asm-arm/arch-versatile/system.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-versatile/system.h
- *
- *  Copyright (C) 2003 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-#include <asm/arch/platform.h>
-
-static inline void arch_idle(void)
-{
-        /*
-         * This should do all the clock switching
-         * and wait for interrupt tricks
-         */
-        cpu_do_idle();
-}
-
-static inline void arch_reset(char mode)
-{
-        u32 val;
-
-        val = __raw_readl(IO_ADDRESS(VERSATILE_SYS_RESETCTL)) & ~0x7;
-        val |= 0x105;
-
-        __raw_writel(0xa05f, IO_ADDRESS(VERSATILE_SYS_LOCK));
-        __raw_writel(val, IO_ADDRESS(VERSATILE_SYS_RESETCTL));
-        __raw_writel(0, IO_ADDRESS(VERSATILE_SYS_LOCK));
-}
-
-#endif
diff --git a/include/asm-arm/arch-versatile/timex.h b/include/asm-arm/arch-versatile/timex.h
deleted file mode 100644
index 38fd04fc9141..000000000000
--- a/include/asm-arm/arch-versatile/timex.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-versatile/timex.h
- *
- *  Versatile architecture timex specifications
- *
- *  Copyright (C) 2003 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#define CLOCK_TICK_RATE         (50000000 / 16)
diff --git a/include/asm-arm/arch-versatile/uncompress.h b/include/asm-arm/arch-versatile/uncompress.h
deleted file mode 100644
index 7215133d0514..000000000000
--- a/include/asm-arm/arch-versatile/uncompress.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-versatile/uncompress.h
- *
- *  Copyright (C) 2003 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define AMBA_UART_DR    (*(volatile unsigned char *)0x101F1000)
-#define AMBA_UART_LCRH  (*(volatile unsigned char *)0x101F102C)
-#define AMBA_UART_CR    (*(volatile unsigned char *)0x101F1030)
-#define AMBA_UART_FR    (*(volatile unsigned char *)0x101F1018)
-
-/*
- * This does not append a newline
- */
-static inline void putc(int c)
-{
-        while (AMBA_UART_FR & (1 << 5))
-                barrier();
-
-        AMBA_UART_DR = c;
-}
-
-static inline void flush(void)
-{
-        while (AMBA_UART_FR & (1 << 3))
-                barrier();
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-versatile/vmalloc.h b/include/asm-arm/arch-versatile/vmalloc.h
deleted file mode 100644
index ac780df62156..000000000000
--- a/include/asm-arm/arch-versatile/vmalloc.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-versatile/vmalloc.h
- *
- *  Copyright (C) 2003 ARM Limited
- *  Copyright (C) 2000 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define VMALLOC_END             (PAGE_OFFSET + 0x18000000)
diff --git a/include/asm-arm/plat-s3c/iic.h b/include/asm-arm/plat-s3c/iic.h
index d08a1f2863e4..5106acaa1d0e 100644
--- a/include/asm-arm/plat-s3c/iic.h
+++ b/include/asm-arm/plat-s3c/iic.h
@@ -1,4 +1,4 @@
-/* linux/include/asm-arm/arch-s3c2410/iic.h
+/* arch/arm/mach-s3c2410/include/mach/iic.h
  *
  * Copyright (c) 2004 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
diff --git a/include/asm-arm/plat-s3c/nand.h b/include/asm-arm/plat-s3c/nand.h
index ad6bbe90616e..f4dcd14af059 100644
--- a/include/asm-arm/plat-s3c/nand.h
+++ b/include/asm-arm/plat-s3c/nand.h
@@ -1,4 +1,4 @@
-/* linux/include/asm-arm/arch-s3c2410/nand.h
+/* arch/arm/mach-s3c2410/include/mach/nand.h
  *
  * Copyright (c) 2004 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
diff --git a/include/asm-arm/plat-s3c/regs-ac97.h b/include/asm-arm/plat-s3c/regs-ac97.h
index b004dee6bcaf..c3878f7acb83 100644
--- a/include/asm-arm/plat-s3c/regs-ac97.h
+++ b/include/asm-arm/plat-s3c/regs-ac97.h
@@ -1,4 +1,4 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-ac97.h
+/* arch/arm/mach-s3c2410/include/mach/regs-ac97.h
  *
  * Copyright (c) 2006 Simtec Electronics <linux@simtec.co.uk>
  *              http://www.simtec.co.uk/products/SWLINUX/
diff --git a/include/asm-arm/plat-s3c/regs-adc.h b/include/asm-arm/plat-s3c/regs-adc.h
index c7f231963e76..4323cccc86cd 100644
--- a/include/asm-arm/plat-s3c/regs-adc.h
+++ b/include/asm-arm/plat-s3c/regs-adc.h
@@ -1,4 +1,4 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-adc.h
+/* arch/arm/mach-s3c2410/include/mach/regs-adc.h
  *
  * Copyright (c) 2004 Shannon Holland <holland@loser.net>
  *
diff --git a/include/asm-arm/plat-s3c/regs-iic.h b/include/asm-arm/plat-s3c/regs-iic.h
index 2ae29522f253..2f7c17de8ac8 100644
--- a/include/asm-arm/plat-s3c/regs-iic.h
+++ b/include/asm-arm/plat-s3c/regs-iic.h
@@ -1,4 +1,4 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-iic.h
+/* arch/arm/mach-s3c2410/include/mach/regs-iic.h
  *
  * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
  *              http://www.simtec.co.uk/products/SWLINUX/
diff --git a/include/asm-arm/plat-s3c/regs-nand.h b/include/asm-arm/plat-s3c/regs-nand.h
index d742205ac172..09f0b5503f5b 100644
--- a/include/asm-arm/plat-s3c/regs-nand.h
+++ b/include/asm-arm/plat-s3c/regs-nand.h
@@ -1,4 +1,4 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-nand.h
+/* arch/arm/mach-s3c2410/include/mach/regs-nand.h
  *
  * Copyright (c) 2004,2005 Simtec Electronics <linux@simtec.co.uk>
  *                    http://www.simtec.co.uk/products/SWLINUX/
diff --git a/include/asm-arm/plat-s3c/regs-rtc.h b/include/asm-arm/plat-s3c/regs-rtc.h
index 93b03c49710a..d5837cf8e402 100644
--- a/include/asm-arm/plat-s3c/regs-rtc.h
+++ b/include/asm-arm/plat-s3c/regs-rtc.h
@@ -1,4 +1,4 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-rtc.h
+/* arch/arm/mach-s3c2410/include/mach/regs-rtc.h
  *
  * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
  *                    http://www.simtec.co.uk/products/SWLINUX/
diff --git a/include/asm-arm/plat-s3c/regs-serial.h b/include/asm-arm/plat-s3c/regs-serial.h
index 923e114db663..a0daa647b92c 100644
--- a/include/asm-arm/plat-s3c/regs-serial.h
+++ b/include/asm-arm/plat-s3c/regs-serial.h
@@ -1,4 +1,4 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-serial.h
+/* arch/arm/mach-s3c2410/include/mach/regs-serial.h
  *
  *  From linux/include/asm-arm/hardware/serial_s3c2410.h
  *
diff --git a/include/asm-arm/plat-s3c/regs-timer.h b/include/asm-arm/plat-s3c/regs-timer.h
index b5bc692f3489..b4366ea39677 100644
--- a/include/asm-arm/plat-s3c/regs-timer.h
+++ b/include/asm-arm/plat-s3c/regs-timer.h
@@ -1,4 +1,4 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-timer.h
+/* arch/arm/mach-s3c2410/include/mach/regs-timer.h
  *
  * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
  *                    http://www.simtec.co.uk/products/SWLINUX/
diff --git a/include/asm-arm/plat-s3c/regs-watchdog.h b/include/asm-arm/plat-s3c/regs-watchdog.h
index 56c4193b7a46..1229f076c0a0 100644
--- a/include/asm-arm/plat-s3c/regs-watchdog.h
+++ b/include/asm-arm/plat-s3c/regs-watchdog.h
@@ -1,4 +1,4 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-watchdog.h
+/* arch/arm/mach-s3c2410/include/mach/regs-watchdog.h
  *
  * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
  *                    http://www.simtec.co.uk/products/SWLINUX/
diff --git a/include/asm-arm/plat-s3c24xx/regs-iis.h b/include/asm-arm/plat-s3c24xx/regs-iis.h
index eaf77916a602..a6f1d5df13b4 100644
--- a/include/asm-arm/plat-s3c24xx/regs-iis.h
+++ b/include/asm-arm/plat-s3c24xx/regs-iis.h
@@ -1,4 +1,4 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-iis.h
+/* arch/arm/mach-s3c2410/include/mach/regs-iis.h
  *
  * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
  *                    http://www.simtec.co.uk/products/SWLINUX/
diff --git a/include/asm-arm/plat-s3c24xx/regs-spi.h b/include/asm-arm/plat-s3c24xx/regs-spi.h
index ea565b007d04..2b35479ee35c 100644
--- a/include/asm-arm/plat-s3c24xx/regs-spi.h
+++ b/include/asm-arm/plat-s3c24xx/regs-spi.h
@@ -1,4 +1,4 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-spi.h
+/* arch/arm/mach-s3c2410/include/mach/regs-spi.h
  *
  * Copyright (c) 2004 Fetron GmbH
  *
diff --git a/include/asm-arm/plat-s3c24xx/regs-udc.h b/include/asm-arm/plat-s3c24xx/regs-udc.h
index e1e9805d2d9a..f0dd4a41b37b 100644
--- a/include/asm-arm/plat-s3c24xx/regs-udc.h
+++ b/include/asm-arm/plat-s3c24xx/regs-udc.h
@@ -1,4 +1,4 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-udc.h
+/* arch/arm/mach-s3c2410/include/mach/regs-udc.h
  *
  * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
  *
diff --git a/include/asm-arm/plat-s3c24xx/udc.h b/include/asm-arm/plat-s3c24xx/udc.h
index b8aa6cb69b58..546bb4008f49 100644
--- a/include/asm-arm/plat-s3c24xx/udc.h
+++ b/include/asm-arm/plat-s3c24xx/udc.h
@@ -1,4 +1,4 @@
-/* linux/include/asm-arm/arch-s3c2410/udc.h
+/* arch/arm/mach-s3c2410/include/mach/udc.h
  *
  * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org>
  *
diff --git a/sound/arm/pxa2xx-ac97.c b/sound/arm/pxa2xx-ac97.c
index 158f7b50b780..199cca3366df 100644
--- a/sound/arm/pxa2xx-ac97.c
+++ b/sound/arm/pxa2xx-ac97.c
@@ -26,10 +26,10 @@
 
 #include <asm/irq.h>
 #include <linux/mutex.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-gpio.h>
-#include <asm/arch/audio.h>
+#include <mach/hardware.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-gpio.h>
+#include <mach/audio.h>
 
 #include "pxa2xx-pcm.h"
 
diff --git a/sound/arm/pxa2xx-pcm.c b/sound/arm/pxa2xx-pcm.c
index 9a104e2430f5..381094aab235 100644
--- a/sound/arm/pxa2xx-pcm.c
+++ b/sound/arm/pxa2xx-pcm.c
@@ -21,8 +21,8 @@
 #include <sound/pcm_params.h>
 
 #include <asm/dma.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa-regs.h>
+#include <mach/hardware.h>
+#include <mach/pxa-regs.h>
 
 #include "pxa2xx-pcm.h"
 
diff --git a/sound/arm/sa11xx-uda1341.c b/sound/arm/sa11xx-uda1341.c
index 40c213e70593..b9c51bf8cd71 100644
--- a/sound/arm/sa11xx-uda1341.c
+++ b/sound/arm/sa11xx-uda1341.c
@@ -71,8 +71,8 @@
 #include <linux/pm.h>
 #endif
 
-#include <asm/arch/hardware.h>
-#include <asm/arch/h3600.h>
+#include <mach/hardware.h>
+#include <mach/h3600.h>
 #include <asm/mach-types.h>
 #include <asm/dma.h>
 
diff --git a/sound/oss/vidc.c b/sound/oss/vidc.c
index 41cd4f25de04..725fef0f59a3 100644
--- a/sound/oss/vidc.c
+++ b/sound/oss/vidc.c
@@ -22,7 +22,7 @@
 #include <linux/kernel.h>
 #include <linux/interrupt.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/dma.h>
 #include <asm/io.h>
 #include <asm/hardware/iomd.h>
diff --git a/sound/oss/vidc_fill.S b/sound/oss/vidc_fill.S
index d2cb210cc402..bed34921d176 100644
--- a/sound/oss/vidc_fill.S
+++ b/sound/oss/vidc_fill.S
@@ -11,7 +11,7 @@
  */
 #include <linux/linkage.h>
 #include <asm/assembler.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/hardware/iomd.h>
 
                 .text
diff --git a/sound/oss/waveartist.c b/sound/oss/waveartist.c
index d84c49787f6f..c47842fad657 100644
--- a/sound/oss/waveartist.c
+++ b/sound/oss/waveartist.c
@@ -47,7 +47,7 @@
 #include "waveartist.h"
 
 #ifdef CONFIG_ARM
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #endif
 
diff --git a/sound/soc/at32/playpaq_wm8510.c b/sound/soc/at32/playpaq_wm8510.c
index fee5f8e58957..3f326219f1ec 100644
--- a/sound/soc/at32/playpaq_wm8510.c
+++ b/sound/soc/at32/playpaq_wm8510.c
@@ -36,8 +36,8 @@
 #include <sound/soc.h>
 #include <sound/soc-dapm.h>
 
-#include <asm/arch/at32ap700x.h>
-#include <asm/arch/portmux.h>
+#include <mach/at32ap700x.h>
+#include <mach/portmux.h>
 
 #include "../codecs/wm8510.h"
 #include "at32-pcm.h"
diff --git a/sound/soc/at91/at91-pcm.c b/sound/soc/at91/at91-pcm.c
index d47492b2b6e5..7ab48bd25e4c 100644
--- a/sound/soc/at91/at91-pcm.c
+++ b/sound/soc/at91/at91-pcm.c
@@ -28,8 +28,8 @@
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
 
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_ssc.h>
+#include <mach/hardware.h>
+#include <mach/at91_ssc.h>
 
 #include "at91-pcm.h"
 
diff --git a/sound/soc/at91/at91-pcm.h b/sound/soc/at91/at91-pcm.h
index 58d0f00a07b2..e5aada2cb102 100644
--- a/sound/soc/at91/at91-pcm.h
+++ b/sound/soc/at91/at91-pcm.h
@@ -19,7 +19,7 @@
 #ifndef _AT91_PCM_H
 #define _AT91_PCM_H
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 struct at91_ssc_periph {
         void __iomem    *base;
diff --git a/sound/soc/at91/at91-ssc.c b/sound/soc/at91/at91-ssc.c
index 090e607f8692..5d44515e62e0 100644
--- a/sound/soc/at91/at91-ssc.c
+++ b/sound/soc/at91/at91-ssc.c
@@ -28,9 +28,9 @@
 #include <sound/initval.h>
 #include <sound/soc.h>
 
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_ssc.h>
+#include <mach/hardware.h>
+#include <mach/at91_pmc.h>
+#include <mach/at91_ssc.h>
 
 #include "at91-pcm.h"
 #include "at91-ssc.h"
diff --git a/sound/soc/at91/eti_b1_wm8731.c b/sound/soc/at91/eti_b1_wm8731.c
index d61a4537e604..b081e83766b7 100644
--- a/sound/soc/at91/eti_b1_wm8731.c
+++ b/sound/soc/at91/eti_b1_wm8731.c
@@ -33,8 +33,8 @@
 #include <sound/soc.h>
 #include <sound/soc-dapm.h>
 
-#include <asm/arch/hardware.h>
-#include <asm/arch/gpio.h>
+#include <mach/hardware.h>
+#include <mach/gpio.h>
 
 #include "../codecs/wm8731.h"
 #include "at91-pcm.h"
diff --git a/sound/soc/davinci/davinci-evm.c b/sound/soc/davinci/davinci-evm.c
index 0722eebe3d6a..65fdbd81a379 100644
--- a/sound/soc/davinci/davinci-evm.c
+++ b/sound/soc/davinci/davinci-evm.c
@@ -20,7 +20,7 @@
 #include <sound/soc-dapm.h>
 
 #include <asm/dma.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 #include "../codecs/tlv320aic3x.h"
 #include "davinci-pcm.h"
diff --git a/sound/soc/omap/n810.c b/sound/soc/omap/n810.c
index 02cec96859b8..7694621ec40b 100644
--- a/sound/soc/omap/n810.c
+++ b/sound/soc/omap/n810.c
@@ -29,9 +29,9 @@
 #include <sound/soc-dapm.h>
 
 #include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <linux/gpio.h>
-#include <asm/arch/mcbsp.h>
+#include <mach/mcbsp.h>
 
 #include "omap-mcbsp.h"
 #include "omap-pcm.h"
diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c
index 00b0c9d73cd4..35310e16d7f3 100644
--- a/sound/soc/omap/omap-mcbsp.c
+++ b/sound/soc/omap/omap-mcbsp.c
@@ -30,9 +30,9 @@
 #include <sound/initval.h>
 #include <sound/soc.h>
 
-#include <asm/arch/control.h>
-#include <asm/arch/dma.h>
-#include <asm/arch/mcbsp.h>
+#include <mach/control.h>
+#include <mach/dma.h>
+#include <mach/mcbsp.h>
 #include "omap-mcbsp.h"
 #include "omap-pcm.h"
 
diff --git a/sound/soc/omap/omap-pcm.c b/sound/soc/omap/omap-pcm.c
index e092f3d836d0..690bfeaec4a0 100644
--- a/sound/soc/omap/omap-pcm.c
+++ b/sound/soc/omap/omap-pcm.c
@@ -27,7 +27,7 @@
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
 
-#include <asm/arch/dma.h>
+#include <mach/dma.h>
 #include "omap-pcm.h"
 
 static const struct snd_pcm_hardware omap_pcm_hardware = {
diff --git a/sound/soc/pxa/corgi.c b/sound/soc/pxa/corgi.c
index c0294464a23a..0a53f72077fd 100644
--- a/sound/soc/pxa/corgi.c
+++ b/sound/soc/pxa/corgi.c
@@ -25,10 +25,10 @@
 
 #include <asm/mach-types.h>
 #include <asm/hardware/scoop.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/corgi.h>
-#include <asm/arch/audio.h>
+#include <mach/pxa-regs.h>
+#include <mach/hardware.h>
+#include <mach/corgi.h>
+#include <mach/audio.h>
 
 #include "../codecs/wm8731.h"
 #include "pxa2xx-pcm.h"
diff --git a/sound/soc/pxa/e800_wm9712.c b/sound/soc/pxa/e800_wm9712.c
index 06e8afb25277..6781c5be242f 100644
--- a/sound/soc/pxa/e800_wm9712.c
+++ b/sound/soc/pxa/e800_wm9712.c
@@ -21,9 +21,9 @@
 #include <sound/soc-dapm.h>
 
 #include <asm/mach-types.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/audio.h>
+#include <mach/pxa-regs.h>
+#include <mach/hardware.h>
+#include <mach/audio.h>
 
 #include "../codecs/wm9712.h"
 #include "pxa2xx-pcm.h"
diff --git a/sound/soc/pxa/em-x270.c b/sound/soc/pxa/em-x270.c
index 02dcac39cdf6..d9c3f7b28be2 100644
--- a/sound/soc/pxa/em-x270.c
+++ b/sound/soc/pxa/em-x270.c
@@ -30,9 +30,9 @@
 #include <sound/soc-dapm.h>
 
 #include <asm/mach-types.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/audio.h>
+#include <mach/pxa-regs.h>
+#include <mach/hardware.h>
+#include <mach/audio.h>
 
 #include "../codecs/wm9712.h"
 #include "pxa2xx-pcm.h"
diff --git a/sound/soc/pxa/poodle.c b/sound/soc/pxa/poodle.c
index d968cf71b569..a4697f7e2921 100644
--- a/sound/soc/pxa/poodle.c
+++ b/sound/soc/pxa/poodle.c
@@ -26,10 +26,10 @@
 
 #include <asm/mach-types.h>
 #include <asm/hardware/locomo.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/poodle.h>
-#include <asm/arch/audio.h>
+#include <mach/pxa-regs.h>
+#include <mach/hardware.h>
+#include <mach/poodle.h>
+#include <mach/audio.h>
 
 #include "../codecs/wm8731.h"
 #include "pxa2xx-pcm.h"
diff --git a/sound/soc/pxa/pxa2xx-ac97.c b/sound/soc/pxa/pxa2xx-ac97.c
index b45a4f199ef7..d94a495bd6bd 100644
--- a/sound/soc/pxa/pxa2xx-ac97.c
+++ b/sound/soc/pxa/pxa2xx-ac97.c
@@ -26,10 +26,10 @@
 
 #include <asm/irq.h>
 #include <linux/mutex.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-gpio.h>
-#include <asm/arch/audio.h>
+#include <mach/hardware.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-gpio.h>
+#include <mach/audio.h>
 
 #include "pxa2xx-pcm.h"
 #include "pxa2xx-ac97.h"
diff --git a/sound/soc/pxa/pxa2xx-i2s.c b/sound/soc/pxa/pxa2xx-i2s.c
index f69870f4f673..8548818eea08 100644
--- a/sound/soc/pxa/pxa2xx-i2s.c
+++ b/sound/soc/pxa/pxa2xx-i2s.c
@@ -21,10 +21,10 @@
 #include <sound/initval.h>
 #include <sound/soc.h>
 
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa2xx-gpio.h>
-#include <asm/arch/audio.h>
+#include <mach/hardware.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-gpio.h>
+#include <mach/audio.h>
 
 #include "pxa2xx-pcm.h"
 #include "pxa2xx-i2s.h"
diff --git a/sound/soc/pxa/pxa2xx-pcm.c b/sound/soc/pxa/pxa2xx-pcm.c
index 77708f879c96..4345f387fe41 100644
--- a/sound/soc/pxa/pxa2xx-pcm.c
+++ b/sound/soc/pxa/pxa2xx-pcm.c
@@ -22,9 +22,9 @@
 #include <sound/soc.h>
 
 #include <asm/dma.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/audio.h>
+#include <mach/hardware.h>
+#include <mach/pxa-regs.h>
+#include <mach/audio.h>
 
 #include "pxa2xx-pcm.h"
 
diff --git a/sound/soc/pxa/spitz.c b/sound/soc/pxa/spitz.c
index 64385797da5d..eefc25b83514 100644
--- a/sound/soc/pxa/spitz.c
+++ b/sound/soc/pxa/spitz.c
@@ -26,10 +26,10 @@
 
 #include <asm/mach-types.h>
 #include <asm/hardware/scoop.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/akita.h>
-#include <asm/arch/spitz.h>
+#include <mach/pxa-regs.h>
+#include <mach/hardware.h>
+#include <mach/akita.h>
+#include <mach/spitz.h>
 #include "../codecs/wm8750.h"
 #include "pxa2xx-pcm.h"
 #include "pxa2xx-i2s.h"
diff --git a/sound/soc/pxa/tosa.c b/sound/soc/pxa/tosa.c
index 22971a0f040e..2baaa750f123 100644
--- a/sound/soc/pxa/tosa.c
+++ b/sound/soc/pxa/tosa.c
@@ -29,10 +29,10 @@
 #include <sound/soc-dapm.h>
 
 #include <asm/mach-types.h>
-#include <asm/arch/tosa.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/audio.h>
+#include <mach/tosa.h>
+#include <mach/pxa-regs.h>
+#include <mach/hardware.h>
+#include <mach/audio.h>
 
 #include "../codecs/wm9712.h"
 #include "pxa2xx-pcm.h"
diff --git a/sound/soc/s3c24xx/neo1973_wm8753.c b/sound/soc/s3c24xx/neo1973_wm8753.c
index 47bf9a0aab79..8089f8ee05c0 100644
--- a/sound/soc/s3c24xx/neo1973_wm8753.c
+++ b/sound/soc/s3c24xx/neo1973_wm8753.c
@@ -25,12 +25,12 @@
 #include <sound/tlv.h>
 
 #include <asm/hardware/scoop.h>
-#include <asm/arch/regs-clock.h>
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/audio.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-gpio.h>
+#include <mach/hardware.h>
+#include <mach/audio.h>
 #include <linux/io.h>
-#include <asm/arch/spi-gpio.h>
+#include <mach/spi-gpio.h>
 
 #include <asm/plat-s3c24xx/regs-iis.h>
 
diff --git a/sound/soc/s3c24xx/s3c2412-i2s.c b/sound/soc/s3c24xx/s3c2412-i2s.c
index 59c3d5355f55..ded7d995a922 100644
--- a/sound/soc/s3c24xx/s3c2412-i2s.c
+++ b/sound/soc/s3c24xx/s3c2412-i2s.c
@@ -28,16 +28,16 @@
 #include <sound/pcm_params.h>
 #include <sound/initval.h>
 #include <sound/soc.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 
 #include <linux/io.h>
 #include <asm/dma.h>
 
 #include <asm/plat-s3c24xx/regs-s3c2412-iis.h>
 
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/audio.h>
-#include <asm/arch/dma.h>
+#include <mach/regs-gpio.h>
+#include <mach/audio.h>
+#include <mach/dma.h>
 
 #include "s3c24xx-pcm.h"
 #include "s3c2412-i2s.h"
diff --git a/sound/soc/s3c24xx/s3c2443-ac97.c b/sound/soc/s3c24xx/s3c2443-ac97.c
index a37167398ab5..19c5c3cf5d8c 100644
--- a/sound/soc/s3c24xx/s3c2443-ac97.c
+++ b/sound/soc/s3c24xx/s3c2443-ac97.c
@@ -27,13 +27,13 @@
 #include <sound/initval.h>
 #include <sound/soc.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/plat-s3c/regs-ac97.h>
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-clock.h>
-#include <asm/arch/audio.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-clock.h>
+#include <mach/audio.h>
 #include <asm/dma.h>
-#include <asm/arch/dma.h>
+#include <mach/dma.h>
 
 #include "s3c24xx-pcm.h"
 #include "s3c24xx-ac97.h"
diff --git a/sound/soc/s3c24xx/s3c24xx-i2s.c b/sound/soc/s3c24xx/s3c24xx-i2s.c
index ff614d645e79..ba4476b55fbc 100644
--- a/sound/soc/s3c24xx/s3c24xx-i2s.c
+++ b/sound/soc/s3c24xx/s3c24xx-i2s.c
@@ -27,12 +27,12 @@
 #include <sound/initval.h>
 #include <sound/soc.h>
 
-#include <asm/arch/hardware.h>
-#include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-clock.h>
-#include <asm/arch/audio.h>
+#include <mach/hardware.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-clock.h>
+#include <mach/audio.h>
 #include <asm/dma.h>
-#include <asm/arch/dma.h>
+#include <mach/dma.h>
 
 #include <asm/plat-s3c24xx/regs-iis.h>
 
diff --git a/sound/soc/s3c24xx/s3c24xx-pcm.c b/sound/soc/s3c24xx/s3c24xx-pcm.c
index fadd33e2a733..e13e614bada9 100644
--- a/sound/soc/s3c24xx/s3c24xx-pcm.c
+++ b/sound/soc/s3c24xx/s3c24xx-pcm.c
@@ -27,9 +27,9 @@
 #include <sound/soc.h>
 
 #include <asm/dma.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/dma.h>
-#include <asm/arch/audio.h>
+#include <mach/hardware.h>
+#include <mach/dma.h>
+#include <mach/audio.h>
 
 #include "s3c24xx-pcm.h"