KVM: MMU: Set nx bit correctly on shadow ptes

While the page table walker correctly generates a guest page fault
if a guest tries to execute a non-executable page, the shadow code does
not mark it non-executable.  This means that if a guest accesses an nx
page first with a read access, then subsequent code fetch accesses will
succeed.

Fix by setting the nx bit on shadow ptes.

Signed-off-by: Avi Kivity <avi@qumranet.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/drivers/kvm/paging_tmpl.h b/drivers/kvm/paging_tmpl.h
index 7688cbf413c8..59ba752a6880 100644
--- a/drivers/kvm/paging_tmpl.h
+++ b/drivers/kvm/paging_tmpl.h
@@ -255,6 +255,8 @@ static void FNAME(set_pte)(struct kvm_vcpu *vcpu, pt_element_t gpte,
         spte |= gpte & PT64_NX_MASK;
         if (!dirty)
                 pte_access &= ~ACC_WRITE_MASK;
+        if (!(pte_access & ACC_EXEC_MASK))
+                spte |= PT64_NX_MASK;
 
         page = gfn_to_page(vcpu->kvm, gfn);