[ARM] Kirkwood: implement GPIO and GPIO interrupt support

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>

5 files changed, 75 insertions, 6 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f1a3b10cfa9e..d840a64c6ce6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -386,6 +386,7 @@ config ARCH_KIRKWOOD
         bool "Marvell Kirkwood"
         select CPU_FEROCEON
         select PCI
+        select GENERIC_GPIO
         select GENERIC_TIME
         select GENERIC_CLOCKEVENTS
         select PLAT_ORION
diff --git a/arch/arm/mach-kirkwood/include/mach/gpio.h b/arch/arm/mach-kirkwood/include/mach/gpio.h
new file mode 100644
index 000000000000..81b335eb62ec
--- /dev/null
+++ b/arch/arm/mach-kirkwood/include/mach/gpio.h
@@ -0,0 +1,38 @@
+/*
+ * arch/asm-arm/mach-kirkwood/include/mach/gpio.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H
+
+#include <mach/irqs.h>
+#include <plat/gpio.h>
+#include <asm-generic/gpio.h>           /* cansleep wrappers */
+
+#define GPIO_MAX                50
+#define GPIO_OFF(pin)           (((pin) >> 5) ? 0x0140 : 0x0100)
+#define GPIO_OUT(pin)           (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x00)
+#define GPIO_IO_CONF(pin)       (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x04)
+#define GPIO_BLINK_EN(pin)      (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x08)
+#define GPIO_IN_POL(pin)        (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x0c)
+#define GPIO_DATA_IN(pin)       (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x10)
+#define GPIO_EDGE_CAUSE(pin)    (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x14)
+#define GPIO_EDGE_MASK(pin)     (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x18)
+#define GPIO_LEVEL_MASK(pin)    (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x1c)
+
+static inline int gpio_to_irq(int pin)
+{
+        return pin + IRQ_KIRKWOOD_GPIO_START;
+}
+
+static inline int irq_to_gpio(int irq)
+{
+        return irq - IRQ_KIRKWOOD_GPIO_START;
+}
+
+
+#endif
diff --git a/arch/arm/mach-kirkwood/include/mach/irqs.h b/arch/arm/mach-kirkwood/include/mach/irqs.h
index 3a964bb14973..f00a0a45a67e 100644
--- a/arch/arm/mach-kirkwood/include/mach/irqs.h
+++ b/arch/arm/mach-kirkwood/include/mach/irqs.h
@@ -11,8 +11,6 @@
 #ifndef __ASM_ARCH_IRQS_H
 #define __ASM_ARCH_IRQS_H
 
-#include "kirkwood.h"   /* need GPIO_MAX */
-
 /*
  * Low Interrupt Controller
  */
@@ -57,7 +55,7 @@
  * KIRKWOOD General Purpose Pins
  */
 #define IRQ_KIRKWOOD_GPIO_START 64
-#define NR_GPIO_IRQS            GPIO_MAX
+#define NR_GPIO_IRQS            50
 
 #define NR_IRQS                 (IRQ_KIRKWOOD_GPIO_START + NR_GPIO_IRQS)
 
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index eae42406fd86..ada480c0e197 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -117,7 +117,4 @@
 #define SATA_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x80000)
 
 
-#define GPIO_MAX                50
-
-
 #endif
diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c
index 5790643ffe07..efb86b700276 100644
--- a/arch/arm/mach-kirkwood/irq.c
+++ b/arch/arm/mach-kirkwood/irq.c
@@ -13,10 +13,45 @@
 #include <linux/irq.h>
 #include <linux/io.h>
 #include <plat/irq.h>
+#include <asm/gpio.h>
 #include "common.h"
 
+static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+        BUG_ON(irq < IRQ_KIRKWOOD_GPIO_LOW_0_7);
+        BUG_ON(irq > IRQ_KIRKWOOD_GPIO_HIGH_16_23);
+
+        orion_gpio_irq_handler((irq - IRQ_KIRKWOOD_GPIO_LOW_0_7) << 3);
+}
+
 void __init kirkwood_init_irq(void)
 {
+        int i;
+
         orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
         orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
+
+        /*
+         * Mask and clear GPIO IRQ interrupts.
+         */
+        writel(0, GPIO_LEVEL_MASK(0));
+        writel(0, GPIO_EDGE_MASK(0));
+        writel(0, GPIO_EDGE_CAUSE(0));
+        writel(0, GPIO_LEVEL_MASK(32));
+        writel(0, GPIO_EDGE_MASK(32));
+        writel(0, GPIO_EDGE_CAUSE(32));
+
+        for (i = IRQ_KIRKWOOD_GPIO_START; i < NR_IRQS; i++) {
+                set_irq_chip(i, &orion_gpio_irq_level_chip);
+                set_irq_handler(i, handle_level_irq);
+                irq_desc[i].status |= IRQ_LEVEL;
+                set_irq_flags(i, IRQF_VALID);
+        }
+        set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler);
+        set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler);
+        set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler);
+        set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler);
+        set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler);
+        set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler);
+        set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23, gpio_irq_handler);
 }