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authorDavid Daney <ddaney@caviumnetworks.com>2008-12-11 18:33:27 -0500
committerRalf Baechle <ralf@linux-mips.org>2009-01-11 04:57:22 -0500
commit47d979eca33f8df49bfead2d5efa23a70b413882 (patch)
treee70554c6042ba2acf5c01df8e15a572ebf6e60d3
parent0dd4781bca56871434507ed35d5bb8ef92077907 (diff)
MIPS: Hook Cavium OCTEON cache init into cache.c
Follow precedent of other boards, and hook-up the CPU specific cache init. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--arch/mips/include/asm/cpu-features.h3
-rw-r--r--arch/mips/mm/cache.c6
2 files changed, 9 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 12d12dfe73c0..a0d14f85b781 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -38,6 +38,9 @@
38#ifndef cpu_has_tx39_cache 38#ifndef cpu_has_tx39_cache
39#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE) 39#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
40#endif 40#endif
41#ifndef cpu_has_octeon_cache
42#define cpu_has_octeon_cache 0
43#endif
41#ifndef cpu_has_fpu 44#ifndef cpu_has_fpu
42#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) 45#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
43#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) 46#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 1eb7c71e3d6a..98ad0a82c29e 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -182,6 +182,12 @@ void __devinit cpu_cache_init(void)
182 tx39_cache_init(); 182 tx39_cache_init();
183 } 183 }
184 184
185 if (cpu_has_octeon_cache) {
186 extern void __weak octeon_cache_init(void);
187
188 octeon_cache_init();
189 }
190
185 setup_protection_map(); 191 setup_protection_map();
186} 192}
187 193