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authorSyed Mohammed, Khasim <x0khasim@ti.com>2007-06-22 00:48:07 -0400
committerTony Lindgren <tony@atomide.com>2008-02-08 13:38:00 -0500
commit471b3aa70c2ba00e1a8c8399f848cbc04fd0beae (patch)
tree3601fc47ee59160ad209d8f08532304009124676
parentf8151e5c327bfc41f0993a45fb61ea121bebfee4 (diff)
ARM: OMAP: Pre-3430 clean-up for dmtimer.c
Cleanup DM timer list for OMAP2 and OMAP1 to allow adding support for 3430. Signed-off-by: Syed Mohammed Khasim <x0khasim@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-rw-r--r--arch/arm/plat-omap/dmtimer.c65
1 files changed, 41 insertions, 24 deletions
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 3856f5aedfc1..0b5689edf2f2 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -48,7 +48,7 @@
48#define OMAP_TIMER_COUNTER_REG 0x28 48#define OMAP_TIMER_COUNTER_REG 0x28
49#define OMAP_TIMER_LOAD_REG 0x2c 49#define OMAP_TIMER_LOAD_REG 0x2c
50#define OMAP_TIMER_TRIGGER_REG 0x30 50#define OMAP_TIMER_TRIGGER_REG 0x30
51#define OMAP_TIMER_WRITE_PEND_REG 0x34 51#define OMAP_TIMER_WRITE_PEND_REG 0x34
52#define OMAP_TIMER_MATCH_REG 0x38 52#define OMAP_TIMER_MATCH_REG 0x38
53#define OMAP_TIMER_CAPTURE_REG 0x3c 53#define OMAP_TIMER_CAPTURE_REG 0x3c
54#define OMAP_TIMER_IF_CTRL_REG 0x40 54#define OMAP_TIMER_IF_CTRL_REG 0x40
@@ -82,8 +82,11 @@ struct omap_dm_timer {
82 82
83#define omap_dm_clk_enable(x) 83#define omap_dm_clk_enable(x)
84#define omap_dm_clk_disable(x) 84#define omap_dm_clk_disable(x)
85#define omap2_dm_timers NULL
86#define omap2_dm_source_names NULL
87#define omap2_dm_source_clocks NULL
85 88
86static struct omap_dm_timer dm_timers[] = { 89static struct omap_dm_timer omap1_dm_timers[] = {
87 { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 }, 90 { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
88 { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 }, 91 { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 },
89 { .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 }, 92 { .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 },
@@ -94,12 +97,15 @@ static struct omap_dm_timer dm_timers[] = {
94 { .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 }, 97 { .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 },
95}; 98};
96 99
100static const int dm_timer_count = ARRAY_SIZE(omap1_dm_timers);
101
97#elif defined(CONFIG_ARCH_OMAP2) 102#elif defined(CONFIG_ARCH_OMAP2)
98 103
99#define omap_dm_clk_enable(x) clk_enable(x) 104#define omap_dm_clk_enable(x) clk_enable(x)
100#define omap_dm_clk_disable(x) clk_disable(x) 105#define omap_dm_clk_disable(x) clk_disable(x)
106#define omap1_dm_timers NULL
101 107
102static struct omap_dm_timer dm_timers[] = { 108static struct omap_dm_timer omap2_dm_timers[] = {
103 { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 }, 109 { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
104 { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 }, 110 { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 },
105 { .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 }, 111 { .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 },
@@ -114,13 +120,15 @@ static struct omap_dm_timer dm_timers[] = {
114 { .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 }, 120 { .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 },
115}; 121};
116 122
117static const char *dm_source_names[] = { 123static const char *omap2_dm_source_names[] __initdata = {
118 "sys_ck", 124 "sys_ck",
119 "func_32k_ck", 125 "func_32k_ck",
120 "alt_ck" 126 "alt_ck",
127 NULL
121}; 128};
122 129
123static struct clk *dm_source_clocks[3]; 130static struct clk **omap2_dm_source_clocks[3];
131static const int dm_timer_count = ARRAY_SIZE(omap2_dm_timers);
124 132
125#else 133#else
126 134
@@ -128,7 +136,10 @@ static struct clk *dm_source_clocks[3];
128 136
129#endif 137#endif
130 138
131static const int dm_timer_count = ARRAY_SIZE(dm_timers); 139static struct omap_dm_timer *dm_timers;
140static char **dm_source_names;
141static struct clk **dm_source_clocks;
142
132static spinlock_t dm_timer_lock; 143static spinlock_t dm_timer_lock;
133 144
134static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg) 145static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg)
@@ -486,7 +497,7 @@ int omap_dm_timers_active(void)
486 return 0; 497 return 0;
487} 498}
488 499
489int omap_dm_timer_init(void) 500int __init omap_dm_timer_init(void)
490{ 501{
491 struct omap_dm_timer *timer; 502 struct omap_dm_timer *timer;
492 int i; 503 int i;
@@ -495,27 +506,33 @@ int omap_dm_timer_init(void)
495 return -ENODEV; 506 return -ENODEV;
496 507
497 spin_lock_init(&dm_timer_lock); 508 spin_lock_init(&dm_timer_lock);
498#ifdef CONFIG_ARCH_OMAP2 509
499 for (i = 0; i < ARRAY_SIZE(dm_source_names); i++) { 510 if (cpu_class_is_omap1())
500 dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]); 511 dm_timers = omap1_dm_timers;
501 BUG_ON(dm_source_clocks[i] == NULL); 512 else if (cpu_is_omap24xx()) {
513 dm_timers = omap2_dm_timers;
514 dm_source_names = (char **)omap2_dm_source_names;
515 dm_source_clocks = (struct clk **)omap2_dm_source_clocks;
502 } 516 }
503#endif 517
518 if (cpu_class_is_omap2())
519 for (i = 0; dm_source_names[i] != NULL; i++)
520 dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]);
521
504 if (cpu_is_omap243x()) 522 if (cpu_is_omap243x())
505 dm_timers[0].phys_base = 0x49018000; 523 dm_timers[0].phys_base = 0x49018000;
506 524
507 for (i = 0; i < dm_timer_count; i++) { 525 for (i = 0; i < dm_timer_count; i++) {
508#ifdef CONFIG_ARCH_OMAP2
509 char clk_name[16];
510#endif
511
512 timer = &dm_timers[i]; 526 timer = &dm_timers[i];
513 timer->io_base = (void __iomem *) io_p2v(timer->phys_base); 527 timer->io_base = (void __iomem *)io_p2v(timer->phys_base);
514#ifdef CONFIG_ARCH_OMAP2 528#ifdef CONFIG_ARCH_OMAP2
515 sprintf(clk_name, "gpt%d_ick", i + 1); 529 if (cpu_class_is_omap2()) {
516 timer->iclk = clk_get(NULL, clk_name); 530 char clk_name[16];
517 sprintf(clk_name, "gpt%d_fck", i + 1); 531 sprintf(clk_name, "gpt%d_ick", i + 1);
518 timer->fclk = clk_get(NULL, clk_name); 532 timer->iclk = clk_get(NULL, clk_name);
533 sprintf(clk_name, "gpt%d_fck", i + 1);
534 timer->fclk = clk_get(NULL, clk_name);
535 }
519#endif 536#endif
520 } 537 }
521 538