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authorKyle McMartin <kyle@parisc-linux.org>2006-08-13 22:15:47 -0400
committerMatthew Wilcox <willy@parisc-linux.org>2006-10-04 08:44:47 -0400
commit4068d93cd17561bcbfc821c831cb048385320bd6 (patch)
treedb2e8f3ad3c8ab729cff1304cba984a4bc0a3735
parent78b656b8bf933101b42409b4492734b23427bfc3 (diff)
[PARISC] Untangle <asm/processor.h> header include mess
asm/processor.h on parisc wants spinlocks for cpuinfo, but linux/spinlock_types.h needs lockdep, and lockdep wants prefetch. This leads to a horrible circular dependancy, because <asm/processor.h> is including something which depends on things which are not defined until the end of the file. Kludge around this by moving prefetch related code into <asm/prefetch.h> and including it before <linux/spinlock_types.h>, however this is just a temporary solution until this mess can be cleaned up. Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
-rw-r--r--include/asm-parisc/prefetch.h36
-rw-r--r--include/asm-parisc/processor.h28
2 files changed, 38 insertions, 26 deletions
diff --git a/include/asm-parisc/prefetch.h b/include/asm-parisc/prefetch.h
new file mode 100644
index 000000000000..f5a2e7ae2662
--- /dev/null
+++ b/include/asm-parisc/prefetch.h
@@ -0,0 +1,36 @@
1/*
2 * include/asm-parisc/prefetch.h
3 *
4 * PA 2.0 defines data prefetch instructions on page 6-11 of the Kane book.
5 * In addition, many implementations do hardware prefetching of both
6 * instructions and data.
7 *
8 * PA7300LC (page 14-4 of the ERS) also implements prefetching by a load
9 * to gr0 but not in a way that Linux can use. If the load would cause an
10 * interruption (eg due to prefetching 0), it is suppressed on PA2.0
11 * processors, but not on 7300LC.
12 *
13 */
14
15#ifndef __ASM_PARISC_PREFETCH_H
16#define __ASM_PARISC_PREFETCH_H
17
18#ifndef __ASSEMBLY__
19#ifdef CONFIG_PREFETCH
20
21#define ARCH_HAS_PREFETCH
22extern inline void prefetch(const void *addr)
23{
24 __asm__("ldw 0(%0), %%r0" : : "r" (addr));
25}
26
27#define ARCH_HAS_PREFETCHW
28extern inline void prefetchw(const void *addr)
29{
30 __asm__("ldd 0(%0), %%r0" : : "r" (addr));
31}
32
33#endif /* CONFIG_PREFETCH */
34#endif /* __ASSEMBLY__ */
35
36#endif /* __ASM_PARISC_PROCESSOR_H */
diff --git a/include/asm-parisc/processor.h b/include/asm-parisc/processor.h
index b73626f040da..c72b8fa49686 100644
--- a/include/asm-parisc/processor.h
+++ b/include/asm-parisc/processor.h
@@ -9,6 +9,8 @@
9#define __ASM_PARISC_PROCESSOR_H 9#define __ASM_PARISC_PROCESSOR_H
10 10
11#ifndef __ASSEMBLY__ 11#ifndef __ASSEMBLY__
12#include <asm/prefetch.h> /* lockdep.h needs <linux/prefetch.h> */
13
12#include <linux/threads.h> 14#include <linux/threads.h>
13#include <linux/spinlock_types.h> 15#include <linux/spinlock_types.h>
14 16
@@ -328,32 +330,6 @@ extern unsigned long get_wchan(struct task_struct *p);
328#define KSTK_EIP(tsk) ((tsk)->thread.regs.iaoq[0]) 330#define KSTK_EIP(tsk) ((tsk)->thread.regs.iaoq[0])
329#define KSTK_ESP(tsk) ((tsk)->thread.regs.gr[30]) 331#define KSTK_ESP(tsk) ((tsk)->thread.regs.gr[30])
330 332
331
332/*
333 * PA 2.0 defines data prefetch instructions on page 6-11 of the Kane book.
334 * In addition, many implementations do hardware prefetching of both
335 * instructions and data.
336 *
337 * PA7300LC (page 14-4 of the ERS) also implements prefetching by a load
338 * to gr0 but not in a way that Linux can use. If the load would cause an
339 * interruption (eg due to prefetching 0), it is suppressed on PA2.0
340 * processors, but not on 7300LC.
341 */
342#ifdef CONFIG_PREFETCH
343#define ARCH_HAS_PREFETCH
344#define ARCH_HAS_PREFETCHW
345
346extern inline void prefetch(const void *addr)
347{
348 __asm__("ldw 0(%0), %%r0" : : "r" (addr));
349}
350
351extern inline void prefetchw(const void *addr)
352{
353 __asm__("ldd 0(%0), %%r0" : : "r" (addr));
354}
355#endif
356
357#define cpu_relax() barrier() 333#define cpu_relax() barrier()
358 334
359#endif /* __ASSEMBLY__ */ 335#endif /* __ASSEMBLY__ */