[MIPS] Don't drag a platform specific header into generic arch code.

For some platforms it's definitions may conflict.  So that's the one-liner.
The rest is 10 square kilometers of collateral damage fixup this include
used to paper over.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

16 files changed, 73 insertions, 86 deletions

diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index 21eb5993a19f..2e011470c347 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -13,9 +13,9 @@
 #include <asm/system.h>
 #include <asm/hardirq.h>
 #include <asm/hazards.h>
+#include <asm/irq.h>
 #include <asm/mmu_context.h>
 #include <asm/smp.h>
-#include <asm/mips-boards/maltaint.h>
 #include <asm/mipsregs.h>
 #include <asm/cacheflush.h>
 #include <asm/time.h>
@@ -614,7 +614,7 @@ int setup_irq_smtc(unsigned int irq, struct irqaction * new,
 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
         unsigned int vpe = current_cpu_data.vpe_id;
 
-        vpemask[vpe][irq - MIPSCPU_INT_BASE] = 1;
+        vpemask[vpe][irq - MIPS_CPU_IRQ_BASE] = 1;
 #endif
         irq_hwmask[irq] = hwmask;
 
@@ -822,7 +822,7 @@ void ipi_decode(struct smtc_ipi *pipi)
         switch (type_copy) {
         case SMTC_CLOCK_TICK:
                 irq_enter();
-                kstat_this_cpu.irqs[MIPSCPU_INT_BASE + MIPSCPU_INT_CPUCTR]++;
+                kstat_this_cpu.irqs[MIPS_CPU_IRQ_BASE + cp0_perfcount_irq]++;
                 /* Invoke Clock "Interrupt" */
                 ipi_timer_latch[dest_copy] = 0;
 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index 7def1ff3da94..d48d1d5bea0a 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -200,10 +200,15 @@ EXPORT_SYMBOL(null_perf_irq);
 EXPORT_SYMBOL(perf_irq);
 
 /*
+ * Timer interrupt
+ */
+int cp0_compare_irq;
+
+/*
  * Performance counter IRQ or -1 if shared with timer
  */
-int mipsxx_perfcount_irq;
-EXPORT_SYMBOL(mipsxx_perfcount_irq);
+int cp0_perfcount_irq;
+EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
 
 /*
  * Possibly handle a performance counter interrupt.
@@ -213,12 +218,12 @@ static inline int handle_perf_irq (int r2)
 {
         /*
          * The performance counter overflow interrupt may be shared with the
-         * timer interrupt (mipsxx_perfcount_irq < 0). If it is and a
+         * timer interrupt (cp0_perfcount_irq < 0). If it is and a
          * performance counter has overflowed (perf_irq() == IRQ_HANDLED)
          * and we can't reliably determine if a counter interrupt has also
          * happened (!r2) then don't check for a timer interrupt.
          */
-        return (mipsxx_perfcount_irq < 0) &&
+        return (cp0_perfcount_irq < 0) &&
                 perf_irq() == IRQ_HANDLED &&
                 !r2;
 }
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index a7a17eb9bfcd..b1233644fcca 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1350,9 +1350,6 @@ void __init per_cpu_trap_init(void)
         if (!secondaryTC) {
 #endif /* CONFIG_MIPS_MT_SMTC */
 
-        /*
-         * Interrupt handling.
-         */
         if (cpu_has_veic || cpu_has_vint) {
                 write_c0_ebase (ebase);
                 /* Setting vector spacing enables EI/VI mode  */
@@ -1366,6 +1363,23 @@ void __init per_cpu_trap_init(void)
                 } else
                         set_c0_cause(CAUSEF_IV);
         }
+
+        /*
+         * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
+         *
+         *  o read IntCtl.IPTI to determine the timer interrupt
+         *  o read IntCtl.IPPCI to determine the performance counter interrupt
+         */
+        if (cpu_has_mips_r2) {
+                cp0_compare_irq = (read_c0_intctl () >> 29) & 7;
+                cp0_perfcount_irq = -1;
+        } else {
+                cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
+                cp0_perfcount_irq = (read_c0_intctl () >> 26) & 7;
+                if (cp0_perfcount_irq != cp0_compare_irq)
+                        cp0_perfcount_irq = -1;
+        }
+
 #ifdef CONFIG_MIPS_MT_SMTC
         }
 #endif /* CONFIG_MIPS_MT_SMTC */
diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c
index 9f49da95aacf..6c8f0255e85d 100644
--- a/arch/mips/mips-boards/atlas/atlas_int.c
+++ b/arch/mips/mips-boards/atlas/atlas_int.c
@@ -189,7 +189,7 @@ asmlinkage void plat_irq_dispatch(void)
         if (irq == MIPSCPU_INT_ATLAS)
                 atlas_hw0_irqdispatch();
         else if (irq >= 0)
-                do_IRQ(MIPSCPU_INT_BASE + irq);
+                do_IRQ(MIPS_CPU_IRQ_BASE + irq);
         else
                 spurious_interrupt();
 }
@@ -261,11 +261,11 @@ void __init arch_init_irq(void)
         } else if (cpu_has_vint) {
                 set_vi_handler (MIPSCPU_INT_ATLAS, atlas_hw0_irqdispatch);
 #ifdef CONFIG_MIPS_MT_SMTC
-                setup_irq_smtc (MIPSCPU_INT_BASE + MIPSCPU_INT_ATLAS,
+                setup_irq_smtc (MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS,
                                 &atlasirq, (0x100 << MIPSCPU_INT_ATLAS));
 #else /* Not SMTC */
-                setup_irq(MIPSCPU_INT_BASE + MIPSCPU_INT_ATLAS, &atlasirq);
+                setup_irq(MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS, &atlasirq);
 #endif /* CONFIG_MIPS_MT_SMTC */
         } else
-                setup_irq(MIPSCPU_INT_BASE + MIPSCPU_INT_ATLAS, &atlasirq);
+                setup_irq(MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS, &atlasirq);
 }
diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c
index 8f1000f51b3d..c45d556aa96b 100644
--- a/arch/mips/mips-boards/generic/time.c
+++ b/arch/mips/mips-boards/generic/time.c
@@ -54,7 +54,7 @@
 unsigned long cpu_khz;
 
 static int mips_cpu_timer_irq;
-extern int mipsxx_perfcount_irq;
+extern int cp0_perfcount_irq;
 extern void smtc_timer_broadcast(int);
 
 static void mips_timer_dispatch(void)
@@ -64,7 +64,7 @@ static void mips_timer_dispatch(void)
 
 static void mips_perf_dispatch(void)
 {
-        do_IRQ(mipsxx_perfcount_irq);
+        do_IRQ(cp0_perfcount_irq);
 }
 
 /*
@@ -82,12 +82,12 @@ static inline int handle_perf_irq (int r2)
 {
         /*
          * The performance counter overflow interrupt may be shared with the
-         * timer interrupt (mipsxx_perfcount_irq < 0). If it is and a
+         * timer interrupt (cp0_perfcount_irq < 0). If it is and a
          * performance counter has overflowed (perf_irq() == IRQ_HANDLED)
          * and we can't reliably determine if a counter interrupt has also
          * happened (!r2) then don't check for a timer interrupt.
          */
-        return (mipsxx_perfcount_irq < 0) &&
+        return (cp0_perfcount_irq < 0) &&
                 perf_irq() == IRQ_HANDLED &&
                 !r2;
 }
@@ -259,42 +259,31 @@ static struct irqaction perf_irqaction = {
 
 void __init plat_perf_setup(struct irqaction *irq)
 {
-        int hwint = 0;
-        mipsxx_perfcount_irq = -1;
+        cp0_perfcount_irq = -1;
 
 #ifdef MSC01E_INT_BASE
         if (cpu_has_veic) {
                 set_vi_handler (MSC01E_INT_PERFCTR, mips_perf_dispatch);
-                mipsxx_perfcount_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
+                cp0_perfcount_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
         } else
 #endif
-        if (cpu_has_mips_r2) {
-                /*
-                 * Read IntCtl.IPPCI to determine the performance
-                 * counter interrupt
-                 */
-                hwint = (read_c0_intctl () >> 26) & 7;
-                if (hwint != MIPSCPU_INT_CPUCTR) {
-                        if (cpu_has_vint)
-                                set_vi_handler (hwint, mips_perf_dispatch);
-                        mipsxx_perfcount_irq = MIPSCPU_INT_BASE + hwint;
-                }
-        }
-        if (mipsxx_perfcount_irq >= 0) {
+        if (cp0_perfcount_irq >= 0) {
+                if (cpu_has_vint)
+                        set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
 #ifdef CONFIG_MIPS_MT_SMTC
-                setup_irq_smtc(mipsxx_perfcount_irq, irq, 0x100 << hwint);
+                setup_irq_smtc(cp0_perfcount_irq, irq,
+                               0x100 << cp0_perfcount_irq);
 #else
-                setup_irq(mipsxx_perfcount_irq, irq);
+                setup_irq(cp0_perfcount_irq, irq);
 #endif /* CONFIG_MIPS_MT_SMTC */
 #ifdef CONFIG_SMP
-                set_irq_handler(mipsxx_perfcount_irq, handle_percpu_irq);
+                set_irq_handler(cp0_perfcount_irq, handle_percpu_irq);
 #endif
         }
 }
 
 void __init plat_timer_setup(struct irqaction *irq)
 {
-        int hwint = 0;
 #ifdef MSC01E_INT_BASE
         if (cpu_has_veic) {
                 set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch);
@@ -303,22 +292,15 @@ void __init plat_timer_setup(struct irqaction *irq)
         else
 #endif
         {
-                if (cpu_has_mips_r2)
-                        /*
-                         * Read IntCtl.IPTI to determine the timer interrupt
-                         */
-                        hwint = (read_c0_intctl () >> 29) & 7;
-                else
-                        hwint = MIPSCPU_INT_CPUCTR;
                 if (cpu_has_vint)
-                        set_vi_handler (hwint, mips_timer_dispatch);
-                mips_cpu_timer_irq = MIPSCPU_INT_BASE + hwint;
+                        set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
+                mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
         }
 
         /* we are using the cpu counter for timer interrupts */
         irq->handler = mips_timer_interrupt;    /* we use our own handler */
 #ifdef CONFIG_MIPS_MT_SMTC
-        setup_irq_smtc(mips_cpu_timer_irq, irq, 0x100 << hwint);
+        setup_irq_smtc(mips_cpu_timer_irq, irq, 0x100 << cp0_compare_irq);
 #else
         setup_irq(mips_cpu_timer_irq, irq);
 #endif /* CONFIG_MIPS_MT_SMTC */
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
index 1668cc21d5b5..c78d48349600 100644
--- a/arch/mips/mips-boards/malta/malta_int.c
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -257,7 +257,7 @@ asmlinkage void plat_irq_dispatch(void)
         if (irq == MIPSCPU_INT_I8259A)
                 malta_hw0_irqdispatch();
         else if (irq > 0)
-                do_IRQ(MIPSCPU_INT_BASE + irq);
+                do_IRQ(MIPS_CPU_IRQ_BASE + irq);
         else
                 spurious_interrupt();
 }
@@ -326,17 +326,17 @@ void __init arch_init_irq(void)
                 set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
                 set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch);
 #ifdef CONFIG_MIPS_MT_SMTC
-                setup_irq_smtc (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq,
+                setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq,
                         (0x100 << MIPSCPU_INT_I8259A));
-                setup_irq_smtc (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI,
+                setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
                         &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI));
 #else /* Not SMTC */
-                setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
-                setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
+                setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
+                setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
 #endif /* CONFIG_MIPS_MT_SMTC */
         }
         else {
-                setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
-                setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
+                setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
+                setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
         }
 }
diff --git a/arch/mips/mips-boards/sead/sead_int.c b/arch/mips/mips-boards/sead/sead_int.c
index c4b9de3a7f27..9ca0f82f1360 100644
--- a/arch/mips/mips-boards/sead/sead_int.c
+++ b/arch/mips/mips-boards/sead/sead_int.c
@@ -106,7 +106,7 @@ asmlinkage void plat_irq_dispatch(void)
         irq = irq_ffs(pending);
 
         if (irq >= 0)
-                do_IRQ(MIPSCPU_INT_BASE + irq);
+                do_IRQ(MIPS_CPU_IRQ_BASE + irq);
         else
                 spurious_interrupt();
 }
diff --git a/arch/mips/mips-boards/sead/sead_setup.c b/arch/mips/mips-boards/sead/sead_setup.c
index 811aba100605..bb801409d39b 100644
--- a/arch/mips/mips-boards/sead/sead_setup.c
+++ b/arch/mips/mips-boards/sead/sead_setup.c
@@ -68,7 +68,7 @@ static void __init serial_init(void)
 #else
         s.iobase = SEAD_UART0_REGS_BASE+3;
 #endif
-        s.irq = MIPSCPU_INT_BASE + MIPSCPU_INT_UART0;
+        s.irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_UART0;
         s.uartclk = SEAD_BASE_BAUD * 16;
         s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ;
         s.iotype = UPIO_PORT;
diff --git a/arch/mips/mips-boards/sim/sim_int.c b/arch/mips/mips-boards/sim/sim_int.c
index 15ac0655c1ff..766e0159ee5b 100644
--- a/arch/mips/mips-boards/sim/sim_int.c
+++ b/arch/mips/mips-boards/sim/sim_int.c
@@ -77,7 +77,7 @@ asmlinkage void plat_irq_dispatch(void)
         irq = irq_ffs(pending);
 
         if (irq > 0)
-                do_IRQ(MIPSCPU_INT_BASE + irq);
+                do_IRQ(MIPS_CPU_IRQ_BASE + irq);
         else
                 spurious_interrupt();
 }
diff --git a/arch/mips/mips-boards/sim/sim_time.c b/arch/mips/mips-boards/sim/sim_time.c
index d3a21c741514..7224ffe31d36 100644
--- a/arch/mips/mips-boards/sim/sim_time.c
+++ b/arch/mips/mips-boards/sim/sim_time.c
@@ -71,8 +71,8 @@ irqreturn_t sim_timer_interrupt(int irq, void *dev_id)
 
         int vpflags = dvpe();
         write_c0_compare (read_c0_count() - 1);
-        clear_c0_cause(0x100 << MIPSCPU_INT_CPUCTR);
-        set_c0_status(0x100 << MIPSCPU_INT_CPUCTR);
+        clear_c0_cause(0x100 << cp0_compare_irq);
+        set_c0_status(0x100 << cp0_compare_irq);
         irq_enable_hazard();
         evpe(vpflags);
 
@@ -183,8 +183,8 @@ void __init plat_timer_setup(struct irqaction *irq)
         }
         else {
                 if (cpu_has_vint)
-                        set_vi_handler(MIPSCPU_INT_CPUCTR, mips_timer_dispatch);
-                mips_cpu_timer_irq = MIPSCPU_INT_BASE + MIPSCPU_INT_CPUCTR;
+                        set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
+                mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
         }
 
         /* we are using the cpu counter for timer interrupts */
diff --git a/drivers/net/mipsnet.c b/drivers/net/mipsnet.c
index 638a279ec505..9853c74f6bbf 100644
--- a/drivers/net/mipsnet.c
+++ b/drivers/net/mipsnet.c
@@ -240,7 +240,7 @@ static int __init mipsnet_probe(struct device *dev)
          * TODO: probe for these or load them from PARAM
          */
         netdev->base_addr = 0x4200;
-        netdev->irq = MIPSCPU_INT_BASE + MIPSCPU_INT_MB0 +
+        netdev->irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_MB0 +
                       inl(mipsnet_reg_address(netdev, interruptInfo));
 
         // Get the io region now, get irq on open()
diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h
index 91803ba30ff2..3ca6a076124d 100644
--- a/include/asm-mips/irq.h
+++ b/include/asm-mips/irq.h
@@ -72,4 +72,13 @@ extern int allocate_irqno(void);
 extern void alloc_legacy_irqno(void);
 extern void free_irqno(unsigned int irq);
 
+/*
+ * Before R2 the timer and performance counter interrupts were both fixed to
+ * IE7.  Since R2 their number has to be read from the c0_intctl register.
+ */
+#define CP0_LEGACY_COMPARE_IRQ 7
+
+extern int cp0_compare_irq;
+extern int cp0_perfcount_irq;
+
 #endif /* _ASM_IRQ_H */
diff --git a/include/asm-mips/mips-boards/atlasint.h b/include/asm-mips/mips-boards/atlasint.h
index 76add42e486e..93ba1c1b2a4f 100644
--- a/include/asm-mips/mips-boards/atlasint.h
+++ b/include/asm-mips/mips-boards/atlasint.h
@@ -28,11 +28,6 @@
 
 #include <irq.h>
 
-/*
- * Interrupts 0..7 are used for Atlas CPU interrupts (nonEIC mode)
- */
-#define MIPSCPU_INT_BASE        MIPS_CPU_IRQ_BASE
-
 /* CPU interrupt offsets */
 #define MIPSCPU_INT_SW0         0
 #define MIPSCPU_INT_SW1         1
@@ -42,7 +37,6 @@
 #define MIPSCPU_INT_MB2         4
 #define MIPSCPU_INT_MB3         5
 #define MIPSCPU_INT_MB4         6
-#define MIPSCPU_INT_CPUCTR      7
 
 /*
  * Interrupts 8..39 are used for Atlas interrupt controller interrupts
diff --git a/include/asm-mips/mips-boards/maltaint.h b/include/asm-mips/mips-boards/maltaint.h
index 9180d6466113..7461318f1cd1 100644
--- a/include/asm-mips/mips-boards/maltaint.h
+++ b/include/asm-mips/mips-boards/maltaint.h
@@ -32,11 +32,6 @@
  */
 #define MALTA_INT_BASE          0
 
-/*
- * Interrupts 16..23 are used for Malta CPU interrupts (nonEIC mode)
- */
-#define MIPSCPU_INT_BASE        MIPS_CPU_IRQ_BASE
-
 /* CPU interrupt offsets */
 #define MIPSCPU_INT_SW0         0
 #define MIPSCPU_INT_SW1         1
@@ -49,7 +44,6 @@
 #define MIPSCPU_INT_COREHI      MIPSCPU_INT_MB3
 #define MIPSCPU_INT_MB4         6
 #define MIPSCPU_INT_CORELO      MIPSCPU_INT_MB4
-#define MIPSCPU_INT_CPUCTR      7
 
 /*
  * Interrupts 64..127 are used for Soc-it Classic interrupts
diff --git a/include/asm-mips/mips-boards/seadint.h b/include/asm-mips/mips-boards/seadint.h
index 4f6a3933699d..e710bae07340 100644
--- a/include/asm-mips/mips-boards/seadint.h
+++ b/include/asm-mips/mips-boards/seadint.h
@@ -22,14 +22,7 @@
 
 #include <irq.h>
 
-/*
- * Interrupts 0..7 are used for SEAD CPU interrupts
- */
-#define MIPSCPU_INT_BASE        MIPS_CPU_IRQ_BASE
-
 #define MIPSCPU_INT_UART0       2
 #define MIPSCPU_INT_UART1       3
 
-#define MIPSCPU_INT_CPUCTR      7
-
 #endif /* !(_MIPS_SEADINT_H) */
diff --git a/include/asm-mips/mips-boards/simint.h b/include/asm-mips/mips-boards/simint.h
index 54f2fe621d69..8ef6db76d5c1 100644
--- a/include/asm-mips/mips-boards/simint.h
+++ b/include/asm-mips/mips-boards/simint.h
@@ -21,15 +21,11 @@
 
 #define SIM_INT_BASE            0
 #define MIPSCPU_INT_MB0         2
-#define MIPSCPU_INT_BASE        MIPS_CPU_IRQ_BASE
 #define MIPS_CPU_TIMER_IRQ      7
 
 
-#define MIPSCPU_INT_CPUCTR      7
-
 #define MSC01E_INT_BASE         64
 
-#define MIPSCPU_INT_CPUCTR      7
 #define MSC01E_INT_CPUCTR       11
 
 #endif