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authorAndi Kleen <ak@suse.de>2007-05-02 13:27:20 -0400
committerAndi Kleen <andi@basil.nowhere.org>2007-05-02 13:27:20 -0400
commit3aefbe0746580a710d4392a884ac1e4aac7c728f (patch)
treea83d2b9dccdce97c57e5914831310762dd27a5de
parente859dc553c857f4672b3bbb73ee9170a901f8712 (diff)
[PATCH] i386: Implement X86_FEATURE_SYNC_RDTSC on i386
Syncs up with x86-64. Signed-off-by: Andi Kleen <ak@suse.de>
-rw-r--r--arch/i386/kernel/cpu/intel.c4
-rw-r--r--include/asm-i386/cpufeature.h1
-rw-r--r--include/asm-i386/tsc.h4
3 files changed, 4 insertions, 5 deletions
diff --git a/arch/i386/kernel/cpu/intel.c b/arch/i386/kernel/cpu/intel.c
index 56fe26584957..dc4e08147b1f 100644
--- a/arch/i386/kernel/cpu/intel.c
+++ b/arch/i386/kernel/cpu/intel.c
@@ -188,8 +188,10 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
188 } 188 }
189#endif 189#endif
190 190
191 if (c->x86 == 15) 191 if (c->x86 == 15) {
192 set_bit(X86_FEATURE_P4, c->x86_capability); 192 set_bit(X86_FEATURE_P4, c->x86_capability);
193 set_bit(X86_FEATURE_SYNC_RDTSC, c->x86_capability);
194 }
193 if (c->x86 == 6) 195 if (c->x86 == 6)
194 set_bit(X86_FEATURE_P3, c->x86_capability); 196 set_bit(X86_FEATURE_P3, c->x86_capability);
195 if ((c->x86 == 0xf && c->x86_model >= 0x03) || 197 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
diff --git a/include/asm-i386/cpufeature.h b/include/asm-i386/cpufeature.h
index 20e849ae6ddc..b8a3a5a85fd3 100644
--- a/include/asm-i386/cpufeature.h
+++ b/include/asm-i386/cpufeature.h
@@ -79,6 +79,7 @@
79#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ 79#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */
80#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ 80#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */
81#define X86_FEATURE_LAPIC_TIMER_BROKEN (3*32+ 14) /* lapic timer broken in C1 */ 81#define X86_FEATURE_LAPIC_TIMER_BROKEN (3*32+ 14) /* lapic timer broken in C1 */
82#define X86_FEATURE_SYNC_RDTSC (3*32+15) /* RDTSC synchronizes the CPU */
82 83
83/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ 84/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
84#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ 85#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
diff --git a/include/asm-i386/tsc.h b/include/asm-i386/tsc.h
index 346976632e15..0181f9df7539 100644
--- a/include/asm-i386/tsc.h
+++ b/include/asm-i386/tsc.h
@@ -35,7 +35,6 @@ static inline cycles_t get_cycles(void)
35static __always_inline cycles_t get_cycles_sync(void) 35static __always_inline cycles_t get_cycles_sync(void)
36{ 36{
37 unsigned long long ret; 37 unsigned long long ret;
38#ifdef X86_FEATURE_SYNC_RDTSC
39 unsigned eax; 38 unsigned eax;
40 39
41 /* 40 /*
@@ -44,9 +43,6 @@ static __always_inline cycles_t get_cycles_sync(void)
44 */ 43 */
45 alternative_io("cpuid", ASM_NOP2, X86_FEATURE_SYNC_RDTSC, 44 alternative_io("cpuid", ASM_NOP2, X86_FEATURE_SYNC_RDTSC,
46 "=a" (eax), "0" (1) : "ebx","ecx","edx","memory"); 45 "=a" (eax), "0" (1) : "ebx","ecx","edx","memory");
47#else
48 sync_core();
49#endif
50 rdtscll(ret); 46 rdtscll(ret);
51 47
52 return ret; 48 return ret;