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authorStuart Yoder <b08248@freescale.com>2007-03-02 14:42:33 -0500
committerPaul Mackerras <paulus@samba.org>2007-03-08 23:03:24 -0500
commit27565903e94d548256bf5923653ab2a9668c9b9f (patch)
tree9e03081e80a9fd7af6a00e9e4c3b9b1112af94a0
parent500798d48fdcffbbc7f619bd3e6b5b5cea6869d1 (diff)
[POWERPC] Update interrupt info in booting-without-of.txt
Create a new section descrbing how interrupts are represented in the device tree. Added more detail. Clarified some things. Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
-rw-r--r--Documentation/powerpc/booting-without-of.txt123
1 files changed, 87 insertions, 36 deletions
diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt
index eaa0c3285ac9..6d5a5a0fa5e8 100644
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -1108,42 +1108,7 @@ See appendix A for an example partial SOC node definition for the
1108MPC8540. 1108MPC8540.
1109 1109
1110 1110
11112) Specifying interrupt information for SOC devices 11112) Representing devices without a current OF specification
1112---------------------------------------------------
1113
1114Each device that is part of an SOC and which generates interrupts
1115should have the following properties:
1116
1117 - interrupt-parent : contains the phandle of the interrupt
1118 controller which handles interrupts for this device
1119 - interrupts : a list of tuples representing the interrupt
1120 number and the interrupt sense and level for each interrupt
1121 for this device.
1122
1123This information is used by the kernel to build the interrupt table
1124for the interrupt controllers in the system.
1125
1126Sense and level information should be encoded as follows:
1127
1128 Devices connected to openPIC-compatible controllers should encode
1129 sense and polarity as follows:
1130
1131 0 = low to high edge sensitive type enabled
1132 1 = active low level sensitive type enabled
1133 2 = active high level sensitive type enabled
1134 3 = high to low edge sensitive type enabled
1135
1136 ISA PIC interrupt controllers should adhere to the ISA PIC
1137 encodings listed below:
1138
1139 0 = active low level sensitive type enabled
1140 1 = active high level sensitive type enabled
1141 2 = high to low edge sensitive type enabled
1142 3 = low to high edge sensitive type enabled
1143
1144
1145
11463) Representing devices without a current OF specification
1147---------------------------------------------------------- 1112----------------------------------------------------------
1148 1113
1149Currently, there are many devices on SOCs that do not have a standard 1114Currently, there are many devices on SOCs that do not have a standard
@@ -1732,6 +1697,92 @@ platforms are moved over to use the flattened-device-tree model.
1732 1697
1733 More devices will be defined as this spec matures. 1698 More devices will be defined as this spec matures.
1734 1699
1700VII - Specifying interrupt information for devices
1701===================================================
1702
1703The device tree represents the busses and devices of a hardware
1704system in a form similar to the physical bus topology of the
1705hardware.
1706
1707In addition, a logical 'interrupt tree' exists which represents the
1708hierarchy and routing of interrupts in the hardware.
1709
1710The interrupt tree model is fully described in the
1711document "Open Firmware Recommended Practice: Interrupt
1712Mapping Version 0.9". The document is available at:
1713<http://playground.sun.com/1275/practice>.
1714
17151) interrupts property
1716----------------------
1717
1718Devices that generate interrupts to a single interrupt controller
1719should use the conventional OF representation described in the
1720OF interrupt mapping documentation.
1721
1722Each device which generates interrupts must have an 'interrupt'
1723property. The interrupt property value is an arbitrary number of
1724of 'interrupt specifier' values which describe the interrupt or
1725interrupts for the device.
1726
1727The encoding of an interrupt specifier is determined by the
1728interrupt domain in which the device is located in the
1729interrupt tree. The root of an interrupt domain specifies in
1730its #interrupt-cells property the number of 32-bit cells
1731required to encode an interrupt specifier. See the OF interrupt
1732mapping documentation for a detailed description of domains.
1733
1734For example, the binding for the OpenPIC interrupt controller
1735specifies an #interrupt-cells value of 2 to encode the interrupt
1736number and level/sense information. All interrupt children in an
1737OpenPIC interrupt domain use 2 cells per interrupt in their interrupts
1738property.
1739
1740The PCI bus binding specifies a #interrupt-cell value of 1 to encode
1741which interrupt pin (INTA,INTB,INTC,INTD) is used.
1742
17432) interrupt-parent property
1744----------------------------
1745
1746The interrupt-parent property is specified to define an explicit
1747link between a device node and its interrupt parent in
1748the interrupt tree. The value of interrupt-parent is the
1749phandle of the parent node.
1750
1751If the interrupt-parent property is not defined for a node, it's
1752interrupt parent is assumed to be an ancestor in the node's
1753_device tree_ hierarchy.
1754
17553) OpenPIC Interrupt Controllers
1756--------------------------------
1757
1758OpenPIC interrupt controllers require 2 cells to encode
1759interrupt information. The first cell defines the interrupt
1760number. The second cell defines the sense and level
1761information.
1762
1763Sense and level information should be encoded as follows:
1764
1765 0 = low to high edge sensitive type enabled
1766 1 = active low level sensitive type enabled
1767 2 = active high level sensitive type enabled
1768 3 = high to low edge sensitive type enabled
1769
17704) ISA Interrupt Controllers
1771----------------------------
1772
1773ISA PIC interrupt controllers require 2 cells to encode
1774interrupt information. The first cell defines the interrupt
1775number. The second cell defines the sense and level
1776information.
1777
1778ISA PIC interrupt controllers should adhere to the ISA PIC
1779encodings listed below:
1780
1781 0 = active low level sensitive type enabled
1782 1 = active high level sensitive type enabled
1783 2 = high to low edge sensitive type enabled
1784 3 = low to high edge sensitive type enabled
1785
1735 1786
1736Appendix A - Sample SOC node for MPC8540 1787Appendix A - Sample SOC node for MPC8540
1737======================================== 1788========================================