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authorLennert Buytenhek <buytenh@wantstofly.org>2005-11-01 14:44:26 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2005-11-01 14:44:26 -0500
commite9b72e43d96a1ea2be0f513c78f16743a835d252 (patch)
treeed3a2cb9a84f56754ac1e4469c3a58f963b86237
parent69a857610ad212ce4bcd8e6b13f25408691403de (diff)
[ARM] 3064/1: start using ixp2000_reg_wrb
Patch from Lennert Buytenhek Switch the users of ixp2000_reg_write that depend on writes being flushed out of the write buffer by the time that function returns over to ixp2000_reg_wrb. When using XCB=101, writes to the same functional unit are still guaranteed to complete in order, so we only need to protect against: - reordering of writes to different functional units - masking an interrupt and then reenabling the IRQ bit in CPSR Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r--arch/arm/mach-ixp2000/core.c30
-rw-r--r--arch/arm/mach-ixp2000/ixdp2x00.c4
-rw-r--r--arch/arm/mach-ixp2000/ixdp2x01.c8
-rw-r--r--arch/arm/mach-ixp2000/pci.c6
-rw-r--r--include/asm-arm/arch-ixp2000/system.h17
5 files changed, 33 insertions, 32 deletions
diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c
index 01c393c504d0..69c6cf81a44d 100644
--- a/arch/arm/mach-ixp2000/core.c
+++ b/arch/arm/mach-ixp2000/core.c
@@ -62,7 +62,7 @@ void ixp2000_acquire_slowport(struct slowport_cfg *new_cfg, struct slowport_cfg
62 ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC); 62 ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC);
63 ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC); 63 ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC);
64 ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR); 64 ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR);
65 ixp2000_reg_write(IXP2000_SLOWPORT_ADC, new_cfg->ADC); 65 ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, new_cfg->ADC);
66} 66}
67 67
68void ixp2000_release_slowport(struct slowport_cfg *old_cfg) 68void ixp2000_release_slowport(struct slowport_cfg *old_cfg)
@@ -71,7 +71,7 @@ void ixp2000_release_slowport(struct slowport_cfg *old_cfg)
71 ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC); 71 ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC);
72 ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC); 72 ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC);
73 ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR); 73 ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR);
74 ixp2000_reg_write(IXP2000_SLOWPORT_ADC, old_cfg->ADC); 74 ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, old_cfg->ADC);
75 75
76 spin_unlock_irqrestore(&ixp2000_slowport_lock, 76 spin_unlock_irqrestore(&ixp2000_slowport_lock,
77 ixp2000_slowport_irq_flags); 77 ixp2000_slowport_irq_flags);
@@ -145,7 +145,7 @@ void __init ixp2000_map_io(void)
145 iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc)); 145 iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));
146 146
147 /* Set slowport to 8-bit mode. */ 147 /* Set slowport to 8-bit mode. */
148 ixp2000_reg_write(IXP2000_SLOWPORT_FRM, 1); 148 ixp2000_reg_wrb(IXP2000_SLOWPORT_FRM, 1);
149} 149}
150 150
151 151
@@ -209,7 +209,7 @@ static int ixp2000_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
209 write_seqlock(&xtime_lock); 209 write_seqlock(&xtime_lock);
210 210
211 /* clear timer 1 */ 211 /* clear timer 1 */
212 ixp2000_reg_write(IXP2000_T1_CLR, 1); 212 ixp2000_reg_wrb(IXP2000_T1_CLR, 1);
213 213
214 while ((next_jiffy_time - *missing_jiffy_timer_csr) > ticks_per_jiffy) { 214 while ((next_jiffy_time - *missing_jiffy_timer_csr) > ticks_per_jiffy) {
215 timer_tick(regs); 215 timer_tick(regs);
@@ -252,12 +252,12 @@ void __init ixp2000_init_time(unsigned long tick_rate)
252 252
253 ixp2000_reg_write(IXP2000_T4_CLR, 0); 253 ixp2000_reg_write(IXP2000_T4_CLR, 0);
254 ixp2000_reg_write(IXP2000_T4_CLD, -1); 254 ixp2000_reg_write(IXP2000_T4_CLD, -1);
255 ixp2000_reg_write(IXP2000_T4_CTL, (1 << 7)); 255 ixp2000_reg_wrb(IXP2000_T4_CTL, (1 << 7));
256 missing_jiffy_timer_csr = IXP2000_T4_CSR; 256 missing_jiffy_timer_csr = IXP2000_T4_CSR;
257 } else { 257 } else {
258 ixp2000_reg_write(IXP2000_T2_CLR, 0); 258 ixp2000_reg_write(IXP2000_T2_CLR, 0);
259 ixp2000_reg_write(IXP2000_T2_CLD, -1); 259 ixp2000_reg_write(IXP2000_T2_CLD, -1);
260 ixp2000_reg_write(IXP2000_T2_CTL, (1 << 7)); 260 ixp2000_reg_wrb(IXP2000_T2_CTL, (1 << 7));
261 missing_jiffy_timer_csr = IXP2000_T2_CSR; 261 missing_jiffy_timer_csr = IXP2000_T2_CSR;
262 } 262 }
263 next_jiffy_time = 0xffffffff; 263 next_jiffy_time = 0xffffffff;
@@ -279,7 +279,7 @@ static void update_gpio_int_csrs(void)
279 ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge); 279 ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge);
280 ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge); 280 ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge);
281 ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low); 281 ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low);
282 ixp2000_reg_write(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high); 282 ixp2000_reg_wrb(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high);
283} 283}
284 284
285void gpio_line_config(int line, int direction) 285void gpio_line_config(int line, int direction)
@@ -297,9 +297,9 @@ void gpio_line_config(int line, int direction)
297 GPIO_IRQ_level_high &= ~(1 << line); 297 GPIO_IRQ_level_high &= ~(1 << line);
298 update_gpio_int_csrs(); 298 update_gpio_int_csrs();
299 299
300 ixp2000_reg_write(IXP2000_GPIO_PDSR, 1 << line); 300 ixp2000_reg_wrb(IXP2000_GPIO_PDSR, 1 << line);
301 } else if (direction == GPIO_IN) { 301 } else if (direction == GPIO_IN) {
302 ixp2000_reg_write(IXP2000_GPIO_PDCR, 1 << line); 302 ixp2000_reg_wrb(IXP2000_GPIO_PDCR, 1 << line);
303 } 303 }
304 local_irq_restore(flags); 304 local_irq_restore(flags);
305} 305}
@@ -365,12 +365,12 @@ static void ixp2000_GPIO_irq_mask_ack(unsigned int irq)
365 365
366 ixp2000_reg_write(IXP2000_GPIO_EDSR, (1 << (irq - IRQ_IXP2000_GPIO0))); 366 ixp2000_reg_write(IXP2000_GPIO_EDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
367 ixp2000_reg_write(IXP2000_GPIO_LDSR, (1 << (irq - IRQ_IXP2000_GPIO0))); 367 ixp2000_reg_write(IXP2000_GPIO_LDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
368 ixp2000_reg_write(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0))); 368 ixp2000_reg_wrb(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0)));
369} 369}
370 370
371static void ixp2000_GPIO_irq_mask(unsigned int irq) 371static void ixp2000_GPIO_irq_mask(unsigned int irq)
372{ 372{
373 ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0))); 373 ixp2000_reg_wrb(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
374} 374}
375 375
376static void ixp2000_GPIO_irq_unmask(unsigned int irq) 376static void ixp2000_GPIO_irq_unmask(unsigned int irq)
@@ -389,9 +389,9 @@ static void ixp2000_pci_irq_mask(unsigned int irq)
389{ 389{
390 unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE; 390 unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
391 if (irq == IRQ_IXP2000_PCIA) 391 if (irq == IRQ_IXP2000_PCIA)
392 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26))); 392 ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26)));
393 else if (irq == IRQ_IXP2000_PCIB) 393 else if (irq == IRQ_IXP2000_PCIB)
394 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27))); 394 ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27)));
395} 395}
396 396
397static void ixp2000_pci_irq_unmask(unsigned int irq) 397static void ixp2000_pci_irq_unmask(unsigned int irq)
@@ -411,7 +411,7 @@ static struct irqchip ixp2000_pci_irq_chip = {
411 411
412static void ixp2000_irq_mask(unsigned int irq) 412static void ixp2000_irq_mask(unsigned int irq)
413{ 413{
414 ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, (1 << irq)); 414 ixp2000_reg_wrb(IXP2000_IRQ_ENABLE_CLR, (1 << irq));
415} 415}
416 416
417static void ixp2000_irq_unmask(unsigned int irq) 417static void ixp2000_irq_unmask(unsigned int irq)
@@ -443,7 +443,7 @@ void __init ixp2000_init_irq(void)
443 ixp2000_reg_write(IXP2000_GPIO_INCR, -1); 443 ixp2000_reg_write(IXP2000_GPIO_INCR, -1);
444 444
445 /* clear PCI interrupt sources */ 445 /* clear PCI interrupt sources */
446 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, 0); 446 ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, 0);
447 447
448 /* 448 /*
449 * Certain bits in the IRQ status register of the 449 * Certain bits in the IRQ status register of the
diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c
index 8b4a839b6279..00af934dea39 100644
--- a/arch/arm/mach-ixp2000/ixdp2x00.c
+++ b/arch/arm/mach-ixp2000/ixdp2x00.c
@@ -81,7 +81,7 @@ static void ixdp2x00_irq_mask(unsigned int irq)
81 81
82 dummy = *board_irq_mask; 82 dummy = *board_irq_mask;
83 dummy |= IXP2000_BOARD_IRQ_MASK(irq); 83 dummy |= IXP2000_BOARD_IRQ_MASK(irq);
84 ixp2000_reg_write(board_irq_mask, dummy); 84 ixp2000_reg_wrb(board_irq_mask, dummy);
85 85
86#ifdef CONFIG_ARCH_IXDP2400 86#ifdef CONFIG_ARCH_IXDP2400
87 if (machine_is_ixdp2400()) 87 if (machine_is_ixdp2400())
@@ -101,7 +101,7 @@ static void ixdp2x00_irq_unmask(unsigned int irq)
101 101
102 dummy = *board_irq_mask; 102 dummy = *board_irq_mask;
103 dummy &= ~IXP2000_BOARD_IRQ_MASK(irq); 103 dummy &= ~IXP2000_BOARD_IRQ_MASK(irq);
104 ixp2000_reg_write(board_irq_mask, dummy); 104 ixp2000_reg_wrb(board_irq_mask, dummy);
105 105
106 if (machine_is_ixdp2400()) 106 if (machine_is_ixdp2400())
107 ixp2000_release_slowport(&old_cfg); 107 ixp2000_release_slowport(&old_cfg);
diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c
index fee1d7b73503..dfaaa2d281e7 100644
--- a/arch/arm/mach-ixp2000/ixdp2x01.c
+++ b/arch/arm/mach-ixp2000/ixdp2x01.c
@@ -51,7 +51,7 @@
51 *************************************************************************/ 51 *************************************************************************/
52static void ixdp2x01_irq_mask(unsigned int irq) 52static void ixdp2x01_irq_mask(unsigned int irq)
53{ 53{
54 ixp2000_reg_write(IXDP2X01_INT_MASK_SET_REG, 54 ixp2000_reg_wrb(IXDP2X01_INT_MASK_SET_REG,
55 IXP2000_BOARD_IRQ_MASK(irq)); 55 IXP2000_BOARD_IRQ_MASK(irq));
56} 56}
57 57
@@ -114,7 +114,7 @@ void __init ixdp2x01_init_irq(void)
114 114
115 /* Mask all interrupts from CPLD, disable simulation */ 115 /* Mask all interrupts from CPLD, disable simulation */
116 ixp2000_reg_write(IXDP2X01_INT_MASK_SET_REG, 0xffffffff); 116 ixp2000_reg_write(IXDP2X01_INT_MASK_SET_REG, 0xffffffff);
117 ixp2000_reg_write(IXDP2X01_INT_SIM_REG, 0); 117 ixp2000_reg_wrb(IXDP2X01_INT_SIM_REG, 0);
118 118
119 for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) { 119 for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) {
120 if (irq & valid_irq_mask) { 120 if (irq & valid_irq_mask) {
@@ -316,7 +316,7 @@ static struct flash_platform_data ixdp2x01_flash_platform_data = {
316 316
317static unsigned long ixdp2x01_flash_bank_setup(unsigned long ofs) 317static unsigned long ixdp2x01_flash_bank_setup(unsigned long ofs)
318{ 318{
319 ixp2000_reg_write(IXDP2X01_CPLD_FLASH_REG, 319 ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG,
320 ((ofs >> IXDP2X01_FLASH_WINDOW_BITS) | IXDP2X01_CPLD_FLASH_INTERN)); 320 ((ofs >> IXDP2X01_FLASH_WINDOW_BITS) | IXDP2X01_CPLD_FLASH_INTERN));
321 return (ofs & IXDP2X01_FLASH_WINDOW_MASK); 321 return (ofs & IXDP2X01_FLASH_WINDOW_MASK);
322} 322}
@@ -363,7 +363,7 @@ static struct platform_device *ixdp2x01_devices[] __initdata = {
363 363
364static void __init ixdp2x01_init_machine(void) 364static void __init ixdp2x01_init_machine(void)
365{ 365{
366 ixp2000_reg_write(IXDP2X01_CPLD_FLASH_REG, 366 ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG,
367 (IXDP2X01_CPLD_FLASH_BANK_MASK | IXDP2X01_CPLD_FLASH_INTERN)); 367 (IXDP2X01_CPLD_FLASH_BANK_MASK | IXDP2X01_CPLD_FLASH_INTERN));
368 368
369 ixdp2x01_flash_data.nr_banks = 369 ixdp2x01_flash_data.nr_banks =
diff --git a/arch/arm/mach-ixp2000/pci.c b/arch/arm/mach-ixp2000/pci.c
index 522205acb316..d4bf1e1c0031 100644
--- a/arch/arm/mach-ixp2000/pci.c
+++ b/arch/arm/mach-ixp2000/pci.c
@@ -148,7 +148,7 @@ int ixp2000_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_re
148 local_irq_save(flags); 148 local_irq_save(flags);
149 temp = *(IXP2000_PCI_CONTROL); 149 temp = *(IXP2000_PCI_CONTROL);
150 if (temp & ((1 << 8) | (1 << 5))) { 150 if (temp & ((1 << 8) | (1 << 5))) {
151 ixp2000_reg_write(IXP2000_PCI_CONTROL, temp); 151 ixp2000_reg_wrb(IXP2000_PCI_CONTROL, temp);
152 } 152 }
153 153
154 temp = *(IXP2000_PCI_CMDSTAT); 154 temp = *(IXP2000_PCI_CMDSTAT);
@@ -178,8 +178,8 @@ clear_master_aborts(void)
178 178
179 local_irq_save(flags); 179 local_irq_save(flags);
180 temp = *(IXP2000_PCI_CONTROL); 180 temp = *(IXP2000_PCI_CONTROL);
181 if (temp & ((1 << 8) | (1 << 5))) { 181 if (temp & ((1 << 8) | (1 << 5))) {
182 ixp2000_reg_write(IXP2000_PCI_CONTROL, temp); 182 ixp2000_reg_wrb(IXP2000_PCI_CONTROL, temp);
183 } 183 }
184 184
185 temp = *(IXP2000_PCI_CMDSTAT); 185 temp = *(IXP2000_PCI_CMDSTAT);
diff --git a/include/asm-arm/arch-ixp2000/system.h b/include/asm-arm/arch-ixp2000/system.h
index d9d6d9d07e02..ddbbb34b5f95 100644
--- a/include/asm-arm/arch-ixp2000/system.h
+++ b/include/asm-arm/arch-ixp2000/system.h
@@ -26,23 +26,24 @@ static inline void arch_reset(char mode)
26 * RedBoot bank. 26 * RedBoot bank.
27 */ 27 */
28 if (machine_is_ixdp2401()) { 28 if (machine_is_ixdp2401()) {
29 *IXDP2X01_CPLD_FLASH_REG = ((0 >> IXDP2X01_FLASH_WINDOW_BITS) 29 ixp2000_reg_write(IXDP2X01_CPLD_FLASH_REG,
30 | IXDP2X01_CPLD_FLASH_INTERN); 30 ((0 >> IXDP2X01_FLASH_WINDOW_BITS)
31 *IXDP2X01_CPLD_RESET_REG = 0xffffffff; 31 | IXDP2X01_CPLD_FLASH_INTERN));
32 ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0xffffffff);
32 } 33 }
33 34
34 /* 35 /*
35 * On IXDP2801 we need to write this magic sequence to the CPLD 36 * On IXDP2801 we need to write this magic sequence to the CPLD
36 * to cause a complete reset of the CPU and all external devices 37 * to cause a complete reset of the CPU and all external devices
37 * and moves the flash bank register back to 0. 38 * and move the flash bank register back to 0.
38 */ 39 */
39 if (machine_is_ixdp2801()) { 40 if (machine_is_ixdp2801()) {
40 unsigned long reset_reg = *IXDP2X01_CPLD_RESET_REG; 41 unsigned long reset_reg = *IXDP2X01_CPLD_RESET_REG;
42
41 reset_reg = 0x55AA0000 | (reset_reg & 0x0000FFFF); 43 reset_reg = 0x55AA0000 | (reset_reg & 0x0000FFFF);
42 *IXDP2X01_CPLD_RESET_REG = reset_reg; 44 ixp2000_reg_write(IXDP2X01_CPLD_RESET_REG, reset_reg);
43 mb(); 45 ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0x80000000);
44 *IXDP2X01_CPLD_RESET_REG = 0x80000000;
45 } 46 }
46 47
47 *IXP2000_RESET0 = RSTALL; 48 ixp2000_reg_wrb(IXP2000_RESET0, RSTALL);
48} 49}