litmus-rt.git - The LITMUS^RT kernel.

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author	Yehuda Sadeh <yehuda@hq.newdream.net>	2010-05-18 19:38:08 -0400
committer	Sage Weil <sage@newdream.net>	2010-10-20 18:37:25 -0400
commit	ae1533b62b3369e6ae32338f4a77d64d0e88f676 (patch)
tree	9a54b1c1c8a52a4ae46bc0c5421d04e93ac6495f
parent	68b4476b0bc13fef18266b4140309a30e86739d2 (diff)

ceph-rbd: osdc support for osd call and rollback operations

This will be used for rbd snapshots administration. Signed-off-by: Yehuda Sadeh <yehuda@hq.newdream.net>

-rw-r--r--

-rw-r--r--

-rw-r--r--

3 files changed, 29 insertions, 0 deletions

                 ceph_encode_need(p, end, n, bad);               \
                 ceph_encode_copy(p, pv, n);                     \
         } while (0)
+#define ceph_encode_string_safe(p, end, s, n, bad)              \
+        do {                                                    \
+                ceph_encode_need(p, end, n, bad);               \
+                ceph_encode_string(p, end, s, n);               \
+        } while (0)
 #endif
         case CEPH_OSD_OP_GETXATTR:
         case CEPH_OSD_OP_SETXATTR:
         case CEPH_OSD_OP_CMPXATTR:
+        case CEPH_OSD_OP_CALL:
                 return 1;
         default:
                 return 0;
                 ceph_pagelist_append(req->r_trail, src->xattr.val,
                                      src->xattr.value_len);
                 break;
+        case CEPH_OSD_OP_CALL:
+                BUG_ON(!req->r_trail);
+                dst->cls.class_len = src->cls.class_len;
+                dst->cls.method_len = src->cls.method_len;
+                dst->cls.indata_len = cpu_to_le32(src->cls.indata_len);
+                ceph_pagelist_append(req->r_trail, src->cls.class_name,
+                                     src->cls.class_len);
+                ceph_pagelist_append(req->r_trail, src->cls.method_name,
+                                     src->cls.method_len);
+                ceph_pagelist_append(req->r_trail, src->cls.indata,
+                                     src->cls.indata_len);
+                break;
+        case CEPH_OSD_OP_ROLLBACK:
+                dst->snap.snapid = cpu_to_le64(src->snap.snapid);
+                break;
         case CEPH_OSD_OP_STARTSYNC:
                 break;
         default:
                         __u8 cmp_mode;     /* CEPH_OSD_CMPXATTR_MODE_* */
                 } xattr;
                 struct {
+                        const char *class_name;
                         __u8 class_len;
+                        const char *method_name;
                         __u8 method_len;
                         __u8 argc;
+                        const char *indata;
                         u32 indata_len;
                 } cls;
                 struct {
                         u64 cookie, count;
                 } pgls;
+                struct {
+                        u64 snapid;
+                } snap;
         };
         u32 payload_len;
 };

/* cnic.c: Broadcom CNIC core network driver. * * Copyright (c) 2006-2010 Broadcom Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation. * */ #ifndef CNIC_DEFS_H #define CNIC_DEFS_H /* KWQ (kernel work queue) request op codes */ #define L2_KWQE_OPCODE_VALUE_FLUSH (4) #define L4_KWQE_OPCODE_VALUE_CONNECT1 (50) #define L4_KWQE_OPCODE_VALUE_CONNECT2 (51) #define L4_KWQE_OPCODE_VALUE_CONNECT3 (52) #define L4_KWQE_OPCODE_VALUE_RESET (53) #define L4_KWQE_OPCODE_VALUE_CLOSE (54) #define L4_KWQE_OPCODE_VALUE_UPDATE_SECRET (60) #define L4_KWQE_OPCODE_VALUE_INIT_ULP (61) #define L4_KWQE_OPCODE_VALUE_OFFLOAD_PG (1) #define L4_KWQE_OPCODE_VALUE_UPDATE_PG (9) #define L4_KWQE_OPCODE_VALUE_UPLOAD_PG (14) #define L5CM_RAMROD_CMD_ID_BASE (0x80) #define L5CM_RAMROD_CMD_ID_TCP_CONNECT (L5CM_RAMROD_CMD_ID_BASE + 3) #define L5CM_RAMROD_CMD_ID_CLOSE (L5CM_RAMROD_CMD_ID_BASE + 12) #define L5CM_RAMROD_CMD_ID_ABORT (L5CM_RAMROD_CMD_ID_BASE + 13) #define L5CM_RAMROD_CMD_ID_SEARCHER_DELETE (L5CM_RAMROD_CMD_ID_BASE + 14) #define L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD (L5CM_RAMROD_CMD_ID_BASE + 15) /* KCQ (kernel completion queue) response op codes */ #define L4_KCQE_OPCODE_VALUE_CLOSE_COMP (53) #define L4_KCQE_OPCODE_VALUE_RESET_COMP (54) #define L4_KCQE_OPCODE_VALUE_FW_TCP_UPDATE (55) #define L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE (56) #define L4_KCQE_OPCODE_VALUE_RESET_RECEIVED (57) #define L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED (58) #define L4_KCQE_OPCODE_VALUE_INIT_ULP (61) #define L4_KCQE_OPCODE_VALUE_OFFLOAD_PG (1) #define L4_KCQE_OPCODE_VALUE_UPDATE_PG (9) #define L4_KCQE_OPCODE_VALUE_UPLOAD_PG (14) /* KCQ (kernel completion queue) completion status */ #define L4_KCQE_COMPLETION_STATUS_SUCCESS (0) #define L4_KCQE_COMPLETION_STATUS_TIMEOUT (0x93) #define L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL (0x83) #define L4_KCQE_COMPLETION_STATUS_OFFLOADED_PG (0x89) #define L4_LAYER_CODE (4) #define L2_LAYER_CODE (2) /* * L4 KCQ CQE */ struct l4_kcq { u32 cid; u32 pg_cid; u32 conn_id; u32 pg_host_opaque; #if defined(__BIG_ENDIAN) u16 status; u16 reserved1; #elif defined(__LITTLE_ENDIAN) u16 reserved1; u16 status; #endif u32 reserved2[2]; #if defined(__BIG_ENDIAN) u8 flags; #define L4_KCQ_RESERVED3 (0x7<<0) #define L4_KCQ_RESERVED3_SHIFT 0 #define L4_KCQ_RAMROD_COMPLETION (0x1<<3) /* Everest only */ #define L4_KCQ_RAMROD_COMPLETION_SHIFT 3 #define L4_KCQ_LAYER_CODE (0x7<<4) #define L4_KCQ_LAYER_CODE_SHIFT 4 #define L4_KCQ_RESERVED4 (0x1<<7) #define L4_KCQ_RESERVED4_SHIFT 7 u8 op_code; u16 qe_self_seq; #elif defined(__LITTLE_ENDIAN) u16 qe_self_seq; u8 op_code; u8 flags; #define L4_KCQ_RESERVED3 (0xF<<0) #define L4_KCQ_RESERVED3_SHIFT 0 #define L4_KCQ_RAMROD_COMPLETION (0x1<<3) /* Everest only */ #define L4_KCQ_RAMROD_COMPLETION_SHIFT 3 #define L4_KCQ_LAYER_CODE (0x7<<4) #define L4_KCQ_LAYER_CODE_SHIFT 4 #define L4_KCQ_RESERVED4 (0x1<<7) #define L4_KCQ_RESERVED4_SHIFT 7 #endif }; /* * L4 KCQ CQE PG upload */ struct l4_kcq_upload_pg { u32 pg_cid; #if defined(__BIG_ENDIAN) u16 pg_status; u16 pg_ipid_count; #elif defined(__LITTLE_ENDIAN) u16 pg_ipid_count; u16 pg_status; #endif u32 reserved1[5]; #if defined(__BIG_ENDIAN) u8 flags; #define L4_KCQ_UPLOAD_PG_RESERVED3 (0xF<<0) #define L4_KCQ_UPLOAD_PG_RESERVED3_SHIFT 0 #define L4_KCQ_UPLOAD_PG_LAYER_CODE (0x7<<4) #define L4_KCQ_UPLOAD_PG_LAYER_CODE_SHIFT 4 #define L4_KCQ_UPLOAD_PG_RESERVED4 (0x1<<7) #define L4_KCQ_UPLOAD_PG_RESERVED4_SHIFT 7 u8 op_code; u16 qe_self_seq; #elif defined(__LITTLE_ENDIAN) u16 qe_self_seq; u8 op_code; u8 flags; #define L4_KCQ_UPLOAD_PG_RESERVED3 (0xF<<0) #define L4_KCQ_UPLOAD_PG_RESERVED3_SHIFT 0 #define L4_KCQ_UPLOAD_PG_LAYER_CODE (0x7<<4) #define L4_KCQ_UPLOAD_PG_LAYER_CODE_SHIFT 4 #define L4_KCQ_UPLOAD_PG_RESERVED4 (0x1<<7) #define L4_KCQ_UPLOAD_PG_RESERVED4_SHIFT 7 #endif }; /* * Gracefully close the connection request */ struct l4_kwq_close_req { #if defined(__BIG_ENDIAN) u8 flags; #define L4_KWQ_CLOSE_REQ_RESERVED1 (0xF<<0) #define L4_KWQ_CLOSE_REQ_RESERVED1_SHIFT 0 #define L4_KWQ_CLOSE_REQ_LAYER_CODE (0x7<<4) #define L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT 4 #define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT (0x1<<7) #define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT_SHIFT 7 u8 op_code; u16 reserved0; #elif defined(__LITTLE_ENDIAN) u16 reserved0; u8 op_code; u8 flags; #define L4_KWQ_CLOSE_REQ_RESERVED1 (0xF<<0) #define L4_KWQ_CLOSE_REQ_RESERVED1_SHIFT 0 #define L4_KWQ_CLOSE_REQ_LAYER_CODE (0x7<<4) #define L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT 4 #define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT (0x1<<7) #define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT_SHIFT 7 #endif u32 cid; u32 reserved2[6]; }; /* * The first request to be passed in order to establish connection in option2 */ struct l4_kwq_connect_req1 { #if defined(__BIG_ENDIAN) u8 flags; #define L4_KWQ_CONNECT_REQ1_RESERVED1 (0xF<<0) #define L4_KWQ_CONNECT_REQ1_RESERVED1_SHIFT 0 #define L4_KWQ_CONNECT_REQ1_LAYER_CODE (0x7<<4) #define L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT 4 #define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT (0x1<<7) #define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT_SHIFT 7 u8 op_code; u8 reserved0; u8 conn_flags; #define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE (0x1<<0) #define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE_SHIFT 0 #define L4_KWQ_CONNECT_REQ1_IP_V6 (0x1<<1) #define L4_KWQ_CONNECT_REQ1_IP_V6_SHIFT 1 #define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG (0x1<<2) #define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG_SHIFT 2 #define L4_KWQ_CONNECT_REQ1_RSRV (0x1F<<3) #define L4_KWQ_CONNECT_REQ1_RSRV_SHIFT 3 #elif defined(__LITTLE_ENDIAN) u8 conn_flags; #define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE (0x1<<0) #define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE_SHIFT 0 #define L4_KWQ_CONNECT_REQ1_IP_V6 (0x1<<1) #define L4_KWQ_CONNECT_REQ1_IP_V6_SHIFT 1 #define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG (0x1<<2) #define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG_SHIFT 2 #define L4_KWQ_CONNECT_REQ1_RSRV (0x1F<<3) #define L4_KWQ_CONNECT_REQ1_RSRV_SHIFT 3 u8 reserved0; u8 op_code; u8 flags; #define L4_KWQ_CONNECT_REQ1_RESERVED1 (0xF<<0) #define L4_KWQ_CONNECT_REQ1_RESERVED1_SHIFT 0 #define L4_KWQ_CONNECT_REQ1_LAYER_CODE (0x7<<4) #define L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT 4 #define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT (0x1<<7) #define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT_SHIFT 7 #endif u32 cid; u32 pg_cid; u32 src_ip; u32 dst_ip; #if defined(__BIG_ENDIAN) u16 dst_port; u16 src_port; #elif defined(__LITTLE_ENDIAN) u16 src_port; u16 dst_port; #endif #if defined(__BIG_ENDIAN) u8 rsrv1[3]; u8 tcp_flags; #define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK (0x1<<0) #define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK_SHIFT 0 #define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE (0x1<<1) #define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE_SHIFT 1 #define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE (0x1<<2) #define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE_SHIFT 2 #define L4_KWQ_CONNECT_REQ1_TIME_STAMP (0x1<<3) #define L4_KWQ_CONNECT_REQ1_TIME_STAMP_SHIFT 3 #define L4_KWQ_CONNECT_REQ1_SACK (0x1<<4) #define L4_KWQ_CONNECT_REQ1_SACK_SHIFT 4 #define L4_KWQ_CONNECT_REQ1_SEG_SCALING (0x1<<5) #define L4_KWQ_CONNECT_REQ1_SEG_SCALING_SHIFT 5 #define L4_KWQ_CONNECT_REQ1_RESERVED2 (0x3<<6) #define L4_KWQ_CONNECT_REQ1_RESERVED2_SHIFT 6 #elif defined(__LITTLE_ENDIAN) u8 tcp_flags; #define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK (0x1<<0) #define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK_SHIFT 0 #define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE (0x1<<1) #define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE_SHIFT 1 #define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE (0x1<<2) #define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE_SHIFT 2 #define L4_KWQ_CONNECT_REQ1_TIME_STAMP (0x1<<3) #define L4_KWQ_CONNECT_REQ1_TIME_STAMP_SHIFT 3 #define L4_KWQ_CONNECT_REQ1_SACK (0x1<<4) #define L4_KWQ_CONNECT_REQ1_SACK_SHIFT 4 #define L4_KWQ_CONNECT_REQ1_SEG_SCALING (0x1<<5) #define L4_KWQ_CONNECT_REQ1_SEG_SCALING_SHIFT 5 #define L4_KWQ_CONNECT_REQ1_RESERVED2 (0x3<<6) #define L4_KWQ_CONNECT_REQ1_RESERVED2_SHIFT 6 u8 rsrv1[3]; #endif u32 rsrv2; }; /* * The second ( optional )request to be passed in order to establish * connection in option2 - for IPv6 only */ struct l4_kwq_connect_req2 { #if defined(__BIG_ENDIAN) u8 flags; #define L4_KWQ_CONNECT_REQ2_RESERVED1 (0xF<<0) #define L4_KWQ_CONNECT_REQ2_RESERVED1_SHIFT 0 #define L4_KWQ_CONNECT_REQ2_LAYER_CODE (0x7<<4) #define L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT 4 #define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT (0x1<<7) #define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT_SHIFT 7 u8 op_code; u8 reserved0; u8 rsrv; #elif defined(__LITTLE_ENDIAN) u8 rsrv; u8 reserved0; u8 op_code; u8 flags; #define L4_KWQ_CONNECT_REQ2_RESERVED1 (0xF<<0) #define L4_KWQ_CONNECT_REQ2_RESERVED1_SHIFT 0 #define L4_KWQ_CONNECT_REQ2_LAYER_CODE (0x7<<4) #define L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT 4 #define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT (0x1<<7) #define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT_SHIFT 7 #endif u32 reserved2; u32 src_ip_v6_2; u32 src_ip_v6_3; u32 src_ip_v6_4; u32 dst_ip_v6_2; u32 dst_ip_v6_3; u32 dst_ip_v6_4; }; /* * The third ( and last )request to be passed in order to establish * connection in option2 */ struct l4_kwq_connect_req3 { #if defined(__BIG_ENDIAN) u8 flags; #define L4_KWQ_CONNECT_REQ3_RESERVED1 (0xF<<0) #define L4_KWQ_CONNECT_REQ3_RESERVED1_SHIFT 0 #define L4_KWQ_CONNECT_REQ3_LAYER_CODE (0x7<<4) #define L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT 4 #define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT (0x1<<7) #define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT_SHIFT 7 u8 op_code; u16 reserved0; #elif defined(__LITTLE_ENDIAN) u16 reserved0; u8 op_code; u8 flags; #define L4_KWQ_CONNECT_REQ3_RESERVED1 (0xF<<0) #define L4_KWQ_CONNECT_REQ3_RESERVED1_SHIFT 0 #define L4_KWQ_CONNECT_REQ3_LAYER_CODE (0x7<<4) #define L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT 4 #define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT (0x1<<7) #define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT_SHIFT 7 #endif u32 ka_timeout; u32 ka_interval ; #if defined(__BIG_ENDIAN) u8 snd_seq_scale; u8 ttl; u8 tos; u8 ka_max_probe_count; #elif defined(__LITTLE_ENDIAN) u8 ka_max_probe_count; u8 tos; u8 ttl; u8 snd_seq_scale; #endif #if defined(__BIG_ENDIAN) u16 pmtu; u16 mss; #elif defined(__LITTLE_ENDIAN) u16 mss; u16 pmtu; #endif u32 rcv_buf; u32 snd_buf; u32 seed; }; /* * a KWQE request to offload a PG connection */ struct l4_kwq_offload_pg { #if defined(__BIG_ENDIAN) u8 flags; #define L4_KWQ_OFFLOAD_PG_RESERVED1 (0xF<<0) #define L4_KWQ_OFFLOAD_PG_RESERVED1_SHIFT 0 #define L4_KWQ_OFFLOAD_PG_LAYER_CODE (0x7<<4) #define L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT 4 #define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT (0x1<<7) #define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT_SHIFT 7 u8 op_code; u16 reserved0; #elif defined(__LITTLE_ENDIAN) u16 reserved0; u8 op_code; u8 flags; #define L4_KWQ_OFFLOAD_PG_RESERVED1 (0xF<<0) #define L4_KWQ_OFFLOAD_PG_RESERVED1_SHIFT 0 #define L4_KWQ_OFFLOAD_PG_LAYER_CODE (0x7<<4) #define L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT 4 #define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT (0x1<<7) #define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT_SHIFT 7 #endif #if defined(__BIG_ENDIAN) u8 l2hdr_nbytes; u8 pg_flags; #define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP (0x1<<0) #define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP_SHIFT 0 #define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING (0x1<<1) #define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING_SHIFT 1 #define L4_KWQ_OFFLOAD_PG_RESERVED2 (0x3F<<2) #define L4_KWQ_OFFLOAD_PG_RESERVED2_SHIFT 2 u8 da0; u8 da1; #elif defined(__LITTLE_ENDIAN) u8 da1; u8 da0; u8 pg_flags; #define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP (0x1<<0) #define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP_SHIFT 0 #define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING (0x1<<1) #define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING_SHIFT 1 #define L4_KWQ_OFFLOAD_PG_RESERVED2 (0x3F<<2) #define L4_KWQ_OFFLOAD_PG_RESERVED2_SHIFT 2 u8 l2hdr_nbytes; #endif #if defined(__BIG_ENDIAN) u8 da2; u8 da3; u8 da4; u8 da5; #elif defined(__LITTLE_ENDIAN) u8 da5; u8 da4; u8 da3; u8 da2; #endif #if defined(__BIG_ENDIAN) u8 sa0; u8 sa1; u8 sa2; u8 sa3; #elif defined(__LITTLE_ENDIAN) u8 sa3; u8 sa2; u8 sa1; u8 sa0; #endif #if defined(__BIG_ENDIAN) u8 sa4; u8 sa5; u16 etype; #elif defined(__LITTLE_ENDIAN) u16 etype; u8 sa5; u8 sa4; #endif #if defined(__BIG_ENDIAN) u16 vlan_tag; u16 ipid_start; #elif defined(__LITTLE_ENDIAN) u16 ipid_start; u16 vlan_tag; #endif #if defined(__BIG_ENDIAN) u16 ipid_count; u16 reserved3; #elif defined(__LITTLE_ENDIAN) u16 reserved3; u16 ipid_count; #endif u32 host_opaque; }; /* * Abortively close the connection request */ struct l4_kwq_reset_req { #if defined(__BIG_ENDIAN) u8 flags; #define L4_KWQ_RESET_REQ_RESERVED1 (0xF<<0) #define L4_KWQ_RESET_REQ_RESERVED1_SHIFT 0 #define L4_KWQ_RESET_REQ_LAYER_CODE (0x7<<4) #define L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT 4 #define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT (0x1<<7) #define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT_SHIFT 7 u8 op_code; u16 reserved0; #elif defined(__LITTLE_ENDIAN) u16 reserved0; u8 op_code; u8 flags; #define L4_KWQ_RESET_REQ_RESERVED1 (0xF<<0) #define L4_KWQ_RESET_REQ_RESERVED1_SHIFT 0 #define L4_KWQ_RESET_REQ_LAYER_CODE (0x7<<4) #define L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT 4 #define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT (0x1<<7) #define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT_SHIFT 7 #endif u32 cid; u32 reserved2[6]; }; /* * a KWQE request to update a PG connection */ struct l4_kwq_update_pg { #if defined(__BIG_ENDIAN) u8 flags; #define L4_KWQ_UPDATE_PG_RESERVED1 (0xF<<0) #define L4_KWQ_UPDATE_PG_RESERVED1_SHIFT 0 #define L4_KWQ_UPDATE_PG_LAYER_CODE (0x7<<4) #define L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT 4 #define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT (0x1<<7) #define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT_SHIFT 7 u8 opcode; u16 oper16; #elif defined(__LITTLE_ENDIAN) u16 oper16; u8 opcode; u8 flags; #define L4_KWQ_UPDATE_PG_RESERVED1 (0xF<<0) #define L4_KWQ_UPDATE_PG_RESERVED1_SHIFT 0 #define L4_KWQ_UPDATE_PG_LAYER_CODE (0x7<<4) #define L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT 4 #define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT (0x1<<7) #define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT_SHIFT 7 #endif u32 pg_cid; u32 pg_host_opaque; #if defined(__BIG_ENDIAN) u8 pg_valids; #define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT (0x1<<0) #define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT_SHIFT 0 #define L4_KWQ_UPDATE_PG_VALIDS_DA (0x1<<1) #define L4_KWQ_UPDATE_PG_VALIDS_DA_SHIFT 1 #define L4_KWQ_UPDATE_PG_RESERVERD2 (0x3F<<2) #define L4_KWQ_UPDATE_PG_RESERVERD2_SHIFT 2 u8 pg_unused_a; u16 pg_ipid_count; #elif defined(__LITTLE_ENDIAN) u16 pg_ipid_count; u8 pg_unused_a; u8 pg_valids; #define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT (0x1<<0) #define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT_SHIFT 0 #define L4_KWQ_UPDATE_PG_VALIDS_DA (0x1<<1) #define L4_KWQ_UPDATE_PG_VALIDS_DA_SHIFT 1 #define L4_KWQ_UPDATE_PG_RESERVERD2 (0x3F<<2) #define L4_KWQ_UPDATE_PG_RESERVERD2_SHIFT 2 #endif #if defined(__BIG_ENDIAN) u16 reserverd3; u8 da0; u8 da1; #elif defined(__LITTLE_ENDIAN) u8 da1; u8 da0; u16 reserverd3; #endif #if defined(__BIG_ENDIAN) u8 da2; u8 da3; u8 da4; u8 da5; #elif defined(__LITTLE_ENDIAN) u8 da5; u8 da4; u8 da3; u8 da2; #endif u32 reserved4; u32 reserved5; }; /* * a KWQE request to upload a PG or L4 context */ struct l4_kwq_upload { #if defined(__BIG_ENDIAN) u8 flags; #define L4_KWQ_UPLOAD_RESERVED1 (0xF<<0) #define L4_KWQ_UPLOAD_RESERVED1_SHIFT 0 #define L4_KWQ_UPLOAD_LAYER_CODE (0x7<<4) #define L4_KWQ_UPLOAD_LAYER_CODE_SHIFT 4 #define L4_KWQ_UPLOAD_LINKED_WITH_NEXT (0x1<<7) #define L4_KWQ_UPLOAD_LINKED_WITH_NEXT_SHIFT 7 u8 opcode; u16 oper16; #elif defined(__LITTLE_ENDIAN) u16 oper16; u8 opcode; u8 flags; #define L4_KWQ_UPLOAD_RESERVED1 (0xF<<0) #define L4_KWQ_UPLOAD_RESERVED1_SHIFT 0 #define L4_KWQ_UPLOAD_LAYER_CODE (0x7<<4) #define L4_KWQ_UPLOAD_LAYER_CODE_SHIFT 4 #define L4_KWQ_UPLOAD_LINKED_WITH_NEXT (0x1<<7) #define L4_KWQ_UPLOAD_LINKED_WITH_NEXT_SHIFT 7 #endif u32 cid; u32 reserved2[6]; }; /* * bnx2x structures */ /* * iSCSI context region, used only in iSCSI */ struct ustorm_iscsi_rq_db { struct regpair pbl_base; struct regpair curr_pbe; }; /* * iSCSI context region, used only in iSCSI */ struct ustorm_iscsi_r2tq_db { struct regpair pbl_base; struct regpair curr_pbe; }; /* * iSCSI context region, used only in iSCSI */ struct ustorm_iscsi_cq_db { #if defined(__BIG_ENDIAN) u16 cq_sn; u16 prod; #elif defined(__LITTLE_ENDIAN) u16 prod; u16 cq_sn; #endif struct regpair curr_pbe; }; /* * iSCSI context region, used only in iSCSI */ struct rings_db { struct ustorm_iscsi_rq_db rq; struct ustorm_iscsi_r2tq_db r2tq; struct ustorm_iscsi_cq_db cq[8]; #if defined(__BIG_ENDIAN) u16 rq_prod; u16 r2tq_prod; #elif defined(__LITTLE_ENDIAN) u16 r2tq_prod; u16 rq_prod; #endif struct regpair cq_pbl_base; }; /* * iSCSI context region, used only in iSCSI */ struct ustorm_iscsi_placement_db { u32 sgl_base_lo; u32 sgl_base_hi; u32 local_sge_0_address_hi; u32 local_sge_0_address_lo; #if defined(__BIG_ENDIAN) u16 curr_sge_offset; u16 local_sge_0_size; #elif defined(__LITTLE_ENDIAN) u16 local_sge_0_size; u16 curr_sge_offset; #endif u32 local_sge_1_address_hi; u32 local_sge_1_address_lo; #if defined(__BIG_ENDIAN) u16 reserved6; u16 local_sge_1_size; #elif defined(__LITTLE_ENDIAN) u16 local_sge_1_size; u16 reserved6; #endif #if defined(__BIG_ENDIAN) u8 sgl_size; u8 local_sge_index_2b; u16 reserved7; #elif defined(__LITTLE_ENDIAN) u16 reserved7; u8 local_sge_index_2b; u8 sgl_size; #endif u32 rem_pdu; u32 place_db_bitfield_1; #define USTORM_ISCSI_PLACEMENT_DB_REM_PDU_PAYLOAD (0xFFFFFF<<0) #define USTORM_ISCSI_PLACEMENT_DB_REM_PDU_PAYLOAD_SHIFT 0 #define USTORM_ISCSI_PLACEMENT_DB_CQ_ID (0xFF<<24) #define USTORM_ISCSI_PLACEMENT_DB_CQ_ID_SHIFT 24 u32 place_db_bitfield_2; #define USTORM_ISCSI_PLACEMENT_DB_BYTES_2_TRUNCATE (0xFFFFFF<<0) #define USTORM_ISCSI_PLACEMENT_DB_BYTES_2_TRUNCATE_SHIFT 0 #define USTORM_ISCSI_PLACEMENT_DB_HOST_SGE_INDEX (0xFF<<24) #define USTORM_ISCSI_PLACEMENT_DB_HOST_SGE_INDEX_SHIFT 24 u32 nal; #define USTORM_ISCSI_PLACEMENT_DB_REM_SGE_SIZE (0xFFFFFF<<0) #define USTORM_ISCSI_PLACEMENT_DB_REM_SGE_SIZE_SHIFT 0 #define USTORM_ISCSI_PLACEMENT_DB_EXP_PADDING_2B (0x3<<24) #define USTORM_ISCSI_PLACEMENT_DB_EXP_PADDING_2B_SHIFT 24 #define USTORM_ISCSI_PLACEMENT_DB_EXP_DIGEST_3B (0x7<<26) #define USTORM_ISCSI_PLACEMENT_DB_EXP_DIGEST_3B_SHIFT 26 #define USTORM_ISCSI_PLACEMENT_DB_NAL_LEN_3B (0x7<<29) #define USTORM_ISCSI_PLACEMENT_DB_NAL_LEN_3B_SHIFT 29 }; /* * Ustorm iSCSI Storm Context */ struct ustorm_iscsi_st_context { u32 exp_stat_sn; u32 exp_data_sn; struct rings_db ring; struct regpair task_pbl_base; struct regpair tce_phy_addr; struct ustorm_iscsi_placement_db place_db; u32 data_rcv_seq; u32 rem_rcv_len; #if defined(__BIG_ENDIAN) u16 hdr_itt; u16 iscsi_conn_id; #elif defined(__LITTLE_ENDIAN) u16 iscsi_conn_id; u16 hdr_itt; #endif u32 nal_bytes; #if defined(__BIG_ENDIAN) u8 hdr_second_byte_union; u8 bitfield_0; #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU (0x1<<0) #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU_SHIFT 0 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE (0x1<<1) #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE_SHIFT 1 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1 (0x3F<<2) #define USTORM_ISCSI_ST_CONTEXT_RESERVED1_SHIFT 2 u8 task_pdu_cache_index; u8 task_pbe_cache_index; #elif defined(__LITTLE_ENDIAN) u8 task_pbe_cache_index; u8 task_pdu_cache_index; u8 bitfield_0; #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU (0x1<<0) #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU_SHIFT 0 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE (0x1<<1) #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE_SHIFT 1 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1 (0x3F<<2) #define USTORM_ISCSI_ST_CONTEXT_RESERVED1_SHIFT 2 u8 hdr_second_byte_union; #endif #if defined(__BIG_ENDIAN) u16 reserved3; u8 reserved2; u8 acDecrement; #elif defined(__LITTLE_ENDIAN) u8 acDecrement; u8 reserved2; u16 reserved3; #endif u32 task_stat; #if defined(__BIG_ENDIAN) u8 hdr_opcode; u8 num_cqs; u16 reserved5; #elif defined(__LITTLE_ENDIAN) u16 reserved5; u8 num_cqs; u8 hdr_opcode; #endif u32 negotiated_rx; #define USTORM_ISCSI_ST_CONTEXT_MAX_RECV_PDU_LENGTH (0xFFFFFF<<0) #define USTORM_ISCSI_ST_CONTEXT_MAX_RECV_PDU_LENGTH_SHIFT 0 #define USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS (0xFF<<24) #define USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT 24 u32 negotiated_rx_and_flags; #define USTORM_ISCSI_ST_CONTEXT_MAX_BURST_LENGTH (0xFFFFFF<<0) #define USTORM_ISCSI_ST_CONTEXT_MAX_BURST_LENGTH_SHIFT 0 #define USTORM_ISCSI_ST_CONTEXT_B_CQE_POSTED_OR_HEADER_CACHED (0x1<<24) #define USTORM_ISCSI_ST_CONTEXT_B_CQE_POSTED_OR_HEADER_CACHED_SHIFT 24 #define USTORM_ISCSI_ST_CONTEXT_B_HDR_DIGEST_EN (0x1<<25) #define USTORM_ISCSI_ST_CONTEXT_B_HDR_DIGEST_EN_SHIFT 25 #define USTORM_ISCSI_ST_CONTEXT_B_DATA_DIGEST_EN (0x1<<26) #define USTORM_ISCSI_ST_CONTEXT_B_DATA_DIGEST_EN_SHIFT 26 #define USTORM_ISCSI_ST_CONTEXT_B_PROTOCOL_ERROR (0x1<<27) #define USTORM_ISCSI_ST_CONTEXT_B_PROTOCOL_ERROR_SHIFT 27 #define USTORM_ISCSI_ST_CONTEXT_B_TASK_VALID (0x1<<28) #define USTORM_ISCSI_ST_CONTEXT_B_TASK_VALID_SHIFT 28 #define USTORM_ISCSI_ST_CONTEXT_TASK_TYPE (0x3<<29) #define USTORM_ISCSI_ST_CONTEXT_TASK_TYPE_SHIFT 29 #define USTORM_ISCSI_ST_CONTEXT_B_ALL_DATA_ACKED (0x1<<31) #define USTORM_ISCSI_ST_CONTEXT_B_ALL_DATA_ACKED_SHIFT 31 }; /* * TCP context region, shared in TOE, RDMA and ISCSI */ struct tstorm_tcp_st_context_section { u32 flags1; #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_SRTT_20B (0xFFFFFF<<0) #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_SRTT_20B_SHIFT 0 #define TSTORM_TCP_ST_CONTEXT_SECTION_PAWS_INVALID (0x1<<24) #define TSTORM_TCP_ST_CONTEXT_SECTION_PAWS_INVALID_SHIFT 24 #define TSTORM_TCP_ST_CONTEXT_SECTION_TIMESTAMP_EXISTS (0x1<<25) #define TSTORM_TCP_ST_CONTEXT_SECTION_TIMESTAMP_EXISTS_SHIFT 25 #define TSTORM_TCP_ST_CONTEXT_SECTION_ISLE_EXISTS (0x1<<26) #define TSTORM_TCP_ST_CONTEXT_SECTION_ISLE_EXISTS_SHIFT 26 #define TSTORM_TCP_ST_CONTEXT_SECTION_STOP_RX_PAYLOAD (0x1<<27) #define TSTORM_TCP_ST_CONTEXT_SECTION_STOP_RX_PAYLOAD_SHIFT 27 #define TSTORM_TCP_ST_CONTEXT_SECTION_KA_ENABLED (0x1<<28) #define TSTORM_TCP_ST_CONTEXT_SECTION_KA_ENABLED_SHIFT 28 #define TSTORM_TCP_ST_CONTEXT_SECTION_FIRST_RTO_ESTIMATE (0x1<<29) #define TSTORM_TCP_ST_CONTEXT_SECTION_FIRST_RTO_ESTIMATE_SHIFT 29 #define TSTORM_TCP_ST_CONTEXT_SECTION_MAX_SEG_RETRANSMIT_EN (0x1<<30) #define TSTORM_TCP_ST_CONTEXT_SECTION_MAX_SEG_RETRANSMIT_EN_SHIFT 30 #define TSTORM_TCP_ST_CONTEXT_SECTION_RESERVED3 (0x1<<31) #define TSTORM_TCP_ST_CONTEXT_SECTION_RESERVED3_SHIFT 31 u32 flags2; #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_VARIATION_20B (0xFFFFFF<<0) #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_VARIATION_20B_SHIFT 0 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN (0x1<<24) #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN_SHIFT 24 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_COUNTER_EN (0x1<<25) #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_COUNTER_EN_SHIFT 25 #define __TSTORM_TCP_ST_CONTEXT_SECTION_KA_PROBE_SENT (0x1<<26) #define __TSTORM_TCP_ST_CONTEXT_SECTION_KA_PROBE_SENT_SHIFT 26 #define __TSTORM_TCP_ST_CONTEXT_SECTION_PERSIST_PROBE_SENT (0x1<<27) #define __TSTORM_TCP_ST_CONTEXT_SECTION_PERSIST_PROBE_SENT_SHIFT 27 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<28) #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 28 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<29) #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 29 #define __TSTORM_TCP_ST_CONTEXT_SECTION_SECOND_ISLE_DROPPED (0x1<<30) #define __TSTORM_TCP_ST_CONTEXT_SECTION_SECOND_ISLE_DROPPED_SHIFT 30 #define __TSTORM_TCP_ST_CONTEXT_SECTION_DONT_SUPPORT_OOO (0x1<<31) #define __TSTORM_TCP_ST_CONTEXT_SECTION_DONT_SUPPORT_OOO_SHIFT 31 #if defined(__BIG_ENDIAN) u16 reserved_slowpath; u8 tcp_sm_state_3b; u8 rto_exp_3b; #elif defined(__LITTLE_ENDIAN) u8 rto_exp_3b; u8 tcp_sm_state_3b; u16 reserved_slowpath; #endif u32 rcv_nxt; u32 timestamp_recent; u32 timestamp_recent_time; u32 cwnd; u32 ss_thresh; u32 cwnd_accum; u32 prev_seg_seq; u32 expected_rel_seq; u32 recover; #if defined(__BIG_ENDIAN) u8 retransmit_count; u8 ka_max_probe_count; u8 persist_probe_count; u8 ka_probe_count; #elif defined(__LITTLE_ENDIAN) u8 ka_probe_count; u8 persist_probe_count; u8 ka_max_probe_count; u8 retransmit_count; #endif #if defined(__BIG_ENDIAN) u8 statistics_counter_id; u8 ooo_support_mode; u8 snd_wnd_scale_4b; u8 dup_ack_count; #elif defined(__LITTLE_ENDIAN) u8 dup_ack_count; u8 snd_wnd_scale_4b; u8 ooo_support_mode; u8 statistics_counter_id; #endif u32 retransmit_start_time; u32 ka_timeout; u32 ka_interval; u32 isle_start_seq; u32 isle_end_seq; #if defined(__BIG_ENDIAN) u16 mss; u16 recent_seg_wnd; #elif defined(__LITTLE_ENDIAN) u16 recent_seg_wnd; u16 mss; #endif u32 reserved4; u32 max_rt_time; #if defined(__BIG_ENDIAN) u16 lsb_mac_address; u16 vlan_id; #elif defined(__LITTLE_ENDIAN) u16 vlan_id; u16 lsb_mac_address; #endif u32 msb_mac_address; u32 reserved2; }; /* * Termination variables */ struct iscsi_term_vars { u8 BitMap; #define ISCSI_TERM_VARS_TCP_STATE (0xF<<0) #define ISCSI_TERM_VARS_TCP_STATE_SHIFT 0 #define ISCSI_TERM_VARS_FIN_RECEIVED_SBIT (0x1<<4) #define ISCSI_TERM_VARS_FIN_RECEIVED_SBIT_SHIFT 4 #define ISCSI_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT (0x1<<5) #define ISCSI_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT_SHIFT 5 #define ISCSI_TERM_VARS_TERM_ON_CHIP (0x1<<6) #define ISCSI_TERM_VARS_TERM_ON_CHIP_SHIFT 6 #define ISCSI_TERM_VARS_RSRV (0x1<<7) #define ISCSI_TERM_VARS_RSRV_SHIFT 7 }; /* * iSCSI context region, used only in iSCSI */ struct tstorm_iscsi_st_context_section { #if defined(__BIG_ENDIAN) u16 rem_tcp_data_len; u16 brb_offset; #elif defined(__LITTLE_ENDIAN) u16 brb_offset; u16 rem_tcp_data_len; #endif u32 b2nh; #if defined(__BIG_ENDIAN) u16 rq_cons; u8 flags; #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN (0x1<<0) #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN_SHIFT 0 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN (0x1<<1) #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN_SHIFT 1 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER (0x1<<2) #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER_SHIFT 2 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE (0x1<<3) #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE_SHIFT 3 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS (0x1<<4) #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS_SHIFT 4 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_FLAGS_RSRV (0x7<<5) #define TSTORM_ISCSI_ST_CONTEXT_SECTION_FLAGS_RSRV_SHIFT 5 u8 hdr_bytes_2_fetch; #elif defined(__LITTLE_ENDIAN) u8 hdr_bytes_2_fetch; u8 flags; #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN (0x1<<0) #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN_SHIFT 0 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN (0x1<<1) #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN_SHIFT 1 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER (0x1<<2) #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER_SHIFT 2 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE (0x1<<3) #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE_SHIFT 3 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS (0x1<<4) #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS_SHIFT 4 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_FLAGS_RSRV (0x7<<5) #define TSTORM_ISCSI_ST_CONTEXT_SECTION_FLAGS_RSRV_SHIFT 5 u16 rq_cons; #endif struct regpair rq_db_phy_addr; #if defined(__BIG_ENDIAN) struct iscsi_term_vars term_vars; u8 scratchpad_idx; u16 iscsi_conn_id; #elif defined(__LITTLE_ENDIAN) u16 iscsi_conn_id; u8 scratchpad_idx; struct iscsi_term_vars term_vars; #endif u32 reserved2; }; /*


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