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authorAlberto Mardegan <mardy@users.sourceforge.net>2006-03-31 05:31:46 -0500
committerLinus Torvalds <torvalds@g5.osdl.org>2006-03-31 15:19:00 -0500
commit9b0e1c5dd2941aec566047e10a5cc929ca7f7d4f (patch)
tree5d21dda4ee4b36f3f2247558190e12087a58070d
parent1a37d5f51020b9967d4b4094f6d627d0873a6469 (diff)
[PATCH] w100fb: Add acceleration support to ATI Imageon
Add acceleration support in w100fb.c (i.e. ATI Imageons) for the copyarea and fillrect operations. Signed-off-by: Alberto Mardegan <mardy@users.sourceforge.net> Signed-off-by: Antonino Daplas <adaplas@pol.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
-rw-r--r--drivers/video/w100fb.c162
-rw-r--r--drivers/video/w100fb.h748
2 files changed, 611 insertions, 299 deletions
diff --git a/drivers/video/w100fb.c b/drivers/video/w100fb.c
index f6e24ee85f07..5fc86ea20692 100644
--- a/drivers/video/w100fb.c
+++ b/drivers/video/w100fb.c
@@ -4,8 +4,9 @@
4 * Frame Buffer Device for ATI Imageon w100 (Wallaby) 4 * Frame Buffer Device for ATI Imageon w100 (Wallaby)
5 * 5 *
6 * Copyright (C) 2002, ATI Corp. 6 * Copyright (C) 2002, ATI Corp.
7 * Copyright (C) 2004-2005 Richard Purdie 7 * Copyright (C) 2004-2006 Richard Purdie
8 * Copyright (c) 2005 Ian Molton 8 * Copyright (c) 2005 Ian Molton
9 * Copyright (c) 2006 Alberto Mardegan
9 * 10 *
10 * Rewritten for 2.6 by Richard Purdie <rpurdie@rpsys.net> 11 * Rewritten for 2.6 by Richard Purdie <rpurdie@rpsys.net>
11 * 12 *
@@ -14,6 +15,9 @@
14 * 15 *
15 * w32xx support by Ian Molton 16 * w32xx support by Ian Molton
16 * 17 *
18 * Hardware acceleration support by Alberto Mardegan
19 * <mardy@users.sourceforge.net>
20 *
17 * This program is free software; you can redistribute it and/or modify 21 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as 22 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation. 23 * published by the Free Software Foundation.
@@ -47,6 +51,7 @@ static void w100_set_dispregs(struct w100fb_par*);
47static void w100_update_enable(void); 51static void w100_update_enable(void);
48static void w100_update_disable(void); 52static void w100_update_disable(void);
49static void calc_hsync(struct w100fb_par *par); 53static void calc_hsync(struct w100fb_par *par);
54static void w100_init_graphic_engine(struct w100fb_par *par);
50struct w100_pll_info *w100_get_xtal_table(unsigned int freq); 55struct w100_pll_info *w100_get_xtal_table(unsigned int freq);
51 56
52/* Pseudo palette size */ 57/* Pseudo palette size */
@@ -248,6 +253,152 @@ static int w100fb_blank(int blank_mode, struct fb_info *info)
248} 253}
249 254
250 255
256static void w100_fifo_wait(int entries)
257{
258 union rbbm_status_u status;
259 int i;
260
261 for (i = 0; i < 2000000; i++) {
262 status.val = readl(remapped_regs + mmRBBM_STATUS);
263 if (status.f.cmdfifo_avail >= entries)
264 return;
265 udelay(1);
266 }
267 printk(KERN_ERR "w100fb: FIFO Timeout!\n");
268}
269
270
271static int w100fb_sync(struct fb_info *info)
272{
273 union rbbm_status_u status;
274 int i;
275
276 for (i = 0; i < 2000000; i++) {
277 status.val = readl(remapped_regs + mmRBBM_STATUS);
278 if (!status.f.gui_active)
279 return 0;
280 udelay(1);
281 }
282 printk(KERN_ERR "w100fb: Graphic engine timeout!\n");
283 return -EBUSY;
284}
285
286
287static void w100_init_graphic_engine(struct w100fb_par *par)
288{
289 union dp_gui_master_cntl_u gmc;
290 union dp_mix_u dp_mix;
291 union dp_datatype_u dp_datatype;
292 union dp_cntl_u dp_cntl;
293
294 w100_fifo_wait(4);
295 writel(W100_FB_BASE, remapped_regs + mmDST_OFFSET);
296 writel(par->xres, remapped_regs + mmDST_PITCH);
297 writel(W100_FB_BASE, remapped_regs + mmSRC_OFFSET);
298 writel(par->xres, remapped_regs + mmSRC_PITCH);
299
300 w100_fifo_wait(3);
301 writel(0, remapped_regs + mmSC_TOP_LEFT);
302 writel((par->yres << 16) | par->xres, remapped_regs + mmSC_BOTTOM_RIGHT);
303 writel(0x1fff1fff, remapped_regs + mmSRC_SC_BOTTOM_RIGHT);
304
305 w100_fifo_wait(4);
306 dp_cntl.val = 0;
307 dp_cntl.f.dst_x_dir = 1;
308 dp_cntl.f.dst_y_dir = 1;
309 dp_cntl.f.src_x_dir = 1;
310 dp_cntl.f.src_y_dir = 1;
311 dp_cntl.f.dst_major_x = 1;
312 dp_cntl.f.src_major_x = 1;
313 writel(dp_cntl.val, remapped_regs + mmDP_CNTL);
314
315 gmc.val = 0;
316 gmc.f.gmc_src_pitch_offset_cntl = 1;
317 gmc.f.gmc_dst_pitch_offset_cntl = 1;
318 gmc.f.gmc_src_clipping = 1;
319 gmc.f.gmc_dst_clipping = 1;
320 gmc.f.gmc_brush_datatype = GMC_BRUSH_NONE;
321 gmc.f.gmc_dst_datatype = 3; /* from DstType_16Bpp_444 */
322 gmc.f.gmc_src_datatype = SRC_DATATYPE_EQU_DST;
323 gmc.f.gmc_byte_pix_order = 1;
324 gmc.f.gmc_default_sel = 0;
325 gmc.f.gmc_rop3 = ROP3_SRCCOPY;
326 gmc.f.gmc_dp_src_source = DP_SRC_MEM_RECTANGULAR;
327 gmc.f.gmc_clr_cmp_fcn_dis = 1;
328 gmc.f.gmc_wr_msk_dis = 1;
329 gmc.f.gmc_dp_op = DP_OP_ROP;
330 writel(gmc.val, remapped_regs + mmDP_GUI_MASTER_CNTL);
331
332 dp_datatype.val = dp_mix.val = 0;
333 dp_datatype.f.dp_dst_datatype = gmc.f.gmc_dst_datatype;
334 dp_datatype.f.dp_brush_datatype = gmc.f.gmc_brush_datatype;
335 dp_datatype.f.dp_src2_type = 0;
336 dp_datatype.f.dp_src2_datatype = gmc.f.gmc_src_datatype;
337 dp_datatype.f.dp_src_datatype = gmc.f.gmc_src_datatype;
338 dp_datatype.f.dp_byte_pix_order = gmc.f.gmc_byte_pix_order;
339 writel(dp_datatype.val, remapped_regs + mmDP_DATATYPE);
340
341 dp_mix.f.dp_src_source = gmc.f.gmc_dp_src_source;
342 dp_mix.f.dp_src2_source = 1;
343 dp_mix.f.dp_rop3 = gmc.f.gmc_rop3;
344 dp_mix.f.dp_op = gmc.f.gmc_dp_op;
345 writel(dp_mix.val, remapped_regs + mmDP_MIX);
346}
347
348
349static void w100fb_fillrect(struct fb_info *info,
350 const struct fb_fillrect *rect)
351{
352 union dp_gui_master_cntl_u gmc;
353
354 if (info->state != FBINFO_STATE_RUNNING)
355 return;
356 if (info->flags & FBINFO_HWACCEL_DISABLED) {
357 cfb_fillrect(info, rect);
358 return;
359 }
360
361 gmc.val = readl(remapped_regs + mmDP_GUI_MASTER_CNTL);
362 gmc.f.gmc_rop3 = ROP3_PATCOPY;
363 gmc.f.gmc_brush_datatype = GMC_BRUSH_SOLID_COLOR;
364 w100_fifo_wait(2);
365 writel(gmc.val, remapped_regs + mmDP_GUI_MASTER_CNTL);
366 writel(rect->color, remapped_regs + mmDP_BRUSH_FRGD_CLR);
367
368 w100_fifo_wait(2);
369 writel((rect->dy << 16) | (rect->dx & 0xffff), remapped_regs + mmDST_Y_X);
370 writel((rect->width << 16) | (rect->height & 0xffff),
371 remapped_regs + mmDST_WIDTH_HEIGHT);
372}
373
374
375static void w100fb_copyarea(struct fb_info *info,
376 const struct fb_copyarea *area)
377{
378 u32 dx = area->dx, dy = area->dy, sx = area->sx, sy = area->sy;
379 u32 h = area->height, w = area->width;
380 union dp_gui_master_cntl_u gmc;
381
382 if (info->state != FBINFO_STATE_RUNNING)
383 return;
384 if (info->flags & FBINFO_HWACCEL_DISABLED) {
385 cfb_copyarea(info, area);
386 return;
387 }
388
389 gmc.val = readl(remapped_regs + mmDP_GUI_MASTER_CNTL);
390 gmc.f.gmc_rop3 = ROP3_SRCCOPY;
391 gmc.f.gmc_brush_datatype = GMC_BRUSH_NONE;
392 w100_fifo_wait(1);
393 writel(gmc.val, remapped_regs + mmDP_GUI_MASTER_CNTL);
394
395 w100_fifo_wait(3);
396 writel((sy << 16) | (sx & 0xffff), remapped_regs + mmSRC_Y_X);
397 writel((dy << 16) | (dx & 0xffff), remapped_regs + mmDST_Y_X);
398 writel((w << 16) | (h & 0xffff), remapped_regs + mmDST_WIDTH_HEIGHT);
399}
400
401
251/* 402/*
252 * Change the resolution by calling the appropriate hardware functions 403 * Change the resolution by calling the appropriate hardware functions
253 */ 404 */
@@ -265,6 +416,7 @@ static void w100fb_activate_var(struct w100fb_par *par)
265 w100_init_lcd(par); 416 w100_init_lcd(par);
266 w100_set_dispregs(par); 417 w100_set_dispregs(par);
267 w100_update_enable(); 418 w100_update_enable();
419 w100_init_graphic_engine(par);
268 420
269 calc_hsync(par); 421 calc_hsync(par);
270 422
@@ -394,9 +546,10 @@ static struct fb_ops w100fb_ops = {
394 .fb_set_par = w100fb_set_par, 546 .fb_set_par = w100fb_set_par,
395 .fb_setcolreg = w100fb_setcolreg, 547 .fb_setcolreg = w100fb_setcolreg,
396 .fb_blank = w100fb_blank, 548 .fb_blank = w100fb_blank,
397 .fb_fillrect = cfb_fillrect, 549 .fb_fillrect = w100fb_fillrect,
398 .fb_copyarea = cfb_copyarea, 550 .fb_copyarea = w100fb_copyarea,
399 .fb_imageblit = cfb_imageblit, 551 .fb_imageblit = cfb_imageblit,
552 .fb_sync = w100fb_sync,
400}; 553};
401 554
402#ifdef CONFIG_PM 555#ifdef CONFIG_PM
@@ -543,7 +696,8 @@ int __init w100fb_probe(struct platform_device *pdev)
543 } 696 }
544 697
545 info->fbops = &w100fb_ops; 698 info->fbops = &w100fb_ops;
546 info->flags = FBINFO_DEFAULT; 699 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA |
700 FBINFO_HWACCEL_FILLRECT;
547 info->node = -1; 701 info->node = -1;
548 info->screen_base = remapped_fbuf + (W100_FB_BASE-MEM_WINDOW_BASE); 702 info->screen_base = remapped_fbuf + (W100_FB_BASE-MEM_WINDOW_BASE);
549 info->screen_size = REMAPPED_FB_LEN; 703 info->screen_size = REMAPPED_FB_LEN;
diff --git a/drivers/video/w100fb.h b/drivers/video/w100fb.h
index 7a58a1e3e427..fffae7b4f6e9 100644
--- a/drivers/video/w100fb.h
+++ b/drivers/video/w100fb.h
@@ -122,15 +122,32 @@
122/* Block DISPLAY End: */ 122/* Block DISPLAY End: */
123 123
124/* Block GFX Start: */ 124/* Block GFX Start: */
125#define mmDST_OFFSET 0x1004
126#define mmDST_PITCH 0x1008
127#define mmDST_Y_X 0x1038
128#define mmDST_WIDTH_HEIGHT 0x1198
129#define mmDP_GUI_MASTER_CNTL 0x106C
125#define mmBRUSH_OFFSET 0x108C 130#define mmBRUSH_OFFSET 0x108C
126#define mmBRUSH_Y_X 0x1074 131#define mmBRUSH_Y_X 0x1074
132#define mmDP_BRUSH_FRGD_CLR 0x107C
133#define mmSRC_OFFSET 0x11AC
134#define mmSRC_PITCH 0x11B0
135#define mmSRC_Y_X 0x1034
127#define mmDEFAULT_PITCH_OFFSET 0x10A0 136#define mmDEFAULT_PITCH_OFFSET 0x10A0
128#define mmDEFAULT_SC_BOTTOM_RIGHT 0x10A8 137#define mmDEFAULT_SC_BOTTOM_RIGHT 0x10A8
129#define mmDEFAULT2_SC_BOTTOM_RIGHT 0x10AC 138#define mmDEFAULT2_SC_BOTTOM_RIGHT 0x10AC
139#define mmSC_TOP_LEFT 0x11BC
140#define mmSC_BOTTOM_RIGHT 0x11C0
141#define mmSRC_SC_BOTTOM_RIGHT 0x11C4
130#define mmGLOBAL_ALPHA 0x1210 142#define mmGLOBAL_ALPHA 0x1210
131#define mmFILTER_COEF 0x1214 143#define mmFILTER_COEF 0x1214
132#define mmMVC_CNTL_START 0x11E0 144#define mmMVC_CNTL_START 0x11E0
133#define mmE2_ARITHMETIC_CNTL 0x1220 145#define mmE2_ARITHMETIC_CNTL 0x1220
146#define mmDP_CNTL 0x11C8
147#define mmDP_CNTL_DST_DIR 0x11CC
148#define mmDP_DATATYPE 0x12C4
149#define mmDP_MIX 0x12C8
150#define mmDP_WRITE_MSK 0x12CC
134#define mmENG_CNTL 0x13E8 151#define mmENG_CNTL 0x13E8
135#define mmENG_PERF_CNT 0x13F0 152#define mmENG_PERF_CNT 0x13F0
136/* Block GFX End: */ 153/* Block GFX End: */
@@ -179,6 +196,7 @@
179/* Block RBBM Start: */ 196/* Block RBBM Start: */
180#define mmWAIT_UNTIL 0x1400 197#define mmWAIT_UNTIL 0x1400
181#define mmISYNC_CNTL 0x1404 198#define mmISYNC_CNTL 0x1404
199#define mmRBBM_STATUS 0x0140
182#define mmRBBM_CNTL 0x0144 200#define mmRBBM_CNTL 0x0144
183#define mmNQWAIT_UNTIL 0x0150 201#define mmNQWAIT_UNTIL 0x0150
184/* Block RBBM End: */ 202/* Block RBBM End: */
@@ -225,147 +243,147 @@
225/* Register structure definitions */ 243/* Register structure definitions */
226 244
227struct wrap_top_dir_t { 245struct wrap_top_dir_t {
228 unsigned long top_addr : 23; 246 u32 top_addr : 23;
229 unsigned long : 9; 247 u32 : 9;
230} __attribute__((packed)); 248} __attribute__((packed));
231 249
232union wrap_top_dir_u { 250union wrap_top_dir_u {
233 unsigned long val : 32; 251 u32 val : 32;
234 struct wrap_top_dir_t f; 252 struct wrap_top_dir_t f;
235} __attribute__((packed)); 253} __attribute__((packed));
236 254
237struct wrap_start_dir_t { 255struct wrap_start_dir_t {
238 unsigned long start_addr : 23; 256 u32 start_addr : 23;
239 unsigned long : 9; 257 u32 : 9;
240} __attribute__((packed)); 258} __attribute__((packed));
241 259
242union wrap_start_dir_u { 260union wrap_start_dir_u {
243 unsigned long val : 32; 261 u32 val : 32;
244 struct wrap_start_dir_t f; 262 struct wrap_start_dir_t f;
245} __attribute__((packed)); 263} __attribute__((packed));
246 264
247struct cif_cntl_t { 265struct cif_cntl_t {
248 unsigned long swap_reg : 2; 266 u32 swap_reg : 2;
249 unsigned long swap_fbuf_1 : 2; 267 u32 swap_fbuf_1 : 2;
250 unsigned long swap_fbuf_2 : 2; 268 u32 swap_fbuf_2 : 2;
251 unsigned long swap_fbuf_3 : 2; 269 u32 swap_fbuf_3 : 2;
252 unsigned long pmi_int_disable : 1; 270 u32 pmi_int_disable : 1;
253 unsigned long pmi_schmen_disable : 1; 271 u32 pmi_schmen_disable : 1;
254 unsigned long intb_oe : 1; 272 u32 intb_oe : 1;
255 unsigned long en_wait_to_compensate_dq_prop_dly : 1; 273 u32 en_wait_to_compensate_dq_prop_dly : 1;
256 unsigned long compensate_wait_rd_size : 2; 274 u32 compensate_wait_rd_size : 2;
257 unsigned long wait_asserted_timeout_val : 2; 275 u32 wait_asserted_timeout_val : 2;
258 unsigned long wait_masked_val : 2; 276 u32 wait_masked_val : 2;
259 unsigned long en_wait_timeout : 1; 277 u32 en_wait_timeout : 1;
260 unsigned long en_one_clk_setup_before_wait : 1; 278 u32 en_one_clk_setup_before_wait : 1;
261 unsigned long interrupt_active_high : 1; 279 u32 interrupt_active_high : 1;
262 unsigned long en_overwrite_straps : 1; 280 u32 en_overwrite_straps : 1;
263 unsigned long strap_wait_active_hi : 1; 281 u32 strap_wait_active_hi : 1;
264 unsigned long lat_busy_count : 2; 282 u32 lat_busy_count : 2;
265 unsigned long lat_rd_pm4_sclk_busy : 1; 283 u32 lat_rd_pm4_sclk_busy : 1;
266 unsigned long dis_system_bits : 1; 284 u32 dis_system_bits : 1;
267 unsigned long dis_mr : 1; 285 u32 dis_mr : 1;
268 unsigned long cif_spare_1 : 4; 286 u32 cif_spare_1 : 4;
269} __attribute__((packed)); 287} __attribute__((packed));
270 288
271union cif_cntl_u { 289union cif_cntl_u {
272 unsigned long val : 32; 290 u32 val : 32;
273 struct cif_cntl_t f; 291 struct cif_cntl_t f;
274} __attribute__((packed)); 292} __attribute__((packed));
275 293
276struct cfgreg_base_t { 294struct cfgreg_base_t {
277 unsigned long cfgreg_base : 24; 295 u32 cfgreg_base : 24;
278 unsigned long : 8; 296 u32 : 8;
279} __attribute__((packed)); 297} __attribute__((packed));
280 298
281union cfgreg_base_u { 299union cfgreg_base_u {
282 unsigned long val : 32; 300 u32 val : 32;
283 struct cfgreg_base_t f; 301 struct cfgreg_base_t f;
284} __attribute__((packed)); 302} __attribute__((packed));
285 303
286struct cif_io_t { 304struct cif_io_t {
287 unsigned long dq_srp : 1; 305 u32 dq_srp : 1;
288 unsigned long dq_srn : 1; 306 u32 dq_srn : 1;
289 unsigned long dq_sp : 4; 307 u32 dq_sp : 4;
290 unsigned long dq_sn : 4; 308 u32 dq_sn : 4;
291 unsigned long waitb_srp : 1; 309 u32 waitb_srp : 1;
292 unsigned long waitb_srn : 1; 310 u32 waitb_srn : 1;
293 unsigned long waitb_sp : 4; 311 u32 waitb_sp : 4;
294 unsigned long waitb_sn : 4; 312 u32 waitb_sn : 4;
295 unsigned long intb_srp : 1; 313 u32 intb_srp : 1;
296 unsigned long intb_srn : 1; 314 u32 intb_srn : 1;
297 unsigned long intb_sp : 4; 315 u32 intb_sp : 4;
298 unsigned long intb_sn : 4; 316 u32 intb_sn : 4;
299 unsigned long : 2; 317 u32 : 2;
300} __attribute__((packed)); 318} __attribute__((packed));
301 319
302union cif_io_u { 320union cif_io_u {
303 unsigned long val : 32; 321 u32 val : 32;
304 struct cif_io_t f; 322 struct cif_io_t f;
305} __attribute__((packed)); 323} __attribute__((packed));
306 324
307struct cif_read_dbg_t { 325struct cif_read_dbg_t {
308 unsigned long unpacker_pre_fetch_trig_gen : 2; 326 u32 unpacker_pre_fetch_trig_gen : 2;
309 unsigned long dly_second_rd_fetch_trig : 1; 327 u32 dly_second_rd_fetch_trig : 1;
310 unsigned long rst_rd_burst_id : 1; 328 u32 rst_rd_burst_id : 1;
311 unsigned long dis_rd_burst_id : 1; 329 u32 dis_rd_burst_id : 1;
312 unsigned long en_block_rd_when_packer_is_not_emp : 1; 330 u32 en_block_rd_when_packer_is_not_emp : 1;
313 unsigned long dis_pre_fetch_cntl_sm : 1; 331 u32 dis_pre_fetch_cntl_sm : 1;
314 unsigned long rbbm_chrncy_dis : 1; 332 u32 rbbm_chrncy_dis : 1;
315 unsigned long rbbm_rd_after_wr_lat : 2; 333 u32 rbbm_rd_after_wr_lat : 2;
316 unsigned long dis_be_during_rd : 1; 334 u32 dis_be_during_rd : 1;
317 unsigned long one_clk_invalidate_pulse : 1; 335 u32 one_clk_invalidate_pulse : 1;
318 unsigned long dis_chnl_priority : 1; 336 u32 dis_chnl_priority : 1;
319 unsigned long rst_read_path_a_pls : 1; 337 u32 rst_read_path_a_pls : 1;
320 unsigned long rst_read_path_b_pls : 1; 338 u32 rst_read_path_b_pls : 1;
321 unsigned long dis_reg_rd_fetch_trig : 1; 339 u32 dis_reg_rd_fetch_trig : 1;
322 unsigned long dis_rd_fetch_trig_from_ind_addr : 1; 340 u32 dis_rd_fetch_trig_from_ind_addr : 1;
323 unsigned long dis_rd_same_byte_to_trig_fetch : 1; 341 u32 dis_rd_same_byte_to_trig_fetch : 1;
324 unsigned long dis_dir_wrap : 1; 342 u32 dis_dir_wrap : 1;
325 unsigned long dis_ring_buf_to_force_dec : 1; 343 u32 dis_ring_buf_to_force_dec : 1;
326 unsigned long dis_addr_comp_in_16bit : 1; 344 u32 dis_addr_comp_in_16bit : 1;
327 unsigned long clr_w : 1; 345 u32 clr_w : 1;
328 unsigned long err_rd_tag_is_3 : 1; 346 u32 err_rd_tag_is_3 : 1;
329 unsigned long err_load_when_ful_a : 1; 347 u32 err_load_when_ful_a : 1;
330 unsigned long err_load_when_ful_b : 1; 348 u32 err_load_when_ful_b : 1;
331 unsigned long : 7; 349 u32 : 7;
332} __attribute__((packed)); 350} __attribute__((packed));
333 351
334union cif_read_dbg_u { 352union cif_read_dbg_u {
335 unsigned long val : 32; 353 u32 val : 32;
336 struct cif_read_dbg_t f; 354 struct cif_read_dbg_t f;
337} __attribute__((packed)); 355} __attribute__((packed));
338 356
339struct cif_write_dbg_t { 357struct cif_write_dbg_t {
340 unsigned long packer_timeout_count : 2; 358 u32 packer_timeout_count : 2;
341 unsigned long en_upper_load_cond : 1; 359 u32 en_upper_load_cond : 1;
342 unsigned long en_chnl_change_cond : 1; 360 u32 en_chnl_change_cond : 1;
343 unsigned long dis_addr_comp_cond : 1; 361 u32 dis_addr_comp_cond : 1;
344 unsigned long dis_load_same_byte_addr_cond : 1; 362 u32 dis_load_same_byte_addr_cond : 1;
345 unsigned long dis_timeout_cond : 1; 363 u32 dis_timeout_cond : 1;
346 unsigned long dis_timeout_during_rbbm : 1; 364 u32 dis_timeout_during_rbbm : 1;
347 unsigned long dis_packer_ful_during_rbbm_timeout : 1; 365 u32 dis_packer_ful_during_rbbm_timeout : 1;
348 unsigned long en_dword_split_to_rbbm : 1; 366 u32 en_dword_split_to_rbbm : 1;
349 unsigned long en_dummy_val : 1; 367 u32 en_dummy_val : 1;
350 unsigned long dummy_val_sel : 1; 368 u32 dummy_val_sel : 1;
351 unsigned long mask_pm4_wrptr_dec : 1; 369 u32 mask_pm4_wrptr_dec : 1;
352 unsigned long dis_mc_clean_cond : 1; 370 u32 dis_mc_clean_cond : 1;
353 unsigned long err_two_reqi_during_ful : 1; 371 u32 err_two_reqi_during_ful : 1;
354 unsigned long err_reqi_during_idle_clk : 1; 372 u32 err_reqi_during_idle_clk : 1;
355 unsigned long err_global : 1; 373 u32 err_global : 1;
356 unsigned long en_wr_buf_dbg_load : 1; 374 u32 en_wr_buf_dbg_load : 1;
357 unsigned long en_wr_buf_dbg_path : 1; 375 u32 en_wr_buf_dbg_path : 1;
358 unsigned long sel_wr_buf_byte : 3; 376 u32 sel_wr_buf_byte : 3;
359 unsigned long dis_rd_flush_wr : 1; 377 u32 dis_rd_flush_wr : 1;
360 unsigned long dis_packer_ful_cond : 1; 378 u32 dis_packer_ful_cond : 1;
361 unsigned long dis_invalidate_by_ops_chnl : 1; 379 u32 dis_invalidate_by_ops_chnl : 1;
362 unsigned long en_halt_when_reqi_err : 1; 380 u32 en_halt_when_reqi_err : 1;
363 unsigned long cif_spare_2 : 5; 381 u32 cif_spare_2 : 5;
364 unsigned long : 1; 382 u32 : 1;
365} __attribute__((packed)); 383} __attribute__((packed));
366 384
367union cif_write_dbg_u { 385union cif_write_dbg_u {
368 unsigned long val : 32; 386 u32 val : 32;
369 struct cif_write_dbg_t f; 387 struct cif_write_dbg_t f;
370} __attribute__((packed)); 388} __attribute__((packed));
371 389
@@ -403,327 +421,327 @@ union cpu_defaults_u {
403} __attribute__((packed)); 421} __attribute__((packed));
404 422
405struct crtc_total_t { 423struct crtc_total_t {
406 unsigned long crtc_h_total : 10; 424 u32 crtc_h_total : 10;
407 unsigned long : 6; 425 u32 : 6;
408 unsigned long crtc_v_total : 10; 426 u32 crtc_v_total : 10;
409 unsigned long : 6; 427 u32 : 6;
410} __attribute__((packed)); 428} __attribute__((packed));
411 429
412union crtc_total_u { 430union crtc_total_u {
413 unsigned long val : 32; 431 u32 val : 32;
414 struct crtc_total_t f; 432 struct crtc_total_t f;
415} __attribute__((packed)); 433} __attribute__((packed));
416 434
417struct crtc_ss_t { 435struct crtc_ss_t {
418 unsigned long ss_start : 10; 436 u32 ss_start : 10;
419 unsigned long : 6; 437 u32 : 6;
420 unsigned long ss_end : 10; 438 u32 ss_end : 10;
421 unsigned long : 2; 439 u32 : 2;
422 unsigned long ss_align : 1; 440 u32 ss_align : 1;
423 unsigned long ss_pol : 1; 441 u32 ss_pol : 1;
424 unsigned long ss_run_mode : 1; 442 u32 ss_run_mode : 1;
425 unsigned long ss_en : 1; 443 u32 ss_en : 1;
426} __attribute__((packed)); 444} __attribute__((packed));
427 445
428union crtc_ss_u { 446union crtc_ss_u {
429 unsigned long val : 32; 447 u32 val : 32;
430 struct crtc_ss_t f; 448 struct crtc_ss_t f;
431} __attribute__((packed)); 449} __attribute__((packed));
432 450
433struct active_h_disp_t { 451struct active_h_disp_t {
434 unsigned long active_h_start : 10; 452 u32 active_h_start : 10;
435 unsigned long : 6; 453 u32 : 6;
436 unsigned long active_h_end : 10; 454 u32 active_h_end : 10;
437 unsigned long : 6; 455 u32 : 6;
438} __attribute__((packed)); 456} __attribute__((packed));
439 457
440union active_h_disp_u { 458union active_h_disp_u {
441 unsigned long val : 32; 459 u32 val : 32;
442 struct active_h_disp_t f; 460 struct active_h_disp_t f;
443} __attribute__((packed)); 461} __attribute__((packed));
444 462
445struct active_v_disp_t { 463struct active_v_disp_t {
446 unsigned long active_v_start : 10; 464 u32 active_v_start : 10;
447 unsigned long : 6; 465 u32 : 6;
448 unsigned long active_v_end : 10; 466 u32 active_v_end : 10;
449 unsigned long : 6; 467 u32 : 6;
450} __attribute__((packed)); 468} __attribute__((packed));
451 469
452union active_v_disp_u { 470union active_v_disp_u {
453 unsigned long val : 32; 471 u32 val : 32;
454 struct active_v_disp_t f; 472 struct active_v_disp_t f;
455} __attribute__((packed)); 473} __attribute__((packed));
456 474
457struct graphic_h_disp_t { 475struct graphic_h_disp_t {
458 unsigned long graphic_h_start : 10; 476 u32 graphic_h_start : 10;
459 unsigned long : 6; 477 u32 : 6;
460 unsigned long graphic_h_end : 10; 478 u32 graphic_h_end : 10;
461 unsigned long : 6; 479 u32 : 6;
462} __attribute__((packed)); 480} __attribute__((packed));
463 481
464union graphic_h_disp_u { 482union graphic_h_disp_u {
465 unsigned long val : 32; 483 u32 val : 32;
466 struct graphic_h_disp_t f; 484 struct graphic_h_disp_t f;
467} __attribute__((packed)); 485} __attribute__((packed));
468 486
469struct graphic_v_disp_t { 487struct graphic_v_disp_t {
470 unsigned long graphic_v_start : 10; 488 u32 graphic_v_start : 10;
471 unsigned long : 6; 489 u32 : 6;
472 unsigned long graphic_v_end : 10; 490 u32 graphic_v_end : 10;
473 unsigned long : 6; 491 u32 : 6;
474} __attribute__((packed)); 492} __attribute__((packed));
475 493
476union graphic_v_disp_u{ 494union graphic_v_disp_u{
477 unsigned long val : 32; 495 u32 val : 32;
478 struct graphic_v_disp_t f; 496 struct graphic_v_disp_t f;
479} __attribute__((packed)); 497} __attribute__((packed));
480 498
481struct graphic_ctrl_t_w100 { 499struct graphic_ctrl_t_w100 {
482 unsigned long color_depth : 3; 500 u32 color_depth : 3;
483 unsigned long portrait_mode : 2; 501 u32 portrait_mode : 2;
484 unsigned long low_power_on : 1; 502 u32 low_power_on : 1;
485 unsigned long req_freq : 4; 503 u32 req_freq : 4;
486 unsigned long en_crtc : 1; 504 u32 en_crtc : 1;
487 unsigned long en_graphic_req : 1; 505 u32 en_graphic_req : 1;
488 unsigned long en_graphic_crtc : 1; 506 u32 en_graphic_crtc : 1;
489 unsigned long total_req_graphic : 9; 507 u32 total_req_graphic : 9;
490 unsigned long lcd_pclk_on : 1; 508 u32 lcd_pclk_on : 1;
491 unsigned long lcd_sclk_on : 1; 509 u32 lcd_sclk_on : 1;
492 unsigned long pclk_running : 1; 510 u32 pclk_running : 1;
493 unsigned long sclk_running : 1; 511 u32 sclk_running : 1;
494 unsigned long : 6; 512 u32 : 6;
495} __attribute__((packed)); 513} __attribute__((packed));
496 514
497struct graphic_ctrl_t_w32xx { 515struct graphic_ctrl_t_w32xx {
498 unsigned long color_depth : 3; 516 u32 color_depth : 3;
499 unsigned long portrait_mode : 2; 517 u32 portrait_mode : 2;
500 unsigned long low_power_on : 1; 518 u32 low_power_on : 1;
501 unsigned long req_freq : 4; 519 u32 req_freq : 4;
502 unsigned long en_crtc : 1; 520 u32 en_crtc : 1;
503 unsigned long en_graphic_req : 1; 521 u32 en_graphic_req : 1;
504 unsigned long en_graphic_crtc : 1; 522 u32 en_graphic_crtc : 1;
505 unsigned long total_req_graphic : 10; 523 u32 total_req_graphic : 10;
506 unsigned long lcd_pclk_on : 1; 524 u32 lcd_pclk_on : 1;
507 unsigned long lcd_sclk_on : 1; 525 u32 lcd_sclk_on : 1;
508 unsigned long pclk_running : 1; 526 u32 pclk_running : 1;
509 unsigned long sclk_running : 1; 527 u32 sclk_running : 1;
510 unsigned long : 5; 528 u32 : 5;
511} __attribute__((packed)); 529} __attribute__((packed));
512 530
513union graphic_ctrl_u { 531union graphic_ctrl_u {
514 unsigned long val : 32; 532 u32 val : 32;
515 struct graphic_ctrl_t_w100 f_w100; 533 struct graphic_ctrl_t_w100 f_w100;
516 struct graphic_ctrl_t_w32xx f_w32xx; 534 struct graphic_ctrl_t_w32xx f_w32xx;
517} __attribute__((packed)); 535} __attribute__((packed));
518 536
519struct video_ctrl_t { 537struct video_ctrl_t {
520 unsigned long video_mode : 1; 538 u32 video_mode : 1;
521 unsigned long keyer_en : 1; 539 u32 keyer_en : 1;
522 unsigned long en_video_req : 1; 540 u32 en_video_req : 1;
523 unsigned long en_graphic_req_video : 1; 541 u32 en_graphic_req_video : 1;
524 unsigned long en_video_crtc : 1; 542 u32 en_video_crtc : 1;
525 unsigned long video_hor_exp : 2; 543 u32 video_hor_exp : 2;
526 unsigned long video_ver_exp : 2; 544 u32 video_ver_exp : 2;
527 unsigned long uv_combine : 1; 545 u32 uv_combine : 1;
528 unsigned long total_req_video : 9; 546 u32 total_req_video : 9;
529 unsigned long video_ch_sel : 1; 547 u32 video_ch_sel : 1;
530 unsigned long video_portrait : 2; 548 u32 video_portrait : 2;
531 unsigned long yuv2rgb_en : 1; 549 u32 yuv2rgb_en : 1;
532 unsigned long yuv2rgb_option : 1; 550 u32 yuv2rgb_option : 1;
533 unsigned long video_inv_hor : 1; 551 u32 video_inv_hor : 1;
534 unsigned long video_inv_ver : 1; 552 u32 video_inv_ver : 1;
535 unsigned long gamma_sel : 2; 553 u32 gamma_sel : 2;
536 unsigned long dis_limit : 1; 554 u32 dis_limit : 1;
537 unsigned long en_uv_hblend : 1; 555 u32 en_uv_hblend : 1;
538 unsigned long rgb_gamma_sel : 2; 556 u32 rgb_gamma_sel : 2;
539} __attribute__((packed)); 557} __attribute__((packed));
540 558
541union video_ctrl_u { 559union video_ctrl_u {
542 unsigned long val : 32; 560 u32 val : 32;
543 struct video_ctrl_t f; 561 struct video_ctrl_t f;
544} __attribute__((packed)); 562} __attribute__((packed));
545 563
546struct disp_db_buf_cntl_rd_t { 564struct disp_db_buf_cntl_rd_t {
547 unsigned long en_db_buf : 1; 565 u32 en_db_buf : 1;
548 unsigned long update_db_buf_done : 1; 566 u32 update_db_buf_done : 1;
549 unsigned long db_buf_cntl : 6; 567 u32 db_buf_cntl : 6;
550 unsigned long : 24; 568 u32 : 24;
551} __attribute__((packed)); 569} __attribute__((packed));
552 570
553union disp_db_buf_cntl_rd_u { 571union disp_db_buf_cntl_rd_u {
554 unsigned long val : 32; 572 u32 val : 32;
555 struct disp_db_buf_cntl_rd_t f; 573 struct disp_db_buf_cntl_rd_t f;
556} __attribute__((packed)); 574} __attribute__((packed));
557 575
558struct disp_db_buf_cntl_wr_t { 576struct disp_db_buf_cntl_wr_t {
559 unsigned long en_db_buf : 1; 577 u32 en_db_buf : 1;
560 unsigned long update_db_buf : 1; 578 u32 update_db_buf : 1;
561 unsigned long db_buf_cntl : 6; 579 u32 db_buf_cntl : 6;
562 unsigned long : 24; 580 u32 : 24;
563} __attribute__((packed)); 581} __attribute__((packed));
564 582
565union disp_db_buf_cntl_wr_u { 583union disp_db_buf_cntl_wr_u {
566 unsigned long val : 32; 584 u32 val : 32;
567 struct disp_db_buf_cntl_wr_t f; 585 struct disp_db_buf_cntl_wr_t f;
568} __attribute__((packed)); 586} __attribute__((packed));
569 587
570struct gamma_value1_t { 588struct gamma_value1_t {
571 unsigned long gamma1 : 8; 589 u32 gamma1 : 8;
572 unsigned long gamma2 : 8; 590 u32 gamma2 : 8;
573 unsigned long gamma3 : 8; 591 u32 gamma3 : 8;
574 unsigned long gamma4 : 8; 592 u32 gamma4 : 8;
575} __attribute__((packed)); 593} __attribute__((packed));
576 594
577union gamma_value1_u { 595union gamma_value1_u {
578 unsigned long val : 32; 596 u32 val : 32;
579 struct gamma_value1_t f; 597 struct gamma_value1_t f;
580} __attribute__((packed)); 598} __attribute__((packed));
581 599
582struct gamma_value2_t { 600struct gamma_value2_t {
583 unsigned long gamma5 : 8; 601 u32 gamma5 : 8;
584 unsigned long gamma6 : 8; 602 u32 gamma6 : 8;
585 unsigned long gamma7 : 8; 603 u32 gamma7 : 8;
586 unsigned long gamma8 : 8; 604 u32 gamma8 : 8;
587} __attribute__((packed)); 605} __attribute__((packed));
588 606
589union gamma_value2_u { 607union gamma_value2_u {
590 unsigned long val : 32; 608 u32 val : 32;
591 struct gamma_value2_t f; 609 struct gamma_value2_t f;
592} __attribute__((packed)); 610} __attribute__((packed));
593 611
594struct gamma_slope_t { 612struct gamma_slope_t {
595 unsigned long slope1 : 3; 613 u32 slope1 : 3;
596 unsigned long slope2 : 3; 614 u32 slope2 : 3;
597 unsigned long slope3 : 3; 615 u32 slope3 : 3;
598 unsigned long slope4 : 3; 616 u32 slope4 : 3;
599 unsigned long slope5 : 3; 617 u32 slope5 : 3;
600 unsigned long slope6 : 3; 618 u32 slope6 : 3;
601 unsigned long slope7 : 3; 619 u32 slope7 : 3;
602 unsigned long slope8 : 3; 620 u32 slope8 : 3;
603 unsigned long : 8; 621 u32 : 8;
604} __attribute__((packed)); 622} __attribute__((packed));
605 623
606union gamma_slope_u { 624union gamma_slope_u {
607 unsigned long val : 32; 625 u32 val : 32;
608 struct gamma_slope_t f; 626 struct gamma_slope_t f;
609} __attribute__((packed)); 627} __attribute__((packed));
610 628
611struct mc_ext_mem_location_t { 629struct mc_ext_mem_location_t {
612 unsigned long mc_ext_mem_start : 16; 630 u32 mc_ext_mem_start : 16;
613 unsigned long mc_ext_mem_top : 16; 631 u32 mc_ext_mem_top : 16;
614} __attribute__((packed)); 632} __attribute__((packed));
615 633
616union mc_ext_mem_location_u { 634union mc_ext_mem_location_u {
617 unsigned long val : 32; 635 u32 val : 32;
618 struct mc_ext_mem_location_t f; 636 struct mc_ext_mem_location_t f;
619} __attribute__((packed)); 637} __attribute__((packed));
620 638
621struct mc_fb_location_t { 639struct mc_fb_location_t {
622 unsigned long mc_fb_start : 16; 640 u32 mc_fb_start : 16;
623 unsigned long mc_fb_top : 16; 641 u32 mc_fb_top : 16;
624} __attribute__((packed)); 642} __attribute__((packed));
625 643
626union mc_fb_location_u { 644union mc_fb_location_u {
627 unsigned long val : 32; 645 u32 val : 32;
628 struct mc_fb_location_t f; 646 struct mc_fb_location_t f;
629} __attribute__((packed)); 647} __attribute__((packed));
630 648
631struct clk_pin_cntl_t { 649struct clk_pin_cntl_t {
632 unsigned long osc_en : 1; 650 u32 osc_en : 1;
633 unsigned long osc_gain : 5; 651 u32 osc_gain : 5;
634 unsigned long dont_use_xtalin : 1; 652 u32 dont_use_xtalin : 1;
635 unsigned long xtalin_pm_en : 1; 653 u32 xtalin_pm_en : 1;
636 unsigned long xtalin_dbl_en : 1; 654 u32 xtalin_dbl_en : 1;
637 unsigned long : 7; 655 u32 : 7;
638 unsigned long cg_debug : 16; 656 u32 cg_debug : 16;
639} __attribute__((packed)); 657} __attribute__((packed));
640 658
641union clk_pin_cntl_u { 659union clk_pin_cntl_u {
642 unsigned long val : 32; 660 u32 val : 32;
643 struct clk_pin_cntl_t f; 661 struct clk_pin_cntl_t f;
644} __attribute__((packed)); 662} __attribute__((packed));
645 663
646struct pll_ref_fb_div_t { 664struct pll_ref_fb_div_t {
647 unsigned long pll_ref_div : 4; 665 u32 pll_ref_div : 4;
648 unsigned long : 4; 666 u32 : 4;
649 unsigned long pll_fb_div_int : 6; 667 u32 pll_fb_div_int : 6;
650 unsigned long : 2; 668 u32 : 2;
651 unsigned long pll_fb_div_frac : 3; 669 u32 pll_fb_div_frac : 3;
652 unsigned long : 1; 670 u32 : 1;
653 unsigned long pll_reset_time : 4; 671 u32 pll_reset_time : 4;
654 unsigned long pll_lock_time : 8; 672 u32 pll_lock_time : 8;
655} __attribute__((packed)); 673} __attribute__((packed));
656 674
657union pll_ref_fb_div_u { 675union pll_ref_fb_div_u {
658 unsigned long val : 32; 676 u32 val : 32;
659 struct pll_ref_fb_div_t f; 677 struct pll_ref_fb_div_t f;
660} __attribute__((packed)); 678} __attribute__((packed));
661 679
662struct pll_cntl_t { 680struct pll_cntl_t {
663 unsigned long pll_pwdn : 1; 681 u32 pll_pwdn : 1;
664 unsigned long pll_reset : 1; 682 u32 pll_reset : 1;
665 unsigned long pll_pm_en : 1; 683 u32 pll_pm_en : 1;
666 unsigned long pll_mode : 1; 684 u32 pll_mode : 1;
667 unsigned long pll_refclk_sel : 1; 685 u32 pll_refclk_sel : 1;
668 unsigned long pll_fbclk_sel : 1; 686 u32 pll_fbclk_sel : 1;
669 unsigned long pll_tcpoff : 1; 687 u32 pll_tcpoff : 1;
670 unsigned long pll_pcp : 3; 688 u32 pll_pcp : 3;
671 unsigned long pll_pvg : 3; 689 u32 pll_pvg : 3;
672 unsigned long pll_vcofr : 1; 690 u32 pll_vcofr : 1;
673 unsigned long pll_ioffset : 2; 691 u32 pll_ioffset : 2;
674 unsigned long pll_pecc_mode : 2; 692 u32 pll_pecc_mode : 2;
675 unsigned long pll_pecc_scon : 2; 693 u32 pll_pecc_scon : 2;
676 unsigned long pll_dactal : 4; 694 u32 pll_dactal : 4;
677 unsigned long pll_cp_clip : 2; 695 u32 pll_cp_clip : 2;
678 unsigned long pll_conf : 3; 696 u32 pll_conf : 3;
679 unsigned long pll_mbctrl : 2; 697 u32 pll_mbctrl : 2;
680 unsigned long pll_ring_off : 1; 698 u32 pll_ring_off : 1;
681} __attribute__((packed)); 699} __attribute__((packed));
682 700
683union pll_cntl_u { 701union pll_cntl_u {
684 unsigned long val : 32; 702 u32 val : 32;
685 struct pll_cntl_t f; 703 struct pll_cntl_t f;
686} __attribute__((packed)); 704} __attribute__((packed));
687 705
688struct sclk_cntl_t { 706struct sclk_cntl_t {
689 unsigned long sclk_src_sel : 2; 707 u32 sclk_src_sel : 2;
690 unsigned long : 2; 708 u32 : 2;
691 unsigned long sclk_post_div_fast : 4; 709 u32 sclk_post_div_fast : 4;
692 unsigned long sclk_clkon_hys : 3; 710 u32 sclk_clkon_hys : 3;
693 unsigned long sclk_post_div_slow : 4; 711 u32 sclk_post_div_slow : 4;
694 unsigned long disp_cg_ok2switch_en : 1; 712 u32 disp_cg_ok2switch_en : 1;
695 unsigned long sclk_force_reg : 1; 713 u32 sclk_force_reg : 1;
696 unsigned long sclk_force_disp : 1; 714 u32 sclk_force_disp : 1;
697 unsigned long sclk_force_mc : 1; 715 u32 sclk_force_mc : 1;
698 unsigned long sclk_force_extmc : 1; 716 u32 sclk_force_extmc : 1;
699 unsigned long sclk_force_cp : 1; 717 u32 sclk_force_cp : 1;
700 unsigned long sclk_force_e2 : 1; 718 u32 sclk_force_e2 : 1;
701 unsigned long sclk_force_e3 : 1; 719 u32 sclk_force_e3 : 1;
702 unsigned long sclk_force_idct : 1; 720 u32 sclk_force_idct : 1;
703 unsigned long sclk_force_bist : 1; 721 u32 sclk_force_bist : 1;
704 unsigned long busy_extend_cp : 1; 722 u32 busy_extend_cp : 1;
705 unsigned long busy_extend_e2 : 1; 723 u32 busy_extend_e2 : 1;
706 unsigned long busy_extend_e3 : 1; 724 u32 busy_extend_e3 : 1;
707 unsigned long busy_extend_idct : 1; 725 u32 busy_extend_idct : 1;
708 unsigned long : 3; 726 u32 : 3;
709} __attribute__((packed)); 727} __attribute__((packed));
710 728
711union sclk_cntl_u { 729union sclk_cntl_u {
712 unsigned long val : 32; 730 u32 val : 32;
713 struct sclk_cntl_t f; 731 struct sclk_cntl_t f;
714} __attribute__((packed)); 732} __attribute__((packed));
715 733
716struct pclk_cntl_t { 734struct pclk_cntl_t {
717 unsigned long pclk_src_sel : 2; 735 u32 pclk_src_sel : 2;
718 unsigned long : 2; 736 u32 : 2;
719 unsigned long pclk_post_div : 4; 737 u32 pclk_post_div : 4;
720 unsigned long : 8; 738 u32 : 8;
721 unsigned long pclk_force_disp : 1; 739 u32 pclk_force_disp : 1;
722 unsigned long : 15; 740 u32 : 15;
723} __attribute__((packed)); 741} __attribute__((packed));
724 742
725union pclk_cntl_u { 743union pclk_cntl_u {
726 unsigned long val : 32; 744 u32 val : 32;
727 struct pclk_cntl_t f; 745 struct pclk_cntl_t f;
728} __attribute__((packed)); 746} __attribute__((packed));
729 747
@@ -735,36 +753,176 @@ union pclk_cntl_u {
735#define TESTCLK_SRC_XTAL 0x06 753#define TESTCLK_SRC_XTAL 0x06
736 754
737struct clk_test_cntl_t { 755struct clk_test_cntl_t {
738 unsigned long testclk_sel : 4; 756 u32 testclk_sel : 4;
739 unsigned long : 3; 757 u32 : 3;
740 unsigned long start_check_freq : 1; 758 u32 start_check_freq : 1;
741 unsigned long tstcount_rst : 1; 759 u32 tstcount_rst : 1;
742 unsigned long : 15; 760 u32 : 15;
743 unsigned long test_count : 8; 761 u32 test_count : 8;
744} __attribute__((packed)); 762} __attribute__((packed));
745 763
746union clk_test_cntl_u { 764union clk_test_cntl_u {
747 unsigned long val : 32; 765 u32 val : 32;
748 struct clk_test_cntl_t f; 766 struct clk_test_cntl_t f;
749} __attribute__((packed)); 767} __attribute__((packed));
750 768
751struct pwrmgt_cntl_t { 769struct pwrmgt_cntl_t {
752 unsigned long pwm_enable : 1; 770 u32 pwm_enable : 1;
753 unsigned long : 1; 771 u32 : 1;
754 unsigned long pwm_mode_req : 2; 772 u32 pwm_mode_req : 2;
755 unsigned long pwm_wakeup_cond : 2; 773 u32 pwm_wakeup_cond : 2;
756 unsigned long pwm_fast_noml_hw_en : 1; 774 u32 pwm_fast_noml_hw_en : 1;
757 unsigned long pwm_noml_fast_hw_en : 1; 775 u32 pwm_noml_fast_hw_en : 1;
758 unsigned long pwm_fast_noml_cond : 4; 776 u32 pwm_fast_noml_cond : 4;
759 unsigned long pwm_noml_fast_cond : 4; 777 u32 pwm_noml_fast_cond : 4;
760 unsigned long pwm_idle_timer : 8; 778 u32 pwm_idle_timer : 8;
761 unsigned long pwm_busy_timer : 8; 779 u32 pwm_busy_timer : 8;
762} __attribute__((packed)); 780} __attribute__((packed));
763 781
764union pwrmgt_cntl_u { 782union pwrmgt_cntl_u {
765 unsigned long val : 32; 783 u32 val : 32;
766 struct pwrmgt_cntl_t f; 784 struct pwrmgt_cntl_t f;
767} __attribute__((packed)); 785} __attribute__((packed));
768 786
787#define SRC_DATATYPE_EQU_DST 3
788
789#define ROP3_SRCCOPY 0xcc
790#define ROP3_PATCOPY 0xf0
791
792#define GMC_BRUSH_SOLID_COLOR 13
793#define GMC_BRUSH_NONE 15
794
795#define DP_SRC_MEM_RECTANGULAR 2
796
797#define DP_OP_ROP 0
798
799struct dp_gui_master_cntl_t {
800 u32 gmc_src_pitch_offset_cntl : 1;
801 u32 gmc_dst_pitch_offset_cntl : 1;
802 u32 gmc_src_clipping : 1;
803 u32 gmc_dst_clipping : 1;
804 u32 gmc_brush_datatype : 4;
805 u32 gmc_dst_datatype : 4;
806 u32 gmc_src_datatype : 3;
807 u32 gmc_byte_pix_order : 1;
808 u32 gmc_default_sel : 1;
809 u32 gmc_rop3 : 8;
810 u32 gmc_dp_src_source : 3;
811 u32 gmc_clr_cmp_fcn_dis : 1;
812 u32 : 1;
813 u32 gmc_wr_msk_dis : 1;
814 u32 gmc_dp_op : 1;
815} __attribute__((packed));
816
817union dp_gui_master_cntl_u {
818 u32 val : 32;
819 struct dp_gui_master_cntl_t f;
820} __attribute__((packed));
821
822struct rbbm_status_t {
823 u32 cmdfifo_avail : 7;
824 u32 : 1;
825 u32 hirq_on_rbb : 1;
826 u32 cprq_on_rbb : 1;
827 u32 cfrq_on_rbb : 1;
828 u32 hirq_in_rtbuf : 1;
829 u32 cprq_in_rtbuf : 1;
830 u32 cfrq_in_rtbuf : 1;
831 u32 cf_pipe_busy : 1;
832 u32 eng_ev_busy : 1;
833 u32 cp_cmdstrm_busy : 1;
834 u32 e2_busy : 1;
835 u32 rb2d_busy : 1;
836 u32 rb3d_busy : 1;
837 u32 se_busy : 1;
838 u32 re_busy : 1;
839 u32 tam_busy : 1;
840 u32 tdm_busy : 1;
841 u32 pb_busy : 1;
842 u32 : 6;
843 u32 gui_active : 1;
844} __attribute__((packed));
845
846union rbbm_status_u {
847 u32 val : 32;
848 struct rbbm_status_t f;
849} __attribute__((packed));
850
851struct dp_datatype_t {
852 u32 dp_dst_datatype : 4;
853 u32 : 4;
854 u32 dp_brush_datatype : 4;
855 u32 dp_src2_type : 1;
856 u32 dp_src2_datatype : 3;
857 u32 dp_src_datatype : 3;
858 u32 : 11;
859 u32 dp_byte_pix_order : 1;
860 u32 : 1;
861} __attribute__((packed));
862
863union dp_datatype_u {
864 u32 val : 32;
865 struct dp_datatype_t f;
866} __attribute__((packed));
867
868struct dp_mix_t {
869 u32 : 8;
870 u32 dp_src_source : 3;
871 u32 dp_src2_source : 3;
872 u32 : 2;
873 u32 dp_rop3 : 8;
874 u32 dp_op : 1;
875 u32 : 7;
876} __attribute__((packed));
877
878union dp_mix_u {
879 u32 val : 32;
880 struct dp_mix_t f;
881} __attribute__((packed));
882
883struct eng_cntl_t {
884 u32 erc_reg_rd_ws : 1;
885 u32 erc_reg_wr_ws : 1;
886 u32 erc_idle_reg_wr : 1;
887 u32 dis_engine_triggers : 1;
888 u32 dis_rop_src_uses_dst_w_h : 1;
889 u32 dis_src_uses_dst_dirmaj : 1;
890 u32 : 6;
891 u32 force_3dclk_when_2dclk : 1;
892 u32 : 19;
893} __attribute__((packed));
894
895union eng_cntl_u {
896 u32 val : 32;
897 struct eng_cntl_t f;
898} __attribute__((packed));
899
900struct dp_cntl_t {
901 u32 dst_x_dir : 1;
902 u32 dst_y_dir : 1;
903 u32 src_x_dir : 1;
904 u32 src_y_dir : 1;
905 u32 dst_major_x : 1;
906 u32 src_major_x : 1;
907 u32 : 26;
908} __attribute__((packed));
909
910union dp_cntl_u {
911 u32 val : 32;
912 struct dp_cntl_t f;
913} __attribute__((packed));
914
915struct dp_cntl_dst_dir_t {
916 u32 : 15;
917 u32 dst_y_dir : 1;
918 u32 : 15;
919 u32 dst_x_dir : 1;
920} __attribute__((packed));
921
922union dp_cntl_dst_dir_u {
923 u32 val : 32;
924 struct dp_cntl_dst_dir_t f;
925} __attribute__((packed));
926
769#endif 927#endif
770 928