diff options
author | Chris Wilson <chris@chris-wilson.co.uk> | 2011-02-02 07:13:49 -0500 |
---|---|---|
committer | Chris Wilson <chris@chris-wilson.co.uk> | 2011-02-02 10:52:38 -0500 |
commit | 71a77e07d0e33b57d4a50c173e5ce4fabceddbec (patch) | |
tree | 5bc38bd4d4cfcbf28a5ff2cef8a88d22da873037 | |
parent | 5fe49d86f9d01044abf687a8cd21edef636d58aa (diff) |
drm/i915: Invalidate TLB caches on SNB BLT/BSD rings
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: stable@kernel.org
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 26 |
2 files changed, 19 insertions, 11 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5cfc68940f17..15d94c63918c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
@@ -174,7 +174,9 @@ | |||
174 | * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! | 174 | * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! |
175 | */ | 175 | */ |
176 | #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1) | 176 | #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1) |
177 | #define MI_FLUSH_DW MI_INSTR(0x26, 2) /* for GEN6 */ | 177 | #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ |
178 | #define MI_INVALIDATE_TLB (1<<18) | ||
179 | #define MI_INVALIDATE_BSD (1<<7) | ||
178 | #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) | 180 | #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) |
179 | #define MI_BATCH_NON_SECURE (1) | 181 | #define MI_BATCH_NON_SECURE (1) |
180 | #define MI_BATCH_NON_SECURE_I965 (1<<8) | 182 | #define MI_BATCH_NON_SECURE_I965 (1<<8) |
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 6218fa97aa1e..445f27efe677 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c | |||
@@ -1059,22 +1059,25 @@ static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, | |||
1059 | } | 1059 | } |
1060 | 1060 | ||
1061 | static int gen6_ring_flush(struct intel_ring_buffer *ring, | 1061 | static int gen6_ring_flush(struct intel_ring_buffer *ring, |
1062 | u32 invalidate_domains, | 1062 | u32 invalidate, u32 flush) |
1063 | u32 flush_domains) | ||
1064 | { | 1063 | { |
1064 | uint32_t cmd; | ||
1065 | int ret; | 1065 | int ret; |
1066 | 1066 | ||
1067 | if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0) | 1067 | if (((invalidate | flush) & I915_GEM_GPU_DOMAINS) == 0) |
1068 | return 0; | 1068 | return 0; |
1069 | 1069 | ||
1070 | ret = intel_ring_begin(ring, 4); | 1070 | ret = intel_ring_begin(ring, 4); |
1071 | if (ret) | 1071 | if (ret) |
1072 | return ret; | 1072 | return ret; |
1073 | 1073 | ||
1074 | intel_ring_emit(ring, MI_FLUSH_DW); | 1074 | cmd = MI_FLUSH_DW; |
1075 | intel_ring_emit(ring, 0); | 1075 | if (invalidate & I915_GEM_GPU_DOMAINS) |
1076 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; | ||
1077 | intel_ring_emit(ring, cmd); | ||
1076 | intel_ring_emit(ring, 0); | 1078 | intel_ring_emit(ring, 0); |
1077 | intel_ring_emit(ring, 0); | 1079 | intel_ring_emit(ring, 0); |
1080 | intel_ring_emit(ring, MI_NOOP); | ||
1078 | intel_ring_advance(ring); | 1081 | intel_ring_advance(ring); |
1079 | return 0; | 1082 | return 0; |
1080 | } | 1083 | } |
@@ -1230,22 +1233,25 @@ static int blt_ring_begin(struct intel_ring_buffer *ring, | |||
1230 | } | 1233 | } |
1231 | 1234 | ||
1232 | static int blt_ring_flush(struct intel_ring_buffer *ring, | 1235 | static int blt_ring_flush(struct intel_ring_buffer *ring, |
1233 | u32 invalidate_domains, | 1236 | u32 invalidate, u32 flush) |
1234 | u32 flush_domains) | ||
1235 | { | 1237 | { |
1238 | uint32_t cmd; | ||
1236 | int ret; | 1239 | int ret; |
1237 | 1240 | ||
1238 | if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0) | 1241 | if (((invalidate | flush) & I915_GEM_DOMAIN_RENDER) == 0) |
1239 | return 0; | 1242 | return 0; |
1240 | 1243 | ||
1241 | ret = blt_ring_begin(ring, 4); | 1244 | ret = blt_ring_begin(ring, 4); |
1242 | if (ret) | 1245 | if (ret) |
1243 | return ret; | 1246 | return ret; |
1244 | 1247 | ||
1245 | intel_ring_emit(ring, MI_FLUSH_DW); | 1248 | cmd = MI_FLUSH_DW; |
1246 | intel_ring_emit(ring, 0); | 1249 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
1250 | cmd |= MI_INVALIDATE_TLB; | ||
1251 | intel_ring_emit(ring, cmd); | ||
1247 | intel_ring_emit(ring, 0); | 1252 | intel_ring_emit(ring, 0); |
1248 | intel_ring_emit(ring, 0); | 1253 | intel_ring_emit(ring, 0); |
1254 | intel_ring_emit(ring, MI_NOOP); | ||
1249 | intel_ring_advance(ring); | 1255 | intel_ring_advance(ring); |
1250 | return 0; | 1256 | return 0; |
1251 | } | 1257 | } |