Revert "ARM: 6943/1: mm: use TTBR1 instead of reserved context ID"

This reverts commit 52af9c6cd863fe37d1103035ec7ee22ac1296458.

Will Deacon reports that:

 In 52af9c6c ("ARM: 6943/1: mm: use TTBR1 instead of reserved context ID")
 I updated the ASID rollover code to use only the kernel page tables
 whilst updating the ASID.

 Unfortunately, the code to restore the user page tables was part of a
 later patch which isn't yet in mainline, so this leaves the code
 quite broken.

We're also in the process of eliminating __ARCH_WANT_INTERRUPTS_ON_CTXSW
from ARM, so lets revert these until we can properly sort out what we're
doing with the ARM context switching.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

2 files changed, 11 insertions, 10 deletions

diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 8bfae964b133..b6c776ae4039 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -24,7 +24,9 @@ DEFINE_PER_CPU(struct mm_struct *, current_mm);
 
 /*
  * We fork()ed a process, and we need a new context for the child
- * to run in.
+ * to run in.  We reserve version 0 for initial tasks so we will
+ * always allocate an ASID. The ASID 0 is reserved for the TTBR
+ * register changing sequence.
  */
 void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
 {
@@ -34,11 +36,8 @@ void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
 
 static void flush_context(void)
 {
-        u32 ttb;
-        /* Copy TTBR1 into TTBR0 */
-        asm volatile("mrc       p15, 0, %0, c2, c0, 1\n"
-                     "mcr       p15, 0, %0, c2, c0, 0"
-                     : "=r" (ttb));
+        /* set the reserved ASID before flushing the TLB */
+        asm("mcr        p15, 0, %0, c13, c0, 1\n" : : "r" (0));
         isb();
         local_flush_tlb_all();
         if (icache_is_vivt_asid_tagged()) {
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index b3b566ec83d3..3c3867850a30 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -108,16 +108,18 @@ ENTRY(cpu_v7_switch_mm)
 #ifdef CONFIG_ARM_ERRATA_430973
         mcr     p15, 0, r2, c7, c5, 6           @ flush BTAC/BTB
 #endif
-        mrc     p15, 0, r2, c2, c0, 1           @ load TTB 1
-        mcr     p15, 0, r2, c2, c0, 0           @ into TTB 0
+#ifdef CONFIG_ARM_ERRATA_754322
+        dsb
+#endif
+        mcr     p15, 0, r2, c13, c0, 1          @ set reserved context ID
+        isb
+1:      mcr     p15, 0, r0, c2, c0, 0           @ set TTB 0
         isb
 #ifdef CONFIG_ARM_ERRATA_754322
         dsb
 #endif
         mcr     p15, 0, r1, c13, c0, 1          @ set context ID
         isb
-        mcr     p15, 0, r0, c2, c0, 0           @ set TTB 0
-        isb
 #endif
         mov     pc, lr
 ENDPROC(cpu_v7_switch_mm)