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authorJorge Eduardo Candelaria <jedu@slimlogic.co.uk>2011-05-16 19:35:07 -0400
committerLiam Girdwood <lrg@slimlogic.co.uk>2011-05-27 05:49:10 -0400
commita2974732ca7614aaf0baf9d6dd3ad893d50ce1c5 (patch)
tree6af645e033860d67b69eeca47bde4a5b4c71018f
parenta320e3c3d6351814afa5182159df88d2637e0f6f (diff)
TPS65911: Add new irq definitions
TPS65911 adds new interrupt sources, as well as two new registers to handle them, one for interrupt status and one for interrupt masking. The added irqs are: -VMBCH2 - Low and High threshold -GPIO1-8 - Rising and falling edge detection -WTCHDG - Watchdog interrupt -PWRDN - PWRDN reset interrupt The code should handle these new registers only when the chip version is TPS65911. Signed-off-by: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk> Acked-by: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
-rw-r--r--drivers/mfd/tps65910-irq.c57
-rw-r--r--include/linux/mfd/tps65910.h32
2 files changed, 75 insertions, 14 deletions
diff --git a/drivers/mfd/tps65910-irq.c b/drivers/mfd/tps65910-irq.c
index b8435e045f81..2bfad5c86cc7 100644
--- a/drivers/mfd/tps65910-irq.c
+++ b/drivers/mfd/tps65910-irq.c
@@ -41,8 +41,8 @@ static inline int irq_to_tps65910_irq(struct tps65910 *tps65910,
41static irqreturn_t tps65910_irq(int irq, void *irq_data) 41static irqreturn_t tps65910_irq(int irq, void *irq_data)
42{ 42{
43 struct tps65910 *tps65910 = irq_data; 43 struct tps65910 *tps65910 = irq_data;
44 u16 irq_sts; 44 u32 irq_sts;
45 u16 irq_mask; 45 u32 irq_mask;
46 u8 reg; 46 u8 reg;
47 int i; 47 int i;
48 48
@@ -50,18 +50,28 @@ static irqreturn_t tps65910_irq(int irq, void *irq_data)
50 irq_sts = reg; 50 irq_sts = reg;
51 tps65910->read(tps65910, TPS65910_INT_STS2, 1, &reg); 51 tps65910->read(tps65910, TPS65910_INT_STS2, 1, &reg);
52 irq_sts |= reg << 8; 52 irq_sts |= reg << 8;
53 switch (tps65910_chip_id(tps65910)) {
54 case TPS65911:
55 tps65910->read(tps65910, TPS65910_INT_STS3, 1, &reg);
56 irq_sts |= reg << 16;
57 }
53 58
54 tps65910->read(tps65910, TPS65910_INT_MSK, 1, &reg); 59 tps65910->read(tps65910, TPS65910_INT_MSK, 1, &reg);
55 irq_mask = reg; 60 irq_mask = reg;
56 tps65910->read(tps65910, TPS65910_INT_MSK2, 1, &reg); 61 tps65910->read(tps65910, TPS65910_INT_MSK2, 1, &reg);
57 irq_mask |= reg << 8; 62 irq_mask |= reg << 8;
63 switch (tps65910_chip_id(tps65910)) {
64 case TPS65911:
65 tps65910->read(tps65910, TPS65910_INT_MSK3, 1, &reg);
66 irq_mask |= reg << 16;
67 }
58 68
59 irq_sts &= ~irq_mask; 69 irq_sts &= ~irq_mask;
60 70
61 if (!irq_sts) 71 if (!irq_sts)
62 return IRQ_NONE; 72 return IRQ_NONE;
63 73
64 for (i = 0; i < TPS65910_NUM_IRQ; i++) { 74 for (i = 0; i < tps65910->irq_num; i++) {
65 75
66 if (!(irq_sts & (1 << i))) 76 if (!(irq_sts & (1 << i)))
67 continue; 77 continue;
@@ -71,9 +81,15 @@ static irqreturn_t tps65910_irq(int irq, void *irq_data)
71 81
72 /* Write the STS register back to clear IRQs we handled */ 82 /* Write the STS register back to clear IRQs we handled */
73 reg = irq_sts & 0xFF; 83 reg = irq_sts & 0xFF;
84 irq_sts >>= 8;
74 tps65910->write(tps65910, TPS65910_INT_STS, 1, &reg); 85 tps65910->write(tps65910, TPS65910_INT_STS, 1, &reg);
75 reg = irq_sts >> 8; 86 reg = irq_sts & 0xFF;
76 tps65910->write(tps65910, TPS65910_INT_STS2, 1, &reg); 87 tps65910->write(tps65910, TPS65910_INT_STS2, 1, &reg);
88 switch (tps65910_chip_id(tps65910)) {
89 case TPS65911:
90 reg = irq_sts >> 8;
91 tps65910->write(tps65910, TPS65910_INT_STS3, 1, &reg);
92 }
77 93
78 return IRQ_HANDLED; 94 return IRQ_HANDLED;
79} 95}
@@ -88,19 +104,29 @@ static void tps65910_irq_lock(struct irq_data *data)
88static void tps65910_irq_sync_unlock(struct irq_data *data) 104static void tps65910_irq_sync_unlock(struct irq_data *data)
89{ 105{
90 struct tps65910 *tps65910 = irq_data_get_irq_chip_data(data); 106 struct tps65910 *tps65910 = irq_data_get_irq_chip_data(data);
91 u16 reg_mask; 107 u32 reg_mask;
92 u8 reg; 108 u8 reg;
93 109
94 tps65910->read(tps65910, TPS65910_INT_MSK, 1, &reg); 110 tps65910->read(tps65910, TPS65910_INT_MSK, 1, &reg);
95 reg_mask = reg; 111 reg_mask = reg;
96 tps65910->read(tps65910, TPS65910_INT_MSK2, 1, &reg); 112 tps65910->read(tps65910, TPS65910_INT_MSK2, 1, &reg);
97 reg_mask |= reg << 8; 113 reg_mask |= reg << 8;
114 switch (tps65910_chip_id(tps65910)) {
115 case TPS65911:
116 tps65910->read(tps65910, TPS65910_INT_MSK3, 1, &reg);
117 reg_mask |= reg << 16;
118 }
98 119
99 if (tps65910->irq_mask != reg_mask) { 120 if (tps65910->irq_mask != reg_mask) {
100 reg = tps65910->irq_mask & 0xFF; 121 reg = tps65910->irq_mask & 0xFF;
101 tps65910->write(tps65910, TPS65910_INT_MSK, 1, &reg); 122 tps65910->write(tps65910, TPS65910_INT_MSK, 1, &reg);
102 reg = tps65910->irq_mask >> 8; 123 reg = tps65910->irq_mask >> 8 & 0xFF;
103 tps65910->write(tps65910, TPS65910_INT_MSK2, 1, &reg); 124 tps65910->write(tps65910, TPS65910_INT_MSK2, 1, &reg);
125 switch (tps65910_chip_id(tps65910)) {
126 case TPS65911:
127 reg = tps65910->irq_mask >> 16;
128 tps65910->write(tps65910, TPS65910_INT_MSK3, 1, &reg);
129 }
104 } 130 }
105 mutex_unlock(&tps65910->irq_lock); 131 mutex_unlock(&tps65910->irq_lock);
106} 132}
@@ -132,7 +158,6 @@ int tps65910_irq_init(struct tps65910 *tps65910, int irq,
132{ 158{
133 int ret, cur_irq; 159 int ret, cur_irq;
134 int flags = IRQF_ONESHOT; 160 int flags = IRQF_ONESHOT;
135 u8 reg;
136 161
137 if (!irq) { 162 if (!irq) {
138 dev_warn(tps65910->dev, "No interrupt support, no core IRQ\n"); 163 dev_warn(tps65910->dev, "No interrupt support, no core IRQ\n");
@@ -144,19 +169,22 @@ int tps65910_irq_init(struct tps65910 *tps65910, int irq,
144 return -EINVAL; 169 return -EINVAL;
145 } 170 }
146 171
147 /* Mask top level interrupts */ 172 tps65910->irq_mask = 0xFFFFFF;
148 reg = 0xFF;
149 tps65910->write(tps65910, TPS65910_INT_MSK, 1, &reg);
150 reg = 0x03;
151 tps65910->write(tps65910, TPS65910_INT_MSK2, 1, &reg);
152 173
153 mutex_init(&tps65910->irq_lock); 174 mutex_init(&tps65910->irq_lock);
154 tps65910->chip_irq = irq; 175 tps65910->chip_irq = irq;
155 tps65910->irq_base = pdata->irq_base; 176 tps65910->irq_base = pdata->irq_base;
156 177
178 switch (tps65910_chip_id(tps65910)) {
179 case TPS65910:
180 tps65910->irq_num = TPS65910_NUM_IRQ;
181 case TPS65911:
182 tps65910->irq_num = TPS65911_NUM_IRQ;
183 }
184
157 /* Register with genirq */ 185 /* Register with genirq */
158 for (cur_irq = tps65910->irq_base; 186 for (cur_irq = tps65910->irq_base;
159 cur_irq < TPS65910_NUM_IRQ + tps65910->irq_base; 187 cur_irq < tps65910->irq_num + tps65910->irq_base;
160 cur_irq++) { 188 cur_irq++) {
161 irq_set_chip_data(cur_irq, tps65910); 189 irq_set_chip_data(cur_irq, tps65910);
162 irq_set_chip_and_handler(cur_irq, &tps65910_irq_chip, 190 irq_set_chip_and_handler(cur_irq, &tps65910_irq_chip,
@@ -174,6 +202,9 @@ int tps65910_irq_init(struct tps65910 *tps65910, int irq,
174 202
175 ret = request_threaded_irq(irq, NULL, tps65910_irq, flags, 203 ret = request_threaded_irq(irq, NULL, tps65910_irq, flags,
176 "tps65910", tps65910); 204 "tps65910", tps65910);
205
206 irq_set_irq_type(irq, IRQ_TYPE_LEVEL_LOW);
207
177 if (ret != 0) 208 if (ret != 0)
178 dev_err(tps65910->dev, "Failed to request IRQ: %d\n", ret); 209 dev_err(tps65910->dev, "Failed to request IRQ: %d\n", ret);
179 210
diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h
index 20359e669ae7..32bb7b81f713 100644
--- a/include/linux/mfd/tps65910.h
+++ b/include/linux/mfd/tps65910.h
@@ -763,6 +763,35 @@
763#define TPS65910_IRQ_GPIO_F 9 763#define TPS65910_IRQ_GPIO_F 9
764#define TPS65910_NUM_IRQ 10 764#define TPS65910_NUM_IRQ 10
765 765
766#define TPS65911_IRQ_VBAT_VMBDCH 0
767#define TPS65911_IRQ_VBAT_VMBDCH2L 1
768#define TPS65911_IRQ_VBAT_VMBDCH2H 2
769#define TPS65911_IRQ_VBAT_VMHI 3
770#define TPS65911_IRQ_PWRON 4
771#define TPS65911_IRQ_PWRON_LP 5
772#define TPS65911_IRQ_PWRHOLD_F 6
773#define TPS65911_IRQ_PWRHOLD_R 7
774#define TPS65911_IRQ_HOTDIE 8
775#define TPS65911_IRQ_RTC_ALARM 9
776#define TPS65911_IRQ_RTC_PERIOD 10
777#define TPS65911_IRQ_GPIO0_R 11
778#define TPS65911_IRQ_GPIO0_F 12
779#define TPS65911_IRQ_GPIO1_R 13
780#define TPS65911_IRQ_GPIO1_F 14
781#define TPS65911_IRQ_GPIO2_R 15
782#define TPS65911_IRQ_GPIO2_F 16
783#define TPS65911_IRQ_GPIO3_R 17
784#define TPS65911_IRQ_GPIO3_F 18
785#define TPS65911_IRQ_GPIO4_R 19
786#define TPS65911_IRQ_GPIO4_F 20
787#define TPS65911_IRQ_GPIO5_R 21
788#define TPS65911_IRQ_GPIO5_F 22
789#define TPS65911_IRQ_WTCHDG 23
790#define TPS65911_IRQ_PWRDN 24
791
792#define TPS65911_NUM_IRQ 25
793
794
766/* GPIO Register Definitions */ 795/* GPIO Register Definitions */
767#define TPS65910_GPIO_DEB BIT(2) 796#define TPS65910_GPIO_DEB BIT(2)
768#define TPS65910_GPIO_PUEN BIT(3) 797#define TPS65910_GPIO_PUEN BIT(3)
@@ -806,7 +835,8 @@ struct tps65910 {
806 struct mutex irq_lock; 835 struct mutex irq_lock;
807 int chip_irq; 836 int chip_irq;
808 int irq_base; 837 int irq_base;
809 u16 irq_mask; 838 int irq_num;
839 u32 irq_mask;
810}; 840};
811 841
812struct tps65910_platform_data { 842struct tps65910_platform_data {