diff options
author | Jeff Kirsher <jeffrey.t.kirsher@intel.com> | 2010-12-01 14:59:50 -0500 |
---|---|---|
committer | Jeff Kirsher <jeffrey.t.kirsher@intel.com> | 2010-12-11 01:12:32 -0500 |
commit | 667445008db3f45a760c235d771be0c9671e59e5 (patch) | |
tree | 6b6fea62bfcfeb78a6deeb851b70c8eda0700c17 | |
parent | 19a0b67afd174c4db261d587b5c67704dcd53c17 (diff) |
Intel Wired LAN drivers: Use static const
Based on work by Joe Perches <joe@perches.com>
Using static const to decrease data and overall object size.
CC: Joe Perches <joe@perches.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Tested-by: Emil Tantilov <emil.s.tantilov@intel.com>
-rw-r--r-- | drivers/net/e1000/e1000_hw.c | 20 | ||||
-rw-r--r-- | drivers/net/e1000/e1000_param.c | 13 | ||||
-rw-r--r-- | drivers/net/e1000e/phy.c | 11 | ||||
-rw-r--r-- | drivers/net/igb/e1000_phy.c | 11 | ||||
-rw-r--r-- | drivers/net/ixgb/ixgb_param.c | 21 | ||||
-rw-r--r-- | drivers/net/ixgbe/ixgbe_ethtool.c | 24 | ||||
-rw-r--r-- | drivers/net/ixgbevf/ethtool.c | 18 |
7 files changed, 65 insertions, 53 deletions
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c index c7e242b69a18..77d08e697b74 100644 --- a/drivers/net/e1000/e1000_hw.c +++ b/drivers/net/e1000/e1000_hw.c | |||
@@ -4892,11 +4892,11 @@ static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, | |||
4892 | } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ | 4892 | } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ |
4893 | u16 cur_agc_value; | 4893 | u16 cur_agc_value; |
4894 | u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; | 4894 | u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; |
4895 | u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = | 4895 | static const u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = { |
4896 | { IGP01E1000_PHY_AGC_A, | 4896 | IGP01E1000_PHY_AGC_A, |
4897 | IGP01E1000_PHY_AGC_B, | 4897 | IGP01E1000_PHY_AGC_B, |
4898 | IGP01E1000_PHY_AGC_C, | 4898 | IGP01E1000_PHY_AGC_C, |
4899 | IGP01E1000_PHY_AGC_D | 4899 | IGP01E1000_PHY_AGC_D |
4900 | }; | 4900 | }; |
4901 | /* Read the AGC registers for all channels */ | 4901 | /* Read the AGC registers for all channels */ |
4902 | for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { | 4902 | for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { |
@@ -5071,11 +5071,11 @@ static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up) | |||
5071 | { | 5071 | { |
5072 | s32 ret_val; | 5072 | s32 ret_val; |
5073 | u16 phy_data, phy_saved_data, speed, duplex, i; | 5073 | u16 phy_data, phy_saved_data, speed, duplex, i; |
5074 | u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = | 5074 | static const u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = { |
5075 | { IGP01E1000_PHY_AGC_PARAM_A, | 5075 | IGP01E1000_PHY_AGC_PARAM_A, |
5076 | IGP01E1000_PHY_AGC_PARAM_B, | 5076 | IGP01E1000_PHY_AGC_PARAM_B, |
5077 | IGP01E1000_PHY_AGC_PARAM_C, | 5077 | IGP01E1000_PHY_AGC_PARAM_C, |
5078 | IGP01E1000_PHY_AGC_PARAM_D | 5078 | IGP01E1000_PHY_AGC_PARAM_D |
5079 | }; | 5079 | }; |
5080 | u16 min_length, max_length; | 5080 | u16 min_length, max_length; |
5081 | 5081 | ||
diff --git a/drivers/net/e1000/e1000_param.c b/drivers/net/e1000/e1000_param.c index 10d8d98bb797..1301eba8b57a 100644 --- a/drivers/net/e1000/e1000_param.c +++ b/drivers/net/e1000/e1000_param.c | |||
@@ -352,12 +352,13 @@ void __devinit e1000_check_options(struct e1000_adapter *adapter) | |||
352 | } | 352 | } |
353 | { /* Flow Control */ | 353 | { /* Flow Control */ |
354 | 354 | ||
355 | struct e1000_opt_list fc_list[] = | 355 | static const struct e1000_opt_list fc_list[] = { |
356 | {{ E1000_FC_NONE, "Flow Control Disabled" }, | 356 | { E1000_FC_NONE, "Flow Control Disabled" }, |
357 | { E1000_FC_RX_PAUSE,"Flow Control Receive Only" }, | 357 | { E1000_FC_RX_PAUSE, "Flow Control Receive Only" }, |
358 | { E1000_FC_TX_PAUSE,"Flow Control Transmit Only" }, | 358 | { E1000_FC_TX_PAUSE, "Flow Control Transmit Only" }, |
359 | { E1000_FC_FULL, "Flow Control Enabled" }, | 359 | { E1000_FC_FULL, "Flow Control Enabled" }, |
360 | { E1000_FC_DEFAULT, "Flow Control Hardware Default" }}; | 360 | { E1000_FC_DEFAULT, "Flow Control Hardware Default" } |
361 | }; | ||
361 | 362 | ||
362 | opt = (struct e1000_option) { | 363 | opt = (struct e1000_option) { |
363 | .type = list_option, | 364 | .type = list_option, |
diff --git a/drivers/net/e1000e/phy.c b/drivers/net/e1000e/phy.c index 3d3dc0c82355..6ad90ccb4bab 100644 --- a/drivers/net/e1000e/phy.c +++ b/drivers/net/e1000e/phy.c | |||
@@ -1840,11 +1840,12 @@ s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw) | |||
1840 | u16 phy_data, i, agc_value = 0; | 1840 | u16 phy_data, i, agc_value = 0; |
1841 | u16 cur_agc_index, max_agc_index = 0; | 1841 | u16 cur_agc_index, max_agc_index = 0; |
1842 | u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; | 1842 | u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; |
1843 | u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = | 1843 | static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { |
1844 | {IGP02E1000_PHY_AGC_A, | 1844 | IGP02E1000_PHY_AGC_A, |
1845 | IGP02E1000_PHY_AGC_B, | 1845 | IGP02E1000_PHY_AGC_B, |
1846 | IGP02E1000_PHY_AGC_C, | 1846 | IGP02E1000_PHY_AGC_C, |
1847 | IGP02E1000_PHY_AGC_D}; | 1847 | IGP02E1000_PHY_AGC_D |
1848 | }; | ||
1848 | 1849 | ||
1849 | /* Read the AGC registers for all channels */ | 1850 | /* Read the AGC registers for all channels */ |
1850 | for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { | 1851 | for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { |
diff --git a/drivers/net/igb/e1000_phy.c b/drivers/net/igb/e1000_phy.c index ddd036a78999..6694bf3e5ad9 100644 --- a/drivers/net/igb/e1000_phy.c +++ b/drivers/net/igb/e1000_phy.c | |||
@@ -1757,11 +1757,12 @@ s32 igb_get_cable_length_igp_2(struct e1000_hw *hw) | |||
1757 | u16 phy_data, i, agc_value = 0; | 1757 | u16 phy_data, i, agc_value = 0; |
1758 | u16 cur_agc_index, max_agc_index = 0; | 1758 | u16 cur_agc_index, max_agc_index = 0; |
1759 | u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; | 1759 | u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; |
1760 | u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = | 1760 | static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { |
1761 | {IGP02E1000_PHY_AGC_A, | 1761 | IGP02E1000_PHY_AGC_A, |
1762 | IGP02E1000_PHY_AGC_B, | 1762 | IGP02E1000_PHY_AGC_B, |
1763 | IGP02E1000_PHY_AGC_C, | 1763 | IGP02E1000_PHY_AGC_C, |
1764 | IGP02E1000_PHY_AGC_D}; | 1764 | IGP02E1000_PHY_AGC_D |
1765 | }; | ||
1765 | 1766 | ||
1766 | /* Read the AGC registers for all channels */ | 1767 | /* Read the AGC registers for all channels */ |
1767 | for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { | 1768 | for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { |
diff --git a/drivers/net/ixgb/ixgb_param.c b/drivers/net/ixgb/ixgb_param.c index 88a08f056241..dd7fbeb1f7d1 100644 --- a/drivers/net/ixgb/ixgb_param.c +++ b/drivers/net/ixgb/ixgb_param.c | |||
@@ -191,9 +191,9 @@ struct ixgb_option { | |||
191 | } r; | 191 | } r; |
192 | struct { /* list_option info */ | 192 | struct { /* list_option info */ |
193 | int nr; | 193 | int nr; |
194 | struct ixgb_opt_list { | 194 | const struct ixgb_opt_list { |
195 | int i; | 195 | int i; |
196 | char *str; | 196 | const char *str; |
197 | } *p; | 197 | } *p; |
198 | } l; | 198 | } l; |
199 | } arg; | 199 | } arg; |
@@ -226,7 +226,7 @@ ixgb_validate_option(unsigned int *value, const struct ixgb_option *opt) | |||
226 | break; | 226 | break; |
227 | case list_option: { | 227 | case list_option: { |
228 | int i; | 228 | int i; |
229 | struct ixgb_opt_list *ent; | 229 | const struct ixgb_opt_list *ent; |
230 | 230 | ||
231 | for (i = 0; i < opt->arg.l.nr; i++) { | 231 | for (i = 0; i < opt->arg.l.nr; i++) { |
232 | ent = &opt->arg.l.p[i]; | 232 | ent = &opt->arg.l.p[i]; |
@@ -322,14 +322,15 @@ ixgb_check_options(struct ixgb_adapter *adapter) | |||
322 | } | 322 | } |
323 | { /* Flow Control */ | 323 | { /* Flow Control */ |
324 | 324 | ||
325 | struct ixgb_opt_list fc_list[] = | 325 | static const struct ixgb_opt_list fc_list[] = { |
326 | {{ ixgb_fc_none, "Flow Control Disabled" }, | 326 | { ixgb_fc_none, "Flow Control Disabled" }, |
327 | { ixgb_fc_rx_pause,"Flow Control Receive Only" }, | 327 | { ixgb_fc_rx_pause, "Flow Control Receive Only" }, |
328 | { ixgb_fc_tx_pause,"Flow Control Transmit Only" }, | 328 | { ixgb_fc_tx_pause, "Flow Control Transmit Only" }, |
329 | { ixgb_fc_full, "Flow Control Enabled" }, | 329 | { ixgb_fc_full, "Flow Control Enabled" }, |
330 | { ixgb_fc_default, "Flow Control Hardware Default" }}; | 330 | { ixgb_fc_default, "Flow Control Hardware Default" } |
331 | }; | ||
331 | 332 | ||
332 | const struct ixgb_option opt = { | 333 | static const struct ixgb_option opt = { |
333 | .type = list_option, | 334 | .type = list_option, |
334 | .name = "Flow Control", | 335 | .name = "Flow Control", |
335 | .err = "reading default settings from EEPROM", | 336 | .err = "reading default settings from EEPROM", |
diff --git a/drivers/net/ixgbe/ixgbe_ethtool.c b/drivers/net/ixgbe/ixgbe_ethtool.c index ef3f9105a05d..90a740d77e5d 100644 --- a/drivers/net/ixgbe/ixgbe_ethtool.c +++ b/drivers/net/ixgbe/ixgbe_ethtool.c | |||
@@ -1157,7 +1157,7 @@ struct ixgbe_reg_test { | |||
1157 | #define TABLE64_TEST_HI 6 | 1157 | #define TABLE64_TEST_HI 6 |
1158 | 1158 | ||
1159 | /* default 82599 register test */ | 1159 | /* default 82599 register test */ |
1160 | static struct ixgbe_reg_test reg_test_82599[] = { | 1160 | static const struct ixgbe_reg_test reg_test_82599[] = { |
1161 | { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, | 1161 | { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, |
1162 | { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, | 1162 | { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, |
1163 | { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | 1163 | { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, |
@@ -1181,7 +1181,7 @@ static struct ixgbe_reg_test reg_test_82599[] = { | |||
1181 | }; | 1181 | }; |
1182 | 1182 | ||
1183 | /* default 82598 register test */ | 1183 | /* default 82598 register test */ |
1184 | static struct ixgbe_reg_test reg_test_82598[] = { | 1184 | static const struct ixgbe_reg_test reg_test_82598[] = { |
1185 | { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, | 1185 | { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, |
1186 | { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, | 1186 | { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, |
1187 | { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | 1187 | { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, |
@@ -1208,18 +1208,22 @@ static struct ixgbe_reg_test reg_test_82598[] = { | |||
1208 | { 0, 0, 0, 0 } | 1208 | { 0, 0, 0, 0 } |
1209 | }; | 1209 | }; |
1210 | 1210 | ||
1211 | static const u32 register_test_patterns[] = { | ||
1212 | 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF | ||
1213 | }; | ||
1214 | |||
1211 | #define REG_PATTERN_TEST(R, M, W) \ | 1215 | #define REG_PATTERN_TEST(R, M, W) \ |
1212 | { \ | 1216 | { \ |
1213 | u32 pat, val, before; \ | 1217 | u32 pat, val, before; \ |
1214 | const u32 _test[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \ | 1218 | for (pat = 0; pat < ARRAY_SIZE(register_test_patterns); pat++) { \ |
1215 | for (pat = 0; pat < ARRAY_SIZE(_test); pat++) { \ | ||
1216 | before = readl(adapter->hw.hw_addr + R); \ | 1219 | before = readl(adapter->hw.hw_addr + R); \ |
1217 | writel((_test[pat] & W), (adapter->hw.hw_addr + R)); \ | 1220 | writel((register_test_patterns[pat] & W), \ |
1221 | (adapter->hw.hw_addr + R)); \ | ||
1218 | val = readl(adapter->hw.hw_addr + R); \ | 1222 | val = readl(adapter->hw.hw_addr + R); \ |
1219 | if (val != (_test[pat] & W & M)) { \ | 1223 | if (val != (register_test_patterns[pat] & W & M)) { \ |
1220 | e_err(drv, "pattern test reg %04X failed: got " \ | 1224 | e_err(drv, "pattern test reg %04X failed: got " \ |
1221 | "0x%08X expected 0x%08X\n", \ | 1225 | "0x%08X expected 0x%08X\n", \ |
1222 | R, val, (_test[pat] & W & M)); \ | 1226 | R, val, (register_test_patterns[pat] & W & M)); \ |
1223 | *data = R; \ | 1227 | *data = R; \ |
1224 | writel(before, adapter->hw.hw_addr + R); \ | 1228 | writel(before, adapter->hw.hw_addr + R); \ |
1225 | return 1; \ | 1229 | return 1; \ |
@@ -1246,7 +1250,7 @@ static struct ixgbe_reg_test reg_test_82598[] = { | |||
1246 | 1250 | ||
1247 | static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data) | 1251 | static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data) |
1248 | { | 1252 | { |
1249 | struct ixgbe_reg_test *test; | 1253 | const struct ixgbe_reg_test *test; |
1250 | u32 value, before, after; | 1254 | u32 value, before, after; |
1251 | u32 i, toggle; | 1255 | u32 i, toggle; |
1252 | 1256 | ||
diff --git a/drivers/net/ixgbevf/ethtool.c b/drivers/net/ixgbevf/ethtool.c index 4cc817acfb62..fa29b3c8c464 100644 --- a/drivers/net/ixgbevf/ethtool.c +++ b/drivers/net/ixgbevf/ethtool.c | |||
@@ -544,7 +544,7 @@ struct ixgbevf_reg_test { | |||
544 | #define TABLE64_TEST_HI 6 | 544 | #define TABLE64_TEST_HI 6 |
545 | 545 | ||
546 | /* default VF register test */ | 546 | /* default VF register test */ |
547 | static struct ixgbevf_reg_test reg_test_vf[] = { | 547 | static const struct ixgbevf_reg_test reg_test_vf[] = { |
548 | { IXGBE_VFRDBAL(0), 2, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 }, | 548 | { IXGBE_VFRDBAL(0), 2, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 }, |
549 | { IXGBE_VFRDBAH(0), 2, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | 549 | { IXGBE_VFRDBAH(0), 2, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, |
550 | { IXGBE_VFRDLEN(0), 2, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, | 550 | { IXGBE_VFRDLEN(0), 2, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, |
@@ -557,19 +557,23 @@ static struct ixgbevf_reg_test reg_test_vf[] = { | |||
557 | { 0, 0, 0, 0 } | 557 | { 0, 0, 0, 0 } |
558 | }; | 558 | }; |
559 | 559 | ||
560 | static const u32 register_test_patterns[] = { | ||
561 | 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF | ||
562 | }; | ||
563 | |||
560 | #define REG_PATTERN_TEST(R, M, W) \ | 564 | #define REG_PATTERN_TEST(R, M, W) \ |
561 | { \ | 565 | { \ |
562 | u32 pat, val, before; \ | 566 | u32 pat, val, before; \ |
563 | const u32 _test[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \ | 567 | for (pat = 0; pat < ARRAY_SIZE(register_test_patterns); pat++) { \ |
564 | for (pat = 0; pat < ARRAY_SIZE(_test); pat++) { \ | ||
565 | before = readl(adapter->hw.hw_addr + R); \ | 568 | before = readl(adapter->hw.hw_addr + R); \ |
566 | writel((_test[pat] & W), (adapter->hw.hw_addr + R)); \ | 569 | writel((register_test_patterns[pat] & W), \ |
570 | (adapter->hw.hw_addr + R)); \ | ||
567 | val = readl(adapter->hw.hw_addr + R); \ | 571 | val = readl(adapter->hw.hw_addr + R); \ |
568 | if (val != (_test[pat] & W & M)) { \ | 572 | if (val != (register_test_patterns[pat] & W & M)) { \ |
569 | hw_dbg(&adapter->hw, \ | 573 | hw_dbg(&adapter->hw, \ |
570 | "pattern test reg %04X failed: got " \ | 574 | "pattern test reg %04X failed: got " \ |
571 | "0x%08X expected 0x%08X\n", \ | 575 | "0x%08X expected 0x%08X\n", \ |
572 | R, val, (_test[pat] & W & M)); \ | 576 | R, val, (register_test_patterns[pat] & W & M)); \ |
573 | *data = R; \ | 577 | *data = R; \ |
574 | writel(before, adapter->hw.hw_addr + R); \ | 578 | writel(before, adapter->hw.hw_addr + R); \ |
575 | return 1; \ | 579 | return 1; \ |
@@ -596,7 +600,7 @@ static struct ixgbevf_reg_test reg_test_vf[] = { | |||
596 | 600 | ||
597 | static int ixgbevf_reg_test(struct ixgbevf_adapter *adapter, u64 *data) | 601 | static int ixgbevf_reg_test(struct ixgbevf_adapter *adapter, u64 *data) |
598 | { | 602 | { |
599 | struct ixgbevf_reg_test *test; | 603 | const struct ixgbevf_reg_test *test; |
600 | u32 i; | 604 | u32 i; |
601 | 605 | ||
602 | test = reg_test_vf; | 606 | test = reg_test_vf; |