diff options
author | Sergei Shtylyov <sshtylyov@ru.mvista.com> | 2007-07-09 17:17:55 -0400 |
---|---|---|
committer | Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> | 2007-07-09 17:17:55 -0400 |
commit | 83a6d4ab3b09c0c1921b657bbaac5ada3c9c3623 (patch) | |
tree | 21f86005466a0c9f87f60e13ffc3e7135e24818e | |
parent | 2648e5d9a80d8a020feb343c52a8704e978e60c6 (diff) |
cmd64x: init. code cleanup
Fix two minor issues with PCI0646 chip reporting in the init_chipset() method:
"IRQ workaround enabled" message printed out not only for revision 0x01 and
"CMD646: chipset revision" printed twice (by IDE core and the driver itself).
Also, remove empty/pointless switch cases for the chips other than PCI0646,
duplicate write to the MRDMODE register when enabling interrupts and MEMORY
READ LINE cycles, and needless/misplaced initialization of the timing registers
in this method.
Switch to reading only the PCI revision ID register itself, not the whole 32
bits at its address in init_chipset() and init_hwif() methods; in addition,
get rid of the useless clearing of hwif->autodma and perform some cosmetic
style changes in the latter method.
Refactor ata66_cmd64x() by moving all the code into the 'switch' statement,
renaming/adding variables, and fixing the coding style.
While at it, finally get rid of the meaningless aliasing register #define's...
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
-rw-r--r-- | drivers/ide/pci/cmd64x.c | 126 |
1 files changed, 45 insertions, 81 deletions
diff --git a/drivers/ide/pci/cmd64x.c b/drivers/ide/pci/cmd64x.c index 7c57dc696f52..b0aa7d03b8a5 100644 --- a/drivers/ide/pci/cmd64x.c +++ b/drivers/ide/pci/cmd64x.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * linux/drivers/ide/pci/cmd64x.c Version 1.47 Mar 19, 2007 | 2 | * linux/drivers/ide/pci/cmd64x.c Version 1.50 May 10, 2007 |
3 | * | 3 | * |
4 | * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines. | 4 | * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines. |
5 | * Due to massive hardware bugs, UltraDMA is only supported | 5 | * Due to massive hardware bugs, UltraDMA is only supported |
@@ -52,9 +52,6 @@ | |||
52 | #define ARTTIM23_DIS_RA2 0x04 | 52 | #define ARTTIM23_DIS_RA2 0x04 |
53 | #define ARTTIM23_DIS_RA3 0x08 | 53 | #define ARTTIM23_DIS_RA3 0x08 |
54 | #define ARTTIM23_INTR_CH1 0x10 | 54 | #define ARTTIM23_INTR_CH1 0x10 |
55 | #define ARTTIM2 0x57 | ||
56 | #define ARTTIM3 0x57 | ||
57 | #define DRWTIM23 0x58 | ||
58 | #define DRWTIM2 0x58 | 55 | #define DRWTIM2 0x58 |
59 | #define BRST 0x59 | 56 | #define BRST 0x59 |
60 | #define DRWTIM3 0x5b | 57 | #define DRWTIM3 0x5b |
@@ -469,71 +466,43 @@ static int cmd646_1_ide_dma_end (ide_drive_t *drive) | |||
469 | 466 | ||
470 | static unsigned int __devinit init_chipset_cmd64x(struct pci_dev *dev, const char *name) | 467 | static unsigned int __devinit init_chipset_cmd64x(struct pci_dev *dev, const char *name) |
471 | { | 468 | { |
472 | u32 class_rev = 0; | ||
473 | u8 mrdmode = 0; | 469 | u8 mrdmode = 0; |
474 | 470 | ||
475 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); | 471 | if (dev->device == PCI_DEVICE_ID_CMD_646) { |
476 | class_rev &= 0xff; | 472 | u8 rev = 0; |
477 | 473 | ||
478 | switch(dev->device) { | 474 | pci_read_config_byte(dev, PCI_REVISION_ID, &rev); |
479 | case PCI_DEVICE_ID_CMD_643: | 475 | |
480 | break; | 476 | switch (rev) { |
481 | case PCI_DEVICE_ID_CMD_646: | 477 | case 0x07: |
482 | printk(KERN_INFO "%s: chipset revision 0x%02X, ", name, class_rev); | 478 | case 0x05: |
483 | switch(class_rev) { | 479 | printk("%s: UltraDMA capable", name); |
484 | case 0x07: | ||
485 | case 0x05: | ||
486 | printk("UltraDMA Capable"); | ||
487 | break; | ||
488 | case 0x03: | ||
489 | printk("MultiWord DMA Force Limited"); | ||
490 | break; | ||
491 | case 0x01: | ||
492 | default: | ||
493 | printk("MultiWord DMA Limited, IRQ workaround enabled"); | ||
494 | break; | ||
495 | } | ||
496 | printk("\n"); | ||
497 | break; | ||
498 | case PCI_DEVICE_ID_CMD_648: | ||
499 | case PCI_DEVICE_ID_CMD_649: | ||
500 | break; | 480 | break; |
481 | case 0x03: | ||
501 | default: | 482 | default: |
483 | printk("%s: MultiWord DMA force limited", name); | ||
484 | break; | ||
485 | case 0x01: | ||
486 | printk("%s: MultiWord DMA limited, " | ||
487 | "IRQ workaround enabled\n", name); | ||
502 | break; | 488 | break; |
489 | } | ||
503 | } | 490 | } |
504 | 491 | ||
505 | /* Set a good latency timer and cache line size value. */ | 492 | /* Set a good latency timer and cache line size value. */ |
506 | (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); | 493 | (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); |
507 | /* FIXME: pci_set_master() to ensure a good latency timer value */ | 494 | /* FIXME: pci_set_master() to ensure a good latency timer value */ |
508 | 495 | ||
509 | /* Setup interrupts. */ | 496 | /* |
510 | (void) pci_read_config_byte(dev, MRDMODE, &mrdmode); | 497 | * Enable interrupts, select MEMORY READ LINE for reads. |
511 | mrdmode &= ~(0x30); | 498 | * |
512 | (void) pci_write_config_byte(dev, MRDMODE, mrdmode); | 499 | * NOTE: although not mentioned in the PCI0646U specs, |
513 | 500 | * bits 0-1 are write only and won't be read back as | |
514 | /* Use MEMORY READ LINE for reads. | 501 | * set or not -- PCI0646U2 specs clarify this point. |
515 | * NOTE: Although not mentioned in the PCI0646U specs, | ||
516 | * these bits are write only and won't be read | ||
517 | * back as set or not. The PCI0646U2 specs clarify | ||
518 | * this point. | ||
519 | */ | 502 | */ |
520 | (void) pci_write_config_byte(dev, MRDMODE, mrdmode | 0x02); | 503 | (void) pci_read_config_byte (dev, MRDMODE, &mrdmode); |
521 | 504 | mrdmode &= ~0x30; | |
522 | /* Set reasonable active/recovery/address-setup values. */ | 505 | (void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02)); |
523 | (void) pci_write_config_byte(dev, ARTTIM0, 0x40); | ||
524 | (void) pci_write_config_byte(dev, DRWTIM0, 0x3f); | ||
525 | (void) pci_write_config_byte(dev, ARTTIM1, 0x40); | ||
526 | (void) pci_write_config_byte(dev, DRWTIM1, 0x3f); | ||
527 | #ifdef __i386__ | ||
528 | (void) pci_write_config_byte(dev, ARTTIM23, 0x1c); | ||
529 | #else | ||
530 | (void) pci_write_config_byte(dev, ARTTIM23, 0x5c); | ||
531 | #endif | ||
532 | (void) pci_write_config_byte(dev, DRWTIM23, 0x3f); | ||
533 | (void) pci_write_config_byte(dev, DRWTIM3, 0x3f); | ||
534 | #ifdef CONFIG_PPC | ||
535 | (void) pci_write_config_byte(dev, UDIDETCR0, 0xf0); | ||
536 | #endif /* CONFIG_PPC */ | ||
537 | 506 | ||
538 | #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS) | 507 | #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS) |
539 | 508 | ||
@@ -550,27 +519,25 @@ static unsigned int __devinit init_chipset_cmd64x(struct pci_dev *dev, const cha | |||
550 | 519 | ||
551 | static unsigned int __devinit ata66_cmd64x(ide_hwif_t *hwif) | 520 | static unsigned int __devinit ata66_cmd64x(ide_hwif_t *hwif) |
552 | { | 521 | { |
553 | u8 ata66 = 0, mask = (hwif->channel) ? 0x02 : 0x01; | 522 | struct pci_dev *dev = hwif->pci_dev; |
523 | u8 bmidecsr = 0, mask = hwif->channel ? 0x02 : 0x01; | ||
554 | 524 | ||
555 | switch(hwif->pci_dev->device) { | 525 | switch (dev->device) { |
556 | case PCI_DEVICE_ID_CMD_643: | 526 | case PCI_DEVICE_ID_CMD_648: |
557 | case PCI_DEVICE_ID_CMD_646: | 527 | case PCI_DEVICE_ID_CMD_649: |
558 | return ata66; | 528 | pci_read_config_byte(dev, BMIDECSR, &bmidecsr); |
559 | default: | 529 | return (bmidecsr & mask) ? 1 : 0; |
560 | break; | 530 | default: |
531 | return 0; | ||
561 | } | 532 | } |
562 | pci_read_config_byte(hwif->pci_dev, BMIDECSR, &ata66); | ||
563 | return (ata66 & mask) ? 1 : 0; | ||
564 | } | 533 | } |
565 | 534 | ||
566 | static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif) | 535 | static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif) |
567 | { | 536 | { |
568 | struct pci_dev *dev = hwif->pci_dev; | 537 | struct pci_dev *dev = hwif->pci_dev; |
569 | unsigned int class_rev; | 538 | u8 rev = 0; |
570 | 539 | ||
571 | hwif->autodma = 0; | 540 | pci_read_config_byte(dev, PCI_REVISION_ID, &rev); |
572 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); | ||
573 | class_rev &= 0xff; | ||
574 | 541 | ||
575 | hwif->tuneproc = &cmd64x_tune_drive; | 542 | hwif->tuneproc = &cmd64x_tune_drive; |
576 | hwif->speedproc = &cmd64x_tune_chipset; | 543 | hwif->speedproc = &cmd64x_tune_chipset; |
@@ -580,8 +547,8 @@ static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif) | |||
580 | if (!hwif->dma_base) | 547 | if (!hwif->dma_base) |
581 | return; | 548 | return; |
582 | 549 | ||
583 | hwif->atapi_dma = 1; | 550 | hwif->atapi_dma = 1; |
584 | 551 | hwif->mwdma_mask = 0x07; | |
585 | hwif->ultra_mask = hwif->cds->udma_mask; | 552 | hwif->ultra_mask = hwif->cds->udma_mask; |
586 | 553 | ||
587 | /* | 554 | /* |
@@ -596,16 +563,15 @@ static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif) | |||
596 | * | 563 | * |
597 | * So we only do UltraDMA on revision 0x05 and 0x07 chipsets. | 564 | * So we only do UltraDMA on revision 0x05 and 0x07 chipsets. |
598 | */ | 565 | */ |
599 | if (dev->device == PCI_DEVICE_ID_CMD_646 && class_rev < 5) | 566 | if (dev->device == PCI_DEVICE_ID_CMD_646 && rev < 5) |
600 | hwif->ultra_mask = 0x00; | 567 | hwif->ultra_mask = 0x00; |
601 | 568 | ||
602 | hwif->mwdma_mask = 0x07; | ||
603 | |||
604 | hwif->ide_dma_check = &cmd64x_config_drive_for_dma; | 569 | hwif->ide_dma_check = &cmd64x_config_drive_for_dma; |
605 | if (!(hwif->udma_four)) | 570 | |
571 | if (!hwif->udma_four) | ||
606 | hwif->udma_four = ata66_cmd64x(hwif); | 572 | hwif->udma_four = ata66_cmd64x(hwif); |
607 | 573 | ||
608 | switch(dev->device) { | 574 | switch (dev->device) { |
609 | case PCI_DEVICE_ID_CMD_648: | 575 | case PCI_DEVICE_ID_CMD_648: |
610 | case PCI_DEVICE_ID_CMD_649: | 576 | case PCI_DEVICE_ID_CMD_649: |
611 | alt_irq_bits: | 577 | alt_irq_bits: |
@@ -614,10 +580,10 @@ static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif) | |||
614 | break; | 580 | break; |
615 | case PCI_DEVICE_ID_CMD_646: | 581 | case PCI_DEVICE_ID_CMD_646: |
616 | hwif->chipset = ide_cmd646; | 582 | hwif->chipset = ide_cmd646; |
617 | if (class_rev == 0x01) { | 583 | if (rev == 0x01) { |
618 | hwif->ide_dma_end = &cmd646_1_ide_dma_end; | 584 | hwif->ide_dma_end = &cmd646_1_ide_dma_end; |
619 | break; | 585 | break; |
620 | } else if (class_rev >= 0x03) | 586 | } else if (rev >= 0x03) |
621 | goto alt_irq_bits; | 587 | goto alt_irq_bits; |
622 | /* fall thru */ | 588 | /* fall thru */ |
623 | default: | 589 | default: |
@@ -626,11 +592,9 @@ static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif) | |||
626 | break; | 592 | break; |
627 | } | 593 | } |
628 | 594 | ||
629 | |||
630 | if (!noautodma) | 595 | if (!noautodma) |
631 | hwif->autodma = 1; | 596 | hwif->autodma = 1; |
632 | hwif->drives[0].autodma = hwif->autodma; | 597 | hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma; |
633 | hwif->drives[1].autodma = hwif->autodma; | ||
634 | } | 598 | } |
635 | 599 | ||
636 | static int __devinit init_setup_cmd64x(struct pci_dev *dev, ide_pci_device_t *d) | 600 | static int __devinit init_setup_cmd64x(struct pci_dev *dev, ide_pci_device_t *d) |