sh: shmin updates.

This fixes up shmin (and SH7706/SH7708) IPR support for some of the
recent API changes.

Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

4 files changed, 50 insertions, 4 deletions

diff --git a/arch/sh/boards/shmin/setup.c b/arch/sh/boards/shmin/setup.c
index a31a1d1e2681..bed9ca653d3a 100644
--- a/arch/sh/boards/shmin/setup.c
+++ b/arch/sh/boards/shmin/setup.c
@@ -12,12 +12,22 @@
 #include <asm/irq.h>
 #include <asm/io.h>
 
-#define PFC_PHCR        0xa400010e
+#define PFC_PHCR        0xa400010eUL
+#define INTC_ICR1       0xffd00000UL
+#define INTC_IPRC       0xa4000016UL
+
+static struct ipr_data shmin_ipr_map[] = {
+        { .irq=32, .addr=INTC_IPRC, .shift= 0, .priority=0 }, 
+        { .irq=33, .addr=INTC_IPRC, .shift= 4, .priority=0 }, 
+        { .irq=34, .addr=INTC_IPRC, .shift= 8, .priority=8 }, 
+        { .irq=35, .addr=INTC_IPRC, .shift=12, .priority=0 }, 
+};
 
 static void __init init_shmin_irq(void)
 {
         ctrl_outw(0x2a00, PFC_PHCR);    // IRQ0-3=IRQ
         ctrl_outw(0x0aaa, INTC_ICR1);   // IRQ0-3=IRQ-mode,Low-active.
+        make_ipr_irq(shmin_ipr_map, ARRAY_SIZE(shmin_ipr_map));
 }
 
 static void __iomem *shmin_ioport_map(unsigned long port, unsigned int size)
diff --git a/arch/sh/kernel/cpu/irq/ipr.c b/arch/sh/kernel/cpu/irq/ipr.c
index 35eb5751a3aa..210280b6fddf 100644
--- a/arch/sh/kernel/cpu/irq/ipr.c
+++ b/arch/sh/kernel/cpu/irq/ipr.c
@@ -43,16 +43,29 @@ static struct irq_chip ipr_irq_chip = {
         .mask_ack       = disable_ipr_irq,
 };
 
+unsigned int map_ipridx_to_addr(int idx) __attribute__ ((weak));
+unsigned int map_ipridx_to_addr(int idx)
+{
+        return 0;
+}
+
 void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs)
 {
         int i;
 
         for (i = 0; i < nr_irqs; i++) {
                 unsigned int irq = table[i].irq;
-                table[i].addr = map_ipridx_to_addr(table[i].ipr_idx);
+
+                if (!irq)
+                        irq = table[i].irq = i;
+
                 /* could the IPR index be mapped, if not we ignore this */
-                if (table[i].addr == 0)
-                        continue;
+                if (!table[i].addr) {
+                        table[i].addr = map_ipridx_to_addr(table[i].ipr_idx);
+                        if (!table[i].addr)
+                                continue;
+                }
+
                 disable_irq_nosync(irq);
                 set_irq_chip_and_handler_name(irq, &ipr_irq_chip,
                                       handle_level_irq, "level");
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7709.c b/arch/sh/kernel/cpu/sh3/setup-sh7709.c
index ff43ef2a1f0c..dc9b211cf87f 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7709.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7709.c
@@ -51,3 +51,24 @@ static int __init sh7709_devices_setup(void)
                                     ARRAY_SIZE(sh7709_devices));
 }
 __initcall(sh7709_devices_setup);
+
+#define IPRx(A,N) .addr=A, .shift=0*N*-1
+#define IPRA(N) IPRx(0xfffffee2UL,N)
+#define IPRB(N) IPRx(0xfffffee4UL,N)
+#define IPRE(N) IPRx(0xa400001aUL,N)
+
+static struct ipr_data sh7709_ipr_map[] = {
+        [16]            = { IPRA(15-12), 2 }, /* TMU TUNI0 */
+        [17]            = { IPRA(11-8),  4 }, /* TMU TUNI1 */
+        [22]            = { IPRA(3-0),   2 }, /* RTC CUI */
+        [23 ... 26]     = { IPRB(7-4),   3 }, /* SCI */
+        [27]            = { IPRB(15-12), 2 }, /* WDT ITI */
+        [48 ... 51]     = { IPRE(15-12), 7 }, /* DMA */
+        [52 ... 55]     = { IPRE(11-8),  3 }, /* IRDA */
+        [56 ... 59]     = { IPRE(7-4),   3 }, /* SCIF */
+};
+
+void __init init_IRQ_ipr()
+{
+        make_ipr_irq(sh7709_ipr_map, ARRAY_SIZE(sh7709_ipr_map));
+}
diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig
index 29f4ee35c6dc..fddf6680ec4f 100644
--- a/arch/sh/mm/Kconfig
+++ b/arch/sh/mm/Kconfig
@@ -72,6 +72,7 @@ config CPU_SUBTYPE_SH7705
 config CPU_SUBTYPE_SH7706
         bool "Support SH7706 processor"
         select CPU_SH3
+        select CPU_HAS_IPR_IRQ
         help
           Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU.
 
@@ -92,6 +93,7 @@ config CPU_SUBTYPE_SH7708
 config CPU_SUBTYPE_SH7709
         bool "Support SH7709 processor"
         select CPU_SH3
+        select CPU_HAS_IPR_IRQ
         select CPU_HAS_PINT_IRQ
         help
           Select SH7709 if you have a  80 Mhz SH-3 HD6417709 CPU.