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authorDan Williams <dan.j.williams@intel.com>2007-05-14 20:03:36 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-05-16 10:35:27 -0400
commitd73d8011779292788def2cd2520d6f39d9b406de (patch)
tree4a74fca4a1e549091414a0a0cbbc2cf63fcbd64e
parente702a7155d14a6e11645e17d829217ae98fd45bb (diff)
[ARM] 4383/1: iop: fix usage of '__init' and 'inline' in iop files
WARNING: arch/arm/mach-iop13xx/built-in.o - Section mismatch: reference to .init.text:iop13xx_pcie_map_irq from .text between 'iop13xx_pci_setup' (at offset 0x7fc) and 'iop13xx_map_pci_memory' While fixing this warning I also recalled Adrian Bunk's recommendation to not use inline in .c files, as 'iop13xx_map_pci_memory' is needlessly inlined. Removing 'inline' uncovered some dead code so that is cleaned up as well. Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat
-rw-r--r--arch/arm/mach-iop13xx/irq.c54
-rw-r--r--arch/arm/mach-iop13xx/msi.c16
-rw-r--r--arch/arm/mach-iop13xx/pci.c8
-rw-r--r--arch/arm/mach-iop32x/glantank.c2
-rw-r--r--arch/arm/mach-iop32x/iq31244.c4
-rw-r--r--arch/arm/mach-iop32x/iq80321.c2
-rw-r--r--arch/arm/mach-iop32x/irq.c4
-rw-r--r--arch/arm/mach-iop32x/n2100.c2
-rw-r--r--arch/arm/mach-iop33x/iq80331.c2
-rw-r--r--arch/arm/mach-iop33x/iq80332.c2
-rw-r--r--arch/arm/mach-iop33x/irq.c12
-rw-r--r--arch/arm/plat-iop/pci.c4
12 files changed, 38 insertions, 74 deletions
diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c
index 5791addd436b..69f07b25b3c9 100644
--- a/arch/arm/mach-iop13xx/irq.c
+++ b/arch/arm/mach-iop13xx/irq.c
@@ -30,77 +30,65 @@
30 30
31/* INTCTL0 CP6 R0 Page 4 31/* INTCTL0 CP6 R0 Page 4
32 */ 32 */
33static inline u32 read_intctl_0(void) 33static u32 read_intctl_0(void)
34{ 34{
35 u32 val; 35 u32 val;
36 asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val)); 36 asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val));
37 return val; 37 return val;
38} 38}
39static inline void write_intctl_0(u32 val) 39static void write_intctl_0(u32 val)
40{ 40{
41 asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val)); 41 asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val));
42} 42}
43 43
44/* INTCTL1 CP6 R1 Page 4 44/* INTCTL1 CP6 R1 Page 4
45 */ 45 */
46static inline u32 read_intctl_1(void) 46static u32 read_intctl_1(void)
47{ 47{
48 u32 val; 48 u32 val;
49 asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val)); 49 asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val));
50 return val; 50 return val;
51} 51}
52static inline void write_intctl_1(u32 val) 52static void write_intctl_1(u32 val)
53{ 53{
54 asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val)); 54 asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val));
55} 55}
56 56
57/* INTCTL2 CP6 R2 Page 4 57/* INTCTL2 CP6 R2 Page 4
58 */ 58 */
59static inline u32 read_intctl_2(void) 59static u32 read_intctl_2(void)
60{ 60{
61 u32 val; 61 u32 val;
62 asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val)); 62 asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val));
63 return val; 63 return val;
64} 64}
65static inline void write_intctl_2(u32 val) 65static void write_intctl_2(u32 val)
66{ 66{
67 asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val)); 67 asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val));
68} 68}
69 69
70/* INTCTL3 CP6 R3 Page 4 70/* INTCTL3 CP6 R3 Page 4
71 */ 71 */
72static inline u32 read_intctl_3(void) 72static u32 read_intctl_3(void)
73{ 73{
74 u32 val; 74 u32 val;
75 asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val)); 75 asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val));
76 return val; 76 return val;
77} 77}
78static inline void write_intctl_3(u32 val) 78static void write_intctl_3(u32 val)
79{ 79{
80 asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val)); 80 asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val));
81} 81}
82 82
83/* INTSTR0 CP6 R0 Page 5 83/* INTSTR0 CP6 R0 Page 5
84 */ 84 */
85static inline u32 read_intstr_0(void) 85static void write_intstr_0(u32 val)
86{
87 u32 val;
88 asm volatile("mrc p6, 0, %0, c0, c5, 0":"=r" (val));
89 return val;
90}
91static inline void write_intstr_0(u32 val)
92{ 86{
93 asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val)); 87 asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val));
94} 88}
95 89
96/* INTSTR1 CP6 R1 Page 5 90/* INTSTR1 CP6 R1 Page 5
97 */ 91 */
98static inline u32 read_intstr_1(void)
99{
100 u32 val;
101 asm volatile("mrc p6, 0, %0, c1, c5, 0":"=r" (val));
102 return val;
103}
104static void write_intstr_1(u32 val) 92static void write_intstr_1(u32 val)
105{ 93{
106 asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val)); 94 asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val));
@@ -108,12 +96,6 @@ static void write_intstr_1(u32 val)
108 96
109/* INTSTR2 CP6 R2 Page 5 97/* INTSTR2 CP6 R2 Page 5
110 */ 98 */
111static inline u32 read_intstr_2(void)
112{
113 u32 val;
114 asm volatile("mrc p6, 0, %0, c2, c5, 0":"=r" (val));
115 return val;
116}
117static void write_intstr_2(u32 val) 99static void write_intstr_2(u32 val)
118{ 100{
119 asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val)); 101 asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val));
@@ -121,12 +103,6 @@ static void write_intstr_2(u32 val)
121 103
122/* INTSTR3 CP6 R3 Page 5 104/* INTSTR3 CP6 R3 Page 5
123 */ 105 */
124static inline u32 read_intstr_3(void)
125{
126 u32 val;
127 asm volatile("mrc p6, 0, %0, c3, c5, 0":"=r" (val));
128 return val;
129}
130static void write_intstr_3(u32 val) 106static void write_intstr_3(u32 val)
131{ 107{
132 asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val)); 108 asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val));
@@ -134,12 +110,6 @@ static void write_intstr_3(u32 val)
134 110
135/* INTBASE CP6 R0 Page 2 111/* INTBASE CP6 R0 Page 2
136 */ 112 */
137static inline u32 read_intbase(void)
138{
139 u32 val;
140 asm volatile("mrc p6, 0, %0, c0, c2, 0":"=r" (val));
141 return val;
142}
143static void write_intbase(u32 val) 113static void write_intbase(u32 val)
144{ 114{
145 asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val)); 115 asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val));
@@ -147,12 +117,6 @@ static void write_intbase(u32 val)
147 117
148/* INTSIZE CP6 R2 Page 2 118/* INTSIZE CP6 R2 Page 2
149 */ 119 */
150static inline u32 read_intsize(void)
151{
152 u32 val;
153 asm volatile("mrc p6, 0, %0, c2, c2, 0":"=r" (val));
154 return val;
155}
156static void write_intsize(u32 val) 120static void write_intsize(u32 val)
157{ 121{
158 asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val)); 122 asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val));
diff --git a/arch/arm/mach-iop13xx/msi.c b/arch/arm/mach-iop13xx/msi.c
index 062d2acdd5e5..63ef1124ca5c 100644
--- a/arch/arm/mach-iop13xx/msi.c
+++ b/arch/arm/mach-iop13xx/msi.c
@@ -30,52 +30,52 @@ static DECLARE_BITMAP(msi_irq_in_use, IOP13XX_NUM_MSI_IRQS);
30 30
31/* IMIPR0 CP6 R8 Page 1 31/* IMIPR0 CP6 R8 Page 1
32 */ 32 */
33static inline u32 read_imipr_0(void) 33static u32 read_imipr_0(void)
34{ 34{
35 u32 val; 35 u32 val;
36 asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val)); 36 asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val));
37 return val; 37 return val;
38} 38}
39static inline void write_imipr_0(u32 val) 39static void write_imipr_0(u32 val)
40{ 40{
41 asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val)); 41 asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val));
42} 42}
43 43
44/* IMIPR1 CP6 R9 Page 1 44/* IMIPR1 CP6 R9 Page 1
45 */ 45 */
46static inline u32 read_imipr_1(void) 46static u32 read_imipr_1(void)
47{ 47{
48 u32 val; 48 u32 val;
49 asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val)); 49 asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val));
50 return val; 50 return val;
51} 51}
52static inline void write_imipr_1(u32 val) 52static void write_imipr_1(u32 val)
53{ 53{
54 asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val)); 54 asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val));
55} 55}
56 56
57/* IMIPR2 CP6 R10 Page 1 57/* IMIPR2 CP6 R10 Page 1
58 */ 58 */
59static inline u32 read_imipr_2(void) 59static u32 read_imipr_2(void)
60{ 60{
61 u32 val; 61 u32 val;
62 asm volatile("mrc p6, 0, %0, c10, c1, 0":"=r" (val)); 62 asm volatile("mrc p6, 0, %0, c10, c1, 0":"=r" (val));
63 return val; 63 return val;
64} 64}
65static inline void write_imipr_2(u32 val) 65static void write_imipr_2(u32 val)
66{ 66{
67 asm volatile("mcr p6, 0, %0, c10, c1, 0"::"r" (val)); 67 asm volatile("mcr p6, 0, %0, c10, c1, 0"::"r" (val));
68} 68}
69 69
70/* IMIPR3 CP6 R11 Page 1 70/* IMIPR3 CP6 R11 Page 1
71 */ 71 */
72static inline u32 read_imipr_3(void) 72static u32 read_imipr_3(void)
73{ 73{
74 u32 val; 74 u32 val;
75 asm volatile("mrc p6, 0, %0, c11, c1, 0":"=r" (val)); 75 asm volatile("mrc p6, 0, %0, c11, c1, 0":"=r" (val));
76 return val; 76 return val;
77} 77}
78static inline void write_imipr_3(u32 val) 78static void write_imipr_3(u32 val)
79{ 79{
80 asm volatile("mcr p6, 0, %0, c11, c1, 0"::"r" (val)); 80 asm volatile("mcr p6, 0, %0, c11, c1, 0"::"r" (val));
81} 81}
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index 1c9e94c38b7e..69e8953832fd 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -144,7 +144,7 @@ void iop13xx_map_pci_memory(void)
144 } 144 }
145} 145}
146 146
147static inline int iop13xx_atu_function(int atu) 147static int iop13xx_atu_function(int atu)
148{ 148{
149 int func = 0; 149 int func = 0;
150 /* the function number depends on the value of the 150 /* the function number depends on the value of the
@@ -259,7 +259,7 @@ static int iop13xx_atux_pci_status(int clear)
259 * data. Note that the data dependency on %0 encourages an abort 259 * data. Note that the data dependency on %0 encourages an abort
260 * to be detected before we return. 260 * to be detected before we return.
261 */ 261 */
262static inline u32 iop13xx_atux_read(unsigned long addr) 262static u32 iop13xx_atux_read(unsigned long addr)
263{ 263{
264 u32 val; 264 u32 val;
265 265
@@ -387,7 +387,7 @@ static int iop13xx_atue_pci_status(int clear)
387 return err; 387 return err;
388} 388}
389 389
390static inline int __init 390static int
391iop13xx_pcie_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) 391iop13xx_pcie_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
392{ 392{
393 WARN_ON(idsel != 0); 393 WARN_ON(idsel != 0);
@@ -401,7 +401,7 @@ iop13xx_pcie_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
401 } 401 }
402} 402}
403 403
404static inline u32 iop13xx_atue_read(unsigned long addr) 404static u32 iop13xx_atue_read(unsigned long addr)
405{ 405{
406 u32 val; 406 u32 val;
407 407
diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c
index 45f4f13ae11b..5776fd884115 100644
--- a/arch/arm/mach-iop32x/glantank.c
+++ b/arch/arm/mach-iop32x/glantank.c
@@ -75,7 +75,7 @@ void __init glantank_map_io(void)
75#define INTC IRQ_IOP32X_XINT2 75#define INTC IRQ_IOP32X_XINT2
76#define INTD IRQ_IOP32X_XINT3 76#define INTD IRQ_IOP32X_XINT3
77 77
78static inline int __init 78static int __init
79glantank_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 79glantank_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
80{ 80{
81 static int pci_irq_table[][4] = { 81 static int pci_irq_table[][4] = {
diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c
index 7b21c6e13e59..d4eefbea1fe6 100644
--- a/arch/arm/mach-iop32x/iq31244.c
+++ b/arch/arm/mach-iop32x/iq31244.c
@@ -104,7 +104,7 @@ void __init iq31244_map_io(void)
104/* 104/*
105 * EP80219/IQ31244 PCI. 105 * EP80219/IQ31244 PCI.
106 */ 106 */
107static inline int __init 107static int __init
108ep80219_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 108ep80219_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
109{ 109{
110 int irq; 110 int irq;
@@ -140,7 +140,7 @@ static struct hw_pci ep80219_pci __initdata = {
140 .map_irq = ep80219_pci_map_irq, 140 .map_irq = ep80219_pci_map_irq,
141}; 141};
142 142
143static inline int __init 143static int __init
144iq31244_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 144iq31244_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
145{ 145{
146 int irq; 146 int irq;
diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c
index bc25fb91e7b9..8d9f49164a84 100644
--- a/arch/arm/mach-iop32x/iq80321.c
+++ b/arch/arm/mach-iop32x/iq80321.c
@@ -72,7 +72,7 @@ void __init iq80321_map_io(void)
72/* 72/*
73 * IQ80321 PCI. 73 * IQ80321 PCI.
74 */ 74 */
75static inline int __init 75static int __init
76iq80321_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 76iq80321_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
77{ 77{
78 int irq; 78 int irq;
diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c
index 82598dc18d80..c971171c2905 100644
--- a/arch/arm/mach-iop32x/irq.c
+++ b/arch/arm/mach-iop32x/irq.c
@@ -21,12 +21,12 @@
21 21
22static u32 iop32x_mask; 22static u32 iop32x_mask;
23 23
24static inline void intctl_write(u32 val) 24static void intctl_write(u32 val)
25{ 25{
26 asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); 26 asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
27} 27}
28 28
29static inline void intstr_write(u32 val) 29static void intstr_write(u32 val)
30{ 30{
31 asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val)); 31 asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val));
32} 32}
diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c
index 5f07344d96f3..d55005d64781 100644
--- a/arch/arm/mach-iop32x/n2100.c
+++ b/arch/arm/mach-iop32x/n2100.c
@@ -76,7 +76,7 @@ void __init n2100_map_io(void)
76/* 76/*
77 * N2100 PCI. 77 * N2100 PCI.
78 */ 78 */
79static inline int __init 79static int __init
80n2100_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 80n2100_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
81{ 81{
82 int irq; 82 int irq;
diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c
index 376c932830be..2b063180687a 100644
--- a/arch/arm/mach-iop33x/iq80331.c
+++ b/arch/arm/mach-iop33x/iq80331.c
@@ -55,7 +55,7 @@ static struct sys_timer iq80331_timer = {
55/* 55/*
56 * IQ80331 PCI. 56 * IQ80331 PCI.
57 */ 57 */
58static inline int __init 58static int __init
59iq80331_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 59iq80331_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
60{ 60{
61 int irq; 61 int irq;
diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c
index 58c81496c6f6..7889ce3cb08e 100644
--- a/arch/arm/mach-iop33x/iq80332.c
+++ b/arch/arm/mach-iop33x/iq80332.c
@@ -55,7 +55,7 @@ static struct sys_timer iq80332_timer = {
55/* 55/*
56 * IQ80332 PCI. 56 * IQ80332 PCI.
57 */ 57 */
58static inline int __init 58static int __init
59iq80332_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 59iq80332_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
60{ 60{
61 int irq; 61 int irq;
diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c
index c65ea78a2427..f09dd054b9c0 100644
--- a/arch/arm/mach-iop33x/irq.c
+++ b/arch/arm/mach-iop33x/irq.c
@@ -22,32 +22,32 @@
22static u32 iop33x_mask0; 22static u32 iop33x_mask0;
23static u32 iop33x_mask1; 23static u32 iop33x_mask1;
24 24
25static inline void intctl0_write(u32 val) 25static void intctl0_write(u32 val)
26{ 26{
27 asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); 27 asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
28} 28}
29 29
30static inline void intctl1_write(u32 val) 30static void intctl1_write(u32 val)
31{ 31{
32 asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val)); 32 asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val));
33} 33}
34 34
35static inline void intstr0_write(u32 val) 35static void intstr0_write(u32 val)
36{ 36{
37 asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val)); 37 asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val));
38} 38}
39 39
40static inline void intstr1_write(u32 val) 40static void intstr1_write(u32 val)
41{ 41{
42 asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val)); 42 asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val));
43} 43}
44 44
45static inline void intbase_write(u32 val) 45static void intbase_write(u32 val)
46{ 46{
47 asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val)); 47 asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val));
48} 48}
49 49
50static inline void intsize_write(u32 val) 50static void intsize_write(u32 val)
51{ 51{
52 asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val)); 52 asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val));
53} 53}
diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c
index e2744b7227c5..d3605934f1c7 100644
--- a/arch/arm/plat-iop/pci.c
+++ b/arch/arm/plat-iop/pci.c
@@ -88,7 +88,7 @@ static int iop3xx_pci_status(void)
88 * data. Note that the 4 nop's ensure that we are able to handle 88 * data. Note that the 4 nop's ensure that we are able to handle
89 * a delayed abort (in theory.) 89 * a delayed abort (in theory.)
90 */ 90 */
91static inline u32 iop3xx_read(unsigned long addr) 91static u32 iop3xx_read(unsigned long addr)
92{ 92{
93 u32 val; 93 u32 val;
94 94
@@ -321,7 +321,7 @@ void __init iop3xx_atu_disable(void)
321/* Flag to determine whether the ATU is initialized and the PCI bus scanned */ 321/* Flag to determine whether the ATU is initialized and the PCI bus scanned */
322int init_atu; 322int init_atu;
323 323
324void iop3xx_pci_preinit(void) 324void __init iop3xx_pci_preinit(void)
325{ 325{
326 if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) { 326 if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) {
327 iop3xx_atu_disable(); 327 iop3xx_atu_disable();
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-06 21:54:42 -0500