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authorMaciej W. Rozycki <macro@linux-mips.org>2005-02-01 15:18:59 -0500
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 14:30:20 -0400
commitaa0980b8090878bf42bc73a13d051a203a201d7d (patch)
treec4e411d4100a6006b0bc2945742b0ab2fa10b2e5
parentbec0204dfb35cd5b91c0b34f97a481f363f6b272 (diff)
Fixes for system controllers for Atlas/Malta core cards.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat
-rw-r--r--arch/mips/mips-boards/generic/init.c61
-rw-r--r--arch/mips/mips-boards/generic/pci.c158
-rw-r--r--arch/mips/pci/ops-bonito64.c14
-rw-r--r--arch/mips/pci/ops-gt64120.c10
-rw-r--r--arch/mips/pci/ops-msc.c31
-rw-r--r--include/asm-mips/mips-boards/msc01_pci.h241
6 files changed, 297 insertions, 218 deletions
diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c
index 311155d1d3ed..d821b13d24a0 100644
--- a/arch/mips/mips-boards/generic/init.c
+++ b/arch/mips/mips-boards/generic/init.c
@@ -1,6 +1,8 @@
1/* 1/*
2 * Carsten Langgaard, carstenl@mips.com 2 * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc.
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. 3 * All rights reserved.
4 * Authors: Carsten Langgaard <carstenl@mips.com>
5 * Maciej W. Rozycki <macro@mips.com>
4 * 6 *
5 * This program is free software; you can distribute it and/or modify it 7 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as 8 * under the terms of the GNU General Public License (Version 2) as
@@ -22,18 +24,17 @@
22#include <linux/string.h> 24#include <linux/string.h>
23#include <linux/kernel.h> 25#include <linux/kernel.h>
24 26
25#include <asm/io.h>
26#include <asm/bootinfo.h> 27#include <asm/bootinfo.h>
28#include <asm/gt64120.h>
29#include <asm/io.h>
30#include <asm/system.h>
31
27#include <asm/mips-boards/prom.h> 32#include <asm/mips-boards/prom.h>
28#include <asm/mips-boards/generic.h> 33#include <asm/mips-boards/generic.h>
29#ifdef CONFIG_MIPS_GT64120
30#include <asm/gt64120.h>
31#endif
32#include <asm/mips-boards/msc01_pci.h>
33#include <asm/mips-boards/bonito64.h> 34#include <asm/mips-boards/bonito64.h>
34#ifdef CONFIG_MIPS_MALTA 35#include <asm/mips-boards/msc01_pci.h>
36
35#include <asm/mips-boards/malta.h> 37#include <asm/mips-boards/malta.h>
36#endif
37 38
38#ifdef CONFIG_KGDB 39#ifdef CONFIG_KGDB
39extern int rs_kgdb_hook(int, int); 40extern int rs_kgdb_hook(int, int);
@@ -225,6 +226,8 @@ void __init kgdb_config (void)
225 226
226void __init prom_init(void) 227void __init prom_init(void)
227{ 228{
229 u32 start, map, mask, data;
230
228 prom_argc = fw_arg0; 231 prom_argc = fw_arg0;
229 _prom_argv = (int *) fw_arg1; 232 _prom_argv = (int *) fw_arg1;
230 _prom_envp = (int *) fw_arg2; 233 _prom_envp = (int *) fw_arg2;
@@ -266,12 +269,15 @@ void __init prom_init(void)
266#else 269#else
267 GT_WRITE(GT_PCI0_CMD_OFS, 0); 270 GT_WRITE(GT_PCI0_CMD_OFS, 0);
268#endif 271#endif
272 /* Fix up PCI I/O mapping if necessary (for Atlas). */
273 start = GT_READ(GT_PCI0IOLD_OFS);
274 map = GT_READ(GT_PCI0IOREMAP_OFS);
275 if ((start & map) != 0) {
276 map &= ~start;
277 GT_WRITE(GT_PCI0IOREMAP_OFS, map);
278 }
269 279
270#ifdef CONFIG_MIPS_MALTA
271 set_io_port_base(MALTA_GT_PORT_BASE); 280 set_io_port_base(MALTA_GT_PORT_BASE);
272#else
273 set_io_port_base((unsigned long)ioremap(0, 0x20000000));
274#endif
275 break; 281 break;
276 282
277 case MIPS_REVISION_CORID_CORE_EMUL_BON: 283 case MIPS_REVISION_CORID_CORE_EMUL_BON:
@@ -300,11 +306,7 @@ void __init prom_init(void)
300 BONITO_BONGENCFG_BYTESWAP; 306 BONITO_BONGENCFG_BYTESWAP;
301#endif 307#endif
302 308
303#ifdef CONFIG_MIPS_MALTA
304 set_io_port_base(MALTA_BONITO_PORT_BASE); 309 set_io_port_base(MALTA_BONITO_PORT_BASE);
305#else
306 set_io_port_base((unsigned long)ioremap(0, 0x20000000));
307#endif
308 break; 310 break;
309 311
310 case MIPS_REVISION_CORID_CORE_MSC: 312 case MIPS_REVISION_CORID_CORE_MSC:
@@ -312,6 +314,12 @@ void __init prom_init(void)
312 case MIPS_REVISION_CORID_CORE_EMUL_MSC: 314 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
313 _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); 315 _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000);
314 316
317 mb();
318 MSC_READ(MSC01_PCI_CFG, data);
319 MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT);
320 wmb();
321
322 /* Fix up lane swapping. */
315#ifdef CONFIG_CPU_LITTLE_ENDIAN 323#ifdef CONFIG_CPU_LITTLE_ENDIAN
316 MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP); 324 MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP);
317#else 325#else
@@ -320,12 +328,23 @@ void __init prom_init(void)
320 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF | 328 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF |
321 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF); 329 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF);
322#endif 330#endif
331 /* Fix up target memory mapping. */
332 MSC_READ(MSC01_PCI_BAR0, mask);
333 MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK);
334
335 /* Don't handle target retries indefinitely. */
336 if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) ==
337 MSC01_PCI_CFG_MAXRTRY_MSK)
338 data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK <<
339 MSC01_PCI_CFG_MAXRTRY_SHF)) |
340 ((MSC01_PCI_CFG_MAXRTRY_MSK - 1) <<
341 MSC01_PCI_CFG_MAXRTRY_SHF);
342
343 wmb();
344 MSC_WRITE(MSC01_PCI_CFG, data);
345 mb();
323 346
324#ifdef CONFIG_MIPS_MALTA
325 set_io_port_base(MALTA_MSC_PORT_BASE); 347 set_io_port_base(MALTA_MSC_PORT_BASE);
326#else
327 set_io_port_base((unsigned long)ioremap(0, 0x20000000));
328#endif
329 break; 348 break;
330 349
331 default: 350 default:
diff --git a/arch/mips/mips-boards/generic/pci.c b/arch/mips/mips-boards/generic/pci.c
index 5dadedffba13..c8398c497a21 100644
--- a/arch/mips/mips-boards/generic/pci.c
+++ b/arch/mips/mips-boards/generic/pci.c
@@ -1,6 +1,8 @@
1/* 1/*
2 * Carsten Langgaard, carstenl@mips.com 2 * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc.
3 * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved. 3 * All rights reserved.
4 * Authors: Carsten Langgaard <carstenl@mips.com>
5 * Maciej W. Rozycki <macro@mips.com>
4 * 6 *
5 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) 7 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
6 * 8 *
@@ -19,65 +21,46 @@
19 * 21 *
20 * MIPS boards specific PCI support. 22 * MIPS boards specific PCI support.
21 */ 23 */
22#include <linux/config.h>
23#include <linux/types.h> 24#include <linux/types.h>
24#include <linux/pci.h> 25#include <linux/pci.h>
25#include <linux/kernel.h> 26#include <linux/kernel.h>
26#include <linux/init.h> 27#include <linux/init.h>
27 28
28#include <asm/mips-boards/generic.h>
29#include <asm/gt64120.h> 29#include <asm/gt64120.h>
30
31#include <asm/mips-boards/generic.h>
30#include <asm/mips-boards/bonito64.h> 32#include <asm/mips-boards/bonito64.h>
31#include <asm/mips-boards/msc01_pci.h> 33#include <asm/mips-boards/msc01_pci.h>
32#ifdef CONFIG_MIPS_MALTA
33#include <asm/mips-boards/malta.h>
34#endif
35 34
36static struct resource bonito64_mem_resource = { 35static struct resource bonito64_mem_resource = {
37 .name = "Bonito PCI MEM", 36 .name = "Bonito PCI MEM",
38 .start = 0x10000000UL,
39 .end = 0x1bffffffUL,
40 .flags = IORESOURCE_MEM, 37 .flags = IORESOURCE_MEM,
41}; 38};
42 39
43static struct resource bonito64_io_resource = { 40static struct resource bonito64_io_resource = {
44 .name = "Bonito IO MEM", 41 .name = "Bonito PCI I/O",
45 .start = 0x00002000UL, /* avoid conflicts with YAMON allocated I/O addresses */ 42 .start = 0x00000000UL,
46 .end = 0x000fffffUL, 43 .end = 0x000fffffUL,
47 .flags = IORESOURCE_IO, 44 .flags = IORESOURCE_IO,
48}; 45};
49 46
50static struct resource gt64120_mem_resource = { 47static struct resource gt64120_mem_resource = {
51 .name = "GT64120 PCI MEM", 48 .name = "GT-64120 PCI MEM",
52 .start = 0x10000000UL,
53 .end = 0x1bdfffffUL,
54 .flags = IORESOURCE_MEM, 49 .flags = IORESOURCE_MEM,
55}; 50};
56 51
57static struct resource gt64120_io_resource = { 52static struct resource gt64120_io_resource = {
58 .name = "GT64120 IO MEM", 53 .name = "GT-64120 PCI I/O",
59#ifdef CONFIG_MIPS_ATLAS
60 .start = 0x18000000UL,
61 .end = 0x181fffffUL,
62#endif
63#ifdef CONFIG_MIPS_MALTA
64 .start = 0x00002000UL,
65 .end = 0x001fffffUL,
66#endif
67 .flags = IORESOURCE_IO, 54 .flags = IORESOURCE_IO,
68}; 55};
69 56
70static struct resource msc_mem_resource = { 57static struct resource msc_mem_resource = {
71 .name = "MSC PCI MEM", 58 .name = "MSC PCI MEM",
72 .start = 0x10000000UL,
73 .end = 0x1fffffffUL,
74 .flags = IORESOURCE_MEM, 59 .flags = IORESOURCE_MEM,
75}; 60};
76 61
77static struct resource msc_io_resource = { 62static struct resource msc_io_resource = {
78 .name = "MSC IO MEM", 63 .name = "MSC PCI I/O",
79 .start = 0x00002000UL,
80 .end = 0x007fffffUL,
81 .flags = IORESOURCE_IO, 64 .flags = IORESOURCE_IO,
82}; 65};
83 66
@@ -89,7 +72,6 @@ static struct pci_controller bonito64_controller = {
89 .pci_ops = &bonito64_pci_ops, 72 .pci_ops = &bonito64_pci_ops,
90 .io_resource = &bonito64_io_resource, 73 .io_resource = &bonito64_io_resource,
91 .mem_resource = &bonito64_mem_resource, 74 .mem_resource = &bonito64_mem_resource,
92 .mem_offset = 0x10000000UL,
93 .io_offset = 0x00000000UL, 75 .io_offset = 0x00000000UL,
94}; 76};
95 77
@@ -97,21 +79,18 @@ static struct pci_controller gt64120_controller = {
97 .pci_ops = &gt64120_pci_ops, 79 .pci_ops = &gt64120_pci_ops,
98 .io_resource = &gt64120_io_resource, 80 .io_resource = &gt64120_io_resource,
99 .mem_resource = &gt64120_mem_resource, 81 .mem_resource = &gt64120_mem_resource,
100 .mem_offset = 0x00000000UL,
101 .io_offset = 0x00000000UL,
102}; 82};
103 83
104static struct pci_controller msc_controller = { 84static struct pci_controller msc_controller = {
105 .pci_ops = &msc_pci_ops, 85 .pci_ops = &msc_pci_ops,
106 .io_resource = &msc_io_resource, 86 .io_resource = &msc_io_resource,
107 .mem_resource = &msc_mem_resource, 87 .mem_resource = &msc_mem_resource,
108 .mem_offset = 0x10000000UL,
109 .io_offset = 0x00000000UL,
110}; 88};
111 89
112void __init mips_pcibios_init(void) 90void __init mips_pcibios_init(void)
113{ 91{
114 struct pci_controller *controller; 92 struct pci_controller *controller;
93 unsigned long start, end, map, start1, end1, map1, map2, map3, mask;
115 94
116 switch (mips_revision_corid) { 95 switch (mips_revision_corid) {
117 case MIPS_REVISION_CORID_QED_RM5261: 96 case MIPS_REVISION_CORID_QED_RM5261:
@@ -130,29 +109,138 @@ void __init mips_pcibios_init(void)
130 (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */ 109 (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */
131 (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/ 110 (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/
132 ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/ 111 ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/
133 GT_PCI0_CFGADDR_CONFIGEN_BIT ); 112 GT_PCI0_CFGADDR_CONFIGEN_BIT);
134 113
135 /* Perform the write */ 114 /* Perform the write */
136 GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE)); 115 GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE));
137 116
117 /* Set up resource ranges from the controller's registers. */
118 start = GT_READ(GT_PCI0M0LD_OFS);
119 end = GT_READ(GT_PCI0M0HD_OFS);
120 map = GT_READ(GT_PCI0M0REMAP_OFS);
121 end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);
122 start1 = GT_READ(GT_PCI0M1LD_OFS);
123 end1 = GT_READ(GT_PCI0M1HD_OFS);
124 map1 = GT_READ(GT_PCI0M1REMAP_OFS);
125 end1 = (end1 & GT_PCI_HD_MSK) | (start1 & ~GT_PCI_HD_MSK);
126 /* Cannot support multiple windows, use the wider. */
127 if (end1 - start1 > end - start) {
128 start = start1;
129 end = end1;
130 map = map1;
131 }
132 mask = ~(start ^ end);
133 /* We don't support remapping with a discontiguous mask. */
134 BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
135 mask != ~((mask & -mask) - 1));
136 gt64120_mem_resource.start = start;
137 gt64120_mem_resource.end = end;
138 gt64120_controller.mem_offset = (start & mask) - (map & mask);
139 /* Addresses are 36-bit, so do shifts in the destinations. */
140 gt64120_mem_resource.start <<= GT_PCI_DCRM_SHF;
141 gt64120_mem_resource.end <<= GT_PCI_DCRM_SHF;
142 gt64120_mem_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1;
143 gt64120_controller.mem_offset <<= GT_PCI_DCRM_SHF;
144
145 start = GT_READ(GT_PCI0IOLD_OFS);
146 end = GT_READ(GT_PCI0IOHD_OFS);
147 map = GT_READ(GT_PCI0IOREMAP_OFS);
148 end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);
149 mask = ~(start ^ end);
150 /* We don't support remapping with a discontiguous mask. */
151 BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
152 mask != ~((mask & -mask) - 1));
153 gt64120_io_resource.start = map & mask;
154 gt64120_io_resource.end = (map & mask) | ~mask;
155 gt64120_controller.io_offset = 0;
156 /* Addresses are 36-bit, so do shifts in the destinations. */
157 gt64120_io_resource.start <<= GT_PCI_DCRM_SHF;
158 gt64120_io_resource.end <<= GT_PCI_DCRM_SHF;
159 gt64120_io_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1;
160
138 controller = &gt64120_controller; 161 controller = &gt64120_controller;
139 break; 162 break;
140 163
141 case MIPS_REVISION_CORID_BONITO64: 164 case MIPS_REVISION_CORID_BONITO64:
142 case MIPS_REVISION_CORID_CORE_20K: 165 case MIPS_REVISION_CORID_CORE_20K:
143 case MIPS_REVISION_CORID_CORE_EMUL_BON: 166 case MIPS_REVISION_CORID_CORE_EMUL_BON:
167 /* Set up resource ranges from the controller's registers. */
168 map = BONITO_PCIMAP;
169 map1 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO0) >>
170 BONITO_PCIMAP_PCIMAP_LO0_SHIFT;
171 map2 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO1) >>
172 BONITO_PCIMAP_PCIMAP_LO1_SHIFT;
173 map3 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO2) >>
174 BONITO_PCIMAP_PCIMAP_LO2_SHIFT;
175 /* Combine as many adjacent windows as possible. */
176 map = map1;
177 start = BONITO_PCILO0_BASE;
178 end = 1;
179 if (map3 == map2 + 1) {
180 map = map2;
181 start = BONITO_PCILO1_BASE;
182 end++;
183 }
184 if (map2 == map1 + 1) {
185 map = map1;
186 start = BONITO_PCILO0_BASE;
187 end++;
188 }
189 bonito64_mem_resource.start = start;
190 bonito64_mem_resource.end = start +
191 BONITO_PCIMAP_WINBASE(end) - 1;
192 bonito64_controller.mem_offset = start -
193 BONITO_PCIMAP_WINBASE(map);
194
144 controller = &bonito64_controller; 195 controller = &bonito64_controller;
145 break; 196 break;
146 197
147 case MIPS_REVISION_CORID_CORE_MSC: 198 case MIPS_REVISION_CORID_CORE_MSC:
148 case MIPS_REVISION_CORID_CORE_FPGA2: 199 case MIPS_REVISION_CORID_CORE_FPGA2:
149 case MIPS_REVISION_CORID_CORE_EMUL_MSC: 200 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
201 /* Set up resource ranges from the controller's registers. */
202 MSC_READ(MSC01_PCI_SC2PMBASL, start);
203 MSC_READ(MSC01_PCI_SC2PMMSKL, mask);
204 MSC_READ(MSC01_PCI_SC2PMMAPL, map);
205 msc_mem_resource.start = start & mask;
206 msc_mem_resource.end = (start & mask) | ~mask;
207 msc_controller.mem_offset = (start & mask) - (map & mask);
208
209 MSC_READ(MSC01_PCI_SC2PIOBASL, start);
210 MSC_READ(MSC01_PCI_SC2PIOMSKL, mask);
211 MSC_READ(MSC01_PCI_SC2PIOMAPL, map);
212 msc_io_resource.start = map & mask;
213 msc_io_resource.end = (map & mask) | ~mask;
214 msc_controller.io_offset = 0;
215 ioport_resource.end = ~mask;
216
217 /* If ranges overlap I/O takes precedence. */
218 start = start & mask;
219 end = start | ~mask;
220 if ((start >= msc_mem_resource.start &&
221 start <= msc_mem_resource.end) ||
222 (end >= msc_mem_resource.start &&
223 end <= msc_mem_resource.end)) {
224 /* Use the larger space. */
225 start = max(start, msc_mem_resource.start);
226 end = min(end, msc_mem_resource.end);
227 if (start - msc_mem_resource.start >=
228 msc_mem_resource.end - end)
229 msc_mem_resource.end = start - 1;
230 else
231 msc_mem_resource.start = end + 1;
232 }
233
150 controller = &msc_controller; 234 controller = &msc_controller;
151 break; 235 break;
152 default: 236 default:
153 return; 237 return;
154 } 238 }
155 239
240 if (controller->io_resource->start < 0x00001000UL) /* FIXME */
241 controller->io_resource->start = 0x00001000UL;
242
243 iomem_resource.end &= 0xfffffffffULL; /* 64 GB */
156 ioport_resource.end = controller->io_resource->end; 244 ioport_resource.end = controller->io_resource->end;
157 245
158 register_pci_controller (controller); 246 register_pci_controller (controller);
diff --git a/arch/mips/pci/ops-bonito64.c b/arch/mips/pci/ops-bonito64.c
index 4b4e086a7eb1..dc35270b65a2 100644
--- a/arch/mips/pci/ops-bonito64.c
+++ b/arch/mips/pci/ops-bonito64.c
@@ -1,6 +1,8 @@
1/* 1/*
2 * Carsten Langgaard, carstenl@mips.com 2 * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc.
3 * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved. 3 * All rights reserved.
4 * Authors: Carsten Langgaard <carstenl@mips.com>
5 * Maciej W. Rozycki <macro@mips.com>
4 * 6 *
5 * This program is free software; you can distribute it and/or modify it 7 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as 8 * under the terms of the GNU General Public License (Version 2) as
@@ -17,7 +19,6 @@
17 * 19 *
18 * MIPS boards specific PCI support. 20 * MIPS boards specific PCI support.
19 */ 21 */
20#include <linux/config.h>
21#include <linux/types.h> 22#include <linux/types.h>
22#include <linux/pci.h> 23#include <linux/pci.h>
23#include <linux/kernel.h> 24#include <linux/kernel.h>
@@ -57,13 +58,6 @@ static int bonito64_pcibios_config_access(unsigned char access_type,
57 return -1; 58 return -1;
58 } 59 }
59 60
60#ifdef CONFIG_MIPS_BOARDS_GEN
61 if ((busnum == 0) && (PCI_SLOT(devfn) == 17)) {
62 /* MIPS Core boards have Bonito connected as device 17 */
63 return -1;
64 }
65#endif
66
67 /* Clear cause register bits */ 61 /* Clear cause register bits */
68 BONITO_PCICMD |= (BONITO_PCICMD_MABORT_CLR | 62 BONITO_PCICMD |= (BONITO_PCICMD_MABORT_CLR |
69 BONITO_PCICMD_MTABORT_CLR); 63 BONITO_PCICMD_MTABORT_CLR);
diff --git a/arch/mips/pci/ops-gt64120.c b/arch/mips/pci/ops-gt64120.c
index 7b99dfa33dfc..6335844d607a 100644
--- a/arch/mips/pci/ops-gt64120.c
+++ b/arch/mips/pci/ops-gt64120.c
@@ -1,6 +1,8 @@
1/* 1/*
2 * Carsten Langgaard, carstenl@mips.com 2 * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc.
3 * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved. 3 * All rights reserved.
4 * Authors: Carsten Langgaard <carstenl@mips.com>
5 * Maciej W. Rozycki <macro@mips.com>
4 * 6 *
5 * This program is free software; you can distribute it and/or modify it 7 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as 8 * under the terms of the GNU General Public License (Version 2) as
@@ -43,10 +45,6 @@ static int gt64120_pcibios_config_access(unsigned char access_type,
43 unsigned char busnum = bus->number; 45 unsigned char busnum = bus->number;
44 u32 intr; 46 u32 intr;
45 47
46 if ((busnum == 0) && (PCI_SLOT(devfn) == 0))
47 /* Galileo itself is devfn 0, don't move it around */
48 return -1;
49
50 if ((busnum == 0) && (devfn >= PCI_DEVFN(31, 0))) 48 if ((busnum == 0) && (devfn >= PCI_DEVFN(31, 0)))
51 return -1; /* Because of a bug in the galileo (for slot 31). */ 49 return -1; /* Because of a bug in the galileo (for slot 31). */
52 50
diff --git a/arch/mips/pci/ops-msc.c b/arch/mips/pci/ops-msc.c
index 7bc099643a9d..5d9fbb0f4670 100644
--- a/arch/mips/pci/ops-msc.c
+++ b/arch/mips/pci/ops-msc.c
@@ -21,7 +21,6 @@
21 * MIPS boards specific PCI support. 21 * MIPS boards specific PCI support.
22 * 22 *
23 */ 23 */
24#include <linux/config.h>
25#include <linux/types.h> 24#include <linux/types.h>
26#include <linux/pci.h> 25#include <linux/pci.h>
27#include <linux/kernel.h> 26#include <linux/kernel.h>
@@ -49,34 +48,17 @@ static int msc_pcibios_config_access(unsigned char access_type,
49 struct pci_bus *bus, unsigned int devfn, int where, u32 * data) 48 struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
50{ 49{
51 unsigned char busnum = bus->number; 50 unsigned char busnum = bus->number;
52 unsigned char type;
53 u32 intr; 51 u32 intr;
54 52
55#ifdef CONFIG_MIPS_BOARDS_GEN
56 if ((busnum == 0) && (PCI_SLOT(devfn) == 17)) {
57 /* MIPS Core boards have SOCit connected as device 17 */
58 return -1;
59 }
60#endif
61
62 /* Clear status register bits. */ 53 /* Clear status register bits. */
63 MSC_WRITE(MSC01_PCI_INTSTAT, 54 MSC_WRITE(MSC01_PCI_INTSTAT,
64 (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT)); 55 (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT));
65 56
66 /* Setup address */
67 if (busnum == 0)
68 type = 0; /* Type 0 */
69 else
70 type = 1; /* Type 1 */
71
72 MSC_WRITE(MSC01_PCI_CFGADDR, 57 MSC_WRITE(MSC01_PCI_CFGADDR,
73 ((busnum << MSC01_PCI_CFGADDR_BNUM_SHF) | 58 ((busnum << MSC01_PCI_CFGADDR_BNUM_SHF) |
74 (PCI_SLOT(devfn) << MSC01_PCI_CFGADDR_DNUM_SHF) 59 (PCI_SLOT(devfn) << MSC01_PCI_CFGADDR_DNUM_SHF) |
75 | (PCI_FUNC(devfn) << 60 (PCI_FUNC(devfn) << MSC01_PCI_CFGADDR_FNUM_SHF) |
76 MSC01_PCI_CFGADDR_FNUM_SHF) | ((where / 61 ((where / 4) << MSC01_PCI_CFGADDR_RNUM_SHF)));
77 4) <<
78 MSC01_PCI_CFGADDR_RNUM_SHF)
79 | (type)));
80 62
81 /* Perform access */ 63 /* Perform access */
82 if (access_type == PCI_ACCESS_WRITE) 64 if (access_type == PCI_ACCESS_WRITE)
@@ -86,15 +68,12 @@ static int msc_pcibios_config_access(unsigned char access_type,
86 68
87 /* Detect Master/Target abort */ 69 /* Detect Master/Target abort */
88 MSC_READ(MSC01_PCI_INTSTAT, intr); 70 MSC_READ(MSC01_PCI_INTSTAT, intr);
89 if (intr & (MSC01_PCI_INTCFG_MA_BIT | 71 if (intr & (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT)) {
90 MSC01_PCI_INTCFG_TA_BIT)) {
91 /* Error occurred */ 72 /* Error occurred */
92 73
93 /* Clear bits */ 74 /* Clear bits */
94 MSC_READ(MSC01_PCI_INTSTAT, intr);
95 MSC_WRITE(MSC01_PCI_INTSTAT, 75 MSC_WRITE(MSC01_PCI_INTSTAT,
96 (MSC01_PCI_INTCFG_MA_BIT | 76 (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT));
97 MSC01_PCI_INTCFG_TA_BIT));
98 77
99 return -1; 78 return -1;
100 } 79 }
diff --git a/include/asm-mips/mips-boards/msc01_pci.h b/include/asm-mips/mips-boards/msc01_pci.h
index 6b2a87a38f4b..8eaefb837b9d 100644
--- a/include/asm-mips/mips-boards/msc01_pci.h
+++ b/include/asm-mips/mips-boards/msc01_pci.h
@@ -1,8 +1,9 @@
1/* 1/*
2 * PCI Register definitions for the MIPS System Controller. 2 * PCI Register definitions for the MIPS System Controller.
3 * 3 *
4 * Carsten Langgaard, carstenl@mips.com 4 * Copyright (C) 2002, 2005 MIPS Technologies, Inc. All rights reserved.
5 * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. 5 * Authors: Carsten Langgaard <carstenl@mips.com>
6 * Maciej W. Rozycki <macro@mips.com>
6 * 7 *
7 * This file is subject to the terms and conditions of the GNU General Public 8 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive 9 * License. See the file "COPYING" in the main directory of this archive
@@ -29,22 +30,22 @@
29#define MSC01_PCI_CFGADDR_OFS 0x0610 30#define MSC01_PCI_CFGADDR_OFS 0x0610
30#define MSC01_PCI_CFGDATA_OFS 0x0618 31#define MSC01_PCI_CFGDATA_OFS 0x0618
31#define MSC01_PCI_IACK_OFS 0x0620 32#define MSC01_PCI_IACK_OFS 0x0620
32#define MSC01_PCI_HEAD0_OFS 0x2000 /* DevID, VendorID */ 33#define MSC01_PCI_HEAD0_OFS 0x2000 /* DevID, VendorID */
33#define MSC01_PCI_HEAD1_OFS 0x2008 /* Status, Command */ 34#define MSC01_PCI_HEAD1_OFS 0x2008 /* Status, Command */
34#define MSC01_PCI_HEAD2_OFS 0x2010 /* Class code, RevID */ 35#define MSC01_PCI_HEAD2_OFS 0x2010 /* Class code, RevID */
35#define MSC01_PCI_HEAD3_OFS 0x2018 /* bist, header, latency */ 36#define MSC01_PCI_HEAD3_OFS 0x2018 /* bist, header, latency */
36#define MSC01_PCI_HEAD4_OFS 0x2020 /* BAR 0 */ 37#define MSC01_PCI_HEAD4_OFS 0x2020 /* BAR 0 */
37#define MSC01_PCI_HEAD5_OFS 0x2028 /* BAR 1 */ 38#define MSC01_PCI_HEAD5_OFS 0x2028 /* BAR 1 */
38#define MSC01_PCI_HEAD6_OFS 0x2030 /* BAR 2 */ 39#define MSC01_PCI_HEAD6_OFS 0x2030 /* BAR 2 */
39#define MSC01_PCI_HEAD7_OFS 0x2038 /* BAR 3 */ 40#define MSC01_PCI_HEAD7_OFS 0x2038 /* BAR 3 */
40#define MSC01_PCI_HEAD8_OFS 0x2040 /* BAR 4 */ 41#define MSC01_PCI_HEAD8_OFS 0x2040 /* BAR 4 */
41#define MSC01_PCI_HEAD9_OFS 0x2048 /* BAR 5 */ 42#define MSC01_PCI_HEAD9_OFS 0x2048 /* BAR 5 */
42#define MSC01_PCI_HEAD10_OFS 0x2050 /* CardBus CIS Ptr */ 43#define MSC01_PCI_HEAD10_OFS 0x2050 /* CardBus CIS Ptr */
43#define MSC01_PCI_HEAD11_OFS 0x2058 /* SubSystem ID, -VendorID */ 44#define MSC01_PCI_HEAD11_OFS 0x2058 /* SubSystem ID, -VendorID */
44#define MSC01_PCI_HEAD12_OFS 0x2060 /* ROM BAR */ 45#define MSC01_PCI_HEAD12_OFS 0x2060 /* ROM BAR */
45#define MSC01_PCI_HEAD13_OFS 0x2068 /* Capabilities ptr */ 46#define MSC01_PCI_HEAD13_OFS 0x2068 /* Capabilities ptr */
46#define MSC01_PCI_HEAD14_OFS 0x2070 /* reserved */ 47#define MSC01_PCI_HEAD14_OFS 0x2070 /* reserved */
47#define MSC01_PCI_HEAD15_OFS 0x2078 /* Maxl, ming, intpin, int */ 48#define MSC01_PCI_HEAD15_OFS 0x2078 /* Maxl, ming, intpin, int */
48#define MSC01_PCI_BAR0_OFS 0x2220 49#define MSC01_PCI_BAR0_OFS 0x2220
49#define MSC01_PCI_CFG_OFS 0x2380 50#define MSC01_PCI_CFG_OFS 0x2380
50#define MSC01_PCI_SWAP_OFS 0x2388 51#define MSC01_PCI_SWAP_OFS 0x2388
@@ -86,73 +87,73 @@
86#define MSC01_PCI_P2SCMAPL_MAP_SHF 24 87#define MSC01_PCI_P2SCMAPL_MAP_SHF 24
87#define MSC01_PCI_P2SCMAPL_MAP_MSK 0xff000000 88#define MSC01_PCI_P2SCMAPL_MAP_MSK 0xff000000
88 89
89#define MSC01_PCI_INTCFG_RST_SHF 10 90#define MSC01_PCI_INTCFG_RST_SHF 10
90#define MSC01_PCI_INTCFG_RST_MSK 0x00000400 91#define MSC01_PCI_INTCFG_RST_MSK 0x00000400
91#define MSC01_PCI_INTCFG_RST_BIT 0x00000400 92#define MSC01_PCI_INTCFG_RST_BIT 0x00000400
92#define MSC01_PCI_INTCFG_MWE_SHF 9 93#define MSC01_PCI_INTCFG_MWE_SHF 9
93#define MSC01_PCI_INTCFG_MWE_MSK 0x00000200 94#define MSC01_PCI_INTCFG_MWE_MSK 0x00000200
94#define MSC01_PCI_INTCFG_MWE_BIT 0x00000200 95#define MSC01_PCI_INTCFG_MWE_BIT 0x00000200
95#define MSC01_PCI_INTCFG_DTO_SHF 8 96#define MSC01_PCI_INTCFG_DTO_SHF 8
96#define MSC01_PCI_INTCFG_DTO_MSK 0x00000100 97#define MSC01_PCI_INTCFG_DTO_MSK 0x00000100
97#define MSC01_PCI_INTCFG_DTO_BIT 0x00000100 98#define MSC01_PCI_INTCFG_DTO_BIT 0x00000100
98#define MSC01_PCI_INTCFG_MA_SHF 7 99#define MSC01_PCI_INTCFG_MA_SHF 7
99#define MSC01_PCI_INTCFG_MA_MSK 0x00000080 100#define MSC01_PCI_INTCFG_MA_MSK 0x00000080
100#define MSC01_PCI_INTCFG_MA_BIT 0x00000080 101#define MSC01_PCI_INTCFG_MA_BIT 0x00000080
101#define MSC01_PCI_INTCFG_TA_SHF 6 102#define MSC01_PCI_INTCFG_TA_SHF 6
102#define MSC01_PCI_INTCFG_TA_MSK 0x00000040 103#define MSC01_PCI_INTCFG_TA_MSK 0x00000040
103#define MSC01_PCI_INTCFG_TA_BIT 0x00000040 104#define MSC01_PCI_INTCFG_TA_BIT 0x00000040
104#define MSC01_PCI_INTCFG_RTY_SHF 5 105#define MSC01_PCI_INTCFG_RTY_SHF 5
105#define MSC01_PCI_INTCFG_RTY_MSK 0x00000020 106#define MSC01_PCI_INTCFG_RTY_MSK 0x00000020
106#define MSC01_PCI_INTCFG_RTY_BIT 0x00000020 107#define MSC01_PCI_INTCFG_RTY_BIT 0x00000020
107#define MSC01_PCI_INTCFG_MWP_SHF 4 108#define MSC01_PCI_INTCFG_MWP_SHF 4
108#define MSC01_PCI_INTCFG_MWP_MSK 0x00000010 109#define MSC01_PCI_INTCFG_MWP_MSK 0x00000010
109#define MSC01_PCI_INTCFG_MWP_BIT 0x00000010 110#define MSC01_PCI_INTCFG_MWP_BIT 0x00000010
110#define MSC01_PCI_INTCFG_MRP_SHF 3 111#define MSC01_PCI_INTCFG_MRP_SHF 3
111#define MSC01_PCI_INTCFG_MRP_MSK 0x00000008 112#define MSC01_PCI_INTCFG_MRP_MSK 0x00000008
112#define MSC01_PCI_INTCFG_MRP_BIT 0x00000008 113#define MSC01_PCI_INTCFG_MRP_BIT 0x00000008
113#define MSC01_PCI_INTCFG_SWP_SHF 2 114#define MSC01_PCI_INTCFG_SWP_SHF 2
114#define MSC01_PCI_INTCFG_SWP_MSK 0x00000004 115#define MSC01_PCI_INTCFG_SWP_MSK 0x00000004
115#define MSC01_PCI_INTCFG_SWP_BIT 0x00000004 116#define MSC01_PCI_INTCFG_SWP_BIT 0x00000004
116#define MSC01_PCI_INTCFG_SRP_SHF 1 117#define MSC01_PCI_INTCFG_SRP_SHF 1
117#define MSC01_PCI_INTCFG_SRP_MSK 0x00000002 118#define MSC01_PCI_INTCFG_SRP_MSK 0x00000002
118#define MSC01_PCI_INTCFG_SRP_BIT 0x00000002 119#define MSC01_PCI_INTCFG_SRP_BIT 0x00000002
119#define MSC01_PCI_INTCFG_SE_SHF 0 120#define MSC01_PCI_INTCFG_SE_SHF 0
120#define MSC01_PCI_INTCFG_SE_MSK 0x00000001 121#define MSC01_PCI_INTCFG_SE_MSK 0x00000001
121#define MSC01_PCI_INTCFG_SE_BIT 0x00000001 122#define MSC01_PCI_INTCFG_SE_BIT 0x00000001
122 123
123#define MSC01_PCI_INTSTAT_RST_SHF 10 124#define MSC01_PCI_INTSTAT_RST_SHF 10
124#define MSC01_PCI_INTSTAT_RST_MSK 0x00000400 125#define MSC01_PCI_INTSTAT_RST_MSK 0x00000400
125#define MSC01_PCI_INTSTAT_RST_BIT 0x00000400 126#define MSC01_PCI_INTSTAT_RST_BIT 0x00000400
126#define MSC01_PCI_INTSTAT_MWE_SHF 9 127#define MSC01_PCI_INTSTAT_MWE_SHF 9
127#define MSC01_PCI_INTSTAT_MWE_MSK 0x00000200 128#define MSC01_PCI_INTSTAT_MWE_MSK 0x00000200
128#define MSC01_PCI_INTSTAT_MWE_BIT 0x00000200 129#define MSC01_PCI_INTSTAT_MWE_BIT 0x00000200
129#define MSC01_PCI_INTSTAT_DTO_SHF 8 130#define MSC01_PCI_INTSTAT_DTO_SHF 8
130#define MSC01_PCI_INTSTAT_DTO_MSK 0x00000100 131#define MSC01_PCI_INTSTAT_DTO_MSK 0x00000100
131#define MSC01_PCI_INTSTAT_DTO_BIT 0x00000100 132#define MSC01_PCI_INTSTAT_DTO_BIT 0x00000100
132#define MSC01_PCI_INTSTAT_MA_SHF 7 133#define MSC01_PCI_INTSTAT_MA_SHF 7
133#define MSC01_PCI_INTSTAT_MA_MSK 0x00000080 134#define MSC01_PCI_INTSTAT_MA_MSK 0x00000080
134#define MSC01_PCI_INTSTAT_MA_BIT 0x00000080 135#define MSC01_PCI_INTSTAT_MA_BIT 0x00000080
135#define MSC01_PCI_INTSTAT_TA_SHF 6 136#define MSC01_PCI_INTSTAT_TA_SHF 6
136#define MSC01_PCI_INTSTAT_TA_MSK 0x00000040 137#define MSC01_PCI_INTSTAT_TA_MSK 0x00000040
137#define MSC01_PCI_INTSTAT_TA_BIT 0x00000040 138#define MSC01_PCI_INTSTAT_TA_BIT 0x00000040
138#define MSC01_PCI_INTSTAT_RTY_SHF 5 139#define MSC01_PCI_INTSTAT_RTY_SHF 5
139#define MSC01_PCI_INTSTAT_RTY_MSK 0x00000020 140#define MSC01_PCI_INTSTAT_RTY_MSK 0x00000020
140#define MSC01_PCI_INTSTAT_RTY_BIT 0x00000020 141#define MSC01_PCI_INTSTAT_RTY_BIT 0x00000020
141#define MSC01_PCI_INTSTAT_MWP_SHF 4 142#define MSC01_PCI_INTSTAT_MWP_SHF 4
142#define MSC01_PCI_INTSTAT_MWP_MSK 0x00000010 143#define MSC01_PCI_INTSTAT_MWP_MSK 0x00000010
143#define MSC01_PCI_INTSTAT_MWP_BIT 0x00000010 144#define MSC01_PCI_INTSTAT_MWP_BIT 0x00000010
144#define MSC01_PCI_INTSTAT_MRP_SHF 3 145#define MSC01_PCI_INTSTAT_MRP_SHF 3
145#define MSC01_PCI_INTSTAT_MRP_MSK 0x00000008 146#define MSC01_PCI_INTSTAT_MRP_MSK 0x00000008
146#define MSC01_PCI_INTSTAT_MRP_BIT 0x00000008 147#define MSC01_PCI_INTSTAT_MRP_BIT 0x00000008
147#define MSC01_PCI_INTSTAT_SWP_SHF 2 148#define MSC01_PCI_INTSTAT_SWP_SHF 2
148#define MSC01_PCI_INTSTAT_SWP_MSK 0x00000004 149#define MSC01_PCI_INTSTAT_SWP_MSK 0x00000004
149#define MSC01_PCI_INTSTAT_SWP_BIT 0x00000004 150#define MSC01_PCI_INTSTAT_SWP_BIT 0x00000004
150#define MSC01_PCI_INTSTAT_SRP_SHF 1 151#define MSC01_PCI_INTSTAT_SRP_SHF 1
151#define MSC01_PCI_INTSTAT_SRP_MSK 0x00000002 152#define MSC01_PCI_INTSTAT_SRP_MSK 0x00000002
152#define MSC01_PCI_INTSTAT_SRP_BIT 0x00000002 153#define MSC01_PCI_INTSTAT_SRP_BIT 0x00000002
153#define MSC01_PCI_INTSTAT_SE_SHF 0 154#define MSC01_PCI_INTSTAT_SE_SHF 0
154#define MSC01_PCI_INTSTAT_SE_MSK 0x00000001 155#define MSC01_PCI_INTSTAT_SE_MSK 0x00000001
155#define MSC01_PCI_INTSTAT_SE_BIT 0x00000001 156#define MSC01_PCI_INTSTAT_SE_BIT 0x00000001
156 157
157#define MSC01_PCI_CFGADDR_BNUM_SHF 16 158#define MSC01_PCI_CFGADDR_BNUM_SHF 16
158#define MSC01_PCI_CFGADDR_BNUM_MSK 0x00ff0000 159#define MSC01_PCI_CFGADDR_BNUM_MSK 0x00ff0000
@@ -167,29 +168,29 @@
167#define MSC01_PCI_CFGDATA_DATA_MSK 0xffffffff 168#define MSC01_PCI_CFGDATA_DATA_MSK 0xffffffff
168 169
169/* The defines below are ONLY valid for a MEM bar! */ 170/* The defines below are ONLY valid for a MEM bar! */
170#define MSC01_PCI_BAR0_SIZE_SHF 4 171#define MSC01_PCI_BAR0_SIZE_SHF 4
171#define MSC01_PCI_BAR0_SIZE_MSK 0xfffffff0 172#define MSC01_PCI_BAR0_SIZE_MSK 0xfffffff0
172#define MSC01_PCI_BAR0_P_SHF 3 173#define MSC01_PCI_BAR0_P_SHF 3
173#define MSC01_PCI_BAR0_P_MSK 0x00000008 174#define MSC01_PCI_BAR0_P_MSK 0x00000008
174#define MSC01_PCI_BAR0_P_BIT MSC01_PCI_BAR0_P_MSK 175#define MSC01_PCI_BAR0_P_BIT MSC01_PCI_BAR0_P_MSK
175#define MSC01_PCI_BAR0_D_SHF 1 176#define MSC01_PCI_BAR0_D_SHF 1
176#define MSC01_PCI_BAR0_D_MSK 0x00000006 177#define MSC01_PCI_BAR0_D_MSK 0x00000006
177#define MSC01_PCI_BAR0_T_SHF 0 178#define MSC01_PCI_BAR0_T_SHF 0
178#define MSC01_PCI_BAR0_T_MSK 0x00000001 179#define MSC01_PCI_BAR0_T_MSK 0x00000001
179#define MSC01_PCI_BAR0_T_BIT MSC01_PCI_BAR0_T_MSK 180#define MSC01_PCI_BAR0_T_BIT MSC01_PCI_BAR0_T_MSK
180 181
181 182
182#define MSC01_PCI_CFG_RA_SHF 17 183#define MSC01_PCI_CFG_RA_SHF 17
183#define MSC01_PCI_CFG_RA_MSK 0x00020000 184#define MSC01_PCI_CFG_RA_MSK 0x00020000
184#define MSC01_PCI_CFG_RA_BIT MSC01_PCI_CFG_RA_MSK 185#define MSC01_PCI_CFG_RA_BIT MSC01_PCI_CFG_RA_MSK
185#define MSC01_PCI_CFG_G_SHF 16 186#define MSC01_PCI_CFG_G_SHF 16
186#define MSC01_PCI_CFG_G_MSK 0x00010000 187#define MSC01_PCI_CFG_G_MSK 0x00010000
187#define MSC01_PCI_CFG_G_BIT MSC01_PCI_CFG_G_MSK 188#define MSC01_PCI_CFG_G_BIT MSC01_PCI_CFG_G_MSK
188#define MSC01_PCI_CFG_EN_SHF 15 189#define MSC01_PCI_CFG_EN_SHF 15
189#define MSC01_PCI_CFG_EN_MSK 0x00008000 190#define MSC01_PCI_CFG_EN_MSK 0x00008000
190#define MSC01_PCI_CFG_EN_BIT MSC01_PCI_CFG_EN_MSK 191#define MSC01_PCI_CFG_EN_BIT MSC01_PCI_CFG_EN_MSK
191#define MSC01_PCI_CFG_MAXRTRY_SHF 0 192#define MSC01_PCI_CFG_MAXRTRY_SHF 0
192#define MSC01_PCI_CFG_MAXRTRY_MSK 0x000000ff 193#define MSC01_PCI_CFG_MAXRTRY_MSK 0x00000fff
193 194
194#define MSC01_PCI_SWAP_IO_SHF 18 195#define MSC01_PCI_SWAP_IO_SHF 18
195#define MSC01_PCI_SWAP_IO_MSK 0x000c0000 196#define MSC01_PCI_SWAP_IO_MSK 0x000c0000
@@ -206,7 +207,7 @@
206 * FIXME - are these macros specific to Malta and co or to the MSC? If the 207 * FIXME - are these macros specific to Malta and co or to the MSC? If the
207 * latter, they should be moved elsewhere. 208 * latter, they should be moved elsewhere.
208 */ 209 */
209#define MIPS_MSC01_PCI_REG_BASE 0x1bd00000 210#define MIPS_MSC01_PCI_REG_BASE 0x1bd00000
210 211
211extern unsigned long _pcictrl_msc; 212extern unsigned long _pcictrl_msc;
212 213
@@ -219,19 +220,19 @@ extern unsigned long _pcictrl_msc;
219 * Registers absolute addresses 220 * Registers absolute addresses
220 */ 221 */
221 222
222#define MSC01_PCI_ID (MSC01_PCI_REG_BASE + MSC01_PCI_ID_OFS) 223#define MSC01_PCI_ID (MSC01_PCI_REG_BASE + MSC01_PCI_ID_OFS)
223#define MSC01_PCI_SC2PMBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMBASL_OFS) 224#define MSC01_PCI_SC2PMBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMBASL_OFS)
224#define MSC01_PCI_SC2PMMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMSKL_OFS) 225#define MSC01_PCI_SC2PMMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMSKL_OFS)
225#define MSC01_PCI_SC2PMMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMAPL_OFS) 226#define MSC01_PCI_SC2PMMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMAPL_OFS)
226#define MSC01_PCI_SC2PIOBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOBASL_OFS) 227#define MSC01_PCI_SC2PIOBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOBASL_OFS)
227#define MSC01_PCI_SC2PIOMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMSKL_OFS) 228#define MSC01_PCI_SC2PIOMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMSKL_OFS)
228#define MSC01_PCI_SC2PIOMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMAPL_OFS) 229#define MSC01_PCI_SC2PIOMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMAPL_OFS)
229#define MSC01_PCI_P2SCMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMSKL_OFS) 230#define MSC01_PCI_P2SCMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMSKL_OFS)
230#define MSC01_PCI_P2SCMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMAPL_OFS) 231#define MSC01_PCI_P2SCMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMAPL_OFS)
231#define MSC01_PCI_INTCFG (MSC01_PCI_REG_BASE + MSC01_PCI_INTCFG_OFS) 232#define MSC01_PCI_INTCFG (MSC01_PCI_REG_BASE + MSC01_PCI_INTCFG_OFS)
232#define MSC01_PCI_INTSTAT (MSC01_PCI_REG_BASE + MSC01_PCI_INTSTAT_OFS) 233#define MSC01_PCI_INTSTAT (MSC01_PCI_REG_BASE + MSC01_PCI_INTSTAT_OFS)
233#define MSC01_PCI_CFGADDR (MSC01_PCI_REG_BASE + MSC01_PCI_CFGADDR_OFS) 234#define MSC01_PCI_CFGADDR (MSC01_PCI_REG_BASE + MSC01_PCI_CFGADDR_OFS)
234#define MSC01_PCI_CFGDATA (MSC01_PCI_REG_BASE + MSC01_PCI_CFGDATA_OFS) 235#define MSC01_PCI_CFGDATA (MSC01_PCI_REG_BASE + MSC01_PCI_CFGDATA_OFS)
235#define MSC01_PCI_IACK (MSC01_PCI_REG_BASE + MSC01_PCI_IACK_OFS) 236#define MSC01_PCI_IACK (MSC01_PCI_REG_BASE + MSC01_PCI_IACK_OFS)
236#define MSC01_PCI_HEAD0 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD0_OFS) 237#define MSC01_PCI_HEAD0 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD0_OFS)
237#define MSC01_PCI_HEAD1 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD1_OFS) 238#define MSC01_PCI_HEAD1 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD1_OFS)
@@ -248,7 +249,7 @@ extern unsigned long _pcictrl_msc;
248#define MSC01_PCI_HEAD12 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) 249#define MSC01_PCI_HEAD12 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
249#define MSC01_PCI_HEAD13 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) 250#define MSC01_PCI_HEAD13 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
250#define MSC01_PCI_HEAD14 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) 251#define MSC01_PCI_HEAD14 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
251#define MSC01_PCI_HEAD15 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) 252#define MSC01_PCI_HEAD15 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
252#define MSC01_PCI_BAR0 (MSC01_PCI_REG_BASE + MSC01_PCI_BAR0_OFS) 253#define MSC01_PCI_BAR0 (MSC01_PCI_REG_BASE + MSC01_PCI_BAR0_OFS)
253#define MSC01_PCI_CFG (MSC01_PCI_REG_BASE + MSC01_PCI_CFG_OFS) 254#define MSC01_PCI_CFG (MSC01_PCI_REG_BASE + MSC01_PCI_CFG_OFS)
254#define MSC01_PCI_SWAP (MSC01_PCI_REG_BASE + MSC01_PCI_SWAP_OFS) 255#define MSC01_PCI_SWAP (MSC01_PCI_REG_BASE + MSC01_PCI_SWAP_OFS)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 20:51:09 -0500