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authorThomas Bogendoerfer <tsbogend@alpha.franken.de>2008-05-29 16:05:07 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-06-16 10:14:48 -0400
commit938b2b14172bd098972df2a5157bfabf161c90e5 (patch)
treef50c7ee265327f6b29905e2c45ed12ecaa4b4492
parent1f34f2e4262bae8a1aa6d8fd6306b07074d33718 (diff)
[MIPS] Malta: Fix build errors for 64-bit kernels
Fix 64-bit Malta by using CKSEG0ADDR and correct casts. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--arch/mips/mips-boards/generic/amon.c4
-rw-r--r--include/asm-mips/gic.h4
2 files changed, 4 insertions, 4 deletions
diff --git a/arch/mips/mips-boards/generic/amon.c b/arch/mips/mips-boards/generic/amon.c
index b7633fda4180..96236bf33838 100644
--- a/arch/mips/mips-boards/generic/amon.c
+++ b/arch/mips/mips-boards/generic/amon.c
@@ -28,7 +28,7 @@
28 28
29int amon_cpu_avail(int cpu) 29int amon_cpu_avail(int cpu)
30{ 30{
31 struct cpulaunch *launch = (struct cpulaunch *)KSEG0ADDR(CPULAUNCH); 31 struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
32 32
33 if (cpu < 0 || cpu >= NCPULAUNCH) { 33 if (cpu < 0 || cpu >= NCPULAUNCH) {
34 pr_debug("avail: cpu%d is out of range\n", cpu); 34 pr_debug("avail: cpu%d is out of range\n", cpu);
@@ -53,7 +53,7 @@ void amon_cpu_start(int cpu,
53 unsigned long gp, unsigned long a0) 53 unsigned long gp, unsigned long a0)
54{ 54{
55 volatile struct cpulaunch *launch = 55 volatile struct cpulaunch *launch =
56 (struct cpulaunch *)KSEG0ADDR(CPULAUNCH); 56 (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
57 57
58 if (!amon_cpu_avail(cpu)) 58 if (!amon_cpu_avail(cpu))
59 return; 59 return;
diff --git a/include/asm-mips/gic.h b/include/asm-mips/gic.h
index 3a492f225f00..954807d9d66a 100644
--- a/include/asm-mips/gic.h
+++ b/include/asm-mips/gic.h
@@ -24,8 +24,8 @@
24 24
25#define MSK(n) ((1 << (n)) - 1) 25#define MSK(n) ((1 << (n)) - 1)
26#define REG32(addr) (*(volatile unsigned int *) (addr)) 26#define REG32(addr) (*(volatile unsigned int *) (addr))
27#define REG(base, offs) REG32((unsigned int)(base) + offs##_##OFS) 27#define REG(base, offs) REG32((unsigned long)(base) + offs##_##OFS)
28#define REGP(base, phys) REG32((unsigned int)(base) + (phys)) 28#define REGP(base, phys) REG32((unsigned long)(base) + (phys))
29 29
30/* Accessors */ 30/* Accessors */
31#define GIC_REG(segment, offset) \ 31#define GIC_REG(segment, offset) \