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authorVille Syrjälä <syrjala@sci.fi>2006-01-09 23:53:27 -0500
committerLinus Torvalds <torvalds@g5.osdl.org>2006-01-10 11:01:48 -0500
commit25163c56ed88a3009e7c1d808d3a052357301d63 (patch)
tree8b70b0c0e0cb1d84b1e9b75ebe57088a52c510ac
parente98cef1e9e0ef0c5c02f6f3daa4da7956ad1c9ea (diff)
[PATCH] atyfb: Set ECP divider
Set ECP (scaler/overlay clock) divider. The limits were taken from the XFree86 ati driver. Signed-off-by: Ville Syrjälä <syrjala@sci.fi> Signed-off-by: Antonino Daplas <adaplas@pol.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat
-rw-r--r--drivers/video/aty/atyfb.h1
-rw-r--r--drivers/video/aty/atyfb_base.c90
-rw-r--r--drivers/video/aty/mach64_ct.c17
3 files changed, 63 insertions, 45 deletions
diff --git a/drivers/video/aty/atyfb.h b/drivers/video/aty/atyfb.h
index 71d30b5ea819..e9b7a64c1ac4 100644
--- a/drivers/video/aty/atyfb.h
+++ b/drivers/video/aty/atyfb.h
@@ -50,6 +50,7 @@ struct pll_info {
50 int sclk, mclk, mclk_pm, xclk; 50 int sclk, mclk, mclk_pm, xclk;
51 int ref_div; 51 int ref_div;
52 int ref_clk; 52 int ref_clk;
53 int ecp_max;
53}; 54};
54 55
55typedef struct { 56typedef struct {
diff --git a/drivers/video/aty/atyfb_base.c b/drivers/video/aty/atyfb_base.c
index ea3eebcb0236..209d44680862 100644
--- a/drivers/video/aty/atyfb_base.c
+++ b/drivers/video/aty/atyfb_base.c
@@ -368,58 +368,58 @@ static unsigned long phys_guiregbase[FB_MAX] __initdata = { 0, };
368static struct { 368static struct {
369 u16 pci_id; 369 u16 pci_id;
370 const char *name; 370 const char *name;
371 int pll, mclk, xclk; 371 int pll, mclk, xclk, ecp_max;
372 u32 features; 372 u32 features;
373} aty_chips[] __devinitdata = { 373} aty_chips[] __devinitdata = {
374#ifdef CONFIG_FB_ATY_GX 374#ifdef CONFIG_FB_ATY_GX
375 /* Mach64 GX */ 375 /* Mach64 GX */
376 { PCI_CHIP_MACH64GX, "ATI888GX00 (Mach64 GX)", 135, 50, 50, ATI_CHIP_88800GX }, 376 { PCI_CHIP_MACH64GX, "ATI888GX00 (Mach64 GX)", 135, 50, 50, 0, ATI_CHIP_88800GX },
377 { PCI_CHIP_MACH64CX, "ATI888CX00 (Mach64 CX)", 135, 50, 50, ATI_CHIP_88800CX }, 377 { PCI_CHIP_MACH64CX, "ATI888CX00 (Mach64 CX)", 135, 50, 50, 0, ATI_CHIP_88800CX },
378#endif /* CONFIG_FB_ATY_GX */ 378#endif /* CONFIG_FB_ATY_GX */
379 379
380#ifdef CONFIG_FB_ATY_CT 380#ifdef CONFIG_FB_ATY_CT
381 { PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, ATI_CHIP_264CT }, 381 { PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, 0, ATI_CHIP_264CT },
382 { PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, ATI_CHIP_264ET }, 382 { PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, 0, ATI_CHIP_264ET },
383 { PCI_CHIP_MACH64VT, "ATI264VT? (Mach64 VT)", 170, 67, 67, ATI_CHIP_264VT }, 383 { PCI_CHIP_MACH64VT, "ATI264VT? (Mach64 VT)", 170, 67, 67, 80, ATI_CHIP_264VT },
384 { PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, ATI_CHIP_264GT }, 384 { PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, 80, ATI_CHIP_264GT },
385 /* FIXME { ...ATI_264GU, maybe ATI_CHIP_264GTDVD }, */ 385 /* FIXME { ...ATI_264GU, maybe ATI_CHIP_264GTDVD }, */
386 { PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GTB)", 200, 67, 67, ATI_CHIP_264GTB }, 386 { PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GTB)", 200, 67, 67, 100, ATI_CHIP_264GTB },
387 { PCI_CHIP_MACH64VU, "ATI264VTB (Mach64 VU)", 200, 67, 67, ATI_CHIP_264VT3 }, 387 { PCI_CHIP_MACH64VU, "ATI264VTB (Mach64 VU)", 200, 67, 67, 80, ATI_CHIP_264VT3 },
388 388
389 { PCI_CHIP_MACH64LT, "3D RAGE LT (Mach64 LT)", 135, 63, 63, ATI_CHIP_264LT }, 389 { PCI_CHIP_MACH64LT, "3D RAGE LT (Mach64 LT)", 135, 63, 63, 0, ATI_CHIP_264LT },
390 /* FIXME chipset maybe ATI_CHIP_264LTPRO ? */ 390 /* FIXME chipset maybe ATI_CHIP_264LTPRO ? */
391 { PCI_CHIP_MACH64LG, "3D RAGE LT-G (Mach64 LG)", 230, 63, 63, ATI_CHIP_264LTG | M64F_LT_LCD_REGS | M64F_G3_PB_1024x768 }, 391 { PCI_CHIP_MACH64LG, "3D RAGE LT-G (Mach64 LG)", 230, 63, 63, 100, ATI_CHIP_264LTG | M64F_LT_LCD_REGS | M64F_G3_PB_1024x768 },
392 392
393 { PCI_CHIP_MACH64VV, "ATI264VT4 (Mach64 VV)", 230, 83, 83, ATI_CHIP_264VT4 }, 393 { PCI_CHIP_MACH64VV, "ATI264VT4 (Mach64 VV)", 230, 83, 83, 100, ATI_CHIP_264VT4 },
394 394
395 { PCI_CHIP_MACH64GV, "3D RAGE IIC (Mach64 GV, PCI)", 230, 83, 83, ATI_CHIP_264GT2C }, 395 { PCI_CHIP_MACH64GV, "3D RAGE IIC (Mach64 GV, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
396 { PCI_CHIP_MACH64GW, "3D RAGE IIC (Mach64 GW, AGP)", 230, 83, 83, ATI_CHIP_264GT2C }, 396 { PCI_CHIP_MACH64GW, "3D RAGE IIC (Mach64 GW, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
397 { PCI_CHIP_MACH64GY, "3D RAGE IIC (Mach64 GY, PCI)", 230, 83, 83, ATI_CHIP_264GT2C }, 397 { PCI_CHIP_MACH64GY, "3D RAGE IIC (Mach64 GY, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
398 { PCI_CHIP_MACH64GZ, "3D RAGE IIC (Mach64 GZ, AGP)", 230, 83, 83, ATI_CHIP_264GT2C }, 398 { PCI_CHIP_MACH64GZ, "3D RAGE IIC (Mach64 GZ, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
399 399
400 { PCI_CHIP_MACH64GB, "3D RAGE PRO (Mach64 GB, BGA, AGP)", 230, 100, 100, ATI_CHIP_264GTPRO }, 400 { PCI_CHIP_MACH64GB, "3D RAGE PRO (Mach64 GB, BGA, AGP)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
401 { PCI_CHIP_MACH64GD, "3D RAGE PRO (Mach64 GD, BGA, AGP 1x)", 230, 100, 100, ATI_CHIP_264GTPRO }, 401 { PCI_CHIP_MACH64GD, "3D RAGE PRO (Mach64 GD, BGA, AGP 1x)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
402 { PCI_CHIP_MACH64GI, "3D RAGE PRO (Mach64 GI, BGA, PCI)", 230, 100, 100, ATI_CHIP_264GTPRO | M64F_MAGIC_VRAM_SIZE }, 402 { PCI_CHIP_MACH64GI, "3D RAGE PRO (Mach64 GI, BGA, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO | M64F_MAGIC_VRAM_SIZE },
403 { PCI_CHIP_MACH64GP, "3D RAGE PRO (Mach64 GP, PQFP, PCI)", 230, 100, 100, ATI_CHIP_264GTPRO }, 403 { PCI_CHIP_MACH64GP, "3D RAGE PRO (Mach64 GP, PQFP, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
404 { PCI_CHIP_MACH64GQ, "3D RAGE PRO (Mach64 GQ, PQFP, PCI, limited 3D)", 230, 100, 100, ATI_CHIP_264GTPRO }, 404 { PCI_CHIP_MACH64GQ, "3D RAGE PRO (Mach64 GQ, PQFP, PCI, limited 3D)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
405 405
406 { PCI_CHIP_MACH64LB, "3D RAGE LT PRO (Mach64 LB, AGP)", 236, 75, 100, ATI_CHIP_264LTPRO }, 406 { PCI_CHIP_MACH64LB, "3D RAGE LT PRO (Mach64 LB, AGP)", 236, 75, 100, 135, ATI_CHIP_264LTPRO },
407 { PCI_CHIP_MACH64LD, "3D RAGE LT PRO (Mach64 LD, AGP)", 230, 100, 100, ATI_CHIP_264LTPRO }, 407 { PCI_CHIP_MACH64LD, "3D RAGE LT PRO (Mach64 LD, AGP)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
408 { PCI_CHIP_MACH64LI, "3D RAGE LT PRO (Mach64 LI, PCI)", 230, 100, 100, ATI_CHIP_264LTPRO | M64F_G3_PB_1_1 | M64F_G3_PB_1024x768 }, 408 { PCI_CHIP_MACH64LI, "3D RAGE LT PRO (Mach64 LI, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1_1 | M64F_G3_PB_1024x768 },
409 { PCI_CHIP_MACH64LP, "3D RAGE LT PRO (Mach64 LP, PCI)", 230, 100, 100, ATI_CHIP_264LTPRO }, 409 { PCI_CHIP_MACH64LP, "3D RAGE LT PRO (Mach64 LP, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
410 { PCI_CHIP_MACH64LQ, "3D RAGE LT PRO (Mach64 LQ, PCI)", 230, 100, 100, ATI_CHIP_264LTPRO }, 410 { PCI_CHIP_MACH64LQ, "3D RAGE LT PRO (Mach64 LQ, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
411 411
412 { PCI_CHIP_MACH64GM, "3D RAGE XL (Mach64 GM, AGP)", 230, 83, 63, ATI_CHIP_264XL }, 412 { PCI_CHIP_MACH64GM, "3D RAGE XL (Mach64 GM, AGP)", 230, 83, 63, 135, ATI_CHIP_264XL },
413 { PCI_CHIP_MACH64GN, "3D RAGE XL (Mach64 GN, AGP)", 230, 83, 63, ATI_CHIP_264XL }, 413 { PCI_CHIP_MACH64GN, "3D RAGE XL (Mach64 GN, AGP)", 230, 83, 63, 135, ATI_CHIP_264XL },
414 { PCI_CHIP_MACH64GO, "3D RAGE XL (Mach64 GO, PCI-66/BGA)", 230, 83, 63, ATI_CHIP_264XL }, 414 { PCI_CHIP_MACH64GO, "3D RAGE XL (Mach64 GO, PCI-66/BGA)", 230, 83, 63, 135, ATI_CHIP_264XL },
415 { PCI_CHIP_MACH64GR, "3D RAGE XL (Mach64 GR, PCI-33MHz)", 235, 83, 63, ATI_CHIP_264XL | M64F_SDRAM_MAGIC_PLL }, 415 { PCI_CHIP_MACH64GR, "3D RAGE XL (Mach64 GR, PCI-33MHz)", 230, 83, 63, 135, ATI_CHIP_264XL | M64F_SDRAM_MAGIC_PLL },
416 { PCI_CHIP_MACH64GL, "3D RAGE XL (Mach64 GL, PCI)", 230, 83, 63, ATI_CHIP_264XL }, 416 { PCI_CHIP_MACH64GL, "3D RAGE XL (Mach64 GL, PCI)", 230, 83, 63, 135, ATI_CHIP_264XL },
417 { PCI_CHIP_MACH64GS, "3D RAGE XL (Mach64 GS, PCI)", 230, 83, 63, ATI_CHIP_264XL }, 417 { PCI_CHIP_MACH64GS, "3D RAGE XL (Mach64 GS, PCI)", 230, 83, 63, 135, ATI_CHIP_264XL },
418 418
419 { PCI_CHIP_MACH64LM, "3D RAGE Mobility P/M (Mach64 LM, AGP 2x)", 230, 83, 125, ATI_CHIP_MOBILITY }, 419 { PCI_CHIP_MACH64LM, "3D RAGE Mobility P/M (Mach64 LM, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
420 { PCI_CHIP_MACH64LN, "3D RAGE Mobility L (Mach64 LN, AGP 2x)", 230, 83, 125, ATI_CHIP_MOBILITY }, 420 { PCI_CHIP_MACH64LN, "3D RAGE Mobility L (Mach64 LN, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
421 { PCI_CHIP_MACH64LR, "3D RAGE Mobility P/M (Mach64 LR, PCI)", 230, 83, 125, ATI_CHIP_MOBILITY }, 421 { PCI_CHIP_MACH64LR, "3D RAGE Mobility P/M (Mach64 LR, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
422 { PCI_CHIP_MACH64LS, "3D RAGE Mobility L (Mach64 LS, PCI)", 230, 83, 125, ATI_CHIP_MOBILITY }, 422 { PCI_CHIP_MACH64LS, "3D RAGE Mobility L (Mach64 LS, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
423#endif /* CONFIG_FB_ATY_CT */ 423#endif /* CONFIG_FB_ATY_CT */
424}; 424};
425 425
@@ -440,6 +440,7 @@ static int __devinit correct_chipset(struct atyfb_par *par)
440 par->pll_limits.pll_max = aty_chips[i].pll; 440 par->pll_limits.pll_max = aty_chips[i].pll;
441 par->pll_limits.mclk = aty_chips[i].mclk; 441 par->pll_limits.mclk = aty_chips[i].mclk;
442 par->pll_limits.xclk = aty_chips[i].xclk; 442 par->pll_limits.xclk = aty_chips[i].xclk;
443 par->pll_limits.ecp_max = aty_chips[i].ecp_max;
443 par->features = aty_chips[i].features; 444 par->features = aty_chips[i].features;
444 445
445 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par); 446 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
@@ -465,18 +466,21 @@ static int __devinit correct_chipset(struct atyfb_par *par)
465 par->pll_limits.pll_max = 170; 466 par->pll_limits.pll_max = 170;
466 par->pll_limits.mclk = 67; 467 par->pll_limits.mclk = 67;
467 par->pll_limits.xclk = 67; 468 par->pll_limits.xclk = 67;
469 par->pll_limits.ecp_max = 80;
468 par->features = ATI_CHIP_264VT; 470 par->features = ATI_CHIP_264VT;
469 } else if(rev == 0x40) { 471 } else if(rev == 0x40) {
470 name = "ATI264VTA4 (Mach64 VT)"; 472 name = "ATI264VTA4 (Mach64 VT)";
471 par->pll_limits.pll_max = 200; 473 par->pll_limits.pll_max = 200;
472 par->pll_limits.mclk = 67; 474 par->pll_limits.mclk = 67;
473 par->pll_limits.xclk = 67; 475 par->pll_limits.xclk = 67;
476 par->pll_limits.ecp_max = 80;
474 par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV; 477 par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
475 } else { 478 } else {
476 name = "ATI264VTB (Mach64 VT)"; 479 name = "ATI264VTB (Mach64 VT)";
477 par->pll_limits.pll_max = 200; 480 par->pll_limits.pll_max = 200;
478 par->pll_limits.mclk = 67; 481 par->pll_limits.mclk = 67;
479 par->pll_limits.xclk = 67; 482 par->pll_limits.xclk = 67;
483 par->pll_limits.ecp_max = 80;
480 par->features = ATI_CHIP_264VTB; 484 par->features = ATI_CHIP_264VTB;
481 } 485 }
482 break; 486 break;
@@ -486,11 +490,13 @@ static int __devinit correct_chipset(struct atyfb_par *par)
486 par->pll_limits.pll_max = 170; 490 par->pll_limits.pll_max = 170;
487 par->pll_limits.mclk = 67; 491 par->pll_limits.mclk = 67;
488 par->pll_limits.xclk = 67; 492 par->pll_limits.xclk = 67;
493 par->pll_limits.ecp_max = 80;
489 par->features = ATI_CHIP_264GTB; 494 par->features = ATI_CHIP_264GTB;
490 } else if(rev == 0x02) { 495 } else if(rev == 0x02) {
491 par->pll_limits.pll_max = 200; 496 par->pll_limits.pll_max = 200;
492 par->pll_limits.mclk = 67; 497 par->pll_limits.mclk = 67;
493 par->pll_limits.xclk = 67; 498 par->pll_limits.xclk = 67;
499 par->pll_limits.ecp_max = 100;
494 par->features = ATI_CHIP_264GTB; 500 par->features = ATI_CHIP_264GTB;
495 } 501 }
496 break; 502 break;
diff --git a/drivers/video/aty/mach64_ct.c b/drivers/video/aty/mach64_ct.c
index 9bdb2aab01aa..e7056934c6a8 100644
--- a/drivers/video/aty/mach64_ct.c
+++ b/drivers/video/aty/mach64_ct.c
@@ -206,9 +206,7 @@ static int aty_valid_pll_ct(const struct fb_info *info, u32 vclk_per, struct pll
206{ 206{
207 u32 q; 207 u32 q;
208 struct atyfb_par *par = (struct atyfb_par *) info->par; 208 struct atyfb_par *par = (struct atyfb_par *) info->par;
209#ifdef DEBUG
210 int pllvclk; 209 int pllvclk;
211#endif
212 210
213 /* FIXME: use the VTB/GTB /{3,6,12} post dividers if they're better suited */ 211 /* FIXME: use the VTB/GTB /{3,6,12} post dividers if they're better suited */
214 q = par->ref_clk_per * pll->pll_ref_div * 4 / vclk_per; 212 q = par->ref_clk_per * pll->pll_ref_div * 4 / vclk_per;
@@ -223,13 +221,26 @@ static int aty_valid_pll_ct(const struct fb_info *info, u32 vclk_per, struct pll
223 pll->vclk_post_div_real = postdividers[pll->vclk_post_div]; 221 pll->vclk_post_div_real = postdividers[pll->vclk_post_div];
224 // pll->vclk_post_div <<= 6; 222 // pll->vclk_post_div <<= 6;
225 pll->vclk_fb_div = q * pll->vclk_post_div_real / 8; 223 pll->vclk_fb_div = q * pll->vclk_post_div_real / 8;
226#ifdef DEBUG
227 pllvclk = (1000000 * 2 * pll->vclk_fb_div) / 224 pllvclk = (1000000 * 2 * pll->vclk_fb_div) /
228 (par->ref_clk_per * pll->pll_ref_div); 225 (par->ref_clk_per * pll->pll_ref_div);
226#ifdef DEBUG
229 printk("atyfb(%s): pllvclk=%d MHz, vclk=%d MHz\n", 227 printk("atyfb(%s): pllvclk=%d MHz, vclk=%d MHz\n",
230 __FUNCTION__, pllvclk, pllvclk / pll->vclk_post_div_real); 228 __FUNCTION__, pllvclk, pllvclk / pll->vclk_post_div_real);
231#endif 229#endif
232 pll->pll_vclk_cntl = 0x03; /* VCLK = PLL_VCLK/VCLKx_POST */ 230 pll->pll_vclk_cntl = 0x03; /* VCLK = PLL_VCLK/VCLKx_POST */
231
232 /* Set ECP (scaler/overlay clock) divider */
233 if (par->pll_limits.ecp_max) {
234 int ecp = pllvclk / pll->vclk_post_div_real;
235 int ecp_div = 0;
236
237 while (ecp > par->pll_limits.ecp_max && ecp_div < 2) {
238 ecp >>= 1;
239 ecp_div++;
240 }
241 pll->pll_vclk_cntl |= ecp_div << 4;
242 }
243
233 return 0; 244 return 0;
234} 245}
235 246
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 12:40:07 -0500