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authorRalf Baechle <ralf@linux-mips.org>2007-10-11 18:46:15 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-10-11 18:46:15 -0400
commit21a151d8ca3aa74ee79f9791a9d4dc370d3e0636 (patch)
tree8556b3a32ded6a49225beb4a7aa4447cc87a0e00
parent49a89efbbbcc178a39555c43bd59a7593c429664 (diff)
[MIPS] checkfiles: Fix "need space after that ','" errors.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat
-rw-r--r--arch/mips/au1000/common/dbdma.c4
-rw-r--r--arch/mips/au1000/common/dbg_io.c2
-rw-r--r--arch/mips/au1000/common/power.c2
-rw-r--r--arch/mips/au1000/pb1200/irqmap.c2
-rw-r--r--arch/mips/boot/addinitrd.c10
-rw-r--r--arch/mips/boot/elf2ecoff.c2
-rw-r--r--arch/mips/kernel/binfmt_elfo32.c2
-rw-r--r--arch/mips/kernel/gdb-stub.c8
-rw-r--r--arch/mips/kernel/i8259.c14
-rw-r--r--arch/mips/kernel/irixelf.c8
-rw-r--r--arch/mips/kernel/irixsig.c8
-rw-r--r--arch/mips/kernel/irq.c4
-rw-r--r--arch/mips/kernel/kspd.c2
-rw-r--r--arch/mips/kernel/linux32.c10
-rw-r--r--arch/mips/kernel/signal.c4
-rw-r--r--arch/mips/kernel/smtc.c6
-rw-r--r--arch/mips/kernel/syscall.c2
-rw-r--r--arch/mips/kernel/sysirix.c2
-rw-r--r--arch/mips/kernel/vpe.c2
-rw-r--r--arch/mips/math-emu/cp1emu.c24
-rw-r--r--arch/mips/math-emu/dp_mul.c2
-rw-r--r--arch/mips/math-emu/ieee754.c12
-rw-r--r--arch/mips/math-emu/ieee754dp.h12
-rw-r--r--arch/mips/math-emu/ieee754int.h30
-rw-r--r--arch/mips/math-emu/ieee754sp.h12
-rw-r--r--arch/mips/mips-boards/atlas/atlas_gdb.c2
-rw-r--r--arch/mips/mips-boards/malta/malta_int.c2
-rw-r--r--arch/mips/mips-boards/malta/malta_setup.c2
-rw-r--r--arch/mips/mm/c-r4k.c8
-rw-r--r--arch/mips/mm/cerr-sb1.c24
-rw-r--r--arch/mips/mm/pg-sb1.c4
-rw-r--r--arch/mips/mm/pgtable.c8
-rw-r--r--arch/mips/mm/tlb-r8k.c2
-rw-r--r--arch/mips/mm/tlbex.c94
-rw-r--r--arch/mips/pci/pci-bcm1480.c6
-rw-r--r--arch/mips/pci/pci-bcm1480ht.c4
-rw-r--r--arch/mips/pci/pci-sb1250.c4
-rw-r--r--arch/mips/philips/pnx8550/common/proc.c32
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_serial.c8
-rw-r--r--arch/mips/pmc-sierra/yosemite/ht.c2
-rw-r--r--arch/mips/sgi-ip27/ip27-smp.c2
-rw-r--r--arch/mips/sibyte/bcm1480/irq.c8
-rw-r--r--arch/mips/sibyte/cfe/console.c2
-rw-r--r--arch/mips/sibyte/cfe/setup.c2
-rw-r--r--arch/mips/sibyte/sb1250/irq.c8
-rw-r--r--arch/mips/sibyte/sb1250/prom.c2
-rw-r--r--arch/mips/sibyte/swarm/dbg_io.c4
-rw-r--r--arch/mips/sni/reset.c2
-rw-r--r--arch/mips/sni/sniprom.c2
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c2
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c4
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/setup.c4
-rw-r--r--arch/mips/vr41xx/nec-cmbvr4133/init.c6
-rw-r--r--arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c6
-rw-r--r--include/asm-mips/addrspace.h6
-rw-r--r--include/asm-mips/asm.h66
-rw-r--r--include/asm-mips/atomic.h28
-rw-r--r--include/asm-mips/cmpxchg.h4
-rw-r--r--include/asm-mips/delay.h2
-rw-r--r--include/asm-mips/floppy.h2
-rw-r--r--include/asm-mips/fw/cfe/cfe_api.h24
-rw-r--r--include/asm-mips/hazards.h2
-rw-r--r--include/asm-mips/io.h18
-rw-r--r--include/asm-mips/ioctl.h16
-rw-r--r--include/asm-mips/ioctls.h12
-rw-r--r--include/asm-mips/jmr3927/tx3927.h32
-rw-r--r--include/asm-mips/local.h20
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx_dbdma.h14
-rw-r--r--include/asm-mips/mach-generic/mangle-port.h32
-rw-r--r--include/asm-mips/mach-ip27/mangle-port.h16
-rw-r--r--include/asm-mips/mach-ip32/mangle-port.h16
-rw-r--r--include/asm-mips/mach-jmr3927/mangle-port.h16
-rw-r--r--include/asm-mips/mach-pnx8550/kernel-entry-init.h2
-rw-r--r--include/asm-mips/mach-pnx8550/uart.h2
-rw-r--r--include/asm-mips/mc146818-time.h4
-rw-r--r--include/asm-mips/mips-boards/bonito64.h20
-rw-r--r--include/asm-mips/mips-boards/malta.h2
-rw-r--r--include/asm-mips/mipsmtregs.h60
-rw-r--r--include/asm-mips/mipsregs.h4
-rw-r--r--include/asm-mips/mmu_context.h4
-rw-r--r--include/asm-mips/paccess.h8
-rw-r--r--include/asm-mips/page.h2
-rw-r--r--include/asm-mips/pci/bridge.h2
-rw-r--r--include/asm-mips/pgalloc.h6
-rw-r--r--include/asm-mips/pgtable-32.h2
-rw-r--r--include/asm-mips/pgtable-64.h4
-rw-r--r--include/asm-mips/pgtable.h4
-rw-r--r--include/asm-mips/r4kcache.h6
-rw-r--r--include/asm-mips/semaphore.h2
-rw-r--r--include/asm-mips/sgiarcs.h34
-rw-r--r--include/asm-mips/sibyte/bcm1480_int.h22
-rw-r--r--include/asm-mips/sibyte/bcm1480_l2c.h102
-rw-r--r--include/asm-mips/sibyte/bcm1480_mc.h644
-rw-r--r--include/asm-mips/sibyte/bcm1480_regs.h18
-rw-r--r--include/asm-mips/sibyte/bcm1480_scd.h102
-rw-r--r--include/asm-mips/sibyte/board.h4
-rw-r--r--include/asm-mips/sibyte/sb1250_defs.h14
-rw-r--r--include/asm-mips/sibyte/sb1250_dma.h246
-rw-r--r--include/asm-mips/sibyte/sb1250_genbus.h322
-rw-r--r--include/asm-mips/sibyte/sb1250_int.h22
-rw-r--r--include/asm-mips/sibyte/sb1250_l2c.h64
-rw-r--r--include/asm-mips/sibyte/sb1250_ldt.h194
-rw-r--r--include/asm-mips/sibyte/sb1250_mac.h284
-rw-r--r--include/asm-mips/sibyte/sb1250_mc.h306
-rw-r--r--include/asm-mips/sibyte/sb1250_regs.h32
-rw-r--r--include/asm-mips/sibyte/sb1250_scd.h306
-rw-r--r--include/asm-mips/sibyte/sb1250_smbus.h62
-rw-r--r--include/asm-mips/sibyte/sb1250_syncser.h16
-rw-r--r--include/asm-mips/sibyte/sb1250_uart.h70
-rw-r--r--include/asm-mips/siginfo.h4
-rw-r--r--include/asm-mips/sn/addrs.h6
-rw-r--r--include/asm-mips/sn/klconfig.h2
-rw-r--r--include/asm-mips/stackframe.h8
-rw-r--r--include/asm-mips/system.h4
-rw-r--r--include/asm-mips/tlbflush.h4
-rw-r--r--include/asm-mips/tx4938/rbtx4938.h2
-rw-r--r--include/asm-mips/tx4938/tx4938.h44
-rw-r--r--include/asm-mips/tx4938/tx4938_mips.h8
-rw-r--r--include/asm-mips/uaccess.h40
-rw-r--r--include/asm-mips/vga.h4
-rw-r--r--include/asm-mips/xtalk/xtalk.h2
121 files changed, 1951 insertions, 1943 deletions
diff --git a/arch/mips/au1000/common/dbdma.c b/arch/mips/au1000/common/dbdma.c
index d15b047d480d..461cf0139737 100644
--- a/arch/mips/au1000/common/dbdma.c
+++ b/arch/mips/au1000/common/dbdma.c
@@ -213,7 +213,7 @@ au1xxx_ddma_add_device(dbdev_tab_t *dev)
213 if ( NULL != p ) 213 if ( NULL != p )
214 { 214 {
215 memcpy(p, dev, sizeof(dbdev_tab_t)); 215 memcpy(p, dev, sizeof(dbdev_tab_t));
216 p->dev_id = DSCR_DEV2CUSTOM_ID(new_id,dev->dev_id); 216 p->dev_id = DSCR_DEV2CUSTOM_ID(new_id, dev->dev_id);
217 ret = p->dev_id; 217 ret = p->dev_id;
218 new_id++; 218 new_id++;
219#if 0 219#if 0
@@ -671,7 +671,7 @@ _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags)
671 * parts. If it is fixedin the future, these dma_cache_inv will just 671 * parts. If it is fixedin the future, these dma_cache_inv will just
672 * be nothing more than empty macros. See io.h. 672 * be nothing more than empty macros. See io.h.
673 * */ 673 * */
674 dma_cache_inv((unsigned long)buf,nbytes); 674 dma_cache_inv((unsigned long)buf, nbytes);
675 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ 675 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
676 au_sync(); 676 au_sync();
677 dma_cache_wback_inv((unsigned long)dp, sizeof(dp)); 677 dma_cache_wback_inv((unsigned long)dp, sizeof(dp));
diff --git a/arch/mips/au1000/common/dbg_io.c b/arch/mips/au1000/common/dbg_io.c
index 0a50af7f34b8..79e0b0a51ace 100644
--- a/arch/mips/au1000/common/dbg_io.c
+++ b/arch/mips/au1000/common/dbg_io.c
@@ -53,7 +53,7 @@ typedef unsigned int uint32;
53 53
54/* memory-mapped read/write of the port */ 54/* memory-mapped read/write of the port */
55#define UART16550_READ(y) (au_readl(DEBUG_BASE + y) & 0xff) 55#define UART16550_READ(y) (au_readl(DEBUG_BASE + y) & 0xff)
56#define UART16550_WRITE(y,z) (au_writel(z&0xff, DEBUG_BASE + y)) 56#define UART16550_WRITE(y, z) (au_writel(z&0xff, DEBUG_BASE + y))
57 57
58extern unsigned long get_au1x00_uart_baud_base(void); 58extern unsigned long get_au1x00_uart_baud_base(void);
59extern unsigned long cal_r4koff(void); 59extern unsigned long cal_r4koff(void);
diff --git a/arch/mips/au1000/common/power.c b/arch/mips/au1000/common/power.c
index 3901e8e04755..6f57f72a7d57 100644
--- a/arch/mips/au1000/common/power.c
+++ b/arch/mips/au1000/common/power.c
@@ -211,7 +211,7 @@ int au_sleep(void)
211 unsigned long wakeup, flags; 211 unsigned long wakeup, flags;
212 extern void save_and_sleep(void); 212 extern void save_and_sleep(void);
213 213
214 spin_lock_irqsave(&pm_lock,flags); 214 spin_lock_irqsave(&pm_lock, flags);
215 215
216 save_core_regs(); 216 save_core_regs();
217 217
diff --git a/arch/mips/au1000/pb1200/irqmap.c b/arch/mips/au1000/pb1200/irqmap.c
index b73b2d18bf56..7c708db04a88 100644
--- a/arch/mips/au1000/pb1200/irqmap.c
+++ b/arch/mips/au1000/pb1200/irqmap.c
@@ -132,7 +132,7 @@ static void pb1200_shutdown_irq( unsigned int irq_nr )
132 pb1200_disable_irq(irq_nr); 132 pb1200_disable_irq(irq_nr);
133 if (--pb1200_cascade_en == 0) 133 if (--pb1200_cascade_en == 0)
134 { 134 {
135 free_irq(AU1000_GPIO_7,&pb1200_cascade_handler ); 135 free_irq(AU1000_GPIO_7, &pb1200_cascade_handler );
136 } 136 }
137 return; 137 return;
138} 138}
diff --git a/arch/mips/boot/addinitrd.c b/arch/mips/boot/addinitrd.c
index 193e4be52e79..b5b3febc10cc 100644
--- a/arch/mips/boot/addinitrd.c
+++ b/arch/mips/boot/addinitrd.c
@@ -40,7 +40,7 @@ void die(char *s)
40 40
41int main(int argc, char *argv[]) 41int main(int argc, char *argv[])
42{ 42{
43 int fd_vmlinux,fd_initrd,fd_outfile; 43 int fd_vmlinux, fd_initrd, fd_outfile;
44 FILHDR efile; 44 FILHDR efile;
45 AOUTHDR eaout; 45 AOUTHDR eaout;
46 SCNHDR esecs[3]; 46 SCNHDR esecs[3];
@@ -48,15 +48,15 @@ int main(int argc, char *argv[])
48 char buf[1024]; 48 char buf[1024];
49 unsigned long loadaddr; 49 unsigned long loadaddr;
50 unsigned long initrd_header[2]; 50 unsigned long initrd_header[2];
51 int i,cnt; 51 int i, cnt;
52 int swab = 0; 52 int swab = 0;
53 53
54 if (argc != 4) { 54 if (argc != 4) {
55 printf("Usage: %s <vmlinux> <initrd> <outfile>\n",argv[0]); 55 printf("Usage: %s <vmlinux> <initrd> <outfile>\n", argv[0]);
56 exit(1); 56 exit(1);
57 } 57 }
58 58
59 if ((fd_vmlinux = open (argv[1],O_RDONLY)) < 0) 59 if ((fd_vmlinux = open (argv[1], O_RDONLY)) < 0)
60 die("open vmlinux"); 60 die("open vmlinux");
61 if (read (fd_vmlinux, &efile, sizeof efile) != sizeof efile) 61 if (read (fd_vmlinux, &efile, sizeof efile) != sizeof efile)
62 die("read file header"); 62 die("read file header");
@@ -98,7 +98,7 @@ int main(int argc, char *argv[])
98 eaout.dsize = esecs[1].s_size = initrd_header[1] = SWAB(st.st_size+8); 98 eaout.dsize = esecs[1].s_size = initrd_header[1] = SWAB(st.st_size+8);
99 eaout.data_start = esecs[1].s_vaddr = esecs[1].s_paddr = SWAB(loadaddr); 99 eaout.data_start = esecs[1].s_vaddr = esecs[1].s_paddr = SWAB(loadaddr);
100 100
101 if ((fd_outfile = open (argv[3], O_RDWR|O_CREAT|O_TRUNC,0666)) < 0) 101 if ((fd_outfile = open (argv[3], O_RDWR|O_CREAT|O_TRUNC, 0666)) < 0)
102 die("open outfile"); 102 die("open outfile");
103 if (write (fd_outfile, &efile, sizeof efile) != sizeof efile) 103 if (write (fd_outfile, &efile, sizeof efile) != sizeof efile)
104 die("write file header"); 104 die("write file header");
diff --git a/arch/mips/boot/elf2ecoff.c b/arch/mips/boot/elf2ecoff.c
index c3543d9eb266..c5a7f308c405 100644
--- a/arch/mips/boot/elf2ecoff.c
+++ b/arch/mips/boot/elf2ecoff.c
@@ -467,7 +467,7 @@ int main(int argc, char *argv[])
467 esecs[0].s_scnptr = N_TXTOFF(efh, eah); 467 esecs[0].s_scnptr = N_TXTOFF(efh, eah);
468 esecs[1].s_scnptr = N_DATOFF(efh, eah); 468 esecs[1].s_scnptr = N_DATOFF(efh, eah);
469#define ECOFF_SEGMENT_ALIGNMENT(a) 0x10 469#define ECOFF_SEGMENT_ALIGNMENT(a) 0x10
470#define ECOFF_ROUND(s,a) (((s)+(a)-1)&~((a)-1)) 470#define ECOFF_ROUND(s, a) (((s)+(a)-1)&~((a)-1))
471 esecs[2].s_scnptr = esecs[1].s_scnptr + 471 esecs[2].s_scnptr = esecs[1].s_scnptr +
472 ECOFF_ROUND(esecs[1].s_size, ECOFF_SEGMENT_ALIGNMENT(&eah)); 472 ECOFF_ROUND(esecs[1].s_size, ECOFF_SEGMENT_ALIGNMENT(&eah));
473 if (addflag) { 473 if (addflag) {
diff --git a/arch/mips/kernel/binfmt_elfo32.c b/arch/mips/kernel/binfmt_elfo32.c
index 993f7ec70f35..da41eac195ca 100644
--- a/arch/mips/kernel/binfmt_elfo32.c
+++ b/arch/mips/kernel/binfmt_elfo32.c
@@ -110,7 +110,7 @@ jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value)
110} 110}
111 111
112#undef ELF_CORE_COPY_REGS 112#undef ELF_CORE_COPY_REGS
113#define ELF_CORE_COPY_REGS(_dest,_regs) elf32_core_copy_regs(_dest,_regs); 113#define ELF_CORE_COPY_REGS(_dest, _regs) elf32_core_copy_regs(_dest, _regs);
114 114
115void elf32_core_copy_regs(elf_gregset_t grp, struct pt_regs *regs) 115void elf32_core_copy_regs(elf_gregset_t grp, struct pt_regs *regs)
116{ 116{
diff --git a/arch/mips/kernel/gdb-stub.c b/arch/mips/kernel/gdb-stub.c
index 989d06c3827b..c33f6f22d86a 100644
--- a/arch/mips/kernel/gdb-stub.c
+++ b/arch/mips/kernel/gdb-stub.c
@@ -902,7 +902,7 @@ void handle_exception(struct gdb_regs *regs)
902 hex2mem(ptr, (char *)&regs->frame_ptr, 2*sizeof(long), 0, 0); 902 hex2mem(ptr, (char *)&regs->frame_ptr, 2*sizeof(long), 0, 0);
903 ptr += 2*(2*sizeof(long)); 903 ptr += 2*(2*sizeof(long));
904 hex2mem(ptr, (char *)&regs->cp0_index, 16*sizeof(long), 0, 0); 904 hex2mem(ptr, (char *)&regs->cp0_index, 16*sizeof(long), 0, 0);
905 strcpy(output_buffer,"OK"); 905 strcpy(output_buffer, "OK");
906 } 906 }
907 break; 907 break;
908 908
@@ -919,7 +919,7 @@ void handle_exception(struct gdb_regs *regs)
919 break; 919 break;
920 strcpy(output_buffer, "E03"); 920 strcpy(output_buffer, "E03");
921 } else 921 } else
922 strcpy(output_buffer,"E01"); 922 strcpy(output_buffer, "E01");
923 break; 923 break;
924 924
925 /* 925 /*
@@ -996,7 +996,7 @@ void handle_exception(struct gdb_regs *regs)
996 ptr = &input_buffer[1]; 996 ptr = &input_buffer[1];
997 if (!hexToInt(&ptr, &baudrate)) 997 if (!hexToInt(&ptr, &baudrate))
998 { 998 {
999 strcpy(output_buffer,"B01"); 999 strcpy(output_buffer, "B01");
1000 break; 1000 break;
1001 } 1001 }
1002 1002
@@ -1015,7 +1015,7 @@ void handle_exception(struct gdb_regs *regs)
1015 break; 1015 break;
1016 default: 1016 default:
1017 baudrate = 0; 1017 baudrate = 0;
1018 strcpy(output_buffer,"B02"); 1018 strcpy(output_buffer, "B02");
1019 goto x1; 1019 goto x1;
1020 } 1020 }
1021 1021
diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c
index a860b21e63e9..471013577108 100644
--- a/arch/mips/kernel/i8259.c
+++ b/arch/mips/kernel/i8259.c
@@ -127,14 +127,14 @@ static inline int i8259A_irq_real(unsigned int irq)
127 int irqmask = 1 << irq; 127 int irqmask = 1 << irq;
128 128
129 if (irq < 8) { 129 if (irq < 8) {
130 outb(0x0B,PIC_MASTER_CMD); /* ISR register */ 130 outb(0x0B, PIC_MASTER_CMD); /* ISR register */
131 value = inb(PIC_MASTER_CMD) & irqmask; 131 value = inb(PIC_MASTER_CMD) & irqmask;
132 outb(0x0A,PIC_MASTER_CMD); /* back to the IRR register */ 132 outb(0x0A, PIC_MASTER_CMD); /* back to the IRR register */
133 return value; 133 return value;
134 } 134 }
135 outb(0x0B,PIC_SLAVE_CMD); /* ISR register */ 135 outb(0x0B, PIC_SLAVE_CMD); /* ISR register */
136 value = inb(PIC_SLAVE_CMD) & (irqmask >> 8); 136 value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
137 outb(0x0A,PIC_SLAVE_CMD); /* back to the IRR register */ 137 outb(0x0A, PIC_SLAVE_CMD); /* back to the IRR register */
138 return value; 138 return value;
139} 139}
140 140
@@ -175,12 +175,12 @@ handle_real_irq:
175 if (irq & 8) { 175 if (irq & 8) {
176 inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */ 176 inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
177 outb(cached_slave_mask, PIC_SLAVE_IMR); 177 outb(cached_slave_mask, PIC_SLAVE_IMR);
178 outb(0x60+(irq&7),PIC_SLAVE_CMD);/* 'Specific EOI' to slave */ 178 outb(0x60+(irq&7), PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
179 outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */ 179 outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
180 } else { 180 } else {
181 inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */ 181 inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
182 outb(cached_master_mask, PIC_MASTER_IMR); 182 outb(cached_master_mask, PIC_MASTER_IMR);
183 outb(0x60+irq,PIC_MASTER_CMD); /* 'Specific EOI to master */ 183 outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */
184 } 184 }
185 smtc_im_ack_irq(irq); 185 smtc_im_ack_irq(irq);
186 spin_unlock_irqrestore(&i8259A_lock, flags); 186 spin_unlock_irqrestore(&i8259A_lock, flags);
diff --git a/arch/mips/kernel/irixelf.c b/arch/mips/kernel/irixelf.c
index e3b4b547a822..8ef5cf4cc423 100644
--- a/arch/mips/kernel/irixelf.c
+++ b/arch/mips/kernel/irixelf.c
@@ -231,16 +231,16 @@ static unsigned long * create_irix_tables(char * p, int argc, int envc,
231 sp -= argc+1; 231 sp -= argc+1;
232 argv = sp; 232 argv = sp;
233 233
234 __put_user((elf_addr_t)argc,--sp); 234 __put_user((elf_addr_t)argc, --sp);
235 current->mm->arg_start = (unsigned long) p; 235 current->mm->arg_start = (unsigned long) p;
236 while (argc-->0) { 236 while (argc-->0) {
237 __put_user((unsigned long)p,argv++); 237 __put_user((unsigned long)p, argv++);
238 p += strlen_user(p); 238 p += strlen_user(p);
239 } 239 }
240 __put_user((unsigned long) NULL, argv); 240 __put_user((unsigned long) NULL, argv);
241 current->mm->arg_end = current->mm->env_start = (unsigned long) p; 241 current->mm->arg_end = current->mm->env_start = (unsigned long) p;
242 while (envc-->0) { 242 while (envc-->0) {
243 __put_user((unsigned long)p,envp++); 243 __put_user((unsigned long)p, envp++);
244 p += strlen_user(p); 244 p += strlen_user(p);
245 } 245 }
246 __put_user((unsigned long) NULL, envp); 246 __put_user((unsigned long) NULL, envp);
@@ -831,7 +831,7 @@ static int load_irix_library(struct file *file)
831 int retval; 831 int retval;
832 unsigned int bss; 832 unsigned int bss;
833 int error; 833 int error;
834 int i,j, k; 834 int i, j, k;
835 835
836 error = kernel_read(file, 0, (char *) &elf_ex, sizeof(elf_ex)); 836 error = kernel_read(file, 0, (char *) &elf_ex, sizeof(elf_ex));
837 if (error != sizeof(elf_ex)) 837 if (error != sizeof(elf_ex))
diff --git a/arch/mips/kernel/irixsig.c b/arch/mips/kernel/irixsig.c
index 28b2a8f00911..85c2e389edd6 100644
--- a/arch/mips/kernel/irixsig.c
+++ b/arch/mips/kernel/irixsig.c
@@ -163,9 +163,9 @@ static inline int handle_signal(unsigned long sig, siginfo_t *info,
163 ret = setup_irix_frame(ka, regs, sig, oldset); 163 ret = setup_irix_frame(ka, regs, sig, oldset);
164 164
165 spin_lock_irq(&current->sighand->siglock); 165 spin_lock_irq(&current->sighand->siglock);
166 sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask); 166 sigorsets(&current->blocked, &current->blocked, &ka->sa.sa_mask);
167 if (!(ka->sa.sa_flags & SA_NODEFER)) 167 if (!(ka->sa.sa_flags & SA_NODEFER))
168 sigaddset(&current->blocked,sig); 168 sigaddset(&current->blocked, sig);
169 recalc_sigpending(); 169 recalc_sigpending();
170 spin_unlock_irq(&current->sighand->siglock); 170 spin_unlock_irq(&current->sighand->siglock);
171 171
@@ -605,8 +605,8 @@ repeat:
605 current->state = TASK_INTERRUPTIBLE; 605 current->state = TASK_INTERRUPTIBLE;
606 read_lock(&tasklist_lock); 606 read_lock(&tasklist_lock);
607 tsk = current; 607 tsk = current;
608 list_for_each(_p,&tsk->children) { 608 list_for_each(_p, &tsk->children) {
609 p = list_entry(_p,struct task_struct,sibling); 609 p = list_entry(_p, struct task_struct, sibling);
610 if ((type == IRIX_P_PID) && p->pid != pid) 610 if ((type == IRIX_P_PID) && p->pid != pid)
611 continue; 611 continue;
612 if ((type == IRIX_P_PGID) && process_group(p) != pid) 612 if ((type == IRIX_P_PGID) && process_group(p) != pid)
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index a990aad2f049..d06e9c9af790 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -93,7 +93,7 @@ int show_interrupts(struct seq_file *p, void *v)
93 if (i == 0) { 93 if (i == 0) {
94 seq_printf(p, " "); 94 seq_printf(p, " ");
95 for_each_online_cpu(j) 95 for_each_online_cpu(j)
96 seq_printf(p, "CPU%d ",j); 96 seq_printf(p, "CPU%d ", j);
97 seq_putc(p, '\n'); 97 seq_putc(p, '\n');
98 } 98 }
99 99
@@ -102,7 +102,7 @@ int show_interrupts(struct seq_file *p, void *v)
102 action = irq_desc[i].action; 102 action = irq_desc[i].action;
103 if (!action) 103 if (!action)
104 goto skip; 104 goto skip;
105 seq_printf(p, "%3d: ",i); 105 seq_printf(p, "%3d: ", i);
106#ifndef CONFIG_SMP 106#ifndef CONFIG_SMP
107 seq_printf(p, "%10u ", kstat_irqs(i)); 107 seq_printf(p, "%10u ", kstat_irqs(i));
108#else 108#else
diff --git a/arch/mips/kernel/kspd.c b/arch/mips/kernel/kspd.c
index 1ed176606548..d2c2e00e5864 100644
--- a/arch/mips/kernel/kspd.c
+++ b/arch/mips/kernel/kspd.c
@@ -239,7 +239,7 @@ void sp_work_handle_request(void)
239 case MTSP_SYSCALL_GETTOD: 239 case MTSP_SYSCALL_GETTOD:
240 memset(&tz, 0, sizeof(tz)); 240 memset(&tz, 0, sizeof(tz));
241 if ((ret.retval = sp_syscall(__NR_gettimeofday, (int)&tv, 241 if ((ret.retval = sp_syscall(__NR_gettimeofday, (int)&tv,
242 (int)&tz, 0,0)) == 0) 242 (int)&tz, 0, 0)) == 0)
243 ret.retval = tv.tv_sec; 243 ret.retval = tv.tv_sec;
244 break; 244 break;
245 245
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c
index a6de17081cad..d6e01215fb2b 100644
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -58,10 +58,10 @@
58#define AA(__x) ((unsigned long)((int)__x)) 58#define AA(__x) ((unsigned long)((int)__x))
59 59
60#ifdef __MIPSEB__ 60#ifdef __MIPSEB__
61#define merge_64(r1,r2) ((((r1) & 0xffffffffUL) << 32) + ((r2) & 0xffffffffUL)) 61#define merge_64(r1, r2) ((((r1) & 0xffffffffUL) << 32) + ((r2) & 0xffffffffUL))
62#endif 62#endif
63#ifdef __MIPSEL__ 63#ifdef __MIPSEL__
64#define merge_64(r1,r2) ((((r2) & 0xffffffffUL) << 32) + ((r1) & 0xffffffffUL)) 64#define merge_64(r1, r2) ((((r2) & 0xffffffffUL) << 32) + ((r1) & 0xffffffffUL))
65#endif 65#endif
66 66
67/* 67/*
@@ -96,7 +96,7 @@ int cp_compat_stat(struct kstat *stat, struct compat_stat __user *statbuf)
96#endif 96#endif
97 tmp.st_blocks = stat->blocks; 97 tmp.st_blocks = stat->blocks;
98 tmp.st_blksize = stat->blksize; 98 tmp.st_blksize = stat->blksize;
99 return copy_to_user(statbuf,&tmp,sizeof(tmp)) ? -EFAULT : 0; 99 return copy_to_user(statbuf, &tmp, sizeof(tmp)) ? -EFAULT : 0;
100} 100}
101 101
102asmlinkage unsigned long 102asmlinkage unsigned long
@@ -510,11 +510,11 @@ asmlinkage int sys32_ustat(dev_t dev, struct ustat32 __user * ubuf32)
510 if (err) 510 if (err)
511 goto out; 511 goto out;
512 512
513 memset(&tmp32,0,sizeof(struct ustat32)); 513 memset(&tmp32, 0, sizeof(struct ustat32));
514 tmp32.f_tfree = tmp.f_tfree; 514 tmp32.f_tfree = tmp.f_tfree;
515 tmp32.f_tinode = tmp.f_tinode; 515 tmp32.f_tinode = tmp.f_tinode;
516 516
517 err = copy_to_user(ubuf32,&tmp32,sizeof(struct ustat32)) ? -EFAULT : 0; 517 err = copy_to_user(ubuf32, &tmp32, sizeof(struct ustat32)) ? -EFAULT : 0;
518 518
519out: 519out:
520 return err; 520 return err;
diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
index 2a08ce41bf2b..a4e106c56ab5 100644
--- a/arch/mips/kernel/signal.c
+++ b/arch/mips/kernel/signal.c
@@ -613,9 +613,9 @@ static int handle_signal(unsigned long sig, siginfo_t *info,
613 ret = current->thread.abi->setup_frame(ka, regs, sig, oldset); 613 ret = current->thread.abi->setup_frame(ka, regs, sig, oldset);
614 614
615 spin_lock_irq(&current->sighand->siglock); 615 spin_lock_irq(&current->sighand->siglock);
616 sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask); 616 sigorsets(&current->blocked, &current->blocked, &ka->sa.sa_mask);
617 if (!(ka->sa.sa_flags & SA_NODEFER)) 617 if (!(ka->sa.sa_flags & SA_NODEFER))
618 sigaddset(&current->blocked,sig); 618 sigaddset(&current->blocked, sig);
619 recalc_sigpending(); 619 recalc_sigpending();
620 spin_unlock_irq(&current->sighand->siglock); 620 spin_unlock_irq(&current->sighand->siglock);
621 621
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index 770182887c5b..4d91e2f455c0 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -180,7 +180,7 @@ void __init sanitize_tlb_entries(void)
180 180
181static void smtc_configure_tlb(void) 181static void smtc_configure_tlb(void)
182{ 182{
183 int i,tlbsiz,vpes; 183 int i, tlbsiz, vpes;
184 unsigned long mvpconf0; 184 unsigned long mvpconf0;
185 unsigned long config1val; 185 unsigned long config1val;
186 186
@@ -423,7 +423,7 @@ void mipsmt_prepare_cpus(void)
423 * code. Leave it alone! 423 * code. Leave it alone!
424 */ 424 */
425 if (tc != 0) { 425 if (tc != 0) {
426 smtc_tc_setup(vpe,tc, cpu); 426 smtc_tc_setup(vpe, tc, cpu);
427 cpu++; 427 cpu++;
428 } 428 }
429 printk(" %d", tc); 429 printk(" %d", tc);
@@ -431,7 +431,7 @@ void mipsmt_prepare_cpus(void)
431 } 431 }
432 if (slop) { 432 if (slop) {
433 if (tc != 0) { 433 if (tc != 0) {
434 smtc_tc_setup(vpe,tc, cpu); 434 smtc_tc_setup(vpe, tc, cpu);
435 cpu++; 435 cpu++;
436 } 436 }
437 printk(" %d", tc); 437 printk(" %d", tc);
diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c
index ef2c6360d052..17c4374d2209 100644
--- a/arch/mips/kernel/syscall.c
+++ b/arch/mips/kernel/syscall.c
@@ -245,7 +245,7 @@ asmlinkage int sys_olduname(struct oldold_utsname __user * name)
245 245
246 if (!name) 246 if (!name)
247 return -EFAULT; 247 return -EFAULT;
248 if (!access_ok(VERIFY_WRITE,name,sizeof(struct oldold_utsname))) 248 if (!access_ok(VERIFY_WRITE, name, sizeof(struct oldold_utsname)))
249 return -EFAULT; 249 return -EFAULT;
250 250
251 error = __copy_to_user(&name->sysname, &utsname()->sysname, 251 error = __copy_to_user(&name->sysname, &utsname()->sysname,
diff --git a/arch/mips/kernel/sysirix.c b/arch/mips/kernel/sysirix.c
index b50239574c95..ee7790d9debe 100644
--- a/arch/mips/kernel/sysirix.c
+++ b/arch/mips/kernel/sysirix.c
@@ -778,7 +778,7 @@ asmlinkage int irix_times(struct tms __user *tbuf)
778 int err = 0; 778 int err = 0;
779 779
780 if (tbuf) { 780 if (tbuf) {
781 if (!access_ok(VERIFY_WRITE,tbuf,sizeof *tbuf)) 781 if (!access_ok(VERIFY_WRITE, tbuf, sizeof *tbuf))
782 return -EFAULT; 782 return -EFAULT;
783 783
784 err = __put_user(current->utime, &tbuf->tms_utime); 784 err = __put_user(current->utime, &tbuf->tms_utime);
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
index 3c09b9785f4c..45077c4b2e22 100644
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -1044,7 +1044,7 @@ static int getcwd(char *buff, int size)
1044 old_fs = get_fs(); 1044 old_fs = get_fs();
1045 set_fs(KERNEL_DS); 1045 set_fs(KERNEL_DS);
1046 1046
1047 ret = sys_getcwd(buff,size); 1047 ret = sys_getcwd(buff, size);
1048 1048
1049 set_fs(old_fs); 1049 set_fs(old_fs);
1050 1050
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index c44e9cc2b19c..b08fc65c13a6 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -178,24 +178,24 @@ static int isBranchInstr(mips_instruction * i)
178#define FR_BIT 0 178#define FR_BIT 0
179#endif 179#endif
180 180
181#define SIFROMREG(si,x) ((si) = \ 181#define SIFROMREG(si, x) ((si) = \
182 (xcp->cp0_status & FR_BIT) || !(x & 1) ? \ 182 (xcp->cp0_status & FR_BIT) || !(x & 1) ? \
183 (int)ctx->fpr[x] : \ 183 (int)ctx->fpr[x] : \
184 (int)(ctx->fpr[x & ~1] >> 32 )) 184 (int)(ctx->fpr[x & ~1] >> 32 ))
185#define SITOREG(si,x) (ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)] = \ 185#define SITOREG(si, x) (ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)] = \
186 (xcp->cp0_status & FR_BIT) || !(x & 1) ? \ 186 (xcp->cp0_status & FR_BIT) || !(x & 1) ? \
187 ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \ 187 ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \
188 ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32) 188 ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32)
189 189
190#define DIFROMREG(di,x) ((di) = \ 190#define DIFROMREG(di, x) ((di) = \
191 ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)]) 191 ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)])
192#define DITOREG(di,x) (ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)] \ 192#define DITOREG(di, x) (ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)] \
193 = (di)) 193 = (di))
194 194
195#define SPFROMREG(sp,x) SIFROMREG((sp).bits,x) 195#define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
196#define SPTOREG(sp,x) SITOREG((sp).bits,x) 196#define SPTOREG(sp, x) SITOREG((sp).bits, x)
197#define DPFROMREG(dp,x) DIFROMREG((dp).bits,x) 197#define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
198#define DPTOREG(dp,x) DITOREG((dp).bits,x) 198#define DPTOREG(dp, x) DITOREG((dp).bits, x)
199 199
200/* 200/*
201 * Emulate the single floating point instruction pointed at by EPC. 201 * Emulate the single floating point instruction pointed at by EPC.
@@ -584,12 +584,12 @@ static ieee754sp fpemu_sp_rsqrt(ieee754sp s)
584 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s)); 584 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
585} 585}
586 586
587DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add,); 587DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
588DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub,); 588DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
589DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg); 589DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
590DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg); 590DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
591DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add,); 591DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
592DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub,); 592DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
593DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); 593DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
594DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); 594DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
595 595
diff --git a/arch/mips/math-emu/dp_mul.c b/arch/mips/math-emu/dp_mul.c
index f2373902f524..48908a809c17 100644
--- a/arch/mips/math-emu/dp_mul.c
+++ b/arch/mips/math-emu/dp_mul.c
@@ -121,7 +121,7 @@ ieee754dp ieee754dp_mul(ieee754dp x, ieee754dp y)
121 */ 121 */
122 122
123 /* 32 * 32 => 64 */ 123 /* 32 * 32 => 64 */
124#define DPXMULT(x,y) ((u64)(x) * (u64)y) 124#define DPXMULT(x, y) ((u64)(x) * (u64)y)
125 125
126 { 126 {
127 unsigned lxm = xm; 127 unsigned lxm = xm;
diff --git a/arch/mips/math-emu/ieee754.c b/arch/mips/math-emu/ieee754.c
index a93c45dbdefd..946aee331788 100644
--- a/arch/mips/math-emu/ieee754.c
+++ b/arch/mips/math-emu/ieee754.c
@@ -47,13 +47,13 @@
47 47
48 48
49#if (defined(BYTE_ORDER) && BYTE_ORDER == LITTLE_ENDIAN) || defined(__MIPSEL__) 49#if (defined(BYTE_ORDER) && BYTE_ORDER == LITTLE_ENDIAN) || defined(__MIPSEL__)
50#define SPSTR(s,b,m) {m,b,s} 50#define SPSTR(s, b, m) {m, b, s}
51#define DPSTR(s,b,mh,ml) {ml,mh,b,s} 51#define DPSTR(s, b, mh, ml) {ml, mh, b, s}
52#endif 52#endif
53 53
54#ifdef __MIPSEB__ 54#ifdef __MIPSEB__
55#define SPSTR(s,b,m) {s,b,m} 55#define SPSTR(s, b, m) {s, b, m}
56#define DPSTR(s,b,mh,ml) {s,b,mh,ml} 56#define DPSTR(s, b, mh, ml) {s, b, mh, ml}
57#endif 57#endif
58 58
59const struct ieee754dp_konst __ieee754dp_spcvals[] = { 59const struct ieee754dp_konst __ieee754dp_spcvals[] = {
@@ -65,7 +65,7 @@ const struct ieee754dp_konst __ieee754dp_spcvals[] = {
65 DPSTR(1, 3 + DP_EBIAS, 0x40000, 0), /* - 10.0 */ 65 DPSTR(1, 3 + DP_EBIAS, 0x40000, 0), /* - 10.0 */
66 DPSTR(0, DP_EMAX + 1 + DP_EBIAS, 0, 0), /* + infinity */ 66 DPSTR(0, DP_EMAX + 1 + DP_EBIAS, 0, 0), /* + infinity */
67 DPSTR(1, DP_EMAX + 1 + DP_EBIAS, 0, 0), /* - infinity */ 67 DPSTR(1, DP_EMAX + 1 + DP_EBIAS, 0, 0), /* - infinity */
68 DPSTR(0,DP_EMAX+1+DP_EBIAS,0x7FFFF,0xFFFFFFFF), /* + indef quiet Nan */ 68 DPSTR(0, DP_EMAX+1+DP_EBIAS, 0x7FFFF, 0xFFFFFFFF), /* + indef quiet Nan */
69 DPSTR(0, DP_EMAX + DP_EBIAS, 0xFFFFF, 0xFFFFFFFF), /* + max */ 69 DPSTR(0, DP_EMAX + DP_EBIAS, 0xFFFFF, 0xFFFFFFFF), /* + max */
70 DPSTR(1, DP_EMAX + DP_EBIAS, 0xFFFFF, 0xFFFFFFFF), /* - max */ 70 DPSTR(1, DP_EMAX + DP_EBIAS, 0xFFFFF, 0xFFFFFFFF), /* - max */
71 DPSTR(0, DP_EMIN + DP_EBIAS, 0, 0), /* + min normal */ 71 DPSTR(0, DP_EMIN + DP_EBIAS, 0, 0), /* + min normal */
@@ -85,7 +85,7 @@ const struct ieee754sp_konst __ieee754sp_spcvals[] = {
85 SPSTR(1, 3 + SP_EBIAS, 0x200000), /* - 10.0 */ 85 SPSTR(1, 3 + SP_EBIAS, 0x200000), /* - 10.0 */
86 SPSTR(0, SP_EMAX + 1 + SP_EBIAS, 0), /* + infinity */ 86 SPSTR(0, SP_EMAX + 1 + SP_EBIAS, 0), /* + infinity */
87 SPSTR(1, SP_EMAX + 1 + SP_EBIAS, 0), /* - infinity */ 87 SPSTR(1, SP_EMAX + 1 + SP_EBIAS, 0), /* - infinity */
88 SPSTR(0,SP_EMAX+1+SP_EBIAS,0x3FFFFF), /* + indef quiet Nan */ 88 SPSTR(0, SP_EMAX+1+SP_EBIAS, 0x3FFFFF), /* + indef quiet Nan */
89 SPSTR(0, SP_EMAX + SP_EBIAS, 0x7FFFFF), /* + max normal */ 89 SPSTR(0, SP_EMAX + SP_EBIAS, 0x7FFFFF), /* + max normal */
90 SPSTR(1, SP_EMAX + SP_EBIAS, 0x7FFFFF), /* - max normal */ 90 SPSTR(1, SP_EMAX + SP_EBIAS, 0x7FFFFF), /* - max normal */
91 SPSTR(0, SP_EMIN + SP_EBIAS, 0), /* + min normal */ 91 SPSTR(0, SP_EMIN + SP_EBIAS, 0), /* + min normal */
diff --git a/arch/mips/math-emu/ieee754dp.h b/arch/mips/math-emu/ieee754dp.h
index a37370dae232..8977eb585a37 100644
--- a/arch/mips/math-emu/ieee754dp.h
+++ b/arch/mips/math-emu/ieee754dp.h
@@ -43,8 +43,8 @@
43/* convert denormal to normalized with extended exponent */ 43/* convert denormal to normalized with extended exponent */
44#define DPDNORMx(m,e) \ 44#define DPDNORMx(m,e) \
45 while( (m >> DP_MBITS) == 0) { m <<= 1; e--; } 45 while( (m >> DP_MBITS) == 0) { m <<= 1; e--; }
46#define DPDNORMX DPDNORMx(xm,xe) 46#define DPDNORMX DPDNORMx(xm, xe)
47#define DPDNORMY DPDNORMx(ym,ye) 47#define DPDNORMY DPDNORMx(ym, ye)
48 48
49static __inline ieee754dp builddp(int s, int bx, u64 m) 49static __inline ieee754dp builddp(int s, int bx, u64 m)
50{ 50{
@@ -71,13 +71,13 @@ extern ieee754dp ieee754dp_bestnan(ieee754dp, ieee754dp);
71extern ieee754dp ieee754dp_format(int, int, u64); 71extern ieee754dp ieee754dp_format(int, int, u64);
72 72
73 73
74#define DPNORMRET2(s,e,m,name,a0,a1) \ 74#define DPNORMRET2(s, e, m, name, a0, a1) \
75{ \ 75{ \
76 ieee754dp V = ieee754dp_format(s,e,m); \ 76 ieee754dp V = ieee754dp_format(s, e, m); \
77 if(TSTX()) \ 77 if(TSTX()) \
78 return ieee754dp_xcpt(V,name,a0,a1); \ 78 return ieee754dp_xcpt(V, name, a0, a1); \
79 else \ 79 else \
80 return V; \ 80 return V; \
81} 81}
82 82
83#define DPNORMRET1(s,e,m,name,a0) DPNORMRET2(s,e,m,name,a0,a0) 83#define DPNORMRET1(s, e, m, name, a0) DPNORMRET2(s, e, m, name, a0, a0)
diff --git a/arch/mips/math-emu/ieee754int.h b/arch/mips/math-emu/ieee754int.h
index 4a5a81d6b893..1a846c5425cd 100644
--- a/arch/mips/math-emu/ieee754int.h
+++ b/arch/mips/math-emu/ieee754int.h
@@ -55,16 +55,16 @@
55#define DPBEXP(dp) (dp.parts.bexp) 55#define DPBEXP(dp) (dp.parts.bexp)
56#define DPMANT(dp) (dp.parts.mant) 56#define DPMANT(dp) (dp.parts.mant)
57 57
58#define CLPAIR(x,y) ((x)*6+(y)) 58#define CLPAIR(x, y) ((x)*6+(y))
59 59
60#define CLEARCX \ 60#define CLEARCX \
61 (ieee754_csr.cx = 0) 61 (ieee754_csr.cx = 0)
62 62
63#define SETCX(x) \ 63#define SETCX(x) \
64 (ieee754_csr.cx |= (x),ieee754_csr.sx |= (x)) 64 (ieee754_csr.cx |= (x), ieee754_csr.sx |= (x))
65 65
66#define SETANDTESTCX(x) \ 66#define SETANDTESTCX(x) \
67 (SETCX(x),ieee754_csr.mx & (x)) 67 (SETCX(x), ieee754_csr.mx & (x))
68 68
69#define TSTX() \ 69#define TSTX() \
70 (ieee754_csr.cx & ieee754_csr.mx) 70 (ieee754_csr.cx & ieee754_csr.mx)
@@ -76,7 +76,7 @@
76#define COMPYSP \ 76#define COMPYSP \
77 unsigned ym; int ye; int ys; int yc 77 unsigned ym; int ye; int ys; int yc
78 78
79#define EXPLODESP(v,vc,vs,ve,vm) \ 79#define EXPLODESP(v, vc, vs, ve, vm) \
80{\ 80{\
81 vs = SPSIGN(v);\ 81 vs = SPSIGN(v);\
82 ve = SPBEXP(v);\ 82 ve = SPBEXP(v);\
@@ -100,8 +100,8 @@
100 vc = IEEE754_CLASS_NORM;\ 100 vc = IEEE754_CLASS_NORM;\
101 }\ 101 }\
102} 102}
103#define EXPLODEXSP EXPLODESP(x,xc,xs,xe,xm) 103#define EXPLODEXSP EXPLODESP(x, xc, xs, xe, xm)
104#define EXPLODEYSP EXPLODESP(y,yc,ys,ye,ym) 104#define EXPLODEYSP EXPLODESP(y, yc, ys, ye, ym)
105 105
106 106
107#define COMPXDP \ 107#define COMPXDP \
@@ -110,7 +110,7 @@ u64 xm; int xe; int xs; int xc
110#define COMPYDP \ 110#define COMPYDP \
111u64 ym; int ye; int ys; int yc 111u64 ym; int ye; int ys; int yc
112 112
113#define EXPLODEDP(v,vc,vs,ve,vm) \ 113#define EXPLODEDP(v, vc, vs, ve, vm) \
114{\ 114{\
115 vm = DPMANT(v);\ 115 vm = DPMANT(v);\
116 vs = DPSIGN(v);\ 116 vs = DPSIGN(v);\
@@ -134,10 +134,10 @@ u64 ym; int ye; int ys; int yc
134 vc = IEEE754_CLASS_NORM;\ 134 vc = IEEE754_CLASS_NORM;\
135 }\ 135 }\
136} 136}
137#define EXPLODEXDP EXPLODEDP(x,xc,xs,xe,xm) 137#define EXPLODEXDP EXPLODEDP(x, xc, xs, xe, xm)
138#define EXPLODEYDP EXPLODEDP(y,yc,ys,ye,ym) 138#define EXPLODEYDP EXPLODEDP(y, yc, ys, ye, ym)
139 139
140#define FLUSHDP(v,vc,vs,ve,vm) \ 140#define FLUSHDP(v, vc, vs, ve, vm) \
141 if(vc==IEEE754_CLASS_DNORM) {\ 141 if(vc==IEEE754_CLASS_DNORM) {\
142 if(ieee754_csr.nod) {\ 142 if(ieee754_csr.nod) {\
143 SETCX(IEEE754_INEXACT);\ 143 SETCX(IEEE754_INEXACT);\
@@ -148,7 +148,7 @@ u64 ym; int ye; int ys; int yc
148 }\ 148 }\
149 } 149 }
150 150
151#define FLUSHSP(v,vc,vs,ve,vm) \ 151#define FLUSHSP(v, vc, vs, ve, vm) \
152 if(vc==IEEE754_CLASS_DNORM) {\ 152 if(vc==IEEE754_CLASS_DNORM) {\
153 if(ieee754_csr.nod) {\ 153 if(ieee754_csr.nod) {\
154 SETCX(IEEE754_INEXACT);\ 154 SETCX(IEEE754_INEXACT);\
@@ -159,7 +159,7 @@ u64 ym; int ye; int ys; int yc
159 }\ 159 }\
160 } 160 }
161 161
162#define FLUSHXDP FLUSHDP(x,xc,xs,xe,xm) 162#define FLUSHXDP FLUSHDP(x, xc, xs, xe, xm)
163#define FLUSHYDP FLUSHDP(y,yc,ys,ye,ym) 163#define FLUSHYDP FLUSHDP(y, yc, ys, ye, ym)
164#define FLUSHXSP FLUSHSP(x,xc,xs,xe,xm) 164#define FLUSHXSP FLUSHSP(x, xc, xs, xe, xm)
165#define FLUSHYSP FLUSHSP(y,yc,ys,ye,ym) 165#define FLUSHYSP FLUSHSP(y, yc, ys, ye, ym)
diff --git a/arch/mips/math-emu/ieee754sp.h b/arch/mips/math-emu/ieee754sp.h
index ae82f51297e5..9917c1e4d947 100644
--- a/arch/mips/math-emu/ieee754sp.h
+++ b/arch/mips/math-emu/ieee754sp.h
@@ -48,8 +48,8 @@
48/* convert denormal to normalized with extended exponent */ 48/* convert denormal to normalized with extended exponent */
49#define SPDNORMx(m,e) \ 49#define SPDNORMx(m,e) \
50 while( (m >> SP_MBITS) == 0) { m <<= 1; e--; } 50 while( (m >> SP_MBITS) == 0) { m <<= 1; e--; }
51#define SPDNORMX SPDNORMx(xm,xe) 51#define SPDNORMX SPDNORMx(xm, xe)
52#define SPDNORMY SPDNORMx(ym,ye) 52#define SPDNORMY SPDNORMx(ym, ye)
53 53
54static __inline ieee754sp buildsp(int s, int bx, unsigned m) 54static __inline ieee754sp buildsp(int s, int bx, unsigned m)
55{ 55{
@@ -77,13 +77,13 @@ extern ieee754sp ieee754sp_bestnan(ieee754sp, ieee754sp);
77extern ieee754sp ieee754sp_format(int, int, unsigned); 77extern ieee754sp ieee754sp_format(int, int, unsigned);
78 78
79 79
80#define SPNORMRET2(s,e,m,name,a0,a1) \ 80#define SPNORMRET2(s, e, m, name, a0, a1) \
81{ \ 81{ \
82 ieee754sp V = ieee754sp_format(s,e,m); \ 82 ieee754sp V = ieee754sp_format(s, e, m); \
83 if(TSTX()) \ 83 if(TSTX()) \
84 return ieee754sp_xcpt(V,name,a0,a1); \ 84 return ieee754sp_xcpt(V, name, a0, a1); \
85 else \ 85 else \
86 return V; \ 86 return V; \
87} 87}
88 88
89#define SPNORMRET1(s,e,m,name,a0) SPNORMRET2(s,e,m,name,a0,a0) 89#define SPNORMRET1(s, e, m, name, a0) SPNORMRET2(s, e, m, name, a0, a0)
diff --git a/arch/mips/mips-boards/atlas/atlas_gdb.c b/arch/mips/mips-boards/atlas/atlas_gdb.c
index fb65280f1780..00c98cff62dc 100644
--- a/arch/mips/mips-boards/atlas/atlas_gdb.c
+++ b/arch/mips/mips-boards/atlas/atlas_gdb.c
@@ -22,7 +22,7 @@
22#include <asm/mips-boards/saa9730_uart.h> 22#include <asm/mips-boards/saa9730_uart.h>
23 23
24#define INB(a) inb((unsigned long)a) 24#define INB(a) inb((unsigned long)a)
25#define OUTB(x,a) outb(x,(unsigned long)a) 25#define OUTB(x, a) outb(x, (unsigned long)a)
26 26
27/* 27/*
28 * This is the interface to the remote debugger stub 28 * This is the interface to the remote debugger stub
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
index 8232392750a8..f010261b75d8 100644
--- a/arch/mips/mips-boards/malta/malta_int.c
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -124,7 +124,7 @@ static void corehi_irqdispatch(void)
124{ 124{
125 unsigned int intedge, intsteer, pcicmd, pcibadaddr; 125 unsigned int intedge, intsteer, pcicmd, pcibadaddr;
126 unsigned int pcimstat, intisr, inten, intpol; 126 unsigned int pcimstat, intisr, inten, intpol;
127 unsigned int intrcause,datalo,datahi; 127 unsigned int intrcause, datalo, datahi;
128 struct pt_regs *regs = get_irq_regs(); 128 struct pt_regs *regs = get_irq_regs();
129 129
130 printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n"); 130 printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c
index e243d5efcb38..9a2636e56243 100644
--- a/arch/mips/mips-boards/malta/malta_setup.c
+++ b/arch/mips/mips-boards/malta/malta_setup.c
@@ -176,7 +176,7 @@ void __init plat_mem_setup(void)
176 0, /* orig-video-page */ 176 0, /* orig-video-page */
177 0, /* orig-video-mode */ 177 0, /* orig-video-mode */
178 80, /* orig-video-cols */ 178 80, /* orig-video-cols */
179 0,0,0, /* ega_ax, ega_bx, ega_cx */ 179 0, 0, 0, /* ega_ax, ega_bx, ega_cx */
180 25, /* orig-video-lines */ 180 25, /* orig-video-lines */
181 VIDEO_TYPE_VGAC, /* orig-video-isVGA */ 181 VIDEO_TYPE_VGAC, /* orig-video-isVGA */
182 16 /* orig-video-points */ 182 16 /* orig-video-points */
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 8b7b7c57baca..971f6c047b8a 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -164,12 +164,12 @@ static inline void tx49_blast_icache32(void)
164 /* I'm in even chunk. blast odd chunks */ 164 /* I'm in even chunk. blast odd chunks */
165 for (ws = 0; ws < ws_end; ws += ws_inc) 165 for (ws = 0; ws < ws_end; ws += ws_inc)
166 for (addr = start + 0x400; addr < end; addr += 0x400 * 2) 166 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
167 cache32_unroll32(addr|ws,Index_Invalidate_I); 167 cache32_unroll32(addr|ws, Index_Invalidate_I);
168 CACHE32_UNROLL32_ALIGN; 168 CACHE32_UNROLL32_ALIGN;
169 /* I'm in odd chunk. blast even chunks */ 169 /* I'm in odd chunk. blast even chunks */
170 for (ws = 0; ws < ws_end; ws += ws_inc) 170 for (ws = 0; ws < ws_end; ws += ws_inc)
171 for (addr = start; addr < end; addr += 0x400 * 2) 171 for (addr = start; addr < end; addr += 0x400 * 2)
172 cache32_unroll32(addr|ws,Index_Invalidate_I); 172 cache32_unroll32(addr|ws, Index_Invalidate_I);
173} 173}
174 174
175static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page) 175static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
@@ -195,12 +195,12 @@ static inline void tx49_blast_icache32_page_indexed(unsigned long page)
195 /* I'm in even chunk. blast odd chunks */ 195 /* I'm in even chunk. blast odd chunks */
196 for (ws = 0; ws < ws_end; ws += ws_inc) 196 for (ws = 0; ws < ws_end; ws += ws_inc)
197 for (addr = start + 0x400; addr < end; addr += 0x400 * 2) 197 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
198 cache32_unroll32(addr|ws,Index_Invalidate_I); 198 cache32_unroll32(addr|ws, Index_Invalidate_I);
199 CACHE32_UNROLL32_ALIGN; 199 CACHE32_UNROLL32_ALIGN;
200 /* I'm in odd chunk. blast even chunks */ 200 /* I'm in odd chunk. blast even chunks */
201 for (ws = 0; ws < ws_end; ws += ws_inc) 201 for (ws = 0; ws < ws_end; ws += ws_inc)
202 for (addr = start; addr < end; addr += 0x400 * 2) 202 for (addr = start; addr < end; addr += 0x400 * 2)
203 cache32_unroll32(addr|ws,Index_Invalidate_I); 203 cache32_unroll32(addr|ws, Index_Invalidate_I);
204} 204}
205 205
206static void (* r4k_blast_icache_page)(unsigned long addr); 206static void (* r4k_blast_icache_page)(unsigned long addr);
diff --git a/arch/mips/mm/cerr-sb1.c b/arch/mips/mm/cerr-sb1.c
index 4c72e650f9b6..e7f539e3284b 100644
--- a/arch/mips/mm/cerr-sb1.c
+++ b/arch/mips/mm/cerr-sb1.c
@@ -271,14 +271,22 @@ asmlinkage void sb1_cache_error(void)
271 271
272/* Parity lookup table. */ 272/* Parity lookup table. */
273static const uint8_t parity[256] = { 273static const uint8_t parity[256] = {
274 0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, 274 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
275 1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0, 275 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
276 1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0, 276 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
277 0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, 277 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
278 1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0, 278 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
279 0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, 279 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
280 0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, 280 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
281 1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0 281 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
282 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
283 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
284 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
285 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
286 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
287 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
288 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
289 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0
282}; 290};
283 291
284/* Masks to select bits for Hamming parity, mask_72_64[i] for bit[i] */ 292/* Masks to select bits for Hamming parity, mask_72_64[i] for bit[i] */
diff --git a/arch/mips/mm/pg-sb1.c b/arch/mips/mm/pg-sb1.c
index 82f42ace73c8..a3e98c243a89 100644
--- a/arch/mips/mm/pg-sb1.c
+++ b/arch/mips/mm/pg-sb1.c
@@ -188,9 +188,9 @@ static inline void copy_page_cpu(void *to, void *from)
188 : "+r" (src), "+r" (dst) 188 : "+r" (src), "+r" (dst)
189 : "r" (end) 189 : "r" (end)
190#ifdef CONFIG_64BIT 190#ifdef CONFIG_64BIT
191 : "$8","$9","$10","$11","memory"); 191 : "$8", "$9", "$10", "$11", "memory");
192#else 192#else
193 : "$2","$3","$6","$7","$8","$9","$10","$11","memory"); 193 : "$2", "$3", "$6", "$7", "$8", "$9", "$10", "$11", "memory");
194#endif 194#endif
195} 195}
196 196
diff --git a/arch/mips/mm/pgtable.c b/arch/mips/mm/pgtable.c
index c93aa6cbcaca..57df1c38e303 100644
--- a/arch/mips/mm/pgtable.c
+++ b/arch/mips/mm/pgtable.c
@@ -29,9 +29,9 @@ void show_mem(void)
29 shared += page_count(page) - 1; 29 shared += page_count(page) - 1;
30 } 30 }
31 printk("%d pages of RAM\n", total); 31 printk("%d pages of RAM\n", total);
32 printk("%d pages of HIGHMEM\n",highmem); 32 printk("%d pages of HIGHMEM\n", highmem);
33 printk("%d reserved pages\n",reserved); 33 printk("%d reserved pages\n", reserved);
34 printk("%d pages shared\n",shared); 34 printk("%d pages shared\n", shared);
35 printk("%d pages swap cached\n",cached); 35 printk("%d pages swap cached\n", cached);
36#endif 36#endif
37} 37}
diff --git a/arch/mips/mm/tlb-r8k.c b/arch/mips/mm/tlb-r8k.c
index 266a47d65eed..bd8409d8ff62 100644
--- a/arch/mips/mm/tlb-r8k.c
+++ b/arch/mips/mm/tlb-r8k.c
@@ -56,7 +56,7 @@ void local_flush_tlb_mm(struct mm_struct *mm)
56 int cpu = smp_processor_id(); 56 int cpu = smp_processor_id();
57 57
58 if (cpu_context(cpu, mm) != 0) 58 if (cpu_context(cpu, mm) != 0)
59 drop_mmu_context(mm,cpu); 59 drop_mmu_context(mm, cpu);
60} 60}
61 61
62void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, 62void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index c3da4fefbcb4..a61246d3533d 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -141,53 +141,53 @@ struct insn {
141 | (f) << FUNC_SH) 141 | (f) << FUNC_SH)
142 142
143static __initdata struct insn insn_table[] = { 143static __initdata struct insn insn_table[] = {
144 { insn_addiu, M(addiu_op,0,0,0,0,0), RS | RT | SIMM }, 144 { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
145 { insn_addu, M(spec_op,0,0,0,0,addu_op), RS | RT | RD }, 145 { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
146 { insn_and, M(spec_op,0,0,0,0,and_op), RS | RT | RD }, 146 { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
147 { insn_andi, M(andi_op,0,0,0,0,0), RS | RT | UIMM }, 147 { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
148 { insn_beq, M(beq_op,0,0,0,0,0), RS | RT | BIMM }, 148 { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
149 { insn_beql, M(beql_op,0,0,0,0,0), RS | RT | BIMM }, 149 { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
150 { insn_bgez, M(bcond_op,0,bgez_op,0,0,0), RS | BIMM }, 150 { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM },
151 { insn_bgezl, M(bcond_op,0,bgezl_op,0,0,0), RS | BIMM }, 151 { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM },
152 { insn_bltz, M(bcond_op,0,bltz_op,0,0,0), RS | BIMM }, 152 { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
153 { insn_bltzl, M(bcond_op,0,bltzl_op,0,0,0), RS | BIMM }, 153 { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM },
154 { insn_bne, M(bne_op,0,0,0,0,0), RS | RT | BIMM }, 154 { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
155 { insn_daddiu, M(daddiu_op,0,0,0,0,0), RS | RT | SIMM }, 155 { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
156 { insn_daddu, M(spec_op,0,0,0,0,daddu_op), RS | RT | RD }, 156 { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },
157 { insn_dmfc0, M(cop0_op,dmfc_op,0,0,0,0), RT | RD | SET}, 157 { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
158 { insn_dmtc0, M(cop0_op,dmtc_op,0,0,0,0), RT | RD | SET}, 158 { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
159 { insn_dsll, M(spec_op,0,0,0,0,dsll_op), RT | RD | RE }, 159 { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
160 { insn_dsll32, M(spec_op,0,0,0,0,dsll32_op), RT | RD | RE }, 160 { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE },
161 { insn_dsra, M(spec_op,0,0,0,0,dsra_op), RT | RD | RE }, 161 { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
162 { insn_dsrl, M(spec_op,0,0,0,0,dsrl_op), RT | RD | RE }, 162 { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
163 { insn_dsrl32, M(spec_op,0,0,0,0,dsrl32_op), RT | RD | RE }, 163 { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
164 { insn_dsubu, M(spec_op,0,0,0,0,dsubu_op), RS | RT | RD }, 164 { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
165 { insn_eret, M(cop0_op,cop_op,0,0,0,eret_op), 0 }, 165 { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 },
166 { insn_j, M(j_op,0,0,0,0,0), JIMM }, 166 { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
167 { insn_jal, M(jal_op,0,0,0,0,0), JIMM }, 167 { insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM },
168 { insn_jr, M(spec_op,0,0,0,0,jr_op), RS }, 168 { insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS },
169 { insn_ld, M(ld_op,0,0,0,0,0), RS | RT | SIMM }, 169 { insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
170 { insn_ll, M(ll_op,0,0,0,0,0), RS | RT | SIMM }, 170 { insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
171 { insn_lld, M(lld_op,0,0,0,0,0), RS | RT | SIMM }, 171 { insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
172 { insn_lui, M(lui_op,0,0,0,0,0), RT | SIMM }, 172 { insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM },
173 { insn_lw, M(lw_op,0,0,0,0,0), RS | RT | SIMM }, 173 { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
174 { insn_mfc0, M(cop0_op,mfc_op,0,0,0,0), RT | RD | SET}, 174 { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET},
175 { insn_mtc0, M(cop0_op,mtc_op,0,0,0,0), RT | RD | SET}, 175 { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},
176 { insn_ori, M(ori_op,0,0,0,0,0), RS | RT | UIMM }, 176 { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
177 { insn_rfe, M(cop0_op,cop_op,0,0,0,rfe_op), 0 }, 177 { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 },
178 { insn_sc, M(sc_op,0,0,0,0,0), RS | RT | SIMM }, 178 { insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
179 { insn_scd, M(scd_op,0,0,0,0,0), RS | RT | SIMM }, 179 { insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
180 { insn_sd, M(sd_op,0,0,0,0,0), RS | RT | SIMM }, 180 { insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
181 { insn_sll, M(spec_op,0,0,0,0,sll_op), RT | RD | RE }, 181 { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE },
182 { insn_sra, M(spec_op,0,0,0,0,sra_op), RT | RD | RE }, 182 { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE },
183 { insn_srl, M(spec_op,0,0,0,0,srl_op), RT | RD | RE }, 183 { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE },
184 { insn_subu, M(spec_op,0,0,0,0,subu_op), RS | RT | RD }, 184 { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD },
185 { insn_sw, M(sw_op,0,0,0,0,0), RS | RT | SIMM }, 185 { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
186 { insn_tlbp, M(cop0_op,cop_op,0,0,0,tlbp_op), 0 }, 186 { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 },
187 { insn_tlbwi, M(cop0_op,cop_op,0,0,0,tlbwi_op), 0 }, 187 { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 },
188 { insn_tlbwr, M(cop0_op,cop_op,0,0,0,tlbwr_op), 0 }, 188 { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 },
189 { insn_xor, M(spec_op,0,0,0,0,xor_op), RS | RT | RD }, 189 { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD },
190 { insn_xori, M(xori_op,0,0,0,0,0), RS | RT | UIMM }, 190 { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
191 { insn_invalid, 0, 0 } 191 { insn_invalid, 0, 0 }
192}; 192};
193 193
diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c
index 2b4e30c7d105..5443ea3596f8 100644
--- a/arch/mips/pci/pci-bcm1480.c
+++ b/arch/mips/pci/pci-bcm1480.c
@@ -49,8 +49,8 @@
49 * Macros for calculating offsets into config space given a device 49 * Macros for calculating offsets into config space given a device
50 * structure or dev/fun/reg 50 * structure or dev/fun/reg
51 */ 51 */
52#define CFGOFFSET(bus,devfn,where) (((bus)<<16)+((devfn)<<8)+(where)) 52#define CFGOFFSET(bus, devfn, where) (((bus)<<16)+((devfn)<<8)+(where))
53#define CFGADDR(bus,devfn,where) CFGOFFSET((bus)->number,(devfn),where) 53#define CFGADDR(bus, devfn, where) CFGOFFSET((bus)->number, (devfn), where)
54 54
55static void *cfg_space; 55static void *cfg_space;
56 56
@@ -255,7 +255,7 @@ static int __init bcm1480_pcibios_init(void)
255 register_pci_controller(&bcm1480_controller); 255 register_pci_controller(&bcm1480_controller);
256 256
257#ifdef CONFIG_VGA_CONSOLE 257#ifdef CONFIG_VGA_CONSOLE
258 take_over_console(&vga_con,0,MAX_NR_CONSOLES-1,1); 258 take_over_console(&vga_con, 0, MAX_NR_CONSOLES-1, 1);
259#endif 259#endif
260 return 0; 260 return 0;
261} 261}
diff --git a/arch/mips/pci/pci-bcm1480ht.c b/arch/mips/pci/pci-bcm1480ht.c
index ba2e34b09231..a63e3bd6b0ac 100644
--- a/arch/mips/pci/pci-bcm1480ht.c
+++ b/arch/mips/pci/pci-bcm1480ht.c
@@ -48,8 +48,8 @@
48 * Macros for calculating offsets into config space given a device 48 * Macros for calculating offsets into config space given a device
49 * structure or dev/fun/reg 49 * structure or dev/fun/reg
50 */ 50 */
51#define CFGOFFSET(bus,devfn,where) (((bus)<<16)+((devfn)<<8)+(where)) 51#define CFGOFFSET(bus, devfn, where) (((bus)<<16)+((devfn)<<8)+(where))
52#define CFGADDR(bus,devfn,where) CFGOFFSET((bus)->number,(devfn),where) 52#define CFGADDR(bus, devfn, where) CFGOFFSET((bus)->number, (devfn), where)
53 53
54static void *ht_cfg_space; 54static void *ht_cfg_space;
55 55
diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c
index c1ac6493155e..42e4d2c800fa 100644
--- a/arch/mips/pci/pci-sb1250.c
+++ b/arch/mips/pci/pci-sb1250.c
@@ -49,8 +49,8 @@
49 * Macros for calculating offsets into config space given a device 49 * Macros for calculating offsets into config space given a device
50 * structure or dev/fun/reg 50 * structure or dev/fun/reg
51 */ 51 */
52#define CFGOFFSET(bus,devfn,where) (((bus)<<16) + ((devfn)<<8) + (where)) 52#define CFGOFFSET(bus, devfn, where) (((bus)<<16) + ((devfn)<<8) + (where))
53#define CFGADDR(bus,devfn,where) CFGOFFSET((bus)->number,(devfn),where) 53#define CFGADDR(bus, devfn, where) CFGOFFSET((bus)->number, (devfn), where)
54 54
55static void *cfg_space; 55static void *cfg_space;
56 56
diff --git a/arch/mips/philips/pnx8550/common/proc.c b/arch/mips/philips/pnx8550/common/proc.c
index 416f834784bc..18b125e3b65d 100644
--- a/arch/mips/philips/pnx8550/common/proc.c
+++ b/arch/mips/philips/pnx8550/common/proc.c
@@ -33,14 +33,14 @@ static int pnx8550_timers_read(char* page, char** start, off_t offset, int count
33 int configPR = read_c0_config7(); 33 int configPR = read_c0_config7();
34 34
35 if (offset==0) { 35 if (offset==0) {
36 len += sprintf(&page[len],"Timer: count, compare, tc, status\n"); 36 len += sprintf(&page[len], "Timer: count, compare, tc, status\n");
37 len += sprintf(&page[len]," 1: %11i, %8i, %1i, %s\n", 37 len += sprintf(&page[len], " 1: %11i, %8i, %1i, %s\n",
38 read_c0_count(), read_c0_compare(), 38 read_c0_count(), read_c0_compare(),
39 (configPR>>6)&0x1, ((configPR>>3)&0x1)? "off":"on"); 39 (configPR>>6)&0x1, ((configPR>>3)&0x1)? "off":"on");
40 len += sprintf(&page[len]," 2: %11i, %8i, %1i, %s\n", 40 len += sprintf(&page[len], " 2: %11i, %8i, %1i, %s\n",
41 read_c0_count2(), read_c0_compare2(), 41 read_c0_count2(), read_c0_compare2(),
42 (configPR>>7)&0x1, ((configPR>>4)&0x1)? "off":"on"); 42 (configPR>>7)&0x1, ((configPR>>4)&0x1)? "off":"on");
43 len += sprintf(&page[len]," 3: %11i, %8i, %1i, %s\n", 43 len += sprintf(&page[len], " 3: %11i, %8i, %1i, %s\n",
44 read_c0_count3(), read_c0_compare3(), 44 read_c0_count3(), read_c0_compare3(),
45 (configPR>>8)&0x1, ((configPR>>5)&0x1)? "off":"on"); 45 (configPR>>8)&0x1, ((configPR>>5)&0x1)? "off":"on");
46 } 46 }
@@ -53,18 +53,18 @@ static int pnx8550_registers_read(char* page, char** start, off_t offset, int co
53 int len = 0; 53 int len = 0;
54 54
55 if (offset==0) { 55 if (offset==0) {
56 len += sprintf(&page[len],"config1: %#10.8x\n",read_c0_config1()); 56 len += sprintf(&page[len], "config1: %#10.8x\n", read_c0_config1());
57 len += sprintf(&page[len],"config2: %#10.8x\n",read_c0_config2()); 57 len += sprintf(&page[len], "config2: %#10.8x\n", read_c0_config2());
58 len += sprintf(&page[len],"config3: %#10.8x\n",read_c0_config3()); 58 len += sprintf(&page[len], "config3: %#10.8x\n", read_c0_config3());
59 len += sprintf(&page[len],"configPR: %#10.8x\n",read_c0_config7()); 59 len += sprintf(&page[len], "configPR: %#10.8x\n", read_c0_config7());
60 len += sprintf(&page[len],"status: %#10.8x\n",read_c0_status()); 60 len += sprintf(&page[len], "status: %#10.8x\n", read_c0_status());
61 len += sprintf(&page[len],"cause: %#10.8x\n",read_c0_cause()); 61 len += sprintf(&page[len], "cause: %#10.8x\n", read_c0_cause());
62 len += sprintf(&page[len],"count: %#10.8x\n",read_c0_count()); 62 len += sprintf(&page[len], "count: %#10.8x\n", read_c0_count());
63 len += sprintf(&page[len],"count_2: %#10.8x\n",read_c0_count2()); 63 len += sprintf(&page[len], "count_2: %#10.8x\n", read_c0_count2());
64 len += sprintf(&page[len],"count_3: %#10.8x\n",read_c0_count3()); 64 len += sprintf(&page[len], "count_3: %#10.8x\n", read_c0_count3());
65 len += sprintf(&page[len],"compare: %#10.8x\n",read_c0_compare()); 65 len += sprintf(&page[len], "compare: %#10.8x\n", read_c0_compare());
66 len += sprintf(&page[len],"compare_2: %#10.8x\n",read_c0_compare2()); 66 len += sprintf(&page[len], "compare_2: %#10.8x\n", read_c0_compare2());
67 len += sprintf(&page[len],"compare_3: %#10.8x\n",read_c0_compare3()); 67 len += sprintf(&page[len], "compare_3: %#10.8x\n", read_c0_compare3());
68 } 68 }
69 69
70 return len; 70 return len;
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_serial.c b/arch/mips/pmc-sierra/msp71xx/msp_serial.c
index e25bac537d77..15e7b8000b4c 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_serial.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_serial.c
@@ -117,7 +117,7 @@ void __init msp_serial_setup(void)
117 117
118 /* Initialize first serial port */ 118 /* Initialize first serial port */
119 up.mapbase = MSP_UART0_BASE; 119 up.mapbase = MSP_UART0_BASE;
120 up.membase = ioremap_nocache(up.mapbase,MSP_UART_REG_LEN); 120 up.membase = ioremap_nocache(up.mapbase, MSP_UART_REG_LEN);
121 up.irq = MSP_INT_UART0; 121 up.irq = MSP_INT_UART0;
122 up.uartclk = uartclk; 122 up.uartclk = uartclk;
123 up.regshift = 2; 123 up.regshift = 2;
@@ -145,9 +145,9 @@ void __init msp_serial_setup(void)
145 if( DEBUG_PORT_BASE == KSEG1ADDR(MSP_UART1_BASE) ) { 145 if( DEBUG_PORT_BASE == KSEG1ADDR(MSP_UART1_BASE) ) {
146 if( mips_machtype == MACH_MSP4200_FPGA 146 if( mips_machtype == MACH_MSP4200_FPGA
147 || mips_machtype == MACH_MSP7120_FPGA ) 147 || mips_machtype == MACH_MSP7120_FPGA )
148 initDebugPort(uartclk,19200); 148 initDebugPort(uartclk, 19200);
149 else 149 else
150 initDebugPort(uartclk,57600); 150 initDebugPort(uartclk, 57600);
151 } 151 }
152#endif 152#endif
153 break; 153 break;
@@ -157,7 +157,7 @@ void __init msp_serial_setup(void)
157 } 157 }
158 158
159 up.mapbase = MSP_UART1_BASE; 159 up.mapbase = MSP_UART1_BASE;
160 up.membase = ioremap_nocache(up.mapbase,MSP_UART_REG_LEN); 160 up.membase = ioremap_nocache(up.mapbase, MSP_UART_REG_LEN);
161 up.irq = MSP_INT_UART1; 161 up.irq = MSP_INT_UART1;
162 up.line = 1; 162 up.line = 1;
163 up.private_data = (void*)UART1_STATUS_REG; 163 up.private_data = (void*)UART1_STATUS_REG;
diff --git a/arch/mips/pmc-sierra/yosemite/ht.c b/arch/mips/pmc-sierra/yosemite/ht.c
index 1f7c999eb7c6..6380662bbf3c 100644
--- a/arch/mips/pmc-sierra/yosemite/ht.c
+++ b/arch/mips/pmc-sierra/yosemite/ht.c
@@ -115,7 +115,7 @@ static int titan_ht_config_read_word(struct pci_dev *device,
115 115
116u32 longswap(unsigned long l) 116u32 longswap(unsigned long l)
117{ 117{
118 unsigned char b1,b2,b3,b4; 118 unsigned char b1, b2, b3, b4;
119 119
120 b1 = l&255; 120 b1 = l&255;
121 b2 = (l>>8)&255; 121 b2 = (l>>8)&255;
diff --git a/arch/mips/sgi-ip27/ip27-smp.c b/arch/mips/sgi-ip27/ip27-smp.c
index 493777e39a01..a70656d42191 100644
--- a/arch/mips/sgi-ip27/ip27-smp.c
+++ b/arch/mips/sgi-ip27/ip27-smp.c
@@ -176,7 +176,7 @@ void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle)
176 unsigned long gp = (unsigned long)task_thread_info(idle); 176 unsigned long gp = (unsigned long)task_thread_info(idle);
177 unsigned long sp = __KSTK_TOS(idle); 177 unsigned long sp = __KSTK_TOS(idle);
178 178
179 LAUNCH_SLAVE(cputonasid(cpu),cputoslice(cpu), 179 LAUNCH_SLAVE(cputonasid(cpu), cputoslice(cpu),
180 (launch_proc_t)MAPPED_KERN_RW_TO_K0(smp_bootstrap), 180 (launch_proc_t)MAPPED_KERN_RW_TO_K0(smp_bootstrap),
181 0, (void *) sp, (void *) gp); 181 0, (void *) sp, (void *) gp);
182} 182}
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index cf979dbb282d..7aa79bf63c4a 100644
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -289,7 +289,7 @@ int bcm1480_steal_irq(int irq)
289 if (irq >= BCM1480_NR_IRQS) 289 if (irq >= BCM1480_NR_IRQS)
290 return -EINVAL; 290 return -EINVAL;
291 291
292 spin_lock_irqsave(&desc->lock,flags); 292 spin_lock_irqsave(&desc->lock, flags);
293 /* Don't allow sharing at all for these */ 293 /* Don't allow sharing at all for these */
294 if (desc->action != NULL) 294 if (desc->action != NULL)
295 retval = -EBUSY; 295 retval = -EBUSY;
@@ -297,7 +297,7 @@ int bcm1480_steal_irq(int irq)
297 desc->action = &bcm1480_dummy_action; 297 desc->action = &bcm1480_dummy_action;
298 desc->depth = 0; 298 desc->depth = 0;
299 } 299 }
300 spin_unlock_irqrestore(&desc->lock,flags); 300 spin_unlock_irqrestore(&desc->lock, flags);
301 return 0; 301 return 0;
302} 302}
303 303
@@ -431,8 +431,8 @@ void __init arch_init_irq(void)
431 431
432#include <linux/delay.h> 432#include <linux/delay.h>
433 433
434#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg))) 434#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
435#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg))) 435#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
436 436
437static void bcm1480_kgdb_interrupt(void) 437static void bcm1480_kgdb_interrupt(void)
438{ 438{
diff --git a/arch/mips/sibyte/cfe/console.c b/arch/mips/sibyte/cfe/console.c
index 7a4ecfcde48d..81e3d54376e9 100644
--- a/arch/mips/sibyte/cfe/console.c
+++ b/arch/mips/sibyte/cfe/console.c
@@ -14,7 +14,7 @@ static void cfe_console_write(struct console *cons, const char *str,
14{ 14{
15 int i, last, written; 15 int i, last, written;
16 16
17 for (i=0,last=0; i<count; i++) { 17 for (i=0, last=0; i<count; i++) {
18 if (!str[i]) 18 if (!str[i])
19 /* XXXKW can/should this ever happen? */ 19 /* XXXKW can/should this ever happen? */
20 return; 20 return;
diff --git a/arch/mips/sibyte/cfe/setup.c b/arch/mips/sibyte/cfe/setup.c
index 147b7fb02e64..dbd6e6fdd3f9 100644
--- a/arch/mips/sibyte/cfe/setup.c
+++ b/arch/mips/sibyte/cfe/setup.c
@@ -309,7 +309,7 @@ void __init prom_init(void)
309 } 309 }
310 310
311#ifdef CONFIG_KGDB 311#ifdef CONFIG_KGDB
312 if ((arg = strstr(arcs_cmdline,"kgdb=duart")) != NULL) 312 if ((arg = strstr(arcs_cmdline, "kgdb=duart")) != NULL)
313 kgdb_port = (arg[10] == '0') ? 0 : 1; 313 kgdb_port = (arg[10] == '0') ? 0 : 1;
314 else 314 else
315 kgdb_port = 1; 315 kgdb_port = 1;
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index 6a4cc84194a9..7659174819c6 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -259,7 +259,7 @@ int sb1250_steal_irq(int irq)
259 if (irq >= SB1250_NR_IRQS) 259 if (irq >= SB1250_NR_IRQS)
260 return -EINVAL; 260 return -EINVAL;
261 261
262 spin_lock_irqsave(&desc->lock,flags); 262 spin_lock_irqsave(&desc->lock, flags);
263 /* Don't allow sharing at all for these */ 263 /* Don't allow sharing at all for these */
264 if (desc->action != NULL) 264 if (desc->action != NULL)
265 retval = -EBUSY; 265 retval = -EBUSY;
@@ -267,7 +267,7 @@ int sb1250_steal_irq(int irq)
267 desc->action = &sb1250_dummy_action; 267 desc->action = &sb1250_dummy_action;
268 desc->depth = 0; 268 desc->depth = 0;
269 } 269 }
270 spin_unlock_irqrestore(&desc->lock,flags); 270 spin_unlock_irqrestore(&desc->lock, flags);
271 return 0; 271 return 0;
272} 272}
273 273
@@ -381,8 +381,8 @@ void __init arch_init_irq(void)
381 381
382#include <linux/delay.h> 382#include <linux/delay.h>
383 383
384#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg))) 384#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
385#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg))) 385#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
386 386
387static void sb1250_kgdb_interrupt(void) 387static void sb1250_kgdb_interrupt(void)
388{ 388{
diff --git a/arch/mips/sibyte/sb1250/prom.c b/arch/mips/sibyte/sb1250/prom.c
index f07ad3baccab..cf8f6b3de86c 100644
--- a/arch/mips/sibyte/sb1250/prom.c
+++ b/arch/mips/sibyte/sb1250/prom.c
@@ -66,7 +66,7 @@ static void prom_linux_exit(void)
66{ 66{
67#ifdef CONFIG_SMP 67#ifdef CONFIG_SMP
68 if (smp_processor_id()) { 68 if (smp_processor_id()) {
69 smp_call_function(prom_cpu0_exit,NULL,1,1); 69 smp_call_function(prom_cpu0_exit, NULL, 1, 1);
70 } 70 }
71#endif 71#endif
72 while(1); 72 while(1);
diff --git a/arch/mips/sibyte/swarm/dbg_io.c b/arch/mips/sibyte/swarm/dbg_io.c
index 75ce14c8eb69..b97ae3048482 100644
--- a/arch/mips/sibyte/swarm/dbg_io.c
+++ b/arch/mips/sibyte/swarm/dbg_io.c
@@ -37,8 +37,8 @@ static int duart_initialized = 0; /* 0: need to be init'ed by kgdb */
37/* -------------------- END OF CONFIG --------------------- */ 37/* -------------------- END OF CONFIG --------------------- */
38extern int kgdb_port; 38extern int kgdb_port;
39 39
40#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg))) 40#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
41#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg))) 41#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
42 42
43void putDebugChar(unsigned char c); 43void putDebugChar(unsigned char c);
44unsigned char getDebugChar(void); 44unsigned char getDebugChar(void);
diff --git a/arch/mips/sni/reset.c b/arch/mips/sni/reset.c
index 38b6a97a31b5..79f8d70f48c9 100644
--- a/arch/mips/sni/reset.c
+++ b/arch/mips/sni/reset.c
@@ -35,7 +35,7 @@ void sni_machine_restart(char *command)
35 kb_wait(); 35 kb_wait();
36 for (j = 0; j < 100000 ; j++) 36 for (j = 0; j < 100000 ; j++)
37 /* nothing */; 37 /* nothing */;
38 outb_p(0xfe,0x64); /* pulse reset low */ 38 outb_p(0xfe, 0x64); /* pulse reset low */
39 } 39 }
40 } 40 }
41} 41}
diff --git a/arch/mips/sni/sniprom.c b/arch/mips/sni/sniprom.c
index 11eddd43458d..eff4b89d7b75 100644
--- a/arch/mips/sni/sniprom.c
+++ b/arch/mips/sni/sniprom.c
@@ -233,7 +233,7 @@ void __init prom_init(void)
233 systype = "RM300-Exx"; 233 systype = "RM300-Exx";
234 break; 234 break;
235 } 235 }
236 pr_debug("Found SNI brdtype %02x name %s\n", sni_brd_type,systype); 236 pr_debug("Found SNI brdtype %02x name %s\n", sni_brd_type, systype);
237 237
238#ifdef DEBUG 238#ifdef DEBUG
239 sni_idprom_dump(); 239 sni_idprom_dump();
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
index 305eb12f84cc..3f808b629242 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
@@ -176,7 +176,7 @@ static const u32 toshiba_rbtx4927_irq_debug_flag =
176 printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \ 176 printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
177 } 177 }
178#else 178#else
179#define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag,str...) 179#define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag, str...)
180#endif 180#endif
181 181
182 182
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
index 4f302062b2d6..acaf613358c7 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
@@ -122,7 +122,7 @@ static const u32 toshiba_rbtx4927_setup_debug_flag =
122 printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \ 122 printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
123 } 123 }
124#else 124#else
125#define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...) 125#define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag, str...)
126#endif 126#endif
127 127
128/* These functions are used for rebooting or halting the machine*/ 128/* These functions are used for rebooting or halting the machine*/
@@ -497,7 +497,7 @@ void __init tx4927_pci_setup(void)
497 "Internal"); 497 "Internal");
498 called = 1; 498 called = 1;
499 } 499 }
500 printk("%s PCIC --%s PCICLK:",toshiba_name, 500 printk("%s PCIC --%s PCICLK:", toshiba_name,
501 (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : ""); 501 (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : "");
502 if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) { 502 if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) {
503 int pciclk = 0; 503 int pciclk = 0;
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/setup.c b/arch/mips/tx4938/toshiba_rbtx4938/setup.c
index 304b406fcb9d..ceecaf498957 100644
--- a/arch/mips/tx4938/toshiba_rbtx4938/setup.c
+++ b/arch/mips/tx4938/toshiba_rbtx4938/setup.c
@@ -457,9 +457,9 @@ extern struct pci_controller tx4938_pci_controller[];
457static int __init tx4938_pcibios_init(void) 457static int __init tx4938_pcibios_init(void)
458{ 458{
459 unsigned long mem_base[2]; 459 unsigned long mem_base[2];
460 unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0,TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */ 460 unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0, TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */
461 unsigned long io_base[2]; 461 unsigned long io_base[2];
462 unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0,TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */ 462 unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0, TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */
463 /* TX4938 PCIC1: 64K MEM/IO is enough for ETH0,ETH1 */ 463 /* TX4938 PCIC1: 64K MEM/IO is enough for ETH0,ETH1 */
464 int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB); 464 int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB);
465 465
diff --git a/arch/mips/vr41xx/nec-cmbvr4133/init.c b/arch/mips/vr41xx/nec-cmbvr4133/init.c
index ae1af6b21c45..7c5e18ee2231 100644
--- a/arch/mips/vr41xx/nec-cmbvr4133/init.c
+++ b/arch/mips/vr41xx/nec-cmbvr4133/init.c
@@ -36,7 +36,7 @@ void disable_pcnet(void)
36 */ 36 */
37 37
38 writel((2 << 16) | 38 writel((2 << 16) |
39 (PCI_DEVFN(1,0) << 8) | 39 (PCI_DEVFN(1, 0) << 8) |
40 (0 & 0xfc) | 40 (0 & 0xfc) |
41 1UL, 41 1UL,
42 PCICONFAREG); 42 PCICONFAREG);
@@ -44,7 +44,7 @@ void disable_pcnet(void)
44 data = readl(PCICONFDREG); 44 data = readl(PCICONFDREG);
45 45
46 writel((2 << 16) | 46 writel((2 << 16) |
47 (PCI_DEVFN(1,0) << 8) | 47 (PCI_DEVFN(1, 0) << 8) |
48 (4 & 0xfc) | 48 (4 & 0xfc) |
49 1UL, 49 1UL,
50 PCICONFAREG); 50 PCICONFAREG);
@@ -52,7 +52,7 @@ void disable_pcnet(void)
52 data = readl(PCICONFDREG); 52 data = readl(PCICONFDREG);
53 53
54 writel((2 << 16) | 54 writel((2 << 16) |
55 (PCI_DEVFN(1,0) << 8) | 55 (PCI_DEVFN(1, 0) << 8) |
56 (4 & 0xfc) | 56 (4 & 0xfc) |
57 1UL, 57 1UL,
58 PCICONFAREG); 58 PCICONFAREG);
diff --git a/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c b/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c
index f45caccedc07..1341f3287d04 100644
--- a/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c
+++ b/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c
@@ -38,7 +38,7 @@
38 outb_p((dev_no), DATA_PORT(port)); \ 38 outb_p((dev_no), DATA_PORT(port)); \
39 } while(0) 39 } while(0)
40 40
41#define WRITE_CONFIG_DATA(port,index,data) \ 41#define WRITE_CONFIG_DATA(port, index, data) \
42 do { \ 42 do { \
43 outb_p((index), INDEX_PORT(port)); \ 43 outb_p((index), INDEX_PORT(port)); \
44 outb_p((data), DATA_PORT(port)); \ 44 outb_p((data), DATA_PORT(port)); \
@@ -206,8 +206,8 @@ static inline u16 ali_config_readw(u8 reg, int devfn)
206int vr4133_rockhopper = 0; 206int vr4133_rockhopper = 0;
207void __init ali_m5229_preinit(void) 207void __init ali_m5229_preinit(void)
208{ 208{
209 if (ali_config_readw(PCI_VENDOR_ID,16) == PCI_VENDOR_ID_AL && 209 if (ali_config_readw(PCI_VENDOR_ID, 16) == PCI_VENDOR_ID_AL &&
210 ali_config_readw(PCI_DEVICE_ID,16) == PCI_DEVICE_ID_AL_M1533) { 210 ali_config_readw(PCI_DEVICE_ID, 16) == PCI_DEVICE_ID_AL_M1533) {
211 printk(KERN_INFO "Found an NEC Rockhopper \n"); 211 printk(KERN_INFO "Found an NEC Rockhopper \n");
212 vr4133_rockhopper = 1; 212 vr4133_rockhopper = 1;
213 /* 213 /*
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
index 0b3ff9c48409..0bb7a93b7a5e 100644
--- a/include/asm-mips/addrspace.h
+++ b/include/asm-mips/addrspace.h
@@ -123,10 +123,10 @@
123/* 123/*
124 * 64-bit address conversions 124 * 64-bit address conversions
125 */ 125 */
126#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED,(p)) 126#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p))
127#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE,(p)) 127#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
128#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK) 128#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
129#define PHYS_TO_XKPHYS(cm,a) (_CONST64_(0x8000000000000000) | \ 129#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \
130 ((cm)<<59) | (a)) 130 ((cm)<<59) | (a))
131 131
132/* 132/*
diff --git a/include/asm-mips/asm.h b/include/asm-mips/asm.h
index 838eb3144d81..12e17581b823 100644
--- a/include/asm-mips/asm.h
+++ b/include/asm-mips/asm.h
@@ -21,11 +21,11 @@
21 21
22#ifndef CAT 22#ifndef CAT
23#ifdef __STDC__ 23#ifdef __STDC__
24#define __CAT(str1,str2) str1##str2 24#define __CAT(str1, str2) str1##str2
25#else 25#else
26#define __CAT(str1,str2) str1/**/str2 26#define __CAT(str1, str2) str1/**/str2
27#endif 27#endif
28#define CAT(str1,str2) __CAT(str1,str2) 28#define CAT(str1, str2) __CAT(str1, str2)
29#endif 29#endif
30 30
31/* 31/*
@@ -51,9 +51,9 @@
51#define LEAF(symbol) \ 51#define LEAF(symbol) \
52 .globl symbol; \ 52 .globl symbol; \
53 .align 2; \ 53 .align 2; \
54 .type symbol,@function; \ 54 .type symbol, @function; \
55 .ent symbol,0; \ 55 .ent symbol, 0; \
56symbol: .frame sp,0,ra 56symbol: .frame sp, 0, ra
57 57
58/* 58/*
59 * NESTED - declare nested routine entry point 59 * NESTED - declare nested routine entry point
@@ -61,8 +61,8 @@ symbol: .frame sp,0,ra
61#define NESTED(symbol, framesize, rpc) \ 61#define NESTED(symbol, framesize, rpc) \
62 .globl symbol; \ 62 .globl symbol; \
63 .align 2; \ 63 .align 2; \
64 .type symbol,@function; \ 64 .type symbol, @function; \
65 .ent symbol,0; \ 65 .ent symbol, 0; \
66symbol: .frame sp, framesize, rpc 66symbol: .frame sp, framesize, rpc
67 67
68/* 68/*
@@ -70,7 +70,7 @@ symbol: .frame sp, framesize, rpc
70 */ 70 */
71#define END(function) \ 71#define END(function) \
72 .end function; \ 72 .end function; \
73 .size function,.-function 73 .size function, .-function
74 74
75/* 75/*
76 * EXPORT - export definition of symbol 76 * EXPORT - export definition of symbol
@@ -84,7 +84,7 @@ symbol:
84 */ 84 */
85#define FEXPORT(symbol) \ 85#define FEXPORT(symbol) \
86 .globl symbol; \ 86 .globl symbol; \
87 .type symbol,@function; \ 87 .type symbol, @function; \
88symbol: 88symbol:
89 89
90/* 90/*
@@ -97,7 +97,7 @@ symbol = value
97#define PANIC(msg) \ 97#define PANIC(msg) \
98 .set push; \ 98 .set push; \
99 .set reorder; \ 99 .set reorder; \
100 PTR_LA a0,8f; \ 100 PTR_LA a0, 8f; \
101 jal panic; \ 101 jal panic; \
1029: b 9b; \ 1029: b 9b; \
103 .set pop; \ 103 .set pop; \
@@ -110,7 +110,7 @@ symbol = value
110#define PRINT(string) \ 110#define PRINT(string) \
111 .set push; \ 111 .set push; \
112 .set reorder; \ 112 .set reorder; \
113 PTR_LA a0,8f; \ 113 PTR_LA a0, 8f; \
114 jal printk; \ 114 jal printk; \
115 .set pop; \ 115 .set pop; \
116 TEXT(string) 116 TEXT(string)
@@ -146,19 +146,19 @@ symbol = value
146#define PREF(hint,addr) \ 146#define PREF(hint,addr) \
147 .set push; \ 147 .set push; \
148 .set mips4; \ 148 .set mips4; \
149 pref hint,addr; \ 149 pref hint, addr; \
150 .set pop 150 .set pop
151 151
152#define PREFX(hint,addr) \ 152#define PREFX(hint,addr) \
153 .set push; \ 153 .set push; \
154 .set mips4; \ 154 .set mips4; \
155 prefx hint,addr; \ 155 prefx hint, addr; \
156 .set pop 156 .set pop
157 157
158#else /* !CONFIG_CPU_HAS_PREFETCH */ 158#else /* !CONFIG_CPU_HAS_PREFETCH */
159 159
160#define PREF(hint,addr) 160#define PREF(hint, addr)
161#define PREFX(hint,addr) 161#define PREFX(hint, addr)
162 162
163#endif /* !CONFIG_CPU_HAS_PREFETCH */ 163#endif /* !CONFIG_CPU_HAS_PREFETCH */
164 164
@@ -166,43 +166,43 @@ symbol = value
166 * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs. 166 * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
167 */ 167 */
168#if (_MIPS_ISA == _MIPS_ISA_MIPS1) 168#if (_MIPS_ISA == _MIPS_ISA_MIPS1)
169#define MOVN(rd,rs,rt) \ 169#define MOVN(rd, rs, rt) \
170 .set push; \ 170 .set push; \
171 .set reorder; \ 171 .set reorder; \
172 beqz rt,9f; \ 172 beqz rt, 9f; \
173 move rd,rs; \ 173 move rd, rs; \
174 .set pop; \ 174 .set pop; \
1759: 1759:
176#define MOVZ(rd,rs,rt) \ 176#define MOVZ(rd, rs, rt) \
177 .set push; \ 177 .set push; \
178 .set reorder; \ 178 .set reorder; \
179 bnez rt,9f; \ 179 bnez rt, 9f; \
180 move rd,rs; \ 180 move rd, rs; \
181 .set pop; \ 181 .set pop; \
1829: 1829:
183#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */ 183#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
184#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) 184#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
185#define MOVN(rd,rs,rt) \ 185#define MOVN(rd, rs, rt) \
186 .set push; \ 186 .set push; \
187 .set noreorder; \ 187 .set noreorder; \
188 bnezl rt,9f; \ 188 bnezl rt, 9f; \
189 move rd,rs; \ 189 move rd, rs; \
190 .set pop; \ 190 .set pop; \
1919: 1919:
192#define MOVZ(rd,rs,rt) \ 192#define MOVZ(rd, rs, rt) \
193 .set push; \ 193 .set push; \
194 .set noreorder; \ 194 .set noreorder; \
195 beqzl rt,9f; \ 195 beqzl rt, 9f; \
196 move rd,rs; \ 196 move rd, rs; \
197 .set pop; \ 197 .set pop; \
1989: 1989:
199#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */ 199#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
200#if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \ 200#if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
201 (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64) 201 (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
202#define MOVN(rd,rs,rt) \ 202#define MOVN(rd, rs, rt) \
203 movn rd,rs,rt 203 movn rd, rs, rt
204#define MOVZ(rd,rs,rt) \ 204#define MOVZ(rd, rs, rt) \
205 movz rd,rs,rt 205 movz rd, rs, rt
206#endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */ 206#endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */
207 207
208/* 208/*
@@ -396,6 +396,6 @@ symbol = value
396#define MTC0 dmtc0 396#define MTC0 dmtc0
397#endif 397#endif
398 398
399#define SSNOP sll zero,zero,1 399#define SSNOP sll zero, zero, 1
400 400
401#endif /* __ASM_ASM_H */ 401#endif /* __ASM_ASM_H */
diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h
index 7d8003769a44..a798d6299a79 100644
--- a/include/asm-mips/atomic.h
+++ b/include/asm-mips/atomic.h
@@ -39,7 +39,7 @@ typedef struct { volatile int counter; } atomic_t;
39 * 39 *
40 * Atomically sets the value of @v to @i. 40 * Atomically sets the value of @v to @i.
41 */ 41 */
42#define atomic_set(v,i) ((v)->counter = (i)) 42#define atomic_set(v, i) ((v)->counter = (i))
43 43
44/* 44/*
45 * atomic_add - add integer to atomic variable 45 * atomic_add - add integer to atomic variable
@@ -335,8 +335,8 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
335} 335}
336#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) 336#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
337 337
338#define atomic_dec_return(v) atomic_sub_return(1,(v)) 338#define atomic_dec_return(v) atomic_sub_return(1, (v))
339#define atomic_inc_return(v) atomic_add_return(1,(v)) 339#define atomic_inc_return(v) atomic_add_return(1, (v))
340 340
341/* 341/*
342 * atomic_sub_and_test - subtract value from variable and test result 342 * atomic_sub_and_test - subtract value from variable and test result
@@ -347,7 +347,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
347 * true if the result is zero, or false for all 347 * true if the result is zero, or false for all
348 * other cases. 348 * other cases.
349 */ 349 */
350#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0) 350#define atomic_sub_and_test(i, v) (atomic_sub_return((i), (v)) == 0)
351 351
352/* 352/*
353 * atomic_inc_and_test - increment and test 353 * atomic_inc_and_test - increment and test
@@ -381,7 +381,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
381 * 381 *
382 * Atomically increments @v by 1. 382 * Atomically increments @v by 1.
383 */ 383 */
384#define atomic_inc(v) atomic_add(1,(v)) 384#define atomic_inc(v) atomic_add(1, (v))
385 385
386/* 386/*
387 * atomic_dec - decrement and test 387 * atomic_dec - decrement and test
@@ -389,7 +389,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
389 * 389 *
390 * Atomically decrements @v by 1. 390 * Atomically decrements @v by 1.
391 */ 391 */
392#define atomic_dec(v) atomic_sub(1,(v)) 392#define atomic_dec(v) atomic_sub(1, (v))
393 393
394/* 394/*
395 * atomic_add_negative - add and test if negative 395 * atomic_add_negative - add and test if negative
@@ -400,7 +400,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
400 * if the result is negative, or false when 400 * if the result is negative, or false when
401 * result is greater than or equal to zero. 401 * result is greater than or equal to zero.
402 */ 402 */
403#define atomic_add_negative(i,v) (atomic_add_return(i, (v)) < 0) 403#define atomic_add_negative(i, v) (atomic_add_return(i, (v)) < 0)
404 404
405#ifdef CONFIG_64BIT 405#ifdef CONFIG_64BIT
406 406
@@ -420,7 +420,7 @@ typedef struct { volatile long counter; } atomic64_t;
420 * @v: pointer of type atomic64_t 420 * @v: pointer of type atomic64_t
421 * @i: required value 421 * @i: required value
422 */ 422 */
423#define atomic64_set(v,i) ((v)->counter = (i)) 423#define atomic64_set(v, i) ((v)->counter = (i))
424 424
425/* 425/*
426 * atomic64_add - add integer to atomic variable 426 * atomic64_add - add integer to atomic variable
@@ -718,8 +718,8 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
718 718
719#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0) 719#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
720 720
721#define atomic64_dec_return(v) atomic64_sub_return(1,(v)) 721#define atomic64_dec_return(v) atomic64_sub_return(1, (v))
722#define atomic64_inc_return(v) atomic64_add_return(1,(v)) 722#define atomic64_inc_return(v) atomic64_add_return(1, (v))
723 723
724/* 724/*
725 * atomic64_sub_and_test - subtract value from variable and test result 725 * atomic64_sub_and_test - subtract value from variable and test result
@@ -730,7 +730,7 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
730 * true if the result is zero, or false for all 730 * true if the result is zero, or false for all
731 * other cases. 731 * other cases.
732 */ 732 */
733#define atomic64_sub_and_test(i,v) (atomic64_sub_return((i), (v)) == 0) 733#define atomic64_sub_and_test(i, v) (atomic64_sub_return((i), (v)) == 0)
734 734
735/* 735/*
736 * atomic64_inc_and_test - increment and test 736 * atomic64_inc_and_test - increment and test
@@ -764,7 +764,7 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
764 * 764 *
765 * Atomically increments @v by 1. 765 * Atomically increments @v by 1.
766 */ 766 */
767#define atomic64_inc(v) atomic64_add(1,(v)) 767#define atomic64_inc(v) atomic64_add(1, (v))
768 768
769/* 769/*
770 * atomic64_dec - decrement and test 770 * atomic64_dec - decrement and test
@@ -772,7 +772,7 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
772 * 772 *
773 * Atomically decrements @v by 1. 773 * Atomically decrements @v by 1.
774 */ 774 */
775#define atomic64_dec(v) atomic64_sub(1,(v)) 775#define atomic64_dec(v) atomic64_sub(1, (v))
776 776
777/* 777/*
778 * atomic64_add_negative - add and test if negative 778 * atomic64_add_negative - add and test if negative
@@ -783,7 +783,7 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
783 * if the result is negative, or false when 783 * if the result is negative, or false when
784 * result is greater than or equal to zero. 784 * result is greater than or equal to zero.
785 */ 785 */
786#define atomic64_add_negative(i,v) (atomic64_add_return(i, (v)) < 0) 786#define atomic64_add_negative(i, v) (atomic64_add_return(i, (v)) < 0)
787 787
788#endif /* CONFIG_64BIT */ 788#endif /* CONFIG_64BIT */
789 789
diff --git a/include/asm-mips/cmpxchg.h b/include/asm-mips/cmpxchg.h
index c5b4708e003b..a5ec0e5dc5b8 100644
--- a/include/asm-mips/cmpxchg.h
+++ b/include/asm-mips/cmpxchg.h
@@ -72,7 +72,7 @@
72 */ 72 */
73extern void __cmpxchg_called_with_bad_pointer(void); 73extern void __cmpxchg_called_with_bad_pointer(void);
74 74
75#define __cmpxchg(ptr,old,new,barrier) \ 75#define __cmpxchg(ptr, old, new, barrier) \
76({ \ 76({ \
77 __typeof__(ptr) __ptr = (ptr); \ 77 __typeof__(ptr) __ptr = (ptr); \
78 __typeof__(*(ptr)) __old = (old); \ 78 __typeof__(*(ptr)) __old = (old); \
@@ -102,6 +102,6 @@ extern void __cmpxchg_called_with_bad_pointer(void);
102}) 102})
103 103
104#define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_llsc_mb()) 104#define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_llsc_mb())
105#define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new,) 105#define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new, )
106 106
107#endif /* __ASM_CMPXCHG_H */ 107#endif /* __ASM_CMPXCHG_H */
diff --git a/include/asm-mips/delay.h b/include/asm-mips/delay.h
index 223d156efb9f..fab32131e9b4 100644
--- a/include/asm-mips/delay.h
+++ b/include/asm-mips/delay.h
@@ -81,7 +81,7 @@ static inline void __udelay(unsigned long usecs, unsigned long lpj)
81 81
82#define __udelay_val cpu_data[raw_smp_processor_id()].udelay_val 82#define __udelay_val cpu_data[raw_smp_processor_id()].udelay_val
83 83
84#define udelay(usecs) __udelay((usecs),__udelay_val) 84#define udelay(usecs) __udelay((usecs), __udelay_val)
85 85
86/* make sure "usecs *= ..." in udelay do not overflow. */ 86/* make sure "usecs *= ..." in udelay do not overflow. */
87#if HZ >= 1000 87#if HZ >= 1000
diff --git a/include/asm-mips/floppy.h b/include/asm-mips/floppy.h
index dcadd8562523..a62d0990c8ae 100644
--- a/include/asm-mips/floppy.h
+++ b/include/asm-mips/floppy.h
@@ -49,7 +49,7 @@ static inline void fd_cacheflush(char * addr, long size)
49 * Actually this needs to be a bit more complicated since the so much different 49 * Actually this needs to be a bit more complicated since the so much different
50 * hardware available with MIPS CPUs ... 50 * hardware available with MIPS CPUs ...
51 */ 51 */
52#define CROSS_64KB(a,s) ((unsigned long)(a)/K_64 != ((unsigned long)(a) + (s) - 1) / K_64) 52#define CROSS_64KB(a, s) ((unsigned long)(a)/K_64 != ((unsigned long)(a) + (s) - 1) / K_64)
53 53
54#define EXTRA_FLOPPY_PARAMS 54#define EXTRA_FLOPPY_PARAMS
55 55
diff --git a/include/asm-mips/fw/cfe/cfe_api.h b/include/asm-mips/fw/cfe/cfe_api.h
index d8230cc53b81..41cf050b6810 100644
--- a/include/asm-mips/fw/cfe/cfe_api.h
+++ b/include/asm-mips/fw/cfe/cfe_api.h
@@ -136,25 +136,25 @@ int64_t cfe_getticks(void);
136 */ 136 */
137#ifdef CFE_API_IMPL_NAMESPACE 137#ifdef CFE_API_IMPL_NAMESPACE
138#define cfe_close(a) __cfe_close(a) 138#define cfe_close(a) __cfe_close(a)
139#define cfe_cpu_start(a,b,c,d,e) __cfe_cpu_start(a,b,c,d,e) 139#define cfe_cpu_start(a, b, c, d, e) __cfe_cpu_start(a, b, c, d, e)
140#define cfe_cpu_stop(a) __cfe_cpu_stop(a) 140#define cfe_cpu_stop(a) __cfe_cpu_stop(a)
141#define cfe_enumenv(a,b,d,e,f) __cfe_enumenv(a,b,d,e,f) 141#define cfe_enumenv(a, b, d, e, f) __cfe_enumenv(a, b, d, e, f)
142#define cfe_enummem(a,b,c,d,e) __cfe_enummem(a,b,c,d,e) 142#define cfe_enummem(a, b, c, d, e) __cfe_enummem(a, b, c, d, e)
143#define cfe_exit(a,b) __cfe_exit(a,b) 143#define cfe_exit(a, b) __cfe_exit(a, b)
144#define cfe_flushcache(a) __cfe_cacheflush(a) 144#define cfe_flushcache(a) __cfe_cacheflush(a)
145#define cfe_getdevinfo(a) __cfe_getdevinfo(a) 145#define cfe_getdevinfo(a) __cfe_getdevinfo(a)
146#define cfe_getenv(a,b,c) __cfe_getenv(a,b,c) 146#define cfe_getenv(a, b, c) __cfe_getenv(a, b, c)
147#define cfe_getfwinfo(a) __cfe_getfwinfo(a) 147#define cfe_getfwinfo(a) __cfe_getfwinfo(a)
148#define cfe_getstdhandle(a) __cfe_getstdhandle(a) 148#define cfe_getstdhandle(a) __cfe_getstdhandle(a)
149#define cfe_init(a,b) __cfe_init(a,b) 149#define cfe_init(a, b) __cfe_init(a, b)
150#define cfe_inpstat(a) __cfe_inpstat(a) 150#define cfe_inpstat(a) __cfe_inpstat(a)
151#define cfe_ioctl(a,b,c,d,e,f) __cfe_ioctl(a,b,c,d,e,f) 151#define cfe_ioctl(a, b, c, d, e, f) __cfe_ioctl(a, b, c, d, e, f)
152#define cfe_open(a) __cfe_open(a) 152#define cfe_open(a) __cfe_open(a)
153#define cfe_read(a,b,c) __cfe_read(a,b,c) 153#define cfe_read(a, b, c) __cfe_read(a, b, c)
154#define cfe_readblk(a,b,c,d) __cfe_readblk(a,b,c,d) 154#define cfe_readblk(a, b, c, d) __cfe_readblk(a, b, c, d)
155#define cfe_setenv(a,b) __cfe_setenv(a,b) 155#define cfe_setenv(a, b) __cfe_setenv(a, b)
156#define cfe_write(a,b,c) __cfe_write(a,b,c) 156#define cfe_write(a, b, c) __cfe_write(a, b, c)
157#define cfe_writeblk(a,b,c,d) __cfe_writeblk(a,b,c,d) 157#define cfe_writeblk(a, b, c, d __cfe_writeblk(a, b, c, d)
158#endif /* CFE_API_IMPL_NAMESPACE */ 158#endif /* CFE_API_IMPL_NAMESPACE */
159 159
160int cfe_close(int handle); 160int cfe_close(int handle);
diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h
index 6a5fa32f615b..7e843b5fee92 100644
--- a/include/asm-mips/hazards.h
+++ b/include/asm-mips/hazards.h
@@ -193,7 +193,7 @@ ASMMACRO(enable_fpu_hazard,
193 .set mips64; 193 .set mips64;
194 .set noreorder; 194 .set noreorder;
195 _ssnop; 195 _ssnop;
196 bnezl $0,.+4; 196 bnezl $0, .+4;
197 _ssnop; 197 _ssnop;
198 .set pop 198 .set pop
199) 199)
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
index 7ba92890ea13..2cd8323c8586 100644
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -40,11 +40,11 @@
40 * hardware. An example use would be for flash memory that's used for 40 * hardware. An example use would be for flash memory that's used for
41 * execute in place. 41 * execute in place.
42 */ 42 */
43# define __raw_ioswabb(a,x) (x) 43# define __raw_ioswabb(a, x) (x)
44# define __raw_ioswabw(a,x) (x) 44# define __raw_ioswabw(a, x) (x)
45# define __raw_ioswabl(a,x) (x) 45# define __raw_ioswabl(a, x) (x)
46# define __raw_ioswabq(a,x) (x) 46# define __raw_ioswabq(a, x) (x)
47# define ____raw_ioswabq(a,x) (x) 47# define ____raw_ioswabq(a, x) (x)
48 48
49/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */ 49/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
50 50
@@ -561,9 +561,9 @@ extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
561extern void (*_dma_cache_wback)(unsigned long start, unsigned long size); 561extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
562extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); 562extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
563 563
564#define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start,size) 564#define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start, size)
565#define dma_cache_wback(start, size) _dma_cache_wback(start,size) 565#define dma_cache_wback(start, size) _dma_cache_wback(start, size)
566#define dma_cache_inv(start, size) _dma_cache_inv(start,size) 566#define dma_cache_inv(start, size) _dma_cache_inv(start, size)
567 567
568#else /* Sane hardware */ 568#else /* Sane hardware */
569 569
@@ -587,7 +587,7 @@ extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
587#define __CSR_32_ADJUST 0 587#define __CSR_32_ADJUST 0
588#endif 588#endif
589 589
590#define csr_out32(v,a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v)) 590#define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
591#define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST)) 591#define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
592 592
593/* 593/*
diff --git a/include/asm-mips/ioctl.h b/include/asm-mips/ioctl.h
index 2036fcb9f117..85067e248a83 100644
--- a/include/asm-mips/ioctl.h
+++ b/include/asm-mips/ioctl.h
@@ -54,7 +54,7 @@
54#define _IOC_IN 0x80000000 54#define _IOC_IN 0x80000000
55#define _IOC_INOUT (IOC_IN|IOC_OUT) 55#define _IOC_INOUT (IOC_IN|IOC_OUT)
56 56
57#define _IOC(dir,type,nr,size) \ 57#define _IOC(dir, type, nr, size) \
58 (((dir) << _IOC_DIRSHIFT) | \ 58 (((dir) << _IOC_DIRSHIFT) | \
59 ((type) << _IOC_TYPESHIFT) | \ 59 ((type) << _IOC_TYPESHIFT) | \
60 ((nr) << _IOC_NRSHIFT) | \ 60 ((nr) << _IOC_NRSHIFT) | \
@@ -68,13 +68,13 @@ extern unsigned int __invalid_size_argument_for_IOC;
68 sizeof(t) : __invalid_size_argument_for_IOC) 68 sizeof(t) : __invalid_size_argument_for_IOC)
69 69
70/* used to create numbers */ 70/* used to create numbers */
71#define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0) 71#define _IO(type, nr) _IOC(_IOC_NONE, (type), (nr), 0)
72#define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),(_IOC_TYPECHECK(size))) 72#define _IOR(type, nr, size) _IOC(_IOC_READ, (type), (nr), (_IOC_TYPECHECK(size)))
73#define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size))) 73#define _IOW(type, nr, size) _IOC(_IOC_WRITE, (type), (nr), (_IOC_TYPECHECK(size)))
74#define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size))) 74#define _IOWR(type, nr, size) _IOC(_IOC_READ|_IOC_WRITE, (type), (nr), (_IOC_TYPECHECK(size)))
75#define _IOR_BAD(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size)) 75#define _IOR_BAD(type, nr, size) _IOC(_IOC_READ, (type), (nr), sizeof(size))
76#define _IOW_BAD(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size)) 76#define _IOW_BAD(type, nr, size) _IOC(_IOC_WRITE, (type), (nr), sizeof(size))
77#define _IOWR_BAD(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size)) 77#define _IOWR_BAD(type, nr, size) _IOC(_IOC_READ|_IOC_WRITE, (type), (nr), sizeof(size))
78 78
79 79
80/* used to decode them.. */ 80/* used to decode them.. */
diff --git a/include/asm-mips/ioctls.h b/include/asm-mips/ioctls.h
index 5097cbf183a9..3f04a995ec54 100644
--- a/include/asm-mips/ioctls.h
+++ b/include/asm-mips/ioctls.h
@@ -77,12 +77,12 @@
77#define TIOCSBRK 0x5427 /* BSD compatibility */ 77#define TIOCSBRK 0x5427 /* BSD compatibility */
78#define TIOCCBRK 0x5428 /* BSD compatibility */ 78#define TIOCCBRK 0x5428 /* BSD compatibility */
79#define TIOCGSID 0x7416 /* Return the session ID of FD */ 79#define TIOCGSID 0x7416 /* Return the session ID of FD */
80#define TCGETS2 _IOR('T',0x2A, struct termios2) 80#define TCGETS2 _IOR('T', 0x2A, struct termios2)
81#define TCSETS2 _IOW('T',0x2B, struct termios2) 81#define TCSETS2 _IOW('T', 0x2B, struct termios2)
82#define TCSETSW2 _IOW('T',0x2C, struct termios2) 82#define TCSETSW2 _IOW('T', 0x2C, struct termios2)
83#define TCSETSF2 _IOW('T',0x2D, struct termios2) 83#define TCSETSF2 _IOW('T', 0x2D, struct termios2)
84#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ 84#define TIOCGPTN _IOR('T', 0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
85#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ 85#define TIOCSPTLCK _IOW('T', 0x31, int) /* Lock/unlock Pty */
86 86
87/* I hope the range from 0x5480 on is free ... */ 87/* I hope the range from 0x5480 on is free ... */
88#define TIOCSCTTY 0x5480 /* become controlling tty */ 88#define TIOCSCTTY 0x5480 /* become controlling tty */
diff --git a/include/asm-mips/jmr3927/tx3927.h b/include/asm-mips/jmr3927/tx3927.h
index 4be2f25f70dd..211bcf47fffb 100644
--- a/include/asm-mips/jmr3927/tx3927.h
+++ b/include/asm-mips/jmr3927/tx3927.h
@@ -53,23 +53,23 @@ struct tx3927_dma_reg {
53#include <asm/byteorder.h> 53#include <asm/byteorder.h>
54 54
55#ifdef __BIG_ENDIAN 55#ifdef __BIG_ENDIAN
56#define endian_def_s2(e1,e2) \ 56#define endian_def_s2(e1, e2) \
57 volatile unsigned short e1,e2 57 volatile unsigned short e1, e2
58#define endian_def_sb2(e1,e2,e3) \ 58#define endian_def_sb2(e1, e2, e3) \
59 volatile unsigned short e1;volatile unsigned char e2,e3 59 volatile unsigned short e1;volatile unsigned char e2, e3
60#define endian_def_b2s(e1,e2,e3) \ 60#define endian_def_b2s(e1, e2, e3) \
61 volatile unsigned char e1,e2;volatile unsigned short e3 61 volatile unsigned char e1, e2;volatile unsigned short e3
62#define endian_def_b4(e1,e2,e3,e4) \ 62#define endian_def_b4(e1, e2, e3, e4) \
63 volatile unsigned char e1,e2,e3,e4 63 volatile unsigned char e1, e2, e3, e4
64#else 64#else
65#define endian_def_s2(e1,e2) \ 65#define endian_def_s2(e1, e2) \
66 volatile unsigned short e2,e1 66 volatile unsigned short e2, e1
67#define endian_def_sb2(e1,e2,e3) \ 67#define endian_def_sb2(e1, e2, e3) \
68 volatile unsigned char e3,e2;volatile unsigned short e1 68 volatile unsigned char e3, e2;volatile unsigned short e1
69#define endian_def_b2s(e1,e2,e3) \ 69#define endian_def_b2s(e1, e2, e3) \
70 volatile unsigned short e3;volatile unsigned char e2,e1 70 volatile unsigned short e3;volatile unsigned char e2, e1
71#define endian_def_b4(e1,e2,e3,e4) \ 71#define endian_def_b4(e1, e2, e3, e4) \
72 volatile unsigned char e4,e3,e2,e1 72 volatile unsigned char e4, e3, e2, e1
73#endif 73#endif
74 74
75struct tx3927_pcic_reg { 75struct tx3927_pcic_reg {
diff --git a/include/asm-mips/local.h b/include/asm-mips/local.h
index f9a5ce5c9af1..f96fd59e0845 100644
--- a/include/asm-mips/local.h
+++ b/include/asm-mips/local.h
@@ -15,10 +15,10 @@ typedef struct
15#define LOCAL_INIT(i) { ATOMIC_LONG_INIT(i) } 15#define LOCAL_INIT(i) { ATOMIC_LONG_INIT(i) }
16 16
17#define local_read(l) atomic_long_read(&(l)->a) 17#define local_read(l) atomic_long_read(&(l)->a)
18#define local_set(l,i) atomic_long_set(&(l)->a, (i)) 18#define local_set(l, i) atomic_long_set(&(l)->a, (i))
19 19
20#define local_add(i,l) atomic_long_add((i),(&(l)->a)) 20#define local_add(i, l) atomic_long_add((i), (&(l)->a))
21#define local_sub(i,l) atomic_long_sub((i),(&(l)->a)) 21#define local_sub(i, l) atomic_long_sub((i), (&(l)->a))
22#define local_inc(l) atomic_long_inc(&(l)->a) 22#define local_inc(l) atomic_long_inc(&(l)->a)
23#define local_dec(l) atomic_long_dec(&(l)->a) 23#define local_dec(l) atomic_long_dec(&(l)->a)
24 24
@@ -117,7 +117,7 @@ static __inline__ long local_sub_return(long i, local_t * l)
117 117
118#define local_cmpxchg(l, o, n) \ 118#define local_cmpxchg(l, o, n) \
119 ((long)cmpxchg_local(&((l)->a.counter), (o), (n))) 119 ((long)cmpxchg_local(&((l)->a.counter), (o), (n)))
120#define local_xchg(l, n) (xchg_local(&((l)->a.counter),(n))) 120#define local_xchg(l, n) (xchg_local(&((l)->a.counter), (n)))
121 121
122/** 122/**
123 * local_add_unless - add unless the number is a given value 123 * local_add_unless - add unless the number is a given value
@@ -138,8 +138,8 @@ static __inline__ long local_sub_return(long i, local_t * l)
138}) 138})
139#define local_inc_not_zero(l) local_add_unless((l), 1, 0) 139#define local_inc_not_zero(l) local_add_unless((l), 1, 0)
140 140
141#define local_dec_return(l) local_sub_return(1,(l)) 141#define local_dec_return(l) local_sub_return(1, (l))
142#define local_inc_return(l) local_add_return(1,(l)) 142#define local_inc_return(l) local_add_return(1, (l))
143 143
144/* 144/*
145 * local_sub_and_test - subtract value from variable and test result 145 * local_sub_and_test - subtract value from variable and test result
@@ -150,7 +150,7 @@ static __inline__ long local_sub_return(long i, local_t * l)
150 * true if the result is zero, or false for all 150 * true if the result is zero, or false for all
151 * other cases. 151 * other cases.
152 */ 152 */
153#define local_sub_and_test(i,l) (local_sub_return((i), (l)) == 0) 153#define local_sub_and_test(i, l) (local_sub_return((i), (l)) == 0)
154 154
155/* 155/*
156 * local_inc_and_test - increment and test 156 * local_inc_and_test - increment and test
@@ -181,7 +181,7 @@ static __inline__ long local_sub_return(long i, local_t * l)
181 * if the result is negative, or false when 181 * if the result is negative, or false when
182 * result is greater than or equal to zero. 182 * result is greater than or equal to zero.
183 */ 183 */
184#define local_add_negative(i,l) (local_add_return(i, (l)) < 0) 184#define local_add_negative(i, l) (local_add_return(i, (l)) < 0)
185 185
186/* Use these for per-cpu local_t variables: on some archs they are 186/* Use these for per-cpu local_t variables: on some archs they are
187 * much more efficient than these naive implementations. Note they take 187 * much more efficient than these naive implementations. Note they take
@@ -190,8 +190,8 @@ static __inline__ long local_sub_return(long i, local_t * l)
190 190
191#define __local_inc(l) ((l)->a.counter++) 191#define __local_inc(l) ((l)->a.counter++)
192#define __local_dec(l) ((l)->a.counter++) 192#define __local_dec(l) ((l)->a.counter++)
193#define __local_add(i,l) ((l)->a.counter+=(i)) 193#define __local_add(i, l) ((l)->a.counter+=(i))
194#define __local_sub(i,l) ((l)->a.counter-=(i)) 194#define __local_sub(i, l) ((l)->a.counter-=(i))
195 195
196/* Need to disable preemption for the cpu local counters otherwise we could 196/* Need to disable preemption for the cpu local counters otherwise we could
197 still access a variable of a previous CPU in a non atomic way. */ 197 still access a variable of a previous CPU in a non atomic way. */
diff --git a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
index eeb0c3115b6a..93d507cea518 100644
--- a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
+++ b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
@@ -199,7 +199,7 @@ typedef volatile struct au1xxx_ddma_desc {
199#define DSCR_CMD0_ALWAYS 31 199#define DSCR_CMD0_ALWAYS 31
200#define DSCR_NDEV_IDS 32 200#define DSCR_NDEV_IDS 32
201/* THis macro is used to find/create custom device types */ 201/* THis macro is used to find/create custom device types */
202#define DSCR_DEV2CUSTOM_ID(x,d) (((((x)&0xFFFF)<<8)|0x32000000)|((d)&0xFF)) 202#define DSCR_DEV2CUSTOM_ID(x, d) (((((x)&0xFFFF)<<8)|0x32000000)|((d)&0xFF))
203#define DSCR_CUSTOM2DEV_ID(x) ((x)&0xFF) 203#define DSCR_CUSTOM2DEV_ID(x) ((x)&0xFF)
204 204
205 205
@@ -373,14 +373,14 @@ void * au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp);
373 Some compatibilty macros -- 373 Some compatibilty macros --
374 Needed to make changes to API without breaking existing drivers 374 Needed to make changes to API without breaking existing drivers
375*/ 375*/
376#define au1xxx_dbdma_put_source(chanid,buf,nbytes)_au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE) 376#define au1xxx_dbdma_put_source(chanid, buf, nbytes)_au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE)
377#define au1xxx_dbdma_put_source_flags(chanid,buf,nbytes,flags) _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags) 377#define au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags)
378#define put_source_flags(chanid,buf,nbytes,flags) au1xxx_dbdma_put_source_flags(chanid,buf,nbytes,flags) 378#define put_source_flags(chanid, buf, nbytes, flags) au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags)
379 379
380 380
381#define au1xxx_dbdma_put_dest(chanid,buf,nbytes) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE) 381#define au1xxx_dbdma_put_dest(chanid, buf, nbytes) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE)
382#define au1xxx_dbdma_put_dest_flags(chanid,buf,nbytes,flags) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags) 382#define au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags)
383#define put_dest_flags(chanid,buf,nbytes,flags) au1xxx_dbdma_put_dest_flags(chanid,buf,nbytes,flags) 383#define put_dest_flags(chanid, buf, nbytes, flags) au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags)
384 384
385/* 385/*
386 * Flags for the put_source/put_dest functions. 386 * Flags for the put_source/put_dest functions.
diff --git a/include/asm-mips/mach-generic/mangle-port.h b/include/asm-mips/mach-generic/mangle-port.h
index 6e1b0c075de7..f49dc990214b 100644
--- a/include/asm-mips/mach-generic/mangle-port.h
+++ b/include/asm-mips/mach-generic/mangle-port.h
@@ -27,25 +27,25 @@
27 */ 27 */
28#if defined(CONFIG_SWAP_IO_SPACE) 28#if defined(CONFIG_SWAP_IO_SPACE)
29 29
30# define ioswabb(a,x) (x) 30# define ioswabb(a, x) (x)
31# define __mem_ioswabb(a,x) (x) 31# define __mem_ioswabb(a, x) (x)
32# define ioswabw(a,x) le16_to_cpu(x) 32# define ioswabw(a, x) le16_to_cpu(x)
33# define __mem_ioswabw(a,x) (x) 33# define __mem_ioswabw(a, x) (x)
34# define ioswabl(a,x) le32_to_cpu(x) 34# define ioswabl(a, x) le32_to_cpu(x)
35# define __mem_ioswabl(a,x) (x) 35# define __mem_ioswabl(a, x) (x)
36# define ioswabq(a,x) le64_to_cpu(x) 36# define ioswabq(a, x) le64_to_cpu(x)
37# define __mem_ioswabq(a,x) (x) 37# define __mem_ioswabq(a, x) (x)
38 38
39#else 39#else
40 40
41# define ioswabb(a,x) (x) 41# define ioswabb(a, x) (x)
42# define __mem_ioswabb(a,x) (x) 42# define __mem_ioswabb(a, x) (x)
43# define ioswabw(a,x) (x) 43# define ioswabw(a, x) (x)
44# define __mem_ioswabw(a,x) cpu_to_le16(x) 44# define __mem_ioswabw(a, x) cpu_to_le16(x)
45# define ioswabl(a,x) (x) 45# define ioswabl(a, x) (x)
46# define __mem_ioswabl(a,x) cpu_to_le32(x) 46# define __mem_ioswabl(a, x) cpu_to_le32(x)
47# define ioswabq(a,x) (x) 47# define ioswabq(a, x) (x)
48# define __mem_ioswabq(a,x) cpu_to_le32(x) 48# define __mem_ioswabq(a, x) cpu_to_le32(x)
49 49
50#endif 50#endif
51 51
diff --git a/include/asm-mips/mach-ip27/mangle-port.h b/include/asm-mips/mach-ip27/mangle-port.h
index d615312a451a..f6e4912ea062 100644
--- a/include/asm-mips/mach-ip27/mangle-port.h
+++ b/include/asm-mips/mach-ip27/mangle-port.h
@@ -13,13 +13,13 @@
13#define __swizzle_addr_l(port) (port) 13#define __swizzle_addr_l(port) (port)
14#define __swizzle_addr_q(port) (port) 14#define __swizzle_addr_q(port) (port)
15 15
16# define ioswabb(a,x) (x) 16# define ioswabb(a, x) (x)
17# define __mem_ioswabb(a,x) (x) 17# define __mem_ioswabb(a, x) (x)
18# define ioswabw(a,x) (x) 18# define ioswabw(a, x) (x)
19# define __mem_ioswabw(a,x) cpu_to_le16(x) 19# define __mem_ioswabw(a, x) cpu_to_le16(x)
20# define ioswabl(a,x) (x) 20# define ioswabl(a, x) (x)
21# define __mem_ioswabl(a,x) cpu_to_le32(x) 21# define __mem_ioswabl(a, x) cpu_to_le32(x)
22# define ioswabq(a,x) (x) 22# define ioswabq(a, x) (x)
23# define __mem_ioswabq(a,x) cpu_to_le32(x) 23# define __mem_ioswabq(a, x) cpu_to_le32(x)
24 24
25#endif /* __ASM_MACH_IP27_MANGLE_PORT_H */ 25#endif /* __ASM_MACH_IP27_MANGLE_PORT_H */
diff --git a/include/asm-mips/mach-ip32/mangle-port.h b/include/asm-mips/mach-ip32/mangle-port.h
index 81320eb55324..f1d0f1756a9f 100644
--- a/include/asm-mips/mach-ip32/mangle-port.h
+++ b/include/asm-mips/mach-ip32/mangle-port.h
@@ -14,13 +14,13 @@
14#define __swizzle_addr_l(port) (port) 14#define __swizzle_addr_l(port) (port)
15#define __swizzle_addr_q(port) (port) 15#define __swizzle_addr_q(port) (port)
16 16
17# define ioswabb(a,x) (x) 17# define ioswabb(a, x) (x)
18# define __mem_ioswabb(a,x) (x) 18# define __mem_ioswabb(a, x) (x)
19# define ioswabw(a,x) (x) 19# define ioswabw(a, x) (x)
20# define __mem_ioswabw(a,x) cpu_to_le16(x) 20# define __mem_ioswabw(a, x) cpu_to_le16(x)
21# define ioswabl(a,x) (x) 21# define ioswabl(a, x) (x)
22# define __mem_ioswabl(a,x) cpu_to_le32(x) 22# define __mem_ioswabl(a, x) cpu_to_le32(x)
23# define ioswabq(a,x) (x) 23# define ioswabq(a, x) (x)
24# define __mem_ioswabq(a,x) cpu_to_le32(x) 24# define __mem_ioswabq(a, x) cpu_to_le32(x)
25 25
26#endif /* __ASM_MACH_IP32_MANGLE_PORT_H */ 26#endif /* __ASM_MACH_IP32_MANGLE_PORT_H */
diff --git a/include/asm-mips/mach-jmr3927/mangle-port.h b/include/asm-mips/mach-jmr3927/mangle-port.h
index 501a202631b5..11bffcd1043b 100644
--- a/include/asm-mips/mach-jmr3927/mangle-port.h
+++ b/include/asm-mips/mach-jmr3927/mangle-port.h
@@ -6,13 +6,13 @@ extern unsigned long __swizzle_addr_b(unsigned long port);
6#define __swizzle_addr_l(port) (port) 6#define __swizzle_addr_l(port) (port)
7#define __swizzle_addr_q(port) (port) 7#define __swizzle_addr_q(port) (port)
8 8
9#define ioswabb(a,x) (x) 9#define ioswabb(a, x) (x)
10#define __mem_ioswabb(a,x) (x) 10#define __mem_ioswabb(a, x) (x)
11#define ioswabw(a,x) le16_to_cpu(x) 11#define ioswabw(a, x) le16_to_cpu(x)
12#define __mem_ioswabw(a,x) (x) 12#define __mem_ioswabw(a, x) (x)
13#define ioswabl(a,x) le32_to_cpu(x) 13#define ioswabl(a, x) le32_to_cpu(x)
14#define __mem_ioswabl(a,x) (x) 14#define __mem_ioswabl(a, x) (x)
15#define ioswabq(a,x) le64_to_cpu(x) 15#define ioswabq(a, x) le64_to_cpu(x)
16#define __mem_ioswabq(a,x) (x) 16#define __mem_ioswabq(a, x) (x)
17 17
18#endif /* __ASM_MACH_JMR3927_MANGLE_PORT_H */ 18#endif /* __ASM_MACH_JMR3927_MANGLE_PORT_H */
diff --git a/include/asm-mips/mach-pnx8550/kernel-entry-init.h b/include/asm-mips/mach-pnx8550/kernel-entry-init.h
index 982079f410b5..bdde00c9199b 100644
--- a/include/asm-mips/mach-pnx8550/kernel-entry-init.h
+++ b/include/asm-mips/mach-pnx8550/kernel-entry-init.h
@@ -44,7 +44,7 @@ cache_begin: li t0, (1<<28)
44 mfc0 t0, CP0_CONFIG, 7 44 mfc0 t0, CP0_CONFIG, 7
45 HAZARD_CP0 45 HAZARD_CP0
46 46
47 and t0,~((1<<19) | (1<<20)) /* TLB/MAP cleared */ 47 and t0, ~((1<<19) | (1<<20)) /* TLB/MAP cleared */
48 mtc0 t0, CP0_CONFIG, 7 48 mtc0 t0, CP0_CONFIG, 7
49 HAZARD_CP0 49 HAZARD_CP0
50 50
diff --git a/include/asm-mips/mach-pnx8550/uart.h b/include/asm-mips/mach-pnx8550/uart.h
index 814a7a15ab49..ad7608d44874 100644
--- a/include/asm-mips/mach-pnx8550/uart.h
+++ b/include/asm-mips/mach-pnx8550/uart.h
@@ -15,7 +15,7 @@
15 15
16/* early macros needed for prom/kgdb */ 16/* early macros needed for prom/kgdb */
17 17
18#define ip3106_lcr(base,port) *(volatile u32 *)(base+(port*0x1000) + 0x000) 18#define ip3106_lcr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x000)
19#define ip3106_mcr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x004) 19#define ip3106_mcr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x004)
20#define ip3106_baud(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x008) 20#define ip3106_baud(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x008)
21#define ip3106_cfg(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x00C) 21#define ip3106_cfg(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x00C)
diff --git a/include/asm-mips/mc146818-time.h b/include/asm-mips/mc146818-time.h
index 41ac8d363c67..cdc379a0a94e 100644
--- a/include/asm-mips/mc146818-time.h
+++ b/include/asm-mips/mc146818-time.h
@@ -63,8 +63,8 @@ static inline int mc146818_set_rtc_mmss(unsigned long nowtime)
63 BIN_TO_BCD(real_seconds); 63 BIN_TO_BCD(real_seconds);
64 BIN_TO_BCD(real_minutes); 64 BIN_TO_BCD(real_minutes);
65 } 65 }
66 CMOS_WRITE(real_seconds,RTC_SECONDS); 66 CMOS_WRITE(real_seconds, RTC_SECONDS);
67 CMOS_WRITE(real_minutes,RTC_MINUTES); 67 CMOS_WRITE(real_minutes, RTC_MINUTES);
68 } else { 68 } else {
69 printk(KERN_WARNING 69 printk(KERN_WARNING
70 "set_rtc_mmss: can't update from %d to %d\n", 70 "set_rtc_mmss: can't update from %d to %d\n",
diff --git a/include/asm-mips/mips-boards/bonito64.h b/include/asm-mips/mips-boards/bonito64.h
index dc3fc32eedd8..a0f04bb99c99 100644
--- a/include/asm-mips/mips-boards/bonito64.h
+++ b/include/asm-mips/mips-boards/bonito64.h
@@ -387,7 +387,7 @@ extern unsigned long _pcictrl_bonito_pcicfg;
387#define BONITO_PCIMAP_PCIMAP_LO2 0x0003f000 387#define BONITO_PCIMAP_PCIMAP_LO2 0x0003f000
388#define BONITO_PCIMAP_PCIMAP_LO2_SHIFT 12 388#define BONITO_PCIMAP_PCIMAP_LO2_SHIFT 12
389#define BONITO_PCIMAP_PCIMAP_2 0x00040000 389#define BONITO_PCIMAP_PCIMAP_2 0x00040000
390#define BONITO_PCIMAP_WIN(WIN,ADDR) ((((ADDR)>>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6)) 390#define BONITO_PCIMAP_WIN(WIN, ADDR) ((((ADDR)>>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
391 391
392#define BONITO_PCIMAP_WINSIZE (1<<26) 392#define BONITO_PCIMAP_WINSIZE (1<<26)
393#define BONITO_PCIMAP_WINOFFSET(ADDR) ((ADDR) & (BONITO_PCIMAP_WINSIZE - 1)) 393#define BONITO_PCIMAP_WINOFFSET(ADDR) ((ADDR) & (BONITO_PCIMAP_WINSIZE - 1))
@@ -412,19 +412,19 @@ extern unsigned long _pcictrl_bonito_pcicfg;
412 412
413#define BONITO_PCIMEMBASECFG_ASHIFT 23 413#define BONITO_PCIMEMBASECFG_ASHIFT 23
414#define BONITO_PCIMEMBASECFG_AMASK 0x007fffff 414#define BONITO_PCIMEMBASECFG_AMASK 0x007fffff
415#define BONITO_PCIMEMBASECFGSIZE(WIN,SIZE) (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) 415#define BONITO_PCIMEMBASECFGSIZE(WIN, SIZE) (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)
416#define BONITO_PCIMEMBASECFGBASE(WIN,BASE) (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) 416#define BONITO_PCIMEMBASECFGBASE(WIN, BASE) (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS)
417 417
418#define BONITO_PCIMEMBASECFG_SIZE(WIN,CFG) (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK) 418#define BONITO_PCIMEMBASECFG_SIZE(WIN, CFG) (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK)
419 419
420 420
421#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) 421#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
422#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) 422#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
423#define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) 423#define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
424 424
425#define BONITO_PCITOPHYS(WIN,ADDR,CFG) ( \ 425#define BONITO_PCITOPHYS(WIN, ADDR, CFG) ( \
426 (((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG)))) | \ 426 (((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG)))) | \
427 (BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG)) \ 427 (BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG)) \
428 ) 428 )
429 429
430/* PCICmd */ 430/* PCICmd */
diff --git a/include/asm-mips/mips-boards/malta.h b/include/asm-mips/mips-boards/malta.h
index eec91001bb65..93bf4e51b8a4 100644
--- a/include/asm-mips/mips-boards/malta.h
+++ b/include/asm-mips/mips-boards/malta.h
@@ -72,7 +72,7 @@ static inline unsigned long get_msc_port_base(unsigned long reg)
72 72
73#define SMSC_CONFIG_ACTIVATE_ENABLE 1 73#define SMSC_CONFIG_ACTIVATE_ENABLE 1
74 74
75#define SMSC_WRITE(x,a) outb(x,a) 75#define SMSC_WRITE(x, a) outb(x, a)
76 76
77#define MALTA_JMPRS_REG 0x1f000210 77#define MALTA_JMPRS_REG 0x1f000210
78 78
diff --git a/include/asm-mips/mipsmtregs.h b/include/asm-mips/mipsmtregs.h
index 294bca12cd3f..5a2f8a3a6a1f 100644
--- a/include/asm-mips/mipsmtregs.h
+++ b/include/asm-mips/mipsmtregs.h
@@ -41,27 +41,27 @@
41 * Macros for use in assembly language code 41 * Macros for use in assembly language code
42 */ 42 */
43 43
44#define CP0_MVPCONTROL $0,1 44#define CP0_MVPCONTROL $0, 1
45#define CP0_MVPCONF0 $0,2 45#define CP0_MVPCONF0 $0, 2
46#define CP0_MVPCONF1 $0,3 46#define CP0_MVPCONF1 $0, 3
47#define CP0_VPECONTROL $1,1 47#define CP0_VPECONTROL $1, 1
48#define CP0_VPECONF0 $1,2 48#define CP0_VPECONF0 $1, 2
49#define CP0_VPECONF1 $1,3 49#define CP0_VPECONF1 $1, 3
50#define CP0_YQMASK $1,4 50#define CP0_YQMASK $1, 4
51#define CP0_VPESCHEDULE $1,5 51#define CP0_VPESCHEDULE $1, 5
52#define CP0_VPESCHEFBK $1,6 52#define CP0_VPESCHEFBK $1, 6
53#define CP0_TCSTATUS $2,1 53#define CP0_TCSTATUS $2, 1
54#define CP0_TCBIND $2,2 54#define CP0_TCBIND $2, 2
55#define CP0_TCRESTART $2,3 55#define CP0_TCRESTART $2, 3
56#define CP0_TCHALT $2,4 56#define CP0_TCHALT $2, 4
57#define CP0_TCCONTEXT $2,5 57#define CP0_TCCONTEXT $2, 5
58#define CP0_TCSCHEDULE $2,6 58#define CP0_TCSCHEDULE $2, 6
59#define CP0_TCSCHEFBK $2,7 59#define CP0_TCSCHEFBK $2, 7
60#define CP0_SRSCONF0 $6,1 60#define CP0_SRSCONF0 $6, 1
61#define CP0_SRSCONF1 $6,2 61#define CP0_SRSCONF1 $6, 2
62#define CP0_SRSCONF2 $6,3 62#define CP0_SRSCONF2 $6, 3
63#define CP0_SRSCONF3 $6,4 63#define CP0_SRSCONF3 $6, 4
64#define CP0_SRSCONF4 $6,5 64#define CP0_SRSCONF4 $6, 5
65 65
66#endif 66#endif
67 67
@@ -291,7 +291,7 @@ static inline void ehb(void)
291 __res; \ 291 __res; \
292}) 292})
293 293
294#define mftr(rt,u,sel) \ 294#define mftr(rt, u, sel) \
295({ \ 295({ \
296 unsigned long __res; \ 296 unsigned long __res; \
297 \ 297 \
@@ -315,7 +315,7 @@ do { \
315 : : "r" (v)); \ 315 : : "r" (v)); \
316} while (0) 316} while (0)
317 317
318#define mttc0(rd,sel,v) \ 318#define mttc0(rd, sel, v) \
319({ \ 319({ \
320 __asm__ __volatile__( \ 320 __asm__ __volatile__( \
321 " .set push \n" \ 321 " .set push \n" \
@@ -330,7 +330,7 @@ do { \
330}) 330})
331 331
332 332
333#define mttr(rd,u,sel,v) \ 333#define mttr(rd, u, sel, v) \
334({ \ 334({ \
335 __asm__ __volatile__( \ 335 __asm__ __volatile__( \
336 "mttr %0," #rd ", " #u ", " #sel \ 336 "mttr %0," #rd ", " #u ", " #sel \
@@ -362,7 +362,7 @@ do { \
362#define write_vpe_c0_config1(val) mttc0(16, 1, val) 362#define write_vpe_c0_config1(val) mttc0(16, 1, val)
363#define read_vpe_c0_config7() mftc0(16, 7) 363#define read_vpe_c0_config7() mftc0(16, 7)
364#define write_vpe_c0_config7(val) mttc0(16, 7, val) 364#define write_vpe_c0_config7(val) mttc0(16, 7, val)
365#define read_vpe_c0_ebase() mftc0(15,1) 365#define read_vpe_c0_ebase() mftc0(15, 1)
366#define write_vpe_c0_ebase(val) mttc0(15, 1, val) 366#define write_vpe_c0_ebase(val) mttc0(15, 1, val)
367#define write_vpe_c0_compare(val) mttc0(11, 0, val) 367#define write_vpe_c0_compare(val) mttc0(11, 0, val)
368#define read_vpe_c0_badvaddr() mftc0(8, 0) 368#define read_vpe_c0_badvaddr() mftc0(8, 0)
@@ -372,15 +372,15 @@ do { \
372 372
373/* TC */ 373/* TC */
374#define read_tc_c0_tcstatus() mftc0(2, 1) 374#define read_tc_c0_tcstatus() mftc0(2, 1)
375#define write_tc_c0_tcstatus(val) mttc0(2,1,val) 375#define write_tc_c0_tcstatus(val) mttc0(2, 1, val)
376#define read_tc_c0_tcbind() mftc0(2, 2) 376#define read_tc_c0_tcbind() mftc0(2, 2)
377#define write_tc_c0_tcbind(val) mttc0(2,2,val) 377#define write_tc_c0_tcbind(val) mttc0(2, 2, val)
378#define read_tc_c0_tcrestart() mftc0(2, 3) 378#define read_tc_c0_tcrestart() mftc0(2, 3)
379#define write_tc_c0_tcrestart(val) mttc0(2,3,val) 379#define write_tc_c0_tcrestart(val) mttc0(2, 3, val)
380#define read_tc_c0_tchalt() mftc0(2, 4) 380#define read_tc_c0_tchalt() mftc0(2, 4)
381#define write_tc_c0_tchalt(val) mttc0(2,4,val) 381#define write_tc_c0_tchalt(val) mttc0(2, 4, val)
382#define read_tc_c0_tccontext() mftc0(2, 5) 382#define read_tc_c0_tccontext() mftc0(2, 5)
383#define write_tc_c0_tccontext(val) mttc0(2,5,val) 383#define write_tc_c0_tccontext(val) mttc0(2, 5, val)
384 384
385/* GPR */ 385/* GPR */
386#define read_tc_gpr_sp() mftgpr(29) 386#define read_tc_gpr_sp() mftgpr(29)
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 18f47f1e8cd5..aa17f658f73c 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -981,7 +981,7 @@ do { \
981#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) 981#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
982 982
983/* MIPSR2 */ 983/* MIPSR2 */
984#define read_c0_hwrena() __read_32bit_c0_register($7,0) 984#define read_c0_hwrena() __read_32bit_c0_register($7, 0)
985#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) 985#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
986 986
987#define read_c0_intctl() __read_32bit_c0_register($12, 1) 987#define read_c0_intctl() __read_32bit_c0_register($12, 1)
@@ -993,7 +993,7 @@ do { \
993#define read_c0_srsmap() __read_32bit_c0_register($12, 3) 993#define read_c0_srsmap() __read_32bit_c0_register($12, 3)
994#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) 994#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
995 995
996#define read_c0_ebase() __read_32bit_c0_register($15,1) 996#define read_c0_ebase() __read_32bit_c0_register($15, 1)
997#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) 997#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
998 998
999/* 999/*
diff --git a/include/asm-mips/mmu_context.h b/include/asm-mips/mmu_context.h
index 65024ffd7879..b3b7a689e7d3 100644
--- a/include/asm-mips/mmu_context.h
+++ b/include/asm-mips/mmu_context.h
@@ -107,7 +107,7 @@ get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
107 107
108#else /* CONFIG_MIPS_MT_SMTC */ 108#else /* CONFIG_MIPS_MT_SMTC */
109 109
110#define get_new_mmu_context(mm,cpu) smtc_get_new_mmu_context((mm),(cpu)) 110#define get_new_mmu_context(mm, cpu) smtc_get_new_mmu_context((mm), (cpu))
111 111
112#endif /* CONFIG_MIPS_MT_SMTC */ 112#endif /* CONFIG_MIPS_MT_SMTC */
113 113
@@ -191,7 +191,7 @@ static inline void destroy_context(struct mm_struct *mm)
191{ 191{
192} 192}
193 193
194#define deactivate_mm(tsk,mm) do { } while (0) 194#define deactivate_mm(tsk, mm) do { } while (0)
195 195
196/* 196/*
197 * After we have set current->mm to a new value, this activates 197 * After we have set current->mm to a new value, this activates
diff --git a/include/asm-mips/paccess.h b/include/asm-mips/paccess.h
index 8c08fa904b2c..c2394f8b0fe1 100644
--- a/include/asm-mips/paccess.h
+++ b/include/asm-mips/paccess.h
@@ -25,13 +25,13 @@
25extern asmlinkage void handle_ibe(void); 25extern asmlinkage void handle_ibe(void);
26extern asmlinkage void handle_dbe(void); 26extern asmlinkage void handle_dbe(void);
27 27
28#define put_dbe(x,ptr) __put_dbe((x),(ptr),sizeof(*(ptr))) 28#define put_dbe(x, ptr) __put_dbe((x), (ptr), sizeof(*(ptr)))
29#define get_dbe(x,ptr) __get_dbe((x),(ptr),sizeof(*(ptr))) 29#define get_dbe(x, ptr) __get_dbe((x), (ptr), sizeof(*(ptr)))
30 30
31struct __large_pstruct { unsigned long buf[100]; }; 31struct __large_pstruct { unsigned long buf[100]; };
32#define __mp(x) (*(struct __large_pstruct *)(x)) 32#define __mp(x) (*(struct __large_pstruct *)(x))
33 33
34#define __get_dbe(x,ptr,size) \ 34#define __get_dbe(x, ptr, size) \
35({ \ 35({ \
36 long __gu_err; \ 36 long __gu_err; \
37 __typeof__(*(ptr)) __gu_val; \ 37 __typeof__(*(ptr)) __gu_val; \
@@ -70,7 +70,7 @@ struct __large_pstruct { unsigned long buf[100]; };
70 70
71extern void __get_dbe_unknown(void); 71extern void __get_dbe_unknown(void);
72 72
73#define __put_dbe(x,ptr,size) \ 73#define __put_dbe(x, ptr, size) \
74({ \ 74({ \
75 long __pu_err; \ 75 long __pu_err; \
76 __typeof__(*(ptr)) __pu_val; \ 76 __typeof__(*(ptr)) __pu_val; \
diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h
index e3301e54d559..d2ea983bec06 100644
--- a/include/asm-mips/page.h
+++ b/include/asm-mips/page.h
@@ -153,7 +153,7 @@ typedef struct { unsigned long pgprot; } pgprot_t;
153 ((unsigned long)(x) - PAGE_OFFSET + PHYS_OFFSET) 153 ((unsigned long)(x) - PAGE_OFFSET + PHYS_OFFSET)
154#endif 154#endif
155#define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET)) 155#define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET))
156#define __pa_symbol(x) __pa(RELOC_HIDE((unsigned long)(x),0)) 156#define __pa_symbol(x) __pa(RELOC_HIDE((unsigned long)(x), 0))
157 157
158#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT) 158#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
159 159
diff --git a/include/asm-mips/pci/bridge.h b/include/asm-mips/pci/bridge.h
index 0c45e7598f3f..b84feebf2cef 100644
--- a/include/asm-mips/pci/bridge.h
+++ b/include/asm-mips/pci/bridge.h
@@ -360,7 +360,7 @@ typedef struct bridge_err_cmdword_s {
360#define BRIDGE_TYPE0_CFG_FUNC_OFF 0x00000100 /* Type 0 Cfg Func Offset (1..7) */ 360#define BRIDGE_TYPE0_CFG_FUNC_OFF 0x00000100 /* Type 0 Cfg Func Offset (1..7) */
361#define BRIDGE_TYPE0_CFG_DEV(s) (BRIDGE_TYPE0_CFG_DEV0+\ 361#define BRIDGE_TYPE0_CFG_DEV(s) (BRIDGE_TYPE0_CFG_DEV0+\
362 (s)*BRIDGE_TYPE0_CFG_SLOT_OFF) 362 (s)*BRIDGE_TYPE0_CFG_SLOT_OFF)
363#define BRIDGE_TYPE0_CFG_DEVF(s,f) (BRIDGE_TYPE0_CFG_DEV0+\ 363#define BRIDGE_TYPE0_CFG_DEVF(s, f) (BRIDGE_TYPE0_CFG_DEV0+\
364 (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\ 364 (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\
365 (f)*BRIDGE_TYPE0_CFG_FUNC_OFF) 365 (f)*BRIDGE_TYPE0_CFG_FUNC_OFF)
366 366
diff --git a/include/asm-mips/pgalloc.h b/include/asm-mips/pgalloc.h
index 9fb57c035213..81b72122207a 100644
--- a/include/asm-mips/pgalloc.h
+++ b/include/asm-mips/pgalloc.h
@@ -95,7 +95,7 @@ static inline void pte_free(struct page *pte)
95 __free_pages(pte, PTE_ORDER); 95 __free_pages(pte, PTE_ORDER);
96} 96}
97 97
98#define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte)) 98#define __pte_free_tlb(tlb, pte) tlb_remove_page((tlb), (pte))
99 99
100#ifdef CONFIG_32BIT 100#ifdef CONFIG_32BIT
101 101
@@ -104,7 +104,7 @@ static inline void pte_free(struct page *pte)
104 * inside the pgd, so has no extra memory associated with it. 104 * inside the pgd, so has no extra memory associated with it.
105 */ 105 */
106#define pmd_free(x) do { } while (0) 106#define pmd_free(x) do { } while (0)
107#define __pmd_free_tlb(tlb,x) do { } while (0) 107#define __pmd_free_tlb(tlb, x) do { } while (0)
108 108
109#endif 109#endif
110 110
@@ -125,7 +125,7 @@ static inline void pmd_free(pmd_t *pmd)
125 free_pages((unsigned long)pmd, PMD_ORDER); 125 free_pages((unsigned long)pmd, PMD_ORDER);
126} 126}
127 127
128#define __pmd_free_tlb(tlb,x) pmd_free(x) 128#define __pmd_free_tlb(tlb, x) pmd_free(x)
129 129
130#endif 130#endif
131 131
diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h
index 59c865deb0c7..a0947092d0e0 100644
--- a/include/asm-mips/pgtable-32.h
+++ b/include/asm-mips/pgtable-32.h
@@ -140,7 +140,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
140#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) 140#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
141 141
142/* to find an entry in a page-table-directory */ 142/* to find an entry in a page-table-directory */
143#define pgd_offset(mm,addr) ((mm)->pgd + pgd_index(addr)) 143#define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr))
144 144
145/* Find an entry in the third-level page table.. */ 145/* Find an entry in the third-level page table.. */
146#define __pte_offset(address) \ 146#define __pte_offset(address) \
diff --git a/include/asm-mips/pgtable-64.h b/include/asm-mips/pgtable-64.h
index a8aed9c6a159..943515f0ef87 100644
--- a/include/asm-mips/pgtable-64.h
+++ b/include/asm-mips/pgtable-64.h
@@ -193,7 +193,7 @@ static inline void pud_clear(pud_t *pudp)
193#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) 193#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
194 194
195/* to find an entry in a page-table-directory */ 195/* to find an entry in a page-table-directory */
196#define pgd_offset(mm,addr) ((mm)->pgd + pgd_index(addr)) 196#define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr))
197 197
198static inline unsigned long pud_page_vaddr(pud_t pud) 198static inline unsigned long pud_page_vaddr(pud_t pud)
199{ 199{
@@ -237,7 +237,7 @@ static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
237 237
238#define __swp_type(x) (((x).val >> 32) & 0xff) 238#define __swp_type(x) (((x).val >> 32) & 0xff)
239#define __swp_offset(x) ((x).val >> 40) 239#define __swp_offset(x) ((x).val >> 40)
240#define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) }) 240#define __swp_entry(type, offset) ((swp_entry_t) { pte_val(mk_swap_pte((type), (offset))) })
241#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 241#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
242#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 242#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
243 243
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h
index d2ee28156743..17a7703a2969 100644
--- a/include/asm-mips/pgtable.h
+++ b/include/asm-mips/pgtable.h
@@ -103,7 +103,7 @@ static inline void set_pte(pte_t *ptep, pte_t pte)
103 } 103 }
104 } 104 }
105} 105}
106#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) 106#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
107 107
108static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 108static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
109{ 109{
@@ -140,7 +140,7 @@ static inline void set_pte(pte_t *ptep, pte_t pteval)
140 } 140 }
141#endif 141#endif
142} 142}
143#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) 143#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
144 144
145static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 145static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
146{ 146{
diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h
index 3c8e3c8d1a9a..2b8466ffd3ca 100644
--- a/include/asm-mips/r4kcache.h
+++ b/include/asm-mips/r4kcache.h
@@ -354,7 +354,7 @@ static inline void blast_##pfx##cache##lsize(void) \
354 \ 354 \
355 for (ws = 0; ws < ws_end; ws += ws_inc) \ 355 for (ws = 0; ws < ws_end; ws += ws_inc) \
356 for (addr = start; addr < end; addr += lsize * 32) \ 356 for (addr = start; addr < end; addr += lsize * 32) \
357 cache##lsize##_unroll32(addr|ws,indexop); \ 357 cache##lsize##_unroll32(addr|ws, indexop); \
358 \ 358 \
359 __##pfx##flush_epilogue \ 359 __##pfx##flush_epilogue \
360} \ 360} \
@@ -367,7 +367,7 @@ static inline void blast_##pfx##cache##lsize##_page(unsigned long page) \
367 __##pfx##flush_prologue \ 367 __##pfx##flush_prologue \
368 \ 368 \
369 do { \ 369 do { \
370 cache##lsize##_unroll32(start,hitop); \ 370 cache##lsize##_unroll32(start, hitop); \
371 start += lsize * 32; \ 371 start += lsize * 32; \
372 } while (start < end); \ 372 } while (start < end); \
373 \ 373 \
@@ -388,7 +388,7 @@ static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page)
388 \ 388 \
389 for (ws = 0; ws < ws_end; ws += ws_inc) \ 389 for (ws = 0; ws < ws_end; ws += ws_inc) \
390 for (addr = start; addr < end; addr += lsize * 32) \ 390 for (addr = start; addr < end; addr += lsize * 32) \
391 cache##lsize##_unroll32(addr|ws,indexop); \ 391 cache##lsize##_unroll32(addr|ws, indexop); \
392 \ 392 \
393 __##pfx##flush_epilogue \ 393 __##pfx##flush_epilogue \
394} 394}
diff --git a/include/asm-mips/semaphore.h b/include/asm-mips/semaphore.h
index ea2413c58e78..080daa77f867 100644
--- a/include/asm-mips/semaphore.h
+++ b/include/asm-mips/semaphore.h
@@ -46,7 +46,7 @@ struct semaphore {
46} 46}
47 47
48#define __DECLARE_SEMAPHORE_GENERIC(name, count) \ 48#define __DECLARE_SEMAPHORE_GENERIC(name, count) \
49 struct semaphore name = __SEMAPHORE_INITIALIZER(name,count) 49 struct semaphore name = __SEMAPHORE_INITIALIZER(name, count)
50 50
51#define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name, 1) 51#define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name, 1)
52#define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name, 0) 52#define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name, 0)
diff --git a/include/asm-mips/sgiarcs.h b/include/asm-mips/sgiarcs.h
index 6d1eda60e01f..721327f88601 100644
--- a/include/asm-mips/sgiarcs.h
+++ b/include/asm-mips/sgiarcs.h
@@ -369,8 +369,8 @@ struct linux_smonblock {
369#if defined(CONFIG_64BIT) && defined(CONFIG_ARC32) 369#if defined(CONFIG_64BIT) && defined(CONFIG_ARC32)
370 370
371#define __arc_clobbers \ 371#define __arc_clobbers \
372 "$2","$3" /* ... */, "$8","$9","$10","$11", \ 372 "$2", "$3" /* ... */, "$8", "$9", "$10", "$11", \
373 "$12","$13","$14","$15","$16","$24","$25","$31" 373 "$12", "$13", "$14", "$15", "$16", "$24", "$25", "$31"
374 374
375#define ARC_CALL0(dest) \ 375#define ARC_CALL0(dest) \
376({ long __res; \ 376({ long __res; \
@@ -382,11 +382,11 @@ struct linux_smonblock {
382 "move\t%0, $2" \ 382 "move\t%0, $2" \
383 : "=r" (__res), "=r" (__vec) \ 383 : "=r" (__res), "=r" (__vec) \
384 : "1" (__vec) \ 384 : "1" (__vec) \
385 : __arc_clobbers, "$4","$5","$6","$7"); \ 385 : __arc_clobbers, "$4", "$5", "$6", "$7"); \
386 (unsigned long) __res; \ 386 (unsigned long) __res; \
387}) 387})
388 388
389#define ARC_CALL1(dest,a1) \ 389#define ARC_CALL1(dest, a1) \
390({ long __res; \ 390({ long __res; \
391 register signed int __a1 __asm__("$4") = (int) (long) (a1); \ 391 register signed int __a1 __asm__("$4") = (int) (long) (a1); \
392 long __vec = (long) romvec->dest; \ 392 long __vec = (long) romvec->dest; \
@@ -397,11 +397,11 @@ struct linux_smonblock {
397 "move\t%0, $2" \ 397 "move\t%0, $2" \
398 : "=r" (__res), "=r" (__vec) \ 398 : "=r" (__res), "=r" (__vec) \
399 : "1" (__vec), "r" (__a1) \ 399 : "1" (__vec), "r" (__a1) \
400 : __arc_clobbers, "$5","$6","$7"); \ 400 : __arc_clobbers, "$5", "$6", "$7"); \
401 (unsigned long) __res; \ 401 (unsigned long) __res; \
402}) 402})
403 403
404#define ARC_CALL2(dest,a1,a2) \ 404#define ARC_CALL2(dest, a1, a2) \
405({ long __res; \ 405({ long __res; \
406 register signed int __a1 __asm__("$4") = (int) (long) (a1); \ 406 register signed int __a1 __asm__("$4") = (int) (long) (a1); \
407 register signed int __a2 __asm__("$5") = (int) (long) (a2); \ 407 register signed int __a2 __asm__("$5") = (int) (long) (a2); \
@@ -413,11 +413,11 @@ struct linux_smonblock {
413 "move\t%0, $2" \ 413 "move\t%0, $2" \
414 : "=r" (__res), "=r" (__vec) \ 414 : "=r" (__res), "=r" (__vec) \
415 : "1" (__vec), "r" (__a1), "r" (__a2) \ 415 : "1" (__vec), "r" (__a1), "r" (__a2) \
416 : __arc_clobbers, "$6","$7"); \ 416 : __arc_clobbers, "$6", "$7"); \
417 __res; \ 417 __res; \
418}) 418})
419 419
420#define ARC_CALL3(dest,a1,a2,a3) \ 420#define ARC_CALL3(dest, a1, a2, a3) \
421({ long __res; \ 421({ long __res; \
422 register signed int __a1 __asm__("$4") = (int) (long) (a1); \ 422 register signed int __a1 __asm__("$4") = (int) (long) (a1); \
423 register signed int __a2 __asm__("$5") = (int) (long) (a2); \ 423 register signed int __a2 __asm__("$5") = (int) (long) (a2); \
@@ -434,7 +434,7 @@ struct linux_smonblock {
434 __res; \ 434 __res; \
435}) 435})
436 436
437#define ARC_CALL4(dest,a1,a2,a3,a4) \ 437#define ARC_CALL4(dest, a1, a2, a3, a4) \
438({ long __res; \ 438({ long __res; \
439 register signed int __a1 __asm__("$4") = (int) (long) (a1); \ 439 register signed int __a1 __asm__("$4") = (int) (long) (a1); \
440 register signed int __a2 __asm__("$5") = (int) (long) (a2); \ 440 register signed int __a2 __asm__("$5") = (int) (long) (a2); \
@@ -453,7 +453,7 @@ struct linux_smonblock {
453 __res; \ 453 __res; \
454}) 454})
455 455
456#define ARC_CALL5(dest,a1,a2,a3,a4,a5) \ 456#define ARC_CALL5(dest, a1, a2, a3, a4, a5) \
457({ long __res; \ 457({ long __res; \
458 register signed int __a1 __asm__("$4") = (int) (long) (a1); \ 458 register signed int __a1 __asm__("$4") = (int) (long) (a1); \
459 register signed int __a2 __asm__("$5") = (int) (long) (a2); \ 459 register signed int __a2 __asm__("$5") = (int) (long) (a2); \
@@ -468,8 +468,8 @@ struct linux_smonblock {
468 "daddu\t$29, 32\n\t" \ 468 "daddu\t$29, 32\n\t" \
469 "move\t%0, $2" \ 469 "move\t%0, $2" \
470 : "=r" (__res), "=r" (__vec) \ 470 : "=r" (__res), "=r" (__vec) \
471 : "1" (__vec), \ 471 : "1" (__vec), \
472 "r" (__a1), "r" (__a2), "r" (__a3), "r" (__a4), \ 472 "r" (__a1), "r" (__a2), "r" (__a3), "r" (__a4), \
473 "r" (__a5) \ 473 "r" (__a5) \
474 : __arc_clobbers); \ 474 : __arc_clobbers); \
475 __res; \ 475 __res; \
@@ -488,7 +488,7 @@ struct linux_smonblock {
488 __res; \ 488 __res; \
489}) 489})
490 490
491#define ARC_CALL1(dest,a1) \ 491#define ARC_CALL1(dest, a1) \
492({ long __res; \ 492({ long __res; \
493 long __a1 = (long) (a1); \ 493 long __a1 = (long) (a1); \
494 long (*__vec)(long) = (void *) romvec->dest; \ 494 long (*__vec)(long) = (void *) romvec->dest; \
@@ -497,7 +497,7 @@ struct linux_smonblock {
497 __res; \ 497 __res; \
498}) 498})
499 499
500#define ARC_CALL2(dest,a1,a2) \ 500#define ARC_CALL2(dest, a1, a2) \
501({ long __res; \ 501({ long __res; \
502 long __a1 = (long) (a1); \ 502 long __a1 = (long) (a1); \
503 long __a2 = (long) (a2); \ 503 long __a2 = (long) (a2); \
@@ -507,7 +507,7 @@ struct linux_smonblock {
507 __res; \ 507 __res; \
508}) 508})
509 509
510#define ARC_CALL3(dest,a1,a2,a3) \ 510#define ARC_CALL3(dest, a1, a2, a3) \
511({ long __res; \ 511({ long __res; \
512 long __a1 = (long) (a1); \ 512 long __a1 = (long) (a1); \
513 long __a2 = (long) (a2); \ 513 long __a2 = (long) (a2); \
@@ -518,7 +518,7 @@ struct linux_smonblock {
518 __res; \ 518 __res; \
519}) 519})
520 520
521#define ARC_CALL4(dest,a1,a2,a3,a4) \ 521#define ARC_CALL4(dest, a1, a2, a3, a4) \
522({ long __res; \ 522({ long __res; \
523 long __a1 = (long) (a1); \ 523 long __a1 = (long) (a1); \
524 long __a2 = (long) (a2); \ 524 long __a2 = (long) (a2); \
@@ -530,7 +530,7 @@ struct linux_smonblock {
530 __res; \ 530 __res; \
531}) 531})
532 532
533#define ARC_CALL5(dest,a1,a2,a3,a4,a5) \ 533#define ARC_CALL5(dest, a1, a2, a3, a4, a5) \
534({ long __res; \ 534({ long __res; \
535 long __a1 = (long) (a1); \ 535 long __a1 = (long) (a1); \
536 long __a2 = (long) (a2); \ 536 long __a2 = (long) (a2); \
diff --git a/include/asm-mips/sibyte/bcm1480_int.h b/include/asm-mips/sibyte/bcm1480_int.h
index c0d5206020fd..6109557c14e9 100644
--- a/include/asm-mips/sibyte/bcm1480_int.h
+++ b/include/asm-mips/sibyte/bcm1480_int.h
@@ -157,7 +157,7 @@
157 * Mask values for each interrupt 157 * Mask values for each interrupt
158 */ 158 */
159 159
160#define _BCM1480_INT_MASK(w,n) _SB_MAKEMASK(w,((n) & 0x3F)) 160#define _BCM1480_INT_MASK(w, n) _SB_MAKEMASK(w, ((n) & 0x3F))
161#define _BCM1480_INT_MASK1(n) _SB_MAKEMASK1(((n) & 0x3F)) 161#define _BCM1480_INT_MASK1(n) _SB_MAKEMASK1(((n) & 0x3F))
162#define _BCM1480_INT_OFFSET(n) (((n) & 0x40) << 6) 162#define _BCM1480_INT_OFFSET(n) (((n) & 0x40) << 6)
163 163
@@ -196,7 +196,7 @@
196#define M_BCM1480_INT_PMI_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH) 196#define M_BCM1480_INT_PMI_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH)
197#define M_BCM1480_INT_PMO_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW) 197#define M_BCM1480_INT_PMO_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW)
198#define M_BCM1480_INT_PMO_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH) 198#define M_BCM1480_INT_PMO_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH)
199#define M_BCM1480_INT_MBOX_ALL _BCM1480_INT_MASK(8,K_BCM1480_INT_MBOX_0_0) 199#define M_BCM1480_INT_MBOX_ALL _BCM1480_INT_MASK(8, K_BCM1480_INT_MBOX_0_0)
200#define M_BCM1480_INT_MBOX_0_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0) 200#define M_BCM1480_INT_MBOX_0_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0)
201#define M_BCM1480_INT_MBOX_0_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1) 201#define M_BCM1480_INT_MBOX_0_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1)
202#define M_BCM1480_INT_MBOX_0_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2) 202#define M_BCM1480_INT_MBOX_0_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2)
@@ -269,9 +269,9 @@
269 */ 269 */
270 270
271#define S_BCM1480_INT_HT_INTMSG 0 271#define S_BCM1480_INT_HT_INTMSG 0
272#define M_BCM1480_INT_HT_INTMSG _SB_MAKEMASK(3,S_BCM1480_INT_HT_INTMSG) 272#define M_BCM1480_INT_HT_INTMSG _SB_MAKEMASK(3, S_BCM1480_INT_HT_INTMSG)
273#define V_BCM1480_INT_HT_INTMSG(x) _SB_MAKEVALUE(x,S_BCM1480_INT_HT_INTMSG) 273#define V_BCM1480_INT_HT_INTMSG(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTMSG)
274#define G_BCM1480_INT_HT_INTMSG(x) _SB_GETVALUE(x,S_BCM1480_INT_HT_INTMSG,M_BCM1480_INT_HT_INTMSG) 274#define G_BCM1480_INT_HT_INTMSG(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_INTMSG, M_BCM1480_INT_HT_INTMSG)
275 275
276#define K_BCM1480_INT_HT_INTMSG_FIXED 0 276#define K_BCM1480_INT_HT_INTMSG_FIXED 0
277#define K_BCM1480_INT_HT_INTMSG_ARBITRATED 1 277#define K_BCM1480_INT_HT_INTMSG_ARBITRATED 1
@@ -291,14 +291,14 @@
291#define V_BCM1480_INT_HT_LOGICALDEST M_BCM1480_INT_HT_DESTMODE 291#define V_BCM1480_INT_HT_LOGICALDEST M_BCM1480_INT_HT_DESTMODE
292 292
293#define S_BCM1480_INT_HT_INTDEST 5 293#define S_BCM1480_INT_HT_INTDEST 5
294#define M_BCM1480_INT_HT_INTDEST _SB_MAKEMASK(8,S_BCM1480_INT_HT_INTDEST) 294#define M_BCM1480_INT_HT_INTDEST _SB_MAKEMASK(8, S_BCM1480_INT_HT_INTDEST)
295#define V_BCM1480_INT_HT_INTDEST(x) _SB_MAKEVALUE(x,S_BCM1480_INT_HT_INTDEST) 295#define V_BCM1480_INT_HT_INTDEST(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTDEST)
296#define G_BCM1480_INT_HT_INTDEST(x) _SB_GETVALUE(x,S_BCM1480_INT_HT_INTDEST,M_BCM1480_INT_HT_INTDEST) 296#define G_BCM1480_INT_HT_INTDEST(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_INTDEST, M_BCM1480_INT_HT_INTDEST)
297 297
298#define S_BCM1480_INT_HT_VECTOR 13 298#define S_BCM1480_INT_HT_VECTOR 13
299#define M_BCM1480_INT_HT_VECTOR _SB_MAKEMASK(8,S_BCM1480_INT_HT_VECTOR) 299#define M_BCM1480_INT_HT_VECTOR _SB_MAKEMASK(8, S_BCM1480_INT_HT_VECTOR)
300#define V_BCM1480_INT_HT_VECTOR(x) _SB_MAKEVALUE(x,S_BCM1480_INT_HT_VECTOR) 300#define V_BCM1480_INT_HT_VECTOR(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_VECTOR)
301#define G_BCM1480_INT_HT_VECTOR(x) _SB_GETVALUE(x,S_BCM1480_INT_HT_VECTOR,M_BCM1480_INT_HT_VECTOR) 301#define G_BCM1480_INT_HT_VECTOR(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_VECTOR, M_BCM1480_INT_HT_VECTOR)
302 302
303/* 303/*
304 * Vector prefix (Table 4-7) 304 * Vector prefix (Table 4-7)
diff --git a/include/asm-mips/sibyte/bcm1480_l2c.h b/include/asm-mips/sibyte/bcm1480_l2c.h
index 886b099565e6..fd75817f7ac4 100644
--- a/include/asm-mips/sibyte/bcm1480_l2c.h
+++ b/include/asm-mips/sibyte/bcm1480_l2c.h
@@ -40,22 +40,22 @@
40 */ 40 */
41 41
42#define S_BCM1480_L2C_MGMT_INDEX 5 42#define S_BCM1480_L2C_MGMT_INDEX 5
43#define M_BCM1480_L2C_MGMT_INDEX _SB_MAKEMASK(12,S_BCM1480_L2C_MGMT_INDEX) 43#define M_BCM1480_L2C_MGMT_INDEX _SB_MAKEMASK(12, S_BCM1480_L2C_MGMT_INDEX)
44#define V_BCM1480_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_MGMT_INDEX) 44#define V_BCM1480_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_INDEX)
45#define G_BCM1480_L2C_MGMT_INDEX(x) _SB_GETVALUE(x,S_BCM1480_L2C_MGMT_INDEX,M_BCM1480_L2C_MGMT_INDEX) 45#define G_BCM1480_L2C_MGMT_INDEX(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_INDEX, M_BCM1480_L2C_MGMT_INDEX)
46 46
47#define S_BCM1480_L2C_MGMT_WAY 17 47#define S_BCM1480_L2C_MGMT_WAY 17
48#define M_BCM1480_L2C_MGMT_WAY _SB_MAKEMASK(3,S_BCM1480_L2C_MGMT_WAY) 48#define M_BCM1480_L2C_MGMT_WAY _SB_MAKEMASK(3, S_BCM1480_L2C_MGMT_WAY)
49#define V_BCM1480_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_MGMT_WAY) 49#define V_BCM1480_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_WAY)
50#define G_BCM1480_L2C_MGMT_WAY(x) _SB_GETVALUE(x,S_BCM1480_L2C_MGMT_WAY,M_BCM1480_L2C_MGMT_WAY) 50#define G_BCM1480_L2C_MGMT_WAY(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_WAY, M_BCM1480_L2C_MGMT_WAY)
51 51
52#define M_BCM1480_L2C_MGMT_DIRTY _SB_MAKEMASK1(20) 52#define M_BCM1480_L2C_MGMT_DIRTY _SB_MAKEMASK1(20)
53#define M_BCM1480_L2C_MGMT_VALID _SB_MAKEMASK1(21) 53#define M_BCM1480_L2C_MGMT_VALID _SB_MAKEMASK1(21)
54 54
55#define S_BCM1480_L2C_MGMT_ECC_DIAG 22 55#define S_BCM1480_L2C_MGMT_ECC_DIAG 22
56#define M_BCM1480_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2,S_BCM1480_L2C_MGMT_ECC_DIAG) 56#define M_BCM1480_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2, S_BCM1480_L2C_MGMT_ECC_DIAG)
57#define V_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_MGMT_ECC_DIAG) 57#define V_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG)
58#define G_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x,S_BCM1480_L2C_MGMT_ECC_DIAG,M_BCM1480_L2C_MGMT_ECC_DIAG) 58#define G_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG, M_BCM1480_L2C_MGMT_ECC_DIAG)
59 59
60#define A_BCM1480_L2C_MGMT_TAG_BASE 0x00D0000000 60#define A_BCM1480_L2C_MGMT_TAG_BASE 0x00D0000000
61 61
@@ -68,36 +68,36 @@
68 */ 68 */
69 69
70#define S_BCM1480_L2C_TAG_MBZ 0 70#define S_BCM1480_L2C_TAG_MBZ 0
71#define M_BCM1480_L2C_TAG_MBZ _SB_MAKEMASK(5,S_BCM1480_L2C_TAG_MBZ) 71#define M_BCM1480_L2C_TAG_MBZ _SB_MAKEMASK(5, S_BCM1480_L2C_TAG_MBZ)
72 72
73#define S_BCM1480_L2C_TAG_INDEX 5 73#define S_BCM1480_L2C_TAG_INDEX 5
74#define M_BCM1480_L2C_TAG_INDEX _SB_MAKEMASK(12,S_BCM1480_L2C_TAG_INDEX) 74#define M_BCM1480_L2C_TAG_INDEX _SB_MAKEMASK(12, S_BCM1480_L2C_TAG_INDEX)
75#define V_BCM1480_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_INDEX) 75#define V_BCM1480_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_INDEX)
76#define G_BCM1480_L2C_TAG_INDEX(x) _SB_GETVALUE(x,S_BCM1480_L2C_TAG_INDEX,M_BCM1480_L2C_TAG_INDEX) 76#define G_BCM1480_L2C_TAG_INDEX(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_INDEX, M_BCM1480_L2C_TAG_INDEX)
77 77
78/* Note that index bit 16 is also tag bit 40 */ 78/* Note that index bit 16 is also tag bit 40 */
79#define S_BCM1480_L2C_TAG_TAG 17 79#define S_BCM1480_L2C_TAG_TAG 17
80#define M_BCM1480_L2C_TAG_TAG _SB_MAKEMASK(23,S_BCM1480_L2C_TAG_TAG) 80#define M_BCM1480_L2C_TAG_TAG _SB_MAKEMASK(23, S_BCM1480_L2C_TAG_TAG)
81#define V_BCM1480_L2C_TAG_TAG(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_TAG) 81#define V_BCM1480_L2C_TAG_TAG(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_TAG)
82#define G_BCM1480_L2C_TAG_TAG(x) _SB_GETVALUE(x,S_BCM1480_L2C_TAG_TAG,M_BCM1480_L2C_TAG_TAG) 82#define G_BCM1480_L2C_TAG_TAG(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_TAG, M_BCM1480_L2C_TAG_TAG)
83 83
84#define S_BCM1480_L2C_TAG_ECC 40 84#define S_BCM1480_L2C_TAG_ECC 40
85#define M_BCM1480_L2C_TAG_ECC _SB_MAKEMASK(6,S_BCM1480_L2C_TAG_ECC) 85#define M_BCM1480_L2C_TAG_ECC _SB_MAKEMASK(6, S_BCM1480_L2C_TAG_ECC)
86#define V_BCM1480_L2C_TAG_ECC(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_ECC) 86#define V_BCM1480_L2C_TAG_ECC(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_ECC)
87#define G_BCM1480_L2C_TAG_ECC(x) _SB_GETVALUE(x,S_BCM1480_L2C_TAG_ECC,M_BCM1480_L2C_TAG_ECC) 87#define G_BCM1480_L2C_TAG_ECC(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_ECC, M_BCM1480_L2C_TAG_ECC)
88 88
89#define S_BCM1480_L2C_TAG_WAY 46 89#define S_BCM1480_L2C_TAG_WAY 46
90#define M_BCM1480_L2C_TAG_WAY _SB_MAKEMASK(3,S_BCM1480_L2C_TAG_WAY) 90#define M_BCM1480_L2C_TAG_WAY _SB_MAKEMASK(3, S_BCM1480_L2C_TAG_WAY)
91#define V_BCM1480_L2C_TAG_WAY(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_TAG_WAY) 91#define V_BCM1480_L2C_TAG_WAY(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_WAY)
92#define G_BCM1480_L2C_TAG_WAY(x) _SB_GETVALUE(x,S_BCM1480_L2C_TAG_WAY,M_BCM1480_L2C_TAG_WAY) 92#define G_BCM1480_L2C_TAG_WAY(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_WAY, M_BCM1480_L2C_TAG_WAY)
93 93
94#define M_BCM1480_L2C_TAG_DIRTY _SB_MAKEMASK1(49) 94#define M_BCM1480_L2C_TAG_DIRTY _SB_MAKEMASK1(49)
95#define M_BCM1480_L2C_TAG_VALID _SB_MAKEMASK1(50) 95#define M_BCM1480_L2C_TAG_VALID _SB_MAKEMASK1(50)
96 96
97#define S_BCM1480_L2C_DATA_ECC 51 97#define S_BCM1480_L2C_DATA_ECC 51
98#define M_BCM1480_L2C_DATA_ECC _SB_MAKEMASK(10,S_BCM1480_L2C_DATA_ECC) 98#define M_BCM1480_L2C_DATA_ECC _SB_MAKEMASK(10, S_BCM1480_L2C_DATA_ECC)
99#define V_BCM1480_L2C_DATA_ECC(x) _SB_MAKEVALUE(x,S_BCM1480_L2C_DATA_ECC) 99#define V_BCM1480_L2C_DATA_ECC(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_DATA_ECC)
100#define G_BCM1480_L2C_DATA_ECC(x) _SB_GETVALUE(x,S_BCM1480_L2C_DATA_ECC,M_BCM1480_L2C_DATA_ECC) 100#define G_BCM1480_L2C_DATA_ECC(x) _SB_GETVALUE(x, S_BCM1480_L2C_DATA_ECC, M_BCM1480_L2C_DATA_ECC)
101 101
102 102
103/* 103/*
@@ -105,24 +105,24 @@
105 */ 105 */
106 106
107#define S_BCM1480_L2C_MISC0_WAY_REMOTE 0 107#define S_BCM1480_L2C_MISC0_WAY_REMOTE 0
108#define M_BCM1480_L2C_MISC0_WAY_REMOTE _SB_MAKEMASK(8,S_BCM1480_L2C_MISC0_WAY_REMOTE) 108#define M_BCM1480_L2C_MISC0_WAY_REMOTE _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_REMOTE)
109#define G_BCM1480_L2C_MISC0_WAY_REMOTE(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_WAY_REMOTE,M_BCM1480_L2C_MISC0_WAY_REMOTE) 109#define G_BCM1480_L2C_MISC0_WAY_REMOTE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_REMOTE, M_BCM1480_L2C_MISC0_WAY_REMOTE)
110 110
111#define S_BCM1480_L2C_MISC0_WAY_LOCAL 8 111#define S_BCM1480_L2C_MISC0_WAY_LOCAL 8
112#define M_BCM1480_L2C_MISC0_WAY_LOCAL _SB_MAKEMASK(8,S_BCM1480_L2C_MISC0_WAY_LOCAL) 112#define M_BCM1480_L2C_MISC0_WAY_LOCAL _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_LOCAL)
113#define G_BCM1480_L2C_MISC0_WAY_LOCAL(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_WAY_LOCAL,M_BCM1480_L2C_MISC0_WAY_LOCAL) 113#define G_BCM1480_L2C_MISC0_WAY_LOCAL(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_LOCAL, M_BCM1480_L2C_MISC0_WAY_LOCAL)
114 114
115#define S_BCM1480_L2C_MISC0_WAY_ENABLE 16 115#define S_BCM1480_L2C_MISC0_WAY_ENABLE 16
116#define M_BCM1480_L2C_MISC0_WAY_ENABLE _SB_MAKEMASK(8,S_BCM1480_L2C_MISC0_WAY_ENABLE) 116#define M_BCM1480_L2C_MISC0_WAY_ENABLE _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_ENABLE)
117#define G_BCM1480_L2C_MISC0_WAY_ENABLE(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_WAY_ENABLE,M_BCM1480_L2C_MISC0_WAY_ENABLE) 117#define G_BCM1480_L2C_MISC0_WAY_ENABLE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_ENABLE, M_BCM1480_L2C_MISC0_WAY_ENABLE)
118 118
119#define S_BCM1480_L2C_MISC0_CACHE_DISABLE 24 119#define S_BCM1480_L2C_MISC0_CACHE_DISABLE 24
120#define M_BCM1480_L2C_MISC0_CACHE_DISABLE _SB_MAKEMASK(2,S_BCM1480_L2C_MISC0_CACHE_DISABLE) 120#define M_BCM1480_L2C_MISC0_CACHE_DISABLE _SB_MAKEMASK(2, S_BCM1480_L2C_MISC0_CACHE_DISABLE)
121#define G_BCM1480_L2C_MISC0_CACHE_DISABLE(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_CACHE_DISABLE,M_BCM1480_L2C_MISC0_CACHE_DISABLE) 121#define G_BCM1480_L2C_MISC0_CACHE_DISABLE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_CACHE_DISABLE, M_BCM1480_L2C_MISC0_CACHE_DISABLE)
122 122
123#define S_BCM1480_L2C_MISC0_CACHE_QUAD 26 123#define S_BCM1480_L2C_MISC0_CACHE_QUAD 26
124#define M_BCM1480_L2C_MISC0_CACHE_QUAD _SB_MAKEMASK(2,S_BCM1480_L2C_MISC0_CACHE_QUAD) 124#define M_BCM1480_L2C_MISC0_CACHE_QUAD _SB_MAKEMASK(2, S_BCM1480_L2C_MISC0_CACHE_QUAD)
125#define G_BCM1480_L2C_MISC0_CACHE_QUAD(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC0_CACHE_QUAD,M_BCM1480_L2C_MISC0_CACHE_QUAD) 125#define G_BCM1480_L2C_MISC0_CACHE_QUAD(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_CACHE_QUAD, M_BCM1480_L2C_MISC0_CACHE_QUAD)
126 126
127#define S_BCM1480_L2C_MISC0_MC_PRIORITY 30 127#define S_BCM1480_L2C_MISC0_MC_PRIORITY 30
128#define M_BCM1480_L2C_MISC0_MC_PRIORITY _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_MC_PRIORITY) 128#define M_BCM1480_L2C_MISC0_MC_PRIORITY _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_MC_PRIORITY)
@@ -136,24 +136,24 @@
136 */ 136 */
137 137
138#define S_BCM1480_L2C_MISC1_WAY_AGENT_0 0 138#define S_BCM1480_L2C_MISC1_WAY_AGENT_0 0
139#define M_BCM1480_L2C_MISC1_WAY_AGENT_0 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_0) 139#define M_BCM1480_L2C_MISC1_WAY_AGENT_0 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_0)
140#define G_BCM1480_L2C_MISC1_WAY_AGENT_0(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_0,M_BCM1480_L2C_MISC1_WAY_AGENT_0) 140#define G_BCM1480_L2C_MISC1_WAY_AGENT_0(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_0, M_BCM1480_L2C_MISC1_WAY_AGENT_0)
141 141
142#define S_BCM1480_L2C_MISC1_WAY_AGENT_1 8 142#define S_BCM1480_L2C_MISC1_WAY_AGENT_1 8
143#define M_BCM1480_L2C_MISC1_WAY_AGENT_1 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_1) 143#define M_BCM1480_L2C_MISC1_WAY_AGENT_1 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_1)
144#define G_BCM1480_L2C_MISC1_WAY_AGENT_1(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_1,M_BCM1480_L2C_MISC1_WAY_AGENT_1) 144#define G_BCM1480_L2C_MISC1_WAY_AGENT_1(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_1, M_BCM1480_L2C_MISC1_WAY_AGENT_1)
145 145
146#define S_BCM1480_L2C_MISC1_WAY_AGENT_2 16 146#define S_BCM1480_L2C_MISC1_WAY_AGENT_2 16
147#define M_BCM1480_L2C_MISC1_WAY_AGENT_2 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_2) 147#define M_BCM1480_L2C_MISC1_WAY_AGENT_2 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_2)
148#define G_BCM1480_L2C_MISC1_WAY_AGENT_2(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_2,M_BCM1480_L2C_MISC1_WAY_AGENT_2) 148#define G_BCM1480_L2C_MISC1_WAY_AGENT_2(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_2, M_BCM1480_L2C_MISC1_WAY_AGENT_2)
149 149
150#define S_BCM1480_L2C_MISC1_WAY_AGENT_3 24 150#define S_BCM1480_L2C_MISC1_WAY_AGENT_3 24
151#define M_BCM1480_L2C_MISC1_WAY_AGENT_3 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_3) 151#define M_BCM1480_L2C_MISC1_WAY_AGENT_3 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_3)
152#define G_BCM1480_L2C_MISC1_WAY_AGENT_3(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_3,M_BCM1480_L2C_MISC1_WAY_AGENT_3) 152#define G_BCM1480_L2C_MISC1_WAY_AGENT_3(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_3, M_BCM1480_L2C_MISC1_WAY_AGENT_3)
153 153
154#define S_BCM1480_L2C_MISC1_WAY_AGENT_4 32 154#define S_BCM1480_L2C_MISC1_WAY_AGENT_4 32
155#define M_BCM1480_L2C_MISC1_WAY_AGENT_4 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC1_WAY_AGENT_4) 155#define M_BCM1480_L2C_MISC1_WAY_AGENT_4 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_4)
156#define G_BCM1480_L2C_MISC1_WAY_AGENT_4(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC1_WAY_AGENT_4,M_BCM1480_L2C_MISC1_WAY_AGENT_4) 156#define G_BCM1480_L2C_MISC1_WAY_AGENT_4(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_4, M_BCM1480_L2C_MISC1_WAY_AGENT_4)
157 157
158 158
159/* 159/*
@@ -161,16 +161,16 @@
161 */ 161 */
162 162
163#define S_BCM1480_L2C_MISC2_WAY_AGENT_8 0 163#define S_BCM1480_L2C_MISC2_WAY_AGENT_8 0
164#define M_BCM1480_L2C_MISC2_WAY_AGENT_8 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC2_WAY_AGENT_8) 164#define M_BCM1480_L2C_MISC2_WAY_AGENT_8 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_8)
165#define G_BCM1480_L2C_MISC2_WAY_AGENT_8(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC2_WAY_AGENT_8,M_BCM1480_L2C_MISC2_WAY_AGENT_8) 165#define G_BCM1480_L2C_MISC2_WAY_AGENT_8(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_8, M_BCM1480_L2C_MISC2_WAY_AGENT_8)
166 166
167#define S_BCM1480_L2C_MISC2_WAY_AGENT_9 8 167#define S_BCM1480_L2C_MISC2_WAY_AGENT_9 8
168#define M_BCM1480_L2C_MISC2_WAY_AGENT_9 _SB_MAKEMASK(8,S_BCM1480_L2C_MISC2_WAY_AGENT_9) 168#define M_BCM1480_L2C_MISC2_WAY_AGENT_9 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_9)
169#define G_BCM1480_L2C_MISC2_WAY_AGENT_9(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC2_WAY_AGENT_9,M_BCM1480_L2C_MISC2_WAY_AGENT_9) 169#define G_BCM1480_L2C_MISC2_WAY_AGENT_9(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_9, M_BCM1480_L2C_MISC2_WAY_AGENT_9)
170 170
171#define S_BCM1480_L2C_MISC2_WAY_AGENT_A 16 171#define S_BCM1480_L2C_MISC2_WAY_AGENT_A 16
172#define M_BCM1480_L2C_MISC2_WAY_AGENT_A _SB_MAKEMASK(8,S_BCM1480_L2C_MISC2_WAY_AGENT_A) 172#define M_BCM1480_L2C_MISC2_WAY_AGENT_A _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_A)
173#define G_BCM1480_L2C_MISC2_WAY_AGENT_A(x) _SB_GETVALUE(x,S_BCM1480_L2C_MISC2_WAY_AGENT_A,M_BCM1480_L2C_MISC2_WAY_AGENT_A) 173#define G_BCM1480_L2C_MISC2_WAY_AGENT_A(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_A, M_BCM1480_L2C_MISC2_WAY_AGENT_A)
174 174
175 175
176#endif /* _BCM1480_L2C_H */ 176#endif /* _BCM1480_L2C_H */
diff --git a/include/asm-mips/sibyte/bcm1480_mc.h b/include/asm-mips/sibyte/bcm1480_mc.h
index a6a437451da4..f26a41a82b59 100644
--- a/include/asm-mips/sibyte/bcm1480_mc.h
+++ b/include/asm-mips/sibyte/bcm1480_mc.h
@@ -40,27 +40,27 @@
40 */ 40 */
41 41
42#define S_BCM1480_MC_INTLV0 0 42#define S_BCM1480_MC_INTLV0 0
43#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV0) 43#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV0)
44#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV0) 44#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0)
45#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV0,M_BCM1480_MC_INTLV0) 45#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0)
46#define V_BCM1480_MC_INTLV0_DEFAULT V_BCM1480_MC_INTLV0(0) 46#define V_BCM1480_MC_INTLV0_DEFAULT V_BCM1480_MC_INTLV0(0)
47 47
48#define S_BCM1480_MC_INTLV1 8 48#define S_BCM1480_MC_INTLV1 8
49#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV1) 49#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV1)
50#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV1) 50#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1)
51#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV1,M_BCM1480_MC_INTLV1) 51#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1)
52#define V_BCM1480_MC_INTLV1_DEFAULT V_BCM1480_MC_INTLV1(0) 52#define V_BCM1480_MC_INTLV1_DEFAULT V_BCM1480_MC_INTLV1(0)
53 53
54#define S_BCM1480_MC_INTLV2 16 54#define S_BCM1480_MC_INTLV2 16
55#define M_BCM1480_MC_INTLV2 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV2) 55#define M_BCM1480_MC_INTLV2 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV2)
56#define V_BCM1480_MC_INTLV2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV2) 56#define V_BCM1480_MC_INTLV2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV2)
57#define G_BCM1480_MC_INTLV2(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV2,M_BCM1480_MC_INTLV2) 57#define G_BCM1480_MC_INTLV2(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV2, M_BCM1480_MC_INTLV2)
58#define V_BCM1480_MC_INTLV2_DEFAULT V_BCM1480_MC_INTLV2(0) 58#define V_BCM1480_MC_INTLV2_DEFAULT V_BCM1480_MC_INTLV2(0)
59 59
60#define S_BCM1480_MC_CS_MODE 32 60#define S_BCM1480_MC_CS_MODE 32
61#define M_BCM1480_MC_CS_MODE _SB_MAKEMASK(8,S_BCM1480_MC_CS_MODE) 61#define M_BCM1480_MC_CS_MODE _SB_MAKEMASK(8, S_BCM1480_MC_CS_MODE)
62#define V_BCM1480_MC_CS_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS_MODE) 62#define V_BCM1480_MC_CS_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS_MODE)
63#define G_BCM1480_MC_CS_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_CS_MODE,M_BCM1480_MC_CS_MODE) 63#define G_BCM1480_MC_CS_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_CS_MODE, M_BCM1480_MC_CS_MODE)
64#define V_BCM1480_MC_CS_MODE_DEFAULT V_BCM1480_MC_CS_MODE(0) 64#define V_BCM1480_MC_CS_MODE_DEFAULT V_BCM1480_MC_CS_MODE(0)
65 65
66#define V_BCM1480_MC_CONFIG_DEFAULT (V_BCM1480_MC_INTLV0_DEFAULT | \ 66#define V_BCM1480_MC_CONFIG_DEFAULT (V_BCM1480_MC_INTLV0_DEFAULT | \
@@ -81,131 +81,131 @@
81 */ 81 */
82 82
83#define S_BCM1480_MC_CS0_START 0 83#define S_BCM1480_MC_CS0_START 0
84#define M_BCM1480_MC_CS0_START _SB_MAKEMASK(12,S_BCM1480_MC_CS0_START) 84#define M_BCM1480_MC_CS0_START _SB_MAKEMASK(12, S_BCM1480_MC_CS0_START)
85#define V_BCM1480_MC_CS0_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS0_START) 85#define V_BCM1480_MC_CS0_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_START)
86#define G_BCM1480_MC_CS0_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS0_START,M_BCM1480_MC_CS0_START) 86#define G_BCM1480_MC_CS0_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0_START, M_BCM1480_MC_CS0_START)
87 87
88#define S_BCM1480_MC_CS1_START 16 88#define S_BCM1480_MC_CS1_START 16
89#define M_BCM1480_MC_CS1_START _SB_MAKEMASK(12,S_BCM1480_MC_CS1_START) 89#define M_BCM1480_MC_CS1_START _SB_MAKEMASK(12, S_BCM1480_MC_CS1_START)
90#define V_BCM1480_MC_CS1_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS1_START) 90#define V_BCM1480_MC_CS1_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_START)
91#define G_BCM1480_MC_CS1_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS1_START,M_BCM1480_MC_CS1_START) 91#define G_BCM1480_MC_CS1_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS1_START, M_BCM1480_MC_CS1_START)
92 92
93#define S_BCM1480_MC_CS2_START 32 93#define S_BCM1480_MC_CS2_START 32
94#define M_BCM1480_MC_CS2_START _SB_MAKEMASK(12,S_BCM1480_MC_CS2_START) 94#define M_BCM1480_MC_CS2_START _SB_MAKEMASK(12, S_BCM1480_MC_CS2_START)
95#define V_BCM1480_MC_CS2_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS2_START) 95#define V_BCM1480_MC_CS2_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_START)
96#define G_BCM1480_MC_CS2_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS2_START,M_BCM1480_MC_CS2_START) 96#define G_BCM1480_MC_CS2_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS2_START, M_BCM1480_MC_CS2_START)
97 97
98#define S_BCM1480_MC_CS3_START 48 98#define S_BCM1480_MC_CS3_START 48
99#define M_BCM1480_MC_CS3_START _SB_MAKEMASK(12,S_BCM1480_MC_CS3_START) 99#define M_BCM1480_MC_CS3_START _SB_MAKEMASK(12, S_BCM1480_MC_CS3_START)
100#define V_BCM1480_MC_CS3_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS3_START) 100#define V_BCM1480_MC_CS3_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_START)
101#define G_BCM1480_MC_CS3_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS3_START,M_BCM1480_MC_CS3_START) 101#define G_BCM1480_MC_CS3_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS3_START, M_BCM1480_MC_CS3_START)
102 102
103/* 103/*
104 * Chip Select End Address Register (Table 83) 104 * Chip Select End Address Register (Table 83)
105 */ 105 */
106 106
107#define S_BCM1480_MC_CS0_END 0 107#define S_BCM1480_MC_CS0_END 0
108#define M_BCM1480_MC_CS0_END _SB_MAKEMASK(12,S_BCM1480_MC_CS0_END) 108#define M_BCM1480_MC_CS0_END _SB_MAKEMASK(12, S_BCM1480_MC_CS0_END)
109#define V_BCM1480_MC_CS0_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS0_END) 109#define V_BCM1480_MC_CS0_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_END)
110#define G_BCM1480_MC_CS0_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS0_END,M_BCM1480_MC_CS0_END) 110#define G_BCM1480_MC_CS0_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0_END, M_BCM1480_MC_CS0_END)
111 111
112#define S_BCM1480_MC_CS1_END 16 112#define S_BCM1480_MC_CS1_END 16
113#define M_BCM1480_MC_CS1_END _SB_MAKEMASK(12,S_BCM1480_MC_CS1_END) 113#define M_BCM1480_MC_CS1_END _SB_MAKEMASK(12, S_BCM1480_MC_CS1_END)
114#define V_BCM1480_MC_CS1_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS1_END) 114#define V_BCM1480_MC_CS1_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_END)
115#define G_BCM1480_MC_CS1_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS1_END,M_BCM1480_MC_CS1_END) 115#define G_BCM1480_MC_CS1_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS1_END, M_BCM1480_MC_CS1_END)
116 116
117#define S_BCM1480_MC_CS2_END 32 117#define S_BCM1480_MC_CS2_END 32
118#define M_BCM1480_MC_CS2_END _SB_MAKEMASK(12,S_BCM1480_MC_CS2_END) 118#define M_BCM1480_MC_CS2_END _SB_MAKEMASK(12, S_BCM1480_MC_CS2_END)
119#define V_BCM1480_MC_CS2_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS2_END) 119#define V_BCM1480_MC_CS2_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_END)
120#define G_BCM1480_MC_CS2_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS2_END,M_BCM1480_MC_CS2_END) 120#define G_BCM1480_MC_CS2_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS2_END, M_BCM1480_MC_CS2_END)
121 121
122#define S_BCM1480_MC_CS3_END 48 122#define S_BCM1480_MC_CS3_END 48
123#define M_BCM1480_MC_CS3_END _SB_MAKEMASK(12,S_BCM1480_MC_CS3_END) 123#define M_BCM1480_MC_CS3_END _SB_MAKEMASK(12, S_BCM1480_MC_CS3_END)
124#define V_BCM1480_MC_CS3_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS3_END) 124#define V_BCM1480_MC_CS3_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_END)
125#define G_BCM1480_MC_CS3_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS3_END,M_BCM1480_MC_CS3_END) 125#define G_BCM1480_MC_CS3_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS3_END, M_BCM1480_MC_CS3_END)
126 126
127/* 127/*
128 * Row Address Bit Select Register 0 (Table 84) 128 * Row Address Bit Select Register 0 (Table 84)
129 */ 129 */
130 130
131#define S_BCM1480_MC_ROW00 0 131#define S_BCM1480_MC_ROW00 0
132#define M_BCM1480_MC_ROW00 _SB_MAKEMASK(6,S_BCM1480_MC_ROW00) 132#define M_BCM1480_MC_ROW00 _SB_MAKEMASK(6, S_BCM1480_MC_ROW00)
133#define V_BCM1480_MC_ROW00(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW00) 133#define V_BCM1480_MC_ROW00(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW00)
134#define G_BCM1480_MC_ROW00(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW00,M_BCM1480_MC_ROW00) 134#define G_BCM1480_MC_ROW00(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW00, M_BCM1480_MC_ROW00)
135 135
136#define S_BCM1480_MC_ROW01 8 136#define S_BCM1480_MC_ROW01 8
137#define M_BCM1480_MC_ROW01 _SB_MAKEMASK(6,S_BCM1480_MC_ROW01) 137#define M_BCM1480_MC_ROW01 _SB_MAKEMASK(6, S_BCM1480_MC_ROW01)
138#define V_BCM1480_MC_ROW01(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW01) 138#define V_BCM1480_MC_ROW01(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW01)
139#define G_BCM1480_MC_ROW01(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW01,M_BCM1480_MC_ROW01) 139#define G_BCM1480_MC_ROW01(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW01, M_BCM1480_MC_ROW01)
140 140
141#define S_BCM1480_MC_ROW02 16 141#define S_BCM1480_MC_ROW02 16
142#define M_BCM1480_MC_ROW02 _SB_MAKEMASK(6,S_BCM1480_MC_ROW02) 142#define M_BCM1480_MC_ROW02 _SB_MAKEMASK(6, S_BCM1480_MC_ROW02)
143#define V_BCM1480_MC_ROW02(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW02) 143#define V_BCM1480_MC_ROW02(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW02)
144#define G_BCM1480_MC_ROW02(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW02,M_BCM1480_MC_ROW02) 144#define G_BCM1480_MC_ROW02(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW02, M_BCM1480_MC_ROW02)
145 145
146#define S_BCM1480_MC_ROW03 24 146#define S_BCM1480_MC_ROW03 24
147#define M_BCM1480_MC_ROW03 _SB_MAKEMASK(6,S_BCM1480_MC_ROW03) 147#define M_BCM1480_MC_ROW03 _SB_MAKEMASK(6, S_BCM1480_MC_ROW03)
148#define V_BCM1480_MC_ROW03(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW03) 148#define V_BCM1480_MC_ROW03(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW03)
149#define G_BCM1480_MC_ROW03(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW03,M_BCM1480_MC_ROW03) 149#define G_BCM1480_MC_ROW03(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW03, M_BCM1480_MC_ROW03)
150 150
151#define S_BCM1480_MC_ROW04 32 151#define S_BCM1480_MC_ROW04 32
152#define M_BCM1480_MC_ROW04 _SB_MAKEMASK(6,S_BCM1480_MC_ROW04) 152#define M_BCM1480_MC_ROW04 _SB_MAKEMASK(6, S_BCM1480_MC_ROW04)
153#define V_BCM1480_MC_ROW04(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW04) 153#define V_BCM1480_MC_ROW04(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW04)
154#define G_BCM1480_MC_ROW04(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW04,M_BCM1480_MC_ROW04) 154#define G_BCM1480_MC_ROW04(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW04, M_BCM1480_MC_ROW04)
155 155
156#define S_BCM1480_MC_ROW05 40 156#define S_BCM1480_MC_ROW05 40
157#define M_BCM1480_MC_ROW05 _SB_MAKEMASK(6,S_BCM1480_MC_ROW05) 157#define M_BCM1480_MC_ROW05 _SB_MAKEMASK(6, S_BCM1480_MC_ROW05)
158#define V_BCM1480_MC_ROW05(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW05) 158#define V_BCM1480_MC_ROW05(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW05)
159#define G_BCM1480_MC_ROW05(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW05,M_BCM1480_MC_ROW05) 159#define G_BCM1480_MC_ROW05(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW05, M_BCM1480_MC_ROW05)
160 160
161#define S_BCM1480_MC_ROW06 48 161#define S_BCM1480_MC_ROW06 48
162#define M_BCM1480_MC_ROW06 _SB_MAKEMASK(6,S_BCM1480_MC_ROW06) 162#define M_BCM1480_MC_ROW06 _SB_MAKEMASK(6, S_BCM1480_MC_ROW06)
163#define V_BCM1480_MC_ROW06(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW06) 163#define V_BCM1480_MC_ROW06(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW06)
164#define G_BCM1480_MC_ROW06(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW06,M_BCM1480_MC_ROW06) 164#define G_BCM1480_MC_ROW06(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW06, M_BCM1480_MC_ROW06)
165 165
166#define S_BCM1480_MC_ROW07 56 166#define S_BCM1480_MC_ROW07 56
167#define M_BCM1480_MC_ROW07 _SB_MAKEMASK(6,S_BCM1480_MC_ROW07) 167#define M_BCM1480_MC_ROW07 _SB_MAKEMASK(6, S_BCM1480_MC_ROW07)
168#define V_BCM1480_MC_ROW07(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW07) 168#define V_BCM1480_MC_ROW07(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW07)
169#define G_BCM1480_MC_ROW07(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW07,M_BCM1480_MC_ROW07) 169#define G_BCM1480_MC_ROW07(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW07, M_BCM1480_MC_ROW07)
170 170
171/* 171/*
172 * Row Address Bit Select Register 1 (Table 85) 172 * Row Address Bit Select Register 1 (Table 85)
173 */ 173 */
174 174
175#define S_BCM1480_MC_ROW08 0 175#define S_BCM1480_MC_ROW08 0
176#define M_BCM1480_MC_ROW08 _SB_MAKEMASK(6,S_BCM1480_MC_ROW08) 176#define M_BCM1480_MC_ROW08 _SB_MAKEMASK(6, S_BCM1480_MC_ROW08)
177#define V_BCM1480_MC_ROW08(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW08) 177#define V_BCM1480_MC_ROW08(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW08)
178#define G_BCM1480_MC_ROW08(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW08,M_BCM1480_MC_ROW08) 178#define G_BCM1480_MC_ROW08(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW08, M_BCM1480_MC_ROW08)
179 179
180#define S_BCM1480_MC_ROW09 8 180#define S_BCM1480_MC_ROW09 8
181#define M_BCM1480_MC_ROW09 _SB_MAKEMASK(6,S_BCM1480_MC_ROW09) 181#define M_BCM1480_MC_ROW09 _SB_MAKEMASK(6, S_BCM1480_MC_ROW09)
182#define V_BCM1480_MC_ROW09(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW09) 182#define V_BCM1480_MC_ROW09(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW09)
183#define G_BCM1480_MC_ROW09(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW09,M_BCM1480_MC_ROW09) 183#define G_BCM1480_MC_ROW09(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW09, M_BCM1480_MC_ROW09)
184 184
185#define S_BCM1480_MC_ROW10 16 185#define S_BCM1480_MC_ROW10 16
186#define M_BCM1480_MC_ROW10 _SB_MAKEMASK(6,S_BCM1480_MC_ROW10) 186#define M_BCM1480_MC_ROW10 _SB_MAKEMASK(6, S_BCM1480_MC_ROW10)
187#define V_BCM1480_MC_ROW10(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW10) 187#define V_BCM1480_MC_ROW10(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW10)
188#define G_BCM1480_MC_ROW10(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW10,M_BCM1480_MC_ROW10) 188#define G_BCM1480_MC_ROW10(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW10, M_BCM1480_MC_ROW10)
189 189
190#define S_BCM1480_MC_ROW11 24 190#define S_BCM1480_MC_ROW11 24
191#define M_BCM1480_MC_ROW11 _SB_MAKEMASK(6,S_BCM1480_MC_ROW11) 191#define M_BCM1480_MC_ROW11 _SB_MAKEMASK(6, S_BCM1480_MC_ROW11)
192#define V_BCM1480_MC_ROW11(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW11) 192#define V_BCM1480_MC_ROW11(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW11)
193#define G_BCM1480_MC_ROW11(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW11,M_BCM1480_MC_ROW11) 193#define G_BCM1480_MC_ROW11(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW11, M_BCM1480_MC_ROW11)
194 194
195#define S_BCM1480_MC_ROW12 32 195#define S_BCM1480_MC_ROW12 32
196#define M_BCM1480_MC_ROW12 _SB_MAKEMASK(6,S_BCM1480_MC_ROW12) 196#define M_BCM1480_MC_ROW12 _SB_MAKEMASK(6, S_BCM1480_MC_ROW12)
197#define V_BCM1480_MC_ROW12(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW12) 197#define V_BCM1480_MC_ROW12(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW12)
198#define G_BCM1480_MC_ROW12(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW12,M_BCM1480_MC_ROW12) 198#define G_BCM1480_MC_ROW12(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW12, M_BCM1480_MC_ROW12)
199 199
200#define S_BCM1480_MC_ROW13 40 200#define S_BCM1480_MC_ROW13 40
201#define M_BCM1480_MC_ROW13 _SB_MAKEMASK(6,S_BCM1480_MC_ROW13) 201#define M_BCM1480_MC_ROW13 _SB_MAKEMASK(6, S_BCM1480_MC_ROW13)
202#define V_BCM1480_MC_ROW13(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW13) 202#define V_BCM1480_MC_ROW13(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW13)
203#define G_BCM1480_MC_ROW13(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW13,M_BCM1480_MC_ROW13) 203#define G_BCM1480_MC_ROW13(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW13, M_BCM1480_MC_ROW13)
204 204
205#define S_BCM1480_MC_ROW14 48 205#define S_BCM1480_MC_ROW14 48
206#define M_BCM1480_MC_ROW14 _SB_MAKEMASK(6,S_BCM1480_MC_ROW14) 206#define M_BCM1480_MC_ROW14 _SB_MAKEMASK(6, S_BCM1480_MC_ROW14)
207#define V_BCM1480_MC_ROW14(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW14) 207#define V_BCM1480_MC_ROW14(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW14)
208#define G_BCM1480_MC_ROW14(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW14,M_BCM1480_MC_ROW14) 208#define G_BCM1480_MC_ROW14(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW14, M_BCM1480_MC_ROW14)
209 209
210#define K_BCM1480_MC_ROWX_BIT_SPACING 8 210#define K_BCM1480_MC_ROWX_BIT_SPACING 8
211 211
@@ -214,80 +214,80 @@
214 */ 214 */
215 215
216#define S_BCM1480_MC_COL00 0 216#define S_BCM1480_MC_COL00 0
217#define M_BCM1480_MC_COL00 _SB_MAKEMASK(6,S_BCM1480_MC_COL00) 217#define M_BCM1480_MC_COL00 _SB_MAKEMASK(6, S_BCM1480_MC_COL00)
218#define V_BCM1480_MC_COL00(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL00) 218#define V_BCM1480_MC_COL00(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL00)
219#define G_BCM1480_MC_COL00(x) _SB_GETVALUE(x,S_BCM1480_MC_COL00,M_BCM1480_MC_COL00) 219#define G_BCM1480_MC_COL00(x) _SB_GETVALUE(x, S_BCM1480_MC_COL00, M_BCM1480_MC_COL00)
220 220
221#define S_BCM1480_MC_COL01 8 221#define S_BCM1480_MC_COL01 8
222#define M_BCM1480_MC_COL01 _SB_MAKEMASK(6,S_BCM1480_MC_COL01) 222#define M_BCM1480_MC_COL01 _SB_MAKEMASK(6, S_BCM1480_MC_COL01)
223#define V_BCM1480_MC_COL01(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL01) 223#define V_BCM1480_MC_COL01(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL01)
224#define G_BCM1480_MC_COL01(x) _SB_GETVALUE(x,S_BCM1480_MC_COL01,M_BCM1480_MC_COL01) 224#define G_BCM1480_MC_COL01(x) _SB_GETVALUE(x, S_BCM1480_MC_COL01, M_BCM1480_MC_COL01)
225 225
226#define S_BCM1480_MC_COL02 16 226#define S_BCM1480_MC_COL02 16
227#define M_BCM1480_MC_COL02 _SB_MAKEMASK(6,S_BCM1480_MC_COL02) 227#define M_BCM1480_MC_COL02 _SB_MAKEMASK(6, S_BCM1480_MC_COL02)
228#define V_BCM1480_MC_COL02(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL02) 228#define V_BCM1480_MC_COL02(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL02)
229#define G_BCM1480_MC_COL02(x) _SB_GETVALUE(x,S_BCM1480_MC_COL02,M_BCM1480_MC_COL02) 229#define G_BCM1480_MC_COL02(x) _SB_GETVALUE(x, S_BCM1480_MC_COL02, M_BCM1480_MC_COL02)
230 230
231#define S_BCM1480_MC_COL03 24 231#define S_BCM1480_MC_COL03 24
232#define M_BCM1480_MC_COL03 _SB_MAKEMASK(6,S_BCM1480_MC_COL03) 232#define M_BCM1480_MC_COL03 _SB_MAKEMASK(6, S_BCM1480_MC_COL03)
233#define V_BCM1480_MC_COL03(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL03) 233#define V_BCM1480_MC_COL03(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL03)
234#define G_BCM1480_MC_COL03(x) _SB_GETVALUE(x,S_BCM1480_MC_COL03,M_BCM1480_MC_COL03) 234#define G_BCM1480_MC_COL03(x) _SB_GETVALUE(x, S_BCM1480_MC_COL03, M_BCM1480_MC_COL03)
235 235
236#define S_BCM1480_MC_COL04 32 236#define S_BCM1480_MC_COL04 32
237#define M_BCM1480_MC_COL04 _SB_MAKEMASK(6,S_BCM1480_MC_COL04) 237#define M_BCM1480_MC_COL04 _SB_MAKEMASK(6, S_BCM1480_MC_COL04)
238#define V_BCM1480_MC_COL04(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL04) 238#define V_BCM1480_MC_COL04(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL04)
239#define G_BCM1480_MC_COL04(x) _SB_GETVALUE(x,S_BCM1480_MC_COL04,M_BCM1480_MC_COL04) 239#define G_BCM1480_MC_COL04(x) _SB_GETVALUE(x, S_BCM1480_MC_COL04, M_BCM1480_MC_COL04)
240 240
241#define S_BCM1480_MC_COL05 40 241#define S_BCM1480_MC_COL05 40
242#define M_BCM1480_MC_COL05 _SB_MAKEMASK(6,S_BCM1480_MC_COL05) 242#define M_BCM1480_MC_COL05 _SB_MAKEMASK(6, S_BCM1480_MC_COL05)
243#define V_BCM1480_MC_COL05(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL05) 243#define V_BCM1480_MC_COL05(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL05)
244#define G_BCM1480_MC_COL05(x) _SB_GETVALUE(x,S_BCM1480_MC_COL05,M_BCM1480_MC_COL05) 244#define G_BCM1480_MC_COL05(x) _SB_GETVALUE(x, S_BCM1480_MC_COL05, M_BCM1480_MC_COL05)
245 245
246#define S_BCM1480_MC_COL06 48 246#define S_BCM1480_MC_COL06 48
247#define M_BCM1480_MC_COL06 _SB_MAKEMASK(6,S_BCM1480_MC_COL06) 247#define M_BCM1480_MC_COL06 _SB_MAKEMASK(6, S_BCM1480_MC_COL06)
248#define V_BCM1480_MC_COL06(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL06) 248#define V_BCM1480_MC_COL06(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL06)
249#define G_BCM1480_MC_COL06(x) _SB_GETVALUE(x,S_BCM1480_MC_COL06,M_BCM1480_MC_COL06) 249#define G_BCM1480_MC_COL06(x) _SB_GETVALUE(x, S_BCM1480_MC_COL06, M_BCM1480_MC_COL06)
250 250
251#define S_BCM1480_MC_COL07 56 251#define S_BCM1480_MC_COL07 56
252#define M_BCM1480_MC_COL07 _SB_MAKEMASK(6,S_BCM1480_MC_COL07) 252#define M_BCM1480_MC_COL07 _SB_MAKEMASK(6, S_BCM1480_MC_COL07)
253#define V_BCM1480_MC_COL07(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL07) 253#define V_BCM1480_MC_COL07(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL07)
254#define G_BCM1480_MC_COL07(x) _SB_GETVALUE(x,S_BCM1480_MC_COL07,M_BCM1480_MC_COL07) 254#define G_BCM1480_MC_COL07(x) _SB_GETVALUE(x, S_BCM1480_MC_COL07, M_BCM1480_MC_COL07)
255 255
256/* 256/*
257 * Column Address Bit Select Register 1 (Table 87) 257 * Column Address Bit Select Register 1 (Table 87)
258 */ 258 */
259 259
260#define S_BCM1480_MC_COL08 0 260#define S_BCM1480_MC_COL08 0
261#define M_BCM1480_MC_COL08 _SB_MAKEMASK(6,S_BCM1480_MC_COL08) 261#define M_BCM1480_MC_COL08 _SB_MAKEMASK(6, S_BCM1480_MC_COL08)
262#define V_BCM1480_MC_COL08(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL08) 262#define V_BCM1480_MC_COL08(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL08)
263#define G_BCM1480_MC_COL08(x) _SB_GETVALUE(x,S_BCM1480_MC_COL08,M_BCM1480_MC_COL08) 263#define G_BCM1480_MC_COL08(x) _SB_GETVALUE(x, S_BCM1480_MC_COL08, M_BCM1480_MC_COL08)
264 264
265#define S_BCM1480_MC_COL09 8 265#define S_BCM1480_MC_COL09 8
266#define M_BCM1480_MC_COL09 _SB_MAKEMASK(6,S_BCM1480_MC_COL09) 266#define M_BCM1480_MC_COL09 _SB_MAKEMASK(6, S_BCM1480_MC_COL09)
267#define V_BCM1480_MC_COL09(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL09) 267#define V_BCM1480_MC_COL09(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL09)
268#define G_BCM1480_MC_COL09(x) _SB_GETVALUE(x,S_BCM1480_MC_COL09,M_BCM1480_MC_COL09) 268#define G_BCM1480_MC_COL09(x) _SB_GETVALUE(x, S_BCM1480_MC_COL09, M_BCM1480_MC_COL09)
269 269
270#define S_BCM1480_MC_COL10 16 /* not a valid position, must be prog as 0 */ 270#define S_BCM1480_MC_COL10 16 /* not a valid position, must be prog as 0 */
271 271
272#define S_BCM1480_MC_COL11 24 272#define S_BCM1480_MC_COL11 24
273#define M_BCM1480_MC_COL11 _SB_MAKEMASK(6,S_BCM1480_MC_COL11) 273#define M_BCM1480_MC_COL11 _SB_MAKEMASK(6, S_BCM1480_MC_COL11)
274#define V_BCM1480_MC_COL11(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL11) 274#define V_BCM1480_MC_COL11(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL11)
275#define G_BCM1480_MC_COL11(x) _SB_GETVALUE(x,S_BCM1480_MC_COL11,M_BCM1480_MC_COL11) 275#define G_BCM1480_MC_COL11(x) _SB_GETVALUE(x, S_BCM1480_MC_COL11, M_BCM1480_MC_COL11)
276 276
277#define S_BCM1480_MC_COL12 32 277#define S_BCM1480_MC_COL12 32
278#define M_BCM1480_MC_COL12 _SB_MAKEMASK(6,S_BCM1480_MC_COL12) 278#define M_BCM1480_MC_COL12 _SB_MAKEMASK(6, S_BCM1480_MC_COL12)
279#define V_BCM1480_MC_COL12(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL12) 279#define V_BCM1480_MC_COL12(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL12)
280#define G_BCM1480_MC_COL12(x) _SB_GETVALUE(x,S_BCM1480_MC_COL12,M_BCM1480_MC_COL12) 280#define G_BCM1480_MC_COL12(x) _SB_GETVALUE(x, S_BCM1480_MC_COL12, M_BCM1480_MC_COL12)
281 281
282#define S_BCM1480_MC_COL13 40 282#define S_BCM1480_MC_COL13 40
283#define M_BCM1480_MC_COL13 _SB_MAKEMASK(6,S_BCM1480_MC_COL13) 283#define M_BCM1480_MC_COL13 _SB_MAKEMASK(6, S_BCM1480_MC_COL13)
284#define V_BCM1480_MC_COL13(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL13) 284#define V_BCM1480_MC_COL13(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL13)
285#define G_BCM1480_MC_COL13(x) _SB_GETVALUE(x,S_BCM1480_MC_COL13,M_BCM1480_MC_COL13) 285#define G_BCM1480_MC_COL13(x) _SB_GETVALUE(x, S_BCM1480_MC_COL13, M_BCM1480_MC_COL13)
286 286
287#define S_BCM1480_MC_COL14 48 287#define S_BCM1480_MC_COL14 48
288#define M_BCM1480_MC_COL14 _SB_MAKEMASK(6,S_BCM1480_MC_COL14) 288#define M_BCM1480_MC_COL14 _SB_MAKEMASK(6, S_BCM1480_MC_COL14)
289#define V_BCM1480_MC_COL14(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL14) 289#define V_BCM1480_MC_COL14(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL14)
290#define G_BCM1480_MC_COL14(x) _SB_GETVALUE(x,S_BCM1480_MC_COL14,M_BCM1480_MC_COL14) 290#define G_BCM1480_MC_COL14(x) _SB_GETVALUE(x, S_BCM1480_MC_COL14, M_BCM1480_MC_COL14)
291 291
292#define K_BCM1480_MC_COLX_BIT_SPACING 8 292#define K_BCM1480_MC_COLX_BIT_SPACING 8
293 293
@@ -296,38 +296,38 @@
296 */ 296 */
297 297
298#define S_BCM1480_MC_CS01_BANK0 0 298#define S_BCM1480_MC_CS01_BANK0 0
299#define M_BCM1480_MC_CS01_BANK0 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK0) 299#define M_BCM1480_MC_CS01_BANK0 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK0)
300#define V_BCM1480_MC_CS01_BANK0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK0) 300#define V_BCM1480_MC_CS01_BANK0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK0)
301#define G_BCM1480_MC_CS01_BANK0(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK0,M_BCM1480_MC_CS01_BANK0) 301#define G_BCM1480_MC_CS01_BANK0(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK0, M_BCM1480_MC_CS01_BANK0)
302 302
303#define S_BCM1480_MC_CS01_BANK1 8 303#define S_BCM1480_MC_CS01_BANK1 8
304#define M_BCM1480_MC_CS01_BANK1 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK1) 304#define M_BCM1480_MC_CS01_BANK1 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK1)
305#define V_BCM1480_MC_CS01_BANK1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK1) 305#define V_BCM1480_MC_CS01_BANK1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK1)
306#define G_BCM1480_MC_CS01_BANK1(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK1,M_BCM1480_MC_CS01_BANK1) 306#define G_BCM1480_MC_CS01_BANK1(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK1, M_BCM1480_MC_CS01_BANK1)
307 307
308#define S_BCM1480_MC_CS01_BANK2 16 308#define S_BCM1480_MC_CS01_BANK2 16
309#define M_BCM1480_MC_CS01_BANK2 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK2) 309#define M_BCM1480_MC_CS01_BANK2 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK2)
310#define V_BCM1480_MC_CS01_BANK2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK2) 310#define V_BCM1480_MC_CS01_BANK2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK2)
311#define G_BCM1480_MC_CS01_BANK2(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK2,M_BCM1480_MC_CS01_BANK2) 311#define G_BCM1480_MC_CS01_BANK2(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK2, M_BCM1480_MC_CS01_BANK2)
312 312
313/* 313/*
314 * CS2 and CS3 Bank Address Bit Select Register (Table 89) 314 * CS2 and CS3 Bank Address Bit Select Register (Table 89)
315 */ 315 */
316 316
317#define S_BCM1480_MC_CS23_BANK0 0 317#define S_BCM1480_MC_CS23_BANK0 0
318#define M_BCM1480_MC_CS23_BANK0 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK0) 318#define M_BCM1480_MC_CS23_BANK0 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK0)
319#define V_BCM1480_MC_CS23_BANK0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK0) 319#define V_BCM1480_MC_CS23_BANK0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK0)
320#define G_BCM1480_MC_CS23_BANK0(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK0,M_BCM1480_MC_CS23_BANK0) 320#define G_BCM1480_MC_CS23_BANK0(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK0, M_BCM1480_MC_CS23_BANK0)
321 321
322#define S_BCM1480_MC_CS23_BANK1 8 322#define S_BCM1480_MC_CS23_BANK1 8
323#define M_BCM1480_MC_CS23_BANK1 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK1) 323#define M_BCM1480_MC_CS23_BANK1 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK1)
324#define V_BCM1480_MC_CS23_BANK1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK1) 324#define V_BCM1480_MC_CS23_BANK1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK1)
325#define G_BCM1480_MC_CS23_BANK1(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK1,M_BCM1480_MC_CS23_BANK1) 325#define G_BCM1480_MC_CS23_BANK1(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK1, M_BCM1480_MC_CS23_BANK1)
326 326
327#define S_BCM1480_MC_CS23_BANK2 16 327#define S_BCM1480_MC_CS23_BANK2 16
328#define M_BCM1480_MC_CS23_BANK2 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK2) 328#define M_BCM1480_MC_CS23_BANK2 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK2)
329#define V_BCM1480_MC_CS23_BANK2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK2) 329#define V_BCM1480_MC_CS23_BANK2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK2)
330#define G_BCM1480_MC_CS23_BANK2(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK2,M_BCM1480_MC_CS23_BANK2) 330#define G_BCM1480_MC_CS23_BANK2(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK2, M_BCM1480_MC_CS23_BANK2)
331 331
332#define K_BCM1480_MC_CSXX_BANKX_BIT_SPACING 8 332#define K_BCM1480_MC_CSXX_BANKX_BIT_SPACING 8
333 333
@@ -336,9 +336,9 @@
336 */ 336 */
337 337
338#define S_BCM1480_MC_COMMAND 0 338#define S_BCM1480_MC_COMMAND 0
339#define M_BCM1480_MC_COMMAND _SB_MAKEMASK(4,S_BCM1480_MC_COMMAND) 339#define M_BCM1480_MC_COMMAND _SB_MAKEMASK(4, S_BCM1480_MC_COMMAND)
340#define V_BCM1480_MC_COMMAND(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COMMAND) 340#define V_BCM1480_MC_COMMAND(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COMMAND)
341#define G_BCM1480_MC_COMMAND(x) _SB_GETVALUE(x,S_BCM1480_MC_COMMAND,M_BCM1480_MC_COMMAND) 341#define G_BCM1480_MC_COMMAND(x) _SB_GETVALUE(x, S_BCM1480_MC_COMMAND, M_BCM1480_MC_COMMAND)
342 342
343#define K_BCM1480_MC_COMMAND_EMRS 0 343#define K_BCM1480_MC_COMMAND_EMRS 0
344#define K_BCM1480_MC_COMMAND_MRS 1 344#define K_BCM1480_MC_COMMAND_MRS 1
@@ -382,9 +382,9 @@
382#define M_BCM1480_MC_CS6 _SB_MAKEMASK1(10) 382#define M_BCM1480_MC_CS6 _SB_MAKEMASK1(10)
383#define M_BCM1480_MC_CS7 _SB_MAKEMASK1(11) 383#define M_BCM1480_MC_CS7 _SB_MAKEMASK1(11)
384 384
385#define M_BCM1480_MC_CS _SB_MAKEMASK(8,S_BCM1480_MC_CS0) 385#define M_BCM1480_MC_CS _SB_MAKEMASK(8, S_BCM1480_MC_CS0)
386#define V_BCM1480_MC_CS(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS0) 386#define V_BCM1480_MC_CS(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0)
387#define G_BCM1480_MC_CS(x) _SB_GETVALUE(x,S_BCM1480_MC_CS0,M_BCM1480_MC_CS0) 387#define G_BCM1480_MC_CS(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0, M_BCM1480_MC_CS0)
388 388
389#define M_BCM1480_MC_CMD_ACTIVE _SB_MAKEMASK1(16) 389#define M_BCM1480_MC_CMD_ACTIVE _SB_MAKEMASK1(16)
390 390
@@ -393,21 +393,21 @@
393 */ 393 */
394 394
395#define S_BCM1480_MC_EMODE 0 395#define S_BCM1480_MC_EMODE 0
396#define M_BCM1480_MC_EMODE _SB_MAKEMASK(15,S_BCM1480_MC_EMODE) 396#define M_BCM1480_MC_EMODE _SB_MAKEMASK(15, S_BCM1480_MC_EMODE)
397#define V_BCM1480_MC_EMODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_EMODE) 397#define V_BCM1480_MC_EMODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_EMODE)
398#define G_BCM1480_MC_EMODE(x) _SB_GETVALUE(x,S_BCM1480_MC_EMODE,M_BCM1480_MC_EMODE) 398#define G_BCM1480_MC_EMODE(x) _SB_GETVALUE(x, S_BCM1480_MC_EMODE, M_BCM1480_MC_EMODE)
399#define V_BCM1480_MC_EMODE_DEFAULT V_BCM1480_MC_EMODE(0) 399#define V_BCM1480_MC_EMODE_DEFAULT V_BCM1480_MC_EMODE(0)
400 400
401#define S_BCM1480_MC_MODE 16 401#define S_BCM1480_MC_MODE 16
402#define M_BCM1480_MC_MODE _SB_MAKEMASK(15,S_BCM1480_MC_MODE) 402#define M_BCM1480_MC_MODE _SB_MAKEMASK(15, S_BCM1480_MC_MODE)
403#define V_BCM1480_MC_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_MODE) 403#define V_BCM1480_MC_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_MODE)
404#define G_BCM1480_MC_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_MODE,M_BCM1480_MC_MODE) 404#define G_BCM1480_MC_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_MODE, M_BCM1480_MC_MODE)
405#define V_BCM1480_MC_MODE_DEFAULT V_BCM1480_MC_MODE(0) 405#define V_BCM1480_MC_MODE_DEFAULT V_BCM1480_MC_MODE(0)
406 406
407#define S_BCM1480_MC_DRAM_TYPE 32 407#define S_BCM1480_MC_DRAM_TYPE 32
408#define M_BCM1480_MC_DRAM_TYPE _SB_MAKEMASK(4,S_BCM1480_MC_DRAM_TYPE) 408#define M_BCM1480_MC_DRAM_TYPE _SB_MAKEMASK(4, S_BCM1480_MC_DRAM_TYPE)
409#define V_BCM1480_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DRAM_TYPE) 409#define V_BCM1480_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DRAM_TYPE)
410#define G_BCM1480_MC_DRAM_TYPE(x) _SB_GETVALUE(x,S_BCM1480_MC_DRAM_TYPE,M_BCM1480_MC_DRAM_TYPE) 410#define G_BCM1480_MC_DRAM_TYPE(x) _SB_GETVALUE(x, S_BCM1480_MC_DRAM_TYPE, M_BCM1480_MC_DRAM_TYPE)
411 411
412#define K_BCM1480_MC_DRAM_TYPE_JEDEC 0 412#define K_BCM1480_MC_DRAM_TYPE_JEDEC 0
413#define K_BCM1480_MC_DRAM_TYPE_FCRAM 1 413#define K_BCM1480_MC_DRAM_TYPE_FCRAM 1
@@ -431,9 +431,9 @@
431#define M_BCM1480_MC_ECC_DISABLE _SB_MAKEMASK1(39) 431#define M_BCM1480_MC_ECC_DISABLE _SB_MAKEMASK1(39)
432 432
433#define S_BCM1480_MC_PG_POLICY 40 433#define S_BCM1480_MC_PG_POLICY 40
434#define M_BCM1480_MC_PG_POLICY _SB_MAKEMASK(2,S_BCM1480_MC_PG_POLICY) 434#define M_BCM1480_MC_PG_POLICY _SB_MAKEMASK(2, S_BCM1480_MC_PG_POLICY)
435#define V_BCM1480_MC_PG_POLICY(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PG_POLICY) 435#define V_BCM1480_MC_PG_POLICY(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PG_POLICY)
436#define G_BCM1480_MC_PG_POLICY(x) _SB_GETVALUE(x,S_BCM1480_MC_PG_POLICY,M_BCM1480_MC_PG_POLICY) 436#define G_BCM1480_MC_PG_POLICY(x) _SB_GETVALUE(x, S_BCM1480_MC_PG_POLICY, M_BCM1480_MC_PG_POLICY)
437 437
438#define K_BCM1480_MC_PG_POLICY_CLOSED 0 438#define K_BCM1480_MC_PG_POLICY_CLOSED 0
439#define K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK 1 439#define K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK 1
@@ -454,16 +454,16 @@
454 */ 454 */
455 455
456#define S_BCM1480_MC_CLK_RATIO 0 456#define S_BCM1480_MC_CLK_RATIO 0
457#define M_BCM1480_MC_CLK_RATIO _SB_MAKEMASK(6,S_BCM1480_MC_CLK_RATIO) 457#define M_BCM1480_MC_CLK_RATIO _SB_MAKEMASK(6, S_BCM1480_MC_CLK_RATIO)
458#define V_BCM1480_MC_CLK_RATIO(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CLK_RATIO) 458#define V_BCM1480_MC_CLK_RATIO(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CLK_RATIO)
459#define G_BCM1480_MC_CLK_RATIO(x) _SB_GETVALUE(x,S_BCM1480_MC_CLK_RATIO,M_BCM1480_MC_CLK_RATIO) 459#define G_BCM1480_MC_CLK_RATIO(x) _SB_GETVALUE(x, S_BCM1480_MC_CLK_RATIO, M_BCM1480_MC_CLK_RATIO)
460 460
461#define V_BCM1480_MC_CLK_RATIO_DEFAULT V_BCM1480_MC_CLK_RATIO(10) 461#define V_BCM1480_MC_CLK_RATIO_DEFAULT V_BCM1480_MC_CLK_RATIO(10)
462 462
463#define S_BCM1480_MC_REF_RATE 8 463#define S_BCM1480_MC_REF_RATE 8
464#define M_BCM1480_MC_REF_RATE _SB_MAKEMASK(8,S_BCM1480_MC_REF_RATE) 464#define M_BCM1480_MC_REF_RATE _SB_MAKEMASK(8, S_BCM1480_MC_REF_RATE)
465#define V_BCM1480_MC_REF_RATE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_REF_RATE) 465#define V_BCM1480_MC_REF_RATE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_REF_RATE)
466#define G_BCM1480_MC_REF_RATE(x) _SB_GETVALUE(x,S_BCM1480_MC_REF_RATE,M_BCM1480_MC_REF_RATE) 466#define G_BCM1480_MC_REF_RATE(x) _SB_GETVALUE(x, S_BCM1480_MC_REF_RATE, M_BCM1480_MC_REF_RATE)
467 467
468#define K_BCM1480_MC_REF_RATE_100MHz 0x31 468#define K_BCM1480_MC_REF_RATE_100MHz 0x31
469#define K_BCM1480_MC_REF_RATE_200MHz 0x62 469#define K_BCM1480_MC_REF_RATE_200MHz 0x62
@@ -519,20 +519,20 @@
519#define M_BCM1480_MC_CS_ODD_ODT_EN _SB_MAKEMASK1(32) 519#define M_BCM1480_MC_CS_ODD_ODT_EN _SB_MAKEMASK1(32)
520 520
521#define S_BCM1480_MC_ODT0 0 521#define S_BCM1480_MC_ODT0 0
522#define M_BCM1480_MC_ODT0 _SB_MAKEMASK(8,S_BCM1480_MC_ODT0) 522#define M_BCM1480_MC_ODT0 _SB_MAKEMASK(8, S_BCM1480_MC_ODT0)
523#define V_BCM1480_MC_ODT0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT0) 523#define V_BCM1480_MC_ODT0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT0)
524 524
525#define S_BCM1480_MC_ODT2 8 525#define S_BCM1480_MC_ODT2 8
526#define M_BCM1480_MC_ODT2 _SB_MAKEMASK(8,S_BCM1480_MC_ODT2) 526#define M_BCM1480_MC_ODT2 _SB_MAKEMASK(8, S_BCM1480_MC_ODT2)
527#define V_BCM1480_MC_ODT2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT2) 527#define V_BCM1480_MC_ODT2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT2)
528 528
529#define S_BCM1480_MC_ODT4 16 529#define S_BCM1480_MC_ODT4 16
530#define M_BCM1480_MC_ODT4 _SB_MAKEMASK(8,S_BCM1480_MC_ODT4) 530#define M_BCM1480_MC_ODT4 _SB_MAKEMASK(8, S_BCM1480_MC_ODT4)
531#define V_BCM1480_MC_ODT4(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT4) 531#define V_BCM1480_MC_ODT4(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT4)
532 532
533#define S_BCM1480_MC_ODT6 24 533#define S_BCM1480_MC_ODT6 24
534#define M_BCM1480_MC_ODT6 _SB_MAKEMASK(8,S_BCM1480_MC_ODT6) 534#define M_BCM1480_MC_ODT6 _SB_MAKEMASK(8, S_BCM1480_MC_ODT6)
535#define V_BCM1480_MC_ODT6(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ODT6) 535#define V_BCM1480_MC_ODT6(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT6)
536#endif 536#endif
537 537
538/* 538/*
@@ -540,70 +540,70 @@
540 */ 540 */
541 541
542#define S_BCM1480_MC_ADDR_COARSE_ADJ 0 542#define S_BCM1480_MC_ADDR_COARSE_ADJ 0
543#define M_BCM1480_MC_ADDR_COARSE_ADJ _SB_MAKEMASK(6,S_BCM1480_MC_ADDR_COARSE_ADJ) 543#define M_BCM1480_MC_ADDR_COARSE_ADJ _SB_MAKEMASK(6, S_BCM1480_MC_ADDR_COARSE_ADJ)
544#define V_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_COARSE_ADJ) 544#define V_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_COARSE_ADJ)
545#define G_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_ADDR_COARSE_ADJ,M_BCM1480_MC_ADDR_COARSE_ADJ) 545#define G_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_ADDR_COARSE_ADJ, M_BCM1480_MC_ADDR_COARSE_ADJ)
546#define V_BCM1480_MC_ADDR_COARSE_ADJ_DEFAULT V_BCM1480_MC_ADDR_COARSE_ADJ(0x0) 546#define V_BCM1480_MC_ADDR_COARSE_ADJ_DEFAULT V_BCM1480_MC_ADDR_COARSE_ADJ(0x0)
547 547
548#if SIBYTE_HDR_FEATURE(1480, PASS2) 548#if SIBYTE_HDR_FEATURE(1480, PASS2)
549#define S_BCM1480_MC_ADDR_FREQ_RANGE 8 549#define S_BCM1480_MC_ADDR_FREQ_RANGE 8
550#define M_BCM1480_MC_ADDR_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_ADDR_FREQ_RANGE) 550#define M_BCM1480_MC_ADDR_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_ADDR_FREQ_RANGE)
551#define V_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_FREQ_RANGE) 551#define V_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_FREQ_RANGE)
552#define G_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_ADDR_FREQ_RANGE,M_BCM1480_MC_ADDR_FREQ_RANGE) 552#define G_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_ADDR_FREQ_RANGE, M_BCM1480_MC_ADDR_FREQ_RANGE)
553#define V_BCM1480_MC_ADDR_FREQ_RANGE_DEFAULT V_BCM1480_MC_ADDR_FREQ_RANGE(0x4) 553#define V_BCM1480_MC_ADDR_FREQ_RANGE_DEFAULT V_BCM1480_MC_ADDR_FREQ_RANGE(0x4)
554#endif 554#endif
555 555
556#define S_BCM1480_MC_ADDR_FINE_ADJ 8 556#define S_BCM1480_MC_ADDR_FINE_ADJ 8
557#define M_BCM1480_MC_ADDR_FINE_ADJ _SB_MAKEMASK(4,S_BCM1480_MC_ADDR_FINE_ADJ) 557#define M_BCM1480_MC_ADDR_FINE_ADJ _SB_MAKEMASK(4, S_BCM1480_MC_ADDR_FINE_ADJ)
558#define V_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_FINE_ADJ) 558#define V_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_FINE_ADJ)
559#define G_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_ADDR_FINE_ADJ,M_BCM1480_MC_ADDR_FINE_ADJ) 559#define G_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_ADDR_FINE_ADJ, M_BCM1480_MC_ADDR_FINE_ADJ)
560#define V_BCM1480_MC_ADDR_FINE_ADJ_DEFAULT V_BCM1480_MC_ADDR_FINE_ADJ(0x8) 560#define V_BCM1480_MC_ADDR_FINE_ADJ_DEFAULT V_BCM1480_MC_ADDR_FINE_ADJ(0x8)
561 561
562#define S_BCM1480_MC_DQI_COARSE_ADJ 16 562#define S_BCM1480_MC_DQI_COARSE_ADJ 16
563#define M_BCM1480_MC_DQI_COARSE_ADJ _SB_MAKEMASK(6,S_BCM1480_MC_DQI_COARSE_ADJ) 563#define M_BCM1480_MC_DQI_COARSE_ADJ _SB_MAKEMASK(6, S_BCM1480_MC_DQI_COARSE_ADJ)
564#define V_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_COARSE_ADJ) 564#define V_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_COARSE_ADJ)
565#define G_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQI_COARSE_ADJ,M_BCM1480_MC_DQI_COARSE_ADJ) 565#define G_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQI_COARSE_ADJ, M_BCM1480_MC_DQI_COARSE_ADJ)
566#define V_BCM1480_MC_DQI_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQI_COARSE_ADJ(0x0) 566#define V_BCM1480_MC_DQI_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQI_COARSE_ADJ(0x0)
567 567
568#if SIBYTE_HDR_FEATURE(1480, PASS2) 568#if SIBYTE_HDR_FEATURE(1480, PASS2)
569#define S_BCM1480_MC_DQI_FREQ_RANGE 24 569#define S_BCM1480_MC_DQI_FREQ_RANGE 24
570#define M_BCM1480_MC_DQI_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_DQI_FREQ_RANGE) 570#define M_BCM1480_MC_DQI_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_DQI_FREQ_RANGE)
571#define V_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_FREQ_RANGE) 571#define V_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_FREQ_RANGE)
572#define G_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_DQI_FREQ_RANGE,M_BCM1480_MC_DQI_FREQ_RANGE) 572#define G_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_DQI_FREQ_RANGE, M_BCM1480_MC_DQI_FREQ_RANGE)
573#define V_BCM1480_MC_DQI_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQI_FREQ_RANGE(0x4) 573#define V_BCM1480_MC_DQI_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQI_FREQ_RANGE(0x4)
574#endif 574#endif
575 575
576#define S_BCM1480_MC_DQI_FINE_ADJ 24 576#define S_BCM1480_MC_DQI_FINE_ADJ 24
577#define M_BCM1480_MC_DQI_FINE_ADJ _SB_MAKEMASK(4,S_BCM1480_MC_DQI_FINE_ADJ) 577#define M_BCM1480_MC_DQI_FINE_ADJ _SB_MAKEMASK(4, S_BCM1480_MC_DQI_FINE_ADJ)
578#define V_BCM1480_MC_DQI_FINE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_FINE_ADJ) 578#define V_BCM1480_MC_DQI_FINE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_FINE_ADJ)
579#define G_BCM1480_MC_DQI_FINE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQI_FINE_ADJ,M_BCM1480_MC_DQI_FINE_ADJ) 579#define G_BCM1480_MC_DQI_FINE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQI_FINE_ADJ, M_BCM1480_MC_DQI_FINE_ADJ)
580#define V_BCM1480_MC_DQI_FINE_ADJ_DEFAULT V_BCM1480_MC_DQI_FINE_ADJ(0x8) 580#define V_BCM1480_MC_DQI_FINE_ADJ_DEFAULT V_BCM1480_MC_DQI_FINE_ADJ(0x8)
581 581
582#define S_BCM1480_MC_DQO_COARSE_ADJ 32 582#define S_BCM1480_MC_DQO_COARSE_ADJ 32
583#define M_BCM1480_MC_DQO_COARSE_ADJ _SB_MAKEMASK(6,S_BCM1480_MC_DQO_COARSE_ADJ) 583#define M_BCM1480_MC_DQO_COARSE_ADJ _SB_MAKEMASK(6, S_BCM1480_MC_DQO_COARSE_ADJ)
584#define V_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_COARSE_ADJ) 584#define V_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_COARSE_ADJ)
585#define G_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQO_COARSE_ADJ,M_BCM1480_MC_DQO_COARSE_ADJ) 585#define G_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQO_COARSE_ADJ, M_BCM1480_MC_DQO_COARSE_ADJ)
586#define V_BCM1480_MC_DQO_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQO_COARSE_ADJ(0x0) 586#define V_BCM1480_MC_DQO_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQO_COARSE_ADJ(0x0)
587 587
588#if SIBYTE_HDR_FEATURE(1480, PASS2) 588#if SIBYTE_HDR_FEATURE(1480, PASS2)
589#define S_BCM1480_MC_DQO_FREQ_RANGE 40 589#define S_BCM1480_MC_DQO_FREQ_RANGE 40
590#define M_BCM1480_MC_DQO_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_DQO_FREQ_RANGE) 590#define M_BCM1480_MC_DQO_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_DQO_FREQ_RANGE)
591#define V_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_FREQ_RANGE) 591#define V_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_FREQ_RANGE)
592#define G_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_DQO_FREQ_RANGE,M_BCM1480_MC_DQO_FREQ_RANGE) 592#define G_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_DQO_FREQ_RANGE, M_BCM1480_MC_DQO_FREQ_RANGE)
593#define V_BCM1480_MC_DQO_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQO_FREQ_RANGE(0x4) 593#define V_BCM1480_MC_DQO_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQO_FREQ_RANGE(0x4)
594#endif 594#endif
595 595
596#define S_BCM1480_MC_DQO_FINE_ADJ 40 596#define S_BCM1480_MC_DQO_FINE_ADJ 40
597#define M_BCM1480_MC_DQO_FINE_ADJ _SB_MAKEMASK(4,S_BCM1480_MC_DQO_FINE_ADJ) 597#define M_BCM1480_MC_DQO_FINE_ADJ _SB_MAKEMASK(4, S_BCM1480_MC_DQO_FINE_ADJ)
598#define V_BCM1480_MC_DQO_FINE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_FINE_ADJ) 598#define V_BCM1480_MC_DQO_FINE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_FINE_ADJ)
599#define G_BCM1480_MC_DQO_FINE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQO_FINE_ADJ,M_BCM1480_MC_DQO_FINE_ADJ) 599#define G_BCM1480_MC_DQO_FINE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQO_FINE_ADJ, M_BCM1480_MC_DQO_FINE_ADJ)
600#define V_BCM1480_MC_DQO_FINE_ADJ_DEFAULT V_BCM1480_MC_DQO_FINE_ADJ(0x8) 600#define V_BCM1480_MC_DQO_FINE_ADJ_DEFAULT V_BCM1480_MC_DQO_FINE_ADJ(0x8)
601 601
602#if SIBYTE_HDR_FEATURE(1480, PASS2) 602#if SIBYTE_HDR_FEATURE(1480, PASS2)
603#define S_BCM1480_MC_DLL_PDSEL 44 603#define S_BCM1480_MC_DLL_PDSEL 44
604#define M_BCM1480_MC_DLL_PDSEL _SB_MAKEMASK(2,S_BCM1480_MC_DLL_PDSEL) 604#define M_BCM1480_MC_DLL_PDSEL _SB_MAKEMASK(2, S_BCM1480_MC_DLL_PDSEL)
605#define V_BCM1480_MC_DLL_PDSEL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_PDSEL) 605#define V_BCM1480_MC_DLL_PDSEL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_PDSEL)
606#define G_BCM1480_MC_DLL_PDSEL(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_PDSEL,M_BCM1480_MC_DLL_PDSEL) 606#define G_BCM1480_MC_DLL_PDSEL(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_PDSEL, M_BCM1480_MC_DLL_PDSEL)
607#define V_BCM1480_MC_DLL_DEFAULT_PDSEL V_BCM1480_MC_DLL_PDSEL(0x0) 607#define V_BCM1480_MC_DLL_DEFAULT_PDSEL V_BCM1480_MC_DLL_PDSEL(0x0)
608 608
609#define M_BCM1480_MC_DLL_REGBYPASS _SB_MAKEMASK1(46) 609#define M_BCM1480_MC_DLL_REGBYPASS _SB_MAKEMASK1(46)
@@ -611,38 +611,38 @@
611#endif 611#endif
612 612
613#define S_BCM1480_MC_DLL_DEFAULT 48 613#define S_BCM1480_MC_DLL_DEFAULT 48
614#define M_BCM1480_MC_DLL_DEFAULT _SB_MAKEMASK(6,S_BCM1480_MC_DLL_DEFAULT) 614#define M_BCM1480_MC_DLL_DEFAULT _SB_MAKEMASK(6, S_BCM1480_MC_DLL_DEFAULT)
615#define V_BCM1480_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_DEFAULT) 615#define V_BCM1480_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_DEFAULT)
616#define G_BCM1480_MC_DLL_DEFAULT(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_DEFAULT,M_BCM1480_MC_DLL_DEFAULT) 616#define G_BCM1480_MC_DLL_DEFAULT(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_DEFAULT, M_BCM1480_MC_DLL_DEFAULT)
617#define V_BCM1480_MC_DLL_DEFAULT_DEFAULT V_BCM1480_MC_DLL_DEFAULT(0x10) 617#define V_BCM1480_MC_DLL_DEFAULT_DEFAULT V_BCM1480_MC_DLL_DEFAULT(0x10)
618 618
619#if SIBYTE_HDR_FEATURE(1480, PASS2) 619#if SIBYTE_HDR_FEATURE(1480, PASS2)
620#define S_BCM1480_MC_DLL_REGCTRL 54 620#define S_BCM1480_MC_DLL_REGCTRL 54
621#define M_BCM1480_MC_DLL_REGCTRL _SB_MAKEMASK(2,S_BCM1480_MC_DLL_REGCTRL) 621#define M_BCM1480_MC_DLL_REGCTRL _SB_MAKEMASK(2, S_BCM1480_MC_DLL_REGCTRL)
622#define V_BCM1480_MC_DLL_REGCTRL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_REGCTRL) 622#define V_BCM1480_MC_DLL_REGCTRL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_REGCTRL)
623#define G_BCM1480_MC_DLL_REGCTRL(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_REGCTRL,M_BCM1480_MC_DLL_REGCTRL) 623#define G_BCM1480_MC_DLL_REGCTRL(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_REGCTRL, M_BCM1480_MC_DLL_REGCTRL)
624#define V_BCM1480_MC_DLL_DEFAULT_REGCTRL V_BCM1480_MC_DLL_REGCTRL(0x0) 624#define V_BCM1480_MC_DLL_DEFAULT_REGCTRL V_BCM1480_MC_DLL_REGCTRL(0x0)
625#endif 625#endif
626 626
627#if SIBYTE_HDR_FEATURE(1480, PASS2) 627#if SIBYTE_HDR_FEATURE(1480, PASS2)
628#define S_BCM1480_MC_DLL_FREQ_RANGE 56 628#define S_BCM1480_MC_DLL_FREQ_RANGE 56
629#define M_BCM1480_MC_DLL_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_DLL_FREQ_RANGE) 629#define M_BCM1480_MC_DLL_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_DLL_FREQ_RANGE)
630#define V_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_FREQ_RANGE) 630#define V_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_FREQ_RANGE)
631#define G_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_FREQ_RANGE,M_BCM1480_MC_DLL_FREQ_RANGE) 631#define G_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_FREQ_RANGE, M_BCM1480_MC_DLL_FREQ_RANGE)
632#define V_BCM1480_MC_DLL_FREQ_RANGE_DEFAULT V_BCM1480_MC_DLL_FREQ_RANGE(0x4) 632#define V_BCM1480_MC_DLL_FREQ_RANGE_DEFAULT V_BCM1480_MC_DLL_FREQ_RANGE(0x4)
633#endif 633#endif
634 634
635#define S_BCM1480_MC_DLL_STEP_SIZE 56 635#define S_BCM1480_MC_DLL_STEP_SIZE 56
636#define M_BCM1480_MC_DLL_STEP_SIZE _SB_MAKEMASK(4,S_BCM1480_MC_DLL_STEP_SIZE) 636#define M_BCM1480_MC_DLL_STEP_SIZE _SB_MAKEMASK(4, S_BCM1480_MC_DLL_STEP_SIZE)
637#define V_BCM1480_MC_DLL_STEP_SIZE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_STEP_SIZE) 637#define V_BCM1480_MC_DLL_STEP_SIZE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_STEP_SIZE)
638#define G_BCM1480_MC_DLL_STEP_SIZE(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_STEP_SIZE,M_BCM1480_MC_DLL_STEP_SIZE) 638#define G_BCM1480_MC_DLL_STEP_SIZE(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_STEP_SIZE, M_BCM1480_MC_DLL_STEP_SIZE)
639#define V_BCM1480_MC_DLL_STEP_SIZE_DEFAULT V_BCM1480_MC_DLL_STEP_SIZE(0x8) 639#define V_BCM1480_MC_DLL_STEP_SIZE_DEFAULT V_BCM1480_MC_DLL_STEP_SIZE(0x8)
640 640
641#if SIBYTE_HDR_FEATURE(1480, PASS2) 641#if SIBYTE_HDR_FEATURE(1480, PASS2)
642#define S_BCM1480_MC_DLL_BGCTRL 60 642#define S_BCM1480_MC_DLL_BGCTRL 60
643#define M_BCM1480_MC_DLL_BGCTRL _SB_MAKEMASK(2,S_BCM1480_MC_DLL_BGCTRL) 643#define M_BCM1480_MC_DLL_BGCTRL _SB_MAKEMASK(2, S_BCM1480_MC_DLL_BGCTRL)
644#define V_BCM1480_MC_DLL_BGCTRL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_BGCTRL) 644#define V_BCM1480_MC_DLL_BGCTRL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_BGCTRL)
645#define G_BCM1480_MC_DLL_BGCTRL(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_BGCTRL,M_BCM1480_MC_DLL_BGCTRL) 645#define G_BCM1480_MC_DLL_BGCTRL(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_BGCTRL, M_BCM1480_MC_DLL_BGCTRL)
646#define V_BCM1480_MC_DLL_DEFAULT_BGCTRL V_BCM1480_MC_DLL_BGCTRL(0x0) 646#define V_BCM1480_MC_DLL_DEFAULT_BGCTRL V_BCM1480_MC_DLL_BGCTRL(0x0)
647#endif 647#endif
648 648
@@ -653,37 +653,37 @@
653 */ 653 */
654 654
655#define S_BCM1480_MC_RTT_BYP_PULLDOWN 0 655#define S_BCM1480_MC_RTT_BYP_PULLDOWN 0
656#define M_BCM1480_MC_RTT_BYP_PULLDOWN _SB_MAKEMASK(3,S_BCM1480_MC_RTT_BYP_PULLDOWN) 656#define M_BCM1480_MC_RTT_BYP_PULLDOWN _SB_MAKEMASK(3, S_BCM1480_MC_RTT_BYP_PULLDOWN)
657#define V_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_RTT_BYP_PULLDOWN) 657#define V_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_RTT_BYP_PULLDOWN)
658#define G_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_RTT_BYP_PULLDOWN,M_BCM1480_MC_RTT_BYP_PULLDOWN) 658#define G_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_RTT_BYP_PULLDOWN, M_BCM1480_MC_RTT_BYP_PULLDOWN)
659 659
660#define S_BCM1480_MC_RTT_BYP_PULLUP 6 660#define S_BCM1480_MC_RTT_BYP_PULLUP 6
661#define M_BCM1480_MC_RTT_BYP_PULLUP _SB_MAKEMASK(3,S_BCM1480_MC_RTT_BYP_PULLUP) 661#define M_BCM1480_MC_RTT_BYP_PULLUP _SB_MAKEMASK(3, S_BCM1480_MC_RTT_BYP_PULLUP)
662#define V_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_RTT_BYP_PULLUP) 662#define V_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_RTT_BYP_PULLUP)
663#define G_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_GETVALUE(x,S_BCM1480_MC_RTT_BYP_PULLUP,M_BCM1480_MC_RTT_BYP_PULLUP) 663#define G_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_GETVALUE(x, S_BCM1480_MC_RTT_BYP_PULLUP, M_BCM1480_MC_RTT_BYP_PULLUP)
664 664
665#define M_BCM1480_MC_RTT_BYPASS _SB_MAKEMASK1(8) 665#define M_BCM1480_MC_RTT_BYPASS _SB_MAKEMASK1(8)
666#define M_BCM1480_MC_RTT_COMP_MOV_AVG _SB_MAKEMASK1(9) 666#define M_BCM1480_MC_RTT_COMP_MOV_AVG _SB_MAKEMASK1(9)
667 667
668#define S_BCM1480_MC_PVT_BYP_C1_PULLDOWN 10 668#define S_BCM1480_MC_PVT_BYP_C1_PULLDOWN 10
669#define M_BCM1480_MC_PVT_BYP_C1_PULLDOWN _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) 669#define M_BCM1480_MC_PVT_BYP_C1_PULLDOWN _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN)
670#define V_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) 670#define V_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN)
671#define G_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN,M_BCM1480_MC_PVT_BYP_C1_PULLDOWN) 671#define G_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN, M_BCM1480_MC_PVT_BYP_C1_PULLDOWN)
672 672
673#define S_BCM1480_MC_PVT_BYP_C1_PULLUP 15 673#define S_BCM1480_MC_PVT_BYP_C1_PULLUP 15
674#define M_BCM1480_MC_PVT_BYP_C1_PULLUP _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C1_PULLUP) 674#define M_BCM1480_MC_PVT_BYP_C1_PULLUP _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C1_PULLUP)
675#define V_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLUP) 675#define V_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLUP)
676#define G_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLUP,M_BCM1480_MC_PVT_BYP_C1_PULLUP) 676#define G_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLUP, M_BCM1480_MC_PVT_BYP_C1_PULLUP)
677 677
678#define S_BCM1480_MC_PVT_BYP_C2_PULLDOWN 20 678#define S_BCM1480_MC_PVT_BYP_C2_PULLDOWN 20
679#define M_BCM1480_MC_PVT_BYP_C2_PULLDOWN _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN) 679#define M_BCM1480_MC_PVT_BYP_C2_PULLDOWN _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN)
680#define V_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN) 680#define V_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN)
681#define G_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN,M_BCM1480_MC_PVT_BYP_C2_PULLDOWN) 681#define G_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN, M_BCM1480_MC_PVT_BYP_C2_PULLDOWN)
682 682
683#define S_BCM1480_MC_PVT_BYP_C2_PULLUP 25 683#define S_BCM1480_MC_PVT_BYP_C2_PULLUP 25
684#define M_BCM1480_MC_PVT_BYP_C2_PULLUP _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C2_PULLUP) 684#define M_BCM1480_MC_PVT_BYP_C2_PULLUP _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C2_PULLUP)
685#define V_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLUP) 685#define V_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLUP)
686#define G_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLUP,M_BCM1480_MC_PVT_BYP_C2_PULLUP) 686#define G_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLUP, M_BCM1480_MC_PVT_BYP_C2_PULLUP)
687 687
688#define M_BCM1480_MC_PVT_BYPASS _SB_MAKEMASK1(30) 688#define M_BCM1480_MC_PVT_BYPASS _SB_MAKEMASK1(30)
689#define M_BCM1480_MC_PVT_COMP_MOV_AVG _SB_MAKEMASK1(31) 689#define M_BCM1480_MC_PVT_COMP_MOV_AVG _SB_MAKEMASK1(31)
@@ -703,111 +703,111 @@
703 */ 703 */
704 704
705#define S_BCM1480_MC_DATA_INVERT 0 705#define S_BCM1480_MC_DATA_INVERT 0
706#define M_DATA_ECC_INVERT _SB_MAKEMASK(64,S_BCM1480_MC_ECC_INVERT) 706#define M_DATA_ECC_INVERT _SB_MAKEMASK(64, S_BCM1480_MC_ECC_INVERT)
707 707
708/* 708/*
709 * ECC Test ECC Register (Table 96) 709 * ECC Test ECC Register (Table 96)
710 */ 710 */
711 711
712#define S_BCM1480_MC_ECC_INVERT 0 712#define S_BCM1480_MC_ECC_INVERT 0
713#define M_BCM1480_MC_ECC_INVERT _SB_MAKEMASK(8,S_BCM1480_MC_ECC_INVERT) 713#define M_BCM1480_MC_ECC_INVERT _SB_MAKEMASK(8, S_BCM1480_MC_ECC_INVERT)
714 714
715/* 715/*
716 * SDRAM Timing Register (Table 97) 716 * SDRAM Timing Register (Table 97)
717 */ 717 */
718 718
719#define S_BCM1480_MC_tRCD 0 719#define S_BCM1480_MC_tRCD 0
720#define M_BCM1480_MC_tRCD _SB_MAKEMASK(4,S_BCM1480_MC_tRCD) 720#define M_BCM1480_MC_tRCD _SB_MAKEMASK(4, S_BCM1480_MC_tRCD)
721#define V_BCM1480_MC_tRCD(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRCD) 721#define V_BCM1480_MC_tRCD(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRCD)
722#define G_BCM1480_MC_tRCD(x) _SB_GETVALUE(x,S_BCM1480_MC_tRCD,M_BCM1480_MC_tRCD) 722#define G_BCM1480_MC_tRCD(x) _SB_GETVALUE(x, S_BCM1480_MC_tRCD, M_BCM1480_MC_tRCD)
723#define K_BCM1480_MC_tRCD_DEFAULT 3 723#define K_BCM1480_MC_tRCD_DEFAULT 3
724#define V_BCM1480_MC_tRCD_DEFAULT V_BCM1480_MC_tRCD(K_BCM1480_MC_tRCD_DEFAULT) 724#define V_BCM1480_MC_tRCD_DEFAULT V_BCM1480_MC_tRCD(K_BCM1480_MC_tRCD_DEFAULT)
725 725
726#define S_BCM1480_MC_tCL 4 726#define S_BCM1480_MC_tCL 4
727#define M_BCM1480_MC_tCL _SB_MAKEMASK(4,S_BCM1480_MC_tCL) 727#define M_BCM1480_MC_tCL _SB_MAKEMASK(4, S_BCM1480_MC_tCL)
728#define V_BCM1480_MC_tCL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tCL) 728#define V_BCM1480_MC_tCL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tCL)
729#define G_BCM1480_MC_tCL(x) _SB_GETVALUE(x,S_BCM1480_MC_tCL,M_BCM1480_MC_tCL) 729#define G_BCM1480_MC_tCL(x) _SB_GETVALUE(x, S_BCM1480_MC_tCL, M_BCM1480_MC_tCL)
730#define K_BCM1480_MC_tCL_DEFAULT 2 730#define K_BCM1480_MC_tCL_DEFAULT 2
731#define V_BCM1480_MC_tCL_DEFAULT V_BCM1480_MC_tCL(K_BCM1480_MC_tCL_DEFAULT) 731#define V_BCM1480_MC_tCL_DEFAULT V_BCM1480_MC_tCL(K_BCM1480_MC_tCL_DEFAULT)
732 732
733#define M_BCM1480_MC_tCrDh _SB_MAKEMASK1(8) 733#define M_BCM1480_MC_tCrDh _SB_MAKEMASK1(8)
734 734
735#define S_BCM1480_MC_tWR 9 735#define S_BCM1480_MC_tWR 9
736#define M_BCM1480_MC_tWR _SB_MAKEMASK(3,S_BCM1480_MC_tWR) 736#define M_BCM1480_MC_tWR _SB_MAKEMASK(3, S_BCM1480_MC_tWR)
737#define V_BCM1480_MC_tWR(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tWR) 737#define V_BCM1480_MC_tWR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tWR)
738#define G_BCM1480_MC_tWR(x) _SB_GETVALUE(x,S_BCM1480_MC_tWR,M_BCM1480_MC_tWR) 738#define G_BCM1480_MC_tWR(x) _SB_GETVALUE(x, S_BCM1480_MC_tWR, M_BCM1480_MC_tWR)
739#define K_BCM1480_MC_tWR_DEFAULT 2 739#define K_BCM1480_MC_tWR_DEFAULT 2
740#define V_BCM1480_MC_tWR_DEFAULT V_BCM1480_MC_tWR(K_BCM1480_MC_tWR_DEFAULT) 740#define V_BCM1480_MC_tWR_DEFAULT V_BCM1480_MC_tWR(K_BCM1480_MC_tWR_DEFAULT)
741 741
742#define S_BCM1480_MC_tCwD 12 742#define S_BCM1480_MC_tCwD 12
743#define M_BCM1480_MC_tCwD _SB_MAKEMASK(4,S_BCM1480_MC_tCwD) 743#define M_BCM1480_MC_tCwD _SB_MAKEMASK(4, S_BCM1480_MC_tCwD)
744#define V_BCM1480_MC_tCwD(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tCwD) 744#define V_BCM1480_MC_tCwD(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tCwD)
745#define G_BCM1480_MC_tCwD(x) _SB_GETVALUE(x,S_BCM1480_MC_tCwD,M_BCM1480_MC_tCwD) 745#define G_BCM1480_MC_tCwD(x) _SB_GETVALUE(x, S_BCM1480_MC_tCwD, M_BCM1480_MC_tCwD)
746#define K_BCM1480_MC_tCwD_DEFAULT 1 746#define K_BCM1480_MC_tCwD_DEFAULT 1
747#define V_BCM1480_MC_tCwD_DEFAULT V_BCM1480_MC_tCwD(K_BCM1480_MC_tCwD_DEFAULT) 747#define V_BCM1480_MC_tCwD_DEFAULT V_BCM1480_MC_tCwD(K_BCM1480_MC_tCwD_DEFAULT)
748 748
749#define S_BCM1480_MC_tRP 16 749#define S_BCM1480_MC_tRP 16
750#define M_BCM1480_MC_tRP _SB_MAKEMASK(4,S_BCM1480_MC_tRP) 750#define M_BCM1480_MC_tRP _SB_MAKEMASK(4, S_BCM1480_MC_tRP)
751#define V_BCM1480_MC_tRP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRP) 751#define V_BCM1480_MC_tRP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRP)
752#define G_BCM1480_MC_tRP(x) _SB_GETVALUE(x,S_BCM1480_MC_tRP,M_BCM1480_MC_tRP) 752#define G_BCM1480_MC_tRP(x) _SB_GETVALUE(x, S_BCM1480_MC_tRP, M_BCM1480_MC_tRP)
753#define K_BCM1480_MC_tRP_DEFAULT 4 753#define K_BCM1480_MC_tRP_DEFAULT 4
754#define V_BCM1480_MC_tRP_DEFAULT V_BCM1480_MC_tRP(K_BCM1480_MC_tRP_DEFAULT) 754#define V_BCM1480_MC_tRP_DEFAULT V_BCM1480_MC_tRP(K_BCM1480_MC_tRP_DEFAULT)
755 755
756#define S_BCM1480_MC_tRRD 20 756#define S_BCM1480_MC_tRRD 20
757#define M_BCM1480_MC_tRRD _SB_MAKEMASK(4,S_BCM1480_MC_tRRD) 757#define M_BCM1480_MC_tRRD _SB_MAKEMASK(4, S_BCM1480_MC_tRRD)
758#define V_BCM1480_MC_tRRD(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRRD) 758#define V_BCM1480_MC_tRRD(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRRD)
759#define G_BCM1480_MC_tRRD(x) _SB_GETVALUE(x,S_BCM1480_MC_tRRD,M_BCM1480_MC_tRRD) 759#define G_BCM1480_MC_tRRD(x) _SB_GETVALUE(x, S_BCM1480_MC_tRRD, M_BCM1480_MC_tRRD)
760#define K_BCM1480_MC_tRRD_DEFAULT 2 760#define K_BCM1480_MC_tRRD_DEFAULT 2
761#define V_BCM1480_MC_tRRD_DEFAULT V_BCM1480_MC_tRRD(K_BCM1480_MC_tRRD_DEFAULT) 761#define V_BCM1480_MC_tRRD_DEFAULT V_BCM1480_MC_tRRD(K_BCM1480_MC_tRRD_DEFAULT)
762 762
763#define S_BCM1480_MC_tRCw 24 763#define S_BCM1480_MC_tRCw 24
764#define M_BCM1480_MC_tRCw _SB_MAKEMASK(5,S_BCM1480_MC_tRCw) 764#define M_BCM1480_MC_tRCw _SB_MAKEMASK(5, S_BCM1480_MC_tRCw)
765#define V_BCM1480_MC_tRCw(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRCw) 765#define V_BCM1480_MC_tRCw(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRCw)
766#define G_BCM1480_MC_tRCw(x) _SB_GETVALUE(x,S_BCM1480_MC_tRCw,M_BCM1480_MC_tRCw) 766#define G_BCM1480_MC_tRCw(x) _SB_GETVALUE(x, S_BCM1480_MC_tRCw, M_BCM1480_MC_tRCw)
767#define K_BCM1480_MC_tRCw_DEFAULT 10 767#define K_BCM1480_MC_tRCw_DEFAULT 10
768#define V_BCM1480_MC_tRCw_DEFAULT V_BCM1480_MC_tRCw(K_BCM1480_MC_tRCw_DEFAULT) 768#define V_BCM1480_MC_tRCw_DEFAULT V_BCM1480_MC_tRCw(K_BCM1480_MC_tRCw_DEFAULT)
769 769
770#define S_BCM1480_MC_tRCr 32 770#define S_BCM1480_MC_tRCr 32
771#define M_BCM1480_MC_tRCr _SB_MAKEMASK(5,S_BCM1480_MC_tRCr) 771#define M_BCM1480_MC_tRCr _SB_MAKEMASK(5, S_BCM1480_MC_tRCr)
772#define V_BCM1480_MC_tRCr(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRCr) 772#define V_BCM1480_MC_tRCr(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRCr)
773#define G_BCM1480_MC_tRCr(x) _SB_GETVALUE(x,S_BCM1480_MC_tRCr,M_BCM1480_MC_tRCr) 773#define G_BCM1480_MC_tRCr(x) _SB_GETVALUE(x, S_BCM1480_MC_tRCr, M_BCM1480_MC_tRCr)
774#define K_BCM1480_MC_tRCr_DEFAULT 9 774#define K_BCM1480_MC_tRCr_DEFAULT 9
775#define V_BCM1480_MC_tRCr_DEFAULT V_BCM1480_MC_tRCr(K_BCM1480_MC_tRCr_DEFAULT) 775#define V_BCM1480_MC_tRCr_DEFAULT V_BCM1480_MC_tRCr(K_BCM1480_MC_tRCr_DEFAULT)
776 776
777#if SIBYTE_HDR_FEATURE(1480, PASS2) 777#if SIBYTE_HDR_FEATURE(1480, PASS2)
778#define S_BCM1480_MC_tFAW 40 778#define S_BCM1480_MC_tFAW 40
779#define M_BCM1480_MC_tFAW _SB_MAKEMASK(6,S_BCM1480_MC_tFAW) 779#define M_BCM1480_MC_tFAW _SB_MAKEMASK(6, S_BCM1480_MC_tFAW)
780#define V_BCM1480_MC_tFAW(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tFAW) 780#define V_BCM1480_MC_tFAW(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tFAW)
781#define G_BCM1480_MC_tFAW(x) _SB_GETVALUE(x,S_BCM1480_MC_tFAW,M_BCM1480_MC_tFAW) 781#define G_BCM1480_MC_tFAW(x) _SB_GETVALUE(x, S_BCM1480_MC_tFAW, M_BCM1480_MC_tFAW)
782#define K_BCM1480_MC_tFAW_DEFAULT 0 782#define K_BCM1480_MC_tFAW_DEFAULT 0
783#define V_BCM1480_MC_tFAW_DEFAULT V_BCM1480_MC_tFAW(K_BCM1480_MC_tFAW_DEFAULT) 783#define V_BCM1480_MC_tFAW_DEFAULT V_BCM1480_MC_tFAW(K_BCM1480_MC_tFAW_DEFAULT)
784#endif 784#endif
785 785
786#define S_BCM1480_MC_tRFC 48 786#define S_BCM1480_MC_tRFC 48
787#define M_BCM1480_MC_tRFC _SB_MAKEMASK(7,S_BCM1480_MC_tRFC) 787#define M_BCM1480_MC_tRFC _SB_MAKEMASK(7, S_BCM1480_MC_tRFC)
788#define V_BCM1480_MC_tRFC(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRFC) 788#define V_BCM1480_MC_tRFC(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRFC)
789#define G_BCM1480_MC_tRFC(x) _SB_GETVALUE(x,S_BCM1480_MC_tRFC,M_BCM1480_MC_tRFC) 789#define G_BCM1480_MC_tRFC(x) _SB_GETVALUE(x, S_BCM1480_MC_tRFC, M_BCM1480_MC_tRFC)
790#define K_BCM1480_MC_tRFC_DEFAULT 12 790#define K_BCM1480_MC_tRFC_DEFAULT 12
791#define V_BCM1480_MC_tRFC_DEFAULT V_BCM1480_MC_tRFC(K_BCM1480_MC_tRFC_DEFAULT) 791#define V_BCM1480_MC_tRFC_DEFAULT V_BCM1480_MC_tRFC(K_BCM1480_MC_tRFC_DEFAULT)
792 792
793#define S_BCM1480_MC_tFIFO 56 793#define S_BCM1480_MC_tFIFO 56
794#define M_BCM1480_MC_tFIFO _SB_MAKEMASK(2,S_BCM1480_MC_tFIFO) 794#define M_BCM1480_MC_tFIFO _SB_MAKEMASK(2, S_BCM1480_MC_tFIFO)
795#define V_BCM1480_MC_tFIFO(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tFIFO) 795#define V_BCM1480_MC_tFIFO(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tFIFO)
796#define G_BCM1480_MC_tFIFO(x) _SB_GETVALUE(x,S_BCM1480_MC_tFIFO,M_BCM1480_MC_tFIFO) 796#define G_BCM1480_MC_tFIFO(x) _SB_GETVALUE(x, S_BCM1480_MC_tFIFO, M_BCM1480_MC_tFIFO)
797#define K_BCM1480_MC_tFIFO_DEFAULT 0 797#define K_BCM1480_MC_tFIFO_DEFAULT 0
798#define V_BCM1480_MC_tFIFO_DEFAULT V_BCM1480_MC_tFIFO(K_BCM1480_MC_tFIFO_DEFAULT) 798#define V_BCM1480_MC_tFIFO_DEFAULT V_BCM1480_MC_tFIFO(K_BCM1480_MC_tFIFO_DEFAULT)
799 799
800#define S_BCM1480_MC_tW2R 58 800#define S_BCM1480_MC_tW2R 58
801#define M_BCM1480_MC_tW2R _SB_MAKEMASK(2,S_BCM1480_MC_tW2R) 801#define M_BCM1480_MC_tW2R _SB_MAKEMASK(2, S_BCM1480_MC_tW2R)
802#define V_BCM1480_MC_tW2R(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tW2R) 802#define V_BCM1480_MC_tW2R(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tW2R)
803#define G_BCM1480_MC_tW2R(x) _SB_GETVALUE(x,S_BCM1480_MC_tW2R,M_BCM1480_MC_tW2R) 803#define G_BCM1480_MC_tW2R(x) _SB_GETVALUE(x, S_BCM1480_MC_tW2R, M_BCM1480_MC_tW2R)
804#define K_BCM1480_MC_tW2R_DEFAULT 1 804#define K_BCM1480_MC_tW2R_DEFAULT 1
805#define V_BCM1480_MC_tW2R_DEFAULT V_BCM1480_MC_tW2R(K_BCM1480_MC_tW2R_DEFAULT) 805#define V_BCM1480_MC_tW2R_DEFAULT V_BCM1480_MC_tW2R(K_BCM1480_MC_tW2R_DEFAULT)
806 806
807#define S_BCM1480_MC_tR2W 60 807#define S_BCM1480_MC_tR2W 60
808#define M_BCM1480_MC_tR2W _SB_MAKEMASK(2,S_BCM1480_MC_tR2W) 808#define M_BCM1480_MC_tR2W _SB_MAKEMASK(2, S_BCM1480_MC_tR2W)
809#define V_BCM1480_MC_tR2W(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tR2W) 809#define V_BCM1480_MC_tR2W(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tR2W)
810#define G_BCM1480_MC_tR2W(x) _SB_GETVALUE(x,S_BCM1480_MC_tR2W,M_BCM1480_MC_tR2W) 810#define G_BCM1480_MC_tR2W(x) _SB_GETVALUE(x, S_BCM1480_MC_tR2W, M_BCM1480_MC_tR2W)
811#define K_BCM1480_MC_tR2W_DEFAULT 0 811#define K_BCM1480_MC_tR2W_DEFAULT 0
812#define V_BCM1480_MC_tR2W_DEFAULT V_BCM1480_MC_tR2W(K_BCM1480_MC_tR2W_DEFAULT) 812#define V_BCM1480_MC_tR2W_DEFAULT V_BCM1480_MC_tR2W(K_BCM1480_MC_tR2W_DEFAULT)
813 813
@@ -835,30 +835,30 @@
835#if SIBYTE_HDR_FEATURE(1480, PASS2) 835#if SIBYTE_HDR_FEATURE(1480, PASS2)
836 836
837#define S_BCM1480_MC_tAL 0 837#define S_BCM1480_MC_tAL 0
838#define M_BCM1480_MC_tAL _SB_MAKEMASK(4,S_BCM1480_MC_tAL) 838#define M_BCM1480_MC_tAL _SB_MAKEMASK(4, S_BCM1480_MC_tAL)
839#define V_BCM1480_MC_tAL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tAL) 839#define V_BCM1480_MC_tAL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tAL)
840#define G_BCM1480_MC_tAL(x) _SB_GETVALUE(x,S_BCM1480_MC_tAL,M_BCM1480_MC_tAL) 840#define G_BCM1480_MC_tAL(x) _SB_GETVALUE(x, S_BCM1480_MC_tAL, M_BCM1480_MC_tAL)
841#define K_BCM1480_MC_tAL_DEFAULT 0 841#define K_BCM1480_MC_tAL_DEFAULT 0
842#define V_BCM1480_MC_tAL_DEFAULT V_BCM1480_MC_tAL(K_BCM1480_MC_tAL_DEFAULT) 842#define V_BCM1480_MC_tAL_DEFAULT V_BCM1480_MC_tAL(K_BCM1480_MC_tAL_DEFAULT)
843 843
844#define S_BCM1480_MC_tRTP 4 844#define S_BCM1480_MC_tRTP 4
845#define M_BCM1480_MC_tRTP _SB_MAKEMASK(3,S_BCM1480_MC_tRTP) 845#define M_BCM1480_MC_tRTP _SB_MAKEMASK(3, S_BCM1480_MC_tRTP)
846#define V_BCM1480_MC_tRTP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRTP) 846#define V_BCM1480_MC_tRTP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRTP)
847#define G_BCM1480_MC_tRTP(x) _SB_GETVALUE(x,S_BCM1480_MC_tRTP,M_BCM1480_MC_tRTP) 847#define G_BCM1480_MC_tRTP(x) _SB_GETVALUE(x, S_BCM1480_MC_tRTP, M_BCM1480_MC_tRTP)
848#define K_BCM1480_MC_tRTP_DEFAULT 2 848#define K_BCM1480_MC_tRTP_DEFAULT 2
849#define V_BCM1480_MC_tRTP_DEFAULT V_BCM1480_MC_tRTP(K_BCM1480_MC_tRTP_DEFAULT) 849#define V_BCM1480_MC_tRTP_DEFAULT V_BCM1480_MC_tRTP(K_BCM1480_MC_tRTP_DEFAULT)
850 850
851#define S_BCM1480_MC_tW2W 8 851#define S_BCM1480_MC_tW2W 8
852#define M_BCM1480_MC_tW2W _SB_MAKEMASK(2,S_BCM1480_MC_tW2W) 852#define M_BCM1480_MC_tW2W _SB_MAKEMASK(2, S_BCM1480_MC_tW2W)
853#define V_BCM1480_MC_tW2W(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tW2W) 853#define V_BCM1480_MC_tW2W(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tW2W)
854#define G_BCM1480_MC_tW2W(x) _SB_GETVALUE(x,S_BCM1480_MC_tW2W,M_BCM1480_MC_tW2W) 854#define G_BCM1480_MC_tW2W(x) _SB_GETVALUE(x, S_BCM1480_MC_tW2W, M_BCM1480_MC_tW2W)
855#define K_BCM1480_MC_tW2W_DEFAULT 0 855#define K_BCM1480_MC_tW2W_DEFAULT 0
856#define V_BCM1480_MC_tW2W_DEFAULT V_BCM1480_MC_tW2W(K_BCM1480_MC_tW2W_DEFAULT) 856#define V_BCM1480_MC_tW2W_DEFAULT V_BCM1480_MC_tW2W(K_BCM1480_MC_tW2W_DEFAULT)
857 857
858#define S_BCM1480_MC_tRAP 12 858#define S_BCM1480_MC_tRAP 12
859#define M_BCM1480_MC_tRAP _SB_MAKEMASK(4,S_BCM1480_MC_tRAP) 859#define M_BCM1480_MC_tRAP _SB_MAKEMASK(4, S_BCM1480_MC_tRAP)
860#define V_BCM1480_MC_tRAP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRAP) 860#define V_BCM1480_MC_tRAP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRAP)
861#define G_BCM1480_MC_tRAP(x) _SB_GETVALUE(x,S_BCM1480_MC_tRAP,M_BCM1480_MC_tRAP) 861#define G_BCM1480_MC_tRAP(x) _SB_GETVALUE(x, S_BCM1480_MC_tRAP, M_BCM1480_MC_tRAP)
862#define K_BCM1480_MC_tRAP_DEFAULT 0 862#define K_BCM1480_MC_tRAP_DEFAULT 0
863#define V_BCM1480_MC_tRAP_DEFAULT V_BCM1480_MC_tRAP(K_BCM1480_MC_tRAP_DEFAULT) 863#define V_BCM1480_MC_tRAP_DEFAULT V_BCM1480_MC_tRAP(K_BCM1480_MC_tRAP_DEFAULT)
864 864
@@ -875,30 +875,30 @@
875 */ 875 */
876 876
877#define S_BCM1480_MC_BLK_SET_MARK 8 877#define S_BCM1480_MC_BLK_SET_MARK 8
878#define M_BCM1480_MC_BLK_SET_MARK _SB_MAKEMASK(4,S_BCM1480_MC_BLK_SET_MARK) 878#define M_BCM1480_MC_BLK_SET_MARK _SB_MAKEMASK(4, S_BCM1480_MC_BLK_SET_MARK)
879#define V_BCM1480_MC_BLK_SET_MARK(x) _SB_MAKEVALUE(x,S_BCM1480_MC_BLK_SET_MARK) 879#define V_BCM1480_MC_BLK_SET_MARK(x) _SB_MAKEVALUE(x, S_BCM1480_MC_BLK_SET_MARK)
880#define G_BCM1480_MC_BLK_SET_MARK(x) _SB_GETVALUE(x,S_BCM1480_MC_BLK_SET_MARK,M_BCM1480_MC_BLK_SET_MARK) 880#define G_BCM1480_MC_BLK_SET_MARK(x) _SB_GETVALUE(x, S_BCM1480_MC_BLK_SET_MARK, M_BCM1480_MC_BLK_SET_MARK)
881 881
882#define S_BCM1480_MC_BLK_CLR_MARK 12 882#define S_BCM1480_MC_BLK_CLR_MARK 12
883#define M_BCM1480_MC_BLK_CLR_MARK _SB_MAKEMASK(4,S_BCM1480_MC_BLK_CLR_MARK) 883#define M_BCM1480_MC_BLK_CLR_MARK _SB_MAKEMASK(4, S_BCM1480_MC_BLK_CLR_MARK)
884#define V_BCM1480_MC_BLK_CLR_MARK(x) _SB_MAKEVALUE(x,S_BCM1480_MC_BLK_CLR_MARK) 884#define V_BCM1480_MC_BLK_CLR_MARK(x) _SB_MAKEVALUE(x, S_BCM1480_MC_BLK_CLR_MARK)
885#define G_BCM1480_MC_BLK_CLR_MARK(x) _SB_GETVALUE(x,S_BCM1480_MC_BLK_CLR_MARK,M_BCM1480_MC_BLK_CLR_MARK) 885#define G_BCM1480_MC_BLK_CLR_MARK(x) _SB_GETVALUE(x, S_BCM1480_MC_BLK_CLR_MARK, M_BCM1480_MC_BLK_CLR_MARK)
886 886
887#define M_BCM1480_MC_PKT_PRIORITY _SB_MAKEMASK1(16) 887#define M_BCM1480_MC_PKT_PRIORITY _SB_MAKEMASK1(16)
888 888
889#define S_BCM1480_MC_MAX_AGE 20 889#define S_BCM1480_MC_MAX_AGE 20
890#define M_BCM1480_MC_MAX_AGE _SB_MAKEMASK(4,S_BCM1480_MC_MAX_AGE) 890#define M_BCM1480_MC_MAX_AGE _SB_MAKEMASK(4, S_BCM1480_MC_MAX_AGE)
891#define V_BCM1480_MC_MAX_AGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_MAX_AGE) 891#define V_BCM1480_MC_MAX_AGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_MAX_AGE)
892#define G_BCM1480_MC_MAX_AGE(x) _SB_GETVALUE(x,S_BCM1480_MC_MAX_AGE,M_BCM1480_MC_MAX_AGE) 892#define G_BCM1480_MC_MAX_AGE(x) _SB_GETVALUE(x, S_BCM1480_MC_MAX_AGE, M_BCM1480_MC_MAX_AGE)
893 893
894#define M_BCM1480_MC_BERR_DISABLE _SB_MAKEMASK1(29) 894#define M_BCM1480_MC_BERR_DISABLE _SB_MAKEMASK1(29)
895#define M_BCM1480_MC_FORCE_SEQ _SB_MAKEMASK1(30) 895#define M_BCM1480_MC_FORCE_SEQ _SB_MAKEMASK1(30)
896#define M_BCM1480_MC_VGEN _SB_MAKEMASK1(32) 896#define M_BCM1480_MC_VGEN _SB_MAKEMASK1(32)
897 897
898#define S_BCM1480_MC_SLEW 33 898#define S_BCM1480_MC_SLEW 33
899#define M_BCM1480_MC_SLEW _SB_MAKEMASK(2,S_BCM1480_MC_SLEW) 899#define M_BCM1480_MC_SLEW _SB_MAKEMASK(2, S_BCM1480_MC_SLEW)
900#define V_BCM1480_MC_SLEW(x) _SB_MAKEVALUE(x,S_BCM1480_MC_SLEW) 900#define V_BCM1480_MC_SLEW(x) _SB_MAKEVALUE(x, S_BCM1480_MC_SLEW)
901#define G_BCM1480_MC_SLEW(x) _SB_GETVALUE(x,S_BCM1480_MC_SLEW,M_BCM1480_MC_SLEW) 901#define G_BCM1480_MC_SLEW(x) _SB_GETVALUE(x, S_BCM1480_MC_SLEW, M_BCM1480_MC_SLEW)
902 902
903#define M_BCM1480_MC_SSTL_VOLTAGE _SB_MAKEMASK1(35) 903#define M_BCM1480_MC_SSTL_VOLTAGE _SB_MAKEMASK1(35)
904 904
@@ -907,19 +907,19 @@
907 */ 907 */
908 908
909#define S_BCM1480_MC_INTLV0 0 909#define S_BCM1480_MC_INTLV0 0
910#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV0) 910#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV0)
911#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV0) 911#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0)
912#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV0,M_BCM1480_MC_INTLV0) 912#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0)
913 913
914#define S_BCM1480_MC_INTLV1 8 914#define S_BCM1480_MC_INTLV1 8
915#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV1) 915#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV1)
916#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV1) 916#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1)
917#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV1,M_BCM1480_MC_INTLV1) 917#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1)
918 918
919#define S_BCM1480_MC_INTLV_MODE 16 919#define S_BCM1480_MC_INTLV_MODE 16
920#define M_BCM1480_MC_INTLV_MODE _SB_MAKEMASK(3,S_BCM1480_MC_INTLV_MODE) 920#define M_BCM1480_MC_INTLV_MODE _SB_MAKEMASK(3, S_BCM1480_MC_INTLV_MODE)
921#define V_BCM1480_MC_INTLV_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV_MODE) 921#define V_BCM1480_MC_INTLV_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV_MODE)
922#define G_BCM1480_MC_INTLV_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV_MODE,M_BCM1480_MC_INTLV_MODE) 922#define G_BCM1480_MC_INTLV_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV_MODE, M_BCM1480_MC_INTLV_MODE)
923 923
924#define K_BCM1480_MC_INTLV_MODE_NONE 0x0 924#define K_BCM1480_MC_INTLV_MODE_NONE 0x0
925#define K_BCM1480_MC_INTLV_MODE_01 0x1 925#define K_BCM1480_MC_INTLV_MODE_01 0x1
@@ -938,9 +938,9 @@
938 */ 938 */
939 939
940#define S_BCM1480_MC_ECC_ERR_ADDR 0 940#define S_BCM1480_MC_ECC_ERR_ADDR 0
941#define M_BCM1480_MC_ECC_ERR_ADDR _SB_MAKEMASK(37,S_BCM1480_MC_ECC_ERR_ADDR) 941#define M_BCM1480_MC_ECC_ERR_ADDR _SB_MAKEMASK(37, S_BCM1480_MC_ECC_ERR_ADDR)
942#define V_BCM1480_MC_ECC_ERR_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_ERR_ADDR) 942#define V_BCM1480_MC_ECC_ERR_ADDR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_ERR_ADDR)
943#define G_BCM1480_MC_ECC_ERR_ADDR(x) _SB_GETVALUE(x,S_BCM1480_MC_ECC_ERR_ADDR,M_BCM1480_MC_ECC_ERR_ADDR) 943#define G_BCM1480_MC_ECC_ERR_ADDR(x) _SB_GETVALUE(x, S_BCM1480_MC_ECC_ERR_ADDR, M_BCM1480_MC_ECC_ERR_ADDR)
944 944
945#if SIBYTE_HDR_FEATURE(1480, PASS2) 945#if SIBYTE_HDR_FEATURE(1480, PASS2)
946#define M_BCM1480_MC_ECC_ERR_RMW _SB_MAKEMASK1(60) 946#define M_BCM1480_MC_ECC_ERR_RMW _SB_MAKEMASK1(60)
@@ -955,27 +955,27 @@
955 */ 955 */
956 956
957#define S_BCM1480_MC_ECC_CORR_ADDR 0 957#define S_BCM1480_MC_ECC_CORR_ADDR 0
958#define M_BCM1480_MC_ECC_CORR_ADDR _SB_MAKEMASK(37,S_BCM1480_MC_ECC_CORR_ADDR) 958#define M_BCM1480_MC_ECC_CORR_ADDR _SB_MAKEMASK(37, S_BCM1480_MC_ECC_CORR_ADDR)
959#define V_BCM1480_MC_ECC_CORR_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_CORR_ADDR) 959#define V_BCM1480_MC_ECC_CORR_ADDR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_CORR_ADDR)
960#define G_BCM1480_MC_ECC_CORR_ADDR(x) _SB_GETVALUE(x,S_BCM1480_MC_ECC_CORR_ADDR,M_BCM1480_MC_ECC_CORR_ADDR) 960#define G_BCM1480_MC_ECC_CORR_ADDR(x) _SB_GETVALUE(x, S_BCM1480_MC_ECC_CORR_ADDR, M_BCM1480_MC_ECC_CORR_ADDR)
961 961
962/* 962/*
963 * Global ECC Correction Register (Table 103) 963 * Global ECC Correction Register (Table 103)
964 */ 964 */
965 965
966#define S_BCM1480_MC_ECC_CORRECT 0 966#define S_BCM1480_MC_ECC_CORRECT 0
967#define M_BCM1480_MC_ECC_CORRECT _SB_MAKEMASK(64,S_BCM1480_MC_ECC_CORRECT) 967#define M_BCM1480_MC_ECC_CORRECT _SB_MAKEMASK(64, S_BCM1480_MC_ECC_CORRECT)
968#define V_BCM1480_MC_ECC_CORRECT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_CORRECT) 968#define V_BCM1480_MC_ECC_CORRECT(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_CORRECT)
969#define G_BCM1480_MC_ECC_CORRECT(x) _SB_GETVALUE(x,S_BCM1480_MC_ECC_CORRECT,M_BCM1480_MC_ECC_CORRECT) 969#define G_BCM1480_MC_ECC_CORRECT(x) _SB_GETVALUE(x, S_BCM1480_MC_ECC_CORRECT, M_BCM1480_MC_ECC_CORRECT)
970 970
971/* 971/*
972 * Global ECC Performance Counters Control Register (Table 104) 972 * Global ECC Performance Counters Control Register (Table 104)
973 */ 973 */
974 974
975#define S_BCM1480_MC_CHANNEL_SELECT 0 975#define S_BCM1480_MC_CHANNEL_SELECT 0
976#define M_BCM1480_MC_CHANNEL_SELECT _SB_MAKEMASK(4,S_BCM1480_MC_CHANNEL_SELECT) 976#define M_BCM1480_MC_CHANNEL_SELECT _SB_MAKEMASK(4, S_BCM1480_MC_CHANNEL_SELECT)
977#define V_BCM1480_MC_CHANNEL_SELECT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CHANNEL_SELECT) 977#define V_BCM1480_MC_CHANNEL_SELECT(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CHANNEL_SELECT)
978#define G_BCM1480_MC_CHANNEL_SELECT(x) _SB_GETVALUE(x,S_BCM1480_MC_CHANNEL_SELECT,M_BCM1480_MC_CHANNEL_SELECT) 978#define G_BCM1480_MC_CHANNEL_SELECT(x) _SB_GETVALUE(x, S_BCM1480_MC_CHANNEL_SELECT, M_BCM1480_MC_CHANNEL_SELECT)
979#define K_BCM1480_MC_CHANNEL_SELECT_0 0x1 979#define K_BCM1480_MC_CHANNEL_SELECT_0 0x1
980#define K_BCM1480_MC_CHANNEL_SELECT_1 0x2 980#define K_BCM1480_MC_CHANNEL_SELECT_1 0x2
981#define K_BCM1480_MC_CHANNEL_SELECT_2 0x4 981#define K_BCM1480_MC_CHANNEL_SELECT_2 0x4
diff --git a/include/asm-mips/sibyte/bcm1480_regs.h b/include/asm-mips/sibyte/bcm1480_regs.h
index c34d36b6b8c2..b4077bb72611 100644
--- a/include/asm-mips/sibyte/bcm1480_regs.h
+++ b/include/asm-mips/sibyte/bcm1480_regs.h
@@ -87,7 +87,7 @@
87#define BCM1480_MC_REGISTER_SPACING 0x1000 87#define BCM1480_MC_REGISTER_SPACING 0x1000
88 88
89#define A_BCM1480_MC_BASE(ctlid) (A_BCM1480_MC_BASE_0+(ctlid)*BCM1480_MC_REGISTER_SPACING) 89#define A_BCM1480_MC_BASE(ctlid) (A_BCM1480_MC_BASE_0+(ctlid)*BCM1480_MC_REGISTER_SPACING)
90#define A_BCM1480_MC_REGISTER(ctlid,reg) (A_BCM1480_MC_BASE(ctlid)+(reg)) 90#define A_BCM1480_MC_REGISTER(ctlid, reg) (A_BCM1480_MC_BASE(ctlid)+(reg))
91 91
92#define R_BCM1480_MC_CONFIG 0x0000000100 92#define R_BCM1480_MC_CONFIG 0x0000000100
93#define R_BCM1480_MC_CS_START 0x0000000120 93#define R_BCM1480_MC_CS_START 0x0000000120
@@ -327,7 +327,7 @@
327#define BCM1480_SCD_NUM_WDOGS 4 327#define BCM1480_SCD_NUM_WDOGS 4
328 328
329#define A_BCM1480_SCD_WDOG_BASE(w) (A_BCM1480_SCD_WDOG_0+((w)&2)*0x1000 + ((w)&1)*0x100) 329#define A_BCM1480_SCD_WDOG_BASE(w) (A_BCM1480_SCD_WDOG_0+((w)&2)*0x1000 + ((w)&1)*0x100)
330#define A_BCM1480_SCD_WDOG_REGISTER(w,r) (A_BCM1480_SCD_WDOG_BASE(w) + (r)) 330#define A_BCM1480_SCD_WDOG_REGISTER(w, r) (A_BCM1480_SCD_WDOG_BASE(w) + (r))
331 331
332#define A_BCM1480_SCD_WDOG_INIT_2 0x0010022050 332#define A_BCM1480_SCD_WDOG_INIT_2 0x0010022050
333#define A_BCM1480_SCD_WDOG_CNT_2 0x0010022058 333#define A_BCM1480_SCD_WDOG_CNT_2 0x0010022058
@@ -372,7 +372,7 @@
372#define BCM1480_IMR_REGISTER_SPACING_SHIFT 13 372#define BCM1480_IMR_REGISTER_SPACING_SHIFT 13
373 373
374#define A_BCM1480_IMR_MAPPER(cpu) (A_BCM1480_IMR_CPU0_BASE+(cpu)*BCM1480_IMR_REGISTER_SPACING) 374#define A_BCM1480_IMR_MAPPER(cpu) (A_BCM1480_IMR_CPU0_BASE+(cpu)*BCM1480_IMR_REGISTER_SPACING)
375#define A_BCM1480_IMR_REGISTER(cpu,reg) (A_BCM1480_IMR_MAPPER(cpu)+(reg)) 375#define A_BCM1480_IMR_REGISTER(cpu, reg) (A_BCM1480_IMR_MAPPER(cpu)+(reg))
376 376
377/* Most IMR registers are 128 bits, implemented as non-contiguous 377/* Most IMR registers are 128 bits, implemented as non-contiguous
378 64-bit registers high (_H) and low (_L) */ 378 64-bit registers high (_H) and low (_L) */
@@ -413,7 +413,7 @@
413 413
414#define A_BCM1480_IMR_ALIAS_MAILBOX(cpu) (A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE + \ 414#define A_BCM1480_IMR_ALIAS_MAILBOX(cpu) (A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE + \
415 (cpu)*BCM1480_IMR_ALIAS_MAILBOX_SPACING) 415 (cpu)*BCM1480_IMR_ALIAS_MAILBOX_SPACING)
416#define A_BCM1480_IMR_ALIAS_MAILBOX_REGISTER(cpu,reg) (A_BCM1480_IMR_ALIAS_MAILBOX(cpu)+(reg)) 416#define A_BCM1480_IMR_ALIAS_MAILBOX_REGISTER(cpu, reg) (A_BCM1480_IMR_ALIAS_MAILBOX(cpu)+(reg))
417 417
418#define R_BCM1480_IMR_ALIAS_MAILBOX_0 0x0000 /* 0x0x0 */ 418#define R_BCM1480_IMR_ALIAS_MAILBOX_0 0x0000 /* 0x0x0 */
419#define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET 0x0008 /* 0x0x8 */ 419#define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET 0x0008 /* 0x0x8 */
@@ -427,7 +427,7 @@
427#define R_BCM1480_IMR_MAILBOX_SET 0x08 427#define R_BCM1480_IMR_MAILBOX_SET 0x08
428#define R_BCM1480_IMR_MAILBOX_CLR 0x10 428#define R_BCM1480_IMR_MAILBOX_CLR 0x10
429#define R_BCM1480_IMR_MAILBOX_NUM_SPACING 0x20 429#define R_BCM1480_IMR_MAILBOX_NUM_SPACING 0x20
430#define A_BCM1480_MAILBOX_REGISTER(num,reg,cpu) \ 430#define A_BCM1480_MAILBOX_REGISTER(num, reg, cpu) \
431 (A_BCM1480_IMR_CPU0_BASE + \ 431 (A_BCM1480_IMR_CPU0_BASE + \
432 (num * R_BCM1480_IMR_MAILBOX_NUM_SPACING) + \ 432 (num * R_BCM1480_IMR_MAILBOX_NUM_SPACING) + \
433 (cpu * BCM1480_IMR_REGISTER_SPACING) + \ 433 (cpu * BCM1480_IMR_REGISTER_SPACING) + \
@@ -550,7 +550,7 @@
550#define BCM1480_HR_REGISTER_SPACING 0x80000 550#define BCM1480_HR_REGISTER_SPACING 0x80000
551 551
552#define A_BCM1480_HR_BASE(idx) (A_BCM1480_HR_BASE_0 + ((idx)*BCM1480_HR_REGISTER_SPACING)) 552#define A_BCM1480_HR_BASE(idx) (A_BCM1480_HR_BASE_0 + ((idx)*BCM1480_HR_REGISTER_SPACING))
553#define A_BCM1480_HR_REGISTER(idx,reg) (A_BCM1480_HR_BASE(idx) + (reg)) 553#define A_BCM1480_HR_REGISTER(idx, reg) (A_BCM1480_HR_BASE(idx) + (reg))
554 554
555#define R_BCM1480_HR_CFG 0x0000000000 555#define R_BCM1480_HR_CFG 0x0000000000
556 556
@@ -599,9 +599,9 @@
599#define BCM1480_PM_NUM_CHANNELS 32 599#define BCM1480_PM_NUM_CHANNELS 32
600 600
601#define A_BCM1480_PMI_LCL_BASE(idx) (A_BCM1480_PMI_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING)) 601#define A_BCM1480_PMI_LCL_BASE(idx) (A_BCM1480_PMI_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING))
602#define A_BCM1480_PMI_LCL_REGISTER(idx,reg) (A_BCM1480_PMI_LCL_BASE(idx) + (reg)) 602#define A_BCM1480_PMI_LCL_REGISTER(idx, reg) (A_BCM1480_PMI_LCL_BASE(idx) + (reg))
603#define A_BCM1480_PMO_LCL_BASE(idx) (A_BCM1480_PMO_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING)) 603#define A_BCM1480_PMO_LCL_BASE(idx) (A_BCM1480_PMO_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING))
604#define A_BCM1480_PMO_LCL_REGISTER(idx,reg) (A_BCM1480_PMO_LCL_BASE(idx) + (reg)) 604#define A_BCM1480_PMO_LCL_REGISTER(idx, reg) (A_BCM1480_PMO_LCL_BASE(idx) + (reg))
605 605
606#define BCM1480_PM_INT_PACKING 8 606#define BCM1480_PM_INT_PACKING 8
607#define BCM1480_PM_INT_FUNCTION_SPACING 0x40 607#define BCM1480_PM_INT_FUNCTION_SPACING 0x40
@@ -721,7 +721,7 @@
721#define BCM1480_HSP_REGISTER_SPACING 0x80000 721#define BCM1480_HSP_REGISTER_SPACING 0x80000
722 722
723#define A_BCM1480_HSP_BASE(idx) (A_BCM1480_HSP_BASE_0 + ((idx)*BCM1480_HSP_REGISTER_SPACING)) 723#define A_BCM1480_HSP_BASE(idx) (A_BCM1480_HSP_BASE_0 + ((idx)*BCM1480_HSP_REGISTER_SPACING))
724#define A_BCM1480_HSP_REGISTER(idx,reg) (A_BCM1480_HSP_BASE(idx) + (reg)) 724#define A_BCM1480_HSP_REGISTER(idx, reg) (A_BCM1480_HSP_BASE(idx) + (reg))
725 725
726#define R_BCM1480_HSP_RX_SPI4_CFG_0 0x0000000000 726#define R_BCM1480_HSP_RX_SPI4_CFG_0 0x0000000000
727#define R_BCM1480_HSP_RX_SPI4_CFG_1 0x0000000008 727#define R_BCM1480_HSP_RX_SPI4_CFG_1 0x0000000008
diff --git a/include/asm-mips/sibyte/bcm1480_scd.h b/include/asm-mips/sibyte/bcm1480_scd.h
index 6111d6dcf117..25ef24cbb92a 100644
--- a/include/asm-mips/sibyte/bcm1480_scd.h
+++ b/include/asm-mips/sibyte/bcm1480_scd.h
@@ -99,22 +99,22 @@
99#define M_BCM1480_SYS_IOB_DIV _SB_MAKEMASK1(5) 99#define M_BCM1480_SYS_IOB_DIV _SB_MAKEMASK1(5)
100 100
101#define S_BCM1480_SYS_PLL_DIV _SB_MAKE64(6) 101#define S_BCM1480_SYS_PLL_DIV _SB_MAKE64(6)
102#define M_BCM1480_SYS_PLL_DIV _SB_MAKEMASK(5,S_BCM1480_SYS_PLL_DIV) 102#define M_BCM1480_SYS_PLL_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_PLL_DIV)
103#define V_BCM1480_SYS_PLL_DIV(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_PLL_DIV) 103#define V_BCM1480_SYS_PLL_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_PLL_DIV)
104#define G_BCM1480_SYS_PLL_DIV(x) _SB_GETVALUE(x,S_BCM1480_SYS_PLL_DIV,M_BCM1480_SYS_PLL_DIV) 104#define G_BCM1480_SYS_PLL_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_PLL_DIV, M_BCM1480_SYS_PLL_DIV)
105 105
106#define S_BCM1480_SYS_SW_DIV _SB_MAKE64(11) 106#define S_BCM1480_SYS_SW_DIV _SB_MAKE64(11)
107#define M_BCM1480_SYS_SW_DIV _SB_MAKEMASK(5,S_BCM1480_SYS_SW_DIV) 107#define M_BCM1480_SYS_SW_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_SW_DIV)
108#define V_BCM1480_SYS_SW_DIV(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_SW_DIV) 108#define V_BCM1480_SYS_SW_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_SW_DIV)
109#define G_BCM1480_SYS_SW_DIV(x) _SB_GETVALUE(x,S_BCM1480_SYS_SW_DIV,M_BCM1480_SYS_SW_DIV) 109#define G_BCM1480_SYS_SW_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_SW_DIV, M_BCM1480_SYS_SW_DIV)
110 110
111#define M_BCM1480_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) 111#define M_BCM1480_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16)
112#define M_BCM1480_SYS_DUART1_ENABLE _SB_MAKEMASK1(17) 112#define M_BCM1480_SYS_DUART1_ENABLE _SB_MAKEMASK1(17)
113 113
114#define S_BCM1480_SYS_BOOT_MODE _SB_MAKE64(18) 114#define S_BCM1480_SYS_BOOT_MODE _SB_MAKE64(18)
115#define M_BCM1480_SYS_BOOT_MODE _SB_MAKEMASK(2,S_BCM1480_SYS_BOOT_MODE) 115#define M_BCM1480_SYS_BOOT_MODE _SB_MAKEMASK(2, S_BCM1480_SYS_BOOT_MODE)
116#define V_BCM1480_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_BOOT_MODE) 116#define V_BCM1480_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_BOOT_MODE)
117#define G_BCM1480_SYS_BOOT_MODE(x) _SB_GETVALUE(x,S_BCM1480_SYS_BOOT_MODE,M_BCM1480_SYS_BOOT_MODE) 117#define G_BCM1480_SYS_BOOT_MODE(x) _SB_GETVALUE(x, S_BCM1480_SYS_BOOT_MODE, M_BCM1480_SYS_BOOT_MODE)
118#define K_BCM1480_SYS_BOOT_MODE_ROM32 0 118#define K_BCM1480_SYS_BOOT_MODE_ROM32 0
119#define K_BCM1480_SYS_BOOT_MODE_ROM8 1 119#define K_BCM1480_SYS_BOOT_MODE_ROM8 1
120#define K_BCM1480_SYS_BOOT_MODE_SMBUS_SMALL 2 120#define K_BCM1480_SYS_BOOT_MODE_SMBUS_SMALL 2
@@ -129,16 +129,16 @@
129#define M_BCM1480_SYS_RESERVED25 _SB_MAKEMASK1(25) 129#define M_BCM1480_SYS_RESERVED25 _SB_MAKEMASK1(25)
130 130
131#define S_BCM1480_SYS_CONFIG 26 131#define S_BCM1480_SYS_CONFIG 26
132#define M_BCM1480_SYS_CONFIG _SB_MAKEMASK(6,S_BCM1480_SYS_CONFIG) 132#define M_BCM1480_SYS_CONFIG _SB_MAKEMASK(6, S_BCM1480_SYS_CONFIG)
133#define V_BCM1480_SYS_CONFIG(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_CONFIG) 133#define V_BCM1480_SYS_CONFIG(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_CONFIG)
134#define G_BCM1480_SYS_CONFIG(x) _SB_GETVALUE(x,S_BCM1480_SYS_CONFIG,M_BCM1480_SYS_CONFIG) 134#define G_BCM1480_SYS_CONFIG(x) _SB_GETVALUE(x, S_BCM1480_SYS_CONFIG, M_BCM1480_SYS_CONFIG)
135 135
136#define M_BCM1480_SYS_RESERVED32 _SB_MAKEMASK(32,15) 136#define M_BCM1480_SYS_RESERVED32 _SB_MAKEMASK(32, 15)
137 137
138#define S_BCM1480_SYS_NODEID 47 138#define S_BCM1480_SYS_NODEID 47
139#define M_BCM1480_SYS_NODEID _SB_MAKEMASK(4,S_BCM1480_SYS_NODEID) 139#define M_BCM1480_SYS_NODEID _SB_MAKEMASK(4, S_BCM1480_SYS_NODEID)
140#define V_BCM1480_SYS_NODEID(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_NODEID) 140#define V_BCM1480_SYS_NODEID(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_NODEID)
141#define G_BCM1480_SYS_NODEID(x) _SB_GETVALUE(x,S_BCM1480_SYS_NODEID,M_BCM1480_SYS_NODEID) 141#define G_BCM1480_SYS_NODEID(x) _SB_GETVALUE(x, S_BCM1480_SYS_NODEID, M_BCM1480_SYS_NODEID)
142 142
143#define M_BCM1480_SYS_CCNUMA_EN _SB_MAKEMASK1(51) 143#define M_BCM1480_SYS_CCNUMA_EN _SB_MAKEMASK1(51)
144#define M_BCM1480_SYS_CPU_RESET_0 _SB_MAKEMASK1(52) 144#define M_BCM1480_SYS_CPU_RESET_0 _SB_MAKEMASK1(52)
@@ -196,9 +196,9 @@
196#define M_BCM1480_SCD_WDOG_ENABLE _SB_MAKEMASK1(0) 196#define M_BCM1480_SCD_WDOG_ENABLE _SB_MAKEMASK1(0)
197 197
198#define S_BCM1480_SCD_WDOG_RESET_TYPE 2 198#define S_BCM1480_SCD_WDOG_RESET_TYPE 2
199#define M_BCM1480_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(5,S_BCM1480_SCD_WDOG_RESET_TYPE) 199#define M_BCM1480_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(5, S_BCM1480_SCD_WDOG_RESET_TYPE)
200#define V_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_WDOG_RESET_TYPE) 200#define V_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE)
201#define G_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x,S_BCM1480_SCD_WDOG_RESET_TYPE,M_BCM1480_SCD_WDOG_RESET_TYPE) 201#define G_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE, M_BCM1480_SCD_WDOG_RESET_TYPE)
202 202
203#define K_BCM1480_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ 203#define K_BCM1480_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */
204#define K_BCM1480_SCD_WDOG_RESET_SOFT 1 204#define K_BCM1480_SCD_WDOG_RESET_SOFT 1
@@ -244,24 +244,24 @@
244 */ 244 */
245 245
246#define S_SPC_CFG_SRC4 32 246#define S_SPC_CFG_SRC4 32
247#define M_SPC_CFG_SRC4 _SB_MAKEMASK(8,S_SPC_CFG_SRC4) 247#define M_SPC_CFG_SRC4 _SB_MAKEMASK(8, S_SPC_CFG_SRC4)
248#define V_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC4) 248#define V_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC4)
249#define G_SPC_CFG_SRC4(x) _SB_GETVALUE(x,S_SPC_CFG_SRC4,M_SPC_CFG_SRC4) 249#define G_SPC_CFG_SRC4(x) _SB_GETVALUE(x, S_SPC_CFG_SRC4, M_SPC_CFG_SRC4)
250 250
251#define S_SPC_CFG_SRC5 40 251#define S_SPC_CFG_SRC5 40
252#define M_SPC_CFG_SRC5 _SB_MAKEMASK(8,S_SPC_CFG_SRC5) 252#define M_SPC_CFG_SRC5 _SB_MAKEMASK(8, S_SPC_CFG_SRC5)
253#define V_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC5) 253#define V_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC5)
254#define G_SPC_CFG_SRC5(x) _SB_GETVALUE(x,S_SPC_CFG_SRC5,M_SPC_CFG_SRC5) 254#define G_SPC_CFG_SRC5(x) _SB_GETVALUE(x, S_SPC_CFG_SRC5, M_SPC_CFG_SRC5)
255 255
256#define S_SPC_CFG_SRC6 48 256#define S_SPC_CFG_SRC6 48
257#define M_SPC_CFG_SRC6 _SB_MAKEMASK(8,S_SPC_CFG_SRC6) 257#define M_SPC_CFG_SRC6 _SB_MAKEMASK(8, S_SPC_CFG_SRC6)
258#define V_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC6) 258#define V_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC6)
259#define G_SPC_CFG_SRC6(x) _SB_GETVALUE(x,S_SPC_CFG_SRC6,M_SPC_CFG_SRC6) 259#define G_SPC_CFG_SRC6(x) _SB_GETVALUE(x, S_SPC_CFG_SRC6, M_SPC_CFG_SRC6)
260 260
261#define S_SPC_CFG_SRC7 56 261#define S_SPC_CFG_SRC7 56
262#define M_SPC_CFG_SRC7 _SB_MAKEMASK(8,S_SPC_CFG_SRC7) 262#define M_SPC_CFG_SRC7 _SB_MAKEMASK(8, S_SPC_CFG_SRC7)
263#define V_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC7) 263#define V_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC7)
264#define G_SPC_CFG_SRC7(x) _SB_GETVALUE(x,S_SPC_CFG_SRC7,M_SPC_CFG_SRC7) 264#define G_SPC_CFG_SRC7(x) _SB_GETVALUE(x, S_SPC_CFG_SRC7, M_SPC_CFG_SRC7)
265 265
266/* 266/*
267 * System Performance Counter Control Register (Table 32) 267 * System Performance Counter Control Register (Table 32)
@@ -281,9 +281,9 @@
281 */ 281 */
282 282
283#define S_BCM1480_SPC_CNT_COUNT 0 283#define S_BCM1480_SPC_CNT_COUNT 0
284#define M_BCM1480_SPC_CNT_COUNT _SB_MAKEMASK(40,S_BCM1480_SPC_CNT_COUNT) 284#define M_BCM1480_SPC_CNT_COUNT _SB_MAKEMASK(40, S_BCM1480_SPC_CNT_COUNT)
285#define V_BCM1480_SPC_CNT_COUNT(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CNT_COUNT) 285#define V_BCM1480_SPC_CNT_COUNT(x) _SB_MAKEVALUE(x, S_BCM1480_SPC_CNT_COUNT)
286#define G_BCM1480_SPC_CNT_COUNT(x) _SB_GETVALUE(x,S_BCM1480_SPC_CNT_COUNT,M_BCM1480_SPC_CNT_COUNT) 286#define G_BCM1480_SPC_CNT_COUNT(x) _SB_GETVALUE(x, S_BCM1480_SPC_CNT_COUNT, M_BCM1480_SPC_CNT_COUNT)
287 287
288#define M_BCM1480_SPC_CNT_OFLOW _SB_MAKEMASK1(40) 288#define M_BCM1480_SPC_CNT_OFLOW _SB_MAKEMASK1(40)
289 289
@@ -322,13 +322,13 @@
322 * slightly different. 322 * slightly different.
323 */ 323 */
324 324
325#define M_BCM1480_ATRAP_INDEX _SB_MAKEMASK(4,0) 325#define M_BCM1480_ATRAP_INDEX _SB_MAKEMASK(4, 0)
326#define M_BCM1480_ATRAP_ADDRESS _SB_MAKEMASK(40,0) 326#define M_BCM1480_ATRAP_ADDRESS _SB_MAKEMASK(40, 0)
327 327
328#define S_BCM1480_ATRAP_CFG_CNT 0 328#define S_BCM1480_ATRAP_CFG_CNT 0
329#define M_BCM1480_ATRAP_CFG_CNT _SB_MAKEMASK(3,S_BCM1480_ATRAP_CFG_CNT) 329#define M_BCM1480_ATRAP_CFG_CNT _SB_MAKEMASK(3, S_BCM1480_ATRAP_CFG_CNT)
330#define V_BCM1480_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_CNT) 330#define V_BCM1480_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CNT)
331#define G_BCM1480_ATRAP_CFG_CNT(x) _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_CNT,M_BCM1480_ATRAP_CFG_CNT) 331#define G_BCM1480_ATRAP_CFG_CNT(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CNT, M_BCM1480_ATRAP_CFG_CNT)
332 332
333#define M_BCM1480_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) 333#define M_BCM1480_ATRAP_CFG_WRITE _SB_MAKEMASK1(3)
334#define M_BCM1480_ATRAP_CFG_ALL _SB_MAKEMASK1(4) 334#define M_BCM1480_ATRAP_CFG_ALL _SB_MAKEMASK1(4)
@@ -337,9 +337,9 @@
337#define M_BCM1480_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) 337#define M_BCM1480_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7)
338 338
339#define S_BCM1480_ATRAP_CFG_AGENTID 8 339#define S_BCM1480_ATRAP_CFG_AGENTID 8
340#define M_BCM1480_ATRAP_CFG_AGENTID _SB_MAKEMASK(4,S_BCM1480_ATRAP_CFG_AGENTID) 340#define M_BCM1480_ATRAP_CFG_AGENTID _SB_MAKEMASK(4, S_BCM1480_ATRAP_CFG_AGENTID)
341#define V_BCM1480_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_AGENTID) 341#define V_BCM1480_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID)
342#define G_BCM1480_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_AGENTID,M_BCM1480_ATRAP_CFG_AGENTID) 342#define G_BCM1480_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID, M_BCM1480_ATRAP_CFG_AGENTID)
343 343
344 344
345#define K_BCM1480_BUS_AGENT_CPU0 0 345#define K_BCM1480_BUS_AGENT_CPU0 0
@@ -354,9 +354,9 @@
354#define K_BCM1480_BUS_AGENT_PM 10 354#define K_BCM1480_BUS_AGENT_PM 10
355 355
356#define S_BCM1480_ATRAP_CFG_CATTR 12 356#define S_BCM1480_ATRAP_CFG_CATTR 12
357#define M_BCM1480_ATRAP_CFG_CATTR _SB_MAKEMASK(2,S_BCM1480_ATRAP_CFG_CATTR) 357#define M_BCM1480_ATRAP_CFG_CATTR _SB_MAKEMASK(2, S_BCM1480_ATRAP_CFG_CATTR)
358#define V_BCM1480_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_CATTR) 358#define V_BCM1480_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CATTR)
359#define G_BCM1480_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_CATTR,M_BCM1480_ATRAP_CFG_CATTR) 359#define G_BCM1480_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CATTR, M_BCM1480_ATRAP_CFG_CATTR)
360 360
361#define K_BCM1480_ATRAP_CFG_CATTR_IGNORE 0 361#define K_BCM1480_ATRAP_CFG_CATTR_IGNORE 0
362#define K_BCM1480_ATRAP_CFG_CATTR_UNC 1 362#define K_BCM1480_ATRAP_CFG_CATTR_UNC 1
@@ -382,9 +382,9 @@
382#define M_BCM1480_SCD_TRSEQ_TID_MATCH_EN _SB_MAKEMASK1(25) 382#define M_BCM1480_SCD_TRSEQ_TID_MATCH_EN _SB_MAKEMASK1(25)
383 383
384#define S_BCM1480_SCD_TRSEQ_SWFUNC 26 384#define S_BCM1480_SCD_TRSEQ_SWFUNC 26
385#define M_BCM1480_SCD_TRSEQ_SWFUNC _SB_MAKEMASK(2,S_BCM1480_SCD_TRSEQ_SWFUNC) 385#define M_BCM1480_SCD_TRSEQ_SWFUNC _SB_MAKEMASK(2, S_BCM1480_SCD_TRSEQ_SWFUNC)
386#define V_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRSEQ_SWFUNC) 386#define V_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC)
387#define G_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_GETVALUE(x,S_BCM1480_SCD_TRSEQ_SWFUNC,M_BCM1480_SCD_TRSEQ_SWFUNC) 387#define G_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC, M_BCM1480_SCD_TRSEQ_SWFUNC)
388 388
389/* 389/*
390 * Trace Control Register (Table 49) 390 * Trace Control Register (Table 49)
@@ -395,9 +395,9 @@
395 */ 395 */
396 396
397#define S_BCM1480_SCD_TRACE_CFG_MODE 16 397#define S_BCM1480_SCD_TRACE_CFG_MODE 16
398#define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2,S_BCM1480_SCD_TRACE_CFG_MODE) 398#define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2, S_BCM1480_SCD_TRACE_CFG_MODE)
399#define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRACE_CFG_MODE) 399#define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE)
400#define G_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_GETVALUE(x,S_BCM1480_SCD_TRACE_CFG_MODE,M_BCM1480_SCD_TRACE_CFG_MODE) 400#define G_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE, M_BCM1480_SCD_TRACE_CFG_MODE)
401 401
402#define K_BCM1480_SCD_TRACE_CFG_MODE_BLOCKERS 0 402#define K_BCM1480_SCD_TRACE_CFG_MODE_BLOCKERS 0
403#define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1 403#define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1
diff --git a/include/asm-mips/sibyte/board.h b/include/asm-mips/sibyte/board.h
index 73bce901a378..da198a1c8c81 100644
--- a/include/asm-mips/sibyte/board.h
+++ b/include/asm-mips/sibyte/board.h
@@ -41,7 +41,7 @@
41#ifdef __ASSEMBLY__ 41#ifdef __ASSEMBLY__
42 42
43#ifdef LEDS_PHYS 43#ifdef LEDS_PHYS
44#define setleds(t0,t1,c0,c1,c2,c3) \ 44#define setleds(t0, t1, c0, c1, c2, c3) \
45 li t0, (LEDS_PHYS|0xa0000000); \ 45 li t0, (LEDS_PHYS|0xa0000000); \
46 li t1, c0; \ 46 li t1, c0; \
47 sb t1, 0x18(t0); \ 47 sb t1, 0x18(t0); \
@@ -52,7 +52,7 @@
52 li t1, c3; \ 52 li t1, c3; \
53 sb t1, 0x00(t0) 53 sb t1, 0x00(t0)
54#else 54#else
55#define setleds(t0,t1,c0,c1,c2,c3) 55#define setleds(t0, t1, c0, c1, c2, c3)
56#endif /* LEDS_PHYS */ 56#endif /* LEDS_PHYS */
57 57
58#else 58#else
diff --git a/include/asm-mips/sibyte/sb1250_defs.h b/include/asm-mips/sibyte/sb1250_defs.h
index a885491217c1..09365f9111fa 100644
--- a/include/asm-mips/sibyte/sb1250_defs.h
+++ b/include/asm-mips/sibyte/sb1250_defs.h
@@ -232,18 +232,18 @@
232 * Make a mask for 'v' bits at position 'n' 232 * Make a mask for 'v' bits at position 'n'
233 */ 233 */
234 234
235#define _SB_MAKEMASK(v,n) (_SB_MAKE64((_SB_MAKE64(1)<<(v))-1) << _SB_MAKE64(n)) 235#define _SB_MAKEMASK(v, n) (_SB_MAKE64((_SB_MAKE64(1)<<(v))-1) << _SB_MAKE64(n))
236#define _SB_MAKEMASK_32(v,n) (_SB_MAKE32((_SB_MAKE32(1)<<(v))-1) << _SB_MAKE32(n)) 236#define _SB_MAKEMASK_32(v, n) (_SB_MAKE32((_SB_MAKE32(1)<<(v))-1) << _SB_MAKE32(n))
237 237
238/* 238/*
239 * Make a value at 'v' at bit position 'n' 239 * Make a value at 'v' at bit position 'n'
240 */ 240 */
241 241
242#define _SB_MAKEVALUE(v,n) (_SB_MAKE64(v) << _SB_MAKE64(n)) 242#define _SB_MAKEVALUE(v, n) (_SB_MAKE64(v) << _SB_MAKE64(n))
243#define _SB_MAKEVALUE_32(v,n) (_SB_MAKE32(v) << _SB_MAKE32(n)) 243#define _SB_MAKEVALUE_32(v, n) (_SB_MAKE32(v) << _SB_MAKE32(n))
244 244
245#define _SB_GETVALUE(v,n,m) ((_SB_MAKE64(v) & _SB_MAKE64(m)) >> _SB_MAKE64(n)) 245#define _SB_GETVALUE(v, n, m) ((_SB_MAKE64(v) & _SB_MAKE64(m)) >> _SB_MAKE64(n))
246#define _SB_GETVALUE_32(v,n,m) ((_SB_MAKE32(v) & _SB_MAKE32(m)) >> _SB_MAKE32(n)) 246#define _SB_GETVALUE_32(v, n, m) ((_SB_MAKE32(v) & _SB_MAKE32(m)) >> _SB_MAKE32(n))
247 247
248/* 248/*
249 * Macros to read/write on-chip registers 249 * Macros to read/write on-chip registers
@@ -252,7 +252,7 @@
252 252
253 253
254#if defined(__mips64) && !defined(__ASSEMBLY__) 254#if defined(__mips64) && !defined(__ASSEMBLY__)
255#define SBWRITECSR(csr,val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val) 255#define SBWRITECSR(csr, val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val)
256#define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr))) 256#define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr)))
257#endif /* __ASSEMBLY__ */ 257#endif /* __ASSEMBLY__ */
258 258
diff --git a/include/asm-mips/sibyte/sb1250_dma.h b/include/asm-mips/sibyte/sb1250_dma.h
index e6145f524fbd..bad56171d747 100644
--- a/include/asm-mips/sibyte/sb1250_dma.h
+++ b/include/asm-mips/sibyte/sb1250_dma.h
@@ -57,9 +57,9 @@
57#define M_DMA_RESERVED1 _SB_MAKEMASK1(2) 57#define M_DMA_RESERVED1 _SB_MAKEMASK1(2)
58 58
59#define S_DMA_DESC_TYPE _SB_MAKE64(1) 59#define S_DMA_DESC_TYPE _SB_MAKE64(1)
60#define M_DMA_DESC_TYPE _SB_MAKEMASK(2,S_DMA_DESC_TYPE) 60#define M_DMA_DESC_TYPE _SB_MAKEMASK(2, S_DMA_DESC_TYPE)
61#define V_DMA_DESC_TYPE(x) _SB_MAKEVALUE(x,S_DMA_DESC_TYPE) 61#define V_DMA_DESC_TYPE(x) _SB_MAKEVALUE(x, S_DMA_DESC_TYPE)
62#define G_DMA_DESC_TYPE(x) _SB_GETVALUE(x,S_DMA_DESC_TYPE,M_DMA_DESC_TYPE) 62#define G_DMA_DESC_TYPE(x) _SB_GETVALUE(x, S_DMA_DESC_TYPE, M_DMA_DESC_TYPE)
63 63
64#define K_DMA_DESC_TYPE_RING_AL 0 64#define K_DMA_DESC_TYPE_RING_AL 0
65#define K_DMA_DESC_TYPE_CHAIN_AL 1 65#define K_DMA_DESC_TYPE_CHAIN_AL 1
@@ -76,24 +76,24 @@
76#define M_DMA_TDX_EN _SB_MAKEMASK1(7) 76#define M_DMA_TDX_EN _SB_MAKEMASK1(7)
77 77
78#define S_DMA_INT_PKTCNT _SB_MAKE64(8) 78#define S_DMA_INT_PKTCNT _SB_MAKE64(8)
79#define M_DMA_INT_PKTCNT _SB_MAKEMASK(8,S_DMA_INT_PKTCNT) 79#define M_DMA_INT_PKTCNT _SB_MAKEMASK(8, S_DMA_INT_PKTCNT)
80#define V_DMA_INT_PKTCNT(x) _SB_MAKEVALUE(x,S_DMA_INT_PKTCNT) 80#define V_DMA_INT_PKTCNT(x) _SB_MAKEVALUE(x, S_DMA_INT_PKTCNT)
81#define G_DMA_INT_PKTCNT(x) _SB_GETVALUE(x,S_DMA_INT_PKTCNT,M_DMA_INT_PKTCNT) 81#define G_DMA_INT_PKTCNT(x) _SB_GETVALUE(x, S_DMA_INT_PKTCNT, M_DMA_INT_PKTCNT)
82 82
83#define S_DMA_RINGSZ _SB_MAKE64(16) 83#define S_DMA_RINGSZ _SB_MAKE64(16)
84#define M_DMA_RINGSZ _SB_MAKEMASK(16,S_DMA_RINGSZ) 84#define M_DMA_RINGSZ _SB_MAKEMASK(16, S_DMA_RINGSZ)
85#define V_DMA_RINGSZ(x) _SB_MAKEVALUE(x,S_DMA_RINGSZ) 85#define V_DMA_RINGSZ(x) _SB_MAKEVALUE(x, S_DMA_RINGSZ)
86#define G_DMA_RINGSZ(x) _SB_GETVALUE(x,S_DMA_RINGSZ,M_DMA_RINGSZ) 86#define G_DMA_RINGSZ(x) _SB_GETVALUE(x, S_DMA_RINGSZ, M_DMA_RINGSZ)
87 87
88#define S_DMA_HIGH_WATERMARK _SB_MAKE64(32) 88#define S_DMA_HIGH_WATERMARK _SB_MAKE64(32)
89#define M_DMA_HIGH_WATERMARK _SB_MAKEMASK(16,S_DMA_HIGH_WATERMARK) 89#define M_DMA_HIGH_WATERMARK _SB_MAKEMASK(16, S_DMA_HIGH_WATERMARK)
90#define V_DMA_HIGH_WATERMARK(x) _SB_MAKEVALUE(x,S_DMA_HIGH_WATERMARK) 90#define V_DMA_HIGH_WATERMARK(x) _SB_MAKEVALUE(x, S_DMA_HIGH_WATERMARK)
91#define G_DMA_HIGH_WATERMARK(x) _SB_GETVALUE(x,S_DMA_HIGH_WATERMARK,M_DMA_HIGH_WATERMARK) 91#define G_DMA_HIGH_WATERMARK(x) _SB_GETVALUE(x, S_DMA_HIGH_WATERMARK, M_DMA_HIGH_WATERMARK)
92 92
93#define S_DMA_LOW_WATERMARK _SB_MAKE64(48) 93#define S_DMA_LOW_WATERMARK _SB_MAKE64(48)
94#define M_DMA_LOW_WATERMARK _SB_MAKEMASK(16,S_DMA_LOW_WATERMARK) 94#define M_DMA_LOW_WATERMARK _SB_MAKEMASK(16, S_DMA_LOW_WATERMARK)
95#define V_DMA_LOW_WATERMARK(x) _SB_MAKEVALUE(x,S_DMA_LOW_WATERMARK) 95#define V_DMA_LOW_WATERMARK(x) _SB_MAKEVALUE(x, S_DMA_LOW_WATERMARK)
96#define G_DMA_LOW_WATERMARK(x) _SB_GETVALUE(x,S_DMA_LOW_WATERMARK,M_DMA_LOW_WATERMARK) 96#define G_DMA_LOW_WATERMARK(x) _SB_GETVALUE(x, S_DMA_LOW_WATERMARK, M_DMA_LOW_WATERMARK)
97 97
98/* 98/*
99 * Ethernet and Serial DMA Configuration Register 1 (Table 7-5) 99 * Ethernet and Serial DMA Configuration Register 1 (Table 7-5)
@@ -116,37 +116,37 @@
116#define M_DMA_TX_FC_PAUSE_EN _SB_MAKEMASK1(7) 116#define M_DMA_TX_FC_PAUSE_EN _SB_MAKEMASK1(7)
117#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 117#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
118 118
119#define M_DMA_MBZ1 _SB_MAKEMASK(6,15) 119#define M_DMA_MBZ1 _SB_MAKEMASK(6, 15)
120 120
121#define S_DMA_HDR_SIZE _SB_MAKE64(21) 121#define S_DMA_HDR_SIZE _SB_MAKE64(21)
122#define M_DMA_HDR_SIZE _SB_MAKEMASK(9,S_DMA_HDR_SIZE) 122#define M_DMA_HDR_SIZE _SB_MAKEMASK(9, S_DMA_HDR_SIZE)
123#define V_DMA_HDR_SIZE(x) _SB_MAKEVALUE(x,S_DMA_HDR_SIZE) 123#define V_DMA_HDR_SIZE(x) _SB_MAKEVALUE(x, S_DMA_HDR_SIZE)
124#define G_DMA_HDR_SIZE(x) _SB_GETVALUE(x,S_DMA_HDR_SIZE,M_DMA_HDR_SIZE) 124#define G_DMA_HDR_SIZE(x) _SB_GETVALUE(x, S_DMA_HDR_SIZE, M_DMA_HDR_SIZE)
125 125
126#define M_DMA_MBZ2 _SB_MAKEMASK(5,32) 126#define M_DMA_MBZ2 _SB_MAKEMASK(5, 32)
127 127
128#define S_DMA_ASICXFR_SIZE _SB_MAKE64(37) 128#define S_DMA_ASICXFR_SIZE _SB_MAKE64(37)
129#define M_DMA_ASICXFR_SIZE _SB_MAKEMASK(9,S_DMA_ASICXFR_SIZE) 129#define M_DMA_ASICXFR_SIZE _SB_MAKEMASK(9, S_DMA_ASICXFR_SIZE)
130#define V_DMA_ASICXFR_SIZE(x) _SB_MAKEVALUE(x,S_DMA_ASICXFR_SIZE) 130#define V_DMA_ASICXFR_SIZE(x) _SB_MAKEVALUE(x, S_DMA_ASICXFR_SIZE)
131#define G_DMA_ASICXFR_SIZE(x) _SB_GETVALUE(x,S_DMA_ASICXFR_SIZE,M_DMA_ASICXFR_SIZE) 131#define G_DMA_ASICXFR_SIZE(x) _SB_GETVALUE(x, S_DMA_ASICXFR_SIZE, M_DMA_ASICXFR_SIZE)
132 132
133#define S_DMA_INT_TIMEOUT _SB_MAKE64(48) 133#define S_DMA_INT_TIMEOUT _SB_MAKE64(48)
134#define M_DMA_INT_TIMEOUT _SB_MAKEMASK(16,S_DMA_INT_TIMEOUT) 134#define M_DMA_INT_TIMEOUT _SB_MAKEMASK(16, S_DMA_INT_TIMEOUT)
135#define V_DMA_INT_TIMEOUT(x) _SB_MAKEVALUE(x,S_DMA_INT_TIMEOUT) 135#define V_DMA_INT_TIMEOUT(x) _SB_MAKEVALUE(x, S_DMA_INT_TIMEOUT)
136#define G_DMA_INT_TIMEOUT(x) _SB_GETVALUE(x,S_DMA_INT_TIMEOUT,M_DMA_INT_TIMEOUT) 136#define G_DMA_INT_TIMEOUT(x) _SB_GETVALUE(x, S_DMA_INT_TIMEOUT, M_DMA_INT_TIMEOUT)
137 137
138/* 138/*
139 * Ethernet and Serial DMA Descriptor base address (Table 7-6) 139 * Ethernet and Serial DMA Descriptor base address (Table 7-6)
140 */ 140 */
141 141
142#define M_DMA_DSCRBASE_MBZ _SB_MAKEMASK(4,0) 142#define M_DMA_DSCRBASE_MBZ _SB_MAKEMASK(4, 0)
143 143
144 144
145/* 145/*
146 * ASIC Mode Base Address (Table 7-7) 146 * ASIC Mode Base Address (Table 7-7)
147 */ 147 */
148 148
149#define M_DMA_ASIC_BASE_MBZ _SB_MAKEMASK(20,0) 149#define M_DMA_ASIC_BASE_MBZ _SB_MAKEMASK(20, 0)
150 150
151/* 151/*
152 * DMA Descriptor Count Registers (Table 7-8) 152 * DMA Descriptor Count Registers (Table 7-8)
@@ -160,9 +160,9 @@
160 */ 160 */
161 161
162#define S_DMA_CURDSCR_ADDR _SB_MAKE64(0) 162#define S_DMA_CURDSCR_ADDR _SB_MAKE64(0)
163#define M_DMA_CURDSCR_ADDR _SB_MAKEMASK(40,S_DMA_CURDSCR_ADDR) 163#define M_DMA_CURDSCR_ADDR _SB_MAKEMASK(40, S_DMA_CURDSCR_ADDR)
164#define S_DMA_CURDSCR_COUNT _SB_MAKE64(40) 164#define S_DMA_CURDSCR_COUNT _SB_MAKE64(40)
165#define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16,S_DMA_CURDSCR_COUNT) 165#define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16, S_DMA_CURDSCR_COUNT)
166 166
167#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 167#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
168#define M_DMA_TX_CH_PAUSE_ON _SB_MAKEMASK1(56) 168#define M_DMA_TX_CH_PAUSE_ON _SB_MAKEMASK1(56)
@@ -173,12 +173,12 @@
173 */ 173 */
174#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 174#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
175#define S_DMA_OODLOST_RX _SB_MAKE64(0) 175#define S_DMA_OODLOST_RX _SB_MAKE64(0)
176#define M_DMA_OODLOST_RX _SB_MAKEMASK(16,S_DMA_OODLOST_RX) 176#define M_DMA_OODLOST_RX _SB_MAKEMASK(16, S_DMA_OODLOST_RX)
177#define G_DMA_OODLOST_RX(x) _SB_GETVALUE(x,S_DMA_OODLOST_RX,M_DMA_OODLOST_RX) 177#define G_DMA_OODLOST_RX(x) _SB_GETVALUE(x, S_DMA_OODLOST_RX, M_DMA_OODLOST_RX)
178 178
179#define S_DMA_EOP_COUNT_RX _SB_MAKE64(16) 179#define S_DMA_EOP_COUNT_RX _SB_MAKE64(16)
180#define M_DMA_EOP_COUNT_RX _SB_MAKEMASK(8,S_DMA_EOP_COUNT_RX) 180#define M_DMA_EOP_COUNT_RX _SB_MAKEMASK(8, S_DMA_EOP_COUNT_RX)
181#define G_DMA_EOP_COUNT_RX(x) _SB_GETVALUE(x,S_DMA_EOP_COUNT_RX,M_DMA_EOP_COUNT_RX) 181#define G_DMA_EOP_COUNT_RX(x) _SB_GETVALUE(x, S_DMA_EOP_COUNT_RX, M_DMA_EOP_COUNT_RX)
182#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 182#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
183 183
184/* ********************************************************************* 184/* *********************************************************************
@@ -190,39 +190,39 @@
190 */ 190 */
191 191
192#define S_DMA_DSCRA_OFFSET _SB_MAKE64(0) 192#define S_DMA_DSCRA_OFFSET _SB_MAKE64(0)
193#define M_DMA_DSCRA_OFFSET _SB_MAKEMASK(5,S_DMA_DSCRA_OFFSET) 193#define M_DMA_DSCRA_OFFSET _SB_MAKEMASK(5, S_DMA_DSCRA_OFFSET)
194#define V_DMA_DSCRA_OFFSET(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_OFFSET) 194#define V_DMA_DSCRA_OFFSET(x) _SB_MAKEVALUE(x, S_DMA_DSCRA_OFFSET)
195#define G_DMA_DSCRA_OFFSET(x) _SB_GETVALUE(x,S_DMA_DSCRA_OFFSET,M_DMA_DSCRA_OFFSET) 195#define G_DMA_DSCRA_OFFSET(x) _SB_GETVALUE(x, S_DMA_DSCRA_OFFSET, M_DMA_DSCRA_OFFSET)
196 196
197/* Note: Don't shift the address over, just mask it with the mask below */ 197/* Note: Don't shift the address over, just mask it with the mask below */
198#define S_DMA_DSCRA_A_ADDR _SB_MAKE64(5) 198#define S_DMA_DSCRA_A_ADDR _SB_MAKE64(5)
199#define M_DMA_DSCRA_A_ADDR _SB_MAKEMASK(35,S_DMA_DSCRA_A_ADDR) 199#define M_DMA_DSCRA_A_ADDR _SB_MAKEMASK(35, S_DMA_DSCRA_A_ADDR)
200 200
201#define M_DMA_DSCRA_A_ADDR_OFFSET (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR) 201#define M_DMA_DSCRA_A_ADDR_OFFSET (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR)
202 202
203#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 203#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
204#define S_DMA_DSCRA_A_ADDR_UA _SB_MAKE64(0) 204#define S_DMA_DSCRA_A_ADDR_UA _SB_MAKE64(0)
205#define M_DMA_DSCRA_A_ADDR_UA _SB_MAKEMASK(40,S_DMA_DSCRA_A_ADDR_UA) 205#define M_DMA_DSCRA_A_ADDR_UA _SB_MAKEMASK(40, S_DMA_DSCRA_A_ADDR_UA)
206#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 206#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
207 207
208#define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40) 208#define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40)
209#define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9,S_DMA_DSCRA_A_SIZE) 209#define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9, S_DMA_DSCRA_A_SIZE)
210#define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_A_SIZE) 210#define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRA_A_SIZE)
211#define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRA_A_SIZE,M_DMA_DSCRA_A_SIZE) 211#define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRA_A_SIZE, M_DMA_DSCRA_A_SIZE)
212 212
213#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 213#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
214#define S_DMA_DSCRA_DSCR_CNT _SB_MAKE64(40) 214#define S_DMA_DSCRA_DSCR_CNT _SB_MAKE64(40)
215#define M_DMA_DSCRA_DSCR_CNT _SB_MAKEMASK(8,S_DMA_DSCRA_DSCR_CNT) 215#define M_DMA_DSCRA_DSCR_CNT _SB_MAKEMASK(8, S_DMA_DSCRA_DSCR_CNT)
216#define G_DMA_DSCRA_DSCR_CNT(x) _SB_GETVALUE(x,S_DMA_DSCRA_DSCR_CNT,M_DMA_DSCRA_DSCR_CNT) 216#define G_DMA_DSCRA_DSCR_CNT(x) _SB_GETVALUE(x, S_DMA_DSCRA_DSCR_CNT, M_DMA_DSCRA_DSCR_CNT)
217#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 217#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
218 218
219#define M_DMA_DSCRA_INTERRUPT _SB_MAKEMASK1(49) 219#define M_DMA_DSCRA_INTERRUPT _SB_MAKEMASK1(49)
220#define M_DMA_DSCRA_OFFSETB _SB_MAKEMASK1(50) 220#define M_DMA_DSCRA_OFFSETB _SB_MAKEMASK1(50)
221 221
222#define S_DMA_DSCRA_STATUS _SB_MAKE64(51) 222#define S_DMA_DSCRA_STATUS _SB_MAKE64(51)
223#define M_DMA_DSCRA_STATUS _SB_MAKEMASK(13,S_DMA_DSCRA_STATUS) 223#define M_DMA_DSCRA_STATUS _SB_MAKEMASK(13, S_DMA_DSCRA_STATUS)
224#define V_DMA_DSCRA_STATUS(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_STATUS) 224#define V_DMA_DSCRA_STATUS(x) _SB_MAKEVALUE(x, S_DMA_DSCRA_STATUS)
225#define G_DMA_DSCRA_STATUS(x) _SB_GETVALUE(x,S_DMA_DSCRA_STATUS,M_DMA_DSCRA_STATUS) 225#define G_DMA_DSCRA_STATUS(x) _SB_GETVALUE(x, S_DMA_DSCRA_STATUS, M_DMA_DSCRA_STATUS)
226 226
227/* 227/*
228 * Descriptor doubleword "B" (Table 7-13) 228 * Descriptor doubleword "B" (Table 7-13)
@@ -230,49 +230,49 @@
230 230
231 231
232#define S_DMA_DSCRB_OPTIONS _SB_MAKE64(0) 232#define S_DMA_DSCRB_OPTIONS _SB_MAKE64(0)
233#define M_DMA_DSCRB_OPTIONS _SB_MAKEMASK(4,S_DMA_DSCRB_OPTIONS) 233#define M_DMA_DSCRB_OPTIONS _SB_MAKEMASK(4, S_DMA_DSCRB_OPTIONS)
234#define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_OPTIONS) 234#define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_OPTIONS)
235#define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x,S_DMA_DSCRB_OPTIONS,M_DMA_DSCRB_OPTIONS) 235#define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x, S_DMA_DSCRB_OPTIONS, M_DMA_DSCRB_OPTIONS)
236 236
237#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 237#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
238#define S_DMA_DSCRB_A_SIZE _SB_MAKE64(8) 238#define S_DMA_DSCRB_A_SIZE _SB_MAKE64(8)
239#define M_DMA_DSCRB_A_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_A_SIZE) 239#define M_DMA_DSCRB_A_SIZE _SB_MAKEMASK(14, S_DMA_DSCRB_A_SIZE)
240#define V_DMA_DSCRB_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_A_SIZE) 240#define V_DMA_DSCRB_A_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_A_SIZE)
241#define G_DMA_DSCRB_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_A_SIZE,M_DMA_DSCRB_A_SIZE) 241#define G_DMA_DSCRB_A_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRB_A_SIZE, M_DMA_DSCRB_A_SIZE)
242#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 242#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
243 243
244#define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10) 244#define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10)
245 245
246/* Note: Don't shift the address over, just mask it with the mask below */ 246/* Note: Don't shift the address over, just mask it with the mask below */
247#define S_DMA_DSCRB_B_ADDR _SB_MAKE64(5) 247#define S_DMA_DSCRB_B_ADDR _SB_MAKE64(5)
248#define M_DMA_DSCRB_B_ADDR _SB_MAKEMASK(35,S_DMA_DSCRB_B_ADDR) 248#define M_DMA_DSCRB_B_ADDR _SB_MAKEMASK(35, S_DMA_DSCRB_B_ADDR)
249 249
250#define S_DMA_DSCRB_B_SIZE _SB_MAKE64(40) 250#define S_DMA_DSCRB_B_SIZE _SB_MAKE64(40)
251#define M_DMA_DSCRB_B_SIZE _SB_MAKEMASK(9,S_DMA_DSCRB_B_SIZE) 251#define M_DMA_DSCRB_B_SIZE _SB_MAKEMASK(9, S_DMA_DSCRB_B_SIZE)
252#define V_DMA_DSCRB_B_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_B_SIZE) 252#define V_DMA_DSCRB_B_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_B_SIZE)
253#define G_DMA_DSCRB_B_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_B_SIZE,M_DMA_DSCRB_B_SIZE) 253#define G_DMA_DSCRB_B_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRB_B_SIZE, M_DMA_DSCRB_B_SIZE)
254 254
255#define M_DMA_DSCRB_B_VALID _SB_MAKEMASK1(49) 255#define M_DMA_DSCRB_B_VALID _SB_MAKEMASK1(49)
256 256
257#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 257#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
258#define S_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKE64(48) 258#define S_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKE64(48)
259#define M_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKEMASK(2,S_DMA_DSCRB_PKT_SIZE_MSB) 259#define M_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKEMASK(2, S_DMA_DSCRB_PKT_SIZE_MSB)
260#define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB) 260#define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_PKT_SIZE_MSB)
261#define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB,M_DMA_DSCRB_PKT_SIZE_MSB) 261#define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x, S_DMA_DSCRB_PKT_SIZE_MSB, M_DMA_DSCRB_PKT_SIZE_MSB)
262#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 262#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
263 263
264#define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50) 264#define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50)
265#define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_PKT_SIZE) 265#define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14, S_DMA_DSCRB_PKT_SIZE)
266#define V_DMA_DSCRB_PKT_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE) 266#define V_DMA_DSCRB_PKT_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_PKT_SIZE)
267#define G_DMA_DSCRB_PKT_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE,M_DMA_DSCRB_PKT_SIZE) 267#define G_DMA_DSCRB_PKT_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRB_PKT_SIZE, M_DMA_DSCRB_PKT_SIZE)
268 268
269/* 269/*
270 * from pass2 some bits in dscr_b are also used for rx status 270 * from pass2 some bits in dscr_b are also used for rx status
271 */ 271 */
272#define S_DMA_DSCRB_STATUS _SB_MAKE64(0) 272#define S_DMA_DSCRB_STATUS _SB_MAKE64(0)
273#define M_DMA_DSCRB_STATUS _SB_MAKEMASK(1,S_DMA_DSCRB_STATUS) 273#define M_DMA_DSCRB_STATUS _SB_MAKEMASK(1, S_DMA_DSCRB_STATUS)
274#define V_DMA_DSCRB_STATUS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_STATUS) 274#define V_DMA_DSCRB_STATUS(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_STATUS)
275#define G_DMA_DSCRB_STATUS(x) _SB_GETVALUE(x,S_DMA_DSCRB_STATUS,M_DMA_DSCRB_STATUS) 275#define G_DMA_DSCRB_STATUS(x) _SB_GETVALUE(x, S_DMA_DSCRB_STATUS, M_DMA_DSCRB_STATUS)
276 276
277/* 277/*
278 * Ethernet Descriptor Status Bits (Table 7-15) 278 * Ethernet Descriptor Status Bits (Table 7-15)
@@ -293,14 +293,14 @@
293#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 293#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
294 294
295#define S_DMA_ETHRX_RXCH 53 295#define S_DMA_ETHRX_RXCH 53
296#define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2,S_DMA_ETHRX_RXCH) 296#define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2, S_DMA_ETHRX_RXCH)
297#define V_DMA_ETHRX_RXCH(x) _SB_MAKEVALUE(x,S_DMA_ETHRX_RXCH) 297#define V_DMA_ETHRX_RXCH(x) _SB_MAKEVALUE(x, S_DMA_ETHRX_RXCH)
298#define G_DMA_ETHRX_RXCH(x) _SB_GETVALUE(x,S_DMA_ETHRX_RXCH,M_DMA_ETHRX_RXCH) 298#define G_DMA_ETHRX_RXCH(x) _SB_GETVALUE(x, S_DMA_ETHRX_RXCH, M_DMA_ETHRX_RXCH)
299 299
300#define S_DMA_ETHRX_PKTTYPE 55 300#define S_DMA_ETHRX_PKTTYPE 55
301#define M_DMA_ETHRX_PKTTYPE _SB_MAKEMASK(3,S_DMA_ETHRX_PKTTYPE) 301#define M_DMA_ETHRX_PKTTYPE _SB_MAKEMASK(3, S_DMA_ETHRX_PKTTYPE)
302#define V_DMA_ETHRX_PKTTYPE(x) _SB_MAKEVALUE(x,S_DMA_ETHRX_PKTTYPE) 302#define V_DMA_ETHRX_PKTTYPE(x) _SB_MAKEVALUE(x, S_DMA_ETHRX_PKTTYPE)
303#define G_DMA_ETHRX_PKTTYPE(x) _SB_GETVALUE(x,S_DMA_ETHRX_PKTTYPE,M_DMA_ETHRX_PKTTYPE) 303#define G_DMA_ETHRX_PKTTYPE(x) _SB_GETVALUE(x, S_DMA_ETHRX_PKTTYPE, M_DMA_ETHRX_PKTTYPE)
304 304
305#define K_DMA_ETHRX_PKTTYPE_IPV4 0 305#define K_DMA_ETHRX_PKTTYPE_IPV4 0
306#define K_DMA_ETHRX_PKTTYPE_ARPV4 1 306#define K_DMA_ETHRX_PKTTYPE_ARPV4 1
@@ -385,21 +385,21 @@
385 * Register: DM_DSCR_BASE_3 385 * Register: DM_DSCR_BASE_3
386 */ 386 */
387 387
388#define M_DM_DSCR_BASE_MBZ _SB_MAKEMASK(4,0) 388#define M_DM_DSCR_BASE_MBZ _SB_MAKEMASK(4, 0)
389 389
390/* Note: Just mask the base address and then OR it in. */ 390/* Note: Just mask the base address and then OR it in. */
391#define S_DM_DSCR_BASE_ADDR _SB_MAKE64(4) 391#define S_DM_DSCR_BASE_ADDR _SB_MAKE64(4)
392#define M_DM_DSCR_BASE_ADDR _SB_MAKEMASK(36,S_DM_DSCR_BASE_ADDR) 392#define M_DM_DSCR_BASE_ADDR _SB_MAKEMASK(36, S_DM_DSCR_BASE_ADDR)
393 393
394#define S_DM_DSCR_BASE_RINGSZ _SB_MAKE64(40) 394#define S_DM_DSCR_BASE_RINGSZ _SB_MAKE64(40)
395#define M_DM_DSCR_BASE_RINGSZ _SB_MAKEMASK(16,S_DM_DSCR_BASE_RINGSZ) 395#define M_DM_DSCR_BASE_RINGSZ _SB_MAKEMASK(16, S_DM_DSCR_BASE_RINGSZ)
396#define V_DM_DSCR_BASE_RINGSZ(x) _SB_MAKEVALUE(x,S_DM_DSCR_BASE_RINGSZ) 396#define V_DM_DSCR_BASE_RINGSZ(x) _SB_MAKEVALUE(x, S_DM_DSCR_BASE_RINGSZ)
397#define G_DM_DSCR_BASE_RINGSZ(x) _SB_GETVALUE(x,S_DM_DSCR_BASE_RINGSZ,M_DM_DSCR_BASE_RINGSZ) 397#define G_DM_DSCR_BASE_RINGSZ(x) _SB_GETVALUE(x, S_DM_DSCR_BASE_RINGSZ, M_DM_DSCR_BASE_RINGSZ)
398 398
399#define S_DM_DSCR_BASE_PRIORITY _SB_MAKE64(56) 399#define S_DM_DSCR_BASE_PRIORITY _SB_MAKE64(56)
400#define M_DM_DSCR_BASE_PRIORITY _SB_MAKEMASK(3,S_DM_DSCR_BASE_PRIORITY) 400#define M_DM_DSCR_BASE_PRIORITY _SB_MAKEMASK(3, S_DM_DSCR_BASE_PRIORITY)
401#define V_DM_DSCR_BASE_PRIORITY(x) _SB_MAKEVALUE(x,S_DM_DSCR_BASE_PRIORITY) 401#define V_DM_DSCR_BASE_PRIORITY(x) _SB_MAKEVALUE(x, S_DM_DSCR_BASE_PRIORITY)
402#define G_DM_DSCR_BASE_PRIORITY(x) _SB_GETVALUE(x,S_DM_DSCR_BASE_PRIORITY,M_DM_DSCR_BASE_PRIORITY) 402#define G_DM_DSCR_BASE_PRIORITY(x) _SB_GETVALUE(x, S_DM_DSCR_BASE_PRIORITY, M_DM_DSCR_BASE_PRIORITY)
403 403
404#define K_DM_DSCR_BASE_PRIORITY_1 0 404#define K_DM_DSCR_BASE_PRIORITY_1 0
405#define K_DM_DSCR_BASE_PRIORITY_2 1 405#define K_DM_DSCR_BASE_PRIORITY_2 1
@@ -429,12 +429,12 @@
429 */ 429 */
430 430
431#define S_DM_CUR_DSCR_DSCR_ADDR _SB_MAKE64(0) 431#define S_DM_CUR_DSCR_DSCR_ADDR _SB_MAKE64(0)
432#define M_DM_CUR_DSCR_DSCR_ADDR _SB_MAKEMASK(40,S_DM_CUR_DSCR_DSCR_ADDR) 432#define M_DM_CUR_DSCR_DSCR_ADDR _SB_MAKEMASK(40, S_DM_CUR_DSCR_DSCR_ADDR)
433 433
434#define S_DM_CUR_DSCR_DSCR_COUNT _SB_MAKE64(48) 434#define S_DM_CUR_DSCR_DSCR_COUNT _SB_MAKE64(48)
435#define M_DM_CUR_DSCR_DSCR_COUNT _SB_MAKEMASK(16,S_DM_CUR_DSCR_DSCR_COUNT) 435#define M_DM_CUR_DSCR_DSCR_COUNT _SB_MAKEMASK(16, S_DM_CUR_DSCR_DSCR_COUNT)
436#define V_DM_CUR_DSCR_DSCR_COUNT(r) _SB_MAKEVALUE(r,S_DM_CUR_DSCR_DSCR_COUNT) 436#define V_DM_CUR_DSCR_DSCR_COUNT(r) _SB_MAKEVALUE(r, S_DM_CUR_DSCR_DSCR_COUNT)
437#define G_DM_CUR_DSCR_DSCR_COUNT(r) _SB_GETVALUE(r,S_DM_CUR_DSCR_DSCR_COUNT,\ 437#define G_DM_CUR_DSCR_DSCR_COUNT(r) _SB_GETVALUE(r, S_DM_CUR_DSCR_DSCR_COUNT,\
438 M_DM_CUR_DSCR_DSCR_COUNT) 438 M_DM_CUR_DSCR_DSCR_COUNT)
439 439
440 440
@@ -447,15 +447,15 @@
447 * Register: DM_PARTIAL_3 447 * Register: DM_PARTIAL_3
448 */ 448 */
449#define S_DM_PARTIAL_CRC_PARTIAL _SB_MAKE64(0) 449#define S_DM_PARTIAL_CRC_PARTIAL _SB_MAKE64(0)
450#define M_DM_PARTIAL_CRC_PARTIAL _SB_MAKEMASK(32,S_DM_PARTIAL_CRC_PARTIAL) 450#define M_DM_PARTIAL_CRC_PARTIAL _SB_MAKEMASK(32, S_DM_PARTIAL_CRC_PARTIAL)
451#define V_DM_PARTIAL_CRC_PARTIAL(r) _SB_MAKEVALUE(r,S_DM_PARTIAL_CRC_PARTIAL) 451#define V_DM_PARTIAL_CRC_PARTIAL(r) _SB_MAKEVALUE(r, S_DM_PARTIAL_CRC_PARTIAL)
452#define G_DM_PARTIAL_CRC_PARTIAL(r) _SB_GETVALUE(r,S_DM_PARTIAL_CRC_PARTIAL,\ 452#define G_DM_PARTIAL_CRC_PARTIAL(r) _SB_GETVALUE(r, S_DM_PARTIAL_CRC_PARTIAL,\
453 M_DM_PARTIAL_CRC_PARTIAL) 453 M_DM_PARTIAL_CRC_PARTIAL)
454 454
455#define S_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKE64(32) 455#define S_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKE64(32)
456#define M_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKEMASK(16,S_DM_PARTIAL_TCPCS_PARTIAL) 456#define M_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKEMASK(16, S_DM_PARTIAL_TCPCS_PARTIAL)
457#define V_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_MAKEVALUE(r,S_DM_PARTIAL_TCPCS_PARTIAL) 457#define V_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_MAKEVALUE(r, S_DM_PARTIAL_TCPCS_PARTIAL)
458#define G_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_GETVALUE(r,S_DM_PARTIAL_TCPCS_PARTIAL,\ 458#define G_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_GETVALUE(r, S_DM_PARTIAL_TCPCS_PARTIAL,\
459 M_DM_PARTIAL_TCPCS_PARTIAL) 459 M_DM_PARTIAL_TCPCS_PARTIAL)
460 460
461#define M_DM_PARTIAL_ODD_BYTE _SB_MAKEMASK1(48) 461#define M_DM_PARTIAL_ODD_BYTE _SB_MAKEMASK1(48)
@@ -469,15 +469,15 @@
469 * Register: CRC_DEF_1 469 * Register: CRC_DEF_1
470 */ 470 */
471#define S_CRC_DEF_CRC_INIT _SB_MAKE64(0) 471#define S_CRC_DEF_CRC_INIT _SB_MAKE64(0)
472#define M_CRC_DEF_CRC_INIT _SB_MAKEMASK(32,S_CRC_DEF_CRC_INIT) 472#define M_CRC_DEF_CRC_INIT _SB_MAKEMASK(32, S_CRC_DEF_CRC_INIT)
473#define V_CRC_DEF_CRC_INIT(r) _SB_MAKEVALUE(r,S_CRC_DEF_CRC_INIT) 473#define V_CRC_DEF_CRC_INIT(r) _SB_MAKEVALUE(r, S_CRC_DEF_CRC_INIT)
474#define G_CRC_DEF_CRC_INIT(r) _SB_GETVALUE(r,S_CRC_DEF_CRC_INIT,\ 474#define G_CRC_DEF_CRC_INIT(r) _SB_GETVALUE(r, S_CRC_DEF_CRC_INIT,\
475 M_CRC_DEF_CRC_INIT) 475 M_CRC_DEF_CRC_INIT)
476 476
477#define S_CRC_DEF_CRC_POLY _SB_MAKE64(32) 477#define S_CRC_DEF_CRC_POLY _SB_MAKE64(32)
478#define M_CRC_DEF_CRC_POLY _SB_MAKEMASK(32,S_CRC_DEF_CRC_POLY) 478#define M_CRC_DEF_CRC_POLY _SB_MAKEMASK(32, S_CRC_DEF_CRC_POLY)
479#define V_CRC_DEF_CRC_POLY(r) _SB_MAKEVALUE(r,S_CRC_DEF_CRC_POLY) 479#define V_CRC_DEF_CRC_POLY(r) _SB_MAKEVALUE(r, S_CRC_DEF_CRC_POLY)
480#define G_CRC_DEF_CRC_POLY(r) _SB_GETVALUE(r,S_CRC_DEF_CRC_POLY,\ 480#define G_CRC_DEF_CRC_POLY(r) _SB_GETVALUE(r, S_CRC_DEF_CRC_POLY,\
481 M_CRC_DEF_CRC_POLY) 481 M_CRC_DEF_CRC_POLY)
482#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 482#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
483 483
@@ -489,21 +489,21 @@
489 * Register: CTCP_DEF_1 489 * Register: CTCP_DEF_1
490 */ 490 */
491#define S_CTCP_DEF_CRC_TXOR _SB_MAKE64(0) 491#define S_CTCP_DEF_CRC_TXOR _SB_MAKE64(0)
492#define M_CTCP_DEF_CRC_TXOR _SB_MAKEMASK(32,S_CTCP_DEF_CRC_TXOR) 492#define M_CTCP_DEF_CRC_TXOR _SB_MAKEMASK(32, S_CTCP_DEF_CRC_TXOR)
493#define V_CTCP_DEF_CRC_TXOR(r) _SB_MAKEVALUE(r,S_CTCP_DEF_CRC_TXOR) 493#define V_CTCP_DEF_CRC_TXOR(r) _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_TXOR)
494#define G_CTCP_DEF_CRC_TXOR(r) _SB_GETVALUE(r,S_CTCP_DEF_CRC_TXOR,\ 494#define G_CTCP_DEF_CRC_TXOR(r) _SB_GETVALUE(r, S_CTCP_DEF_CRC_TXOR,\
495 M_CTCP_DEF_CRC_TXOR) 495 M_CTCP_DEF_CRC_TXOR)
496 496
497#define S_CTCP_DEF_TCPCS_INIT _SB_MAKE64(32) 497#define S_CTCP_DEF_TCPCS_INIT _SB_MAKE64(32)
498#define M_CTCP_DEF_TCPCS_INIT _SB_MAKEMASK(16,S_CTCP_DEF_TCPCS_INIT) 498#define M_CTCP_DEF_TCPCS_INIT _SB_MAKEMASK(16, S_CTCP_DEF_TCPCS_INIT)
499#define V_CTCP_DEF_TCPCS_INIT(r) _SB_MAKEVALUE(r,S_CTCP_DEF_TCPCS_INIT) 499#define V_CTCP_DEF_TCPCS_INIT(r) _SB_MAKEVALUE(r, S_CTCP_DEF_TCPCS_INIT)
500#define G_CTCP_DEF_TCPCS_INIT(r) _SB_GETVALUE(r,S_CTCP_DEF_TCPCS_INIT,\ 500#define G_CTCP_DEF_TCPCS_INIT(r) _SB_GETVALUE(r, S_CTCP_DEF_TCPCS_INIT,\
501 M_CTCP_DEF_TCPCS_INIT) 501 M_CTCP_DEF_TCPCS_INIT)
502 502
503#define S_CTCP_DEF_CRC_WIDTH _SB_MAKE64(48) 503#define S_CTCP_DEF_CRC_WIDTH _SB_MAKE64(48)
504#define M_CTCP_DEF_CRC_WIDTH _SB_MAKEMASK(2,S_CTCP_DEF_CRC_WIDTH) 504#define M_CTCP_DEF_CRC_WIDTH _SB_MAKEMASK(2, S_CTCP_DEF_CRC_WIDTH)
505#define V_CTCP_DEF_CRC_WIDTH(r) _SB_MAKEVALUE(r,S_CTCP_DEF_CRC_WIDTH) 505#define V_CTCP_DEF_CRC_WIDTH(r) _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_WIDTH)
506#define G_CTCP_DEF_CRC_WIDTH(r) _SB_GETVALUE(r,S_CTCP_DEF_CRC_WIDTH,\ 506#define G_CTCP_DEF_CRC_WIDTH(r) _SB_GETVALUE(r, S_CTCP_DEF_CRC_WIDTH,\
507 M_CTCP_DEF_CRC_WIDTH) 507 M_CTCP_DEF_CRC_WIDTH)
508 508
509#define K_CTCP_DEF_CRC_WIDTH_4 0 509#define K_CTCP_DEF_CRC_WIDTH_4 0
@@ -519,7 +519,7 @@
519 */ 519 */
520 520
521#define S_DM_DSCRA_DST_ADDR _SB_MAKE64(0) 521#define S_DM_DSCRA_DST_ADDR _SB_MAKE64(0)
522#define M_DM_DSCRA_DST_ADDR _SB_MAKEMASK(40,S_DM_DSCRA_DST_ADDR) 522#define M_DM_DSCRA_DST_ADDR _SB_MAKEMASK(40, S_DM_DSCRA_DST_ADDR)
523 523
524#define M_DM_DSCRA_UN_DEST _SB_MAKEMASK1(40) 524#define M_DM_DSCRA_UN_DEST _SB_MAKEMASK1(40)
525#define M_DM_DSCRA_UN_SRC _SB_MAKEMASK1(41) 525#define M_DM_DSCRA_UN_SRC _SB_MAKEMASK1(41)
@@ -529,30 +529,30 @@
529#endif /* up to 1250 PASS1 */ 529#endif /* up to 1250 PASS1 */
530 530
531#define S_DM_DSCRA_DIR_DEST _SB_MAKE64(44) 531#define S_DM_DSCRA_DIR_DEST _SB_MAKE64(44)
532#define M_DM_DSCRA_DIR_DEST _SB_MAKEMASK(2,S_DM_DSCRA_DIR_DEST) 532#define M_DM_DSCRA_DIR_DEST _SB_MAKEMASK(2, S_DM_DSCRA_DIR_DEST)
533#define V_DM_DSCRA_DIR_DEST(x) _SB_MAKEVALUE(x,S_DM_DSCRA_DIR_DEST) 533#define V_DM_DSCRA_DIR_DEST(x) _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_DEST)
534#define G_DM_DSCRA_DIR_DEST(x) _SB_GETVALUE(x,S_DM_DSCRA_DIR_DEST,M_DM_DSCRA_DIR_DEST) 534#define G_DM_DSCRA_DIR_DEST(x) _SB_GETVALUE(x, S_DM_DSCRA_DIR_DEST, M_DM_DSCRA_DIR_DEST)
535 535
536#define K_DM_DSCRA_DIR_DEST_INCR 0 536#define K_DM_DSCRA_DIR_DEST_INCR 0
537#define K_DM_DSCRA_DIR_DEST_DECR 1 537#define K_DM_DSCRA_DIR_DEST_DECR 1
538#define K_DM_DSCRA_DIR_DEST_CONST 2 538#define K_DM_DSCRA_DIR_DEST_CONST 2
539 539
540#define V_DM_DSCRA_DIR_DEST_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_INCR,S_DM_DSCRA_DIR_DEST) 540#define V_DM_DSCRA_DIR_DEST_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_INCR, S_DM_DSCRA_DIR_DEST)
541#define V_DM_DSCRA_DIR_DEST_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_DECR,S_DM_DSCRA_DIR_DEST) 541#define V_DM_DSCRA_DIR_DEST_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_DECR, S_DM_DSCRA_DIR_DEST)
542#define V_DM_DSCRA_DIR_DEST_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_CONST,S_DM_DSCRA_DIR_DEST) 542#define V_DM_DSCRA_DIR_DEST_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_CONST, S_DM_DSCRA_DIR_DEST)
543 543
544#define S_DM_DSCRA_DIR_SRC _SB_MAKE64(46) 544#define S_DM_DSCRA_DIR_SRC _SB_MAKE64(46)
545#define M_DM_DSCRA_DIR_SRC _SB_MAKEMASK(2,S_DM_DSCRA_DIR_SRC) 545#define M_DM_DSCRA_DIR_SRC _SB_MAKEMASK(2, S_DM_DSCRA_DIR_SRC)
546#define V_DM_DSCRA_DIR_SRC(x) _SB_MAKEVALUE(x,S_DM_DSCRA_DIR_SRC) 546#define V_DM_DSCRA_DIR_SRC(x) _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_SRC)
547#define G_DM_DSCRA_DIR_SRC(x) _SB_GETVALUE(x,S_DM_DSCRA_DIR_SRC,M_DM_DSCRA_DIR_SRC) 547#define G_DM_DSCRA_DIR_SRC(x) _SB_GETVALUE(x, S_DM_DSCRA_DIR_SRC, M_DM_DSCRA_DIR_SRC)
548 548
549#define K_DM_DSCRA_DIR_SRC_INCR 0 549#define K_DM_DSCRA_DIR_SRC_INCR 0
550#define K_DM_DSCRA_DIR_SRC_DECR 1 550#define K_DM_DSCRA_DIR_SRC_DECR 1
551#define K_DM_DSCRA_DIR_SRC_CONST 2 551#define K_DM_DSCRA_DIR_SRC_CONST 2
552 552
553#define V_DM_DSCRA_DIR_SRC_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_INCR,S_DM_DSCRA_DIR_SRC) 553#define V_DM_DSCRA_DIR_SRC_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_INCR, S_DM_DSCRA_DIR_SRC)
554#define V_DM_DSCRA_DIR_SRC_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_DECR,S_DM_DSCRA_DIR_SRC) 554#define V_DM_DSCRA_DIR_SRC_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_DECR, S_DM_DSCRA_DIR_SRC)
555#define V_DM_DSCRA_DIR_SRC_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_CONST,S_DM_DSCRA_DIR_SRC) 555#define V_DM_DSCRA_DIR_SRC_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_CONST, S_DM_DSCRA_DIR_SRC)
556 556
557 557
558#define M_DM_DSCRA_ZERO_MEM _SB_MAKEMASK1(48) 558#define M_DM_DSCRA_ZERO_MEM _SB_MAKEMASK1(48)
@@ -576,19 +576,19 @@
576#define M_DM_DSCRA_CRC_XBIT _SB_MAKEMASK1(61) 576#define M_DM_DSCRA_CRC_XBIT _SB_MAKEMASK1(61)
577#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 577#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
578 578
579#define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(3,61) 579#define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(3, 61)
580 580
581/* 581/*
582 * Data Mover Descriptor Doubleword "B" (Table 7-25) 582 * Data Mover Descriptor Doubleword "B" (Table 7-25)
583 */ 583 */
584 584
585#define S_DM_DSCRB_SRC_ADDR _SB_MAKE64(0) 585#define S_DM_DSCRB_SRC_ADDR _SB_MAKE64(0)
586#define M_DM_DSCRB_SRC_ADDR _SB_MAKEMASK(40,S_DM_DSCRB_SRC_ADDR) 586#define M_DM_DSCRB_SRC_ADDR _SB_MAKEMASK(40, S_DM_DSCRB_SRC_ADDR)
587 587
588#define S_DM_DSCRB_SRC_LENGTH _SB_MAKE64(40) 588#define S_DM_DSCRB_SRC_LENGTH _SB_MAKE64(40)
589#define M_DM_DSCRB_SRC_LENGTH _SB_MAKEMASK(20,S_DM_DSCRB_SRC_LENGTH) 589#define M_DM_DSCRB_SRC_LENGTH _SB_MAKEMASK(20, S_DM_DSCRB_SRC_LENGTH)
590#define V_DM_DSCRB_SRC_LENGTH(x) _SB_MAKEVALUE(x,S_DM_DSCRB_SRC_LENGTH) 590#define V_DM_DSCRB_SRC_LENGTH(x) _SB_MAKEVALUE(x, S_DM_DSCRB_SRC_LENGTH)
591#define G_DM_DSCRB_SRC_LENGTH(x) _SB_GETVALUE(x,S_DM_DSCRB_SRC_LENGTH,M_DM_DSCRB_SRC_LENGTH) 591#define G_DM_DSCRB_SRC_LENGTH(x) _SB_GETVALUE(x, S_DM_DSCRB_SRC_LENGTH, M_DM_DSCRB_SRC_LENGTH)
592 592
593 593
594#endif 594#endif
diff --git a/include/asm-mips/sibyte/sb1250_genbus.h b/include/asm-mips/sibyte/sb1250_genbus.h
index 1b5cbc5c6454..94e9c7c8e783 100644
--- a/include/asm-mips/sibyte/sb1250_genbus.h
+++ b/include/asm-mips/sibyte/sb1250_genbus.h
@@ -11,7 +11,7 @@
11 * 11 *
12 ********************************************************************* 12 *********************************************************************
13 * 13 *
14 * Copyright 2000,2001,2002,2003 14 * Copyright 2000, 2001, 2002, 2003
15 * Broadcom Corporation. All rights reserved. 15 * Broadcom Corporation. All rights reserved.
16 * 16 *
17 * This program is free software; you can redistribute it and/or 17 * This program is free software; you can redistribute it and/or
@@ -47,7 +47,7 @@
47#define M_IO_ENA_RDY _SB_MAKEMASK1(S_IO_ENA_RDY) 47#define M_IO_ENA_RDY _SB_MAKEMASK1(S_IO_ENA_RDY)
48 48
49#define S_IO_WIDTH_SEL 2 49#define S_IO_WIDTH_SEL 2
50#define M_IO_WIDTH_SEL _SB_MAKEMASK(2,S_IO_WIDTH_SEL) 50#define M_IO_WIDTH_SEL _SB_MAKEMASK(2, S_IO_WIDTH_SEL)
51#define K_IO_WIDTH_SEL_1 0 51#define K_IO_WIDTH_SEL_1 0
52#define K_IO_WIDTH_SEL_2 1 52#define K_IO_WIDTH_SEL_2 1
53#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ 53#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
@@ -55,8 +55,8 @@
55#define K_IO_WIDTH_SEL_1L 2 55#define K_IO_WIDTH_SEL_1L 2
56#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 56#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
57#define K_IO_WIDTH_SEL_4 3 57#define K_IO_WIDTH_SEL_4 3
58#define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x,S_IO_WIDTH_SEL) 58#define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x, S_IO_WIDTH_SEL)
59#define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x,S_IO_WIDTH_SEL,M_IO_WIDTH_SEL) 59#define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x, S_IO_WIDTH_SEL, M_IO_WIDTH_SEL)
60 60
61#define S_IO_PARITY_ENA 4 61#define S_IO_PARITY_ENA 4
62#define M_IO_PARITY_ENA _SB_MAKEMASK1(S_IO_PARITY_ENA) 62#define M_IO_PARITY_ENA _SB_MAKEMASK1(S_IO_PARITY_ENA)
@@ -71,18 +71,18 @@
71#define M_IO_NONMUX _SB_MAKEMASK1(S_IO_NONMUX) 71#define M_IO_NONMUX _SB_MAKEMASK1(S_IO_NONMUX)
72 72
73#define S_IO_TIMEOUT 8 73#define S_IO_TIMEOUT 8
74#define M_IO_TIMEOUT _SB_MAKEMASK(8,S_IO_TIMEOUT) 74#define M_IO_TIMEOUT _SB_MAKEMASK(8, S_IO_TIMEOUT)
75#define V_IO_TIMEOUT(x) _SB_MAKEVALUE(x,S_IO_TIMEOUT) 75#define V_IO_TIMEOUT(x) _SB_MAKEVALUE(x, S_IO_TIMEOUT)
76#define G_IO_TIMEOUT(x) _SB_GETVALUE(x,S_IO_TIMEOUT,M_IO_TIMEOUT) 76#define G_IO_TIMEOUT(x) _SB_GETVALUE(x, S_IO_TIMEOUT, M_IO_TIMEOUT)
77 77
78/* 78/*
79 * Generic Bus Region Size register (Table 11-5) 79 * Generic Bus Region Size register (Table 11-5)
80 */ 80 */
81 81
82#define S_IO_MULT_SIZE 0 82#define S_IO_MULT_SIZE 0
83#define M_IO_MULT_SIZE _SB_MAKEMASK(12,S_IO_MULT_SIZE) 83#define M_IO_MULT_SIZE _SB_MAKEMASK(12, S_IO_MULT_SIZE)
84#define V_IO_MULT_SIZE(x) _SB_MAKEVALUE(x,S_IO_MULT_SIZE) 84#define V_IO_MULT_SIZE(x) _SB_MAKEVALUE(x, S_IO_MULT_SIZE)
85#define G_IO_MULT_SIZE(x) _SB_GETVALUE(x,S_IO_MULT_SIZE,M_IO_MULT_SIZE) 85#define G_IO_MULT_SIZE(x) _SB_GETVALUE(x, S_IO_MULT_SIZE, M_IO_MULT_SIZE)
86 86
87#define S_IO_REGSIZE 16 /* # bits to shift size for this reg */ 87#define S_IO_REGSIZE 16 /* # bits to shift size for this reg */
88 88
@@ -91,9 +91,9 @@
91 */ 91 */
92 92
93#define S_IO_START_ADDR 0 93#define S_IO_START_ADDR 0
94#define M_IO_START_ADDR _SB_MAKEMASK(14,S_IO_START_ADDR) 94#define M_IO_START_ADDR _SB_MAKEMASK(14, S_IO_START_ADDR)
95#define V_IO_START_ADDR(x) _SB_MAKEVALUE(x,S_IO_START_ADDR) 95#define V_IO_START_ADDR(x) _SB_MAKEVALUE(x, S_IO_START_ADDR)
96#define G_IO_START_ADDR(x) _SB_GETVALUE(x,S_IO_START_ADDR,M_IO_START_ADDR) 96#define G_IO_START_ADDR(x) _SB_GETVALUE(x, S_IO_START_ADDR, M_IO_START_ADDR)
97 97
98#define S_IO_ADDRBASE 16 /* # bits to shift addr for this reg */ 98#define S_IO_ADDRBASE 16 /* # bits to shift addr for this reg */
99 99
@@ -105,9 +105,9 @@
105 */ 105 */
106 106
107#define S_IO_ALE_WIDTH 0 107#define S_IO_ALE_WIDTH 0
108#define M_IO_ALE_WIDTH _SB_MAKEMASK(3,S_IO_ALE_WIDTH) 108#define M_IO_ALE_WIDTH _SB_MAKEMASK(3, S_IO_ALE_WIDTH)
109#define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_ALE_WIDTH) 109#define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x, S_IO_ALE_WIDTH)
110#define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x,S_IO_ALE_WIDTH,M_IO_ALE_WIDTH) 110#define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x, S_IO_ALE_WIDTH, M_IO_ALE_WIDTH)
111 111
112#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ 112#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
113 || SIBYTE_HDR_FEATURE_CHIP(1480) 113 || SIBYTE_HDR_FEATURE_CHIP(1480)
@@ -115,27 +115,27 @@
115#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 115#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
116 116
117#define S_IO_ALE_TO_CS 4 117#define S_IO_ALE_TO_CS 4
118#define M_IO_ALE_TO_CS _SB_MAKEMASK(2,S_IO_ALE_TO_CS) 118#define M_IO_ALE_TO_CS _SB_MAKEMASK(2, S_IO_ALE_TO_CS)
119#define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_CS) 119#define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x, S_IO_ALE_TO_CS)
120#define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x,S_IO_ALE_TO_CS,M_IO_ALE_TO_CS) 120#define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x, S_IO_ALE_TO_CS, M_IO_ALE_TO_CS)
121 121
122#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ 122#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
123 || SIBYTE_HDR_FEATURE_CHIP(1480) 123 || SIBYTE_HDR_FEATURE_CHIP(1480)
124#define S_IO_BURST_WIDTH _SB_MAKE64(6) 124#define S_IO_BURST_WIDTH _SB_MAKE64(6)
125#define M_IO_BURST_WIDTH _SB_MAKEMASK(2,S_IO_BURST_WIDTH) 125#define M_IO_BURST_WIDTH _SB_MAKEMASK(2, S_IO_BURST_WIDTH)
126#define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x,S_IO_BURST_WIDTH) 126#define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x, S_IO_BURST_WIDTH)
127#define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x,S_IO_BURST_WIDTH,M_IO_BURST_WIDTH) 127#define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x, S_IO_BURST_WIDTH, M_IO_BURST_WIDTH)
128#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 128#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
129 129
130#define S_IO_CS_WIDTH 8 130#define S_IO_CS_WIDTH 8
131#define M_IO_CS_WIDTH _SB_MAKEMASK(5,S_IO_CS_WIDTH) 131#define M_IO_CS_WIDTH _SB_MAKEMASK(5, S_IO_CS_WIDTH)
132#define V_IO_CS_WIDTH(x) _SB_MAKEVALUE(x,S_IO_CS_WIDTH) 132#define V_IO_CS_WIDTH(x) _SB_MAKEVALUE(x, S_IO_CS_WIDTH)
133#define G_IO_CS_WIDTH(x) _SB_GETVALUE(x,S_IO_CS_WIDTH,M_IO_CS_WIDTH) 133#define G_IO_CS_WIDTH(x) _SB_GETVALUE(x, S_IO_CS_WIDTH, M_IO_CS_WIDTH)
134 134
135#define S_IO_RDY_SMPLE 13 135#define S_IO_RDY_SMPLE 13
136#define M_IO_RDY_SMPLE _SB_MAKEMASK(3,S_IO_RDY_SMPLE) 136#define M_IO_RDY_SMPLE _SB_MAKEMASK(3, S_IO_RDY_SMPLE)
137#define V_IO_RDY_SMPLE(x) _SB_MAKEVALUE(x,S_IO_RDY_SMPLE) 137#define V_IO_RDY_SMPLE(x) _SB_MAKEVALUE(x, S_IO_RDY_SMPLE)
138#define G_IO_RDY_SMPLE(x) _SB_GETVALUE(x,S_IO_RDY_SMPLE,M_IO_RDY_SMPLE) 138#define G_IO_RDY_SMPLE(x) _SB_GETVALUE(x, S_IO_RDY_SMPLE, M_IO_RDY_SMPLE)
139 139
140 140
141/* 141/*
@@ -143,9 +143,9 @@
143 */ 143 */
144 144
145#define S_IO_ALE_TO_WRITE 0 145#define S_IO_ALE_TO_WRITE 0
146#define M_IO_ALE_TO_WRITE _SB_MAKEMASK(3,S_IO_ALE_TO_WRITE) 146#define M_IO_ALE_TO_WRITE _SB_MAKEMASK(3, S_IO_ALE_TO_WRITE)
147#define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_WRITE) 147#define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x, S_IO_ALE_TO_WRITE)
148#define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x,S_IO_ALE_TO_WRITE,M_IO_ALE_TO_WRITE) 148#define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x, S_IO_ALE_TO_WRITE, M_IO_ALE_TO_WRITE)
149 149
150#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ 150#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
151 || SIBYTE_HDR_FEATURE_CHIP(1480) 151 || SIBYTE_HDR_FEATURE_CHIP(1480)
@@ -153,30 +153,30 @@
153#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 153#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
154 154
155#define S_IO_WRITE_WIDTH 4 155#define S_IO_WRITE_WIDTH 4
156#define M_IO_WRITE_WIDTH _SB_MAKEMASK(4,S_IO_WRITE_WIDTH) 156#define M_IO_WRITE_WIDTH _SB_MAKEMASK(4, S_IO_WRITE_WIDTH)
157#define V_IO_WRITE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_WRITE_WIDTH) 157#define V_IO_WRITE_WIDTH(x) _SB_MAKEVALUE(x, S_IO_WRITE_WIDTH)
158#define G_IO_WRITE_WIDTH(x) _SB_GETVALUE(x,S_IO_WRITE_WIDTH,M_IO_WRITE_WIDTH) 158#define G_IO_WRITE_WIDTH(x) _SB_GETVALUE(x, S_IO_WRITE_WIDTH, M_IO_WRITE_WIDTH)
159 159
160#define S_IO_IDLE_CYCLE 8 160#define S_IO_IDLE_CYCLE 8
161#define M_IO_IDLE_CYCLE _SB_MAKEMASK(4,S_IO_IDLE_CYCLE) 161#define M_IO_IDLE_CYCLE _SB_MAKEMASK(4, S_IO_IDLE_CYCLE)
162#define V_IO_IDLE_CYCLE(x) _SB_MAKEVALUE(x,S_IO_IDLE_CYCLE) 162#define V_IO_IDLE_CYCLE(x) _SB_MAKEVALUE(x, S_IO_IDLE_CYCLE)
163#define G_IO_IDLE_CYCLE(x) _SB_GETVALUE(x,S_IO_IDLE_CYCLE,M_IO_IDLE_CYCLE) 163#define G_IO_IDLE_CYCLE(x) _SB_GETVALUE(x, S_IO_IDLE_CYCLE, M_IO_IDLE_CYCLE)
164 164
165#define S_IO_OE_TO_CS 12 165#define S_IO_OE_TO_CS 12
166#define M_IO_OE_TO_CS _SB_MAKEMASK(2,S_IO_OE_TO_CS) 166#define M_IO_OE_TO_CS _SB_MAKEMASK(2, S_IO_OE_TO_CS)
167#define V_IO_OE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_OE_TO_CS) 167#define V_IO_OE_TO_CS(x) _SB_MAKEVALUE(x, S_IO_OE_TO_CS)
168#define G_IO_OE_TO_CS(x) _SB_GETVALUE(x,S_IO_OE_TO_CS,M_IO_OE_TO_CS) 168#define G_IO_OE_TO_CS(x) _SB_GETVALUE(x, S_IO_OE_TO_CS, M_IO_OE_TO_CS)
169 169
170#define S_IO_CS_TO_OE 14 170#define S_IO_CS_TO_OE 14
171#define M_IO_CS_TO_OE _SB_MAKEMASK(2,S_IO_CS_TO_OE) 171#define M_IO_CS_TO_OE _SB_MAKEMASK(2, S_IO_CS_TO_OE)
172#define V_IO_CS_TO_OE(x) _SB_MAKEVALUE(x,S_IO_CS_TO_OE) 172#define V_IO_CS_TO_OE(x) _SB_MAKEVALUE(x, S_IO_CS_TO_OE)
173#define G_IO_CS_TO_OE(x) _SB_GETVALUE(x,S_IO_CS_TO_OE,M_IO_CS_TO_OE) 173#define G_IO_CS_TO_OE(x) _SB_GETVALUE(x, S_IO_CS_TO_OE, M_IO_CS_TO_OE)
174 174
175/* 175/*
176 * Generic Bus Interrupt Status Register (Table 11-9) 176 * Generic Bus Interrupt Status Register (Table 11-9)
177 */ 177 */
178 178
179#define M_IO_CS_ERR_INT _SB_MAKEMASK(0,8) 179#define M_IO_CS_ERR_INT _SB_MAKEMASK(0, 8)
180#define M_IO_CS0_ERR_INT _SB_MAKEMASK1(0) 180#define M_IO_CS0_ERR_INT _SB_MAKEMASK1(0)
181#define M_IO_CS1_ERR_INT _SB_MAKEMASK1(1) 181#define M_IO_CS1_ERR_INT _SB_MAKEMASK1(1)
182#define M_IO_CS2_ERR_INT _SB_MAKEMASK1(2) 182#define M_IO_CS2_ERR_INT _SB_MAKEMASK1(2)
@@ -200,116 +200,116 @@
200 */ 200 */
201 201
202#define S_IO_SLEW0 0 202#define S_IO_SLEW0 0
203#define M_IO_SLEW0 _SB_MAKEMASK(2,S_IO_SLEW0) 203#define M_IO_SLEW0 _SB_MAKEMASK(2, S_IO_SLEW0)
204#define V_IO_SLEW0(x) _SB_MAKEVALUE(x,S_IO_SLEW0) 204#define V_IO_SLEW0(x) _SB_MAKEVALUE(x, S_IO_SLEW0)
205#define G_IO_SLEW0(x) _SB_GETVALUE(x,S_IO_SLEW0,M_IO_SLEW0) 205#define G_IO_SLEW0(x) _SB_GETVALUE(x, S_IO_SLEW0, M_IO_SLEW0)
206 206
207#define S_IO_DRV_A 2 207#define S_IO_DRV_A 2
208#define M_IO_DRV_A _SB_MAKEMASK(2,S_IO_DRV_A) 208#define M_IO_DRV_A _SB_MAKEMASK(2, S_IO_DRV_A)
209#define V_IO_DRV_A(x) _SB_MAKEVALUE(x,S_IO_DRV_A) 209#define V_IO_DRV_A(x) _SB_MAKEVALUE(x, S_IO_DRV_A)
210#define G_IO_DRV_A(x) _SB_GETVALUE(x,S_IO_DRV_A,M_IO_DRV_A) 210#define G_IO_DRV_A(x) _SB_GETVALUE(x, S_IO_DRV_A, M_IO_DRV_A)
211 211
212#define S_IO_DRV_B 6 212#define S_IO_DRV_B 6
213#define M_IO_DRV_B _SB_MAKEMASK(2,S_IO_DRV_B) 213#define M_IO_DRV_B _SB_MAKEMASK(2, S_IO_DRV_B)
214#define V_IO_DRV_B(x) _SB_MAKEVALUE(x,S_IO_DRV_B) 214#define V_IO_DRV_B(x) _SB_MAKEVALUE(x, S_IO_DRV_B)
215#define G_IO_DRV_B(x) _SB_GETVALUE(x,S_IO_DRV_B,M_IO_DRV_B) 215#define G_IO_DRV_B(x) _SB_GETVALUE(x, S_IO_DRV_B, M_IO_DRV_B)
216 216
217#define S_IO_DRV_C 10 217#define S_IO_DRV_C 10
218#define M_IO_DRV_C _SB_MAKEMASK(2,S_IO_DRV_C) 218#define M_IO_DRV_C _SB_MAKEMASK(2, S_IO_DRV_C)
219#define V_IO_DRV_C(x) _SB_MAKEVALUE(x,S_IO_DRV_C) 219#define V_IO_DRV_C(x) _SB_MAKEVALUE(x, S_IO_DRV_C)
220#define G_IO_DRV_C(x) _SB_GETVALUE(x,S_IO_DRV_C,M_IO_DRV_C) 220#define G_IO_DRV_C(x) _SB_GETVALUE(x, S_IO_DRV_C, M_IO_DRV_C)
221 221
222#define S_IO_DRV_D 14 222#define S_IO_DRV_D 14
223#define M_IO_DRV_D _SB_MAKEMASK(2,S_IO_DRV_D) 223#define M_IO_DRV_D _SB_MAKEMASK(2, S_IO_DRV_D)
224#define V_IO_DRV_D(x) _SB_MAKEVALUE(x,S_IO_DRV_D) 224#define V_IO_DRV_D(x) _SB_MAKEVALUE(x, S_IO_DRV_D)
225#define G_IO_DRV_D(x) _SB_GETVALUE(x,S_IO_DRV_D,M_IO_DRV_D) 225#define G_IO_DRV_D(x) _SB_GETVALUE(x, S_IO_DRV_D, M_IO_DRV_D)
226 226
227/* 227/*
228 * Generic Bus Output Drive Control Register 1 (Table 14-19) 228 * Generic Bus Output Drive Control Register 1 (Table 14-19)
229 */ 229 */
230 230
231#define S_IO_DRV_E 2 231#define S_IO_DRV_E 2
232#define M_IO_DRV_E _SB_MAKEMASK(2,S_IO_DRV_E) 232#define M_IO_DRV_E _SB_MAKEMASK(2, S_IO_DRV_E)
233#define V_IO_DRV_E(x) _SB_MAKEVALUE(x,S_IO_DRV_E) 233#define V_IO_DRV_E(x) _SB_MAKEVALUE(x, S_IO_DRV_E)
234#define G_IO_DRV_E(x) _SB_GETVALUE(x,S_IO_DRV_E,M_IO_DRV_E) 234#define G_IO_DRV_E(x) _SB_GETVALUE(x, S_IO_DRV_E, M_IO_DRV_E)
235 235
236#define S_IO_DRV_F 6 236#define S_IO_DRV_F 6
237#define M_IO_DRV_F _SB_MAKEMASK(2,S_IO_DRV_F) 237#define M_IO_DRV_F _SB_MAKEMASK(2, S_IO_DRV_F)
238#define V_IO_DRV_F(x) _SB_MAKEVALUE(x,S_IO_DRV_F) 238#define V_IO_DRV_F(x) _SB_MAKEVALUE(x, S_IO_DRV_F)
239#define G_IO_DRV_F(x) _SB_GETVALUE(x,S_IO_DRV_F,M_IO_DRV_F) 239#define G_IO_DRV_F(x) _SB_GETVALUE(x, S_IO_DRV_F, M_IO_DRV_F)
240 240
241#define S_IO_SLEW1 8 241#define S_IO_SLEW1 8
242#define M_IO_SLEW1 _SB_MAKEMASK(2,S_IO_SLEW1) 242#define M_IO_SLEW1 _SB_MAKEMASK(2, S_IO_SLEW1)
243#define V_IO_SLEW1(x) _SB_MAKEVALUE(x,S_IO_SLEW1) 243#define V_IO_SLEW1(x) _SB_MAKEVALUE(x, S_IO_SLEW1)
244#define G_IO_SLEW1(x) _SB_GETVALUE(x,S_IO_SLEW1,M_IO_SLEW1) 244#define G_IO_SLEW1(x) _SB_GETVALUE(x, S_IO_SLEW1, M_IO_SLEW1)
245 245
246#define S_IO_DRV_G 10 246#define S_IO_DRV_G 10
247#define M_IO_DRV_G _SB_MAKEMASK(2,S_IO_DRV_G) 247#define M_IO_DRV_G _SB_MAKEMASK(2, S_IO_DRV_G)
248#define V_IO_DRV_G(x) _SB_MAKEVALUE(x,S_IO_DRV_G) 248#define V_IO_DRV_G(x) _SB_MAKEVALUE(x, S_IO_DRV_G)
249#define G_IO_DRV_G(x) _SB_GETVALUE(x,S_IO_DRV_G,M_IO_DRV_G) 249#define G_IO_DRV_G(x) _SB_GETVALUE(x, S_IO_DRV_G, M_IO_DRV_G)
250 250
251#define S_IO_SLEW2 12 251#define S_IO_SLEW2 12
252#define M_IO_SLEW2 _SB_MAKEMASK(2,S_IO_SLEW2) 252#define M_IO_SLEW2 _SB_MAKEMASK(2, S_IO_SLEW2)
253#define V_IO_SLEW2(x) _SB_MAKEVALUE(x,S_IO_SLEW2) 253#define V_IO_SLEW2(x) _SB_MAKEVALUE(x, S_IO_SLEW2)
254#define G_IO_SLEW2(x) _SB_GETVALUE(x,S_IO_SLEW2,M_IO_SLEW2) 254#define G_IO_SLEW2(x) _SB_GETVALUE(x, S_IO_SLEW2, M_IO_SLEW2)
255 255
256#define S_IO_DRV_H 14 256#define S_IO_DRV_H 14
257#define M_IO_DRV_H _SB_MAKEMASK(2,S_IO_DRV_H) 257#define M_IO_DRV_H _SB_MAKEMASK(2, S_IO_DRV_H)
258#define V_IO_DRV_H(x) _SB_MAKEVALUE(x,S_IO_DRV_H) 258#define V_IO_DRV_H(x) _SB_MAKEVALUE(x, S_IO_DRV_H)
259#define G_IO_DRV_H(x) _SB_GETVALUE(x,S_IO_DRV_H,M_IO_DRV_H) 259#define G_IO_DRV_H(x) _SB_GETVALUE(x, S_IO_DRV_H, M_IO_DRV_H)
260 260
261/* 261/*
262 * Generic Bus Output Drive Control Register 2 (Table 14-20) 262 * Generic Bus Output Drive Control Register 2 (Table 14-20)
263 */ 263 */
264 264
265#define S_IO_DRV_J 2 265#define S_IO_DRV_J 2
266#define M_IO_DRV_J _SB_MAKEMASK(2,S_IO_DRV_J) 266#define M_IO_DRV_J _SB_MAKEMASK(2, S_IO_DRV_J)
267#define V_IO_DRV_J(x) _SB_MAKEVALUE(x,S_IO_DRV_J) 267#define V_IO_DRV_J(x) _SB_MAKEVALUE(x, S_IO_DRV_J)
268#define G_IO_DRV_J(x) _SB_GETVALUE(x,S_IO_DRV_J,M_IO_DRV_J) 268#define G_IO_DRV_J(x) _SB_GETVALUE(x, S_IO_DRV_J, M_IO_DRV_J)
269 269
270#define S_IO_DRV_K 6 270#define S_IO_DRV_K 6
271#define M_IO_DRV_K _SB_MAKEMASK(2,S_IO_DRV_K) 271#define M_IO_DRV_K _SB_MAKEMASK(2, S_IO_DRV_K)
272#define V_IO_DRV_K(x) _SB_MAKEVALUE(x,S_IO_DRV_K) 272#define V_IO_DRV_K(x) _SB_MAKEVALUE(x, S_IO_DRV_K)
273#define G_IO_DRV_K(x) _SB_GETVALUE(x,S_IO_DRV_K,M_IO_DRV_K) 273#define G_IO_DRV_K(x) _SB_GETVALUE(x, S_IO_DRV_K, M_IO_DRV_K)
274 274
275#define S_IO_DRV_L 10 275#define S_IO_DRV_L 10
276#define M_IO_DRV_L _SB_MAKEMASK(2,S_IO_DRV_L) 276#define M_IO_DRV_L _SB_MAKEMASK(2, S_IO_DRV_L)
277#define V_IO_DRV_L(x) _SB_MAKEVALUE(x,S_IO_DRV_L) 277#define V_IO_DRV_L(x) _SB_MAKEVALUE(x, S_IO_DRV_L)
278#define G_IO_DRV_L(x) _SB_GETVALUE(x,S_IO_DRV_L,M_IO_DRV_L) 278#define G_IO_DRV_L(x) _SB_GETVALUE(x, S_IO_DRV_L, M_IO_DRV_L)
279 279
280#define S_IO_DRV_M 14 280#define S_IO_DRV_M 14
281#define M_IO_DRV_M _SB_MAKEMASK(2,S_IO_DRV_M) 281#define M_IO_DRV_M _SB_MAKEMASK(2, S_IO_DRV_M)
282#define V_IO_DRV_M(x) _SB_MAKEVALUE(x,S_IO_DRV_M) 282#define V_IO_DRV_M(x) _SB_MAKEVALUE(x, S_IO_DRV_M)
283#define G_IO_DRV_M(x) _SB_GETVALUE(x,S_IO_DRV_M,M_IO_DRV_M) 283#define G_IO_DRV_M(x) _SB_GETVALUE(x, S_IO_DRV_M, M_IO_DRV_M)
284 284
285/* 285/*
286 * Generic Bus Output Drive Control Register 3 (Table 14-21) 286 * Generic Bus Output Drive Control Register 3 (Table 14-21)
287 */ 287 */
288 288
289#define S_IO_SLEW3 0 289#define S_IO_SLEW3 0
290#define M_IO_SLEW3 _SB_MAKEMASK(2,S_IO_SLEW3) 290#define M_IO_SLEW3 _SB_MAKEMASK(2, S_IO_SLEW3)
291#define V_IO_SLEW3(x) _SB_MAKEVALUE(x,S_IO_SLEW3) 291#define V_IO_SLEW3(x) _SB_MAKEVALUE(x, S_IO_SLEW3)
292#define G_IO_SLEW3(x) _SB_GETVALUE(x,S_IO_SLEW3,M_IO_SLEW3) 292#define G_IO_SLEW3(x) _SB_GETVALUE(x, S_IO_SLEW3, M_IO_SLEW3)
293 293
294#define S_IO_DRV_N 2 294#define S_IO_DRV_N 2
295#define M_IO_DRV_N _SB_MAKEMASK(2,S_IO_DRV_N) 295#define M_IO_DRV_N _SB_MAKEMASK(2, S_IO_DRV_N)
296#define V_IO_DRV_N(x) _SB_MAKEVALUE(x,S_IO_DRV_N) 296#define V_IO_DRV_N(x) _SB_MAKEVALUE(x, S_IO_DRV_N)
297#define G_IO_DRV_N(x) _SB_GETVALUE(x,S_IO_DRV_N,M_IO_DRV_N) 297#define G_IO_DRV_N(x) _SB_GETVALUE(x, S_IO_DRV_N, M_IO_DRV_N)
298 298
299#define S_IO_DRV_P 6 299#define S_IO_DRV_P 6
300#define M_IO_DRV_P _SB_MAKEMASK(2,S_IO_DRV_P) 300#define M_IO_DRV_P _SB_MAKEMASK(2, S_IO_DRV_P)
301#define V_IO_DRV_P(x) _SB_MAKEVALUE(x,S_IO_DRV_P) 301#define V_IO_DRV_P(x) _SB_MAKEVALUE(x, S_IO_DRV_P)
302#define G_IO_DRV_P(x) _SB_GETVALUE(x,S_IO_DRV_P,M_IO_DRV_P) 302#define G_IO_DRV_P(x) _SB_GETVALUE(x, S_IO_DRV_P, M_IO_DRV_P)
303 303
304#define S_IO_DRV_Q 10 304#define S_IO_DRV_Q 10
305#define M_IO_DRV_Q _SB_MAKEMASK(2,S_IO_DRV_Q) 305#define M_IO_DRV_Q _SB_MAKEMASK(2, S_IO_DRV_Q)
306#define V_IO_DRV_Q(x) _SB_MAKEVALUE(x,S_IO_DRV_Q) 306#define V_IO_DRV_Q(x) _SB_MAKEVALUE(x, S_IO_DRV_Q)
307#define G_IO_DRV_Q(x) _SB_GETVALUE(x,S_IO_DRV_Q,M_IO_DRV_Q) 307#define G_IO_DRV_Q(x) _SB_GETVALUE(x, S_IO_DRV_Q, M_IO_DRV_Q)
308 308
309#define S_IO_DRV_R 14 309#define S_IO_DRV_R 14
310#define M_IO_DRV_R _SB_MAKEMASK(2,S_IO_DRV_R) 310#define M_IO_DRV_R _SB_MAKEMASK(2, S_IO_DRV_R)
311#define V_IO_DRV_R(x) _SB_MAKEVALUE(x,S_IO_DRV_R) 311#define V_IO_DRV_R(x) _SB_MAKEVALUE(x, S_IO_DRV_R)
312#define G_IO_DRV_R(x) _SB_GETVALUE(x,S_IO_DRV_R,M_IO_DRV_R) 312#define G_IO_DRV_R(x) _SB_GETVALUE(x, S_IO_DRV_R, M_IO_DRV_R)
313 313
314 314
315/* 315/*
@@ -329,9 +329,9 @@
329 329
330#if SIBYTE_HDR_FEATURE_CHIP(1480) 330#if SIBYTE_HDR_FEATURE_CHIP(1480)
331#define S_PCMCIA_MODE 16 331#define S_PCMCIA_MODE 16
332#define M_PCMCIA_MODE _SB_MAKEMASK(3,S_PCMCIA_MODE) 332#define M_PCMCIA_MODE _SB_MAKEMASK(3, S_PCMCIA_MODE)
333#define V_PCMCIA_MODE(x) _SB_MAKEVALUE(x,S_PCMCIA_MODE) 333#define V_PCMCIA_MODE(x) _SB_MAKEVALUE(x, S_PCMCIA_MODE)
334#define G_PCMCIA_MODE(x) _SB_GETVALUE(x,S_PCMCIA_MODE,M_PCMCIA_MODE) 334#define G_PCMCIA_MODE(x) _SB_GETVALUE(x, S_PCMCIA_MODE, M_PCMCIA_MODE)
335 335
336#define K_PCMCIA_MODE_PCMA_NOB 0 /* standard PCMCIA "A", no "B" */ 336#define K_PCMCIA_MODE_PCMA_NOB 0 /* standard PCMCIA "A", no "B" */
337#define K_PCMCIA_MODE_IDEA_NOB 1 /* IDE "A", no "B" */ 337#define K_PCMCIA_MODE_IDEA_NOB 1 /* IDE "A", no "B" */
@@ -369,49 +369,49 @@
369#define K_GPIO_INTR_SPLIT 3 369#define K_GPIO_INTR_SPLIT 3
370 370
371#define S_GPIO_INTR_TYPEX(n) (((n)/2)*2) 371#define S_GPIO_INTR_TYPEX(n) (((n)/2)*2)
372#define M_GPIO_INTR_TYPEX(n) _SB_MAKEMASK(2,S_GPIO_INTR_TYPEX(n)) 372#define M_GPIO_INTR_TYPEX(n) _SB_MAKEMASK(2, S_GPIO_INTR_TYPEX(n))
373#define V_GPIO_INTR_TYPEX(n,x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPEX(n)) 373#define V_GPIO_INTR_TYPEX(n, x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPEX(n))
374#define G_GPIO_INTR_TYPEX(n,x) _SB_GETVALUE(x,S_GPIO_INTR_TYPEX(n),M_GPIO_INTR_TYPEX(n)) 374#define G_GPIO_INTR_TYPEX(n, x) _SB_GETVALUE(x, S_GPIO_INTR_TYPEX(n), M_GPIO_INTR_TYPEX(n))
375 375
376#define S_GPIO_INTR_TYPE0 0 376#define S_GPIO_INTR_TYPE0 0
377#define M_GPIO_INTR_TYPE0 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE0) 377#define M_GPIO_INTR_TYPE0 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE0)
378#define V_GPIO_INTR_TYPE0(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE0) 378#define V_GPIO_INTR_TYPE0(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE0)
379#define G_GPIO_INTR_TYPE0(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE0,M_GPIO_INTR_TYPE0) 379#define G_GPIO_INTR_TYPE0(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE0, M_GPIO_INTR_TYPE0)
380 380
381#define S_GPIO_INTR_TYPE2 2 381#define S_GPIO_INTR_TYPE2 2
382#define M_GPIO_INTR_TYPE2 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE2) 382#define M_GPIO_INTR_TYPE2 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE2)
383#define V_GPIO_INTR_TYPE2(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE2) 383#define V_GPIO_INTR_TYPE2(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE2)
384#define G_GPIO_INTR_TYPE2(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE2,M_GPIO_INTR_TYPE2) 384#define G_GPIO_INTR_TYPE2(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE2, M_GPIO_INTR_TYPE2)
385 385
386#define S_GPIO_INTR_TYPE4 4 386#define S_GPIO_INTR_TYPE4 4
387#define M_GPIO_INTR_TYPE4 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE4) 387#define M_GPIO_INTR_TYPE4 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE4)
388#define V_GPIO_INTR_TYPE4(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE4) 388#define V_GPIO_INTR_TYPE4(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE4)
389#define G_GPIO_INTR_TYPE4(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE4,M_GPIO_INTR_TYPE4) 389#define G_GPIO_INTR_TYPE4(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE4, M_GPIO_INTR_TYPE4)
390 390
391#define S_GPIO_INTR_TYPE6 6 391#define S_GPIO_INTR_TYPE6 6
392#define M_GPIO_INTR_TYPE6 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE6) 392#define M_GPIO_INTR_TYPE6 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE6)
393#define V_GPIO_INTR_TYPE6(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE6) 393#define V_GPIO_INTR_TYPE6(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE6)
394#define G_GPIO_INTR_TYPE6(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE6,M_GPIO_INTR_TYPE6) 394#define G_GPIO_INTR_TYPE6(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE6, M_GPIO_INTR_TYPE6)
395 395
396#define S_GPIO_INTR_TYPE8 8 396#define S_GPIO_INTR_TYPE8 8
397#define M_GPIO_INTR_TYPE8 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE8) 397#define M_GPIO_INTR_TYPE8 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE8)
398#define V_GPIO_INTR_TYPE8(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE8) 398#define V_GPIO_INTR_TYPE8(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE8)
399#define G_GPIO_INTR_TYPE8(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE8,M_GPIO_INTR_TYPE8) 399#define G_GPIO_INTR_TYPE8(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE8, M_GPIO_INTR_TYPE8)
400 400
401#define S_GPIO_INTR_TYPE10 10 401#define S_GPIO_INTR_TYPE10 10
402#define M_GPIO_INTR_TYPE10 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE10) 402#define M_GPIO_INTR_TYPE10 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE10)
403#define V_GPIO_INTR_TYPE10(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE10) 403#define V_GPIO_INTR_TYPE10(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE10)
404#define G_GPIO_INTR_TYPE10(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE10,M_GPIO_INTR_TYPE10) 404#define G_GPIO_INTR_TYPE10(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE10, M_GPIO_INTR_TYPE10)
405 405
406#define S_GPIO_INTR_TYPE12 12 406#define S_GPIO_INTR_TYPE12 12
407#define M_GPIO_INTR_TYPE12 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE12) 407#define M_GPIO_INTR_TYPE12 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE12)
408#define V_GPIO_INTR_TYPE12(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE12) 408#define V_GPIO_INTR_TYPE12(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE12)
409#define G_GPIO_INTR_TYPE12(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE12,M_GPIO_INTR_TYPE12) 409#define G_GPIO_INTR_TYPE12(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE12, M_GPIO_INTR_TYPE12)
410 410
411#define S_GPIO_INTR_TYPE14 14 411#define S_GPIO_INTR_TYPE14 14
412#define M_GPIO_INTR_TYPE14 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE14) 412#define M_GPIO_INTR_TYPE14 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE14)
413#define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE14) 413#define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE14)
414#define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE14,M_GPIO_INTR_TYPE14) 414#define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE14, M_GPIO_INTR_TYPE14)
415 415
416#if SIBYTE_HDR_FEATURE_CHIP(1480) 416#if SIBYTE_HDR_FEATURE_CHIP(1480)
417 417
@@ -425,49 +425,49 @@
425#define K_GPIO_INTR_UNPRED2 3 425#define K_GPIO_INTR_UNPRED2 3
426 426
427#define S_GPIO_INTR_ATYPEX(n) (((n)/2)*2) 427#define S_GPIO_INTR_ATYPEX(n) (((n)/2)*2)
428#define M_GPIO_INTR_ATYPEX(n) _SB_MAKEMASK(2,S_GPIO_INTR_ATYPEX(n)) 428#define M_GPIO_INTR_ATYPEX(n) _SB_MAKEMASK(2, S_GPIO_INTR_ATYPEX(n))
429#define V_GPIO_INTR_ATYPEX(n,x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPEX(n)) 429#define V_GPIO_INTR_ATYPEX(n, x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPEX(n))
430#define G_GPIO_INTR_ATYPEX(n,x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPEX(n),M_GPIO_INTR_ATYPEX(n)) 430#define G_GPIO_INTR_ATYPEX(n, x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPEX(n), M_GPIO_INTR_ATYPEX(n))
431 431
432#define S_GPIO_INTR_ATYPE0 0 432#define S_GPIO_INTR_ATYPE0 0
433#define M_GPIO_INTR_ATYPE0 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE0) 433#define M_GPIO_INTR_ATYPE0 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE0)
434#define V_GPIO_INTR_ATYPE0(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE0) 434#define V_GPIO_INTR_ATYPE0(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE0)
435#define G_GPIO_INTR_ATYPE0(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE0,M_GPIO_INTR_ATYPE0) 435#define G_GPIO_INTR_ATYPE0(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE0, M_GPIO_INTR_ATYPE0)
436 436
437#define S_GPIO_INTR_ATYPE2 2 437#define S_GPIO_INTR_ATYPE2 2
438#define M_GPIO_INTR_ATYPE2 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE2) 438#define M_GPIO_INTR_ATYPE2 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE2)
439#define V_GPIO_INTR_ATYPE2(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE2) 439#define V_GPIO_INTR_ATYPE2(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE2)
440#define G_GPIO_INTR_ATYPE2(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE2,M_GPIO_INTR_ATYPE2) 440#define G_GPIO_INTR_ATYPE2(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE2, M_GPIO_INTR_ATYPE2)
441 441
442#define S_GPIO_INTR_ATYPE4 4 442#define S_GPIO_INTR_ATYPE4 4
443#define M_GPIO_INTR_ATYPE4 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE4) 443#define M_GPIO_INTR_ATYPE4 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE4)
444#define V_GPIO_INTR_ATYPE4(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE4) 444#define V_GPIO_INTR_ATYPE4(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE4)
445#define G_GPIO_INTR_ATYPE4(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE4,M_GPIO_INTR_ATYPE4) 445#define G_GPIO_INTR_ATYPE4(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE4, M_GPIO_INTR_ATYPE4)
446 446
447#define S_GPIO_INTR_ATYPE6 6 447#define S_GPIO_INTR_ATYPE6 6
448#define M_GPIO_INTR_ATYPE6 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE6) 448#define M_GPIO_INTR_ATYPE6 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE6)
449#define V_GPIO_INTR_ATYPE6(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE6) 449#define V_GPIO_INTR_ATYPE6(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE6)
450#define G_GPIO_INTR_ATYPE6(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE6,M_GPIO_INTR_ATYPE6) 450#define G_GPIO_INTR_ATYPE6(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE6, M_GPIO_INTR_ATYPE6)
451 451
452#define S_GPIO_INTR_ATYPE8 8 452#define S_GPIO_INTR_ATYPE8 8
453#define M_GPIO_INTR_ATYPE8 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE8) 453#define M_GPIO_INTR_ATYPE8 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE8)
454#define V_GPIO_INTR_ATYPE8(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE8) 454#define V_GPIO_INTR_ATYPE8(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE8)
455#define G_GPIO_INTR_ATYPE8(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE8,M_GPIO_INTR_ATYPE8) 455#define G_GPIO_INTR_ATYPE8(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE8, M_GPIO_INTR_ATYPE8)
456 456
457#define S_GPIO_INTR_ATYPE10 10 457#define S_GPIO_INTR_ATYPE10 10
458#define M_GPIO_INTR_ATYPE10 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE10) 458#define M_GPIO_INTR_ATYPE10 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE10)
459#define V_GPIO_INTR_ATYPE10(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE10) 459#define V_GPIO_INTR_ATYPE10(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE10)
460#define G_GPIO_INTR_ATYPE10(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE10,M_GPIO_INTR_ATYPE10) 460#define G_GPIO_INTR_ATYPE10(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE10, M_GPIO_INTR_ATYPE10)
461 461
462#define S_GPIO_INTR_ATYPE12 12 462#define S_GPIO_INTR_ATYPE12 12
463#define M_GPIO_INTR_ATYPE12 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE12) 463#define M_GPIO_INTR_ATYPE12 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE12)
464#define V_GPIO_INTR_ATYPE12(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE12) 464#define V_GPIO_INTR_ATYPE12(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE12)
465#define G_GPIO_INTR_ATYPE12(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE12,M_GPIO_INTR_ATYPE12) 465#define G_GPIO_INTR_ATYPE12(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE12, M_GPIO_INTR_ATYPE12)
466 466
467#define S_GPIO_INTR_ATYPE14 14 467#define S_GPIO_INTR_ATYPE14 14
468#define M_GPIO_INTR_ATYPE14 _SB_MAKEMASK(2,S_GPIO_INTR_ATYPE14) 468#define M_GPIO_INTR_ATYPE14 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE14)
469#define V_GPIO_INTR_ATYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_ATYPE14) 469#define V_GPIO_INTR_ATYPE14(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE14)
470#define G_GPIO_INTR_ATYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_ATYPE14,M_GPIO_INTR_ATYPE14) 470#define G_GPIO_INTR_ATYPE14(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE14, M_GPIO_INTR_ATYPE14)
471#endif 471#endif
472 472
473 473
diff --git a/include/asm-mips/sibyte/sb1250_int.h b/include/asm-mips/sibyte/sb1250_int.h
index 94e8299b0a2a..f2850b4bcfd4 100644
--- a/include/asm-mips/sibyte/sb1250_int.h
+++ b/include/asm-mips/sibyte/sb1250_int.h
@@ -10,7 +10,7 @@
10 * 10 *
11 ********************************************************************* 11 *********************************************************************
12 * 12 *
13 * Copyright 2000,2001,2002,2003 13 * Copyright 2000, 2001, 2002, 2003
14 * Broadcom Corporation. All rights reserved. 14 * Broadcom Corporation. All rights reserved.
15 * 15 *
16 * This program is free software; you can redistribute it and/or 16 * This program is free software; you can redistribute it and/or
@@ -150,7 +150,7 @@
150#define M_INT_MBOX_1 _SB_MAKEMASK1(K_INT_MBOX_1) 150#define M_INT_MBOX_1 _SB_MAKEMASK1(K_INT_MBOX_1)
151#define M_INT_MBOX_2 _SB_MAKEMASK1(K_INT_MBOX_2) 151#define M_INT_MBOX_2 _SB_MAKEMASK1(K_INT_MBOX_2)
152#define M_INT_MBOX_3 _SB_MAKEMASK1(K_INT_MBOX_3) 152#define M_INT_MBOX_3 _SB_MAKEMASK1(K_INT_MBOX_3)
153#define M_INT_MBOX_ALL _SB_MAKEMASK(4,K_INT_MBOX_0) 153#define M_INT_MBOX_ALL _SB_MAKEMASK(4, K_INT_MBOX_0)
154#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 154#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
155#define M_INT_CYCLE_CP0_INT _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT) 155#define M_INT_CYCLE_CP0_INT _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT)
156#define M_INT_CYCLE_CP1_INT _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT) 156#define M_INT_CYCLE_CP1_INT _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT)
@@ -208,9 +208,9 @@
208 */ 208 */
209 209
210#define S_INT_LDT_INTMSG 0 210#define S_INT_LDT_INTMSG 0
211#define M_INT_LDT_INTMSG _SB_MAKEMASK(3,S_INT_LDT_INTMSG) 211#define M_INT_LDT_INTMSG _SB_MAKEMASK(3, S_INT_LDT_INTMSG)
212#define V_INT_LDT_INTMSG(x) _SB_MAKEVALUE(x,S_INT_LDT_INTMSG) 212#define V_INT_LDT_INTMSG(x) _SB_MAKEVALUE(x, S_INT_LDT_INTMSG)
213#define G_INT_LDT_INTMSG(x) _SB_GETVALUE(x,S_INT_LDT_INTMSG,M_INT_LDT_INTMSG) 213#define G_INT_LDT_INTMSG(x) _SB_GETVALUE(x, S_INT_LDT_INTMSG, M_INT_LDT_INTMSG)
214 214
215#define K_INT_LDT_INTMSG_FIXED 0 215#define K_INT_LDT_INTMSG_FIXED 0
216#define K_INT_LDT_INTMSG_ARBITRATED 1 216#define K_INT_LDT_INTMSG_ARBITRATED 1
@@ -228,14 +228,14 @@
228#define M_INT_LDT_LOGICALDEST _SB_MAKEMASK1(4) 228#define M_INT_LDT_LOGICALDEST _SB_MAKEMASK1(4)
229 229
230#define S_INT_LDT_INTDEST 5 230#define S_INT_LDT_INTDEST 5
231#define M_INT_LDT_INTDEST _SB_MAKEMASK(10,S_INT_LDT_INTDEST) 231#define M_INT_LDT_INTDEST _SB_MAKEMASK(10, S_INT_LDT_INTDEST)
232#define V_INT_LDT_INTDEST(x) _SB_MAKEVALUE(x,S_INT_LDT_INTDEST) 232#define V_INT_LDT_INTDEST(x) _SB_MAKEVALUE(x, S_INT_LDT_INTDEST)
233#define G_INT_LDT_INTDEST(x) _SB_GETVALUE(x,S_INT_LDT_INTDEST,M_INT_LDT_INTDEST) 233#define G_INT_LDT_INTDEST(x) _SB_GETVALUE(x, S_INT_LDT_INTDEST, M_INT_LDT_INTDEST)
234 234
235#define S_INT_LDT_VECTOR 13 235#define S_INT_LDT_VECTOR 13
236#define M_INT_LDT_VECTOR _SB_MAKEMASK(8,S_INT_LDT_VECTOR) 236#define M_INT_LDT_VECTOR _SB_MAKEMASK(8, S_INT_LDT_VECTOR)
237#define V_INT_LDT_VECTOR(x) _SB_MAKEVALUE(x,S_INT_LDT_VECTOR) 237#define V_INT_LDT_VECTOR(x) _SB_MAKEVALUE(x, S_INT_LDT_VECTOR)
238#define G_INT_LDT_VECTOR(x) _SB_GETVALUE(x,S_INT_LDT_VECTOR,M_INT_LDT_VECTOR) 238#define G_INT_LDT_VECTOR(x) _SB_GETVALUE(x, S_INT_LDT_VECTOR, M_INT_LDT_VECTOR)
239 239
240/* 240/*
241 * Vector format (Table 4-6) 241 * Vector format (Table 4-6)
diff --git a/include/asm-mips/sibyte/sb1250_l2c.h b/include/asm-mips/sibyte/sb1250_l2c.h
index 842f205094af..6554dcf05cfe 100644
--- a/include/asm-mips/sibyte/sb1250_l2c.h
+++ b/include/asm-mips/sibyte/sb1250_l2c.h
@@ -40,27 +40,27 @@
40 */ 40 */
41 41
42#define S_L2C_TAG_MBZ 0 42#define S_L2C_TAG_MBZ 0
43#define M_L2C_TAG_MBZ _SB_MAKEMASK(5,S_L2C_TAG_MBZ) 43#define M_L2C_TAG_MBZ _SB_MAKEMASK(5, S_L2C_TAG_MBZ)
44 44
45#define S_L2C_TAG_INDEX 5 45#define S_L2C_TAG_INDEX 5
46#define M_L2C_TAG_INDEX _SB_MAKEMASK(12,S_L2C_TAG_INDEX) 46#define M_L2C_TAG_INDEX _SB_MAKEMASK(12, S_L2C_TAG_INDEX)
47#define V_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x,S_L2C_TAG_INDEX) 47#define V_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x, S_L2C_TAG_INDEX)
48#define G_L2C_TAG_INDEX(x) _SB_GETVALUE(x,S_L2C_TAG_INDEX,M_L2C_TAG_INDEX) 48#define G_L2C_TAG_INDEX(x) _SB_GETVALUE(x, S_L2C_TAG_INDEX, M_L2C_TAG_INDEX)
49 49
50#define S_L2C_TAG_TAG 17 50#define S_L2C_TAG_TAG 17
51#define M_L2C_TAG_TAG _SB_MAKEMASK(23,S_L2C_TAG_TAG) 51#define M_L2C_TAG_TAG _SB_MAKEMASK(23, S_L2C_TAG_TAG)
52#define V_L2C_TAG_TAG(x) _SB_MAKEVALUE(x,S_L2C_TAG_TAG) 52#define V_L2C_TAG_TAG(x) _SB_MAKEVALUE(x, S_L2C_TAG_TAG)
53#define G_L2C_TAG_TAG(x) _SB_GETVALUE(x,S_L2C_TAG_TAG,M_L2C_TAG_TAG) 53#define G_L2C_TAG_TAG(x) _SB_GETVALUE(x, S_L2C_TAG_TAG, M_L2C_TAG_TAG)
54 54
55#define S_L2C_TAG_ECC 40 55#define S_L2C_TAG_ECC 40
56#define M_L2C_TAG_ECC _SB_MAKEMASK(6,S_L2C_TAG_ECC) 56#define M_L2C_TAG_ECC _SB_MAKEMASK(6, S_L2C_TAG_ECC)
57#define V_L2C_TAG_ECC(x) _SB_MAKEVALUE(x,S_L2C_TAG_ECC) 57#define V_L2C_TAG_ECC(x) _SB_MAKEVALUE(x, S_L2C_TAG_ECC)
58#define G_L2C_TAG_ECC(x) _SB_GETVALUE(x,S_L2C_TAG_ECC,M_L2C_TAG_ECC) 58#define G_L2C_TAG_ECC(x) _SB_GETVALUE(x, S_L2C_TAG_ECC, M_L2C_TAG_ECC)
59 59
60#define S_L2C_TAG_WAY 46 60#define S_L2C_TAG_WAY 46
61#define M_L2C_TAG_WAY _SB_MAKEMASK(2,S_L2C_TAG_WAY) 61#define M_L2C_TAG_WAY _SB_MAKEMASK(2, S_L2C_TAG_WAY)
62#define V_L2C_TAG_WAY(x) _SB_MAKEVALUE(x,S_L2C_TAG_WAY) 62#define V_L2C_TAG_WAY(x) _SB_MAKEVALUE(x, S_L2C_TAG_WAY)
63#define G_L2C_TAG_WAY(x) _SB_GETVALUE(x,S_L2C_TAG_WAY,M_L2C_TAG_WAY) 63#define G_L2C_TAG_WAY(x) _SB_GETVALUE(x, S_L2C_TAG_WAY, M_L2C_TAG_WAY)
64 64
65#define M_L2C_TAG_DIRTY _SB_MAKEMASK1(48) 65#define M_L2C_TAG_DIRTY _SB_MAKEMASK1(48)
66#define M_L2C_TAG_VALID _SB_MAKEMASK1(49) 66#define M_L2C_TAG_VALID _SB_MAKEMASK1(49)
@@ -70,32 +70,32 @@
70 */ 70 */
71 71
72#define S_L2C_MGMT_INDEX 5 72#define S_L2C_MGMT_INDEX 5
73#define M_L2C_MGMT_INDEX _SB_MAKEMASK(12,S_L2C_MGMT_INDEX) 73#define M_L2C_MGMT_INDEX _SB_MAKEMASK(12, S_L2C_MGMT_INDEX)
74#define V_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x,S_L2C_MGMT_INDEX) 74#define V_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x, S_L2C_MGMT_INDEX)
75#define G_L2C_MGMT_INDEX(x) _SB_GETVALUE(x,S_L2C_MGMT_INDEX,M_L2C_MGMT_INDEX) 75#define G_L2C_MGMT_INDEX(x) _SB_GETVALUE(x, S_L2C_MGMT_INDEX, M_L2C_MGMT_INDEX)
76 76
77#define S_L2C_MGMT_QUADRANT 15 77#define S_L2C_MGMT_QUADRANT 15
78#define M_L2C_MGMT_QUADRANT _SB_MAKEMASK(2,S_L2C_MGMT_QUADRANT) 78#define M_L2C_MGMT_QUADRANT _SB_MAKEMASK(2, S_L2C_MGMT_QUADRANT)
79#define V_L2C_MGMT_QUADRANT(x) _SB_MAKEVALUE(x,S_L2C_MGMT_QUADRANT) 79#define V_L2C_MGMT_QUADRANT(x) _SB_MAKEVALUE(x, S_L2C_MGMT_QUADRANT)
80#define G_L2C_MGMT_QUADRANT(x) _SB_GETVALUE(x,S_L2C_MGMT_QUADRANT,M_L2C_MGMT_QUADRANT) 80#define G_L2C_MGMT_QUADRANT(x) _SB_GETVALUE(x, S_L2C_MGMT_QUADRANT, M_L2C_MGMT_QUADRANT)
81 81
82#define S_L2C_MGMT_HALF 16 82#define S_L2C_MGMT_HALF 16
83#define M_L2C_MGMT_HALF _SB_MAKEMASK(1,S_L2C_MGMT_HALF) 83#define M_L2C_MGMT_HALF _SB_MAKEMASK(1, S_L2C_MGMT_HALF)
84 84
85#define S_L2C_MGMT_WAY 17 85#define S_L2C_MGMT_WAY 17
86#define M_L2C_MGMT_WAY _SB_MAKEMASK(2,S_L2C_MGMT_WAY) 86#define M_L2C_MGMT_WAY _SB_MAKEMASK(2, S_L2C_MGMT_WAY)
87#define V_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x,S_L2C_MGMT_WAY) 87#define V_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x, S_L2C_MGMT_WAY)
88#define G_L2C_MGMT_WAY(x) _SB_GETVALUE(x,S_L2C_MGMT_WAY,M_L2C_MGMT_WAY) 88#define G_L2C_MGMT_WAY(x) _SB_GETVALUE(x, S_L2C_MGMT_WAY, M_L2C_MGMT_WAY)
89 89
90#define S_L2C_MGMT_ECC_DIAG 21 90#define S_L2C_MGMT_ECC_DIAG 21
91#define M_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2,S_L2C_MGMT_ECC_DIAG) 91#define M_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2, S_L2C_MGMT_ECC_DIAG)
92#define V_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x,S_L2C_MGMT_ECC_DIAG) 92#define V_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x, S_L2C_MGMT_ECC_DIAG)
93#define G_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x,S_L2C_MGMT_ECC_DIAG,M_L2C_MGMT_ECC_DIAG) 93#define G_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x, S_L2C_MGMT_ECC_DIAG, M_L2C_MGMT_ECC_DIAG)
94 94
95#define S_L2C_MGMT_TAG 23 95#define S_L2C_MGMT_TAG 23
96#define M_L2C_MGMT_TAG _SB_MAKEMASK(4,S_L2C_MGMT_TAG) 96#define M_L2C_MGMT_TAG _SB_MAKEMASK(4, S_L2C_MGMT_TAG)
97#define V_L2C_MGMT_TAG(x) _SB_MAKEVALUE(x,S_L2C_MGMT_TAG) 97#define V_L2C_MGMT_TAG(x) _SB_MAKEVALUE(x, S_L2C_MGMT_TAG)
98#define G_L2C_MGMT_TAG(x) _SB_GETVALUE(x,S_L2C_MGMT_TAG,M_L2C_MGMT_TAG) 98#define G_L2C_MGMT_TAG(x) _SB_GETVALUE(x, S_L2C_MGMT_TAG, M_L2C_MGMT_TAG)
99 99
100#define M_L2C_MGMT_DIRTY _SB_MAKEMASK1(19) 100#define M_L2C_MGMT_DIRTY _SB_MAKEMASK1(19)
101#define M_L2C_MGMT_VALID _SB_MAKEMASK1(20) 101#define M_L2C_MGMT_VALID _SB_MAKEMASK1(20)
@@ -111,9 +111,9 @@
111 * L2 Read Misc. register (A_L2_READ_MISC) 111 * L2 Read Misc. register (A_L2_READ_MISC)
112 */ 112 */
113#define S_L2C_MISC_NO_WAY 10 113#define S_L2C_MISC_NO_WAY 10
114#define M_L2C_MISC_NO_WAY _SB_MAKEMASK(4,S_L2C_MISC_NO_WAY) 114#define M_L2C_MISC_NO_WAY _SB_MAKEMASK(4, S_L2C_MISC_NO_WAY)
115#define V_L2C_MISC_NO_WAY(x) _SB_MAKEVALUE(x,S_L2C_MISC_NO_WAY) 115#define V_L2C_MISC_NO_WAY(x) _SB_MAKEVALUE(x, S_L2C_MISC_NO_WAY)
116#define G_L2C_MISC_NO_WAY(x) _SB_GETVALUE(x,S_L2C_MISC_NO_WAY,M_L2C_MISC_NO_WAY) 116#define G_L2C_MISC_NO_WAY(x) _SB_GETVALUE(x, S_L2C_MISC_NO_WAY, M_L2C_MISC_NO_WAY)
117 117
118#define M_L2C_MISC_ECC_CLEANUP_DIS _SB_MAKEMASK1(9) 118#define M_L2C_MISC_ECC_CLEANUP_DIS _SB_MAKEMASK1(9)
119#define M_L2C_MISC_MC_PRIO_LOW _SB_MAKEMASK1(8) 119#define M_L2C_MISC_MC_PRIO_LOW _SB_MAKEMASK1(8)
diff --git a/include/asm-mips/sibyte/sb1250_ldt.h b/include/asm-mips/sibyte/sb1250_ldt.h
index 7092535d1108..081e8b1c4ad0 100644
--- a/include/asm-mips/sibyte/sb1250_ldt.h
+++ b/include/asm-mips/sibyte/sb1250_ldt.h
@@ -10,7 +10,7 @@
10 * 10 *
11 ********************************************************************* 11 *********************************************************************
12 * 12 *
13 * Copyright 2000,2001,2002,2003 13 * Copyright 2000, 2001, 2002, 2003
14 * Broadcom Corporation. All rights reserved. 14 * Broadcom Corporation. All rights reserved.
15 * 15 *
16 * This program is free software; you can redistribute it and/or 16 * This program is free software; you can redistribute it and/or
@@ -81,14 +81,14 @@
81 */ 81 */
82 82
83#define S_LDT_DEVICEID_VENDOR 0 83#define S_LDT_DEVICEID_VENDOR 0
84#define M_LDT_DEVICEID_VENDOR _SB_MAKEMASK_32(16,S_LDT_DEVICEID_VENDOR) 84#define M_LDT_DEVICEID_VENDOR _SB_MAKEMASK_32(16, S_LDT_DEVICEID_VENDOR)
85#define V_LDT_DEVICEID_VENDOR(x) _SB_MAKEVALUE_32(x,S_LDT_DEVICEID_VENDOR) 85#define V_LDT_DEVICEID_VENDOR(x) _SB_MAKEVALUE_32(x, S_LDT_DEVICEID_VENDOR)
86#define G_LDT_DEVICEID_VENDOR(x) _SB_GETVALUE_32(x,S_LDT_DEVICEID_VENDOR,M_LDT_DEVICEID_VENDOR) 86#define G_LDT_DEVICEID_VENDOR(x) _SB_GETVALUE_32(x, S_LDT_DEVICEID_VENDOR, M_LDT_DEVICEID_VENDOR)
87 87
88#define S_LDT_DEVICEID_DEVICEID 16 88#define S_LDT_DEVICEID_DEVICEID 16
89#define M_LDT_DEVICEID_DEVICEID _SB_MAKEMASK_32(16,S_LDT_DEVICEID_DEVICEID) 89#define M_LDT_DEVICEID_DEVICEID _SB_MAKEMASK_32(16, S_LDT_DEVICEID_DEVICEID)
90#define V_LDT_DEVICEID_DEVICEID(x) _SB_MAKEVALUE_32(x,S_LDT_DEVICEID_DEVICEID) 90#define V_LDT_DEVICEID_DEVICEID(x) _SB_MAKEVALUE_32(x, S_LDT_DEVICEID_DEVICEID)
91#define G_LDT_DEVICEID_DEVICEID(x) _SB_GETVALUE_32(x,S_LDT_DEVICEID_DEVICEID,M_LDT_DEVICEID_DEVICEID) 91#define G_LDT_DEVICEID_DEVICEID(x) _SB_GETVALUE_32(x, S_LDT_DEVICEID_DEVICEID, M_LDT_DEVICEID_DEVICEID)
92 92
93 93
94/* 94/*
@@ -111,14 +111,14 @@
111 */ 111 */
112 112
113#define S_LDT_CLASSREV_REV 0 113#define S_LDT_CLASSREV_REV 0
114#define M_LDT_CLASSREV_REV _SB_MAKEMASK_32(8,S_LDT_CLASSREV_REV) 114#define M_LDT_CLASSREV_REV _SB_MAKEMASK_32(8, S_LDT_CLASSREV_REV)
115#define V_LDT_CLASSREV_REV(x) _SB_MAKEVALUE_32(x,S_LDT_CLASSREV_REV) 115#define V_LDT_CLASSREV_REV(x) _SB_MAKEVALUE_32(x, S_LDT_CLASSREV_REV)
116#define G_LDT_CLASSREV_REV(x) _SB_GETVALUE_32(x,S_LDT_CLASSREV_REV,M_LDT_CLASSREV_REV) 116#define G_LDT_CLASSREV_REV(x) _SB_GETVALUE_32(x, S_LDT_CLASSREV_REV, M_LDT_CLASSREV_REV)
117 117
118#define S_LDT_CLASSREV_CLASS 8 118#define S_LDT_CLASSREV_CLASS 8
119#define M_LDT_CLASSREV_CLASS _SB_MAKEMASK_32(24,S_LDT_CLASSREV_CLASS) 119#define M_LDT_CLASSREV_CLASS _SB_MAKEMASK_32(24, S_LDT_CLASSREV_CLASS)
120#define V_LDT_CLASSREV_CLASS(x) _SB_MAKEVALUE_32(x,S_LDT_CLASSREV_CLASS) 120#define V_LDT_CLASSREV_CLASS(x) _SB_MAKEVALUE_32(x, S_LDT_CLASSREV_CLASS)
121#define G_LDT_CLASSREV_CLASS(x) _SB_GETVALUE_32(x,S_LDT_CLASSREV_CLASS,M_LDT_CLASSREV_CLASS) 121#define G_LDT_CLASSREV_CLASS(x) _SB_GETVALUE_32(x, S_LDT_CLASSREV_CLASS, M_LDT_CLASSREV_CLASS)
122 122
123#define K_LDT_REV 0x01 123#define K_LDT_REV 0x01
124#define K_LDT_CLASS 0x060000 124#define K_LDT_CLASS 0x060000
@@ -128,26 +128,26 @@
128 */ 128 */
129 129
130#define S_LDT_DEVHDR_CLINESZ 0 130#define S_LDT_DEVHDR_CLINESZ 0
131#define M_LDT_DEVHDR_CLINESZ _SB_MAKEMASK_32(8,S_LDT_DEVHDR_CLINESZ) 131#define M_LDT_DEVHDR_CLINESZ _SB_MAKEMASK_32(8, S_LDT_DEVHDR_CLINESZ)
132#define V_LDT_DEVHDR_CLINESZ(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_CLINESZ) 132#define V_LDT_DEVHDR_CLINESZ(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_CLINESZ)
133#define G_LDT_DEVHDR_CLINESZ(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_CLINESZ,M_LDT_DEVHDR_CLINESZ) 133#define G_LDT_DEVHDR_CLINESZ(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_CLINESZ, M_LDT_DEVHDR_CLINESZ)
134 134
135#define S_LDT_DEVHDR_LATTMR 8 135#define S_LDT_DEVHDR_LATTMR 8
136#define M_LDT_DEVHDR_LATTMR _SB_MAKEMASK_32(8,S_LDT_DEVHDR_LATTMR) 136#define M_LDT_DEVHDR_LATTMR _SB_MAKEMASK_32(8, S_LDT_DEVHDR_LATTMR)
137#define V_LDT_DEVHDR_LATTMR(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_LATTMR) 137#define V_LDT_DEVHDR_LATTMR(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_LATTMR)
138#define G_LDT_DEVHDR_LATTMR(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_LATTMR,M_LDT_DEVHDR_LATTMR) 138#define G_LDT_DEVHDR_LATTMR(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_LATTMR, M_LDT_DEVHDR_LATTMR)
139 139
140#define S_LDT_DEVHDR_HDRTYPE 16 140#define S_LDT_DEVHDR_HDRTYPE 16
141#define M_LDT_DEVHDR_HDRTYPE _SB_MAKEMASK_32(8,S_LDT_DEVHDR_HDRTYPE) 141#define M_LDT_DEVHDR_HDRTYPE _SB_MAKEMASK_32(8, S_LDT_DEVHDR_HDRTYPE)
142#define V_LDT_DEVHDR_HDRTYPE(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_HDRTYPE) 142#define V_LDT_DEVHDR_HDRTYPE(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_HDRTYPE)
143#define G_LDT_DEVHDR_HDRTYPE(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_HDRTYPE,M_LDT_DEVHDR_HDRTYPE) 143#define G_LDT_DEVHDR_HDRTYPE(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_HDRTYPE, M_LDT_DEVHDR_HDRTYPE)
144 144
145#define K_LDT_DEVHDR_HDRTYPE_TYPE1 1 145#define K_LDT_DEVHDR_HDRTYPE_TYPE1 1
146 146
147#define S_LDT_DEVHDR_BIST 24 147#define S_LDT_DEVHDR_BIST 24
148#define M_LDT_DEVHDR_BIST _SB_MAKEMASK_32(8,S_LDT_DEVHDR_BIST) 148#define M_LDT_DEVHDR_BIST _SB_MAKEMASK_32(8, S_LDT_DEVHDR_BIST)
149#define V_LDT_DEVHDR_BIST(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_BIST) 149#define V_LDT_DEVHDR_BIST(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_BIST)
150#define G_LDT_DEVHDR_BIST(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_BIST,M_LDT_DEVHDR_BIST) 150#define G_LDT_DEVHDR_BIST(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_BIST, M_LDT_DEVHDR_BIST)
151 151
152 152
153 153
@@ -170,9 +170,9 @@
170#define M_LDT_STATUS_MSTRDPARERR _SB_MAKEMASK1_32(24) 170#define M_LDT_STATUS_MSTRDPARERR _SB_MAKEMASK1_32(24)
171 171
172#define S_LDT_STATUS_DEVSELTIMING 25 172#define S_LDT_STATUS_DEVSELTIMING 25
173#define M_LDT_STATUS_DEVSELTIMING _SB_MAKEMASK_32(2,S_LDT_STATUS_DEVSELTIMING) 173#define M_LDT_STATUS_DEVSELTIMING _SB_MAKEMASK_32(2, S_LDT_STATUS_DEVSELTIMING)
174#define V_LDT_STATUS_DEVSELTIMING(x) _SB_MAKEVALUE_32(x,S_LDT_STATUS_DEVSELTIMING) 174#define V_LDT_STATUS_DEVSELTIMING(x) _SB_MAKEVALUE_32(x, S_LDT_STATUS_DEVSELTIMING)
175#define G_LDT_STATUS_DEVSELTIMING(x) _SB_GETVALUE_32(x,S_LDT_STATUS_DEVSELTIMING,M_LDT_STATUS_DEVSELTIMING) 175#define G_LDT_STATUS_DEVSELTIMING(x) _SB_GETVALUE_32(x, S_LDT_STATUS_DEVSELTIMING, M_LDT_STATUS_DEVSELTIMING)
176 176
177#define M_LDT_STATUS_SIGDTGTABORT _SB_MAKEMASK1_32(27) 177#define M_LDT_STATUS_SIGDTGTABORT _SB_MAKEMASK1_32(27)
178#define M_LDT_STATUS_RCVDTGTABORT _SB_MAKEMASK1_32(28) 178#define M_LDT_STATUS_RCVDTGTABORT _SB_MAKEMASK1_32(28)
@@ -208,9 +208,9 @@
208#define M_LDT_CMD_DOUBLEENDED _SB_MAKEMASK1_32(17) 208#define M_LDT_CMD_DOUBLEENDED _SB_MAKEMASK1_32(17)
209 209
210#define S_LDT_CMD_CAPTYPE 29 210#define S_LDT_CMD_CAPTYPE 29
211#define M_LDT_CMD_CAPTYPE _SB_MAKEMASK_32(3,S_LDT_CMD_CAPTYPE) 211#define M_LDT_CMD_CAPTYPE _SB_MAKEMASK_32(3, S_LDT_CMD_CAPTYPE)
212#define V_LDT_CMD_CAPTYPE(x) _SB_MAKEVALUE_32(x,S_LDT_CMD_CAPTYPE) 212#define V_LDT_CMD_CAPTYPE(x) _SB_MAKEVALUE_32(x, S_LDT_CMD_CAPTYPE)
213#define G_LDT_CMD_CAPTYPE(x) _SB_GETVALUE_32(x,S_LDT_CMD_CAPTYPE,M_LDT_CMD_CAPTYPE) 213#define G_LDT_CMD_CAPTYPE(x) _SB_GETVALUE_32(x, S_LDT_CMD_CAPTYPE, M_LDT_CMD_CAPTYPE)
214 214
215/* 215/*
216 * LDT link control register (Table 8-18), and (Table 8-19) 216 * LDT link control register (Table 8-18), and (Table 8-19)
@@ -225,35 +225,35 @@
225#define M_LDT_LINKCTRL_XMITOFF _SB_MAKEMASK1_32(7) 225#define M_LDT_LINKCTRL_XMITOFF _SB_MAKEMASK1_32(7)
226 226
227#define S_LDT_LINKCTRL_CRCERR 8 227#define S_LDT_LINKCTRL_CRCERR 8
228#define M_LDT_LINKCTRL_CRCERR _SB_MAKEMASK_32(4,S_LDT_LINKCTRL_CRCERR) 228#define M_LDT_LINKCTRL_CRCERR _SB_MAKEMASK_32(4, S_LDT_LINKCTRL_CRCERR)
229#define V_LDT_LINKCTRL_CRCERR(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_CRCERR) 229#define V_LDT_LINKCTRL_CRCERR(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_CRCERR)
230#define G_LDT_LINKCTRL_CRCERR(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_CRCERR,M_LDT_LINKCTRL_CRCERR) 230#define G_LDT_LINKCTRL_CRCERR(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_CRCERR, M_LDT_LINKCTRL_CRCERR)
231 231
232#define S_LDT_LINKCTRL_MAXIN 16 232#define S_LDT_LINKCTRL_MAXIN 16
233#define M_LDT_LINKCTRL_MAXIN _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_MAXIN) 233#define M_LDT_LINKCTRL_MAXIN _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_MAXIN)
234#define V_LDT_LINKCTRL_MAXIN(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_MAXIN) 234#define V_LDT_LINKCTRL_MAXIN(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_MAXIN)
235#define G_LDT_LINKCTRL_MAXIN(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_MAXIN,M_LDT_LINKCTRL_MAXIN) 235#define G_LDT_LINKCTRL_MAXIN(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_MAXIN, M_LDT_LINKCTRL_MAXIN)
236 236
237#define M_LDT_LINKCTRL_DWFCLN _SB_MAKEMASK1_32(19) 237#define M_LDT_LINKCTRL_DWFCLN _SB_MAKEMASK1_32(19)
238 238
239#define S_LDT_LINKCTRL_MAXOUT 20 239#define S_LDT_LINKCTRL_MAXOUT 20
240#define M_LDT_LINKCTRL_MAXOUT _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_MAXOUT) 240#define M_LDT_LINKCTRL_MAXOUT _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_MAXOUT)
241#define V_LDT_LINKCTRL_MAXOUT(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_MAXOUT) 241#define V_LDT_LINKCTRL_MAXOUT(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_MAXOUT)
242#define G_LDT_LINKCTRL_MAXOUT(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_MAXOUT,M_LDT_LINKCTRL_MAXOUT) 242#define G_LDT_LINKCTRL_MAXOUT(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_MAXOUT, M_LDT_LINKCTRL_MAXOUT)
243 243
244#define M_LDT_LINKCTRL_DWFCOUT _SB_MAKEMASK1_32(23) 244#define M_LDT_LINKCTRL_DWFCOUT _SB_MAKEMASK1_32(23)
245 245
246#define S_LDT_LINKCTRL_WIDTHIN 24 246#define S_LDT_LINKCTRL_WIDTHIN 24
247#define M_LDT_LINKCTRL_WIDTHIN _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_WIDTHIN) 247#define M_LDT_LINKCTRL_WIDTHIN _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_WIDTHIN)
248#define V_LDT_LINKCTRL_WIDTHIN(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_WIDTHIN) 248#define V_LDT_LINKCTRL_WIDTHIN(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_WIDTHIN)
249#define G_LDT_LINKCTRL_WIDTHIN(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_WIDTHIN,M_LDT_LINKCTRL_WIDTHIN) 249#define G_LDT_LINKCTRL_WIDTHIN(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_WIDTHIN, M_LDT_LINKCTRL_WIDTHIN)
250 250
251#define M_LDT_LINKCTRL_DWFCLIN_EN _SB_MAKEMASK1_32(27) 251#define M_LDT_LINKCTRL_DWFCLIN_EN _SB_MAKEMASK1_32(27)
252 252
253#define S_LDT_LINKCTRL_WIDTHOUT 28 253#define S_LDT_LINKCTRL_WIDTHOUT 28
254#define M_LDT_LINKCTRL_WIDTHOUT _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_WIDTHOUT) 254#define M_LDT_LINKCTRL_WIDTHOUT _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_WIDTHOUT)
255#define V_LDT_LINKCTRL_WIDTHOUT(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_WIDTHOUT) 255#define V_LDT_LINKCTRL_WIDTHOUT(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_WIDTHOUT)
256#define G_LDT_LINKCTRL_WIDTHOUT(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_WIDTHOUT,M_LDT_LINKCTRL_WIDTHOUT) 256#define G_LDT_LINKCTRL_WIDTHOUT(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_WIDTHOUT, M_LDT_LINKCTRL_WIDTHOUT)
257 257
258#define M_LDT_LINKCTRL_DWFCOUT_EN _SB_MAKEMASK1_32(31) 258#define M_LDT_LINKCTRL_DWFCOUT_EN _SB_MAKEMASK1_32(31)
259 259
@@ -262,9 +262,9 @@
262 */ 262 */
263 263
264#define S_LDT_LINKFREQ_FREQ 8 264#define S_LDT_LINKFREQ_FREQ 8
265#define M_LDT_LINKFREQ_FREQ _SB_MAKEMASK_32(4,S_LDT_LINKFREQ_FREQ) 265#define M_LDT_LINKFREQ_FREQ _SB_MAKEMASK_32(4, S_LDT_LINKFREQ_FREQ)
266#define V_LDT_LINKFREQ_FREQ(x) _SB_MAKEVALUE_32(x,S_LDT_LINKFREQ_FREQ) 266#define V_LDT_LINKFREQ_FREQ(x) _SB_MAKEVALUE_32(x, S_LDT_LINKFREQ_FREQ)
267#define G_LDT_LINKFREQ_FREQ(x) _SB_GETVALUE_32(x,S_LDT_LINKFREQ_FREQ,M_LDT_LINKFREQ_FREQ) 267#define G_LDT_LINKFREQ_FREQ(x) _SB_GETVALUE_32(x, S_LDT_LINKFREQ_FREQ, M_LDT_LINKFREQ_FREQ)
268 268
269#define K_LDT_LINKFREQ_200MHZ 0 269#define K_LDT_LINKFREQ_200MHZ 0
270#define K_LDT_LINKFREQ_300MHZ 1 270#define K_LDT_LINKFREQ_300MHZ 1
@@ -293,16 +293,16 @@
293 293
294 294
295#define S_LDT_SRICMD_RXMARGIN 20 295#define S_LDT_SRICMD_RXMARGIN 20
296#define M_LDT_SRICMD_RXMARGIN _SB_MAKEMASK_32(5,S_LDT_SRICMD_RXMARGIN) 296#define M_LDT_SRICMD_RXMARGIN _SB_MAKEMASK_32(5, S_LDT_SRICMD_RXMARGIN)
297#define V_LDT_SRICMD_RXMARGIN(x) _SB_MAKEVALUE_32(x,S_LDT_SRICMD_RXMARGIN) 297#define V_LDT_SRICMD_RXMARGIN(x) _SB_MAKEVALUE_32(x, S_LDT_SRICMD_RXMARGIN)
298#define G_LDT_SRICMD_RXMARGIN(x) _SB_GETVALUE_32(x,S_LDT_SRICMD_RXMARGIN,M_LDT_SRICMD_RXMARGIN) 298#define G_LDT_SRICMD_RXMARGIN(x) _SB_GETVALUE_32(x, S_LDT_SRICMD_RXMARGIN, M_LDT_SRICMD_RXMARGIN)
299 299
300#define M_LDT_SRICMD_LDTPLLCOMPAT _SB_MAKEMASK1_32(25) 300#define M_LDT_SRICMD_LDTPLLCOMPAT _SB_MAKEMASK1_32(25)
301 301
302#define S_LDT_SRICMD_TXINITIALOFFSET 28 302#define S_LDT_SRICMD_TXINITIALOFFSET 28
303#define M_LDT_SRICMD_TXINITIALOFFSET _SB_MAKEMASK_32(3,S_LDT_SRICMD_TXINITIALOFFSET) 303#define M_LDT_SRICMD_TXINITIALOFFSET _SB_MAKEMASK_32(3, S_LDT_SRICMD_TXINITIALOFFSET)
304#define V_LDT_SRICMD_TXINITIALOFFSET(x) _SB_MAKEVALUE_32(x,S_LDT_SRICMD_TXINITIALOFFSET) 304#define V_LDT_SRICMD_TXINITIALOFFSET(x) _SB_MAKEVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET)
305#define G_LDT_SRICMD_TXINITIALOFFSET(x) _SB_GETVALUE_32(x,S_LDT_SRICMD_TXINITIALOFFSET,M_LDT_SRICMD_TXINITIALOFFSET) 305#define G_LDT_SRICMD_TXINITIALOFFSET(x) _SB_GETVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET, M_LDT_SRICMD_TXINITIALOFFSET)
306 306
307#define M_LDT_SRICMD_LINKFREQDIRECT _SB_MAKEMASK1_32(31) 307#define M_LDT_SRICMD_LINKFREQDIRECT _SB_MAKEMASK1_32(31)
308 308
@@ -340,73 +340,73 @@
340 */ 340 */
341 341
342#define S_LDT_SRICTRL_NEEDRESP 0 342#define S_LDT_SRICTRL_NEEDRESP 0
343#define M_LDT_SRICTRL_NEEDRESP _SB_MAKEMASK_32(2,S_LDT_SRICTRL_NEEDRESP) 343#define M_LDT_SRICTRL_NEEDRESP _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDRESP)
344#define V_LDT_SRICTRL_NEEDRESP(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_NEEDRESP) 344#define V_LDT_SRICTRL_NEEDRESP(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDRESP)
345#define G_LDT_SRICTRL_NEEDRESP(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_NEEDRESP,M_LDT_SRICTRL_NEEDRESP) 345#define G_LDT_SRICTRL_NEEDRESP(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDRESP, M_LDT_SRICTRL_NEEDRESP)
346 346
347#define S_LDT_SRICTRL_NEEDNPREQ 2 347#define S_LDT_SRICTRL_NEEDNPREQ 2
348#define M_LDT_SRICTRL_NEEDNPREQ _SB_MAKEMASK_32(2,S_LDT_SRICTRL_NEEDNPREQ) 348#define M_LDT_SRICTRL_NEEDNPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDNPREQ)
349#define V_LDT_SRICTRL_NEEDNPREQ(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_NEEDNPREQ) 349#define V_LDT_SRICTRL_NEEDNPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDNPREQ)
350#define G_LDT_SRICTRL_NEEDNPREQ(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_NEEDNPREQ,M_LDT_SRICTRL_NEEDNPREQ) 350#define G_LDT_SRICTRL_NEEDNPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDNPREQ, M_LDT_SRICTRL_NEEDNPREQ)
351 351
352#define S_LDT_SRICTRL_NEEDPREQ 4 352#define S_LDT_SRICTRL_NEEDPREQ 4
353#define M_LDT_SRICTRL_NEEDPREQ _SB_MAKEMASK_32(2,S_LDT_SRICTRL_NEEDPREQ) 353#define M_LDT_SRICTRL_NEEDPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDPREQ)
354#define V_LDT_SRICTRL_NEEDPREQ(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_NEEDPREQ) 354#define V_LDT_SRICTRL_NEEDPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDPREQ)
355#define G_LDT_SRICTRL_NEEDPREQ(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_NEEDPREQ,M_LDT_SRICTRL_NEEDPREQ) 355#define G_LDT_SRICTRL_NEEDPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDPREQ, M_LDT_SRICTRL_NEEDPREQ)
356 356
357#define S_LDT_SRICTRL_WANTRESP 8 357#define S_LDT_SRICTRL_WANTRESP 8
358#define M_LDT_SRICTRL_WANTRESP _SB_MAKEMASK_32(2,S_LDT_SRICTRL_WANTRESP) 358#define M_LDT_SRICTRL_WANTRESP _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTRESP)
359#define V_LDT_SRICTRL_WANTRESP(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_WANTRESP) 359#define V_LDT_SRICTRL_WANTRESP(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTRESP)
360#define G_LDT_SRICTRL_WANTRESP(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_WANTRESP,M_LDT_SRICTRL_WANTRESP) 360#define G_LDT_SRICTRL_WANTRESP(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTRESP, M_LDT_SRICTRL_WANTRESP)
361 361
362#define S_LDT_SRICTRL_WANTNPREQ 10 362#define S_LDT_SRICTRL_WANTNPREQ 10
363#define M_LDT_SRICTRL_WANTNPREQ _SB_MAKEMASK_32(2,S_LDT_SRICTRL_WANTNPREQ) 363#define M_LDT_SRICTRL_WANTNPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTNPREQ)
364#define V_LDT_SRICTRL_WANTNPREQ(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_WANTNPREQ) 364#define V_LDT_SRICTRL_WANTNPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTNPREQ)
365#define G_LDT_SRICTRL_WANTNPREQ(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_WANTNPREQ,M_LDT_SRICTRL_WANTNPREQ) 365#define G_LDT_SRICTRL_WANTNPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTNPREQ, M_LDT_SRICTRL_WANTNPREQ)
366 366
367#define S_LDT_SRICTRL_WANTPREQ 12 367#define S_LDT_SRICTRL_WANTPREQ 12
368#define M_LDT_SRICTRL_WANTPREQ _SB_MAKEMASK_32(2,S_LDT_SRICTRL_WANTPREQ) 368#define M_LDT_SRICTRL_WANTPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTPREQ)
369#define V_LDT_SRICTRL_WANTPREQ(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_WANTPREQ) 369#define V_LDT_SRICTRL_WANTPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTPREQ)
370#define G_LDT_SRICTRL_WANTPREQ(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_WANTPREQ,M_LDT_SRICTRL_WANTPREQ) 370#define G_LDT_SRICTRL_WANTPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTPREQ, M_LDT_SRICTRL_WANTPREQ)
371 371
372#define S_LDT_SRICTRL_BUFRELSPACE 16 372#define S_LDT_SRICTRL_BUFRELSPACE 16
373#define M_LDT_SRICTRL_BUFRELSPACE _SB_MAKEMASK_32(4,S_LDT_SRICTRL_BUFRELSPACE) 373#define M_LDT_SRICTRL_BUFRELSPACE _SB_MAKEMASK_32(4, S_LDT_SRICTRL_BUFRELSPACE)
374#define V_LDT_SRICTRL_BUFRELSPACE(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_BUFRELSPACE) 374#define V_LDT_SRICTRL_BUFRELSPACE(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_BUFRELSPACE)
375#define G_LDT_SRICTRL_BUFRELSPACE(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_BUFRELSPACE,M_LDT_SRICTRL_BUFRELSPACE) 375#define G_LDT_SRICTRL_BUFRELSPACE(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_BUFRELSPACE, M_LDT_SRICTRL_BUFRELSPACE)
376 376
377/* 377/*
378 * LDT SRI Transmit Buffer Count register (Table 8-26) 378 * LDT SRI Transmit Buffer Count register (Table 8-26)
379 */ 379 */
380 380
381#define S_LDT_TXBUFCNT_PCMD 0 381#define S_LDT_TXBUFCNT_PCMD 0
382#define M_LDT_TXBUFCNT_PCMD _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_PCMD) 382#define M_LDT_TXBUFCNT_PCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_PCMD)
383#define V_LDT_TXBUFCNT_PCMD(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_PCMD) 383#define V_LDT_TXBUFCNT_PCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_PCMD)
384#define G_LDT_TXBUFCNT_PCMD(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_PCMD,M_LDT_TXBUFCNT_PCMD) 384#define G_LDT_TXBUFCNT_PCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_PCMD, M_LDT_TXBUFCNT_PCMD)
385 385
386#define S_LDT_TXBUFCNT_PDATA 4 386#define S_LDT_TXBUFCNT_PDATA 4
387#define M_LDT_TXBUFCNT_PDATA _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_PDATA) 387#define M_LDT_TXBUFCNT_PDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_PDATA)
388#define V_LDT_TXBUFCNT_PDATA(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_PDATA) 388#define V_LDT_TXBUFCNT_PDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_PDATA)
389#define G_LDT_TXBUFCNT_PDATA(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_PDATA,M_LDT_TXBUFCNT_PDATA) 389#define G_LDT_TXBUFCNT_PDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_PDATA, M_LDT_TXBUFCNT_PDATA)
390 390
391#define S_LDT_TXBUFCNT_NPCMD 8 391#define S_LDT_TXBUFCNT_NPCMD 8
392#define M_LDT_TXBUFCNT_NPCMD _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_NPCMD) 392#define M_LDT_TXBUFCNT_NPCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_NPCMD)
393#define V_LDT_TXBUFCNT_NPCMD(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_NPCMD) 393#define V_LDT_TXBUFCNT_NPCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_NPCMD)
394#define G_LDT_TXBUFCNT_NPCMD(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_NPCMD,M_LDT_TXBUFCNT_NPCMD) 394#define G_LDT_TXBUFCNT_NPCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_NPCMD, M_LDT_TXBUFCNT_NPCMD)
395 395
396#define S_LDT_TXBUFCNT_NPDATA 12 396#define S_LDT_TXBUFCNT_NPDATA 12
397#define M_LDT_TXBUFCNT_NPDATA _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_NPDATA) 397#define M_LDT_TXBUFCNT_NPDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_NPDATA)
398#define V_LDT_TXBUFCNT_NPDATA(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_NPDATA) 398#define V_LDT_TXBUFCNT_NPDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_NPDATA)
399#define G_LDT_TXBUFCNT_NPDATA(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_NPDATA,M_LDT_TXBUFCNT_NPDATA) 399#define G_LDT_TXBUFCNT_NPDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_NPDATA, M_LDT_TXBUFCNT_NPDATA)
400 400
401#define S_LDT_TXBUFCNT_RCMD 16 401#define S_LDT_TXBUFCNT_RCMD 16
402#define M_LDT_TXBUFCNT_RCMD _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_RCMD) 402#define M_LDT_TXBUFCNT_RCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_RCMD)
403#define V_LDT_TXBUFCNT_RCMD(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_RCMD) 403#define V_LDT_TXBUFCNT_RCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_RCMD)
404#define G_LDT_TXBUFCNT_RCMD(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_RCMD,M_LDT_TXBUFCNT_RCMD) 404#define G_LDT_TXBUFCNT_RCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_RCMD, M_LDT_TXBUFCNT_RCMD)
405 405
406#define S_LDT_TXBUFCNT_RDATA 20 406#define S_LDT_TXBUFCNT_RDATA 20
407#define M_LDT_TXBUFCNT_RDATA _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_RDATA) 407#define M_LDT_TXBUFCNT_RDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_RDATA)
408#define V_LDT_TXBUFCNT_RDATA(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_RDATA) 408#define V_LDT_TXBUFCNT_RDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_RDATA)
409#define G_LDT_TXBUFCNT_RDATA(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_RDATA,M_LDT_TXBUFCNT_RDATA) 409#define G_LDT_TXBUFCNT_RDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_RDATA, M_LDT_TXBUFCNT_RDATA)
410 410
411#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 411#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
412/* 412/*
@@ -414,9 +414,9 @@
414 */ 414 */
415 415
416#define S_LDT_ADDSTATUS_TGTDONE 0 416#define S_LDT_ADDSTATUS_TGTDONE 0
417#define M_LDT_ADDSTATUS_TGTDONE _SB_MAKEMASK_32(8,S_LDT_ADDSTATUS_TGTDONE) 417#define M_LDT_ADDSTATUS_TGTDONE _SB_MAKEMASK_32(8, S_LDT_ADDSTATUS_TGTDONE)
418#define V_LDT_ADDSTATUS_TGTDONE(x) _SB_MAKEVALUE_32(x,S_LDT_ADDSTATUS_TGTDONE) 418#define V_LDT_ADDSTATUS_TGTDONE(x) _SB_MAKEVALUE_32(x, S_LDT_ADDSTATUS_TGTDONE)
419#define G_LDT_ADDSTATUS_TGTDONE(x) _SB_GETVALUE_32(x,S_LDT_ADDSTATUS_TGTDONE,M_LDT_ADDSTATUS_TGTDONE) 419#define G_LDT_ADDSTATUS_TGTDONE(x) _SB_GETVALUE_32(x, S_LDT_ADDSTATUS_TGTDONE, M_LDT_ADDSTATUS_TGTDONE)
420#endif /* 1250 PASS2 || 112x PASS1 */ 420#endif /* 1250 PASS2 || 112x PASS1 */
421 421
422#endif 422#endif
diff --git a/include/asm-mips/sibyte/sb1250_mac.h b/include/asm-mips/sibyte/sb1250_mac.h
index 833c8b59d687..b6faf08ca81d 100644
--- a/include/asm-mips/sibyte/sb1250_mac.h
+++ b/include/asm-mips/sibyte/sb1250_mac.h
@@ -55,8 +55,8 @@
55#define M_MAC_BURST_EN _SB_MAKEMASK1(5) 55#define M_MAC_BURST_EN _SB_MAKEMASK1(5)
56 56
57#define S_MAC_TX_PAUSE _SB_MAKE64(6) 57#define S_MAC_TX_PAUSE _SB_MAKE64(6)
58#define M_MAC_TX_PAUSE_CNT _SB_MAKEMASK(3,S_MAC_TX_PAUSE) 58#define M_MAC_TX_PAUSE_CNT _SB_MAKEMASK(3, S_MAC_TX_PAUSE)
59#define V_MAC_TX_PAUSE_CNT(x) _SB_MAKEVALUE(x,S_MAC_TX_PAUSE) 59#define V_MAC_TX_PAUSE_CNT(x) _SB_MAKEVALUE(x, S_MAC_TX_PAUSE)
60 60
61#define K_MAC_TX_PAUSE_CNT_512 0 61#define K_MAC_TX_PAUSE_CNT_512 0
62#define K_MAC_TX_PAUSE_CNT_1K 1 62#define K_MAC_TX_PAUSE_CNT_1K 1
@@ -76,7 +76,7 @@
76#define V_MAC_TX_PAUSE_CNT_32K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_32K) 76#define V_MAC_TX_PAUSE_CNT_32K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_32K)
77#define V_MAC_TX_PAUSE_CNT_64K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_64K) 77#define V_MAC_TX_PAUSE_CNT_64K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_64K)
78 78
79#define M_MAC_RESERVED1 _SB_MAKEMASK(8,9) 79#define M_MAC_RESERVED1 _SB_MAKEMASK(8, 9)
80 80
81#define M_MAC_AP_STAT_EN _SB_MAKEMASK1(17) 81#define M_MAC_AP_STAT_EN _SB_MAKEMASK1(17)
82 82
@@ -91,15 +91,15 @@
91#define M_MAC_DRP_OSZPKT_EN _SB_MAKEMASK1(24) 91#define M_MAC_DRP_OSZPKT_EN _SB_MAKEMASK1(24)
92#define M_MAC_DRP_LENERRPKT_EN _SB_MAKEMASK1(25) 92#define M_MAC_DRP_LENERRPKT_EN _SB_MAKEMASK1(25)
93 93
94#define M_MAC_RESERVED3 _SB_MAKEMASK(6,26) 94#define M_MAC_RESERVED3 _SB_MAKEMASK(6, 26)
95 95
96#define M_MAC_BYPASS_SEL _SB_MAKEMASK1(32) 96#define M_MAC_BYPASS_SEL _SB_MAKEMASK1(32)
97#define M_MAC_HDX_EN _SB_MAKEMASK1(33) 97#define M_MAC_HDX_EN _SB_MAKEMASK1(33)
98 98
99#define S_MAC_SPEED_SEL _SB_MAKE64(34) 99#define S_MAC_SPEED_SEL _SB_MAKE64(34)
100#define M_MAC_SPEED_SEL _SB_MAKEMASK(2,S_MAC_SPEED_SEL) 100#define M_MAC_SPEED_SEL _SB_MAKEMASK(2, S_MAC_SPEED_SEL)
101#define V_MAC_SPEED_SEL(x) _SB_MAKEVALUE(x,S_MAC_SPEED_SEL) 101#define V_MAC_SPEED_SEL(x) _SB_MAKEVALUE(x, S_MAC_SPEED_SEL)
102#define G_MAC_SPEED_SEL(x) _SB_GETVALUE(x,S_MAC_SPEED_SEL,M_MAC_SPEED_SEL) 102#define G_MAC_SPEED_SEL(x) _SB_GETVALUE(x, S_MAC_SPEED_SEL, M_MAC_SPEED_SEL)
103 103
104#define K_MAC_SPEED_SEL_10MBPS 0 104#define K_MAC_SPEED_SEL_10MBPS 0
105#define K_MAC_SPEED_SEL_100MBPS 1 105#define K_MAC_SPEED_SEL_100MBPS 1
@@ -117,9 +117,9 @@
117#define M_MAC_SS_EN _SB_MAKEMASK1(39) 117#define M_MAC_SS_EN _SB_MAKEMASK1(39)
118 118
119#define S_MAC_BYPASS_CFG _SB_MAKE64(40) 119#define S_MAC_BYPASS_CFG _SB_MAKE64(40)
120#define M_MAC_BYPASS_CFG _SB_MAKEMASK(2,S_MAC_BYPASS_CFG) 120#define M_MAC_BYPASS_CFG _SB_MAKEMASK(2, S_MAC_BYPASS_CFG)
121#define V_MAC_BYPASS_CFG(x) _SB_MAKEVALUE(x,S_MAC_BYPASS_CFG) 121#define V_MAC_BYPASS_CFG(x) _SB_MAKEVALUE(x, S_MAC_BYPASS_CFG)
122#define G_MAC_BYPASS_CFG(x) _SB_GETVALUE(x,S_MAC_BYPASS_CFG,M_MAC_BYPASS_CFG) 122#define G_MAC_BYPASS_CFG(x) _SB_GETVALUE(x, S_MAC_BYPASS_CFG, M_MAC_BYPASS_CFG)
123 123
124#define K_MAC_BYPASS_GMII 0 124#define K_MAC_BYPASS_GMII 0
125#define K_MAC_BYPASS_ENCODED 1 125#define K_MAC_BYPASS_ENCODED 1
@@ -138,9 +138,9 @@
138#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 138#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
139 139
140#define S_MAC_BYPASS_IFG _SB_MAKE64(46) 140#define S_MAC_BYPASS_IFG _SB_MAKE64(46)
141#define M_MAC_BYPASS_IFG _SB_MAKEMASK(8,S_MAC_BYPASS_IFG) 141#define M_MAC_BYPASS_IFG _SB_MAKEMASK(8, S_MAC_BYPASS_IFG)
142#define V_MAC_BYPASS_IFG(x) _SB_MAKEVALUE(x,S_MAC_BYPASS_IFG) 142#define V_MAC_BYPASS_IFG(x) _SB_MAKEVALUE(x, S_MAC_BYPASS_IFG)
143#define G_MAC_BYPASS_IFG(x) _SB_GETVALUE(x,S_MAC_BYPASS_IFG,M_MAC_BYPASS_IFG) 143#define G_MAC_BYPASS_IFG(x) _SB_GETVALUE(x, S_MAC_BYPASS_IFG, M_MAC_BYPASS_IFG)
144 144
145#define K_MAC_FC_CMD_DISABLED 0 145#define K_MAC_FC_CMD_DISABLED 0
146#define K_MAC_FC_CMD_ENABLED 1 146#define K_MAC_FC_CMD_ENABLED 1
@@ -153,14 +153,14 @@
153#define M_MAC_FC_SEL _SB_MAKEMASK1(54) 153#define M_MAC_FC_SEL _SB_MAKEMASK1(54)
154 154
155#define S_MAC_FC_CMD _SB_MAKE64(55) 155#define S_MAC_FC_CMD _SB_MAKE64(55)
156#define M_MAC_FC_CMD _SB_MAKEMASK(2,S_MAC_FC_CMD) 156#define M_MAC_FC_CMD _SB_MAKEMASK(2, S_MAC_FC_CMD)
157#define V_MAC_FC_CMD(x) _SB_MAKEVALUE(x,S_MAC_FC_CMD) 157#define V_MAC_FC_CMD(x) _SB_MAKEVALUE(x, S_MAC_FC_CMD)
158#define G_MAC_FC_CMD(x) _SB_GETVALUE(x,S_MAC_FC_CMD,M_MAC_FC_CMD) 158#define G_MAC_FC_CMD(x) _SB_GETVALUE(x, S_MAC_FC_CMD, M_MAC_FC_CMD)
159 159
160#define S_MAC_RX_CH_SEL _SB_MAKE64(57) 160#define S_MAC_RX_CH_SEL _SB_MAKE64(57)
161#define M_MAC_RX_CH_SEL _SB_MAKEMASK(7,S_MAC_RX_CH_SEL) 161#define M_MAC_RX_CH_SEL _SB_MAKEMASK(7, S_MAC_RX_CH_SEL)
162#define V_MAC_RX_CH_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_SEL) 162#define V_MAC_RX_CH_SEL(x) _SB_MAKEVALUE(x, S_MAC_RX_CH_SEL)
163#define G_MAC_RX_CH_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_SEL,M_MAC_RX_CH_SEL) 163#define G_MAC_RX_CH_SEL(x) _SB_GETVALUE(x, S_MAC_RX_CH_SEL, M_MAC_RX_CH_SEL)
164 164
165 165
166/* 166/*
@@ -202,14 +202,14 @@
202 */ 202 */
203 203
204#define S_MAC_TXD_WEIGHT0 _SB_MAKE64(0) 204#define S_MAC_TXD_WEIGHT0 _SB_MAKE64(0)
205#define M_MAC_TXD_WEIGHT0 _SB_MAKEMASK(4,S_MAC_TXD_WEIGHT0) 205#define M_MAC_TXD_WEIGHT0 _SB_MAKEMASK(4, S_MAC_TXD_WEIGHT0)
206#define V_MAC_TXD_WEIGHT0(x) _SB_MAKEVALUE(x,S_MAC_TXD_WEIGHT0) 206#define V_MAC_TXD_WEIGHT0(x) _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT0)
207#define G_MAC_TXD_WEIGHT0(x) _SB_GETVALUE(x,S_MAC_TXD_WEIGHT0,M_MAC_TXD_WEIGHT0) 207#define G_MAC_TXD_WEIGHT0(x) _SB_GETVALUE(x, S_MAC_TXD_WEIGHT0, M_MAC_TXD_WEIGHT0)
208 208
209#define S_MAC_TXD_WEIGHT1 _SB_MAKE64(4) 209#define S_MAC_TXD_WEIGHT1 _SB_MAKE64(4)
210#define M_MAC_TXD_WEIGHT1 _SB_MAKEMASK(4,S_MAC_TXD_WEIGHT1) 210#define M_MAC_TXD_WEIGHT1 _SB_MAKEMASK(4, S_MAC_TXD_WEIGHT1)
211#define V_MAC_TXD_WEIGHT1(x) _SB_MAKEVALUE(x,S_MAC_TXD_WEIGHT1) 211#define V_MAC_TXD_WEIGHT1(x) _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT1)
212#define G_MAC_TXD_WEIGHT1(x) _SB_GETVALUE(x,S_MAC_TXD_WEIGHT1,M_MAC_TXD_WEIGHT1) 212#define G_MAC_TXD_WEIGHT1(x) _SB_GETVALUE(x, S_MAC_TXD_WEIGHT1, M_MAC_TXD_WEIGHT1)
213 213
214/* 214/*
215 * MAC Fifo Threshhold registers (Table 9-14) 215 * MAC Fifo Threshhold registers (Table 9-14)
@@ -221,50 +221,50 @@
221#define S_MAC_TX_WR_THRSH _SB_MAKE64(0) 221#define S_MAC_TX_WR_THRSH _SB_MAKE64(0)
222#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) 222#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
223/* XXX: Can't enable, as it has the same name as a pass2+ define below. */ 223/* XXX: Can't enable, as it has the same name as a pass2+ define below. */
224/* #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(6,S_MAC_TX_WR_THRSH) */ 224/* #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(6, S_MAC_TX_WR_THRSH) */
225#endif /* up to 1250 PASS1 */ 225#endif /* up to 1250 PASS1 */
226#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 226#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
227#define M_MAC_TX_WR_THRSH _SB_MAKEMASK(7,S_MAC_TX_WR_THRSH) 227#define M_MAC_TX_WR_THRSH _SB_MAKEMASK(7, S_MAC_TX_WR_THRSH)
228#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 228#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
229#define V_MAC_TX_WR_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_WR_THRSH) 229#define V_MAC_TX_WR_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_WR_THRSH)
230#define G_MAC_TX_WR_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_WR_THRSH,M_MAC_TX_WR_THRSH) 230#define G_MAC_TX_WR_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_WR_THRSH, M_MAC_TX_WR_THRSH)
231 231
232#define S_MAC_TX_RD_THRSH _SB_MAKE64(8) 232#define S_MAC_TX_RD_THRSH _SB_MAKE64(8)
233#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) 233#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
234/* XXX: Can't enable, as it has the same name as a pass2+ define below. */ 234/* XXX: Can't enable, as it has the same name as a pass2+ define below. */
235/* #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(6,S_MAC_TX_RD_THRSH) */ 235/* #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(6, S_MAC_TX_RD_THRSH) */
236#endif /* up to 1250 PASS1 */ 236#endif /* up to 1250 PASS1 */
237#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 237#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
238#define M_MAC_TX_RD_THRSH _SB_MAKEMASK(7,S_MAC_TX_RD_THRSH) 238#define M_MAC_TX_RD_THRSH _SB_MAKEMASK(7, S_MAC_TX_RD_THRSH)
239#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 239#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
240#define V_MAC_TX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RD_THRSH) 240#define V_MAC_TX_RD_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_RD_THRSH)
241#define G_MAC_TX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RD_THRSH,M_MAC_TX_RD_THRSH) 241#define G_MAC_TX_RD_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_RD_THRSH, M_MAC_TX_RD_THRSH)
242 242
243#define S_MAC_TX_RL_THRSH _SB_MAKE64(16) 243#define S_MAC_TX_RL_THRSH _SB_MAKE64(16)
244#define M_MAC_TX_RL_THRSH _SB_MAKEMASK(4,S_MAC_TX_RL_THRSH) 244#define M_MAC_TX_RL_THRSH _SB_MAKEMASK(4, S_MAC_TX_RL_THRSH)
245#define V_MAC_TX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RL_THRSH) 245#define V_MAC_TX_RL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_RL_THRSH)
246#define G_MAC_TX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RL_THRSH,M_MAC_TX_RL_THRSH) 246#define G_MAC_TX_RL_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_RL_THRSH, M_MAC_TX_RL_THRSH)
247 247
248#define S_MAC_RX_PL_THRSH _SB_MAKE64(24) 248#define S_MAC_RX_PL_THRSH _SB_MAKE64(24)
249#define M_MAC_RX_PL_THRSH _SB_MAKEMASK(6,S_MAC_RX_PL_THRSH) 249#define M_MAC_RX_PL_THRSH _SB_MAKEMASK(6, S_MAC_RX_PL_THRSH)
250#define V_MAC_RX_PL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_PL_THRSH) 250#define V_MAC_RX_PL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_PL_THRSH)
251#define G_MAC_RX_PL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_PL_THRSH,M_MAC_RX_PL_THRSH) 251#define G_MAC_RX_PL_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_PL_THRSH, M_MAC_RX_PL_THRSH)
252 252
253#define S_MAC_RX_RD_THRSH _SB_MAKE64(32) 253#define S_MAC_RX_RD_THRSH _SB_MAKE64(32)
254#define M_MAC_RX_RD_THRSH _SB_MAKEMASK(6,S_MAC_RX_RD_THRSH) 254#define M_MAC_RX_RD_THRSH _SB_MAKEMASK(6, S_MAC_RX_RD_THRSH)
255#define V_MAC_RX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RD_THRSH) 255#define V_MAC_RX_RD_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_RD_THRSH)
256#define G_MAC_RX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RD_THRSH,M_MAC_RX_RD_THRSH) 256#define G_MAC_RX_RD_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_RD_THRSH, M_MAC_RX_RD_THRSH)
257 257
258#define S_MAC_RX_RL_THRSH _SB_MAKE64(40) 258#define S_MAC_RX_RL_THRSH _SB_MAKE64(40)
259#define M_MAC_RX_RL_THRSH _SB_MAKEMASK(6,S_MAC_RX_RL_THRSH) 259#define M_MAC_RX_RL_THRSH _SB_MAKEMASK(6, S_MAC_RX_RL_THRSH)
260#define V_MAC_RX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RL_THRSH) 260#define V_MAC_RX_RL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_RL_THRSH)
261#define G_MAC_RX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RL_THRSH,M_MAC_RX_RL_THRSH) 261#define G_MAC_RX_RL_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_RL_THRSH, M_MAC_RX_RL_THRSH)
262 262
263#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 263#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
264#define S_MAC_ENC_FC_THRSH _SB_MAKE64(56) 264#define S_MAC_ENC_FC_THRSH _SB_MAKE64(56)
265#define M_MAC_ENC_FC_THRSH _SB_MAKEMASK(6,S_MAC_ENC_FC_THRSH) 265#define M_MAC_ENC_FC_THRSH _SB_MAKEMASK(6, S_MAC_ENC_FC_THRSH)
266#define V_MAC_ENC_FC_THRSH(x) _SB_MAKEVALUE(x,S_MAC_ENC_FC_THRSH) 266#define V_MAC_ENC_FC_THRSH(x) _SB_MAKEVALUE(x, S_MAC_ENC_FC_THRSH)
267#define G_MAC_ENC_FC_THRSH(x) _SB_GETVALUE(x,S_MAC_ENC_FC_THRSH,M_MAC_ENC_FC_THRSH) 267#define G_MAC_ENC_FC_THRSH(x) _SB_GETVALUE(x, S_MAC_ENC_FC_THRSH, M_MAC_ENC_FC_THRSH)
268#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 268#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
269 269
270/* 270/*
@@ -276,51 +276,51 @@
276 276
277/* XXXCGD: ??? Unused in pass2? */ 277/* XXXCGD: ??? Unused in pass2? */
278#define S_MAC_IFG_RX _SB_MAKE64(0) 278#define S_MAC_IFG_RX _SB_MAKE64(0)
279#define M_MAC_IFG_RX _SB_MAKEMASK(6,S_MAC_IFG_RX) 279#define M_MAC_IFG_RX _SB_MAKEMASK(6, S_MAC_IFG_RX)
280#define V_MAC_IFG_RX(x) _SB_MAKEVALUE(x,S_MAC_IFG_RX) 280#define V_MAC_IFG_RX(x) _SB_MAKEVALUE(x, S_MAC_IFG_RX)
281#define G_MAC_IFG_RX(x) _SB_GETVALUE(x,S_MAC_IFG_RX,M_MAC_IFG_RX) 281#define G_MAC_IFG_RX(x) _SB_GETVALUE(x, S_MAC_IFG_RX, M_MAC_IFG_RX)
282 282
283#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 283#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
284#define S_MAC_PRE_LEN _SB_MAKE64(0) 284#define S_MAC_PRE_LEN _SB_MAKE64(0)
285#define M_MAC_PRE_LEN _SB_MAKEMASK(6,S_MAC_PRE_LEN) 285#define M_MAC_PRE_LEN _SB_MAKEMASK(6, S_MAC_PRE_LEN)
286#define V_MAC_PRE_LEN(x) _SB_MAKEVALUE(x,S_MAC_PRE_LEN) 286#define V_MAC_PRE_LEN(x) _SB_MAKEVALUE(x, S_MAC_PRE_LEN)
287#define G_MAC_PRE_LEN(x) _SB_GETVALUE(x,S_MAC_PRE_LEN,M_MAC_PRE_LEN) 287#define G_MAC_PRE_LEN(x) _SB_GETVALUE(x, S_MAC_PRE_LEN, M_MAC_PRE_LEN)
288#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 288#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
289 289
290#define S_MAC_IFG_TX _SB_MAKE64(6) 290#define S_MAC_IFG_TX _SB_MAKE64(6)
291#define M_MAC_IFG_TX _SB_MAKEMASK(6,S_MAC_IFG_TX) 291#define M_MAC_IFG_TX _SB_MAKEMASK(6, S_MAC_IFG_TX)
292#define V_MAC_IFG_TX(x) _SB_MAKEVALUE(x,S_MAC_IFG_TX) 292#define V_MAC_IFG_TX(x) _SB_MAKEVALUE(x, S_MAC_IFG_TX)
293#define G_MAC_IFG_TX(x) _SB_GETVALUE(x,S_MAC_IFG_TX,M_MAC_IFG_TX) 293#define G_MAC_IFG_TX(x) _SB_GETVALUE(x, S_MAC_IFG_TX, M_MAC_IFG_TX)
294 294
295#define S_MAC_IFG_THRSH _SB_MAKE64(12) 295#define S_MAC_IFG_THRSH _SB_MAKE64(12)
296#define M_MAC_IFG_THRSH _SB_MAKEMASK(6,S_MAC_IFG_THRSH) 296#define M_MAC_IFG_THRSH _SB_MAKEMASK(6, S_MAC_IFG_THRSH)
297#define V_MAC_IFG_THRSH(x) _SB_MAKEVALUE(x,S_MAC_IFG_THRSH) 297#define V_MAC_IFG_THRSH(x) _SB_MAKEVALUE(x, S_MAC_IFG_THRSH)
298#define G_MAC_IFG_THRSH(x) _SB_GETVALUE(x,S_MAC_IFG_THRSH,M_MAC_IFG_THRSH) 298#define G_MAC_IFG_THRSH(x) _SB_GETVALUE(x, S_MAC_IFG_THRSH, M_MAC_IFG_THRSH)
299 299
300#define S_MAC_BACKOFF_SEL _SB_MAKE64(18) 300#define S_MAC_BACKOFF_SEL _SB_MAKE64(18)
301#define M_MAC_BACKOFF_SEL _SB_MAKEMASK(4,S_MAC_BACKOFF_SEL) 301#define M_MAC_BACKOFF_SEL _SB_MAKEMASK(4, S_MAC_BACKOFF_SEL)
302#define V_MAC_BACKOFF_SEL(x) _SB_MAKEVALUE(x,S_MAC_BACKOFF_SEL) 302#define V_MAC_BACKOFF_SEL(x) _SB_MAKEVALUE(x, S_MAC_BACKOFF_SEL)
303#define G_MAC_BACKOFF_SEL(x) _SB_GETVALUE(x,S_MAC_BACKOFF_SEL,M_MAC_BACKOFF_SEL) 303#define G_MAC_BACKOFF_SEL(x) _SB_GETVALUE(x, S_MAC_BACKOFF_SEL, M_MAC_BACKOFF_SEL)
304 304
305#define S_MAC_LFSR_SEED _SB_MAKE64(22) 305#define S_MAC_LFSR_SEED _SB_MAKE64(22)
306#define M_MAC_LFSR_SEED _SB_MAKEMASK(8,S_MAC_LFSR_SEED) 306#define M_MAC_LFSR_SEED _SB_MAKEMASK(8, S_MAC_LFSR_SEED)
307#define V_MAC_LFSR_SEED(x) _SB_MAKEVALUE(x,S_MAC_LFSR_SEED) 307#define V_MAC_LFSR_SEED(x) _SB_MAKEVALUE(x, S_MAC_LFSR_SEED)
308#define G_MAC_LFSR_SEED(x) _SB_GETVALUE(x,S_MAC_LFSR_SEED,M_MAC_LFSR_SEED) 308#define G_MAC_LFSR_SEED(x) _SB_GETVALUE(x, S_MAC_LFSR_SEED, M_MAC_LFSR_SEED)
309 309
310#define S_MAC_SLOT_SIZE _SB_MAKE64(30) 310#define S_MAC_SLOT_SIZE _SB_MAKE64(30)
311#define M_MAC_SLOT_SIZE _SB_MAKEMASK(10,S_MAC_SLOT_SIZE) 311#define M_MAC_SLOT_SIZE _SB_MAKEMASK(10, S_MAC_SLOT_SIZE)
312#define V_MAC_SLOT_SIZE(x) _SB_MAKEVALUE(x,S_MAC_SLOT_SIZE) 312#define V_MAC_SLOT_SIZE(x) _SB_MAKEVALUE(x, S_MAC_SLOT_SIZE)
313#define G_MAC_SLOT_SIZE(x) _SB_GETVALUE(x,S_MAC_SLOT_SIZE,M_MAC_SLOT_SIZE) 313#define G_MAC_SLOT_SIZE(x) _SB_GETVALUE(x, S_MAC_SLOT_SIZE, M_MAC_SLOT_SIZE)
314 314
315#define S_MAC_MIN_FRAMESZ _SB_MAKE64(40) 315#define S_MAC_MIN_FRAMESZ _SB_MAKE64(40)
316#define M_MAC_MIN_FRAMESZ _SB_MAKEMASK(8,S_MAC_MIN_FRAMESZ) 316#define M_MAC_MIN_FRAMESZ _SB_MAKEMASK(8, S_MAC_MIN_FRAMESZ)
317#define V_MAC_MIN_FRAMESZ(x) _SB_MAKEVALUE(x,S_MAC_MIN_FRAMESZ) 317#define V_MAC_MIN_FRAMESZ(x) _SB_MAKEVALUE(x, S_MAC_MIN_FRAMESZ)
318#define G_MAC_MIN_FRAMESZ(x) _SB_GETVALUE(x,S_MAC_MIN_FRAMESZ,M_MAC_MIN_FRAMESZ) 318#define G_MAC_MIN_FRAMESZ(x) _SB_GETVALUE(x, S_MAC_MIN_FRAMESZ, M_MAC_MIN_FRAMESZ)
319 319
320#define S_MAC_MAX_FRAMESZ _SB_MAKE64(48) 320#define S_MAC_MAX_FRAMESZ _SB_MAKE64(48)
321#define M_MAC_MAX_FRAMESZ _SB_MAKEMASK(16,S_MAC_MAX_FRAMESZ) 321#define M_MAC_MAX_FRAMESZ _SB_MAKEMASK(16, S_MAC_MAX_FRAMESZ)
322#define V_MAC_MAX_FRAMESZ(x) _SB_MAKEVALUE(x,S_MAC_MAX_FRAMESZ) 322#define V_MAC_MAX_FRAMESZ(x) _SB_MAKEVALUE(x, S_MAC_MAX_FRAMESZ)
323#define G_MAC_MAX_FRAMESZ(x) _SB_GETVALUE(x,S_MAC_MAX_FRAMESZ,M_MAC_MAX_FRAMESZ) 323#define G_MAC_MAX_FRAMESZ(x) _SB_GETVALUE(x, S_MAC_MAX_FRAMESZ, M_MAC_MAX_FRAMESZ)
324 324
325/* 325/*
326 * These constants are used to configure the fields within the Frame 326 * These constants are used to configure the fields within the Frame
@@ -377,20 +377,20 @@
377 */ 377 */
378 378
379#define S_MAC_VLAN_TAG _SB_MAKE64(0) 379#define S_MAC_VLAN_TAG _SB_MAKE64(0)
380#define M_MAC_VLAN_TAG _SB_MAKEMASK(32,S_MAC_VLAN_TAG) 380#define M_MAC_VLAN_TAG _SB_MAKEMASK(32, S_MAC_VLAN_TAG)
381#define V_MAC_VLAN_TAG(x) _SB_MAKEVALUE(x,S_MAC_VLAN_TAG) 381#define V_MAC_VLAN_TAG(x) _SB_MAKEVALUE(x, S_MAC_VLAN_TAG)
382#define G_MAC_VLAN_TAG(x) _SB_GETVALUE(x,S_MAC_VLAN_TAG,M_MAC_VLAN_TAG) 382#define G_MAC_VLAN_TAG(x) _SB_GETVALUE(x, S_MAC_VLAN_TAG, M_MAC_VLAN_TAG)
383 383
384#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 384#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
385#define S_MAC_TX_PKT_OFFSET _SB_MAKE64(32) 385#define S_MAC_TX_PKT_OFFSET _SB_MAKE64(32)
386#define M_MAC_TX_PKT_OFFSET _SB_MAKEMASK(8,S_MAC_TX_PKT_OFFSET) 386#define M_MAC_TX_PKT_OFFSET _SB_MAKEMASK(8, S_MAC_TX_PKT_OFFSET)
387#define V_MAC_TX_PKT_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_TX_PKT_OFFSET) 387#define V_MAC_TX_PKT_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_TX_PKT_OFFSET)
388#define G_MAC_TX_PKT_OFFSET(x) _SB_GETVALUE(x,S_MAC_TX_PKT_OFFSET,M_MAC_TX_PKT_OFFSET) 388#define G_MAC_TX_PKT_OFFSET(x) _SB_GETVALUE(x, S_MAC_TX_PKT_OFFSET, M_MAC_TX_PKT_OFFSET)
389 389
390#define S_MAC_TX_CRC_OFFSET _SB_MAKE64(40) 390#define S_MAC_TX_CRC_OFFSET _SB_MAKE64(40)
391#define M_MAC_TX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_TX_CRC_OFFSET) 391#define M_MAC_TX_CRC_OFFSET _SB_MAKEMASK(8, S_MAC_TX_CRC_OFFSET)
392#define V_MAC_TX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_TX_CRC_OFFSET) 392#define V_MAC_TX_CRC_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_TX_CRC_OFFSET)
393#define G_MAC_TX_CRC_OFFSET(x) _SB_GETVALUE(x,S_MAC_TX_CRC_OFFSET,M_MAC_TX_CRC_OFFSET) 393#define G_MAC_TX_CRC_OFFSET(x) _SB_GETVALUE(x, S_MAC_TX_CRC_OFFSET, M_MAC_TX_CRC_OFFSET)
394 394
395#define M_MAC_CH_BASE_FC_EN _SB_MAKEMASK1(48) 395#define M_MAC_CH_BASE_FC_EN _SB_MAKEMASK1(48)
396#endif /* 1250 PASS3 || 112x PASS1 */ 396#endif /* 1250 PASS3 || 112x PASS1 */
@@ -425,7 +425,7 @@
425 * is that you'll use one of the "S_" things above 425 * is that you'll use one of the "S_" things above
426 * and pass just the six bits to a DMA-channel-specific ISR 426 * and pass just the six bits to a DMA-channel-specific ISR
427 */ 427 */
428#define M_MAC_INT_CHANNEL _SB_MAKEMASK(8,0) 428#define M_MAC_INT_CHANNEL _SB_MAKEMASK(8, 0)
429#define M_MAC_INT_EOP_COUNT _SB_MAKEMASK1(0) 429#define M_MAC_INT_EOP_COUNT _SB_MAKEMASK1(0)
430#define M_MAC_INT_EOP_TIMER _SB_MAKEMASK1(1) 430#define M_MAC_INT_EOP_TIMER _SB_MAKEMASK1(1)
431#define M_MAC_INT_EOP_SEEN _SB_MAKEMASK1(2) 431#define M_MAC_INT_EOP_SEEN _SB_MAKEMASK1(2)
@@ -440,19 +440,19 @@
440 * In the following definitions we use ch (0/1) and txrx (TX=1, RX=0, see 440 * In the following definitions we use ch (0/1) and txrx (TX=1, RX=0, see
441 * also DMA_TX/DMA_RX in sb_regs.h). 441 * also DMA_TX/DMA_RX in sb_regs.h).
442 */ 442 */
443#define S_MAC_STATUS_CH_OFFSET(ch,txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH) 443#define S_MAC_STATUS_CH_OFFSET(ch, txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH)
444 444
445#define M_MAC_STATUS_CHANNEL(ch,txrx) _SB_MAKEVALUE(_SB_MAKEMASK(8,0),S_MAC_STATUS_CH_OFFSET(ch,txrx)) 445#define M_MAC_STATUS_CHANNEL(ch, txrx) _SB_MAKEVALUE(_SB_MAKEMASK(8, 0), S_MAC_STATUS_CH_OFFSET(ch, txrx))
446#define M_MAC_STATUS_EOP_COUNT(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_COUNT,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 446#define M_MAC_STATUS_EOP_COUNT(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_COUNT, S_MAC_STATUS_CH_OFFSET(ch, txrx))
447#define M_MAC_STATUS_EOP_TIMER(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_TIMER,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 447#define M_MAC_STATUS_EOP_TIMER(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_TIMER, S_MAC_STATUS_CH_OFFSET(ch, txrx))
448#define M_MAC_STATUS_EOP_SEEN(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_SEEN,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 448#define M_MAC_STATUS_EOP_SEEN(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_SEEN, S_MAC_STATUS_CH_OFFSET(ch, txrx))
449#define M_MAC_STATUS_HWM(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_HWM,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 449#define M_MAC_STATUS_HWM(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_HWM, S_MAC_STATUS_CH_OFFSET(ch, txrx))
450#define M_MAC_STATUS_LWM(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_LWM,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 450#define M_MAC_STATUS_LWM(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_LWM, S_MAC_STATUS_CH_OFFSET(ch, txrx))
451#define M_MAC_STATUS_DSCR(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DSCR,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 451#define M_MAC_STATUS_DSCR(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DSCR, S_MAC_STATUS_CH_OFFSET(ch, txrx))
452#define M_MAC_STATUS_ERR(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_ERR,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 452#define M_MAC_STATUS_ERR(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_ERR, S_MAC_STATUS_CH_OFFSET(ch, txrx))
453#define M_MAC_STATUS_DZERO(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DZERO,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 453#define M_MAC_STATUS_DZERO(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DZERO, S_MAC_STATUS_CH_OFFSET(ch, txrx))
454#define M_MAC_STATUS_DROP(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DROP,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 454#define M_MAC_STATUS_DROP(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DROP, S_MAC_STATUS_CH_OFFSET(ch, txrx))
455#define M_MAC_STATUS_OTHER_ERR _SB_MAKEVALUE(_SB_MAKEMASK(7,0),40) 455#define M_MAC_STATUS_OTHER_ERR _SB_MAKEVALUE(_SB_MAKEMASK(7, 0), 40)
456 456
457 457
458#define M_MAC_RX_UNDRFL _SB_MAKEMASK1(40) 458#define M_MAC_RX_UNDRFL _SB_MAKEMASK1(40)
@@ -467,9 +467,9 @@
467#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 467#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
468 468
469#define S_MAC_COUNTER_ADDR _SB_MAKE64(47) 469#define S_MAC_COUNTER_ADDR _SB_MAKE64(47)
470#define M_MAC_COUNTER_ADDR _SB_MAKEMASK(5,S_MAC_COUNTER_ADDR) 470#define M_MAC_COUNTER_ADDR _SB_MAKEMASK(5, S_MAC_COUNTER_ADDR)
471#define V_MAC_COUNTER_ADDR(x) _SB_MAKEVALUE(x,S_MAC_COUNTER_ADDR) 471#define V_MAC_COUNTER_ADDR(x) _SB_MAKEVALUE(x, S_MAC_COUNTER_ADDR)
472#define G_MAC_COUNTER_ADDR(x) _SB_GETVALUE(x,S_MAC_COUNTER_ADDR,M_MAC_COUNTER_ADDR) 472#define G_MAC_COUNTER_ADDR(x) _SB_GETVALUE(x, S_MAC_COUNTER_ADDR, M_MAC_COUNTER_ADDR)
473 473
474#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 474#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
475#define M_MAC_TX_PAUSE_ON _SB_MAKEMASK1(52) 475#define M_MAC_TX_PAUSE_ON _SB_MAKEMASK1(52)
@@ -483,24 +483,24 @@
483 */ 483 */
484 484
485#define S_MAC_TX_WRPTR _SB_MAKE64(0) 485#define S_MAC_TX_WRPTR _SB_MAKE64(0)
486#define M_MAC_TX_WRPTR _SB_MAKEMASK(6,S_MAC_TX_WRPTR) 486#define M_MAC_TX_WRPTR _SB_MAKEMASK(6, S_MAC_TX_WRPTR)
487#define V_MAC_TX_WRPTR(x) _SB_MAKEVALUE(x,S_MAC_TX_WRPTR) 487#define V_MAC_TX_WRPTR(x) _SB_MAKEVALUE(x, S_MAC_TX_WRPTR)
488#define G_MAC_TX_WRPTR(x) _SB_GETVALUE(x,S_MAC_TX_WRPTR,M_MAC_TX_WRPTR) 488#define G_MAC_TX_WRPTR(x) _SB_GETVALUE(x, S_MAC_TX_WRPTR, M_MAC_TX_WRPTR)
489 489
490#define S_MAC_TX_RDPTR _SB_MAKE64(8) 490#define S_MAC_TX_RDPTR _SB_MAKE64(8)
491#define M_MAC_TX_RDPTR _SB_MAKEMASK(6,S_MAC_TX_RDPTR) 491#define M_MAC_TX_RDPTR _SB_MAKEMASK(6, S_MAC_TX_RDPTR)
492#define V_MAC_TX_RDPTR(x) _SB_MAKEVALUE(x,S_MAC_TX_RDPTR) 492#define V_MAC_TX_RDPTR(x) _SB_MAKEVALUE(x, S_MAC_TX_RDPTR)
493#define G_MAC_TX_RDPTR(x) _SB_GETVALUE(x,S_MAC_TX_RDPTR,M_MAC_TX_RDPTR) 493#define G_MAC_TX_RDPTR(x) _SB_GETVALUE(x, S_MAC_TX_RDPTR, M_MAC_TX_RDPTR)
494 494
495#define S_MAC_RX_WRPTR _SB_MAKE64(16) 495#define S_MAC_RX_WRPTR _SB_MAKE64(16)
496#define M_MAC_RX_WRPTR _SB_MAKEMASK(6,S_MAC_RX_WRPTR) 496#define M_MAC_RX_WRPTR _SB_MAKEMASK(6, S_MAC_RX_WRPTR)
497#define V_MAC_RX_WRPTR(x) _SB_MAKEVALUE(x,S_MAC_RX_WRPTR) 497#define V_MAC_RX_WRPTR(x) _SB_MAKEVALUE(x, S_MAC_RX_WRPTR)
498#define G_MAC_RX_WRPTR(x) _SB_GETVALUE(x,S_MAC_RX_WRPTR,M_MAC_TX_WRPTR) 498#define G_MAC_RX_WRPTR(x) _SB_GETVALUE(x, S_MAC_RX_WRPTR, M_MAC_TX_WRPTR)
499 499
500#define S_MAC_RX_RDPTR _SB_MAKE64(24) 500#define S_MAC_RX_RDPTR _SB_MAKE64(24)
501#define M_MAC_RX_RDPTR _SB_MAKEMASK(6,S_MAC_RX_RDPTR) 501#define M_MAC_RX_RDPTR _SB_MAKEMASK(6, S_MAC_RX_RDPTR)
502#define V_MAC_RX_RDPTR(x) _SB_MAKEVALUE(x,S_MAC_RX_RDPTR) 502#define V_MAC_RX_RDPTR(x) _SB_MAKEVALUE(x, S_MAC_RX_RDPTR)
503#define G_MAC_RX_RDPTR(x) _SB_GETVALUE(x,S_MAC_RX_RDPTR,M_MAC_TX_RDPTR) 503#define G_MAC_RX_RDPTR(x) _SB_GETVALUE(x, S_MAC_RX_RDPTR, M_MAC_TX_RDPTR)
504 504
505/* 505/*
506 * MAC Fifo End Of Packet Count Registers (Table 9-20) [Debug register] 506 * MAC Fifo End Of Packet Count Registers (Table 9-20) [Debug register]
@@ -510,14 +510,14 @@
510 */ 510 */
511 511
512#define S_MAC_TX_EOP_COUNTER _SB_MAKE64(0) 512#define S_MAC_TX_EOP_COUNTER _SB_MAKE64(0)
513#define M_MAC_TX_EOP_COUNTER _SB_MAKEMASK(6,S_MAC_TX_EOP_COUNTER) 513#define M_MAC_TX_EOP_COUNTER _SB_MAKEMASK(6, S_MAC_TX_EOP_COUNTER)
514#define V_MAC_TX_EOP_COUNTER(x) _SB_MAKEVALUE(x,S_MAC_TX_EOP_COUNTER) 514#define V_MAC_TX_EOP_COUNTER(x) _SB_MAKEVALUE(x, S_MAC_TX_EOP_COUNTER)
515#define G_MAC_TX_EOP_COUNTER(x) _SB_GETVALUE(x,S_MAC_TX_EOP_COUNTER,M_MAC_TX_EOP_COUNTER) 515#define G_MAC_TX_EOP_COUNTER(x) _SB_GETVALUE(x, S_MAC_TX_EOP_COUNTER, M_MAC_TX_EOP_COUNTER)
516 516
517#define S_MAC_RX_EOP_COUNTER _SB_MAKE64(8) 517#define S_MAC_RX_EOP_COUNTER _SB_MAKE64(8)
518#define M_MAC_RX_EOP_COUNTER _SB_MAKEMASK(6,S_MAC_RX_EOP_COUNTER) 518#define M_MAC_RX_EOP_COUNTER _SB_MAKEMASK(6, S_MAC_RX_EOP_COUNTER)
519#define V_MAC_RX_EOP_COUNTER(x) _SB_MAKEVALUE(x,S_MAC_RX_EOP_COUNTER) 519#define V_MAC_RX_EOP_COUNTER(x) _SB_MAKEVALUE(x, S_MAC_RX_EOP_COUNTER)
520#define G_MAC_RX_EOP_COUNTER(x) _SB_GETVALUE(x,S_MAC_RX_EOP_COUNTER,M_MAC_RX_EOP_COUNTER) 520#define G_MAC_RX_EOP_COUNTER(x) _SB_GETVALUE(x, S_MAC_RX_EOP_COUNTER, M_MAC_RX_EOP_COUNTER)
521 521
522/* 522/*
523 * MAC Recieve Address Filter Exact Match Registers (Table 9-21) 523 * MAC Recieve Address Filter Exact Match Registers (Table 9-21)
@@ -565,24 +565,24 @@
565#define S_TYPECFG_TYPESIZE _SB_MAKE64(16) 565#define S_TYPECFG_TYPESIZE _SB_MAKE64(16)
566 566
567#define S_TYPECFG_TYPE0 _SB_MAKE64(0) 567#define S_TYPECFG_TYPE0 _SB_MAKE64(0)
568#define M_TYPECFG_TYPE0 _SB_MAKEMASK(16,S_TYPECFG_TYPE0) 568#define M_TYPECFG_TYPE0 _SB_MAKEMASK(16, S_TYPECFG_TYPE0)
569#define V_TYPECFG_TYPE0(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE0) 569#define V_TYPECFG_TYPE0(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE0)
570#define G_TYPECFG_TYPE0(x) _SB_GETVALUE(x,S_TYPECFG_TYPE0,M_TYPECFG_TYPE0) 570#define G_TYPECFG_TYPE0(x) _SB_GETVALUE(x, S_TYPECFG_TYPE0, M_TYPECFG_TYPE0)
571 571
572#define S_TYPECFG_TYPE1 _SB_MAKE64(0) 572#define S_TYPECFG_TYPE1 _SB_MAKE64(0)
573#define M_TYPECFG_TYPE1 _SB_MAKEMASK(16,S_TYPECFG_TYPE1) 573#define M_TYPECFG_TYPE1 _SB_MAKEMASK(16, S_TYPECFG_TYPE1)
574#define V_TYPECFG_TYPE1(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE1) 574#define V_TYPECFG_TYPE1(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE1)
575#define G_TYPECFG_TYPE1(x) _SB_GETVALUE(x,S_TYPECFG_TYPE1,M_TYPECFG_TYPE1) 575#define G_TYPECFG_TYPE1(x) _SB_GETVALUE(x, S_TYPECFG_TYPE1, M_TYPECFG_TYPE1)
576 576
577#define S_TYPECFG_TYPE2 _SB_MAKE64(0) 577#define S_TYPECFG_TYPE2 _SB_MAKE64(0)
578#define M_TYPECFG_TYPE2 _SB_MAKEMASK(16,S_TYPECFG_TYPE2) 578#define M_TYPECFG_TYPE2 _SB_MAKEMASK(16, S_TYPECFG_TYPE2)
579#define V_TYPECFG_TYPE2(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE2) 579#define V_TYPECFG_TYPE2(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE2)
580#define G_TYPECFG_TYPE2(x) _SB_GETVALUE(x,S_TYPECFG_TYPE2,M_TYPECFG_TYPE2) 580#define G_TYPECFG_TYPE2(x) _SB_GETVALUE(x, S_TYPECFG_TYPE2, M_TYPECFG_TYPE2)
581 581
582#define S_TYPECFG_TYPE3 _SB_MAKE64(0) 582#define S_TYPECFG_TYPE3 _SB_MAKE64(0)
583#define M_TYPECFG_TYPE3 _SB_MAKEMASK(16,S_TYPECFG_TYPE3) 583#define M_TYPECFG_TYPE3 _SB_MAKEMASK(16, S_TYPECFG_TYPE3)
584#define V_TYPECFG_TYPE3(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE3) 584#define V_TYPECFG_TYPE3(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE3)
585#define G_TYPECFG_TYPE3(x) _SB_GETVALUE(x,S_TYPECFG_TYPE3,M_TYPECFG_TYPE3) 585#define G_TYPECFG_TYPE3(x) _SB_GETVALUE(x, S_TYPECFG_TYPE3, M_TYPECFG_TYPE3)
586 586
587/* 587/*
588 * MAC Receive Address Filter Control Registers (Table 9-24) 588 * MAC Receive Address Filter Control Registers (Table 9-24)
@@ -603,28 +603,28 @@
603#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 603#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
604 604
605#define S_MAC_IPHDR_OFFSET _SB_MAKE64(8) 605#define S_MAC_IPHDR_OFFSET _SB_MAKE64(8)
606#define M_MAC_IPHDR_OFFSET _SB_MAKEMASK(8,S_MAC_IPHDR_OFFSET) 606#define M_MAC_IPHDR_OFFSET _SB_MAKEMASK(8, S_MAC_IPHDR_OFFSET)
607#define V_MAC_IPHDR_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_IPHDR_OFFSET) 607#define V_MAC_IPHDR_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_IPHDR_OFFSET)
608#define G_MAC_IPHDR_OFFSET(x) _SB_GETVALUE(x,S_MAC_IPHDR_OFFSET,M_MAC_IPHDR_OFFSET) 608#define G_MAC_IPHDR_OFFSET(x) _SB_GETVALUE(x, S_MAC_IPHDR_OFFSET, M_MAC_IPHDR_OFFSET)
609 609
610#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 610#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
611#define S_MAC_RX_CRC_OFFSET _SB_MAKE64(16) 611#define S_MAC_RX_CRC_OFFSET _SB_MAKE64(16)
612#define M_MAC_RX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_RX_CRC_OFFSET) 612#define M_MAC_RX_CRC_OFFSET _SB_MAKEMASK(8, S_MAC_RX_CRC_OFFSET)
613#define V_MAC_RX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_CRC_OFFSET) 613#define V_MAC_RX_CRC_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_RX_CRC_OFFSET)
614#define G_MAC_RX_CRC_OFFSET(x) _SB_GETVALUE(x,S_MAC_RX_CRC_OFFSET,M_MAC_RX_CRC_OFFSET) 614#define G_MAC_RX_CRC_OFFSET(x) _SB_GETVALUE(x, S_MAC_RX_CRC_OFFSET, M_MAC_RX_CRC_OFFSET)
615 615
616#define S_MAC_RX_PKT_OFFSET _SB_MAKE64(24) 616#define S_MAC_RX_PKT_OFFSET _SB_MAKE64(24)
617#define M_MAC_RX_PKT_OFFSET _SB_MAKEMASK(8,S_MAC_RX_PKT_OFFSET) 617#define M_MAC_RX_PKT_OFFSET _SB_MAKEMASK(8, S_MAC_RX_PKT_OFFSET)
618#define V_MAC_RX_PKT_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_PKT_OFFSET) 618#define V_MAC_RX_PKT_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_RX_PKT_OFFSET)
619#define G_MAC_RX_PKT_OFFSET(x) _SB_GETVALUE(x,S_MAC_RX_PKT_OFFSET,M_MAC_RX_PKT_OFFSET) 619#define G_MAC_RX_PKT_OFFSET(x) _SB_GETVALUE(x, S_MAC_RX_PKT_OFFSET, M_MAC_RX_PKT_OFFSET)
620 620
621#define M_MAC_FWDPAUSE_EN _SB_MAKEMASK1(32) 621#define M_MAC_FWDPAUSE_EN _SB_MAKEMASK1(32)
622#define M_MAC_VLAN_DET_EN _SB_MAKEMASK1(33) 622#define M_MAC_VLAN_DET_EN _SB_MAKEMASK1(33)
623 623
624#define S_MAC_RX_CH_MSN_SEL _SB_MAKE64(34) 624#define S_MAC_RX_CH_MSN_SEL _SB_MAKE64(34)
625#define M_MAC_RX_CH_MSN_SEL _SB_MAKEMASK(8,S_MAC_RX_CH_MSN_SEL) 625#define M_MAC_RX_CH_MSN_SEL _SB_MAKEMASK(8, S_MAC_RX_CH_MSN_SEL)
626#define V_MAC_RX_CH_MSN_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_MSN_SEL) 626#define V_MAC_RX_CH_MSN_SEL(x) _SB_MAKEVALUE(x, S_MAC_RX_CH_MSN_SEL)
627#define G_MAC_RX_CH_MSN_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_MSN_SEL,M_MAC_RX_CH_MSN_SEL) 627#define G_MAC_RX_CH_MSN_SEL(x) _SB_GETVALUE(x, S_MAC_RX_CH_MSN_SEL, M_MAC_RX_CH_MSN_SEL)
628#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 628#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
629 629
630/* 630/*
diff --git a/include/asm-mips/sibyte/sb1250_mc.h b/include/asm-mips/sibyte/sb1250_mc.h
index 4fe848ffbc31..1eb1b5a88736 100644
--- a/include/asm-mips/sibyte/sb1250_mc.h
+++ b/include/asm-mips/sibyte/sb1250_mc.h
@@ -10,7 +10,7 @@
10 * 10 *
11 ********************************************************************* 11 *********************************************************************
12 * 12 *
13 * Copyright 2000,2001,2002,2003 13 * Copyright 2000, 2001, 2002, 2003
14 * Broadcom Corporation. All rights reserved. 14 * Broadcom Corporation. All rights reserved.
15 * 15 *
16 * This program is free software; you can redistribute it and/or 16 * This program is free software; you can redistribute it and/or
@@ -40,73 +40,73 @@
40 */ 40 */
41 41
42#define S_MC_RESERVED0 0 42#define S_MC_RESERVED0 0
43#define M_MC_RESERVED0 _SB_MAKEMASK(8,S_MC_RESERVED0) 43#define M_MC_RESERVED0 _SB_MAKEMASK(8, S_MC_RESERVED0)
44 44
45#define S_MC_CHANNEL_SEL 8 45#define S_MC_CHANNEL_SEL 8
46#define M_MC_CHANNEL_SEL _SB_MAKEMASK(8,S_MC_CHANNEL_SEL) 46#define M_MC_CHANNEL_SEL _SB_MAKEMASK(8, S_MC_CHANNEL_SEL)
47#define V_MC_CHANNEL_SEL(x) _SB_MAKEVALUE(x,S_MC_CHANNEL_SEL) 47#define V_MC_CHANNEL_SEL(x) _SB_MAKEVALUE(x, S_MC_CHANNEL_SEL)
48#define G_MC_CHANNEL_SEL(x) _SB_GETVALUE(x,S_MC_CHANNEL_SEL,M_MC_CHANNEL_SEL) 48#define G_MC_CHANNEL_SEL(x) _SB_GETVALUE(x, S_MC_CHANNEL_SEL, M_MC_CHANNEL_SEL)
49 49
50#define S_MC_BANK0_MAP 16 50#define S_MC_BANK0_MAP 16
51#define M_MC_BANK0_MAP _SB_MAKEMASK(4,S_MC_BANK0_MAP) 51#define M_MC_BANK0_MAP _SB_MAKEMASK(4, S_MC_BANK0_MAP)
52#define V_MC_BANK0_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK0_MAP) 52#define V_MC_BANK0_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK0_MAP)
53#define G_MC_BANK0_MAP(x) _SB_GETVALUE(x,S_MC_BANK0_MAP,M_MC_BANK0_MAP) 53#define G_MC_BANK0_MAP(x) _SB_GETVALUE(x, S_MC_BANK0_MAP, M_MC_BANK0_MAP)
54 54
55#define K_MC_BANK0_MAP_DEFAULT 0x00 55#define K_MC_BANK0_MAP_DEFAULT 0x00
56#define V_MC_BANK0_MAP_DEFAULT V_MC_BANK0_MAP(K_MC_BANK0_MAP_DEFAULT) 56#define V_MC_BANK0_MAP_DEFAULT V_MC_BANK0_MAP(K_MC_BANK0_MAP_DEFAULT)
57 57
58#define S_MC_BANK1_MAP 20 58#define S_MC_BANK1_MAP 20
59#define M_MC_BANK1_MAP _SB_MAKEMASK(4,S_MC_BANK1_MAP) 59#define M_MC_BANK1_MAP _SB_MAKEMASK(4, S_MC_BANK1_MAP)
60#define V_MC_BANK1_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK1_MAP) 60#define V_MC_BANK1_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK1_MAP)
61#define G_MC_BANK1_MAP(x) _SB_GETVALUE(x,S_MC_BANK1_MAP,M_MC_BANK1_MAP) 61#define G_MC_BANK1_MAP(x) _SB_GETVALUE(x, S_MC_BANK1_MAP, M_MC_BANK1_MAP)
62 62
63#define K_MC_BANK1_MAP_DEFAULT 0x08 63#define K_MC_BANK1_MAP_DEFAULT 0x08
64#define V_MC_BANK1_MAP_DEFAULT V_MC_BANK1_MAP(K_MC_BANK1_MAP_DEFAULT) 64#define V_MC_BANK1_MAP_DEFAULT V_MC_BANK1_MAP(K_MC_BANK1_MAP_DEFAULT)
65 65
66#define S_MC_BANK2_MAP 24 66#define S_MC_BANK2_MAP 24
67#define M_MC_BANK2_MAP _SB_MAKEMASK(4,S_MC_BANK2_MAP) 67#define M_MC_BANK2_MAP _SB_MAKEMASK(4, S_MC_BANK2_MAP)
68#define V_MC_BANK2_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK2_MAP) 68#define V_MC_BANK2_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK2_MAP)
69#define G_MC_BANK2_MAP(x) _SB_GETVALUE(x,S_MC_BANK2_MAP,M_MC_BANK2_MAP) 69#define G_MC_BANK2_MAP(x) _SB_GETVALUE(x, S_MC_BANK2_MAP, M_MC_BANK2_MAP)
70 70
71#define K_MC_BANK2_MAP_DEFAULT 0x09 71#define K_MC_BANK2_MAP_DEFAULT 0x09
72#define V_MC_BANK2_MAP_DEFAULT V_MC_BANK2_MAP(K_MC_BANK2_MAP_DEFAULT) 72#define V_MC_BANK2_MAP_DEFAULT V_MC_BANK2_MAP(K_MC_BANK2_MAP_DEFAULT)
73 73
74#define S_MC_BANK3_MAP 28 74#define S_MC_BANK3_MAP 28
75#define M_MC_BANK3_MAP _SB_MAKEMASK(4,S_MC_BANK3_MAP) 75#define M_MC_BANK3_MAP _SB_MAKEMASK(4, S_MC_BANK3_MAP)
76#define V_MC_BANK3_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK3_MAP) 76#define V_MC_BANK3_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK3_MAP)
77#define G_MC_BANK3_MAP(x) _SB_GETVALUE(x,S_MC_BANK3_MAP,M_MC_BANK3_MAP) 77#define G_MC_BANK3_MAP(x) _SB_GETVALUE(x, S_MC_BANK3_MAP, M_MC_BANK3_MAP)
78 78
79#define K_MC_BANK3_MAP_DEFAULT 0x0C 79#define K_MC_BANK3_MAP_DEFAULT 0x0C
80#define V_MC_BANK3_MAP_DEFAULT V_MC_BANK3_MAP(K_MC_BANK3_MAP_DEFAULT) 80#define V_MC_BANK3_MAP_DEFAULT V_MC_BANK3_MAP(K_MC_BANK3_MAP_DEFAULT)
81 81
82#define M_MC_RESERVED1 _SB_MAKEMASK(8,32) 82#define M_MC_RESERVED1 _SB_MAKEMASK(8, 32)
83 83
84#define S_MC_QUEUE_SIZE 40 84#define S_MC_QUEUE_SIZE 40
85#define M_MC_QUEUE_SIZE _SB_MAKEMASK(4,S_MC_QUEUE_SIZE) 85#define M_MC_QUEUE_SIZE _SB_MAKEMASK(4, S_MC_QUEUE_SIZE)
86#define V_MC_QUEUE_SIZE(x) _SB_MAKEVALUE(x,S_MC_QUEUE_SIZE) 86#define V_MC_QUEUE_SIZE(x) _SB_MAKEVALUE(x, S_MC_QUEUE_SIZE)
87#define G_MC_QUEUE_SIZE(x) _SB_GETVALUE(x,S_MC_QUEUE_SIZE,M_MC_QUEUE_SIZE) 87#define G_MC_QUEUE_SIZE(x) _SB_GETVALUE(x, S_MC_QUEUE_SIZE, M_MC_QUEUE_SIZE)
88#define V_MC_QUEUE_SIZE_DEFAULT V_MC_QUEUE_SIZE(0x0A) 88#define V_MC_QUEUE_SIZE_DEFAULT V_MC_QUEUE_SIZE(0x0A)
89 89
90#define S_MC_AGE_LIMIT 44 90#define S_MC_AGE_LIMIT 44
91#define M_MC_AGE_LIMIT _SB_MAKEMASK(4,S_MC_AGE_LIMIT) 91#define M_MC_AGE_LIMIT _SB_MAKEMASK(4, S_MC_AGE_LIMIT)
92#define V_MC_AGE_LIMIT(x) _SB_MAKEVALUE(x,S_MC_AGE_LIMIT) 92#define V_MC_AGE_LIMIT(x) _SB_MAKEVALUE(x, S_MC_AGE_LIMIT)
93#define G_MC_AGE_LIMIT(x) _SB_GETVALUE(x,S_MC_AGE_LIMIT,M_MC_AGE_LIMIT) 93#define G_MC_AGE_LIMIT(x) _SB_GETVALUE(x, S_MC_AGE_LIMIT, M_MC_AGE_LIMIT)
94#define V_MC_AGE_LIMIT_DEFAULT V_MC_AGE_LIMIT(8) 94#define V_MC_AGE_LIMIT_DEFAULT V_MC_AGE_LIMIT(8)
95 95
96#define S_MC_WR_LIMIT 48 96#define S_MC_WR_LIMIT 48
97#define M_MC_WR_LIMIT _SB_MAKEMASK(4,S_MC_WR_LIMIT) 97#define M_MC_WR_LIMIT _SB_MAKEMASK(4, S_MC_WR_LIMIT)
98#define V_MC_WR_LIMIT(x) _SB_MAKEVALUE(x,S_MC_WR_LIMIT) 98#define V_MC_WR_LIMIT(x) _SB_MAKEVALUE(x, S_MC_WR_LIMIT)
99#define G_MC_WR_LIMIT(x) _SB_GETVALUE(x,S_MC_WR_LIMIT,M_MC_WR_LIMIT) 99#define G_MC_WR_LIMIT(x) _SB_GETVALUE(x, S_MC_WR_LIMIT, M_MC_WR_LIMIT)
100#define V_MC_WR_LIMIT_DEFAULT V_MC_WR_LIMIT(5) 100#define V_MC_WR_LIMIT_DEFAULT V_MC_WR_LIMIT(5)
101 101
102#define M_MC_IOB1HIGHPRIORITY _SB_MAKEMASK1(52) 102#define M_MC_IOB1HIGHPRIORITY _SB_MAKEMASK1(52)
103 103
104#define M_MC_RESERVED2 _SB_MAKEMASK(3,53) 104#define M_MC_RESERVED2 _SB_MAKEMASK(3, 53)
105 105
106#define S_MC_CS_MODE 56 106#define S_MC_CS_MODE 56
107#define M_MC_CS_MODE _SB_MAKEMASK(4,S_MC_CS_MODE) 107#define M_MC_CS_MODE _SB_MAKEMASK(4, S_MC_CS_MODE)
108#define V_MC_CS_MODE(x) _SB_MAKEVALUE(x,S_MC_CS_MODE) 108#define V_MC_CS_MODE(x) _SB_MAKEVALUE(x, S_MC_CS_MODE)
109#define G_MC_CS_MODE(x) _SB_GETVALUE(x,S_MC_CS_MODE,M_MC_CS_MODE) 109#define G_MC_CS_MODE(x) _SB_GETVALUE(x, S_MC_CS_MODE, M_MC_CS_MODE)
110 110
111#define K_MC_CS_MODE_MSB_CS 0 111#define K_MC_CS_MODE_MSB_CS 0
112#define K_MC_CS_MODE_INTLV_CS 15 112#define K_MC_CS_MODE_INTLV_CS 15
@@ -138,9 +138,9 @@
138 */ 138 */
139 139
140#define S_MC_CLK_RATIO 0 140#define S_MC_CLK_RATIO 0
141#define M_MC_CLK_RATIO _SB_MAKEMASK(4,S_MC_CLK_RATIO) 141#define M_MC_CLK_RATIO _SB_MAKEMASK(4, S_MC_CLK_RATIO)
142#define V_MC_CLK_RATIO(x) _SB_MAKEVALUE(x,S_MC_CLK_RATIO) 142#define V_MC_CLK_RATIO(x) _SB_MAKEVALUE(x, S_MC_CLK_RATIO)
143#define G_MC_CLK_RATIO(x) _SB_GETVALUE(x,S_MC_CLK_RATIO,M_MC_CLK_RATIO) 143#define G_MC_CLK_RATIO(x) _SB_GETVALUE(x, S_MC_CLK_RATIO, M_MC_CLK_RATIO)
144 144
145#define K_MC_CLK_RATIO_2X 4 145#define K_MC_CLK_RATIO_2X 4
146#define K_MC_CLK_RATIO_25X 5 146#define K_MC_CLK_RATIO_25X 5
@@ -158,9 +158,9 @@
158#define V_MC_CLK_RATIO_DEFAULT V_MC_CLK_RATIO_25X 158#define V_MC_CLK_RATIO_DEFAULT V_MC_CLK_RATIO_25X
159 159
160#define S_MC_REF_RATE 8 160#define S_MC_REF_RATE 8
161#define M_MC_REF_RATE _SB_MAKEMASK(8,S_MC_REF_RATE) 161#define M_MC_REF_RATE _SB_MAKEMASK(8, S_MC_REF_RATE)
162#define V_MC_REF_RATE(x) _SB_MAKEVALUE(x,S_MC_REF_RATE) 162#define V_MC_REF_RATE(x) _SB_MAKEVALUE(x, S_MC_REF_RATE)
163#define G_MC_REF_RATE(x) _SB_GETVALUE(x,S_MC_REF_RATE,M_MC_REF_RATE) 163#define G_MC_REF_RATE(x) _SB_GETVALUE(x, S_MC_REF_RATE, M_MC_REF_RATE)
164 164
165#define K_MC_REF_RATE_100MHz 0x62 165#define K_MC_REF_RATE_100MHz 0x62
166#define K_MC_REF_RATE_133MHz 0x81 166#define K_MC_REF_RATE_133MHz 0x81
@@ -172,21 +172,21 @@
172#define V_MC_REF_RATE_DEFAULT V_MC_REF_RATE_100MHz 172#define V_MC_REF_RATE_DEFAULT V_MC_REF_RATE_100MHz
173 173
174#define S_MC_CLOCK_DRIVE 16 174#define S_MC_CLOCK_DRIVE 16
175#define M_MC_CLOCK_DRIVE _SB_MAKEMASK(4,S_MC_CLOCK_DRIVE) 175#define M_MC_CLOCK_DRIVE _SB_MAKEMASK(4, S_MC_CLOCK_DRIVE)
176#define V_MC_CLOCK_DRIVE(x) _SB_MAKEVALUE(x,S_MC_CLOCK_DRIVE) 176#define V_MC_CLOCK_DRIVE(x) _SB_MAKEVALUE(x, S_MC_CLOCK_DRIVE)
177#define G_MC_CLOCK_DRIVE(x) _SB_GETVALUE(x,S_MC_CLOCK_DRIVE,M_MC_CLOCK_DRIVE) 177#define G_MC_CLOCK_DRIVE(x) _SB_GETVALUE(x, S_MC_CLOCK_DRIVE, M_MC_CLOCK_DRIVE)
178#define V_MC_CLOCK_DRIVE_DEFAULT V_MC_CLOCK_DRIVE(0xF) 178#define V_MC_CLOCK_DRIVE_DEFAULT V_MC_CLOCK_DRIVE(0xF)
179 179
180#define S_MC_DATA_DRIVE 20 180#define S_MC_DATA_DRIVE 20
181#define M_MC_DATA_DRIVE _SB_MAKEMASK(4,S_MC_DATA_DRIVE) 181#define M_MC_DATA_DRIVE _SB_MAKEMASK(4, S_MC_DATA_DRIVE)
182#define V_MC_DATA_DRIVE(x) _SB_MAKEVALUE(x,S_MC_DATA_DRIVE) 182#define V_MC_DATA_DRIVE(x) _SB_MAKEVALUE(x, S_MC_DATA_DRIVE)
183#define G_MC_DATA_DRIVE(x) _SB_GETVALUE(x,S_MC_DATA_DRIVE,M_MC_DATA_DRIVE) 183#define G_MC_DATA_DRIVE(x) _SB_GETVALUE(x, S_MC_DATA_DRIVE, M_MC_DATA_DRIVE)
184#define V_MC_DATA_DRIVE_DEFAULT V_MC_DATA_DRIVE(0x0) 184#define V_MC_DATA_DRIVE_DEFAULT V_MC_DATA_DRIVE(0x0)
185 185
186#define S_MC_ADDR_DRIVE 24 186#define S_MC_ADDR_DRIVE 24
187#define M_MC_ADDR_DRIVE _SB_MAKEMASK(4,S_MC_ADDR_DRIVE) 187#define M_MC_ADDR_DRIVE _SB_MAKEMASK(4, S_MC_ADDR_DRIVE)
188#define V_MC_ADDR_DRIVE(x) _SB_MAKEVALUE(x,S_MC_ADDR_DRIVE) 188#define V_MC_ADDR_DRIVE(x) _SB_MAKEVALUE(x, S_MC_ADDR_DRIVE)
189#define G_MC_ADDR_DRIVE(x) _SB_GETVALUE(x,S_MC_ADDR_DRIVE,M_MC_ADDR_DRIVE) 189#define G_MC_ADDR_DRIVE(x) _SB_GETVALUE(x, S_MC_ADDR_DRIVE, M_MC_ADDR_DRIVE)
190#define V_MC_ADDR_DRIVE_DEFAULT V_MC_ADDR_DRIVE(0x0) 190#define V_MC_ADDR_DRIVE_DEFAULT V_MC_ADDR_DRIVE(0x0)
191 191
192#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 192#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
@@ -196,27 +196,27 @@
196#define M_MC_DLL_BYPASS _SB_MAKEMASK1(31) 196#define M_MC_DLL_BYPASS _SB_MAKEMASK1(31)
197 197
198#define S_MC_DQI_SKEW 32 198#define S_MC_DQI_SKEW 32
199#define M_MC_DQI_SKEW _SB_MAKEMASK(8,S_MC_DQI_SKEW) 199#define M_MC_DQI_SKEW _SB_MAKEMASK(8, S_MC_DQI_SKEW)
200#define V_MC_DQI_SKEW(x) _SB_MAKEVALUE(x,S_MC_DQI_SKEW) 200#define V_MC_DQI_SKEW(x) _SB_MAKEVALUE(x, S_MC_DQI_SKEW)
201#define G_MC_DQI_SKEW(x) _SB_GETVALUE(x,S_MC_DQI_SKEW,M_MC_DQI_SKEW) 201#define G_MC_DQI_SKEW(x) _SB_GETVALUE(x, S_MC_DQI_SKEW, M_MC_DQI_SKEW)
202#define V_MC_DQI_SKEW_DEFAULT V_MC_DQI_SKEW(0) 202#define V_MC_DQI_SKEW_DEFAULT V_MC_DQI_SKEW(0)
203 203
204#define S_MC_DQO_SKEW 40 204#define S_MC_DQO_SKEW 40
205#define M_MC_DQO_SKEW _SB_MAKEMASK(8,S_MC_DQO_SKEW) 205#define M_MC_DQO_SKEW _SB_MAKEMASK(8, S_MC_DQO_SKEW)
206#define V_MC_DQO_SKEW(x) _SB_MAKEVALUE(x,S_MC_DQO_SKEW) 206#define V_MC_DQO_SKEW(x) _SB_MAKEVALUE(x, S_MC_DQO_SKEW)
207#define G_MC_DQO_SKEW(x) _SB_GETVALUE(x,S_MC_DQO_SKEW,M_MC_DQO_SKEW) 207#define G_MC_DQO_SKEW(x) _SB_GETVALUE(x, S_MC_DQO_SKEW, M_MC_DQO_SKEW)
208#define V_MC_DQO_SKEW_DEFAULT V_MC_DQO_SKEW(0) 208#define V_MC_DQO_SKEW_DEFAULT V_MC_DQO_SKEW(0)
209 209
210#define S_MC_ADDR_SKEW 48 210#define S_MC_ADDR_SKEW 48
211#define M_MC_ADDR_SKEW _SB_MAKEMASK(8,S_MC_ADDR_SKEW) 211#define M_MC_ADDR_SKEW _SB_MAKEMASK(8, S_MC_ADDR_SKEW)
212#define V_MC_ADDR_SKEW(x) _SB_MAKEVALUE(x,S_MC_ADDR_SKEW) 212#define V_MC_ADDR_SKEW(x) _SB_MAKEVALUE(x, S_MC_ADDR_SKEW)
213#define G_MC_ADDR_SKEW(x) _SB_GETVALUE(x,S_MC_ADDR_SKEW,M_MC_ADDR_SKEW) 213#define G_MC_ADDR_SKEW(x) _SB_GETVALUE(x, S_MC_ADDR_SKEW, M_MC_ADDR_SKEW)
214#define V_MC_ADDR_SKEW_DEFAULT V_MC_ADDR_SKEW(0x0F) 214#define V_MC_ADDR_SKEW_DEFAULT V_MC_ADDR_SKEW(0x0F)
215 215
216#define S_MC_DLL_DEFAULT 56 216#define S_MC_DLL_DEFAULT 56
217#define M_MC_DLL_DEFAULT _SB_MAKEMASK(8,S_MC_DLL_DEFAULT) 217#define M_MC_DLL_DEFAULT _SB_MAKEMASK(8, S_MC_DLL_DEFAULT)
218#define V_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x,S_MC_DLL_DEFAULT) 218#define V_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x, S_MC_DLL_DEFAULT)
219#define G_MC_DLL_DEFAULT(x) _SB_GETVALUE(x,S_MC_DLL_DEFAULT,M_MC_DLL_DEFAULT) 219#define G_MC_DLL_DEFAULT(x) _SB_GETVALUE(x, S_MC_DLL_DEFAULT, M_MC_DLL_DEFAULT)
220#define V_MC_DLL_DEFAULT_DEFAULT V_MC_DLL_DEFAULT(0x10) 220#define V_MC_DLL_DEFAULT_DEFAULT V_MC_DLL_DEFAULT(0x10)
221 221
222#define V_MC_CLKCONFIG_DEFAULT V_MC_DLL_DEFAULT_DEFAULT | \ 222#define V_MC_CLKCONFIG_DEFAULT V_MC_DLL_DEFAULT_DEFAULT | \
@@ -235,9 +235,9 @@
235 */ 235 */
236 236
237#define S_MC_COMMAND 0 237#define S_MC_COMMAND 0
238#define M_MC_COMMAND _SB_MAKEMASK(4,S_MC_COMMAND) 238#define M_MC_COMMAND _SB_MAKEMASK(4, S_MC_COMMAND)
239#define V_MC_COMMAND(x) _SB_MAKEVALUE(x,S_MC_COMMAND) 239#define V_MC_COMMAND(x) _SB_MAKEVALUE(x, S_MC_COMMAND)
240#define G_MC_COMMAND(x) _SB_GETVALUE(x,S_MC_COMMAND,M_MC_COMMAND) 240#define G_MC_COMMAND(x) _SB_GETVALUE(x, S_MC_COMMAND, M_MC_COMMAND)
241 241
242#define K_MC_COMMAND_EMRS 0 242#define K_MC_COMMAND_EMRS 0
243#define K_MC_COMMAND_MRS 1 243#define K_MC_COMMAND_MRS 1
@@ -267,21 +267,21 @@
267 */ 267 */
268 268
269#define S_MC_EMODE 0 269#define S_MC_EMODE 0
270#define M_MC_EMODE _SB_MAKEMASK(15,S_MC_EMODE) 270#define M_MC_EMODE _SB_MAKEMASK(15, S_MC_EMODE)
271#define V_MC_EMODE(x) _SB_MAKEVALUE(x,S_MC_EMODE) 271#define V_MC_EMODE(x) _SB_MAKEVALUE(x, S_MC_EMODE)
272#define G_MC_EMODE(x) _SB_GETVALUE(x,S_MC_EMODE,M_MC_EMODE) 272#define G_MC_EMODE(x) _SB_GETVALUE(x, S_MC_EMODE, M_MC_EMODE)
273#define V_MC_EMODE_DEFAULT V_MC_EMODE(0) 273#define V_MC_EMODE_DEFAULT V_MC_EMODE(0)
274 274
275#define S_MC_MODE 16 275#define S_MC_MODE 16
276#define M_MC_MODE _SB_MAKEMASK(15,S_MC_MODE) 276#define M_MC_MODE _SB_MAKEMASK(15, S_MC_MODE)
277#define V_MC_MODE(x) _SB_MAKEVALUE(x,S_MC_MODE) 277#define V_MC_MODE(x) _SB_MAKEVALUE(x, S_MC_MODE)
278#define G_MC_MODE(x) _SB_GETVALUE(x,S_MC_MODE,M_MC_MODE) 278#define G_MC_MODE(x) _SB_GETVALUE(x, S_MC_MODE, M_MC_MODE)
279#define V_MC_MODE_DEFAULT V_MC_MODE(0x22) 279#define V_MC_MODE_DEFAULT V_MC_MODE(0x22)
280 280
281#define S_MC_DRAM_TYPE 32 281#define S_MC_DRAM_TYPE 32
282#define M_MC_DRAM_TYPE _SB_MAKEMASK(3,S_MC_DRAM_TYPE) 282#define M_MC_DRAM_TYPE _SB_MAKEMASK(3, S_MC_DRAM_TYPE)
283#define V_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x,S_MC_DRAM_TYPE) 283#define V_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x, S_MC_DRAM_TYPE)
284#define G_MC_DRAM_TYPE(x) _SB_GETVALUE(x,S_MC_DRAM_TYPE,M_MC_DRAM_TYPE) 284#define G_MC_DRAM_TYPE(x) _SB_GETVALUE(x, S_MC_DRAM_TYPE, M_MC_DRAM_TYPE)
285 285
286#define K_MC_DRAM_TYPE_JEDEC 0 286#define K_MC_DRAM_TYPE_JEDEC 0
287#define K_MC_DRAM_TYPE_FCRAM 1 287#define K_MC_DRAM_TYPE_FCRAM 1
@@ -309,16 +309,16 @@
309#define M_MC_r2rIDLE_TWOCYCLES _SB_MAKEMASK1(62) 309#define M_MC_r2rIDLE_TWOCYCLES _SB_MAKEMASK1(62)
310 310
311#define S_MC_tFIFO 56 311#define S_MC_tFIFO 56
312#define M_MC_tFIFO _SB_MAKEMASK(4,S_MC_tFIFO) 312#define M_MC_tFIFO _SB_MAKEMASK(4, S_MC_tFIFO)
313#define V_MC_tFIFO(x) _SB_MAKEVALUE(x,S_MC_tFIFO) 313#define V_MC_tFIFO(x) _SB_MAKEVALUE(x, S_MC_tFIFO)
314#define G_MC_tFIFO(x) _SB_GETVALUE(x,S_MC_tFIFO,M_MC_tFIFO) 314#define G_MC_tFIFO(x) _SB_GETVALUE(x, S_MC_tFIFO, M_MC_tFIFO)
315#define K_MC_tFIFO_DEFAULT 1 315#define K_MC_tFIFO_DEFAULT 1
316#define V_MC_tFIFO_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT) 316#define V_MC_tFIFO_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT)
317 317
318#define S_MC_tRFC 52 318#define S_MC_tRFC 52
319#define M_MC_tRFC _SB_MAKEMASK(4,S_MC_tRFC) 319#define M_MC_tRFC _SB_MAKEMASK(4, S_MC_tRFC)
320#define V_MC_tRFC(x) _SB_MAKEVALUE(x,S_MC_tRFC) 320#define V_MC_tRFC(x) _SB_MAKEVALUE(x, S_MC_tRFC)
321#define G_MC_tRFC(x) _SB_GETVALUE(x,S_MC_tRFC,M_MC_tRFC) 321#define G_MC_tRFC(x) _SB_GETVALUE(x, S_MC_tRFC, M_MC_tRFC)
322#define K_MC_tRFC_DEFAULT 12 322#define K_MC_tRFC_DEFAULT 12
323#define V_MC_tRFC_DEFAULT V_MC_tRFC(K_MC_tRFC_DEFAULT) 323#define V_MC_tRFC_DEFAULT V_MC_tRFC(K_MC_tRFC_DEFAULT)
324 324
@@ -327,44 +327,44 @@
327#endif 327#endif
328 328
329#define S_MC_tCwCr 40 329#define S_MC_tCwCr 40
330#define M_MC_tCwCr _SB_MAKEMASK(4,S_MC_tCwCr) 330#define M_MC_tCwCr _SB_MAKEMASK(4, S_MC_tCwCr)
331#define V_MC_tCwCr(x) _SB_MAKEVALUE(x,S_MC_tCwCr) 331#define V_MC_tCwCr(x) _SB_MAKEVALUE(x, S_MC_tCwCr)
332#define G_MC_tCwCr(x) _SB_GETVALUE(x,S_MC_tCwCr,M_MC_tCwCr) 332#define G_MC_tCwCr(x) _SB_GETVALUE(x, S_MC_tCwCr, M_MC_tCwCr)
333#define K_MC_tCwCr_DEFAULT 4 333#define K_MC_tCwCr_DEFAULT 4
334#define V_MC_tCwCr_DEFAULT V_MC_tCwCr(K_MC_tCwCr_DEFAULT) 334#define V_MC_tCwCr_DEFAULT V_MC_tCwCr(K_MC_tCwCr_DEFAULT)
335 335
336#define S_MC_tRCr 28 336#define S_MC_tRCr 28
337#define M_MC_tRCr _SB_MAKEMASK(4,S_MC_tRCr) 337#define M_MC_tRCr _SB_MAKEMASK(4, S_MC_tRCr)
338#define V_MC_tRCr(x) _SB_MAKEVALUE(x,S_MC_tRCr) 338#define V_MC_tRCr(x) _SB_MAKEVALUE(x, S_MC_tRCr)
339#define G_MC_tRCr(x) _SB_GETVALUE(x,S_MC_tRCr,M_MC_tRCr) 339#define G_MC_tRCr(x) _SB_GETVALUE(x, S_MC_tRCr, M_MC_tRCr)
340#define K_MC_tRCr_DEFAULT 9 340#define K_MC_tRCr_DEFAULT 9
341#define V_MC_tRCr_DEFAULT V_MC_tRCr(K_MC_tRCr_DEFAULT) 341#define V_MC_tRCr_DEFAULT V_MC_tRCr(K_MC_tRCr_DEFAULT)
342 342
343#define S_MC_tRCw 24 343#define S_MC_tRCw 24
344#define M_MC_tRCw _SB_MAKEMASK(4,S_MC_tRCw) 344#define M_MC_tRCw _SB_MAKEMASK(4, S_MC_tRCw)
345#define V_MC_tRCw(x) _SB_MAKEVALUE(x,S_MC_tRCw) 345#define V_MC_tRCw(x) _SB_MAKEVALUE(x, S_MC_tRCw)
346#define G_MC_tRCw(x) _SB_GETVALUE(x,S_MC_tRCw,M_MC_tRCw) 346#define G_MC_tRCw(x) _SB_GETVALUE(x, S_MC_tRCw, M_MC_tRCw)
347#define K_MC_tRCw_DEFAULT 10 347#define K_MC_tRCw_DEFAULT 10
348#define V_MC_tRCw_DEFAULT V_MC_tRCw(K_MC_tRCw_DEFAULT) 348#define V_MC_tRCw_DEFAULT V_MC_tRCw(K_MC_tRCw_DEFAULT)
349 349
350#define S_MC_tRRD 20 350#define S_MC_tRRD 20
351#define M_MC_tRRD _SB_MAKEMASK(4,S_MC_tRRD) 351#define M_MC_tRRD _SB_MAKEMASK(4, S_MC_tRRD)
352#define V_MC_tRRD(x) _SB_MAKEVALUE(x,S_MC_tRRD) 352#define V_MC_tRRD(x) _SB_MAKEVALUE(x, S_MC_tRRD)
353#define G_MC_tRRD(x) _SB_GETVALUE(x,S_MC_tRRD,M_MC_tRRD) 353#define G_MC_tRRD(x) _SB_GETVALUE(x, S_MC_tRRD, M_MC_tRRD)
354#define K_MC_tRRD_DEFAULT 2 354#define K_MC_tRRD_DEFAULT 2
355#define V_MC_tRRD_DEFAULT V_MC_tRRD(K_MC_tRRD_DEFAULT) 355#define V_MC_tRRD_DEFAULT V_MC_tRRD(K_MC_tRRD_DEFAULT)
356 356
357#define S_MC_tRP 16 357#define S_MC_tRP 16
358#define M_MC_tRP _SB_MAKEMASK(4,S_MC_tRP) 358#define M_MC_tRP _SB_MAKEMASK(4, S_MC_tRP)
359#define V_MC_tRP(x) _SB_MAKEVALUE(x,S_MC_tRP) 359#define V_MC_tRP(x) _SB_MAKEVALUE(x, S_MC_tRP)
360#define G_MC_tRP(x) _SB_GETVALUE(x,S_MC_tRP,M_MC_tRP) 360#define G_MC_tRP(x) _SB_GETVALUE(x, S_MC_tRP, M_MC_tRP)
361#define K_MC_tRP_DEFAULT 4 361#define K_MC_tRP_DEFAULT 4
362#define V_MC_tRP_DEFAULT V_MC_tRP(K_MC_tRP_DEFAULT) 362#define V_MC_tRP_DEFAULT V_MC_tRP(K_MC_tRP_DEFAULT)
363 363
364#define S_MC_tCwD 8 364#define S_MC_tCwD 8
365#define M_MC_tCwD _SB_MAKEMASK(4,S_MC_tCwD) 365#define M_MC_tCwD _SB_MAKEMASK(4, S_MC_tCwD)
366#define V_MC_tCwD(x) _SB_MAKEVALUE(x,S_MC_tCwD) 366#define V_MC_tCwD(x) _SB_MAKEVALUE(x, S_MC_tCwD)
367#define G_MC_tCwD(x) _SB_GETVALUE(x,S_MC_tCwD,M_MC_tCwD) 367#define G_MC_tCwD(x) _SB_GETVALUE(x, S_MC_tCwD, M_MC_tCwD)
368#define K_MC_tCwD_DEFAULT 1 368#define K_MC_tCwD_DEFAULT 1
369#define V_MC_tCwD_DEFAULT V_MC_tCwD(K_MC_tCwD_DEFAULT) 369#define V_MC_tCwD_DEFAULT V_MC_tCwD(K_MC_tCwD_DEFAULT)
370 370
@@ -372,16 +372,16 @@
372#define M_MC_tCrDh M_tCrDh 372#define M_MC_tCrDh M_tCrDh
373 373
374#define S_MC_tCrD 4 374#define S_MC_tCrD 4
375#define M_MC_tCrD _SB_MAKEMASK(3,S_MC_tCrD) 375#define M_MC_tCrD _SB_MAKEMASK(3, S_MC_tCrD)
376#define V_MC_tCrD(x) _SB_MAKEVALUE(x,S_MC_tCrD) 376#define V_MC_tCrD(x) _SB_MAKEVALUE(x, S_MC_tCrD)
377#define G_MC_tCrD(x) _SB_GETVALUE(x,S_MC_tCrD,M_MC_tCrD) 377#define G_MC_tCrD(x) _SB_GETVALUE(x, S_MC_tCrD, M_MC_tCrD)
378#define K_MC_tCrD_DEFAULT 2 378#define K_MC_tCrD_DEFAULT 2
379#define V_MC_tCrD_DEFAULT V_MC_tCrD(K_MC_tCrD_DEFAULT) 379#define V_MC_tCrD_DEFAULT V_MC_tCrD(K_MC_tCrD_DEFAULT)
380 380
381#define S_MC_tRCD 0 381#define S_MC_tRCD 0
382#define M_MC_tRCD _SB_MAKEMASK(4,S_MC_tRCD) 382#define M_MC_tRCD _SB_MAKEMASK(4, S_MC_tRCD)
383#define V_MC_tRCD(x) _SB_MAKEVALUE(x,S_MC_tRCD) 383#define V_MC_tRCD(x) _SB_MAKEVALUE(x, S_MC_tRCD)
384#define G_MC_tRCD(x) _SB_GETVALUE(x,S_MC_tRCD,M_MC_tRCD) 384#define G_MC_tRCD(x) _SB_GETVALUE(x, S_MC_tRCD, M_MC_tRCD)
385#define K_MC_tRCD_DEFAULT 3 385#define K_MC_tRCD_DEFAULT 3
386#define V_MC_tRCD_DEFAULT V_MC_tRCD(K_MC_tRCD_DEFAULT) 386#define V_MC_tRCD_DEFAULT V_MC_tRCD(K_MC_tRCD_DEFAULT)
387 387
@@ -409,76 +409,76 @@
409 */ 409 */
410 410
411#define S_MC_CS0_START 0 411#define S_MC_CS0_START 0
412#define M_MC_CS0_START _SB_MAKEMASK(16,S_MC_CS0_START) 412#define M_MC_CS0_START _SB_MAKEMASK(16, S_MC_CS0_START)
413#define V_MC_CS0_START(x) _SB_MAKEVALUE(x,S_MC_CS0_START) 413#define V_MC_CS0_START(x) _SB_MAKEVALUE(x, S_MC_CS0_START)
414#define G_MC_CS0_START(x) _SB_GETVALUE(x,S_MC_CS0_START,M_MC_CS0_START) 414#define G_MC_CS0_START(x) _SB_GETVALUE(x, S_MC_CS0_START, M_MC_CS0_START)
415 415
416#define S_MC_CS1_START 16 416#define S_MC_CS1_START 16
417#define M_MC_CS1_START _SB_MAKEMASK(16,S_MC_CS1_START) 417#define M_MC_CS1_START _SB_MAKEMASK(16, S_MC_CS1_START)
418#define V_MC_CS1_START(x) _SB_MAKEVALUE(x,S_MC_CS1_START) 418#define V_MC_CS1_START(x) _SB_MAKEVALUE(x, S_MC_CS1_START)
419#define G_MC_CS1_START(x) _SB_GETVALUE(x,S_MC_CS1_START,M_MC_CS1_START) 419#define G_MC_CS1_START(x) _SB_GETVALUE(x, S_MC_CS1_START, M_MC_CS1_START)
420 420
421#define S_MC_CS2_START 32 421#define S_MC_CS2_START 32
422#define M_MC_CS2_START _SB_MAKEMASK(16,S_MC_CS2_START) 422#define M_MC_CS2_START _SB_MAKEMASK(16, S_MC_CS2_START)
423#define V_MC_CS2_START(x) _SB_MAKEVALUE(x,S_MC_CS2_START) 423#define V_MC_CS2_START(x) _SB_MAKEVALUE(x, S_MC_CS2_START)
424#define G_MC_CS2_START(x) _SB_GETVALUE(x,S_MC_CS2_START,M_MC_CS2_START) 424#define G_MC_CS2_START(x) _SB_GETVALUE(x, S_MC_CS2_START, M_MC_CS2_START)
425 425
426#define S_MC_CS3_START 48 426#define S_MC_CS3_START 48
427#define M_MC_CS3_START _SB_MAKEMASK(16,S_MC_CS3_START) 427#define M_MC_CS3_START _SB_MAKEMASK(16, S_MC_CS3_START)
428#define V_MC_CS3_START(x) _SB_MAKEVALUE(x,S_MC_CS3_START) 428#define V_MC_CS3_START(x) _SB_MAKEVALUE(x, S_MC_CS3_START)
429#define G_MC_CS3_START(x) _SB_GETVALUE(x,S_MC_CS3_START,M_MC_CS3_START) 429#define G_MC_CS3_START(x) _SB_GETVALUE(x, S_MC_CS3_START, M_MC_CS3_START)
430 430
431/* 431/*
432 * Chip Select End Address Register (Table 6-18) 432 * Chip Select End Address Register (Table 6-18)
433 */ 433 */
434 434
435#define S_MC_CS0_END 0 435#define S_MC_CS0_END 0
436#define M_MC_CS0_END _SB_MAKEMASK(16,S_MC_CS0_END) 436#define M_MC_CS0_END _SB_MAKEMASK(16, S_MC_CS0_END)
437#define V_MC_CS0_END(x) _SB_MAKEVALUE(x,S_MC_CS0_END) 437#define V_MC_CS0_END(x) _SB_MAKEVALUE(x, S_MC_CS0_END)
438#define G_MC_CS0_END(x) _SB_GETVALUE(x,S_MC_CS0_END,M_MC_CS0_END) 438#define G_MC_CS0_END(x) _SB_GETVALUE(x, S_MC_CS0_END, M_MC_CS0_END)
439 439
440#define S_MC_CS1_END 16 440#define S_MC_CS1_END 16
441#define M_MC_CS1_END _SB_MAKEMASK(16,S_MC_CS1_END) 441#define M_MC_CS1_END _SB_MAKEMASK(16, S_MC_CS1_END)
442#define V_MC_CS1_END(x) _SB_MAKEVALUE(x,S_MC_CS1_END) 442#define V_MC_CS1_END(x) _SB_MAKEVALUE(x, S_MC_CS1_END)
443#define G_MC_CS1_END(x) _SB_GETVALUE(x,S_MC_CS1_END,M_MC_CS1_END) 443#define G_MC_CS1_END(x) _SB_GETVALUE(x, S_MC_CS1_END, M_MC_CS1_END)
444 444
445#define S_MC_CS2_END 32 445#define S_MC_CS2_END 32
446#define M_MC_CS2_END _SB_MAKEMASK(16,S_MC_CS2_END) 446#define M_MC_CS2_END _SB_MAKEMASK(16, S_MC_CS2_END)
447#define V_MC_CS2_END(x) _SB_MAKEVALUE(x,S_MC_CS2_END) 447#define V_MC_CS2_END(x) _SB_MAKEVALUE(x, S_MC_CS2_END)
448#define G_MC_CS2_END(x) _SB_GETVALUE(x,S_MC_CS2_END,M_MC_CS2_END) 448#define G_MC_CS2_END(x) _SB_GETVALUE(x, S_MC_CS2_END, M_MC_CS2_END)
449 449
450#define S_MC_CS3_END 48 450#define S_MC_CS3_END 48
451#define M_MC_CS3_END _SB_MAKEMASK(16,S_MC_CS3_END) 451#define M_MC_CS3_END _SB_MAKEMASK(16, S_MC_CS3_END)
452#define V_MC_CS3_END(x) _SB_MAKEVALUE(x,S_MC_CS3_END) 452#define V_MC_CS3_END(x) _SB_MAKEVALUE(x, S_MC_CS3_END)
453#define G_MC_CS3_END(x) _SB_GETVALUE(x,S_MC_CS3_END,M_MC_CS3_END) 453#define G_MC_CS3_END(x) _SB_GETVALUE(x, S_MC_CS3_END, M_MC_CS3_END)
454 454
455/* 455/*
456 * Chip Select Interleave Register (Table 6-19) 456 * Chip Select Interleave Register (Table 6-19)
457 */ 457 */
458 458
459#define S_MC_INTLV_RESERVED 0 459#define S_MC_INTLV_RESERVED 0
460#define M_MC_INTLV_RESERVED _SB_MAKEMASK(5,S_MC_INTLV_RESERVED) 460#define M_MC_INTLV_RESERVED _SB_MAKEMASK(5, S_MC_INTLV_RESERVED)
461 461
462#define S_MC_INTERLEAVE 7 462#define S_MC_INTERLEAVE 7
463#define M_MC_INTERLEAVE _SB_MAKEMASK(18,S_MC_INTERLEAVE) 463#define M_MC_INTERLEAVE _SB_MAKEMASK(18, S_MC_INTERLEAVE)
464#define V_MC_INTERLEAVE(x) _SB_MAKEVALUE(x,S_MC_INTERLEAVE) 464#define V_MC_INTERLEAVE(x) _SB_MAKEVALUE(x, S_MC_INTERLEAVE)
465 465
466#define S_MC_INTLV_MBZ 25 466#define S_MC_INTLV_MBZ 25
467#define M_MC_INTLV_MBZ _SB_MAKEMASK(39,S_MC_INTLV_MBZ) 467#define M_MC_INTLV_MBZ _SB_MAKEMASK(39, S_MC_INTLV_MBZ)
468 468
469/* 469/*
470 * Row Address Bits Register (Table 6-20) 470 * Row Address Bits Register (Table 6-20)
471 */ 471 */
472 472
473#define S_MC_RAS_RESERVED 0 473#define S_MC_RAS_RESERVED 0
474#define M_MC_RAS_RESERVED _SB_MAKEMASK(5,S_MC_RAS_RESERVED) 474#define M_MC_RAS_RESERVED _SB_MAKEMASK(5, S_MC_RAS_RESERVED)
475 475
476#define S_MC_RAS_SELECT 12 476#define S_MC_RAS_SELECT 12
477#define M_MC_RAS_SELECT _SB_MAKEMASK(25,S_MC_RAS_SELECT) 477#define M_MC_RAS_SELECT _SB_MAKEMASK(25, S_MC_RAS_SELECT)
478#define V_MC_RAS_SELECT(x) _SB_MAKEVALUE(x,S_MC_RAS_SELECT) 478#define V_MC_RAS_SELECT(x) _SB_MAKEVALUE(x, S_MC_RAS_SELECT)
479 479
480#define S_MC_RAS_MBZ 37 480#define S_MC_RAS_MBZ 37
481#define M_MC_RAS_MBZ _SB_MAKEMASK(27,S_MC_RAS_MBZ) 481#define M_MC_RAS_MBZ _SB_MAKEMASK(27, S_MC_RAS_MBZ)
482 482
483 483
484/* 484/*
@@ -486,14 +486,14 @@
486 */ 486 */
487 487
488#define S_MC_CAS_RESERVED 0 488#define S_MC_CAS_RESERVED 0
489#define M_MC_CAS_RESERVED _SB_MAKEMASK(5,S_MC_CAS_RESERVED) 489#define M_MC_CAS_RESERVED _SB_MAKEMASK(5, S_MC_CAS_RESERVED)
490 490
491#define S_MC_CAS_SELECT 5 491#define S_MC_CAS_SELECT 5
492#define M_MC_CAS_SELECT _SB_MAKEMASK(18,S_MC_CAS_SELECT) 492#define M_MC_CAS_SELECT _SB_MAKEMASK(18, S_MC_CAS_SELECT)
493#define V_MC_CAS_SELECT(x) _SB_MAKEVALUE(x,S_MC_CAS_SELECT) 493#define V_MC_CAS_SELECT(x) _SB_MAKEVALUE(x, S_MC_CAS_SELECT)
494 494
495#define S_MC_CAS_MBZ 23 495#define S_MC_CAS_MBZ 23
496#define M_MC_CAS_MBZ _SB_MAKEMASK(41,S_MC_CAS_MBZ) 496#define M_MC_CAS_MBZ _SB_MAKEMASK(41, S_MC_CAS_MBZ)
497 497
498 498
499/* 499/*
@@ -501,14 +501,14 @@
501 */ 501 */
502 502
503#define S_MC_BA_RESERVED 0 503#define S_MC_BA_RESERVED 0
504#define M_MC_BA_RESERVED _SB_MAKEMASK(5,S_MC_BA_RESERVED) 504#define M_MC_BA_RESERVED _SB_MAKEMASK(5, S_MC_BA_RESERVED)
505 505
506#define S_MC_BA_SELECT 5 506#define S_MC_BA_SELECT 5
507#define M_MC_BA_SELECT _SB_MAKEMASK(20,S_MC_BA_SELECT) 507#define M_MC_BA_SELECT _SB_MAKEMASK(20, S_MC_BA_SELECT)
508#define V_MC_BA_SELECT(x) _SB_MAKEVALUE(x,S_MC_BA_SELECT) 508#define V_MC_BA_SELECT(x) _SB_MAKEVALUE(x, S_MC_BA_SELECT)
509 509
510#define S_MC_BA_MBZ 25 510#define S_MC_BA_MBZ 25
511#define M_MC_BA_MBZ _SB_MAKEMASK(39,S_MC_BA_MBZ) 511#define M_MC_BA_MBZ _SB_MAKEMASK(39, S_MC_BA_MBZ)
512 512
513/* 513/*
514 * Chip Select Attribute Register (Table 6-23) 514 * Chip Select Attribute Register (Table 6-23)
@@ -520,31 +520,31 @@
520#define K_MC_CS_ATTR_OPEN 3 520#define K_MC_CS_ATTR_OPEN 3
521 521
522#define S_MC_CS0_PAGE 0 522#define S_MC_CS0_PAGE 0
523#define M_MC_CS0_PAGE _SB_MAKEMASK(2,S_MC_CS0_PAGE) 523#define M_MC_CS0_PAGE _SB_MAKEMASK(2, S_MC_CS0_PAGE)
524#define V_MC_CS0_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS0_PAGE) 524#define V_MC_CS0_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS0_PAGE)
525#define G_MC_CS0_PAGE(x) _SB_GETVALUE(x,S_MC_CS0_PAGE,M_MC_CS0_PAGE) 525#define G_MC_CS0_PAGE(x) _SB_GETVALUE(x, S_MC_CS0_PAGE, M_MC_CS0_PAGE)
526 526
527#define S_MC_CS1_PAGE 16 527#define S_MC_CS1_PAGE 16
528#define M_MC_CS1_PAGE _SB_MAKEMASK(2,S_MC_CS1_PAGE) 528#define M_MC_CS1_PAGE _SB_MAKEMASK(2, S_MC_CS1_PAGE)
529#define V_MC_CS1_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS1_PAGE) 529#define V_MC_CS1_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS1_PAGE)
530#define G_MC_CS1_PAGE(x) _SB_GETVALUE(x,S_MC_CS1_PAGE,M_MC_CS1_PAGE) 530#define G_MC_CS1_PAGE(x) _SB_GETVALUE(x, S_MC_CS1_PAGE, M_MC_CS1_PAGE)
531 531
532#define S_MC_CS2_PAGE 32 532#define S_MC_CS2_PAGE 32
533#define M_MC_CS2_PAGE _SB_MAKEMASK(2,S_MC_CS2_PAGE) 533#define M_MC_CS2_PAGE _SB_MAKEMASK(2, S_MC_CS2_PAGE)
534#define V_MC_CS2_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS2_PAGE) 534#define V_MC_CS2_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS2_PAGE)
535#define G_MC_CS2_PAGE(x) _SB_GETVALUE(x,S_MC_CS2_PAGE,M_MC_CS2_PAGE) 535#define G_MC_CS2_PAGE(x) _SB_GETVALUE(x, S_MC_CS2_PAGE, M_MC_CS2_PAGE)
536 536
537#define S_MC_CS3_PAGE 48 537#define S_MC_CS3_PAGE 48
538#define M_MC_CS3_PAGE _SB_MAKEMASK(2,S_MC_CS3_PAGE) 538#define M_MC_CS3_PAGE _SB_MAKEMASK(2, S_MC_CS3_PAGE)
539#define V_MC_CS3_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS3_PAGE) 539#define V_MC_CS3_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS3_PAGE)
540#define G_MC_CS3_PAGE(x) _SB_GETVALUE(x,S_MC_CS3_PAGE,M_MC_CS3_PAGE) 540#define G_MC_CS3_PAGE(x) _SB_GETVALUE(x, S_MC_CS3_PAGE, M_MC_CS3_PAGE)
541 541
542/* 542/*
543 * ECC Test ECC Register (Table 6-25) 543 * ECC Test ECC Register (Table 6-25)
544 */ 544 */
545 545
546#define S_MC_ECC_INVERT 0 546#define S_MC_ECC_INVERT 0
547#define M_MC_ECC_INVERT _SB_MAKEMASK(8,S_MC_ECC_INVERT) 547#define M_MC_ECC_INVERT _SB_MAKEMASK(8, S_MC_ECC_INVERT)
548 548
549 549
550#endif 550#endif
diff --git a/include/asm-mips/sibyte/sb1250_regs.h b/include/asm-mips/sibyte/sb1250_regs.h
index 220b7e94f1bf..8f53ec817a5e 100644
--- a/include/asm-mips/sibyte/sb1250_regs.h
+++ b/include/asm-mips/sibyte/sb1250_regs.h
@@ -66,7 +66,7 @@
66#define MC_REGISTER_SPACING 0x1000 66#define MC_REGISTER_SPACING 0x1000
67 67
68#define A_MC_BASE(ctlid) ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0) 68#define A_MC_BASE(ctlid) ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0)
69#define A_MC_REGISTER(ctlid,reg) (A_MC_BASE(ctlid)+(reg)) 69#define A_MC_REGISTER(ctlid, reg) (A_MC_BASE(ctlid)+(reg))
70 70
71#define R_MC_CONFIG 0x0000000100 71#define R_MC_CONFIG 0x0000000100
72#define R_MC_DRAMCMD 0x0000000120 72#define R_MC_DRAMCMD 0x0000000120
@@ -173,23 +173,23 @@
173 173
174#define R_MAC_DMA_CHANNELS 0x800 /* Relative to A_MAC_CHANNEL_BASE */ 174#define R_MAC_DMA_CHANNELS 0x800 /* Relative to A_MAC_CHANNEL_BASE */
175 175
176#define A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) \ 176#define A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan) \
177 ((A_MAC_CHANNEL_BASE(macnum)) + \ 177 ((A_MAC_CHANNEL_BASE(macnum)) + \
178 R_MAC_DMA_CHANNELS + \ 178 R_MAC_DMA_CHANNELS + \
179 (MAC_DMA_TXRX_SPACING*(txrx)) + \ 179 (MAC_DMA_TXRX_SPACING*(txrx)) + \
180 (MAC_DMA_CHANNEL_SPACING*(chan))) 180 (MAC_DMA_CHANNEL_SPACING*(chan)))
181 181
182#define R_MAC_DMA_CHANNEL_BASE(txrx,chan) \ 182#define R_MAC_DMA_CHANNEL_BASE(txrx, chan) \
183 (R_MAC_DMA_CHANNELS + \ 183 (R_MAC_DMA_CHANNELS + \
184 (MAC_DMA_TXRX_SPACING*(txrx)) + \ 184 (MAC_DMA_TXRX_SPACING*(txrx)) + \
185 (MAC_DMA_CHANNEL_SPACING*(chan))) 185 (MAC_DMA_CHANNEL_SPACING*(chan)))
186 186
187#define A_MAC_DMA_REGISTER(macnum,txrx,chan,reg) \ 187#define A_MAC_DMA_REGISTER(macnum, txrx, chan, reg) \
188 (A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) + \ 188 (A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan) + \
189 (reg)) 189 (reg))
190 190
191#define R_MAC_DMA_REGISTER(txrx,chan,reg) \ 191#define R_MAC_DMA_REGISTER(txrx, chan, reg) \
192 (R_MAC_DMA_CHANNEL_BASE(txrx,chan) + \ 192 (R_MAC_DMA_CHANNEL_BASE(txrx, chan) + \
193 (reg)) 193 (reg))
194 194
195/* 195/*
@@ -415,8 +415,8 @@
415 R_SER_DMA_CHANNELS + \ 415 R_SER_DMA_CHANNELS + \
416 (SER_DMA_TXRX_SPACING*(txrx))) 416 (SER_DMA_TXRX_SPACING*(txrx)))
417 417
418#define A_SER_DMA_REGISTER(sernum,txrx,reg) \ 418#define A_SER_DMA_REGISTER(sernum, txrx, reg) \
419 (A_SER_DMA_CHANNEL_BASE(sernum,txrx) + \ 419 (A_SER_DMA_CHANNEL_BASE(sernum, txrx) + \
420 (reg)) 420 (reg))
421 421
422 422
@@ -499,7 +499,7 @@
499 499
500#define IO_EXT_REGISTER_SPACING 8 500#define IO_EXT_REGISTER_SPACING 8
501#define A_IO_EXT_CS_BASE(cs) (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs)) 501#define A_IO_EXT_CS_BASE(cs) (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs))
502#define R_IO_EXT_REG(reg,cs) ((cs)*IO_EXT_REGISTER_SPACING + (reg)) 502#define R_IO_EXT_REG(reg, cs) ((cs)*IO_EXT_REGISTER_SPACING + (reg))
503 503
504#define R_IO_EXT_CFG 0x0000 504#define R_IO_EXT_CFG 0x0000
505#define R_IO_EXT_MULT_SIZE 0x0100 505#define R_IO_EXT_MULT_SIZE 0x0100
@@ -587,7 +587,7 @@
587#define A_SMB_1 0x0010060008 587#define A_SMB_1 0x0010060008
588#define SMB_REGISTER_SPACING 0x8 588#define SMB_REGISTER_SPACING 0x8
589#define A_SMB_BASE(idx) (A_SMB_0+(idx)*SMB_REGISTER_SPACING) 589#define A_SMB_BASE(idx) (A_SMB_0+(idx)*SMB_REGISTER_SPACING)
590#define A_SMB_REGISTER(idx,reg) (A_SMB_BASE(idx)+(reg)) 590#define A_SMB_REGISTER(idx, reg) (A_SMB_BASE(idx)+(reg))
591 591
592#define R_SMB_XTRA 0x0000000000 592#define R_SMB_XTRA 0x0000000000
593#define R_SMB_FREQ 0x0000000010 593#define R_SMB_FREQ 0x0000000010
@@ -611,7 +611,7 @@
611#define SCD_WDOG_SPACING 0x100 611#define SCD_WDOG_SPACING 0x100
612#define SCD_NUM_WDOGS 2 612#define SCD_NUM_WDOGS 2
613#define A_SCD_WDOG_BASE(w) (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w)) 613#define A_SCD_WDOG_BASE(w) (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w))
614#define A_SCD_WDOG_REGISTER(w,r) (A_SCD_WDOG_BASE(w) + (r)) 614#define A_SCD_WDOG_REGISTER(w, r) (A_SCD_WDOG_BASE(w) + (r))
615 615
616#define R_SCD_WDOG_INIT 0x0000000000 616#define R_SCD_WDOG_INIT 0x0000000000
617#define R_SCD_WDOG_CNT 0x0000000008 617#define R_SCD_WDOG_CNT 0x0000000008
@@ -635,7 +635,7 @@
635#define A_SCD_TIMER_3 0x0010020178 635#define A_SCD_TIMER_3 0x0010020178
636#define SCD_NUM_TIMERS 4 636#define SCD_NUM_TIMERS 4
637#define A_SCD_TIMER_BASE(w) (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1)) 637#define A_SCD_TIMER_BASE(w) (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1))
638#define A_SCD_TIMER_REGISTER(w,r) (A_SCD_TIMER_BASE(w) + (r)) 638#define A_SCD_TIMER_REGISTER(w, r) (A_SCD_TIMER_BASE(w) + (r))
639 639
640#define R_SCD_TIMER_INIT 0x0000000000 640#define R_SCD_TIMER_INIT 0x0000000000
641#define R_SCD_TIMER_CNT 0x0000000010 641#define R_SCD_TIMER_CNT 0x0000000010
@@ -714,7 +714,7 @@
714#define IMR_REGISTER_SPACING_SHIFT 13 714#define IMR_REGISTER_SPACING_SHIFT 13
715 715
716#define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING) 716#define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING)
717#define A_IMR_REGISTER(cpu,reg) (A_IMR_MAPPER(cpu)+(reg)) 717#define A_IMR_REGISTER(cpu, reg) (A_IMR_MAPPER(cpu)+(reg))
718 718
719#define R_IMR_INTERRUPT_DIAG 0x0010 719#define R_IMR_INTERRUPT_DIAG 0x0010
720#define R_IMR_INTERRUPT_LDT 0x0018 720#define R_IMR_INTERRUPT_LDT 0x0018
@@ -821,7 +821,7 @@
821#define DM_REGISTER_SPACING 0x20 821#define DM_REGISTER_SPACING 0x20
822#define DM_NUM_CHANNELS 4 822#define DM_NUM_CHANNELS 4
823#define A_DM_BASE(idx) (A_DM_0 + ((idx) * DM_REGISTER_SPACING)) 823#define A_DM_BASE(idx) (A_DM_0 + ((idx) * DM_REGISTER_SPACING))
824#define A_DM_REGISTER(idx,reg) (A_DM_BASE(idx) + (reg)) 824#define A_DM_REGISTER(idx, reg) (A_DM_BASE(idx) + (reg))
825 825
826#define R_DM_DSCR_BASE 0x0000000000 826#define R_DM_DSCR_BASE 0x0000000000
827#define R_DM_DSCR_COUNT 0x0000000008 827#define R_DM_DSCR_COUNT 0x0000000008
@@ -843,7 +843,7 @@
843#define DM_CRC_REGISTER_SPACING 0x10 843#define DM_CRC_REGISTER_SPACING 0x10
844#define DM_CRC_NUM_CHANNELS 2 844#define DM_CRC_NUM_CHANNELS 2
845#define A_DM_CRC_BASE(idx) (A_DM_CRC_0 + ((idx) * DM_CRC_REGISTER_SPACING)) 845#define A_DM_CRC_BASE(idx) (A_DM_CRC_0 + ((idx) * DM_CRC_REGISTER_SPACING))
846#define A_DM_CRC_REGISTER(idx,reg) (A_DM_CRC_BASE(idx) + (reg)) 846#define A_DM_CRC_REGISTER(idx, reg) (A_DM_CRC_BASE(idx) + (reg))
847 847
848#define R_CRC_DEF_0 0x00 848#define R_CRC_DEF_0 0x00
849#define R_CTCP_DEF_0 0x08 849#define R_CTCP_DEF_0 0x08
diff --git a/include/asm-mips/sibyte/sb1250_scd.h b/include/asm-mips/sibyte/sb1250_scd.h
index 9ea3da367ab6..e49c3e89b5ee 100644
--- a/include/asm-mips/sibyte/sb1250_scd.h
+++ b/include/asm-mips/sibyte/sb1250_scd.h
@@ -42,12 +42,12 @@
42 * System Revision Register (Table 4-1) 42 * System Revision Register (Table 4-1)
43 */ 43 */
44 44
45#define M_SYS_RESERVED _SB_MAKEMASK(8,0) 45#define M_SYS_RESERVED _SB_MAKEMASK(8, 0)
46 46
47#define S_SYS_REVISION _SB_MAKE64(8) 47#define S_SYS_REVISION _SB_MAKE64(8)
48#define M_SYS_REVISION _SB_MAKEMASK(8,S_SYS_REVISION) 48#define M_SYS_REVISION _SB_MAKEMASK(8, S_SYS_REVISION)
49#define V_SYS_REVISION(x) _SB_MAKEVALUE(x,S_SYS_REVISION) 49#define V_SYS_REVISION(x) _SB_MAKEVALUE(x, S_SYS_REVISION)
50#define G_SYS_REVISION(x) _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION) 50#define G_SYS_REVISION(x) _SB_GETVALUE(x, S_SYS_REVISION, M_SYS_REVISION)
51 51
52#define K_SYS_REVISION_BCM1250_PASS1 0x01 52#define K_SYS_REVISION_BCM1250_PASS1 0x01
53 53
@@ -94,9 +94,9 @@
94 94
95/*Cache size - 23:20 of revision register*/ 95/*Cache size - 23:20 of revision register*/
96#define S_SYS_L2C_SIZE _SB_MAKE64(20) 96#define S_SYS_L2C_SIZE _SB_MAKE64(20)
97#define M_SYS_L2C_SIZE _SB_MAKEMASK(4,S_SYS_L2C_SIZE) 97#define M_SYS_L2C_SIZE _SB_MAKEMASK(4, S_SYS_L2C_SIZE)
98#define V_SYS_L2C_SIZE(x) _SB_MAKEVALUE(x,S_SYS_L2C_SIZE) 98#define V_SYS_L2C_SIZE(x) _SB_MAKEVALUE(x, S_SYS_L2C_SIZE)
99#define G_SYS_L2C_SIZE(x) _SB_GETVALUE(x,S_SYS_L2C_SIZE,M_SYS_L2C_SIZE) 99#define G_SYS_L2C_SIZE(x) _SB_GETVALUE(x, S_SYS_L2C_SIZE, M_SYS_L2C_SIZE)
100 100
101#define K_SYS_L2C_SIZE_1MB 0 101#define K_SYS_L2C_SIZE_1MB 0
102#define K_SYS_L2C_SIZE_512KB 5 102#define K_SYS_L2C_SIZE_512KB 5
@@ -110,16 +110,16 @@
110 110
111/* Number of CPU cores, bits 27:24 of revision register*/ 111/* Number of CPU cores, bits 27:24 of revision register*/
112#define S_SYS_NUM_CPUS _SB_MAKE64(24) 112#define S_SYS_NUM_CPUS _SB_MAKE64(24)
113#define M_SYS_NUM_CPUS _SB_MAKEMASK(4,S_SYS_NUM_CPUS) 113#define M_SYS_NUM_CPUS _SB_MAKEMASK(4, S_SYS_NUM_CPUS)
114#define V_SYS_NUM_CPUS(x) _SB_MAKEVALUE(x,S_SYS_NUM_CPUS) 114#define V_SYS_NUM_CPUS(x) _SB_MAKEVALUE(x, S_SYS_NUM_CPUS)
115#define G_SYS_NUM_CPUS(x) _SB_GETVALUE(x,S_SYS_NUM_CPUS,M_SYS_NUM_CPUS) 115#define G_SYS_NUM_CPUS(x) _SB_GETVALUE(x, S_SYS_NUM_CPUS, M_SYS_NUM_CPUS)
116 116
117 117
118/* XXX: discourage people from using these constants. */ 118/* XXX: discourage people from using these constants. */
119#define S_SYS_PART _SB_MAKE64(16) 119#define S_SYS_PART _SB_MAKE64(16)
120#define M_SYS_PART _SB_MAKEMASK(16,S_SYS_PART) 120#define M_SYS_PART _SB_MAKEMASK(16, S_SYS_PART)
121#define V_SYS_PART(x) _SB_MAKEVALUE(x,S_SYS_PART) 121#define V_SYS_PART(x) _SB_MAKEVALUE(x, S_SYS_PART)
122#define G_SYS_PART(x) _SB_GETVALUE(x,S_SYS_PART,M_SYS_PART) 122#define G_SYS_PART(x) _SB_GETVALUE(x, S_SYS_PART, M_SYS_PART)
123 123
124/* XXX: discourage people from using these constants. */ 124/* XXX: discourage people from using these constants. */
125#define K_SYS_PART_SB1250 0x1250 125#define K_SYS_PART_SB1250 0x1250
@@ -131,9 +131,9 @@
131 131
132/* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */ 132/* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */
133#define S_SYS_SOC_TYPE _SB_MAKE64(16) 133#define S_SYS_SOC_TYPE _SB_MAKE64(16)
134#define M_SYS_SOC_TYPE _SB_MAKEMASK(4,S_SYS_SOC_TYPE) 134#define M_SYS_SOC_TYPE _SB_MAKEMASK(4, S_SYS_SOC_TYPE)
135#define V_SYS_SOC_TYPE(x) _SB_MAKEVALUE(x,S_SYS_SOC_TYPE) 135#define V_SYS_SOC_TYPE(x) _SB_MAKEVALUE(x, S_SYS_SOC_TYPE)
136#define G_SYS_SOC_TYPE(x) _SB_GETVALUE(x,S_SYS_SOC_TYPE,M_SYS_SOC_TYPE) 136#define G_SYS_SOC_TYPE(x) _SB_GETVALUE(x, S_SYS_SOC_TYPE, M_SYS_SOC_TYPE)
137 137
138#define K_SYS_SOC_TYPE_BCM1250 0x0 138#define K_SYS_SOC_TYPE_BCM1250 0x0
139#define K_SYS_SOC_TYPE_BCM1120 0x1 139#define K_SYS_SOC_TYPE_BCM1120 0x1
@@ -170,9 +170,9 @@
170#endif 170#endif
171 171
172#define S_SYS_WID _SB_MAKE64(32) 172#define S_SYS_WID _SB_MAKE64(32)
173#define M_SYS_WID _SB_MAKEMASK(32,S_SYS_WID) 173#define M_SYS_WID _SB_MAKEMASK(32, S_SYS_WID)
174#define V_SYS_WID(x) _SB_MAKEVALUE(x,S_SYS_WID) 174#define V_SYS_WID(x) _SB_MAKEVALUE(x, S_SYS_WID)
175#define G_SYS_WID(x) _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID) 175#define G_SYS_WID(x) _SB_GETVALUE(x, S_SYS_WID, M_SYS_WID)
176 176
177/* 177/*
178 * System Manufacturing Register 178 * System Manufacturing Register
@@ -182,36 +182,36 @@
182#if SIBYTE_HDR_FEATURE_1250_112x 182#if SIBYTE_HDR_FEATURE_1250_112x
183/* Wafer ID: bits 31:0 */ 183/* Wafer ID: bits 31:0 */
184#define S_SYS_WAFERID1_200 _SB_MAKE64(0) 184#define S_SYS_WAFERID1_200 _SB_MAKE64(0)
185#define M_SYS_WAFERID1_200 _SB_MAKEMASK(32,S_SYS_WAFERID1_200) 185#define M_SYS_WAFERID1_200 _SB_MAKEMASK(32, S_SYS_WAFERID1_200)
186#define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID1_200) 186#define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x, S_SYS_WAFERID1_200)
187#define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x,S_SYS_WAFERID1_200,M_SYS_WAFERID1_200) 187#define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x, S_SYS_WAFERID1_200, M_SYS_WAFERID1_200)
188 188
189#define S_SYS_BIN _SB_MAKE64(32) 189#define S_SYS_BIN _SB_MAKE64(32)
190#define M_SYS_BIN _SB_MAKEMASK(4,S_SYS_BIN) 190#define M_SYS_BIN _SB_MAKEMASK(4, S_SYS_BIN)
191#define V_SYS_BIN(x) _SB_MAKEVALUE(x,S_SYS_BIN) 191#define V_SYS_BIN(x) _SB_MAKEVALUE(x, S_SYS_BIN)
192#define G_SYS_BIN(x) _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN) 192#define G_SYS_BIN(x) _SB_GETVALUE(x, S_SYS_BIN, M_SYS_BIN)
193 193
194/* Wafer ID: bits 39:36 */ 194/* Wafer ID: bits 39:36 */
195#define S_SYS_WAFERID2_200 _SB_MAKE64(36) 195#define S_SYS_WAFERID2_200 _SB_MAKE64(36)
196#define M_SYS_WAFERID2_200 _SB_MAKEMASK(4,S_SYS_WAFERID2_200) 196#define M_SYS_WAFERID2_200 _SB_MAKEMASK(4, S_SYS_WAFERID2_200)
197#define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID2_200) 197#define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x, S_SYS_WAFERID2_200)
198#define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x,S_SYS_WAFERID2_200,M_SYS_WAFERID2_200) 198#define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x, S_SYS_WAFERID2_200, M_SYS_WAFERID2_200)
199 199
200/* Wafer ID: bits 39:0 */ 200/* Wafer ID: bits 39:0 */
201#define S_SYS_WAFERID_300 _SB_MAKE64(0) 201#define S_SYS_WAFERID_300 _SB_MAKE64(0)
202#define M_SYS_WAFERID_300 _SB_MAKEMASK(40,S_SYS_WAFERID_300) 202#define M_SYS_WAFERID_300 _SB_MAKEMASK(40, S_SYS_WAFERID_300)
203#define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x,S_SYS_WAFERID_300) 203#define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x, S_SYS_WAFERID_300)
204#define G_SYS_WAFERID_300(x) _SB_GETVALUE(x,S_SYS_WAFERID_300,M_SYS_WAFERID_300) 204#define G_SYS_WAFERID_300(x) _SB_GETVALUE(x, S_SYS_WAFERID_300, M_SYS_WAFERID_300)
205 205
206#define S_SYS_XPOS _SB_MAKE64(40) 206#define S_SYS_XPOS _SB_MAKE64(40)
207#define M_SYS_XPOS _SB_MAKEMASK(6,S_SYS_XPOS) 207#define M_SYS_XPOS _SB_MAKEMASK(6, S_SYS_XPOS)
208#define V_SYS_XPOS(x) _SB_MAKEVALUE(x,S_SYS_XPOS) 208#define V_SYS_XPOS(x) _SB_MAKEVALUE(x, S_SYS_XPOS)
209#define G_SYS_XPOS(x) _SB_GETVALUE(x,S_SYS_XPOS,M_SYS_XPOS) 209#define G_SYS_XPOS(x) _SB_GETVALUE(x, S_SYS_XPOS, M_SYS_XPOS)
210 210
211#define S_SYS_YPOS _SB_MAKE64(46) 211#define S_SYS_YPOS _SB_MAKE64(46)
212#define M_SYS_YPOS _SB_MAKEMASK(6,S_SYS_YPOS) 212#define M_SYS_YPOS _SB_MAKEMASK(6, S_SYS_YPOS)
213#define V_SYS_YPOS(x) _SB_MAKEVALUE(x,S_SYS_YPOS) 213#define V_SYS_YPOS(x) _SB_MAKEVALUE(x, S_SYS_YPOS)
214#define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS) 214#define G_SYS_YPOS(x) _SB_GETVALUE(x, S_SYS_YPOS, M_SYS_YPOS)
215#endif 215#endif
216 216
217 217
@@ -227,9 +227,9 @@
227#define M_SYS_IOB1_DIV _SB_MAKEMASK1(6) 227#define M_SYS_IOB1_DIV _SB_MAKEMASK1(6)
228 228
229#define S_SYS_PLL_DIV _SB_MAKE64(7) 229#define S_SYS_PLL_DIV _SB_MAKE64(7)
230#define M_SYS_PLL_DIV _SB_MAKEMASK(5,S_SYS_PLL_DIV) 230#define M_SYS_PLL_DIV _SB_MAKEMASK(5, S_SYS_PLL_DIV)
231#define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x,S_SYS_PLL_DIV) 231#define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x, S_SYS_PLL_DIV)
232#define G_SYS_PLL_DIV(x) _SB_GETVALUE(x,S_SYS_PLL_DIV,M_SYS_PLL_DIV) 232#define G_SYS_PLL_DIV(x) _SB_GETVALUE(x, S_SYS_PLL_DIV, M_SYS_PLL_DIV)
233 233
234#define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12) 234#define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12)
235#define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13) 235#define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13)
@@ -238,9 +238,9 @@
238#define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) 238#define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16)
239 239
240#define S_SYS_BOOT_MODE _SB_MAKE64(17) 240#define S_SYS_BOOT_MODE _SB_MAKE64(17)
241#define M_SYS_BOOT_MODE _SB_MAKEMASK(2,S_SYS_BOOT_MODE) 241#define M_SYS_BOOT_MODE _SB_MAKEMASK(2, S_SYS_BOOT_MODE)
242#define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x,S_SYS_BOOT_MODE) 242#define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x, S_SYS_BOOT_MODE)
243#define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x,S_SYS_BOOT_MODE,M_SYS_BOOT_MODE) 243#define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x, S_SYS_BOOT_MODE, M_SYS_BOOT_MODE)
244#define K_SYS_BOOT_MODE_ROM32 0 244#define K_SYS_BOOT_MODE_ROM32 0
245#define K_SYS_BOOT_MODE_ROM8 1 245#define K_SYS_BOOT_MODE_ROM8 1
246#define K_SYS_BOOT_MODE_SMBUS_SMALL 2 246#define K_SYS_BOOT_MODE_SMBUS_SMALL 2
@@ -255,9 +255,9 @@
255#define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25) 255#define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25)
256 256
257#define S_SYS_CONFIG 26 257#define S_SYS_CONFIG 26
258#define M_SYS_CONFIG _SB_MAKEMASK(6,S_SYS_CONFIG) 258#define M_SYS_CONFIG _SB_MAKEMASK(6, S_SYS_CONFIG)
259#define V_SYS_CONFIG(x) _SB_MAKEVALUE(x,S_SYS_CONFIG) 259#define V_SYS_CONFIG(x) _SB_MAKEVALUE(x, S_SYS_CONFIG)
260#define G_SYS_CONFIG(x) _SB_GETVALUE(x,S_SYS_CONFIG,M_SYS_CONFIG) 260#define G_SYS_CONFIG(x) _SB_GETVALUE(x, S_SYS_CONFIG, M_SYS_CONFIG)
261 261
262/* The following bits are writeable by JTAG only. */ 262/* The following bits are writeable by JTAG only. */
263 263
@@ -265,20 +265,20 @@
265#define M_SYS_CLKSTEP _SB_MAKEMASK1(33) 265#define M_SYS_CLKSTEP _SB_MAKEMASK1(33)
266 266
267#define S_SYS_CLKCOUNT 34 267#define S_SYS_CLKCOUNT 34
268#define M_SYS_CLKCOUNT _SB_MAKEMASK(8,S_SYS_CLKCOUNT) 268#define M_SYS_CLKCOUNT _SB_MAKEMASK(8, S_SYS_CLKCOUNT)
269#define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x,S_SYS_CLKCOUNT) 269#define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x, S_SYS_CLKCOUNT)
270#define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x,S_SYS_CLKCOUNT,M_SYS_CLKCOUNT) 270#define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x, S_SYS_CLKCOUNT, M_SYS_CLKCOUNT)
271 271
272#define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42) 272#define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42)
273 273
274#define S_SYS_PLL_IREF 43 274#define S_SYS_PLL_IREF 43
275#define M_SYS_PLL_IREF _SB_MAKEMASK(2,S_SYS_PLL_IREF) 275#define M_SYS_PLL_IREF _SB_MAKEMASK(2, S_SYS_PLL_IREF)
276 276
277#define S_SYS_PLL_VCO 45 277#define S_SYS_PLL_VCO 45
278#define M_SYS_PLL_VCO _SB_MAKEMASK(2,S_SYS_PLL_VCO) 278#define M_SYS_PLL_VCO _SB_MAKEMASK(2, S_SYS_PLL_VCO)
279 279
280#define S_SYS_PLL_VREG 47 280#define S_SYS_PLL_VREG 47
281#define M_SYS_PLL_VREG _SB_MAKEMASK(2,S_SYS_PLL_VREG) 281#define M_SYS_PLL_VREG _SB_MAKEMASK(2, S_SYS_PLL_VREG)
282 282
283#define M_SYS_MEM_RESET _SB_MAKEMASK1(49) 283#define M_SYS_MEM_RESET _SB_MAKEMASK1(49)
284#define M_SYS_L2C_RESET _SB_MAKEMASK1(50) 284#define M_SYS_L2C_RESET _SB_MAKEMASK1(50)
@@ -314,13 +314,13 @@
314 */ 314 */
315 315
316#define S_MBOX_INT_3 0 316#define S_MBOX_INT_3 0
317#define M_MBOX_INT_3 _SB_MAKEMASK(16,S_MBOX_INT_3) 317#define M_MBOX_INT_3 _SB_MAKEMASK(16, S_MBOX_INT_3)
318#define S_MBOX_INT_2 16 318#define S_MBOX_INT_2 16
319#define M_MBOX_INT_2 _SB_MAKEMASK(16,S_MBOX_INT_2) 319#define M_MBOX_INT_2 _SB_MAKEMASK(16, S_MBOX_INT_2)
320#define S_MBOX_INT_1 32 320#define S_MBOX_INT_1 32
321#define M_MBOX_INT_1 _SB_MAKEMASK(16,S_MBOX_INT_1) 321#define M_MBOX_INT_1 _SB_MAKEMASK(16, S_MBOX_INT_1)
322#define S_MBOX_INT_0 48 322#define S_MBOX_INT_0 48
323#define M_MBOX_INT_0 _SB_MAKEMASK(16,S_MBOX_INT_0) 323#define M_MBOX_INT_0 _SB_MAKEMASK(16, S_MBOX_INT_0)
324 324
325/* 325/*
326 * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10) 326 * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10)
@@ -330,18 +330,18 @@
330#define V_SCD_WDOG_FREQ 1000000 330#define V_SCD_WDOG_FREQ 1000000
331 331
332#define S_SCD_WDOG_INIT 0 332#define S_SCD_WDOG_INIT 0
333#define M_SCD_WDOG_INIT _SB_MAKEMASK(23,S_SCD_WDOG_INIT) 333#define M_SCD_WDOG_INIT _SB_MAKEMASK(23, S_SCD_WDOG_INIT)
334 334
335#define S_SCD_WDOG_CNT 0 335#define S_SCD_WDOG_CNT 0
336#define M_SCD_WDOG_CNT _SB_MAKEMASK(23,S_SCD_WDOG_CNT) 336#define M_SCD_WDOG_CNT _SB_MAKEMASK(23, S_SCD_WDOG_CNT)
337 337
338#define S_SCD_WDOG_ENABLE 0 338#define S_SCD_WDOG_ENABLE 0
339#define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(S_SCD_WDOG_ENABLE) 339#define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(S_SCD_WDOG_ENABLE)
340 340
341#define S_SCD_WDOG_RESET_TYPE 2 341#define S_SCD_WDOG_RESET_TYPE 2
342#define M_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(3,S_SCD_WDOG_RESET_TYPE) 342#define M_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(3, S_SCD_WDOG_RESET_TYPE)
343#define V_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x,S_SCD_WDOG_RESET_TYPE) 343#define V_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x, S_SCD_WDOG_RESET_TYPE)
344#define G_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x,S_SCD_WDOG_RESET_TYPE,M_SCD_WDOG_RESET_TYPE) 344#define G_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x, S_SCD_WDOG_RESET_TYPE, M_SCD_WDOG_RESET_TYPE)
345 345
346#define K_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ 346#define K_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */
347#define K_SCD_WDOG_RESET_SOFT 1 347#define K_SCD_WDOG_RESET_SOFT 1
@@ -363,15 +363,15 @@
363#define V_SCD_TIMER_FREQ 1000000 363#define V_SCD_TIMER_FREQ 1000000
364 364
365#define S_SCD_TIMER_INIT 0 365#define S_SCD_TIMER_INIT 0
366#define M_SCD_TIMER_INIT _SB_MAKEMASK(23,S_SCD_TIMER_INIT) 366#define M_SCD_TIMER_INIT _SB_MAKEMASK(23, S_SCD_TIMER_INIT)
367#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT) 367#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x, S_SCD_TIMER_INIT)
368#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT) 368#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x, S_SCD_TIMER_INIT, M_SCD_TIMER_INIT)
369 369
370#define V_SCD_TIMER_WIDTH 23 370#define V_SCD_TIMER_WIDTH 23
371#define S_SCD_TIMER_CNT 0 371#define S_SCD_TIMER_CNT 0
372#define M_SCD_TIMER_CNT _SB_MAKEMASK(V_SCD_TIMER_WIDTH,S_SCD_TIMER_CNT) 372#define M_SCD_TIMER_CNT _SB_MAKEMASK(V_SCD_TIMER_WIDTH, S_SCD_TIMER_CNT)
373#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT) 373#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x, S_SCD_TIMER_CNT)
374#define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x,S_SCD_TIMER_CNT,M_SCD_TIMER_CNT) 374#define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x, S_SCD_TIMER_CNT, M_SCD_TIMER_CNT)
375 375
376#define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0) 376#define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0)
377#define M_SCD_TIMER_MODE _SB_MAKEMASK1(1) 377#define M_SCD_TIMER_MODE _SB_MAKEMASK1(1)
@@ -382,24 +382,24 @@
382 */ 382 */
383 383
384#define S_SPC_CFG_SRC0 0 384#define S_SPC_CFG_SRC0 0
385#define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0) 385#define M_SPC_CFG_SRC0 _SB_MAKEMASK(8, S_SPC_CFG_SRC0)
386#define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0) 386#define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC0)
387#define G_SPC_CFG_SRC0(x) _SB_GETVALUE(x,S_SPC_CFG_SRC0,M_SPC_CFG_SRC0) 387#define G_SPC_CFG_SRC0(x) _SB_GETVALUE(x, S_SPC_CFG_SRC0, M_SPC_CFG_SRC0)
388 388
389#define S_SPC_CFG_SRC1 8 389#define S_SPC_CFG_SRC1 8
390#define M_SPC_CFG_SRC1 _SB_MAKEMASK(8,S_SPC_CFG_SRC1) 390#define M_SPC_CFG_SRC1 _SB_MAKEMASK(8, S_SPC_CFG_SRC1)
391#define V_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC1) 391#define V_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC1)
392#define G_SPC_CFG_SRC1(x) _SB_GETVALUE(x,S_SPC_CFG_SRC1,M_SPC_CFG_SRC1) 392#define G_SPC_CFG_SRC1(x) _SB_GETVALUE(x, S_SPC_CFG_SRC1, M_SPC_CFG_SRC1)
393 393
394#define S_SPC_CFG_SRC2 16 394#define S_SPC_CFG_SRC2 16
395#define M_SPC_CFG_SRC2 _SB_MAKEMASK(8,S_SPC_CFG_SRC2) 395#define M_SPC_CFG_SRC2 _SB_MAKEMASK(8, S_SPC_CFG_SRC2)
396#define V_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC2) 396#define V_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC2)
397#define G_SPC_CFG_SRC2(x) _SB_GETVALUE(x,S_SPC_CFG_SRC2,M_SPC_CFG_SRC2) 397#define G_SPC_CFG_SRC2(x) _SB_GETVALUE(x, S_SPC_CFG_SRC2, M_SPC_CFG_SRC2)
398 398
399#define S_SPC_CFG_SRC3 24 399#define S_SPC_CFG_SRC3 24
400#define M_SPC_CFG_SRC3 _SB_MAKEMASK(8,S_SPC_CFG_SRC3) 400#define M_SPC_CFG_SRC3 _SB_MAKEMASK(8, S_SPC_CFG_SRC3)
401#define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC3) 401#define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC3)
402#define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_SPC_CFG_SRC3,M_SPC_CFG_SRC3) 402#define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x, S_SPC_CFG_SRC3, M_SPC_CFG_SRC3)
403 403
404#if SIBYTE_HDR_FEATURE_1250_112x 404#if SIBYTE_HDR_FEATURE_1250_112x
405#define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32) 405#define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32)
@@ -412,57 +412,57 @@
412 */ 412 */
413 413
414#define S_SCD_BERR_TID 8 414#define S_SCD_BERR_TID 8
415#define M_SCD_BERR_TID _SB_MAKEMASK(10,S_SCD_BERR_TID) 415#define M_SCD_BERR_TID _SB_MAKEMASK(10, S_SCD_BERR_TID)
416#define V_SCD_BERR_TID(x) _SB_MAKEVALUE(x,S_SCD_BERR_TID) 416#define V_SCD_BERR_TID(x) _SB_MAKEVALUE(x, S_SCD_BERR_TID)
417#define G_SCD_BERR_TID(x) _SB_GETVALUE(x,S_SCD_BERR_TID,M_SCD_BERR_TID) 417#define G_SCD_BERR_TID(x) _SB_GETVALUE(x, S_SCD_BERR_TID, M_SCD_BERR_TID)
418 418
419#define S_SCD_BERR_RID 18 419#define S_SCD_BERR_RID 18
420#define M_SCD_BERR_RID _SB_MAKEMASK(4,S_SCD_BERR_RID) 420#define M_SCD_BERR_RID _SB_MAKEMASK(4, S_SCD_BERR_RID)
421#define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x,S_SCD_BERR_RID) 421#define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x, S_SCD_BERR_RID)
422#define G_SCD_BERR_RID(x) _SB_GETVALUE(x,S_SCD_BERR_RID,M_SCD_BERR_RID) 422#define G_SCD_BERR_RID(x) _SB_GETVALUE(x, S_SCD_BERR_RID, M_SCD_BERR_RID)
423 423
424#define S_SCD_BERR_DCODE 22 424#define S_SCD_BERR_DCODE 22
425#define M_SCD_BERR_DCODE _SB_MAKEMASK(3,S_SCD_BERR_DCODE) 425#define M_SCD_BERR_DCODE _SB_MAKEMASK(3, S_SCD_BERR_DCODE)
426#define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x,S_SCD_BERR_DCODE) 426#define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x, S_SCD_BERR_DCODE)
427#define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x,S_SCD_BERR_DCODE,M_SCD_BERR_DCODE) 427#define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x, S_SCD_BERR_DCODE, M_SCD_BERR_DCODE)
428 428
429#define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30) 429#define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30)
430 430
431 431
432#define S_SCD_L2ECC_CORR_D 0 432#define S_SCD_L2ECC_CORR_D 0
433#define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_D) 433#define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_D)
434#define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_D) 434#define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_D)
435#define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_D,M_SCD_L2ECC_CORR_D) 435#define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x, S_SCD_L2ECC_CORR_D, M_SCD_L2ECC_CORR_D)
436 436
437#define S_SCD_L2ECC_BAD_D 8 437#define S_SCD_L2ECC_BAD_D 8
438#define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_D) 438#define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_D)
439#define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_D) 439#define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_D)
440#define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_D,M_SCD_L2ECC_BAD_D) 440#define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x, S_SCD_L2ECC_BAD_D, M_SCD_L2ECC_BAD_D)
441 441
442#define S_SCD_L2ECC_CORR_T 16 442#define S_SCD_L2ECC_CORR_T 16
443#define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_T) 443#define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_T)
444#define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_T) 444#define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_T)
445#define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_T,M_SCD_L2ECC_CORR_T) 445#define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x, S_SCD_L2ECC_CORR_T, M_SCD_L2ECC_CORR_T)
446 446
447#define S_SCD_L2ECC_BAD_T 24 447#define S_SCD_L2ECC_BAD_T 24
448#define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_T) 448#define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_T)
449#define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_T) 449#define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_T)
450#define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_T,M_SCD_L2ECC_BAD_T) 450#define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x, S_SCD_L2ECC_BAD_T, M_SCD_L2ECC_BAD_T)
451 451
452#define S_SCD_MEM_ECC_CORR 0 452#define S_SCD_MEM_ECC_CORR 0
453#define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8,S_SCD_MEM_ECC_CORR) 453#define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8, S_SCD_MEM_ECC_CORR)
454#define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_CORR) 454#define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x, S_SCD_MEM_ECC_CORR)
455#define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_CORR,M_SCD_MEM_ECC_CORR) 455#define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x, S_SCD_MEM_ECC_CORR, M_SCD_MEM_ECC_CORR)
456 456
457#define S_SCD_MEM_ECC_BAD 8 457#define S_SCD_MEM_ECC_BAD 8
458#define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8,S_SCD_MEM_ECC_BAD) 458#define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8, S_SCD_MEM_ECC_BAD)
459#define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_BAD) 459#define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x, S_SCD_MEM_ECC_BAD)
460#define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_BAD,M_SCD_MEM_ECC_BAD) 460#define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x, S_SCD_MEM_ECC_BAD, M_SCD_MEM_ECC_BAD)
461 461
462#define S_SCD_MEM_BUSERR 16 462#define S_SCD_MEM_BUSERR 16
463#define M_SCD_MEM_BUSERR _SB_MAKEMASK(8,S_SCD_MEM_BUSERR) 463#define M_SCD_MEM_BUSERR _SB_MAKEMASK(8, S_SCD_MEM_BUSERR)
464#define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x,S_SCD_MEM_BUSERR) 464#define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x, S_SCD_MEM_BUSERR)
465#define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x,S_SCD_MEM_BUSERR,M_SCD_MEM_BUSERR) 465#define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x, S_SCD_MEM_BUSERR, M_SCD_MEM_BUSERR)
466 466
467 467
468/* 468/*
@@ -470,13 +470,13 @@
470 */ 470 */
471 471
472#if SIBYTE_HDR_FEATURE_1250_112x 472#if SIBYTE_HDR_FEATURE_1250_112x
473#define M_ATRAP_INDEX _SB_MAKEMASK(4,0) 473#define M_ATRAP_INDEX _SB_MAKEMASK(4, 0)
474#define M_ATRAP_ADDRESS _SB_MAKEMASK(40,0) 474#define M_ATRAP_ADDRESS _SB_MAKEMASK(40, 0)
475 475
476#define S_ATRAP_CFG_CNT 0 476#define S_ATRAP_CFG_CNT 0
477#define M_ATRAP_CFG_CNT _SB_MAKEMASK(3,S_ATRAP_CFG_CNT) 477#define M_ATRAP_CFG_CNT _SB_MAKEMASK(3, S_ATRAP_CFG_CNT)
478#define V_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CNT) 478#define V_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x, S_ATRAP_CFG_CNT)
479#define G_ATRAP_CFG_CNT(x) _SB_GETVALUE(x,S_ATRAP_CFG_CNT,M_ATRAP_CFG_CNT) 479#define G_ATRAP_CFG_CNT(x) _SB_GETVALUE(x, S_ATRAP_CFG_CNT, M_ATRAP_CFG_CNT)
480 480
481#define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) 481#define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3)
482#define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4) 482#define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4)
@@ -485,9 +485,9 @@
485#define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) 485#define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7)
486 486
487#define S_ATRAP_CFG_AGENTID 8 487#define S_ATRAP_CFG_AGENTID 8
488#define M_ATRAP_CFG_AGENTID _SB_MAKEMASK(4,S_ATRAP_CFG_AGENTID) 488#define M_ATRAP_CFG_AGENTID _SB_MAKEMASK(4, S_ATRAP_CFG_AGENTID)
489#define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_AGENTID) 489#define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x, S_ATRAP_CFG_AGENTID)
490#define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x,S_ATRAP_CFG_AGENTID,M_ATRAP_CFG_AGENTID) 490#define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x, S_ATRAP_CFG_AGENTID, M_ATRAP_CFG_AGENTID)
491 491
492#define K_BUS_AGENT_CPU0 0 492#define K_BUS_AGENT_CPU0 0
493#define K_BUS_AGENT_CPU1 1 493#define K_BUS_AGENT_CPU1 1
@@ -498,9 +498,9 @@
498#define K_BUS_AGENT_MC 7 498#define K_BUS_AGENT_MC 7
499 499
500#define S_ATRAP_CFG_CATTR 12 500#define S_ATRAP_CFG_CATTR 12
501#define M_ATRAP_CFG_CATTR _SB_MAKEMASK(3,S_ATRAP_CFG_CATTR) 501#define M_ATRAP_CFG_CATTR _SB_MAKEMASK(3, S_ATRAP_CFG_CATTR)
502#define V_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CATTR) 502#define V_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x, S_ATRAP_CFG_CATTR)
503#define G_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x,S_ATRAP_CFG_CATTR,M_ATRAP_CFG_CATTR) 503#define G_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x, S_ATRAP_CFG_CATTR, M_ATRAP_CFG_CATTR)
504 504
505#define K_ATRAP_CFG_CATTR_IGNORE 0 505#define K_ATRAP_CFG_CATTR_IGNORE 0
506#define K_ATRAP_CFG_CATTR_UNC 1 506#define K_ATRAP_CFG_CATTR_UNC 1
@@ -541,18 +541,18 @@
541#endif /* 1480 */ 541#endif /* 1480 */
542#endif /* 1250/112x */ 542#endif /* 1250/112x */
543 543
544#define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_SCD_TRACE_CFG_CUR_ADDR) 544#define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8, S_SCD_TRACE_CFG_CUR_ADDR)
545#define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR) 545#define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR)
546#define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR) 546#define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR, M_SCD_TRACE_CFG_CUR_ADDR)
547 547
548/* 548/*
549 * Trace Event registers 549 * Trace Event registers
550 */ 550 */
551 551
552#define S_SCD_TREVT_ADDR_MATCH 0 552#define S_SCD_TREVT_ADDR_MATCH 0
553#define M_SCD_TREVT_ADDR_MATCH _SB_MAKEMASK(4,S_SCD_TREVT_ADDR_MATCH) 553#define M_SCD_TREVT_ADDR_MATCH _SB_MAKEMASK(4, S_SCD_TREVT_ADDR_MATCH)
554#define V_SCD_TREVT_ADDR_MATCH(x) _SB_MAKEVALUE(x,S_SCD_TREVT_ADDR_MATCH) 554#define V_SCD_TREVT_ADDR_MATCH(x) _SB_MAKEVALUE(x, S_SCD_TREVT_ADDR_MATCH)
555#define G_SCD_TREVT_ADDR_MATCH(x) _SB_GETVALUE(x,S_SCD_TREVT_ADDR_MATCH,M_SCD_TREVT_ADDR_MATCH) 555#define G_SCD_TREVT_ADDR_MATCH(x) _SB_GETVALUE(x, S_SCD_TREVT_ADDR_MATCH, M_SCD_TREVT_ADDR_MATCH)
556 556
557#define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4) 557#define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4)
558#define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5) 558#define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5)
@@ -563,48 +563,48 @@
563#define M_SCD_TREVT_READ _SB_MAKEMASK1(11) 563#define M_SCD_TREVT_READ _SB_MAKEMASK1(11)
564 564
565#define S_SCD_TREVT_REQID 12 565#define S_SCD_TREVT_REQID 12
566#define M_SCD_TREVT_REQID _SB_MAKEMASK(4,S_SCD_TREVT_REQID) 566#define M_SCD_TREVT_REQID _SB_MAKEMASK(4, S_SCD_TREVT_REQID)
567#define V_SCD_TREVT_REQID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_REQID) 567#define V_SCD_TREVT_REQID(x) _SB_MAKEVALUE(x, S_SCD_TREVT_REQID)
568#define G_SCD_TREVT_REQID(x) _SB_GETVALUE(x,S_SCD_TREVT_REQID,M_SCD_TREVT_REQID) 568#define G_SCD_TREVT_REQID(x) _SB_GETVALUE(x, S_SCD_TREVT_REQID, M_SCD_TREVT_REQID)
569 569
570#define S_SCD_TREVT_RESPID 16 570#define S_SCD_TREVT_RESPID 16
571#define M_SCD_TREVT_RESPID _SB_MAKEMASK(4,S_SCD_TREVT_RESPID) 571#define M_SCD_TREVT_RESPID _SB_MAKEMASK(4, S_SCD_TREVT_RESPID)
572#define V_SCD_TREVT_RESPID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_RESPID) 572#define V_SCD_TREVT_RESPID(x) _SB_MAKEVALUE(x, S_SCD_TREVT_RESPID)
573#define G_SCD_TREVT_RESPID(x) _SB_GETVALUE(x,S_SCD_TREVT_RESPID,M_SCD_TREVT_RESPID) 573#define G_SCD_TREVT_RESPID(x) _SB_GETVALUE(x, S_SCD_TREVT_RESPID, M_SCD_TREVT_RESPID)
574 574
575#define S_SCD_TREVT_DATAID 20 575#define S_SCD_TREVT_DATAID 20
576#define M_SCD_TREVT_DATAID _SB_MAKEMASK(4,S_SCD_TREVT_DATAID) 576#define M_SCD_TREVT_DATAID _SB_MAKEMASK(4, S_SCD_TREVT_DATAID)
577#define V_SCD_TREVT_DATAID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_DATAID) 577#define V_SCD_TREVT_DATAID(x) _SB_MAKEVALUE(x, S_SCD_TREVT_DATAID)
578#define G_SCD_TREVT_DATAID(x) _SB_GETVALUE(x,S_SCD_TREVT_DATAID,M_SCD_TREVT_DATID) 578#define G_SCD_TREVT_DATAID(x) _SB_GETVALUE(x, S_SCD_TREVT_DATAID, M_SCD_TREVT_DATID)
579 579
580#define S_SCD_TREVT_COUNT 24 580#define S_SCD_TREVT_COUNT 24
581#define M_SCD_TREVT_COUNT _SB_MAKEMASK(8,S_SCD_TREVT_COUNT) 581#define M_SCD_TREVT_COUNT _SB_MAKEMASK(8, S_SCD_TREVT_COUNT)
582#define V_SCD_TREVT_COUNT(x) _SB_MAKEVALUE(x,S_SCD_TREVT_COUNT) 582#define V_SCD_TREVT_COUNT(x) _SB_MAKEVALUE(x, S_SCD_TREVT_COUNT)
583#define G_SCD_TREVT_COUNT(x) _SB_GETVALUE(x,S_SCD_TREVT_COUNT,M_SCD_TREVT_COUNT) 583#define G_SCD_TREVT_COUNT(x) _SB_GETVALUE(x, S_SCD_TREVT_COUNT, M_SCD_TREVT_COUNT)
584 584
585/* 585/*
586 * Trace Sequence registers 586 * Trace Sequence registers
587 */ 587 */
588 588
589#define S_SCD_TRSEQ_EVENT4 0 589#define S_SCD_TRSEQ_EVENT4 0
590#define M_SCD_TRSEQ_EVENT4 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT4) 590#define M_SCD_TRSEQ_EVENT4 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT4)
591#define V_SCD_TRSEQ_EVENT4(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT4) 591#define V_SCD_TRSEQ_EVENT4(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT4)
592#define G_SCD_TRSEQ_EVENT4(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT4,M_SCD_TRSEQ_EVENT4) 592#define G_SCD_TRSEQ_EVENT4(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT4, M_SCD_TRSEQ_EVENT4)
593 593
594#define S_SCD_TRSEQ_EVENT3 4 594#define S_SCD_TRSEQ_EVENT3 4
595#define M_SCD_TRSEQ_EVENT3 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT3) 595#define M_SCD_TRSEQ_EVENT3 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT3)
596#define V_SCD_TRSEQ_EVENT3(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT3) 596#define V_SCD_TRSEQ_EVENT3(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT3)
597#define G_SCD_TRSEQ_EVENT3(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT3,M_SCD_TRSEQ_EVENT3) 597#define G_SCD_TRSEQ_EVENT3(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT3, M_SCD_TRSEQ_EVENT3)
598 598
599#define S_SCD_TRSEQ_EVENT2 8 599#define S_SCD_TRSEQ_EVENT2 8
600#define M_SCD_TRSEQ_EVENT2 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT2) 600#define M_SCD_TRSEQ_EVENT2 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT2)
601#define V_SCD_TRSEQ_EVENT2(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT2) 601#define V_SCD_TRSEQ_EVENT2(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT2)
602#define G_SCD_TRSEQ_EVENT2(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT2,M_SCD_TRSEQ_EVENT2) 602#define G_SCD_TRSEQ_EVENT2(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT2, M_SCD_TRSEQ_EVENT2)
603 603
604#define S_SCD_TRSEQ_EVENT1 12 604#define S_SCD_TRSEQ_EVENT1 12
605#define M_SCD_TRSEQ_EVENT1 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT1) 605#define M_SCD_TRSEQ_EVENT1 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT1)
606#define V_SCD_TRSEQ_EVENT1(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT1) 606#define V_SCD_TRSEQ_EVENT1(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT1)
607#define G_SCD_TRSEQ_EVENT1(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT1,M_SCD_TRSEQ_EVENT1) 607#define G_SCD_TRSEQ_EVENT1(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT1, M_SCD_TRSEQ_EVENT1)
608 608
609#define K_SCD_TRSEQ_E0 0 609#define K_SCD_TRSEQ_E0 0
610#define K_SCD_TRSEQ_E1 1 610#define K_SCD_TRSEQ_E1 1
@@ -629,9 +629,9 @@
629 V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED)) 629 V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED))
630 630
631#define S_SCD_TRSEQ_FUNCTION 16 631#define S_SCD_TRSEQ_FUNCTION 16
632#define M_SCD_TRSEQ_FUNCTION _SB_MAKEMASK(4,S_SCD_TRSEQ_FUNCTION) 632#define M_SCD_TRSEQ_FUNCTION _SB_MAKEMASK(4, S_SCD_TRSEQ_FUNCTION)
633#define V_SCD_TRSEQ_FUNCTION(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_FUNCTION) 633#define V_SCD_TRSEQ_FUNCTION(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_FUNCTION)
634#define G_SCD_TRSEQ_FUNCTION(x) _SB_GETVALUE(x,S_SCD_TRSEQ_FUNCTION,M_SCD_TRSEQ_FUNCTION) 634#define G_SCD_TRSEQ_FUNCTION(x) _SB_GETVALUE(x, S_SCD_TRSEQ_FUNCTION, M_SCD_TRSEQ_FUNCTION)
635 635
636#define K_SCD_TRSEQ_FUNC_NOP 0 636#define K_SCD_TRSEQ_FUNC_NOP 0
637#define K_SCD_TRSEQ_FUNC_START 1 637#define K_SCD_TRSEQ_FUNC_START 1
diff --git a/include/asm-mips/sibyte/sb1250_smbus.h b/include/asm-mips/sibyte/sb1250_smbus.h
index 279a912213cd..04769923cf1e 100644
--- a/include/asm-mips/sibyte/sb1250_smbus.h
+++ b/include/asm-mips/sibyte/sb1250_smbus.h
@@ -41,16 +41,16 @@
41 */ 41 */
42 42
43#define S_SMB_FREQ_DIV 0 43#define S_SMB_FREQ_DIV 0
44#define M_SMB_FREQ_DIV _SB_MAKEMASK(13,S_SMB_FREQ_DIV) 44#define M_SMB_FREQ_DIV _SB_MAKEMASK(13, S_SMB_FREQ_DIV)
45#define V_SMB_FREQ_DIV(x) _SB_MAKEVALUE(x,S_SMB_FREQ_DIV) 45#define V_SMB_FREQ_DIV(x) _SB_MAKEVALUE(x, S_SMB_FREQ_DIV)
46 46
47#define K_SMB_FREQ_400KHZ 0x1F 47#define K_SMB_FREQ_400KHZ 0x1F
48#define K_SMB_FREQ_100KHZ 0x7D 48#define K_SMB_FREQ_100KHZ 0x7D
49#define K_SMB_FREQ_10KHZ 1250 49#define K_SMB_FREQ_10KHZ 1250
50 50
51#define S_SMB_CMD 0 51#define S_SMB_CMD 0
52#define M_SMB_CMD _SB_MAKEMASK(8,S_SMB_CMD) 52#define M_SMB_CMD _SB_MAKEMASK(8, S_SMB_CMD)
53#define V_SMB_CMD(x) _SB_MAKEVALUE(x,S_SMB_CMD) 53#define V_SMB_CMD(x) _SB_MAKEVALUE(x, S_SMB_CMD)
54 54
55/* 55/*
56 * SMBus control register (Table 14-4) 56 * SMBus control register (Table 14-4)
@@ -61,7 +61,7 @@
61 61
62#define S_SMB_DATA_OUT 4 62#define S_SMB_DATA_OUT 4
63#define M_SMB_DATA_OUT _SB_MAKEMASK1(S_SMB_DATA_OUT) 63#define M_SMB_DATA_OUT _SB_MAKEMASK1(S_SMB_DATA_OUT)
64#define V_SMB_DATA_OUT(x) _SB_MAKEVALUE(x,S_SMB_DATA_OUT) 64#define V_SMB_DATA_OUT(x) _SB_MAKEVALUE(x, S_SMB_DATA_OUT)
65 65
66#define M_SMB_DATA_DIR _SB_MAKEMASK1(5) 66#define M_SMB_DATA_DIR _SB_MAKEMASK1(5)
67#define M_SMB_DATA_DIR_OUTPUT M_SMB_DATA_DIR 67#define M_SMB_DATA_DIR_OUTPUT M_SMB_DATA_DIR
@@ -79,35 +79,35 @@
79#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 79#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
80#define S_SMB_SCL_IN 5 80#define S_SMB_SCL_IN 5
81#define M_SMB_SCL_IN _SB_MAKEMASK1(S_SMB_SCL_IN) 81#define M_SMB_SCL_IN _SB_MAKEMASK1(S_SMB_SCL_IN)
82#define V_SMB_SCL_IN(x) _SB_MAKEVALUE(x,S_SMB_SCL_IN) 82#define V_SMB_SCL_IN(x) _SB_MAKEVALUE(x, S_SMB_SCL_IN)
83#define G_SMB_SCL_IN(x) _SB_GETVALUE(x,S_SMB_SCL_IN,M_SMB_SCL_IN) 83#define G_SMB_SCL_IN(x) _SB_GETVALUE(x, S_SMB_SCL_IN, M_SMB_SCL_IN)
84#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 84#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
85 85
86#define S_SMB_REF 6 86#define S_SMB_REF 6
87#define M_SMB_REF _SB_MAKEMASK1(S_SMB_REF) 87#define M_SMB_REF _SB_MAKEMASK1(S_SMB_REF)
88#define V_SMB_REF(x) _SB_MAKEVALUE(x,S_SMB_REF) 88#define V_SMB_REF(x) _SB_MAKEVALUE(x, S_SMB_REF)
89#define G_SMB_REF(x) _SB_GETVALUE(x,S_SMB_REF,M_SMB_REF) 89#define G_SMB_REF(x) _SB_GETVALUE(x, S_SMB_REF, M_SMB_REF)
90 90
91#define S_SMB_DATA_IN 7 91#define S_SMB_DATA_IN 7
92#define M_SMB_DATA_IN _SB_MAKEMASK1(S_SMB_DATA_IN) 92#define M_SMB_DATA_IN _SB_MAKEMASK1(S_SMB_DATA_IN)
93#define V_SMB_DATA_IN(x) _SB_MAKEVALUE(x,S_SMB_DATA_IN) 93#define V_SMB_DATA_IN(x) _SB_MAKEVALUE(x, S_SMB_DATA_IN)
94#define G_SMB_DATA_IN(x) _SB_GETVALUE(x,S_SMB_DATA_IN,M_SMB_DATA_IN) 94#define G_SMB_DATA_IN(x) _SB_GETVALUE(x, S_SMB_DATA_IN, M_SMB_DATA_IN)
95 95
96/* 96/*
97 * SMBus Start/Command registers (Table 14-9) 97 * SMBus Start/Command registers (Table 14-9)
98 */ 98 */
99 99
100#define S_SMB_ADDR 0 100#define S_SMB_ADDR 0
101#define M_SMB_ADDR _SB_MAKEMASK(7,S_SMB_ADDR) 101#define M_SMB_ADDR _SB_MAKEMASK(7, S_SMB_ADDR)
102#define V_SMB_ADDR(x) _SB_MAKEVALUE(x,S_SMB_ADDR) 102#define V_SMB_ADDR(x) _SB_MAKEVALUE(x, S_SMB_ADDR)
103#define G_SMB_ADDR(x) _SB_GETVALUE(x,S_SMB_ADDR,M_SMB_ADDR) 103#define G_SMB_ADDR(x) _SB_GETVALUE(x, S_SMB_ADDR, M_SMB_ADDR)
104 104
105#define M_SMB_QDATA _SB_MAKEMASK1(7) 105#define M_SMB_QDATA _SB_MAKEMASK1(7)
106 106
107#define S_SMB_TT 8 107#define S_SMB_TT 8
108#define M_SMB_TT _SB_MAKEMASK(3,S_SMB_TT) 108#define M_SMB_TT _SB_MAKEMASK(3, S_SMB_TT)
109#define V_SMB_TT(x) _SB_MAKEVALUE(x,S_SMB_TT) 109#define V_SMB_TT(x) _SB_MAKEVALUE(x, S_SMB_TT)
110#define G_SMB_TT(x) _SB_GETVALUE(x,S_SMB_TT,M_SMB_TT) 110#define G_SMB_TT(x) _SB_GETVALUE(x, S_SMB_TT, M_SMB_TT)
111 111
112#define K_SMB_TT_WR1BYTE 0 112#define K_SMB_TT_WR1BYTE 0
113#define K_SMB_TT_WR2BYTE 1 113#define K_SMB_TT_WR2BYTE 1
@@ -134,12 +134,12 @@
134 */ 134 */
135 135
136#define S_SMB_LB 0 136#define S_SMB_LB 0
137#define M_SMB_LB _SB_MAKEMASK(8,S_SMB_LB) 137#define M_SMB_LB _SB_MAKEMASK(8, S_SMB_LB)
138#define V_SMB_LB(x) _SB_MAKEVALUE(x,S_SMB_LB) 138#define V_SMB_LB(x) _SB_MAKEVALUE(x, S_SMB_LB)
139 139
140#define S_SMB_MB 8 140#define S_SMB_MB 8
141#define M_SMB_MB _SB_MAKEMASK(8,S_SMB_MB) 141#define M_SMB_MB _SB_MAKEMASK(8, S_SMB_MB)
142#define V_SMB_MB(x) _SB_MAKEVALUE(x,S_SMB_MB) 142#define V_SMB_MB(x) _SB_MAKEVALUE(x, S_SMB_MB)
143 143
144 144
145/* 145/*
@@ -147,22 +147,22 @@
147 */ 147 */
148 148
149#define S_SPEC_PEC 0 149#define S_SPEC_PEC 0
150#define M_SPEC_PEC _SB_MAKEMASK(8,S_SPEC_PEC) 150#define M_SPEC_PEC _SB_MAKEMASK(8, S_SPEC_PEC)
151#define V_SPEC_MB(x) _SB_MAKEVALUE(x,S_SPEC_PEC) 151#define V_SPEC_MB(x) _SB_MAKEVALUE(x, S_SPEC_PEC)
152 152
153 153
154#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 154#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
155 155
156#define S_SMB_CMDH 8 156#define S_SMB_CMDH 8
157#define M_SMB_CMDH _SB_MAKEMASK(8,S_SMB_CMDH) 157#define M_SMB_CMDH _SB_MAKEMASK(8, S_SMB_CMDH)
158#define V_SMB_CMDH(x) _SB_MAKEVALUE(x,S_SMB_CMDH) 158#define V_SMB_CMDH(x) _SB_MAKEVALUE(x, S_SMB_CMDH)
159 159
160#define M_SMB_EXTEND _SB_MAKEMASK1(14) 160#define M_SMB_EXTEND _SB_MAKEMASK1(14)
161 161
162#define S_SMB_DFMT 8 162#define S_SMB_DFMT 8
163#define M_SMB_DFMT _SB_MAKEMASK(3,S_SMB_DFMT) 163#define M_SMB_DFMT _SB_MAKEMASK(3, S_SMB_DFMT)
164#define V_SMB_DFMT(x) _SB_MAKEVALUE(x,S_SMB_DFMT) 164#define V_SMB_DFMT(x) _SB_MAKEVALUE(x, S_SMB_DFMT)
165#define G_SMB_DFMT(x) _SB_GETVALUE(x,S_SMB_DFMT,M_SMB_DFMT) 165#define G_SMB_DFMT(x) _SB_GETVALUE(x, S_SMB_DFMT, M_SMB_DFMT)
166 166
167#define K_SMB_DFMT_1BYTE 0 167#define K_SMB_DFMT_1BYTE 0
168#define K_SMB_DFMT_2BYTE 1 168#define K_SMB_DFMT_2BYTE 1
@@ -183,9 +183,9 @@
183#define V_SMB_DFMT_RESERVED V_SMB_DFMT(K_SMB_DFMT_RESERVED) 183#define V_SMB_DFMT_RESERVED V_SMB_DFMT(K_SMB_DFMT_RESERVED)
184 184
185#define S_SMB_AFMT 11 185#define S_SMB_AFMT 11
186#define M_SMB_AFMT _SB_MAKEMASK(2,S_SMB_AFMT) 186#define M_SMB_AFMT _SB_MAKEMASK(2, S_SMB_AFMT)
187#define V_SMB_AFMT(x) _SB_MAKEVALUE(x,S_SMB_AFMT) 187#define V_SMB_AFMT(x) _SB_MAKEVALUE(x, S_SMB_AFMT)
188#define G_SMB_AFMT(x) _SB_GETVALUE(x,S_SMB_AFMT,M_SMB_AFMT) 188#define G_SMB_AFMT(x) _SB_GETVALUE(x, S_SMB_AFMT, M_SMB_AFMT)
189 189
190#define K_SMB_AFMT_NONE 0 190#define K_SMB_AFMT_NONE 0
191#define K_SMB_AFMT_ADDR 1 191#define K_SMB_AFMT_ADDR 1
diff --git a/include/asm-mips/sibyte/sb1250_syncser.h b/include/asm-mips/sibyte/sb1250_syncser.h
index dd154ac505d8..d4b8558e0bf1 100644
--- a/include/asm-mips/sibyte/sb1250_syncser.h
+++ b/include/asm-mips/sibyte/sb1250_syncser.h
@@ -43,8 +43,8 @@
43#define M_SYNCSER_MSB_FIRST _SB_MAKEMASK1(1) 43#define M_SYNCSER_MSB_FIRST _SB_MAKEMASK1(1)
44 44
45#define S_SYNCSER_FLAG_NUM 2 45#define S_SYNCSER_FLAG_NUM 2
46#define M_SYNCSER_FLAG_NUM _SB_MAKEMASK(4,S_SYNCSER_FLAG_NUM) 46#define M_SYNCSER_FLAG_NUM _SB_MAKEMASK(4, S_SYNCSER_FLAG_NUM)
47#define V_SYNCSER_FLAG_NUM _SB_MAKEVALUE(x,S_SYNCSER_FLAG_NUM) 47#define V_SYNCSER_FLAG_NUM _SB_MAKEVALUE(x, S_SYNCSER_FLAG_NUM)
48 48
49#define M_SYNCSER_FLAG_EN _SB_MAKEMASK1(6) 49#define M_SYNCSER_FLAG_EN _SB_MAKEMASK1(6)
50#define M_SYNCSER_HDLC_EN _SB_MAKEMASK1(7) 50#define M_SYNCSER_HDLC_EN _SB_MAKEMASK1(7)
@@ -59,8 +59,8 @@
59#define M_SYNCSER_RXCLK_EXT _SB_MAKEMASK1(1) 59#define M_SYNCSER_RXCLK_EXT _SB_MAKEMASK1(1)
60 60
61#define S_SYNCSER_RXSYNC_DLY 2 61#define S_SYNCSER_RXSYNC_DLY 2
62#define M_SYNCSER_RXSYNC_DLY _SB_MAKEMASK(2,S_SYNCSER_RXSYNC_DLY) 62#define M_SYNCSER_RXSYNC_DLY _SB_MAKEMASK(2, S_SYNCSER_RXSYNC_DLY)
63#define V_SYNCSER_RXSYNC_DLY(x) _SB_MAKEVALUE(x,S_SYNCSER_RXSYNC_DLY) 63#define V_SYNCSER_RXSYNC_DLY(x) _SB_MAKEVALUE(x, S_SYNCSER_RXSYNC_DLY)
64 64
65#define M_SYNCSER_RXSYNC_LOW _SB_MAKEMASK1(4) 65#define M_SYNCSER_RXSYNC_LOW _SB_MAKEMASK1(4)
66#define M_SYNCSER_RXSTRB_LOW _SB_MAKEMASK1(5) 66#define M_SYNCSER_RXSTRB_LOW _SB_MAKEMASK1(5)
@@ -72,8 +72,8 @@
72#define M_SYNCSER_TXCLK_EXT _SB_MAKEMASK1(9) 72#define M_SYNCSER_TXCLK_EXT _SB_MAKEMASK1(9)
73 73
74#define S_SYNCSER_TXSYNC_DLY 10 74#define S_SYNCSER_TXSYNC_DLY 10
75#define M_SYNCSER_TXSYNC_DLY _SB_MAKEMASK(2,S_SYNCSER_TXSYNC_DLY) 75#define M_SYNCSER_TXSYNC_DLY _SB_MAKEMASK(2, S_SYNCSER_TXSYNC_DLY)
76#define V_SYNCSER_TXSYNC_DLY(x) _SB_MAKEVALUE(x,S_SYNCSER_TXSYNC_DLY) 76#define V_SYNCSER_TXSYNC_DLY(x) _SB_MAKEVALUE(x, S_SYNCSER_TXSYNC_DLY)
77 77
78#define M_SYNCSER_TXSYNC_LOW _SB_MAKEMASK1(12) 78#define M_SYNCSER_TXSYNC_LOW _SB_MAKEMASK1(12)
79#define M_SYNCSER_TXSTRB_LOW _SB_MAKEMASK1(13) 79#define M_SYNCSER_TXSTRB_LOW _SB_MAKEMASK1(13)
@@ -137,8 +137,8 @@
137#define M_SYNCSER_SEQ_BYTE _SB_MAKEMASK1(1) 137#define M_SYNCSER_SEQ_BYTE _SB_MAKEMASK1(1)
138 138
139#define S_SYNCSER_SEQ_COUNT 2 139#define S_SYNCSER_SEQ_COUNT 2
140#define M_SYNCSER_SEQ_COUNT _SB_MAKEMASK(4,S_SYNCSER_SEQ_COUNT) 140#define M_SYNCSER_SEQ_COUNT _SB_MAKEMASK(4, S_SYNCSER_SEQ_COUNT)
141#define V_SYNCSER_SEQ_COUNT(x) _SB_MAKEVALUE(x,S_SYNCSER_SEQ_COUNT) 141#define V_SYNCSER_SEQ_COUNT(x) _SB_MAKEVALUE(x, S_SYNCSER_SEQ_COUNT)
142 142
143#define M_SYNCSER_SEQ_ENABLE _SB_MAKEMASK1(6) 143#define M_SYNCSER_SEQ_ENABLE _SB_MAKEMASK1(6)
144#define M_SYNCSER_SEQ_STROBE _SB_MAKEMASK1(7) 144#define M_SYNCSER_SEQ_STROBE _SB_MAKEMASK1(7)
diff --git a/include/asm-mips/sibyte/sb1250_uart.h b/include/asm-mips/sibyte/sb1250_uart.h
index cf74fedcbef1..d835bf280140 100644
--- a/include/asm-mips/sibyte/sb1250_uart.h
+++ b/include/asm-mips/sibyte/sb1250_uart.h
@@ -46,8 +46,8 @@
46 */ 46 */
47 47
48#define S_DUART_BITS_PER_CHAR 0 48#define S_DUART_BITS_PER_CHAR 0
49#define M_DUART_BITS_PER_CHAR _SB_MAKEMASK(2,S_DUART_BITS_PER_CHAR) 49#define M_DUART_BITS_PER_CHAR _SB_MAKEMASK(2, S_DUART_BITS_PER_CHAR)
50#define V_DUART_BITS_PER_CHAR(x) _SB_MAKEVALUE(x,S_DUART_BITS_PER_CHAR) 50#define V_DUART_BITS_PER_CHAR(x) _SB_MAKEVALUE(x, S_DUART_BITS_PER_CHAR)
51 51
52#define K_DUART_BITS_PER_CHAR_RSV0 0 52#define K_DUART_BITS_PER_CHAR_RSV0 0
53#define K_DUART_BITS_PER_CHAR_RSV1 1 53#define K_DUART_BITS_PER_CHAR_RSV1 1
@@ -64,8 +64,8 @@
64#define M_DUART_PARITY_TYPE_ODD _SB_MAKEMASK1(2) 64#define M_DUART_PARITY_TYPE_ODD _SB_MAKEMASK1(2)
65 65
66#define S_DUART_PARITY_MODE 3 66#define S_DUART_PARITY_MODE 3
67#define M_DUART_PARITY_MODE _SB_MAKEMASK(2,S_DUART_PARITY_MODE) 67#define M_DUART_PARITY_MODE _SB_MAKEMASK(2, S_DUART_PARITY_MODE)
68#define V_DUART_PARITY_MODE(x) _SB_MAKEVALUE(x,S_DUART_PARITY_MODE) 68#define V_DUART_PARITY_MODE(x) _SB_MAKEVALUE(x, S_DUART_PARITY_MODE)
69 69
70#define K_DUART_PARITY_MODE_ADD 0 70#define K_DUART_PARITY_MODE_ADD 0
71#define K_DUART_PARITY_MODE_ADD_FIXED 1 71#define K_DUART_PARITY_MODE_ADD_FIXED 1
@@ -89,7 +89,7 @@
89 * Register: DUART_MODE_REG_2_B 89 * Register: DUART_MODE_REG_2_B
90 */ 90 */
91 91
92#define M_DUART_MODE_RESERVED1 _SB_MAKEMASK(3,0) /* ignored */ 92#define M_DUART_MODE_RESERVED1 _SB_MAKEMASK(3, 0) /* ignored */
93 93
94#define M_DUART_STOP_BIT_LEN_2 _SB_MAKEMASK1(3) 94#define M_DUART_STOP_BIT_LEN_2 _SB_MAKEMASK1(3)
95#define M_DUART_STOP_BIT_LEN_1 0 95#define M_DUART_STOP_BIT_LEN_1 0
@@ -100,8 +100,8 @@
100#define M_DUART_MODE_RESERVED2 _SB_MAKEMASK1(5) /* must be zero */ 100#define M_DUART_MODE_RESERVED2 _SB_MAKEMASK1(5) /* must be zero */
101 101
102#define S_DUART_CHAN_MODE 6 102#define S_DUART_CHAN_MODE 6
103#define M_DUART_CHAN_MODE _SB_MAKEMASK(2,S_DUART_CHAN_MODE) 103#define M_DUART_CHAN_MODE _SB_MAKEMASK(2, S_DUART_CHAN_MODE)
104#define V_DUART_CHAN_MODE(x) _SB_MAKEVALUE(x,S_DUART_CHAN_MODE) 104#define V_DUART_CHAN_MODE(x) _SB_MAKEVALUE(x, S_DUART_CHAN_MODE)
105 105
106#define K_DUART_CHAN_MODE_NORMAL 0 106#define K_DUART_CHAN_MODE_NORMAL 0
107#define K_DUART_CHAN_MODE_LCL_LOOP 2 107#define K_DUART_CHAN_MODE_LCL_LOOP 2
@@ -123,8 +123,8 @@
123#define M_DUART_TX_DIS _SB_MAKEMASK1(3) 123#define M_DUART_TX_DIS _SB_MAKEMASK1(3)
124 124
125#define S_DUART_MISC_CMD 4 125#define S_DUART_MISC_CMD 4
126#define M_DUART_MISC_CMD _SB_MAKEMASK(3,S_DUART_MISC_CMD) 126#define M_DUART_MISC_CMD _SB_MAKEMASK(3, S_DUART_MISC_CMD)
127#define V_DUART_MISC_CMD(x) _SB_MAKEVALUE(x,S_DUART_MISC_CMD) 127#define V_DUART_MISC_CMD(x) _SB_MAKEVALUE(x, S_DUART_MISC_CMD)
128 128
129#define K_DUART_MISC_CMD_NOACTION0 0 129#define K_DUART_MISC_CMD_NOACTION0 0
130#define K_DUART_MISC_CMD_NOACTION1 1 130#define K_DUART_MISC_CMD_NOACTION1 1
@@ -168,7 +168,7 @@
168 * Register: DUART_CLK_SEL_B 168 * Register: DUART_CLK_SEL_B
169 */ 169 */
170 170
171#define M_DUART_CLK_COUNTER _SB_MAKEMASK(12,0) 171#define M_DUART_CLK_COUNTER _SB_MAKEMASK(12, 0)
172#define V_DUART_BAUD_RATE(x) (100000000/((x)*20)-1) 172#define V_DUART_BAUD_RATE(x) (100000000/((x)*20)-1)
173 173
174/* 174/*
@@ -179,8 +179,8 @@
179 * Register: DUART_TX_HOLD_B 179 * Register: DUART_TX_HOLD_B
180 */ 180 */
181 181
182#define M_DUART_RX_DATA _SB_MAKEMASK(8,0) 182#define M_DUART_RX_DATA _SB_MAKEMASK(8, 0)
183#define M_DUART_TX_DATA _SB_MAKEMASK(8,0) 183#define M_DUART_TX_DATA _SB_MAKEMASK(8, 0)
184 184
185/* 185/*
186 * DUART Input Port Register (Table 10-10) 186 * DUART Input Port Register (Table 10-10)
@@ -202,10 +202,10 @@
202 */ 202 */
203 203
204#define S_DUART_IN_PIN_VAL 0 204#define S_DUART_IN_PIN_VAL 0
205#define M_DUART_IN_PIN_VAL _SB_MAKEMASK(4,S_DUART_IN_PIN_VAL) 205#define M_DUART_IN_PIN_VAL _SB_MAKEMASK(4, S_DUART_IN_PIN_VAL)
206 206
207#define S_DUART_IN_PIN_CHNG 4 207#define S_DUART_IN_PIN_CHNG 4
208#define M_DUART_IN_PIN_CHNG _SB_MAKEMASK(4,S_DUART_IN_PIN_CHNG) 208#define M_DUART_IN_PIN_CHNG _SB_MAKEMASK(4, S_DUART_IN_PIN_CHNG)
209 209
210 210
211/* 211/*
@@ -217,7 +217,7 @@
217#define M_DUART_OPC2_SEL _SB_MAKEMASK1(1) 217#define M_DUART_OPC2_SEL _SB_MAKEMASK1(1)
218#define M_DUART_OPCR_RESERVED1 _SB_MAKEMASK1(2) /* must be zero */ 218#define M_DUART_OPCR_RESERVED1 _SB_MAKEMASK1(2) /* must be zero */
219#define M_DUART_OPC3_SEL _SB_MAKEMASK1(3) 219#define M_DUART_OPC3_SEL _SB_MAKEMASK1(3)
220#define M_DUART_OPCR_RESERVED2 _SB_MAKEMASK(4,4) /* must be zero */ 220#define M_DUART_OPCR_RESERVED2 _SB_MAKEMASK(4, 4) /* must be zero */
221 221
222/* 222/*
223 * DUART Aux Control Register (Table 10-15) 223 * DUART Aux Control Register (Table 10-15)
@@ -228,7 +228,7 @@
228#define M_DUART_IP1_CHNG_ENA _SB_MAKEMASK1(1) 228#define M_DUART_IP1_CHNG_ENA _SB_MAKEMASK1(1)
229#define M_DUART_IP2_CHNG_ENA _SB_MAKEMASK1(2) 229#define M_DUART_IP2_CHNG_ENA _SB_MAKEMASK1(2)
230#define M_DUART_IP3_CHNG_ENA _SB_MAKEMASK1(3) 230#define M_DUART_IP3_CHNG_ENA _SB_MAKEMASK1(3)
231#define M_DUART_ACR_RESERVED _SB_MAKEMASK(4,4) 231#define M_DUART_ACR_RESERVED _SB_MAKEMASK(4, 4)
232 232
233#define M_DUART_CTS_CHNG_ENA _SB_MAKEMASK1(0) 233#define M_DUART_CTS_CHNG_ENA _SB_MAKEMASK1(0)
234#define M_DUART_CIN_CHNG_ENA _SB_MAKEMASK1(2) 234#define M_DUART_CIN_CHNG_ENA _SB_MAKEMASK1(2)
@@ -242,18 +242,18 @@
242 242
243#define S_DUART_ISR_RX_A 1 243#define S_DUART_ISR_RX_A 1
244#define M_DUART_ISR_RX_A _SB_MAKEMASK1(S_DUART_ISR_RX_A) 244#define M_DUART_ISR_RX_A _SB_MAKEMASK1(S_DUART_ISR_RX_A)
245#define V_DUART_ISR_RX_A(x) _SB_MAKEVALUE(x,S_DUART_ISR_RX_A) 245#define V_DUART_ISR_RX_A(x) _SB_MAKEVALUE(x, S_DUART_ISR_RX_A)
246#define G_DUART_ISR_RX_A(x) _SB_GETVALUE(x,S_DUART_ISR_RX_A,M_DUART_ISR_RX_A) 246#define G_DUART_ISR_RX_A(x) _SB_GETVALUE(x, S_DUART_ISR_RX_A, M_DUART_ISR_RX_A)
247 247
248#define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2) 248#define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2)
249#define M_DUART_ISR_IN_A _SB_MAKEMASK1(3) 249#define M_DUART_ISR_IN_A _SB_MAKEMASK1(3)
250#define M_DUART_ISR_ALL_A _SB_MAKEMASK(4,0) 250#define M_DUART_ISR_ALL_A _SB_MAKEMASK(4, 0)
251 251
252#define M_DUART_ISR_TX_B _SB_MAKEMASK1(4) 252#define M_DUART_ISR_TX_B _SB_MAKEMASK1(4)
253#define M_DUART_ISR_RX_B _SB_MAKEMASK1(5) 253#define M_DUART_ISR_RX_B _SB_MAKEMASK1(5)
254#define M_DUART_ISR_BRK_B _SB_MAKEMASK1(6) 254#define M_DUART_ISR_BRK_B _SB_MAKEMASK1(6)
255#define M_DUART_ISR_IN_B _SB_MAKEMASK1(7) 255#define M_DUART_ISR_IN_B _SB_MAKEMASK1(7)
256#define M_DUART_ISR_ALL_B _SB_MAKEMASK(4,4) 256#define M_DUART_ISR_ALL_B _SB_MAKEMASK(4, 4)
257 257
258/* 258/*
259 * DUART Channel A Interrupt Status Register (Table 10-17) 259 * DUART Channel A Interrupt Status Register (Table 10-17)
@@ -266,8 +266,8 @@
266#define M_DUART_ISR_RX _SB_MAKEMASK1(1) 266#define M_DUART_ISR_RX _SB_MAKEMASK1(1)
267#define M_DUART_ISR_BRK _SB_MAKEMASK1(2) 267#define M_DUART_ISR_BRK _SB_MAKEMASK1(2)
268#define M_DUART_ISR_IN _SB_MAKEMASK1(3) 268#define M_DUART_ISR_IN _SB_MAKEMASK1(3)
269#define M_DUART_ISR_ALL _SB_MAKEMASK(4,0) 269#define M_DUART_ISR_ALL _SB_MAKEMASK(4, 0)
270#define M_DUART_ISR_RESERVED _SB_MAKEMASK(4,4) 270#define M_DUART_ISR_RESERVED _SB_MAKEMASK(4, 4)
271 271
272/* 272/*
273 * DUART Interrupt Mask Register (Table 10-19) 273 * DUART Interrupt Mask Register (Table 10-19)
@@ -278,13 +278,13 @@
278#define M_DUART_IMR_RX_A _SB_MAKEMASK1(1) 278#define M_DUART_IMR_RX_A _SB_MAKEMASK1(1)
279#define M_DUART_IMR_BRK_A _SB_MAKEMASK1(2) 279#define M_DUART_IMR_BRK_A _SB_MAKEMASK1(2)
280#define M_DUART_IMR_IN_A _SB_MAKEMASK1(3) 280#define M_DUART_IMR_IN_A _SB_MAKEMASK1(3)
281#define M_DUART_IMR_ALL_A _SB_MAKEMASK(4,0) 281#define M_DUART_IMR_ALL_A _SB_MAKEMASK(4, 0)
282 282
283#define M_DUART_IMR_TX_B _SB_MAKEMASK1(4) 283#define M_DUART_IMR_TX_B _SB_MAKEMASK1(4)
284#define M_DUART_IMR_RX_B _SB_MAKEMASK1(5) 284#define M_DUART_IMR_RX_B _SB_MAKEMASK1(5)
285#define M_DUART_IMR_BRK_B _SB_MAKEMASK1(6) 285#define M_DUART_IMR_BRK_B _SB_MAKEMASK1(6)
286#define M_DUART_IMR_IN_B _SB_MAKEMASK1(7) 286#define M_DUART_IMR_IN_B _SB_MAKEMASK1(7)
287#define M_DUART_IMR_ALL_B _SB_MAKEMASK(4,4) 287#define M_DUART_IMR_ALL_B _SB_MAKEMASK(4, 4)
288 288
289/* 289/*
290 * DUART Channel A Interrupt Mask Register (Table 10-20) 290 * DUART Channel A Interrupt Mask Register (Table 10-20)
@@ -297,8 +297,8 @@
297#define M_DUART_IMR_RX _SB_MAKEMASK1(1) 297#define M_DUART_IMR_RX _SB_MAKEMASK1(1)
298#define M_DUART_IMR_BRK _SB_MAKEMASK1(2) 298#define M_DUART_IMR_BRK _SB_MAKEMASK1(2)
299#define M_DUART_IMR_IN _SB_MAKEMASK1(3) 299#define M_DUART_IMR_IN _SB_MAKEMASK1(3)
300#define M_DUART_IMR_ALL _SB_MAKEMASK(4,0) 300#define M_DUART_IMR_ALL _SB_MAKEMASK(4, 0)
301#define M_DUART_IMR_RESERVED _SB_MAKEMASK(4,4) 301#define M_DUART_IMR_RESERVED _SB_MAKEMASK(4, 4)
302 302
303 303
304/* 304/*
@@ -310,7 +310,7 @@
310#define M_DUART_SET_OPR1 _SB_MAKEMASK1(1) 310#define M_DUART_SET_OPR1 _SB_MAKEMASK1(1)
311#define M_DUART_SET_OPR2 _SB_MAKEMASK1(2) 311#define M_DUART_SET_OPR2 _SB_MAKEMASK1(2)
312#define M_DUART_SET_OPR3 _SB_MAKEMASK1(3) 312#define M_DUART_SET_OPR3 _SB_MAKEMASK1(3)
313#define M_DUART_OPSR_RESERVED _SB_MAKEMASK(4,4) 313#define M_DUART_OPSR_RESERVED _SB_MAKEMASK(4, 4)
314 314
315/* 315/*
316 * DUART Output Port Clear Register (Table 10-23) 316 * DUART Output Port Clear Register (Table 10-23)
@@ -321,7 +321,7 @@
321#define M_DUART_CLR_OPR1 _SB_MAKEMASK1(1) 321#define M_DUART_CLR_OPR1 _SB_MAKEMASK1(1)
322#define M_DUART_CLR_OPR2 _SB_MAKEMASK1(2) 322#define M_DUART_CLR_OPR2 _SB_MAKEMASK1(2)
323#define M_DUART_CLR_OPR3 _SB_MAKEMASK1(3) 323#define M_DUART_CLR_OPR3 _SB_MAKEMASK1(3)
324#define M_DUART_OPCR_RESERVED _SB_MAKEMASK(4,4) 324#define M_DUART_OPCR_RESERVED _SB_MAKEMASK(4, 4)
325 325
326/* 326/*
327 * DUART Output Port RTS Register (Table 10-24) 327 * DUART Output Port RTS Register (Table 10-24)
@@ -332,7 +332,7 @@
332#define M_DUART_OUT_PIN_SET1 _SB_MAKEMASK1(1) 332#define M_DUART_OUT_PIN_SET1 _SB_MAKEMASK1(1)
333#define M_DUART_OUT_PIN_CLR0 _SB_MAKEMASK1(2) 333#define M_DUART_OUT_PIN_CLR0 _SB_MAKEMASK1(2)
334#define M_DUART_OUT_PIN_CLR1 _SB_MAKEMASK1(3) 334#define M_DUART_OUT_PIN_CLR1 _SB_MAKEMASK1(3)
335#define M_DUART_OPRR_RESERVED _SB_MAKEMASK(4,4) 335#define M_DUART_OPRR_RESERVED _SB_MAKEMASK(4, 4)
336 336
337#define M_DUART_OUT_PIN_SET(chan) \ 337#define M_DUART_OUT_PIN_SET(chan) \
338 (chan == 0 ? M_DUART_OUT_PIN_SET0 : M_DUART_OUT_PIN_SET1) 338 (chan == 0 ? M_DUART_OUT_PIN_SET0 : M_DUART_OUT_PIN_SET1)
@@ -345,14 +345,14 @@
345 */ 345 */
346 346
347#define S_DUART_SIG_FULL _SB_MAKE64(0) 347#define S_DUART_SIG_FULL _SB_MAKE64(0)
348#define M_DUART_SIG_FULL _SB_MAKEMASK(4,S_DUART_SIG_FULL) 348#define M_DUART_SIG_FULL _SB_MAKEMASK(4, S_DUART_SIG_FULL)
349#define V_DUART_SIG_FULL(x) _SB_MAKEVALUE(x,S_DUART_SIG_FULL) 349#define V_DUART_SIG_FULL(x) _SB_MAKEVALUE(x, S_DUART_SIG_FULL)
350#define G_DUART_SIG_FULL(x) _SB_GETVALUE(x,S_DUART_SIG_FULL,M_DUART_SIG_FULL) 350#define G_DUART_SIG_FULL(x) _SB_GETVALUE(x, S_DUART_SIG_FULL, M_DUART_SIG_FULL)
351 351
352#define S_DUART_INT_TIME _SB_MAKE64(4) 352#define S_DUART_INT_TIME _SB_MAKE64(4)
353#define M_DUART_INT_TIME _SB_MAKEMASK(4,S_DUART_INT_TIME) 353#define M_DUART_INT_TIME _SB_MAKEMASK(4, S_DUART_INT_TIME)
354#define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x,S_DUART_INT_TIME) 354#define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x, S_DUART_INT_TIME)
355#define G_DUART_INT_TIME(x) _SB_GETVALUE(x,S_DUART_INT_TIME,M_DUART_INT_TIME) 355#define G_DUART_INT_TIME(x) _SB_GETVALUE(x, S_DUART_INT_TIME, M_DUART_INT_TIME)
356#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 356#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
357 357
358 358
diff --git a/include/asm-mips/siginfo.h b/include/asm-mips/siginfo.h
index 2e32949bd674..96e28f18dad1 100644
--- a/include/asm-mips/siginfo.h
+++ b/include/asm-mips/siginfo.h
@@ -106,8 +106,8 @@ typedef struct siginfo {
106#undef SI_TIMER 106#undef SI_TIMER
107#undef SI_MESGQ 107#undef SI_MESGQ
108#define SI_ASYNCIO -2 /* sent by AIO completion */ 108#define SI_ASYNCIO -2 /* sent by AIO completion */
109#define SI_TIMER __SI_CODE(__SI_TIMER,-3) /* sent by timer expiration */ 109#define SI_TIMER __SI_CODE(__SI_TIMER, -3) /* sent by timer expiration */
110#define SI_MESGQ __SI_CODE(__SI_MESGQ,-4) /* sent by real time mesq state change */ 110#define SI_MESGQ __SI_CODE(__SI_MESGQ, -4) /* sent by real time mesq state change */
111 111
112#ifdef __KERNEL__ 112#ifdef __KERNEL__
113 113
diff --git a/include/asm-mips/sn/addrs.h b/include/asm-mips/sn/addrs.h
index 6aa086868249..fec9bdd34913 100644
--- a/include/asm-mips/sn/addrs.h
+++ b/include/asm-mips/sn/addrs.h
@@ -208,9 +208,9 @@
208 UINT64_CAST(_pa) & NASID_MASK | \ 208 UINT64_CAST(_pa) & NASID_MASK | \
209 UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK | \ 209 UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK | \
210 (_rgn) << 3) 210 (_rgn) << 3)
211#define BDPRT_ENTRY_ADDR(_pa,_rgn) (BDPRT_ENTRY((_pa),(_rgn))) 211#define BDPRT_ENTRY_ADDR(_pa, _rgn) (BDPRT_ENTRY((_pa), (_rgn)))
212#define BDPRT_ENTRY_S(_pa,_rgn,_val) (*(__psunsigned_t *)BDPRT_ENTRY((_pa),(_rgn))=(_val)) 212#define BDPRT_ENTRY_S(_pa, _rgn, _val) (*(__psunsigned_t *)BDPRT_ENTRY((_pa), (_rgn))=(_val))
213#define BDPRT_ENTRY_L(_pa,_rgn) (*(__psunsigned_t *)BDPRT_ENTRY((_pa),(_rgn))) 213#define BDPRT_ENTRY_L(_pa, _rgn) (*(__psunsigned_t *)BDPRT_ENTRY((_pa), (_rgn)))
214 214
215#define BDECC_ENTRY(_pa) ((HSPEC_BASE + \ 215#define BDECC_ENTRY(_pa) ((HSPEC_BASE + \
216 NODE_ADDRSPACE_SIZE / 2) | \ 216 NODE_ADDRSPACE_SIZE / 2) | \
diff --git a/include/asm-mips/sn/klconfig.h b/include/asm-mips/sn/klconfig.h
index 852213d03b72..96cfd2ab1bcd 100644
--- a/include/asm-mips/sn/klconfig.h
+++ b/include/asm-mips/sn/klconfig.h
@@ -405,7 +405,7 @@ typedef struct kl_config_hdr {
405#define KLTYPE(_x) ((_x) & KLTYPE_MASK) 405#define KLTYPE(_x) ((_x) & KLTYPE_MASK)
406#define IS_MIO_PRESENT(l) ((l->brd_type == KLTYPE_BASEIO) && \ 406#define IS_MIO_PRESENT(l) ((l->brd_type == KLTYPE_BASEIO) && \
407 (l->brd_flags & SECOND_NIC_PRESENT)) 407 (l->brd_flags & SECOND_NIC_PRESENT))
408#define IS_MIO_IOC3(l,n) (IS_MIO_PRESENT(l) && (n > 2)) 408#define IS_MIO_IOC3(l, n) (IS_MIO_PRESENT(l) && (n > 2))
409 409
410/* 410/*
411 * board structures 411 * board structures
diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h
index 59334f598b78..fb41a8d76392 100644
--- a/include/asm-mips/stackframe.h
+++ b/include/asm-mips/stackframe.h
@@ -393,11 +393,11 @@
393 * and disable interrupts only for the 393 * and disable interrupts only for the
394 * current TC, using the TCStatus register. 394 * current TC, using the TCStatus register.
395 */ 395 */
396 mfc0 t0,CP0_TCSTATUS 396 mfc0 t0, CP0_TCSTATUS
397 /* Fortunately CU 0 is in the same place in both registers */ 397 /* Fortunately CU 0 is in the same place in both registers */
398 /* Set TCU0, TMX, TKSU (for later inversion) and IXMT */ 398 /* Set TCU0, TMX, TKSU (for later inversion) and IXMT */
399 li t1, ST0_CU0 | 0x08001c00 399 li t1, ST0_CU0 | 0x08001c00
400 or t0,t1 400 or t0, t1
401 /* Clear TKSU, leave IXMT */ 401 /* Clear TKSU, leave IXMT */
402 xori t0, 0x00001800 402 xori t0, 0x00001800
403 mtc0 t0, CP0_TCSTATUS 403 mtc0 t0, CP0_TCSTATUS
@@ -429,11 +429,11 @@
429 * current TC, using the TCStatus register. 429 * current TC, using the TCStatus register.
430 */ 430 */
431 _ehb 431 _ehb
432 mfc0 t0,CP0_TCSTATUS 432 mfc0 t0, CP0_TCSTATUS
433 /* Fortunately CU 0 is in the same place in both registers */ 433 /* Fortunately CU 0 is in the same place in both registers */
434 /* Set TCU0, TKSU (for later inversion) and IXMT */ 434 /* Set TCU0, TKSU (for later inversion) and IXMT */
435 li t1, ST0_CU0 | 0x08001c00 435 li t1, ST0_CU0 | 0x08001c00
436 or t0,t1 436 or t0, t1
437 /* Clear TKSU *and* IXMT */ 437 /* Clear TKSU *and* IXMT */
438 xori t0, 0x00001c00 438 xori t0, 0x00001c00
439 mtc0 t0, CP0_TCSTATUS 439 mtc0 t0, CP0_TCSTATUS
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
index 862f161e88b6..90e4b403f531 100644
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -62,7 +62,7 @@ do { \
62#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0) 62#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0)
63#endif 63#endif
64 64
65#define switch_to(prev,next,last) \ 65#define switch_to(prev, next, last) \
66do { \ 66do { \
67 __mips_mt_fpaff_switch_to(prev); \ 67 __mips_mt_fpaff_switch_to(prev); \
68 if (cpu_has_dsp) \ 68 if (cpu_has_dsp) \
@@ -193,7 +193,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
193 return x; 193 return x;
194} 194}
195 195
196#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) 196#define xchg(ptr, x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr))))
197 197
198extern void set_handler(unsigned long offset, void *addr, unsigned long len); 198extern void set_handler(unsigned long offset, void *addr, unsigned long len);
199extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len); 199extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len);
diff --git a/include/asm-mips/tlbflush.h b/include/asm-mips/tlbflush.h
index 276be77c3e85..730e841fb08a 100644
--- a/include/asm-mips/tlbflush.h
+++ b/include/asm-mips/tlbflush.h
@@ -37,10 +37,10 @@ extern void flush_tlb_one(unsigned long vaddr);
37 37
38#define flush_tlb_all() local_flush_tlb_all() 38#define flush_tlb_all() local_flush_tlb_all()
39#define flush_tlb_mm(mm) local_flush_tlb_mm(mm) 39#define flush_tlb_mm(mm) local_flush_tlb_mm(mm)
40#define flush_tlb_range(vma,vmaddr,end) local_flush_tlb_range(vma, vmaddr, end) 40#define flush_tlb_range(vma, vmaddr, end) local_flush_tlb_range(vma, vmaddr, end)
41#define flush_tlb_kernel_range(vmaddr,end) \ 41#define flush_tlb_kernel_range(vmaddr,end) \
42 local_flush_tlb_kernel_range(vmaddr, end) 42 local_flush_tlb_kernel_range(vmaddr, end)
43#define flush_tlb_page(vma,page) local_flush_tlb_page(vma, page) 43#define flush_tlb_page(vma, page) local_flush_tlb_page(vma, page)
44#define flush_tlb_one(vaddr) local_flush_tlb_one(vaddr) 44#define flush_tlb_one(vaddr) local_flush_tlb_one(vaddr)
45 45
46#endif /* CONFIG_SMP */ 46#endif /* CONFIG_SMP */
diff --git a/include/asm-mips/tx4938/rbtx4938.h b/include/asm-mips/tx4938/rbtx4938.h
index b14acb575be2..b180488dcdc4 100644
--- a/include/asm-mips/tx4938/rbtx4938.h
+++ b/include/asm-mips/tx4938/rbtx4938.h
@@ -153,7 +153,7 @@
153#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR) 153#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR)
154#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n)) 154#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n))
155#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n)) 155#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n))
156#define RBTX4938_IRQ_IRC_DMA(ch,n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch,n)) 156#define RBTX4938_IRQ_IRC_DMA(ch, n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch, n))
157#define RBTX4938_IRQ_IRC_PIO (RBTX4938_IRQ_IRC + TX4938_IR_PIO) 157#define RBTX4938_IRQ_IRC_PIO (RBTX4938_IRQ_IRC + TX4938_IR_PIO)
158#define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC) 158#define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC)
159#define RBTX4938_IRQ_IRC_PCIC (RBTX4938_IRQ_IRC + TX4938_IR_PCIC) 159#define RBTX4938_IRQ_IRC_PCIC (RBTX4938_IRQ_IRC + TX4938_IR_PCIC)
diff --git a/include/asm-mips/tx4938/tx4938.h b/include/asm-mips/tx4938/tx4938.h
index afdb19813ca1..650b010761f9 100644
--- a/include/asm-mips/tx4938/tx4938.h
+++ b/include/asm-mips/tx4938/tx4938.h
@@ -16,7 +16,7 @@
16#include <asm/tx4938/tx4938_mips.h> 16#include <asm/tx4938/tx4938_mips.h>
17 17
18#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr)) 18#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr))
19#define tx4938_write_nfmc(b,addr) (*(volatile unsigned int *)(addr)) = (b) 19#define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b)
20 20
21#define TX4938_NR_IRQ_LOCAL TX4938_IRQ_PIC_BEG 21#define TX4938_NR_IRQ_LOCAL TX4938_IRQ_PIC_BEG
22 22
@@ -84,27 +84,27 @@
84#include <asm/byteorder.h> 84#include <asm/byteorder.h>
85 85
86#ifdef __BIG_ENDIAN 86#ifdef __BIG_ENDIAN
87#define endian_def_l2(e1,e2) \ 87#define endian_def_l2(e1, e2) \
88 volatile unsigned long e1,e2 88 volatile unsigned long e1, e2
89#define endian_def_s2(e1,e2) \ 89#define endian_def_s2(e1, e2) \
90 volatile unsigned short e1,e2 90 volatile unsigned short e1, e2
91#define endian_def_sb2(e1,e2,e3) \ 91#define endian_def_sb2(e1, e2, e3) \
92 volatile unsigned short e1;volatile unsigned char e2,e3 92 volatile unsigned short e1;volatile unsigned char e2, e3
93#define endian_def_b2s(e1,e2,e3) \ 93#define endian_def_b2s(e1, e2, e3) \
94 volatile unsigned char e1,e2;volatile unsigned short e3 94 volatile unsigned char e1, e2;volatile unsigned short e3
95#define endian_def_b4(e1,e2,e3,e4) \ 95#define endian_def_b4(e1, e2, e3, e4) \
96 volatile unsigned char e1,e2,e3,e4 96 volatile unsigned char e1, e2, e3, e4
97#else 97#else
98#define endian_def_l2(e1,e2) \ 98#define endian_def_l2(e1, e2) \
99 volatile unsigned long e2,e1 99 volatile unsigned long e2, e1
100#define endian_def_s2(e1,e2) \ 100#define endian_def_s2(e1, e2) \
101 volatile unsigned short e2,e1 101 volatile unsigned short e2, e1
102#define endian_def_sb2(e1,e2,e3) \ 102#define endian_def_sb2(e1, e2, e3) \
103 volatile unsigned char e3,e2;volatile unsigned short e1 103 volatile unsigned char e3, e2;volatile unsigned short e1
104#define endian_def_b2s(e1,e2,e3) \ 104#define endian_def_b2s(e1, e2, e3) \
105 volatile unsigned short e3;volatile unsigned char e2,e1 105 volatile unsigned short e3;volatile unsigned char e2, e1
106#define endian_def_b4(e1,e2,e3,e4) \ 106#define endian_def_b4(e1, e2, e3, e4) \
107 volatile unsigned char e4,e3,e2,e1 107 volatile unsigned char e4, e3, e2, e1
108#endif 108#endif
109 109
110 110
@@ -354,7 +354,7 @@ struct tx4938_ccfg_reg {
354#define TX4938_NUM_IR_SIO 2 354#define TX4938_NUM_IR_SIO 2
355#define TX4938_IR_SIO(n) (8 + (n)) 355#define TX4938_IR_SIO(n) (8 + (n))
356#define TX4938_NUM_IR_DMA 4 356#define TX4938_NUM_IR_DMA 4
357#define TX4938_IR_DMA(ch,n) ((ch ? 27 : 10) + (n)) /* 10-13,27-30 */ 357#define TX4938_IR_DMA(ch, n) ((ch ? 27 : 10) + (n)) /* 10-13, 27-30 */
358#define TX4938_IR_PIO 14 358#define TX4938_IR_PIO 14
359#define TX4938_IR_PDMAC 15 359#define TX4938_IR_PDMAC 15
360#define TX4938_IR_PCIC 16 360#define TX4938_IR_PCIC 16
diff --git a/include/asm-mips/tx4938/tx4938_mips.h b/include/asm-mips/tx4938/tx4938_mips.h
index 5f8498fef005..f346ff58b947 100644
--- a/include/asm-mips/tx4938/tx4938_mips.h
+++ b/include/asm-mips/tx4938/tx4938_mips.h
@@ -19,10 +19,10 @@
19#define reg_rd32(r) ((u32)(*((vu32*)(r)))) 19#define reg_rd32(r) ((u32)(*((vu32*)(r))))
20#define reg_rd64(r) ((u64)(*((vu64*)(r)))) 20#define reg_rd64(r) ((u64)(*((vu64*)(r))))
21 21
22#define reg_wr08(r,v) ((*((vu8 *)(r)))=((u8 )(v))) 22#define reg_wr08(r, v) ((*((vu8 *)(r)))=((u8 )(v)))
23#define reg_wr16(r,v) ((*((vu16*)(r)))=((u16)(v))) 23#define reg_wr16(r, v) ((*((vu16*)(r)))=((u16)(v)))
24#define reg_wr32(r,v) ((*((vu32*)(r)))=((u32)(v))) 24#define reg_wr32(r, v) ((*((vu32*)(r)))=((u32)(v)))
25#define reg_wr64(r,v) ((*((vu64*)(r)))=((u64)(v))) 25#define reg_wr64(r, v) ((*((vu64*)(r)))=((u64)(v)))
26 26
27typedef volatile __signed char vs8; 27typedef volatile __signed char vs8;
28typedef volatile unsigned char vu8; 28typedef volatile unsigned char vu8;
diff --git a/include/asm-mips/uaccess.h b/include/asm-mips/uaccess.h
index 017dfb0d75c3..c30c718994c9 100644
--- a/include/asm-mips/uaccess.h
+++ b/include/asm-mips/uaccess.h
@@ -63,7 +63,7 @@
63#define get_fs() (current_thread_info()->addr_limit) 63#define get_fs() (current_thread_info()->addr_limit)
64#define set_fs(x) (current_thread_info()->addr_limit = (x)) 64#define set_fs(x) (current_thread_info()->addr_limit = (x))
65 65
66#define segment_eq(a,b) ((a).seg == (b).seg) 66#define segment_eq(a, b) ((a).seg == (b).seg)
67 67
68 68
69/* 69/*
@@ -108,7 +108,7 @@
108 (((signed long)((mask) & ((addr) | ((addr) + (size)) | __ua_size(size)))) == 0) 108 (((signed long)((mask) & ((addr) | ((addr) + (size)) | __ua_size(size)))) == 0)
109 109
110#define access_ok(type, addr, size) \ 110#define access_ok(type, addr, size) \
111 likely(__access_ok((unsigned long)(addr), (size),__access_mask)) 111 likely(__access_ok((unsigned long)(addr), (size), __access_mask))
112 112
113/* 113/*
114 * put_user: - Write a simple value into user space. 114 * put_user: - Write a simple value into user space.
@@ -127,7 +127,7 @@
127 * Returns zero on success, or -EFAULT on error. 127 * Returns zero on success, or -EFAULT on error.
128 */ 128 */
129#define put_user(x,ptr) \ 129#define put_user(x,ptr) \
130 __put_user_check((x),(ptr),sizeof(*(ptr))) 130 __put_user_check((x), (ptr), sizeof(*(ptr)))
131 131
132/* 132/*
133 * get_user: - Get a simple variable from user space. 133 * get_user: - Get a simple variable from user space.
@@ -147,7 +147,7 @@
147 * On error, the variable @x is set to zero. 147 * On error, the variable @x is set to zero.
148 */ 148 */
149#define get_user(x,ptr) \ 149#define get_user(x,ptr) \
150 __get_user_check((x),(ptr),sizeof(*(ptr))) 150 __get_user_check((x), (ptr), sizeof(*(ptr)))
151 151
152/* 152/*
153 * __put_user: - Write a simple value into user space, with less checking. 153 * __put_user: - Write a simple value into user space, with less checking.
@@ -169,7 +169,7 @@
169 * Returns zero on success, or -EFAULT on error. 169 * Returns zero on success, or -EFAULT on error.
170 */ 170 */
171#define __put_user(x,ptr) \ 171#define __put_user(x,ptr) \
172 __put_user_nocheck((x),(ptr),sizeof(*(ptr))) 172 __put_user_nocheck((x), (ptr), sizeof(*(ptr)))
173 173
174/* 174/*
175 * __get_user: - Get a simple variable from user space, with less checking. 175 * __get_user: - Get a simple variable from user space, with less checking.
@@ -192,7 +192,7 @@
192 * On error, the variable @x is set to zero. 192 * On error, the variable @x is set to zero.
193 */ 193 */
194#define __get_user(x,ptr) \ 194#define __get_user(x,ptr) \
195 __get_user_nocheck((x),(ptr),sizeof(*(ptr))) 195 __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
196 196
197struct __large_struct { unsigned long buf[100]; }; 197struct __large_struct { unsigned long buf[100]; };
198#define __m(x) (*(struct __large_struct __user *)(x)) 198#define __m(x) (*(struct __large_struct __user *)(x))
@@ -221,7 +221,7 @@ do { \
221 } \ 221 } \
222} while (0) 222} while (0)
223 223
224#define __get_user_nocheck(x,ptr,size) \ 224#define __get_user_nocheck(x, ptr, size) \
225({ \ 225({ \
226 long __gu_err; \ 226 long __gu_err; \
227 \ 227 \
@@ -229,7 +229,7 @@ do { \
229 __gu_err; \ 229 __gu_err; \
230}) 230})
231 231
232#define __get_user_check(x,ptr,size) \ 232#define __get_user_check(x, ptr, size) \
233({ \ 233({ \
234 long __gu_err = -EFAULT; \ 234 long __gu_err = -EFAULT; \
235 const __typeof__(*(ptr)) __user * __gu_ptr = (ptr); \ 235 const __typeof__(*(ptr)) __user * __gu_ptr = (ptr); \
@@ -300,7 +300,7 @@ do { \
300#define __PUT_USER_DW(ptr) __put_user_asm("sd", ptr) 300#define __PUT_USER_DW(ptr) __put_user_asm("sd", ptr)
301#endif 301#endif
302 302
303#define __put_user_nocheck(x,ptr,size) \ 303#define __put_user_nocheck(x, ptr, size) \
304({ \ 304({ \
305 __typeof__(*(ptr)) __pu_val; \ 305 __typeof__(*(ptr)) __pu_val; \
306 long __pu_err = 0; \ 306 long __pu_err = 0; \
@@ -316,7 +316,7 @@ do { \
316 __pu_err; \ 316 __pu_err; \
317}) 317})
318 318
319#define __put_user_check(x,ptr,size) \ 319#define __put_user_check(x, ptr, size) \
320({ \ 320({ \
321 __typeof__(*(ptr)) __user *__pu_addr = (ptr); \ 321 __typeof__(*(ptr)) __user *__pu_addr = (ptr); \
322 __typeof__(*(ptr)) __pu_val = (x); \ 322 __typeof__(*(ptr)) __pu_val = (x); \
@@ -389,7 +389,7 @@ extern void __put_user_unknown(void);
389 389
390extern size_t __copy_user(void *__to, const void *__from, size_t __n); 390extern size_t __copy_user(void *__to, const void *__from, size_t __n);
391 391
392#define __invoke_copy_to_user(to,from,n) \ 392#define __invoke_copy_to_user(to, from, n) \
393({ \ 393({ \
394 register void __user *__cu_to_r __asm__("$4"); \ 394 register void __user *__cu_to_r __asm__("$4"); \
395 register const void *__cu_from_r __asm__("$5"); \ 395 register const void *__cu_from_r __asm__("$5"); \
@@ -421,7 +421,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
421 * Returns number of bytes that could not be copied. 421 * Returns number of bytes that could not be copied.
422 * On success, this will be zero. 422 * On success, this will be zero.
423 */ 423 */
424#define __copy_to_user(to,from,n) \ 424#define __copy_to_user(to, from, n) \
425({ \ 425({ \
426 void __user *__cu_to; \ 426 void __user *__cu_to; \
427 const void *__cu_from; \ 427 const void *__cu_from; \
@@ -437,7 +437,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
437 437
438extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); 438extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
439 439
440#define __copy_to_user_inatomic(to,from,n) \ 440#define __copy_to_user_inatomic(to, from, n) \
441({ \ 441({ \
442 void __user *__cu_to; \ 442 void __user *__cu_to; \
443 const void *__cu_from; \ 443 const void *__cu_from; \
@@ -450,7 +450,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
450 __cu_len; \ 450 __cu_len; \
451}) 451})
452 452
453#define __copy_from_user_inatomic(to,from,n) \ 453#define __copy_from_user_inatomic(to, from, n) \
454({ \ 454({ \
455 void *__cu_to; \ 455 void *__cu_to; \
456 const void __user *__cu_from; \ 456 const void __user *__cu_from; \
@@ -477,7 +477,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
477 * Returns number of bytes that could not be copied. 477 * Returns number of bytes that could not be copied.
478 * On success, this will be zero. 478 * On success, this will be zero.
479 */ 479 */
480#define copy_to_user(to,from,n) \ 480#define copy_to_user(to, from, n) \
481({ \ 481({ \
482 void __user *__cu_to; \ 482 void __user *__cu_to; \
483 const void *__cu_from; \ 483 const void *__cu_from; \
@@ -493,7 +493,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
493 __cu_len; \ 493 __cu_len; \
494}) 494})
495 495
496#define __invoke_copy_from_user(to,from,n) \ 496#define __invoke_copy_from_user(to, from, n) \
497({ \ 497({ \
498 register void *__cu_to_r __asm__("$4"); \ 498 register void *__cu_to_r __asm__("$4"); \
499 register const void __user *__cu_from_r __asm__("$5"); \ 499 register const void __user *__cu_from_r __asm__("$5"); \
@@ -516,7 +516,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
516 __cu_len_r; \ 516 __cu_len_r; \
517}) 517})
518 518
519#define __invoke_copy_from_user_inatomic(to,from,n) \ 519#define __invoke_copy_from_user_inatomic(to, from, n) \
520({ \ 520({ \
521 register void *__cu_to_r __asm__("$4"); \ 521 register void *__cu_to_r __asm__("$4"); \
522 register const void __user *__cu_from_r __asm__("$5"); \ 522 register const void __user *__cu_from_r __asm__("$5"); \
@@ -556,7 +556,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
556 * If some data could not be copied, this function will pad the copied 556 * If some data could not be copied, this function will pad the copied
557 * data to the requested size using zero bytes. 557 * data to the requested size using zero bytes.
558 */ 558 */
559#define __copy_from_user(to,from,n) \ 559#define __copy_from_user(to, from, n) \
560({ \ 560({ \
561 void *__cu_to; \ 561 void *__cu_to; \
562 const void __user *__cu_from; \ 562 const void __user *__cu_from; \
@@ -587,7 +587,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
587 * If some data could not be copied, this function will pad the copied 587 * If some data could not be copied, this function will pad the copied
588 * data to the requested size using zero bytes. 588 * data to the requested size using zero bytes.
589 */ 589 */
590#define copy_from_user(to,from,n) \ 590#define copy_from_user(to, from, n) \
591({ \ 591({ \
592 void *__cu_to; \ 592 void *__cu_to; \
593 const void __user *__cu_from; \ 593 const void __user *__cu_from; \
@@ -605,7 +605,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
605 605
606#define __copy_in_user(to, from, n) __copy_from_user(to, from, n) 606#define __copy_in_user(to, from, n) __copy_from_user(to, from, n)
607 607
608#define copy_in_user(to,from,n) \ 608#define copy_in_user(to, from, n) \
609({ \ 609({ \
610 void __user *__cu_to; \ 610 void __user *__cu_to; \
611 const void __user *__cu_from; \ 611 const void __user *__cu_from; \
diff --git a/include/asm-mips/vga.h b/include/asm-mips/vga.h
index c1dd0b10bc27..f4cff7e4fa8a 100644
--- a/include/asm-mips/vga.h
+++ b/include/asm-mips/vga.h
@@ -13,10 +13,10 @@
13 * access the videoram directly without any black magic. 13 * access the videoram directly without any black magic.
14 */ 14 */
15 15
16#define VGA_MAP_MEM(x,s) (0xb0000000L + (unsigned long)(x)) 16#define VGA_MAP_MEM(x, s) (0xb0000000L + (unsigned long)(x))
17 17
18#define vga_readb(x) (*(x)) 18#define vga_readb(x) (*(x))
19#define vga_writeb(x,y) (*(y) = (x)) 19#define vga_writeb(x, y) (*(y) = (x))
20 20
21#define VT_BUF_HAVE_RW 21#define VT_BUF_HAVE_RW
22/* 22/*
diff --git a/include/asm-mips/xtalk/xtalk.h b/include/asm-mips/xtalk/xtalk.h
index 4a60f27c8817..79bac882a739 100644
--- a/include/asm-mips/xtalk/xtalk.h
+++ b/include/asm-mips/xtalk/xtalk.h
@@ -45,7 +45,7 @@ typedef struct xtalk_piomap_s *xtalk_piomap_t;
45#define XIO_PACKED(x) (((x)&XIO_PORT_BITS) != 0) 45#define XIO_PACKED(x) (((x)&XIO_PORT_BITS) != 0)
46#define XIO_ADDR(x) ((x)&XIO_ADDR_BITS) 46#define XIO_ADDR(x) ((x)&XIO_ADDR_BITS)
47#define XIO_PORT(x) ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT)) 47#define XIO_PORT(x) ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT))
48#define XIO_PACK(p,o) ((((uint64_t)(p))<<XIO_PORT_SHIFT) | ((o)&XIO_ADDR_BITS)) 48#define XIO_PACK(p, o) ((((uint64_t)(p))<<XIO_PORT_SHIFT) | ((o)&XIO_ADDR_BITS))
49 49
50#endif /* !__ASSEMBLY__ */ 50#endif /* !__ASSEMBLY__ */
51 51
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-07 11:50:14 -0500