diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2008-10-23 16:02:03 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-10-23 16:02:03 -0400 |
commit | f8aea20018aefa51bf818914c9c1ef9006353dbb (patch) | |
tree | 36c5ab25fc6808ae635ae69e3f301b11ef52d72f | |
parent | c3c9897c63ebb0b93b7f78724e38d6ee1da04041 (diff) | |
parent | 520a2c2741747062e75f91cd0faddb564fbc64d2 (diff) |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi-misc-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi-misc-2.6: (21 commits)
[SCSI] sd: fix computation of the full size of the device
[SCSI] lib: string_get_size(): don't hang on zero; no decimals on exact
[SCSI] sun3x_esp: Convert && to ||
[SCSI] sd: remove command-size switching code
[SCSI] 3w-9xxx: remove unnecessary local_irq_save/restore for scsi sg copy API
[SCSI] 3w-xxxx: remove unnecessary local_irq_save/restore for scsi sg copy API
[SCSI] fix netlink kernel-doc
[SCSI] sd: Fix handling of NO_SENSE check condition
[SCSI] export busy state via q->lld_busy_fn()
[SCSI] refactor sdev/starget/shost busy checking
[SCSI] mptfusion: Increase scsi-timeouts, similariy to the LSI 4.x driver.
[SCSI] aic7xxx: Take the LED out of diagnostic mode on PM resume
[SCSI] aic79xx: user visible misuse wrong SI units (not disk size!)
[SCSI] ipr: use memory_read_from_buffer()
[SCSI] aic79xx: fix shadowed variables
[SCSI] aic79xx: fix shadowed variables, add statics
[SCSI] aic7xxx: update *_shipped files
[SCSI] aic7xxx: update .reg files
[SCSI] aic7xxx: introduce "dont_generate_debug_code" keyword in aicasm parser
[SCSI] scsi_dh: Initialize path state to be passive when path is not owned
...
23 files changed, 580 insertions, 4293 deletions
diff --git a/drivers/message/fusion/mptscsih.c b/drivers/message/fusion/mptscsih.c index 9f9354fd3516..d62fd4f6b52e 100644 --- a/drivers/message/fusion/mptscsih.c +++ b/drivers/message/fusion/mptscsih.c | |||
@@ -1760,10 +1760,9 @@ mptscsih_get_tm_timeout(MPT_ADAPTER *ioc) | |||
1760 | case FC: | 1760 | case FC: |
1761 | return 40; | 1761 | return 40; |
1762 | case SAS: | 1762 | case SAS: |
1763 | return 10; | ||
1764 | case SPI: | 1763 | case SPI: |
1765 | default: | 1764 | default: |
1766 | return 2; | 1765 | return 10; |
1767 | } | 1766 | } |
1768 | } | 1767 | } |
1769 | 1768 | ||
diff --git a/drivers/scsi/3w-9xxx.c b/drivers/scsi/3w-9xxx.c index b92c19bb6876..5311317c2e4c 100644 --- a/drivers/scsi/3w-9xxx.c +++ b/drivers/scsi/3w-9xxx.c | |||
@@ -1924,12 +1924,9 @@ static void twa_scsiop_execute_scsi_complete(TW_Device_Extension *tw_dev, int re | |||
1924 | (cmd->sc_data_direction == DMA_FROM_DEVICE || | 1924 | (cmd->sc_data_direction == DMA_FROM_DEVICE || |
1925 | cmd->sc_data_direction == DMA_BIDIRECTIONAL)) { | 1925 | cmd->sc_data_direction == DMA_BIDIRECTIONAL)) { |
1926 | if (scsi_sg_count(cmd) == 1) { | 1926 | if (scsi_sg_count(cmd) == 1) { |
1927 | unsigned long flags; | ||
1928 | void *buf = tw_dev->generic_buffer_virt[request_id]; | 1927 | void *buf = tw_dev->generic_buffer_virt[request_id]; |
1929 | 1928 | ||
1930 | local_irq_save(flags); | ||
1931 | scsi_sg_copy_from_buffer(cmd, buf, TW_SECTOR_SIZE); | 1929 | scsi_sg_copy_from_buffer(cmd, buf, TW_SECTOR_SIZE); |
1932 | local_irq_restore(flags); | ||
1933 | } | 1930 | } |
1934 | } | 1931 | } |
1935 | } /* End twa_scsiop_execute_scsi_complete() */ | 1932 | } /* End twa_scsiop_execute_scsi_complete() */ |
diff --git a/drivers/scsi/3w-xxxx.c b/drivers/scsi/3w-xxxx.c index a0537f09aa21..c03f1d2c9e2e 100644 --- a/drivers/scsi/3w-xxxx.c +++ b/drivers/scsi/3w-xxxx.c | |||
@@ -1466,12 +1466,7 @@ static int tw_scsiop_inquiry(TW_Device_Extension *tw_dev, int request_id) | |||
1466 | static void tw_transfer_internal(TW_Device_Extension *tw_dev, int request_id, | 1466 | static void tw_transfer_internal(TW_Device_Extension *tw_dev, int request_id, |
1467 | void *data, unsigned int len) | 1467 | void *data, unsigned int len) |
1468 | { | 1468 | { |
1469 | struct scsi_cmnd *cmd = tw_dev->srb[request_id]; | 1469 | scsi_sg_copy_from_buffer(tw_dev->srb[request_id], data, len); |
1470 | unsigned long flags; | ||
1471 | |||
1472 | local_irq_save(flags); | ||
1473 | scsi_sg_copy_from_buffer(cmd, data, len); | ||
1474 | local_irq_restore(flags); | ||
1475 | } | 1470 | } |
1476 | 1471 | ||
1477 | /* This function is called by the isr to complete an inquiry command */ | 1472 | /* This function is called by the isr to complete an inquiry command */ |
diff --git a/drivers/scsi/aic7xxx/aic79xx.reg b/drivers/scsi/aic7xxx/aic79xx.reg index cca16fc5b4ad..0666c22ab55b 100644 --- a/drivers/scsi/aic7xxx/aic79xx.reg +++ b/drivers/scsi/aic7xxx/aic79xx.reg | |||
@@ -80,6 +80,17 @@ VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#77 $" | |||
80 | } | 80 | } |
81 | 81 | ||
82 | /* | 82 | /* |
83 | * Registers marked "dont_generate_debug_code" are not (yet) referenced | ||
84 | * from the driver code, and this keyword inhibit generation | ||
85 | * of debug code for them. | ||
86 | * | ||
87 | * REG_PRETTY_PRINT config will complain if dont_generate_debug_code | ||
88 | * is added to the register which is referenced in the driver. | ||
89 | * Unreferenced register with no dont_generate_debug_code will result | ||
90 | * in dead code. No warning is issued. | ||
91 | */ | ||
92 | |||
93 | /* | ||
83 | * Mode Pointer | 94 | * Mode Pointer |
84 | * Controls which of the 5, 512byte, address spaces should be used | 95 | * Controls which of the 5, 512byte, address spaces should be used |
85 | * as the source and destination of any register accesses in our | 96 | * as the source and destination of any register accesses in our |
@@ -91,6 +102,7 @@ register MODE_PTR { | |||
91 | field DST_MODE 0x70 | 102 | field DST_MODE 0x70 |
92 | field SRC_MODE 0x07 | 103 | field SRC_MODE 0x07 |
93 | mode_pointer | 104 | mode_pointer |
105 | dont_generate_debug_code | ||
94 | } | 106 | } |
95 | 107 | ||
96 | const SRC_MODE_SHIFT 0 | 108 | const SRC_MODE_SHIFT 0 |
@@ -190,6 +202,7 @@ register SEQINTCODE { | |||
190 | SAW_HWERR, | 202 | SAW_HWERR, |
191 | BAD_SCB_STATUS | 203 | BAD_SCB_STATUS |
192 | } | 204 | } |
205 | dont_generate_debug_code | ||
193 | } | 206 | } |
194 | 207 | ||
195 | /* | 208 | /* |
@@ -207,6 +220,7 @@ register CLRINT { | |||
207 | field CLRSEQINT 0x04 | 220 | field CLRSEQINT 0x04 |
208 | field CLRCMDINT 0x02 | 221 | field CLRCMDINT 0x02 |
209 | field CLRSPLTINT 0x01 | 222 | field CLRSPLTINT 0x01 |
223 | dont_generate_debug_code | ||
210 | } | 224 | } |
211 | 225 | ||
212 | /* | 226 | /* |
@@ -222,6 +236,7 @@ register ERROR { | |||
222 | field SQPARERR 0x08 | 236 | field SQPARERR 0x08 |
223 | field ILLOPCODE 0x04 | 237 | field ILLOPCODE 0x04 |
224 | field DSCTMOUT 0x02 | 238 | field DSCTMOUT 0x02 |
239 | dont_generate_debug_code | ||
225 | } | 240 | } |
226 | 241 | ||
227 | /* | 242 | /* |
@@ -255,6 +270,7 @@ register HCNTRL { | |||
255 | field INTEN 0x02 | 270 | field INTEN 0x02 |
256 | field CHIPRST 0x01 | 271 | field CHIPRST 0x01 |
257 | field CHIPRSTACK 0x01 | 272 | field CHIPRSTACK 0x01 |
273 | dont_generate_debug_code | ||
258 | } | 274 | } |
259 | 275 | ||
260 | /* | 276 | /* |
@@ -265,6 +281,7 @@ register HNSCB_QOFF { | |||
265 | access_mode RW | 281 | access_mode RW |
266 | size 2 | 282 | size 2 |
267 | count 2 | 283 | count 2 |
284 | dont_generate_debug_code | ||
268 | } | 285 | } |
269 | 286 | ||
270 | /* | 287 | /* |
@@ -274,6 +291,7 @@ register HESCB_QOFF { | |||
274 | address 0x008 | 291 | address 0x008 |
275 | access_mode RW | 292 | access_mode RW |
276 | count 2 | 293 | count 2 |
294 | dont_generate_debug_code | ||
277 | } | 295 | } |
278 | 296 | ||
279 | /* | 297 | /* |
@@ -311,6 +329,7 @@ register CLRSEQINTSTAT { | |||
311 | field CLRSEQ_SCSIINT 0x04 | 329 | field CLRSEQ_SCSIINT 0x04 |
312 | field CLRSEQ_PCIINT 0x02 | 330 | field CLRSEQ_PCIINT 0x02 |
313 | field CLRSEQ_SPLTINT 0x01 | 331 | field CLRSEQ_SPLTINT 0x01 |
332 | dont_generate_debug_code | ||
314 | } | 333 | } |
315 | 334 | ||
316 | /* | 335 | /* |
@@ -320,6 +339,7 @@ register SWTIMER { | |||
320 | address 0x00E | 339 | address 0x00E |
321 | access_mode RW | 340 | access_mode RW |
322 | size 2 | 341 | size 2 |
342 | dont_generate_debug_code | ||
323 | } | 343 | } |
324 | 344 | ||
325 | /* | 345 | /* |
@@ -330,6 +350,7 @@ register SNSCB_QOFF { | |||
330 | access_mode RW | 350 | access_mode RW |
331 | size 2 | 351 | size 2 |
332 | modes M_CCHAN | 352 | modes M_CCHAN |
353 | dont_generate_debug_code | ||
333 | } | 354 | } |
334 | 355 | ||
335 | /* | 356 | /* |
@@ -340,6 +361,7 @@ register SESCB_QOFF { | |||
340 | count 2 | 361 | count 2 |
341 | access_mode RW | 362 | access_mode RW |
342 | modes M_CCHAN | 363 | modes M_CCHAN |
364 | dont_generate_debug_code | ||
343 | } | 365 | } |
344 | 366 | ||
345 | /* | 367 | /* |
@@ -350,6 +372,7 @@ register SDSCB_QOFF { | |||
350 | access_mode RW | 372 | access_mode RW |
351 | modes M_CCHAN | 373 | modes M_CCHAN |
352 | size 2 | 374 | size 2 |
375 | dont_generate_debug_code | ||
353 | } | 376 | } |
354 | 377 | ||
355 | /* | 378 | /* |
@@ -378,6 +401,7 @@ register QOFF_CTLSTA { | |||
378 | SCB_QSIZE_8192, | 401 | SCB_QSIZE_8192, |
379 | SCB_QSIZE_16384 | 402 | SCB_QSIZE_16384 |
380 | } | 403 | } |
404 | dont_generate_debug_code | ||
381 | } | 405 | } |
382 | 406 | ||
383 | /* | 407 | /* |
@@ -431,6 +455,7 @@ register DSCOMMAND0 { | |||
431 | field EXTREQLCK 0x10 /* External Request Lock */ | 455 | field EXTREQLCK 0x10 /* External Request Lock */ |
432 | field DISABLE_TWATE 0x02 /* Rev B or greater */ | 456 | field DISABLE_TWATE 0x02 /* Rev B or greater */ |
433 | field CIOPARCKEN 0x01 /* Internal bus parity error enable */ | 457 | field CIOPARCKEN 0x01 /* Internal bus parity error enable */ |
458 | dont_generate_debug_code | ||
434 | } | 459 | } |
435 | 460 | ||
436 | /* | 461 | /* |
@@ -459,6 +484,7 @@ register SG_CACHE_PRE { | |||
459 | field SG_ADDR_MASK 0xf8 | 484 | field SG_ADDR_MASK 0xf8 |
460 | field ODD_SEG 0x04 | 485 | field ODD_SEG 0x04 |
461 | field LAST_SEG 0x02 | 486 | field LAST_SEG 0x02 |
487 | dont_generate_debug_code | ||
462 | } | 488 | } |
463 | 489 | ||
464 | register SG_CACHE_SHADOW { | 490 | register SG_CACHE_SHADOW { |
@@ -491,6 +517,7 @@ register HADDR { | |||
491 | access_mode RW | 517 | access_mode RW |
492 | size 8 | 518 | size 8 |
493 | modes M_DFF0, M_DFF1 | 519 | modes M_DFF0, M_DFF1 |
520 | dont_generate_debug_code | ||
494 | } | 521 | } |
495 | 522 | ||
496 | /* | 523 | /* |
@@ -522,6 +549,7 @@ register HCNT { | |||
522 | access_mode RW | 549 | access_mode RW |
523 | size 3 | 550 | size 3 |
524 | modes M_DFF0, M_DFF1 | 551 | modes M_DFF0, M_DFF1 |
552 | dont_generate_debug_code | ||
525 | } | 553 | } |
526 | 554 | ||
527 | /* | 555 | /* |
@@ -551,6 +579,7 @@ register SGHADDR { | |||
551 | access_mode RW | 579 | access_mode RW |
552 | size 8 | 580 | size 8 |
553 | modes M_DFF0, M_DFF1 | 581 | modes M_DFF0, M_DFF1 |
582 | dont_generate_debug_code | ||
554 | } | 583 | } |
555 | 584 | ||
556 | /* | 585 | /* |
@@ -561,6 +590,7 @@ register SCBHADDR { | |||
561 | access_mode RW | 590 | access_mode RW |
562 | size 8 | 591 | size 8 |
563 | modes M_CCHAN | 592 | modes M_CCHAN |
593 | dont_generate_debug_code | ||
564 | } | 594 | } |
565 | 595 | ||
566 | /* | 596 | /* |
@@ -570,6 +600,7 @@ register SGHCNT { | |||
570 | address 0x084 | 600 | address 0x084 |
571 | access_mode RW | 601 | access_mode RW |
572 | modes M_DFF0, M_DFF1 | 602 | modes M_DFF0, M_DFF1 |
603 | dont_generate_debug_code | ||
573 | } | 604 | } |
574 | 605 | ||
575 | /* | 606 | /* |
@@ -579,6 +610,7 @@ register SCBHCNT { | |||
579 | address 0x084 | 610 | address 0x084 |
580 | access_mode RW | 611 | access_mode RW |
581 | modes M_CCHAN | 612 | modes M_CCHAN |
613 | dont_generate_debug_code | ||
582 | } | 614 | } |
583 | 615 | ||
584 | /* | 616 | /* |
@@ -609,6 +641,7 @@ register DFF_THRSH { | |||
609 | RD_DFTHRSH_90, | 641 | RD_DFTHRSH_90, |
610 | RD_DFTHRSH_MAX | 642 | RD_DFTHRSH_MAX |
611 | } | 643 | } |
644 | dont_generate_debug_code | ||
612 | } | 645 | } |
613 | 646 | ||
614 | /* | 647 | /* |
@@ -817,6 +850,7 @@ register PCIXCTL { | |||
817 | field SRSPDPEEN 0x04 | 850 | field SRSPDPEEN 0x04 |
818 | field TSCSERREN 0x02 | 851 | field TSCSERREN 0x02 |
819 | field CMPABCDIS 0x01 | 852 | field CMPABCDIS 0x01 |
853 | dont_generate_debug_code | ||
820 | } | 854 | } |
821 | 855 | ||
822 | /* | 856 | /* |
@@ -863,6 +897,7 @@ register DCHSPLTSTAT0 { | |||
863 | field RXOVRUN 0x04 | 897 | field RXOVRUN 0x04 |
864 | field RXSCEMSG 0x02 | 898 | field RXSCEMSG 0x02 |
865 | field RXSPLTRSP 0x01 | 899 | field RXSPLTRSP 0x01 |
900 | dont_generate_debug_code | ||
866 | } | 901 | } |
867 | 902 | ||
868 | /* | 903 | /* |
@@ -908,6 +943,7 @@ register DCHSPLTSTAT1 { | |||
908 | modes M_DFF0, M_DFF1 | 943 | modes M_DFF0, M_DFF1 |
909 | count 2 | 944 | count 2 |
910 | field RXDATABUCKET 0x01 | 945 | field RXDATABUCKET 0x01 |
946 | dont_generate_debug_code | ||
911 | } | 947 | } |
912 | 948 | ||
913 | /* | 949 | /* |
@@ -1069,6 +1105,7 @@ register SGSPLTSTAT0 { | |||
1069 | field RXOVRUN 0x04 | 1105 | field RXOVRUN 0x04 |
1070 | field RXSCEMSG 0x02 | 1106 | field RXSCEMSG 0x02 |
1071 | field RXSPLTRSP 0x01 | 1107 | field RXSPLTRSP 0x01 |
1108 | dont_generate_debug_code | ||
1072 | } | 1109 | } |
1073 | 1110 | ||
1074 | /* | 1111 | /* |
@@ -1080,6 +1117,7 @@ register SGSPLTSTAT1 { | |||
1080 | modes M_DFF0, M_DFF1 | 1117 | modes M_DFF0, M_DFF1 |
1081 | count 2 | 1118 | count 2 |
1082 | field RXDATABUCKET 0x01 | 1119 | field RXDATABUCKET 0x01 |
1120 | dont_generate_debug_code | ||
1083 | } | 1121 | } |
1084 | 1122 | ||
1085 | /* | 1123 | /* |
@@ -1091,6 +1129,7 @@ register SFUNCT { | |||
1091 | modes M_CFG | 1129 | modes M_CFG |
1092 | field TEST_GROUP 0xF0 | 1130 | field TEST_GROUP 0xF0 |
1093 | field TEST_NUM 0x0F | 1131 | field TEST_NUM 0x0F |
1132 | dont_generate_debug_code | ||
1094 | } | 1133 | } |
1095 | 1134 | ||
1096 | /* | 1135 | /* |
@@ -1109,6 +1148,7 @@ register DF0PCISTAT { | |||
1109 | field RDPERR 0x04 | 1148 | field RDPERR 0x04 |
1110 | field TWATERR 0x02 | 1149 | field TWATERR 0x02 |
1111 | field DPR 0x01 | 1150 | field DPR 0x01 |
1151 | dont_generate_debug_code | ||
1112 | } | 1152 | } |
1113 | 1153 | ||
1114 | /* | 1154 | /* |
@@ -1204,6 +1244,7 @@ register TARGPCISTAT { | |||
1204 | field SSE 0x40 | 1244 | field SSE 0x40 |
1205 | field STA 0x08 | 1245 | field STA 0x08 |
1206 | field TWATERR 0x02 | 1246 | field TWATERR 0x02 |
1247 | dont_generate_debug_code | ||
1207 | } | 1248 | } |
1208 | 1249 | ||
1209 | /* | 1250 | /* |
@@ -1216,6 +1257,7 @@ register LQIN { | |||
1216 | size 20 | 1257 | size 20 |
1217 | count 2 | 1258 | count 2 |
1218 | modes M_DFF0, M_DFF1, M_SCSI | 1259 | modes M_DFF0, M_DFF1, M_SCSI |
1260 | dont_generate_debug_code | ||
1219 | } | 1261 | } |
1220 | 1262 | ||
1221 | /* | 1263 | /* |
@@ -1247,6 +1289,7 @@ register LUNPTR { | |||
1247 | access_mode RW | 1289 | access_mode RW |
1248 | modes M_CFG | 1290 | modes M_CFG |
1249 | count 2 | 1291 | count 2 |
1292 | dont_generate_debug_code | ||
1250 | } | 1293 | } |
1251 | 1294 | ||
1252 | /* | 1295 | /* |
@@ -1278,6 +1321,7 @@ register CMDLENPTR { | |||
1278 | access_mode RW | 1321 | access_mode RW |
1279 | modes M_CFG | 1322 | modes M_CFG |
1280 | count 1 | 1323 | count 1 |
1324 | dont_generate_debug_code | ||
1281 | } | 1325 | } |
1282 | 1326 | ||
1283 | /* | 1327 | /* |
@@ -1290,6 +1334,7 @@ register ATTRPTR { | |||
1290 | access_mode RW | 1334 | access_mode RW |
1291 | modes M_CFG | 1335 | modes M_CFG |
1292 | count 1 | 1336 | count 1 |
1337 | dont_generate_debug_code | ||
1293 | } | 1338 | } |
1294 | 1339 | ||
1295 | /* | 1340 | /* |
@@ -1302,6 +1347,7 @@ register FLAGPTR { | |||
1302 | access_mode RW | 1347 | access_mode RW |
1303 | modes M_CFG | 1348 | modes M_CFG |
1304 | count 1 | 1349 | count 1 |
1350 | dont_generate_debug_code | ||
1305 | } | 1351 | } |
1306 | 1352 | ||
1307 | /* | 1353 | /* |
@@ -1313,6 +1359,7 @@ register CMDPTR { | |||
1313 | access_mode RW | 1359 | access_mode RW |
1314 | modes M_CFG | 1360 | modes M_CFG |
1315 | count 1 | 1361 | count 1 |
1362 | dont_generate_debug_code | ||
1316 | } | 1363 | } |
1317 | 1364 | ||
1318 | /* | 1365 | /* |
@@ -1324,6 +1371,7 @@ register QNEXTPTR { | |||
1324 | access_mode RW | 1371 | access_mode RW |
1325 | modes M_CFG | 1372 | modes M_CFG |
1326 | count 1 | 1373 | count 1 |
1374 | dont_generate_debug_code | ||
1327 | } | 1375 | } |
1328 | 1376 | ||
1329 | /* | 1377 | /* |
@@ -1347,6 +1395,7 @@ register ABRTBYTEPTR { | |||
1347 | access_mode RW | 1395 | access_mode RW |
1348 | modes M_CFG | 1396 | modes M_CFG |
1349 | count 1 | 1397 | count 1 |
1398 | dont_generate_debug_code | ||
1350 | } | 1399 | } |
1351 | 1400 | ||
1352 | /* | 1401 | /* |
@@ -1358,6 +1407,7 @@ register ABRTBITPTR { | |||
1358 | access_mode RW | 1407 | access_mode RW |
1359 | modes M_CFG | 1408 | modes M_CFG |
1360 | count 1 | 1409 | count 1 |
1410 | dont_generate_debug_code | ||
1361 | } | 1411 | } |
1362 | 1412 | ||
1363 | /* | 1413 | /* |
@@ -1398,6 +1448,7 @@ register LUNLEN { | |||
1398 | count 2 | 1448 | count 2 |
1399 | mask ILUNLEN 0x0F | 1449 | mask ILUNLEN 0x0F |
1400 | mask TLUNLEN 0xF0 | 1450 | mask TLUNLEN 0xF0 |
1451 | dont_generate_debug_code | ||
1401 | } | 1452 | } |
1402 | const LUNLEN_SINGLE_LEVEL_LUN 0xF | 1453 | const LUNLEN_SINGLE_LEVEL_LUN 0xF |
1403 | 1454 | ||
@@ -1410,6 +1461,7 @@ register CDBLIMIT { | |||
1410 | access_mode RW | 1461 | access_mode RW |
1411 | modes M_CFG | 1462 | modes M_CFG |
1412 | count 1 | 1463 | count 1 |
1464 | dont_generate_debug_code | ||
1413 | } | 1465 | } |
1414 | 1466 | ||
1415 | /* | 1467 | /* |
@@ -1422,6 +1474,7 @@ register MAXCMD { | |||
1422 | access_mode RW | 1474 | access_mode RW |
1423 | modes M_CFG | 1475 | modes M_CFG |
1424 | count 9 | 1476 | count 9 |
1477 | dont_generate_debug_code | ||
1425 | } | 1478 | } |
1426 | 1479 | ||
1427 | /* | 1480 | /* |
@@ -1432,6 +1485,7 @@ register MAXCMDCNT { | |||
1432 | address 0x033 | 1485 | address 0x033 |
1433 | access_mode RW | 1486 | access_mode RW |
1434 | modes M_CFG | 1487 | modes M_CFG |
1488 | dont_generate_debug_code | ||
1435 | } | 1489 | } |
1436 | 1490 | ||
1437 | /* | 1491 | /* |
@@ -1490,6 +1544,7 @@ register LQCTL1 { | |||
1490 | field PCI2PCI 0x04 | 1544 | field PCI2PCI 0x04 |
1491 | field SINGLECMD 0x02 | 1545 | field SINGLECMD 0x02 |
1492 | field ABORTPENDING 0x01 | 1546 | field ABORTPENDING 0x01 |
1547 | dont_generate_debug_code | ||
1493 | } | 1548 | } |
1494 | 1549 | ||
1495 | /* | 1550 | /* |
@@ -1508,6 +1563,7 @@ register LQCTL2 { | |||
1508 | field LQOCONTINUE 0x04 | 1563 | field LQOCONTINUE 0x04 |
1509 | field LQOTOIDLE 0x02 | 1564 | field LQOTOIDLE 0x02 |
1510 | field LQOPAUSE 0x01 | 1565 | field LQOPAUSE 0x01 |
1566 | dont_generate_debug_code | ||
1511 | } | 1567 | } |
1512 | 1568 | ||
1513 | /* | 1569 | /* |
@@ -1578,6 +1634,7 @@ register SXFRCTL0 { | |||
1578 | field DFPEXP 0x40 | 1634 | field DFPEXP 0x40 |
1579 | field BIOSCANCELEN 0x10 | 1635 | field BIOSCANCELEN 0x10 |
1580 | field SPIOEN 0x08 | 1636 | field SPIOEN 0x08 |
1637 | dont_generate_debug_code | ||
1581 | } | 1638 | } |
1582 | 1639 | ||
1583 | /* | 1640 | /* |
@@ -1594,6 +1651,7 @@ register SXFRCTL1 { | |||
1594 | field ENSTIMER 0x04 | 1651 | field ENSTIMER 0x04 |
1595 | field ACTNEGEN 0x02 | 1652 | field ACTNEGEN 0x02 |
1596 | field STPWEN 0x01 | 1653 | field STPWEN 0x01 |
1654 | dont_generate_debug_code | ||
1597 | } | 1655 | } |
1598 | 1656 | ||
1599 | /* | 1657 | /* |
@@ -1696,6 +1754,7 @@ register SCSISIGO { | |||
1696 | P_STATUS CDO|IOO, | 1754 | P_STATUS CDO|IOO, |
1697 | P_MESGIN CDO|IOO|MSGO | 1755 | P_MESGIN CDO|IOO|MSGO |
1698 | } | 1756 | } |
1757 | dont_generate_debug_code | ||
1699 | } | 1758 | } |
1700 | 1759 | ||
1701 | /* | 1760 | /* |
@@ -1738,6 +1797,7 @@ register MULTARGID { | |||
1738 | modes M_CFG | 1797 | modes M_CFG |
1739 | size 2 | 1798 | size 2 |
1740 | count 2 | 1799 | count 2 |
1800 | dont_generate_debug_code | ||
1741 | } | 1801 | } |
1742 | 1802 | ||
1743 | /* | 1803 | /* |
@@ -1774,6 +1834,7 @@ register SCSIDAT { | |||
1774 | access_mode RW | 1834 | access_mode RW |
1775 | modes M_DFF0, M_DFF1, M_SCSI | 1835 | modes M_DFF0, M_DFF1, M_SCSI |
1776 | size 2 | 1836 | size 2 |
1837 | dont_generate_debug_code | ||
1777 | } | 1838 | } |
1778 | 1839 | ||
1779 | /* | 1840 | /* |
@@ -1796,6 +1857,7 @@ register TARGIDIN { | |||
1796 | count 2 | 1857 | count 2 |
1797 | field CLKOUT 0x80 | 1858 | field CLKOUT 0x80 |
1798 | field TARGID 0x0F | 1859 | field TARGID 0x0F |
1860 | dont_generate_debug_code | ||
1799 | } | 1861 | } |
1800 | 1862 | ||
1801 | /* | 1863 | /* |
@@ -1825,6 +1887,7 @@ register SBLKCTL { | |||
1825 | field ENAB40 0x08 /* LVD transceiver active */ | 1887 | field ENAB40 0x08 /* LVD transceiver active */ |
1826 | field ENAB20 0x04 /* SE/HVD transceiver active */ | 1888 | field ENAB20 0x04 /* SE/HVD transceiver active */ |
1827 | field SELWIDE 0x02 | 1889 | field SELWIDE 0x02 |
1890 | dont_generate_debug_code | ||
1828 | } | 1891 | } |
1829 | 1892 | ||
1830 | /* | 1893 | /* |
@@ -1842,6 +1905,7 @@ register OPTIONMODE { | |||
1842 | field ENDGFORMCHK 0x04 | 1905 | field ENDGFORMCHK 0x04 |
1843 | field AUTO_MSGOUT_DE 0x02 | 1906 | field AUTO_MSGOUT_DE 0x02 |
1844 | mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE | 1907 | mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE |
1908 | dont_generate_debug_code | ||
1845 | } | 1909 | } |
1846 | 1910 | ||
1847 | /* | 1911 | /* |
@@ -1876,6 +1940,7 @@ register CLRSINT0 { | |||
1876 | field CLROVERRUN 0x04 | 1940 | field CLROVERRUN 0x04 |
1877 | field CLRSPIORDY 0x02 | 1941 | field CLRSPIORDY 0x02 |
1878 | field CLRARBDO 0x01 | 1942 | field CLRARBDO 0x01 |
1943 | dont_generate_debug_code | ||
1879 | } | 1944 | } |
1880 | 1945 | ||
1881 | /* | 1946 | /* |
@@ -1929,6 +1994,7 @@ register CLRSINT1 { | |||
1929 | field CLRSCSIPERR 0x04 | 1994 | field CLRSCSIPERR 0x04 |
1930 | field CLRSTRB2FAST 0x02 | 1995 | field CLRSTRB2FAST 0x02 |
1931 | field CLRREQINIT 0x01 | 1996 | field CLRREQINIT 0x01 |
1997 | dont_generate_debug_code | ||
1932 | } | 1998 | } |
1933 | 1999 | ||
1934 | /* | 2000 | /* |
@@ -1962,6 +2028,7 @@ register CLRSINT2 { | |||
1962 | field CLRWIDE_RES 0x04 /* Modes 0 and 1 only */ | 2028 | field CLRWIDE_RES 0x04 /* Modes 0 and 1 only */ |
1963 | field CLRSDONE 0x02 /* Modes 0 and 1 only */ | 2029 | field CLRSDONE 0x02 /* Modes 0 and 1 only */ |
1964 | field CLRDMADONE 0x01 /* Modes 0 and 1 only */ | 2030 | field CLRDMADONE 0x01 /* Modes 0 and 1 only */ |
2031 | dont_generate_debug_code | ||
1965 | } | 2032 | } |
1966 | 2033 | ||
1967 | /* | 2034 | /* |
@@ -2002,6 +2069,7 @@ register LQISTATE { | |||
2002 | access_mode RO | 2069 | access_mode RO |
2003 | modes M_CFG | 2070 | modes M_CFG |
2004 | count 6 | 2071 | count 6 |
2072 | dont_generate_debug_code | ||
2005 | } | 2073 | } |
2006 | 2074 | ||
2007 | /* | 2075 | /* |
@@ -2022,6 +2090,7 @@ register LQOSTATE { | |||
2022 | access_mode RO | 2090 | access_mode RO |
2023 | modes M_CFG | 2091 | modes M_CFG |
2024 | count 2 | 2092 | count 2 |
2093 | dont_generate_debug_code | ||
2025 | } | 2094 | } |
2026 | 2095 | ||
2027 | /* | 2096 | /* |
@@ -2054,6 +2123,7 @@ register CLRLQIINT0 { | |||
2054 | field CLRLQIBADLQT 0x04 | 2123 | field CLRLQIBADLQT 0x04 |
2055 | field CLRLQIATNLQ 0x02 | 2124 | field CLRLQIATNLQ 0x02 |
2056 | field CLRLQIATNCMD 0x01 | 2125 | field CLRLQIATNCMD 0x01 |
2126 | dont_generate_debug_code | ||
2057 | } | 2127 | } |
2058 | 2128 | ||
2059 | /* | 2129 | /* |
@@ -2070,6 +2140,7 @@ register LQIMODE0 { | |||
2070 | field ENLQIBADLQT 0x04 | 2140 | field ENLQIBADLQT 0x04 |
2071 | field ENLQIATNLQ 0x02 | 2141 | field ENLQIATNLQ 0x02 |
2072 | field ENLQIATNCMD 0x01 | 2142 | field ENLQIATNCMD 0x01 |
2143 | dont_generate_debug_code | ||
2073 | } | 2144 | } |
2074 | 2145 | ||
2075 | /* | 2146 | /* |
@@ -2106,6 +2177,7 @@ register CLRLQIINT1 { | |||
2106 | field CLRLQIBADLQI 0x04 | 2177 | field CLRLQIBADLQI 0x04 |
2107 | field CLRLQIOVERI_LQ 0x02 | 2178 | field CLRLQIOVERI_LQ 0x02 |
2108 | field CLRLQIOVERI_NLQ 0x01 | 2179 | field CLRLQIOVERI_NLQ 0x01 |
2180 | dont_generate_debug_code | ||
2109 | } | 2181 | } |
2110 | 2182 | ||
2111 | /* | 2183 | /* |
@@ -2124,6 +2196,7 @@ register LQIMODE1 { | |||
2124 | field ENLQIBADLQI 0x04 | 2196 | field ENLQIBADLQI 0x04 |
2125 | field ENLQIOVERI_LQ 0x02 /* LQIOVERI1 */ | 2197 | field ENLQIOVERI_LQ 0x02 /* LQIOVERI1 */ |
2126 | field ENLQIOVERI_NLQ 0x01 /* LQIOVERI2 */ | 2198 | field ENLQIOVERI_NLQ 0x01 /* LQIOVERI2 */ |
2199 | dont_generate_debug_code | ||
2127 | } | 2200 | } |
2128 | 2201 | ||
2129 | /* | 2202 | /* |
@@ -2165,6 +2238,7 @@ register CLRSINT3 { | |||
2165 | count 3 | 2238 | count 3 |
2166 | field CLRNTRAMPERR 0x02 | 2239 | field CLRNTRAMPERR 0x02 |
2167 | field CLROSRAMPERR 0x01 | 2240 | field CLROSRAMPERR 0x01 |
2241 | dont_generate_debug_code | ||
2168 | } | 2242 | } |
2169 | 2243 | ||
2170 | /* | 2244 | /* |
@@ -2177,6 +2251,7 @@ register SIMODE3 { | |||
2177 | count 4 | 2251 | count 4 |
2178 | field ENNTRAMPERR 0x02 | 2252 | field ENNTRAMPERR 0x02 |
2179 | field ENOSRAMPERR 0x01 | 2253 | field ENOSRAMPERR 0x01 |
2254 | dont_generate_debug_code | ||
2180 | } | 2255 | } |
2181 | 2256 | ||
2182 | /* | 2257 | /* |
@@ -2207,6 +2282,7 @@ register CLRLQOINT0 { | |||
2207 | field CLRLQOATNLQ 0x04 | 2282 | field CLRLQOATNLQ 0x04 |
2208 | field CLRLQOATNPKT 0x02 | 2283 | field CLRLQOATNPKT 0x02 |
2209 | field CLRLQOTCRC 0x01 | 2284 | field CLRLQOTCRC 0x01 |
2285 | dont_generate_debug_code | ||
2210 | } | 2286 | } |
2211 | 2287 | ||
2212 | /* | 2288 | /* |
@@ -2222,6 +2298,7 @@ register LQOMODE0 { | |||
2222 | field ENLQOATNLQ 0x04 | 2298 | field ENLQOATNLQ 0x04 |
2223 | field ENLQOATNPKT 0x02 | 2299 | field ENLQOATNPKT 0x02 |
2224 | field ENLQOTCRC 0x01 | 2300 | field ENLQOTCRC 0x01 |
2301 | dont_generate_debug_code | ||
2225 | } | 2302 | } |
2226 | 2303 | ||
2227 | /* | 2304 | /* |
@@ -2251,6 +2328,7 @@ register CLRLQOINT1 { | |||
2251 | field CLRLQOBADQAS 0x04 | 2328 | field CLRLQOBADQAS 0x04 |
2252 | field CLRLQOBUSFREE 0x02 | 2329 | field CLRLQOBUSFREE 0x02 |
2253 | field CLRLQOPHACHGINPKT 0x01 | 2330 | field CLRLQOPHACHGINPKT 0x01 |
2331 | dont_generate_debug_code | ||
2254 | } | 2332 | } |
2255 | 2333 | ||
2256 | /* | 2334 | /* |
@@ -2266,6 +2344,7 @@ register LQOMODE1 { | |||
2266 | field ENLQOBADQAS 0x04 | 2344 | field ENLQOBADQAS 0x04 |
2267 | field ENLQOBUSFREE 0x02 | 2345 | field ENLQOBUSFREE 0x02 |
2268 | field ENLQOPHACHGINPKT 0x01 | 2346 | field ENLQOPHACHGINPKT 0x01 |
2347 | dont_generate_debug_code | ||
2269 | } | 2348 | } |
2270 | 2349 | ||
2271 | /* | 2350 | /* |
@@ -2289,6 +2368,7 @@ register OS_SPACE_CNT { | |||
2289 | access_mode RO | 2368 | access_mode RO |
2290 | modes M_CFG | 2369 | modes M_CFG |
2291 | count 2 | 2370 | count 2 |
2371 | dont_generate_debug_code | ||
2292 | } | 2372 | } |
2293 | 2373 | ||
2294 | /* | 2374 | /* |
@@ -2318,6 +2398,7 @@ register GSFIFO { | |||
2318 | access_mode RO | 2398 | access_mode RO |
2319 | size 2 | 2399 | size 2 |
2320 | modes M_DFF0, M_DFF1, M_SCSI | 2400 | modes M_DFF0, M_DFF1, M_SCSI |
2401 | dont_generate_debug_code | ||
2321 | } | 2402 | } |
2322 | 2403 | ||
2323 | /* | 2404 | /* |
@@ -2341,6 +2422,7 @@ register NEXTSCB { | |||
2341 | access_mode RW | 2422 | access_mode RW |
2342 | size 2 | 2423 | size 2 |
2343 | modes M_SCSI | 2424 | modes M_SCSI |
2425 | dont_generate_debug_code | ||
2344 | } | 2426 | } |
2345 | 2427 | ||
2346 | /* | 2428 | /* |
@@ -2357,6 +2439,7 @@ register LQOSCSCTL { | |||
2357 | field LQOBUSETDLY 0x40 | 2439 | field LQOBUSETDLY 0x40 |
2358 | field LQONOHOLDLACK 0x02 | 2440 | field LQONOHOLDLACK 0x02 |
2359 | field LQONOCHKOVER 0x01 | 2441 | field LQONOCHKOVER 0x01 |
2442 | dont_generate_debug_code | ||
2360 | } | 2443 | } |
2361 | 2444 | ||
2362 | /* | 2445 | /* |
@@ -2389,6 +2472,7 @@ register CLRSEQINTSRC { | |||
2389 | field CLRCFG4TSTAT 0x04 | 2472 | field CLRCFG4TSTAT 0x04 |
2390 | field CLRCFG4ICMD 0x02 | 2473 | field CLRCFG4ICMD 0x02 |
2391 | field CLRCFG4TCMD 0x01 | 2474 | field CLRCFG4TCMD 0x01 |
2475 | dont_generate_debug_code | ||
2392 | } | 2476 | } |
2393 | 2477 | ||
2394 | /* | 2478 | /* |
@@ -2415,6 +2499,7 @@ register CURRSCB { | |||
2415 | access_mode RW | 2499 | access_mode RW |
2416 | size 2 | 2500 | size 2 |
2417 | modes M_SCSI | 2501 | modes M_SCSI |
2502 | dont_generate_debug_code | ||
2418 | } | 2503 | } |
2419 | 2504 | ||
2420 | /* | 2505 | /* |
@@ -2472,6 +2557,7 @@ register LASTSCB { | |||
2472 | access_mode RW | 2557 | access_mode RW |
2473 | size 2 | 2558 | size 2 |
2474 | modes M_SCSI | 2559 | modes M_SCSI |
2560 | dont_generate_debug_code | ||
2475 | } | 2561 | } |
2476 | 2562 | ||
2477 | /* | 2563 | /* |
@@ -2494,6 +2580,7 @@ register SHADDR { | |||
2494 | access_mode RO | 2580 | access_mode RO |
2495 | size 8 | 2581 | size 8 |
2496 | modes M_DFF0, M_DFF1 | 2582 | modes M_DFF0, M_DFF1 |
2583 | dont_generate_debug_code | ||
2497 | } | 2584 | } |
2498 | 2585 | ||
2499 | /* | 2586 | /* |
@@ -2513,6 +2600,7 @@ register NEGOADDR { | |||
2513 | address 0x060 | 2600 | address 0x060 |
2514 | access_mode RW | 2601 | access_mode RW |
2515 | modes M_SCSI | 2602 | modes M_SCSI |
2603 | dont_generate_debug_code | ||
2516 | } | 2604 | } |
2517 | 2605 | ||
2518 | /* | 2606 | /* |
@@ -2523,6 +2611,7 @@ register NEGPERIOD { | |||
2523 | access_mode RW | 2611 | access_mode RW |
2524 | modes M_SCSI | 2612 | modes M_SCSI |
2525 | count 1 | 2613 | count 1 |
2614 | dont_generate_debug_code | ||
2526 | } | 2615 | } |
2527 | 2616 | ||
2528 | /* | 2617 | /* |
@@ -2543,6 +2632,7 @@ register NEGOFFSET { | |||
2543 | access_mode RW | 2632 | access_mode RW |
2544 | modes M_SCSI | 2633 | modes M_SCSI |
2545 | count 1 | 2634 | count 1 |
2635 | dont_generate_debug_code | ||
2546 | } | 2636 | } |
2547 | 2637 | ||
2548 | /* | 2638 | /* |
@@ -2557,6 +2647,7 @@ register NEGPPROPTS { | |||
2557 | field PPROPT_QAS 0x04 | 2647 | field PPROPT_QAS 0x04 |
2558 | field PPROPT_DT 0x02 | 2648 | field PPROPT_DT 0x02 |
2559 | field PPROPT_IUT 0x01 | 2649 | field PPROPT_IUT 0x01 |
2650 | dont_generate_debug_code | ||
2560 | } | 2651 | } |
2561 | 2652 | ||
2562 | /* | 2653 | /* |
@@ -2573,6 +2664,7 @@ register NEGCONOPTS { | |||
2573 | field ENAUTOATNI 0x04 | 2664 | field ENAUTOATNI 0x04 |
2574 | field ENAUTOATNO 0x02 | 2665 | field ENAUTOATNO 0x02 |
2575 | field WIDEXFER 0x01 | 2666 | field WIDEXFER 0x01 |
2667 | dont_generate_debug_code | ||
2576 | } | 2668 | } |
2577 | 2669 | ||
2578 | /* | 2670 | /* |
@@ -2583,6 +2675,7 @@ register ANNEXCOL { | |||
2583 | access_mode RW | 2675 | access_mode RW |
2584 | modes M_SCSI | 2676 | modes M_SCSI |
2585 | count 7 | 2677 | count 7 |
2678 | dont_generate_debug_code | ||
2586 | } | 2679 | } |
2587 | 2680 | ||
2588 | /* | 2681 | /* |
@@ -2602,6 +2695,7 @@ register SCSCHKN { | |||
2602 | field DFFACTCLR 0x04 | 2695 | field DFFACTCLR 0x04 |
2603 | field SHVALIDSTDIS 0x02 | 2696 | field SHVALIDSTDIS 0x02 |
2604 | field LSTSGCLRDIS 0x01 | 2697 | field LSTSGCLRDIS 0x01 |
2698 | dont_generate_debug_code | ||
2605 | } | 2699 | } |
2606 | 2700 | ||
2607 | const AHD_ANNEXCOL_PER_DEV0 4 | 2701 | const AHD_ANNEXCOL_PER_DEV0 4 |
@@ -2635,6 +2729,7 @@ register ANNEXDAT { | |||
2635 | access_mode RW | 2729 | access_mode RW |
2636 | modes M_SCSI | 2730 | modes M_SCSI |
2637 | count 3 | 2731 | count 3 |
2732 | dont_generate_debug_code | ||
2638 | } | 2733 | } |
2639 | 2734 | ||
2640 | /* | 2735 | /* |
@@ -2645,6 +2740,7 @@ register IOWNID { | |||
2645 | address 0x067 | 2740 | address 0x067 |
2646 | access_mode RW | 2741 | access_mode RW |
2647 | modes M_SCSI | 2742 | modes M_SCSI |
2743 | dont_generate_debug_code | ||
2648 | } | 2744 | } |
2649 | 2745 | ||
2650 | /* | 2746 | /* |
@@ -2671,6 +2767,7 @@ register TOWNID { | |||
2671 | access_mode RW | 2767 | access_mode RW |
2672 | modes M_SCSI | 2768 | modes M_SCSI |
2673 | count 2 | 2769 | count 2 |
2770 | dont_generate_debug_code | ||
2674 | } | 2771 | } |
2675 | 2772 | ||
2676 | /* | 2773 | /* |
@@ -2702,6 +2799,7 @@ register SHCNT { | |||
2702 | access_mode RW | 2799 | access_mode RW |
2703 | size 3 | 2800 | size 3 |
2704 | modes M_DFF0, M_DFF1 | 2801 | modes M_DFF0, M_DFF1 |
2802 | dont_generate_debug_code | ||
2705 | } | 2803 | } |
2706 | 2804 | ||
2707 | /* | 2805 | /* |
@@ -2789,6 +2887,7 @@ register SCBPTR { | |||
2789 | access_mode RW | 2887 | access_mode RW |
2790 | size 2 | 2888 | size 2 |
2791 | modes M_DFF0, M_DFF1, M_CCHAN, M_SCSI | 2889 | modes M_DFF0, M_DFF1, M_CCHAN, M_SCSI |
2890 | dont_generate_debug_code | ||
2792 | } | 2891 | } |
2793 | 2892 | ||
2794 | /* | 2893 | /* |
@@ -2816,6 +2915,7 @@ register SCBAUTOPTR { | |||
2816 | field AUSCBPTR_EN 0x80 | 2915 | field AUSCBPTR_EN 0x80 |
2817 | field SCBPTR_ADDR 0x38 | 2916 | field SCBPTR_ADDR 0x38 |
2818 | field SCBPTR_OFF 0x07 | 2917 | field SCBPTR_OFF 0x07 |
2918 | dont_generate_debug_code | ||
2819 | } | 2919 | } |
2820 | 2920 | ||
2821 | /* | 2921 | /* |
@@ -2825,6 +2925,7 @@ register CCSGADDR { | |||
2825 | address 0x0AC | 2925 | address 0x0AC |
2826 | access_mode RW | 2926 | access_mode RW |
2827 | modes M_DFF0, M_DFF1 | 2927 | modes M_DFF0, M_DFF1 |
2928 | dont_generate_debug_code | ||
2828 | } | 2929 | } |
2829 | 2930 | ||
2830 | /* | 2931 | /* |
@@ -2834,6 +2935,7 @@ register CCSCBADDR { | |||
2834 | address 0x0AC | 2935 | address 0x0AC |
2835 | access_mode RW | 2936 | access_mode RW |
2836 | modes M_CCHAN | 2937 | modes M_CCHAN |
2938 | dont_generate_debug_code | ||
2837 | } | 2939 | } |
2838 | 2940 | ||
2839 | /* | 2941 | /* |
@@ -2899,6 +3001,7 @@ register CCSGRAM { | |||
2899 | address 0x0B0 | 3001 | address 0x0B0 |
2900 | access_mode RW | 3002 | access_mode RW |
2901 | modes M_DFF0, M_DFF1 | 3003 | modes M_DFF0, M_DFF1 |
3004 | dont_generate_debug_code | ||
2902 | } | 3005 | } |
2903 | 3006 | ||
2904 | /* | 3007 | /* |
@@ -2908,6 +3011,7 @@ register CCSCBRAM { | |||
2908 | address 0x0B0 | 3011 | address 0x0B0 |
2909 | access_mode RW | 3012 | access_mode RW |
2910 | modes M_CCHAN | 3013 | modes M_CCHAN |
3014 | dont_generate_debug_code | ||
2911 | } | 3015 | } |
2912 | 3016 | ||
2913 | /* | 3017 | /* |
@@ -2958,6 +3062,7 @@ register BRDDAT { | |||
2958 | access_mode RW | 3062 | access_mode RW |
2959 | modes M_SCSI | 3063 | modes M_SCSI |
2960 | count 2 | 3064 | count 2 |
3065 | dont_generate_debug_code | ||
2961 | } | 3066 | } |
2962 | 3067 | ||
2963 | /* | 3068 | /* |
@@ -2974,6 +3079,7 @@ register BRDCTL { | |||
2974 | field BRDEN 0x04 | 3079 | field BRDEN 0x04 |
2975 | field BRDRW 0x02 | 3080 | field BRDRW 0x02 |
2976 | field BRDSTB 0x01 | 3081 | field BRDSTB 0x01 |
3082 | dont_generate_debug_code | ||
2977 | } | 3083 | } |
2978 | 3084 | ||
2979 | /* | 3085 | /* |
@@ -2984,6 +3090,7 @@ register SEEADR { | |||
2984 | access_mode RW | 3090 | access_mode RW |
2985 | modes M_SCSI | 3091 | modes M_SCSI |
2986 | count 4 | 3092 | count 4 |
3093 | dont_generate_debug_code | ||
2987 | } | 3094 | } |
2988 | 3095 | ||
2989 | /* | 3096 | /* |
@@ -2995,6 +3102,7 @@ register SEEDAT { | |||
2995 | size 2 | 3102 | size 2 |
2996 | modes M_SCSI | 3103 | modes M_SCSI |
2997 | count 4 | 3104 | count 4 |
3105 | dont_generate_debug_code | ||
2998 | } | 3106 | } |
2999 | 3107 | ||
3000 | /* | 3108 | /* |
@@ -3011,6 +3119,7 @@ register SEESTAT { | |||
3011 | field SEEARBACK 0x04 | 3119 | field SEEARBACK 0x04 |
3012 | field SEEBUSY 0x02 | 3120 | field SEEBUSY 0x02 |
3013 | field SEESTART 0x01 | 3121 | field SEESTART 0x01 |
3122 | dont_generate_debug_code | ||
3014 | } | 3123 | } |
3015 | 3124 | ||
3016 | /* | 3125 | /* |
@@ -3036,6 +3145,7 @@ register SEECTL { | |||
3036 | mask SEEOP_EWDS 0x40 | 3145 | mask SEEOP_EWDS 0x40 |
3037 | field SEERST 0x02 | 3146 | field SEERST 0x02 |
3038 | field SEESTART 0x01 | 3147 | field SEESTART 0x01 |
3148 | dont_generate_debug_code | ||
3039 | } | 3149 | } |
3040 | 3150 | ||
3041 | const SEEOP_ERAL_ADDR 0x80 | 3151 | const SEEOP_ERAL_ADDR 0x80 |
@@ -3050,6 +3160,7 @@ register SCBCNT { | |||
3050 | address 0x0BF | 3160 | address 0x0BF |
3051 | access_mode RW | 3161 | access_mode RW |
3052 | modes M_SCSI | 3162 | modes M_SCSI |
3163 | dont_generate_debug_code | ||
3053 | } | 3164 | } |
3054 | 3165 | ||
3055 | /* | 3166 | /* |
@@ -3061,6 +3172,7 @@ register DFWADDR { | |||
3061 | access_mode RW | 3172 | access_mode RW |
3062 | size 2 | 3173 | size 2 |
3063 | modes M_DFF0, M_DFF1 | 3174 | modes M_DFF0, M_DFF1 |
3175 | dont_generate_debug_code | ||
3064 | } | 3176 | } |
3065 | 3177 | ||
3066 | /* | 3178 | /* |
@@ -3087,6 +3199,7 @@ register DSPDATACTL { | |||
3087 | field DESQDIS 0x10 | 3199 | field DESQDIS 0x10 |
3088 | field RCVROFFSTDIS 0x04 | 3200 | field RCVROFFSTDIS 0x04 |
3089 | field XMITOFFSTDIS 0x02 | 3201 | field XMITOFFSTDIS 0x02 |
3202 | dont_generate_debug_code | ||
3090 | } | 3203 | } |
3091 | 3204 | ||
3092 | /* | 3205 | /* |
@@ -3132,6 +3245,7 @@ register DFDAT { | |||
3132 | address 0x0C4 | 3245 | address 0x0C4 |
3133 | access_mode RW | 3246 | access_mode RW |
3134 | modes M_DFF0, M_DFF1 | 3247 | modes M_DFF0, M_DFF1 |
3248 | dont_generate_debug_code | ||
3135 | } | 3249 | } |
3136 | 3250 | ||
3137 | /* | 3251 | /* |
@@ -3144,6 +3258,7 @@ register DSPSELECT { | |||
3144 | count 1 | 3258 | count 1 |
3145 | field AUTOINCEN 0x80 | 3259 | field AUTOINCEN 0x80 |
3146 | field DSPSEL 0x1F | 3260 | field DSPSEL 0x1F |
3261 | dont_generate_debug_code | ||
3147 | } | 3262 | } |
3148 | 3263 | ||
3149 | const NUMDSPS 0x14 | 3264 | const NUMDSPS 0x14 |
@@ -3158,6 +3273,7 @@ register WRTBIASCTL { | |||
3158 | count 3 | 3273 | count 3 |
3159 | field AUTOXBCDIS 0x80 | 3274 | field AUTOXBCDIS 0x80 |
3160 | field XMITMANVAL 0x3F | 3275 | field XMITMANVAL 0x3F |
3276 | dont_generate_debug_code | ||
3161 | } | 3277 | } |
3162 | 3278 | ||
3163 | /* | 3279 | /* |
@@ -3316,6 +3432,7 @@ register FLAGS { | |||
3316 | count 23 | 3432 | count 23 |
3317 | field ZERO 0x02 | 3433 | field ZERO 0x02 |
3318 | field CARRY 0x01 | 3434 | field CARRY 0x01 |
3435 | dont_generate_debug_code | ||
3319 | } | 3436 | } |
3320 | 3437 | ||
3321 | /* | 3438 | /* |
@@ -3344,6 +3461,7 @@ register SEQRAM { | |||
3344 | address 0x0DA | 3461 | address 0x0DA |
3345 | access_mode RW | 3462 | access_mode RW |
3346 | count 2 | 3463 | count 2 |
3464 | dont_generate_debug_code | ||
3347 | } | 3465 | } |
3348 | 3466 | ||
3349 | /* | 3467 | /* |
@@ -3355,6 +3473,7 @@ register PRGMCNT { | |||
3355 | access_mode RW | 3473 | access_mode RW |
3356 | size 2 | 3474 | size 2 |
3357 | count 5 | 3475 | count 5 |
3476 | dont_generate_debug_code | ||
3358 | } | 3477 | } |
3359 | 3478 | ||
3360 | /* | 3479 | /* |
@@ -3364,6 +3483,7 @@ register ACCUM { | |||
3364 | address 0x0E0 | 3483 | address 0x0E0 |
3365 | access_mode RW | 3484 | access_mode RW |
3366 | accumulator | 3485 | accumulator |
3486 | dont_generate_debug_code | ||
3367 | } | 3487 | } |
3368 | 3488 | ||
3369 | /* | 3489 | /* |
@@ -3380,6 +3500,7 @@ register SINDEX { | |||
3380 | access_mode RW | 3500 | access_mode RW |
3381 | size 2 | 3501 | size 2 |
3382 | sindex | 3502 | sindex |
3503 | dont_generate_debug_code | ||
3383 | } | 3504 | } |
3384 | 3505 | ||
3385 | /* | 3506 | /* |
@@ -3390,6 +3511,7 @@ register DINDEX { | |||
3390 | address 0x0E4 | 3511 | address 0x0E4 |
3391 | access_mode RW | 3512 | access_mode RW |
3392 | size 2 | 3513 | size 2 |
3514 | dont_generate_debug_code | ||
3393 | } | 3515 | } |
3394 | 3516 | ||
3395 | /* | 3517 | /* |
@@ -3415,6 +3537,7 @@ register ALLONES { | |||
3415 | address 0x0E8 | 3537 | address 0x0E8 |
3416 | access_mode RO | 3538 | access_mode RO |
3417 | allones | 3539 | allones |
3540 | dont_generate_debug_code | ||
3418 | } | 3541 | } |
3419 | 3542 | ||
3420 | /* | 3543 | /* |
@@ -3425,6 +3548,7 @@ register ALLZEROS { | |||
3425 | address 0x0EA | 3548 | address 0x0EA |
3426 | access_mode RO | 3549 | access_mode RO |
3427 | allzeros | 3550 | allzeros |
3551 | dont_generate_debug_code | ||
3428 | } | 3552 | } |
3429 | 3553 | ||
3430 | /* | 3554 | /* |
@@ -3435,6 +3559,7 @@ register NONE { | |||
3435 | address 0x0EA | 3559 | address 0x0EA |
3436 | access_mode WO | 3560 | access_mode WO |
3437 | none | 3561 | none |
3562 | dont_generate_debug_code | ||
3438 | } | 3563 | } |
3439 | 3564 | ||
3440 | /* | 3565 | /* |
@@ -3445,6 +3570,7 @@ register NONE { | |||
3445 | register SINDIR { | 3570 | register SINDIR { |
3446 | address 0x0EC | 3571 | address 0x0EC |
3447 | access_mode RO | 3572 | access_mode RO |
3573 | dont_generate_debug_code | ||
3448 | } | 3574 | } |
3449 | 3575 | ||
3450 | /* | 3576 | /* |
@@ -3455,6 +3581,7 @@ register SINDIR { | |||
3455 | register DINDIR { | 3581 | register DINDIR { |
3456 | address 0x0ED | 3582 | address 0x0ED |
3457 | access_mode WO | 3583 | access_mode WO |
3584 | dont_generate_debug_code | ||
3458 | } | 3585 | } |
3459 | 3586 | ||
3460 | /* | 3587 | /* |
@@ -3479,6 +3606,7 @@ register FUNCTION1 { | |||
3479 | register STACK { | 3606 | register STACK { |
3480 | address 0x0F2 | 3607 | address 0x0F2 |
3481 | access_mode RW | 3608 | access_mode RW |
3609 | dont_generate_debug_code | ||
3482 | } | 3610 | } |
3483 | 3611 | ||
3484 | /* | 3612 | /* |
@@ -3491,6 +3619,7 @@ register INTVEC1_ADDR { | |||
3491 | size 2 | 3619 | size 2 |
3492 | modes M_CFG | 3620 | modes M_CFG |
3493 | count 1 | 3621 | count 1 |
3622 | dont_generate_debug_code | ||
3494 | } | 3623 | } |
3495 | 3624 | ||
3496 | /* | 3625 | /* |
@@ -3503,6 +3632,7 @@ register CURADDR { | |||
3503 | size 2 | 3632 | size 2 |
3504 | modes M_SCSI | 3633 | modes M_SCSI |
3505 | count 2 | 3634 | count 2 |
3635 | dont_generate_debug_code | ||
3506 | } | 3636 | } |
3507 | 3637 | ||
3508 | /* | 3638 | /* |
@@ -3515,6 +3645,7 @@ register INTVEC2_ADDR { | |||
3515 | size 2 | 3645 | size 2 |
3516 | modes M_CFG | 3646 | modes M_CFG |
3517 | count 1 | 3647 | count 1 |
3648 | dont_generate_debug_code | ||
3518 | } | 3649 | } |
3519 | 3650 | ||
3520 | /* | 3651 | /* |
@@ -3543,12 +3674,14 @@ scratch_ram { | |||
3543 | modes 0, 1, 2, 3 | 3674 | modes 0, 1, 2, 3 |
3544 | REG0 { | 3675 | REG0 { |
3545 | size 2 | 3676 | size 2 |
3677 | dont_generate_debug_code | ||
3546 | } | 3678 | } |
3547 | REG1 { | 3679 | REG1 { |
3548 | size 2 | 3680 | size 2 |
3549 | } | 3681 | } |
3550 | REG_ISR { | 3682 | REG_ISR { |
3551 | size 2 | 3683 | size 2 |
3684 | dont_generate_debug_code | ||
3552 | } | 3685 | } |
3553 | SG_STATE { | 3686 | SG_STATE { |
3554 | size 1 | 3687 | size 1 |
@@ -3572,9 +3705,11 @@ scratch_ram { | |||
3572 | modes 0, 1, 2, 3 | 3705 | modes 0, 1, 2, 3 |
3573 | LONGJMP_ADDR { | 3706 | LONGJMP_ADDR { |
3574 | size 2 | 3707 | size 2 |
3708 | dont_generate_debug_code | ||
3575 | } | 3709 | } |
3576 | ACCUM_SAVE { | 3710 | ACCUM_SAVE { |
3577 | size 1 | 3711 | size 1 |
3712 | dont_generate_debug_code | ||
3578 | } | 3713 | } |
3579 | } | 3714 | } |
3580 | 3715 | ||
@@ -3591,18 +3726,22 @@ scratch_ram { | |||
3591 | */ | 3726 | */ |
3592 | WAITING_SCB_TAILS { | 3727 | WAITING_SCB_TAILS { |
3593 | size 32 | 3728 | size 32 |
3729 | dont_generate_debug_code | ||
3594 | } | 3730 | } |
3595 | WAITING_TID_HEAD { | 3731 | WAITING_TID_HEAD { |
3596 | size 2 | 3732 | size 2 |
3733 | dont_generate_debug_code | ||
3597 | } | 3734 | } |
3598 | WAITING_TID_TAIL { | 3735 | WAITING_TID_TAIL { |
3599 | size 2 | 3736 | size 2 |
3737 | dont_generate_debug_code | ||
3600 | } | 3738 | } |
3601 | /* | 3739 | /* |
3602 | * SCBID of the next SCB in the new SCB queue. | 3740 | * SCBID of the next SCB in the new SCB queue. |
3603 | */ | 3741 | */ |
3604 | NEXT_QUEUED_SCB_ADDR { | 3742 | NEXT_QUEUED_SCB_ADDR { |
3605 | size 4 | 3743 | size 4 |
3744 | dont_generate_debug_code | ||
3606 | } | 3745 | } |
3607 | /* | 3746 | /* |
3608 | * head of list of SCBs that have | 3747 | * head of list of SCBs that have |
@@ -3611,6 +3750,7 @@ scratch_ram { | |||
3611 | */ | 3750 | */ |
3612 | COMPLETE_SCB_HEAD { | 3751 | COMPLETE_SCB_HEAD { |
3613 | size 2 | 3752 | size 2 |
3753 | dont_generate_debug_code | ||
3614 | } | 3754 | } |
3615 | /* | 3755 | /* |
3616 | * The list of completed SCBs in | 3756 | * The list of completed SCBs in |
@@ -3618,6 +3758,7 @@ scratch_ram { | |||
3618 | */ | 3758 | */ |
3619 | COMPLETE_SCB_DMAINPROG_HEAD { | 3759 | COMPLETE_SCB_DMAINPROG_HEAD { |
3620 | size 2 | 3760 | size 2 |
3761 | dont_generate_debug_code | ||
3621 | } | 3762 | } |
3622 | /* | 3763 | /* |
3623 | * head of list of SCBs that have | 3764 | * head of list of SCBs that have |
@@ -3626,6 +3767,7 @@ scratch_ram { | |||
3626 | */ | 3767 | */ |
3627 | COMPLETE_DMA_SCB_HEAD { | 3768 | COMPLETE_DMA_SCB_HEAD { |
3628 | size 2 | 3769 | size 2 |
3770 | dont_generate_debug_code | ||
3629 | } | 3771 | } |
3630 | /* | 3772 | /* |
3631 | * tail of list of SCBs that have | 3773 | * tail of list of SCBs that have |
@@ -3634,6 +3776,7 @@ scratch_ram { | |||
3634 | */ | 3776 | */ |
3635 | COMPLETE_DMA_SCB_TAIL { | 3777 | COMPLETE_DMA_SCB_TAIL { |
3636 | size 2 | 3778 | size 2 |
3779 | dont_generate_debug_code | ||
3637 | } | 3780 | } |
3638 | /* | 3781 | /* |
3639 | * head of list of SCBs that have | 3782 | * head of list of SCBs that have |
@@ -3643,6 +3786,7 @@ scratch_ram { | |||
3643 | */ | 3786 | */ |
3644 | COMPLETE_ON_QFREEZE_HEAD { | 3787 | COMPLETE_ON_QFREEZE_HEAD { |
3645 | size 2 | 3788 | size 2 |
3789 | dont_generate_debug_code | ||
3646 | } | 3790 | } |
3647 | /* | 3791 | /* |
3648 | * Counting semaphore to prevent new select-outs | 3792 | * Counting semaphore to prevent new select-outs |
@@ -3667,6 +3811,7 @@ scratch_ram { | |||
3667 | */ | 3811 | */ |
3668 | MSG_OUT { | 3812 | MSG_OUT { |
3669 | size 1 | 3813 | size 1 |
3814 | dont_generate_debug_code | ||
3670 | } | 3815 | } |
3671 | /* Parameters for DMA Logic */ | 3816 | /* Parameters for DMA Logic */ |
3672 | DMAPARAMS { | 3817 | DMAPARAMS { |
@@ -3682,6 +3827,7 @@ scratch_ram { | |||
3682 | field DIRECTION 0x04 /* Set indicates PCI->SCSI */ | 3827 | field DIRECTION 0x04 /* Set indicates PCI->SCSI */ |
3683 | field FIFOFLUSH 0x02 | 3828 | field FIFOFLUSH 0x02 |
3684 | field FIFORESET 0x01 | 3829 | field FIFORESET 0x01 |
3830 | dont_generate_debug_code | ||
3685 | } | 3831 | } |
3686 | SEQ_FLAGS { | 3832 | SEQ_FLAGS { |
3687 | size 1 | 3833 | size 1 |
@@ -3703,9 +3849,11 @@ scratch_ram { | |||
3703 | */ | 3849 | */ |
3704 | SAVED_SCSIID { | 3850 | SAVED_SCSIID { |
3705 | size 1 | 3851 | size 1 |
3852 | dont_generate_debug_code | ||
3706 | } | 3853 | } |
3707 | SAVED_LUN { | 3854 | SAVED_LUN { |
3708 | size 1 | 3855 | size 1 |
3856 | dont_generate_debug_code | ||
3709 | } | 3857 | } |
3710 | /* | 3858 | /* |
3711 | * The last bus phase as seen by the sequencer. | 3859 | * The last bus phase as seen by the sequencer. |
@@ -3733,6 +3881,7 @@ scratch_ram { | |||
3733 | */ | 3881 | */ |
3734 | QOUTFIFO_ENTRY_VALID_TAG { | 3882 | QOUTFIFO_ENTRY_VALID_TAG { |
3735 | size 1 | 3883 | size 1 |
3884 | dont_generate_debug_code | ||
3736 | } | 3885 | } |
3737 | /* | 3886 | /* |
3738 | * Kernel and sequencer offsets into the queue of | 3887 | * Kernel and sequencer offsets into the queue of |
@@ -3742,10 +3891,12 @@ scratch_ram { | |||
3742 | KERNEL_TQINPOS { | 3891 | KERNEL_TQINPOS { |
3743 | size 1 | 3892 | size 1 |
3744 | count 1 | 3893 | count 1 |
3894 | dont_generate_debug_code | ||
3745 | } | 3895 | } |
3746 | TQINPOS { | 3896 | TQINPOS { |
3747 | size 1 | 3897 | size 1 |
3748 | count 8 | 3898 | count 8 |
3899 | dont_generate_debug_code | ||
3749 | } | 3900 | } |
3750 | /* | 3901 | /* |
3751 | * Base address of our shared data with the kernel driver in host | 3902 | * Base address of our shared data with the kernel driver in host |
@@ -3754,6 +3905,7 @@ scratch_ram { | |||
3754 | */ | 3905 | */ |
3755 | SHARED_DATA_ADDR { | 3906 | SHARED_DATA_ADDR { |
3756 | size 4 | 3907 | size 4 |
3908 | dont_generate_debug_code | ||
3757 | } | 3909 | } |
3758 | /* | 3910 | /* |
3759 | * Pointer to location in host memory for next | 3911 | * Pointer to location in host memory for next |
@@ -3761,6 +3913,7 @@ scratch_ram { | |||
3761 | */ | 3913 | */ |
3762 | QOUTFIFO_NEXT_ADDR { | 3914 | QOUTFIFO_NEXT_ADDR { |
3763 | size 4 | 3915 | size 4 |
3916 | dont_generate_debug_code | ||
3764 | } | 3917 | } |
3765 | ARG_1 { | 3918 | ARG_1 { |
3766 | size 1 | 3919 | size 1 |
@@ -3773,11 +3926,13 @@ scratch_ram { | |||
3773 | mask CONT_MSG_LOOP_READ 0x03 | 3926 | mask CONT_MSG_LOOP_READ 0x03 |
3774 | mask CONT_MSG_LOOP_TARG 0x02 | 3927 | mask CONT_MSG_LOOP_TARG 0x02 |
3775 | alias RETURN_1 | 3928 | alias RETURN_1 |
3929 | dont_generate_debug_code | ||
3776 | } | 3930 | } |
3777 | ARG_2 { | 3931 | ARG_2 { |
3778 | size 1 | 3932 | size 1 |
3779 | count 1 | 3933 | count 1 |
3780 | alias RETURN_2 | 3934 | alias RETURN_2 |
3935 | dont_generate_debug_code | ||
3781 | } | 3936 | } |
3782 | 3937 | ||
3783 | /* | 3938 | /* |
@@ -3785,6 +3940,7 @@ scratch_ram { | |||
3785 | */ | 3940 | */ |
3786 | LAST_MSG { | 3941 | LAST_MSG { |
3787 | size 1 | 3942 | size 1 |
3943 | dont_generate_debug_code | ||
3788 | } | 3944 | } |
3789 | 3945 | ||
3790 | /* | 3946 | /* |
@@ -3801,6 +3957,7 @@ scratch_ram { | |||
3801 | field MANUALP 0x0C | 3957 | field MANUALP 0x0C |
3802 | field ENAUTOATNP 0x02 | 3958 | field ENAUTOATNP 0x02 |
3803 | field ALTSTIM 0x01 | 3959 | field ALTSTIM 0x01 |
3960 | dont_generate_debug_code | ||
3804 | } | 3961 | } |
3805 | 3962 | ||
3806 | /* | 3963 | /* |
@@ -3809,6 +3966,7 @@ scratch_ram { | |||
3809 | INITIATOR_TAG { | 3966 | INITIATOR_TAG { |
3810 | size 1 | 3967 | size 1 |
3811 | count 1 | 3968 | count 1 |
3969 | dont_generate_debug_code | ||
3812 | } | 3970 | } |
3813 | 3971 | ||
3814 | SEQ_FLAGS2 { | 3972 | SEQ_FLAGS2 { |
@@ -3820,6 +3978,7 @@ scratch_ram { | |||
3820 | 3978 | ||
3821 | ALLOCFIFO_SCBPTR { | 3979 | ALLOCFIFO_SCBPTR { |
3822 | size 2 | 3980 | size 2 |
3981 | dont_generate_debug_code | ||
3823 | } | 3982 | } |
3824 | 3983 | ||
3825 | /* | 3984 | /* |
@@ -3829,6 +3988,7 @@ scratch_ram { | |||
3829 | */ | 3988 | */ |
3830 | INT_COALESCING_TIMER { | 3989 | INT_COALESCING_TIMER { |
3831 | size 2 | 3990 | size 2 |
3991 | dont_generate_debug_code | ||
3832 | } | 3992 | } |
3833 | 3993 | ||
3834 | /* | 3994 | /* |
@@ -3838,6 +3998,7 @@ scratch_ram { | |||
3838 | */ | 3998 | */ |
3839 | INT_COALESCING_MAXCMDS { | 3999 | INT_COALESCING_MAXCMDS { |
3840 | size 1 | 4000 | size 1 |
4001 | dont_generate_debug_code | ||
3841 | } | 4002 | } |
3842 | 4003 | ||
3843 | /* | 4004 | /* |
@@ -3846,6 +4007,7 @@ scratch_ram { | |||
3846 | */ | 4007 | */ |
3847 | INT_COALESCING_MINCMDS { | 4008 | INT_COALESCING_MINCMDS { |
3848 | size 1 | 4009 | size 1 |
4010 | dont_generate_debug_code | ||
3849 | } | 4011 | } |
3850 | 4012 | ||
3851 | /* | 4013 | /* |
@@ -3853,6 +4015,7 @@ scratch_ram { | |||
3853 | */ | 4015 | */ |
3854 | CMDS_PENDING { | 4016 | CMDS_PENDING { |
3855 | size 2 | 4017 | size 2 |
4018 | dont_generate_debug_code | ||
3856 | } | 4019 | } |
3857 | 4020 | ||
3858 | /* | 4021 | /* |
@@ -3860,6 +4023,7 @@ scratch_ram { | |||
3860 | */ | 4023 | */ |
3861 | INT_COALESCING_CMDCOUNT { | 4024 | INT_COALESCING_CMDCOUNT { |
3862 | size 1 | 4025 | size 1 |
4026 | dont_generate_debug_code | ||
3863 | } | 4027 | } |
3864 | 4028 | ||
3865 | /* | 4029 | /* |
@@ -3868,6 +4032,7 @@ scratch_ram { | |||
3868 | */ | 4032 | */ |
3869 | LOCAL_HS_MAILBOX { | 4033 | LOCAL_HS_MAILBOX { |
3870 | size 1 | 4034 | size 1 |
4035 | dont_generate_debug_code | ||
3871 | } | 4036 | } |
3872 | /* | 4037 | /* |
3873 | * Target-mode CDB type to CDB length table used | 4038 | * Target-mode CDB type to CDB length table used |
@@ -3876,6 +4041,7 @@ scratch_ram { | |||
3876 | CMDSIZE_TABLE { | 4041 | CMDSIZE_TABLE { |
3877 | size 8 | 4042 | size 8 |
3878 | count 8 | 4043 | count 8 |
4044 | dont_generate_debug_code | ||
3879 | } | 4045 | } |
3880 | /* | 4046 | /* |
3881 | * When an SCB with the MK_MESSAGE flag is | 4047 | * When an SCB with the MK_MESSAGE flag is |
@@ -3908,25 +4074,31 @@ scb { | |||
3908 | size 4 | 4074 | size 4 |
3909 | alias SCB_CDB_STORE | 4075 | alias SCB_CDB_STORE |
3910 | alias SCB_HOST_CDB_PTR | 4076 | alias SCB_HOST_CDB_PTR |
4077 | dont_generate_debug_code | ||
3911 | } | 4078 | } |
3912 | SCB_RESIDUAL_SGPTR { | 4079 | SCB_RESIDUAL_SGPTR { |
3913 | size 4 | 4080 | size 4 |
3914 | field SG_ADDR_MASK 0xf8 /* In the last byte */ | 4081 | field SG_ADDR_MASK 0xf8 /* In the last byte */ |
3915 | field SG_OVERRUN_RESID 0x02 /* In the first byte */ | 4082 | field SG_OVERRUN_RESID 0x02 /* In the first byte */ |
3916 | field SG_LIST_NULL 0x01 /* In the first byte */ | 4083 | field SG_LIST_NULL 0x01 /* In the first byte */ |
4084 | dont_generate_debug_code | ||
3917 | } | 4085 | } |
3918 | SCB_SCSI_STATUS { | 4086 | SCB_SCSI_STATUS { |
3919 | size 1 | 4087 | size 1 |
3920 | alias SCB_HOST_CDB_LEN | 4088 | alias SCB_HOST_CDB_LEN |
4089 | dont_generate_debug_code | ||
3921 | } | 4090 | } |
3922 | SCB_TARGET_PHASES { | 4091 | SCB_TARGET_PHASES { |
3923 | size 1 | 4092 | size 1 |
4093 | dont_generate_debug_code | ||
3924 | } | 4094 | } |
3925 | SCB_TARGET_DATA_DIR { | 4095 | SCB_TARGET_DATA_DIR { |
3926 | size 1 | 4096 | size 1 |
4097 | dont_generate_debug_code | ||
3927 | } | 4098 | } |
3928 | SCB_TARGET_ITAG { | 4099 | SCB_TARGET_ITAG { |
3929 | size 1 | 4100 | size 1 |
4101 | dont_generate_debug_code | ||
3930 | } | 4102 | } |
3931 | SCB_SENSE_BUSADDR { | 4103 | SCB_SENSE_BUSADDR { |
3932 | /* | 4104 | /* |
@@ -3936,10 +4108,12 @@ scb { | |||
3936 | */ | 4108 | */ |
3937 | size 4 | 4109 | size 4 |
3938 | alias SCB_NEXT_COMPLETE | 4110 | alias SCB_NEXT_COMPLETE |
4111 | dont_generate_debug_code | ||
3939 | } | 4112 | } |
3940 | SCB_TAG { | 4113 | SCB_TAG { |
3941 | alias SCB_FIFO_USE_COUNT | 4114 | alias SCB_FIFO_USE_COUNT |
3942 | size 2 | 4115 | size 2 |
4116 | dont_generate_debug_code | ||
3943 | } | 4117 | } |
3944 | SCB_CONTROL { | 4118 | SCB_CONTROL { |
3945 | size 1 | 4119 | size 1 |
@@ -3959,6 +4133,7 @@ scb { | |||
3959 | SCB_LUN { | 4133 | SCB_LUN { |
3960 | size 1 | 4134 | size 1 |
3961 | field LID 0xff | 4135 | field LID 0xff |
4136 | dont_generate_debug_code | ||
3962 | } | 4137 | } |
3963 | SCB_TASK_ATTRIBUTE { | 4138 | SCB_TASK_ATTRIBUTE { |
3964 | size 1 | 4139 | size 1 |
@@ -3967,16 +4142,20 @@ scb { | |||
3967 | * ignore wide residue message handling. | 4142 | * ignore wide residue message handling. |
3968 | */ | 4143 | */ |
3969 | field SCB_XFERLEN_ODD 0x01 | 4144 | field SCB_XFERLEN_ODD 0x01 |
4145 | dont_generate_debug_code | ||
3970 | } | 4146 | } |
3971 | SCB_CDB_LEN { | 4147 | SCB_CDB_LEN { |
3972 | size 1 | 4148 | size 1 |
3973 | field SCB_CDB_LEN_PTR 0x80 /* CDB in host memory */ | 4149 | field SCB_CDB_LEN_PTR 0x80 /* CDB in host memory */ |
4150 | dont_generate_debug_code | ||
3974 | } | 4151 | } |
3975 | SCB_TASK_MANAGEMENT { | 4152 | SCB_TASK_MANAGEMENT { |
3976 | size 1 | 4153 | size 1 |
4154 | dont_generate_debug_code | ||
3977 | } | 4155 | } |
3978 | SCB_DATAPTR { | 4156 | SCB_DATAPTR { |
3979 | size 8 | 4157 | size 8 |
4158 | dont_generate_debug_code | ||
3980 | } | 4159 | } |
3981 | SCB_DATACNT { | 4160 | SCB_DATACNT { |
3982 | /* | 4161 | /* |
@@ -3986,22 +4165,27 @@ scb { | |||
3986 | size 4 | 4165 | size 4 |
3987 | field SG_LAST_SEG 0x80 /* In the fourth byte */ | 4166 | field SG_LAST_SEG 0x80 /* In the fourth byte */ |
3988 | field SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */ | 4167 | field SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */ |
4168 | dont_generate_debug_code | ||
3989 | } | 4169 | } |
3990 | SCB_SGPTR { | 4170 | SCB_SGPTR { |
3991 | size 4 | 4171 | size 4 |
3992 | field SG_STATUS_VALID 0x04 /* In the first byte */ | 4172 | field SG_STATUS_VALID 0x04 /* In the first byte */ |
3993 | field SG_FULL_RESID 0x02 /* In the first byte */ | 4173 | field SG_FULL_RESID 0x02 /* In the first byte */ |
3994 | field SG_LIST_NULL 0x01 /* In the first byte */ | 4174 | field SG_LIST_NULL 0x01 /* In the first byte */ |
4175 | dont_generate_debug_code | ||
3995 | } | 4176 | } |
3996 | SCB_BUSADDR { | 4177 | SCB_BUSADDR { |
3997 | size 4 | 4178 | size 4 |
4179 | dont_generate_debug_code | ||
3998 | } | 4180 | } |
3999 | SCB_NEXT { | 4181 | SCB_NEXT { |
4000 | alias SCB_NEXT_SCB_BUSADDR | 4182 | alias SCB_NEXT_SCB_BUSADDR |
4001 | size 2 | 4183 | size 2 |
4184 | dont_generate_debug_code | ||
4002 | } | 4185 | } |
4003 | SCB_NEXT2 { | 4186 | SCB_NEXT2 { |
4004 | size 2 | 4187 | size 2 |
4188 | dont_generate_debug_code | ||
4005 | } | 4189 | } |
4006 | SCB_SPARE { | 4190 | SCB_SPARE { |
4007 | size 8 | 4191 | size 8 |
@@ -4009,6 +4193,7 @@ scb { | |||
4009 | } | 4193 | } |
4010 | SCB_DISCONNECTED_LISTS { | 4194 | SCB_DISCONNECTED_LISTS { |
4011 | size 8 | 4195 | size 8 |
4196 | dont_generate_debug_code | ||
4012 | } | 4197 | } |
4013 | } | 4198 | } |
4014 | 4199 | ||
diff --git a/drivers/scsi/aic7xxx/aic79xx_core.c b/drivers/scsi/aic7xxx/aic79xx_core.c index 55508b0fcec4..bdad54ec088c 100644 --- a/drivers/scsi/aic7xxx/aic79xx_core.c +++ b/drivers/scsi/aic7xxx/aic79xx_core.c | |||
@@ -2472,8 +2472,6 @@ ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat) | |||
2472 | if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) | 2472 | if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) |
2473 | ahd_outb(ahd, CLRLQOINT1, 0); | 2473 | ahd_outb(ahd, CLRLQOINT1, 0); |
2474 | } else if ((status & SELTO) != 0) { | 2474 | } else if ((status & SELTO) != 0) { |
2475 | u_int scbid; | ||
2476 | |||
2477 | /* Stop the selection */ | 2475 | /* Stop the selection */ |
2478 | ahd_outb(ahd, SCSISEQ0, 0); | 2476 | ahd_outb(ahd, SCSISEQ0, 0); |
2479 | 2477 | ||
@@ -2583,9 +2581,6 @@ ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat) | |||
2583 | case BUSFREE_DFF0: | 2581 | case BUSFREE_DFF0: |
2584 | case BUSFREE_DFF1: | 2582 | case BUSFREE_DFF1: |
2585 | { | 2583 | { |
2586 | u_int scbid; | ||
2587 | struct scb *scb; | ||
2588 | |||
2589 | mode = busfreetime == BUSFREE_DFF0 | 2584 | mode = busfreetime == BUSFREE_DFF0 |
2590 | ? AHD_MODE_DFF0 : AHD_MODE_DFF1; | 2585 | ? AHD_MODE_DFF0 : AHD_MODE_DFF1; |
2591 | ahd_set_modes(ahd, mode, mode); | 2586 | ahd_set_modes(ahd, mode, mode); |
@@ -3689,7 +3684,7 @@ ahd_free_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel, int force) | |||
3689 | * by the capabilities of the bus connectivity of and sync settings for | 3684 | * by the capabilities of the bus connectivity of and sync settings for |
3690 | * the target. | 3685 | * the target. |
3691 | */ | 3686 | */ |
3692 | void | 3687 | static void |
3693 | ahd_devlimited_syncrate(struct ahd_softc *ahd, | 3688 | ahd_devlimited_syncrate(struct ahd_softc *ahd, |
3694 | struct ahd_initiator_tinfo *tinfo, | 3689 | struct ahd_initiator_tinfo *tinfo, |
3695 | u_int *period, u_int *ppr_options, role_t role) | 3690 | u_int *period, u_int *ppr_options, role_t role) |
@@ -4136,7 +4131,7 @@ ahd_update_neg_table(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, | |||
4136 | 4131 | ||
4137 | /* | 4132 | /* |
4138 | * Harpoon2A assumed that there would be a | 4133 | * Harpoon2A assumed that there would be a |
4139 | * fallback rate between 160MHz and 80Mhz, | 4134 | * fallback rate between 160MHz and 80MHz, |
4140 | * so 7 is used as the period factor rather | 4135 | * so 7 is used as the period factor rather |
4141 | * than 8 for 160MHz. | 4136 | * than 8 for 160MHz. |
4142 | */ | 4137 | */ |
@@ -8708,7 +8703,7 @@ ahd_reset_current_bus(struct ahd_softc *ahd) | |||
8708 | int | 8703 | int |
8709 | ahd_reset_channel(struct ahd_softc *ahd, char channel, int initiate_reset) | 8704 | ahd_reset_channel(struct ahd_softc *ahd, char channel, int initiate_reset) |
8710 | { | 8705 | { |
8711 | struct ahd_devinfo devinfo; | 8706 | struct ahd_devinfo caminfo; |
8712 | u_int initiator; | 8707 | u_int initiator; |
8713 | u_int target; | 8708 | u_int target; |
8714 | u_int max_scsiid; | 8709 | u_int max_scsiid; |
@@ -8729,7 +8724,7 @@ ahd_reset_channel(struct ahd_softc *ahd, char channel, int initiate_reset) | |||
8729 | 8724 | ||
8730 | ahd->pending_device = NULL; | 8725 | ahd->pending_device = NULL; |
8731 | 8726 | ||
8732 | ahd_compile_devinfo(&devinfo, | 8727 | ahd_compile_devinfo(&caminfo, |
8733 | CAM_TARGET_WILDCARD, | 8728 | CAM_TARGET_WILDCARD, |
8734 | CAM_TARGET_WILDCARD, | 8729 | CAM_TARGET_WILDCARD, |
8735 | CAM_LUN_WILDCARD, | 8730 | CAM_LUN_WILDCARD, |
@@ -8868,7 +8863,7 @@ ahd_reset_channel(struct ahd_softc *ahd, char channel, int initiate_reset) | |||
8868 | } | 8863 | } |
8869 | 8864 | ||
8870 | /* Notify the XPT that a bus reset occurred */ | 8865 | /* Notify the XPT that a bus reset occurred */ |
8871 | ahd_send_async(ahd, devinfo.channel, CAM_TARGET_WILDCARD, | 8866 | ahd_send_async(ahd, caminfo.channel, CAM_TARGET_WILDCARD, |
8872 | CAM_LUN_WILDCARD, AC_BUS_RESET); | 8867 | CAM_LUN_WILDCARD, AC_BUS_RESET); |
8873 | 8868 | ||
8874 | ahd_restart(ahd); | 8869 | ahd_restart(ahd); |
diff --git a/drivers/scsi/aic7xxx/aic79xx_pci.c b/drivers/scsi/aic7xxx/aic79xx_pci.c index c25b6adffbf9..a734d77e880e 100644 --- a/drivers/scsi/aic7xxx/aic79xx_pci.c +++ b/drivers/scsi/aic7xxx/aic79xx_pci.c | |||
@@ -223,10 +223,10 @@ static const char *pci_bus_modes[] = | |||
223 | "PCI bus mode unknown", | 223 | "PCI bus mode unknown", |
224 | "PCI bus mode unknown", | 224 | "PCI bus mode unknown", |
225 | "PCI bus mode unknown", | 225 | "PCI bus mode unknown", |
226 | "PCI-X 101-133Mhz", | 226 | "PCI-X 101-133MHz", |
227 | "PCI-X 67-100Mhz", | 227 | "PCI-X 67-100MHz", |
228 | "PCI-X 50-66Mhz", | 228 | "PCI-X 50-66MHz", |
229 | "PCI 33 or 66Mhz" | 229 | "PCI 33 or 66MHz" |
230 | }; | 230 | }; |
231 | 231 | ||
232 | #define TESTMODE 0x00000800ul | 232 | #define TESTMODE 0x00000800ul |
@@ -337,8 +337,6 @@ ahd_pci_config(struct ahd_softc *ahd, const struct ahd_pci_identity *entry) | |||
337 | * 64bit bus (PCI64BIT set in devconfig). | 337 | * 64bit bus (PCI64BIT set in devconfig). |
338 | */ | 338 | */ |
339 | if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { | 339 | if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { |
340 | uint32_t devconfig; | ||
341 | |||
342 | if (bootverbose) | 340 | if (bootverbose) |
343 | printf("%s: Enabling 39Bit Addressing\n", | 341 | printf("%s: Enabling 39Bit Addressing\n", |
344 | ahd_name(ahd)); | 342 | ahd_name(ahd)); |
@@ -483,8 +481,6 @@ ahd_pci_test_register_access(struct ahd_softc *ahd) | |||
483 | goto fail; | 481 | goto fail; |
484 | 482 | ||
485 | if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { | 483 | if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { |
486 | u_int targpcistat; | ||
487 | |||
488 | ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); | 484 | ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); |
489 | targpcistat = ahd_inb(ahd, TARGPCISTAT); | 485 | targpcistat = ahd_inb(ahd, TARGPCISTAT); |
490 | if ((targpcistat & STA) != 0) | 486 | if ((targpcistat & STA) != 0) |
diff --git a/drivers/scsi/aic7xxx/aic79xx_reg.h_shipped b/drivers/scsi/aic7xxx/aic79xx_reg.h_shipped index c21ceab8e913..cdcead071ef6 100644 --- a/drivers/scsi/aic7xxx/aic79xx_reg.h_shipped +++ b/drivers/scsi/aic7xxx/aic79xx_reg.h_shipped | |||
@@ -34,13 +34,6 @@ ahd_reg_print_t ahd_seqintcode_print; | |||
34 | #endif | 34 | #endif |
35 | 35 | ||
36 | #if AIC_DEBUG_REGISTERS | 36 | #if AIC_DEBUG_REGISTERS |
37 | ahd_reg_print_t ahd_clrint_print; | ||
38 | #else | ||
39 | #define ahd_clrint_print(regvalue, cur_col, wrap) \ | ||
40 | ahd_print_register(NULL, 0, "CLRINT", 0x03, regvalue, cur_col, wrap) | ||
41 | #endif | ||
42 | |||
43 | #if AIC_DEBUG_REGISTERS | ||
44 | ahd_reg_print_t ahd_error_print; | 37 | ahd_reg_print_t ahd_error_print; |
45 | #else | 38 | #else |
46 | #define ahd_error_print(regvalue, cur_col, wrap) \ | 39 | #define ahd_error_print(regvalue, cur_col, wrap) \ |
@@ -48,20 +41,6 @@ ahd_reg_print_t ahd_error_print; | |||
48 | #endif | 41 | #endif |
49 | 42 | ||
50 | #if AIC_DEBUG_REGISTERS | 43 | #if AIC_DEBUG_REGISTERS |
51 | ahd_reg_print_t ahd_hcntrl_print; | ||
52 | #else | ||
53 | #define ahd_hcntrl_print(regvalue, cur_col, wrap) \ | ||
54 | ahd_print_register(NULL, 0, "HCNTRL", 0x05, regvalue, cur_col, wrap) | ||
55 | #endif | ||
56 | |||
57 | #if AIC_DEBUG_REGISTERS | ||
58 | ahd_reg_print_t ahd_hnscb_qoff_print; | ||
59 | #else | ||
60 | #define ahd_hnscb_qoff_print(regvalue, cur_col, wrap) \ | ||
61 | ahd_print_register(NULL, 0, "HNSCB_QOFF", 0x06, regvalue, cur_col, wrap) | ||
62 | #endif | ||
63 | |||
64 | #if AIC_DEBUG_REGISTERS | ||
65 | ahd_reg_print_t ahd_hescb_qoff_print; | 44 | ahd_reg_print_t ahd_hescb_qoff_print; |
66 | #else | 45 | #else |
67 | #define ahd_hescb_qoff_print(regvalue, cur_col, wrap) \ | 46 | #define ahd_hescb_qoff_print(regvalue, cur_col, wrap) \ |
@@ -97,13 +76,6 @@ ahd_reg_print_t ahd_swtimer_print; | |||
97 | #endif | 76 | #endif |
98 | 77 | ||
99 | #if AIC_DEBUG_REGISTERS | 78 | #if AIC_DEBUG_REGISTERS |
100 | ahd_reg_print_t ahd_snscb_qoff_print; | ||
101 | #else | ||
102 | #define ahd_snscb_qoff_print(regvalue, cur_col, wrap) \ | ||
103 | ahd_print_register(NULL, 0, "SNSCB_QOFF", 0x10, regvalue, cur_col, wrap) | ||
104 | #endif | ||
105 | |||
106 | #if AIC_DEBUG_REGISTERS | ||
107 | ahd_reg_print_t ahd_sescb_qoff_print; | 79 | ahd_reg_print_t ahd_sescb_qoff_print; |
108 | #else | 80 | #else |
109 | #define ahd_sescb_qoff_print(regvalue, cur_col, wrap) \ | 81 | #define ahd_sescb_qoff_print(regvalue, cur_col, wrap) \ |
@@ -111,20 +83,6 @@ ahd_reg_print_t ahd_sescb_qoff_print; | |||
111 | #endif | 83 | #endif |
112 | 84 | ||
113 | #if AIC_DEBUG_REGISTERS | 85 | #if AIC_DEBUG_REGISTERS |
114 | ahd_reg_print_t ahd_sdscb_qoff_print; | ||
115 | #else | ||
116 | #define ahd_sdscb_qoff_print(regvalue, cur_col, wrap) \ | ||
117 | ahd_print_register(NULL, 0, "SDSCB_QOFF", 0x14, regvalue, cur_col, wrap) | ||
118 | #endif | ||
119 | |||
120 | #if AIC_DEBUG_REGISTERS | ||
121 | ahd_reg_print_t ahd_qoff_ctlsta_print; | ||
122 | #else | ||
123 | #define ahd_qoff_ctlsta_print(regvalue, cur_col, wrap) \ | ||
124 | ahd_print_register(NULL, 0, "QOFF_CTLSTA", 0x16, regvalue, cur_col, wrap) | ||
125 | #endif | ||
126 | |||
127 | #if AIC_DEBUG_REGISTERS | ||
128 | ahd_reg_print_t ahd_intctl_print; | 86 | ahd_reg_print_t ahd_intctl_print; |
129 | #else | 87 | #else |
130 | #define ahd_intctl_print(regvalue, cur_col, wrap) \ | 88 | #define ahd_intctl_print(regvalue, cur_col, wrap) \ |
@@ -139,13 +97,6 @@ ahd_reg_print_t ahd_dfcntrl_print; | |||
139 | #endif | 97 | #endif |
140 | 98 | ||
141 | #if AIC_DEBUG_REGISTERS | 99 | #if AIC_DEBUG_REGISTERS |
142 | ahd_reg_print_t ahd_dscommand0_print; | ||
143 | #else | ||
144 | #define ahd_dscommand0_print(regvalue, cur_col, wrap) \ | ||
145 | ahd_print_register(NULL, 0, "DSCOMMAND0", 0x19, regvalue, cur_col, wrap) | ||
146 | #endif | ||
147 | |||
148 | #if AIC_DEBUG_REGISTERS | ||
149 | ahd_reg_print_t ahd_dfstatus_print; | 100 | ahd_reg_print_t ahd_dfstatus_print; |
150 | #else | 101 | #else |
151 | #define ahd_dfstatus_print(regvalue, cur_col, wrap) \ | 102 | #define ahd_dfstatus_print(regvalue, cur_col, wrap) \ |
@@ -160,13 +111,6 @@ ahd_reg_print_t ahd_sg_cache_shadow_print; | |||
160 | #endif | 111 | #endif |
161 | 112 | ||
162 | #if AIC_DEBUG_REGISTERS | 113 | #if AIC_DEBUG_REGISTERS |
163 | ahd_reg_print_t ahd_sg_cache_pre_print; | ||
164 | #else | ||
165 | #define ahd_sg_cache_pre_print(regvalue, cur_col, wrap) \ | ||
166 | ahd_print_register(NULL, 0, "SG_CACHE_PRE", 0x1b, regvalue, cur_col, wrap) | ||
167 | #endif | ||
168 | |||
169 | #if AIC_DEBUG_REGISTERS | ||
170 | ahd_reg_print_t ahd_lqin_print; | 114 | ahd_reg_print_t ahd_lqin_print; |
171 | #else | 115 | #else |
172 | #define ahd_lqin_print(regvalue, cur_col, wrap) \ | 116 | #define ahd_lqin_print(regvalue, cur_col, wrap) \ |
@@ -293,13 +237,6 @@ ahd_reg_print_t ahd_sxfrctl0_print; | |||
293 | #endif | 237 | #endif |
294 | 238 | ||
295 | #if AIC_DEBUG_REGISTERS | 239 | #if AIC_DEBUG_REGISTERS |
296 | ahd_reg_print_t ahd_sxfrctl1_print; | ||
297 | #else | ||
298 | #define ahd_sxfrctl1_print(regvalue, cur_col, wrap) \ | ||
299 | ahd_print_register(NULL, 0, "SXFRCTL1", 0x3d, regvalue, cur_col, wrap) | ||
300 | #endif | ||
301 | |||
302 | #if AIC_DEBUG_REGISTERS | ||
303 | ahd_reg_print_t ahd_dffstat_print; | 240 | ahd_reg_print_t ahd_dffstat_print; |
304 | #else | 241 | #else |
305 | #define ahd_dffstat_print(regvalue, cur_col, wrap) \ | 242 | #define ahd_dffstat_print(regvalue, cur_col, wrap) \ |
@@ -314,13 +251,6 @@ ahd_reg_print_t ahd_multargid_print; | |||
314 | #endif | 251 | #endif |
315 | 252 | ||
316 | #if AIC_DEBUG_REGISTERS | 253 | #if AIC_DEBUG_REGISTERS |
317 | ahd_reg_print_t ahd_scsisigo_print; | ||
318 | #else | ||
319 | #define ahd_scsisigo_print(regvalue, cur_col, wrap) \ | ||
320 | ahd_print_register(NULL, 0, "SCSISIGO", 0x40, regvalue, cur_col, wrap) | ||
321 | #endif | ||
322 | |||
323 | #if AIC_DEBUG_REGISTERS | ||
324 | ahd_reg_print_t ahd_scsisigi_print; | 254 | ahd_reg_print_t ahd_scsisigi_print; |
325 | #else | 255 | #else |
326 | #define ahd_scsisigi_print(regvalue, cur_col, wrap) \ | 256 | #define ahd_scsisigi_print(regvalue, cur_col, wrap) \ |
@@ -363,13 +293,6 @@ ahd_reg_print_t ahd_selid_print; | |||
363 | #endif | 293 | #endif |
364 | 294 | ||
365 | #if AIC_DEBUG_REGISTERS | 295 | #if AIC_DEBUG_REGISTERS |
366 | ahd_reg_print_t ahd_optionmode_print; | ||
367 | #else | ||
368 | #define ahd_optionmode_print(regvalue, cur_col, wrap) \ | ||
369 | ahd_print_register(NULL, 0, "OPTIONMODE", 0x4a, regvalue, cur_col, wrap) | ||
370 | #endif | ||
371 | |||
372 | #if AIC_DEBUG_REGISTERS | ||
373 | ahd_reg_print_t ahd_sblkctl_print; | 296 | ahd_reg_print_t ahd_sblkctl_print; |
374 | #else | 297 | #else |
375 | #define ahd_sblkctl_print(regvalue, cur_col, wrap) \ | 298 | #define ahd_sblkctl_print(regvalue, cur_col, wrap) \ |
@@ -391,13 +314,6 @@ ahd_reg_print_t ahd_simode0_print; | |||
391 | #endif | 314 | #endif |
392 | 315 | ||
393 | #if AIC_DEBUG_REGISTERS | 316 | #if AIC_DEBUG_REGISTERS |
394 | ahd_reg_print_t ahd_clrsint0_print; | ||
395 | #else | ||
396 | #define ahd_clrsint0_print(regvalue, cur_col, wrap) \ | ||
397 | ahd_print_register(NULL, 0, "CLRSINT0", 0x4b, regvalue, cur_col, wrap) | ||
398 | #endif | ||
399 | |||
400 | #if AIC_DEBUG_REGISTERS | ||
401 | ahd_reg_print_t ahd_sstat1_print; | 317 | ahd_reg_print_t ahd_sstat1_print; |
402 | #else | 318 | #else |
403 | #define ahd_sstat1_print(regvalue, cur_col, wrap) \ | 319 | #define ahd_sstat1_print(regvalue, cur_col, wrap) \ |
@@ -405,13 +321,6 @@ ahd_reg_print_t ahd_sstat1_print; | |||
405 | #endif | 321 | #endif |
406 | 322 | ||
407 | #if AIC_DEBUG_REGISTERS | 323 | #if AIC_DEBUG_REGISTERS |
408 | ahd_reg_print_t ahd_clrsint1_print; | ||
409 | #else | ||
410 | #define ahd_clrsint1_print(regvalue, cur_col, wrap) \ | ||
411 | ahd_print_register(NULL, 0, "CLRSINT1", 0x4c, regvalue, cur_col, wrap) | ||
412 | #endif | ||
413 | |||
414 | #if AIC_DEBUG_REGISTERS | ||
415 | ahd_reg_print_t ahd_sstat2_print; | 324 | ahd_reg_print_t ahd_sstat2_print; |
416 | #else | 325 | #else |
417 | #define ahd_sstat2_print(regvalue, cur_col, wrap) \ | 326 | #define ahd_sstat2_print(regvalue, cur_col, wrap) \ |
@@ -461,17 +370,17 @@ ahd_reg_print_t ahd_lqistat0_print; | |||
461 | #endif | 370 | #endif |
462 | 371 | ||
463 | #if AIC_DEBUG_REGISTERS | 372 | #if AIC_DEBUG_REGISTERS |
464 | ahd_reg_print_t ahd_lqimode0_print; | 373 | ahd_reg_print_t ahd_clrlqiint0_print; |
465 | #else | 374 | #else |
466 | #define ahd_lqimode0_print(regvalue, cur_col, wrap) \ | 375 | #define ahd_clrlqiint0_print(regvalue, cur_col, wrap) \ |
467 | ahd_print_register(NULL, 0, "LQIMODE0", 0x50, regvalue, cur_col, wrap) | 376 | ahd_print_register(NULL, 0, "CLRLQIINT0", 0x50, regvalue, cur_col, wrap) |
468 | #endif | 377 | #endif |
469 | 378 | ||
470 | #if AIC_DEBUG_REGISTERS | 379 | #if AIC_DEBUG_REGISTERS |
471 | ahd_reg_print_t ahd_clrlqiint0_print; | 380 | ahd_reg_print_t ahd_lqimode0_print; |
472 | #else | 381 | #else |
473 | #define ahd_clrlqiint0_print(regvalue, cur_col, wrap) \ | 382 | #define ahd_lqimode0_print(regvalue, cur_col, wrap) \ |
474 | ahd_print_register(NULL, 0, "CLRLQIINT0", 0x50, regvalue, cur_col, wrap) | 383 | ahd_print_register(NULL, 0, "LQIMODE0", 0x50, regvalue, cur_col, wrap) |
475 | #endif | 384 | #endif |
476 | 385 | ||
477 | #if AIC_DEBUG_REGISTERS | 386 | #if AIC_DEBUG_REGISTERS |
@@ -629,17 +538,17 @@ ahd_reg_print_t ahd_seqintsrc_print; | |||
629 | #endif | 538 | #endif |
630 | 539 | ||
631 | #if AIC_DEBUG_REGISTERS | 540 | #if AIC_DEBUG_REGISTERS |
632 | ahd_reg_print_t ahd_seqimode_print; | 541 | ahd_reg_print_t ahd_currscb_print; |
633 | #else | 542 | #else |
634 | #define ahd_seqimode_print(regvalue, cur_col, wrap) \ | 543 | #define ahd_currscb_print(regvalue, cur_col, wrap) \ |
635 | ahd_print_register(NULL, 0, "SEQIMODE", 0x5c, regvalue, cur_col, wrap) | 544 | ahd_print_register(NULL, 0, "CURRSCB", 0x5c, regvalue, cur_col, wrap) |
636 | #endif | 545 | #endif |
637 | 546 | ||
638 | #if AIC_DEBUG_REGISTERS | 547 | #if AIC_DEBUG_REGISTERS |
639 | ahd_reg_print_t ahd_currscb_print; | 548 | ahd_reg_print_t ahd_seqimode_print; |
640 | #else | 549 | #else |
641 | #define ahd_currscb_print(regvalue, cur_col, wrap) \ | 550 | #define ahd_seqimode_print(regvalue, cur_col, wrap) \ |
642 | ahd_print_register(NULL, 0, "CURRSCB", 0x5c, regvalue, cur_col, wrap) | 551 | ahd_print_register(NULL, 0, "SEQIMODE", 0x5c, regvalue, cur_col, wrap) |
643 | #endif | 552 | #endif |
644 | 553 | ||
645 | #if AIC_DEBUG_REGISTERS | 554 | #if AIC_DEBUG_REGISTERS |
@@ -657,13 +566,6 @@ ahd_reg_print_t ahd_lastscb_print; | |||
657 | #endif | 566 | #endif |
658 | 567 | ||
659 | #if AIC_DEBUG_REGISTERS | 568 | #if AIC_DEBUG_REGISTERS |
660 | ahd_reg_print_t ahd_shaddr_print; | ||
661 | #else | ||
662 | #define ahd_shaddr_print(regvalue, cur_col, wrap) \ | ||
663 | ahd_print_register(NULL, 0, "SHADDR", 0x60, regvalue, cur_col, wrap) | ||
664 | #endif | ||
665 | |||
666 | #if AIC_DEBUG_REGISTERS | ||
667 | ahd_reg_print_t ahd_negoaddr_print; | 569 | ahd_reg_print_t ahd_negoaddr_print; |
668 | #else | 570 | #else |
669 | #define ahd_negoaddr_print(regvalue, cur_col, wrap) \ | 571 | #define ahd_negoaddr_print(regvalue, cur_col, wrap) \ |
@@ -748,27 +650,6 @@ ahd_reg_print_t ahd_seloid_print; | |||
748 | #endif | 650 | #endif |
749 | 651 | ||
750 | #if AIC_DEBUG_REGISTERS | 652 | #if AIC_DEBUG_REGISTERS |
751 | ahd_reg_print_t ahd_haddr_print; | ||
752 | #else | ||
753 | #define ahd_haddr_print(regvalue, cur_col, wrap) \ | ||
754 | ahd_print_register(NULL, 0, "HADDR", 0x70, regvalue, cur_col, wrap) | ||
755 | #endif | ||
756 | |||
757 | #if AIC_DEBUG_REGISTERS | ||
758 | ahd_reg_print_t ahd_hcnt_print; | ||
759 | #else | ||
760 | #define ahd_hcnt_print(regvalue, cur_col, wrap) \ | ||
761 | ahd_print_register(NULL, 0, "HCNT", 0x78, regvalue, cur_col, wrap) | ||
762 | #endif | ||
763 | |||
764 | #if AIC_DEBUG_REGISTERS | ||
765 | ahd_reg_print_t ahd_sghaddr_print; | ||
766 | #else | ||
767 | #define ahd_sghaddr_print(regvalue, cur_col, wrap) \ | ||
768 | ahd_print_register(NULL, 0, "SGHADDR", 0x7c, regvalue, cur_col, wrap) | ||
769 | #endif | ||
770 | |||
771 | #if AIC_DEBUG_REGISTERS | ||
772 | ahd_reg_print_t ahd_scbhaddr_print; | 653 | ahd_reg_print_t ahd_scbhaddr_print; |
773 | #else | 654 | #else |
774 | #define ahd_scbhaddr_print(regvalue, cur_col, wrap) \ | 655 | #define ahd_scbhaddr_print(regvalue, cur_col, wrap) \ |
@@ -776,10 +657,10 @@ ahd_reg_print_t ahd_scbhaddr_print; | |||
776 | #endif | 657 | #endif |
777 | 658 | ||
778 | #if AIC_DEBUG_REGISTERS | 659 | #if AIC_DEBUG_REGISTERS |
779 | ahd_reg_print_t ahd_sghcnt_print; | 660 | ahd_reg_print_t ahd_sghaddr_print; |
780 | #else | 661 | #else |
781 | #define ahd_sghcnt_print(regvalue, cur_col, wrap) \ | 662 | #define ahd_sghaddr_print(regvalue, cur_col, wrap) \ |
782 | ahd_print_register(NULL, 0, "SGHCNT", 0x84, regvalue, cur_col, wrap) | 663 | ahd_print_register(NULL, 0, "SGHADDR", 0x7c, regvalue, cur_col, wrap) |
783 | #endif | 664 | #endif |
784 | 665 | ||
785 | #if AIC_DEBUG_REGISTERS | 666 | #if AIC_DEBUG_REGISTERS |
@@ -790,10 +671,10 @@ ahd_reg_print_t ahd_scbhcnt_print; | |||
790 | #endif | 671 | #endif |
791 | 672 | ||
792 | #if AIC_DEBUG_REGISTERS | 673 | #if AIC_DEBUG_REGISTERS |
793 | ahd_reg_print_t ahd_dff_thrsh_print; | 674 | ahd_reg_print_t ahd_sghcnt_print; |
794 | #else | 675 | #else |
795 | #define ahd_dff_thrsh_print(regvalue, cur_col, wrap) \ | 676 | #define ahd_sghcnt_print(regvalue, cur_col, wrap) \ |
796 | ahd_print_register(NULL, 0, "DFF_THRSH", 0x88, regvalue, cur_col, wrap) | 677 | ahd_print_register(NULL, 0, "SGHCNT", 0x84, regvalue, cur_col, wrap) |
797 | #endif | 678 | #endif |
798 | 679 | ||
799 | #if AIC_DEBUG_REGISTERS | 680 | #if AIC_DEBUG_REGISTERS |
@@ -867,13 +748,6 @@ ahd_reg_print_t ahd_targpcistat_print; | |||
867 | #endif | 748 | #endif |
868 | 749 | ||
869 | #if AIC_DEBUG_REGISTERS | 750 | #if AIC_DEBUG_REGISTERS |
870 | ahd_reg_print_t ahd_scbptr_print; | ||
871 | #else | ||
872 | #define ahd_scbptr_print(regvalue, cur_col, wrap) \ | ||
873 | ahd_print_register(NULL, 0, "SCBPTR", 0xa8, regvalue, cur_col, wrap) | ||
874 | #endif | ||
875 | |||
876 | #if AIC_DEBUG_REGISTERS | ||
877 | ahd_reg_print_t ahd_scbautoptr_print; | 751 | ahd_reg_print_t ahd_scbautoptr_print; |
878 | #else | 752 | #else |
879 | #define ahd_scbautoptr_print(regvalue, cur_col, wrap) \ | 753 | #define ahd_scbautoptr_print(regvalue, cur_col, wrap) \ |
@@ -881,13 +755,6 @@ ahd_reg_print_t ahd_scbautoptr_print; | |||
881 | #endif | 755 | #endif |
882 | 756 | ||
883 | #if AIC_DEBUG_REGISTERS | 757 | #if AIC_DEBUG_REGISTERS |
884 | ahd_reg_print_t ahd_ccsgaddr_print; | ||
885 | #else | ||
886 | #define ahd_ccsgaddr_print(regvalue, cur_col, wrap) \ | ||
887 | ahd_print_register(NULL, 0, "CCSGADDR", 0xac, regvalue, cur_col, wrap) | ||
888 | #endif | ||
889 | |||
890 | #if AIC_DEBUG_REGISTERS | ||
891 | ahd_reg_print_t ahd_ccscbaddr_print; | 758 | ahd_reg_print_t ahd_ccscbaddr_print; |
892 | #else | 759 | #else |
893 | #define ahd_ccscbaddr_print(regvalue, cur_col, wrap) \ | 760 | #define ahd_ccscbaddr_print(regvalue, cur_col, wrap) \ |
@@ -909,13 +776,6 @@ ahd_reg_print_t ahd_ccsgctl_print; | |||
909 | #endif | 776 | #endif |
910 | 777 | ||
911 | #if AIC_DEBUG_REGISTERS | 778 | #if AIC_DEBUG_REGISTERS |
912 | ahd_reg_print_t ahd_ccsgram_print; | ||
913 | #else | ||
914 | #define ahd_ccsgram_print(regvalue, cur_col, wrap) \ | ||
915 | ahd_print_register(NULL, 0, "CCSGRAM", 0xb0, regvalue, cur_col, wrap) | ||
916 | #endif | ||
917 | |||
918 | #if AIC_DEBUG_REGISTERS | ||
919 | ahd_reg_print_t ahd_ccscbram_print; | 779 | ahd_reg_print_t ahd_ccscbram_print; |
920 | #else | 780 | #else |
921 | #define ahd_ccscbram_print(regvalue, cur_col, wrap) \ | 781 | #define ahd_ccscbram_print(regvalue, cur_col, wrap) \ |
@@ -930,13 +790,6 @@ ahd_reg_print_t ahd_brddat_print; | |||
930 | #endif | 790 | #endif |
931 | 791 | ||
932 | #if AIC_DEBUG_REGISTERS | 792 | #if AIC_DEBUG_REGISTERS |
933 | ahd_reg_print_t ahd_brdctl_print; | ||
934 | #else | ||
935 | #define ahd_brdctl_print(regvalue, cur_col, wrap) \ | ||
936 | ahd_print_register(NULL, 0, "BRDCTL", 0xb9, regvalue, cur_col, wrap) | ||
937 | #endif | ||
938 | |||
939 | #if AIC_DEBUG_REGISTERS | ||
940 | ahd_reg_print_t ahd_seeadr_print; | 793 | ahd_reg_print_t ahd_seeadr_print; |
941 | #else | 794 | #else |
942 | #define ahd_seeadr_print(regvalue, cur_col, wrap) \ | 795 | #define ahd_seeadr_print(regvalue, cur_col, wrap) \ |
@@ -972,13 +825,6 @@ ahd_reg_print_t ahd_dspdatactl_print; | |||
972 | #endif | 825 | #endif |
973 | 826 | ||
974 | #if AIC_DEBUG_REGISTERS | 827 | #if AIC_DEBUG_REGISTERS |
975 | ahd_reg_print_t ahd_dfdat_print; | ||
976 | #else | ||
977 | #define ahd_dfdat_print(regvalue, cur_col, wrap) \ | ||
978 | ahd_print_register(NULL, 0, "DFDAT", 0xc4, regvalue, cur_col, wrap) | ||
979 | #endif | ||
980 | |||
981 | #if AIC_DEBUG_REGISTERS | ||
982 | ahd_reg_print_t ahd_dspselect_print; | 828 | ahd_reg_print_t ahd_dspselect_print; |
983 | #else | 829 | #else |
984 | #define ahd_dspselect_print(regvalue, cur_col, wrap) \ | 830 | #define ahd_dspselect_print(regvalue, cur_col, wrap) \ |
@@ -1000,13 +846,6 @@ ahd_reg_print_t ahd_seqctl0_print; | |||
1000 | #endif | 846 | #endif |
1001 | 847 | ||
1002 | #if AIC_DEBUG_REGISTERS | 848 | #if AIC_DEBUG_REGISTERS |
1003 | ahd_reg_print_t ahd_flags_print; | ||
1004 | #else | ||
1005 | #define ahd_flags_print(regvalue, cur_col, wrap) \ | ||
1006 | ahd_print_register(NULL, 0, "FLAGS", 0xd8, regvalue, cur_col, wrap) | ||
1007 | #endif | ||
1008 | |||
1009 | #if AIC_DEBUG_REGISTERS | ||
1010 | ahd_reg_print_t ahd_seqintctl_print; | 849 | ahd_reg_print_t ahd_seqintctl_print; |
1011 | #else | 850 | #else |
1012 | #define ahd_seqintctl_print(regvalue, cur_col, wrap) \ | 851 | #define ahd_seqintctl_print(regvalue, cur_col, wrap) \ |
@@ -1014,13 +853,6 @@ ahd_reg_print_t ahd_seqintctl_print; | |||
1014 | #endif | 853 | #endif |
1015 | 854 | ||
1016 | #if AIC_DEBUG_REGISTERS | 855 | #if AIC_DEBUG_REGISTERS |
1017 | ahd_reg_print_t ahd_seqram_print; | ||
1018 | #else | ||
1019 | #define ahd_seqram_print(regvalue, cur_col, wrap) \ | ||
1020 | ahd_print_register(NULL, 0, "SEQRAM", 0xda, regvalue, cur_col, wrap) | ||
1021 | #endif | ||
1022 | |||
1023 | #if AIC_DEBUG_REGISTERS | ||
1024 | ahd_reg_print_t ahd_prgmcnt_print; | 856 | ahd_reg_print_t ahd_prgmcnt_print; |
1025 | #else | 857 | #else |
1026 | #define ahd_prgmcnt_print(regvalue, cur_col, wrap) \ | 858 | #define ahd_prgmcnt_print(regvalue, cur_col, wrap) \ |
@@ -1028,41 +860,6 @@ ahd_reg_print_t ahd_prgmcnt_print; | |||
1028 | #endif | 860 | #endif |
1029 | 861 | ||
1030 | #if AIC_DEBUG_REGISTERS | 862 | #if AIC_DEBUG_REGISTERS |
1031 | ahd_reg_print_t ahd_accum_print; | ||
1032 | #else | ||
1033 | #define ahd_accum_print(regvalue, cur_col, wrap) \ | ||
1034 | ahd_print_register(NULL, 0, "ACCUM", 0xe0, regvalue, cur_col, wrap) | ||
1035 | #endif | ||
1036 | |||
1037 | #if AIC_DEBUG_REGISTERS | ||
1038 | ahd_reg_print_t ahd_sindex_print; | ||
1039 | #else | ||
1040 | #define ahd_sindex_print(regvalue, cur_col, wrap) \ | ||
1041 | ahd_print_register(NULL, 0, "SINDEX", 0xe2, regvalue, cur_col, wrap) | ||
1042 | #endif | ||
1043 | |||
1044 | #if AIC_DEBUG_REGISTERS | ||
1045 | ahd_reg_print_t ahd_dindex_print; | ||
1046 | #else | ||
1047 | #define ahd_dindex_print(regvalue, cur_col, wrap) \ | ||
1048 | ahd_print_register(NULL, 0, "DINDEX", 0xe4, regvalue, cur_col, wrap) | ||
1049 | #endif | ||
1050 | |||
1051 | #if AIC_DEBUG_REGISTERS | ||
1052 | ahd_reg_print_t ahd_allones_print; | ||
1053 | #else | ||
1054 | #define ahd_allones_print(regvalue, cur_col, wrap) \ | ||
1055 | ahd_print_register(NULL, 0, "ALLONES", 0xe8, regvalue, cur_col, wrap) | ||
1056 | #endif | ||
1057 | |||
1058 | #if AIC_DEBUG_REGISTERS | ||
1059 | ahd_reg_print_t ahd_allzeros_print; | ||
1060 | #else | ||
1061 | #define ahd_allzeros_print(regvalue, cur_col, wrap) \ | ||
1062 | ahd_print_register(NULL, 0, "ALLZEROS", 0xea, regvalue, cur_col, wrap) | ||
1063 | #endif | ||
1064 | |||
1065 | #if AIC_DEBUG_REGISTERS | ||
1066 | ahd_reg_print_t ahd_none_print; | 863 | ahd_reg_print_t ahd_none_print; |
1067 | #else | 864 | #else |
1068 | #define ahd_none_print(regvalue, cur_col, wrap) \ | 865 | #define ahd_none_print(regvalue, cur_col, wrap) \ |
@@ -1070,27 +867,6 @@ ahd_reg_print_t ahd_none_print; | |||
1070 | #endif | 867 | #endif |
1071 | 868 | ||
1072 | #if AIC_DEBUG_REGISTERS | 869 | #if AIC_DEBUG_REGISTERS |
1073 | ahd_reg_print_t ahd_sindir_print; | ||
1074 | #else | ||
1075 | #define ahd_sindir_print(regvalue, cur_col, wrap) \ | ||
1076 | ahd_print_register(NULL, 0, "SINDIR", 0xec, regvalue, cur_col, wrap) | ||
1077 | #endif | ||
1078 | |||
1079 | #if AIC_DEBUG_REGISTERS | ||
1080 | ahd_reg_print_t ahd_dindir_print; | ||
1081 | #else | ||
1082 | #define ahd_dindir_print(regvalue, cur_col, wrap) \ | ||
1083 | ahd_print_register(NULL, 0, "DINDIR", 0xed, regvalue, cur_col, wrap) | ||
1084 | #endif | ||
1085 | |||
1086 | #if AIC_DEBUG_REGISTERS | ||
1087 | ahd_reg_print_t ahd_stack_print; | ||
1088 | #else | ||
1089 | #define ahd_stack_print(regvalue, cur_col, wrap) \ | ||
1090 | ahd_print_register(NULL, 0, "STACK", 0xf2, regvalue, cur_col, wrap) | ||
1091 | #endif | ||
1092 | |||
1093 | #if AIC_DEBUG_REGISTERS | ||
1094 | ahd_reg_print_t ahd_intvec1_addr_print; | 870 | ahd_reg_print_t ahd_intvec1_addr_print; |
1095 | #else | 871 | #else |
1096 | #define ahd_intvec1_addr_print(regvalue, cur_col, wrap) \ | 872 | #define ahd_intvec1_addr_print(regvalue, cur_col, wrap) \ |
@@ -1126,17 +902,17 @@ ahd_reg_print_t ahd_accum_save_print; | |||
1126 | #endif | 902 | #endif |
1127 | 903 | ||
1128 | #if AIC_DEBUG_REGISTERS | 904 | #if AIC_DEBUG_REGISTERS |
1129 | ahd_reg_print_t ahd_sram_base_print; | 905 | ahd_reg_print_t ahd_waiting_scb_tails_print; |
1130 | #else | 906 | #else |
1131 | #define ahd_sram_base_print(regvalue, cur_col, wrap) \ | 907 | #define ahd_waiting_scb_tails_print(regvalue, cur_col, wrap) \ |
1132 | ahd_print_register(NULL, 0, "SRAM_BASE", 0x100, regvalue, cur_col, wrap) | 908 | ahd_print_register(NULL, 0, "WAITING_SCB_TAILS", 0x100, regvalue, cur_col, wrap) |
1133 | #endif | 909 | #endif |
1134 | 910 | ||
1135 | #if AIC_DEBUG_REGISTERS | 911 | #if AIC_DEBUG_REGISTERS |
1136 | ahd_reg_print_t ahd_waiting_scb_tails_print; | 912 | ahd_reg_print_t ahd_sram_base_print; |
1137 | #else | 913 | #else |
1138 | #define ahd_waiting_scb_tails_print(regvalue, cur_col, wrap) \ | 914 | #define ahd_sram_base_print(regvalue, cur_col, wrap) \ |
1139 | ahd_print_register(NULL, 0, "WAITING_SCB_TAILS", 0x100, regvalue, cur_col, wrap) | 915 | ahd_print_register(NULL, 0, "SRAM_BASE", 0x100, regvalue, cur_col, wrap) |
1140 | #endif | 916 | #endif |
1141 | 917 | ||
1142 | #if AIC_DEBUG_REGISTERS | 918 | #if AIC_DEBUG_REGISTERS |
@@ -1224,13 +1000,6 @@ ahd_reg_print_t ahd_msg_out_print; | |||
1224 | #endif | 1000 | #endif |
1225 | 1001 | ||
1226 | #if AIC_DEBUG_REGISTERS | 1002 | #if AIC_DEBUG_REGISTERS |
1227 | ahd_reg_print_t ahd_dmaparams_print; | ||
1228 | #else | ||
1229 | #define ahd_dmaparams_print(regvalue, cur_col, wrap) \ | ||
1230 | ahd_print_register(NULL, 0, "DMAPARAMS", 0x138, regvalue, cur_col, wrap) | ||
1231 | #endif | ||
1232 | |||
1233 | #if AIC_DEBUG_REGISTERS | ||
1234 | ahd_reg_print_t ahd_seq_flags_print; | 1003 | ahd_reg_print_t ahd_seq_flags_print; |
1235 | #else | 1004 | #else |
1236 | #define ahd_seq_flags_print(regvalue, cur_col, wrap) \ | 1005 | #define ahd_seq_flags_print(regvalue, cur_col, wrap) \ |
@@ -1238,20 +1007,6 @@ ahd_reg_print_t ahd_seq_flags_print; | |||
1238 | #endif | 1007 | #endif |
1239 | 1008 | ||
1240 | #if AIC_DEBUG_REGISTERS | 1009 | #if AIC_DEBUG_REGISTERS |
1241 | ahd_reg_print_t ahd_saved_scsiid_print; | ||
1242 | #else | ||
1243 | #define ahd_saved_scsiid_print(regvalue, cur_col, wrap) \ | ||
1244 | ahd_print_register(NULL, 0, "SAVED_SCSIID", 0x13a, regvalue, cur_col, wrap) | ||
1245 | #endif | ||
1246 | |||
1247 | #if AIC_DEBUG_REGISTERS | ||
1248 | ahd_reg_print_t ahd_saved_lun_print; | ||
1249 | #else | ||
1250 | #define ahd_saved_lun_print(regvalue, cur_col, wrap) \ | ||
1251 | ahd_print_register(NULL, 0, "SAVED_LUN", 0x13b, regvalue, cur_col, wrap) | ||
1252 | #endif | ||
1253 | |||
1254 | #if AIC_DEBUG_REGISTERS | ||
1255 | ahd_reg_print_t ahd_lastphase_print; | 1010 | ahd_reg_print_t ahd_lastphase_print; |
1256 | #else | 1011 | #else |
1257 | #define ahd_lastphase_print(regvalue, cur_col, wrap) \ | 1012 | #define ahd_lastphase_print(regvalue, cur_col, wrap) \ |
@@ -1273,20 +1028,6 @@ ahd_reg_print_t ahd_kernel_tqinpos_print; | |||
1273 | #endif | 1028 | #endif |
1274 | 1029 | ||
1275 | #if AIC_DEBUG_REGISTERS | 1030 | #if AIC_DEBUG_REGISTERS |
1276 | ahd_reg_print_t ahd_tqinpos_print; | ||
1277 | #else | ||
1278 | #define ahd_tqinpos_print(regvalue, cur_col, wrap) \ | ||
1279 | ahd_print_register(NULL, 0, "TQINPOS", 0x13f, regvalue, cur_col, wrap) | ||
1280 | #endif | ||
1281 | |||
1282 | #if AIC_DEBUG_REGISTERS | ||
1283 | ahd_reg_print_t ahd_shared_data_addr_print; | ||
1284 | #else | ||
1285 | #define ahd_shared_data_addr_print(regvalue, cur_col, wrap) \ | ||
1286 | ahd_print_register(NULL, 0, "SHARED_DATA_ADDR", 0x140, regvalue, cur_col, wrap) | ||
1287 | #endif | ||
1288 | |||
1289 | #if AIC_DEBUG_REGISTERS | ||
1290 | ahd_reg_print_t ahd_qoutfifo_next_addr_print; | 1031 | ahd_reg_print_t ahd_qoutfifo_next_addr_print; |
1291 | #else | 1032 | #else |
1292 | #define ahd_qoutfifo_next_addr_print(regvalue, cur_col, wrap) \ | 1033 | #define ahd_qoutfifo_next_addr_print(regvalue, cur_col, wrap) \ |
@@ -1294,20 +1035,6 @@ ahd_reg_print_t ahd_qoutfifo_next_addr_print; | |||
1294 | #endif | 1035 | #endif |
1295 | 1036 | ||
1296 | #if AIC_DEBUG_REGISTERS | 1037 | #if AIC_DEBUG_REGISTERS |
1297 | ahd_reg_print_t ahd_arg_1_print; | ||
1298 | #else | ||
1299 | #define ahd_arg_1_print(regvalue, cur_col, wrap) \ | ||
1300 | ahd_print_register(NULL, 0, "ARG_1", 0x148, regvalue, cur_col, wrap) | ||
1301 | #endif | ||
1302 | |||
1303 | #if AIC_DEBUG_REGISTERS | ||
1304 | ahd_reg_print_t ahd_arg_2_print; | ||
1305 | #else | ||
1306 | #define ahd_arg_2_print(regvalue, cur_col, wrap) \ | ||
1307 | ahd_print_register(NULL, 0, "ARG_2", 0x149, regvalue, cur_col, wrap) | ||
1308 | #endif | ||
1309 | |||
1310 | #if AIC_DEBUG_REGISTERS | ||
1311 | ahd_reg_print_t ahd_last_msg_print; | 1038 | ahd_reg_print_t ahd_last_msg_print; |
1312 | #else | 1039 | #else |
1313 | #define ahd_last_msg_print(regvalue, cur_col, wrap) \ | 1040 | #define ahd_last_msg_print(regvalue, cur_col, wrap) \ |
@@ -1406,13 +1133,6 @@ ahd_reg_print_t ahd_mk_message_scsiid_print; | |||
1406 | #endif | 1133 | #endif |
1407 | 1134 | ||
1408 | #if AIC_DEBUG_REGISTERS | 1135 | #if AIC_DEBUG_REGISTERS |
1409 | ahd_reg_print_t ahd_scb_residual_datacnt_print; | ||
1410 | #else | ||
1411 | #define ahd_scb_residual_datacnt_print(regvalue, cur_col, wrap) \ | ||
1412 | ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT", 0x180, regvalue, cur_col, wrap) | ||
1413 | #endif | ||
1414 | |||
1415 | #if AIC_DEBUG_REGISTERS | ||
1416 | ahd_reg_print_t ahd_scb_base_print; | 1136 | ahd_reg_print_t ahd_scb_base_print; |
1417 | #else | 1137 | #else |
1418 | #define ahd_scb_base_print(regvalue, cur_col, wrap) \ | 1138 | #define ahd_scb_base_print(regvalue, cur_col, wrap) \ |
@@ -1420,17 +1140,10 @@ ahd_reg_print_t ahd_scb_base_print; | |||
1420 | #endif | 1140 | #endif |
1421 | 1141 | ||
1422 | #if AIC_DEBUG_REGISTERS | 1142 | #if AIC_DEBUG_REGISTERS |
1423 | ahd_reg_print_t ahd_scb_residual_sgptr_print; | 1143 | ahd_reg_print_t ahd_scb_residual_datacnt_print; |
1424 | #else | ||
1425 | #define ahd_scb_residual_sgptr_print(regvalue, cur_col, wrap) \ | ||
1426 | ahd_print_register(NULL, 0, "SCB_RESIDUAL_SGPTR", 0x184, regvalue, cur_col, wrap) | ||
1427 | #endif | ||
1428 | |||
1429 | #if AIC_DEBUG_REGISTERS | ||
1430 | ahd_reg_print_t ahd_scb_scsi_status_print; | ||
1431 | #else | 1144 | #else |
1432 | #define ahd_scb_scsi_status_print(regvalue, cur_col, wrap) \ | 1145 | #define ahd_scb_residual_datacnt_print(regvalue, cur_col, wrap) \ |
1433 | ahd_print_register(NULL, 0, "SCB_SCSI_STATUS", 0x188, regvalue, cur_col, wrap) | 1146 | ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT", 0x180, regvalue, cur_col, wrap) |
1434 | #endif | 1147 | #endif |
1435 | 1148 | ||
1436 | #if AIC_DEBUG_REGISTERS | 1149 | #if AIC_DEBUG_REGISTERS |
@@ -1476,13 +1189,6 @@ ahd_reg_print_t ahd_scb_task_attribute_print; | |||
1476 | #endif | 1189 | #endif |
1477 | 1190 | ||
1478 | #if AIC_DEBUG_REGISTERS | 1191 | #if AIC_DEBUG_REGISTERS |
1479 | ahd_reg_print_t ahd_scb_cdb_len_print; | ||
1480 | #else | ||
1481 | #define ahd_scb_cdb_len_print(regvalue, cur_col, wrap) \ | ||
1482 | ahd_print_register(NULL, 0, "SCB_CDB_LEN", 0x196, regvalue, cur_col, wrap) | ||
1483 | #endif | ||
1484 | |||
1485 | #if AIC_DEBUG_REGISTERS | ||
1486 | ahd_reg_print_t ahd_scb_task_management_print; | 1192 | ahd_reg_print_t ahd_scb_task_management_print; |
1487 | #else | 1193 | #else |
1488 | #define ahd_scb_task_management_print(regvalue, cur_col, wrap) \ | 1194 | #define ahd_scb_task_management_print(regvalue, cur_col, wrap) \ |
@@ -1518,13 +1224,6 @@ ahd_reg_print_t ahd_scb_busaddr_print; | |||
1518 | #endif | 1224 | #endif |
1519 | 1225 | ||
1520 | #if AIC_DEBUG_REGISTERS | 1226 | #if AIC_DEBUG_REGISTERS |
1521 | ahd_reg_print_t ahd_scb_next_print; | ||
1522 | #else | ||
1523 | #define ahd_scb_next_print(regvalue, cur_col, wrap) \ | ||
1524 | ahd_print_register(NULL, 0, "SCB_NEXT", 0x1ac, regvalue, cur_col, wrap) | ||
1525 | #endif | ||
1526 | |||
1527 | #if AIC_DEBUG_REGISTERS | ||
1528 | ahd_reg_print_t ahd_scb_next2_print; | 1227 | ahd_reg_print_t ahd_scb_next2_print; |
1529 | #else | 1228 | #else |
1530 | #define ahd_scb_next2_print(regvalue, cur_col, wrap) \ | 1229 | #define ahd_scb_next2_print(regvalue, cur_col, wrap) \ |
@@ -1717,10 +1416,10 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print; | |||
1717 | 1416 | ||
1718 | #define SG_CACHE_PRE 0x1b | 1417 | #define SG_CACHE_PRE 0x1b |
1719 | 1418 | ||
1720 | #define TYPEPTR 0x20 | ||
1721 | |||
1722 | #define LQIN 0x20 | 1419 | #define LQIN 0x20 |
1723 | 1420 | ||
1421 | #define TYPEPTR 0x20 | ||
1422 | |||
1724 | #define TAGPTR 0x21 | 1423 | #define TAGPTR 0x21 |
1725 | 1424 | ||
1726 | #define LUNPTR 0x22 | 1425 | #define LUNPTR 0x22 |
@@ -1780,6 +1479,14 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print; | |||
1780 | #define SINGLECMD 0x02 | 1479 | #define SINGLECMD 0x02 |
1781 | #define ABORTPENDING 0x01 | 1480 | #define ABORTPENDING 0x01 |
1782 | 1481 | ||
1482 | #define SCSBIST0 0x39 | ||
1483 | #define GSBISTERR 0x40 | ||
1484 | #define GSBISTDONE 0x20 | ||
1485 | #define GSBISTRUN 0x10 | ||
1486 | #define OSBISTERR 0x04 | ||
1487 | #define OSBISTDONE 0x02 | ||
1488 | #define OSBISTRUN 0x01 | ||
1489 | |||
1783 | #define LQCTL2 0x39 | 1490 | #define LQCTL2 0x39 |
1784 | #define LQIRETRY 0x80 | 1491 | #define LQIRETRY 0x80 |
1785 | #define LQICONTINUE 0x40 | 1492 | #define LQICONTINUE 0x40 |
@@ -1790,13 +1497,10 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print; | |||
1790 | #define LQOTOIDLE 0x02 | 1497 | #define LQOTOIDLE 0x02 |
1791 | #define LQOPAUSE 0x01 | 1498 | #define LQOPAUSE 0x01 |
1792 | 1499 | ||
1793 | #define SCSBIST0 0x39 | 1500 | #define SCSBIST1 0x3a |
1794 | #define GSBISTERR 0x40 | 1501 | #define NTBISTERR 0x04 |
1795 | #define GSBISTDONE 0x20 | 1502 | #define NTBISTDONE 0x02 |
1796 | #define GSBISTRUN 0x10 | 1503 | #define NTBISTRUN 0x01 |
1797 | #define OSBISTERR 0x04 | ||
1798 | #define OSBISTDONE 0x02 | ||
1799 | #define OSBISTRUN 0x01 | ||
1800 | 1504 | ||
1801 | #define SCSISEQ0 0x3a | 1505 | #define SCSISEQ0 0x3a |
1802 | #define TEMODEO 0x80 | 1506 | #define TEMODEO 0x80 |
@@ -1805,15 +1509,8 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print; | |||
1805 | #define FORCEBUSFREE 0x10 | 1509 | #define FORCEBUSFREE 0x10 |
1806 | #define SCSIRSTO 0x01 | 1510 | #define SCSIRSTO 0x01 |
1807 | 1511 | ||
1808 | #define SCSBIST1 0x3a | ||
1809 | #define NTBISTERR 0x04 | ||
1810 | #define NTBISTDONE 0x02 | ||
1811 | #define NTBISTRUN 0x01 | ||
1812 | |||
1813 | #define SCSISEQ1 0x3b | 1512 | #define SCSISEQ1 0x3b |
1814 | 1513 | ||
1815 | #define BUSINITID 0x3c | ||
1816 | |||
1817 | #define SXFRCTL0 0x3c | 1514 | #define SXFRCTL0 0x3c |
1818 | #define DFON 0x80 | 1515 | #define DFON 0x80 |
1819 | #define DFPEXP 0x40 | 1516 | #define DFPEXP 0x40 |
@@ -1822,6 +1519,8 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print; | |||
1822 | 1519 | ||
1823 | #define DLCOUNT 0x3c | 1520 | #define DLCOUNT 0x3c |
1824 | 1521 | ||
1522 | #define BUSINITID 0x3c | ||
1523 | |||
1825 | #define SXFRCTL1 0x3d | 1524 | #define SXFRCTL1 0x3d |
1826 | #define BITBUCKET 0x80 | 1525 | #define BITBUCKET 0x80 |
1827 | #define ENSACHK 0x40 | 1526 | #define ENSACHK 0x40 |
@@ -1846,8 +1545,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print; | |||
1846 | #define CURRFIFO_1 0x01 | 1545 | #define CURRFIFO_1 0x01 |
1847 | #define CURRFIFO_0 0x00 | 1546 | #define CURRFIFO_0 0x00 |
1848 | 1547 | ||
1849 | #define MULTARGID 0x40 | ||
1850 | |||
1851 | #define SCSISIGO 0x40 | 1548 | #define SCSISIGO 0x40 |
1852 | #define CDO 0x80 | 1549 | #define CDO 0x80 |
1853 | #define IOO 0x40 | 1550 | #define IOO 0x40 |
@@ -1858,6 +1555,8 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print; | |||
1858 | #define REQO 0x02 | 1555 | #define REQO 0x02 |
1859 | #define ACKO 0x01 | 1556 | #define ACKO 0x01 |
1860 | 1557 | ||
1558 | #define MULTARGID 0x40 | ||
1559 | |||
1861 | #define SCSISIGI 0x41 | 1560 | #define SCSISIGI 0x41 |
1862 | #define ATNI 0x10 | 1561 | #define ATNI 0x10 |
1863 | #define SELI 0x08 | 1562 | #define SELI 0x08 |
@@ -1904,6 +1603,15 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print; | |||
1904 | #define ENAB20 0x04 | 1603 | #define ENAB20 0x04 |
1905 | #define SELWIDE 0x02 | 1604 | #define SELWIDE 0x02 |
1906 | 1605 | ||
1606 | #define CLRSINT0 0x4b | ||
1607 | #define CLRSELDO 0x40 | ||
1608 | #define CLRSELDI 0x20 | ||
1609 | #define CLRSELINGO 0x10 | ||
1610 | #define CLRIOERR 0x08 | ||
1611 | #define CLROVERRUN 0x04 | ||
1612 | #define CLRSPIORDY 0x02 | ||
1613 | #define CLRARBDO 0x01 | ||
1614 | |||
1907 | #define SSTAT0 0x4b | 1615 | #define SSTAT0 0x4b |
1908 | #define TARGET 0x80 | 1616 | #define TARGET 0x80 |
1909 | #define SELDO 0x40 | 1617 | #define SELDO 0x40 |
@@ -1923,14 +1631,14 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print; | |||
1923 | #define ENSPIORDY 0x02 | 1631 | #define ENSPIORDY 0x02 |
1924 | #define ENARBDO 0x01 | 1632 | #define ENARBDO 0x01 |
1925 | 1633 | ||
1926 | #define CLRSINT0 0x4b | 1634 | #define CLRSINT1 0x4c |
1927 | #define CLRSELDO 0x40 | 1635 | #define CLRSELTIMEO 0x80 |
1928 | #define CLRSELDI 0x20 | 1636 | #define CLRATNO 0x40 |
1929 | #define CLRSELINGO 0x10 | 1637 | #define CLRSCSIRSTI 0x20 |
1930 | #define CLRIOERR 0x08 | 1638 | #define CLRBUSFREE 0x08 |
1931 | #define CLROVERRUN 0x04 | 1639 | #define CLRSCSIPERR 0x04 |
1932 | #define CLRSPIORDY 0x02 | 1640 | #define CLRSTRB2FAST 0x02 |
1933 | #define CLRARBDO 0x01 | 1641 | #define CLRREQINIT 0x01 |
1934 | 1642 | ||
1935 | #define SSTAT1 0x4c | 1643 | #define SSTAT1 0x4c |
1936 | #define SELTO 0x80 | 1644 | #define SELTO 0x80 |
@@ -1942,15 +1650,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print; | |||
1942 | #define STRB2FAST 0x02 | 1650 | #define STRB2FAST 0x02 |
1943 | #define REQINIT 0x01 | 1651 | #define REQINIT 0x01 |
1944 | 1652 | ||
1945 | #define CLRSINT1 0x4c | ||
1946 | #define CLRSELTIMEO 0x80 | ||
1947 | #define CLRATNO 0x40 | ||
1948 | #define CLRSCSIRSTI 0x20 | ||
1949 | #define CLRBUSFREE 0x08 | ||
1950 | #define CLRSCSIPERR 0x04 | ||
1951 | #define CLRSTRB2FAST 0x02 | ||
1952 | #define CLRREQINIT 0x01 | ||
1953 | |||
1954 | #define SSTAT2 0x4d | 1653 | #define SSTAT2 0x4d |
1955 | #define BUSFREETIME 0xc0 | 1654 | #define BUSFREETIME 0xc0 |
1956 | #define NONPACKREQ 0x20 | 1655 | #define NONPACKREQ 0x20 |
@@ -1998,14 +1697,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print; | |||
1998 | #define LQIATNLQ 0x02 | 1697 | #define LQIATNLQ 0x02 |
1999 | #define LQIATNCMD 0x01 | 1698 | #define LQIATNCMD 0x01 |
2000 | 1699 | ||
2001 | #define LQIMODE0 0x50 | ||
2002 | #define ENLQIATNQASK 0x20 | ||
2003 | #define ENLQICRCT1 0x10 | ||
2004 | #define ENLQICRCT2 0x08 | ||
2005 | #define ENLQIBADLQT 0x04 | ||
2006 | #define ENLQIATNLQ 0x02 | ||
2007 | #define ENLQIATNCMD 0x01 | ||
2008 | |||
2009 | #define CLRLQIINT0 0x50 | 1700 | #define CLRLQIINT0 0x50 |
2010 | #define CLRLQIATNQAS 0x20 | 1701 | #define CLRLQIATNQAS 0x20 |
2011 | #define CLRLQICRCT1 0x10 | 1702 | #define CLRLQICRCT1 0x10 |
@@ -2014,6 +1705,14 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print; | |||
2014 | #define CLRLQIATNLQ 0x02 | 1705 | #define CLRLQIATNLQ 0x02 |
2015 | #define CLRLQIATNCMD 0x01 | 1706 | #define CLRLQIATNCMD 0x01 |
2016 | 1707 | ||
1708 | #define LQIMODE0 0x50 | ||
1709 | #define ENLQIATNQASK 0x20 | ||
1710 | #define ENLQICRCT1 0x10 | ||
1711 | #define ENLQICRCT2 0x08 | ||
1712 | #define ENLQIBADLQT 0x04 | ||
1713 | #define ENLQIATNLQ 0x02 | ||
1714 | #define ENLQIATNCMD 0x01 | ||
1715 | |||
2017 | #define LQIMODE1 0x51 | 1716 | #define LQIMODE1 0x51 |
2018 | #define ENLQIPHASE_LQ 0x80 | 1717 | #define ENLQIPHASE_LQ 0x80 |
2019 | #define ENLQIPHASE_NLQ 0x40 | 1718 | #define ENLQIPHASE_NLQ 0x40 |
@@ -2160,6 +1859,8 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print; | |||
2160 | #define CFG4ICMD 0x02 | 1859 | #define CFG4ICMD 0x02 |
2161 | #define CFG4TCMD 0x01 | 1860 | #define CFG4TCMD 0x01 |
2162 | 1861 | ||
1862 | #define CURRSCB 0x5c | ||
1863 | |||
2163 | #define SEQIMODE 0x5c | 1864 | #define SEQIMODE 0x5c |
2164 | #define ENCTXTDONE 0x40 | 1865 | #define ENCTXTDONE 0x40 |
2165 | #define ENSAVEPTRS 0x20 | 1866 | #define ENSAVEPTRS 0x20 |
@@ -2169,8 +1870,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print; | |||
2169 | #define ENCFG4ICMD 0x02 | 1870 | #define ENCFG4ICMD 0x02 |
2170 | #define ENCFG4TCMD 0x01 | 1871 | #define ENCFG4TCMD 0x01 |
2171 | 1872 | ||
2172 | #define CURRSCB 0x5c | ||
2173 | |||
2174 | #define MDFFSTAT 0x5d | 1873 | #define MDFFSTAT 0x5d |
2175 | #define SHCNTNEGATIVE 0x40 | 1874 | #define SHCNTNEGATIVE 0x40 |
2176 | #define SHCNTMINUS1 0x20 | 1875 | #define SHCNTMINUS1 0x20 |
@@ -2185,29 +1884,29 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print; | |||
2185 | 1884 | ||
2186 | #define DFFTAG 0x5e | 1885 | #define DFFTAG 0x5e |
2187 | 1886 | ||
1887 | #define LASTSCB 0x5e | ||
1888 | |||
2188 | #define SCSITEST 0x5e | 1889 | #define SCSITEST 0x5e |
2189 | #define CNTRTEST 0x08 | 1890 | #define CNTRTEST 0x08 |
2190 | #define SEL_TXPLL_DEBUG 0x04 | 1891 | #define SEL_TXPLL_DEBUG 0x04 |
2191 | 1892 | ||
2192 | #define LASTSCB 0x5e | ||
2193 | |||
2194 | #define IOPDNCTL 0x5f | 1893 | #define IOPDNCTL 0x5f |
2195 | #define DISABLE_OE 0x80 | 1894 | #define DISABLE_OE 0x80 |
2196 | #define PDN_IDIST 0x04 | 1895 | #define PDN_IDIST 0x04 |
2197 | #define PDN_DIFFSENSE 0x01 | 1896 | #define PDN_DIFFSENSE 0x01 |
2198 | 1897 | ||
2199 | #define DGRPCRCI 0x60 | ||
2200 | |||
2201 | #define SHADDR 0x60 | 1898 | #define SHADDR 0x60 |
2202 | 1899 | ||
2203 | #define NEGOADDR 0x60 | 1900 | #define NEGOADDR 0x60 |
2204 | 1901 | ||
2205 | #define NEGPERIOD 0x61 | 1902 | #define DGRPCRCI 0x60 |
2206 | 1903 | ||
2207 | #define NEGOFFSET 0x62 | 1904 | #define NEGPERIOD 0x61 |
2208 | 1905 | ||
2209 | #define PACKCRCI 0x62 | 1906 | #define PACKCRCI 0x62 |
2210 | 1907 | ||
1908 | #define NEGOFFSET 0x62 | ||
1909 | |||
2211 | #define NEGPPROPTS 0x63 | 1910 | #define NEGPPROPTS 0x63 |
2212 | #define PPROPT_PACE 0x08 | 1911 | #define PPROPT_PACE 0x08 |
2213 | #define PPROPT_QAS 0x04 | 1912 | #define PPROPT_QAS 0x04 |
@@ -2253,8 +1952,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print; | |||
2253 | 1952 | ||
2254 | #define SELOID 0x6b | 1953 | #define SELOID 0x6b |
2255 | 1954 | ||
2256 | #define FAIRNESS 0x6c | ||
2257 | |||
2258 | #define PLL400CTL0 0x6c | 1955 | #define PLL400CTL0 0x6c |
2259 | #define PLL_VCOSEL 0x80 | 1956 | #define PLL_VCOSEL 0x80 |
2260 | #define PLL_PWDN 0x40 | 1957 | #define PLL_PWDN 0x40 |
@@ -2264,6 +1961,8 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print; | |||
2264 | #define PLL_DLPF 0x02 | 1961 | #define PLL_DLPF 0x02 |
2265 | #define PLL_ENFBM 0x01 | 1962 | #define PLL_ENFBM 0x01 |
2266 | 1963 | ||
1964 | #define FAIRNESS 0x6c | ||
1965 | |||
2267 | #define PLL400CTL1 0x6d | 1966 | #define PLL400CTL1 0x6d |
2268 | #define PLL_CNTEN 0x80 | 1967 | #define PLL_CNTEN 0x80 |
2269 | #define PLL_CNTCLR 0x40 | 1968 | #define PLL_CNTCLR 0x40 |
@@ -2275,25 +1974,25 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print; | |||
2275 | 1974 | ||
2276 | #define HADDR 0x70 | 1975 | #define HADDR 0x70 |
2277 | 1976 | ||
2278 | #define HODMAADR 0x70 | ||
2279 | |||
2280 | #define PLLDELAY 0x70 | 1977 | #define PLLDELAY 0x70 |
2281 | #define SPLIT_DROP_REQ 0x80 | 1978 | #define SPLIT_DROP_REQ 0x80 |
2282 | 1979 | ||
2283 | #define HCNT 0x78 | 1980 | #define HODMAADR 0x70 |
2284 | 1981 | ||
2285 | #define HODMACNT 0x78 | 1982 | #define HODMACNT 0x78 |
2286 | 1983 | ||
2287 | #define HODMAEN 0x7a | 1984 | #define HCNT 0x78 |
2288 | 1985 | ||
2289 | #define SGHADDR 0x7c | 1986 | #define HODMAEN 0x7a |
2290 | 1987 | ||
2291 | #define SCBHADDR 0x7c | 1988 | #define SCBHADDR 0x7c |
2292 | 1989 | ||
2293 | #define SGHCNT 0x84 | 1990 | #define SGHADDR 0x7c |
2294 | 1991 | ||
2295 | #define SCBHCNT 0x84 | 1992 | #define SCBHCNT 0x84 |
2296 | 1993 | ||
1994 | #define SGHCNT 0x84 | ||
1995 | |||
2297 | #define DFF_THRSH 0x88 | 1996 | #define DFF_THRSH 0x88 |
2298 | #define WR_DFTHRSH 0x70 | 1997 | #define WR_DFTHRSH 0x70 |
2299 | #define RD_DFTHRSH 0x07 | 1998 | #define RD_DFTHRSH 0x07 |
@@ -2326,10 +2025,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print; | |||
2326 | 2025 | ||
2327 | #define CMCRXMSG0 0x90 | 2026 | #define CMCRXMSG0 0x90 |
2328 | 2027 | ||
2329 | #define OVLYRXMSG0 0x90 | ||
2330 | |||
2331 | #define DCHRXMSG0 0x90 | ||
2332 | |||
2333 | #define ROENABLE 0x90 | 2028 | #define ROENABLE 0x90 |
2334 | #define MSIROEN 0x20 | 2029 | #define MSIROEN 0x20 |
2335 | #define OVLYROEN 0x10 | 2030 | #define OVLYROEN 0x10 |
@@ -2338,11 +2033,11 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print; | |||
2338 | #define DCH1ROEN 0x02 | 2033 | #define DCH1ROEN 0x02 |
2339 | #define DCH0ROEN 0x01 | 2034 | #define DCH0ROEN 0x01 |
2340 | 2035 | ||
2341 | #define OVLYRXMSG1 0x91 | 2036 | #define OVLYRXMSG0 0x90 |
2342 | 2037 | ||
2343 | #define CMCRXMSG1 0x91 | 2038 | #define DCHRXMSG0 0x90 |
2344 | 2039 | ||
2345 | #define DCHRXMSG1 0x91 | 2040 | #define OVLYRXMSG1 0x91 |
2346 | 2041 | ||
2347 | #define NSENABLE 0x91 | 2042 | #define NSENABLE 0x91 |
2348 | #define MSINSEN 0x20 | 2043 | #define MSINSEN 0x20 |
@@ -2352,6 +2047,10 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print; | |||
2352 | #define DCH1NSEN 0x02 | 2047 | #define DCH1NSEN 0x02 |
2353 | #define DCH0NSEN 0x01 | 2048 | #define DCH0NSEN 0x01 |
2354 | 2049 | ||
2050 | #define CMCRXMSG1 0x91 | ||
2051 | |||
2052 | #define DCHRXMSG1 0x91 | ||
2053 | |||
2355 | #define DCHRXMSG2 0x92 | 2054 | #define DCHRXMSG2 0x92 |
2356 | 2055 | ||
2357 | #define CMCRXMSG2 0x92 | 2056 | #define CMCRXMSG2 0x92 |
@@ -2375,24 +2074,24 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print; | |||
2375 | #define TSCSERREN 0x02 | 2074 | #define TSCSERREN 0x02 |
2376 | #define CMPABCDIS 0x01 | 2075 | #define CMPABCDIS 0x01 |
2377 | 2076 | ||
2378 | #define CMCSEQBCNT 0x94 | ||
2379 | |||
2380 | #define OVLYSEQBCNT 0x94 | 2077 | #define OVLYSEQBCNT 0x94 |
2381 | 2078 | ||
2382 | #define DCHSEQBCNT 0x94 | 2079 | #define DCHSEQBCNT 0x94 |
2383 | 2080 | ||
2081 | #define CMCSEQBCNT 0x94 | ||
2082 | |||
2083 | #define CMCSPLTSTAT0 0x96 | ||
2084 | |||
2384 | #define DCHSPLTSTAT0 0x96 | 2085 | #define DCHSPLTSTAT0 0x96 |
2385 | 2086 | ||
2386 | #define OVLYSPLTSTAT0 0x96 | 2087 | #define OVLYSPLTSTAT0 0x96 |
2387 | 2088 | ||
2388 | #define CMCSPLTSTAT0 0x96 | 2089 | #define CMCSPLTSTAT1 0x97 |
2389 | 2090 | ||
2390 | #define OVLYSPLTSTAT1 0x97 | 2091 | #define OVLYSPLTSTAT1 0x97 |
2391 | 2092 | ||
2392 | #define DCHSPLTSTAT1 0x97 | 2093 | #define DCHSPLTSTAT1 0x97 |
2393 | 2094 | ||
2394 | #define CMCSPLTSTAT1 0x97 | ||
2395 | |||
2396 | #define SGRXMSG0 0x98 | 2095 | #define SGRXMSG0 0x98 |
2397 | #define CDNUM 0xf8 | 2096 | #define CDNUM 0xf8 |
2398 | #define CFNUM 0x07 | 2097 | #define CFNUM 0x07 |
@@ -2420,15 +2119,18 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print; | |||
2420 | #define TAG_NUM 0x1f | 2119 | #define TAG_NUM 0x1f |
2421 | #define RLXORD 0x10 | 2120 | #define RLXORD 0x10 |
2422 | 2121 | ||
2122 | #define SGSEQBCNT 0x9c | ||
2123 | |||
2423 | #define SLVSPLTOUTATTR0 0x9c | 2124 | #define SLVSPLTOUTATTR0 0x9c |
2424 | #define LOWER_BCNT 0xff | 2125 | #define LOWER_BCNT 0xff |
2425 | 2126 | ||
2426 | #define SGSEQBCNT 0x9c | ||
2427 | |||
2428 | #define SLVSPLTOUTATTR1 0x9d | 2127 | #define SLVSPLTOUTATTR1 0x9d |
2429 | #define CMPLT_DNUM 0xf8 | 2128 | #define CMPLT_DNUM 0xf8 |
2430 | #define CMPLT_FNUM 0x07 | 2129 | #define CMPLT_FNUM 0x07 |
2431 | 2130 | ||
2131 | #define SLVSPLTOUTATTR2 0x9e | ||
2132 | #define CMPLT_BNUM 0xff | ||
2133 | |||
2432 | #define SGSPLTSTAT0 0x9e | 2134 | #define SGSPLTSTAT0 0x9e |
2433 | #define STAETERM 0x80 | 2135 | #define STAETERM 0x80 |
2434 | #define SCBCERR 0x40 | 2136 | #define SCBCERR 0x40 |
@@ -2439,9 +2141,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print; | |||
2439 | #define RXSCEMSG 0x02 | 2141 | #define RXSCEMSG 0x02 |
2440 | #define RXSPLTRSP 0x01 | 2142 | #define RXSPLTRSP 0x01 |
2441 | 2143 | ||
2442 | #define SLVSPLTOUTATTR2 0x9e | ||
2443 | #define CMPLT_BNUM 0xff | ||
2444 | |||
2445 | #define SGSPLTSTAT1 0x9f | 2144 | #define SGSPLTSTAT1 0x9f |
2446 | #define RXDATABUCKET 0x01 | 2145 | #define RXDATABUCKET 0x01 |
2447 | 2146 | ||
@@ -2497,10 +2196,10 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print; | |||
2497 | 2196 | ||
2498 | #define CCSGADDR 0xac | 2197 | #define CCSGADDR 0xac |
2499 | 2198 | ||
2500 | #define CCSCBADDR 0xac | ||
2501 | |||
2502 | #define CCSCBADR_BK 0xac | 2199 | #define CCSCBADR_BK 0xac |
2503 | 2200 | ||
2201 | #define CCSCBADDR 0xac | ||
2202 | |||
2504 | #define CMC_RAMBIST 0xad | 2203 | #define CMC_RAMBIST 0xad |
2505 | #define SG_ELEMENT_SIZE 0x80 | 2204 | #define SG_ELEMENT_SIZE 0x80 |
2506 | #define SCBRAMBIST_FAIL 0x40 | 2205 | #define SCBRAMBIST_FAIL 0x40 |
@@ -2554,9 +2253,9 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print; | |||
2554 | #define SEEDAT 0xbc | 2253 | #define SEEDAT 0xbc |
2555 | 2254 | ||
2556 | #define SEECTL 0xbe | 2255 | #define SEECTL 0xbe |
2557 | #define SEEOP_EWDS 0x40 | ||
2558 | #define SEEOP_WALL 0x40 | 2256 | #define SEEOP_WALL 0x40 |
2559 | #define SEEOP_EWEN 0x40 | 2257 | #define SEEOP_EWEN 0x40 |
2258 | #define SEEOP_EWDS 0x40 | ||
2560 | #define SEEOPCODE 0x70 | 2259 | #define SEEOPCODE 0x70 |
2561 | #define SEERST 0x02 | 2260 | #define SEERST 0x02 |
2562 | #define SEESTART 0x01 | 2261 | #define SEESTART 0x01 |
@@ -2573,25 +2272,25 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print; | |||
2573 | 2272 | ||
2574 | #define SCBCNT 0xbf | 2273 | #define SCBCNT 0xbf |
2575 | 2274 | ||
2275 | #define DFWADDR 0xc0 | ||
2276 | |||
2576 | #define DSPFLTRCTL 0xc0 | 2277 | #define DSPFLTRCTL 0xc0 |
2577 | #define FLTRDISABLE 0x20 | 2278 | #define FLTRDISABLE 0x20 |
2578 | #define EDGESENSE 0x10 | 2279 | #define EDGESENSE 0x10 |
2579 | #define DSPFCNTSEL 0x0f | 2280 | #define DSPFCNTSEL 0x0f |
2580 | 2281 | ||
2581 | #define DFWADDR 0xc0 | ||
2582 | |||
2583 | #define DSPDATACTL 0xc1 | 2282 | #define DSPDATACTL 0xc1 |
2584 | #define BYPASSENAB 0x80 | 2283 | #define BYPASSENAB 0x80 |
2585 | #define DESQDIS 0x10 | 2284 | #define DESQDIS 0x10 |
2586 | #define RCVROFFSTDIS 0x04 | 2285 | #define RCVROFFSTDIS 0x04 |
2587 | #define XMITOFFSTDIS 0x02 | 2286 | #define XMITOFFSTDIS 0x02 |
2588 | 2287 | ||
2288 | #define DFRADDR 0xc2 | ||
2289 | |||
2589 | #define DSPREQCTL 0xc2 | 2290 | #define DSPREQCTL 0xc2 |
2590 | #define MANREQCTL 0xc0 | 2291 | #define MANREQCTL 0xc0 |
2591 | #define MANREQDLY 0x3f | 2292 | #define MANREQDLY 0x3f |
2592 | 2293 | ||
2593 | #define DFRADDR 0xc2 | ||
2594 | |||
2595 | #define DSPACKCTL 0xc3 | 2294 | #define DSPACKCTL 0xc3 |
2596 | #define MANACKCTL 0xc0 | 2295 | #define MANACKCTL 0xc0 |
2597 | #define MANACKDLY 0x3f | 2296 | #define MANACKDLY 0x3f |
@@ -2612,14 +2311,14 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print; | |||
2612 | 2311 | ||
2613 | #define WRTBIASCALC 0xc7 | 2312 | #define WRTBIASCALC 0xc7 |
2614 | 2313 | ||
2615 | #define DFPTRS 0xc8 | ||
2616 | |||
2617 | #define RCVRBIASCALC 0xc8 | 2314 | #define RCVRBIASCALC 0xc8 |
2618 | 2315 | ||
2619 | #define DFBKPTR 0xc9 | 2316 | #define DFPTRS 0xc8 |
2620 | 2317 | ||
2621 | #define SKEWCALC 0xc9 | 2318 | #define SKEWCALC 0xc9 |
2622 | 2319 | ||
2320 | #define DFBKPTR 0xc9 | ||
2321 | |||
2623 | #define DFDBCTL 0xcb | 2322 | #define DFDBCTL 0xcb |
2624 | #define DFF_CIO_WR_RDY 0x20 | 2323 | #define DFF_CIO_WR_RDY 0x20 |
2625 | #define DFF_CIO_RD_RDY 0x10 | 2324 | #define DFF_CIO_RD_RDY 0x10 |
@@ -2704,12 +2403,12 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print; | |||
2704 | 2403 | ||
2705 | #define ACCUM_SAVE 0xfa | 2404 | #define ACCUM_SAVE 0xfa |
2706 | 2405 | ||
2406 | #define WAITING_SCB_TAILS 0x100 | ||
2407 | |||
2707 | #define AHD_PCI_CONFIG_BASE 0x100 | 2408 | #define AHD_PCI_CONFIG_BASE 0x100 |
2708 | 2409 | ||
2709 | #define SRAM_BASE 0x100 | 2410 | #define SRAM_BASE 0x100 |
2710 | 2411 | ||
2711 | #define WAITING_SCB_TAILS 0x100 | ||
2712 | |||
2713 | #define WAITING_TID_HEAD 0x120 | 2412 | #define WAITING_TID_HEAD 0x120 |
2714 | 2413 | ||
2715 | #define WAITING_TID_TAIL 0x122 | 2414 | #define WAITING_TID_TAIL 0x122 |
@@ -2738,8 +2437,8 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print; | |||
2738 | #define PRELOADEN 0x80 | 2437 | #define PRELOADEN 0x80 |
2739 | #define WIDEODD 0x40 | 2438 | #define WIDEODD 0x40 |
2740 | #define SCSIEN 0x20 | 2439 | #define SCSIEN 0x20 |
2741 | #define SDMAENACK 0x10 | ||
2742 | #define SDMAEN 0x10 | 2440 | #define SDMAEN 0x10 |
2441 | #define SDMAENACK 0x10 | ||
2743 | #define HDMAEN 0x08 | 2442 | #define HDMAEN 0x08 |
2744 | #define HDMAENACK 0x08 | 2443 | #define HDMAENACK 0x08 |
2745 | #define DIRECTION 0x04 | 2444 | #define DIRECTION 0x04 |
@@ -2837,12 +2536,12 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print; | |||
2837 | 2536 | ||
2838 | #define MK_MESSAGE_SCSIID 0x162 | 2537 | #define MK_MESSAGE_SCSIID 0x162 |
2839 | 2538 | ||
2539 | #define SCB_BASE 0x180 | ||
2540 | |||
2840 | #define SCB_RESIDUAL_DATACNT 0x180 | 2541 | #define SCB_RESIDUAL_DATACNT 0x180 |
2841 | #define SCB_CDB_STORE 0x180 | 2542 | #define SCB_CDB_STORE 0x180 |
2842 | #define SCB_HOST_CDB_PTR 0x180 | 2543 | #define SCB_HOST_CDB_PTR 0x180 |
2843 | 2544 | ||
2844 | #define SCB_BASE 0x180 | ||
2845 | |||
2846 | #define SCB_RESIDUAL_SGPTR 0x184 | 2545 | #define SCB_RESIDUAL_SGPTR 0x184 |
2847 | #define SG_ADDR_MASK 0xf8 | 2546 | #define SG_ADDR_MASK 0xf8 |
2848 | #define SG_OVERRUN_RESID 0x02 | 2547 | #define SG_OVERRUN_RESID 0x02 |
@@ -2910,17 +2609,6 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print; | |||
2910 | #define SCB_DISCONNECTED_LISTS 0x1b8 | 2609 | #define SCB_DISCONNECTED_LISTS 0x1b8 |
2911 | 2610 | ||
2912 | 2611 | ||
2913 | #define CMD_GROUP_CODE_SHIFT 0x05 | ||
2914 | #define STIMESEL_MIN 0x18 | ||
2915 | #define STIMESEL_SHIFT 0x03 | ||
2916 | #define INVALID_ADDR 0x80 | ||
2917 | #define AHD_PRECOMP_MASK 0x07 | ||
2918 | #define TARGET_DATA_IN 0x01 | ||
2919 | #define CCSCBADDR_MAX 0x80 | ||
2920 | #define NUMDSPS 0x14 | ||
2921 | #define SEEOP_EWEN_ADDR 0xc0 | ||
2922 | #define AHD_ANNEXCOL_PER_DEV0 0x04 | ||
2923 | #define DST_MODE_SHIFT 0x04 | ||
2924 | #define AHD_TIMER_MAX_US 0x18ffe7 | 2612 | #define AHD_TIMER_MAX_US 0x18ffe7 |
2925 | #define AHD_TIMER_MAX_TICKS 0xffff | 2613 | #define AHD_TIMER_MAX_TICKS 0xffff |
2926 | #define AHD_SENSE_BUFSIZE 0x100 | 2614 | #define AHD_SENSE_BUFSIZE 0x100 |
@@ -2955,32 +2643,43 @@ ahd_reg_print_t ahd_scb_disconnected_lists_print; | |||
2955 | #define LUNLEN_SINGLE_LEVEL_LUN 0x0f | 2643 | #define LUNLEN_SINGLE_LEVEL_LUN 0x0f |
2956 | #define NVRAM_SCB_OFFSET 0x2c | 2644 | #define NVRAM_SCB_OFFSET 0x2c |
2957 | #define STATUS_PKT_SENSE 0xff | 2645 | #define STATUS_PKT_SENSE 0xff |
2646 | #define CMD_GROUP_CODE_SHIFT 0x05 | ||
2958 | #define MAX_OFFSET_PACED_BUG 0x7f | 2647 | #define MAX_OFFSET_PACED_BUG 0x7f |
2959 | #define STIMESEL_BUG_ADJ 0x08 | 2648 | #define STIMESEL_BUG_ADJ 0x08 |
2649 | #define STIMESEL_MIN 0x18 | ||
2650 | #define STIMESEL_SHIFT 0x03 | ||
2960 | #define CCSGRAM_MAXSEGS 0x10 | 2651 | #define CCSGRAM_MAXSEGS 0x10 |
2652 | #define INVALID_ADDR 0x80 | ||
2961 | #define SEEOP_ERAL_ADDR 0x80 | 2653 | #define SEEOP_ERAL_ADDR 0x80 |
2962 | #define AHD_SLEWRATE_DEF_REVB 0x08 | 2654 | #define AHD_SLEWRATE_DEF_REVB 0x08 |
2963 | #define AHD_PRECOMP_CUTBACK_17 0x04 | 2655 | #define AHD_PRECOMP_CUTBACK_17 0x04 |
2656 | #define AHD_PRECOMP_MASK 0x07 | ||
2964 | #define SRC_MODE_SHIFT 0x00 | 2657 | #define SRC_MODE_SHIFT 0x00 |
2965 | #define PKT_OVERRUN_BUFSIZE 0x200 | 2658 | #define PKT_OVERRUN_BUFSIZE 0x200 |
2966 | #define SCB_TRANSFER_SIZE_1BYTE_LUN 0x30 | 2659 | #define SCB_TRANSFER_SIZE_1BYTE_LUN 0x30 |
2660 | #define TARGET_DATA_IN 0x01 | ||
2967 | #define HOST_MSG 0xff | 2661 | #define HOST_MSG 0xff |
2968 | #define MAX_OFFSET 0xfe | 2662 | #define MAX_OFFSET 0xfe |
2969 | #define BUS_16_BIT 0x01 | 2663 | #define BUS_16_BIT 0x01 |
2664 | #define CCSCBADDR_MAX 0x80 | ||
2665 | #define NUMDSPS 0x14 | ||
2666 | #define SEEOP_EWEN_ADDR 0xc0 | ||
2667 | #define AHD_ANNEXCOL_PER_DEV0 0x04 | ||
2668 | #define DST_MODE_SHIFT 0x04 | ||
2970 | 2669 | ||
2971 | 2670 | ||
2972 | /* Downloaded Constant Definitions */ | 2671 | /* Downloaded Constant Definitions */ |
2973 | #define SG_SIZEOF 0x04 | ||
2974 | #define SG_PREFETCH_ALIGN_MASK 0x02 | ||
2975 | #define SG_PREFETCH_CNT_LIMIT 0x01 | ||
2976 | #define CACHELINE_MASK 0x07 | 2672 | #define CACHELINE_MASK 0x07 |
2977 | #define SCB_TRANSFER_SIZE 0x06 | 2673 | #define SCB_TRANSFER_SIZE 0x06 |
2978 | #define PKT_OVERRUN_BUFOFFSET 0x05 | 2674 | #define PKT_OVERRUN_BUFOFFSET 0x05 |
2675 | #define SG_SIZEOF 0x04 | ||
2979 | #define SG_PREFETCH_ADDR_MASK 0x03 | 2676 | #define SG_PREFETCH_ADDR_MASK 0x03 |
2677 | #define SG_PREFETCH_ALIGN_MASK 0x02 | ||
2678 | #define SG_PREFETCH_CNT_LIMIT 0x01 | ||
2980 | #define SG_PREFETCH_CNT 0x00 | 2679 | #define SG_PREFETCH_CNT 0x00 |
2981 | #define DOWNLOAD_CONST_COUNT 0x08 | 2680 | #define DOWNLOAD_CONST_COUNT 0x08 |
2982 | 2681 | ||
2983 | 2682 | ||
2984 | /* Exported Labels */ | 2683 | /* Exported Labels */ |
2985 | #define LABEL_timer_isr 0x28b | ||
2986 | #define LABEL_seq_isr 0x28f | 2684 | #define LABEL_seq_isr 0x28f |
2685 | #define LABEL_timer_isr 0x28b | ||
diff --git a/drivers/scsi/aic7xxx/aic79xx_reg_print.c_shipped b/drivers/scsi/aic7xxx/aic79xx_reg_print.c_shipped index c4c8a96bf5a3..f5ea715d6ac3 100644 --- a/drivers/scsi/aic7xxx/aic79xx_reg_print.c_shipped +++ b/drivers/scsi/aic7xxx/aic79xx_reg_print.c_shipped | |||
@@ -8,18 +8,6 @@ | |||
8 | 8 | ||
9 | #include "aic79xx_osm.h" | 9 | #include "aic79xx_osm.h" |
10 | 10 | ||
11 | static const ahd_reg_parse_entry_t MODE_PTR_parse_table[] = { | ||
12 | { "SRC_MODE", 0x07, 0x07 }, | ||
13 | { "DST_MODE", 0x70, 0x70 } | ||
14 | }; | ||
15 | |||
16 | int | ||
17 | ahd_mode_ptr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
18 | { | ||
19 | return (ahd_print_register(MODE_PTR_parse_table, 2, "MODE_PTR", | ||
20 | 0x00, regvalue, cur_col, wrap)); | ||
21 | } | ||
22 | |||
23 | static const ahd_reg_parse_entry_t INTSTAT_parse_table[] = { | 11 | static const ahd_reg_parse_entry_t INTSTAT_parse_table[] = { |
24 | { "SPLTINT", 0x01, 0x01 }, | 12 | { "SPLTINT", 0x01, 0x01 }, |
25 | { "CMDCMPLT", 0x02, 0x02 }, | 13 | { "CMDCMPLT", 0x02, 0x02 }, |
@@ -39,110 +27,6 @@ ahd_intstat_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
39 | 0x01, regvalue, cur_col, wrap)); | 27 | 0x01, regvalue, cur_col, wrap)); |
40 | } | 28 | } |
41 | 29 | ||
42 | static const ahd_reg_parse_entry_t SEQINTCODE_parse_table[] = { | ||
43 | { "NO_SEQINT", 0x00, 0xff }, | ||
44 | { "BAD_PHASE", 0x01, 0xff }, | ||
45 | { "SEND_REJECT", 0x02, 0xff }, | ||
46 | { "PROTO_VIOLATION", 0x03, 0xff }, | ||
47 | { "NO_MATCH", 0x04, 0xff }, | ||
48 | { "IGN_WIDE_RES", 0x05, 0xff }, | ||
49 | { "PDATA_REINIT", 0x06, 0xff }, | ||
50 | { "HOST_MSG_LOOP", 0x07, 0xff }, | ||
51 | { "BAD_STATUS", 0x08, 0xff }, | ||
52 | { "DATA_OVERRUN", 0x09, 0xff }, | ||
53 | { "MKMSG_FAILED", 0x0a, 0xff }, | ||
54 | { "MISSED_BUSFREE", 0x0b, 0xff }, | ||
55 | { "DUMP_CARD_STATE", 0x0c, 0xff }, | ||
56 | { "ILLEGAL_PHASE", 0x0d, 0xff }, | ||
57 | { "INVALID_SEQINT", 0x0e, 0xff }, | ||
58 | { "CFG4ISTAT_INTR", 0x0f, 0xff }, | ||
59 | { "STATUS_OVERRUN", 0x10, 0xff }, | ||
60 | { "CFG4OVERRUN", 0x11, 0xff }, | ||
61 | { "ENTERING_NONPACK", 0x12, 0xff }, | ||
62 | { "TASKMGMT_FUNC_COMPLETE",0x13, 0xff }, | ||
63 | { "TASKMGMT_CMD_CMPLT_OKAY",0x14, 0xff }, | ||
64 | { "TRACEPOINT0", 0x15, 0xff }, | ||
65 | { "TRACEPOINT1", 0x16, 0xff }, | ||
66 | { "TRACEPOINT2", 0x17, 0xff }, | ||
67 | { "TRACEPOINT3", 0x18, 0xff }, | ||
68 | { "SAW_HWERR", 0x19, 0xff }, | ||
69 | { "BAD_SCB_STATUS", 0x1a, 0xff } | ||
70 | }; | ||
71 | |||
72 | int | ||
73 | ahd_seqintcode_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
74 | { | ||
75 | return (ahd_print_register(SEQINTCODE_parse_table, 27, "SEQINTCODE", | ||
76 | 0x02, regvalue, cur_col, wrap)); | ||
77 | } | ||
78 | |||
79 | static const ahd_reg_parse_entry_t CLRINT_parse_table[] = { | ||
80 | { "CLRSPLTINT", 0x01, 0x01 }, | ||
81 | { "CLRCMDINT", 0x02, 0x02 }, | ||
82 | { "CLRSEQINT", 0x04, 0x04 }, | ||
83 | { "CLRSCSIINT", 0x08, 0x08 }, | ||
84 | { "CLRPCIINT", 0x10, 0x10 }, | ||
85 | { "CLRSWTMINT", 0x20, 0x20 }, | ||
86 | { "CLRBRKADRINT", 0x40, 0x40 }, | ||
87 | { "CLRHWERRINT", 0x80, 0x80 } | ||
88 | }; | ||
89 | |||
90 | int | ||
91 | ahd_clrint_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
92 | { | ||
93 | return (ahd_print_register(CLRINT_parse_table, 8, "CLRINT", | ||
94 | 0x03, regvalue, cur_col, wrap)); | ||
95 | } | ||
96 | |||
97 | static const ahd_reg_parse_entry_t ERROR_parse_table[] = { | ||
98 | { "DSCTMOUT", 0x02, 0x02 }, | ||
99 | { "ILLOPCODE", 0x04, 0x04 }, | ||
100 | { "SQPARERR", 0x08, 0x08 }, | ||
101 | { "DPARERR", 0x10, 0x10 }, | ||
102 | { "MPARERR", 0x20, 0x20 }, | ||
103 | { "CIOACCESFAIL", 0x40, 0x40 }, | ||
104 | { "CIOPARERR", 0x80, 0x80 } | ||
105 | }; | ||
106 | |||
107 | int | ||
108 | ahd_error_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
109 | { | ||
110 | return (ahd_print_register(ERROR_parse_table, 7, "ERROR", | ||
111 | 0x04, regvalue, cur_col, wrap)); | ||
112 | } | ||
113 | |||
114 | static const ahd_reg_parse_entry_t HCNTRL_parse_table[] = { | ||
115 | { "CHIPRST", 0x01, 0x01 }, | ||
116 | { "CHIPRSTACK", 0x01, 0x01 }, | ||
117 | { "INTEN", 0x02, 0x02 }, | ||
118 | { "PAUSE", 0x04, 0x04 }, | ||
119 | { "SWTIMER_START_B", 0x08, 0x08 }, | ||
120 | { "SWINT", 0x10, 0x10 }, | ||
121 | { "POWRDN", 0x40, 0x40 }, | ||
122 | { "SEQ_RESET", 0x80, 0x80 } | ||
123 | }; | ||
124 | |||
125 | int | ||
126 | ahd_hcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
127 | { | ||
128 | return (ahd_print_register(HCNTRL_parse_table, 8, "HCNTRL", | ||
129 | 0x05, regvalue, cur_col, wrap)); | ||
130 | } | ||
131 | |||
132 | int | ||
133 | ahd_hnscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
134 | { | ||
135 | return (ahd_print_register(NULL, 0, "HNSCB_QOFF", | ||
136 | 0x06, regvalue, cur_col, wrap)); | ||
137 | } | ||
138 | |||
139 | int | ||
140 | ahd_hescb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
141 | { | ||
142 | return (ahd_print_register(NULL, 0, "HESCB_QOFF", | ||
143 | 0x08, regvalue, cur_col, wrap)); | ||
144 | } | ||
145 | |||
146 | static const ahd_reg_parse_entry_t HS_MAILBOX_parse_table[] = { | 30 | static const ahd_reg_parse_entry_t HS_MAILBOX_parse_table[] = { |
147 | { "ENINT_COALESCE", 0x40, 0x40 }, | 31 | { "ENINT_COALESCE", 0x40, 0x40 }, |
148 | { "HOST_TQINPOS", 0x80, 0x80 } | 32 | { "HOST_TQINPOS", 0x80, 0x80 } |
@@ -170,77 +54,6 @@ ahd_seqintstat_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
170 | 0x0c, regvalue, cur_col, wrap)); | 54 | 0x0c, regvalue, cur_col, wrap)); |
171 | } | 55 | } |
172 | 56 | ||
173 | static const ahd_reg_parse_entry_t CLRSEQINTSTAT_parse_table[] = { | ||
174 | { "CLRSEQ_SPLTINT", 0x01, 0x01 }, | ||
175 | { "CLRSEQ_PCIINT", 0x02, 0x02 }, | ||
176 | { "CLRSEQ_SCSIINT", 0x04, 0x04 }, | ||
177 | { "CLRSEQ_SEQINT", 0x08, 0x08 }, | ||
178 | { "CLRSEQ_SWTMRTO", 0x10, 0x10 } | ||
179 | }; | ||
180 | |||
181 | int | ||
182 | ahd_clrseqintstat_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
183 | { | ||
184 | return (ahd_print_register(CLRSEQINTSTAT_parse_table, 5, "CLRSEQINTSTAT", | ||
185 | 0x0c, regvalue, cur_col, wrap)); | ||
186 | } | ||
187 | |||
188 | int | ||
189 | ahd_swtimer_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
190 | { | ||
191 | return (ahd_print_register(NULL, 0, "SWTIMER", | ||
192 | 0x0e, regvalue, cur_col, wrap)); | ||
193 | } | ||
194 | |||
195 | int | ||
196 | ahd_snscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
197 | { | ||
198 | return (ahd_print_register(NULL, 0, "SNSCB_QOFF", | ||
199 | 0x10, regvalue, cur_col, wrap)); | ||
200 | } | ||
201 | |||
202 | int | ||
203 | ahd_sescb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
204 | { | ||
205 | return (ahd_print_register(NULL, 0, "SESCB_QOFF", | ||
206 | 0x12, regvalue, cur_col, wrap)); | ||
207 | } | ||
208 | |||
209 | int | ||
210 | ahd_sdscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
211 | { | ||
212 | return (ahd_print_register(NULL, 0, "SDSCB_QOFF", | ||
213 | 0x14, regvalue, cur_col, wrap)); | ||
214 | } | ||
215 | |||
216 | static const ahd_reg_parse_entry_t QOFF_CTLSTA_parse_table[] = { | ||
217 | { "SCB_QSIZE_4", 0x00, 0x0f }, | ||
218 | { "SCB_QSIZE_8", 0x01, 0x0f }, | ||
219 | { "SCB_QSIZE_16", 0x02, 0x0f }, | ||
220 | { "SCB_QSIZE_32", 0x03, 0x0f }, | ||
221 | { "SCB_QSIZE_64", 0x04, 0x0f }, | ||
222 | { "SCB_QSIZE_128", 0x05, 0x0f }, | ||
223 | { "SCB_QSIZE_256", 0x06, 0x0f }, | ||
224 | { "SCB_QSIZE_512", 0x07, 0x0f }, | ||
225 | { "SCB_QSIZE_1024", 0x08, 0x0f }, | ||
226 | { "SCB_QSIZE_2048", 0x09, 0x0f }, | ||
227 | { "SCB_QSIZE_4096", 0x0a, 0x0f }, | ||
228 | { "SCB_QSIZE_8192", 0x0b, 0x0f }, | ||
229 | { "SCB_QSIZE_16384", 0x0c, 0x0f }, | ||
230 | { "SCB_QSIZE", 0x0f, 0x0f }, | ||
231 | { "HS_MAILBOX_ACT", 0x10, 0x10 }, | ||
232 | { "SDSCB_ROLLOVR", 0x20, 0x20 }, | ||
233 | { "NEW_SCB_AVAIL", 0x40, 0x40 }, | ||
234 | { "EMPTY_SCB_AVAIL", 0x80, 0x80 } | ||
235 | }; | ||
236 | |||
237 | int | ||
238 | ahd_qoff_ctlsta_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
239 | { | ||
240 | return (ahd_print_register(QOFF_CTLSTA_parse_table, 18, "QOFF_CTLSTA", | ||
241 | 0x16, regvalue, cur_col, wrap)); | ||
242 | } | ||
243 | |||
244 | static const ahd_reg_parse_entry_t INTCTL_parse_table[] = { | 57 | static const ahd_reg_parse_entry_t INTCTL_parse_table[] = { |
245 | { "SPLTINTEN", 0x01, 0x01 }, | 58 | { "SPLTINTEN", 0x01, 0x01 }, |
246 | { "SEQINTEN", 0x02, 0x02 }, | 59 | { "SEQINTEN", 0x02, 0x02 }, |
@@ -280,22 +93,6 @@ ahd_dfcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
280 | 0x19, regvalue, cur_col, wrap)); | 93 | 0x19, regvalue, cur_col, wrap)); |
281 | } | 94 | } |
282 | 95 | ||
283 | static const ahd_reg_parse_entry_t DSCOMMAND0_parse_table[] = { | ||
284 | { "CIOPARCKEN", 0x01, 0x01 }, | ||
285 | { "DISABLE_TWATE", 0x02, 0x02 }, | ||
286 | { "EXTREQLCK", 0x10, 0x10 }, | ||
287 | { "MPARCKEN", 0x20, 0x20 }, | ||
288 | { "DPARCKEN", 0x40, 0x40 }, | ||
289 | { "CACHETHEN", 0x80, 0x80 } | ||
290 | }; | ||
291 | |||
292 | int | ||
293 | ahd_dscommand0_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
294 | { | ||
295 | return (ahd_print_register(DSCOMMAND0_parse_table, 6, "DSCOMMAND0", | ||
296 | 0x19, regvalue, cur_col, wrap)); | ||
297 | } | ||
298 | |||
299 | static const ahd_reg_parse_entry_t DFSTATUS_parse_table[] = { | 96 | static const ahd_reg_parse_entry_t DFSTATUS_parse_table[] = { |
300 | { "FIFOEMP", 0x01, 0x01 }, | 97 | { "FIFOEMP", 0x01, 0x01 }, |
301 | { "FIFOFULL", 0x02, 0x02 }, | 98 | { "FIFOFULL", 0x02, 0x02 }, |
@@ -327,146 +124,6 @@ ahd_sg_cache_shadow_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
327 | 0x1b, regvalue, cur_col, wrap)); | 124 | 0x1b, regvalue, cur_col, wrap)); |
328 | } | 125 | } |
329 | 126 | ||
330 | static const ahd_reg_parse_entry_t SG_CACHE_PRE_parse_table[] = { | ||
331 | { "LAST_SEG", 0x02, 0x02 }, | ||
332 | { "ODD_SEG", 0x04, 0x04 }, | ||
333 | { "SG_ADDR_MASK", 0xf8, 0xf8 } | ||
334 | }; | ||
335 | |||
336 | int | ||
337 | ahd_sg_cache_pre_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
338 | { | ||
339 | return (ahd_print_register(SG_CACHE_PRE_parse_table, 3, "SG_CACHE_PRE", | ||
340 | 0x1b, regvalue, cur_col, wrap)); | ||
341 | } | ||
342 | |||
343 | int | ||
344 | ahd_lqin_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
345 | { | ||
346 | return (ahd_print_register(NULL, 0, "LQIN", | ||
347 | 0x20, regvalue, cur_col, wrap)); | ||
348 | } | ||
349 | |||
350 | int | ||
351 | ahd_lunptr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
352 | { | ||
353 | return (ahd_print_register(NULL, 0, "LUNPTR", | ||
354 | 0x22, regvalue, cur_col, wrap)); | ||
355 | } | ||
356 | |||
357 | int | ||
358 | ahd_cmdlenptr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
359 | { | ||
360 | return (ahd_print_register(NULL, 0, "CMDLENPTR", | ||
361 | 0x25, regvalue, cur_col, wrap)); | ||
362 | } | ||
363 | |||
364 | int | ||
365 | ahd_attrptr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
366 | { | ||
367 | return (ahd_print_register(NULL, 0, "ATTRPTR", | ||
368 | 0x26, regvalue, cur_col, wrap)); | ||
369 | } | ||
370 | |||
371 | int | ||
372 | ahd_flagptr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
373 | { | ||
374 | return (ahd_print_register(NULL, 0, "FLAGPTR", | ||
375 | 0x27, regvalue, cur_col, wrap)); | ||
376 | } | ||
377 | |||
378 | int | ||
379 | ahd_cmdptr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
380 | { | ||
381 | return (ahd_print_register(NULL, 0, "CMDPTR", | ||
382 | 0x28, regvalue, cur_col, wrap)); | ||
383 | } | ||
384 | |||
385 | int | ||
386 | ahd_qnextptr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
387 | { | ||
388 | return (ahd_print_register(NULL, 0, "QNEXTPTR", | ||
389 | 0x29, regvalue, cur_col, wrap)); | ||
390 | } | ||
391 | |||
392 | int | ||
393 | ahd_abrtbyteptr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
394 | { | ||
395 | return (ahd_print_register(NULL, 0, "ABRTBYTEPTR", | ||
396 | 0x2b, regvalue, cur_col, wrap)); | ||
397 | } | ||
398 | |||
399 | int | ||
400 | ahd_abrtbitptr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
401 | { | ||
402 | return (ahd_print_register(NULL, 0, "ABRTBITPTR", | ||
403 | 0x2c, regvalue, cur_col, wrap)); | ||
404 | } | ||
405 | |||
406 | static const ahd_reg_parse_entry_t LUNLEN_parse_table[] = { | ||
407 | { "ILUNLEN", 0x0f, 0x0f }, | ||
408 | { "TLUNLEN", 0xf0, 0xf0 } | ||
409 | }; | ||
410 | |||
411 | int | ||
412 | ahd_lunlen_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
413 | { | ||
414 | return (ahd_print_register(LUNLEN_parse_table, 2, "LUNLEN", | ||
415 | 0x30, regvalue, cur_col, wrap)); | ||
416 | } | ||
417 | |||
418 | int | ||
419 | ahd_cdblimit_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
420 | { | ||
421 | return (ahd_print_register(NULL, 0, "CDBLIMIT", | ||
422 | 0x31, regvalue, cur_col, wrap)); | ||
423 | } | ||
424 | |||
425 | int | ||
426 | ahd_maxcmd_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
427 | { | ||
428 | return (ahd_print_register(NULL, 0, "MAXCMD", | ||
429 | 0x32, regvalue, cur_col, wrap)); | ||
430 | } | ||
431 | |||
432 | int | ||
433 | ahd_maxcmdcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
434 | { | ||
435 | return (ahd_print_register(NULL, 0, "MAXCMDCNT", | ||
436 | 0x33, regvalue, cur_col, wrap)); | ||
437 | } | ||
438 | |||
439 | static const ahd_reg_parse_entry_t LQCTL1_parse_table[] = { | ||
440 | { "ABORTPENDING", 0x01, 0x01 }, | ||
441 | { "SINGLECMD", 0x02, 0x02 }, | ||
442 | { "PCI2PCI", 0x04, 0x04 } | ||
443 | }; | ||
444 | |||
445 | int | ||
446 | ahd_lqctl1_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
447 | { | ||
448 | return (ahd_print_register(LQCTL1_parse_table, 3, "LQCTL1", | ||
449 | 0x38, regvalue, cur_col, wrap)); | ||
450 | } | ||
451 | |||
452 | static const ahd_reg_parse_entry_t LQCTL2_parse_table[] = { | ||
453 | { "LQOPAUSE", 0x01, 0x01 }, | ||
454 | { "LQOTOIDLE", 0x02, 0x02 }, | ||
455 | { "LQOCONTINUE", 0x04, 0x04 }, | ||
456 | { "LQORETRY", 0x08, 0x08 }, | ||
457 | { "LQIPAUSE", 0x10, 0x10 }, | ||
458 | { "LQITOIDLE", 0x20, 0x20 }, | ||
459 | { "LQICONTINUE", 0x40, 0x40 }, | ||
460 | { "LQIRETRY", 0x80, 0x80 } | ||
461 | }; | ||
462 | |||
463 | int | ||
464 | ahd_lqctl2_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
465 | { | ||
466 | return (ahd_print_register(LQCTL2_parse_table, 8, "LQCTL2", | ||
467 | 0x39, regvalue, cur_col, wrap)); | ||
468 | } | ||
469 | |||
470 | static const ahd_reg_parse_entry_t SCSISEQ0_parse_table[] = { | 127 | static const ahd_reg_parse_entry_t SCSISEQ0_parse_table[] = { |
471 | { "SCSIRSTO", 0x01, 0x01 }, | 128 | { "SCSIRSTO", 0x01, 0x01 }, |
472 | { "FORCEBUSFREE", 0x10, 0x10 }, | 129 | { "FORCEBUSFREE", 0x10, 0x10 }, |
@@ -498,37 +155,6 @@ ahd_scsiseq1_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
498 | 0x3b, regvalue, cur_col, wrap)); | 155 | 0x3b, regvalue, cur_col, wrap)); |
499 | } | 156 | } |
500 | 157 | ||
501 | static const ahd_reg_parse_entry_t SXFRCTL0_parse_table[] = { | ||
502 | { "SPIOEN", 0x08, 0x08 }, | ||
503 | { "BIOSCANCELEN", 0x10, 0x10 }, | ||
504 | { "DFPEXP", 0x40, 0x40 }, | ||
505 | { "DFON", 0x80, 0x80 } | ||
506 | }; | ||
507 | |||
508 | int | ||
509 | ahd_sxfrctl0_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
510 | { | ||
511 | return (ahd_print_register(SXFRCTL0_parse_table, 4, "SXFRCTL0", | ||
512 | 0x3c, regvalue, cur_col, wrap)); | ||
513 | } | ||
514 | |||
515 | static const ahd_reg_parse_entry_t SXFRCTL1_parse_table[] = { | ||
516 | { "STPWEN", 0x01, 0x01 }, | ||
517 | { "ACTNEGEN", 0x02, 0x02 }, | ||
518 | { "ENSTIMER", 0x04, 0x04 }, | ||
519 | { "STIMESEL", 0x18, 0x18 }, | ||
520 | { "ENSPCHK", 0x20, 0x20 }, | ||
521 | { "ENSACHK", 0x40, 0x40 }, | ||
522 | { "BITBUCKET", 0x80, 0x80 } | ||
523 | }; | ||
524 | |||
525 | int | ||
526 | ahd_sxfrctl1_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
527 | { | ||
528 | return (ahd_print_register(SXFRCTL1_parse_table, 7, "SXFRCTL1", | ||
529 | 0x3d, regvalue, cur_col, wrap)); | ||
530 | } | ||
531 | |||
532 | static const ahd_reg_parse_entry_t DFFSTAT_parse_table[] = { | 158 | static const ahd_reg_parse_entry_t DFFSTAT_parse_table[] = { |
533 | { "CURRFIFO_0", 0x00, 0x03 }, | 159 | { "CURRFIFO_0", 0x00, 0x03 }, |
534 | { "CURRFIFO_1", 0x01, 0x03 }, | 160 | { "CURRFIFO_1", 0x01, 0x03 }, |
@@ -545,40 +171,6 @@ ahd_dffstat_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
545 | 0x3f, regvalue, cur_col, wrap)); | 171 | 0x3f, regvalue, cur_col, wrap)); |
546 | } | 172 | } |
547 | 173 | ||
548 | int | ||
549 | ahd_multargid_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
550 | { | ||
551 | return (ahd_print_register(NULL, 0, "MULTARGID", | ||
552 | 0x40, regvalue, cur_col, wrap)); | ||
553 | } | ||
554 | |||
555 | static const ahd_reg_parse_entry_t SCSISIGO_parse_table[] = { | ||
556 | { "P_DATAOUT", 0x00, 0xe0 }, | ||
557 | { "P_DATAOUT_DT", 0x20, 0xe0 }, | ||
558 | { "P_DATAIN", 0x40, 0xe0 }, | ||
559 | { "P_DATAIN_DT", 0x60, 0xe0 }, | ||
560 | { "P_COMMAND", 0x80, 0xe0 }, | ||
561 | { "P_MESGOUT", 0xa0, 0xe0 }, | ||
562 | { "P_STATUS", 0xc0, 0xe0 }, | ||
563 | { "P_MESGIN", 0xe0, 0xe0 }, | ||
564 | { "ACKO", 0x01, 0x01 }, | ||
565 | { "REQO", 0x02, 0x02 }, | ||
566 | { "BSYO", 0x04, 0x04 }, | ||
567 | { "SELO", 0x08, 0x08 }, | ||
568 | { "ATNO", 0x10, 0x10 }, | ||
569 | { "MSGO", 0x20, 0x20 }, | ||
570 | { "IOO", 0x40, 0x40 }, | ||
571 | { "CDO", 0x80, 0x80 }, | ||
572 | { "PHASE_MASK", 0xe0, 0xe0 } | ||
573 | }; | ||
574 | |||
575 | int | ||
576 | ahd_scsisigo_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
577 | { | ||
578 | return (ahd_print_register(SCSISIGO_parse_table, 17, "SCSISIGO", | ||
579 | 0x40, regvalue, cur_col, wrap)); | ||
580 | } | ||
581 | |||
582 | static const ahd_reg_parse_entry_t SCSISIGI_parse_table[] = { | 174 | static const ahd_reg_parse_entry_t SCSISIGI_parse_table[] = { |
583 | { "P_DATAOUT", 0x00, 0xe0 }, | 175 | { "P_DATAOUT", 0x00, 0xe0 }, |
584 | { "P_DATAOUT_DT", 0x20, 0xe0 }, | 176 | { "P_DATAOUT_DT", 0x20, 0xe0 }, |
@@ -624,31 +216,12 @@ ahd_scsiphase_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
624 | } | 216 | } |
625 | 217 | ||
626 | int | 218 | int |
627 | ahd_scsidat_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
628 | { | ||
629 | return (ahd_print_register(NULL, 0, "SCSIDAT", | ||
630 | 0x44, regvalue, cur_col, wrap)); | ||
631 | } | ||
632 | |||
633 | int | ||
634 | ahd_scsibus_print(u_int regvalue, u_int *cur_col, u_int wrap) | 219 | ahd_scsibus_print(u_int regvalue, u_int *cur_col, u_int wrap) |
635 | { | 220 | { |
636 | return (ahd_print_register(NULL, 0, "SCSIBUS", | 221 | return (ahd_print_register(NULL, 0, "SCSIBUS", |
637 | 0x46, regvalue, cur_col, wrap)); | 222 | 0x46, regvalue, cur_col, wrap)); |
638 | } | 223 | } |
639 | 224 | ||
640 | static const ahd_reg_parse_entry_t TARGIDIN_parse_table[] = { | ||
641 | { "TARGID", 0x0f, 0x0f }, | ||
642 | { "CLKOUT", 0x80, 0x80 } | ||
643 | }; | ||
644 | |||
645 | int | ||
646 | ahd_targidin_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
647 | { | ||
648 | return (ahd_print_register(TARGIDIN_parse_table, 2, "TARGIDIN", | ||
649 | 0x48, regvalue, cur_col, wrap)); | ||
650 | } | ||
651 | |||
652 | static const ahd_reg_parse_entry_t SELID_parse_table[] = { | 225 | static const ahd_reg_parse_entry_t SELID_parse_table[] = { |
653 | { "ONEBIT", 0x08, 0x08 }, | 226 | { "ONEBIT", 0x08, 0x08 }, |
654 | { "SELID_MASK", 0xf0, 0xf0 } | 227 | { "SELID_MASK", 0xf0, 0xf0 } |
@@ -661,38 +234,6 @@ ahd_selid_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
661 | 0x49, regvalue, cur_col, wrap)); | 234 | 0x49, regvalue, cur_col, wrap)); |
662 | } | 235 | } |
663 | 236 | ||
664 | static const ahd_reg_parse_entry_t OPTIONMODE_parse_table[] = { | ||
665 | { "AUTO_MSGOUT_DE", 0x02, 0x02 }, | ||
666 | { "ENDGFORMCHK", 0x04, 0x04 }, | ||
667 | { "BUSFREEREV", 0x10, 0x10 }, | ||
668 | { "BIASCANCTL", 0x20, 0x20 }, | ||
669 | { "AUTOACKEN", 0x40, 0x40 }, | ||
670 | { "BIOSCANCTL", 0x80, 0x80 }, | ||
671 | { "OPTIONMODE_DEFAULTS",0x02, 0x02 } | ||
672 | }; | ||
673 | |||
674 | int | ||
675 | ahd_optionmode_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
676 | { | ||
677 | return (ahd_print_register(OPTIONMODE_parse_table, 7, "OPTIONMODE", | ||
678 | 0x4a, regvalue, cur_col, wrap)); | ||
679 | } | ||
680 | |||
681 | static const ahd_reg_parse_entry_t SBLKCTL_parse_table[] = { | ||
682 | { "SELWIDE", 0x02, 0x02 }, | ||
683 | { "ENAB20", 0x04, 0x04 }, | ||
684 | { "ENAB40", 0x08, 0x08 }, | ||
685 | { "DIAGLEDON", 0x40, 0x40 }, | ||
686 | { "DIAGLEDEN", 0x80, 0x80 } | ||
687 | }; | ||
688 | |||
689 | int | ||
690 | ahd_sblkctl_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
691 | { | ||
692 | return (ahd_print_register(SBLKCTL_parse_table, 5, "SBLKCTL", | ||
693 | 0x4a, regvalue, cur_col, wrap)); | ||
694 | } | ||
695 | |||
696 | static const ahd_reg_parse_entry_t SSTAT0_parse_table[] = { | 237 | static const ahd_reg_parse_entry_t SSTAT0_parse_table[] = { |
697 | { "ARBDO", 0x01, 0x01 }, | 238 | { "ARBDO", 0x01, 0x01 }, |
698 | { "SPIORDY", 0x02, 0x02 }, | 239 | { "SPIORDY", 0x02, 0x02 }, |
@@ -728,23 +269,6 @@ ahd_simode0_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
728 | 0x4b, regvalue, cur_col, wrap)); | 269 | 0x4b, regvalue, cur_col, wrap)); |
729 | } | 270 | } |
730 | 271 | ||
731 | static const ahd_reg_parse_entry_t CLRSINT0_parse_table[] = { | ||
732 | { "CLRARBDO", 0x01, 0x01 }, | ||
733 | { "CLRSPIORDY", 0x02, 0x02 }, | ||
734 | { "CLROVERRUN", 0x04, 0x04 }, | ||
735 | { "CLRIOERR", 0x08, 0x08 }, | ||
736 | { "CLRSELINGO", 0x10, 0x10 }, | ||
737 | { "CLRSELDI", 0x20, 0x20 }, | ||
738 | { "CLRSELDO", 0x40, 0x40 } | ||
739 | }; | ||
740 | |||
741 | int | ||
742 | ahd_clrsint0_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
743 | { | ||
744 | return (ahd_print_register(CLRSINT0_parse_table, 7, "CLRSINT0", | ||
745 | 0x4b, regvalue, cur_col, wrap)); | ||
746 | } | ||
747 | |||
748 | static const ahd_reg_parse_entry_t SSTAT1_parse_table[] = { | 272 | static const ahd_reg_parse_entry_t SSTAT1_parse_table[] = { |
749 | { "REQINIT", 0x01, 0x01 }, | 273 | { "REQINIT", 0x01, 0x01 }, |
750 | { "STRB2FAST", 0x02, 0x02 }, | 274 | { "STRB2FAST", 0x02, 0x02 }, |
@@ -763,23 +287,6 @@ ahd_sstat1_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
763 | 0x4c, regvalue, cur_col, wrap)); | 287 | 0x4c, regvalue, cur_col, wrap)); |
764 | } | 288 | } |
765 | 289 | ||
766 | static const ahd_reg_parse_entry_t CLRSINT1_parse_table[] = { | ||
767 | { "CLRREQINIT", 0x01, 0x01 }, | ||
768 | { "CLRSTRB2FAST", 0x02, 0x02 }, | ||
769 | { "CLRSCSIPERR", 0x04, 0x04 }, | ||
770 | { "CLRBUSFREE", 0x08, 0x08 }, | ||
771 | { "CLRSCSIRSTI", 0x20, 0x20 }, | ||
772 | { "CLRATNO", 0x40, 0x40 }, | ||
773 | { "CLRSELTIMEO", 0x80, 0x80 } | ||
774 | }; | ||
775 | |||
776 | int | ||
777 | ahd_clrsint1_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
778 | { | ||
779 | return (ahd_print_register(CLRSINT1_parse_table, 7, "CLRSINT1", | ||
780 | 0x4c, regvalue, cur_col, wrap)); | ||
781 | } | ||
782 | |||
783 | static const ahd_reg_parse_entry_t SSTAT2_parse_table[] = { | 290 | static const ahd_reg_parse_entry_t SSTAT2_parse_table[] = { |
784 | { "BUSFREE_LQO", 0x40, 0xc0 }, | 291 | { "BUSFREE_LQO", 0x40, 0xc0 }, |
785 | { "BUSFREE_DFF0", 0x80, 0xc0 }, | 292 | { "BUSFREE_DFF0", 0x80, 0xc0 }, |
@@ -800,20 +307,6 @@ ahd_sstat2_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
800 | 0x4d, regvalue, cur_col, wrap)); | 307 | 0x4d, regvalue, cur_col, wrap)); |
801 | } | 308 | } |
802 | 309 | ||
803 | static const ahd_reg_parse_entry_t CLRSINT2_parse_table[] = { | ||
804 | { "CLRDMADONE", 0x01, 0x01 }, | ||
805 | { "CLRSDONE", 0x02, 0x02 }, | ||
806 | { "CLRWIDE_RES", 0x04, 0x04 }, | ||
807 | { "CLRNONPACKREQ", 0x20, 0x20 } | ||
808 | }; | ||
809 | |||
810 | int | ||
811 | ahd_clrsint2_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
812 | { | ||
813 | return (ahd_print_register(CLRSINT2_parse_table, 4, "CLRSINT2", | ||
814 | 0x4d, regvalue, cur_col, wrap)); | ||
815 | } | ||
816 | |||
817 | static const ahd_reg_parse_entry_t PERRDIAG_parse_table[] = { | 310 | static const ahd_reg_parse_entry_t PERRDIAG_parse_table[] = { |
818 | { "DTERR", 0x01, 0x01 }, | 311 | { "DTERR", 0x01, 0x01 }, |
819 | { "DGFORMERR", 0x02, 0x02 }, | 312 | { "DGFORMERR", 0x02, 0x02 }, |
@@ -833,26 +326,12 @@ ahd_perrdiag_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
833 | } | 326 | } |
834 | 327 | ||
835 | int | 328 | int |
836 | ahd_lqistate_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
837 | { | ||
838 | return (ahd_print_register(NULL, 0, "LQISTATE", | ||
839 | 0x4e, regvalue, cur_col, wrap)); | ||
840 | } | ||
841 | |||
842 | int | ||
843 | ahd_soffcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) | 329 | ahd_soffcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) |
844 | { | 330 | { |
845 | return (ahd_print_register(NULL, 0, "SOFFCNT", | 331 | return (ahd_print_register(NULL, 0, "SOFFCNT", |
846 | 0x4f, regvalue, cur_col, wrap)); | 332 | 0x4f, regvalue, cur_col, wrap)); |
847 | } | 333 | } |
848 | 334 | ||
849 | int | ||
850 | ahd_lqostate_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
851 | { | ||
852 | return (ahd_print_register(NULL, 0, "LQOSTATE", | ||
853 | 0x4f, regvalue, cur_col, wrap)); | ||
854 | } | ||
855 | |||
856 | static const ahd_reg_parse_entry_t LQISTAT0_parse_table[] = { | 335 | static const ahd_reg_parse_entry_t LQISTAT0_parse_table[] = { |
857 | { "LQIATNCMD", 0x01, 0x01 }, | 336 | { "LQIATNCMD", 0x01, 0x01 }, |
858 | { "LQIATNLQ", 0x02, 0x02 }, | 337 | { "LQIATNLQ", 0x02, 0x02 }, |
@@ -869,56 +348,6 @@ ahd_lqistat0_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
869 | 0x50, regvalue, cur_col, wrap)); | 348 | 0x50, regvalue, cur_col, wrap)); |
870 | } | 349 | } |
871 | 350 | ||
872 | static const ahd_reg_parse_entry_t LQIMODE0_parse_table[] = { | ||
873 | { "ENLQIATNCMD", 0x01, 0x01 }, | ||
874 | { "ENLQIATNLQ", 0x02, 0x02 }, | ||
875 | { "ENLQIBADLQT", 0x04, 0x04 }, | ||
876 | { "ENLQICRCT2", 0x08, 0x08 }, | ||
877 | { "ENLQICRCT1", 0x10, 0x10 }, | ||
878 | { "ENLQIATNQASK", 0x20, 0x20 } | ||
879 | }; | ||
880 | |||
881 | int | ||
882 | ahd_lqimode0_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
883 | { | ||
884 | return (ahd_print_register(LQIMODE0_parse_table, 6, "LQIMODE0", | ||
885 | 0x50, regvalue, cur_col, wrap)); | ||
886 | } | ||
887 | |||
888 | static const ahd_reg_parse_entry_t CLRLQIINT0_parse_table[] = { | ||
889 | { "CLRLQIATNCMD", 0x01, 0x01 }, | ||
890 | { "CLRLQIATNLQ", 0x02, 0x02 }, | ||
891 | { "CLRLQIBADLQT", 0x04, 0x04 }, | ||
892 | { "CLRLQICRCT2", 0x08, 0x08 }, | ||
893 | { "CLRLQICRCT1", 0x10, 0x10 }, | ||
894 | { "CLRLQIATNQAS", 0x20, 0x20 } | ||
895 | }; | ||
896 | |||
897 | int | ||
898 | ahd_clrlqiint0_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
899 | { | ||
900 | return (ahd_print_register(CLRLQIINT0_parse_table, 6, "CLRLQIINT0", | ||
901 | 0x50, regvalue, cur_col, wrap)); | ||
902 | } | ||
903 | |||
904 | static const ahd_reg_parse_entry_t LQIMODE1_parse_table[] = { | ||
905 | { "ENLQIOVERI_NLQ", 0x01, 0x01 }, | ||
906 | { "ENLQIOVERI_LQ", 0x02, 0x02 }, | ||
907 | { "ENLQIBADLQI", 0x04, 0x04 }, | ||
908 | { "ENLQICRCI_NLQ", 0x08, 0x08 }, | ||
909 | { "ENLQICRCI_LQ", 0x10, 0x10 }, | ||
910 | { "ENLIQABORT", 0x20, 0x20 }, | ||
911 | { "ENLQIPHASE_NLQ", 0x40, 0x40 }, | ||
912 | { "ENLQIPHASE_LQ", 0x80, 0x80 } | ||
913 | }; | ||
914 | |||
915 | int | ||
916 | ahd_lqimode1_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
917 | { | ||
918 | return (ahd_print_register(LQIMODE1_parse_table, 8, "LQIMODE1", | ||
919 | 0x51, regvalue, cur_col, wrap)); | ||
920 | } | ||
921 | |||
922 | static const ahd_reg_parse_entry_t LQISTAT1_parse_table[] = { | 351 | static const ahd_reg_parse_entry_t LQISTAT1_parse_table[] = { |
923 | { "LQIOVERI_NLQ", 0x01, 0x01 }, | 352 | { "LQIOVERI_NLQ", 0x01, 0x01 }, |
924 | { "LQIOVERI_LQ", 0x02, 0x02 }, | 353 | { "LQIOVERI_LQ", 0x02, 0x02 }, |
@@ -937,24 +366,6 @@ ahd_lqistat1_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
937 | 0x51, regvalue, cur_col, wrap)); | 366 | 0x51, regvalue, cur_col, wrap)); |
938 | } | 367 | } |
939 | 368 | ||
940 | static const ahd_reg_parse_entry_t CLRLQIINT1_parse_table[] = { | ||
941 | { "CLRLQIOVERI_NLQ", 0x01, 0x01 }, | ||
942 | { "CLRLQIOVERI_LQ", 0x02, 0x02 }, | ||
943 | { "CLRLQIBADLQI", 0x04, 0x04 }, | ||
944 | { "CLRLQICRCI_NLQ", 0x08, 0x08 }, | ||
945 | { "CLRLQICRCI_LQ", 0x10, 0x10 }, | ||
946 | { "CLRLIQABORT", 0x20, 0x20 }, | ||
947 | { "CLRLQIPHASE_NLQ", 0x40, 0x40 }, | ||
948 | { "CLRLQIPHASE_LQ", 0x80, 0x80 } | ||
949 | }; | ||
950 | |||
951 | int | ||
952 | ahd_clrlqiint1_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
953 | { | ||
954 | return (ahd_print_register(CLRLQIINT1_parse_table, 8, "CLRLQIINT1", | ||
955 | 0x51, regvalue, cur_col, wrap)); | ||
956 | } | ||
957 | |||
958 | static const ahd_reg_parse_entry_t LQISTAT2_parse_table[] = { | 369 | static const ahd_reg_parse_entry_t LQISTAT2_parse_table[] = { |
959 | { "LQIGSAVAIL", 0x01, 0x01 }, | 370 | { "LQIGSAVAIL", 0x01, 0x01 }, |
960 | { "LQISTOPCMD", 0x02, 0x02 }, | 371 | { "LQISTOPCMD", 0x02, 0x02 }, |
@@ -985,30 +396,6 @@ ahd_sstat3_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
985 | 0x53, regvalue, cur_col, wrap)); | 396 | 0x53, regvalue, cur_col, wrap)); |
986 | } | 397 | } |
987 | 398 | ||
988 | static const ahd_reg_parse_entry_t SIMODE3_parse_table[] = { | ||
989 | { "ENOSRAMPERR", 0x01, 0x01 }, | ||
990 | { "ENNTRAMPERR", 0x02, 0x02 } | ||
991 | }; | ||
992 | |||
993 | int | ||
994 | ahd_simode3_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
995 | { | ||
996 | return (ahd_print_register(SIMODE3_parse_table, 2, "SIMODE3", | ||
997 | 0x53, regvalue, cur_col, wrap)); | ||
998 | } | ||
999 | |||
1000 | static const ahd_reg_parse_entry_t CLRSINT3_parse_table[] = { | ||
1001 | { "CLROSRAMPERR", 0x01, 0x01 }, | ||
1002 | { "CLRNTRAMPERR", 0x02, 0x02 } | ||
1003 | }; | ||
1004 | |||
1005 | int | ||
1006 | ahd_clrsint3_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1007 | { | ||
1008 | return (ahd_print_register(CLRSINT3_parse_table, 2, "CLRSINT3", | ||
1009 | 0x53, regvalue, cur_col, wrap)); | ||
1010 | } | ||
1011 | |||
1012 | static const ahd_reg_parse_entry_t LQOSTAT0_parse_table[] = { | 399 | static const ahd_reg_parse_entry_t LQOSTAT0_parse_table[] = { |
1013 | { "LQOTCRC", 0x01, 0x01 }, | 400 | { "LQOTCRC", 0x01, 0x01 }, |
1014 | { "LQOATNPKT", 0x02, 0x02 }, | 401 | { "LQOATNPKT", 0x02, 0x02 }, |
@@ -1024,51 +411,6 @@ ahd_lqostat0_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
1024 | 0x54, regvalue, cur_col, wrap)); | 411 | 0x54, regvalue, cur_col, wrap)); |
1025 | } | 412 | } |
1026 | 413 | ||
1027 | static const ahd_reg_parse_entry_t CLRLQOINT0_parse_table[] = { | ||
1028 | { "CLRLQOTCRC", 0x01, 0x01 }, | ||
1029 | { "CLRLQOATNPKT", 0x02, 0x02 }, | ||
1030 | { "CLRLQOATNLQ", 0x04, 0x04 }, | ||
1031 | { "CLRLQOSTOPT2", 0x08, 0x08 }, | ||
1032 | { "CLRLQOTARGSCBPERR", 0x10, 0x10 } | ||
1033 | }; | ||
1034 | |||
1035 | int | ||
1036 | ahd_clrlqoint0_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1037 | { | ||
1038 | return (ahd_print_register(CLRLQOINT0_parse_table, 5, "CLRLQOINT0", | ||
1039 | 0x54, regvalue, cur_col, wrap)); | ||
1040 | } | ||
1041 | |||
1042 | static const ahd_reg_parse_entry_t LQOMODE0_parse_table[] = { | ||
1043 | { "ENLQOTCRC", 0x01, 0x01 }, | ||
1044 | { "ENLQOATNPKT", 0x02, 0x02 }, | ||
1045 | { "ENLQOATNLQ", 0x04, 0x04 }, | ||
1046 | { "ENLQOSTOPT2", 0x08, 0x08 }, | ||
1047 | { "ENLQOTARGSCBPERR", 0x10, 0x10 } | ||
1048 | }; | ||
1049 | |||
1050 | int | ||
1051 | ahd_lqomode0_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1052 | { | ||
1053 | return (ahd_print_register(LQOMODE0_parse_table, 5, "LQOMODE0", | ||
1054 | 0x54, regvalue, cur_col, wrap)); | ||
1055 | } | ||
1056 | |||
1057 | static const ahd_reg_parse_entry_t LQOMODE1_parse_table[] = { | ||
1058 | { "ENLQOPHACHGINPKT", 0x01, 0x01 }, | ||
1059 | { "ENLQOBUSFREE", 0x02, 0x02 }, | ||
1060 | { "ENLQOBADQAS", 0x04, 0x04 }, | ||
1061 | { "ENLQOSTOPI2", 0x08, 0x08 }, | ||
1062 | { "ENLQOINITSCBPERR", 0x10, 0x10 } | ||
1063 | }; | ||
1064 | |||
1065 | int | ||
1066 | ahd_lqomode1_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1067 | { | ||
1068 | return (ahd_print_register(LQOMODE1_parse_table, 5, "LQOMODE1", | ||
1069 | 0x55, regvalue, cur_col, wrap)); | ||
1070 | } | ||
1071 | |||
1072 | static const ahd_reg_parse_entry_t LQOSTAT1_parse_table[] = { | 414 | static const ahd_reg_parse_entry_t LQOSTAT1_parse_table[] = { |
1073 | { "LQOPHACHGINPKT", 0x01, 0x01 }, | 415 | { "LQOPHACHGINPKT", 0x01, 0x01 }, |
1074 | { "LQOBUSFREE", 0x02, 0x02 }, | 416 | { "LQOBUSFREE", 0x02, 0x02 }, |
@@ -1084,21 +426,6 @@ ahd_lqostat1_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
1084 | 0x55, regvalue, cur_col, wrap)); | 426 | 0x55, regvalue, cur_col, wrap)); |
1085 | } | 427 | } |
1086 | 428 | ||
1087 | static const ahd_reg_parse_entry_t CLRLQOINT1_parse_table[] = { | ||
1088 | { "CLRLQOPHACHGINPKT", 0x01, 0x01 }, | ||
1089 | { "CLRLQOBUSFREE", 0x02, 0x02 }, | ||
1090 | { "CLRLQOBADQAS", 0x04, 0x04 }, | ||
1091 | { "CLRLQOSTOPI2", 0x08, 0x08 }, | ||
1092 | { "CLRLQOINITSCBPERR", 0x10, 0x10 } | ||
1093 | }; | ||
1094 | |||
1095 | int | ||
1096 | ahd_clrlqoint1_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1097 | { | ||
1098 | return (ahd_print_register(CLRLQOINT1_parse_table, 5, "CLRLQOINT1", | ||
1099 | 0x55, regvalue, cur_col, wrap)); | ||
1100 | } | ||
1101 | |||
1102 | static const ahd_reg_parse_entry_t LQOSTAT2_parse_table[] = { | 429 | static const ahd_reg_parse_entry_t LQOSTAT2_parse_table[] = { |
1103 | { "LQOSTOP0", 0x01, 0x01 }, | 430 | { "LQOSTOP0", 0x01, 0x01 }, |
1104 | { "LQOPHACHGOUTPKT", 0x02, 0x02 }, | 431 | { "LQOPHACHGOUTPKT", 0x02, 0x02 }, |
@@ -1113,13 +440,6 @@ ahd_lqostat2_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
1113 | 0x56, regvalue, cur_col, wrap)); | 440 | 0x56, regvalue, cur_col, wrap)); |
1114 | } | 441 | } |
1115 | 442 | ||
1116 | int | ||
1117 | ahd_os_space_cnt_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1118 | { | ||
1119 | return (ahd_print_register(NULL, 0, "OS_SPACE_CNT", | ||
1120 | 0x56, regvalue, cur_col, wrap)); | ||
1121 | } | ||
1122 | |||
1123 | static const ahd_reg_parse_entry_t SIMODE1_parse_table[] = { | 443 | static const ahd_reg_parse_entry_t SIMODE1_parse_table[] = { |
1124 | { "ENREQINIT", 0x01, 0x01 }, | 444 | { "ENREQINIT", 0x01, 0x01 }, |
1125 | { "ENSTRB2FAST", 0x02, 0x02 }, | 445 | { "ENSTRB2FAST", 0x02, 0x02 }, |
@@ -1138,13 +458,6 @@ ahd_simode1_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
1138 | 0x57, regvalue, cur_col, wrap)); | 458 | 0x57, regvalue, cur_col, wrap)); |
1139 | } | 459 | } |
1140 | 460 | ||
1141 | int | ||
1142 | ahd_gsfifo_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1143 | { | ||
1144 | return (ahd_print_register(NULL, 0, "GSFIFO", | ||
1145 | 0x58, regvalue, cur_col, wrap)); | ||
1146 | } | ||
1147 | |||
1148 | static const ahd_reg_parse_entry_t DFFSXFRCTL_parse_table[] = { | 461 | static const ahd_reg_parse_entry_t DFFSXFRCTL_parse_table[] = { |
1149 | { "RSTCHN", 0x01, 0x01 }, | 462 | { "RSTCHN", 0x01, 0x01 }, |
1150 | { "CLRCHN", 0x02, 0x02 }, | 463 | { "CLRCHN", 0x02, 0x02 }, |
@@ -1159,44 +472,6 @@ ahd_dffsxfrctl_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
1159 | 0x5a, regvalue, cur_col, wrap)); | 472 | 0x5a, regvalue, cur_col, wrap)); |
1160 | } | 473 | } |
1161 | 474 | ||
1162 | static const ahd_reg_parse_entry_t LQOSCSCTL_parse_table[] = { | ||
1163 | { "LQONOCHKOVER", 0x01, 0x01 }, | ||
1164 | { "LQONOHOLDLACK", 0x02, 0x02 }, | ||
1165 | { "LQOBUSETDLY", 0x40, 0x40 }, | ||
1166 | { "LQOH2A_VERSION", 0x80, 0x80 } | ||
1167 | }; | ||
1168 | |||
1169 | int | ||
1170 | ahd_lqoscsctl_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1171 | { | ||
1172 | return (ahd_print_register(LQOSCSCTL_parse_table, 4, "LQOSCSCTL", | ||
1173 | 0x5a, regvalue, cur_col, wrap)); | ||
1174 | } | ||
1175 | |||
1176 | int | ||
1177 | ahd_nextscb_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1178 | { | ||
1179 | return (ahd_print_register(NULL, 0, "NEXTSCB", | ||
1180 | 0x5a, regvalue, cur_col, wrap)); | ||
1181 | } | ||
1182 | |||
1183 | static const ahd_reg_parse_entry_t CLRSEQINTSRC_parse_table[] = { | ||
1184 | { "CLRCFG4TCMD", 0x01, 0x01 }, | ||
1185 | { "CLRCFG4ICMD", 0x02, 0x02 }, | ||
1186 | { "CLRCFG4TSTAT", 0x04, 0x04 }, | ||
1187 | { "CLRCFG4ISTAT", 0x08, 0x08 }, | ||
1188 | { "CLRCFG4DATA", 0x10, 0x10 }, | ||
1189 | { "CLRSAVEPTRS", 0x20, 0x20 }, | ||
1190 | { "CLRCTXTDONE", 0x40, 0x40 } | ||
1191 | }; | ||
1192 | |||
1193 | int | ||
1194 | ahd_clrseqintsrc_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1195 | { | ||
1196 | return (ahd_print_register(CLRSEQINTSRC_parse_table, 7, "CLRSEQINTSRC", | ||
1197 | 0x5b, regvalue, cur_col, wrap)); | ||
1198 | } | ||
1199 | |||
1200 | static const ahd_reg_parse_entry_t SEQINTSRC_parse_table[] = { | 475 | static const ahd_reg_parse_entry_t SEQINTSRC_parse_table[] = { |
1201 | { "CFG4TCMD", 0x01, 0x01 }, | 476 | { "CFG4TCMD", 0x01, 0x01 }, |
1202 | { "CFG4ICMD", 0x02, 0x02 }, | 477 | { "CFG4ICMD", 0x02, 0x02 }, |
@@ -1231,13 +506,6 @@ ahd_seqimode_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
1231 | 0x5c, regvalue, cur_col, wrap)); | 506 | 0x5c, regvalue, cur_col, wrap)); |
1232 | } | 507 | } |
1233 | 508 | ||
1234 | int | ||
1235 | ahd_currscb_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1236 | { | ||
1237 | return (ahd_print_register(NULL, 0, "CURRSCB", | ||
1238 | 0x5c, regvalue, cur_col, wrap)); | ||
1239 | } | ||
1240 | |||
1241 | static const ahd_reg_parse_entry_t MDFFSTAT_parse_table[] = { | 509 | static const ahd_reg_parse_entry_t MDFFSTAT_parse_table[] = { |
1242 | { "FIFOFREE", 0x01, 0x01 }, | 510 | { "FIFOFREE", 0x01, 0x01 }, |
1243 | { "DATAINFIFO", 0x02, 0x02 }, | 511 | { "DATAINFIFO", 0x02, 0x02 }, |
@@ -1256,308 +524,12 @@ ahd_mdffstat_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
1256 | } | 524 | } |
1257 | 525 | ||
1258 | int | 526 | int |
1259 | ahd_lastscb_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1260 | { | ||
1261 | return (ahd_print_register(NULL, 0, "LASTSCB", | ||
1262 | 0x5e, regvalue, cur_col, wrap)); | ||
1263 | } | ||
1264 | |||
1265 | int | ||
1266 | ahd_shaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1267 | { | ||
1268 | return (ahd_print_register(NULL, 0, "SHADDR", | ||
1269 | 0x60, regvalue, cur_col, wrap)); | ||
1270 | } | ||
1271 | |||
1272 | int | ||
1273 | ahd_negoaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1274 | { | ||
1275 | return (ahd_print_register(NULL, 0, "NEGOADDR", | ||
1276 | 0x60, regvalue, cur_col, wrap)); | ||
1277 | } | ||
1278 | |||
1279 | int | ||
1280 | ahd_negperiod_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1281 | { | ||
1282 | return (ahd_print_register(NULL, 0, "NEGPERIOD", | ||
1283 | 0x61, regvalue, cur_col, wrap)); | ||
1284 | } | ||
1285 | |||
1286 | int | ||
1287 | ahd_negoffset_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1288 | { | ||
1289 | return (ahd_print_register(NULL, 0, "NEGOFFSET", | ||
1290 | 0x62, regvalue, cur_col, wrap)); | ||
1291 | } | ||
1292 | |||
1293 | static const ahd_reg_parse_entry_t NEGPPROPTS_parse_table[] = { | ||
1294 | { "PPROPT_IUT", 0x01, 0x01 }, | ||
1295 | { "PPROPT_DT", 0x02, 0x02 }, | ||
1296 | { "PPROPT_QAS", 0x04, 0x04 }, | ||
1297 | { "PPROPT_PACE", 0x08, 0x08 } | ||
1298 | }; | ||
1299 | |||
1300 | int | ||
1301 | ahd_negppropts_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1302 | { | ||
1303 | return (ahd_print_register(NEGPPROPTS_parse_table, 4, "NEGPPROPTS", | ||
1304 | 0x63, regvalue, cur_col, wrap)); | ||
1305 | } | ||
1306 | |||
1307 | static const ahd_reg_parse_entry_t NEGCONOPTS_parse_table[] = { | ||
1308 | { "WIDEXFER", 0x01, 0x01 }, | ||
1309 | { "ENAUTOATNO", 0x02, 0x02 }, | ||
1310 | { "ENAUTOATNI", 0x04, 0x04 }, | ||
1311 | { "ENSLOWCRC", 0x08, 0x08 }, | ||
1312 | { "RTI_OVRDTRN", 0x10, 0x10 }, | ||
1313 | { "RTI_WRTDIS", 0x20, 0x20 }, | ||
1314 | { "ENSNAPSHOT", 0x40, 0x40 } | ||
1315 | }; | ||
1316 | |||
1317 | int | ||
1318 | ahd_negconopts_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1319 | { | ||
1320 | return (ahd_print_register(NEGCONOPTS_parse_table, 7, "NEGCONOPTS", | ||
1321 | 0x64, regvalue, cur_col, wrap)); | ||
1322 | } | ||
1323 | |||
1324 | int | ||
1325 | ahd_annexcol_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1326 | { | ||
1327 | return (ahd_print_register(NULL, 0, "ANNEXCOL", | ||
1328 | 0x65, regvalue, cur_col, wrap)); | ||
1329 | } | ||
1330 | |||
1331 | int | ||
1332 | ahd_annexdat_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1333 | { | ||
1334 | return (ahd_print_register(NULL, 0, "ANNEXDAT", | ||
1335 | 0x66, regvalue, cur_col, wrap)); | ||
1336 | } | ||
1337 | |||
1338 | static const ahd_reg_parse_entry_t SCSCHKN_parse_table[] = { | ||
1339 | { "LSTSGCLRDIS", 0x01, 0x01 }, | ||
1340 | { "SHVALIDSTDIS", 0x02, 0x02 }, | ||
1341 | { "DFFACTCLR", 0x04, 0x04 }, | ||
1342 | { "SDONEMSKDIS", 0x08, 0x08 }, | ||
1343 | { "WIDERESEN", 0x10, 0x10 }, | ||
1344 | { "CURRFIFODEF", 0x20, 0x20 }, | ||
1345 | { "STSELSKIDDIS", 0x40, 0x40 }, | ||
1346 | { "BIDICHKDIS", 0x80, 0x80 } | ||
1347 | }; | ||
1348 | |||
1349 | int | ||
1350 | ahd_scschkn_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1351 | { | ||
1352 | return (ahd_print_register(SCSCHKN_parse_table, 8, "SCSCHKN", | ||
1353 | 0x66, regvalue, cur_col, wrap)); | ||
1354 | } | ||
1355 | |||
1356 | int | ||
1357 | ahd_iownid_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1358 | { | ||
1359 | return (ahd_print_register(NULL, 0, "IOWNID", | ||
1360 | 0x67, regvalue, cur_col, wrap)); | ||
1361 | } | ||
1362 | |||
1363 | int | ||
1364 | ahd_shcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1365 | { | ||
1366 | return (ahd_print_register(NULL, 0, "SHCNT", | ||
1367 | 0x68, regvalue, cur_col, wrap)); | ||
1368 | } | ||
1369 | |||
1370 | int | ||
1371 | ahd_townid_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1372 | { | ||
1373 | return (ahd_print_register(NULL, 0, "TOWNID", | ||
1374 | 0x69, regvalue, cur_col, wrap)); | ||
1375 | } | ||
1376 | |||
1377 | int | ||
1378 | ahd_seloid_print(u_int regvalue, u_int *cur_col, u_int wrap) | 527 | ahd_seloid_print(u_int regvalue, u_int *cur_col, u_int wrap) |
1379 | { | 528 | { |
1380 | return (ahd_print_register(NULL, 0, "SELOID", | 529 | return (ahd_print_register(NULL, 0, "SELOID", |
1381 | 0x6b, regvalue, cur_col, wrap)); | 530 | 0x6b, regvalue, cur_col, wrap)); |
1382 | } | 531 | } |
1383 | 532 | ||
1384 | int | ||
1385 | ahd_haddr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1386 | { | ||
1387 | return (ahd_print_register(NULL, 0, "HADDR", | ||
1388 | 0x70, regvalue, cur_col, wrap)); | ||
1389 | } | ||
1390 | |||
1391 | int | ||
1392 | ahd_hcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1393 | { | ||
1394 | return (ahd_print_register(NULL, 0, "HCNT", | ||
1395 | 0x78, regvalue, cur_col, wrap)); | ||
1396 | } | ||
1397 | |||
1398 | int | ||
1399 | ahd_sghaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1400 | { | ||
1401 | return (ahd_print_register(NULL, 0, "SGHADDR", | ||
1402 | 0x7c, regvalue, cur_col, wrap)); | ||
1403 | } | ||
1404 | |||
1405 | int | ||
1406 | ahd_scbhaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1407 | { | ||
1408 | return (ahd_print_register(NULL, 0, "SCBHADDR", | ||
1409 | 0x7c, regvalue, cur_col, wrap)); | ||
1410 | } | ||
1411 | |||
1412 | int | ||
1413 | ahd_sghcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1414 | { | ||
1415 | return (ahd_print_register(NULL, 0, "SGHCNT", | ||
1416 | 0x84, regvalue, cur_col, wrap)); | ||
1417 | } | ||
1418 | |||
1419 | int | ||
1420 | ahd_scbhcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1421 | { | ||
1422 | return (ahd_print_register(NULL, 0, "SCBHCNT", | ||
1423 | 0x84, regvalue, cur_col, wrap)); | ||
1424 | } | ||
1425 | |||
1426 | static const ahd_reg_parse_entry_t DFF_THRSH_parse_table[] = { | ||
1427 | { "WR_DFTHRSH_MIN", 0x00, 0x70 }, | ||
1428 | { "RD_DFTHRSH_MIN", 0x00, 0x07 }, | ||
1429 | { "RD_DFTHRSH_25", 0x01, 0x07 }, | ||
1430 | { "RD_DFTHRSH_50", 0x02, 0x07 }, | ||
1431 | { "RD_DFTHRSH_63", 0x03, 0x07 }, | ||
1432 | { "RD_DFTHRSH_75", 0x04, 0x07 }, | ||
1433 | { "RD_DFTHRSH_85", 0x05, 0x07 }, | ||
1434 | { "RD_DFTHRSH_90", 0x06, 0x07 }, | ||
1435 | { "RD_DFTHRSH_MAX", 0x07, 0x07 }, | ||
1436 | { "WR_DFTHRSH_25", 0x10, 0x70 }, | ||
1437 | { "WR_DFTHRSH_50", 0x20, 0x70 }, | ||
1438 | { "WR_DFTHRSH_63", 0x30, 0x70 }, | ||
1439 | { "WR_DFTHRSH_75", 0x40, 0x70 }, | ||
1440 | { "WR_DFTHRSH_85", 0x50, 0x70 }, | ||
1441 | { "WR_DFTHRSH_90", 0x60, 0x70 }, | ||
1442 | { "WR_DFTHRSH_MAX", 0x70, 0x70 }, | ||
1443 | { "RD_DFTHRSH", 0x07, 0x07 }, | ||
1444 | { "WR_DFTHRSH", 0x70, 0x70 } | ||
1445 | }; | ||
1446 | |||
1447 | int | ||
1448 | ahd_dff_thrsh_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1449 | { | ||
1450 | return (ahd_print_register(DFF_THRSH_parse_table, 18, "DFF_THRSH", | ||
1451 | 0x88, regvalue, cur_col, wrap)); | ||
1452 | } | ||
1453 | |||
1454 | static const ahd_reg_parse_entry_t PCIXCTL_parse_table[] = { | ||
1455 | { "CMPABCDIS", 0x01, 0x01 }, | ||
1456 | { "TSCSERREN", 0x02, 0x02 }, | ||
1457 | { "SRSPDPEEN", 0x04, 0x04 }, | ||
1458 | { "SPLTSTADIS", 0x08, 0x08 }, | ||
1459 | { "SPLTSMADIS", 0x10, 0x10 }, | ||
1460 | { "UNEXPSCIEN", 0x20, 0x20 }, | ||
1461 | { "SERRPULSE", 0x80, 0x80 } | ||
1462 | }; | ||
1463 | |||
1464 | int | ||
1465 | ahd_pcixctl_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1466 | { | ||
1467 | return (ahd_print_register(PCIXCTL_parse_table, 7, "PCIXCTL", | ||
1468 | 0x93, regvalue, cur_col, wrap)); | ||
1469 | } | ||
1470 | |||
1471 | static const ahd_reg_parse_entry_t DCHSPLTSTAT0_parse_table[] = { | ||
1472 | { "RXSPLTRSP", 0x01, 0x01 }, | ||
1473 | { "RXSCEMSG", 0x02, 0x02 }, | ||
1474 | { "RXOVRUN", 0x04, 0x04 }, | ||
1475 | { "CNTNOTCMPLT", 0x08, 0x08 }, | ||
1476 | { "SCDATBUCKET", 0x10, 0x10 }, | ||
1477 | { "SCADERR", 0x20, 0x20 }, | ||
1478 | { "SCBCERR", 0x40, 0x40 }, | ||
1479 | { "STAETERM", 0x80, 0x80 } | ||
1480 | }; | ||
1481 | |||
1482 | int | ||
1483 | ahd_dchspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1484 | { | ||
1485 | return (ahd_print_register(DCHSPLTSTAT0_parse_table, 8, "DCHSPLTSTAT0", | ||
1486 | 0x96, regvalue, cur_col, wrap)); | ||
1487 | } | ||
1488 | |||
1489 | static const ahd_reg_parse_entry_t DCHSPLTSTAT1_parse_table[] = { | ||
1490 | { "RXDATABUCKET", 0x01, 0x01 } | ||
1491 | }; | ||
1492 | |||
1493 | int | ||
1494 | ahd_dchspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1495 | { | ||
1496 | return (ahd_print_register(DCHSPLTSTAT1_parse_table, 1, "DCHSPLTSTAT1", | ||
1497 | 0x97, regvalue, cur_col, wrap)); | ||
1498 | } | ||
1499 | |||
1500 | static const ahd_reg_parse_entry_t SGSPLTSTAT0_parse_table[] = { | ||
1501 | { "RXSPLTRSP", 0x01, 0x01 }, | ||
1502 | { "RXSCEMSG", 0x02, 0x02 }, | ||
1503 | { "RXOVRUN", 0x04, 0x04 }, | ||
1504 | { "CNTNOTCMPLT", 0x08, 0x08 }, | ||
1505 | { "SCDATBUCKET", 0x10, 0x10 }, | ||
1506 | { "SCADERR", 0x20, 0x20 }, | ||
1507 | { "SCBCERR", 0x40, 0x40 }, | ||
1508 | { "STAETERM", 0x80, 0x80 } | ||
1509 | }; | ||
1510 | |||
1511 | int | ||
1512 | ahd_sgspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1513 | { | ||
1514 | return (ahd_print_register(SGSPLTSTAT0_parse_table, 8, "SGSPLTSTAT0", | ||
1515 | 0x9e, regvalue, cur_col, wrap)); | ||
1516 | } | ||
1517 | |||
1518 | static const ahd_reg_parse_entry_t SGSPLTSTAT1_parse_table[] = { | ||
1519 | { "RXDATABUCKET", 0x01, 0x01 } | ||
1520 | }; | ||
1521 | |||
1522 | int | ||
1523 | ahd_sgspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1524 | { | ||
1525 | return (ahd_print_register(SGSPLTSTAT1_parse_table, 1, "SGSPLTSTAT1", | ||
1526 | 0x9f, regvalue, cur_col, wrap)); | ||
1527 | } | ||
1528 | |||
1529 | static const ahd_reg_parse_entry_t DF0PCISTAT_parse_table[] = { | ||
1530 | { "DPR", 0x01, 0x01 }, | ||
1531 | { "TWATERR", 0x02, 0x02 }, | ||
1532 | { "RDPERR", 0x04, 0x04 }, | ||
1533 | { "SCAAPERR", 0x08, 0x08 }, | ||
1534 | { "RTA", 0x10, 0x10 }, | ||
1535 | { "RMA", 0x20, 0x20 }, | ||
1536 | { "SSE", 0x40, 0x40 }, | ||
1537 | { "DPE", 0x80, 0x80 } | ||
1538 | }; | ||
1539 | |||
1540 | int | ||
1541 | ahd_df0pcistat_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1542 | { | ||
1543 | return (ahd_print_register(DF0PCISTAT_parse_table, 8, "DF0PCISTAT", | ||
1544 | 0xa0, regvalue, cur_col, wrap)); | ||
1545 | } | ||
1546 | |||
1547 | int | ||
1548 | ahd_reg0_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1549 | { | ||
1550 | return (ahd_print_register(NULL, 0, "REG0", | ||
1551 | 0xa0, regvalue, cur_col, wrap)); | ||
1552 | } | ||
1553 | |||
1554 | int | ||
1555 | ahd_reg_isr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1556 | { | ||
1557 | return (ahd_print_register(NULL, 0, "REG_ISR", | ||
1558 | 0xa4, regvalue, cur_col, wrap)); | ||
1559 | } | ||
1560 | |||
1561 | static const ahd_reg_parse_entry_t SG_STATE_parse_table[] = { | 533 | static const ahd_reg_parse_entry_t SG_STATE_parse_table[] = { |
1562 | { "SEGS_AVAIL", 0x01, 0x01 }, | 534 | { "SEGS_AVAIL", 0x01, 0x01 }, |
1563 | { "LOADING_NEEDED", 0x02, 0x02 }, | 535 | { "LOADING_NEEDED", 0x02, 0x02 }, |
@@ -1571,54 +543,6 @@ ahd_sg_state_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
1571 | 0xa6, regvalue, cur_col, wrap)); | 543 | 0xa6, regvalue, cur_col, wrap)); |
1572 | } | 544 | } |
1573 | 545 | ||
1574 | static const ahd_reg_parse_entry_t TARGPCISTAT_parse_table[] = { | ||
1575 | { "TWATERR", 0x02, 0x02 }, | ||
1576 | { "STA", 0x08, 0x08 }, | ||
1577 | { "SSE", 0x40, 0x40 }, | ||
1578 | { "DPE", 0x80, 0x80 } | ||
1579 | }; | ||
1580 | |||
1581 | int | ||
1582 | ahd_targpcistat_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1583 | { | ||
1584 | return (ahd_print_register(TARGPCISTAT_parse_table, 4, "TARGPCISTAT", | ||
1585 | 0xa7, regvalue, cur_col, wrap)); | ||
1586 | } | ||
1587 | |||
1588 | int | ||
1589 | ahd_scbptr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1590 | { | ||
1591 | return (ahd_print_register(NULL, 0, "SCBPTR", | ||
1592 | 0xa8, regvalue, cur_col, wrap)); | ||
1593 | } | ||
1594 | |||
1595 | static const ahd_reg_parse_entry_t SCBAUTOPTR_parse_table[] = { | ||
1596 | { "SCBPTR_OFF", 0x07, 0x07 }, | ||
1597 | { "SCBPTR_ADDR", 0x38, 0x38 }, | ||
1598 | { "AUSCBPTR_EN", 0x80, 0x80 } | ||
1599 | }; | ||
1600 | |||
1601 | int | ||
1602 | ahd_scbautoptr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1603 | { | ||
1604 | return (ahd_print_register(SCBAUTOPTR_parse_table, 3, "SCBAUTOPTR", | ||
1605 | 0xab, regvalue, cur_col, wrap)); | ||
1606 | } | ||
1607 | |||
1608 | int | ||
1609 | ahd_ccsgaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1610 | { | ||
1611 | return (ahd_print_register(NULL, 0, "CCSGADDR", | ||
1612 | 0xac, regvalue, cur_col, wrap)); | ||
1613 | } | ||
1614 | |||
1615 | int | ||
1616 | ahd_ccscbaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1617 | { | ||
1618 | return (ahd_print_register(NULL, 0, "CCSCBADDR", | ||
1619 | 0xac, regvalue, cur_col, wrap)); | ||
1620 | } | ||
1621 | |||
1622 | static const ahd_reg_parse_entry_t CCSCBCTL_parse_table[] = { | 546 | static const ahd_reg_parse_entry_t CCSCBCTL_parse_table[] = { |
1623 | { "CCSCBRESET", 0x01, 0x01 }, | 547 | { "CCSCBRESET", 0x01, 0x01 }, |
1624 | { "CCSCBDIR", 0x04, 0x04 }, | 548 | { "CCSCBDIR", 0x04, 0x04 }, |
@@ -1651,138 +575,6 @@ ahd_ccsgctl_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
1651 | 0xad, regvalue, cur_col, wrap)); | 575 | 0xad, regvalue, cur_col, wrap)); |
1652 | } | 576 | } |
1653 | 577 | ||
1654 | int | ||
1655 | ahd_ccsgram_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1656 | { | ||
1657 | return (ahd_print_register(NULL, 0, "CCSGRAM", | ||
1658 | 0xb0, regvalue, cur_col, wrap)); | ||
1659 | } | ||
1660 | |||
1661 | int | ||
1662 | ahd_ccscbram_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1663 | { | ||
1664 | return (ahd_print_register(NULL, 0, "CCSCBRAM", | ||
1665 | 0xb0, regvalue, cur_col, wrap)); | ||
1666 | } | ||
1667 | |||
1668 | int | ||
1669 | ahd_brddat_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1670 | { | ||
1671 | return (ahd_print_register(NULL, 0, "BRDDAT", | ||
1672 | 0xb8, regvalue, cur_col, wrap)); | ||
1673 | } | ||
1674 | |||
1675 | static const ahd_reg_parse_entry_t BRDCTL_parse_table[] = { | ||
1676 | { "BRDSTB", 0x01, 0x01 }, | ||
1677 | { "BRDRW", 0x02, 0x02 }, | ||
1678 | { "BRDEN", 0x04, 0x04 }, | ||
1679 | { "BRDADDR", 0x38, 0x38 }, | ||
1680 | { "FLXARBREQ", 0x40, 0x40 }, | ||
1681 | { "FLXARBACK", 0x80, 0x80 } | ||
1682 | }; | ||
1683 | |||
1684 | int | ||
1685 | ahd_brdctl_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1686 | { | ||
1687 | return (ahd_print_register(BRDCTL_parse_table, 6, "BRDCTL", | ||
1688 | 0xb9, regvalue, cur_col, wrap)); | ||
1689 | } | ||
1690 | |||
1691 | int | ||
1692 | ahd_seeadr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1693 | { | ||
1694 | return (ahd_print_register(NULL, 0, "SEEADR", | ||
1695 | 0xba, regvalue, cur_col, wrap)); | ||
1696 | } | ||
1697 | |||
1698 | int | ||
1699 | ahd_seedat_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1700 | { | ||
1701 | return (ahd_print_register(NULL, 0, "SEEDAT", | ||
1702 | 0xbc, regvalue, cur_col, wrap)); | ||
1703 | } | ||
1704 | |||
1705 | static const ahd_reg_parse_entry_t SEECTL_parse_table[] = { | ||
1706 | { "SEEOP_ERAL", 0x40, 0x70 }, | ||
1707 | { "SEEOP_WRITE", 0x50, 0x70 }, | ||
1708 | { "SEEOP_READ", 0x60, 0x70 }, | ||
1709 | { "SEEOP_ERASE", 0x70, 0x70 }, | ||
1710 | { "SEESTART", 0x01, 0x01 }, | ||
1711 | { "SEERST", 0x02, 0x02 }, | ||
1712 | { "SEEOPCODE", 0x70, 0x70 }, | ||
1713 | { "SEEOP_EWEN", 0x40, 0x40 }, | ||
1714 | { "SEEOP_WALL", 0x40, 0x40 }, | ||
1715 | { "SEEOP_EWDS", 0x40, 0x40 } | ||
1716 | }; | ||
1717 | |||
1718 | int | ||
1719 | ahd_seectl_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1720 | { | ||
1721 | return (ahd_print_register(SEECTL_parse_table, 10, "SEECTL", | ||
1722 | 0xbe, regvalue, cur_col, wrap)); | ||
1723 | } | ||
1724 | |||
1725 | static const ahd_reg_parse_entry_t SEESTAT_parse_table[] = { | ||
1726 | { "SEESTART", 0x01, 0x01 }, | ||
1727 | { "SEEBUSY", 0x02, 0x02 }, | ||
1728 | { "SEEARBACK", 0x04, 0x04 }, | ||
1729 | { "LDALTID_L", 0x08, 0x08 }, | ||
1730 | { "SEEOPCODE", 0x70, 0x70 }, | ||
1731 | { "INIT_DONE", 0x80, 0x80 } | ||
1732 | }; | ||
1733 | |||
1734 | int | ||
1735 | ahd_seestat_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1736 | { | ||
1737 | return (ahd_print_register(SEESTAT_parse_table, 6, "SEESTAT", | ||
1738 | 0xbe, regvalue, cur_col, wrap)); | ||
1739 | } | ||
1740 | |||
1741 | static const ahd_reg_parse_entry_t DSPDATACTL_parse_table[] = { | ||
1742 | { "XMITOFFSTDIS", 0x02, 0x02 }, | ||
1743 | { "RCVROFFSTDIS", 0x04, 0x04 }, | ||
1744 | { "DESQDIS", 0x10, 0x10 }, | ||
1745 | { "BYPASSENAB", 0x80, 0x80 } | ||
1746 | }; | ||
1747 | |||
1748 | int | ||
1749 | ahd_dspdatactl_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1750 | { | ||
1751 | return (ahd_print_register(DSPDATACTL_parse_table, 4, "DSPDATACTL", | ||
1752 | 0xc1, regvalue, cur_col, wrap)); | ||
1753 | } | ||
1754 | |||
1755 | int | ||
1756 | ahd_dfdat_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1757 | { | ||
1758 | return (ahd_print_register(NULL, 0, "DFDAT", | ||
1759 | 0xc4, regvalue, cur_col, wrap)); | ||
1760 | } | ||
1761 | |||
1762 | static const ahd_reg_parse_entry_t DSPSELECT_parse_table[] = { | ||
1763 | { "DSPSEL", 0x1f, 0x1f }, | ||
1764 | { "AUTOINCEN", 0x80, 0x80 } | ||
1765 | }; | ||
1766 | |||
1767 | int | ||
1768 | ahd_dspselect_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1769 | { | ||
1770 | return (ahd_print_register(DSPSELECT_parse_table, 2, "DSPSELECT", | ||
1771 | 0xc4, regvalue, cur_col, wrap)); | ||
1772 | } | ||
1773 | |||
1774 | static const ahd_reg_parse_entry_t WRTBIASCTL_parse_table[] = { | ||
1775 | { "XMITMANVAL", 0x3f, 0x3f }, | ||
1776 | { "AUTOXBCDIS", 0x80, 0x80 } | ||
1777 | }; | ||
1778 | |||
1779 | int | ||
1780 | ahd_wrtbiasctl_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1781 | { | ||
1782 | return (ahd_print_register(WRTBIASCTL_parse_table, 2, "WRTBIASCTL", | ||
1783 | 0xc5, regvalue, cur_col, wrap)); | ||
1784 | } | ||
1785 | |||
1786 | static const ahd_reg_parse_entry_t SEQCTL0_parse_table[] = { | 578 | static const ahd_reg_parse_entry_t SEQCTL0_parse_table[] = { |
1787 | { "LOADRAM", 0x01, 0x01 }, | 579 | { "LOADRAM", 0x01, 0x01 }, |
1788 | { "SEQRESET", 0x02, 0x02 }, | 580 | { "SEQRESET", 0x02, 0x02 }, |
@@ -1801,18 +593,6 @@ ahd_seqctl0_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
1801 | 0xd6, regvalue, cur_col, wrap)); | 593 | 0xd6, regvalue, cur_col, wrap)); |
1802 | } | 594 | } |
1803 | 595 | ||
1804 | static const ahd_reg_parse_entry_t FLAGS_parse_table[] = { | ||
1805 | { "CARRY", 0x01, 0x01 }, | ||
1806 | { "ZERO", 0x02, 0x02 } | ||
1807 | }; | ||
1808 | |||
1809 | int | ||
1810 | ahd_flags_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1811 | { | ||
1812 | return (ahd_print_register(FLAGS_parse_table, 2, "FLAGS", | ||
1813 | 0xd8, regvalue, cur_col, wrap)); | ||
1814 | } | ||
1815 | |||
1816 | static const ahd_reg_parse_entry_t SEQINTCTL_parse_table[] = { | 596 | static const ahd_reg_parse_entry_t SEQINTCTL_parse_table[] = { |
1817 | { "IRET", 0x01, 0x01 }, | 597 | { "IRET", 0x01, 0x01 }, |
1818 | { "INTMASK1", 0x02, 0x02 }, | 598 | { "INTMASK1", 0x02, 0x02 }, |
@@ -1831,118 +611,6 @@ ahd_seqintctl_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
1831 | } | 611 | } |
1832 | 612 | ||
1833 | int | 613 | int |
1834 | ahd_seqram_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1835 | { | ||
1836 | return (ahd_print_register(NULL, 0, "SEQRAM", | ||
1837 | 0xda, regvalue, cur_col, wrap)); | ||
1838 | } | ||
1839 | |||
1840 | int | ||
1841 | ahd_prgmcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1842 | { | ||
1843 | return (ahd_print_register(NULL, 0, "PRGMCNT", | ||
1844 | 0xde, regvalue, cur_col, wrap)); | ||
1845 | } | ||
1846 | |||
1847 | int | ||
1848 | ahd_accum_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1849 | { | ||
1850 | return (ahd_print_register(NULL, 0, "ACCUM", | ||
1851 | 0xe0, regvalue, cur_col, wrap)); | ||
1852 | } | ||
1853 | |||
1854 | int | ||
1855 | ahd_sindex_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1856 | { | ||
1857 | return (ahd_print_register(NULL, 0, "SINDEX", | ||
1858 | 0xe2, regvalue, cur_col, wrap)); | ||
1859 | } | ||
1860 | |||
1861 | int | ||
1862 | ahd_dindex_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1863 | { | ||
1864 | return (ahd_print_register(NULL, 0, "DINDEX", | ||
1865 | 0xe4, regvalue, cur_col, wrap)); | ||
1866 | } | ||
1867 | |||
1868 | int | ||
1869 | ahd_allones_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1870 | { | ||
1871 | return (ahd_print_register(NULL, 0, "ALLONES", | ||
1872 | 0xe8, regvalue, cur_col, wrap)); | ||
1873 | } | ||
1874 | |||
1875 | int | ||
1876 | ahd_allzeros_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1877 | { | ||
1878 | return (ahd_print_register(NULL, 0, "ALLZEROS", | ||
1879 | 0xea, regvalue, cur_col, wrap)); | ||
1880 | } | ||
1881 | |||
1882 | int | ||
1883 | ahd_none_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1884 | { | ||
1885 | return (ahd_print_register(NULL, 0, "NONE", | ||
1886 | 0xea, regvalue, cur_col, wrap)); | ||
1887 | } | ||
1888 | |||
1889 | int | ||
1890 | ahd_sindir_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1891 | { | ||
1892 | return (ahd_print_register(NULL, 0, "SINDIR", | ||
1893 | 0xec, regvalue, cur_col, wrap)); | ||
1894 | } | ||
1895 | |||
1896 | int | ||
1897 | ahd_dindir_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1898 | { | ||
1899 | return (ahd_print_register(NULL, 0, "DINDIR", | ||
1900 | 0xed, regvalue, cur_col, wrap)); | ||
1901 | } | ||
1902 | |||
1903 | int | ||
1904 | ahd_stack_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1905 | { | ||
1906 | return (ahd_print_register(NULL, 0, "STACK", | ||
1907 | 0xf2, regvalue, cur_col, wrap)); | ||
1908 | } | ||
1909 | |||
1910 | int | ||
1911 | ahd_intvec1_addr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1912 | { | ||
1913 | return (ahd_print_register(NULL, 0, "INTVEC1_ADDR", | ||
1914 | 0xf4, regvalue, cur_col, wrap)); | ||
1915 | } | ||
1916 | |||
1917 | int | ||
1918 | ahd_curaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1919 | { | ||
1920 | return (ahd_print_register(NULL, 0, "CURADDR", | ||
1921 | 0xf4, regvalue, cur_col, wrap)); | ||
1922 | } | ||
1923 | |||
1924 | int | ||
1925 | ahd_intvec2_addr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1926 | { | ||
1927 | return (ahd_print_register(NULL, 0, "INTVEC2_ADDR", | ||
1928 | 0xf6, regvalue, cur_col, wrap)); | ||
1929 | } | ||
1930 | |||
1931 | int | ||
1932 | ahd_longjmp_addr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1933 | { | ||
1934 | return (ahd_print_register(NULL, 0, "LONGJMP_ADDR", | ||
1935 | 0xf8, regvalue, cur_col, wrap)); | ||
1936 | } | ||
1937 | |||
1938 | int | ||
1939 | ahd_accum_save_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1940 | { | ||
1941 | return (ahd_print_register(NULL, 0, "ACCUM_SAVE", | ||
1942 | 0xfa, regvalue, cur_col, wrap)); | ||
1943 | } | ||
1944 | |||
1945 | int | ||
1946 | ahd_sram_base_print(u_int regvalue, u_int *cur_col, u_int wrap) | 614 | ahd_sram_base_print(u_int regvalue, u_int *cur_col, u_int wrap) |
1947 | { | 615 | { |
1948 | return (ahd_print_register(NULL, 0, "SRAM_BASE", | 616 | return (ahd_print_register(NULL, 0, "SRAM_BASE", |
@@ -1950,69 +618,6 @@ ahd_sram_base_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
1950 | } | 618 | } |
1951 | 619 | ||
1952 | int | 620 | int |
1953 | ahd_waiting_scb_tails_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1954 | { | ||
1955 | return (ahd_print_register(NULL, 0, "WAITING_SCB_TAILS", | ||
1956 | 0x100, regvalue, cur_col, wrap)); | ||
1957 | } | ||
1958 | |||
1959 | int | ||
1960 | ahd_waiting_tid_head_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1961 | { | ||
1962 | return (ahd_print_register(NULL, 0, "WAITING_TID_HEAD", | ||
1963 | 0x120, regvalue, cur_col, wrap)); | ||
1964 | } | ||
1965 | |||
1966 | int | ||
1967 | ahd_waiting_tid_tail_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1968 | { | ||
1969 | return (ahd_print_register(NULL, 0, "WAITING_TID_TAIL", | ||
1970 | 0x122, regvalue, cur_col, wrap)); | ||
1971 | } | ||
1972 | |||
1973 | int | ||
1974 | ahd_next_queued_scb_addr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1975 | { | ||
1976 | return (ahd_print_register(NULL, 0, "NEXT_QUEUED_SCB_ADDR", | ||
1977 | 0x124, regvalue, cur_col, wrap)); | ||
1978 | } | ||
1979 | |||
1980 | int | ||
1981 | ahd_complete_scb_head_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1982 | { | ||
1983 | return (ahd_print_register(NULL, 0, "COMPLETE_SCB_HEAD", | ||
1984 | 0x128, regvalue, cur_col, wrap)); | ||
1985 | } | ||
1986 | |||
1987 | int | ||
1988 | ahd_complete_scb_dmainprog_head_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1989 | { | ||
1990 | return (ahd_print_register(NULL, 0, "COMPLETE_SCB_DMAINPROG_HEAD", | ||
1991 | 0x12a, regvalue, cur_col, wrap)); | ||
1992 | } | ||
1993 | |||
1994 | int | ||
1995 | ahd_complete_dma_scb_head_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1996 | { | ||
1997 | return (ahd_print_register(NULL, 0, "COMPLETE_DMA_SCB_HEAD", | ||
1998 | 0x12c, regvalue, cur_col, wrap)); | ||
1999 | } | ||
2000 | |||
2001 | int | ||
2002 | ahd_complete_dma_scb_tail_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2003 | { | ||
2004 | return (ahd_print_register(NULL, 0, "COMPLETE_DMA_SCB_TAIL", | ||
2005 | 0x12e, regvalue, cur_col, wrap)); | ||
2006 | } | ||
2007 | |||
2008 | int | ||
2009 | ahd_complete_on_qfreeze_head_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2010 | { | ||
2011 | return (ahd_print_register(NULL, 0, "COMPLETE_ON_QFREEZE_HEAD", | ||
2012 | 0x130, regvalue, cur_col, wrap)); | ||
2013 | } | ||
2014 | |||
2015 | int | ||
2016 | ahd_qfreeze_count_print(u_int regvalue, u_int *cur_col, u_int wrap) | 621 | ahd_qfreeze_count_print(u_int regvalue, u_int *cur_col, u_int wrap) |
2017 | { | 622 | { |
2018 | return (ahd_print_register(NULL, 0, "QFREEZE_COUNT", | 623 | return (ahd_print_register(NULL, 0, "QFREEZE_COUNT", |
@@ -2033,33 +638,6 @@ ahd_saved_mode_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
2033 | 0x136, regvalue, cur_col, wrap)); | 638 | 0x136, regvalue, cur_col, wrap)); |
2034 | } | 639 | } |
2035 | 640 | ||
2036 | int | ||
2037 | ahd_msg_out_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2038 | { | ||
2039 | return (ahd_print_register(NULL, 0, "MSG_OUT", | ||
2040 | 0x137, regvalue, cur_col, wrap)); | ||
2041 | } | ||
2042 | |||
2043 | static const ahd_reg_parse_entry_t DMAPARAMS_parse_table[] = { | ||
2044 | { "FIFORESET", 0x01, 0x01 }, | ||
2045 | { "FIFOFLUSH", 0x02, 0x02 }, | ||
2046 | { "DIRECTION", 0x04, 0x04 }, | ||
2047 | { "HDMAEN", 0x08, 0x08 }, | ||
2048 | { "HDMAENACK", 0x08, 0x08 }, | ||
2049 | { "SDMAEN", 0x10, 0x10 }, | ||
2050 | { "SDMAENACK", 0x10, 0x10 }, | ||
2051 | { "SCSIEN", 0x20, 0x20 }, | ||
2052 | { "WIDEODD", 0x40, 0x40 }, | ||
2053 | { "PRELOADEN", 0x80, 0x80 } | ||
2054 | }; | ||
2055 | |||
2056 | int | ||
2057 | ahd_dmaparams_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2058 | { | ||
2059 | return (ahd_print_register(DMAPARAMS_parse_table, 10, "DMAPARAMS", | ||
2060 | 0x138, regvalue, cur_col, wrap)); | ||
2061 | } | ||
2062 | |||
2063 | static const ahd_reg_parse_entry_t SEQ_FLAGS_parse_table[] = { | 641 | static const ahd_reg_parse_entry_t SEQ_FLAGS_parse_table[] = { |
2064 | { "NO_DISCONNECT", 0x01, 0x01 }, | 642 | { "NO_DISCONNECT", 0x01, 0x01 }, |
2065 | { "SPHASE_PENDING", 0x02, 0x02 }, | 643 | { "SPHASE_PENDING", 0x02, 0x02 }, |
@@ -2079,20 +657,6 @@ ahd_seq_flags_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
2079 | 0x139, regvalue, cur_col, wrap)); | 657 | 0x139, regvalue, cur_col, wrap)); |
2080 | } | 658 | } |
2081 | 659 | ||
2082 | int | ||
2083 | ahd_saved_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2084 | { | ||
2085 | return (ahd_print_register(NULL, 0, "SAVED_SCSIID", | ||
2086 | 0x13a, regvalue, cur_col, wrap)); | ||
2087 | } | ||
2088 | |||
2089 | int | ||
2090 | ahd_saved_lun_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2091 | { | ||
2092 | return (ahd_print_register(NULL, 0, "SAVED_LUN", | ||
2093 | 0x13b, regvalue, cur_col, wrap)); | ||
2094 | } | ||
2095 | |||
2096 | static const ahd_reg_parse_entry_t LASTPHASE_parse_table[] = { | 660 | static const ahd_reg_parse_entry_t LASTPHASE_parse_table[] = { |
2097 | { "P_DATAOUT", 0x00, 0xe0 }, | 661 | { "P_DATAOUT", 0x00, 0xe0 }, |
2098 | { "P_DATAOUT_DT", 0x20, 0xe0 }, | 662 | { "P_DATAOUT_DT", 0x20, 0xe0 }, |
@@ -2116,96 +680,6 @@ ahd_lastphase_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
2116 | 0x13c, regvalue, cur_col, wrap)); | 680 | 0x13c, regvalue, cur_col, wrap)); |
2117 | } | 681 | } |
2118 | 682 | ||
2119 | int | ||
2120 | ahd_qoutfifo_entry_valid_tag_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2121 | { | ||
2122 | return (ahd_print_register(NULL, 0, "QOUTFIFO_ENTRY_VALID_TAG", | ||
2123 | 0x13d, regvalue, cur_col, wrap)); | ||
2124 | } | ||
2125 | |||
2126 | int | ||
2127 | ahd_kernel_tqinpos_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2128 | { | ||
2129 | return (ahd_print_register(NULL, 0, "KERNEL_TQINPOS", | ||
2130 | 0x13e, regvalue, cur_col, wrap)); | ||
2131 | } | ||
2132 | |||
2133 | int | ||
2134 | ahd_tqinpos_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2135 | { | ||
2136 | return (ahd_print_register(NULL, 0, "TQINPOS", | ||
2137 | 0x13f, regvalue, cur_col, wrap)); | ||
2138 | } | ||
2139 | |||
2140 | int | ||
2141 | ahd_shared_data_addr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2142 | { | ||
2143 | return (ahd_print_register(NULL, 0, "SHARED_DATA_ADDR", | ||
2144 | 0x140, regvalue, cur_col, wrap)); | ||
2145 | } | ||
2146 | |||
2147 | int | ||
2148 | ahd_qoutfifo_next_addr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2149 | { | ||
2150 | return (ahd_print_register(NULL, 0, "QOUTFIFO_NEXT_ADDR", | ||
2151 | 0x144, regvalue, cur_col, wrap)); | ||
2152 | } | ||
2153 | |||
2154 | static const ahd_reg_parse_entry_t ARG_1_parse_table[] = { | ||
2155 | { "CONT_MSG_LOOP_TARG", 0x02, 0x02 }, | ||
2156 | { "CONT_MSG_LOOP_READ", 0x03, 0x03 }, | ||
2157 | { "CONT_MSG_LOOP_WRITE",0x04, 0x04 }, | ||
2158 | { "EXIT_MSG_LOOP", 0x08, 0x08 }, | ||
2159 | { "MSGOUT_PHASEMIS", 0x10, 0x10 }, | ||
2160 | { "SEND_REJ", 0x20, 0x20 }, | ||
2161 | { "SEND_SENSE", 0x40, 0x40 }, | ||
2162 | { "SEND_MSG", 0x80, 0x80 } | ||
2163 | }; | ||
2164 | |||
2165 | int | ||
2166 | ahd_arg_1_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2167 | { | ||
2168 | return (ahd_print_register(ARG_1_parse_table, 8, "ARG_1", | ||
2169 | 0x148, regvalue, cur_col, wrap)); | ||
2170 | } | ||
2171 | |||
2172 | int | ||
2173 | ahd_arg_2_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2174 | { | ||
2175 | return (ahd_print_register(NULL, 0, "ARG_2", | ||
2176 | 0x149, regvalue, cur_col, wrap)); | ||
2177 | } | ||
2178 | |||
2179 | int | ||
2180 | ahd_last_msg_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2181 | { | ||
2182 | return (ahd_print_register(NULL, 0, "LAST_MSG", | ||
2183 | 0x14a, regvalue, cur_col, wrap)); | ||
2184 | } | ||
2185 | |||
2186 | static const ahd_reg_parse_entry_t SCSISEQ_TEMPLATE_parse_table[] = { | ||
2187 | { "ALTSTIM", 0x01, 0x01 }, | ||
2188 | { "ENAUTOATNP", 0x02, 0x02 }, | ||
2189 | { "MANUALP", 0x0c, 0x0c }, | ||
2190 | { "ENRSELI", 0x10, 0x10 }, | ||
2191 | { "ENSELI", 0x20, 0x20 }, | ||
2192 | { "MANUALCTL", 0x40, 0x40 } | ||
2193 | }; | ||
2194 | |||
2195 | int | ||
2196 | ahd_scsiseq_template_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2197 | { | ||
2198 | return (ahd_print_register(SCSISEQ_TEMPLATE_parse_table, 6, "SCSISEQ_TEMPLATE", | ||
2199 | 0x14b, regvalue, cur_col, wrap)); | ||
2200 | } | ||
2201 | |||
2202 | int | ||
2203 | ahd_initiator_tag_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2204 | { | ||
2205 | return (ahd_print_register(NULL, 0, "INITIATOR_TAG", | ||
2206 | 0x14c, regvalue, cur_col, wrap)); | ||
2207 | } | ||
2208 | |||
2209 | static const ahd_reg_parse_entry_t SEQ_FLAGS2_parse_table[] = { | 683 | static const ahd_reg_parse_entry_t SEQ_FLAGS2_parse_table[] = { |
2210 | { "PENDING_MK_MESSAGE", 0x01, 0x01 }, | 684 | { "PENDING_MK_MESSAGE", 0x01, 0x01 }, |
2211 | { "TARGET_MSG_PENDING", 0x02, 0x02 }, | 685 | { "TARGET_MSG_PENDING", 0x02, 0x02 }, |
@@ -2220,62 +694,6 @@ ahd_seq_flags2_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
2220 | } | 694 | } |
2221 | 695 | ||
2222 | int | 696 | int |
2223 | ahd_allocfifo_scbptr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2224 | { | ||
2225 | return (ahd_print_register(NULL, 0, "ALLOCFIFO_SCBPTR", | ||
2226 | 0x14e, regvalue, cur_col, wrap)); | ||
2227 | } | ||
2228 | |||
2229 | int | ||
2230 | ahd_int_coalescing_timer_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2231 | { | ||
2232 | return (ahd_print_register(NULL, 0, "INT_COALESCING_TIMER", | ||
2233 | 0x150, regvalue, cur_col, wrap)); | ||
2234 | } | ||
2235 | |||
2236 | int | ||
2237 | ahd_int_coalescing_maxcmds_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2238 | { | ||
2239 | return (ahd_print_register(NULL, 0, "INT_COALESCING_MAXCMDS", | ||
2240 | 0x152, regvalue, cur_col, wrap)); | ||
2241 | } | ||
2242 | |||
2243 | int | ||
2244 | ahd_int_coalescing_mincmds_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2245 | { | ||
2246 | return (ahd_print_register(NULL, 0, "INT_COALESCING_MINCMDS", | ||
2247 | 0x153, regvalue, cur_col, wrap)); | ||
2248 | } | ||
2249 | |||
2250 | int | ||
2251 | ahd_cmds_pending_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2252 | { | ||
2253 | return (ahd_print_register(NULL, 0, "CMDS_PENDING", | ||
2254 | 0x154, regvalue, cur_col, wrap)); | ||
2255 | } | ||
2256 | |||
2257 | int | ||
2258 | ahd_int_coalescing_cmdcount_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2259 | { | ||
2260 | return (ahd_print_register(NULL, 0, "INT_COALESCING_CMDCOUNT", | ||
2261 | 0x156, regvalue, cur_col, wrap)); | ||
2262 | } | ||
2263 | |||
2264 | int | ||
2265 | ahd_local_hs_mailbox_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2266 | { | ||
2267 | return (ahd_print_register(NULL, 0, "LOCAL_HS_MAILBOX", | ||
2268 | 0x157, regvalue, cur_col, wrap)); | ||
2269 | } | ||
2270 | |||
2271 | int | ||
2272 | ahd_cmdsize_table_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2273 | { | ||
2274 | return (ahd_print_register(NULL, 0, "CMDSIZE_TABLE", | ||
2275 | 0x158, regvalue, cur_col, wrap)); | ||
2276 | } | ||
2277 | |||
2278 | int | ||
2279 | ahd_mk_message_scb_print(u_int regvalue, u_int *cur_col, u_int wrap) | 697 | ahd_mk_message_scb_print(u_int regvalue, u_int *cur_col, u_int wrap) |
2280 | { | 698 | { |
2281 | return (ahd_print_register(NULL, 0, "MK_MESSAGE_SCB", | 699 | return (ahd_print_register(NULL, 0, "MK_MESSAGE_SCB", |
@@ -2290,53 +708,12 @@ ahd_mk_message_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
2290 | } | 708 | } |
2291 | 709 | ||
2292 | int | 710 | int |
2293 | ahd_scb_residual_datacnt_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2294 | { | ||
2295 | return (ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT", | ||
2296 | 0x180, regvalue, cur_col, wrap)); | ||
2297 | } | ||
2298 | |||
2299 | int | ||
2300 | ahd_scb_base_print(u_int regvalue, u_int *cur_col, u_int wrap) | 711 | ahd_scb_base_print(u_int regvalue, u_int *cur_col, u_int wrap) |
2301 | { | 712 | { |
2302 | return (ahd_print_register(NULL, 0, "SCB_BASE", | 713 | return (ahd_print_register(NULL, 0, "SCB_BASE", |
2303 | 0x180, regvalue, cur_col, wrap)); | 714 | 0x180, regvalue, cur_col, wrap)); |
2304 | } | 715 | } |
2305 | 716 | ||
2306 | static const ahd_reg_parse_entry_t SCB_RESIDUAL_SGPTR_parse_table[] = { | ||
2307 | { "SG_LIST_NULL", 0x01, 0x01 }, | ||
2308 | { "SG_OVERRUN_RESID", 0x02, 0x02 }, | ||
2309 | { "SG_ADDR_MASK", 0xf8, 0xf8 } | ||
2310 | }; | ||
2311 | |||
2312 | int | ||
2313 | ahd_scb_residual_sgptr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2314 | { | ||
2315 | return (ahd_print_register(SCB_RESIDUAL_SGPTR_parse_table, 3, "SCB_RESIDUAL_SGPTR", | ||
2316 | 0x184, regvalue, cur_col, wrap)); | ||
2317 | } | ||
2318 | |||
2319 | int | ||
2320 | ahd_scb_scsi_status_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2321 | { | ||
2322 | return (ahd_print_register(NULL, 0, "SCB_SCSI_STATUS", | ||
2323 | 0x188, regvalue, cur_col, wrap)); | ||
2324 | } | ||
2325 | |||
2326 | int | ||
2327 | ahd_scb_sense_busaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2328 | { | ||
2329 | return (ahd_print_register(NULL, 0, "SCB_SENSE_BUSADDR", | ||
2330 | 0x18c, regvalue, cur_col, wrap)); | ||
2331 | } | ||
2332 | |||
2333 | int | ||
2334 | ahd_scb_tag_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2335 | { | ||
2336 | return (ahd_print_register(NULL, 0, "SCB_TAG", | ||
2337 | 0x190, regvalue, cur_col, wrap)); | ||
2338 | } | ||
2339 | |||
2340 | static const ahd_reg_parse_entry_t SCB_CONTROL_parse_table[] = { | 717 | static const ahd_reg_parse_entry_t SCB_CONTROL_parse_table[] = { |
2341 | { "SCB_TAG_TYPE", 0x03, 0x03 }, | 718 | { "SCB_TAG_TYPE", 0x03, 0x03 }, |
2342 | { "DISCONNECTED", 0x04, 0x04 }, | 719 | { "DISCONNECTED", 0x04, 0x04 }, |
@@ -2366,103 +743,3 @@ ahd_scb_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
2366 | 0x193, regvalue, cur_col, wrap)); | 743 | 0x193, regvalue, cur_col, wrap)); |
2367 | } | 744 | } |
2368 | 745 | ||
2369 | static const ahd_reg_parse_entry_t SCB_LUN_parse_table[] = { | ||
2370 | { "LID", 0xff, 0xff } | ||
2371 | }; | ||
2372 | |||
2373 | int | ||
2374 | ahd_scb_lun_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2375 | { | ||
2376 | return (ahd_print_register(SCB_LUN_parse_table, 1, "SCB_LUN", | ||
2377 | 0x194, regvalue, cur_col, wrap)); | ||
2378 | } | ||
2379 | |||
2380 | static const ahd_reg_parse_entry_t SCB_TASK_ATTRIBUTE_parse_table[] = { | ||
2381 | { "SCB_XFERLEN_ODD", 0x01, 0x01 } | ||
2382 | }; | ||
2383 | |||
2384 | int | ||
2385 | ahd_scb_task_attribute_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2386 | { | ||
2387 | return (ahd_print_register(SCB_TASK_ATTRIBUTE_parse_table, 1, "SCB_TASK_ATTRIBUTE", | ||
2388 | 0x195, regvalue, cur_col, wrap)); | ||
2389 | } | ||
2390 | |||
2391 | static const ahd_reg_parse_entry_t SCB_CDB_LEN_parse_table[] = { | ||
2392 | { "SCB_CDB_LEN_PTR", 0x80, 0x80 } | ||
2393 | }; | ||
2394 | |||
2395 | int | ||
2396 | ahd_scb_cdb_len_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2397 | { | ||
2398 | return (ahd_print_register(SCB_CDB_LEN_parse_table, 1, "SCB_CDB_LEN", | ||
2399 | 0x196, regvalue, cur_col, wrap)); | ||
2400 | } | ||
2401 | |||
2402 | int | ||
2403 | ahd_scb_task_management_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2404 | { | ||
2405 | return (ahd_print_register(NULL, 0, "SCB_TASK_MANAGEMENT", | ||
2406 | 0x197, regvalue, cur_col, wrap)); | ||
2407 | } | ||
2408 | |||
2409 | int | ||
2410 | ahd_scb_dataptr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2411 | { | ||
2412 | return (ahd_print_register(NULL, 0, "SCB_DATAPTR", | ||
2413 | 0x198, regvalue, cur_col, wrap)); | ||
2414 | } | ||
2415 | |||
2416 | static const ahd_reg_parse_entry_t SCB_DATACNT_parse_table[] = { | ||
2417 | { "SG_HIGH_ADDR_BITS", 0x7f, 0x7f }, | ||
2418 | { "SG_LAST_SEG", 0x80, 0x80 } | ||
2419 | }; | ||
2420 | |||
2421 | int | ||
2422 | ahd_scb_datacnt_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2423 | { | ||
2424 | return (ahd_print_register(SCB_DATACNT_parse_table, 2, "SCB_DATACNT", | ||
2425 | 0x1a0, regvalue, cur_col, wrap)); | ||
2426 | } | ||
2427 | |||
2428 | static const ahd_reg_parse_entry_t SCB_SGPTR_parse_table[] = { | ||
2429 | { "SG_LIST_NULL", 0x01, 0x01 }, | ||
2430 | { "SG_FULL_RESID", 0x02, 0x02 }, | ||
2431 | { "SG_STATUS_VALID", 0x04, 0x04 } | ||
2432 | }; | ||
2433 | |||
2434 | int | ||
2435 | ahd_scb_sgptr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2436 | { | ||
2437 | return (ahd_print_register(SCB_SGPTR_parse_table, 3, "SCB_SGPTR", | ||
2438 | 0x1a4, regvalue, cur_col, wrap)); | ||
2439 | } | ||
2440 | |||
2441 | int | ||
2442 | ahd_scb_busaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2443 | { | ||
2444 | return (ahd_print_register(NULL, 0, "SCB_BUSADDR", | ||
2445 | 0x1a8, regvalue, cur_col, wrap)); | ||
2446 | } | ||
2447 | |||
2448 | int | ||
2449 | ahd_scb_next_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2450 | { | ||
2451 | return (ahd_print_register(NULL, 0, "SCB_NEXT", | ||
2452 | 0x1ac, regvalue, cur_col, wrap)); | ||
2453 | } | ||
2454 | |||
2455 | int | ||
2456 | ahd_scb_next2_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2457 | { | ||
2458 | return (ahd_print_register(NULL, 0, "SCB_NEXT2", | ||
2459 | 0x1ae, regvalue, cur_col, wrap)); | ||
2460 | } | ||
2461 | |||
2462 | int | ||
2463 | ahd_scb_disconnected_lists_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
2464 | { | ||
2465 | return (ahd_print_register(NULL, 0, "SCB_DISCONNECTED_LISTS", | ||
2466 | 0x1b8, regvalue, cur_col, wrap)); | ||
2467 | } | ||
2468 | |||
diff --git a/drivers/scsi/aic7xxx/aic7xxx.reg b/drivers/scsi/aic7xxx/aic7xxx.reg index 0d2f763c3427..9a96e55da39a 100644 --- a/drivers/scsi/aic7xxx/aic7xxx.reg +++ b/drivers/scsi/aic7xxx/aic7xxx.reg | |||
@@ -51,6 +51,17 @@ VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic7xxx.reg#40 $" | |||
51 | */ | 51 | */ |
52 | 52 | ||
53 | /* | 53 | /* |
54 | * Registers marked "dont_generate_debug_code" are not (yet) referenced | ||
55 | * from the driver code, and this keyword inhibit generation | ||
56 | * of debug code for them. | ||
57 | * | ||
58 | * REG_PRETTY_PRINT config will complain if dont_generate_debug_code | ||
59 | * is added to the register which is referenced in the driver. | ||
60 | * Unreferenced register with no dont_generate_debug_code will result | ||
61 | * in dead code. No warning is issued. | ||
62 | */ | ||
63 | |||
64 | /* | ||
54 | * SCSI Sequence Control (p. 3-11). | 65 | * SCSI Sequence Control (p. 3-11). |
55 | * Each bit, when set starts a specific SCSI sequence on the bus | 66 | * Each bit, when set starts a specific SCSI sequence on the bus |
56 | */ | 67 | */ |
@@ -97,6 +108,7 @@ register SXFRCTL1 { | |||
97 | field ENSTIMER 0x04 | 108 | field ENSTIMER 0x04 |
98 | field ACTNEGEN 0x02 | 109 | field ACTNEGEN 0x02 |
99 | field STPWEN 0x01 /* Powered Termination */ | 110 | field STPWEN 0x01 /* Powered Termination */ |
111 | dont_generate_debug_code | ||
100 | } | 112 | } |
101 | 113 | ||
102 | /* | 114 | /* |
@@ -155,6 +167,7 @@ register SCSISIGO { | |||
155 | mask P_MESGOUT CDI|MSGI | 167 | mask P_MESGOUT CDI|MSGI |
156 | mask P_STATUS CDI|IOI | 168 | mask P_STATUS CDI|IOI |
157 | mask P_MESGIN CDI|IOI|MSGI | 169 | mask P_MESGIN CDI|IOI|MSGI |
170 | dont_generate_debug_code | ||
158 | } | 171 | } |
159 | 172 | ||
160 | /* | 173 | /* |
@@ -194,6 +207,7 @@ register SCSIID { | |||
194 | */ | 207 | */ |
195 | alias SCSIOFFSET | 208 | alias SCSIOFFSET |
196 | mask SOFS_ULTRA2 0x7f /* Sync offset U2 chips */ | 209 | mask SOFS_ULTRA2 0x7f /* Sync offset U2 chips */ |
210 | dont_generate_debug_code | ||
197 | } | 211 | } |
198 | 212 | ||
199 | /* | 213 | /* |
@@ -205,6 +219,7 @@ register SCSIID { | |||
205 | register SCSIDATL { | 219 | register SCSIDATL { |
206 | address 0x006 | 220 | address 0x006 |
207 | access_mode RW | 221 | access_mode RW |
222 | dont_generate_debug_code | ||
208 | } | 223 | } |
209 | 224 | ||
210 | register SCSIDATH { | 225 | register SCSIDATH { |
@@ -223,6 +238,7 @@ register STCNT { | |||
223 | address 0x008 | 238 | address 0x008 |
224 | size 3 | 239 | size 3 |
225 | access_mode RW | 240 | access_mode RW |
241 | dont_generate_debug_code | ||
226 | } | 242 | } |
227 | 243 | ||
228 | /* ALT_MODE registers (Ultra2 and Ultra160 chips) */ | 244 | /* ALT_MODE registers (Ultra2 and Ultra160 chips) */ |
@@ -248,6 +264,7 @@ register OPTIONMODE { | |||
248 | field AUTO_MSGOUT_DE 0x02 | 264 | field AUTO_MSGOUT_DE 0x02 |
249 | field DIS_MSGIN_DUALEDGE 0x01 | 265 | field DIS_MSGIN_DUALEDGE 0x01 |
250 | mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE|DIS_MSGIN_DUALEDGE | 266 | mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE|DIS_MSGIN_DUALEDGE |
267 | dont_generate_debug_code | ||
251 | } | 268 | } |
252 | 269 | ||
253 | /* ALT_MODE register on Ultra160 chips */ | 270 | /* ALT_MODE register on Ultra160 chips */ |
@@ -256,6 +273,7 @@ register TARGCRCCNT { | |||
256 | size 2 | 273 | size 2 |
257 | access_mode RW | 274 | access_mode RW |
258 | count 2 | 275 | count 2 |
276 | dont_generate_debug_code | ||
259 | } | 277 | } |
260 | 278 | ||
261 | /* | 279 | /* |
@@ -271,6 +289,7 @@ register CLRSINT0 { | |||
271 | field CLRSWRAP 0x08 | 289 | field CLRSWRAP 0x08 |
272 | field CLRIOERR 0x08 /* Ultra2 Only */ | 290 | field CLRIOERR 0x08 /* Ultra2 Only */ |
273 | field CLRSPIORDY 0x02 | 291 | field CLRSPIORDY 0x02 |
292 | dont_generate_debug_code | ||
274 | } | 293 | } |
275 | 294 | ||
276 | /* | 295 | /* |
@@ -306,6 +325,7 @@ register CLRSINT1 { | |||
306 | field CLRSCSIPERR 0x04 | 325 | field CLRSCSIPERR 0x04 |
307 | field CLRPHASECHG 0x02 | 326 | field CLRPHASECHG 0x02 |
308 | field CLRREQINIT 0x01 | 327 | field CLRREQINIT 0x01 |
328 | dont_generate_debug_code | ||
309 | } | 329 | } |
310 | 330 | ||
311 | /* | 331 | /* |
@@ -360,6 +380,7 @@ register SCSIID_ULTRA2 { | |||
360 | access_mode RW | 380 | access_mode RW |
361 | mask TID 0xf0 /* Target ID mask */ | 381 | mask TID 0xf0 /* Target ID mask */ |
362 | mask OID 0x0f /* Our ID mask */ | 382 | mask OID 0x0f /* Our ID mask */ |
383 | dont_generate_debug_code | ||
363 | } | 384 | } |
364 | 385 | ||
365 | /* | 386 | /* |
@@ -425,6 +446,7 @@ register SHADDR { | |||
425 | address 0x014 | 446 | address 0x014 |
426 | size 4 | 447 | size 4 |
427 | access_mode RO | 448 | access_mode RO |
449 | dont_generate_debug_code | ||
428 | } | 450 | } |
429 | 451 | ||
430 | /* | 452 | /* |
@@ -441,6 +463,7 @@ register SELTIMER { | |||
441 | field STAGE2 0x02 | 463 | field STAGE2 0x02 |
442 | field STAGE1 0x01 | 464 | field STAGE1 0x01 |
443 | alias TARGIDIN | 465 | alias TARGIDIN |
466 | dont_generate_debug_code | ||
444 | } | 467 | } |
445 | 468 | ||
446 | /* | 469 | /* |
@@ -453,6 +476,7 @@ register SELID { | |||
453 | access_mode RW | 476 | access_mode RW |
454 | mask SELID_MASK 0xf0 | 477 | mask SELID_MASK 0xf0 |
455 | field ONEBIT 0x08 | 478 | field ONEBIT 0x08 |
479 | dont_generate_debug_code | ||
456 | } | 480 | } |
457 | 481 | ||
458 | register SCAMCTL { | 482 | register SCAMCTL { |
@@ -473,6 +497,7 @@ register TARGID { | |||
473 | size 2 | 497 | size 2 |
474 | access_mode RW | 498 | access_mode RW |
475 | count 14 | 499 | count 14 |
500 | dont_generate_debug_code | ||
476 | } | 501 | } |
477 | 502 | ||
478 | /* | 503 | /* |
@@ -495,6 +520,7 @@ register SPIOCAP { | |||
495 | field EEPROM 0x04 /* Writable external BIOS ROM */ | 520 | field EEPROM 0x04 /* Writable external BIOS ROM */ |
496 | field ROM 0x02 /* Logic for accessing external ROM */ | 521 | field ROM 0x02 /* Logic for accessing external ROM */ |
497 | field SSPIOCPS 0x01 /* Termination and cable detection */ | 522 | field SSPIOCPS 0x01 /* Termination and cable detection */ |
523 | dont_generate_debug_code | ||
498 | } | 524 | } |
499 | 525 | ||
500 | register BRDCTL { | 526 | register BRDCTL { |
@@ -514,6 +540,7 @@ register BRDCTL { | |||
514 | field BRDDAT2 0x04 | 540 | field BRDDAT2 0x04 |
515 | field BRDRW_ULTRA2 0x02 | 541 | field BRDRW_ULTRA2 0x02 |
516 | field BRDSTB_ULTRA2 0x01 | 542 | field BRDSTB_ULTRA2 0x01 |
543 | dont_generate_debug_code | ||
517 | } | 544 | } |
518 | 545 | ||
519 | /* | 546 | /* |
@@ -551,6 +578,7 @@ register SEECTL { | |||
551 | field SEECK 0x04 | 578 | field SEECK 0x04 |
552 | field SEEDO 0x02 | 579 | field SEEDO 0x02 |
553 | field SEEDI 0x01 | 580 | field SEEDI 0x01 |
581 | dont_generate_debug_code | ||
554 | } | 582 | } |
555 | /* | 583 | /* |
556 | * SCSI Block Control (p. 3-32) | 584 | * SCSI Block Control (p. 3-32) |
@@ -601,6 +629,7 @@ register SEQRAM { | |||
601 | address 0x061 | 629 | address 0x061 |
602 | access_mode RW | 630 | access_mode RW |
603 | count 2 | 631 | count 2 |
632 | dont_generate_debug_code | ||
604 | } | 633 | } |
605 | 634 | ||
606 | /* | 635 | /* |
@@ -610,6 +639,7 @@ register SEQRAM { | |||
610 | register SEQADDR0 { | 639 | register SEQADDR0 { |
611 | address 0x062 | 640 | address 0x062 |
612 | access_mode RW | 641 | access_mode RW |
642 | dont_generate_debug_code | ||
613 | } | 643 | } |
614 | 644 | ||
615 | register SEQADDR1 { | 645 | register SEQADDR1 { |
@@ -617,6 +647,7 @@ register SEQADDR1 { | |||
617 | access_mode RW | 647 | access_mode RW |
618 | count 8 | 648 | count 8 |
619 | mask SEQADDR1_MASK 0x01 | 649 | mask SEQADDR1_MASK 0x01 |
650 | dont_generate_debug_code | ||
620 | } | 651 | } |
621 | 652 | ||
622 | /* | 653 | /* |
@@ -627,35 +658,41 @@ register ACCUM { | |||
627 | address 0x064 | 658 | address 0x064 |
628 | access_mode RW | 659 | access_mode RW |
629 | accumulator | 660 | accumulator |
661 | dont_generate_debug_code | ||
630 | } | 662 | } |
631 | 663 | ||
632 | register SINDEX { | 664 | register SINDEX { |
633 | address 0x065 | 665 | address 0x065 |
634 | access_mode RW | 666 | access_mode RW |
635 | sindex | 667 | sindex |
668 | dont_generate_debug_code | ||
636 | } | 669 | } |
637 | 670 | ||
638 | register DINDEX { | 671 | register DINDEX { |
639 | address 0x066 | 672 | address 0x066 |
640 | access_mode RW | 673 | access_mode RW |
674 | dont_generate_debug_code | ||
641 | } | 675 | } |
642 | 676 | ||
643 | register ALLONES { | 677 | register ALLONES { |
644 | address 0x069 | 678 | address 0x069 |
645 | access_mode RO | 679 | access_mode RO |
646 | allones | 680 | allones |
681 | dont_generate_debug_code | ||
647 | } | 682 | } |
648 | 683 | ||
649 | register ALLZEROS { | 684 | register ALLZEROS { |
650 | address 0x06a | 685 | address 0x06a |
651 | access_mode RO | 686 | access_mode RO |
652 | allzeros | 687 | allzeros |
688 | dont_generate_debug_code | ||
653 | } | 689 | } |
654 | 690 | ||
655 | register NONE { | 691 | register NONE { |
656 | address 0x06a | 692 | address 0x06a |
657 | access_mode WO | 693 | access_mode WO |
658 | none | 694 | none |
695 | dont_generate_debug_code | ||
659 | } | 696 | } |
660 | 697 | ||
661 | register FLAGS { | 698 | register FLAGS { |
@@ -664,16 +701,19 @@ register FLAGS { | |||
664 | count 18 | 701 | count 18 |
665 | field ZERO 0x02 | 702 | field ZERO 0x02 |
666 | field CARRY 0x01 | 703 | field CARRY 0x01 |
704 | dont_generate_debug_code | ||
667 | } | 705 | } |
668 | 706 | ||
669 | register SINDIR { | 707 | register SINDIR { |
670 | address 0x06c | 708 | address 0x06c |
671 | access_mode RO | 709 | access_mode RO |
710 | dont_generate_debug_code | ||
672 | } | 711 | } |
673 | 712 | ||
674 | register DINDIR { | 713 | register DINDIR { |
675 | address 0x06d | 714 | address 0x06d |
676 | access_mode WO | 715 | access_mode WO |
716 | dont_generate_debug_code | ||
677 | } | 717 | } |
678 | 718 | ||
679 | register FUNCTION1 { | 719 | register FUNCTION1 { |
@@ -685,6 +725,7 @@ register STACK { | |||
685 | address 0x06f | 725 | address 0x06f |
686 | access_mode RO | 726 | access_mode RO |
687 | count 5 | 727 | count 5 |
728 | dont_generate_debug_code | ||
688 | } | 729 | } |
689 | 730 | ||
690 | const STACK_SIZE 4 | 731 | const STACK_SIZE 4 |
@@ -716,6 +757,7 @@ register DSCOMMAND0 { | |||
716 | field RAMPS 0x04 /* External SCB RAM Present */ | 757 | field RAMPS 0x04 /* External SCB RAM Present */ |
717 | field USCBSIZE32 0x02 /* Use 32byte SCB Page Size */ | 758 | field USCBSIZE32 0x02 /* Use 32byte SCB Page Size */ |
718 | field CIOPARCKEN 0x01 /* Internal bus parity error enable */ | 759 | field CIOPARCKEN 0x01 /* Internal bus parity error enable */ |
760 | dont_generate_debug_code | ||
719 | } | 761 | } |
720 | 762 | ||
721 | register DSCOMMAND1 { | 763 | register DSCOMMAND1 { |
@@ -724,6 +766,7 @@ register DSCOMMAND1 { | |||
724 | mask DSLATT 0xfc /* PCI latency timer (non-ultra2) */ | 766 | mask DSLATT 0xfc /* PCI latency timer (non-ultra2) */ |
725 | field HADDLDSEL1 0x02 /* Host Address Load Select Bits */ | 767 | field HADDLDSEL1 0x02 /* Host Address Load Select Bits */ |
726 | field HADDLDSEL0 0x01 | 768 | field HADDLDSEL0 0x01 |
769 | dont_generate_debug_code | ||
727 | } | 770 | } |
728 | 771 | ||
729 | /* | 772 | /* |
@@ -735,6 +778,7 @@ register BUSTIME { | |||
735 | count 2 | 778 | count 2 |
736 | mask BOFF 0xf0 | 779 | mask BOFF 0xf0 |
737 | mask BON 0x0f | 780 | mask BON 0x0f |
781 | dont_generate_debug_code | ||
738 | } | 782 | } |
739 | 783 | ||
740 | /* | 784 | /* |
@@ -749,6 +793,7 @@ register BUSSPD { | |||
749 | mask STBON 0x07 | 793 | mask STBON 0x07 |
750 | mask DFTHRSH_100 0xc0 | 794 | mask DFTHRSH_100 0xc0 |
751 | mask DFTHRSH_75 0x80 | 795 | mask DFTHRSH_75 0x80 |
796 | dont_generate_debug_code | ||
752 | } | 797 | } |
753 | 798 | ||
754 | /* aic7850/55/60/70/80/95 only */ | 799 | /* aic7850/55/60/70/80/95 only */ |
@@ -756,6 +801,7 @@ register DSPCISTATUS { | |||
756 | address 0x086 | 801 | address 0x086 |
757 | count 4 | 802 | count 4 |
758 | mask DFTHRSH_100 0xc0 | 803 | mask DFTHRSH_100 0xc0 |
804 | dont_generate_debug_code | ||
759 | } | 805 | } |
760 | 806 | ||
761 | /* aic7890/91/96/97 only */ | 807 | /* aic7890/91/96/97 only */ |
@@ -764,6 +810,7 @@ register HS_MAILBOX { | |||
764 | mask HOST_MAILBOX 0xF0 | 810 | mask HOST_MAILBOX 0xF0 |
765 | mask SEQ_MAILBOX 0x0F | 811 | mask SEQ_MAILBOX 0x0F |
766 | mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */ | 812 | mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */ |
813 | dont_generate_debug_code | ||
767 | } | 814 | } |
768 | 815 | ||
769 | const HOST_MAILBOX_SHIFT 4 | 816 | const HOST_MAILBOX_SHIFT 4 |
@@ -784,6 +831,7 @@ register HCNTRL { | |||
784 | field INTEN 0x02 | 831 | field INTEN 0x02 |
785 | field CHIPRST 0x01 | 832 | field CHIPRST 0x01 |
786 | field CHIPRSTACK 0x01 | 833 | field CHIPRSTACK 0x01 |
834 | dont_generate_debug_code | ||
787 | } | 835 | } |
788 | 836 | ||
789 | /* | 837 | /* |
@@ -795,12 +843,14 @@ register HADDR { | |||
795 | address 0x088 | 843 | address 0x088 |
796 | size 4 | 844 | size 4 |
797 | access_mode RW | 845 | access_mode RW |
846 | dont_generate_debug_code | ||
798 | } | 847 | } |
799 | 848 | ||
800 | register HCNT { | 849 | register HCNT { |
801 | address 0x08c | 850 | address 0x08c |
802 | size 3 | 851 | size 3 |
803 | access_mode RW | 852 | access_mode RW |
853 | dont_generate_debug_code | ||
804 | } | 854 | } |
805 | 855 | ||
806 | /* | 856 | /* |
@@ -810,6 +860,7 @@ register HCNT { | |||
810 | register SCBPTR { | 860 | register SCBPTR { |
811 | address 0x090 | 861 | address 0x090 |
812 | access_mode RW | 862 | access_mode RW |
863 | dont_generate_debug_code | ||
813 | } | 864 | } |
814 | 865 | ||
815 | /* | 866 | /* |
@@ -878,6 +929,7 @@ register INTSTAT { | |||
878 | 929 | ||
879 | mask SEQINT_MASK 0xf0|SEQINT /* SEQINT Status Codes */ | 930 | mask SEQINT_MASK 0xf0|SEQINT /* SEQINT Status Codes */ |
880 | mask INT_PEND (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT) | 931 | mask INT_PEND (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT) |
932 | dont_generate_debug_code | ||
881 | } | 933 | } |
882 | 934 | ||
883 | /* | 935 | /* |
@@ -911,6 +963,7 @@ register CLRINT { | |||
911 | field CLRSCSIINT 0x04 | 963 | field CLRSCSIINT 0x04 |
912 | field CLRCMDINT 0x02 | 964 | field CLRCMDINT 0x02 |
913 | field CLRSEQINT 0x01 | 965 | field CLRSEQINT 0x01 |
966 | dont_generate_debug_code | ||
914 | } | 967 | } |
915 | 968 | ||
916 | register DFCNTRL { | 969 | register DFCNTRL { |
@@ -944,6 +997,7 @@ register DFSTATUS { | |||
944 | register DFWADDR { | 997 | register DFWADDR { |
945 | address 0x95 | 998 | address 0x95 |
946 | access_mode RW | 999 | access_mode RW |
1000 | dont_generate_debug_code | ||
947 | } | 1001 | } |
948 | 1002 | ||
949 | register DFRADDR { | 1003 | register DFRADDR { |
@@ -954,6 +1008,7 @@ register DFRADDR { | |||
954 | register DFDAT { | 1008 | register DFDAT { |
955 | address 0x099 | 1009 | address 0x099 |
956 | access_mode RW | 1010 | access_mode RW |
1011 | dont_generate_debug_code | ||
957 | } | 1012 | } |
958 | 1013 | ||
959 | /* | 1014 | /* |
@@ -967,6 +1022,7 @@ register SCBCNT { | |||
967 | count 1 | 1022 | count 1 |
968 | field SCBAUTO 0x80 | 1023 | field SCBAUTO 0x80 |
969 | mask SCBCNT_MASK 0x1f | 1024 | mask SCBCNT_MASK 0x1f |
1025 | dont_generate_debug_code | ||
970 | } | 1026 | } |
971 | 1027 | ||
972 | /* | 1028 | /* |
@@ -977,6 +1033,7 @@ register QINFIFO { | |||
977 | address 0x09b | 1033 | address 0x09b |
978 | access_mode RW | 1034 | access_mode RW |
979 | count 12 | 1035 | count 12 |
1036 | dont_generate_debug_code | ||
980 | } | 1037 | } |
981 | 1038 | ||
982 | /* | 1039 | /* |
@@ -996,6 +1053,7 @@ register QOUTFIFO { | |||
996 | address 0x09d | 1053 | address 0x09d |
997 | access_mode WO | 1054 | access_mode WO |
998 | count 7 | 1055 | count 7 |
1056 | dont_generate_debug_code | ||
999 | } | 1057 | } |
1000 | 1058 | ||
1001 | register CRCCONTROL1 { | 1059 | register CRCCONTROL1 { |
@@ -1008,6 +1066,7 @@ register CRCCONTROL1 { | |||
1008 | field CRCREQCHKEN 0x10 | 1066 | field CRCREQCHKEN 0x10 |
1009 | field TARGCRCENDEN 0x08 | 1067 | field TARGCRCENDEN 0x08 |
1010 | field TARGCRCCNTEN 0x04 | 1068 | field TARGCRCCNTEN 0x04 |
1069 | dont_generate_debug_code | ||
1011 | } | 1070 | } |
1012 | 1071 | ||
1013 | 1072 | ||
@@ -1040,6 +1099,7 @@ register SFUNCT { | |||
1040 | access_mode RW | 1099 | access_mode RW |
1041 | count 4 | 1100 | count 4 |
1042 | field ALT_MODE 0x80 | 1101 | field ALT_MODE 0x80 |
1102 | dont_generate_debug_code | ||
1043 | } | 1103 | } |
1044 | 1104 | ||
1045 | /* | 1105 | /* |
@@ -1053,24 +1113,31 @@ scb { | |||
1053 | size 4 | 1113 | size 4 |
1054 | alias SCB_RESIDUAL_DATACNT | 1114 | alias SCB_RESIDUAL_DATACNT |
1055 | alias SCB_CDB_STORE | 1115 | alias SCB_CDB_STORE |
1116 | dont_generate_debug_code | ||
1056 | } | 1117 | } |
1057 | SCB_RESIDUAL_SGPTR { | 1118 | SCB_RESIDUAL_SGPTR { |
1058 | size 4 | 1119 | size 4 |
1120 | dont_generate_debug_code | ||
1059 | } | 1121 | } |
1060 | SCB_SCSI_STATUS { | 1122 | SCB_SCSI_STATUS { |
1061 | size 1 | 1123 | size 1 |
1124 | dont_generate_debug_code | ||
1062 | } | 1125 | } |
1063 | SCB_TARGET_PHASES { | 1126 | SCB_TARGET_PHASES { |
1064 | size 1 | 1127 | size 1 |
1128 | dont_generate_debug_code | ||
1065 | } | 1129 | } |
1066 | SCB_TARGET_DATA_DIR { | 1130 | SCB_TARGET_DATA_DIR { |
1067 | size 1 | 1131 | size 1 |
1132 | dont_generate_debug_code | ||
1068 | } | 1133 | } |
1069 | SCB_TARGET_ITAG { | 1134 | SCB_TARGET_ITAG { |
1070 | size 1 | 1135 | size 1 |
1136 | dont_generate_debug_code | ||
1071 | } | 1137 | } |
1072 | SCB_DATAPTR { | 1138 | SCB_DATAPTR { |
1073 | size 4 | 1139 | size 4 |
1140 | dont_generate_debug_code | ||
1074 | } | 1141 | } |
1075 | SCB_DATACNT { | 1142 | SCB_DATACNT { |
1076 | /* | 1143 | /* |
@@ -1080,12 +1147,14 @@ scb { | |||
1080 | size 4 | 1147 | size 4 |
1081 | field SG_LAST_SEG 0x80 /* In the fourth byte */ | 1148 | field SG_LAST_SEG 0x80 /* In the fourth byte */ |
1082 | mask SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */ | 1149 | mask SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */ |
1150 | dont_generate_debug_code | ||
1083 | } | 1151 | } |
1084 | SCB_SGPTR { | 1152 | SCB_SGPTR { |
1085 | size 4 | 1153 | size 4 |
1086 | field SG_RESID_VALID 0x04 /* In the first byte */ | 1154 | field SG_RESID_VALID 0x04 /* In the first byte */ |
1087 | field SG_FULL_RESID 0x02 /* In the first byte */ | 1155 | field SG_FULL_RESID 0x02 /* In the first byte */ |
1088 | field SG_LIST_NULL 0x01 /* In the first byte */ | 1156 | field SG_LIST_NULL 0x01 /* In the first byte */ |
1157 | dont_generate_debug_code | ||
1089 | } | 1158 | } |
1090 | SCB_CONTROL { | 1159 | SCB_CONTROL { |
1091 | size 1 | 1160 | size 1 |
@@ -1115,22 +1184,27 @@ scb { | |||
1115 | } | 1184 | } |
1116 | SCB_CDB_LEN { | 1185 | SCB_CDB_LEN { |
1117 | size 1 | 1186 | size 1 |
1187 | dont_generate_debug_code | ||
1118 | } | 1188 | } |
1119 | SCB_SCSIRATE { | 1189 | SCB_SCSIRATE { |
1120 | size 1 | 1190 | size 1 |
1191 | dont_generate_debug_code | ||
1121 | } | 1192 | } |
1122 | SCB_SCSIOFFSET { | 1193 | SCB_SCSIOFFSET { |
1123 | size 1 | 1194 | size 1 |
1124 | count 1 | 1195 | count 1 |
1196 | dont_generate_debug_code | ||
1125 | } | 1197 | } |
1126 | SCB_NEXT { | 1198 | SCB_NEXT { |
1127 | size 1 | 1199 | size 1 |
1200 | dont_generate_debug_code | ||
1128 | } | 1201 | } |
1129 | SCB_64_SPARE { | 1202 | SCB_64_SPARE { |
1130 | size 16 | 1203 | size 16 |
1131 | } | 1204 | } |
1132 | SCB_64_BTT { | 1205 | SCB_64_BTT { |
1133 | size 16 | 1206 | size 16 |
1207 | dont_generate_debug_code | ||
1134 | } | 1208 | } |
1135 | } | 1209 | } |
1136 | 1210 | ||
@@ -1149,6 +1223,7 @@ register SEECTL_2840 { | |||
1149 | field CS_2840 0x04 | 1223 | field CS_2840 0x04 |
1150 | field CK_2840 0x02 | 1224 | field CK_2840 0x02 |
1151 | field DO_2840 0x01 | 1225 | field DO_2840 0x01 |
1226 | dont_generate_debug_code | ||
1152 | } | 1227 | } |
1153 | 1228 | ||
1154 | register STATUS_2840 { | 1229 | register STATUS_2840 { |
@@ -1159,6 +1234,7 @@ register STATUS_2840 { | |||
1159 | mask BIOS_SEL 0x60 | 1234 | mask BIOS_SEL 0x60 |
1160 | mask ADSEL 0x1e | 1235 | mask ADSEL 0x1e |
1161 | field DI_2840 0x01 | 1236 | field DI_2840 0x01 |
1237 | dont_generate_debug_code | ||
1162 | } | 1238 | } |
1163 | 1239 | ||
1164 | /* --------------------- AIC-7870-only definitions -------------------- */ | 1240 | /* --------------------- AIC-7870-only definitions -------------------- */ |
@@ -1166,18 +1242,22 @@ register STATUS_2840 { | |||
1166 | register CCHADDR { | 1242 | register CCHADDR { |
1167 | address 0x0E0 | 1243 | address 0x0E0 |
1168 | size 8 | 1244 | size 8 |
1245 | dont_generate_debug_code | ||
1169 | } | 1246 | } |
1170 | 1247 | ||
1171 | register CCHCNT { | 1248 | register CCHCNT { |
1172 | address 0x0E8 | 1249 | address 0x0E8 |
1250 | dont_generate_debug_code | ||
1173 | } | 1251 | } |
1174 | 1252 | ||
1175 | register CCSGRAM { | 1253 | register CCSGRAM { |
1176 | address 0x0E9 | 1254 | address 0x0E9 |
1255 | dont_generate_debug_code | ||
1177 | } | 1256 | } |
1178 | 1257 | ||
1179 | register CCSGADDR { | 1258 | register CCSGADDR { |
1180 | address 0x0EA | 1259 | address 0x0EA |
1260 | dont_generate_debug_code | ||
1181 | } | 1261 | } |
1182 | 1262 | ||
1183 | register CCSGCTL { | 1263 | register CCSGCTL { |
@@ -1186,11 +1266,13 @@ register CCSGCTL { | |||
1186 | field CCSGEN 0x08 | 1266 | field CCSGEN 0x08 |
1187 | field SG_FETCH_NEEDED 0x02 /* Bit used for software state */ | 1267 | field SG_FETCH_NEEDED 0x02 /* Bit used for software state */ |
1188 | field CCSGRESET 0x01 | 1268 | field CCSGRESET 0x01 |
1269 | dont_generate_debug_code | ||
1189 | } | 1270 | } |
1190 | 1271 | ||
1191 | register CCSCBCNT { | 1272 | register CCSCBCNT { |
1192 | address 0xEF | 1273 | address 0xEF |
1193 | count 1 | 1274 | count 1 |
1275 | dont_generate_debug_code | ||
1194 | } | 1276 | } |
1195 | 1277 | ||
1196 | register CCSCBCTL { | 1278 | register CCSCBCTL { |
@@ -1201,14 +1283,17 @@ register CCSCBCTL { | |||
1201 | field CCSCBEN 0x08 | 1283 | field CCSCBEN 0x08 |
1202 | field CCSCBDIR 0x04 | 1284 | field CCSCBDIR 0x04 |
1203 | field CCSCBRESET 0x01 | 1285 | field CCSCBRESET 0x01 |
1286 | dont_generate_debug_code | ||
1204 | } | 1287 | } |
1205 | 1288 | ||
1206 | register CCSCBADDR { | 1289 | register CCSCBADDR { |
1207 | address 0x0ED | 1290 | address 0x0ED |
1291 | dont_generate_debug_code | ||
1208 | } | 1292 | } |
1209 | 1293 | ||
1210 | register CCSCBRAM { | 1294 | register CCSCBRAM { |
1211 | address 0xEC | 1295 | address 0xEC |
1296 | dont_generate_debug_code | ||
1212 | } | 1297 | } |
1213 | 1298 | ||
1214 | /* | 1299 | /* |
@@ -1218,23 +1303,28 @@ register SCBBADDR { | |||
1218 | address 0x0F0 | 1303 | address 0x0F0 |
1219 | access_mode RW | 1304 | access_mode RW |
1220 | count 3 | 1305 | count 3 |
1306 | dont_generate_debug_code | ||
1221 | } | 1307 | } |
1222 | 1308 | ||
1223 | register CCSCBPTR { | 1309 | register CCSCBPTR { |
1224 | address 0x0F1 | 1310 | address 0x0F1 |
1311 | dont_generate_debug_code | ||
1225 | } | 1312 | } |
1226 | 1313 | ||
1227 | register HNSCB_QOFF { | 1314 | register HNSCB_QOFF { |
1228 | address 0x0F4 | 1315 | address 0x0F4 |
1229 | count 4 | 1316 | count 4 |
1317 | dont_generate_debug_code | ||
1230 | } | 1318 | } |
1231 | 1319 | ||
1232 | register SNSCB_QOFF { | 1320 | register SNSCB_QOFF { |
1233 | address 0x0F6 | 1321 | address 0x0F6 |
1322 | dont_generate_debug_code | ||
1234 | } | 1323 | } |
1235 | 1324 | ||
1236 | register SDSCB_QOFF { | 1325 | register SDSCB_QOFF { |
1237 | address 0x0F8 | 1326 | address 0x0F8 |
1327 | dont_generate_debug_code | ||
1238 | } | 1328 | } |
1239 | 1329 | ||
1240 | register QOFF_CTLSTA { | 1330 | register QOFF_CTLSTA { |
@@ -1244,6 +1334,7 @@ register QOFF_CTLSTA { | |||
1244 | field SDSCB_ROLLOVER 0x10 | 1334 | field SDSCB_ROLLOVER 0x10 |
1245 | mask SCB_QSIZE 0x07 | 1335 | mask SCB_QSIZE 0x07 |
1246 | mask SCB_QSIZE_256 0x06 | 1336 | mask SCB_QSIZE_256 0x06 |
1337 | dont_generate_debug_code | ||
1247 | } | 1338 | } |
1248 | 1339 | ||
1249 | register DFF_THRSH { | 1340 | register DFF_THRSH { |
@@ -1267,6 +1358,7 @@ register DFF_THRSH { | |||
1267 | mask WR_DFTHRSH_90 0x60 | 1358 | mask WR_DFTHRSH_90 0x60 |
1268 | mask WR_DFTHRSH_MAX 0x70 | 1359 | mask WR_DFTHRSH_MAX 0x70 |
1269 | count 4 | 1360 | count 4 |
1361 | dont_generate_debug_code | ||
1270 | } | 1362 | } |
1271 | 1363 | ||
1272 | register SG_CACHE_PRE { | 1364 | register SG_CACHE_PRE { |
@@ -1275,6 +1367,7 @@ register SG_CACHE_PRE { | |||
1275 | mask SG_ADDR_MASK 0xf8 | 1367 | mask SG_ADDR_MASK 0xf8 |
1276 | field LAST_SEG 0x02 | 1368 | field LAST_SEG 0x02 |
1277 | field LAST_SEG_DONE 0x01 | 1369 | field LAST_SEG_DONE 0x01 |
1370 | dont_generate_debug_code | ||
1278 | } | 1371 | } |
1279 | 1372 | ||
1280 | register SG_CACHE_SHADOW { | 1373 | register SG_CACHE_SHADOW { |
@@ -1283,6 +1376,7 @@ register SG_CACHE_SHADOW { | |||
1283 | mask SG_ADDR_MASK 0xf8 | 1376 | mask SG_ADDR_MASK 0xf8 |
1284 | field LAST_SEG 0x02 | 1377 | field LAST_SEG 0x02 |
1285 | field LAST_SEG_DONE 0x01 | 1378 | field LAST_SEG_DONE 0x01 |
1379 | dont_generate_debug_code | ||
1286 | } | 1380 | } |
1287 | /* ---------------------- Scratch RAM Offsets ------------------------- */ | 1381 | /* ---------------------- Scratch RAM Offsets ------------------------- */ |
1288 | /* These offsets are either to values that are initialized by the board's | 1382 | /* These offsets are either to values that are initialized by the board's |
@@ -1309,6 +1403,7 @@ scratch_ram { | |||
1309 | BUSY_TARGETS { | 1403 | BUSY_TARGETS { |
1310 | alias TARG_SCSIRATE | 1404 | alias TARG_SCSIRATE |
1311 | size 16 | 1405 | size 16 |
1406 | dont_generate_debug_code | ||
1312 | } | 1407 | } |
1313 | /* | 1408 | /* |
1314 | * Bit vector of targets that have ULTRA enabled as set by | 1409 | * Bit vector of targets that have ULTRA enabled as set by |
@@ -1321,6 +1416,7 @@ scratch_ram { | |||
1321 | alias CMDSIZE_TABLE | 1416 | alias CMDSIZE_TABLE |
1322 | size 2 | 1417 | size 2 |
1323 | count 2 | 1418 | count 2 |
1419 | dont_generate_debug_code | ||
1324 | } | 1420 | } |
1325 | /* | 1421 | /* |
1326 | * Bit vector of targets that have disconnection disabled as set by | 1422 | * Bit vector of targets that have disconnection disabled as set by |
@@ -1331,6 +1427,7 @@ scratch_ram { | |||
1331 | DISC_DSB { | 1427 | DISC_DSB { |
1332 | size 2 | 1428 | size 2 |
1333 | count 6 | 1429 | count 6 |
1430 | dont_generate_debug_code | ||
1334 | } | 1431 | } |
1335 | CMDSIZE_TABLE_TAIL { | 1432 | CMDSIZE_TABLE_TAIL { |
1336 | size 4 | 1433 | size 4 |
@@ -1341,12 +1438,14 @@ scratch_ram { | |||
1341 | */ | 1438 | */ |
1342 | MWI_RESIDUAL { | 1439 | MWI_RESIDUAL { |
1343 | size 1 | 1440 | size 1 |
1441 | dont_generate_debug_code | ||
1344 | } | 1442 | } |
1345 | /* | 1443 | /* |
1346 | * SCBID of the next SCB to be started by the controller. | 1444 | * SCBID of the next SCB to be started by the controller. |
1347 | */ | 1445 | */ |
1348 | NEXT_QUEUED_SCB { | 1446 | NEXT_QUEUED_SCB { |
1349 | size 1 | 1447 | size 1 |
1448 | dont_generate_debug_code | ||
1350 | } | 1449 | } |
1351 | /* | 1450 | /* |
1352 | * Single byte buffer used to designate the type or message | 1451 | * Single byte buffer used to designate the type or message |
@@ -1354,6 +1453,7 @@ scratch_ram { | |||
1354 | */ | 1453 | */ |
1355 | MSG_OUT { | 1454 | MSG_OUT { |
1356 | size 1 | 1455 | size 1 |
1456 | dont_generate_debug_code | ||
1357 | } | 1457 | } |
1358 | /* Parameters for DMA Logic */ | 1458 | /* Parameters for DMA Logic */ |
1359 | DMAPARAMS { | 1459 | DMAPARAMS { |
@@ -1369,6 +1469,7 @@ scratch_ram { | |||
1369 | field DIRECTION 0x04 /* Set indicates PCI->SCSI */ | 1469 | field DIRECTION 0x04 /* Set indicates PCI->SCSI */ |
1370 | field FIFOFLUSH 0x02 | 1470 | field FIFOFLUSH 0x02 |
1371 | field FIFORESET 0x01 | 1471 | field FIFORESET 0x01 |
1472 | dont_generate_debug_code | ||
1372 | } | 1473 | } |
1373 | SEQ_FLAGS { | 1474 | SEQ_FLAGS { |
1374 | size 1 | 1475 | size 1 |
@@ -1390,9 +1491,11 @@ scratch_ram { | |||
1390 | */ | 1491 | */ |
1391 | SAVED_SCSIID { | 1492 | SAVED_SCSIID { |
1392 | size 1 | 1493 | size 1 |
1494 | dont_generate_debug_code | ||
1393 | } | 1495 | } |
1394 | SAVED_LUN { | 1496 | SAVED_LUN { |
1395 | size 1 | 1497 | size 1 |
1498 | dont_generate_debug_code | ||
1396 | } | 1499 | } |
1397 | /* | 1500 | /* |
1398 | * The last bus phase as seen by the sequencer. | 1501 | * The last bus phase as seen by the sequencer. |
@@ -1417,6 +1520,7 @@ scratch_ram { | |||
1417 | */ | 1520 | */ |
1418 | WAITING_SCBH { | 1521 | WAITING_SCBH { |
1419 | size 1 | 1522 | size 1 |
1523 | dont_generate_debug_code | ||
1420 | } | 1524 | } |
1421 | /* | 1525 | /* |
1422 | * head of list of SCBs that are | 1526 | * head of list of SCBs that are |
@@ -1425,6 +1529,7 @@ scratch_ram { | |||
1425 | */ | 1529 | */ |
1426 | DISCONNECTED_SCBH { | 1530 | DISCONNECTED_SCBH { |
1427 | size 1 | 1531 | size 1 |
1532 | dont_generate_debug_code | ||
1428 | } | 1533 | } |
1429 | /* | 1534 | /* |
1430 | * head of list of SCBs that are | 1535 | * head of list of SCBs that are |
@@ -1432,6 +1537,7 @@ scratch_ram { | |||
1432 | */ | 1537 | */ |
1433 | FREE_SCBH { | 1538 | FREE_SCBH { |
1434 | size 1 | 1539 | size 1 |
1540 | dont_generate_debug_code | ||
1435 | } | 1541 | } |
1436 | /* | 1542 | /* |
1437 | * head of list of SCBs that have | 1543 | * head of list of SCBs that have |
@@ -1446,6 +1552,7 @@ scratch_ram { | |||
1446 | */ | 1552 | */ |
1447 | HSCB_ADDR { | 1553 | HSCB_ADDR { |
1448 | size 4 | 1554 | size 4 |
1555 | dont_generate_debug_code | ||
1449 | } | 1556 | } |
1450 | /* | 1557 | /* |
1451 | * Base address of our shared data with the kernel driver in host | 1558 | * Base address of our shared data with the kernel driver in host |
@@ -1454,15 +1561,19 @@ scratch_ram { | |||
1454 | */ | 1561 | */ |
1455 | SHARED_DATA_ADDR { | 1562 | SHARED_DATA_ADDR { |
1456 | size 4 | 1563 | size 4 |
1564 | dont_generate_debug_code | ||
1457 | } | 1565 | } |
1458 | KERNEL_QINPOS { | 1566 | KERNEL_QINPOS { |
1459 | size 1 | 1567 | size 1 |
1568 | dont_generate_debug_code | ||
1460 | } | 1569 | } |
1461 | QINPOS { | 1570 | QINPOS { |
1462 | size 1 | 1571 | size 1 |
1572 | dont_generate_debug_code | ||
1463 | } | 1573 | } |
1464 | QOUTPOS { | 1574 | QOUTPOS { |
1465 | size 1 | 1575 | size 1 |
1576 | dont_generate_debug_code | ||
1466 | } | 1577 | } |
1467 | /* | 1578 | /* |
1468 | * Kernel and sequencer offsets into the queue of | 1579 | * Kernel and sequencer offsets into the queue of |
@@ -1471,9 +1582,11 @@ scratch_ram { | |||
1471 | */ | 1582 | */ |
1472 | KERNEL_TQINPOS { | 1583 | KERNEL_TQINPOS { |
1473 | size 1 | 1584 | size 1 |
1585 | dont_generate_debug_code | ||
1474 | } | 1586 | } |
1475 | TQINPOS { | 1587 | TQINPOS { |
1476 | size 1 | 1588 | size 1 |
1589 | dont_generate_debug_code | ||
1477 | } | 1590 | } |
1478 | ARG_1 { | 1591 | ARG_1 { |
1479 | size 1 | 1592 | size 1 |
@@ -1486,10 +1599,12 @@ scratch_ram { | |||
1486 | mask CONT_MSG_LOOP 0x04 | 1599 | mask CONT_MSG_LOOP 0x04 |
1487 | mask CONT_TARG_SESSION 0x02 | 1600 | mask CONT_TARG_SESSION 0x02 |
1488 | alias RETURN_1 | 1601 | alias RETURN_1 |
1602 | dont_generate_debug_code | ||
1489 | } | 1603 | } |
1490 | ARG_2 { | 1604 | ARG_2 { |
1491 | size 1 | 1605 | size 1 |
1492 | alias RETURN_2 | 1606 | alias RETURN_2 |
1607 | dont_generate_debug_code | ||
1493 | } | 1608 | } |
1494 | 1609 | ||
1495 | /* | 1610 | /* |
@@ -1498,6 +1613,7 @@ scratch_ram { | |||
1498 | LAST_MSG { | 1613 | LAST_MSG { |
1499 | size 1 | 1614 | size 1 |
1500 | alias TARG_IMMEDIATE_SCB | 1615 | alias TARG_IMMEDIATE_SCB |
1616 | dont_generate_debug_code | ||
1501 | } | 1617 | } |
1502 | 1618 | ||
1503 | /* | 1619 | /* |
@@ -1513,6 +1629,7 @@ scratch_ram { | |||
1513 | field ENAUTOATNO 0x08 | 1629 | field ENAUTOATNO 0x08 |
1514 | field ENAUTOATNI 0x04 | 1630 | field ENAUTOATNI 0x04 |
1515 | field ENAUTOATNP 0x02 | 1631 | field ENAUTOATNP 0x02 |
1632 | dont_generate_debug_code | ||
1516 | } | 1633 | } |
1517 | } | 1634 | } |
1518 | 1635 | ||
@@ -1533,12 +1650,14 @@ scratch_ram { | |||
1533 | field HA_274_EXTENDED_TRANS 0x01 | 1650 | field HA_274_EXTENDED_TRANS 0x01 |
1534 | alias INITIATOR_TAG | 1651 | alias INITIATOR_TAG |
1535 | count 1 | 1652 | count 1 |
1653 | dont_generate_debug_code | ||
1536 | } | 1654 | } |
1537 | 1655 | ||
1538 | SEQ_FLAGS2 { | 1656 | SEQ_FLAGS2 { |
1539 | size 1 | 1657 | size 1 |
1540 | field SCB_DMA 0x01 | 1658 | field SCB_DMA 0x01 |
1541 | field TARGET_MSG_PENDING 0x02 | 1659 | field TARGET_MSG_PENDING 0x02 |
1660 | dont_generate_debug_code | ||
1542 | } | 1661 | } |
1543 | } | 1662 | } |
1544 | 1663 | ||
@@ -1562,6 +1681,7 @@ scratch_ram { | |||
1562 | field ENSPCHK 0x20 | 1681 | field ENSPCHK 0x20 |
1563 | mask HSCSIID 0x07 /* our SCSI ID */ | 1682 | mask HSCSIID 0x07 /* our SCSI ID */ |
1564 | mask HWSCSIID 0x0f /* our SCSI ID if Wide Bus */ | 1683 | mask HWSCSIID 0x0f /* our SCSI ID if Wide Bus */ |
1684 | dont_generate_debug_code | ||
1565 | } | 1685 | } |
1566 | INTDEF { | 1686 | INTDEF { |
1567 | address 0x05c | 1687 | address 0x05c |
@@ -1569,11 +1689,13 @@ scratch_ram { | |||
1569 | count 1 | 1689 | count 1 |
1570 | field EDGE_TRIG 0x80 | 1690 | field EDGE_TRIG 0x80 |
1571 | mask VECTOR 0x0f | 1691 | mask VECTOR 0x0f |
1692 | dont_generate_debug_code | ||
1572 | } | 1693 | } |
1573 | HOSTCONF { | 1694 | HOSTCONF { |
1574 | address 0x05d | 1695 | address 0x05d |
1575 | size 1 | 1696 | size 1 |
1576 | count 1 | 1697 | count 1 |
1698 | dont_generate_debug_code | ||
1577 | } | 1699 | } |
1578 | HA_274_BIOSCTRL { | 1700 | HA_274_BIOSCTRL { |
1579 | address 0x05f | 1701 | address 0x05f |
@@ -1582,6 +1704,7 @@ scratch_ram { | |||
1582 | mask BIOSMODE 0x30 | 1704 | mask BIOSMODE 0x30 |
1583 | mask BIOSDISABLED 0x30 | 1705 | mask BIOSDISABLED 0x30 |
1584 | field CHANNEL_B_PRIMARY 0x08 | 1706 | field CHANNEL_B_PRIMARY 0x08 |
1707 | dont_generate_debug_code | ||
1585 | } | 1708 | } |
1586 | } | 1709 | } |
1587 | 1710 | ||
@@ -1595,6 +1718,7 @@ scratch_ram { | |||
1595 | TARG_OFFSET { | 1718 | TARG_OFFSET { |
1596 | size 16 | 1719 | size 16 |
1597 | count 1 | 1720 | count 1 |
1721 | dont_generate_debug_code | ||
1598 | } | 1722 | } |
1599 | } | 1723 | } |
1600 | 1724 | ||
diff --git a/drivers/scsi/aic7xxx/aic7xxx_core.c b/drivers/scsi/aic7xxx/aic7xxx_core.c index 0ae2b4605d09..e6f2bb7365e6 100644 --- a/drivers/scsi/aic7xxx/aic7xxx_core.c +++ b/drivers/scsi/aic7xxx/aic7xxx_core.c | |||
@@ -814,6 +814,7 @@ ahc_intr(struct ahc_softc *ahc) | |||
814 | static void | 814 | static void |
815 | ahc_restart(struct ahc_softc *ahc) | 815 | ahc_restart(struct ahc_softc *ahc) |
816 | { | 816 | { |
817 | uint8_t sblkctl; | ||
817 | 818 | ||
818 | ahc_pause(ahc); | 819 | ahc_pause(ahc); |
819 | 820 | ||
@@ -868,6 +869,12 @@ ahc_restart(struct ahc_softc *ahc) | |||
868 | ahc_outb(ahc, SEQADDR0, 0); | 869 | ahc_outb(ahc, SEQADDR0, 0); |
869 | ahc_outb(ahc, SEQADDR1, 0); | 870 | ahc_outb(ahc, SEQADDR1, 0); |
870 | 871 | ||
872 | /* | ||
873 | * Take the LED out of diagnostic mode on PM resume, too | ||
874 | */ | ||
875 | sblkctl = ahc_inb(ahc, SBLKCTL); | ||
876 | ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); | ||
877 | |||
871 | ahc_unpause(ahc); | 878 | ahc_unpause(ahc); |
872 | } | 879 | } |
873 | 880 | ||
diff --git a/drivers/scsi/aic7xxx/aic7xxx_reg.h_shipped b/drivers/scsi/aic7xxx/aic7xxx_reg.h_shipped index 2ce1febca207..e821082a4f47 100644 --- a/drivers/scsi/aic7xxx/aic7xxx_reg.h_shipped +++ b/drivers/scsi/aic7xxx/aic7xxx_reg.h_shipped | |||
@@ -27,20 +27,6 @@ ahc_reg_print_t ahc_sxfrctl0_print; | |||
27 | #endif | 27 | #endif |
28 | 28 | ||
29 | #if AIC_DEBUG_REGISTERS | 29 | #if AIC_DEBUG_REGISTERS |
30 | ahc_reg_print_t ahc_sxfrctl1_print; | ||
31 | #else | ||
32 | #define ahc_sxfrctl1_print(regvalue, cur_col, wrap) \ | ||
33 | ahc_print_register(NULL, 0, "SXFRCTL1", 0x02, regvalue, cur_col, wrap) | ||
34 | #endif | ||
35 | |||
36 | #if AIC_DEBUG_REGISTERS | ||
37 | ahc_reg_print_t ahc_scsisigo_print; | ||
38 | #else | ||
39 | #define ahc_scsisigo_print(regvalue, cur_col, wrap) \ | ||
40 | ahc_print_register(NULL, 0, "SCSISIGO", 0x03, regvalue, cur_col, wrap) | ||
41 | #endif | ||
42 | |||
43 | #if AIC_DEBUG_REGISTERS | ||
44 | ahc_reg_print_t ahc_scsisigi_print; | 30 | ahc_reg_print_t ahc_scsisigi_print; |
45 | #else | 31 | #else |
46 | #define ahc_scsisigi_print(regvalue, cur_col, wrap) \ | 32 | #define ahc_scsisigi_print(regvalue, cur_col, wrap) \ |
@@ -55,55 +41,6 @@ ahc_reg_print_t ahc_scsirate_print; | |||
55 | #endif | 41 | #endif |
56 | 42 | ||
57 | #if AIC_DEBUG_REGISTERS | 43 | #if AIC_DEBUG_REGISTERS |
58 | ahc_reg_print_t ahc_scsiid_print; | ||
59 | #else | ||
60 | #define ahc_scsiid_print(regvalue, cur_col, wrap) \ | ||
61 | ahc_print_register(NULL, 0, "SCSIID", 0x05, regvalue, cur_col, wrap) | ||
62 | #endif | ||
63 | |||
64 | #if AIC_DEBUG_REGISTERS | ||
65 | ahc_reg_print_t ahc_scsidatl_print; | ||
66 | #else | ||
67 | #define ahc_scsidatl_print(regvalue, cur_col, wrap) \ | ||
68 | ahc_print_register(NULL, 0, "SCSIDATL", 0x06, regvalue, cur_col, wrap) | ||
69 | #endif | ||
70 | |||
71 | #if AIC_DEBUG_REGISTERS | ||
72 | ahc_reg_print_t ahc_scsidath_print; | ||
73 | #else | ||
74 | #define ahc_scsidath_print(regvalue, cur_col, wrap) \ | ||
75 | ahc_print_register(NULL, 0, "SCSIDATH", 0x07, regvalue, cur_col, wrap) | ||
76 | #endif | ||
77 | |||
78 | #if AIC_DEBUG_REGISTERS | ||
79 | ahc_reg_print_t ahc_stcnt_print; | ||
80 | #else | ||
81 | #define ahc_stcnt_print(regvalue, cur_col, wrap) \ | ||
82 | ahc_print_register(NULL, 0, "STCNT", 0x08, regvalue, cur_col, wrap) | ||
83 | #endif | ||
84 | |||
85 | #if AIC_DEBUG_REGISTERS | ||
86 | ahc_reg_print_t ahc_optionmode_print; | ||
87 | #else | ||
88 | #define ahc_optionmode_print(regvalue, cur_col, wrap) \ | ||
89 | ahc_print_register(NULL, 0, "OPTIONMODE", 0x08, regvalue, cur_col, wrap) | ||
90 | #endif | ||
91 | |||
92 | #if AIC_DEBUG_REGISTERS | ||
93 | ahc_reg_print_t ahc_targcrccnt_print; | ||
94 | #else | ||
95 | #define ahc_targcrccnt_print(regvalue, cur_col, wrap) \ | ||
96 | ahc_print_register(NULL, 0, "TARGCRCCNT", 0x0a, regvalue, cur_col, wrap) | ||
97 | #endif | ||
98 | |||
99 | #if AIC_DEBUG_REGISTERS | ||
100 | ahc_reg_print_t ahc_clrsint0_print; | ||
101 | #else | ||
102 | #define ahc_clrsint0_print(regvalue, cur_col, wrap) \ | ||
103 | ahc_print_register(NULL, 0, "CLRSINT0", 0x0b, regvalue, cur_col, wrap) | ||
104 | #endif | ||
105 | |||
106 | #if AIC_DEBUG_REGISTERS | ||
107 | ahc_reg_print_t ahc_sstat0_print; | 44 | ahc_reg_print_t ahc_sstat0_print; |
108 | #else | 45 | #else |
109 | #define ahc_sstat0_print(regvalue, cur_col, wrap) \ | 46 | #define ahc_sstat0_print(regvalue, cur_col, wrap) \ |
@@ -111,13 +48,6 @@ ahc_reg_print_t ahc_sstat0_print; | |||
111 | #endif | 48 | #endif |
112 | 49 | ||
113 | #if AIC_DEBUG_REGISTERS | 50 | #if AIC_DEBUG_REGISTERS |
114 | ahc_reg_print_t ahc_clrsint1_print; | ||
115 | #else | ||
116 | #define ahc_clrsint1_print(regvalue, cur_col, wrap) \ | ||
117 | ahc_print_register(NULL, 0, "CLRSINT1", 0x0c, regvalue, cur_col, wrap) | ||
118 | #endif | ||
119 | |||
120 | #if AIC_DEBUG_REGISTERS | ||
121 | ahc_reg_print_t ahc_sstat1_print; | 51 | ahc_reg_print_t ahc_sstat1_print; |
122 | #else | 52 | #else |
123 | #define ahc_sstat1_print(regvalue, cur_col, wrap) \ | 53 | #define ahc_sstat1_print(regvalue, cur_col, wrap) \ |
@@ -139,13 +69,6 @@ ahc_reg_print_t ahc_sstat3_print; | |||
139 | #endif | 69 | #endif |
140 | 70 | ||
141 | #if AIC_DEBUG_REGISTERS | 71 | #if AIC_DEBUG_REGISTERS |
142 | ahc_reg_print_t ahc_scsiid_ultra2_print; | ||
143 | #else | ||
144 | #define ahc_scsiid_ultra2_print(regvalue, cur_col, wrap) \ | ||
145 | ahc_print_register(NULL, 0, "SCSIID_ULTRA2", 0x0f, regvalue, cur_col, wrap) | ||
146 | #endif | ||
147 | |||
148 | #if AIC_DEBUG_REGISTERS | ||
149 | ahc_reg_print_t ahc_simode0_print; | 72 | ahc_reg_print_t ahc_simode0_print; |
150 | #else | 73 | #else |
151 | #define ahc_simode0_print(regvalue, cur_col, wrap) \ | 74 | #define ahc_simode0_print(regvalue, cur_col, wrap) \ |
@@ -167,76 +90,6 @@ ahc_reg_print_t ahc_scsibusl_print; | |||
167 | #endif | 90 | #endif |
168 | 91 | ||
169 | #if AIC_DEBUG_REGISTERS | 92 | #if AIC_DEBUG_REGISTERS |
170 | ahc_reg_print_t ahc_scsibush_print; | ||
171 | #else | ||
172 | #define ahc_scsibush_print(regvalue, cur_col, wrap) \ | ||
173 | ahc_print_register(NULL, 0, "SCSIBUSH", 0x13, regvalue, cur_col, wrap) | ||
174 | #endif | ||
175 | |||
176 | #if AIC_DEBUG_REGISTERS | ||
177 | ahc_reg_print_t ahc_sxfrctl2_print; | ||
178 | #else | ||
179 | #define ahc_sxfrctl2_print(regvalue, cur_col, wrap) \ | ||
180 | ahc_print_register(NULL, 0, "SXFRCTL2", 0x13, regvalue, cur_col, wrap) | ||
181 | #endif | ||
182 | |||
183 | #if AIC_DEBUG_REGISTERS | ||
184 | ahc_reg_print_t ahc_shaddr_print; | ||
185 | #else | ||
186 | #define ahc_shaddr_print(regvalue, cur_col, wrap) \ | ||
187 | ahc_print_register(NULL, 0, "SHADDR", 0x14, regvalue, cur_col, wrap) | ||
188 | #endif | ||
189 | |||
190 | #if AIC_DEBUG_REGISTERS | ||
191 | ahc_reg_print_t ahc_seltimer_print; | ||
192 | #else | ||
193 | #define ahc_seltimer_print(regvalue, cur_col, wrap) \ | ||
194 | ahc_print_register(NULL, 0, "SELTIMER", 0x18, regvalue, cur_col, wrap) | ||
195 | #endif | ||
196 | |||
197 | #if AIC_DEBUG_REGISTERS | ||
198 | ahc_reg_print_t ahc_selid_print; | ||
199 | #else | ||
200 | #define ahc_selid_print(regvalue, cur_col, wrap) \ | ||
201 | ahc_print_register(NULL, 0, "SELID", 0x19, regvalue, cur_col, wrap) | ||
202 | #endif | ||
203 | |||
204 | #if AIC_DEBUG_REGISTERS | ||
205 | ahc_reg_print_t ahc_scamctl_print; | ||
206 | #else | ||
207 | #define ahc_scamctl_print(regvalue, cur_col, wrap) \ | ||
208 | ahc_print_register(NULL, 0, "SCAMCTL", 0x1a, regvalue, cur_col, wrap) | ||
209 | #endif | ||
210 | |||
211 | #if AIC_DEBUG_REGISTERS | ||
212 | ahc_reg_print_t ahc_targid_print; | ||
213 | #else | ||
214 | #define ahc_targid_print(regvalue, cur_col, wrap) \ | ||
215 | ahc_print_register(NULL, 0, "TARGID", 0x1b, regvalue, cur_col, wrap) | ||
216 | #endif | ||
217 | |||
218 | #if AIC_DEBUG_REGISTERS | ||
219 | ahc_reg_print_t ahc_spiocap_print; | ||
220 | #else | ||
221 | #define ahc_spiocap_print(regvalue, cur_col, wrap) \ | ||
222 | ahc_print_register(NULL, 0, "SPIOCAP", 0x1b, regvalue, cur_col, wrap) | ||
223 | #endif | ||
224 | |||
225 | #if AIC_DEBUG_REGISTERS | ||
226 | ahc_reg_print_t ahc_brdctl_print; | ||
227 | #else | ||
228 | #define ahc_brdctl_print(regvalue, cur_col, wrap) \ | ||
229 | ahc_print_register(NULL, 0, "BRDCTL", 0x1d, regvalue, cur_col, wrap) | ||
230 | #endif | ||
231 | |||
232 | #if AIC_DEBUG_REGISTERS | ||
233 | ahc_reg_print_t ahc_seectl_print; | ||
234 | #else | ||
235 | #define ahc_seectl_print(regvalue, cur_col, wrap) \ | ||
236 | ahc_print_register(NULL, 0, "SEECTL", 0x1e, regvalue, cur_col, wrap) | ||
237 | #endif | ||
238 | |||
239 | #if AIC_DEBUG_REGISTERS | ||
240 | ahc_reg_print_t ahc_sblkctl_print; | 93 | ahc_reg_print_t ahc_sblkctl_print; |
241 | #else | 94 | #else |
242 | #define ahc_sblkctl_print(regvalue, cur_col, wrap) \ | 95 | #define ahc_sblkctl_print(regvalue, cur_col, wrap) \ |
@@ -244,62 +97,6 @@ ahc_reg_print_t ahc_sblkctl_print; | |||
244 | #endif | 97 | #endif |
245 | 98 | ||
246 | #if AIC_DEBUG_REGISTERS | 99 | #if AIC_DEBUG_REGISTERS |
247 | ahc_reg_print_t ahc_busy_targets_print; | ||
248 | #else | ||
249 | #define ahc_busy_targets_print(regvalue, cur_col, wrap) \ | ||
250 | ahc_print_register(NULL, 0, "BUSY_TARGETS", 0x20, regvalue, cur_col, wrap) | ||
251 | #endif | ||
252 | |||
253 | #if AIC_DEBUG_REGISTERS | ||
254 | ahc_reg_print_t ahc_ultra_enb_print; | ||
255 | #else | ||
256 | #define ahc_ultra_enb_print(regvalue, cur_col, wrap) \ | ||
257 | ahc_print_register(NULL, 0, "ULTRA_ENB", 0x30, regvalue, cur_col, wrap) | ||
258 | #endif | ||
259 | |||
260 | #if AIC_DEBUG_REGISTERS | ||
261 | ahc_reg_print_t ahc_disc_dsb_print; | ||
262 | #else | ||
263 | #define ahc_disc_dsb_print(regvalue, cur_col, wrap) \ | ||
264 | ahc_print_register(NULL, 0, "DISC_DSB", 0x32, regvalue, cur_col, wrap) | ||
265 | #endif | ||
266 | |||
267 | #if AIC_DEBUG_REGISTERS | ||
268 | ahc_reg_print_t ahc_cmdsize_table_tail_print; | ||
269 | #else | ||
270 | #define ahc_cmdsize_table_tail_print(regvalue, cur_col, wrap) \ | ||
271 | ahc_print_register(NULL, 0, "CMDSIZE_TABLE_TAIL", 0x34, regvalue, cur_col, wrap) | ||
272 | #endif | ||
273 | |||
274 | #if AIC_DEBUG_REGISTERS | ||
275 | ahc_reg_print_t ahc_mwi_residual_print; | ||
276 | #else | ||
277 | #define ahc_mwi_residual_print(regvalue, cur_col, wrap) \ | ||
278 | ahc_print_register(NULL, 0, "MWI_RESIDUAL", 0x38, regvalue, cur_col, wrap) | ||
279 | #endif | ||
280 | |||
281 | #if AIC_DEBUG_REGISTERS | ||
282 | ahc_reg_print_t ahc_next_queued_scb_print; | ||
283 | #else | ||
284 | #define ahc_next_queued_scb_print(regvalue, cur_col, wrap) \ | ||
285 | ahc_print_register(NULL, 0, "NEXT_QUEUED_SCB", 0x39, regvalue, cur_col, wrap) | ||
286 | #endif | ||
287 | |||
288 | #if AIC_DEBUG_REGISTERS | ||
289 | ahc_reg_print_t ahc_msg_out_print; | ||
290 | #else | ||
291 | #define ahc_msg_out_print(regvalue, cur_col, wrap) \ | ||
292 | ahc_print_register(NULL, 0, "MSG_OUT", 0x3a, regvalue, cur_col, wrap) | ||
293 | #endif | ||
294 | |||
295 | #if AIC_DEBUG_REGISTERS | ||
296 | ahc_reg_print_t ahc_dmaparams_print; | ||
297 | #else | ||
298 | #define ahc_dmaparams_print(regvalue, cur_col, wrap) \ | ||
299 | ahc_print_register(NULL, 0, "DMAPARAMS", 0x3b, regvalue, cur_col, wrap) | ||
300 | #endif | ||
301 | |||
302 | #if AIC_DEBUG_REGISTERS | ||
303 | ahc_reg_print_t ahc_seq_flags_print; | 100 | ahc_reg_print_t ahc_seq_flags_print; |
304 | #else | 101 | #else |
305 | #define ahc_seq_flags_print(regvalue, cur_col, wrap) \ | 102 | #define ahc_seq_flags_print(regvalue, cur_col, wrap) \ |
@@ -307,20 +104,6 @@ ahc_reg_print_t ahc_seq_flags_print; | |||
307 | #endif | 104 | #endif |
308 | 105 | ||
309 | #if AIC_DEBUG_REGISTERS | 106 | #if AIC_DEBUG_REGISTERS |
310 | ahc_reg_print_t ahc_saved_scsiid_print; | ||
311 | #else | ||
312 | #define ahc_saved_scsiid_print(regvalue, cur_col, wrap) \ | ||
313 | ahc_print_register(NULL, 0, "SAVED_SCSIID", 0x3d, regvalue, cur_col, wrap) | ||
314 | #endif | ||
315 | |||
316 | #if AIC_DEBUG_REGISTERS | ||
317 | ahc_reg_print_t ahc_saved_lun_print; | ||
318 | #else | ||
319 | #define ahc_saved_lun_print(regvalue, cur_col, wrap) \ | ||
320 | ahc_print_register(NULL, 0, "SAVED_LUN", 0x3e, regvalue, cur_col, wrap) | ||
321 | #endif | ||
322 | |||
323 | #if AIC_DEBUG_REGISTERS | ||
324 | ahc_reg_print_t ahc_lastphase_print; | 107 | ahc_reg_print_t ahc_lastphase_print; |
325 | #else | 108 | #else |
326 | #define ahc_lastphase_print(regvalue, cur_col, wrap) \ | 109 | #define ahc_lastphase_print(regvalue, cur_col, wrap) \ |
@@ -328,153 +111,6 @@ ahc_reg_print_t ahc_lastphase_print; | |||
328 | #endif | 111 | #endif |
329 | 112 | ||
330 | #if AIC_DEBUG_REGISTERS | 113 | #if AIC_DEBUG_REGISTERS |
331 | ahc_reg_print_t ahc_waiting_scbh_print; | ||
332 | #else | ||
333 | #define ahc_waiting_scbh_print(regvalue, cur_col, wrap) \ | ||
334 | ahc_print_register(NULL, 0, "WAITING_SCBH", 0x40, regvalue, cur_col, wrap) | ||
335 | #endif | ||
336 | |||
337 | #if AIC_DEBUG_REGISTERS | ||
338 | ahc_reg_print_t ahc_disconnected_scbh_print; | ||
339 | #else | ||
340 | #define ahc_disconnected_scbh_print(regvalue, cur_col, wrap) \ | ||
341 | ahc_print_register(NULL, 0, "DISCONNECTED_SCBH", 0x41, regvalue, cur_col, wrap) | ||
342 | #endif | ||
343 | |||
344 | #if AIC_DEBUG_REGISTERS | ||
345 | ahc_reg_print_t ahc_free_scbh_print; | ||
346 | #else | ||
347 | #define ahc_free_scbh_print(regvalue, cur_col, wrap) \ | ||
348 | ahc_print_register(NULL, 0, "FREE_SCBH", 0x42, regvalue, cur_col, wrap) | ||
349 | #endif | ||
350 | |||
351 | #if AIC_DEBUG_REGISTERS | ||
352 | ahc_reg_print_t ahc_complete_scbh_print; | ||
353 | #else | ||
354 | #define ahc_complete_scbh_print(regvalue, cur_col, wrap) \ | ||
355 | ahc_print_register(NULL, 0, "COMPLETE_SCBH", 0x43, regvalue, cur_col, wrap) | ||
356 | #endif | ||
357 | |||
358 | #if AIC_DEBUG_REGISTERS | ||
359 | ahc_reg_print_t ahc_hscb_addr_print; | ||
360 | #else | ||
361 | #define ahc_hscb_addr_print(regvalue, cur_col, wrap) \ | ||
362 | ahc_print_register(NULL, 0, "HSCB_ADDR", 0x44, regvalue, cur_col, wrap) | ||
363 | #endif | ||
364 | |||
365 | #if AIC_DEBUG_REGISTERS | ||
366 | ahc_reg_print_t ahc_shared_data_addr_print; | ||
367 | #else | ||
368 | #define ahc_shared_data_addr_print(regvalue, cur_col, wrap) \ | ||
369 | ahc_print_register(NULL, 0, "SHARED_DATA_ADDR", 0x48, regvalue, cur_col, wrap) | ||
370 | #endif | ||
371 | |||
372 | #if AIC_DEBUG_REGISTERS | ||
373 | ahc_reg_print_t ahc_kernel_qinpos_print; | ||
374 | #else | ||
375 | #define ahc_kernel_qinpos_print(regvalue, cur_col, wrap) \ | ||
376 | ahc_print_register(NULL, 0, "KERNEL_QINPOS", 0x4c, regvalue, cur_col, wrap) | ||
377 | #endif | ||
378 | |||
379 | #if AIC_DEBUG_REGISTERS | ||
380 | ahc_reg_print_t ahc_qinpos_print; | ||
381 | #else | ||
382 | #define ahc_qinpos_print(regvalue, cur_col, wrap) \ | ||
383 | ahc_print_register(NULL, 0, "QINPOS", 0x4d, regvalue, cur_col, wrap) | ||
384 | #endif | ||
385 | |||
386 | #if AIC_DEBUG_REGISTERS | ||
387 | ahc_reg_print_t ahc_qoutpos_print; | ||
388 | #else | ||
389 | #define ahc_qoutpos_print(regvalue, cur_col, wrap) \ | ||
390 | ahc_print_register(NULL, 0, "QOUTPOS", 0x4e, regvalue, cur_col, wrap) | ||
391 | #endif | ||
392 | |||
393 | #if AIC_DEBUG_REGISTERS | ||
394 | ahc_reg_print_t ahc_kernel_tqinpos_print; | ||
395 | #else | ||
396 | #define ahc_kernel_tqinpos_print(regvalue, cur_col, wrap) \ | ||
397 | ahc_print_register(NULL, 0, "KERNEL_TQINPOS", 0x4f, regvalue, cur_col, wrap) | ||
398 | #endif | ||
399 | |||
400 | #if AIC_DEBUG_REGISTERS | ||
401 | ahc_reg_print_t ahc_tqinpos_print; | ||
402 | #else | ||
403 | #define ahc_tqinpos_print(regvalue, cur_col, wrap) \ | ||
404 | ahc_print_register(NULL, 0, "TQINPOS", 0x50, regvalue, cur_col, wrap) | ||
405 | #endif | ||
406 | |||
407 | #if AIC_DEBUG_REGISTERS | ||
408 | ahc_reg_print_t ahc_arg_1_print; | ||
409 | #else | ||
410 | #define ahc_arg_1_print(regvalue, cur_col, wrap) \ | ||
411 | ahc_print_register(NULL, 0, "ARG_1", 0x51, regvalue, cur_col, wrap) | ||
412 | #endif | ||
413 | |||
414 | #if AIC_DEBUG_REGISTERS | ||
415 | ahc_reg_print_t ahc_arg_2_print; | ||
416 | #else | ||
417 | #define ahc_arg_2_print(regvalue, cur_col, wrap) \ | ||
418 | ahc_print_register(NULL, 0, "ARG_2", 0x52, regvalue, cur_col, wrap) | ||
419 | #endif | ||
420 | |||
421 | #if AIC_DEBUG_REGISTERS | ||
422 | ahc_reg_print_t ahc_last_msg_print; | ||
423 | #else | ||
424 | #define ahc_last_msg_print(regvalue, cur_col, wrap) \ | ||
425 | ahc_print_register(NULL, 0, "LAST_MSG", 0x53, regvalue, cur_col, wrap) | ||
426 | #endif | ||
427 | |||
428 | #if AIC_DEBUG_REGISTERS | ||
429 | ahc_reg_print_t ahc_scsiseq_template_print; | ||
430 | #else | ||
431 | #define ahc_scsiseq_template_print(regvalue, cur_col, wrap) \ | ||
432 | ahc_print_register(NULL, 0, "SCSISEQ_TEMPLATE", 0x54, regvalue, cur_col, wrap) | ||
433 | #endif | ||
434 | |||
435 | #if AIC_DEBUG_REGISTERS | ||
436 | ahc_reg_print_t ahc_ha_274_biosglobal_print; | ||
437 | #else | ||
438 | #define ahc_ha_274_biosglobal_print(regvalue, cur_col, wrap) \ | ||
439 | ahc_print_register(NULL, 0, "HA_274_BIOSGLOBAL", 0x56, regvalue, cur_col, wrap) | ||
440 | #endif | ||
441 | |||
442 | #if AIC_DEBUG_REGISTERS | ||
443 | ahc_reg_print_t ahc_seq_flags2_print; | ||
444 | #else | ||
445 | #define ahc_seq_flags2_print(regvalue, cur_col, wrap) \ | ||
446 | ahc_print_register(NULL, 0, "SEQ_FLAGS2", 0x57, regvalue, cur_col, wrap) | ||
447 | #endif | ||
448 | |||
449 | #if AIC_DEBUG_REGISTERS | ||
450 | ahc_reg_print_t ahc_scsiconf_print; | ||
451 | #else | ||
452 | #define ahc_scsiconf_print(regvalue, cur_col, wrap) \ | ||
453 | ahc_print_register(NULL, 0, "SCSICONF", 0x5a, regvalue, cur_col, wrap) | ||
454 | #endif | ||
455 | |||
456 | #if AIC_DEBUG_REGISTERS | ||
457 | ahc_reg_print_t ahc_intdef_print; | ||
458 | #else | ||
459 | #define ahc_intdef_print(regvalue, cur_col, wrap) \ | ||
460 | ahc_print_register(NULL, 0, "INTDEF", 0x5c, regvalue, cur_col, wrap) | ||
461 | #endif | ||
462 | |||
463 | #if AIC_DEBUG_REGISTERS | ||
464 | ahc_reg_print_t ahc_hostconf_print; | ||
465 | #else | ||
466 | #define ahc_hostconf_print(regvalue, cur_col, wrap) \ | ||
467 | ahc_print_register(NULL, 0, "HOSTCONF", 0x5d, regvalue, cur_col, wrap) | ||
468 | #endif | ||
469 | |||
470 | #if AIC_DEBUG_REGISTERS | ||
471 | ahc_reg_print_t ahc_ha_274_biosctrl_print; | ||
472 | #else | ||
473 | #define ahc_ha_274_biosctrl_print(regvalue, cur_col, wrap) \ | ||
474 | ahc_print_register(NULL, 0, "HA_274_BIOSCTRL", 0x5f, regvalue, cur_col, wrap) | ||
475 | #endif | ||
476 | |||
477 | #if AIC_DEBUG_REGISTERS | ||
478 | ahc_reg_print_t ahc_seqctl_print; | 114 | ahc_reg_print_t ahc_seqctl_print; |
479 | #else | 115 | #else |
480 | #define ahc_seqctl_print(regvalue, cur_col, wrap) \ | 116 | #define ahc_seqctl_print(regvalue, cur_col, wrap) \ |
@@ -482,111 +118,6 @@ ahc_reg_print_t ahc_seqctl_print; | |||
482 | #endif | 118 | #endif |
483 | 119 | ||
484 | #if AIC_DEBUG_REGISTERS | 120 | #if AIC_DEBUG_REGISTERS |
485 | ahc_reg_print_t ahc_seqram_print; | ||
486 | #else | ||
487 | #define ahc_seqram_print(regvalue, cur_col, wrap) \ | ||
488 | ahc_print_register(NULL, 0, "SEQRAM", 0x61, regvalue, cur_col, wrap) | ||
489 | #endif | ||
490 | |||
491 | #if AIC_DEBUG_REGISTERS | ||
492 | ahc_reg_print_t ahc_seqaddr0_print; | ||
493 | #else | ||
494 | #define ahc_seqaddr0_print(regvalue, cur_col, wrap) \ | ||
495 | ahc_print_register(NULL, 0, "SEQADDR0", 0x62, regvalue, cur_col, wrap) | ||
496 | #endif | ||
497 | |||
498 | #if AIC_DEBUG_REGISTERS | ||
499 | ahc_reg_print_t ahc_seqaddr1_print; | ||
500 | #else | ||
501 | #define ahc_seqaddr1_print(regvalue, cur_col, wrap) \ | ||
502 | ahc_print_register(NULL, 0, "SEQADDR1", 0x63, regvalue, cur_col, wrap) | ||
503 | #endif | ||
504 | |||
505 | #if AIC_DEBUG_REGISTERS | ||
506 | ahc_reg_print_t ahc_accum_print; | ||
507 | #else | ||
508 | #define ahc_accum_print(regvalue, cur_col, wrap) \ | ||
509 | ahc_print_register(NULL, 0, "ACCUM", 0x64, regvalue, cur_col, wrap) | ||
510 | #endif | ||
511 | |||
512 | #if AIC_DEBUG_REGISTERS | ||
513 | ahc_reg_print_t ahc_sindex_print; | ||
514 | #else | ||
515 | #define ahc_sindex_print(regvalue, cur_col, wrap) \ | ||
516 | ahc_print_register(NULL, 0, "SINDEX", 0x65, regvalue, cur_col, wrap) | ||
517 | #endif | ||
518 | |||
519 | #if AIC_DEBUG_REGISTERS | ||
520 | ahc_reg_print_t ahc_dindex_print; | ||
521 | #else | ||
522 | #define ahc_dindex_print(regvalue, cur_col, wrap) \ | ||
523 | ahc_print_register(NULL, 0, "DINDEX", 0x66, regvalue, cur_col, wrap) | ||
524 | #endif | ||
525 | |||
526 | #if AIC_DEBUG_REGISTERS | ||
527 | ahc_reg_print_t ahc_allones_print; | ||
528 | #else | ||
529 | #define ahc_allones_print(regvalue, cur_col, wrap) \ | ||
530 | ahc_print_register(NULL, 0, "ALLONES", 0x69, regvalue, cur_col, wrap) | ||
531 | #endif | ||
532 | |||
533 | #if AIC_DEBUG_REGISTERS | ||
534 | ahc_reg_print_t ahc_allzeros_print; | ||
535 | #else | ||
536 | #define ahc_allzeros_print(regvalue, cur_col, wrap) \ | ||
537 | ahc_print_register(NULL, 0, "ALLZEROS", 0x6a, regvalue, cur_col, wrap) | ||
538 | #endif | ||
539 | |||
540 | #if AIC_DEBUG_REGISTERS | ||
541 | ahc_reg_print_t ahc_none_print; | ||
542 | #else | ||
543 | #define ahc_none_print(regvalue, cur_col, wrap) \ | ||
544 | ahc_print_register(NULL, 0, "NONE", 0x6a, regvalue, cur_col, wrap) | ||
545 | #endif | ||
546 | |||
547 | #if AIC_DEBUG_REGISTERS | ||
548 | ahc_reg_print_t ahc_flags_print; | ||
549 | #else | ||
550 | #define ahc_flags_print(regvalue, cur_col, wrap) \ | ||
551 | ahc_print_register(NULL, 0, "FLAGS", 0x6b, regvalue, cur_col, wrap) | ||
552 | #endif | ||
553 | |||
554 | #if AIC_DEBUG_REGISTERS | ||
555 | ahc_reg_print_t ahc_sindir_print; | ||
556 | #else | ||
557 | #define ahc_sindir_print(regvalue, cur_col, wrap) \ | ||
558 | ahc_print_register(NULL, 0, "SINDIR", 0x6c, regvalue, cur_col, wrap) | ||
559 | #endif | ||
560 | |||
561 | #if AIC_DEBUG_REGISTERS | ||
562 | ahc_reg_print_t ahc_dindir_print; | ||
563 | #else | ||
564 | #define ahc_dindir_print(regvalue, cur_col, wrap) \ | ||
565 | ahc_print_register(NULL, 0, "DINDIR", 0x6d, regvalue, cur_col, wrap) | ||
566 | #endif | ||
567 | |||
568 | #if AIC_DEBUG_REGISTERS | ||
569 | ahc_reg_print_t ahc_function1_print; | ||
570 | #else | ||
571 | #define ahc_function1_print(regvalue, cur_col, wrap) \ | ||
572 | ahc_print_register(NULL, 0, "FUNCTION1", 0x6e, regvalue, cur_col, wrap) | ||
573 | #endif | ||
574 | |||
575 | #if AIC_DEBUG_REGISTERS | ||
576 | ahc_reg_print_t ahc_stack_print; | ||
577 | #else | ||
578 | #define ahc_stack_print(regvalue, cur_col, wrap) \ | ||
579 | ahc_print_register(NULL, 0, "STACK", 0x6f, regvalue, cur_col, wrap) | ||
580 | #endif | ||
581 | |||
582 | #if AIC_DEBUG_REGISTERS | ||
583 | ahc_reg_print_t ahc_targ_offset_print; | ||
584 | #else | ||
585 | #define ahc_targ_offset_print(regvalue, cur_col, wrap) \ | ||
586 | ahc_print_register(NULL, 0, "TARG_OFFSET", 0x70, regvalue, cur_col, wrap) | ||
587 | #endif | ||
588 | |||
589 | #if AIC_DEBUG_REGISTERS | ||
590 | ahc_reg_print_t ahc_sram_base_print; | 121 | ahc_reg_print_t ahc_sram_base_print; |
591 | #else | 122 | #else |
592 | #define ahc_sram_base_print(regvalue, cur_col, wrap) \ | 123 | #define ahc_sram_base_print(regvalue, cur_col, wrap) \ |
@@ -594,97 +125,6 @@ ahc_reg_print_t ahc_sram_base_print; | |||
594 | #endif | 125 | #endif |
595 | 126 | ||
596 | #if AIC_DEBUG_REGISTERS | 127 | #if AIC_DEBUG_REGISTERS |
597 | ahc_reg_print_t ahc_bctl_print; | ||
598 | #else | ||
599 | #define ahc_bctl_print(regvalue, cur_col, wrap) \ | ||
600 | ahc_print_register(NULL, 0, "BCTL", 0x84, regvalue, cur_col, wrap) | ||
601 | #endif | ||
602 | |||
603 | #if AIC_DEBUG_REGISTERS | ||
604 | ahc_reg_print_t ahc_dscommand0_print; | ||
605 | #else | ||
606 | #define ahc_dscommand0_print(regvalue, cur_col, wrap) \ | ||
607 | ahc_print_register(NULL, 0, "DSCOMMAND0", 0x84, regvalue, cur_col, wrap) | ||
608 | #endif | ||
609 | |||
610 | #if AIC_DEBUG_REGISTERS | ||
611 | ahc_reg_print_t ahc_bustime_print; | ||
612 | #else | ||
613 | #define ahc_bustime_print(regvalue, cur_col, wrap) \ | ||
614 | ahc_print_register(NULL, 0, "BUSTIME", 0x85, regvalue, cur_col, wrap) | ||
615 | #endif | ||
616 | |||
617 | #if AIC_DEBUG_REGISTERS | ||
618 | ahc_reg_print_t ahc_dscommand1_print; | ||
619 | #else | ||
620 | #define ahc_dscommand1_print(regvalue, cur_col, wrap) \ | ||
621 | ahc_print_register(NULL, 0, "DSCOMMAND1", 0x85, regvalue, cur_col, wrap) | ||
622 | #endif | ||
623 | |||
624 | #if AIC_DEBUG_REGISTERS | ||
625 | ahc_reg_print_t ahc_busspd_print; | ||
626 | #else | ||
627 | #define ahc_busspd_print(regvalue, cur_col, wrap) \ | ||
628 | ahc_print_register(NULL, 0, "BUSSPD", 0x86, regvalue, cur_col, wrap) | ||
629 | #endif | ||
630 | |||
631 | #if AIC_DEBUG_REGISTERS | ||
632 | ahc_reg_print_t ahc_hs_mailbox_print; | ||
633 | #else | ||
634 | #define ahc_hs_mailbox_print(regvalue, cur_col, wrap) \ | ||
635 | ahc_print_register(NULL, 0, "HS_MAILBOX", 0x86, regvalue, cur_col, wrap) | ||
636 | #endif | ||
637 | |||
638 | #if AIC_DEBUG_REGISTERS | ||
639 | ahc_reg_print_t ahc_dspcistatus_print; | ||
640 | #else | ||
641 | #define ahc_dspcistatus_print(regvalue, cur_col, wrap) \ | ||
642 | ahc_print_register(NULL, 0, "DSPCISTATUS", 0x86, regvalue, cur_col, wrap) | ||
643 | #endif | ||
644 | |||
645 | #if AIC_DEBUG_REGISTERS | ||
646 | ahc_reg_print_t ahc_hcntrl_print; | ||
647 | #else | ||
648 | #define ahc_hcntrl_print(regvalue, cur_col, wrap) \ | ||
649 | ahc_print_register(NULL, 0, "HCNTRL", 0x87, regvalue, cur_col, wrap) | ||
650 | #endif | ||
651 | |||
652 | #if AIC_DEBUG_REGISTERS | ||
653 | ahc_reg_print_t ahc_haddr_print; | ||
654 | #else | ||
655 | #define ahc_haddr_print(regvalue, cur_col, wrap) \ | ||
656 | ahc_print_register(NULL, 0, "HADDR", 0x88, regvalue, cur_col, wrap) | ||
657 | #endif | ||
658 | |||
659 | #if AIC_DEBUG_REGISTERS | ||
660 | ahc_reg_print_t ahc_hcnt_print; | ||
661 | #else | ||
662 | #define ahc_hcnt_print(regvalue, cur_col, wrap) \ | ||
663 | ahc_print_register(NULL, 0, "HCNT", 0x8c, regvalue, cur_col, wrap) | ||
664 | #endif | ||
665 | |||
666 | #if AIC_DEBUG_REGISTERS | ||
667 | ahc_reg_print_t ahc_scbptr_print; | ||
668 | #else | ||
669 | #define ahc_scbptr_print(regvalue, cur_col, wrap) \ | ||
670 | ahc_print_register(NULL, 0, "SCBPTR", 0x90, regvalue, cur_col, wrap) | ||
671 | #endif | ||
672 | |||
673 | #if AIC_DEBUG_REGISTERS | ||
674 | ahc_reg_print_t ahc_intstat_print; | ||
675 | #else | ||
676 | #define ahc_intstat_print(regvalue, cur_col, wrap) \ | ||
677 | ahc_print_register(NULL, 0, "INTSTAT", 0x91, regvalue, cur_col, wrap) | ||
678 | #endif | ||
679 | |||
680 | #if AIC_DEBUG_REGISTERS | ||
681 | ahc_reg_print_t ahc_clrint_print; | ||
682 | #else | ||
683 | #define ahc_clrint_print(regvalue, cur_col, wrap) \ | ||
684 | ahc_print_register(NULL, 0, "CLRINT", 0x92, regvalue, cur_col, wrap) | ||
685 | #endif | ||
686 | |||
687 | #if AIC_DEBUG_REGISTERS | ||
688 | ahc_reg_print_t ahc_error_print; | 128 | ahc_reg_print_t ahc_error_print; |
689 | #else | 129 | #else |
690 | #define ahc_error_print(regvalue, cur_col, wrap) \ | 130 | #define ahc_error_print(regvalue, cur_col, wrap) \ |
@@ -706,69 +146,6 @@ ahc_reg_print_t ahc_dfstatus_print; | |||
706 | #endif | 146 | #endif |
707 | 147 | ||
708 | #if AIC_DEBUG_REGISTERS | 148 | #if AIC_DEBUG_REGISTERS |
709 | ahc_reg_print_t ahc_dfwaddr_print; | ||
710 | #else | ||
711 | #define ahc_dfwaddr_print(regvalue, cur_col, wrap) \ | ||
712 | ahc_print_register(NULL, 0, "DFWADDR", 0x95, regvalue, cur_col, wrap) | ||
713 | #endif | ||
714 | |||
715 | #if AIC_DEBUG_REGISTERS | ||
716 | ahc_reg_print_t ahc_dfraddr_print; | ||
717 | #else | ||
718 | #define ahc_dfraddr_print(regvalue, cur_col, wrap) \ | ||
719 | ahc_print_register(NULL, 0, "DFRADDR", 0x97, regvalue, cur_col, wrap) | ||
720 | #endif | ||
721 | |||
722 | #if AIC_DEBUG_REGISTERS | ||
723 | ahc_reg_print_t ahc_dfdat_print; | ||
724 | #else | ||
725 | #define ahc_dfdat_print(regvalue, cur_col, wrap) \ | ||
726 | ahc_print_register(NULL, 0, "DFDAT", 0x99, regvalue, cur_col, wrap) | ||
727 | #endif | ||
728 | |||
729 | #if AIC_DEBUG_REGISTERS | ||
730 | ahc_reg_print_t ahc_scbcnt_print; | ||
731 | #else | ||
732 | #define ahc_scbcnt_print(regvalue, cur_col, wrap) \ | ||
733 | ahc_print_register(NULL, 0, "SCBCNT", 0x9a, regvalue, cur_col, wrap) | ||
734 | #endif | ||
735 | |||
736 | #if AIC_DEBUG_REGISTERS | ||
737 | ahc_reg_print_t ahc_qinfifo_print; | ||
738 | #else | ||
739 | #define ahc_qinfifo_print(regvalue, cur_col, wrap) \ | ||
740 | ahc_print_register(NULL, 0, "QINFIFO", 0x9b, regvalue, cur_col, wrap) | ||
741 | #endif | ||
742 | |||
743 | #if AIC_DEBUG_REGISTERS | ||
744 | ahc_reg_print_t ahc_qincnt_print; | ||
745 | #else | ||
746 | #define ahc_qincnt_print(regvalue, cur_col, wrap) \ | ||
747 | ahc_print_register(NULL, 0, "QINCNT", 0x9c, regvalue, cur_col, wrap) | ||
748 | #endif | ||
749 | |||
750 | #if AIC_DEBUG_REGISTERS | ||
751 | ahc_reg_print_t ahc_qoutfifo_print; | ||
752 | #else | ||
753 | #define ahc_qoutfifo_print(regvalue, cur_col, wrap) \ | ||
754 | ahc_print_register(NULL, 0, "QOUTFIFO", 0x9d, regvalue, cur_col, wrap) | ||
755 | #endif | ||
756 | |||
757 | #if AIC_DEBUG_REGISTERS | ||
758 | ahc_reg_print_t ahc_crccontrol1_print; | ||
759 | #else | ||
760 | #define ahc_crccontrol1_print(regvalue, cur_col, wrap) \ | ||
761 | ahc_print_register(NULL, 0, "CRCCONTROL1", 0x9d, regvalue, cur_col, wrap) | ||
762 | #endif | ||
763 | |||
764 | #if AIC_DEBUG_REGISTERS | ||
765 | ahc_reg_print_t ahc_qoutcnt_print; | ||
766 | #else | ||
767 | #define ahc_qoutcnt_print(regvalue, cur_col, wrap) \ | ||
768 | ahc_print_register(NULL, 0, "QOUTCNT", 0x9e, regvalue, cur_col, wrap) | ||
769 | #endif | ||
770 | |||
771 | #if AIC_DEBUG_REGISTERS | ||
772 | ahc_reg_print_t ahc_scsiphase_print; | 149 | ahc_reg_print_t ahc_scsiphase_print; |
773 | #else | 150 | #else |
774 | #define ahc_scsiphase_print(regvalue, cur_col, wrap) \ | 151 | #define ahc_scsiphase_print(regvalue, cur_col, wrap) \ |
@@ -776,13 +153,6 @@ ahc_reg_print_t ahc_scsiphase_print; | |||
776 | #endif | 153 | #endif |
777 | 154 | ||
778 | #if AIC_DEBUG_REGISTERS | 155 | #if AIC_DEBUG_REGISTERS |
779 | ahc_reg_print_t ahc_sfunct_print; | ||
780 | #else | ||
781 | #define ahc_sfunct_print(regvalue, cur_col, wrap) \ | ||
782 | ahc_print_register(NULL, 0, "SFUNCT", 0x9f, regvalue, cur_col, wrap) | ||
783 | #endif | ||
784 | |||
785 | #if AIC_DEBUG_REGISTERS | ||
786 | ahc_reg_print_t ahc_scb_base_print; | 156 | ahc_reg_print_t ahc_scb_base_print; |
787 | #else | 157 | #else |
788 | #define ahc_scb_base_print(regvalue, cur_col, wrap) \ | 158 | #define ahc_scb_base_print(regvalue, cur_col, wrap) \ |
@@ -790,69 +160,6 @@ ahc_reg_print_t ahc_scb_base_print; | |||
790 | #endif | 160 | #endif |
791 | 161 | ||
792 | #if AIC_DEBUG_REGISTERS | 162 | #if AIC_DEBUG_REGISTERS |
793 | ahc_reg_print_t ahc_scb_cdb_ptr_print; | ||
794 | #else | ||
795 | #define ahc_scb_cdb_ptr_print(regvalue, cur_col, wrap) \ | ||
796 | ahc_print_register(NULL, 0, "SCB_CDB_PTR", 0xa0, regvalue, cur_col, wrap) | ||
797 | #endif | ||
798 | |||
799 | #if AIC_DEBUG_REGISTERS | ||
800 | ahc_reg_print_t ahc_scb_residual_sgptr_print; | ||
801 | #else | ||
802 | #define ahc_scb_residual_sgptr_print(regvalue, cur_col, wrap) \ | ||
803 | ahc_print_register(NULL, 0, "SCB_RESIDUAL_SGPTR", 0xa4, regvalue, cur_col, wrap) | ||
804 | #endif | ||
805 | |||
806 | #if AIC_DEBUG_REGISTERS | ||
807 | ahc_reg_print_t ahc_scb_scsi_status_print; | ||
808 | #else | ||
809 | #define ahc_scb_scsi_status_print(regvalue, cur_col, wrap) \ | ||
810 | ahc_print_register(NULL, 0, "SCB_SCSI_STATUS", 0xa8, regvalue, cur_col, wrap) | ||
811 | #endif | ||
812 | |||
813 | #if AIC_DEBUG_REGISTERS | ||
814 | ahc_reg_print_t ahc_scb_target_phases_print; | ||
815 | #else | ||
816 | #define ahc_scb_target_phases_print(regvalue, cur_col, wrap) \ | ||
817 | ahc_print_register(NULL, 0, "SCB_TARGET_PHASES", 0xa9, regvalue, cur_col, wrap) | ||
818 | #endif | ||
819 | |||
820 | #if AIC_DEBUG_REGISTERS | ||
821 | ahc_reg_print_t ahc_scb_target_data_dir_print; | ||
822 | #else | ||
823 | #define ahc_scb_target_data_dir_print(regvalue, cur_col, wrap) \ | ||
824 | ahc_print_register(NULL, 0, "SCB_TARGET_DATA_DIR", 0xaa, regvalue, cur_col, wrap) | ||
825 | #endif | ||
826 | |||
827 | #if AIC_DEBUG_REGISTERS | ||
828 | ahc_reg_print_t ahc_scb_target_itag_print; | ||
829 | #else | ||
830 | #define ahc_scb_target_itag_print(regvalue, cur_col, wrap) \ | ||
831 | ahc_print_register(NULL, 0, "SCB_TARGET_ITAG", 0xab, regvalue, cur_col, wrap) | ||
832 | #endif | ||
833 | |||
834 | #if AIC_DEBUG_REGISTERS | ||
835 | ahc_reg_print_t ahc_scb_dataptr_print; | ||
836 | #else | ||
837 | #define ahc_scb_dataptr_print(regvalue, cur_col, wrap) \ | ||
838 | ahc_print_register(NULL, 0, "SCB_DATAPTR", 0xac, regvalue, cur_col, wrap) | ||
839 | #endif | ||
840 | |||
841 | #if AIC_DEBUG_REGISTERS | ||
842 | ahc_reg_print_t ahc_scb_datacnt_print; | ||
843 | #else | ||
844 | #define ahc_scb_datacnt_print(regvalue, cur_col, wrap) \ | ||
845 | ahc_print_register(NULL, 0, "SCB_DATACNT", 0xb0, regvalue, cur_col, wrap) | ||
846 | #endif | ||
847 | |||
848 | #if AIC_DEBUG_REGISTERS | ||
849 | ahc_reg_print_t ahc_scb_sgptr_print; | ||
850 | #else | ||
851 | #define ahc_scb_sgptr_print(regvalue, cur_col, wrap) \ | ||
852 | ahc_print_register(NULL, 0, "SCB_SGPTR", 0xb4, regvalue, cur_col, wrap) | ||
853 | #endif | ||
854 | |||
855 | #if AIC_DEBUG_REGISTERS | ||
856 | ahc_reg_print_t ahc_scb_control_print; | 163 | ahc_reg_print_t ahc_scb_control_print; |
857 | #else | 164 | #else |
858 | #define ahc_scb_control_print(regvalue, cur_col, wrap) \ | 165 | #define ahc_scb_control_print(regvalue, cur_col, wrap) \ |
@@ -880,188 +187,6 @@ ahc_reg_print_t ahc_scb_tag_print; | |||
880 | ahc_print_register(NULL, 0, "SCB_TAG", 0xbb, regvalue, cur_col, wrap) | 187 | ahc_print_register(NULL, 0, "SCB_TAG", 0xbb, regvalue, cur_col, wrap) |
881 | #endif | 188 | #endif |
882 | 189 | ||
883 | #if AIC_DEBUG_REGISTERS | ||
884 | ahc_reg_print_t ahc_scb_cdb_len_print; | ||
885 | #else | ||
886 | #define ahc_scb_cdb_len_print(regvalue, cur_col, wrap) \ | ||
887 | ahc_print_register(NULL, 0, "SCB_CDB_LEN", 0xbc, regvalue, cur_col, wrap) | ||
888 | #endif | ||
889 | |||
890 | #if AIC_DEBUG_REGISTERS | ||
891 | ahc_reg_print_t ahc_scb_scsirate_print; | ||
892 | #else | ||
893 | #define ahc_scb_scsirate_print(regvalue, cur_col, wrap) \ | ||
894 | ahc_print_register(NULL, 0, "SCB_SCSIRATE", 0xbd, regvalue, cur_col, wrap) | ||
895 | #endif | ||
896 | |||
897 | #if AIC_DEBUG_REGISTERS | ||
898 | ahc_reg_print_t ahc_scb_scsioffset_print; | ||
899 | #else | ||
900 | #define ahc_scb_scsioffset_print(regvalue, cur_col, wrap) \ | ||
901 | ahc_print_register(NULL, 0, "SCB_SCSIOFFSET", 0xbe, regvalue, cur_col, wrap) | ||
902 | #endif | ||
903 | |||
904 | #if AIC_DEBUG_REGISTERS | ||
905 | ahc_reg_print_t ahc_scb_next_print; | ||
906 | #else | ||
907 | #define ahc_scb_next_print(regvalue, cur_col, wrap) \ | ||
908 | ahc_print_register(NULL, 0, "SCB_NEXT", 0xbf, regvalue, cur_col, wrap) | ||
909 | #endif | ||
910 | |||
911 | #if AIC_DEBUG_REGISTERS | ||
912 | ahc_reg_print_t ahc_scb_64_spare_print; | ||
913 | #else | ||
914 | #define ahc_scb_64_spare_print(regvalue, cur_col, wrap) \ | ||
915 | ahc_print_register(NULL, 0, "SCB_64_SPARE", 0xc0, regvalue, cur_col, wrap) | ||
916 | #endif | ||
917 | |||
918 | #if AIC_DEBUG_REGISTERS | ||
919 | ahc_reg_print_t ahc_seectl_2840_print; | ||
920 | #else | ||
921 | #define ahc_seectl_2840_print(regvalue, cur_col, wrap) \ | ||
922 | ahc_print_register(NULL, 0, "SEECTL_2840", 0xc0, regvalue, cur_col, wrap) | ||
923 | #endif | ||
924 | |||
925 | #if AIC_DEBUG_REGISTERS | ||
926 | ahc_reg_print_t ahc_status_2840_print; | ||
927 | #else | ||
928 | #define ahc_status_2840_print(regvalue, cur_col, wrap) \ | ||
929 | ahc_print_register(NULL, 0, "STATUS_2840", 0xc1, regvalue, cur_col, wrap) | ||
930 | #endif | ||
931 | |||
932 | #if AIC_DEBUG_REGISTERS | ||
933 | ahc_reg_print_t ahc_scb_64_btt_print; | ||
934 | #else | ||
935 | #define ahc_scb_64_btt_print(regvalue, cur_col, wrap) \ | ||
936 | ahc_print_register(NULL, 0, "SCB_64_BTT", 0xd0, regvalue, cur_col, wrap) | ||
937 | #endif | ||
938 | |||
939 | #if AIC_DEBUG_REGISTERS | ||
940 | ahc_reg_print_t ahc_cchaddr_print; | ||
941 | #else | ||
942 | #define ahc_cchaddr_print(regvalue, cur_col, wrap) \ | ||
943 | ahc_print_register(NULL, 0, "CCHADDR", 0xe0, regvalue, cur_col, wrap) | ||
944 | #endif | ||
945 | |||
946 | #if AIC_DEBUG_REGISTERS | ||
947 | ahc_reg_print_t ahc_cchcnt_print; | ||
948 | #else | ||
949 | #define ahc_cchcnt_print(regvalue, cur_col, wrap) \ | ||
950 | ahc_print_register(NULL, 0, "CCHCNT", 0xe8, regvalue, cur_col, wrap) | ||
951 | #endif | ||
952 | |||
953 | #if AIC_DEBUG_REGISTERS | ||
954 | ahc_reg_print_t ahc_ccsgram_print; | ||
955 | #else | ||
956 | #define ahc_ccsgram_print(regvalue, cur_col, wrap) \ | ||
957 | ahc_print_register(NULL, 0, "CCSGRAM", 0xe9, regvalue, cur_col, wrap) | ||
958 | #endif | ||
959 | |||
960 | #if AIC_DEBUG_REGISTERS | ||
961 | ahc_reg_print_t ahc_ccsgaddr_print; | ||
962 | #else | ||
963 | #define ahc_ccsgaddr_print(regvalue, cur_col, wrap) \ | ||
964 | ahc_print_register(NULL, 0, "CCSGADDR", 0xea, regvalue, cur_col, wrap) | ||
965 | #endif | ||
966 | |||
967 | #if AIC_DEBUG_REGISTERS | ||
968 | ahc_reg_print_t ahc_ccsgctl_print; | ||
969 | #else | ||
970 | #define ahc_ccsgctl_print(regvalue, cur_col, wrap) \ | ||
971 | ahc_print_register(NULL, 0, "CCSGCTL", 0xeb, regvalue, cur_col, wrap) | ||
972 | #endif | ||
973 | |||
974 | #if AIC_DEBUG_REGISTERS | ||
975 | ahc_reg_print_t ahc_ccscbram_print; | ||
976 | #else | ||
977 | #define ahc_ccscbram_print(regvalue, cur_col, wrap) \ | ||
978 | ahc_print_register(NULL, 0, "CCSCBRAM", 0xec, regvalue, cur_col, wrap) | ||
979 | #endif | ||
980 | |||
981 | #if AIC_DEBUG_REGISTERS | ||
982 | ahc_reg_print_t ahc_ccscbaddr_print; | ||
983 | #else | ||
984 | #define ahc_ccscbaddr_print(regvalue, cur_col, wrap) \ | ||
985 | ahc_print_register(NULL, 0, "CCSCBADDR", 0xed, regvalue, cur_col, wrap) | ||
986 | #endif | ||
987 | |||
988 | #if AIC_DEBUG_REGISTERS | ||
989 | ahc_reg_print_t ahc_ccscbctl_print; | ||
990 | #else | ||
991 | #define ahc_ccscbctl_print(regvalue, cur_col, wrap) \ | ||
992 | ahc_print_register(NULL, 0, "CCSCBCTL", 0xee, regvalue, cur_col, wrap) | ||
993 | #endif | ||
994 | |||
995 | #if AIC_DEBUG_REGISTERS | ||
996 | ahc_reg_print_t ahc_ccscbcnt_print; | ||
997 | #else | ||
998 | #define ahc_ccscbcnt_print(regvalue, cur_col, wrap) \ | ||
999 | ahc_print_register(NULL, 0, "CCSCBCNT", 0xef, regvalue, cur_col, wrap) | ||
1000 | #endif | ||
1001 | |||
1002 | #if AIC_DEBUG_REGISTERS | ||
1003 | ahc_reg_print_t ahc_scbbaddr_print; | ||
1004 | #else | ||
1005 | #define ahc_scbbaddr_print(regvalue, cur_col, wrap) \ | ||
1006 | ahc_print_register(NULL, 0, "SCBBADDR", 0xf0, regvalue, cur_col, wrap) | ||
1007 | #endif | ||
1008 | |||
1009 | #if AIC_DEBUG_REGISTERS | ||
1010 | ahc_reg_print_t ahc_ccscbptr_print; | ||
1011 | #else | ||
1012 | #define ahc_ccscbptr_print(regvalue, cur_col, wrap) \ | ||
1013 | ahc_print_register(NULL, 0, "CCSCBPTR", 0xf1, regvalue, cur_col, wrap) | ||
1014 | #endif | ||
1015 | |||
1016 | #if AIC_DEBUG_REGISTERS | ||
1017 | ahc_reg_print_t ahc_hnscb_qoff_print; | ||
1018 | #else | ||
1019 | #define ahc_hnscb_qoff_print(regvalue, cur_col, wrap) \ | ||
1020 | ahc_print_register(NULL, 0, "HNSCB_QOFF", 0xf4, regvalue, cur_col, wrap) | ||
1021 | #endif | ||
1022 | |||
1023 | #if AIC_DEBUG_REGISTERS | ||
1024 | ahc_reg_print_t ahc_snscb_qoff_print; | ||
1025 | #else | ||
1026 | #define ahc_snscb_qoff_print(regvalue, cur_col, wrap) \ | ||
1027 | ahc_print_register(NULL, 0, "SNSCB_QOFF", 0xf6, regvalue, cur_col, wrap) | ||
1028 | #endif | ||
1029 | |||
1030 | #if AIC_DEBUG_REGISTERS | ||
1031 | ahc_reg_print_t ahc_sdscb_qoff_print; | ||
1032 | #else | ||
1033 | #define ahc_sdscb_qoff_print(regvalue, cur_col, wrap) \ | ||
1034 | ahc_print_register(NULL, 0, "SDSCB_QOFF", 0xf8, regvalue, cur_col, wrap) | ||
1035 | #endif | ||
1036 | |||
1037 | #if AIC_DEBUG_REGISTERS | ||
1038 | ahc_reg_print_t ahc_qoff_ctlsta_print; | ||
1039 | #else | ||
1040 | #define ahc_qoff_ctlsta_print(regvalue, cur_col, wrap) \ | ||
1041 | ahc_print_register(NULL, 0, "QOFF_CTLSTA", 0xfa, regvalue, cur_col, wrap) | ||
1042 | #endif | ||
1043 | |||
1044 | #if AIC_DEBUG_REGISTERS | ||
1045 | ahc_reg_print_t ahc_dff_thrsh_print; | ||
1046 | #else | ||
1047 | #define ahc_dff_thrsh_print(regvalue, cur_col, wrap) \ | ||
1048 | ahc_print_register(NULL, 0, "DFF_THRSH", 0xfb, regvalue, cur_col, wrap) | ||
1049 | #endif | ||
1050 | |||
1051 | #if AIC_DEBUG_REGISTERS | ||
1052 | ahc_reg_print_t ahc_sg_cache_shadow_print; | ||
1053 | #else | ||
1054 | #define ahc_sg_cache_shadow_print(regvalue, cur_col, wrap) \ | ||
1055 | ahc_print_register(NULL, 0, "SG_CACHE_SHADOW", 0xfc, regvalue, cur_col, wrap) | ||
1056 | #endif | ||
1057 | |||
1058 | #if AIC_DEBUG_REGISTERS | ||
1059 | ahc_reg_print_t ahc_sg_cache_pre_print; | ||
1060 | #else | ||
1061 | #define ahc_sg_cache_pre_print(regvalue, cur_col, wrap) \ | ||
1062 | ahc_print_register(NULL, 0, "SG_CACHE_PRE", 0xfc, regvalue, cur_col, wrap) | ||
1063 | #endif | ||
1064 | |||
1065 | 190 | ||
1066 | #define SCSISEQ 0x00 | 191 | #define SCSISEQ 0x00 |
1067 | #define TEMODE 0x80 | 192 | #define TEMODE 0x80 |
diff --git a/drivers/scsi/aic7xxx/aic7xxx_reg_print.c_shipped b/drivers/scsi/aic7xxx/aic7xxx_reg_print.c_shipped index 309a562b009e..9f9b88047d0c 100644 --- a/drivers/scsi/aic7xxx/aic7xxx_reg_print.c_shipped +++ b/drivers/scsi/aic7xxx/aic7xxx_reg_print.c_shipped | |||
@@ -43,48 +43,6 @@ ahc_sxfrctl0_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
43 | 0x01, regvalue, cur_col, wrap)); | 43 | 0x01, regvalue, cur_col, wrap)); |
44 | } | 44 | } |
45 | 45 | ||
46 | static const ahc_reg_parse_entry_t SXFRCTL1_parse_table[] = { | ||
47 | { "STPWEN", 0x01, 0x01 }, | ||
48 | { "ACTNEGEN", 0x02, 0x02 }, | ||
49 | { "ENSTIMER", 0x04, 0x04 }, | ||
50 | { "ENSPCHK", 0x20, 0x20 }, | ||
51 | { "SWRAPEN", 0x40, 0x40 }, | ||
52 | { "BITBUCKET", 0x80, 0x80 }, | ||
53 | { "STIMESEL", 0x18, 0x18 } | ||
54 | }; | ||
55 | |||
56 | int | ||
57 | ahc_sxfrctl1_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
58 | { | ||
59 | return (ahc_print_register(SXFRCTL1_parse_table, 7, "SXFRCTL1", | ||
60 | 0x02, regvalue, cur_col, wrap)); | ||
61 | } | ||
62 | |||
63 | static const ahc_reg_parse_entry_t SCSISIGO_parse_table[] = { | ||
64 | { "ACKO", 0x01, 0x01 }, | ||
65 | { "REQO", 0x02, 0x02 }, | ||
66 | { "BSYO", 0x04, 0x04 }, | ||
67 | { "SELO", 0x08, 0x08 }, | ||
68 | { "ATNO", 0x10, 0x10 }, | ||
69 | { "MSGO", 0x20, 0x20 }, | ||
70 | { "IOO", 0x40, 0x40 }, | ||
71 | { "CDO", 0x80, 0x80 }, | ||
72 | { "P_DATAOUT", 0x00, 0x00 }, | ||
73 | { "P_DATAIN", 0x40, 0x40 }, | ||
74 | { "P_COMMAND", 0x80, 0x80 }, | ||
75 | { "P_MESGOUT", 0xa0, 0xa0 }, | ||
76 | { "P_STATUS", 0xc0, 0xc0 }, | ||
77 | { "PHASE_MASK", 0xe0, 0xe0 }, | ||
78 | { "P_MESGIN", 0xe0, 0xe0 } | ||
79 | }; | ||
80 | |||
81 | int | ||
82 | ahc_scsisigo_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
83 | { | ||
84 | return (ahc_print_register(SCSISIGO_parse_table, 15, "SCSISIGO", | ||
85 | 0x03, regvalue, cur_col, wrap)); | ||
86 | } | ||
87 | |||
88 | static const ahc_reg_parse_entry_t SCSISIGI_parse_table[] = { | 46 | static const ahc_reg_parse_entry_t SCSISIGI_parse_table[] = { |
89 | { "ACKI", 0x01, 0x01 }, | 47 | { "ACKI", 0x01, 0x01 }, |
90 | { "REQI", 0x02, 0x02 }, | 48 | { "REQI", 0x02, 0x02 }, |
@@ -128,77 +86,6 @@ ahc_scsirate_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
128 | 0x04, regvalue, cur_col, wrap)); | 86 | 0x04, regvalue, cur_col, wrap)); |
129 | } | 87 | } |
130 | 88 | ||
131 | static const ahc_reg_parse_entry_t SCSIID_parse_table[] = { | ||
132 | { "TWIN_CHNLB", 0x80, 0x80 }, | ||
133 | { "OID", 0x0f, 0x0f }, | ||
134 | { "TWIN_TID", 0x70, 0x70 }, | ||
135 | { "SOFS_ULTRA2", 0x7f, 0x7f }, | ||
136 | { "TID", 0xf0, 0xf0 } | ||
137 | }; | ||
138 | |||
139 | int | ||
140 | ahc_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
141 | { | ||
142 | return (ahc_print_register(SCSIID_parse_table, 5, "SCSIID", | ||
143 | 0x05, regvalue, cur_col, wrap)); | ||
144 | } | ||
145 | |||
146 | int | ||
147 | ahc_scsidatl_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
148 | { | ||
149 | return (ahc_print_register(NULL, 0, "SCSIDATL", | ||
150 | 0x06, regvalue, cur_col, wrap)); | ||
151 | } | ||
152 | |||
153 | int | ||
154 | ahc_stcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
155 | { | ||
156 | return (ahc_print_register(NULL, 0, "STCNT", | ||
157 | 0x08, regvalue, cur_col, wrap)); | ||
158 | } | ||
159 | |||
160 | static const ahc_reg_parse_entry_t OPTIONMODE_parse_table[] = { | ||
161 | { "DIS_MSGIN_DUALEDGE", 0x01, 0x01 }, | ||
162 | { "AUTO_MSGOUT_DE", 0x02, 0x02 }, | ||
163 | { "SCSIDATL_IMGEN", 0x04, 0x04 }, | ||
164 | { "EXPPHASEDIS", 0x08, 0x08 }, | ||
165 | { "BUSFREEREV", 0x10, 0x10 }, | ||
166 | { "ATNMGMNTEN", 0x20, 0x20 }, | ||
167 | { "AUTOACKEN", 0x40, 0x40 }, | ||
168 | { "AUTORATEEN", 0x80, 0x80 }, | ||
169 | { "OPTIONMODE_DEFAULTS",0x03, 0x03 } | ||
170 | }; | ||
171 | |||
172 | int | ||
173 | ahc_optionmode_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
174 | { | ||
175 | return (ahc_print_register(OPTIONMODE_parse_table, 9, "OPTIONMODE", | ||
176 | 0x08, regvalue, cur_col, wrap)); | ||
177 | } | ||
178 | |||
179 | int | ||
180 | ahc_targcrccnt_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
181 | { | ||
182 | return (ahc_print_register(NULL, 0, "TARGCRCCNT", | ||
183 | 0x0a, regvalue, cur_col, wrap)); | ||
184 | } | ||
185 | |||
186 | static const ahc_reg_parse_entry_t CLRSINT0_parse_table[] = { | ||
187 | { "CLRSPIORDY", 0x02, 0x02 }, | ||
188 | { "CLRSWRAP", 0x08, 0x08 }, | ||
189 | { "CLRIOERR", 0x08, 0x08 }, | ||
190 | { "CLRSELINGO", 0x10, 0x10 }, | ||
191 | { "CLRSELDI", 0x20, 0x20 }, | ||
192 | { "CLRSELDO", 0x40, 0x40 } | ||
193 | }; | ||
194 | |||
195 | int | ||
196 | ahc_clrsint0_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
197 | { | ||
198 | return (ahc_print_register(CLRSINT0_parse_table, 6, "CLRSINT0", | ||
199 | 0x0b, regvalue, cur_col, wrap)); | ||
200 | } | ||
201 | |||
202 | static const ahc_reg_parse_entry_t SSTAT0_parse_table[] = { | 89 | static const ahc_reg_parse_entry_t SSTAT0_parse_table[] = { |
203 | { "DMADONE", 0x01, 0x01 }, | 90 | { "DMADONE", 0x01, 0x01 }, |
204 | { "SPIORDY", 0x02, 0x02 }, | 91 | { "SPIORDY", 0x02, 0x02 }, |
@@ -218,23 +105,6 @@ ahc_sstat0_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
218 | 0x0b, regvalue, cur_col, wrap)); | 105 | 0x0b, regvalue, cur_col, wrap)); |
219 | } | 106 | } |
220 | 107 | ||
221 | static const ahc_reg_parse_entry_t CLRSINT1_parse_table[] = { | ||
222 | { "CLRREQINIT", 0x01, 0x01 }, | ||
223 | { "CLRPHASECHG", 0x02, 0x02 }, | ||
224 | { "CLRSCSIPERR", 0x04, 0x04 }, | ||
225 | { "CLRBUSFREE", 0x08, 0x08 }, | ||
226 | { "CLRSCSIRSTI", 0x20, 0x20 }, | ||
227 | { "CLRATNO", 0x40, 0x40 }, | ||
228 | { "CLRSELTIMEO", 0x80, 0x80 } | ||
229 | }; | ||
230 | |||
231 | int | ||
232 | ahc_clrsint1_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
233 | { | ||
234 | return (ahc_print_register(CLRSINT1_parse_table, 7, "CLRSINT1", | ||
235 | 0x0c, regvalue, cur_col, wrap)); | ||
236 | } | ||
237 | |||
238 | static const ahc_reg_parse_entry_t SSTAT1_parse_table[] = { | 108 | static const ahc_reg_parse_entry_t SSTAT1_parse_table[] = { |
239 | { "REQINIT", 0x01, 0x01 }, | 109 | { "REQINIT", 0x01, 0x01 }, |
240 | { "PHASECHG", 0x02, 0x02 }, | 110 | { "PHASECHG", 0x02, 0x02 }, |
@@ -284,18 +154,6 @@ ahc_sstat3_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
284 | 0x0e, regvalue, cur_col, wrap)); | 154 | 0x0e, regvalue, cur_col, wrap)); |
285 | } | 155 | } |
286 | 156 | ||
287 | static const ahc_reg_parse_entry_t SCSIID_ULTRA2_parse_table[] = { | ||
288 | { "OID", 0x0f, 0x0f }, | ||
289 | { "TID", 0xf0, 0xf0 } | ||
290 | }; | ||
291 | |||
292 | int | ||
293 | ahc_scsiid_ultra2_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
294 | { | ||
295 | return (ahc_print_register(SCSIID_ULTRA2_parse_table, 2, "SCSIID_ULTRA2", | ||
296 | 0x0f, regvalue, cur_col, wrap)); | ||
297 | } | ||
298 | |||
299 | static const ahc_reg_parse_entry_t SIMODE0_parse_table[] = { | 157 | static const ahc_reg_parse_entry_t SIMODE0_parse_table[] = { |
300 | { "ENDMADONE", 0x01, 0x01 }, | 158 | { "ENDMADONE", 0x01, 0x01 }, |
301 | { "ENSPIORDY", 0x02, 0x02 }, | 159 | { "ENSPIORDY", 0x02, 0x02 }, |
@@ -339,107 +197,6 @@ ahc_scsibusl_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
339 | 0x12, regvalue, cur_col, wrap)); | 197 | 0x12, regvalue, cur_col, wrap)); |
340 | } | 198 | } |
341 | 199 | ||
342 | int | ||
343 | ahc_shaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
344 | { | ||
345 | return (ahc_print_register(NULL, 0, "SHADDR", | ||
346 | 0x14, regvalue, cur_col, wrap)); | ||
347 | } | ||
348 | |||
349 | static const ahc_reg_parse_entry_t SELTIMER_parse_table[] = { | ||
350 | { "STAGE1", 0x01, 0x01 }, | ||
351 | { "STAGE2", 0x02, 0x02 }, | ||
352 | { "STAGE3", 0x04, 0x04 }, | ||
353 | { "STAGE4", 0x08, 0x08 }, | ||
354 | { "STAGE5", 0x10, 0x10 }, | ||
355 | { "STAGE6", 0x20, 0x20 } | ||
356 | }; | ||
357 | |||
358 | int | ||
359 | ahc_seltimer_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
360 | { | ||
361 | return (ahc_print_register(SELTIMER_parse_table, 6, "SELTIMER", | ||
362 | 0x18, regvalue, cur_col, wrap)); | ||
363 | } | ||
364 | |||
365 | static const ahc_reg_parse_entry_t SELID_parse_table[] = { | ||
366 | { "ONEBIT", 0x08, 0x08 }, | ||
367 | { "SELID_MASK", 0xf0, 0xf0 } | ||
368 | }; | ||
369 | |||
370 | int | ||
371 | ahc_selid_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
372 | { | ||
373 | return (ahc_print_register(SELID_parse_table, 2, "SELID", | ||
374 | 0x19, regvalue, cur_col, wrap)); | ||
375 | } | ||
376 | |||
377 | int | ||
378 | ahc_targid_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
379 | { | ||
380 | return (ahc_print_register(NULL, 0, "TARGID", | ||
381 | 0x1b, regvalue, cur_col, wrap)); | ||
382 | } | ||
383 | |||
384 | static const ahc_reg_parse_entry_t SPIOCAP_parse_table[] = { | ||
385 | { "SSPIOCPS", 0x01, 0x01 }, | ||
386 | { "ROM", 0x02, 0x02 }, | ||
387 | { "EEPROM", 0x04, 0x04 }, | ||
388 | { "SEEPROM", 0x08, 0x08 }, | ||
389 | { "EXT_BRDCTL", 0x10, 0x10 }, | ||
390 | { "SOFTCMDEN", 0x20, 0x20 }, | ||
391 | { "SOFT0", 0x40, 0x40 }, | ||
392 | { "SOFT1", 0x80, 0x80 } | ||
393 | }; | ||
394 | |||
395 | int | ||
396 | ahc_spiocap_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
397 | { | ||
398 | return (ahc_print_register(SPIOCAP_parse_table, 8, "SPIOCAP", | ||
399 | 0x1b, regvalue, cur_col, wrap)); | ||
400 | } | ||
401 | |||
402 | static const ahc_reg_parse_entry_t BRDCTL_parse_table[] = { | ||
403 | { "BRDCTL0", 0x01, 0x01 }, | ||
404 | { "BRDSTB_ULTRA2", 0x01, 0x01 }, | ||
405 | { "BRDCTL1", 0x02, 0x02 }, | ||
406 | { "BRDRW_ULTRA2", 0x02, 0x02 }, | ||
407 | { "BRDRW", 0x04, 0x04 }, | ||
408 | { "BRDDAT2", 0x04, 0x04 }, | ||
409 | { "BRDCS", 0x08, 0x08 }, | ||
410 | { "BRDDAT3", 0x08, 0x08 }, | ||
411 | { "BRDSTB", 0x10, 0x10 }, | ||
412 | { "BRDDAT4", 0x10, 0x10 }, | ||
413 | { "BRDDAT5", 0x20, 0x20 }, | ||
414 | { "BRDDAT6", 0x40, 0x40 }, | ||
415 | { "BRDDAT7", 0x80, 0x80 } | ||
416 | }; | ||
417 | |||
418 | int | ||
419 | ahc_brdctl_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
420 | { | ||
421 | return (ahc_print_register(BRDCTL_parse_table, 13, "BRDCTL", | ||
422 | 0x1d, regvalue, cur_col, wrap)); | ||
423 | } | ||
424 | |||
425 | static const ahc_reg_parse_entry_t SEECTL_parse_table[] = { | ||
426 | { "SEEDI", 0x01, 0x01 }, | ||
427 | { "SEEDO", 0x02, 0x02 }, | ||
428 | { "SEECK", 0x04, 0x04 }, | ||
429 | { "SEECS", 0x08, 0x08 }, | ||
430 | { "SEERDY", 0x10, 0x10 }, | ||
431 | { "SEEMS", 0x20, 0x20 }, | ||
432 | { "EXTARBREQ", 0x40, 0x40 }, | ||
433 | { "EXTARBACK", 0x80, 0x80 } | ||
434 | }; | ||
435 | |||
436 | int | ||
437 | ahc_seectl_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
438 | { | ||
439 | return (ahc_print_register(SEECTL_parse_table, 8, "SEECTL", | ||
440 | 0x1e, regvalue, cur_col, wrap)); | ||
441 | } | ||
442 | |||
443 | static const ahc_reg_parse_entry_t SBLKCTL_parse_table[] = { | 200 | static const ahc_reg_parse_entry_t SBLKCTL_parse_table[] = { |
444 | { "XCVR", 0x01, 0x01 }, | 201 | { "XCVR", 0x01, 0x01 }, |
445 | { "SELWIDE", 0x02, 0x02 }, | 202 | { "SELWIDE", 0x02, 0x02 }, |
@@ -458,68 +215,6 @@ ahc_sblkctl_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
458 | 0x1f, regvalue, cur_col, wrap)); | 215 | 0x1f, regvalue, cur_col, wrap)); |
459 | } | 216 | } |
460 | 217 | ||
461 | int | ||
462 | ahc_busy_targets_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
463 | { | ||
464 | return (ahc_print_register(NULL, 0, "BUSY_TARGETS", | ||
465 | 0x20, regvalue, cur_col, wrap)); | ||
466 | } | ||
467 | |||
468 | int | ||
469 | ahc_ultra_enb_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
470 | { | ||
471 | return (ahc_print_register(NULL, 0, "ULTRA_ENB", | ||
472 | 0x30, regvalue, cur_col, wrap)); | ||
473 | } | ||
474 | |||
475 | int | ||
476 | ahc_disc_dsb_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
477 | { | ||
478 | return (ahc_print_register(NULL, 0, "DISC_DSB", | ||
479 | 0x32, regvalue, cur_col, wrap)); | ||
480 | } | ||
481 | |||
482 | int | ||
483 | ahc_mwi_residual_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
484 | { | ||
485 | return (ahc_print_register(NULL, 0, "MWI_RESIDUAL", | ||
486 | 0x38, regvalue, cur_col, wrap)); | ||
487 | } | ||
488 | |||
489 | int | ||
490 | ahc_next_queued_scb_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
491 | { | ||
492 | return (ahc_print_register(NULL, 0, "NEXT_QUEUED_SCB", | ||
493 | 0x39, regvalue, cur_col, wrap)); | ||
494 | } | ||
495 | |||
496 | int | ||
497 | ahc_msg_out_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
498 | { | ||
499 | return (ahc_print_register(NULL, 0, "MSG_OUT", | ||
500 | 0x3a, regvalue, cur_col, wrap)); | ||
501 | } | ||
502 | |||
503 | static const ahc_reg_parse_entry_t DMAPARAMS_parse_table[] = { | ||
504 | { "FIFORESET", 0x01, 0x01 }, | ||
505 | { "FIFOFLUSH", 0x02, 0x02 }, | ||
506 | { "DIRECTION", 0x04, 0x04 }, | ||
507 | { "HDMAEN", 0x08, 0x08 }, | ||
508 | { "HDMAENACK", 0x08, 0x08 }, | ||
509 | { "SDMAEN", 0x10, 0x10 }, | ||
510 | { "SDMAENACK", 0x10, 0x10 }, | ||
511 | { "SCSIEN", 0x20, 0x20 }, | ||
512 | { "WIDEODD", 0x40, 0x40 }, | ||
513 | { "PRELOADEN", 0x80, 0x80 } | ||
514 | }; | ||
515 | |||
516 | int | ||
517 | ahc_dmaparams_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
518 | { | ||
519 | return (ahc_print_register(DMAPARAMS_parse_table, 10, "DMAPARAMS", | ||
520 | 0x3b, regvalue, cur_col, wrap)); | ||
521 | } | ||
522 | |||
523 | static const ahc_reg_parse_entry_t SEQ_FLAGS_parse_table[] = { | 218 | static const ahc_reg_parse_entry_t SEQ_FLAGS_parse_table[] = { |
524 | { "NO_DISCONNECT", 0x01, 0x01 }, | 219 | { "NO_DISCONNECT", 0x01, 0x01 }, |
525 | { "SPHASE_PENDING", 0x02, 0x02 }, | 220 | { "SPHASE_PENDING", 0x02, 0x02 }, |
@@ -539,20 +234,6 @@ ahc_seq_flags_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
539 | 0x3c, regvalue, cur_col, wrap)); | 234 | 0x3c, regvalue, cur_col, wrap)); |
540 | } | 235 | } |
541 | 236 | ||
542 | int | ||
543 | ahc_saved_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
544 | { | ||
545 | return (ahc_print_register(NULL, 0, "SAVED_SCSIID", | ||
546 | 0x3d, regvalue, cur_col, wrap)); | ||
547 | } | ||
548 | |||
549 | int | ||
550 | ahc_saved_lun_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
551 | { | ||
552 | return (ahc_print_register(NULL, 0, "SAVED_LUN", | ||
553 | 0x3e, regvalue, cur_col, wrap)); | ||
554 | } | ||
555 | |||
556 | static const ahc_reg_parse_entry_t LASTPHASE_parse_table[] = { | 237 | static const ahc_reg_parse_entry_t LASTPHASE_parse_table[] = { |
557 | { "MSGI", 0x20, 0x20 }, | 238 | { "MSGI", 0x20, 0x20 }, |
558 | { "IOI", 0x40, 0x40 }, | 239 | { "IOI", 0x40, 0x40 }, |
@@ -574,193 +255,6 @@ ahc_lastphase_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
574 | 0x3f, regvalue, cur_col, wrap)); | 255 | 0x3f, regvalue, cur_col, wrap)); |
575 | } | 256 | } |
576 | 257 | ||
577 | int | ||
578 | ahc_waiting_scbh_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
579 | { | ||
580 | return (ahc_print_register(NULL, 0, "WAITING_SCBH", | ||
581 | 0x40, regvalue, cur_col, wrap)); | ||
582 | } | ||
583 | |||
584 | int | ||
585 | ahc_disconnected_scbh_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
586 | { | ||
587 | return (ahc_print_register(NULL, 0, "DISCONNECTED_SCBH", | ||
588 | 0x41, regvalue, cur_col, wrap)); | ||
589 | } | ||
590 | |||
591 | int | ||
592 | ahc_free_scbh_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
593 | { | ||
594 | return (ahc_print_register(NULL, 0, "FREE_SCBH", | ||
595 | 0x42, regvalue, cur_col, wrap)); | ||
596 | } | ||
597 | |||
598 | int | ||
599 | ahc_hscb_addr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
600 | { | ||
601 | return (ahc_print_register(NULL, 0, "HSCB_ADDR", | ||
602 | 0x44, regvalue, cur_col, wrap)); | ||
603 | } | ||
604 | |||
605 | int | ||
606 | ahc_shared_data_addr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
607 | { | ||
608 | return (ahc_print_register(NULL, 0, "SHARED_DATA_ADDR", | ||
609 | 0x48, regvalue, cur_col, wrap)); | ||
610 | } | ||
611 | |||
612 | int | ||
613 | ahc_kernel_qinpos_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
614 | { | ||
615 | return (ahc_print_register(NULL, 0, "KERNEL_QINPOS", | ||
616 | 0x4c, regvalue, cur_col, wrap)); | ||
617 | } | ||
618 | |||
619 | int | ||
620 | ahc_qinpos_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
621 | { | ||
622 | return (ahc_print_register(NULL, 0, "QINPOS", | ||
623 | 0x4d, regvalue, cur_col, wrap)); | ||
624 | } | ||
625 | |||
626 | int | ||
627 | ahc_qoutpos_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
628 | { | ||
629 | return (ahc_print_register(NULL, 0, "QOUTPOS", | ||
630 | 0x4e, regvalue, cur_col, wrap)); | ||
631 | } | ||
632 | |||
633 | int | ||
634 | ahc_kernel_tqinpos_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
635 | { | ||
636 | return (ahc_print_register(NULL, 0, "KERNEL_TQINPOS", | ||
637 | 0x4f, regvalue, cur_col, wrap)); | ||
638 | } | ||
639 | |||
640 | int | ||
641 | ahc_tqinpos_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
642 | { | ||
643 | return (ahc_print_register(NULL, 0, "TQINPOS", | ||
644 | 0x50, regvalue, cur_col, wrap)); | ||
645 | } | ||
646 | |||
647 | static const ahc_reg_parse_entry_t ARG_1_parse_table[] = { | ||
648 | { "CONT_TARG_SESSION", 0x02, 0x02 }, | ||
649 | { "CONT_MSG_LOOP", 0x04, 0x04 }, | ||
650 | { "EXIT_MSG_LOOP", 0x08, 0x08 }, | ||
651 | { "MSGOUT_PHASEMIS", 0x10, 0x10 }, | ||
652 | { "SEND_REJ", 0x20, 0x20 }, | ||
653 | { "SEND_SENSE", 0x40, 0x40 }, | ||
654 | { "SEND_MSG", 0x80, 0x80 } | ||
655 | }; | ||
656 | |||
657 | int | ||
658 | ahc_arg_1_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
659 | { | ||
660 | return (ahc_print_register(ARG_1_parse_table, 7, "ARG_1", | ||
661 | 0x51, regvalue, cur_col, wrap)); | ||
662 | } | ||
663 | |||
664 | int | ||
665 | ahc_arg_2_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
666 | { | ||
667 | return (ahc_print_register(NULL, 0, "ARG_2", | ||
668 | 0x52, regvalue, cur_col, wrap)); | ||
669 | } | ||
670 | |||
671 | int | ||
672 | ahc_last_msg_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
673 | { | ||
674 | return (ahc_print_register(NULL, 0, "LAST_MSG", | ||
675 | 0x53, regvalue, cur_col, wrap)); | ||
676 | } | ||
677 | |||
678 | static const ahc_reg_parse_entry_t SCSISEQ_TEMPLATE_parse_table[] = { | ||
679 | { "ENAUTOATNP", 0x02, 0x02 }, | ||
680 | { "ENAUTOATNI", 0x04, 0x04 }, | ||
681 | { "ENAUTOATNO", 0x08, 0x08 }, | ||
682 | { "ENRSELI", 0x10, 0x10 }, | ||
683 | { "ENSELI", 0x20, 0x20 }, | ||
684 | { "ENSELO", 0x40, 0x40 } | ||
685 | }; | ||
686 | |||
687 | int | ||
688 | ahc_scsiseq_template_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
689 | { | ||
690 | return (ahc_print_register(SCSISEQ_TEMPLATE_parse_table, 6, "SCSISEQ_TEMPLATE", | ||
691 | 0x54, regvalue, cur_col, wrap)); | ||
692 | } | ||
693 | |||
694 | static const ahc_reg_parse_entry_t HA_274_BIOSGLOBAL_parse_table[] = { | ||
695 | { "HA_274_EXTENDED_TRANS",0x01, 0x01 } | ||
696 | }; | ||
697 | |||
698 | int | ||
699 | ahc_ha_274_biosglobal_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
700 | { | ||
701 | return (ahc_print_register(HA_274_BIOSGLOBAL_parse_table, 1, "HA_274_BIOSGLOBAL", | ||
702 | 0x56, regvalue, cur_col, wrap)); | ||
703 | } | ||
704 | |||
705 | static const ahc_reg_parse_entry_t SEQ_FLAGS2_parse_table[] = { | ||
706 | { "SCB_DMA", 0x01, 0x01 }, | ||
707 | { "TARGET_MSG_PENDING", 0x02, 0x02 } | ||
708 | }; | ||
709 | |||
710 | int | ||
711 | ahc_seq_flags2_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
712 | { | ||
713 | return (ahc_print_register(SEQ_FLAGS2_parse_table, 2, "SEQ_FLAGS2", | ||
714 | 0x57, regvalue, cur_col, wrap)); | ||
715 | } | ||
716 | |||
717 | static const ahc_reg_parse_entry_t SCSICONF_parse_table[] = { | ||
718 | { "ENSPCHK", 0x20, 0x20 }, | ||
719 | { "RESET_SCSI", 0x40, 0x40 }, | ||
720 | { "TERM_ENB", 0x80, 0x80 }, | ||
721 | { "HSCSIID", 0x07, 0x07 }, | ||
722 | { "HWSCSIID", 0x0f, 0x0f } | ||
723 | }; | ||
724 | |||
725 | int | ||
726 | ahc_scsiconf_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
727 | { | ||
728 | return (ahc_print_register(SCSICONF_parse_table, 5, "SCSICONF", | ||
729 | 0x5a, regvalue, cur_col, wrap)); | ||
730 | } | ||
731 | |||
732 | static const ahc_reg_parse_entry_t INTDEF_parse_table[] = { | ||
733 | { "EDGE_TRIG", 0x80, 0x80 }, | ||
734 | { "VECTOR", 0x0f, 0x0f } | ||
735 | }; | ||
736 | |||
737 | int | ||
738 | ahc_intdef_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
739 | { | ||
740 | return (ahc_print_register(INTDEF_parse_table, 2, "INTDEF", | ||
741 | 0x5c, regvalue, cur_col, wrap)); | ||
742 | } | ||
743 | |||
744 | int | ||
745 | ahc_hostconf_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
746 | { | ||
747 | return (ahc_print_register(NULL, 0, "HOSTCONF", | ||
748 | 0x5d, regvalue, cur_col, wrap)); | ||
749 | } | ||
750 | |||
751 | static const ahc_reg_parse_entry_t HA_274_BIOSCTRL_parse_table[] = { | ||
752 | { "CHANNEL_B_PRIMARY", 0x08, 0x08 }, | ||
753 | { "BIOSMODE", 0x30, 0x30 }, | ||
754 | { "BIOSDISABLED", 0x30, 0x30 } | ||
755 | }; | ||
756 | |||
757 | int | ||
758 | ahc_ha_274_biosctrl_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
759 | { | ||
760 | return (ahc_print_register(HA_274_BIOSCTRL_parse_table, 3, "HA_274_BIOSCTRL", | ||
761 | 0x5f, regvalue, cur_col, wrap)); | ||
762 | } | ||
763 | |||
764 | static const ahc_reg_parse_entry_t SEQCTL_parse_table[] = { | 258 | static const ahc_reg_parse_entry_t SEQCTL_parse_table[] = { |
765 | { "LOADRAM", 0x01, 0x01 }, | 259 | { "LOADRAM", 0x01, 0x01 }, |
766 | { "SEQRESET", 0x02, 0x02 }, | 260 | { "SEQRESET", 0x02, 0x02 }, |
@@ -780,285 +274,12 @@ ahc_seqctl_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
780 | } | 274 | } |
781 | 275 | ||
782 | int | 276 | int |
783 | ahc_seqram_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
784 | { | ||
785 | return (ahc_print_register(NULL, 0, "SEQRAM", | ||
786 | 0x61, regvalue, cur_col, wrap)); | ||
787 | } | ||
788 | |||
789 | int | ||
790 | ahc_seqaddr0_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
791 | { | ||
792 | return (ahc_print_register(NULL, 0, "SEQADDR0", | ||
793 | 0x62, regvalue, cur_col, wrap)); | ||
794 | } | ||
795 | |||
796 | static const ahc_reg_parse_entry_t SEQADDR1_parse_table[] = { | ||
797 | { "SEQADDR1_MASK", 0x01, 0x01 } | ||
798 | }; | ||
799 | |||
800 | int | ||
801 | ahc_seqaddr1_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
802 | { | ||
803 | return (ahc_print_register(SEQADDR1_parse_table, 1, "SEQADDR1", | ||
804 | 0x63, regvalue, cur_col, wrap)); | ||
805 | } | ||
806 | |||
807 | int | ||
808 | ahc_accum_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
809 | { | ||
810 | return (ahc_print_register(NULL, 0, "ACCUM", | ||
811 | 0x64, regvalue, cur_col, wrap)); | ||
812 | } | ||
813 | |||
814 | int | ||
815 | ahc_sindex_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
816 | { | ||
817 | return (ahc_print_register(NULL, 0, "SINDEX", | ||
818 | 0x65, regvalue, cur_col, wrap)); | ||
819 | } | ||
820 | |||
821 | int | ||
822 | ahc_dindex_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
823 | { | ||
824 | return (ahc_print_register(NULL, 0, "DINDEX", | ||
825 | 0x66, regvalue, cur_col, wrap)); | ||
826 | } | ||
827 | |||
828 | int | ||
829 | ahc_allones_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
830 | { | ||
831 | return (ahc_print_register(NULL, 0, "ALLONES", | ||
832 | 0x69, regvalue, cur_col, wrap)); | ||
833 | } | ||
834 | |||
835 | int | ||
836 | ahc_allzeros_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
837 | { | ||
838 | return (ahc_print_register(NULL, 0, "ALLZEROS", | ||
839 | 0x6a, regvalue, cur_col, wrap)); | ||
840 | } | ||
841 | |||
842 | int | ||
843 | ahc_none_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
844 | { | ||
845 | return (ahc_print_register(NULL, 0, "NONE", | ||
846 | 0x6a, regvalue, cur_col, wrap)); | ||
847 | } | ||
848 | |||
849 | static const ahc_reg_parse_entry_t FLAGS_parse_table[] = { | ||
850 | { "CARRY", 0x01, 0x01 }, | ||
851 | { "ZERO", 0x02, 0x02 } | ||
852 | }; | ||
853 | |||
854 | int | ||
855 | ahc_flags_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
856 | { | ||
857 | return (ahc_print_register(FLAGS_parse_table, 2, "FLAGS", | ||
858 | 0x6b, regvalue, cur_col, wrap)); | ||
859 | } | ||
860 | |||
861 | int | ||
862 | ahc_sindir_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
863 | { | ||
864 | return (ahc_print_register(NULL, 0, "SINDIR", | ||
865 | 0x6c, regvalue, cur_col, wrap)); | ||
866 | } | ||
867 | |||
868 | int | ||
869 | ahc_dindir_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
870 | { | ||
871 | return (ahc_print_register(NULL, 0, "DINDIR", | ||
872 | 0x6d, regvalue, cur_col, wrap)); | ||
873 | } | ||
874 | |||
875 | int | ||
876 | ahc_stack_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
877 | { | ||
878 | return (ahc_print_register(NULL, 0, "STACK", | ||
879 | 0x6f, regvalue, cur_col, wrap)); | ||
880 | } | ||
881 | |||
882 | int | ||
883 | ahc_targ_offset_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
884 | { | ||
885 | return (ahc_print_register(NULL, 0, "TARG_OFFSET", | ||
886 | 0x70, regvalue, cur_col, wrap)); | ||
887 | } | ||
888 | |||
889 | int | ||
890 | ahc_sram_base_print(u_int regvalue, u_int *cur_col, u_int wrap) | 277 | ahc_sram_base_print(u_int regvalue, u_int *cur_col, u_int wrap) |
891 | { | 278 | { |
892 | return (ahc_print_register(NULL, 0, "SRAM_BASE", | 279 | return (ahc_print_register(NULL, 0, "SRAM_BASE", |
893 | 0x70, regvalue, cur_col, wrap)); | 280 | 0x70, regvalue, cur_col, wrap)); |
894 | } | 281 | } |
895 | 282 | ||
896 | static const ahc_reg_parse_entry_t DSCOMMAND0_parse_table[] = { | ||
897 | { "CIOPARCKEN", 0x01, 0x01 }, | ||
898 | { "USCBSIZE32", 0x02, 0x02 }, | ||
899 | { "RAMPS", 0x04, 0x04 }, | ||
900 | { "INTSCBRAMSEL", 0x08, 0x08 }, | ||
901 | { "EXTREQLCK", 0x10, 0x10 }, | ||
902 | { "MPARCKEN", 0x20, 0x20 }, | ||
903 | { "DPARCKEN", 0x40, 0x40 }, | ||
904 | { "CACHETHEN", 0x80, 0x80 } | ||
905 | }; | ||
906 | |||
907 | int | ||
908 | ahc_dscommand0_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
909 | { | ||
910 | return (ahc_print_register(DSCOMMAND0_parse_table, 8, "DSCOMMAND0", | ||
911 | 0x84, regvalue, cur_col, wrap)); | ||
912 | } | ||
913 | |||
914 | static const ahc_reg_parse_entry_t BUSTIME_parse_table[] = { | ||
915 | { "BON", 0x0f, 0x0f }, | ||
916 | { "BOFF", 0xf0, 0xf0 } | ||
917 | }; | ||
918 | |||
919 | int | ||
920 | ahc_bustime_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
921 | { | ||
922 | return (ahc_print_register(BUSTIME_parse_table, 2, "BUSTIME", | ||
923 | 0x85, regvalue, cur_col, wrap)); | ||
924 | } | ||
925 | |||
926 | static const ahc_reg_parse_entry_t DSCOMMAND1_parse_table[] = { | ||
927 | { "HADDLDSEL0", 0x01, 0x01 }, | ||
928 | { "HADDLDSEL1", 0x02, 0x02 }, | ||
929 | { "DSLATT", 0xfc, 0xfc } | ||
930 | }; | ||
931 | |||
932 | int | ||
933 | ahc_dscommand1_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
934 | { | ||
935 | return (ahc_print_register(DSCOMMAND1_parse_table, 3, "DSCOMMAND1", | ||
936 | 0x85, regvalue, cur_col, wrap)); | ||
937 | } | ||
938 | |||
939 | static const ahc_reg_parse_entry_t BUSSPD_parse_table[] = { | ||
940 | { "STBON", 0x07, 0x07 }, | ||
941 | { "STBOFF", 0x38, 0x38 }, | ||
942 | { "DFTHRSH_75", 0x80, 0x80 }, | ||
943 | { "DFTHRSH", 0xc0, 0xc0 }, | ||
944 | { "DFTHRSH_100", 0xc0, 0xc0 } | ||
945 | }; | ||
946 | |||
947 | int | ||
948 | ahc_busspd_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
949 | { | ||
950 | return (ahc_print_register(BUSSPD_parse_table, 5, "BUSSPD", | ||
951 | 0x86, regvalue, cur_col, wrap)); | ||
952 | } | ||
953 | |||
954 | static const ahc_reg_parse_entry_t HS_MAILBOX_parse_table[] = { | ||
955 | { "SEQ_MAILBOX", 0x0f, 0x0f }, | ||
956 | { "HOST_TQINPOS", 0x80, 0x80 }, | ||
957 | { "HOST_MAILBOX", 0xf0, 0xf0 } | ||
958 | }; | ||
959 | |||
960 | int | ||
961 | ahc_hs_mailbox_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
962 | { | ||
963 | return (ahc_print_register(HS_MAILBOX_parse_table, 3, "HS_MAILBOX", | ||
964 | 0x86, regvalue, cur_col, wrap)); | ||
965 | } | ||
966 | |||
967 | static const ahc_reg_parse_entry_t DSPCISTATUS_parse_table[] = { | ||
968 | { "DFTHRSH_100", 0xc0, 0xc0 } | ||
969 | }; | ||
970 | |||
971 | int | ||
972 | ahc_dspcistatus_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
973 | { | ||
974 | return (ahc_print_register(DSPCISTATUS_parse_table, 1, "DSPCISTATUS", | ||
975 | 0x86, regvalue, cur_col, wrap)); | ||
976 | } | ||
977 | |||
978 | static const ahc_reg_parse_entry_t HCNTRL_parse_table[] = { | ||
979 | { "CHIPRST", 0x01, 0x01 }, | ||
980 | { "CHIPRSTACK", 0x01, 0x01 }, | ||
981 | { "INTEN", 0x02, 0x02 }, | ||
982 | { "PAUSE", 0x04, 0x04 }, | ||
983 | { "IRQMS", 0x08, 0x08 }, | ||
984 | { "SWINT", 0x10, 0x10 }, | ||
985 | { "POWRDN", 0x40, 0x40 } | ||
986 | }; | ||
987 | |||
988 | int | ||
989 | ahc_hcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
990 | { | ||
991 | return (ahc_print_register(HCNTRL_parse_table, 7, "HCNTRL", | ||
992 | 0x87, regvalue, cur_col, wrap)); | ||
993 | } | ||
994 | |||
995 | int | ||
996 | ahc_haddr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
997 | { | ||
998 | return (ahc_print_register(NULL, 0, "HADDR", | ||
999 | 0x88, regvalue, cur_col, wrap)); | ||
1000 | } | ||
1001 | |||
1002 | int | ||
1003 | ahc_hcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1004 | { | ||
1005 | return (ahc_print_register(NULL, 0, "HCNT", | ||
1006 | 0x8c, regvalue, cur_col, wrap)); | ||
1007 | } | ||
1008 | |||
1009 | int | ||
1010 | ahc_scbptr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1011 | { | ||
1012 | return (ahc_print_register(NULL, 0, "SCBPTR", | ||
1013 | 0x90, regvalue, cur_col, wrap)); | ||
1014 | } | ||
1015 | |||
1016 | static const ahc_reg_parse_entry_t INTSTAT_parse_table[] = { | ||
1017 | { "SEQINT", 0x01, 0x01 }, | ||
1018 | { "CMDCMPLT", 0x02, 0x02 }, | ||
1019 | { "SCSIINT", 0x04, 0x04 }, | ||
1020 | { "BRKADRINT", 0x08, 0x08 }, | ||
1021 | { "BAD_PHASE", 0x01, 0x01 }, | ||
1022 | { "INT_PEND", 0x0f, 0x0f }, | ||
1023 | { "SEND_REJECT", 0x11, 0x11 }, | ||
1024 | { "PROTO_VIOLATION", 0x21, 0x21 }, | ||
1025 | { "NO_MATCH", 0x31, 0x31 }, | ||
1026 | { "IGN_WIDE_RES", 0x41, 0x41 }, | ||
1027 | { "PDATA_REINIT", 0x51, 0x51 }, | ||
1028 | { "HOST_MSG_LOOP", 0x61, 0x61 }, | ||
1029 | { "BAD_STATUS", 0x71, 0x71 }, | ||
1030 | { "PERR_DETECTED", 0x81, 0x81 }, | ||
1031 | { "DATA_OVERRUN", 0x91, 0x91 }, | ||
1032 | { "MKMSG_FAILED", 0xa1, 0xa1 }, | ||
1033 | { "MISSED_BUSFREE", 0xb1, 0xb1 }, | ||
1034 | { "SCB_MISMATCH", 0xc1, 0xc1 }, | ||
1035 | { "NO_FREE_SCB", 0xd1, 0xd1 }, | ||
1036 | { "OUT_OF_RANGE", 0xe1, 0xe1 }, | ||
1037 | { "SEQINT_MASK", 0xf1, 0xf1 } | ||
1038 | }; | ||
1039 | |||
1040 | int | ||
1041 | ahc_intstat_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1042 | { | ||
1043 | return (ahc_print_register(INTSTAT_parse_table, 21, "INTSTAT", | ||
1044 | 0x91, regvalue, cur_col, wrap)); | ||
1045 | } | ||
1046 | |||
1047 | static const ahc_reg_parse_entry_t CLRINT_parse_table[] = { | ||
1048 | { "CLRSEQINT", 0x01, 0x01 }, | ||
1049 | { "CLRCMDINT", 0x02, 0x02 }, | ||
1050 | { "CLRSCSIINT", 0x04, 0x04 }, | ||
1051 | { "CLRBRKADRINT", 0x08, 0x08 }, | ||
1052 | { "CLRPARERR", 0x10, 0x10 } | ||
1053 | }; | ||
1054 | |||
1055 | int | ||
1056 | ahc_clrint_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1057 | { | ||
1058 | return (ahc_print_register(CLRINT_parse_table, 5, "CLRINT", | ||
1059 | 0x92, regvalue, cur_col, wrap)); | ||
1060 | } | ||
1061 | |||
1062 | static const ahc_reg_parse_entry_t ERROR_parse_table[] = { | 283 | static const ahc_reg_parse_entry_t ERROR_parse_table[] = { |
1063 | { "ILLHADDR", 0x01, 0x01 }, | 284 | { "ILLHADDR", 0x01, 0x01 }, |
1064 | { "ILLSADDR", 0x02, 0x02 }, | 285 | { "ILLSADDR", 0x02, 0x02 }, |
@@ -1115,62 +336,6 @@ ahc_dfstatus_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
1115 | 0x94, regvalue, cur_col, wrap)); | 336 | 0x94, regvalue, cur_col, wrap)); |
1116 | } | 337 | } |
1117 | 338 | ||
1118 | int | ||
1119 | ahc_dfwaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1120 | { | ||
1121 | return (ahc_print_register(NULL, 0, "DFWADDR", | ||
1122 | 0x95, regvalue, cur_col, wrap)); | ||
1123 | } | ||
1124 | |||
1125 | int | ||
1126 | ahc_dfdat_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1127 | { | ||
1128 | return (ahc_print_register(NULL, 0, "DFDAT", | ||
1129 | 0x99, regvalue, cur_col, wrap)); | ||
1130 | } | ||
1131 | |||
1132 | static const ahc_reg_parse_entry_t SCBCNT_parse_table[] = { | ||
1133 | { "SCBAUTO", 0x80, 0x80 }, | ||
1134 | { "SCBCNT_MASK", 0x1f, 0x1f } | ||
1135 | }; | ||
1136 | |||
1137 | int | ||
1138 | ahc_scbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1139 | { | ||
1140 | return (ahc_print_register(SCBCNT_parse_table, 2, "SCBCNT", | ||
1141 | 0x9a, regvalue, cur_col, wrap)); | ||
1142 | } | ||
1143 | |||
1144 | int | ||
1145 | ahc_qinfifo_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1146 | { | ||
1147 | return (ahc_print_register(NULL, 0, "QINFIFO", | ||
1148 | 0x9b, regvalue, cur_col, wrap)); | ||
1149 | } | ||
1150 | |||
1151 | int | ||
1152 | ahc_qoutfifo_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1153 | { | ||
1154 | return (ahc_print_register(NULL, 0, "QOUTFIFO", | ||
1155 | 0x9d, regvalue, cur_col, wrap)); | ||
1156 | } | ||
1157 | |||
1158 | static const ahc_reg_parse_entry_t CRCCONTROL1_parse_table[] = { | ||
1159 | { "TARGCRCCNTEN", 0x04, 0x04 }, | ||
1160 | { "TARGCRCENDEN", 0x08, 0x08 }, | ||
1161 | { "CRCREQCHKEN", 0x10, 0x10 }, | ||
1162 | { "CRCENDCHKEN", 0x20, 0x20 }, | ||
1163 | { "CRCVALCHKEN", 0x40, 0x40 }, | ||
1164 | { "CRCONSEEN", 0x80, 0x80 } | ||
1165 | }; | ||
1166 | |||
1167 | int | ||
1168 | ahc_crccontrol1_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1169 | { | ||
1170 | return (ahc_print_register(CRCCONTROL1_parse_table, 6, "CRCCONTROL1", | ||
1171 | 0x9d, regvalue, cur_col, wrap)); | ||
1172 | } | ||
1173 | |||
1174 | static const ahc_reg_parse_entry_t SCSIPHASE_parse_table[] = { | 339 | static const ahc_reg_parse_entry_t SCSIPHASE_parse_table[] = { |
1175 | { "DATA_OUT_PHASE", 0x01, 0x01 }, | 340 | { "DATA_OUT_PHASE", 0x01, 0x01 }, |
1176 | { "DATA_IN_PHASE", 0x02, 0x02 }, | 341 | { "DATA_IN_PHASE", 0x02, 0x02 }, |
@@ -1188,17 +353,6 @@ ahc_scsiphase_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
1188 | 0x9e, regvalue, cur_col, wrap)); | 353 | 0x9e, regvalue, cur_col, wrap)); |
1189 | } | 354 | } |
1190 | 355 | ||
1191 | static const ahc_reg_parse_entry_t SFUNCT_parse_table[] = { | ||
1192 | { "ALT_MODE", 0x80, 0x80 } | ||
1193 | }; | ||
1194 | |||
1195 | int | ||
1196 | ahc_sfunct_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1197 | { | ||
1198 | return (ahc_print_register(SFUNCT_parse_table, 1, "SFUNCT", | ||
1199 | 0x9f, regvalue, cur_col, wrap)); | ||
1200 | } | ||
1201 | |||
1202 | int | 356 | int |
1203 | ahc_scb_base_print(u_int regvalue, u_int *cur_col, u_int wrap) | 357 | ahc_scb_base_print(u_int regvalue, u_int *cur_col, u_int wrap) |
1204 | { | 358 | { |
@@ -1206,80 +360,6 @@ ahc_scb_base_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
1206 | 0xa0, regvalue, cur_col, wrap)); | 360 | 0xa0, regvalue, cur_col, wrap)); |
1207 | } | 361 | } |
1208 | 362 | ||
1209 | int | ||
1210 | ahc_scb_cdb_ptr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1211 | { | ||
1212 | return (ahc_print_register(NULL, 0, "SCB_CDB_PTR", | ||
1213 | 0xa0, regvalue, cur_col, wrap)); | ||
1214 | } | ||
1215 | |||
1216 | int | ||
1217 | ahc_scb_residual_sgptr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1218 | { | ||
1219 | return (ahc_print_register(NULL, 0, "SCB_RESIDUAL_SGPTR", | ||
1220 | 0xa4, regvalue, cur_col, wrap)); | ||
1221 | } | ||
1222 | |||
1223 | int | ||
1224 | ahc_scb_scsi_status_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1225 | { | ||
1226 | return (ahc_print_register(NULL, 0, "SCB_SCSI_STATUS", | ||
1227 | 0xa8, regvalue, cur_col, wrap)); | ||
1228 | } | ||
1229 | |||
1230 | int | ||
1231 | ahc_scb_target_phases_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1232 | { | ||
1233 | return (ahc_print_register(NULL, 0, "SCB_TARGET_PHASES", | ||
1234 | 0xa9, regvalue, cur_col, wrap)); | ||
1235 | } | ||
1236 | |||
1237 | int | ||
1238 | ahc_scb_target_data_dir_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1239 | { | ||
1240 | return (ahc_print_register(NULL, 0, "SCB_TARGET_DATA_DIR", | ||
1241 | 0xaa, regvalue, cur_col, wrap)); | ||
1242 | } | ||
1243 | |||
1244 | int | ||
1245 | ahc_scb_target_itag_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1246 | { | ||
1247 | return (ahc_print_register(NULL, 0, "SCB_TARGET_ITAG", | ||
1248 | 0xab, regvalue, cur_col, wrap)); | ||
1249 | } | ||
1250 | |||
1251 | int | ||
1252 | ahc_scb_dataptr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1253 | { | ||
1254 | return (ahc_print_register(NULL, 0, "SCB_DATAPTR", | ||
1255 | 0xac, regvalue, cur_col, wrap)); | ||
1256 | } | ||
1257 | |||
1258 | static const ahc_reg_parse_entry_t SCB_DATACNT_parse_table[] = { | ||
1259 | { "SG_LAST_SEG", 0x80, 0x80 }, | ||
1260 | { "SG_HIGH_ADDR_BITS", 0x7f, 0x7f } | ||
1261 | }; | ||
1262 | |||
1263 | int | ||
1264 | ahc_scb_datacnt_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1265 | { | ||
1266 | return (ahc_print_register(SCB_DATACNT_parse_table, 2, "SCB_DATACNT", | ||
1267 | 0xb0, regvalue, cur_col, wrap)); | ||
1268 | } | ||
1269 | |||
1270 | static const ahc_reg_parse_entry_t SCB_SGPTR_parse_table[] = { | ||
1271 | { "SG_LIST_NULL", 0x01, 0x01 }, | ||
1272 | { "SG_FULL_RESID", 0x02, 0x02 }, | ||
1273 | { "SG_RESID_VALID", 0x04, 0x04 } | ||
1274 | }; | ||
1275 | |||
1276 | int | ||
1277 | ahc_scb_sgptr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1278 | { | ||
1279 | return (ahc_print_register(SCB_SGPTR_parse_table, 3, "SCB_SGPTR", | ||
1280 | 0xb4, regvalue, cur_col, wrap)); | ||
1281 | } | ||
1282 | |||
1283 | static const ahc_reg_parse_entry_t SCB_CONTROL_parse_table[] = { | 363 | static const ahc_reg_parse_entry_t SCB_CONTROL_parse_table[] = { |
1284 | { "DISCONNECTED", 0x04, 0x04 }, | 364 | { "DISCONNECTED", 0x04, 0x04 }, |
1285 | { "ULTRAENB", 0x08, 0x08 }, | 365 | { "ULTRAENB", 0x08, 0x08 }, |
@@ -1331,248 +411,3 @@ ahc_scb_tag_print(u_int regvalue, u_int *cur_col, u_int wrap) | |||
1331 | 0xbb, regvalue, cur_col, wrap)); | 411 | 0xbb, regvalue, cur_col, wrap)); |
1332 | } | 412 | } |
1333 | 413 | ||
1334 | int | ||
1335 | ahc_scb_cdb_len_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1336 | { | ||
1337 | return (ahc_print_register(NULL, 0, "SCB_CDB_LEN", | ||
1338 | 0xbc, regvalue, cur_col, wrap)); | ||
1339 | } | ||
1340 | |||
1341 | int | ||
1342 | ahc_scb_scsirate_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1343 | { | ||
1344 | return (ahc_print_register(NULL, 0, "SCB_SCSIRATE", | ||
1345 | 0xbd, regvalue, cur_col, wrap)); | ||
1346 | } | ||
1347 | |||
1348 | int | ||
1349 | ahc_scb_scsioffset_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1350 | { | ||
1351 | return (ahc_print_register(NULL, 0, "SCB_SCSIOFFSET", | ||
1352 | 0xbe, regvalue, cur_col, wrap)); | ||
1353 | } | ||
1354 | |||
1355 | int | ||
1356 | ahc_scb_next_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1357 | { | ||
1358 | return (ahc_print_register(NULL, 0, "SCB_NEXT", | ||
1359 | 0xbf, regvalue, cur_col, wrap)); | ||
1360 | } | ||
1361 | |||
1362 | static const ahc_reg_parse_entry_t SEECTL_2840_parse_table[] = { | ||
1363 | { "DO_2840", 0x01, 0x01 }, | ||
1364 | { "CK_2840", 0x02, 0x02 }, | ||
1365 | { "CS_2840", 0x04, 0x04 } | ||
1366 | }; | ||
1367 | |||
1368 | int | ||
1369 | ahc_seectl_2840_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1370 | { | ||
1371 | return (ahc_print_register(SEECTL_2840_parse_table, 3, "SEECTL_2840", | ||
1372 | 0xc0, regvalue, cur_col, wrap)); | ||
1373 | } | ||
1374 | |||
1375 | static const ahc_reg_parse_entry_t STATUS_2840_parse_table[] = { | ||
1376 | { "DI_2840", 0x01, 0x01 }, | ||
1377 | { "EEPROM_TF", 0x80, 0x80 }, | ||
1378 | { "ADSEL", 0x1e, 0x1e }, | ||
1379 | { "BIOS_SEL", 0x60, 0x60 } | ||
1380 | }; | ||
1381 | |||
1382 | int | ||
1383 | ahc_status_2840_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1384 | { | ||
1385 | return (ahc_print_register(STATUS_2840_parse_table, 4, "STATUS_2840", | ||
1386 | 0xc1, regvalue, cur_col, wrap)); | ||
1387 | } | ||
1388 | |||
1389 | int | ||
1390 | ahc_scb_64_btt_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1391 | { | ||
1392 | return (ahc_print_register(NULL, 0, "SCB_64_BTT", | ||
1393 | 0xd0, regvalue, cur_col, wrap)); | ||
1394 | } | ||
1395 | |||
1396 | int | ||
1397 | ahc_cchaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1398 | { | ||
1399 | return (ahc_print_register(NULL, 0, "CCHADDR", | ||
1400 | 0xe0, regvalue, cur_col, wrap)); | ||
1401 | } | ||
1402 | |||
1403 | int | ||
1404 | ahc_cchcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1405 | { | ||
1406 | return (ahc_print_register(NULL, 0, "CCHCNT", | ||
1407 | 0xe8, regvalue, cur_col, wrap)); | ||
1408 | } | ||
1409 | |||
1410 | int | ||
1411 | ahc_ccsgram_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1412 | { | ||
1413 | return (ahc_print_register(NULL, 0, "CCSGRAM", | ||
1414 | 0xe9, regvalue, cur_col, wrap)); | ||
1415 | } | ||
1416 | |||
1417 | int | ||
1418 | ahc_ccsgaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1419 | { | ||
1420 | return (ahc_print_register(NULL, 0, "CCSGADDR", | ||
1421 | 0xea, regvalue, cur_col, wrap)); | ||
1422 | } | ||
1423 | |||
1424 | static const ahc_reg_parse_entry_t CCSGCTL_parse_table[] = { | ||
1425 | { "CCSGRESET", 0x01, 0x01 }, | ||
1426 | { "SG_FETCH_NEEDED", 0x02, 0x02 }, | ||
1427 | { "CCSGEN", 0x08, 0x08 }, | ||
1428 | { "CCSGDONE", 0x80, 0x80 } | ||
1429 | }; | ||
1430 | |||
1431 | int | ||
1432 | ahc_ccsgctl_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1433 | { | ||
1434 | return (ahc_print_register(CCSGCTL_parse_table, 4, "CCSGCTL", | ||
1435 | 0xeb, regvalue, cur_col, wrap)); | ||
1436 | } | ||
1437 | |||
1438 | int | ||
1439 | ahc_ccscbram_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1440 | { | ||
1441 | return (ahc_print_register(NULL, 0, "CCSCBRAM", | ||
1442 | 0xec, regvalue, cur_col, wrap)); | ||
1443 | } | ||
1444 | |||
1445 | int | ||
1446 | ahc_ccscbaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1447 | { | ||
1448 | return (ahc_print_register(NULL, 0, "CCSCBADDR", | ||
1449 | 0xed, regvalue, cur_col, wrap)); | ||
1450 | } | ||
1451 | |||
1452 | static const ahc_reg_parse_entry_t CCSCBCTL_parse_table[] = { | ||
1453 | { "CCSCBRESET", 0x01, 0x01 }, | ||
1454 | { "CCSCBDIR", 0x04, 0x04 }, | ||
1455 | { "CCSCBEN", 0x08, 0x08 }, | ||
1456 | { "CCARREN", 0x10, 0x10 }, | ||
1457 | { "ARRDONE", 0x40, 0x40 }, | ||
1458 | { "CCSCBDONE", 0x80, 0x80 } | ||
1459 | }; | ||
1460 | |||
1461 | int | ||
1462 | ahc_ccscbctl_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1463 | { | ||
1464 | return (ahc_print_register(CCSCBCTL_parse_table, 6, "CCSCBCTL", | ||
1465 | 0xee, regvalue, cur_col, wrap)); | ||
1466 | } | ||
1467 | |||
1468 | int | ||
1469 | ahc_ccscbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1470 | { | ||
1471 | return (ahc_print_register(NULL, 0, "CCSCBCNT", | ||
1472 | 0xef, regvalue, cur_col, wrap)); | ||
1473 | } | ||
1474 | |||
1475 | int | ||
1476 | ahc_scbbaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1477 | { | ||
1478 | return (ahc_print_register(NULL, 0, "SCBBADDR", | ||
1479 | 0xf0, regvalue, cur_col, wrap)); | ||
1480 | } | ||
1481 | |||
1482 | int | ||
1483 | ahc_ccscbptr_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1484 | { | ||
1485 | return (ahc_print_register(NULL, 0, "CCSCBPTR", | ||
1486 | 0xf1, regvalue, cur_col, wrap)); | ||
1487 | } | ||
1488 | |||
1489 | int | ||
1490 | ahc_hnscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1491 | { | ||
1492 | return (ahc_print_register(NULL, 0, "HNSCB_QOFF", | ||
1493 | 0xf4, regvalue, cur_col, wrap)); | ||
1494 | } | ||
1495 | |||
1496 | int | ||
1497 | ahc_snscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1498 | { | ||
1499 | return (ahc_print_register(NULL, 0, "SNSCB_QOFF", | ||
1500 | 0xf6, regvalue, cur_col, wrap)); | ||
1501 | } | ||
1502 | |||
1503 | int | ||
1504 | ahc_sdscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1505 | { | ||
1506 | return (ahc_print_register(NULL, 0, "SDSCB_QOFF", | ||
1507 | 0xf8, regvalue, cur_col, wrap)); | ||
1508 | } | ||
1509 | |||
1510 | static const ahc_reg_parse_entry_t QOFF_CTLSTA_parse_table[] = { | ||
1511 | { "SDSCB_ROLLOVER", 0x10, 0x10 }, | ||
1512 | { "SNSCB_ROLLOVER", 0x20, 0x20 }, | ||
1513 | { "SCB_AVAIL", 0x40, 0x40 }, | ||
1514 | { "SCB_QSIZE_256", 0x06, 0x06 }, | ||
1515 | { "SCB_QSIZE", 0x07, 0x07 } | ||
1516 | }; | ||
1517 | |||
1518 | int | ||
1519 | ahc_qoff_ctlsta_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1520 | { | ||
1521 | return (ahc_print_register(QOFF_CTLSTA_parse_table, 5, "QOFF_CTLSTA", | ||
1522 | 0xfa, regvalue, cur_col, wrap)); | ||
1523 | } | ||
1524 | |||
1525 | static const ahc_reg_parse_entry_t DFF_THRSH_parse_table[] = { | ||
1526 | { "RD_DFTHRSH_MIN", 0x00, 0x00 }, | ||
1527 | { "WR_DFTHRSH_MIN", 0x00, 0x00 }, | ||
1528 | { "RD_DFTHRSH_25", 0x01, 0x01 }, | ||
1529 | { "RD_DFTHRSH_50", 0x02, 0x02 }, | ||
1530 | { "RD_DFTHRSH_63", 0x03, 0x03 }, | ||
1531 | { "RD_DFTHRSH_75", 0x04, 0x04 }, | ||
1532 | { "RD_DFTHRSH_85", 0x05, 0x05 }, | ||
1533 | { "RD_DFTHRSH_90", 0x06, 0x06 }, | ||
1534 | { "RD_DFTHRSH", 0x07, 0x07 }, | ||
1535 | { "RD_DFTHRSH_MAX", 0x07, 0x07 }, | ||
1536 | { "WR_DFTHRSH_25", 0x10, 0x10 }, | ||
1537 | { "WR_DFTHRSH_50", 0x20, 0x20 }, | ||
1538 | { "WR_DFTHRSH_63", 0x30, 0x30 }, | ||
1539 | { "WR_DFTHRSH_75", 0x40, 0x40 }, | ||
1540 | { "WR_DFTHRSH_85", 0x50, 0x50 }, | ||
1541 | { "WR_DFTHRSH_90", 0x60, 0x60 }, | ||
1542 | { "WR_DFTHRSH", 0x70, 0x70 }, | ||
1543 | { "WR_DFTHRSH_MAX", 0x70, 0x70 } | ||
1544 | }; | ||
1545 | |||
1546 | int | ||
1547 | ahc_dff_thrsh_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1548 | { | ||
1549 | return (ahc_print_register(DFF_THRSH_parse_table, 18, "DFF_THRSH", | ||
1550 | 0xfb, regvalue, cur_col, wrap)); | ||
1551 | } | ||
1552 | |||
1553 | static const ahc_reg_parse_entry_t SG_CACHE_SHADOW_parse_table[] = { | ||
1554 | { "LAST_SEG_DONE", 0x01, 0x01 }, | ||
1555 | { "LAST_SEG", 0x02, 0x02 }, | ||
1556 | { "SG_ADDR_MASK", 0xf8, 0xf8 } | ||
1557 | }; | ||
1558 | |||
1559 | int | ||
1560 | ahc_sg_cache_shadow_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1561 | { | ||
1562 | return (ahc_print_register(SG_CACHE_SHADOW_parse_table, 3, "SG_CACHE_SHADOW", | ||
1563 | 0xfc, regvalue, cur_col, wrap)); | ||
1564 | } | ||
1565 | |||
1566 | static const ahc_reg_parse_entry_t SG_CACHE_PRE_parse_table[] = { | ||
1567 | { "LAST_SEG_DONE", 0x01, 0x01 }, | ||
1568 | { "LAST_SEG", 0x02, 0x02 }, | ||
1569 | { "SG_ADDR_MASK", 0xf8, 0xf8 } | ||
1570 | }; | ||
1571 | |||
1572 | int | ||
1573 | ahc_sg_cache_pre_print(u_int regvalue, u_int *cur_col, u_int wrap) | ||
1574 | { | ||
1575 | return (ahc_print_register(SG_CACHE_PRE_parse_table, 3, "SG_CACHE_PRE", | ||
1576 | 0xfc, regvalue, cur_col, wrap)); | ||
1577 | } | ||
1578 | |||
diff --git a/drivers/scsi/aic7xxx/aicasm/aicasm_gram.y b/drivers/scsi/aic7xxx/aicasm/aicasm_gram.y index 81be6a261cc8..e4064433842e 100644 --- a/drivers/scsi/aic7xxx/aicasm/aicasm_gram.y +++ b/drivers/scsi/aic7xxx/aicasm/aicasm_gram.y | |||
@@ -147,6 +147,8 @@ void yyerror(const char *string); | |||
147 | 147 | ||
148 | %token T_ACCESS_MODE | 148 | %token T_ACCESS_MODE |
149 | 149 | ||
150 | %token T_DONT_GENERATE_DEBUG_CODE | ||
151 | |||
150 | %token T_MODES | 152 | %token T_MODES |
151 | 153 | ||
152 | %token T_DEFINE | 154 | %token T_DEFINE |
@@ -357,6 +359,7 @@ reg_attribute: | |||
357 | | size | 359 | | size |
358 | | count | 360 | | count |
359 | | access_mode | 361 | | access_mode |
362 | | dont_generate_debug_code | ||
360 | | modes | 363 | | modes |
361 | | field_defn | 364 | | field_defn |
362 | | enum_defn | 365 | | enum_defn |
@@ -410,6 +413,13 @@ access_mode: | |||
410 | } | 413 | } |
411 | ; | 414 | ; |
412 | 415 | ||
416 | dont_generate_debug_code: | ||
417 | T_DONT_GENERATE_DEBUG_CODE | ||
418 | { | ||
419 | cur_symbol->dont_generate_debug_code = 1; | ||
420 | } | ||
421 | ; | ||
422 | |||
413 | modes: | 423 | modes: |
414 | T_MODES mode_list | 424 | T_MODES mode_list |
415 | { | 425 | { |
diff --git a/drivers/scsi/aic7xxx/aicasm/aicasm_scan.l b/drivers/scsi/aic7xxx/aicasm/aicasm_scan.l index 2c7f02daf88d..93c8667cd704 100644 --- a/drivers/scsi/aic7xxx/aicasm/aicasm_scan.l +++ b/drivers/scsi/aic7xxx/aicasm/aicasm_scan.l | |||
@@ -164,6 +164,7 @@ download { return T_DOWNLOAD; } | |||
164 | address { return T_ADDRESS; } | 164 | address { return T_ADDRESS; } |
165 | count { return T_COUNT; } | 165 | count { return T_COUNT; } |
166 | access_mode { return T_ACCESS_MODE; } | 166 | access_mode { return T_ACCESS_MODE; } |
167 | dont_generate_debug_code { return T_DONT_GENERATE_DEBUG_CODE; } | ||
167 | modes { return T_MODES; } | 168 | modes { return T_MODES; } |
168 | RW|RO|WO { | 169 | RW|RO|WO { |
169 | if (strcmp(yytext, "RW") == 0) | 170 | if (strcmp(yytext, "RW") == 0) |
diff --git a/drivers/scsi/aic7xxx/aicasm/aicasm_symbol.c b/drivers/scsi/aic7xxx/aicasm/aicasm_symbol.c index fcd357872b43..078ed600f47a 100644 --- a/drivers/scsi/aic7xxx/aicasm/aicasm_symbol.c +++ b/drivers/scsi/aic7xxx/aicasm/aicasm_symbol.c | |||
@@ -539,6 +539,9 @@ symtable_dump(FILE *ofile, FILE *dfile) | |||
539 | aic_print_include(dfile, stock_include_file); | 539 | aic_print_include(dfile, stock_include_file); |
540 | SLIST_FOREACH(curnode, ®isters, links) { | 540 | SLIST_FOREACH(curnode, ®isters, links) { |
541 | 541 | ||
542 | if (curnode->symbol->dont_generate_debug_code) | ||
543 | continue; | ||
544 | |||
542 | switch(curnode->symbol->type) { | 545 | switch(curnode->symbol->type) { |
543 | case REGISTER: | 546 | case REGISTER: |
544 | case SCBLOC: | 547 | case SCBLOC: |
diff --git a/drivers/scsi/aic7xxx/aicasm/aicasm_symbol.h b/drivers/scsi/aic7xxx/aicasm/aicasm_symbol.h index 05190c1a2fb7..2ba73ae7c777 100644 --- a/drivers/scsi/aic7xxx/aicasm/aicasm_symbol.h +++ b/drivers/scsi/aic7xxx/aicasm/aicasm_symbol.h | |||
@@ -137,7 +137,8 @@ typedef struct symbol { | |||
137 | struct label_info *linfo; | 137 | struct label_info *linfo; |
138 | struct cond_info *condinfo; | 138 | struct cond_info *condinfo; |
139 | struct macro_info *macroinfo; | 139 | struct macro_info *macroinfo; |
140 | }info; | 140 | } info; |
141 | int dont_generate_debug_code; | ||
141 | } symbol_t; | 142 | } symbol_t; |
142 | 143 | ||
143 | typedef struct symbol_ref { | 144 | typedef struct symbol_ref { |
diff --git a/drivers/scsi/device_handler/scsi_dh_rdac.c b/drivers/scsi/device_handler/scsi_dh_rdac.c index a43c3ed4df28..3d50cabca7ee 100644 --- a/drivers/scsi/device_handler/scsi_dh_rdac.c +++ b/drivers/scsi/device_handler/scsi_dh_rdac.c | |||
@@ -401,6 +401,9 @@ static int check_ownership(struct scsi_device *sdev, struct rdac_dh_data *h) | |||
401 | } | 401 | } |
402 | } | 402 | } |
403 | 403 | ||
404 | if (h->lun_state == RDAC_LUN_UNOWNED) | ||
405 | h->state = RDAC_STATE_PASSIVE; | ||
406 | |||
404 | return err; | 407 | return err; |
405 | } | 408 | } |
406 | 409 | ||
diff --git a/drivers/scsi/ipr.c b/drivers/scsi/ipr.c index 098739deb02e..ded854a6dd35 100644 --- a/drivers/scsi/ipr.c +++ b/drivers/scsi/ipr.c | |||
@@ -2456,20 +2456,14 @@ static ssize_t ipr_read_trace(struct kobject *kobj, | |||
2456 | struct Scsi_Host *shost = class_to_shost(dev); | 2456 | struct Scsi_Host *shost = class_to_shost(dev); |
2457 | struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata; | 2457 | struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata; |
2458 | unsigned long lock_flags = 0; | 2458 | unsigned long lock_flags = 0; |
2459 | int size = IPR_TRACE_SIZE; | 2459 | ssize_t ret; |
2460 | char *src = (char *)ioa_cfg->trace; | ||
2461 | |||
2462 | if (off > size) | ||
2463 | return 0; | ||
2464 | if (off + count > size) { | ||
2465 | size -= off; | ||
2466 | count = size; | ||
2467 | } | ||
2468 | 2460 | ||
2469 | spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags); | 2461 | spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags); |
2470 | memcpy(buf, &src[off], count); | 2462 | ret = memory_read_from_buffer(buf, count, &off, ioa_cfg->trace, |
2463 | IPR_TRACE_SIZE); | ||
2471 | spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags); | 2464 | spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags); |
2472 | return count; | 2465 | |
2466 | return ret; | ||
2473 | } | 2467 | } |
2474 | 2468 | ||
2475 | static struct bin_attribute ipr_trace_attr = { | 2469 | static struct bin_attribute ipr_trace_attr = { |
diff --git a/drivers/scsi/scsi_lib.c b/drivers/scsi/scsi_lib.c index e5a9526d2037..f5d3b96890dc 100644 --- a/drivers/scsi/scsi_lib.c +++ b/drivers/scsi/scsi_lib.c | |||
@@ -529,6 +529,14 @@ static void scsi_single_lun_run(struct scsi_device *current_sdev) | |||
529 | spin_unlock_irqrestore(shost->host_lock, flags); | 529 | spin_unlock_irqrestore(shost->host_lock, flags); |
530 | } | 530 | } |
531 | 531 | ||
532 | static inline int scsi_device_is_busy(struct scsi_device *sdev) | ||
533 | { | ||
534 | if (sdev->device_busy >= sdev->queue_depth || sdev->device_blocked) | ||
535 | return 1; | ||
536 | |||
537 | return 0; | ||
538 | } | ||
539 | |||
532 | static inline int scsi_target_is_busy(struct scsi_target *starget) | 540 | static inline int scsi_target_is_busy(struct scsi_target *starget) |
533 | { | 541 | { |
534 | return ((starget->can_queue > 0 && | 542 | return ((starget->can_queue > 0 && |
@@ -536,6 +544,15 @@ static inline int scsi_target_is_busy(struct scsi_target *starget) | |||
536 | starget->target_blocked); | 544 | starget->target_blocked); |
537 | } | 545 | } |
538 | 546 | ||
547 | static inline int scsi_host_is_busy(struct Scsi_Host *shost) | ||
548 | { | ||
549 | if ((shost->can_queue > 0 && shost->host_busy >= shost->can_queue) || | ||
550 | shost->host_blocked || shost->host_self_blocked) | ||
551 | return 1; | ||
552 | |||
553 | return 0; | ||
554 | } | ||
555 | |||
539 | /* | 556 | /* |
540 | * Function: scsi_run_queue() | 557 | * Function: scsi_run_queue() |
541 | * | 558 | * |
@@ -558,11 +575,7 @@ static void scsi_run_queue(struct request_queue *q) | |||
558 | scsi_single_lun_run(sdev); | 575 | scsi_single_lun_run(sdev); |
559 | 576 | ||
560 | spin_lock_irqsave(shost->host_lock, flags); | 577 | spin_lock_irqsave(shost->host_lock, flags); |
561 | while (!list_empty(&shost->starved_list) && | 578 | while (!list_empty(&shost->starved_list) && !scsi_host_is_busy(shost)) { |
562 | !shost->host_blocked && !shost->host_self_blocked && | ||
563 | !((shost->can_queue > 0) && | ||
564 | (shost->host_busy >= shost->can_queue))) { | ||
565 | |||
566 | int flagset; | 579 | int flagset; |
567 | 580 | ||
568 | /* | 581 | /* |
@@ -1348,8 +1361,6 @@ int scsi_prep_fn(struct request_queue *q, struct request *req) | |||
1348 | static inline int scsi_dev_queue_ready(struct request_queue *q, | 1361 | static inline int scsi_dev_queue_ready(struct request_queue *q, |
1349 | struct scsi_device *sdev) | 1362 | struct scsi_device *sdev) |
1350 | { | 1363 | { |
1351 | if (sdev->device_busy >= sdev->queue_depth) | ||
1352 | return 0; | ||
1353 | if (sdev->device_busy == 0 && sdev->device_blocked) { | 1364 | if (sdev->device_busy == 0 && sdev->device_blocked) { |
1354 | /* | 1365 | /* |
1355 | * unblock after device_blocked iterates to zero | 1366 | * unblock after device_blocked iterates to zero |
@@ -1363,7 +1374,7 @@ static inline int scsi_dev_queue_ready(struct request_queue *q, | |||
1363 | return 0; | 1374 | return 0; |
1364 | } | 1375 | } |
1365 | } | 1376 | } |
1366 | if (sdev->device_blocked) | 1377 | if (scsi_device_is_busy(sdev)) |
1367 | return 0; | 1378 | return 0; |
1368 | 1379 | ||
1369 | return 1; | 1380 | return 1; |
@@ -1440,8 +1451,7 @@ static inline int scsi_host_queue_ready(struct request_queue *q, | |||
1440 | return 0; | 1451 | return 0; |
1441 | } | 1452 | } |
1442 | } | 1453 | } |
1443 | if ((shost->can_queue > 0 && shost->host_busy >= shost->can_queue) || | 1454 | if (scsi_host_is_busy(shost)) { |
1444 | shost->host_blocked || shost->host_self_blocked) { | ||
1445 | if (list_empty(&sdev->starved_entry)) | 1455 | if (list_empty(&sdev->starved_entry)) |
1446 | list_add_tail(&sdev->starved_entry, &shost->starved_list); | 1456 | list_add_tail(&sdev->starved_entry, &shost->starved_list); |
1447 | return 0; | 1457 | return 0; |
@@ -1455,6 +1465,37 @@ static inline int scsi_host_queue_ready(struct request_queue *q, | |||
1455 | } | 1465 | } |
1456 | 1466 | ||
1457 | /* | 1467 | /* |
1468 | * Busy state exporting function for request stacking drivers. | ||
1469 | * | ||
1470 | * For efficiency, no lock is taken to check the busy state of | ||
1471 | * shost/starget/sdev, since the returned value is not guaranteed and | ||
1472 | * may be changed after request stacking drivers call the function, | ||
1473 | * regardless of taking lock or not. | ||
1474 | * | ||
1475 | * When scsi can't dispatch I/Os anymore and needs to kill I/Os | ||
1476 | * (e.g. !sdev), scsi needs to return 'not busy'. | ||
1477 | * Otherwise, request stacking drivers may hold requests forever. | ||
1478 | */ | ||
1479 | static int scsi_lld_busy(struct request_queue *q) | ||
1480 | { | ||
1481 | struct scsi_device *sdev = q->queuedata; | ||
1482 | struct Scsi_Host *shost; | ||
1483 | struct scsi_target *starget; | ||
1484 | |||
1485 | if (!sdev) | ||
1486 | return 0; | ||
1487 | |||
1488 | shost = sdev->host; | ||
1489 | starget = scsi_target(sdev); | ||
1490 | |||
1491 | if (scsi_host_in_recovery(shost) || scsi_host_is_busy(shost) || | ||
1492 | scsi_target_is_busy(starget) || scsi_device_is_busy(sdev)) | ||
1493 | return 1; | ||
1494 | |||
1495 | return 0; | ||
1496 | } | ||
1497 | |||
1498 | /* | ||
1458 | * Kill a request for a dead device | 1499 | * Kill a request for a dead device |
1459 | */ | 1500 | */ |
1460 | static void scsi_kill_request(struct request *req, struct request_queue *q) | 1501 | static void scsi_kill_request(struct request *req, struct request_queue *q) |
@@ -1757,6 +1798,7 @@ struct request_queue *scsi_alloc_queue(struct scsi_device *sdev) | |||
1757 | blk_queue_prep_rq(q, scsi_prep_fn); | 1798 | blk_queue_prep_rq(q, scsi_prep_fn); |
1758 | blk_queue_softirq_done(q, scsi_softirq_done); | 1799 | blk_queue_softirq_done(q, scsi_softirq_done); |
1759 | blk_queue_rq_timed_out(q, scsi_times_out); | 1800 | blk_queue_rq_timed_out(q, scsi_times_out); |
1801 | blk_queue_lld_busy(q, scsi_lld_busy); | ||
1760 | return q; | 1802 | return q; |
1761 | } | 1803 | } |
1762 | 1804 | ||
@@ -2105,22 +2147,21 @@ scsi_test_unit_ready(struct scsi_device *sdev, int timeout, int retries, | |||
2105 | do { | 2147 | do { |
2106 | result = scsi_execute_req(sdev, cmd, DMA_NONE, NULL, 0, sshdr, | 2148 | result = scsi_execute_req(sdev, cmd, DMA_NONE, NULL, 0, sshdr, |
2107 | timeout, retries); | 2149 | timeout, retries); |
2108 | } while ((driver_byte(result) & DRIVER_SENSE) && | 2150 | if (sdev->removable && scsi_sense_valid(sshdr) && |
2109 | sshdr && sshdr->sense_key == UNIT_ATTENTION && | 2151 | sshdr->sense_key == UNIT_ATTENTION) |
2110 | --retries); | 2152 | sdev->changed = 1; |
2153 | } while (scsi_sense_valid(sshdr) && | ||
2154 | sshdr->sense_key == UNIT_ATTENTION && --retries); | ||
2111 | 2155 | ||
2112 | if (!sshdr) | 2156 | if (!sshdr) |
2113 | /* could not allocate sense buffer, so can't process it */ | 2157 | /* could not allocate sense buffer, so can't process it */ |
2114 | return result; | 2158 | return result; |
2115 | 2159 | ||
2116 | if ((driver_byte(result) & DRIVER_SENSE) && sdev->removable) { | 2160 | if (sdev->removable && scsi_sense_valid(sshdr) && |
2117 | 2161 | (sshdr->sense_key == UNIT_ATTENTION || | |
2118 | if ((scsi_sense_valid(sshdr)) && | 2162 | sshdr->sense_key == NOT_READY)) { |
2119 | ((sshdr->sense_key == UNIT_ATTENTION) || | 2163 | sdev->changed = 1; |
2120 | (sshdr->sense_key == NOT_READY))) { | 2164 | result = 0; |
2121 | sdev->changed = 1; | ||
2122 | result = 0; | ||
2123 | } | ||
2124 | } | 2165 | } |
2125 | if (!sshdr_external) | 2166 | if (!sshdr_external) |
2126 | kfree(sshdr); | 2167 | kfree(sshdr); |
diff --git a/drivers/scsi/scsi_netlink.c b/drivers/scsi/scsi_netlink.c index b37e133de805..723fdecd91bd 100644 --- a/drivers/scsi/scsi_netlink.c +++ b/drivers/scsi/scsi_netlink.c | |||
@@ -205,16 +205,13 @@ static struct notifier_block scsi_netlink_notifier = { | |||
205 | }; | 205 | }; |
206 | 206 | ||
207 | 207 | ||
208 | /** | 208 | /* |
209 | * GENERIC SCSI transport receive and event handlers | 209 | * GENERIC SCSI transport receive and event handlers |
210 | **/ | 210 | */ |
211 | 211 | ||
212 | /** | 212 | /** |
213 | * scsi_generic_msg_handler - receive message handler for GENERIC transport | 213 | * scsi_generic_msg_handler - receive message handler for GENERIC transport messages |
214 | * messages | ||
215 | * | ||
216 | * @skb: socket receive buffer | 214 | * @skb: socket receive buffer |
217 | * | ||
218 | **/ | 215 | **/ |
219 | static int | 216 | static int |
220 | scsi_generic_msg_handler(struct sk_buff *skb) | 217 | scsi_generic_msg_handler(struct sk_buff *skb) |
diff --git a/drivers/scsi/sd.c b/drivers/scsi/sd.c index 43f34c73df12..c9e1242eaf25 100644 --- a/drivers/scsi/sd.c +++ b/drivers/scsi/sd.c | |||
@@ -1049,7 +1049,6 @@ static int sd_done(struct scsi_cmnd *SCpnt) | |||
1049 | good_bytes = sd_completed_bytes(SCpnt); | 1049 | good_bytes = sd_completed_bytes(SCpnt); |
1050 | break; | 1050 | break; |
1051 | case RECOVERED_ERROR: | 1051 | case RECOVERED_ERROR: |
1052 | case NO_SENSE: | ||
1053 | /* Inform the user, but make sure that it's not treated | 1052 | /* Inform the user, but make sure that it's not treated |
1054 | * as a hard error. | 1053 | * as a hard error. |
1055 | */ | 1054 | */ |
@@ -1058,6 +1057,15 @@ static int sd_done(struct scsi_cmnd *SCpnt) | |||
1058 | memset(SCpnt->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE); | 1057 | memset(SCpnt->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE); |
1059 | good_bytes = scsi_bufflen(SCpnt); | 1058 | good_bytes = scsi_bufflen(SCpnt); |
1060 | break; | 1059 | break; |
1060 | case NO_SENSE: | ||
1061 | /* This indicates a false check condition, so ignore it. An | ||
1062 | * unknown amount of data was transferred so treat it as an | ||
1063 | * error. | ||
1064 | */ | ||
1065 | scsi_print_sense("sd", SCpnt); | ||
1066 | SCpnt->result = 0; | ||
1067 | memset(SCpnt->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE); | ||
1068 | break; | ||
1061 | case ABORTED_COMMAND: | 1069 | case ABORTED_COMMAND: |
1062 | if (sshdr.asc == 0x10) { /* DIF: Disk detected corruption */ | 1070 | if (sshdr.asc == 0x10) { /* DIF: Disk detected corruption */ |
1063 | scsi_print_result(SCpnt); | 1071 | scsi_print_result(SCpnt); |
@@ -1071,15 +1079,6 @@ static int sd_done(struct scsi_cmnd *SCpnt) | |||
1071 | scsi_print_sense("sd", SCpnt); | 1079 | scsi_print_sense("sd", SCpnt); |
1072 | good_bytes = sd_completed_bytes(SCpnt); | 1080 | good_bytes = sd_completed_bytes(SCpnt); |
1073 | } | 1081 | } |
1074 | if (!scsi_device_protection(SCpnt->device) && | ||
1075 | SCpnt->device->use_10_for_rw && | ||
1076 | (SCpnt->cmnd[0] == READ_10 || | ||
1077 | SCpnt->cmnd[0] == WRITE_10)) | ||
1078 | SCpnt->device->use_10_for_rw = 0; | ||
1079 | if (SCpnt->device->use_10_for_ms && | ||
1080 | (SCpnt->cmnd[0] == MODE_SENSE_10 || | ||
1081 | SCpnt->cmnd[0] == MODE_SELECT_10)) | ||
1082 | SCpnt->device->use_10_for_ms = 0; | ||
1083 | break; | 1082 | break; |
1084 | default: | 1083 | default: |
1085 | break; | 1084 | break; |
@@ -1432,7 +1431,7 @@ got_data: | |||
1432 | 1431 | ||
1433 | { | 1432 | { |
1434 | char cap_str_2[10], cap_str_10[10]; | 1433 | char cap_str_2[10], cap_str_10[10]; |
1435 | u64 sz = sdkp->capacity << ffz(~sector_size); | 1434 | u64 sz = (u64)sdkp->capacity << ilog2(sector_size); |
1436 | 1435 | ||
1437 | string_get_size(sz, STRING_UNITS_2, cap_str_2, | 1436 | string_get_size(sz, STRING_UNITS_2, cap_str_2, |
1438 | sizeof(cap_str_2)); | 1437 | sizeof(cap_str_2)); |
diff --git a/drivers/scsi/sun3x_esp.c b/drivers/scsi/sun3x_esp.c index 7514b3a0390e..34a99620e5bd 100644 --- a/drivers/scsi/sun3x_esp.c +++ b/drivers/scsi/sun3x_esp.c | |||
@@ -213,7 +213,7 @@ static int __devinit esp_sun3x_probe(struct platform_device *dev) | |||
213 | esp->ops = &sun3x_esp_ops; | 213 | esp->ops = &sun3x_esp_ops; |
214 | 214 | ||
215 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); | 215 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); |
216 | if (!res && !res->start) | 216 | if (!res || !res->start) |
217 | goto fail_unlink; | 217 | goto fail_unlink; |
218 | 218 | ||
219 | esp->regs = ioremap_nocache(res->start, 0x20); | 219 | esp->regs = ioremap_nocache(res->start, 0x20); |
@@ -221,7 +221,7 @@ static int __devinit esp_sun3x_probe(struct platform_device *dev) | |||
221 | goto fail_unmap_regs; | 221 | goto fail_unmap_regs; |
222 | 222 | ||
223 | res = platform_get_resource(dev, IORESOURCE_MEM, 1); | 223 | res = platform_get_resource(dev, IORESOURCE_MEM, 1); |
224 | if (!res && !res->start) | 224 | if (!res || !res->start) |
225 | goto fail_unmap_regs; | 225 | goto fail_unmap_regs; |
226 | 226 | ||
227 | esp->dma_regs = ioremap_nocache(res->start, 0x10); | 227 | esp->dma_regs = ioremap_nocache(res->start, 0x10); |
diff --git a/lib/string_helpers.c b/lib/string_helpers.c index 8347925030ff..ab431d4cc970 100644 --- a/lib/string_helpers.c +++ b/lib/string_helpers.c | |||
@@ -23,7 +23,7 @@ | |||
23 | int string_get_size(u64 size, const enum string_size_units units, | 23 | int string_get_size(u64 size, const enum string_size_units units, |
24 | char *buf, int len) | 24 | char *buf, int len) |
25 | { | 25 | { |
26 | const char *units_10[] = { "B", "KB", "MB", "GB", "TB", "PB", | 26 | const char *units_10[] = { "B", "kB", "MB", "GB", "TB", "PB", |
27 | "EB", "ZB", "YB", NULL}; | 27 | "EB", "ZB", "YB", NULL}; |
28 | const char *units_2[] = {"B", "KiB", "MiB", "GiB", "TiB", "PiB", | 28 | const char *units_2[] = {"B", "KiB", "MiB", "GiB", "TiB", "PiB", |
29 | "EiB", "ZiB", "YiB", NULL }; | 29 | "EiB", "ZiB", "YiB", NULL }; |
@@ -31,7 +31,7 @@ int string_get_size(u64 size, const enum string_size_units units, | |||
31 | [STRING_UNITS_10] = units_10, | 31 | [STRING_UNITS_10] = units_10, |
32 | [STRING_UNITS_2] = units_2, | 32 | [STRING_UNITS_2] = units_2, |
33 | }; | 33 | }; |
34 | const int divisor[] = { | 34 | const unsigned int divisor[] = { |
35 | [STRING_UNITS_10] = 1000, | 35 | [STRING_UNITS_10] = 1000, |
36 | [STRING_UNITS_2] = 1024, | 36 | [STRING_UNITS_2] = 1024, |
37 | }; | 37 | }; |
@@ -40,23 +40,27 @@ int string_get_size(u64 size, const enum string_size_units units, | |||
40 | char tmp[8]; | 40 | char tmp[8]; |
41 | 41 | ||
42 | tmp[0] = '\0'; | 42 | tmp[0] = '\0'; |
43 | i = 0; | ||
44 | if (size >= divisor[units]) { | ||
45 | while (size >= divisor[units] && units_str[units][i]) { | ||
46 | remainder = do_div(size, divisor[units]); | ||
47 | i++; | ||
48 | } | ||
43 | 49 | ||
44 | for (i = 0; size > divisor[units] && units_str[units][i]; i++) | 50 | sf_cap = size; |
45 | remainder = do_div(size, divisor[units]); | 51 | for (j = 0; sf_cap*10 < 1000; j++) |
52 | sf_cap *= 10; | ||
46 | 53 | ||
47 | sf_cap = size; | 54 | if (j) { |
48 | for (j = 0; sf_cap*10 < 1000; j++) | 55 | remainder *= 1000; |
49 | sf_cap *= 10; | 56 | do_div(remainder, divisor[units]); |
50 | 57 | snprintf(tmp, sizeof(tmp), ".%03lld", | |
51 | if (j) { | 58 | (unsigned long long)remainder); |
52 | remainder *= 1000; | 59 | tmp[j+1] = '\0'; |
53 | do_div(remainder, divisor[units]); | 60 | } |
54 | snprintf(tmp, sizeof(tmp), ".%03lld", | ||
55 | (unsigned long long)remainder); | ||
56 | tmp[j+1] = '\0'; | ||
57 | } | 61 | } |
58 | 62 | ||
59 | snprintf(buf, len, "%lld%s%s", (unsigned long long)size, | 63 | snprintf(buf, len, "%lld%s %s", (unsigned long long)size, |
60 | tmp, units_str[units][i]); | 64 | tmp, units_str[units][i]); |
61 | 65 | ||
62 | return 0; | 66 | return 0; |