drm/i915: reduce some of the duplication of tiling checking

i915_gem_object_fenceable was mostly just a repeat of the
i915_gem_object_fence_offset_ok, but also checking the size (which was
checkecd when we allowed that BO to be tiled in the first place). So
instead, export the latter function and use it in place.

Signed-Off-By: Owain G. Ainsworth <oga@openbsd.org>
Signed-off-by: Eric Anholt <eric@anholt.net>

3 files changed, 5 insertions, 36 deletions

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 953ad64e0553..40b0da37b1f1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -914,7 +914,8 @@ void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
 bool i915_tiling_ok(struct drm_device *dev, int stride, int size,
                     int tiling_mode);
-bool i915_obj_fenceable(struct drm_device *dev, struct drm_gem_object *obj);
+bool i915_gem_object_fence_offset_ok(struct drm_gem_object *obj,
+                                     int tiling_mode);
 
 /* i915_gem_debug.c */
 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 7b12604a9eb8..59dcce054d1e 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3253,7 +3253,8 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
                      obj_priv->tiling_mode != I915_TILING_NONE;
 
         /* Check fence reg constraints and rebind if necessary */
-        if (need_fence && !i915_obj_fenceable(dev, obj))
+        if (need_fence && !i915_gem_object_fence_offset_ok(obj,
+            obj_priv->tiling_mode))
                 i915_gem_object_unbind(obj);
 
         /* Choose the GTT offset for our buffer and put it there. */
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index b0cbe3a62f84..ba247d1f9bc7 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -180,39 +180,6 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
         dev_priv->mm.bit_6_swizzle_y = swizzle_y;
 }
 
-
-/**
- * Returns whether an object is currently fenceable.  If not, it may need
- * to be unbound and have its pitch adjusted.
- */
-bool
-i915_obj_fenceable(struct drm_device *dev, struct drm_gem_object *obj)
-{
-        struct drm_i915_gem_object *obj_priv = obj->driver_private;
-
-        if (IS_I965G(dev)) {
-                /* The 965 can have fences at any page boundary. */
-                if (obj->size & 4095)
-                        return false;
-                return true;
-        } else if (IS_I9XX(dev)) {
-                if (obj_priv->gtt_offset & ~I915_FENCE_START_MASK)
-                        return false;
-        } else {
-                if (obj_priv->gtt_offset & ~I830_FENCE_START_MASK)
-                        return false;
-        }
-
-        /* Power of two sized... */
-        if (obj->size & (obj->size - 1))
-                return false;
-
-        /* Objects must be size aligned as well */
-        if (obj_priv->gtt_offset & (obj->size - 1))
-                return false;
-        return true;
-}
-
 /* Check pitch constriants for all chips & tiling formats */
 bool
 i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
@@ -269,7 +236,7 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
         return true;
 }
 
-static bool
+bool
 i915_gem_object_fence_offset_ok(struct drm_gem_object *obj, int tiling_mode)
 {
         struct drm_device *dev = obj->dev;