MIPS: R46000: Fix Micro-assembler field overflow for R4600 V2

Fix uasm warning, which triggered because of workaround for R4600 V2 CPUs.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6716/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 2 insertions, 2 deletions

diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index 58033c44690d..b611102e23b5 100644
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -273,7 +273,7 @@ void build_clear_page(void)
                 uasm_i_ori(&buf, A2, A0, off);
 
         if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
-                uasm_i_lui(&buf, AT, 0xa000);
+                uasm_i_lui(&buf, AT, uasm_rel_hi(0xa0000000));
 
         off = cache_line_size ? min(8, pref_bias_clear_store / cache_line_size)
                                 * cache_line_size : 0;
@@ -424,7 +424,7 @@ void build_copy_page(void)
                 uasm_i_ori(&buf, A2, A0, off);
 
         if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
-                uasm_i_lui(&buf, AT, 0xa000);
+                uasm_i_lui(&buf, AT, uasm_rel_hi(0xa0000000));
 
         off = cache_line_size ? min(8, pref_bias_copy_load / cache_line_size) *
                                 cache_line_size : 0;