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authorKumar Gala <galak@kernel.crashing.org>2007-09-12 12:52:31 -0400
committerKumar Gala <galak@kernel.crashing.org>2007-09-14 09:53:16 -0400
commitf0c8ac8083cbd9347b398bfddcca20f1e2786016 (patch)
tree7fb8b26ef9242dfba1db898a476437ed234f7989
parent5d54ddcbcf931bf07cd1ce262bda4674ebd1427f (diff)
[POWERPC] DTS cleanup
Removed the following cruft from .dts files: * 32-bit in cpu node -- doesn't exist in any spec and not used by kernel * removed built-in (chrp legacy) * Removed #interrupt-cells in places they don't need to be set * Fixed ranges on lite5200* * Removed clock-frequency from i8259 pic node, not sure where this came from * Removed big-endian from i8259 pic nodes, this was just bogus Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat
-rw-r--r--arch/powerpc/boot/dts/holly.dts1
-rw-r--r--arch/powerpc/boot/dts/kuroboxHD.dts2
-rw-r--r--arch/powerpc/boot/dts/kuroboxHG.dts2
-rw-r--r--arch/powerpc/boot/dts/lite5200.dts7
-rw-r--r--arch/powerpc/boot/dts/lite5200b.dts7
-rw-r--r--arch/powerpc/boot/dts/mpc7448hpc2.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8272ads.dts5
-rw-r--r--arch/powerpc/boot/dts/mpc8313erdb.dts3
-rw-r--r--arch/powerpc/boot/dts/mpc832x_mds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc832x_rdb.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8349emitx.dts3
-rw-r--r--arch/powerpc/boot/dts/mpc8349emitxgp.dts3
-rw-r--r--arch/powerpc/boot/dts/mpc834x_mds.dts3
-rw-r--r--arch/powerpc/boot/dts/mpc836x_mds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8540ads.dts3
-rw-r--r--arch/powerpc/boot/dts/mpc8541cds.dts6
-rw-r--r--arch/powerpc/boot/dts/mpc8544ds.dts5
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dts5
-rw-r--r--arch/powerpc/boot/dts/mpc8555cds.dts6
-rw-r--r--arch/powerpc/boot/dts/mpc8560ads.dts5
-rw-r--r--arch/powerpc/boot/dts/mpc8568mds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8641_hpcn.dts6
-rw-r--r--arch/powerpc/boot/dts/mpc866ads.dts5
-rw-r--r--arch/powerpc/boot/dts/mpc885ads.dts5
-rw-r--r--arch/powerpc/boot/dts/prpmc2800.dts1
25 files changed, 4 insertions, 99 deletions
diff --git a/arch/powerpc/boot/dts/holly.dts b/arch/powerpc/boot/dts/holly.dts
index 1a4d0beccc99..b5d87895fe06 100644
--- a/arch/powerpc/boot/dts/holly.dts
+++ b/arch/powerpc/boot/dts/holly.dts
@@ -31,7 +31,6 @@
31 timebase-frequency = <2faf080>; 31 timebase-frequency = <2faf080>;
32 clock-frequency = <23c34600>; 32 clock-frequency = <23c34600>;
33 bus-frequency = <bebc200>; 33 bus-frequency = <bebc200>;
34 32-bit;
35 }; 34 };
36 }; 35 };
37 36
diff --git a/arch/powerpc/boot/dts/kuroboxHD.dts b/arch/powerpc/boot/dts/kuroboxHD.dts
index a7b3714bc029..ec71ab819fee 100644
--- a/arch/powerpc/boot/dts/kuroboxHD.dts
+++ b/arch/powerpc/boot/dts/kuroboxHD.dts
@@ -47,7 +47,6 @@ XXXX add flash parts, rtc, ??
47 soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */ 47 soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
48 #address-cells = <1>; 48 #address-cells = <1>;
49 #size-cells = <1>; 49 #size-cells = <1>;
50 #interrupt-cells = <2>;
51 device_type = "soc"; 50 device_type = "soc";
52 compatible = "mpc10x"; 51 compatible = "mpc10x";
53 store-gathering = <0>; /* 0 == off, !0 == on */ 52 store-gathering = <0>; /* 0 == off, !0 == on */
@@ -101,7 +100,6 @@ XXXX add flash parts, rtc, ??
101 compatible = "chrp,open-pic"; 100 compatible = "chrp,open-pic";
102 interrupt-controller; 101 interrupt-controller;
103 reg = <80040000 40000>; 102 reg = <80040000 40000>;
104 built-in;
105 }; 103 };
106 104
107 pci@fec00000 { 105 pci@fec00000 {
diff --git a/arch/powerpc/boot/dts/kuroboxHG.dts b/arch/powerpc/boot/dts/kuroboxHG.dts
index a0007b9bcc80..32ecd2319928 100644
--- a/arch/powerpc/boot/dts/kuroboxHG.dts
+++ b/arch/powerpc/boot/dts/kuroboxHG.dts
@@ -47,7 +47,6 @@ XXXX add flash parts, rtc, ??
47 soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */ 47 soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
48 #address-cells = <1>; 48 #address-cells = <1>;
49 #size-cells = <1>; 49 #size-cells = <1>;
50 #interrupt-cells = <2>;
51 device_type = "soc"; 50 device_type = "soc";
52 compatible = "mpc10x"; 51 compatible = "mpc10x";
53 store-gathering = <0>; /* 0 == off, !0 == on */ 52 store-gathering = <0>; /* 0 == off, !0 == on */
@@ -101,7 +100,6 @@ XXXX add flash parts, rtc, ??
101 compatible = "chrp,open-pic"; 100 compatible = "chrp,open-pic";
102 interrupt-controller; 101 interrupt-controller;
103 reg = <80040000 40000>; 102 reg = <80040000 40000>;
104 built-in;
105 }; 103 };
106 104
107 pci@fec00000 { 105 pci@fec00000 {
diff --git a/arch/powerpc/boot/dts/lite5200.dts b/arch/powerpc/boot/dts/lite5200.dts
index d29308fe4c24..d8bcbb870fdc 100644
--- a/arch/powerpc/boot/dts/lite5200.dts
+++ b/arch/powerpc/boot/dts/lite5200.dts
@@ -37,7 +37,6 @@
37 timebase-frequency = <0>; // from bootloader 37 timebase-frequency = <0>; // from bootloader
38 bus-frequency = <0>; // from bootloader 38 bus-frequency = <0>; // from bootloader
39 clock-frequency = <0>; // from bootloader 39 clock-frequency = <0>; // from bootloader
40 32-bit;
41 }; 40 };
42 }; 41 };
43 42
@@ -50,10 +49,9 @@
50 model = "fsl,mpc5200"; 49 model = "fsl,mpc5200";
51 compatible = "mpc5200"; 50 compatible = "mpc5200";
52 revision = ""; // from bootloader 51 revision = ""; // from bootloader
53 #interrupt-cells = <3>;
54 device_type = "soc"; 52 device_type = "soc";
55 ranges = <0 f0000000 f0010000>; 53 ranges = <0 f0000000 0000c000>;
56 reg = <f0000000 00010000>; 54 reg = <f0000000 00000100>;
57 bus-frequency = <0>; // from bootloader 55 bus-frequency = <0>; // from bootloader
58 system-frequency = <0>; // from bootloader 56 system-frequency = <0>; // from bootloader
59 57
@@ -69,7 +67,6 @@
69 device_type = "interrupt-controller"; 67 device_type = "interrupt-controller";
70 compatible = "mpc5200-pic"; 68 compatible = "mpc5200-pic";
71 reg = <500 80>; 69 reg = <500 80>;
72 built-in;
73 }; 70 };
74 71
75 gpt@600 { // General Purpose Timer 72 gpt@600 { // General Purpose Timer
diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts
index f242531f0451..5fe8998abb7c 100644
--- a/arch/powerpc/boot/dts/lite5200b.dts
+++ b/arch/powerpc/boot/dts/lite5200b.dts
@@ -37,7 +37,6 @@
37 timebase-frequency = <0>; // from bootloader 37 timebase-frequency = <0>; // from bootloader
38 bus-frequency = <0>; // from bootloader 38 bus-frequency = <0>; // from bootloader
39 clock-frequency = <0>; // from bootloader 39 clock-frequency = <0>; // from bootloader
40 32-bit;
41 }; 40 };
42 }; 41 };
43 42
@@ -50,10 +49,9 @@
50 model = "fsl,mpc5200b"; 49 model = "fsl,mpc5200b";
51 compatible = "mpc5200"; 50 compatible = "mpc5200";
52 revision = ""; // from bootloader 51 revision = ""; // from bootloader
53 #interrupt-cells = <3>;
54 device_type = "soc"; 52 device_type = "soc";
55 ranges = <0 f0000000 f0010000>; 53 ranges = <0 f0000000 0000c000>;
56 reg = <f0000000 00010000>; 54 reg = <f0000000 00000100>;
57 bus-frequency = <0>; // from bootloader 55 bus-frequency = <0>; // from bootloader
58 system-frequency = <0>; // from bootloader 56 system-frequency = <0>; // from bootloader
59 57
@@ -69,7 +67,6 @@
69 device_type = "interrupt-controller"; 67 device_type = "interrupt-controller";
70 compatible = "mpc5200b-pic\0mpc5200-pic"; 68 compatible = "mpc5200b-pic\0mpc5200-pic";
71 reg = <500 80>; 69 reg = <500 80>;
72 built-in;
73 }; 70 };
74 71
75 gpt@600 { // General Purpose Timer 72 gpt@600 { // General Purpose Timer
diff --git a/arch/powerpc/boot/dts/mpc7448hpc2.dts b/arch/powerpc/boot/dts/mpc7448hpc2.dts
index b9158eb2797e..88cd37da13ef 100644
--- a/arch/powerpc/boot/dts/mpc7448hpc2.dts
+++ b/arch/powerpc/boot/dts/mpc7448hpc2.dts
@@ -31,7 +31,6 @@
31 timebase-frequency = <0>; // 33 MHz, from uboot 31 timebase-frequency = <0>; // 33 MHz, from uboot
32 clock-frequency = <0>; // From U-Boot 32 clock-frequency = <0>; // From U-Boot
33 bus-frequency = <0>; // From U-Boot 33 bus-frequency = <0>; // From U-Boot
34 32-bit;
35 }; 34 };
36 }; 35 };
37 36
@@ -44,7 +43,6 @@
44 tsi108@c0000000 { 43 tsi108@c0000000 {
45 #address-cells = <1>; 44 #address-cells = <1>;
46 #size-cells = <1>; 45 #size-cells = <1>;
47 #interrupt-cells = <2>;
48 device_type = "tsi-bridge"; 46 device_type = "tsi-bridge";
49 ranges = <00000000 c0000000 00010000>; 47 ranges = <00000000 c0000000 00010000>;
50 reg = <c0000000 00010000>; 48 reg = <c0000000 00010000>;
@@ -128,7 +126,6 @@
128 #address-cells = <0>; 126 #address-cells = <0>;
129 #interrupt-cells = <2>; 127 #interrupt-cells = <2>;
130 reg = <7400 400>; 128 reg = <7400 400>;
131 built-in;
132 compatible = "chrp,open-pic"; 129 compatible = "chrp,open-pic";
133 device_type = "open-pic"; 130 device_type = "open-pic";
134 big-endian; 131 big-endian;
@@ -180,7 +177,6 @@
180 device_type = "pic-router"; 177 device_type = "pic-router";
181 #address-cells = <0>; 178 #address-cells = <0>;
182 #interrupt-cells = <2>; 179 #interrupt-cells = <2>;
183 built-in;
184 big-endian; 180 big-endian;
185 interrupts = <17 2>; 181 interrupts = <17 2>;
186 interrupt-parent = <&mpic>; 182 interrupt-parent = <&mpic>;
diff --git a/arch/powerpc/boot/dts/mpc8272ads.dts b/arch/powerpc/boot/dts/mpc8272ads.dts
index 4d09dcad2537..43130541799a 100644
--- a/arch/powerpc/boot/dts/mpc8272ads.dts
+++ b/arch/powerpc/boot/dts/mpc8272ads.dts
@@ -29,7 +29,6 @@
29 timebase-frequency = <0>; 29 timebase-frequency = <0>;
30 bus-frequency = <0>; 30 bus-frequency = <0>;
31 clock-frequency = <0>; 31 clock-frequency = <0>;
32 32-bit;
33 }; 32 };
34 }; 33 };
35 34
@@ -38,7 +37,6 @@
38 #interrupt-cells = <2>; 37 #interrupt-cells = <2>;
39 interrupt-controller; 38 interrupt-controller;
40 reg = <f8200000 f8200004>; 39 reg = <f8200000 f8200004>;
41 built-in;
42 device_type = "pci-pic"; 40 device_type = "pci-pic";
43 }; 41 };
44 42
@@ -56,7 +54,6 @@
56 soc8272@f0000000 { 54 soc8272@f0000000 {
57 #address-cells = <1>; 55 #address-cells = <1>;
58 #size-cells = <1>; 56 #size-cells = <1>;
59 #interrupt-cells = <2>;
60 device_type = "soc"; 57 device_type = "soc";
61 ranges = <00000000 f0000000 00053000>; 58 ranges = <00000000 f0000000 00053000>;
62 reg = <f0000000 10000>; 59 reg = <f0000000 10000>;
@@ -118,7 +115,6 @@
118 cpm@f0000000 { 115 cpm@f0000000 {
119 #address-cells = <1>; 116 #address-cells = <1>;
120 #size-cells = <1>; 117 #size-cells = <1>;
121 #interrupt-cells = <2>;
122 device_type = "cpm"; 118 device_type = "cpm";
123 model = "CPM2"; 119 model = "CPM2";
124 ranges = <00000000 00000000 20000>; 120 ranges = <00000000 00000000 20000>;
@@ -161,7 +157,6 @@
161 #interrupt-cells = <2>; 157 #interrupt-cells = <2>;
162 interrupt-controller; 158 interrupt-controller;
163 reg = <10c00 80>; 159 reg = <10c00 80>;
164 built-in;
165 device_type = "cpm-pic"; 160 device_type = "cpm-pic";
166 compatible = "CPM2"; 161 compatible = "CPM2";
167 }; 162 };
diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts
index c5adbe40364e..abd73a2c5e0c 100644
--- a/arch/powerpc/boot/dts/mpc8313erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
@@ -29,7 +29,6 @@
29 timebase-frequency = <0>; // from bootloader 29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader 30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader 31 clock-frequency = <0>; // from bootloader
32 32-bit;
33 }; 32 };
34 }; 33 };
35 34
@@ -41,7 +40,6 @@
41 soc8313@e0000000 { 40 soc8313@e0000000 {
42 #address-cells = <1>; 41 #address-cells = <1>;
43 #size-cells = <1>; 42 #size-cells = <1>;
44 #interrupt-cells = <2>;
45 device_type = "soc"; 43 device_type = "soc";
46 ranges = <0 e0000000 00100000>; 44 ranges = <0 e0000000 00100000>;
47 reg = <e0000000 00000200>; 45 reg = <e0000000 00000200>;
@@ -207,7 +205,6 @@
207 #address-cells = <0>; 205 #address-cells = <0>;
208 #interrupt-cells = <2>; 206 #interrupt-cells = <2>;
209 reg = <700 100>; 207 reg = <700 100>;
210 built-in;
211 device_type = "ipic"; 208 device_type = "ipic";
212 }; 209 };
213 }; 210 };
diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts
index f158ed781ba8..e88167dc1859 100644
--- a/arch/powerpc/boot/dts/mpc832x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc832x_mds.dts
@@ -29,7 +29,6 @@
29 timebase-frequency = <0>; 29 timebase-frequency = <0>;
30 bus-frequency = <0>; 30 bus-frequency = <0>;
31 clock-frequency = <0>; 31 clock-frequency = <0>;
32 32-bit;
33 }; 32 };
34 }; 33 };
35 34
@@ -46,7 +45,6 @@
46 soc8323@e0000000 { 45 soc8323@e0000000 {
47 #address-cells = <1>; 46 #address-cells = <1>;
48 #size-cells = <1>; 47 #size-cells = <1>;
49 #interrupt-cells = <2>;
50 device_type = "soc"; 48 device_type = "soc";
51 ranges = <0 e0000000 00100000>; 49 ranges = <0 e0000000 00100000>;
52 reg = <e0000000 00000200>; 50 reg = <e0000000 00000200>;
@@ -163,7 +161,6 @@
163 #address-cells = <0>; 161 #address-cells = <0>;
164 #interrupt-cells = <2>; 162 #interrupt-cells = <2>;
165 reg = <700 100>; 163 reg = <700 100>;
166 built-in;
167 device_type = "ipic"; 164 device_type = "ipic";
168 }; 165 };
169 166
@@ -333,7 +330,6 @@
333 #address-cells = <0>; 330 #address-cells = <0>;
334 #interrupt-cells = <1>; 331 #interrupt-cells = <1>;
335 reg = <80 80>; 332 reg = <80 80>;
336 built-in;
337 big-endian; 333 big-endian;
338 interrupts = <20 8 21 8>; //high:32 low:33 334 interrupts = <20 8 21 8>; //high:32 low:33
339 interrupt-parent = < &ipic >; 335 interrupt-parent = < &ipic >;
diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts
index 7c4beff3e200..01393e6d7da9 100644
--- a/arch/powerpc/boot/dts/mpc832x_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts
@@ -29,7 +29,6 @@
29 timebase-frequency = <0>; 29 timebase-frequency = <0>;
30 bus-frequency = <0>; 30 bus-frequency = <0>;
31 clock-frequency = <0>; 31 clock-frequency = <0>;
32 32-bit;
33 }; 32 };
34 }; 33 };
35 34
@@ -41,7 +40,6 @@
41 soc8323@e0000000 { 40 soc8323@e0000000 {
42 #address-cells = <1>; 41 #address-cells = <1>;
43 #size-cells = <1>; 42 #size-cells = <1>;
44 #interrupt-cells = <2>;
45 device_type = "soc"; 43 device_type = "soc";
46 ranges = <0 e0000000 00100000>; 44 ranges = <0 e0000000 00100000>;
47 reg = <e0000000 00000200>; 45 reg = <e0000000 00000200>;
@@ -132,7 +130,6 @@
132 #address-cells = <0>; 130 #address-cells = <0>;
133 #interrupt-cells = <2>; 131 #interrupt-cells = <2>;
134 reg = <700 100>; 132 reg = <700 100>;
135 built-in;
136 device_type = "ipic"; 133 device_type = "ipic";
137 }; 134 };
138 135
@@ -292,7 +289,6 @@
292 #address-cells = <0>; 289 #address-cells = <0>;
293 #interrupt-cells = <1>; 290 #interrupt-cells = <1>;
294 reg = <80 80>; 291 reg = <80 80>;
295 built-in;
296 big-endian; 292 big-endian;
297 interrupts = <20 8 21 8>; //high:32 low:33 293 interrupts = <20 8 21 8>; //high:32 low:33
298 interrupt-parent = <&pic>; 294 interrupt-parent = <&pic>;
diff --git a/arch/powerpc/boot/dts/mpc8349emitx.dts b/arch/powerpc/boot/dts/mpc8349emitx.dts
index 502f47c01797..f98c785081bf 100644
--- a/arch/powerpc/boot/dts/mpc8349emitx.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitx.dts
@@ -28,7 +28,6 @@
28 timebase-frequency = <0>; // from bootloader 28 timebase-frequency = <0>; // from bootloader
29 bus-frequency = <0>; // from bootloader 29 bus-frequency = <0>; // from bootloader
30 clock-frequency = <0>; // from bootloader 30 clock-frequency = <0>; // from bootloader
31 32-bit;
32 }; 31 };
33 }; 32 };
34 33
@@ -40,7 +39,6 @@
40 soc8349@e0000000 { 39 soc8349@e0000000 {
41 #address-cells = <1>; 40 #address-cells = <1>;
42 #size-cells = <1>; 41 #size-cells = <1>;
43 #interrupt-cells = <2>;
44 device_type = "soc"; 42 device_type = "soc";
45 ranges = <0 e0000000 00100000>; 43 ranges = <0 e0000000 00100000>;
46 reg = <e0000000 00000200>; 44 reg = <e0000000 00000200>;
@@ -244,7 +242,6 @@
244 #address-cells = <0>; 242 #address-cells = <0>;
245 #interrupt-cells = <2>; 243 #interrupt-cells = <2>;
246 reg = <700 100>; 244 reg = <700 100>;
247 built-in;
248 device_type = "ipic"; 245 device_type = "ipic";
249 }; 246 };
250 }; 247 };
diff --git a/arch/powerpc/boot/dts/mpc8349emitxgp.dts b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
index 0b8387141d88..7c89ff7f6a37 100644
--- a/arch/powerpc/boot/dts/mpc8349emitxgp.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
@@ -28,7 +28,6 @@
28 timebase-frequency = <0>; // from bootloader 28 timebase-frequency = <0>; // from bootloader
29 bus-frequency = <0>; // from bootloader 29 bus-frequency = <0>; // from bootloader
30 clock-frequency = <0>; // from bootloader 30 clock-frequency = <0>; // from bootloader
31 32-bit;
32 }; 31 };
33 }; 32 };
34 33
@@ -40,7 +39,6 @@
40 soc8349@e0000000 { 39 soc8349@e0000000 {
41 #address-cells = <1>; 40 #address-cells = <1>;
42 #size-cells = <1>; 41 #size-cells = <1>;
43 #interrupt-cells = <2>;
44 device_type = "soc"; 42 device_type = "soc";
45 ranges = <0 e0000000 00100000>; 43 ranges = <0 e0000000 00100000>;
46 reg = <e0000000 00000200>; 44 reg = <e0000000 00000200>;
@@ -176,7 +174,6 @@
176 #address-cells = <0>; 174 #address-cells = <0>;
177 #interrupt-cells = <2>; 175 #interrupt-cells = <2>;
178 reg = <700 100>; 176 reg = <700 100>;
179 built-in;
180 device_type = "ipic"; 177 device_type = "ipic";
181 }; 178 };
182 }; 179 };
diff --git a/arch/powerpc/boot/dts/mpc834x_mds.dts b/arch/powerpc/boot/dts/mpc834x_mds.dts
index 481099756e44..f4ba85775409 100644
--- a/arch/powerpc/boot/dts/mpc834x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc834x_mds.dts
@@ -29,7 +29,6 @@
29 timebase-frequency = <0>; // from bootloader 29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader 30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader 31 clock-frequency = <0>; // from bootloader
32 32-bit;
33 }; 32 };
34 }; 33 };
35 34
@@ -46,7 +45,6 @@
46 soc8349@e0000000 { 45 soc8349@e0000000 {
47 #address-cells = <1>; 46 #address-cells = <1>;
48 #size-cells = <1>; 47 #size-cells = <1>;
49 #interrupt-cells = <2>;
50 device_type = "soc"; 48 device_type = "soc";
51 ranges = <0 e0000000 00100000>; 49 ranges = <0 e0000000 00100000>;
52 reg = <e0000000 00000200>; 50 reg = <e0000000 00000200>;
@@ -332,7 +330,6 @@
332 #address-cells = <0>; 330 #address-cells = <0>;
333 #interrupt-cells = <2>; 331 #interrupt-cells = <2>;
334 reg = <700 100>; 332 reg = <700 100>;
335 built-in;
336 device_type = "ipic"; 333 device_type = "ipic";
337 }; 334 };
338 }; 335 };
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index e3f7c1282068..f14e88ee0f1c 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -34,7 +34,6 @@
34 timebase-frequency = <3EF1480>; 34 timebase-frequency = <3EF1480>;
35 bus-frequency = <FBC5200>; 35 bus-frequency = <FBC5200>;
36 clock-frequency = <1F78A400>; 36 clock-frequency = <1F78A400>;
37 32-bit;
38 }; 37 };
39 }; 38 };
40 39
@@ -51,7 +50,6 @@
51 soc8360@e0000000 { 50 soc8360@e0000000 {
52 #address-cells = <1>; 51 #address-cells = <1>;
53 #size-cells = <1>; 52 #size-cells = <1>;
54 #interrupt-cells = <2>;
55 device_type = "soc"; 53 device_type = "soc";
56 ranges = <0 e0000000 00100000>; 54 ranges = <0 e0000000 00100000>;
57 reg = <e0000000 00000200>; 55 reg = <e0000000 00000200>;
@@ -178,7 +176,6 @@
178 #address-cells = <0>; 176 #address-cells = <0>;
179 #interrupt-cells = <2>; 177 #interrupt-cells = <2>;
180 reg = <700 100>; 178 reg = <700 100>;
181 built-in;
182 device_type = "ipic"; 179 device_type = "ipic";
183 }; 180 };
184 181
@@ -364,7 +361,6 @@
364 #address-cells = <0>; 361 #address-cells = <0>;
365 #interrupt-cells = <1>; 362 #interrupt-cells = <1>;
366 reg = <80 80>; 363 reg = <80 80>;
367 built-in;
368 big-endian; 364 big-endian;
369 interrupts = <20 8 21 8>; //high:32 low:33 365 interrupts = <20 8 21 8>; //high:32 low:33
370 interrupt-parent = < &ipic >; 366 interrupt-parent = < &ipic >;
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index fc8dff9f6201..e038c04b4220 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -30,7 +30,6 @@
30 timebase-frequency = <0>; // 33 MHz, from uboot 30 timebase-frequency = <0>; // 33 MHz, from uboot
31 bus-frequency = <0>; // 166 MHz 31 bus-frequency = <0>; // 166 MHz
32 clock-frequency = <0>; // 825 MHz, from uboot 32 clock-frequency = <0>; // 825 MHz, from uboot
33 32-bit;
34 }; 33 };
35 }; 34 };
36 35
@@ -42,7 +41,6 @@
42 soc8540@e0000000 { 41 soc8540@e0000000 {
43 #address-cells = <1>; 42 #address-cells = <1>;
44 #size-cells = <1>; 43 #size-cells = <1>;
45 #interrupt-cells = <2>;
46 device_type = "soc"; 44 device_type = "soc";
47 ranges = <0 e0000000 00100000>; 45 ranges = <0 e0000000 00100000>;
48 reg = <e0000000 00100000>; // CCSRBAR 1M 46 reg = <e0000000 00100000>; // CCSRBAR 1M
@@ -268,7 +266,6 @@
268 #address-cells = <0>; 266 #address-cells = <0>;
269 #interrupt-cells = <2>; 267 #interrupt-cells = <2>;
270 reg = <40000 40000>; 268 reg = <40000 40000>;
271 built-in;
272 compatible = "chrp,open-pic"; 269 compatible = "chrp,open-pic";
273 device_type = "open-pic"; 270 device_type = "open-pic";
274 big-endian; 271 big-endian;
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index fb0b647f8c2a..98afd4df27bf 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -30,7 +30,6 @@
30 timebase-frequency = <0>; // 33 MHz, from uboot 30 timebase-frequency = <0>; // 33 MHz, from uboot
31 bus-frequency = <0>; // 166 MHz 31 bus-frequency = <0>; // 166 MHz
32 clock-frequency = <0>; // 825 MHz, from uboot 32 clock-frequency = <0>; // 825 MHz, from uboot
33 32-bit;
34 }; 33 };
35 }; 34 };
36 35
@@ -42,7 +41,6 @@
42 soc8541@e0000000 { 41 soc8541@e0000000 {
43 #address-cells = <1>; 42 #address-cells = <1>;
44 #size-cells = <1>; 43 #size-cells = <1>;
45 #interrupt-cells = <2>;
46 device_type = "soc"; 44 device_type = "soc";
47 ranges = <0 e0000000 00100000>; 45 ranges = <0 e0000000 00100000>;
48 reg = <e0000000 00100000>; // CCSRBAR 1M 46 reg = <e0000000 00100000>; // CCSRBAR 1M
@@ -197,15 +195,12 @@
197 device_type = "pci"; 195 device_type = "pci";
198 196
199 i8259@19000 { 197 i8259@19000 {
200 clock-frequency = <0>;
201 interrupt-controller; 198 interrupt-controller;
202 device_type = "interrupt-controller"; 199 device_type = "interrupt-controller";
203 reg = <19000 0 0 0 1>; 200 reg = <19000 0 0 0 1>;
204 #address-cells = <0>; 201 #address-cells = <0>;
205 #interrupt-cells = <2>; 202 #interrupt-cells = <2>;
206 built-in;
207 compatible = "chrp,iic"; 203 compatible = "chrp,iic";
208 big-endian;
209 interrupts = <1>; 204 interrupts = <1>;
210 interrupt-parent = <&pci1>; 205 interrupt-parent = <&pci1>;
211 }; 206 };
@@ -240,7 +235,6 @@
240 #address-cells = <0>; 235 #address-cells = <0>;
241 #interrupt-cells = <2>; 236 #interrupt-cells = <2>;
242 reg = <40000 40000>; 237 reg = <40000 40000>;
243 built-in;
244 compatible = "chrp,open-pic"; 238 compatible = "chrp,open-pic";
245 device_type = "open-pic"; 239 device_type = "open-pic";
246 big-endian; 240 big-endian;
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index 3e79bf0a3159..88082ac6f2cd 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -30,7 +30,6 @@
30 timebase-frequency = <0>; 30 timebase-frequency = <0>;
31 bus-frequency = <0>; 31 bus-frequency = <0>;
32 clock-frequency = <0>; 32 clock-frequency = <0>;
33 32-bit;
34 }; 33 };
35 }; 34 };
36 35
@@ -42,7 +41,6 @@
42 soc8544@e0000000 { 41 soc8544@e0000000 {
43 #address-cells = <1>; 42 #address-cells = <1>;
44 #size-cells = <1>; 43 #size-cells = <1>;
45 #interrupt-cells = <2>;
46 device_type = "soc"; 44 device_type = "soc";
47 45
48 46
@@ -295,12 +293,10 @@
295 reg = <1 20 2 293 reg = <1 20 2
296 1 a0 2 294 1 a0 2
297 1 4d0 2>; 295 1 4d0 2>;
298 clock-frequency = <0>;
299 interrupt-controller; 296 interrupt-controller;
300 device_type = "interrupt-controller"; 297 device_type = "interrupt-controller";
301 #address-cells = <0>; 298 #address-cells = <0>;
302 #interrupt-cells = <2>; 299 #interrupt-cells = <2>;
303 built-in;
304 compatible = "chrp,iic"; 300 compatible = "chrp,iic";
305 interrupts = <9 2>; 301 interrupts = <9 2>;
306 interrupt-parent = <&mpic>; 302 interrupt-parent = <&mpic>;
@@ -350,7 +346,6 @@
350 #address-cells = <0>; 346 #address-cells = <0>;
351 #interrupt-cells = <2>; 347 #interrupt-cells = <2>;
352 reg = <40000 40000>; 348 reg = <40000 40000>;
353 built-in;
354 compatible = "chrp,open-pic"; 349 compatible = "chrp,open-pic";
355 device_type = "open-pic"; 350 device_type = "open-pic";
356 big-endian; 351 big-endian;
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index d215d21fff42..11b823595a08 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -30,7 +30,6 @@
30 timebase-frequency = <0>; // 33 MHz, from uboot 30 timebase-frequency = <0>; // 33 MHz, from uboot
31 bus-frequency = <0>; // 166 MHz 31 bus-frequency = <0>; // 166 MHz
32 clock-frequency = <0>; // 825 MHz, from uboot 32 clock-frequency = <0>; // 825 MHz, from uboot
33 32-bit;
34 }; 33 };
35 }; 34 };
36 35
@@ -42,7 +41,6 @@
42 soc8548@e0000000 { 41 soc8548@e0000000 {
43 #address-cells = <1>; 42 #address-cells = <1>;
44 #size-cells = <1>; 43 #size-cells = <1>;
45 #interrupt-cells = <2>;
46 device_type = "soc"; 44 device_type = "soc";
47 ranges = <00001000 e0001000 000ff000 45 ranges = <00001000 e0001000 000ff000
48 80000000 80000000 10000000 46 80000000 80000000 10000000
@@ -318,7 +316,6 @@
318 interrupt-parent = <&i8259>; 316 interrupt-parent = <&i8259>;
319 317
320 i8259: interrupt-controller@20 { 318 i8259: interrupt-controller@20 {
321 clock-frequency = <0>;
322 interrupt-controller; 319 interrupt-controller;
323 device_type = "interrupt-controller"; 320 device_type = "interrupt-controller";
324 reg = <1 20 2 321 reg = <1 20 2
@@ -326,7 +323,6 @@
326 1 4d0 2>; 323 1 4d0 2>;
327 #address-cells = <0>; 324 #address-cells = <0>;
328 #interrupt-cells = <2>; 325 #interrupt-cells = <2>;
329 built-in;
330 compatible = "chrp,iic"; 326 compatible = "chrp,iic";
331 interrupts = <0 1>; 327 interrupts = <0 1>;
332 interrupt-parent = <&mpic>; 328 interrupt-parent = <&mpic>;
@@ -394,7 +390,6 @@
394 #address-cells = <0>; 390 #address-cells = <0>;
395 #interrupt-cells = <2>; 391 #interrupt-cells = <2>;
396 reg = <40000 40000>; 392 reg = <40000 40000>;
397 built-in;
398 compatible = "chrp,open-pic"; 393 compatible = "chrp,open-pic";
399 device_type = "open-pic"; 394 device_type = "open-pic";
400 big-endian; 395 big-endian;
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index c3c888252121..ce11d11293d0 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -30,7 +30,6 @@
30 timebase-frequency = <0>; // 33 MHz, from uboot 30 timebase-frequency = <0>; // 33 MHz, from uboot
31 bus-frequency = <0>; // 166 MHz 31 bus-frequency = <0>; // 166 MHz
32 clock-frequency = <0>; // 825 MHz, from uboot 32 clock-frequency = <0>; // 825 MHz, from uboot
33 32-bit;
34 }; 33 };
35 }; 34 };
36 35
@@ -42,7 +41,6 @@
42 soc8555@e0000000 { 41 soc8555@e0000000 {
43 #address-cells = <1>; 42 #address-cells = <1>;
44 #size-cells = <1>; 43 #size-cells = <1>;
45 #interrupt-cells = <2>;
46 device_type = "soc"; 44 device_type = "soc";
47 ranges = <0 e0000000 00100000>; 45 ranges = <0 e0000000 00100000>;
48 reg = <e0000000 00100000>; // CCSRBAR 1M 46 reg = <e0000000 00100000>; // CCSRBAR 1M
@@ -197,15 +195,12 @@
197 device_type = "pci"; 195 device_type = "pci";
198 196
199 i8259@19000 { 197 i8259@19000 {
200 clock-frequency = <0>;
201 interrupt-controller; 198 interrupt-controller;
202 device_type = "interrupt-controller"; 199 device_type = "interrupt-controller";
203 reg = <19000 0 0 0 1>; 200 reg = <19000 0 0 0 1>;
204 #address-cells = <0>; 201 #address-cells = <0>;
205 #interrupt-cells = <2>; 202 #interrupt-cells = <2>;
206 built-in;
207 compatible = "chrp,iic"; 203 compatible = "chrp,iic";
208 big-endian;
209 interrupts = <1>; 204 interrupts = <1>;
210 interrupt-parent = <&pci1>; 205 interrupt-parent = <&pci1>;
211 }; 206 };
@@ -240,7 +235,6 @@
240 #address-cells = <0>; 235 #address-cells = <0>;
241 #interrupt-cells = <2>; 236 #interrupt-cells = <2>;
242 reg = <40000 40000>; 237 reg = <40000 40000>;
243 built-in;
244 compatible = "chrp,open-pic"; 238 compatible = "chrp,open-pic";
245 device_type = "open-pic"; 239 device_type = "open-pic";
246 big-endian; 240 big-endian;
diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts
index 16dbe848cecf..cf87c30cf6a8 100644
--- a/arch/powerpc/boot/dts/mpc8560ads.dts
+++ b/arch/powerpc/boot/dts/mpc8560ads.dts
@@ -30,7 +30,6 @@
30 timebase-frequency = <04ead9a0>; 30 timebase-frequency = <04ead9a0>;
31 bus-frequency = <13ab6680>; 31 bus-frequency = <13ab6680>;
32 clock-frequency = <312c8040>; 32 clock-frequency = <312c8040>;
33 32-bit;
34 }; 33 };
35 }; 34 };
36 35
@@ -42,7 +41,6 @@
42 soc8560@e0000000 { 41 soc8560@e0000000 {
43 #address-cells = <1>; 42 #address-cells = <1>;
44 #size-cells = <1>; 43 #size-cells = <1>;
45 #interrupt-cells = <2>;
46 device_type = "soc"; 44 device_type = "soc";
47 ranges = <0 e0000000 00100000>; 45 ranges = <0 e0000000 00100000>;
48 reg = <e0000000 00000200>; 46 reg = <e0000000 00000200>;
@@ -227,14 +225,12 @@
227 #address-cells = <0>; 225 #address-cells = <0>;
228 #interrupt-cells = <2>; 226 #interrupt-cells = <2>;
229 reg = <40000 40000>; 227 reg = <40000 40000>;
230 built-in;
231 device_type = "open-pic"; 228 device_type = "open-pic";
232 }; 229 };
233 230
234 cpm@e0000000 { 231 cpm@e0000000 {
235 #address-cells = <1>; 232 #address-cells = <1>;
236 #size-cells = <1>; 233 #size-cells = <1>;
237 #interrupt-cells = <2>;
238 device_type = "cpm"; 234 device_type = "cpm";
239 model = "CPM2"; 235 model = "CPM2";
240 ranges = <0 0 c0000>; 236 ranges = <0 0 c0000>;
@@ -249,7 +245,6 @@
249 interrupts = <2e 2>; 245 interrupts = <2e 2>;
250 interrupt-parent = <&mpic>; 246 interrupt-parent = <&mpic>;
251 reg = <90c00 80>; 247 reg = <90c00 80>;
252 built-in;
253 device_type = "cpm-pic"; 248 device_type = "cpm-pic";
254 }; 249 };
255 250
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index b1dcfbe8c1f8..c472a4b488e9 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -34,7 +34,6 @@
34 timebase-frequency = <0>; 34 timebase-frequency = <0>;
35 bus-frequency = <0>; 35 bus-frequency = <0>;
36 clock-frequency = <0>; 36 clock-frequency = <0>;
37 32-bit;
38 }; 37 };
39 }; 38 };
40 39
@@ -51,7 +50,6 @@
51 soc8568@e0000000 { 50 soc8568@e0000000 {
52 #address-cells = <1>; 51 #address-cells = <1>;
53 #size-cells = <1>; 52 #size-cells = <1>;
54 #interrupt-cells = <2>;
55 device_type = "soc"; 53 device_type = "soc";
56 ranges = <0 e0000000 00100000>; 54 ranges = <0 e0000000 00100000>;
57 reg = <e0000000 00100000>; 55 reg = <e0000000 00100000>;
@@ -258,7 +256,6 @@
258 #address-cells = <0>; 256 #address-cells = <0>;
259 #interrupt-cells = <2>; 257 #interrupt-cells = <2>;
260 reg = <40000 40000>; 258 reg = <40000 40000>;
261 built-in;
262 compatible = "chrp,open-pic"; 259 compatible = "chrp,open-pic";
263 device_type = "open-pic"; 260 device_type = "open-pic";
264 big-endian; 261 big-endian;
@@ -449,7 +446,6 @@
449 #address-cells = <0>; 446 #address-cells = <0>;
450 #interrupt-cells = <1>; 447 #interrupt-cells = <1>;
451 reg = <80 80>; 448 reg = <80 80>;
452 built-in;
453 big-endian; 449 big-endian;
454 interrupts = <2e 2 2e 2>; //high:30 low:30 450 interrupts = <2e 2 2e 2>; //high:30 low:30
455 interrupt-parent = <&mpic>; 451 interrupt-parent = <&mpic>;
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
index b0166e5c177e..4d53d9bc3a9d 100644
--- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts
+++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
@@ -30,7 +30,6 @@
30 timebase-frequency = <0>; // 33 MHz, from uboot 30 timebase-frequency = <0>; // 33 MHz, from uboot
31 bus-frequency = <0>; // From uboot 31 bus-frequency = <0>; // From uboot
32 clock-frequency = <0>; // From uboot 32 clock-frequency = <0>; // From uboot
33 32-bit;
34 }; 33 };
35 PowerPC,8641@1 { 34 PowerPC,8641@1 {
36 device_type = "cpu"; 35 device_type = "cpu";
@@ -42,7 +41,6 @@
42 timebase-frequency = <0>; // 33 MHz, from uboot 41 timebase-frequency = <0>; // 33 MHz, from uboot
43 bus-frequency = <0>; // From uboot 42 bus-frequency = <0>; // From uboot
44 clock-frequency = <0>; // From uboot 43 clock-frequency = <0>; // From uboot
45 32-bit;
46 }; 44 };
47 }; 45 };
48 46
@@ -54,7 +52,6 @@
54 soc8641@f8000000 { 52 soc8641@f8000000 {
55 #address-cells = <1>; 53 #address-cells = <1>;
56 #size-cells = <1>; 54 #size-cells = <1>;
57 #interrupt-cells = <2>;
58 device_type = "soc"; 55 device_type = "soc";
59 ranges = <00001000 f8001000 000ff000 56 ranges = <00001000 f8001000 000ff000
60 80000000 80000000 20000000 57 80000000 80000000 20000000
@@ -291,12 +288,10 @@
291 reg = <1 20 2 288 reg = <1 20 2
292 1 a0 2 289 1 a0 2
293 1 4d0 2>; 290 1 4d0 2>;
294 clock-frequency = <0>;
295 interrupt-controller; 291 interrupt-controller;
296 device_type = "interrupt-controller"; 292 device_type = "interrupt-controller";
297 #address-cells = <0>; 293 #address-cells = <0>;
298 #interrupt-cells = <2>; 294 #interrupt-cells = <2>;
299 built-in;
300 compatible = "chrp,iic"; 295 compatible = "chrp,iic";
301 interrupts = <9 2>; 296 interrupts = <9 2>;
302 interrupt-parent = 297 interrupt-parent =
@@ -366,7 +361,6 @@
366 #address-cells = <0>; 361 #address-cells = <0>;
367 #interrupt-cells = <2>; 362 #interrupt-cells = <2>;
368 reg = <40000 40000>; 363 reg = <40000 40000>;
369 built-in;
370 compatible = "chrp,open-pic"; 364 compatible = "chrp,open-pic";
371 device_type = "open-pic"; 365 device_type = "open-pic";
372 big-endian; 366 big-endian;
diff --git a/arch/powerpc/boot/dts/mpc866ads.dts b/arch/powerpc/boot/dts/mpc866ads.dts
index e5e7726ddb03..90f2293ed3cd 100644
--- a/arch/powerpc/boot/dts/mpc866ads.dts
+++ b/arch/powerpc/boot/dts/mpc866ads.dts
@@ -30,7 +30,6 @@
30 timebase-frequency = <0>; 30 timebase-frequency = <0>;
31 bus-frequency = <0>; 31 bus-frequency = <0>;
32 clock-frequency = <0>; 32 clock-frequency = <0>;
33 32-bit;
34 interrupts = <f 2>; // decrementer interrupt 33 interrupts = <f 2>; // decrementer interrupt
35 interrupt-parent = <&Mpc8xx_pic>; 34 interrupt-parent = <&Mpc8xx_pic>;
36 }; 35 };
@@ -44,7 +43,6 @@
44 soc866@ff000000 { 43 soc866@ff000000 {
45 #address-cells = <1>; 44 #address-cells = <1>;
46 #size-cells = <1>; 45 #size-cells = <1>;
47 #interrupt-cells = <2>;
48 device_type = "soc"; 46 device_type = "soc";
49 ranges = <0 ff000000 00100000>; 47 ranges = <0 ff000000 00100000>;
50 reg = <ff000000 00000200>; 48 reg = <ff000000 00000200>;
@@ -78,7 +76,6 @@
78 #address-cells = <0>; 76 #address-cells = <0>;
79 #interrupt-cells = <2>; 77 #interrupt-cells = <2>;
80 reg = <0 24>; 78 reg = <0 24>;
81 built-in;
82 device_type = "mpc8xx-pic"; 79 device_type = "mpc8xx-pic";
83 compatible = "CPM"; 80 compatible = "CPM";
84 }; 81 };
@@ -86,7 +83,6 @@
86 cpm@ff000000 { 83 cpm@ff000000 {
87 #address-cells = <1>; 84 #address-cells = <1>;
88 #size-cells = <1>; 85 #size-cells = <1>;
89 #interrupt-cells = <2>;
90 device_type = "cpm"; 86 device_type = "cpm";
91 model = "CPM"; 87 model = "CPM";
92 ranges = <0 0 4000>; 88 ranges = <0 0 4000>;
@@ -103,7 +99,6 @@
103 interrupts = <5 2 0 2>; 99 interrupts = <5 2 0 2>;
104 interrupt-parent = <&Mpc8xx_pic>; 100 interrupt-parent = <&Mpc8xx_pic>;
105 reg = <930 20>; 101 reg = <930 20>;
106 built-in;
107 device_type = "cpm-pic"; 102 device_type = "cpm-pic";
108 compatible = "CPM"; 103 compatible = "CPM";
109 }; 104 };
diff --git a/arch/powerpc/boot/dts/mpc885ads.dts b/arch/powerpc/boot/dts/mpc885ads.dts
index dc7ab9c80611..e9aa9d00da24 100644
--- a/arch/powerpc/boot/dts/mpc885ads.dts
+++ b/arch/powerpc/boot/dts/mpc885ads.dts
@@ -30,7 +30,6 @@
30 timebase-frequency = <0>; 30 timebase-frequency = <0>;
31 bus-frequency = <0>; 31 bus-frequency = <0>;
32 clock-frequency = <0>; 32 clock-frequency = <0>;
33 32-bit;
34 interrupts = <f 2>; // decrementer interrupt 33 interrupts = <f 2>; // decrementer interrupt
35 interrupt-parent = <&Mpc8xx_pic>; 34 interrupt-parent = <&Mpc8xx_pic>;
36 }; 35 };
@@ -44,7 +43,6 @@
44 soc885@ff000000 { 43 soc885@ff000000 {
45 #address-cells = <1>; 44 #address-cells = <1>;
46 #size-cells = <1>; 45 #size-cells = <1>;
47 #interrupt-cells = <2>;
48 device_type = "soc"; 46 device_type = "soc";
49 ranges = <0 ff000000 00100000>; 47 ranges = <0 ff000000 00100000>;
50 reg = <ff000000 00000200>; 48 reg = <ff000000 00000200>;
@@ -98,7 +96,6 @@
98 #address-cells = <0>; 96 #address-cells = <0>;
99 #interrupt-cells = <2>; 97 #interrupt-cells = <2>;
100 reg = <0 24>; 98 reg = <0 24>;
101 built-in;
102 device_type = "mpc8xx-pic"; 99 device_type = "mpc8xx-pic";
103 compatible = "CPM"; 100 compatible = "CPM";
104 }; 101 };
@@ -117,7 +114,6 @@
117 cpm@ff000000 { 114 cpm@ff000000 {
118 #address-cells = <1>; 115 #address-cells = <1>;
119 #size-cells = <1>; 116 #size-cells = <1>;
120 #interrupt-cells = <2>;
121 device_type = "cpm"; 117 device_type = "cpm";
122 model = "CPM"; 118 model = "CPM";
123 ranges = <0 0 4000>; 119 ranges = <0 0 4000>;
@@ -134,7 +130,6 @@
134 interrupts = <5 2 0 2>; 130 interrupts = <5 2 0 2>;
135 interrupt-parent = <&Mpc8xx_pic>; 131 interrupt-parent = <&Mpc8xx_pic>;
136 reg = <930 20>; 132 reg = <930 20>;
137 built-in;
138 device_type = "cpm-pic"; 133 device_type = "cpm-pic";
139 compatible = "CPM"; 134 compatible = "CPM";
140 }; 135 };
diff --git a/arch/powerpc/boot/dts/prpmc2800.dts b/arch/powerpc/boot/dts/prpmc2800.dts
index e416ea67be49..297dfa53fe9e 100644
--- a/arch/powerpc/boot/dts/prpmc2800.dts
+++ b/arch/powerpc/boot/dts/prpmc2800.dts
@@ -43,7 +43,6 @@
43 mv64x60@f1000000 { /* Marvell Discovery */ 43 mv64x60@f1000000 { /* Marvell Discovery */
44 #address-cells = <1>; 44 #address-cells = <1>;
45 #size-cells = <1>; 45 #size-cells = <1>;
46 #interrupt-cells = <1>;
47 model = "mv64360"; /* Default */ 46 model = "mv64360"; /* Default */
48 compatible = "marvell,mv64x60"; 47 compatible = "marvell,mv64x60";
49 clock-frequency = <7f28155>; /* 133.333333 MHz */ 48 clock-frequency = <7f28155>; /* 133.333333 MHz */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 01:15:10 -0500