diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2014-05-21 05:42:10 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2014-05-21 06:25:39 -0400 |
commit | e5eb925a1804c4a52994ba57f4f68ee7a9132905 (patch) | |
tree | 537ff44f413665231fd7932dfdce6d9c34661f0b | |
parent | 60b5f90d0fac7585f1a43ccdad06787b97eda0ab (diff) |
MIPS: Change type of asid_cache to unsigned long
asid_cache must be unsigned long otherwise on 64 bit systems it will
become 0 if the value in get_new_mmu_context() reaches 0xffffffff and
in the end the assumption of ASID_FIRST_VERSION is not true anymore
thus leads to more dangerous things.
Initial patch by Yong Zhang <yong.zhang@windriver.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Reported-by: libin <huawei.libin@huawei.com>
-rw-r--r-- | arch/mips/include/asm/cpu-info.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h index dc2135be2a3a..ff2707ab3295 100644 --- a/arch/mips/include/asm/cpu-info.h +++ b/arch/mips/include/asm/cpu-info.h | |||
@@ -39,14 +39,14 @@ struct cache_desc { | |||
39 | #define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */ | 39 | #define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */ |
40 | 40 | ||
41 | struct cpuinfo_mips { | 41 | struct cpuinfo_mips { |
42 | unsigned int udelay_val; | 42 | unsigned long asid_cache; |
43 | unsigned int asid_cache; | ||
44 | 43 | ||
45 | /* | 44 | /* |
46 | * Capability and feature descriptor structure for MIPS CPU | 45 | * Capability and feature descriptor structure for MIPS CPU |
47 | */ | 46 | */ |
48 | unsigned long options; | 47 | unsigned long options; |
49 | unsigned long ases; | 48 | unsigned long ases; |
49 | unsigned int udelay_val; | ||
50 | unsigned int processor_id; | 50 | unsigned int processor_id; |
51 | unsigned int fpu_id; | 51 | unsigned int fpu_id; |
52 | unsigned int msa_id; | 52 | unsigned int msa_id; |