Merge tag 'omap-for-v3.19/fixes-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes

Merge "omap fixes against v3.19-rc1" from Tony Lindgren:

Fixes for omaps mostly to deal with dra7 timer issues
and hypervisor mode. The other fixes are minor fixes for
various boards. The summary of the fixes is:

- Fix real-time counter rate typos for some frequencies
- Fix counter frequency drift for am572x
- Fix booting of secondary CPU in HYP mode
- Fix n900 board name for legacy user space
- Fix cpufreq in omap2plus_defconfig after Kconfig change
- Fix dra7 qspi partitions

And also, let's re-enable smc91x on some n900 boards that
we have sitting in a few test boot systems after the boot
loader dependencies got fixed.

* tag 'omap-for-v3.19/fixes-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: dts: Revert disabling of smc91x for n900
  ARM: dts: dra7-evm: fix qspi device tree partition size
  ARM: omap2plus_defconfig: use CONFIG_CPUFREQ_DT
  ARM: OMAP2+: Fix n900 board name for legacy user space
  ARM: omap5/dra7xx: Enable booting secondary CPU in HYP mode
  ARM: dra7xx: Fix counter frequency drift for AM572x errata i856
  ARM: omap5/dra7xx: Fix frequency typos

Signed-off-by: Olof Johansson <olof@lixom.net>

9 files changed, 100 insertions, 17 deletions

diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 10b725c7bfc0..ad4118f7e1a6 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -499,23 +499,23 @@
                 };
                 partition@5 {
                         label = "QSPI.u-boot-spl-os";
-                        reg = <0x00140000 0x00010000>;
+                        reg = <0x00140000 0x00080000>;
                 };
                 partition@6 {
                         label = "QSPI.u-boot-env";
-                        reg = <0x00150000 0x00010000>;
+                        reg = <0x001c0000 0x00010000>;
                 };
                 partition@7 {
                         label = "QSPI.u-boot-env.backup1";
-                        reg = <0x00160000 0x0010000>;
+                        reg = <0x001d0000 0x0010000>;
                 };
                 partition@8 {
                         label = "QSPI.kernel";
-                        reg = <0x00170000 0x0800000>;
+                        reg = <0x001e0000 0x0800000>;
                 };
                 partition@9 {
                         label = "QSPI.file-system";
-                        reg = <0x00970000 0x01690000>;
+                        reg = <0x009e0000 0x01620000>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index 53f3ca064140..b550c41b46f1 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -700,11 +700,9 @@
                 };
         };
 
+        /* Ethernet is on some early development boards and qemu */
         ethernet@gpmc {
                 compatible = "smsc,lan91c94";
-
-                status = "disabled";
-
                 interrupt-parent = <&gpio2>;
                 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;  /* gpio54 */
                 reg = <1 0x300 0xf>;            /* 16 byte IO range at offset 0x300 */
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index c2c3a852af9f..667d9d52aa01 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -68,7 +68,7 @@ CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 CONFIG_CPU_FREQ_GOV_POWERSAVE=y
 CONFIG_CPU_FREQ_GOV_USERSPACE=y
 CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_GENERIC_CPUFREQ_CPU0=y
+CONFIG_CPUFREQ_DT=y
 # CONFIG_ARM_OMAP2PLUS_CPUFREQ is not set
 CONFIG_CPU_IDLE=y
 CONFIG_BINFMT_MISC=y
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 608079a1aba6..b61c049f92d6 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -77,6 +77,24 @@ MACHINE_END
 #endif
 
 #ifdef CONFIG_ARCH_OMAP3
+/* Some boards need board name for legacy userspace in /proc/cpuinfo */
+static const char *const n900_boards_compat[] __initconst = {
+        "nokia,omap3-n900",
+        NULL,
+};
+
+DT_MACHINE_START(OMAP3_N900_DT, "Nokia RX-51 board")
+        .reserve        = omap_reserve,
+        .map_io         = omap3_map_io,
+        .init_early     = omap3430_init_early,
+        .init_machine   = omap_generic_init,
+        .init_late      = omap3_init_late,
+        .init_time      = omap3_sync32k_timer_init,
+        .dt_compat      = n900_boards_compat,
+        .restart        = omap3xxx_restart,
+MACHINE_END
+
+/* Generic omap3 boards, most boards can use these */
 static const char *const omap3_boards_compat[] __initconst = {
         "ti,omap3430",
         "ti,omap3",
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 377eea849e7b..db57741c9c8a 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -249,6 +249,7 @@ extern void omap4_cpu_die(unsigned int cpu);
 extern struct smp_operations omap4_smp_ops;
 
 extern void omap5_secondary_startup(void);
+extern void omap5_secondary_hyp_startup(void);
 #endif
 
 #if defined(CONFIG_SMP) && defined(CONFIG_PM)
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index a3c013345c45..a80ac2d70bb1 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -286,6 +286,10 @@
 #define OMAP5XXX_CONTROL_STATUS                0x134
 #define OMAP5_DEVICETYPE_MASK          (0x7 << 6)
 
+/* DRA7XX CONTROL CORE BOOTSTRAP */
+#define DRA7_CTRL_CORE_BOOTSTRAP        0x6c4
+#define DRA7_SPEEDSELECT_MASK           (0x3 << 8)
+
 /*
  * REVISIT: This list of registers is not comprehensive - there are more
  * that should be added.
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 4993d4bfe9b2..6d1dffca6c7b 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -22,6 +22,7 @@
 
 /* Physical address needed since MMU not enabled yet on secondary core */
 #define AUX_CORE_BOOT0_PA                       0x48281800
+#define API_HYP_ENTRY                           0x102
 
 /*
  * OMAP5 specific entry point for secondary CPU to jump from ROM
@@ -41,6 +42,26 @@ wait:	ldr	r2, =AUX_CORE_BOOT0_PA	@ read from AuxCoreBoot0
         b       secondary_startup
 ENDPROC(omap5_secondary_startup)
 /*
+ * Same as omap5_secondary_startup except we call into the ROM to
+ * enable HYP mode first.  This is called instead of
+ * omap5_secondary_startup if the primary CPU was put into HYP mode by
+ * the boot loader.
+ */
+ENTRY(omap5_secondary_hyp_startup)
+wait_2: ldr     r2, =AUX_CORE_BOOT0_PA  @ read from AuxCoreBoot0
+        ldr     r0, [r2]
+        mov     r0, r0, lsr #5
+        mrc     p15, 0, r4, c0, c0, 5
+        and     r4, r4, #0x0f
+        cmp     r0, r4
+        bne     wait_2
+        ldr     r12, =API_HYP_ENTRY
+        adr     r0, hyp_boot
+        smc     #0
+hyp_boot:
+        b       secondary_startup
+ENDPROC(omap5_secondary_hyp_startup)
+/*
  * OMAP4 specific entry point for secondary CPU to jump from ROM
  * code.  This routine also provides a holding flag into which
  * secondary core is held until we're ready for it to initialise.
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 256e84ef0f67..5305ec7341ec 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -22,6 +22,7 @@
 #include <linux/irqchip/arm-gic.h>
 
 #include <asm/smp_scu.h>
+#include <asm/virt.h>
 
 #include "omap-secure.h"
 #include "omap-wakeupgen.h"
@@ -227,8 +228,16 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
         if (omap_secure_apis_support())
                 omap_auxcoreboot_addr(virt_to_phys(startup_addr));
         else
-                writel_relaxed(virt_to_phys(omap5_secondary_startup),
-                               base + OMAP_AUX_CORE_BOOT_1);
+                /*
+                 * If the boot CPU is in HYP mode then start secondary
+                 * CPU in HYP mode as well.
+                 */
+                if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE)
+                        writel_relaxed(virt_to_phys(omap5_secondary_hyp_startup),
+                                       base + OMAP_AUX_CORE_BOOT_1);
+                else
+                        writel_relaxed(virt_to_phys(omap5_secondary_startup),
+                                       base + OMAP_AUX_CORE_BOOT_1);
 
 }
 
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 4f61148ec168..7d45c84c69ba 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -54,6 +54,7 @@
 
 #include "soc.h"
 #include "common.h"
+#include "control.h"
 #include "powerdomain.h"
 #include "omap-secure.h"
 
@@ -496,7 +497,8 @@ static void __init realtime_counter_init(void)
         void __iomem *base;
         static struct clk *sys_clk;
         unsigned long rate;
-        unsigned int reg, num, den;
+        unsigned int reg;
+        unsigned long long num, den;
 
         base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
         if (!base) {
@@ -511,13 +513,42 @@ static void __init realtime_counter_init(void)
         }
 
         rate = clk_get_rate(sys_clk);
+
+        if (soc_is_dra7xx()) {
+                /*
+                 * Errata i856 says the 32.768KHz crystal does not start at
+                 * power on, so the CPU falls back to an emulated 32KHz clock
+                 * based on sysclk / 610 instead. This causes the master counter
+                 * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2
+                 * (OR sysclk * 75 / 244)
+                 *
+                 * This affects at least the DRA7/AM572x 1.0, 1.1 revisions.
+                 * Of course any board built without a populated 32.768KHz
+                 * crystal would also need this fix even if the CPU is fixed
+                 * later.
+                 *
+                 * Either case can be detected by using the two speedselect bits
+                 * If they are not 0, then the 32.768KHz clock driving the
+                 * coarse counter that corrects the fine counter every time it
+                 * ticks is actually rate/610 rather than 32.768KHz and we
+                 * should compensate to avoid the 570ppm (at 20MHz, much worse
+                 * at other rates) too fast system time.
+                 */
+                reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);
+                if (reg & DRA7_SPEEDSELECT_MASK) {
+                        num = 75;
+                        den = 244;
+                        goto sysclk1_based;
+                }
+        }
+
         /* Numerator/denumerator values refer TRM Realtime Counter section */
         switch (rate) {
-        case 1200000:
+        case 12000000:
                 num = 64;
                 den = 125;
                 break;
-        case 1300000:
+        case 13000000:
                 num = 768;
                 den = 1625;
                 break;
@@ -529,11 +560,11 @@ static void __init realtime_counter_init(void)
                 num = 192;
                 den = 625;
                 break;
-        case 2600000:
+        case 26000000:
                 num = 384;
                 den = 1625;
                 break;
-        case 2700000:
+        case 27000000:
                 num = 256;
                 den = 1125;
                 break;
@@ -545,6 +576,7 @@ static void __init realtime_counter_init(void)
                 break;
         }
 
+sysclk1_based:
         /* Program numerator and denumerator registers */
         reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
                         NUMERATOR_DENUMERATOR_MASK;
@@ -556,7 +588,7 @@ static void __init realtime_counter_init(void)
         reg |= den;
         writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
 
-        arch_timer_freq = (rate / den) * num;
+        arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den);
         set_cntfreq();
 
         iounmap(base);