diff options
author | Christian König <christian.koenig@amd.com> | 2014-03-03 06:38:08 -0500 |
---|---|---|
committer | Christian König <christian.koenig@amd.com> | 2014-03-04 08:34:34 -0500 |
commit | df0af4403aa8df728a62ccb62a61b3244871068f (patch) | |
tree | 14aaa2707c8b7740bedd1655c046dafd3864c8b5 | |
parent | 4d1526466296360f56f93c195848c1202b0cc10b (diff) |
drm/radeon: remove struct radeon_bo_list
Just move all fields into radeon_cs_reloc, removing unused/duplicated fields.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r-- | drivers/gpu/drm/radeon/evergreen_cs.c | 210 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r100.c | 40 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r200.c | 20 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r300.c | 32 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r600_cs.c | 110 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon.h | 24 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_cs.c | 23 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_object.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_uvd.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_vce.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_vm.c | 22 |
11 files changed, 244 insertions, 245 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c index c7cac07f139b..5c8b358f9fba 100644 --- a/drivers/gpu/drm/radeon/evergreen_cs.c +++ b/drivers/gpu/drm/radeon/evergreen_cs.c | |||
@@ -1165,7 +1165,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
1165 | "0x%04X\n", reg); | 1165 | "0x%04X\n", reg); |
1166 | return -EINVAL; | 1166 | return -EINVAL; |
1167 | } | 1167 | } |
1168 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 1168 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1169 | break; | 1169 | break; |
1170 | case DB_DEPTH_CONTROL: | 1170 | case DB_DEPTH_CONTROL: |
1171 | track->db_depth_control = radeon_get_ib_value(p, idx); | 1171 | track->db_depth_control = radeon_get_ib_value(p, idx); |
@@ -1196,12 +1196,12 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
1196 | } | 1196 | } |
1197 | ib[idx] &= ~Z_ARRAY_MODE(0xf); | 1197 | ib[idx] &= ~Z_ARRAY_MODE(0xf); |
1198 | track->db_z_info &= ~Z_ARRAY_MODE(0xf); | 1198 | track->db_z_info &= ~Z_ARRAY_MODE(0xf); |
1199 | ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); | 1199 | ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); |
1200 | track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); | 1200 | track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); |
1201 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { | 1201 | if (reloc->tiling_flags & RADEON_TILING_MACRO) { |
1202 | unsigned bankw, bankh, mtaspect, tile_split; | 1202 | unsigned bankw, bankh, mtaspect, tile_split; |
1203 | 1203 | ||
1204 | evergreen_tiling_fields(reloc->lobj.tiling_flags, | 1204 | evergreen_tiling_fields(reloc->tiling_flags, |
1205 | &bankw, &bankh, &mtaspect, | 1205 | &bankw, &bankh, &mtaspect, |
1206 | &tile_split); | 1206 | &tile_split); |
1207 | ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); | 1207 | ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); |
@@ -1237,7 +1237,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
1237 | return -EINVAL; | 1237 | return -EINVAL; |
1238 | } | 1238 | } |
1239 | track->db_z_read_offset = radeon_get_ib_value(p, idx); | 1239 | track->db_z_read_offset = radeon_get_ib_value(p, idx); |
1240 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 1240 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1241 | track->db_z_read_bo = reloc->robj; | 1241 | track->db_z_read_bo = reloc->robj; |
1242 | track->db_dirty = true; | 1242 | track->db_dirty = true; |
1243 | break; | 1243 | break; |
@@ -1249,7 +1249,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
1249 | return -EINVAL; | 1249 | return -EINVAL; |
1250 | } | 1250 | } |
1251 | track->db_z_write_offset = radeon_get_ib_value(p, idx); | 1251 | track->db_z_write_offset = radeon_get_ib_value(p, idx); |
1252 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 1252 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1253 | track->db_z_write_bo = reloc->robj; | 1253 | track->db_z_write_bo = reloc->robj; |
1254 | track->db_dirty = true; | 1254 | track->db_dirty = true; |
1255 | break; | 1255 | break; |
@@ -1261,7 +1261,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
1261 | return -EINVAL; | 1261 | return -EINVAL; |
1262 | } | 1262 | } |
1263 | track->db_s_read_offset = radeon_get_ib_value(p, idx); | 1263 | track->db_s_read_offset = radeon_get_ib_value(p, idx); |
1264 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 1264 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1265 | track->db_s_read_bo = reloc->robj; | 1265 | track->db_s_read_bo = reloc->robj; |
1266 | track->db_dirty = true; | 1266 | track->db_dirty = true; |
1267 | break; | 1267 | break; |
@@ -1273,7 +1273,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
1273 | return -EINVAL; | 1273 | return -EINVAL; |
1274 | } | 1274 | } |
1275 | track->db_s_write_offset = radeon_get_ib_value(p, idx); | 1275 | track->db_s_write_offset = radeon_get_ib_value(p, idx); |
1276 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 1276 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1277 | track->db_s_write_bo = reloc->robj; | 1277 | track->db_s_write_bo = reloc->robj; |
1278 | track->db_dirty = true; | 1278 | track->db_dirty = true; |
1279 | break; | 1279 | break; |
@@ -1297,7 +1297,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
1297 | } | 1297 | } |
1298 | tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16; | 1298 | tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16; |
1299 | track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; | 1299 | track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; |
1300 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 1300 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1301 | track->vgt_strmout_bo[tmp] = reloc->robj; | 1301 | track->vgt_strmout_bo[tmp] = reloc->robj; |
1302 | track->streamout_dirty = true; | 1302 | track->streamout_dirty = true; |
1303 | break; | 1303 | break; |
@@ -1317,7 +1317,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
1317 | "0x%04X\n", reg); | 1317 | "0x%04X\n", reg); |
1318 | return -EINVAL; | 1318 | return -EINVAL; |
1319 | } | 1319 | } |
1320 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 1320 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1321 | case CB_TARGET_MASK: | 1321 | case CB_TARGET_MASK: |
1322 | track->cb_target_mask = radeon_get_ib_value(p, idx); | 1322 | track->cb_target_mask = radeon_get_ib_value(p, idx); |
1323 | track->cb_dirty = true; | 1323 | track->cb_dirty = true; |
@@ -1381,8 +1381,8 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
1381 | "0x%04X\n", reg); | 1381 | "0x%04X\n", reg); |
1382 | return -EINVAL; | 1382 | return -EINVAL; |
1383 | } | 1383 | } |
1384 | ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); | 1384 | ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); |
1385 | track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); | 1385 | track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); |
1386 | } | 1386 | } |
1387 | track->cb_dirty = true; | 1387 | track->cb_dirty = true; |
1388 | break; | 1388 | break; |
@@ -1399,8 +1399,8 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
1399 | "0x%04X\n", reg); | 1399 | "0x%04X\n", reg); |
1400 | return -EINVAL; | 1400 | return -EINVAL; |
1401 | } | 1401 | } |
1402 | ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); | 1402 | ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); |
1403 | track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); | 1403 | track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); |
1404 | } | 1404 | } |
1405 | track->cb_dirty = true; | 1405 | track->cb_dirty = true; |
1406 | break; | 1406 | break; |
@@ -1461,10 +1461,10 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
1461 | return -EINVAL; | 1461 | return -EINVAL; |
1462 | } | 1462 | } |
1463 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { | 1463 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
1464 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { | 1464 | if (reloc->tiling_flags & RADEON_TILING_MACRO) { |
1465 | unsigned bankw, bankh, mtaspect, tile_split; | 1465 | unsigned bankw, bankh, mtaspect, tile_split; |
1466 | 1466 | ||
1467 | evergreen_tiling_fields(reloc->lobj.tiling_flags, | 1467 | evergreen_tiling_fields(reloc->tiling_flags, |
1468 | &bankw, &bankh, &mtaspect, | 1468 | &bankw, &bankh, &mtaspect, |
1469 | &tile_split); | 1469 | &tile_split); |
1470 | ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); | 1470 | ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); |
@@ -1489,10 +1489,10 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
1489 | return -EINVAL; | 1489 | return -EINVAL; |
1490 | } | 1490 | } |
1491 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { | 1491 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
1492 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { | 1492 | if (reloc->tiling_flags & RADEON_TILING_MACRO) { |
1493 | unsigned bankw, bankh, mtaspect, tile_split; | 1493 | unsigned bankw, bankh, mtaspect, tile_split; |
1494 | 1494 | ||
1495 | evergreen_tiling_fields(reloc->lobj.tiling_flags, | 1495 | evergreen_tiling_fields(reloc->tiling_flags, |
1496 | &bankw, &bankh, &mtaspect, | 1496 | &bankw, &bankh, &mtaspect, |
1497 | &tile_split); | 1497 | &tile_split); |
1498 | ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); | 1498 | ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); |
@@ -1520,7 +1520,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
1520 | dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); | 1520 | dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); |
1521 | return -EINVAL; | 1521 | return -EINVAL; |
1522 | } | 1522 | } |
1523 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 1523 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1524 | track->cb_color_fmask_bo[tmp] = reloc->robj; | 1524 | track->cb_color_fmask_bo[tmp] = reloc->robj; |
1525 | break; | 1525 | break; |
1526 | case CB_COLOR0_CMASK: | 1526 | case CB_COLOR0_CMASK: |
@@ -1537,7 +1537,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
1537 | dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); | 1537 | dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); |
1538 | return -EINVAL; | 1538 | return -EINVAL; |
1539 | } | 1539 | } |
1540 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 1540 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1541 | track->cb_color_cmask_bo[tmp] = reloc->robj; | 1541 | track->cb_color_cmask_bo[tmp] = reloc->robj; |
1542 | break; | 1542 | break; |
1543 | case CB_COLOR0_FMASK_SLICE: | 1543 | case CB_COLOR0_FMASK_SLICE: |
@@ -1578,7 +1578,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
1578 | } | 1578 | } |
1579 | tmp = (reg - CB_COLOR0_BASE) / 0x3c; | 1579 | tmp = (reg - CB_COLOR0_BASE) / 0x3c; |
1580 | track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); | 1580 | track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); |
1581 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 1581 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1582 | track->cb_color_bo[tmp] = reloc->robj; | 1582 | track->cb_color_bo[tmp] = reloc->robj; |
1583 | track->cb_dirty = true; | 1583 | track->cb_dirty = true; |
1584 | break; | 1584 | break; |
@@ -1594,7 +1594,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
1594 | } | 1594 | } |
1595 | tmp = ((reg - CB_COLOR8_BASE) / 0x1c) + 8; | 1595 | tmp = ((reg - CB_COLOR8_BASE) / 0x1c) + 8; |
1596 | track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); | 1596 | track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); |
1597 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 1597 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1598 | track->cb_color_bo[tmp] = reloc->robj; | 1598 | track->cb_color_bo[tmp] = reloc->robj; |
1599 | track->cb_dirty = true; | 1599 | track->cb_dirty = true; |
1600 | break; | 1600 | break; |
@@ -1606,7 +1606,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
1606 | return -EINVAL; | 1606 | return -EINVAL; |
1607 | } | 1607 | } |
1608 | track->htile_offset = radeon_get_ib_value(p, idx); | 1608 | track->htile_offset = radeon_get_ib_value(p, idx); |
1609 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 1609 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1610 | track->htile_bo = reloc->robj; | 1610 | track->htile_bo = reloc->robj; |
1611 | track->db_dirty = true; | 1611 | track->db_dirty = true; |
1612 | break; | 1612 | break; |
@@ -1723,7 +1723,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
1723 | "0x%04X\n", reg); | 1723 | "0x%04X\n", reg); |
1724 | return -EINVAL; | 1724 | return -EINVAL; |
1725 | } | 1725 | } |
1726 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 1726 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1727 | break; | 1727 | break; |
1728 | case SX_MEMORY_EXPORT_BASE: | 1728 | case SX_MEMORY_EXPORT_BASE: |
1729 | if (p->rdev->family >= CHIP_CAYMAN) { | 1729 | if (p->rdev->family >= CHIP_CAYMAN) { |
@@ -1737,7 +1737,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
1737 | "0x%04X\n", reg); | 1737 | "0x%04X\n", reg); |
1738 | return -EINVAL; | 1738 | return -EINVAL; |
1739 | } | 1739 | } |
1740 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 1740 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1741 | break; | 1741 | break; |
1742 | case CAYMAN_SX_SCATTER_EXPORT_BASE: | 1742 | case CAYMAN_SX_SCATTER_EXPORT_BASE: |
1743 | if (p->rdev->family < CHIP_CAYMAN) { | 1743 | if (p->rdev->family < CHIP_CAYMAN) { |
@@ -1751,7 +1751,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
1751 | "0x%04X\n", reg); | 1751 | "0x%04X\n", reg); |
1752 | return -EINVAL; | 1752 | return -EINVAL; |
1753 | } | 1753 | } |
1754 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 1754 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1755 | break; | 1755 | break; |
1756 | case SX_MISC: | 1756 | case SX_MISC: |
1757 | track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; | 1757 | track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; |
@@ -1836,7 +1836,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, | |||
1836 | return -EINVAL; | 1836 | return -EINVAL; |
1837 | } | 1837 | } |
1838 | 1838 | ||
1839 | offset = reloc->lobj.gpu_offset + | 1839 | offset = reloc->gpu_offset + |
1840 | (idx_value & 0xfffffff0) + | 1840 | (idx_value & 0xfffffff0) + |
1841 | ((u64)(tmp & 0xff) << 32); | 1841 | ((u64)(tmp & 0xff) << 32); |
1842 | 1842 | ||
@@ -1882,7 +1882,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, | |||
1882 | return -EINVAL; | 1882 | return -EINVAL; |
1883 | } | 1883 | } |
1884 | 1884 | ||
1885 | offset = reloc->lobj.gpu_offset + | 1885 | offset = reloc->gpu_offset + |
1886 | idx_value + | 1886 | idx_value + |
1887 | ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); | 1887 | ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); |
1888 | 1888 | ||
@@ -1909,7 +1909,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, | |||
1909 | return -EINVAL; | 1909 | return -EINVAL; |
1910 | } | 1910 | } |
1911 | 1911 | ||
1912 | offset = reloc->lobj.gpu_offset + | 1912 | offset = reloc->gpu_offset + |
1913 | idx_value + | 1913 | idx_value + |
1914 | ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); | 1914 | ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); |
1915 | 1915 | ||
@@ -1937,7 +1937,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, | |||
1937 | return -EINVAL; | 1937 | return -EINVAL; |
1938 | } | 1938 | } |
1939 | 1939 | ||
1940 | offset = reloc->lobj.gpu_offset + | 1940 | offset = reloc->gpu_offset + |
1941 | radeon_get_ib_value(p, idx+1) + | 1941 | radeon_get_ib_value(p, idx+1) + |
1942 | ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); | 1942 | ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); |
1943 | 1943 | ||
@@ -2027,7 +2027,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, | |||
2027 | DRM_ERROR("bad DISPATCH_INDIRECT\n"); | 2027 | DRM_ERROR("bad DISPATCH_INDIRECT\n"); |
2028 | return -EINVAL; | 2028 | return -EINVAL; |
2029 | } | 2029 | } |
2030 | ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff); | 2030 | ib[idx+0] = idx_value + (u32)(reloc->gpu_offset & 0xffffffff); |
2031 | r = evergreen_cs_track_check(p); | 2031 | r = evergreen_cs_track_check(p); |
2032 | if (r) { | 2032 | if (r) { |
2033 | dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); | 2033 | dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); |
@@ -2049,7 +2049,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, | |||
2049 | return -EINVAL; | 2049 | return -EINVAL; |
2050 | } | 2050 | } |
2051 | 2051 | ||
2052 | offset = reloc->lobj.gpu_offset + | 2052 | offset = reloc->gpu_offset + |
2053 | (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + | 2053 | (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + |
2054 | ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); | 2054 | ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); |
2055 | 2055 | ||
@@ -2106,7 +2106,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, | |||
2106 | tmp = radeon_get_ib_value(p, idx) + | 2106 | tmp = radeon_get_ib_value(p, idx) + |
2107 | ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); | 2107 | ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); |
2108 | 2108 | ||
2109 | offset = reloc->lobj.gpu_offset + tmp; | 2109 | offset = reloc->gpu_offset + tmp; |
2110 | 2110 | ||
2111 | if ((tmp + size) > radeon_bo_size(reloc->robj)) { | 2111 | if ((tmp + size) > radeon_bo_size(reloc->robj)) { |
2112 | dev_warn(p->dev, "CP DMA src buffer too small (%llu %lu)\n", | 2112 | dev_warn(p->dev, "CP DMA src buffer too small (%llu %lu)\n", |
@@ -2144,7 +2144,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, | |||
2144 | tmp = radeon_get_ib_value(p, idx+2) + | 2144 | tmp = radeon_get_ib_value(p, idx+2) + |
2145 | ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32); | 2145 | ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32); |
2146 | 2146 | ||
2147 | offset = reloc->lobj.gpu_offset + tmp; | 2147 | offset = reloc->gpu_offset + tmp; |
2148 | 2148 | ||
2149 | if ((tmp + size) > radeon_bo_size(reloc->robj)) { | 2149 | if ((tmp + size) > radeon_bo_size(reloc->robj)) { |
2150 | dev_warn(p->dev, "CP DMA dst buffer too small (%llu %lu)\n", | 2150 | dev_warn(p->dev, "CP DMA dst buffer too small (%llu %lu)\n", |
@@ -2174,7 +2174,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, | |||
2174 | DRM_ERROR("bad SURFACE_SYNC\n"); | 2174 | DRM_ERROR("bad SURFACE_SYNC\n"); |
2175 | return -EINVAL; | 2175 | return -EINVAL; |
2176 | } | 2176 | } |
2177 | ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 2177 | ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
2178 | } | 2178 | } |
2179 | break; | 2179 | break; |
2180 | case PACKET3_EVENT_WRITE: | 2180 | case PACKET3_EVENT_WRITE: |
@@ -2190,7 +2190,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, | |||
2190 | DRM_ERROR("bad EVENT_WRITE\n"); | 2190 | DRM_ERROR("bad EVENT_WRITE\n"); |
2191 | return -EINVAL; | 2191 | return -EINVAL; |
2192 | } | 2192 | } |
2193 | offset = reloc->lobj.gpu_offset + | 2193 | offset = reloc->gpu_offset + |
2194 | (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + | 2194 | (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + |
2195 | ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); | 2195 | ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); |
2196 | 2196 | ||
@@ -2212,7 +2212,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, | |||
2212 | return -EINVAL; | 2212 | return -EINVAL; |
2213 | } | 2213 | } |
2214 | 2214 | ||
2215 | offset = reloc->lobj.gpu_offset + | 2215 | offset = reloc->gpu_offset + |
2216 | (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + | 2216 | (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + |
2217 | ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); | 2217 | ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); |
2218 | 2218 | ||
@@ -2234,7 +2234,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, | |||
2234 | return -EINVAL; | 2234 | return -EINVAL; |
2235 | } | 2235 | } |
2236 | 2236 | ||
2237 | offset = reloc->lobj.gpu_offset + | 2237 | offset = reloc->gpu_offset + |
2238 | (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + | 2238 | (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + |
2239 | ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); | 2239 | ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); |
2240 | 2240 | ||
@@ -2302,11 +2302,11 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, | |||
2302 | } | 2302 | } |
2303 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { | 2303 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
2304 | ib[idx+1+(i*8)+1] |= | 2304 | ib[idx+1+(i*8)+1] |= |
2305 | TEX_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); | 2305 | TEX_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); |
2306 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { | 2306 | if (reloc->tiling_flags & RADEON_TILING_MACRO) { |
2307 | unsigned bankw, bankh, mtaspect, tile_split; | 2307 | unsigned bankw, bankh, mtaspect, tile_split; |
2308 | 2308 | ||
2309 | evergreen_tiling_fields(reloc->lobj.tiling_flags, | 2309 | evergreen_tiling_fields(reloc->tiling_flags, |
2310 | &bankw, &bankh, &mtaspect, | 2310 | &bankw, &bankh, &mtaspect, |
2311 | &tile_split); | 2311 | &tile_split); |
2312 | ib[idx+1+(i*8)+6] |= TEX_TILE_SPLIT(tile_split); | 2312 | ib[idx+1+(i*8)+6] |= TEX_TILE_SPLIT(tile_split); |
@@ -2318,7 +2318,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, | |||
2318 | } | 2318 | } |
2319 | } | 2319 | } |
2320 | texture = reloc->robj; | 2320 | texture = reloc->robj; |
2321 | toffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 2321 | toffset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
2322 | 2322 | ||
2323 | /* tex mip base */ | 2323 | /* tex mip base */ |
2324 | tex_dim = ib[idx+1+(i*8)+0] & 0x7; | 2324 | tex_dim = ib[idx+1+(i*8)+0] & 0x7; |
@@ -2337,7 +2337,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, | |||
2337 | DRM_ERROR("bad SET_RESOURCE (tex)\n"); | 2337 | DRM_ERROR("bad SET_RESOURCE (tex)\n"); |
2338 | return -EINVAL; | 2338 | return -EINVAL; |
2339 | } | 2339 | } |
2340 | moffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 2340 | moffset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
2341 | mipmap = reloc->robj; | 2341 | mipmap = reloc->robj; |
2342 | } | 2342 | } |
2343 | 2343 | ||
@@ -2364,7 +2364,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, | |||
2364 | ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset; | 2364 | ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset; |
2365 | } | 2365 | } |
2366 | 2366 | ||
2367 | offset64 = reloc->lobj.gpu_offset + offset; | 2367 | offset64 = reloc->gpu_offset + offset; |
2368 | ib[idx+1+(i*8)+0] = offset64; | 2368 | ib[idx+1+(i*8)+0] = offset64; |
2369 | ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) | | 2369 | ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) | |
2370 | (upper_32_bits(offset64) & 0xff); | 2370 | (upper_32_bits(offset64) & 0xff); |
@@ -2445,7 +2445,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, | |||
2445 | offset + 4, radeon_bo_size(reloc->robj)); | 2445 | offset + 4, radeon_bo_size(reloc->robj)); |
2446 | return -EINVAL; | 2446 | return -EINVAL; |
2447 | } | 2447 | } |
2448 | offset += reloc->lobj.gpu_offset; | 2448 | offset += reloc->gpu_offset; |
2449 | ib[idx+1] = offset; | 2449 | ib[idx+1] = offset; |
2450 | ib[idx+2] = upper_32_bits(offset) & 0xff; | 2450 | ib[idx+2] = upper_32_bits(offset) & 0xff; |
2451 | } | 2451 | } |
@@ -2464,7 +2464,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, | |||
2464 | offset + 4, radeon_bo_size(reloc->robj)); | 2464 | offset + 4, radeon_bo_size(reloc->robj)); |
2465 | return -EINVAL; | 2465 | return -EINVAL; |
2466 | } | 2466 | } |
2467 | offset += reloc->lobj.gpu_offset; | 2467 | offset += reloc->gpu_offset; |
2468 | ib[idx+3] = offset; | 2468 | ib[idx+3] = offset; |
2469 | ib[idx+4] = upper_32_bits(offset) & 0xff; | 2469 | ib[idx+4] = upper_32_bits(offset) & 0xff; |
2470 | } | 2470 | } |
@@ -2493,7 +2493,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, | |||
2493 | offset + 8, radeon_bo_size(reloc->robj)); | 2493 | offset + 8, radeon_bo_size(reloc->robj)); |
2494 | return -EINVAL; | 2494 | return -EINVAL; |
2495 | } | 2495 | } |
2496 | offset += reloc->lobj.gpu_offset; | 2496 | offset += reloc->gpu_offset; |
2497 | ib[idx+0] = offset; | 2497 | ib[idx+0] = offset; |
2498 | ib[idx+1] = upper_32_bits(offset) & 0xff; | 2498 | ib[idx+1] = upper_32_bits(offset) & 0xff; |
2499 | break; | 2499 | break; |
@@ -2518,7 +2518,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, | |||
2518 | offset + 4, radeon_bo_size(reloc->robj)); | 2518 | offset + 4, radeon_bo_size(reloc->robj)); |
2519 | return -EINVAL; | 2519 | return -EINVAL; |
2520 | } | 2520 | } |
2521 | offset += reloc->lobj.gpu_offset; | 2521 | offset += reloc->gpu_offset; |
2522 | ib[idx+1] = offset; | 2522 | ib[idx+1] = offset; |
2523 | ib[idx+2] = upper_32_bits(offset) & 0xff; | 2523 | ib[idx+2] = upper_32_bits(offset) & 0xff; |
2524 | } else { | 2524 | } else { |
@@ -2542,7 +2542,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, | |||
2542 | offset + 4, radeon_bo_size(reloc->robj)); | 2542 | offset + 4, radeon_bo_size(reloc->robj)); |
2543 | return -EINVAL; | 2543 | return -EINVAL; |
2544 | } | 2544 | } |
2545 | offset += reloc->lobj.gpu_offset; | 2545 | offset += reloc->gpu_offset; |
2546 | ib[idx+3] = offset; | 2546 | ib[idx+3] = offset; |
2547 | ib[idx+4] = upper_32_bits(offset) & 0xff; | 2547 | ib[idx+4] = upper_32_bits(offset) & 0xff; |
2548 | } else { | 2548 | } else { |
@@ -2717,7 +2717,7 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p) | |||
2717 | dst_offset = radeon_get_ib_value(p, idx+1); | 2717 | dst_offset = radeon_get_ib_value(p, idx+1); |
2718 | dst_offset <<= 8; | 2718 | dst_offset <<= 8; |
2719 | 2719 | ||
2720 | ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8); | 2720 | ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); |
2721 | p->idx += count + 7; | 2721 | p->idx += count + 7; |
2722 | break; | 2722 | break; |
2723 | /* linear */ | 2723 | /* linear */ |
@@ -2725,8 +2725,8 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p) | |||
2725 | dst_offset = radeon_get_ib_value(p, idx+1); | 2725 | dst_offset = radeon_get_ib_value(p, idx+1); |
2726 | dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; | 2726 | dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; |
2727 | 2727 | ||
2728 | ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); | 2728 | ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); |
2729 | ib[idx+2] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; | 2729 | ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; |
2730 | p->idx += count + 3; | 2730 | p->idx += count + 3; |
2731 | break; | 2731 | break; |
2732 | default: | 2732 | default: |
@@ -2768,10 +2768,10 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p) | |||
2768 | dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); | 2768 | dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); |
2769 | return -EINVAL; | 2769 | return -EINVAL; |
2770 | } | 2770 | } |
2771 | ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); | 2771 | ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); |
2772 | ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); | 2772 | ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); |
2773 | ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; | 2773 | ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; |
2774 | ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; | 2774 | ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; |
2775 | p->idx += 5; | 2775 | p->idx += 5; |
2776 | break; | 2776 | break; |
2777 | /* Copy L2T/T2L */ | 2777 | /* Copy L2T/T2L */ |
@@ -2781,22 +2781,22 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p) | |||
2781 | /* tiled src, linear dst */ | 2781 | /* tiled src, linear dst */ |
2782 | src_offset = radeon_get_ib_value(p, idx+1); | 2782 | src_offset = radeon_get_ib_value(p, idx+1); |
2783 | src_offset <<= 8; | 2783 | src_offset <<= 8; |
2784 | ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8); | 2784 | ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); |
2785 | 2785 | ||
2786 | dst_offset = radeon_get_ib_value(p, idx + 7); | 2786 | dst_offset = radeon_get_ib_value(p, idx + 7); |
2787 | dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; | 2787 | dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; |
2788 | ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); | 2788 | ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); |
2789 | ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; | 2789 | ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; |
2790 | } else { | 2790 | } else { |
2791 | /* linear src, tiled dst */ | 2791 | /* linear src, tiled dst */ |
2792 | src_offset = radeon_get_ib_value(p, idx+7); | 2792 | src_offset = radeon_get_ib_value(p, idx+7); |
2793 | src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; | 2793 | src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; |
2794 | ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); | 2794 | ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); |
2795 | ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; | 2795 | ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; |
2796 | 2796 | ||
2797 | dst_offset = radeon_get_ib_value(p, idx+1); | 2797 | dst_offset = radeon_get_ib_value(p, idx+1); |
2798 | dst_offset <<= 8; | 2798 | dst_offset <<= 8; |
2799 | ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8); | 2799 | ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); |
2800 | } | 2800 | } |
2801 | if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { | 2801 | if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { |
2802 | dev_warn(p->dev, "DMA L2T, src buffer too small (%llu %lu)\n", | 2802 | dev_warn(p->dev, "DMA L2T, src buffer too small (%llu %lu)\n", |
@@ -2827,10 +2827,10 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p) | |||
2827 | dst_offset + count, radeon_bo_size(dst_reloc->robj)); | 2827 | dst_offset + count, radeon_bo_size(dst_reloc->robj)); |
2828 | return -EINVAL; | 2828 | return -EINVAL; |
2829 | } | 2829 | } |
2830 | ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xffffffff); | 2830 | ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xffffffff); |
2831 | ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xffffffff); | 2831 | ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xffffffff); |
2832 | ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; | 2832 | ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; |
2833 | ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; | 2833 | ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; |
2834 | p->idx += 5; | 2834 | p->idx += 5; |
2835 | break; | 2835 | break; |
2836 | /* Copy L2L, partial */ | 2836 | /* Copy L2L, partial */ |
@@ -2840,10 +2840,10 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p) | |||
2840 | DRM_ERROR("L2L Partial is cayman only !\n"); | 2840 | DRM_ERROR("L2L Partial is cayman only !\n"); |
2841 | return -EINVAL; | 2841 | return -EINVAL; |
2842 | } | 2842 | } |
2843 | ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset & 0xffffffff); | 2843 | ib[idx+1] += (u32)(src_reloc->gpu_offset & 0xffffffff); |
2844 | ib[idx+2] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; | 2844 | ib[idx+2] += upper_32_bits(src_reloc->gpu_offset) & 0xff; |
2845 | ib[idx+4] += (u32)(dst_reloc->lobj.gpu_offset & 0xffffffff); | 2845 | ib[idx+4] += (u32)(dst_reloc->gpu_offset & 0xffffffff); |
2846 | ib[idx+5] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; | 2846 | ib[idx+5] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; |
2847 | 2847 | ||
2848 | p->idx += 9; | 2848 | p->idx += 9; |
2849 | break; | 2849 | break; |
@@ -2876,12 +2876,12 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p) | |||
2876 | dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); | 2876 | dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); |
2877 | return -EINVAL; | 2877 | return -EINVAL; |
2878 | } | 2878 | } |
2879 | ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); | 2879 | ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); |
2880 | ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset & 0xfffffffc); | 2880 | ib[idx+2] += (u32)(dst2_reloc->gpu_offset & 0xfffffffc); |
2881 | ib[idx+3] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); | 2881 | ib[idx+3] += (u32)(src_reloc->gpu_offset & 0xfffffffc); |
2882 | ib[idx+4] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; | 2882 | ib[idx+4] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; |
2883 | ib[idx+5] += upper_32_bits(dst2_reloc->lobj.gpu_offset) & 0xff; | 2883 | ib[idx+5] += upper_32_bits(dst2_reloc->gpu_offset) & 0xff; |
2884 | ib[idx+6] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; | 2884 | ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff; |
2885 | p->idx += 7; | 2885 | p->idx += 7; |
2886 | break; | 2886 | break; |
2887 | /* Copy L2T Frame to Field */ | 2887 | /* Copy L2T Frame to Field */ |
@@ -2916,10 +2916,10 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p) | |||
2916 | dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); | 2916 | dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); |
2917 | return -EINVAL; | 2917 | return -EINVAL; |
2918 | } | 2918 | } |
2919 | ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8); | 2919 | ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); |
2920 | ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8); | 2920 | ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); |
2921 | ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); | 2921 | ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); |
2922 | ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; | 2922 | ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; |
2923 | p->idx += 10; | 2923 | p->idx += 10; |
2924 | break; | 2924 | break; |
2925 | /* Copy L2T/T2L, partial */ | 2925 | /* Copy L2T/T2L, partial */ |
@@ -2932,16 +2932,16 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p) | |||
2932 | /* detile bit */ | 2932 | /* detile bit */ |
2933 | if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { | 2933 | if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { |
2934 | /* tiled src, linear dst */ | 2934 | /* tiled src, linear dst */ |
2935 | ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8); | 2935 | ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); |
2936 | 2936 | ||
2937 | ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); | 2937 | ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); |
2938 | ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; | 2938 | ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; |
2939 | } else { | 2939 | } else { |
2940 | /* linear src, tiled dst */ | 2940 | /* linear src, tiled dst */ |
2941 | ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); | 2941 | ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); |
2942 | ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; | 2942 | ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; |
2943 | 2943 | ||
2944 | ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8); | 2944 | ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); |
2945 | } | 2945 | } |
2946 | p->idx += 12; | 2946 | p->idx += 12; |
2947 | break; | 2947 | break; |
@@ -2978,10 +2978,10 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p) | |||
2978 | dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); | 2978 | dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); |
2979 | return -EINVAL; | 2979 | return -EINVAL; |
2980 | } | 2980 | } |
2981 | ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8); | 2981 | ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); |
2982 | ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8); | 2982 | ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); |
2983 | ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); | 2983 | ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); |
2984 | ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; | 2984 | ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; |
2985 | p->idx += 10; | 2985 | p->idx += 10; |
2986 | break; | 2986 | break; |
2987 | /* Copy L2T/T2L (tile units) */ | 2987 | /* Copy L2T/T2L (tile units) */ |
@@ -2992,22 +2992,22 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p) | |||
2992 | /* tiled src, linear dst */ | 2992 | /* tiled src, linear dst */ |
2993 | src_offset = radeon_get_ib_value(p, idx+1); | 2993 | src_offset = radeon_get_ib_value(p, idx+1); |
2994 | src_offset <<= 8; | 2994 | src_offset <<= 8; |
2995 | ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8); | 2995 | ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); |
2996 | 2996 | ||
2997 | dst_offset = radeon_get_ib_value(p, idx+7); | 2997 | dst_offset = radeon_get_ib_value(p, idx+7); |
2998 | dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; | 2998 | dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; |
2999 | ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); | 2999 | ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); |
3000 | ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; | 3000 | ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; |
3001 | } else { | 3001 | } else { |
3002 | /* linear src, tiled dst */ | 3002 | /* linear src, tiled dst */ |
3003 | src_offset = radeon_get_ib_value(p, idx+7); | 3003 | src_offset = radeon_get_ib_value(p, idx+7); |
3004 | src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; | 3004 | src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; |
3005 | ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); | 3005 | ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); |
3006 | ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; | 3006 | ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; |
3007 | 3007 | ||
3008 | dst_offset = radeon_get_ib_value(p, idx+1); | 3008 | dst_offset = radeon_get_ib_value(p, idx+1); |
3009 | dst_offset <<= 8; | 3009 | dst_offset <<= 8; |
3010 | ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8); | 3010 | ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); |
3011 | } | 3011 | } |
3012 | if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { | 3012 | if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { |
3013 | dev_warn(p->dev, "DMA L2T, T2L src buffer too small (%llu %lu)\n", | 3013 | dev_warn(p->dev, "DMA L2T, T2L src buffer too small (%llu %lu)\n", |
@@ -3028,8 +3028,8 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p) | |||
3028 | DRM_ERROR("L2T, T2L Partial is cayman only !\n"); | 3028 | DRM_ERROR("L2T, T2L Partial is cayman only !\n"); |
3029 | return -EINVAL; | 3029 | return -EINVAL; |
3030 | } | 3030 | } |
3031 | ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8); | 3031 | ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); |
3032 | ib[idx+4] += (u32)(dst_reloc->lobj.gpu_offset >> 8); | 3032 | ib[idx+4] += (u32)(dst_reloc->gpu_offset >> 8); |
3033 | p->idx += 13; | 3033 | p->idx += 13; |
3034 | break; | 3034 | break; |
3035 | /* Copy L2T broadcast (tile units) */ | 3035 | /* Copy L2T broadcast (tile units) */ |
@@ -3065,10 +3065,10 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p) | |||
3065 | dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); | 3065 | dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); |
3066 | return -EINVAL; | 3066 | return -EINVAL; |
3067 | } | 3067 | } |
3068 | ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8); | 3068 | ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); |
3069 | ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8); | 3069 | ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); |
3070 | ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); | 3070 | ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); |
3071 | ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; | 3071 | ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; |
3072 | p->idx += 10; | 3072 | p->idx += 10; |
3073 | break; | 3073 | break; |
3074 | default: | 3074 | default: |
@@ -3089,8 +3089,8 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p) | |||
3089 | dst_offset, radeon_bo_size(dst_reloc->robj)); | 3089 | dst_offset, radeon_bo_size(dst_reloc->robj)); |
3090 | return -EINVAL; | 3090 | return -EINVAL; |
3091 | } | 3091 | } |
3092 | ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); | 3092 | ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); |
3093 | ib[idx+3] += (upper_32_bits(dst_reloc->lobj.gpu_offset) << 16) & 0x00ff0000; | 3093 | ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000; |
3094 | p->idx += 4; | 3094 | p->idx += 4; |
3095 | break; | 3095 | break; |
3096 | case DMA_PACKET_NOP: | 3096 | case DMA_PACKET_NOP: |
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index 1690a2dc0721..0a894aee7406 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c | |||
@@ -1274,12 +1274,12 @@ int r100_reloc_pitch_offset(struct radeon_cs_parser *p, | |||
1274 | 1274 | ||
1275 | value = radeon_get_ib_value(p, idx); | 1275 | value = radeon_get_ib_value(p, idx); |
1276 | tmp = value & 0x003fffff; | 1276 | tmp = value & 0x003fffff; |
1277 | tmp += (((u32)reloc->lobj.gpu_offset) >> 10); | 1277 | tmp += (((u32)reloc->gpu_offset) >> 10); |
1278 | 1278 | ||
1279 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { | 1279 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
1280 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) | 1280 | if (reloc->tiling_flags & RADEON_TILING_MACRO) |
1281 | tile_flags |= RADEON_DST_TILE_MACRO; | 1281 | tile_flags |= RADEON_DST_TILE_MACRO; |
1282 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { | 1282 | if (reloc->tiling_flags & RADEON_TILING_MICRO) { |
1283 | if (reg == RADEON_SRC_PITCH_OFFSET) { | 1283 | if (reg == RADEON_SRC_PITCH_OFFSET) { |
1284 | DRM_ERROR("Cannot src blit from microtiled surface\n"); | 1284 | DRM_ERROR("Cannot src blit from microtiled surface\n"); |
1285 | radeon_cs_dump_packet(p, pkt); | 1285 | radeon_cs_dump_packet(p, pkt); |
@@ -1325,7 +1325,7 @@ int r100_packet3_load_vbpntr(struct radeon_cs_parser *p, | |||
1325 | return r; | 1325 | return r; |
1326 | } | 1326 | } |
1327 | idx_value = radeon_get_ib_value(p, idx); | 1327 | idx_value = radeon_get_ib_value(p, idx); |
1328 | ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); | 1328 | ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); |
1329 | 1329 | ||
1330 | track->arrays[i + 0].esize = idx_value >> 8; | 1330 | track->arrays[i + 0].esize = idx_value >> 8; |
1331 | track->arrays[i + 0].robj = reloc->robj; | 1331 | track->arrays[i + 0].robj = reloc->robj; |
@@ -1337,7 +1337,7 @@ int r100_packet3_load_vbpntr(struct radeon_cs_parser *p, | |||
1337 | radeon_cs_dump_packet(p, pkt); | 1337 | radeon_cs_dump_packet(p, pkt); |
1338 | return r; | 1338 | return r; |
1339 | } | 1339 | } |
1340 | ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset); | 1340 | ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset); |
1341 | track->arrays[i + 1].robj = reloc->robj; | 1341 | track->arrays[i + 1].robj = reloc->robj; |
1342 | track->arrays[i + 1].esize = idx_value >> 24; | 1342 | track->arrays[i + 1].esize = idx_value >> 24; |
1343 | track->arrays[i + 1].esize &= 0x7F; | 1343 | track->arrays[i + 1].esize &= 0x7F; |
@@ -1351,7 +1351,7 @@ int r100_packet3_load_vbpntr(struct radeon_cs_parser *p, | |||
1351 | return r; | 1351 | return r; |
1352 | } | 1352 | } |
1353 | idx_value = radeon_get_ib_value(p, idx); | 1353 | idx_value = radeon_get_ib_value(p, idx); |
1354 | ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); | 1354 | ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); |
1355 | track->arrays[i + 0].robj = reloc->robj; | 1355 | track->arrays[i + 0].robj = reloc->robj; |
1356 | track->arrays[i + 0].esize = idx_value >> 8; | 1356 | track->arrays[i + 0].esize = idx_value >> 8; |
1357 | track->arrays[i + 0].esize &= 0x7F; | 1357 | track->arrays[i + 0].esize &= 0x7F; |
@@ -1594,7 +1594,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1594 | track->zb.robj = reloc->robj; | 1594 | track->zb.robj = reloc->robj; |
1595 | track->zb.offset = idx_value; | 1595 | track->zb.offset = idx_value; |
1596 | track->zb_dirty = true; | 1596 | track->zb_dirty = true; |
1597 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | 1597 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
1598 | break; | 1598 | break; |
1599 | case RADEON_RB3D_COLOROFFSET: | 1599 | case RADEON_RB3D_COLOROFFSET: |
1600 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); | 1600 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
@@ -1607,7 +1607,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1607 | track->cb[0].robj = reloc->robj; | 1607 | track->cb[0].robj = reloc->robj; |
1608 | track->cb[0].offset = idx_value; | 1608 | track->cb[0].offset = idx_value; |
1609 | track->cb_dirty = true; | 1609 | track->cb_dirty = true; |
1610 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | 1610 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
1611 | break; | 1611 | break; |
1612 | case RADEON_PP_TXOFFSET_0: | 1612 | case RADEON_PP_TXOFFSET_0: |
1613 | case RADEON_PP_TXOFFSET_1: | 1613 | case RADEON_PP_TXOFFSET_1: |
@@ -1621,16 +1621,16 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1621 | return r; | 1621 | return r; |
1622 | } | 1622 | } |
1623 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { | 1623 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
1624 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) | 1624 | if (reloc->tiling_flags & RADEON_TILING_MACRO) |
1625 | tile_flags |= RADEON_TXO_MACRO_TILE; | 1625 | tile_flags |= RADEON_TXO_MACRO_TILE; |
1626 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) | 1626 | if (reloc->tiling_flags & RADEON_TILING_MICRO) |
1627 | tile_flags |= RADEON_TXO_MICRO_TILE_X2; | 1627 | tile_flags |= RADEON_TXO_MICRO_TILE_X2; |
1628 | 1628 | ||
1629 | tmp = idx_value & ~(0x7 << 2); | 1629 | tmp = idx_value & ~(0x7 << 2); |
1630 | tmp |= tile_flags; | 1630 | tmp |= tile_flags; |
1631 | ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset); | 1631 | ib[idx] = tmp + ((u32)reloc->gpu_offset); |
1632 | } else | 1632 | } else |
1633 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | 1633 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
1634 | track->textures[i].robj = reloc->robj; | 1634 | track->textures[i].robj = reloc->robj; |
1635 | track->tex_dirty = true; | 1635 | track->tex_dirty = true; |
1636 | break; | 1636 | break; |
@@ -1648,7 +1648,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1648 | return r; | 1648 | return r; |
1649 | } | 1649 | } |
1650 | track->textures[0].cube_info[i].offset = idx_value; | 1650 | track->textures[0].cube_info[i].offset = idx_value; |
1651 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | 1651 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
1652 | track->textures[0].cube_info[i].robj = reloc->robj; | 1652 | track->textures[0].cube_info[i].robj = reloc->robj; |
1653 | track->tex_dirty = true; | 1653 | track->tex_dirty = true; |
1654 | break; | 1654 | break; |
@@ -1666,7 +1666,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1666 | return r; | 1666 | return r; |
1667 | } | 1667 | } |
1668 | track->textures[1].cube_info[i].offset = idx_value; | 1668 | track->textures[1].cube_info[i].offset = idx_value; |
1669 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | 1669 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
1670 | track->textures[1].cube_info[i].robj = reloc->robj; | 1670 | track->textures[1].cube_info[i].robj = reloc->robj; |
1671 | track->tex_dirty = true; | 1671 | track->tex_dirty = true; |
1672 | break; | 1672 | break; |
@@ -1684,7 +1684,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1684 | return r; | 1684 | return r; |
1685 | } | 1685 | } |
1686 | track->textures[2].cube_info[i].offset = idx_value; | 1686 | track->textures[2].cube_info[i].offset = idx_value; |
1687 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | 1687 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
1688 | track->textures[2].cube_info[i].robj = reloc->robj; | 1688 | track->textures[2].cube_info[i].robj = reloc->robj; |
1689 | track->tex_dirty = true; | 1689 | track->tex_dirty = true; |
1690 | break; | 1690 | break; |
@@ -1702,9 +1702,9 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1702 | return r; | 1702 | return r; |
1703 | } | 1703 | } |
1704 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { | 1704 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
1705 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) | 1705 | if (reloc->tiling_flags & RADEON_TILING_MACRO) |
1706 | tile_flags |= RADEON_COLOR_TILE_ENABLE; | 1706 | tile_flags |= RADEON_COLOR_TILE_ENABLE; |
1707 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) | 1707 | if (reloc->tiling_flags & RADEON_TILING_MICRO) |
1708 | tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; | 1708 | tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; |
1709 | 1709 | ||
1710 | tmp = idx_value & ~(0x7 << 16); | 1710 | tmp = idx_value & ~(0x7 << 16); |
@@ -1772,7 +1772,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1772 | radeon_cs_dump_packet(p, pkt); | 1772 | radeon_cs_dump_packet(p, pkt); |
1773 | return r; | 1773 | return r; |
1774 | } | 1774 | } |
1775 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | 1775 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
1776 | break; | 1776 | break; |
1777 | case RADEON_PP_CNTL: | 1777 | case RADEON_PP_CNTL: |
1778 | { | 1778 | { |
@@ -1932,7 +1932,7 @@ static int r100_packet3_check(struct radeon_cs_parser *p, | |||
1932 | radeon_cs_dump_packet(p, pkt); | 1932 | radeon_cs_dump_packet(p, pkt); |
1933 | return r; | 1933 | return r; |
1934 | } | 1934 | } |
1935 | ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset); | 1935 | ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset); |
1936 | r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); | 1936 | r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); |
1937 | if (r) { | 1937 | if (r) { |
1938 | return r; | 1938 | return r; |
@@ -1946,7 +1946,7 @@ static int r100_packet3_check(struct radeon_cs_parser *p, | |||
1946 | radeon_cs_dump_packet(p, pkt); | 1946 | radeon_cs_dump_packet(p, pkt); |
1947 | return r; | 1947 | return r; |
1948 | } | 1948 | } |
1949 | ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset); | 1949 | ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset); |
1950 | track->num_arrays = 1; | 1950 | track->num_arrays = 1; |
1951 | track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); | 1951 | track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); |
1952 | 1952 | ||
diff --git a/drivers/gpu/drm/radeon/r200.c b/drivers/gpu/drm/radeon/r200.c index b3807edb1936..58f0473aa73f 100644 --- a/drivers/gpu/drm/radeon/r200.c +++ b/drivers/gpu/drm/radeon/r200.c | |||
@@ -185,7 +185,7 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
185 | track->zb.robj = reloc->robj; | 185 | track->zb.robj = reloc->robj; |
186 | track->zb.offset = idx_value; | 186 | track->zb.offset = idx_value; |
187 | track->zb_dirty = true; | 187 | track->zb_dirty = true; |
188 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | 188 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
189 | break; | 189 | break; |
190 | case RADEON_RB3D_COLOROFFSET: | 190 | case RADEON_RB3D_COLOROFFSET: |
191 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); | 191 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
@@ -198,7 +198,7 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
198 | track->cb[0].robj = reloc->robj; | 198 | track->cb[0].robj = reloc->robj; |
199 | track->cb[0].offset = idx_value; | 199 | track->cb[0].offset = idx_value; |
200 | track->cb_dirty = true; | 200 | track->cb_dirty = true; |
201 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | 201 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
202 | break; | 202 | break; |
203 | case R200_PP_TXOFFSET_0: | 203 | case R200_PP_TXOFFSET_0: |
204 | case R200_PP_TXOFFSET_1: | 204 | case R200_PP_TXOFFSET_1: |
@@ -215,16 +215,16 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
215 | return r; | 215 | return r; |
216 | } | 216 | } |
217 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { | 217 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
218 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) | 218 | if (reloc->tiling_flags & RADEON_TILING_MACRO) |
219 | tile_flags |= R200_TXO_MACRO_TILE; | 219 | tile_flags |= R200_TXO_MACRO_TILE; |
220 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) | 220 | if (reloc->tiling_flags & RADEON_TILING_MICRO) |
221 | tile_flags |= R200_TXO_MICRO_TILE; | 221 | tile_flags |= R200_TXO_MICRO_TILE; |
222 | 222 | ||
223 | tmp = idx_value & ~(0x7 << 2); | 223 | tmp = idx_value & ~(0x7 << 2); |
224 | tmp |= tile_flags; | 224 | tmp |= tile_flags; |
225 | ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset); | 225 | ib[idx] = tmp + ((u32)reloc->gpu_offset); |
226 | } else | 226 | } else |
227 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | 227 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
228 | track->textures[i].robj = reloc->robj; | 228 | track->textures[i].robj = reloc->robj; |
229 | track->tex_dirty = true; | 229 | track->tex_dirty = true; |
230 | break; | 230 | break; |
@@ -268,7 +268,7 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
268 | return r; | 268 | return r; |
269 | } | 269 | } |
270 | track->textures[i].cube_info[face - 1].offset = idx_value; | 270 | track->textures[i].cube_info[face - 1].offset = idx_value; |
271 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | 271 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
272 | track->textures[i].cube_info[face - 1].robj = reloc->robj; | 272 | track->textures[i].cube_info[face - 1].robj = reloc->robj; |
273 | track->tex_dirty = true; | 273 | track->tex_dirty = true; |
274 | break; | 274 | break; |
@@ -287,9 +287,9 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
287 | } | 287 | } |
288 | 288 | ||
289 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { | 289 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
290 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) | 290 | if (reloc->tiling_flags & RADEON_TILING_MACRO) |
291 | tile_flags |= RADEON_COLOR_TILE_ENABLE; | 291 | tile_flags |= RADEON_COLOR_TILE_ENABLE; |
292 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) | 292 | if (reloc->tiling_flags & RADEON_TILING_MICRO) |
293 | tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; | 293 | tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; |
294 | 294 | ||
295 | tmp = idx_value & ~(0x7 << 16); | 295 | tmp = idx_value & ~(0x7 << 16); |
@@ -362,7 +362,7 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
362 | radeon_cs_dump_packet(p, pkt); | 362 | radeon_cs_dump_packet(p, pkt); |
363 | return r; | 363 | return r; |
364 | } | 364 | } |
365 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | 365 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
366 | break; | 366 | break; |
367 | case RADEON_PP_CNTL: | 367 | case RADEON_PP_CNTL: |
368 | { | 368 | { |
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c index 7c63ef840e86..41cdf236ee9a 100644 --- a/drivers/gpu/drm/radeon/r300.c +++ b/drivers/gpu/drm/radeon/r300.c | |||
@@ -640,7 +640,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
640 | track->cb[i].robj = reloc->robj; | 640 | track->cb[i].robj = reloc->robj; |
641 | track->cb[i].offset = idx_value; | 641 | track->cb[i].offset = idx_value; |
642 | track->cb_dirty = true; | 642 | track->cb_dirty = true; |
643 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | 643 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
644 | break; | 644 | break; |
645 | case R300_ZB_DEPTHOFFSET: | 645 | case R300_ZB_DEPTHOFFSET: |
646 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); | 646 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
@@ -653,7 +653,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
653 | track->zb.robj = reloc->robj; | 653 | track->zb.robj = reloc->robj; |
654 | track->zb.offset = idx_value; | 654 | track->zb.offset = idx_value; |
655 | track->zb_dirty = true; | 655 | track->zb_dirty = true; |
656 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | 656 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
657 | break; | 657 | break; |
658 | case R300_TX_OFFSET_0: | 658 | case R300_TX_OFFSET_0: |
659 | case R300_TX_OFFSET_0+4: | 659 | case R300_TX_OFFSET_0+4: |
@@ -682,16 +682,16 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
682 | 682 | ||
683 | if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) { | 683 | if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) { |
684 | ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */ | 684 | ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */ |
685 | ((idx_value & ~31) + (u32)reloc->lobj.gpu_offset); | 685 | ((idx_value & ~31) + (u32)reloc->gpu_offset); |
686 | } else { | 686 | } else { |
687 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) | 687 | if (reloc->tiling_flags & RADEON_TILING_MACRO) |
688 | tile_flags |= R300_TXO_MACRO_TILE; | 688 | tile_flags |= R300_TXO_MACRO_TILE; |
689 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) | 689 | if (reloc->tiling_flags & RADEON_TILING_MICRO) |
690 | tile_flags |= R300_TXO_MICRO_TILE; | 690 | tile_flags |= R300_TXO_MICRO_TILE; |
691 | else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) | 691 | else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) |
692 | tile_flags |= R300_TXO_MICRO_TILE_SQUARE; | 692 | tile_flags |= R300_TXO_MICRO_TILE_SQUARE; |
693 | 693 | ||
694 | tmp = idx_value + ((u32)reloc->lobj.gpu_offset); | 694 | tmp = idx_value + ((u32)reloc->gpu_offset); |
695 | tmp |= tile_flags; | 695 | tmp |= tile_flags; |
696 | ib[idx] = tmp; | 696 | ib[idx] = tmp; |
697 | } | 697 | } |
@@ -753,11 +753,11 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
753 | return r; | 753 | return r; |
754 | } | 754 | } |
755 | 755 | ||
756 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) | 756 | if (reloc->tiling_flags & RADEON_TILING_MACRO) |
757 | tile_flags |= R300_COLOR_TILE_ENABLE; | 757 | tile_flags |= R300_COLOR_TILE_ENABLE; |
758 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) | 758 | if (reloc->tiling_flags & RADEON_TILING_MICRO) |
759 | tile_flags |= R300_COLOR_MICROTILE_ENABLE; | 759 | tile_flags |= R300_COLOR_MICROTILE_ENABLE; |
760 | else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) | 760 | else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) |
761 | tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE; | 761 | tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE; |
762 | 762 | ||
763 | tmp = idx_value & ~(0x7 << 16); | 763 | tmp = idx_value & ~(0x7 << 16); |
@@ -838,11 +838,11 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
838 | return r; | 838 | return r; |
839 | } | 839 | } |
840 | 840 | ||
841 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) | 841 | if (reloc->tiling_flags & RADEON_TILING_MACRO) |
842 | tile_flags |= R300_DEPTHMACROTILE_ENABLE; | 842 | tile_flags |= R300_DEPTHMACROTILE_ENABLE; |
843 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) | 843 | if (reloc->tiling_flags & RADEON_TILING_MICRO) |
844 | tile_flags |= R300_DEPTHMICROTILE_TILED; | 844 | tile_flags |= R300_DEPTHMICROTILE_TILED; |
845 | else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) | 845 | else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) |
846 | tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE; | 846 | tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE; |
847 | 847 | ||
848 | tmp = idx_value & ~(0x7 << 16); | 848 | tmp = idx_value & ~(0x7 << 16); |
@@ -1052,7 +1052,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
1052 | radeon_cs_dump_packet(p, pkt); | 1052 | radeon_cs_dump_packet(p, pkt); |
1053 | return r; | 1053 | return r; |
1054 | } | 1054 | } |
1055 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | 1055 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
1056 | break; | 1056 | break; |
1057 | case 0x4e0c: | 1057 | case 0x4e0c: |
1058 | /* RB3D_COLOR_CHANNEL_MASK */ | 1058 | /* RB3D_COLOR_CHANNEL_MASK */ |
@@ -1097,7 +1097,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
1097 | track->aa.robj = reloc->robj; | 1097 | track->aa.robj = reloc->robj; |
1098 | track->aa.offset = idx_value; | 1098 | track->aa.offset = idx_value; |
1099 | track->aa_dirty = true; | 1099 | track->aa_dirty = true; |
1100 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | 1100 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
1101 | break; | 1101 | break; |
1102 | case R300_RB3D_AARESOLVE_PITCH: | 1102 | case R300_RB3D_AARESOLVE_PITCH: |
1103 | track->aa.pitch = idx_value & 0x3FFE; | 1103 | track->aa.pitch = idx_value & 0x3FFE; |
@@ -1162,7 +1162,7 @@ static int r300_packet3_check(struct radeon_cs_parser *p, | |||
1162 | radeon_cs_dump_packet(p, pkt); | 1162 | radeon_cs_dump_packet(p, pkt); |
1163 | return r; | 1163 | return r; |
1164 | } | 1164 | } |
1165 | ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); | 1165 | ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); |
1166 | r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); | 1166 | r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); |
1167 | if (r) { | 1167 | if (r) { |
1168 | return r; | 1168 | return r; |
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c index 2812c7d1ae6f..12511bb5fd6f 100644 --- a/drivers/gpu/drm/radeon/r600_cs.c +++ b/drivers/gpu/drm/radeon/r600_cs.c | |||
@@ -1022,7 +1022,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
1022 | "0x%04X\n", reg); | 1022 | "0x%04X\n", reg); |
1023 | return -EINVAL; | 1023 | return -EINVAL; |
1024 | } | 1024 | } |
1025 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 1025 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1026 | break; | 1026 | break; |
1027 | case SQ_CONFIG: | 1027 | case SQ_CONFIG: |
1028 | track->sq_config = radeon_get_ib_value(p, idx); | 1028 | track->sq_config = radeon_get_ib_value(p, idx); |
@@ -1043,7 +1043,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
1043 | track->db_depth_info = radeon_get_ib_value(p, idx); | 1043 | track->db_depth_info = radeon_get_ib_value(p, idx); |
1044 | ib[idx] &= C_028010_ARRAY_MODE; | 1044 | ib[idx] &= C_028010_ARRAY_MODE; |
1045 | track->db_depth_info &= C_028010_ARRAY_MODE; | 1045 | track->db_depth_info &= C_028010_ARRAY_MODE; |
1046 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { | 1046 | if (reloc->tiling_flags & RADEON_TILING_MACRO) { |
1047 | ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1); | 1047 | ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1); |
1048 | track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1); | 1048 | track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1); |
1049 | } else { | 1049 | } else { |
@@ -1084,9 +1084,9 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
1084 | } | 1084 | } |
1085 | tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16; | 1085 | tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16; |
1086 | track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; | 1086 | track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; |
1087 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 1087 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1088 | track->vgt_strmout_bo[tmp] = reloc->robj; | 1088 | track->vgt_strmout_bo[tmp] = reloc->robj; |
1089 | track->vgt_strmout_bo_mc[tmp] = reloc->lobj.gpu_offset; | 1089 | track->vgt_strmout_bo_mc[tmp] = reloc->gpu_offset; |
1090 | track->streamout_dirty = true; | 1090 | track->streamout_dirty = true; |
1091 | break; | 1091 | break; |
1092 | case VGT_STRMOUT_BUFFER_SIZE_0: | 1092 | case VGT_STRMOUT_BUFFER_SIZE_0: |
@@ -1105,7 +1105,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
1105 | "0x%04X\n", reg); | 1105 | "0x%04X\n", reg); |
1106 | return -EINVAL; | 1106 | return -EINVAL; |
1107 | } | 1107 | } |
1108 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 1108 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1109 | break; | 1109 | break; |
1110 | case R_028238_CB_TARGET_MASK: | 1110 | case R_028238_CB_TARGET_MASK: |
1111 | track->cb_target_mask = radeon_get_ib_value(p, idx); | 1111 | track->cb_target_mask = radeon_get_ib_value(p, idx); |
@@ -1142,10 +1142,10 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
1142 | } | 1142 | } |
1143 | tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4; | 1143 | tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4; |
1144 | track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); | 1144 | track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); |
1145 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { | 1145 | if (reloc->tiling_flags & RADEON_TILING_MACRO) { |
1146 | ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1); | 1146 | ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1); |
1147 | track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1); | 1147 | track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1); |
1148 | } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { | 1148 | } else if (reloc->tiling_flags & RADEON_TILING_MICRO) { |
1149 | ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1); | 1149 | ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1); |
1150 | track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1); | 1150 | track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1); |
1151 | } | 1151 | } |
@@ -1214,7 +1214,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
1214 | } | 1214 | } |
1215 | track->cb_color_frag_bo[tmp] = reloc->robj; | 1215 | track->cb_color_frag_bo[tmp] = reloc->robj; |
1216 | track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8; | 1216 | track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8; |
1217 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 1217 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1218 | } | 1218 | } |
1219 | if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) { | 1219 | if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) { |
1220 | track->cb_dirty = true; | 1220 | track->cb_dirty = true; |
@@ -1245,7 +1245,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
1245 | } | 1245 | } |
1246 | track->cb_color_tile_bo[tmp] = reloc->robj; | 1246 | track->cb_color_tile_bo[tmp] = reloc->robj; |
1247 | track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8; | 1247 | track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8; |
1248 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 1248 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1249 | } | 1249 | } |
1250 | if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) { | 1250 | if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) { |
1251 | track->cb_dirty = true; | 1251 | track->cb_dirty = true; |
@@ -1281,10 +1281,10 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
1281 | } | 1281 | } |
1282 | tmp = (reg - CB_COLOR0_BASE) / 4; | 1282 | tmp = (reg - CB_COLOR0_BASE) / 4; |
1283 | track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; | 1283 | track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; |
1284 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 1284 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1285 | track->cb_color_base_last[tmp] = ib[idx]; | 1285 | track->cb_color_base_last[tmp] = ib[idx]; |
1286 | track->cb_color_bo[tmp] = reloc->robj; | 1286 | track->cb_color_bo[tmp] = reloc->robj; |
1287 | track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset; | 1287 | track->cb_color_bo_mc[tmp] = reloc->gpu_offset; |
1288 | track->cb_dirty = true; | 1288 | track->cb_dirty = true; |
1289 | break; | 1289 | break; |
1290 | case DB_DEPTH_BASE: | 1290 | case DB_DEPTH_BASE: |
@@ -1295,9 +1295,9 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
1295 | return -EINVAL; | 1295 | return -EINVAL; |
1296 | } | 1296 | } |
1297 | track->db_offset = radeon_get_ib_value(p, idx) << 8; | 1297 | track->db_offset = radeon_get_ib_value(p, idx) << 8; |
1298 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 1298 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1299 | track->db_bo = reloc->robj; | 1299 | track->db_bo = reloc->robj; |
1300 | track->db_bo_mc = reloc->lobj.gpu_offset; | 1300 | track->db_bo_mc = reloc->gpu_offset; |
1301 | track->db_dirty = true; | 1301 | track->db_dirty = true; |
1302 | break; | 1302 | break; |
1303 | case DB_HTILE_DATA_BASE: | 1303 | case DB_HTILE_DATA_BASE: |
@@ -1308,7 +1308,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
1308 | return -EINVAL; | 1308 | return -EINVAL; |
1309 | } | 1309 | } |
1310 | track->htile_offset = radeon_get_ib_value(p, idx) << 8; | 1310 | track->htile_offset = radeon_get_ib_value(p, idx) << 8; |
1311 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 1311 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1312 | track->htile_bo = reloc->robj; | 1312 | track->htile_bo = reloc->robj; |
1313 | track->db_dirty = true; | 1313 | track->db_dirty = true; |
1314 | break; | 1314 | break; |
@@ -1377,7 +1377,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
1377 | "0x%04X\n", reg); | 1377 | "0x%04X\n", reg); |
1378 | return -EINVAL; | 1378 | return -EINVAL; |
1379 | } | 1379 | } |
1380 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 1380 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1381 | break; | 1381 | break; |
1382 | case SX_MEMORY_EXPORT_BASE: | 1382 | case SX_MEMORY_EXPORT_BASE: |
1383 | r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); | 1383 | r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); |
@@ -1386,7 +1386,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | |||
1386 | "0x%04X\n", reg); | 1386 | "0x%04X\n", reg); |
1387 | return -EINVAL; | 1387 | return -EINVAL; |
1388 | } | 1388 | } |
1389 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 1389 | ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1390 | break; | 1390 | break; |
1391 | case SX_MISC: | 1391 | case SX_MISC: |
1392 | track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; | 1392 | track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; |
@@ -1672,7 +1672,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
1672 | return -EINVAL; | 1672 | return -EINVAL; |
1673 | } | 1673 | } |
1674 | 1674 | ||
1675 | offset = reloc->lobj.gpu_offset + | 1675 | offset = reloc->gpu_offset + |
1676 | (idx_value & 0xfffffff0) + | 1676 | (idx_value & 0xfffffff0) + |
1677 | ((u64)(tmp & 0xff) << 32); | 1677 | ((u64)(tmp & 0xff) << 32); |
1678 | 1678 | ||
@@ -1713,7 +1713,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
1713 | return -EINVAL; | 1713 | return -EINVAL; |
1714 | } | 1714 | } |
1715 | 1715 | ||
1716 | offset = reloc->lobj.gpu_offset + | 1716 | offset = reloc->gpu_offset + |
1717 | idx_value + | 1717 | idx_value + |
1718 | ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); | 1718 | ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); |
1719 | 1719 | ||
@@ -1765,7 +1765,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
1765 | return -EINVAL; | 1765 | return -EINVAL; |
1766 | } | 1766 | } |
1767 | 1767 | ||
1768 | offset = reloc->lobj.gpu_offset + | 1768 | offset = reloc->gpu_offset + |
1769 | (radeon_get_ib_value(p, idx+1) & 0xfffffff0) + | 1769 | (radeon_get_ib_value(p, idx+1) & 0xfffffff0) + |
1770 | ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); | 1770 | ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); |
1771 | 1771 | ||
@@ -1805,7 +1805,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
1805 | tmp = radeon_get_ib_value(p, idx) + | 1805 | tmp = radeon_get_ib_value(p, idx) + |
1806 | ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); | 1806 | ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); |
1807 | 1807 | ||
1808 | offset = reloc->lobj.gpu_offset + tmp; | 1808 | offset = reloc->gpu_offset + tmp; |
1809 | 1809 | ||
1810 | if ((tmp + size) > radeon_bo_size(reloc->robj)) { | 1810 | if ((tmp + size) > radeon_bo_size(reloc->robj)) { |
1811 | dev_warn(p->dev, "CP DMA src buffer too small (%llu %lu)\n", | 1811 | dev_warn(p->dev, "CP DMA src buffer too small (%llu %lu)\n", |
@@ -1835,7 +1835,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
1835 | tmp = radeon_get_ib_value(p, idx+2) + | 1835 | tmp = radeon_get_ib_value(p, idx+2) + |
1836 | ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32); | 1836 | ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32); |
1837 | 1837 | ||
1838 | offset = reloc->lobj.gpu_offset + tmp; | 1838 | offset = reloc->gpu_offset + tmp; |
1839 | 1839 | ||
1840 | if ((tmp + size) > radeon_bo_size(reloc->robj)) { | 1840 | if ((tmp + size) > radeon_bo_size(reloc->robj)) { |
1841 | dev_warn(p->dev, "CP DMA dst buffer too small (%llu %lu)\n", | 1841 | dev_warn(p->dev, "CP DMA dst buffer too small (%llu %lu)\n", |
@@ -1861,7 +1861,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
1861 | DRM_ERROR("bad SURFACE_SYNC\n"); | 1861 | DRM_ERROR("bad SURFACE_SYNC\n"); |
1862 | return -EINVAL; | 1862 | return -EINVAL; |
1863 | } | 1863 | } |
1864 | ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 1864 | ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1865 | } | 1865 | } |
1866 | break; | 1866 | break; |
1867 | case PACKET3_EVENT_WRITE: | 1867 | case PACKET3_EVENT_WRITE: |
@@ -1877,7 +1877,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
1877 | DRM_ERROR("bad EVENT_WRITE\n"); | 1877 | DRM_ERROR("bad EVENT_WRITE\n"); |
1878 | return -EINVAL; | 1878 | return -EINVAL; |
1879 | } | 1879 | } |
1880 | offset = reloc->lobj.gpu_offset + | 1880 | offset = reloc->gpu_offset + |
1881 | (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + | 1881 | (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + |
1882 | ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); | 1882 | ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); |
1883 | 1883 | ||
@@ -1899,7 +1899,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
1899 | return -EINVAL; | 1899 | return -EINVAL; |
1900 | } | 1900 | } |
1901 | 1901 | ||
1902 | offset = reloc->lobj.gpu_offset + | 1902 | offset = reloc->gpu_offset + |
1903 | (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + | 1903 | (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + |
1904 | ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); | 1904 | ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); |
1905 | 1905 | ||
@@ -1964,11 +1964,11 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
1964 | DRM_ERROR("bad SET_RESOURCE\n"); | 1964 | DRM_ERROR("bad SET_RESOURCE\n"); |
1965 | return -EINVAL; | 1965 | return -EINVAL; |
1966 | } | 1966 | } |
1967 | base_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 1967 | base_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1968 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { | 1968 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
1969 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) | 1969 | if (reloc->tiling_flags & RADEON_TILING_MACRO) |
1970 | ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1); | 1970 | ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1); |
1971 | else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) | 1971 | else if (reloc->tiling_flags & RADEON_TILING_MICRO) |
1972 | ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1); | 1972 | ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1); |
1973 | } | 1973 | } |
1974 | texture = reloc->robj; | 1974 | texture = reloc->robj; |
@@ -1978,13 +1978,13 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
1978 | DRM_ERROR("bad SET_RESOURCE\n"); | 1978 | DRM_ERROR("bad SET_RESOURCE\n"); |
1979 | return -EINVAL; | 1979 | return -EINVAL; |
1980 | } | 1980 | } |
1981 | mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 1981 | mip_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
1982 | mipmap = reloc->robj; | 1982 | mipmap = reloc->robj; |
1983 | r = r600_check_texture_resource(p, idx+(i*7)+1, | 1983 | r = r600_check_texture_resource(p, idx+(i*7)+1, |
1984 | texture, mipmap, | 1984 | texture, mipmap, |
1985 | base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2), | 1985 | base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2), |
1986 | mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3), | 1986 | mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3), |
1987 | reloc->lobj.tiling_flags); | 1987 | reloc->tiling_flags); |
1988 | if (r) | 1988 | if (r) |
1989 | return r; | 1989 | return r; |
1990 | ib[idx+1+(i*7)+2] += base_offset; | 1990 | ib[idx+1+(i*7)+2] += base_offset; |
@@ -2008,7 +2008,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
2008 | ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj) - offset; | 2008 | ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj) - offset; |
2009 | } | 2009 | } |
2010 | 2010 | ||
2011 | offset64 = reloc->lobj.gpu_offset + offset; | 2011 | offset64 = reloc->gpu_offset + offset; |
2012 | ib[idx+1+(i*8)+0] = offset64; | 2012 | ib[idx+1+(i*8)+0] = offset64; |
2013 | ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) | | 2013 | ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) | |
2014 | (upper_32_bits(offset64) & 0xff); | 2014 | (upper_32_bits(offset64) & 0xff); |
@@ -2118,7 +2118,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
2118 | offset + 4, radeon_bo_size(reloc->robj)); | 2118 | offset + 4, radeon_bo_size(reloc->robj)); |
2119 | return -EINVAL; | 2119 | return -EINVAL; |
2120 | } | 2120 | } |
2121 | ib[idx+1] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 2121 | ib[idx+1] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); |
2122 | } | 2122 | } |
2123 | break; | 2123 | break; |
2124 | case PACKET3_SURFACE_BASE_UPDATE: | 2124 | case PACKET3_SURFACE_BASE_UPDATE: |
@@ -2151,7 +2151,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
2151 | offset + 4, radeon_bo_size(reloc->robj)); | 2151 | offset + 4, radeon_bo_size(reloc->robj)); |
2152 | return -EINVAL; | 2152 | return -EINVAL; |
2153 | } | 2153 | } |
2154 | offset += reloc->lobj.gpu_offset; | 2154 | offset += reloc->gpu_offset; |
2155 | ib[idx+1] = offset; | 2155 | ib[idx+1] = offset; |
2156 | ib[idx+2] = upper_32_bits(offset) & 0xff; | 2156 | ib[idx+2] = upper_32_bits(offset) & 0xff; |
2157 | } | 2157 | } |
@@ -2170,7 +2170,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
2170 | offset + 4, radeon_bo_size(reloc->robj)); | 2170 | offset + 4, radeon_bo_size(reloc->robj)); |
2171 | return -EINVAL; | 2171 | return -EINVAL; |
2172 | } | 2172 | } |
2173 | offset += reloc->lobj.gpu_offset; | 2173 | offset += reloc->gpu_offset; |
2174 | ib[idx+3] = offset; | 2174 | ib[idx+3] = offset; |
2175 | ib[idx+4] = upper_32_bits(offset) & 0xff; | 2175 | ib[idx+4] = upper_32_bits(offset) & 0xff; |
2176 | } | 2176 | } |
@@ -2199,7 +2199,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
2199 | offset + 8, radeon_bo_size(reloc->robj)); | 2199 | offset + 8, radeon_bo_size(reloc->robj)); |
2200 | return -EINVAL; | 2200 | return -EINVAL; |
2201 | } | 2201 | } |
2202 | offset += reloc->lobj.gpu_offset; | 2202 | offset += reloc->gpu_offset; |
2203 | ib[idx+0] = offset; | 2203 | ib[idx+0] = offset; |
2204 | ib[idx+1] = upper_32_bits(offset) & 0xff; | 2204 | ib[idx+1] = upper_32_bits(offset) & 0xff; |
2205 | break; | 2205 | break; |
@@ -2224,7 +2224,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
2224 | offset + 4, radeon_bo_size(reloc->robj)); | 2224 | offset + 4, radeon_bo_size(reloc->robj)); |
2225 | return -EINVAL; | 2225 | return -EINVAL; |
2226 | } | 2226 | } |
2227 | offset += reloc->lobj.gpu_offset; | 2227 | offset += reloc->gpu_offset; |
2228 | ib[idx+1] = offset; | 2228 | ib[idx+1] = offset; |
2229 | ib[idx+2] = upper_32_bits(offset) & 0xff; | 2229 | ib[idx+2] = upper_32_bits(offset) & 0xff; |
2230 | } else { | 2230 | } else { |
@@ -2248,7 +2248,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
2248 | offset + 4, radeon_bo_size(reloc->robj)); | 2248 | offset + 4, radeon_bo_size(reloc->robj)); |
2249 | return -EINVAL; | 2249 | return -EINVAL; |
2250 | } | 2250 | } |
2251 | offset += reloc->lobj.gpu_offset; | 2251 | offset += reloc->gpu_offset; |
2252 | ib[idx+3] = offset; | 2252 | ib[idx+3] = offset; |
2253 | ib[idx+4] = upper_32_bits(offset) & 0xff; | 2253 | ib[idx+4] = upper_32_bits(offset) & 0xff; |
2254 | } else { | 2254 | } else { |
@@ -2505,14 +2505,14 @@ int r600_dma_cs_parse(struct radeon_cs_parser *p) | |||
2505 | dst_offset = radeon_get_ib_value(p, idx+1); | 2505 | dst_offset = radeon_get_ib_value(p, idx+1); |
2506 | dst_offset <<= 8; | 2506 | dst_offset <<= 8; |
2507 | 2507 | ||
2508 | ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8); | 2508 | ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); |
2509 | p->idx += count + 5; | 2509 | p->idx += count + 5; |
2510 | } else { | 2510 | } else { |
2511 | dst_offset = radeon_get_ib_value(p, idx+1); | 2511 | dst_offset = radeon_get_ib_value(p, idx+1); |
2512 | dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; | 2512 | dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; |
2513 | 2513 | ||
2514 | ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); | 2514 | ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); |
2515 | ib[idx+2] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; | 2515 | ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; |
2516 | p->idx += count + 3; | 2516 | p->idx += count + 3; |
2517 | } | 2517 | } |
2518 | if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { | 2518 | if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { |
@@ -2539,22 +2539,22 @@ int r600_dma_cs_parse(struct radeon_cs_parser *p) | |||
2539 | /* tiled src, linear dst */ | 2539 | /* tiled src, linear dst */ |
2540 | src_offset = radeon_get_ib_value(p, idx+1); | 2540 | src_offset = radeon_get_ib_value(p, idx+1); |
2541 | src_offset <<= 8; | 2541 | src_offset <<= 8; |
2542 | ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8); | 2542 | ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); |
2543 | 2543 | ||
2544 | dst_offset = radeon_get_ib_value(p, idx+5); | 2544 | dst_offset = radeon_get_ib_value(p, idx+5); |
2545 | dst_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; | 2545 | dst_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; |
2546 | ib[idx+5] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); | 2546 | ib[idx+5] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); |
2547 | ib[idx+6] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; | 2547 | ib[idx+6] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; |
2548 | } else { | 2548 | } else { |
2549 | /* linear src, tiled dst */ | 2549 | /* linear src, tiled dst */ |
2550 | src_offset = radeon_get_ib_value(p, idx+5); | 2550 | src_offset = radeon_get_ib_value(p, idx+5); |
2551 | src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; | 2551 | src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; |
2552 | ib[idx+5] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); | 2552 | ib[idx+5] += (u32)(src_reloc->gpu_offset & 0xfffffffc); |
2553 | ib[idx+6] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; | 2553 | ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff; |
2554 | 2554 | ||
2555 | dst_offset = radeon_get_ib_value(p, idx+1); | 2555 | dst_offset = radeon_get_ib_value(p, idx+1); |
2556 | dst_offset <<= 8; | 2556 | dst_offset <<= 8; |
2557 | ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8); | 2557 | ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); |
2558 | } | 2558 | } |
2559 | p->idx += 7; | 2559 | p->idx += 7; |
2560 | } else { | 2560 | } else { |
@@ -2564,10 +2564,10 @@ int r600_dma_cs_parse(struct radeon_cs_parser *p) | |||
2564 | dst_offset = radeon_get_ib_value(p, idx+1); | 2564 | dst_offset = radeon_get_ib_value(p, idx+1); |
2565 | dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; | 2565 | dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; |
2566 | 2566 | ||
2567 | ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); | 2567 | ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); |
2568 | ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); | 2568 | ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); |
2569 | ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; | 2569 | ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; |
2570 | ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; | 2570 | ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; |
2571 | p->idx += 5; | 2571 | p->idx += 5; |
2572 | } else { | 2572 | } else { |
2573 | src_offset = radeon_get_ib_value(p, idx+2); | 2573 | src_offset = radeon_get_ib_value(p, idx+2); |
@@ -2575,10 +2575,10 @@ int r600_dma_cs_parse(struct radeon_cs_parser *p) | |||
2575 | dst_offset = radeon_get_ib_value(p, idx+1); | 2575 | dst_offset = radeon_get_ib_value(p, idx+1); |
2576 | dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff0000)) << 16; | 2576 | dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff0000)) << 16; |
2577 | 2577 | ||
2578 | ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); | 2578 | ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); |
2579 | ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); | 2579 | ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); |
2580 | ib[idx+3] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; | 2580 | ib[idx+3] += upper_32_bits(src_reloc->gpu_offset) & 0xff; |
2581 | ib[idx+3] += (upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff) << 16; | 2581 | ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) & 0xff) << 16; |
2582 | p->idx += 4; | 2582 | p->idx += 4; |
2583 | } | 2583 | } |
2584 | } | 2584 | } |
@@ -2610,8 +2610,8 @@ int r600_dma_cs_parse(struct radeon_cs_parser *p) | |||
2610 | dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); | 2610 | dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); |
2611 | return -EINVAL; | 2611 | return -EINVAL; |
2612 | } | 2612 | } |
2613 | ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); | 2613 | ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); |
2614 | ib[idx+3] += (upper_32_bits(dst_reloc->lobj.gpu_offset) << 16) & 0x00ff0000; | 2614 | ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000; |
2615 | p->idx += 4; | 2615 | p->idx += 4; |
2616 | break; | 2616 | break; |
2617 | case DMA_PACKET_NOP: | 2617 | case DMA_PACKET_NOP: |
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index cd6a48099547..111deab2492a 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h | |||
@@ -479,15 +479,6 @@ struct radeon_bo { | |||
479 | }; | 479 | }; |
480 | #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) | 480 | #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) |
481 | 481 | ||
482 | struct radeon_bo_list { | ||
483 | struct ttm_validate_buffer tv; | ||
484 | struct radeon_bo *bo; | ||
485 | uint64_t gpu_offset; | ||
486 | unsigned domain; | ||
487 | unsigned alt_domain; | ||
488 | u32 tiling_flags; | ||
489 | }; | ||
490 | |||
491 | int radeon_gem_debugfs_init(struct radeon_device *rdev); | 482 | int radeon_gem_debugfs_init(struct radeon_device *rdev); |
492 | 483 | ||
493 | /* sub-allocation manager, it has to be protected by another lock. | 484 | /* sub-allocation manager, it has to be protected by another lock. |
@@ -987,9 +978,12 @@ void cayman_dma_fini(struct radeon_device *rdev); | |||
987 | struct radeon_cs_reloc { | 978 | struct radeon_cs_reloc { |
988 | struct drm_gem_object *gobj; | 979 | struct drm_gem_object *gobj; |
989 | struct radeon_bo *robj; | 980 | struct radeon_bo *robj; |
990 | struct radeon_bo_list lobj; | 981 | struct ttm_validate_buffer tv; |
982 | uint64_t gpu_offset; | ||
983 | unsigned domain; | ||
984 | unsigned alt_domain; | ||
985 | uint32_t tiling_flags; | ||
991 | uint32_t handle; | 986 | uint32_t handle; |
992 | uint32_t flags; | ||
993 | }; | 987 | }; |
994 | 988 | ||
995 | struct radeon_cs_chunk { | 989 | struct radeon_cs_chunk { |
@@ -1013,7 +1007,7 @@ struct radeon_cs_parser { | |||
1013 | unsigned nrelocs; | 1007 | unsigned nrelocs; |
1014 | struct radeon_cs_reloc *relocs; | 1008 | struct radeon_cs_reloc *relocs; |
1015 | struct radeon_cs_reloc **relocs_ptr; | 1009 | struct radeon_cs_reloc **relocs_ptr; |
1016 | struct radeon_bo_list *vm_bos; | 1010 | struct radeon_cs_reloc *vm_bos; |
1017 | struct list_head validated; | 1011 | struct list_head validated; |
1018 | unsigned dma_reloc_idx; | 1012 | unsigned dma_reloc_idx; |
1019 | /* indices of various chunks */ | 1013 | /* indices of various chunks */ |
@@ -2803,9 +2797,9 @@ int radeon_vm_manager_init(struct radeon_device *rdev); | |||
2803 | void radeon_vm_manager_fini(struct radeon_device *rdev); | 2797 | void radeon_vm_manager_fini(struct radeon_device *rdev); |
2804 | int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); | 2798 | int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); |
2805 | void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); | 2799 | void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); |
2806 | struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev, | 2800 | struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev, |
2807 | struct radeon_vm *vm, | 2801 | struct radeon_vm *vm, |
2808 | struct list_head *head); | 2802 | struct list_head *head); |
2809 | struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, | 2803 | struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, |
2810 | struct radeon_vm *vm, int ring); | 2804 | struct radeon_vm *vm, int ring); |
2811 | void radeon_vm_flush(struct radeon_device *rdev, | 2805 | void radeon_vm_flush(struct radeon_device *rdev, |
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c index 0570e7675fd3..2b6e0ebcc13a 100644 --- a/drivers/gpu/drm/radeon/radeon_cs.c +++ b/drivers/gpu/drm/radeon/radeon_cs.c | |||
@@ -125,7 +125,6 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) | |||
125 | } | 125 | } |
126 | p->relocs_ptr[i] = &p->relocs[i]; | 126 | p->relocs_ptr[i] = &p->relocs[i]; |
127 | p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj); | 127 | p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj); |
128 | p->relocs[i].lobj.bo = p->relocs[i].robj; | ||
129 | 128 | ||
130 | /* The userspace buffer priorities are from 0 to 15. A higher | 129 | /* The userspace buffer priorities are from 0 to 15. A higher |
131 | * number means the buffer is more important. | 130 | * number means the buffer is more important. |
@@ -141,10 +140,10 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) | |||
141 | if (p->ring == R600_RING_TYPE_UVD_INDEX && | 140 | if (p->ring == R600_RING_TYPE_UVD_INDEX && |
142 | (i == 0 || drm_pci_device_is_agp(p->rdev->ddev))) { | 141 | (i == 0 || drm_pci_device_is_agp(p->rdev->ddev))) { |
143 | /* TODO: is this still needed for NI+ ? */ | 142 | /* TODO: is this still needed for NI+ ? */ |
144 | p->relocs[i].lobj.domain = | 143 | p->relocs[i].domain = |
145 | RADEON_GEM_DOMAIN_VRAM; | 144 | RADEON_GEM_DOMAIN_VRAM; |
146 | 145 | ||
147 | p->relocs[i].lobj.alt_domain = | 146 | p->relocs[i].alt_domain = |
148 | RADEON_GEM_DOMAIN_VRAM; | 147 | RADEON_GEM_DOMAIN_VRAM; |
149 | 148 | ||
150 | /* prioritize this over any other relocation */ | 149 | /* prioritize this over any other relocation */ |
@@ -153,16 +152,16 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) | |||
153 | uint32_t domain = r->write_domain ? | 152 | uint32_t domain = r->write_domain ? |
154 | r->write_domain : r->read_domains; | 153 | r->write_domain : r->read_domains; |
155 | 154 | ||
156 | p->relocs[i].lobj.domain = domain; | 155 | p->relocs[i].domain = domain; |
157 | if (domain == RADEON_GEM_DOMAIN_VRAM) | 156 | if (domain == RADEON_GEM_DOMAIN_VRAM) |
158 | domain |= RADEON_GEM_DOMAIN_GTT; | 157 | domain |= RADEON_GEM_DOMAIN_GTT; |
159 | p->relocs[i].lobj.alt_domain = domain; | 158 | p->relocs[i].alt_domain = domain; |
160 | } | 159 | } |
161 | 160 | ||
162 | p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo; | 161 | p->relocs[i].tv.bo = &p->relocs[i].robj->tbo; |
163 | p->relocs[i].handle = r->handle; | 162 | p->relocs[i].handle = r->handle; |
164 | 163 | ||
165 | radeon_cs_buckets_add(&buckets, &p->relocs[i].lobj.tv.head, | 164 | radeon_cs_buckets_add(&buckets, &p->relocs[i].tv.head, |
166 | priority); | 165 | priority); |
167 | } | 166 | } |
168 | 167 | ||
@@ -356,11 +355,11 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data) | |||
356 | static int cmp_size_smaller_first(void *priv, struct list_head *a, | 355 | static int cmp_size_smaller_first(void *priv, struct list_head *a, |
357 | struct list_head *b) | 356 | struct list_head *b) |
358 | { | 357 | { |
359 | struct radeon_bo_list *la = list_entry(a, struct radeon_bo_list, tv.head); | 358 | struct radeon_cs_reloc *la = list_entry(a, struct radeon_cs_reloc, tv.head); |
360 | struct radeon_bo_list *lb = list_entry(b, struct radeon_bo_list, tv.head); | 359 | struct radeon_cs_reloc *lb = list_entry(b, struct radeon_cs_reloc, tv.head); |
361 | 360 | ||
362 | /* Sort A before B if A is smaller. */ | 361 | /* Sort A before B if A is smaller. */ |
363 | return (int)la->bo->tbo.num_pages - (int)lb->bo->tbo.num_pages; | 362 | return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages; |
364 | } | 363 | } |
365 | 364 | ||
366 | /** | 365 | /** |
@@ -786,9 +785,9 @@ int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, | |||
786 | /* FIXME: we assume reloc size is 4 dwords */ | 785 | /* FIXME: we assume reloc size is 4 dwords */ |
787 | if (nomm) { | 786 | if (nomm) { |
788 | *cs_reloc = p->relocs; | 787 | *cs_reloc = p->relocs; |
789 | (*cs_reloc)->lobj.gpu_offset = | 788 | (*cs_reloc)->gpu_offset = |
790 | (u64)relocs_chunk->kdata[idx + 3] << 32; | 789 | (u64)relocs_chunk->kdata[idx + 3] << 32; |
791 | (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0]; | 790 | (*cs_reloc)->gpu_offset |= relocs_chunk->kdata[idx + 0]; |
792 | } else | 791 | } else |
793 | *cs_reloc = p->relocs_ptr[(idx / 4)]; | 792 | *cs_reloc = p->relocs_ptr[(idx / 4)]; |
794 | return 0; | 793 | return 0; |
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c index ed03f2d15853..ca79431b2c1c 100644 --- a/drivers/gpu/drm/radeon/radeon_object.c +++ b/drivers/gpu/drm/radeon/radeon_object.c | |||
@@ -422,7 +422,7 @@ int radeon_bo_list_validate(struct radeon_device *rdev, | |||
422 | struct ww_acquire_ctx *ticket, | 422 | struct ww_acquire_ctx *ticket, |
423 | struct list_head *head, int ring) | 423 | struct list_head *head, int ring) |
424 | { | 424 | { |
425 | struct radeon_bo_list *lobj; | 425 | struct radeon_cs_reloc *lobj; |
426 | struct radeon_bo *bo; | 426 | struct radeon_bo *bo; |
427 | int r; | 427 | int r; |
428 | u64 bytes_moved = 0, initial_bytes_moved; | 428 | u64 bytes_moved = 0, initial_bytes_moved; |
@@ -434,7 +434,7 @@ int radeon_bo_list_validate(struct radeon_device *rdev, | |||
434 | } | 434 | } |
435 | 435 | ||
436 | list_for_each_entry(lobj, head, tv.head) { | 436 | list_for_each_entry(lobj, head, tv.head) { |
437 | bo = lobj->bo; | 437 | bo = lobj->robj; |
438 | if (!bo->pin_count) { | 438 | if (!bo->pin_count) { |
439 | u32 domain = lobj->domain; | 439 | u32 domain = lobj->domain; |
440 | u32 current_domain = | 440 | u32 current_domain = |
diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c b/drivers/gpu/drm/radeon/radeon_uvd.c index ceb7b289b745..6a2e3ff68374 100644 --- a/drivers/gpu/drm/radeon/radeon_uvd.c +++ b/drivers/gpu/drm/radeon/radeon_uvd.c | |||
@@ -453,7 +453,7 @@ static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p, | |||
453 | } | 453 | } |
454 | 454 | ||
455 | reloc = p->relocs_ptr[(idx / 4)]; | 455 | reloc = p->relocs_ptr[(idx / 4)]; |
456 | start = reloc->lobj.gpu_offset; | 456 | start = reloc->gpu_offset; |
457 | end = start + radeon_bo_size(reloc->robj); | 457 | end = start + radeon_bo_size(reloc->robj); |
458 | start += offset; | 458 | start += offset; |
459 | 459 | ||
diff --git a/drivers/gpu/drm/radeon/radeon_vce.c b/drivers/gpu/drm/radeon/radeon_vce.c index 39ec7d8f33ab..76e9904bc537 100644 --- a/drivers/gpu/drm/radeon/radeon_vce.c +++ b/drivers/gpu/drm/radeon/radeon_vce.c | |||
@@ -461,7 +461,7 @@ int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi) | |||
461 | return -EINVAL; | 461 | return -EINVAL; |
462 | } | 462 | } |
463 | 463 | ||
464 | offset += p->relocs_ptr[(idx / 4)]->lobj.gpu_offset; | 464 | offset += p->relocs_ptr[(idx / 4)]->gpu_offset; |
465 | 465 | ||
466 | p->ib.ptr[lo] = offset & 0xFFFFFFFF; | 466 | p->ib.ptr[lo] = offset & 0xFFFFFFFF; |
467 | p->ib.ptr[hi] = offset >> 32; | 467 | p->ib.ptr[hi] = offset >> 32; |
diff --git a/drivers/gpu/drm/radeon/radeon_vm.c b/drivers/gpu/drm/radeon/radeon_vm.c index 81d91b513ce1..2aae6ce49d32 100644 --- a/drivers/gpu/drm/radeon/radeon_vm.c +++ b/drivers/gpu/drm/radeon/radeon_vm.c | |||
@@ -125,33 +125,39 @@ void radeon_vm_manager_fini(struct radeon_device *rdev) | |||
125 | * Add the page directory to the list of BOs to | 125 | * Add the page directory to the list of BOs to |
126 | * validate for command submission (cayman+). | 126 | * validate for command submission (cayman+). |
127 | */ | 127 | */ |
128 | struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev, | 128 | struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev, |
129 | struct radeon_vm *vm, | 129 | struct radeon_vm *vm, |
130 | struct list_head *head) | 130 | struct list_head *head) |
131 | { | 131 | { |
132 | struct radeon_bo_list *list; | 132 | struct radeon_cs_reloc *list; |
133 | unsigned i, idx, size; | 133 | unsigned i, idx, size; |
134 | 134 | ||
135 | size = (radeon_vm_num_pdes(rdev) + 1) * sizeof(struct radeon_bo_list); | 135 | size = (radeon_vm_num_pdes(rdev) + 1) * sizeof(struct radeon_cs_reloc); |
136 | list = kmalloc(size, GFP_KERNEL); | 136 | list = kmalloc(size, GFP_KERNEL); |
137 | if (!list) | 137 | if (!list) |
138 | return NULL; | 138 | return NULL; |
139 | 139 | ||
140 | /* add the vm page table to the list */ | 140 | /* add the vm page table to the list */ |
141 | list[0].bo = vm->page_directory; | 141 | list[0].gobj = NULL; |
142 | list[0].robj = vm->page_directory; | ||
142 | list[0].domain = RADEON_GEM_DOMAIN_VRAM; | 143 | list[0].domain = RADEON_GEM_DOMAIN_VRAM; |
143 | list[0].alt_domain = RADEON_GEM_DOMAIN_VRAM; | 144 | list[0].alt_domain = RADEON_GEM_DOMAIN_VRAM; |
144 | list[0].tv.bo = &vm->page_directory->tbo; | 145 | list[0].tv.bo = &vm->page_directory->tbo; |
146 | list[0].tiling_flags = 0; | ||
147 | list[0].handle = 0; | ||
145 | list_add(&list[0].tv.head, head); | 148 | list_add(&list[0].tv.head, head); |
146 | 149 | ||
147 | for (i = 0, idx = 1; i <= vm->max_pde_used; i++) { | 150 | for (i = 0, idx = 1; i <= vm->max_pde_used; i++) { |
148 | if (!vm->page_tables[i].bo) | 151 | if (!vm->page_tables[i].bo) |
149 | continue; | 152 | continue; |
150 | 153 | ||
151 | list[idx].bo = vm->page_tables[i].bo; | 154 | list[idx].gobj = NULL; |
155 | list[idx].robj = vm->page_tables[i].bo; | ||
152 | list[idx].domain = RADEON_GEM_DOMAIN_VRAM; | 156 | list[idx].domain = RADEON_GEM_DOMAIN_VRAM; |
153 | list[idx].alt_domain = RADEON_GEM_DOMAIN_VRAM; | 157 | list[idx].alt_domain = RADEON_GEM_DOMAIN_VRAM; |
154 | list[idx].tv.bo = &list[idx].bo->tbo; | 158 | list[idx].tv.bo = &list[idx].robj->tbo; |
159 | list[idx].tiling_flags = 0; | ||
160 | list[idx].handle = 0; | ||
155 | list_add(&list[idx++].tv.head, head); | 161 | list_add(&list[idx++].tv.head, head); |
156 | } | 162 | } |
157 | 163 | ||