Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson:
 "A smaller set of fixes this week, and all regression fixes:
   - a handful of issues fixed on at91 with common clock conversion
   - a set of fixes for Marvell mvebu (SMP, coherency, PM)
   - a clock fix for i.MX6Q.
   - ... and a SMP/hotplug fix for Exynos"

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: EXYNOS: Fix core ID used by platsmp and hotplug code
  ARM: at91/dt: add missing clocks property to pwm node in sam9x5.dtsi
  ARM: at91/dt: fix usb0 clocks definition in sam9n12 dtsi
  ARM: at91: at91sam9x5: correct typo error for ohci clock
  ARM: clk-imx6q: parent lvds_sel input from upstream clock gates
  ARM: mvebu: Fix coherency bus notifiers by using separate notifiers
  ARM: mvebu: Fix the operand list in the inline asm of armada_370_xp_pmsu_idle_enter
  ARM: mvebu: fix SMP boot for Armada 38x and Armada 375 Z1 in big endian

8 files changed, 48 insertions, 31 deletions

diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 287795985e32..b84bac5bada4 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -925,7 +925,7 @@
                         compatible = "atmel,at91rm9200-ohci", "usb-ohci";
                         reg = <0x00500000 0x00100000>;
                         interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
-                        clocks = <&usb>, <&uhphs_clk>, <&udphs_clk>,
+                        clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
                                  <&uhpck>;
                         clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
                         status = "disabled";
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 2ebc42140ea6..2c0d6ea3ab41 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -1124,6 +1124,7 @@
                                 compatible = "atmel,at91sam9rl-pwm";
                                 reg = <0xf8034000 0x300>;
                                 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
+                                clocks = <&pwm_clk>;
                                 #pwm-cells = <3>;
                                 status = "disabled";
                         };
@@ -1155,8 +1156,7 @@
                         compatible = "atmel,at91rm9200-ohci", "usb-ohci";
                         reg = <0x00600000 0x100000>;
                         interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
-                        clocks = <&usb>, <&uhphs_clk>, <&udphs_clk>,
-                                 <&uhpck>;
+                        clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
                         clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
                         status = "disabled";
                 };
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 8a134d019cb3..920a4baa53cd 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -40,15 +40,17 @@ static inline void cpu_leave_lowpower(void)
 
 static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
 {
+        u32 mpidr = cpu_logical_map(cpu);
+        u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+
         for (;;) {
 
-                /* make cpu1 to be turned off at next WFI command */
-                if (cpu == 1)
-                        exynos_cpu_power_down(cpu);
+                /* Turn the CPU off on next WFI instruction. */
+                exynos_cpu_power_down(core_id);
 
                 wfi();
 
-                if (pen_release == cpu_logical_map(cpu)) {
+                if (pen_release == core_id) {
                         /*
                          * OK, proper wakeup, we're done
                          */
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 1c8d31e39520..50b9aad5e27b 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -90,7 +90,8 @@ static void exynos_secondary_init(unsigned int cpu)
 static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         unsigned long timeout;
-        unsigned long phys_cpu = cpu_logical_map(cpu);
+        u32 mpidr = cpu_logical_map(cpu);
+        u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
         int ret = -ENOSYS;
 
         /*
@@ -104,17 +105,18 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
          * the holding pen - release it, then wait for it to flag
          * that it has been released by resetting pen_release.
          *
-         * Note that "pen_release" is the hardware CPU ID, whereas
+         * Note that "pen_release" is the hardware CPU core ID, whereas
          * "cpu" is Linux's internal ID.
          */
-        write_pen_release(phys_cpu);
+        write_pen_release(core_id);
 
-        if (!exynos_cpu_power_state(cpu)) {
-                exynos_cpu_power_up(cpu);
+        if (!exynos_cpu_power_state(core_id)) {
+                exynos_cpu_power_up(core_id);
                 timeout = 10;
 
                 /* wait max 10 ms until cpu1 is on */
-                while (exynos_cpu_power_state(cpu) != S5P_CORE_LOCAL_PWR_EN) {
+                while (exynos_cpu_power_state(core_id)
+                       != S5P_CORE_LOCAL_PWR_EN) {
                         if (timeout-- == 0)
                                 break;
 
@@ -145,20 +147,20 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
                  * Try to set boot address using firmware first
                  * and fall back to boot register if it fails.
                  */
-                ret = call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr);
+                ret = call_firmware_op(set_cpu_boot_addr, core_id, boot_addr);
                 if (ret && ret != -ENOSYS)
                         goto fail;
                 if (ret == -ENOSYS) {
-                        void __iomem *boot_reg = cpu_boot_reg(phys_cpu);
+                        void __iomem *boot_reg = cpu_boot_reg(core_id);
 
                         if (IS_ERR(boot_reg)) {
                                 ret = PTR_ERR(boot_reg);
                                 goto fail;
                         }
-                        __raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
+                        __raw_writel(boot_addr, cpu_boot_reg(core_id));
                 }
 
-                call_firmware_op(cpu_boot, phys_cpu);
+                call_firmware_op(cpu_boot, core_id);
 
                 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
 
@@ -227,22 +229,24 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
          * boot register if it fails.
          */
         for (i = 1; i < max_cpus; ++i) {
-                unsigned long phys_cpu;
                 unsigned long boot_addr;
+                u32 mpidr;
+                u32 core_id;
                 int ret;
 
-                phys_cpu = cpu_logical_map(i);
+                mpidr = cpu_logical_map(i);
+                core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
                 boot_addr = virt_to_phys(exynos4_secondary_startup);
 
-                ret = call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr);
+                ret = call_firmware_op(set_cpu_boot_addr, core_id, boot_addr);
                 if (ret && ret != -ENOSYS)
                         break;
                 if (ret == -ENOSYS) {
-                        void __iomem *boot_reg = cpu_boot_reg(phys_cpu);
+                        void __iomem *boot_reg = cpu_boot_reg(core_id);
 
                         if (IS_ERR(boot_reg))
                                 break;
-                        __raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
+                        __raw_writel(boot_addr, cpu_boot_reg(core_id));
                 }
         }
 }
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 8e795dea02ec..8556c787e59c 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -70,7 +70,7 @@ static const char *cko_sels[] = { "cko1", "cko2", };
 static const char *lvds_sels[] = {
         "dummy", "dummy", "dummy", "dummy", "dummy", "dummy",
         "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref",
-        "pcie_ref", "sata_ref",
+        "pcie_ref_125m", "sata_ref_100m",
 };
 
 enum mx6q_clks {
@@ -491,7 +491,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 
         /* All existing boards with PCIe use LVDS1 */
         if (IS_ENABLED(CONFIG_PCI_IMX6))
-                clk_set_parent(clk[lvds1_sel], clk[sata_ref]);
+                clk_set_parent(clk[lvds1_sel], clk[sata_ref_100m]);
 
         /* Set initial power mode */
         imx6q_set_lpm(WAIT_CLOCKED);
diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
index 477202fd39cc..2bdc3233abe2 100644
--- a/arch/arm/mach-mvebu/coherency.c
+++ b/arch/arm/mach-mvebu/coherency.c
@@ -292,6 +292,10 @@ static struct notifier_block mvebu_hwcc_nb = {
         .notifier_call = mvebu_hwcc_notifier,
 };
 
+static struct notifier_block mvebu_hwcc_pci_nb = {
+        .notifier_call = mvebu_hwcc_notifier,
+};
+
 static void __init armada_370_coherency_init(struct device_node *np)
 {
         struct resource res;
@@ -427,7 +431,7 @@ static int __init coherency_pci_init(void)
 {
         if (coherency_available())
                 bus_register_notifier(&pci_bus_type,
-                                       &mvebu_hwcc_nb);
+                                       &mvebu_hwcc_pci_nb);
         return 0;
 }
 
diff --git a/arch/arm/mach-mvebu/headsmp-a9.S b/arch/arm/mach-mvebu/headsmp-a9.S
index 5925366bc03c..da5bb292b91c 100644
--- a/arch/arm/mach-mvebu/headsmp-a9.S
+++ b/arch/arm/mach-mvebu/headsmp-a9.S
@@ -15,6 +15,8 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 
+#include <asm/assembler.h>
+
         __CPUINIT
 #define CPU_RESUME_ADDR_REG 0xf10182d4
 
@@ -22,13 +24,18 @@
 .global armada_375_smp_cpu1_enable_code_end
 
 armada_375_smp_cpu1_enable_code_start:
-        ldr     r0, [pc, #4]
+ARM_BE8(setend  be)
+        adr     r0, 1f
+        ldr     r0, [r0]
         ldr     r1, [r0]
+ARM_BE8(rev     r1, r1)
         mov     pc, r1
+1:
         .word   CPU_RESUME_ADDR_REG
 armada_375_smp_cpu1_enable_code_end:
 
 ENTRY(mvebu_cortex_a9_secondary_startup)
+ARM_BE8(setend  be)
         bl      v7_invalidate_l1
         b       secondary_startup
 ENDPROC(mvebu_cortex_a9_secondary_startup)
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index a1d407c0febe..25aa8237d668 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -201,12 +201,12 @@ static noinline int do_armada_370_xp_cpu_suspend(unsigned long deepidle)
 
         /* Test the CR_C bit and set it if it was cleared */
         asm volatile(
-        "mrc    p15, 0, %0, c1, c0, 0 \n\t"
-        "tst    %0, #(1 << 2) \n\t"
-        "orreq  %0, %0, #(1 << 2) \n\t"
-        "mcreq  p15, 0, %0, c1, c0, 0 \n\t"
+        "mrc    p15, 0, r0, c1, c0, 0 \n\t"
+        "tst    r0, #(1 << 2) \n\t"
+        "orreq  r0, r0, #(1 << 2) \n\t"
+        "mcreq  p15, 0, r0, c1, c0, 0 \n\t"
         "isb    "
-        : : "r" (0));
+        : : : "r0");
 
         pr_warn("Failed to suspend the system\n");