diff options
author | Dan Carpenter <dan.carpenter@oracle.com> | 2014-05-05 04:53:05 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2014-05-07 15:44:24 -0400 |
commit | d1f88a667c16e38d5a796b5fcdfd4ddbac1f638f (patch) | |
tree | 4ecdf94894ea939694cc61399e472c3d412f7c6e | |
parent | d28071d102f232d92e52af06d242d041074b54b6 (diff) |
isdn: hisax: remove some dead code
The HISAX_HFC4S8S_PCIMEM code hasn't been able to compile since before
the start of git history. I have deleted it.
There are also a few indenting mistakes where one side of the ifdef
wasn't indented correctly which I fixed as well.
Reported-by: Walter Harms <wharms@bfs.de>
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r-- | drivers/isdn/hisax/hfc4s8s_l1.c | 111 |
1 files changed, 4 insertions, 107 deletions
diff --git a/drivers/isdn/hisax/hfc4s8s_l1.c b/drivers/isdn/hisax/hfc4s8s_l1.c index 414dbf6da89a..fc9f9d03fa13 100644 --- a/drivers/isdn/hisax/hfc4s8s_l1.c +++ b/drivers/isdn/hisax/hfc4s8s_l1.c | |||
@@ -197,25 +197,6 @@ typedef struct _hfc4s8s_hw { | |||
197 | 197 | ||
198 | 198 | ||
199 | 199 | ||
200 | /***************************/ | ||
201 | /* inline function defines */ | ||
202 | /***************************/ | ||
203 | #ifdef HISAX_HFC4S8S_PCIMEM /* inline functions memory mapped */ | ||
204 | |||
205 | /* memory write and dummy IO read to avoid PCI byte merge problems */ | ||
206 | #define Write_hfc8(a, b, c) {(*((volatile u_char *)(a->membase + b)) = c); inb(a->iobase + 4);} | ||
207 | /* memory write without dummy IO access for fifo data access */ | ||
208 | #define fWrite_hfc8(a, b, c) (*((volatile u_char *)(a->membase + b)) = c) | ||
209 | #define Read_hfc8(a, b) (*((volatile u_char *)(a->membase + b))) | ||
210 | #define Write_hfc16(a, b, c) (*((volatile unsigned short *)(a->membase + b)) = c) | ||
211 | #define Read_hfc16(a, b) (*((volatile unsigned short *)(a->membase + b))) | ||
212 | #define Write_hfc32(a, b, c) (*((volatile unsigned long *)(a->membase + b)) = c) | ||
213 | #define Read_hfc32(a, b) (*((volatile unsigned long *)(a->membase + b))) | ||
214 | #define wait_busy(a) {while ((Read_hfc8(a, R_STATUS) & M_BUSY));} | ||
215 | #define PCI_ENA_MEMIO 0x03 | ||
216 | |||
217 | #else | ||
218 | |||
219 | /* inline functions io mapped */ | 200 | /* inline functions io mapped */ |
220 | static inline void | 201 | static inline void |
221 | SetRegAddr(hfc4s8s_hw *a, u_char b) | 202 | SetRegAddr(hfc4s8s_hw *a, u_char b) |
@@ -306,8 +287,6 @@ wait_busy(hfc4s8s_hw *a) | |||
306 | 287 | ||
307 | #define PCI_ENA_REGIO 0x01 | 288 | #define PCI_ENA_REGIO 0x01 |
308 | 289 | ||
309 | #endif /* HISAX_HFC4S8S_PCIMEM */ | ||
310 | |||
311 | /******************************************************/ | 290 | /******************************************************/ |
312 | /* function to read critical counter registers that */ | 291 | /* function to read critical counter registers that */ |
313 | /* may be updated by the chip during read */ | 292 | /* may be updated by the chip during read */ |
@@ -724,26 +703,15 @@ rx_d_frame(struct hfc4s8s_l1 *l1p, int ech) | |||
724 | return; | 703 | return; |
725 | } else { | 704 | } else { |
726 | /* read errornous D frame */ | 705 | /* read errornous D frame */ |
727 | |||
728 | #ifndef HISAX_HFC4S8S_PCIMEM | ||
729 | SetRegAddr(l1p->hw, A_FIFO_DATA0); | 706 | SetRegAddr(l1p->hw, A_FIFO_DATA0); |
730 | #endif | ||
731 | 707 | ||
732 | while (z1 >= 4) { | 708 | while (z1 >= 4) { |
733 | #ifdef HISAX_HFC4S8S_PCIMEM | ||
734 | Read_hfc32(l1p->hw, A_FIFO_DATA0); | ||
735 | #else | ||
736 | fRead_hfc32(l1p->hw); | 709 | fRead_hfc32(l1p->hw); |
737 | #endif | ||
738 | z1 -= 4; | 710 | z1 -= 4; |
739 | } | 711 | } |
740 | 712 | ||
741 | while (z1--) | 713 | while (z1--) |
742 | #ifdef HISAX_HFC4S8S_PCIMEM | 714 | fRead_hfc8(l1p->hw); |
743 | Read_hfc8(l1p->hw, A_FIFO_DATA0); | ||
744 | #else | ||
745 | fRead_hfc8(l1p->hw); | ||
746 | #endif | ||
747 | 715 | ||
748 | Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); | 716 | Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); |
749 | wait_busy(l1p->hw); | 717 | wait_busy(l1p->hw); |
@@ -753,27 +721,16 @@ rx_d_frame(struct hfc4s8s_l1 *l1p, int ech) | |||
753 | 721 | ||
754 | cp = skb->data; | 722 | cp = skb->data; |
755 | 723 | ||
756 | #ifndef HISAX_HFC4S8S_PCIMEM | ||
757 | SetRegAddr(l1p->hw, A_FIFO_DATA0); | 724 | SetRegAddr(l1p->hw, A_FIFO_DATA0); |
758 | #endif | ||
759 | 725 | ||
760 | while (z1 >= 4) { | 726 | while (z1 >= 4) { |
761 | #ifdef HISAX_HFC4S8S_PCIMEM | ||
762 | *((unsigned long *) cp) = | ||
763 | Read_hfc32(l1p->hw, A_FIFO_DATA0); | ||
764 | #else | ||
765 | *((unsigned long *) cp) = fRead_hfc32(l1p->hw); | 727 | *((unsigned long *) cp) = fRead_hfc32(l1p->hw); |
766 | #endif | ||
767 | cp += 4; | 728 | cp += 4; |
768 | z1 -= 4; | 729 | z1 -= 4; |
769 | } | 730 | } |
770 | 731 | ||
771 | while (z1--) | 732 | while (z1--) |
772 | #ifdef HISAX_HFC4S8S_PCIMEM | 733 | *cp++ = fRead_hfc8(l1p->hw); |
773 | *cp++ = Read_hfc8(l1p->hw, A_FIFO_DATA0); | ||
774 | #else | ||
775 | *cp++ = fRead_hfc8(l1p->hw); | ||
776 | #endif | ||
777 | 734 | ||
778 | Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); /* increment f counter */ | 735 | Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); /* increment f counter */ |
779 | wait_busy(l1p->hw); | 736 | wait_busy(l1p->hw); |
@@ -859,28 +816,17 @@ rx_b_frame(struct hfc4s8s_btype *bch) | |||
859 | wait_busy(l1->hw); | 816 | wait_busy(l1->hw); |
860 | return; | 817 | return; |
861 | } | 818 | } |
862 | #ifndef HISAX_HFC4S8S_PCIMEM | ||
863 | SetRegAddr(l1->hw, A_FIFO_DATA0); | 819 | SetRegAddr(l1->hw, A_FIFO_DATA0); |
864 | #endif | ||
865 | 820 | ||
866 | while (z1 >= 4) { | 821 | while (z1 >= 4) { |
867 | #ifdef HISAX_HFC4S8S_PCIMEM | ||
868 | *((unsigned long *) bch->rx_ptr) = | ||
869 | Read_hfc32(l1->hw, A_FIFO_DATA0); | ||
870 | #else | ||
871 | *((unsigned long *) bch->rx_ptr) = | 822 | *((unsigned long *) bch->rx_ptr) = |
872 | fRead_hfc32(l1->hw); | 823 | fRead_hfc32(l1->hw); |
873 | #endif | ||
874 | bch->rx_ptr += 4; | 824 | bch->rx_ptr += 4; |
875 | z1 -= 4; | 825 | z1 -= 4; |
876 | } | 826 | } |
877 | 827 | ||
878 | while (z1--) | 828 | while (z1--) |
879 | #ifdef HISAX_HFC4S8S_PCIMEM | 829 | *(bch->rx_ptr++) = fRead_hfc8(l1->hw); |
880 | *(bch->rx_ptr++) = Read_hfc8(l1->hw, A_FIFO_DATA0); | ||
881 | #else | ||
882 | *(bch->rx_ptr++) = fRead_hfc8(l1->hw); | ||
883 | #endif | ||
884 | 830 | ||
885 | if (hdlc_complete) { | 831 | if (hdlc_complete) { |
886 | /* increment f counter */ | 832 | /* increment f counter */ |
@@ -940,29 +886,17 @@ tx_d_frame(struct hfc4s8s_l1 *l1p) | |||
940 | if ((skb = skb_dequeue(&l1p->d_tx_queue))) { | 886 | if ((skb = skb_dequeue(&l1p->d_tx_queue))) { |
941 | cp = skb->data; | 887 | cp = skb->data; |
942 | cnt = skb->len; | 888 | cnt = skb->len; |
943 | #ifndef HISAX_HFC4S8S_PCIMEM | ||
944 | SetRegAddr(l1p->hw, A_FIFO_DATA0); | 889 | SetRegAddr(l1p->hw, A_FIFO_DATA0); |
945 | #endif | ||
946 | 890 | ||
947 | while (cnt >= 4) { | 891 | while (cnt >= 4) { |
948 | #ifdef HISAX_HFC4S8S_PCIMEM | ||
949 | fWrite_hfc32(l1p->hw, A_FIFO_DATA0, | ||
950 | *(unsigned long *) cp); | ||
951 | #else | ||
952 | SetRegAddr(l1p->hw, A_FIFO_DATA0); | 892 | SetRegAddr(l1p->hw, A_FIFO_DATA0); |
953 | fWrite_hfc32(l1p->hw, *(unsigned long *) cp); | 893 | fWrite_hfc32(l1p->hw, *(unsigned long *) cp); |
954 | #endif | ||
955 | cp += 4; | 894 | cp += 4; |
956 | cnt -= 4; | 895 | cnt -= 4; |
957 | } | 896 | } |
958 | 897 | ||
959 | #ifdef HISAX_HFC4S8S_PCIMEM | ||
960 | while (cnt--) | ||
961 | fWrite_hfc8(l1p->hw, A_FIFO_DATA0, *cp++); | ||
962 | #else | ||
963 | while (cnt--) | 898 | while (cnt--) |
964 | fWrite_hfc8(l1p->hw, *cp++); | 899 | fWrite_hfc8(l1p->hw, *cp++); |
965 | #endif | ||
966 | 900 | ||
967 | l1p->tx_cnt = skb->truesize; | 901 | l1p->tx_cnt = skb->truesize; |
968 | Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); /* increment f counter */ | 902 | Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); /* increment f counter */ |
@@ -1037,26 +971,15 @@ tx_b_frame(struct hfc4s8s_btype *bch) | |||
1037 | cp = skb->data + bch->tx_cnt; | 971 | cp = skb->data + bch->tx_cnt; |
1038 | bch->tx_cnt += cnt; | 972 | bch->tx_cnt += cnt; |
1039 | 973 | ||
1040 | #ifndef HISAX_HFC4S8S_PCIMEM | ||
1041 | SetRegAddr(l1->hw, A_FIFO_DATA0); | 974 | SetRegAddr(l1->hw, A_FIFO_DATA0); |
1042 | #endif | ||
1043 | while (cnt >= 4) { | 975 | while (cnt >= 4) { |
1044 | #ifdef HISAX_HFC4S8S_PCIMEM | ||
1045 | fWrite_hfc32(l1->hw, A_FIFO_DATA0, | ||
1046 | *(unsigned long *) cp); | ||
1047 | #else | ||
1048 | fWrite_hfc32(l1->hw, *(unsigned long *) cp); | 976 | fWrite_hfc32(l1->hw, *(unsigned long *) cp); |
1049 | #endif | ||
1050 | cp += 4; | 977 | cp += 4; |
1051 | cnt -= 4; | 978 | cnt -= 4; |
1052 | } | 979 | } |
1053 | 980 | ||
1054 | while (cnt--) | 981 | while (cnt--) |
1055 | #ifdef HISAX_HFC4S8S_PCIMEM | 982 | fWrite_hfc8(l1->hw, *cp++); |
1056 | fWrite_hfc8(l1->hw, A_FIFO_DATA0, *cp++); | ||
1057 | #else | ||
1058 | fWrite_hfc8(l1->hw, *cp++); | ||
1059 | #endif | ||
1060 | 983 | ||
1061 | if (bch->tx_cnt >= skb->len) { | 984 | if (bch->tx_cnt >= skb->len) { |
1062 | if (bch->mode == L1_MODE_HDLC) { | 985 | if (bch->mode == L1_MODE_HDLC) { |
@@ -1281,10 +1204,8 @@ hfc4s8s_interrupt(int intno, void *dev_id) | |||
1281 | if (!hw || !(hw->mr.r_irq_ctrl & M_GLOB_IRQ_EN)) | 1204 | if (!hw || !(hw->mr.r_irq_ctrl & M_GLOB_IRQ_EN)) |
1282 | return IRQ_NONE; | 1205 | return IRQ_NONE; |
1283 | 1206 | ||
1284 | #ifndef HISAX_HFC4S8S_PCIMEM | ||
1285 | /* read current selected regsister */ | 1207 | /* read current selected regsister */ |
1286 | old_ioreg = GetRegAddr(hw); | 1208 | old_ioreg = GetRegAddr(hw); |
1287 | #endif | ||
1288 | 1209 | ||
1289 | /* Layer 1 State change */ | 1210 | /* Layer 1 State change */ |
1290 | hw->mr.r_irq_statech |= | 1211 | hw->mr.r_irq_statech |= |
@@ -1292,9 +1213,7 @@ hfc4s8s_interrupt(int intno, void *dev_id) | |||
1292 | if (! | 1213 | if (! |
1293 | (b = (Read_hfc8(hw, R_STATUS) & (M_MISC_IRQSTA | M_FR_IRQSTA))) | 1214 | (b = (Read_hfc8(hw, R_STATUS) & (M_MISC_IRQSTA | M_FR_IRQSTA))) |
1294 | && !hw->mr.r_irq_statech) { | 1215 | && !hw->mr.r_irq_statech) { |
1295 | #ifndef HISAX_HFC4S8S_PCIMEM | ||
1296 | SetRegAddr(hw, old_ioreg); | 1216 | SetRegAddr(hw, old_ioreg); |
1297 | #endif | ||
1298 | return IRQ_NONE; | 1217 | return IRQ_NONE; |
1299 | } | 1218 | } |
1300 | 1219 | ||
@@ -1322,9 +1241,7 @@ hfc4s8s_interrupt(int intno, void *dev_id) | |||
1322 | /* queue the request to allow other cards to interrupt */ | 1241 | /* queue the request to allow other cards to interrupt */ |
1323 | schedule_work(&hw->tqueue); | 1242 | schedule_work(&hw->tqueue); |
1324 | 1243 | ||
1325 | #ifndef HISAX_HFC4S8S_PCIMEM | ||
1326 | SetRegAddr(hw, old_ioreg); | 1244 | SetRegAddr(hw, old_ioreg); |
1327 | #endif | ||
1328 | return IRQ_HANDLED; | 1245 | return IRQ_HANDLED; |
1329 | } /* hfc4s8s_interrupt */ | 1246 | } /* hfc4s8s_interrupt */ |
1330 | 1247 | ||
@@ -1471,13 +1388,8 @@ static void | |||
1471 | release_pci_ports(hfc4s8s_hw *hw) | 1388 | release_pci_ports(hfc4s8s_hw *hw) |
1472 | { | 1389 | { |
1473 | pci_write_config_word(hw->pdev, PCI_COMMAND, 0); | 1390 | pci_write_config_word(hw->pdev, PCI_COMMAND, 0); |
1474 | #ifdef HISAX_HFC4S8S_PCIMEM | ||
1475 | if (hw->membase) | ||
1476 | iounmap((void *) hw->membase); | ||
1477 | #else | ||
1478 | if (hw->iobase) | 1391 | if (hw->iobase) |
1479 | release_region(hw->iobase, 8); | 1392 | release_region(hw->iobase, 8); |
1480 | #endif | ||
1481 | } | 1393 | } |
1482 | 1394 | ||
1483 | /*****************************************/ | 1395 | /*****************************************/ |
@@ -1486,11 +1398,7 @@ release_pci_ports(hfc4s8s_hw *hw) | |||
1486 | static void | 1398 | static void |
1487 | enable_pci_ports(hfc4s8s_hw *hw) | 1399 | enable_pci_ports(hfc4s8s_hw *hw) |
1488 | { | 1400 | { |
1489 | #ifdef HISAX_HFC4S8S_PCIMEM | ||
1490 | pci_write_config_word(hw->pdev, PCI_COMMAND, PCI_ENA_MEMIO); | ||
1491 | #else | ||
1492 | pci_write_config_word(hw->pdev, PCI_COMMAND, PCI_ENA_REGIO); | 1401 | pci_write_config_word(hw->pdev, PCI_COMMAND, PCI_ENA_REGIO); |
1493 | #endif | ||
1494 | } | 1402 | } |
1495 | 1403 | ||
1496 | /*************************************/ | 1404 | /*************************************/ |
@@ -1561,15 +1469,9 @@ setup_instance(hfc4s8s_hw *hw) | |||
1561 | hw->irq); | 1469 | hw->irq); |
1562 | goto out; | 1470 | goto out; |
1563 | } | 1471 | } |
1564 | #ifdef HISAX_HFC4S8S_PCIMEM | ||
1565 | printk(KERN_INFO | ||
1566 | "HFC-4S/8S: found PCI card at membase 0x%p, irq %d\n", | ||
1567 | hw->hw_membase, hw->irq); | ||
1568 | #else | ||
1569 | printk(KERN_INFO | 1472 | printk(KERN_INFO |
1570 | "HFC-4S/8S: found PCI card at iobase 0x%x, irq %d\n", | 1473 | "HFC-4S/8S: found PCI card at iobase 0x%x, irq %d\n", |
1571 | hw->iobase, hw->irq); | 1474 | hw->iobase, hw->irq); |
1572 | #endif | ||
1573 | 1475 | ||
1574 | hfc_hardware_enable(hw, 1, 0); | 1476 | hfc_hardware_enable(hw, 1, 0); |
1575 | 1477 | ||
@@ -1614,17 +1516,12 @@ hfc4s8s_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
1614 | hw->irq = pdev->irq; | 1516 | hw->irq = pdev->irq; |
1615 | hw->iobase = pci_resource_start(pdev, 0); | 1517 | hw->iobase = pci_resource_start(pdev, 0); |
1616 | 1518 | ||
1617 | #ifdef HISAX_HFC4S8S_PCIMEM | ||
1618 | hw->hw_membase = (u_char *) pci_resource_start(pdev, 1); | ||
1619 | hw->membase = ioremap((ulong) hw->hw_membase, 256); | ||
1620 | #else | ||
1621 | if (!request_region(hw->iobase, 8, hw->card_name)) { | 1519 | if (!request_region(hw->iobase, 8, hw->card_name)) { |
1622 | printk(KERN_INFO | 1520 | printk(KERN_INFO |
1623 | "HFC-4S/8S: failed to request address space at 0x%04x\n", | 1521 | "HFC-4S/8S: failed to request address space at 0x%04x\n", |
1624 | hw->iobase); | 1522 | hw->iobase); |
1625 | goto out; | 1523 | goto out; |
1626 | } | 1524 | } |
1627 | #endif | ||
1628 | 1525 | ||
1629 | pci_set_drvdata(pdev, hw); | 1526 | pci_set_drvdata(pdev, hw); |
1630 | err = setup_instance(hw); | 1527 | err = setup_instance(hw); |