diff options
| author | John Crispin <blogic@openwrt.org> | 2012-07-11 10:33:43 -0400 |
|---|---|---|
| committer | John Crispin <blogic@openwrt.org> | 2012-09-13 04:31:00 -0400 |
| commit | c9e854cf940fbc09846c255895efceb3bc9bf095 (patch) | |
| tree | e56a5460f02e9c415d10ffa718d5d78d062f4b82 | |
| parent | 6a88a0f762a61f212d4bbcf1ad45369f28014484 (diff) | |
GPIO: MIPS: lantiq: fix overflow inside stp-xway driver
The driver was using a 16 bit field for storing the shadow value of the shift
register cascade. This resulted in only the first 2 shift registeres receiving
the correct data. The third shift register would always receive 0x00.
Fix this by using a 32bit field for the shadow value.
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-kernel@vger.kernel.org
| -rw-r--r-- | drivers/gpio/gpio-stp-xway.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpio/gpio-stp-xway.c b/drivers/gpio/gpio-stp-xway.c index e35096bf3cfb..8bead0bb6459 100644 --- a/drivers/gpio/gpio-stp-xway.c +++ b/drivers/gpio/gpio-stp-xway.c | |||
| @@ -82,7 +82,7 @@ struct xway_stp { | |||
| 82 | struct gpio_chip gc; | 82 | struct gpio_chip gc; |
| 83 | void __iomem *virt; | 83 | void __iomem *virt; |
| 84 | u32 edge; /* rising or falling edge triggered shift register */ | 84 | u32 edge; /* rising or falling edge triggered shift register */ |
| 85 | u16 shadow; /* shadow the shift registers state */ | 85 | u32 shadow; /* shadow the shift registers state */ |
| 86 | u8 groups; /* we can drive 1-3 groups of 8bit each */ | 86 | u8 groups; /* we can drive 1-3 groups of 8bit each */ |
| 87 | u8 dsl; /* the 2 LSBs can be driven by the dsl core */ | 87 | u8 dsl; /* the 2 LSBs can be driven by the dsl core */ |
| 88 | u8 phy1; /* 3 bits can be driven by phy1 */ | 88 | u8 phy1; /* 3 bits can be driven by phy1 */ |