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authorJoakim Tjernlund <Joakim.Tjernlund@transmode.se>2008-05-12 17:02:30 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2008-05-13 11:02:25 -0400
commitc9bfcb3151040cff6714542d1da04ccd7e2d3efc (patch)
treee3df8626f2b60d9373f8dfe125927f31d8381e1b
parentf4ed0deae8983591264d0e194e168ef65f4775f5 (diff)
spi_mpc83xx: much improved driver
The current driver may cause glitches on SPI CLK line since one must disable the SPI controller before changing any HW settings. Fix this by implementing a local spi_transfer function that won't change speed and/or word size while CS is active. While doing that heavy lifting a few other issues were addressed too: - Make word size 16 and 32 work too. - Honor bits_per_word and speed_hz in spi transaction. - Optimize the common path. This also stops using the "bitbang" framework (except for a few constants). [Roel Kluin <12o3l@tiscali.nl>: "irq" needs to be signed] Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
-rw-r--r--drivers/spi/Kconfig1
-rw-r--r--drivers/spi/spi_mpc83xx.c411
2 files changed, 282 insertions, 130 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index fae9e8f3d092..66ec5d8808de 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -126,7 +126,6 @@ config SPI_MPC52xx_PSC
126config SPI_MPC83xx 126config SPI_MPC83xx
127 tristate "Freescale MPC83xx/QUICC Engine SPI controller" 127 tristate "Freescale MPC83xx/QUICC Engine SPI controller"
128 depends on SPI_MASTER && (PPC_83xx || QUICC_ENGINE) && EXPERIMENTAL 128 depends on SPI_MASTER && (PPC_83xx || QUICC_ENGINE) && EXPERIMENTAL
129 select SPI_BITBANG
130 help 129 help
131 This enables using the Freescale MPC83xx and QUICC Engine SPI 130 This enables using the Freescale MPC83xx and QUICC Engine SPI
132 controllers in master mode. 131 controllers in master mode.
diff --git a/drivers/spi/spi_mpc83xx.c b/drivers/spi/spi_mpc83xx.c
index 189f706b9e4b..6832da6f7109 100644
--- a/drivers/spi/spi_mpc83xx.c
+++ b/drivers/spi/spi_mpc83xx.c
@@ -49,6 +49,7 @@ struct mpc83xx_spi_reg {
49#define SPMODE_LEN(x) ((x) << 20) 49#define SPMODE_LEN(x) ((x) << 20)
50#define SPMODE_PM(x) ((x) << 16) 50#define SPMODE_PM(x) ((x) << 16)
51#define SPMODE_OP (1 << 14) 51#define SPMODE_OP (1 << 14)
52#define SPMODE_CG(x) ((x) << 7)
52 53
53/* 54/*
54 * Default for SPI Mode: 55 * Default for SPI Mode:
@@ -67,10 +68,6 @@ struct mpc83xx_spi_reg {
67 68
68/* SPI Controller driver's private data. */ 69/* SPI Controller driver's private data. */
69struct mpc83xx_spi { 70struct mpc83xx_spi {
70 /* bitbang has to be first */
71 struct spi_bitbang bitbang;
72 struct completion done;
73
74 struct mpc83xx_spi_reg __iomem *base; 71 struct mpc83xx_spi_reg __iomem *base;
75 72
76 /* rx & tx bufs from the spi_transfer */ 73 /* rx & tx bufs from the spi_transfer */
@@ -82,7 +79,7 @@ struct mpc83xx_spi {
82 u32(*get_tx) (struct mpc83xx_spi *); 79 u32(*get_tx) (struct mpc83xx_spi *);
83 80
84 unsigned int count; 81 unsigned int count;
85 u32 irq; 82 int irq;
86 83
87 unsigned nsecs; /* (clock cycle time)/2 */ 84 unsigned nsecs; /* (clock cycle time)/2 */
88 85
@@ -94,6 +91,25 @@ struct mpc83xx_spi {
94 91
95 void (*activate_cs) (u8 cs, u8 polarity); 92 void (*activate_cs) (u8 cs, u8 polarity);
96 void (*deactivate_cs) (u8 cs, u8 polarity); 93 void (*deactivate_cs) (u8 cs, u8 polarity);
94
95 u8 busy;
96
97 struct workqueue_struct *workqueue;
98 struct work_struct work;
99
100 struct list_head queue;
101 spinlock_t lock;
102
103 struct completion done;
104};
105
106struct spi_mpc83xx_cs {
107 /* functions to deal with different sized buffers */
108 void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
109 u32 (*get_tx) (struct mpc83xx_spi *);
110 u32 rx_shift; /* RX data reg shift when in qe mode */
111 u32 tx_shift; /* TX data reg shift when in qe mode */
112 u32 hw_mode; /* Holds HW mode register settings */
97}; 113};
98 114
99static inline void mpc83xx_spi_write_reg(__be32 __iomem * reg, u32 val) 115static inline void mpc83xx_spi_write_reg(__be32 __iomem * reg, u32 val)
@@ -137,6 +153,7 @@ static void mpc83xx_spi_chipselect(struct spi_device *spi, int value)
137{ 153{
138 struct mpc83xx_spi *mpc83xx_spi; 154 struct mpc83xx_spi *mpc83xx_spi;
139 u8 pol = spi->mode & SPI_CS_HIGH ? 1 : 0; 155 u8 pol = spi->mode & SPI_CS_HIGH ? 1 : 0;
156 struct spi_mpc83xx_cs *cs = spi->controller_state;
140 157
141 mpc83xx_spi = spi_master_get_devdata(spi->master); 158 mpc83xx_spi = spi_master_get_devdata(spi->master);
142 159
@@ -147,50 +164,26 @@ static void mpc83xx_spi_chipselect(struct spi_device *spi, int value)
147 164
148 if (value == BITBANG_CS_ACTIVE) { 165 if (value == BITBANG_CS_ACTIVE) {
149 u32 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode); 166 u32 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
150 u32 len = spi->bits_per_word;
151 u8 pm;
152 167
153 if (len == 32) 168 mpc83xx_spi->rx_shift = cs->rx_shift;
154 len = 0; 169 mpc83xx_spi->tx_shift = cs->tx_shift;
155 else 170 mpc83xx_spi->get_rx = cs->get_rx;
156 len = len - 1; 171 mpc83xx_spi->get_tx = cs->get_tx;
157 172
158 /* mask out bits we are going to set */ 173 if (cs->hw_mode != regval) {
159 regval &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH 174 unsigned long flags;
160 | SPMODE_LEN(0xF) | SPMODE_DIV16 175 void *tmp_ptr = &mpc83xx_spi->base->mode;
161 | SPMODE_PM(0xF) | SPMODE_REV | SPMODE_LOOP); 176
162 177 regval = cs->hw_mode;
163 if (spi->mode & SPI_CPHA) 178 /* Turn off IRQs locally to minimize time that
164 regval |= SPMODE_CP_BEGIN_EDGECLK; 179 * SPI is disabled
165 if (spi->mode & SPI_CPOL) 180 */
166 regval |= SPMODE_CI_INACTIVEHIGH; 181 local_irq_save(flags);
167 if (!(spi->mode & SPI_LSB_FIRST)) 182 /* Turn off SPI unit prior changing mode */
168 regval |= SPMODE_REV; 183 mpc83xx_spi_write_reg(tmp_ptr, regval & ~SPMODE_ENABLE);
169 if (spi->mode & SPI_LOOP) 184 mpc83xx_spi_write_reg(tmp_ptr, regval);
170 regval |= SPMODE_LOOP; 185 local_irq_restore(flags);
171
172 regval |= SPMODE_LEN(len);
173
174 if ((mpc83xx_spi->spibrg / spi->max_speed_hz) >= 64) {
175 pm = mpc83xx_spi->spibrg / (spi->max_speed_hz * 64) - 1;
176 if (pm > 0x0f) {
177 dev_err(&spi->dev, "Requested speed is too "
178 "low: %d Hz. Will use %d Hz instead.\n",
179 spi->max_speed_hz,
180 mpc83xx_spi->spibrg / 1024);
181 pm = 0x0f;
182 }
183 regval |= SPMODE_PM(pm) | SPMODE_DIV16;
184 } else {
185 pm = mpc83xx_spi->spibrg / (spi->max_speed_hz * 4);
186 if (pm)
187 pm--;
188 regval |= SPMODE_PM(pm);
189 } 186 }
190
191 /* Turn off SPI unit prior changing mode */
192 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
193 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
194 if (mpc83xx_spi->activate_cs) 187 if (mpc83xx_spi->activate_cs)
195 mpc83xx_spi->activate_cs(spi->chip_select, pol); 188 mpc83xx_spi->activate_cs(spi->chip_select, pol);
196 } 189 }
@@ -201,8 +194,9 @@ int mpc83xx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
201{ 194{
202 struct mpc83xx_spi *mpc83xx_spi; 195 struct mpc83xx_spi *mpc83xx_spi;
203 u32 regval; 196 u32 regval;
204 u8 bits_per_word; 197 u8 bits_per_word, pm;
205 u32 hz; 198 u32 hz;
199 struct spi_mpc83xx_cs *cs = spi->controller_state;
206 200
207 mpc83xx_spi = spi_master_get_devdata(spi->master); 201 mpc83xx_spi = spi_master_get_devdata(spi->master);
208 202
@@ -223,61 +217,191 @@ int mpc83xx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
223 || ((bits_per_word > 16) && (bits_per_word != 32))) 217 || ((bits_per_word > 16) && (bits_per_word != 32)))
224 return -EINVAL; 218 return -EINVAL;
225 219
226 mpc83xx_spi->rx_shift = 0; 220 if (!hz)
227 mpc83xx_spi->tx_shift = 0; 221 hz = spi->max_speed_hz;
222
223 cs->rx_shift = 0;
224 cs->tx_shift = 0;
228 if (bits_per_word <= 8) { 225 if (bits_per_word <= 8) {
229 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8; 226 cs->get_rx = mpc83xx_spi_rx_buf_u8;
230 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8; 227 cs->get_tx = mpc83xx_spi_tx_buf_u8;
231 if (mpc83xx_spi->qe_mode) { 228 if (mpc83xx_spi->qe_mode) {
232 mpc83xx_spi->rx_shift = 16; 229 cs->rx_shift = 16;
233 mpc83xx_spi->tx_shift = 24; 230 cs->tx_shift = 24;
234 } 231 }
235 } else if (bits_per_word <= 16) { 232 } else if (bits_per_word <= 16) {
236 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u16; 233 cs->get_rx = mpc83xx_spi_rx_buf_u16;
237 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u16; 234 cs->get_tx = mpc83xx_spi_tx_buf_u16;
238 if (mpc83xx_spi->qe_mode) { 235 if (mpc83xx_spi->qe_mode) {
239 mpc83xx_spi->rx_shift = 16; 236 cs->rx_shift = 16;
240 mpc83xx_spi->tx_shift = 16; 237 cs->tx_shift = 16;
241 } 238 }
242 } else if (bits_per_word <= 32) { 239 } else if (bits_per_word <= 32) {
243 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u32; 240 cs->get_rx = mpc83xx_spi_rx_buf_u32;
244 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u32; 241 cs->get_tx = mpc83xx_spi_tx_buf_u32;
245 } else 242 } else
246 return -EINVAL; 243 return -EINVAL;
247 244
248 if (mpc83xx_spi->qe_mode && spi->mode & SPI_LSB_FIRST) { 245 if (mpc83xx_spi->qe_mode && spi->mode & SPI_LSB_FIRST) {
249 mpc83xx_spi->tx_shift = 0; 246 cs->tx_shift = 0;
250 if (bits_per_word <= 8) 247 if (bits_per_word <= 8)
251 mpc83xx_spi->rx_shift = 8; 248 cs->rx_shift = 8;
252 else 249 else
253 mpc83xx_spi->rx_shift = 0; 250 cs->rx_shift = 0;
254 } 251 }
255 252
256 /* nsecs = (clock period)/2 */ 253 mpc83xx_spi->rx_shift = cs->rx_shift;
257 if (!hz) 254 mpc83xx_spi->tx_shift = cs->tx_shift;
258 hz = spi->max_speed_hz; 255 mpc83xx_spi->get_rx = cs->get_rx;
259 mpc83xx_spi->nsecs = (1000000000 / 2) / hz; 256 mpc83xx_spi->get_tx = cs->get_tx;
260 if (mpc83xx_spi->nsecs > MAX_UDELAY_MS * 1000)
261 return -EINVAL;
262 257
263 if (bits_per_word == 32) 258 if (bits_per_word == 32)
264 bits_per_word = 0; 259 bits_per_word = 0;
265 else 260 else
266 bits_per_word = bits_per_word - 1; 261 bits_per_word = bits_per_word - 1;
267 262
268 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
269
270 /* mask out bits we are going to set */ 263 /* mask out bits we are going to set */
271 regval &= ~(SPMODE_LEN(0xF) | SPMODE_REV); 264 cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
272 regval |= SPMODE_LEN(bits_per_word); 265 | SPMODE_PM(0xF));
273 if (!(spi->mode & SPI_LSB_FIRST)) 266
274 regval |= SPMODE_REV; 267 cs->hw_mode |= SPMODE_LEN(bits_per_word);
268
269 if ((mpc83xx_spi->spibrg / hz) >= 64) {
270 pm = mpc83xx_spi->spibrg / (hz * 64) - 1;
271 if (pm > 0x0f) {
272 dev_err(&spi->dev, "Requested speed is too "
273 "low: %d Hz. Will use %d Hz instead.\n",
274 hz, mpc83xx_spi->spibrg / 1024);
275 pm = 0x0f;
276 }
277 cs->hw_mode |= SPMODE_PM(pm) | SPMODE_DIV16;
278 } else {
279 pm = mpc83xx_spi->spibrg / (hz * 4);
280 if (pm)
281 pm--;
282 cs->hw_mode |= SPMODE_PM(pm);
283 }
284 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
285 if (cs->hw_mode != regval) {
286 unsigned long flags;
287 void *tmp_ptr = &mpc83xx_spi->base->mode;
288
289 regval = cs->hw_mode;
290 /* Turn off IRQs locally to minimize time
291 * that SPI is disabled
292 */
293 local_irq_save(flags);
294 /* Turn off SPI unit prior changing mode */
295 mpc83xx_spi_write_reg(tmp_ptr, regval & ~SPMODE_ENABLE);
296 mpc83xx_spi_write_reg(tmp_ptr, regval);
297 local_irq_restore(flags);
298 }
299 return 0;
300}
275 301
276 /* Turn off SPI unit prior changing mode */ 302static int mpc83xx_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
277 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0); 303{
278 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval); 304 struct mpc83xx_spi *mpc83xx_spi;
305 u32 word, len, bits_per_word;
279 306
280 return 0; 307 mpc83xx_spi = spi_master_get_devdata(spi->master);
308
309 mpc83xx_spi->tx = t->tx_buf;
310 mpc83xx_spi->rx = t->rx_buf;
311 bits_per_word = spi->bits_per_word;
312 if (t->bits_per_word)
313 bits_per_word = t->bits_per_word;
314 len = t->len;
315 if (bits_per_word > 8)
316 len /= 2;
317 if (bits_per_word > 16)
318 len /= 2;
319 mpc83xx_spi->count = len;
320 INIT_COMPLETION(mpc83xx_spi->done);
321
322 /* enable rx ints */
323 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, SPIM_NE);
324
325 /* transmit word */
326 word = mpc83xx_spi->get_tx(mpc83xx_spi);
327 mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
328
329 wait_for_completion(&mpc83xx_spi->done);
330
331 /* disable rx ints */
332 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
333
334 return mpc83xx_spi->count;
335}
336
337static void mpc83xx_spi_work(struct work_struct *work)
338{
339 struct mpc83xx_spi *mpc83xx_spi =
340 container_of(work, struct mpc83xx_spi, work);
341
342 spin_lock_irq(&mpc83xx_spi->lock);
343 mpc83xx_spi->busy = 1;
344 while (!list_empty(&mpc83xx_spi->queue)) {
345 struct spi_message *m;
346 struct spi_device *spi;
347 struct spi_transfer *t = NULL;
348 unsigned cs_change;
349 int status, nsecs = 50;
350
351 m = container_of(mpc83xx_spi->queue.next,
352 struct spi_message, queue);
353 list_del_init(&m->queue);
354 spin_unlock_irq(&mpc83xx_spi->lock);
355
356 spi = m->spi;
357 cs_change = 1;
358 status = 0;
359 list_for_each_entry(t, &m->transfers, transfer_list) {
360 if (t->bits_per_word || t->speed_hz) {
361 /* Don't allow changes if CS is active */
362 status = -EINVAL;
363
364 if (cs_change)
365 status = mpc83xx_spi_setup_transfer(spi, t);
366 if (status < 0)
367 break;
368 }
369
370 if (cs_change)
371 mpc83xx_spi_chipselect(spi, BITBANG_CS_ACTIVE);
372 cs_change = t->cs_change;
373 if (t->len)
374 status = mpc83xx_spi_bufs(spi, t);
375 if (status) {
376 status = -EMSGSIZE;
377 break;
378 }
379 m->actual_length += t->len;
380
381 if (t->delay_usecs)
382 udelay(t->delay_usecs);
383
384 if (cs_change) {
385 ndelay(nsecs);
386 mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
387 ndelay(nsecs);
388 }
389 }
390
391 m->status = status;
392 m->complete(m->context);
393
394 if (status || !cs_change) {
395 ndelay(nsecs);
396 mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
397 }
398
399 mpc83xx_spi_setup_transfer(spi, NULL);
400
401 spin_lock_irq(&mpc83xx_spi->lock);
402 }
403 mpc83xx_spi->busy = 0;
404 spin_unlock_irq(&mpc83xx_spi->lock);
281} 405}
282 406
283/* the spi->mode bits understood by this driver: */ 407/* the spi->mode bits understood by this driver: */
@@ -286,9 +410,10 @@ int mpc83xx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
286 410
287static int mpc83xx_spi_setup(struct spi_device *spi) 411static int mpc83xx_spi_setup(struct spi_device *spi)
288{ 412{
289 struct spi_bitbang *bitbang;
290 struct mpc83xx_spi *mpc83xx_spi; 413 struct mpc83xx_spi *mpc83xx_spi;
291 int retval; 414 int retval;
415 u32 hw_mode;
416 struct spi_mpc83xx_cs *cs = spi->controller_state;
292 417
293 if (spi->mode & ~MODEBITS) { 418 if (spi->mode & ~MODEBITS) {
294 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n", 419 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
@@ -299,63 +424,56 @@ static int mpc83xx_spi_setup(struct spi_device *spi)
299 if (!spi->max_speed_hz) 424 if (!spi->max_speed_hz)
300 return -EINVAL; 425 return -EINVAL;
301 426
302 bitbang = spi_master_get_devdata(spi->master); 427 if (!cs) {
428 cs = kzalloc(sizeof *cs, GFP_KERNEL);
429 if (!cs)
430 return -ENOMEM;
431 spi->controller_state = cs;
432 }
303 mpc83xx_spi = spi_master_get_devdata(spi->master); 433 mpc83xx_spi = spi_master_get_devdata(spi->master);
304 434
305 if (!spi->bits_per_word) 435 if (!spi->bits_per_word)
306 spi->bits_per_word = 8; 436 spi->bits_per_word = 8;
307 437
438 hw_mode = cs->hw_mode; /* Save orginal settings */
439 cs->hw_mode = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
440 /* mask out bits we are going to set */
441 cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
442 | SPMODE_REV | SPMODE_LOOP);
443
444 if (spi->mode & SPI_CPHA)
445 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
446 if (spi->mode & SPI_CPOL)
447 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
448 if (!(spi->mode & SPI_LSB_FIRST))
449 cs->hw_mode |= SPMODE_REV;
450 if (spi->mode & SPI_LOOP)
451 cs->hw_mode |= SPMODE_LOOP;
452
308 retval = mpc83xx_spi_setup_transfer(spi, NULL); 453 retval = mpc83xx_spi_setup_transfer(spi, NULL);
309 if (retval < 0) 454 if (retval < 0) {
455 cs->hw_mode = hw_mode; /* Restore settings */
310 return retval; 456 return retval;
457 }
311 458
312 dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec\n", 459 dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u Hz\n",
313 __func__, spi->mode & (SPI_CPOL | SPI_CPHA), 460 __func__, spi->mode & (SPI_CPOL | SPI_CPHA),
314 spi->bits_per_word, 2 * mpc83xx_spi->nsecs); 461 spi->bits_per_word, spi->max_speed_hz);
315 462#if 0 /* Don't think this is needed */
316 /* NOTE we _need_ to call chipselect() early, ideally with adapter 463 /* NOTE we _need_ to call chipselect() early, ideally with adapter
317 * setup, unless the hardware defaults cooperate to avoid confusion 464 * setup, unless the hardware defaults cooperate to avoid confusion
318 * between normal (active low) and inverted chipselects. 465 * between normal (active low) and inverted chipselects.
319 */ 466 */
320 467
321 /* deselect chip (low or high) */ 468 /* deselect chip (low or high) */
322 spin_lock(&bitbang->lock); 469 spin_lock(&mpc83xx_spi->lock);
323 if (!bitbang->busy) { 470 if (!mpc83xx_spi->busy)
324 bitbang->chipselect(spi, BITBANG_CS_INACTIVE); 471 mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
325 ndelay(mpc83xx_spi->nsecs); 472 spin_unlock(&mpc83xx_spi->lock);
326 } 473#endif
327 spin_unlock(&bitbang->lock);
328
329 return 0; 474 return 0;
330} 475}
331 476
332static int mpc83xx_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
333{
334 struct mpc83xx_spi *mpc83xx_spi;
335 u32 word;
336
337 mpc83xx_spi = spi_master_get_devdata(spi->master);
338
339 mpc83xx_spi->tx = t->tx_buf;
340 mpc83xx_spi->rx = t->rx_buf;
341 mpc83xx_spi->count = t->len;
342 INIT_COMPLETION(mpc83xx_spi->done);
343
344 /* enable rx ints */
345 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, SPIM_NE);
346
347 /* transmit word */
348 word = mpc83xx_spi->get_tx(mpc83xx_spi);
349 mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
350
351 wait_for_completion(&mpc83xx_spi->done);
352
353 /* disable rx ints */
354 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
355
356 return t->len - mpc83xx_spi->count;
357}
358
359irqreturn_t mpc83xx_spi_irq(s32 irq, void *context_data) 477irqreturn_t mpc83xx_spi_irq(s32 irq, void *context_data)
360{ 478{
361 struct mpc83xx_spi *mpc83xx_spi = context_data; 479 struct mpc83xx_spi *mpc83xx_spi = context_data;
@@ -395,6 +513,28 @@ irqreturn_t mpc83xx_spi_irq(s32 irq, void *context_data)
395 513
396 return ret; 514 return ret;
397} 515}
516static int mpc83xx_spi_transfer(struct spi_device *spi,
517 struct spi_message *m)
518{
519 struct mpc83xx_spi *mpc83xx_spi = spi_master_get_devdata(spi->master);
520 unsigned long flags;
521
522 m->actual_length = 0;
523 m->status = -EINPROGRESS;
524
525 spin_lock_irqsave(&mpc83xx_spi->lock, flags);
526 list_add_tail(&m->queue, &mpc83xx_spi->queue);
527 queue_work(mpc83xx_spi->workqueue, &mpc83xx_spi->work);
528 spin_unlock_irqrestore(&mpc83xx_spi->lock, flags);
529
530 return 0;
531}
532
533
534static void mpc83xx_spi_cleanup(struct spi_device *spi)
535{
536 kfree(spi->controller_state);
537}
398 538
399static int __init mpc83xx_spi_probe(struct platform_device *dev) 539static int __init mpc83xx_spi_probe(struct platform_device *dev)
400{ 540{
@@ -426,11 +566,11 @@ static int __init mpc83xx_spi_probe(struct platform_device *dev)
426 ret = -ENODEV; 566 ret = -ENODEV;
427 goto free_master; 567 goto free_master;
428 } 568 }
569 master->setup = mpc83xx_spi_setup;
570 master->transfer = mpc83xx_spi_transfer;
571 master->cleanup = mpc83xx_spi_cleanup;
572
429 mpc83xx_spi = spi_master_get_devdata(master); 573 mpc83xx_spi = spi_master_get_devdata(master);
430 mpc83xx_spi->bitbang.master = spi_master_get(master);
431 mpc83xx_spi->bitbang.chipselect = mpc83xx_spi_chipselect;
432 mpc83xx_spi->bitbang.setup_transfer = mpc83xx_spi_setup_transfer;
433 mpc83xx_spi->bitbang.txrx_bufs = mpc83xx_spi_bufs;
434 mpc83xx_spi->activate_cs = pdata->activate_cs; 574 mpc83xx_spi->activate_cs = pdata->activate_cs;
435 mpc83xx_spi->deactivate_cs = pdata->deactivate_cs; 575 mpc83xx_spi->deactivate_cs = pdata->deactivate_cs;
436 mpc83xx_spi->qe_mode = pdata->qe_mode; 576 mpc83xx_spi->qe_mode = pdata->qe_mode;
@@ -445,7 +585,6 @@ static int __init mpc83xx_spi_probe(struct platform_device *dev)
445 mpc83xx_spi->tx_shift = 24; 585 mpc83xx_spi->tx_shift = 24;
446 } 586 }
447 587
448 mpc83xx_spi->bitbang.master->setup = mpc83xx_spi_setup;
449 init_completion(&mpc83xx_spi->done); 588 init_completion(&mpc83xx_spi->done);
450 589
451 mpc83xx_spi->base = ioremap(r->start, r->end - r->start + 1); 590 mpc83xx_spi->base = ioremap(r->start, r->end - r->start + 1);
@@ -483,11 +622,21 @@ static int __init mpc83xx_spi_probe(struct platform_device *dev)
483 regval |= SPMODE_OP; 622 regval |= SPMODE_OP;
484 623
485 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval); 624 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
625 spin_lock_init(&mpc83xx_spi->lock);
626 init_completion(&mpc83xx_spi->done);
627 INIT_WORK(&mpc83xx_spi->work, mpc83xx_spi_work);
628 INIT_LIST_HEAD(&mpc83xx_spi->queue);
486 629
487 ret = spi_bitbang_start(&mpc83xx_spi->bitbang); 630 mpc83xx_spi->workqueue = create_singlethread_workqueue(
488 631 master->dev.parent->bus_id);
489 if (ret != 0) 632 if (mpc83xx_spi->workqueue == NULL) {
633 ret = -EBUSY;
490 goto free_irq; 634 goto free_irq;
635 }
636
637 ret = spi_register_master(master);
638 if (ret < 0)
639 goto unreg_master;
491 640
492 printk(KERN_INFO 641 printk(KERN_INFO
493 "%s: MPC83xx SPI Controller driver at 0x%p (irq = %d)\n", 642 "%s: MPC83xx SPI Controller driver at 0x%p (irq = %d)\n",
@@ -495,6 +644,8 @@ static int __init mpc83xx_spi_probe(struct platform_device *dev)
495 644
496 return ret; 645 return ret;
497 646
647unreg_master:
648 destroy_workqueue(mpc83xx_spi->workqueue);
498free_irq: 649free_irq:
499 free_irq(mpc83xx_spi->irq, mpc83xx_spi); 650 free_irq(mpc83xx_spi->irq, mpc83xx_spi);
500unmap_io: 651unmap_io:
@@ -515,10 +666,12 @@ static int __exit mpc83xx_spi_remove(struct platform_device *dev)
515 master = platform_get_drvdata(dev); 666 master = platform_get_drvdata(dev);
516 mpc83xx_spi = spi_master_get_devdata(master); 667 mpc83xx_spi = spi_master_get_devdata(master);
517 668
518 spi_bitbang_stop(&mpc83xx_spi->bitbang); 669 flush_workqueue(mpc83xx_spi->workqueue);
670 destroy_workqueue(mpc83xx_spi->workqueue);
671 spi_unregister_master(master);
672
519 free_irq(mpc83xx_spi->irq, mpc83xx_spi); 673 free_irq(mpc83xx_spi->irq, mpc83xx_spi);
520 iounmap(mpc83xx_spi->base); 674 iounmap(mpc83xx_spi->base);
521 spi_master_put(mpc83xx_spi->bitbang.master);
522 675
523 return 0; 676 return 0;
524} 677}